sys/contrib/octeon-sdk/cvmx-csr-db.c

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  38
  39 /**
  40  * @file
  41  *
  42  * Configuration and status register (CSR) address and type definitions for
  43  * Octeon.
  44  *
  45  * This file is auto generated. Do not edit.
  46  *
  47  * <hr>$Revision: 41586 $<hr>
  48  *
  49  */
  50
  51 #include "cvmx-csr-db.h"
  52
  53 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xxp2[] = {
  54          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
  55         {"cvmx_asx#_int_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      4,      0},
  56         {"cvmx_asx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      4,      4},
  57         {"cvmx_asx#_prt_loop"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      3,      8},
  58         {"cvmx_asx#_rld_bypass"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      2,      11},
  59         {"cvmx_asx#_rld_bypass_setting",        CVMX_CSR_DB_TYPE_RSL,   64,     8,      2,      13},
  60         {"cvmx_asx#_rld_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     3,      15},
  61         {"cvmx_asx#_rld_data_drv"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     12,     3,      18},
  62         {"cvmx_asx#_rld_fcram_mode"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     2,      21},
  63         {"cvmx_asx#_rld_nctl_strong"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     16,     2,      23},
  64         {"cvmx_asx#_rld_nctl_weak"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     18,     2,      25},
  65         {"cvmx_asx#_rld_pctl_strong"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     20,     2,      27},
  66         {"cvmx_asx#_rld_pctl_weak"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     22,     2,      29},
  67         {"cvmx_asx#_rld_setting"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     24,     2,      31},
  68         {"cvmx_asx#_rx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     26,     2,      33},
  69         {"cvmx_asx#_rx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     34,     2,      35},
  70         {"cvmx_asx#_rx_wol"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     36,     3,      37},
  71         {"cvmx_asx#_rx_wol_msk"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     38,     1,      40},
  72         {"cvmx_asx#_rx_wol_powok"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     40,     2,      41},
  73         {"cvmx_asx#_rx_wol_sig"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     42,     2,      43},
  74         {"cvmx_asx#_tx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     44,     2,      45},
  75         {"cvmx_asx#_tx_comp_byp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     52,     3,      47},
  76         {"cvmx_asx#_tx_hi_water#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     54,     2,      50},
  77         {"cvmx_asx#_tx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     62,     2,      52},
  78         {"cvmx_asx0_dbg_data_drv"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     64,     3,      54},
  79         {"cvmx_asx0_dbg_data_enable"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     65,     2,      57},
  80         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     66,     2,      59},
  81         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     67,     2,      61},
  82         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     68,     2,      63},
  83         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     69,     2,      65},
  84         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     70,     15,     67},
  85         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     103,    2,      82},
  86         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     136,    15,     84},
  87         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     169,    2,      99},
  88         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     170,    2,      101},
  89         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     186,    2,      103},
  90         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     202,    2,      105},
  91         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     203,    2,      107},
  92         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     204,    2,      109},
  93         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     205,    1,      111},
  94         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     221,    3,      112},
  95         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     222,    2,      115},
  96         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     223,    4,      117},
  97         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     224,    2,      121},
  98         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     225,    3,      123},
  99         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     229,    7,      126},
 100         {"cvmx_dbg_data"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     245,    7,      133},
 101         {"cvmx_dfa_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     246,    3,      140},
 102         {"cvmx_dfa_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     247,    10,     143},
 103         {"cvmx_dfa_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     248,    2,      153},
 104         {"cvmx_dfa_dbell"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     249,    2,      155},
 105         {"cvmx_dfa_difctl"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     250,    4,      157},
 106         {"cvmx_dfa_difrdptr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     251,    3,      161},
 107         {"cvmx_dfa_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     252,    21,     164},
 108         {"cvmx_dfa_memcfg0"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     253,    16,     185},
 109         {"cvmx_dfa_memcfg1"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     254,    11,     201},
 110         {"cvmx_dfa_memcfg2"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     255,    8,      212},
 111         {"cvmx_dfa_memfadr"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     256,    6,      220},
 112         {"cvmx_dfa_memfcr"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     257,    6,      226},
 113         {"cvmx_dfa_memrld"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     258,    2,      232},
 114         {"cvmx_dfa_ncbctl"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     259,    8,      234},
 115         {"cvmx_dfa_sbd_dbg0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     260,    1,      242},
 116         {"cvmx_dfa_sbd_dbg1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     261,    1,      243},
 117         {"cvmx_dfa_sbd_dbg2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     262,    1,      244},
 118         {"cvmx_dfa_sbd_dbg3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     263,    1,      245},
 119         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     264,    6,      246},
 120         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     265,    7,      252},
 121         {"cvmx_fpa_fpf#_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     266,    3,      259},
 122         {"cvmx_fpa_fpf#_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     273,    2,      262},
 123         {"cvmx_fpa_fpf0_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     280,    3,      264},
 124         {"cvmx_fpa_fpf0_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     281,    2,      267},
 125         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     282,    29,     269},
 126         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     283,    29,     298},
 127         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     284,    2,      327},
 128         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     292,    2,      329},
 129         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     300,    3,      331},
 130         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     301,    3,      334},
 131         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     302,    2,      337},
 132         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     303,    2,      339},
 133         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     304,    8,      341},
 134         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     306,    2,      349},
 135         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     308,    3,      351},
 136         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     310,    2,      354},
 137         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     312,    5,      356},
 138         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     320,    1,      361},
 139         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     328,    1,      362},
 140         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     336,    1,      363},
 141         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     344,    1,      364},
 142         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     352,    1,      365},
 143         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     360,    1,      366},
 144         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     368,    2,      367},
 145         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     376,    4,      369},
 146         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     384,    2,      373},
 147         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     392,    11,     375},
 148         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     400,    9,      386},
 149         {"cvmx_gmx#_rx#_frm_max"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     408,    2,      395},
 150         {"cvmx_gmx#_rx#_frm_min"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     416,    2,      397},
 151         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     424,    2,      399},
 152         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     432,    20,     401},
 153         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     440,    20,     421},
 154         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     448,    2,      441},
 155         {"cvmx_gmx#_rx#_rx_inbnd"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     456,    4,      443},
 156         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     464,    2,      447},
 157         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     472,    2,      449},
 158         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     480,    2,      451},
 159         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     488,    2,      453},
 160         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     496,    2,      455},
 161         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     504,    2,      457},
 162         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     512,    2,      459},
 163         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     520,    2,      461},
 164         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     528,    2,      463},
 165         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     536,    2,      465},
 166         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     544,    4,      467},
 167         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     552,    2,      471},
 168         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     560,    2,      473},
 169         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     568,    2,      475},
 170         {"cvmx_gmx#_rx_pass_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     576,    2,      477},
 171         {"cvmx_gmx#_rx_pass_map#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     578,    2,      479},
 172         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     610,    2,      481},
 173         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     612,    2,      483},
 174         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     620,    3,      485},
 175         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     622,    5,      488},
 176         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     630,    2,      493},
 177         {"cvmx_gmx#_tx#_clk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     638,    2,      495},
 178         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     646,    3,      497},
 179         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     654,    2,      500},
 180         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     662,    2,      502},
 181         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     670,    2,      504},
 182         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     678,    2,      506},
 183         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     686,    2,      508},
 184         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     694,    2,      510},
 185         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     702,    2,      512},
 186         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     710,    2,      514},
 187         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     718,    2,      516},
 188         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     726,    2,      518},
 189         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     734,    2,      520},
 190         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     742,    2,      522},
 191         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     750,    2,      524},
 192         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     758,    2,      526},
 193         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     766,    2,      528},
 194         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     774,    2,      530},
 195         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     782,    2,      532},
 196         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     790,    2,      534},
 197         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     798,    2,      536},
 198         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     806,    2,      538},
 199         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     808,    2,      540},
 200         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     810,    2,      542},
 201         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     812,    3,      544},
 202         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     814,    7,      547},
 203         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     816,    7,      554},
 204         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     818,    2,      561},
 205         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     820,    2,      563},
 206         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     822,    4,      565},
 207         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     824,    2,      569},
 208         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     826,    2,      571},
 209         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     828,    2,      573},
 210         {"cvmx_gmx#_tx_spi_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     830,    3,      575},
 211         {"cvmx_gmx#_tx_spi_max"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     832,    3,      578},
 212         {"cvmx_gmx#_tx_spi_thresh"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     834,    2,      581},
 213         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     836,    7,      583},
 214         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     852,    2,      590},
 215         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     853,    2,      592},
 216         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     854,    2,      594},
 217         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     855,    2,      596},
 218         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     856,    19,     598},
 219         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     857,    6,      617},
 220         {"cvmx_iob_dwb_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     858,    3,      623},
 221         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     859,    3,      626},
 222         {"cvmx_iob_i2c_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     860,    3,      629},
 223         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     861,    5,      632},
 224         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     862,    5,      637},
 225         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     863,    1,      642},
 226         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     864,    1,      643},
 227         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     865,    5,      644},
 228         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     866,    5,      649},
 229         {"cvmx_iob_n2c_l2c_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     867,    3,      654},
 230         {"cvmx_iob_n2c_rsp_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     868,    3,      657},
 231         {"cvmx_iob_outb_com_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     869,    3,      660},
 232         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     870,    5,      663},
 233         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     871,    5,      668},
 234         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     872,    1,      673},
 235         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     873,    1,      674},
 236         {"cvmx_iob_outb_fpa_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     874,    3,      675},
 237         {"cvmx_iob_outb_req_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     875,    3,      678},
 238         {"cvmx_iob_p2c_req_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     876,    3,      681},
 239         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     877,    2,      684},
 240         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     878,    2,      686},
 241         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     879,    2,      688},
 242         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     880,    2,      690},
 243         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     881,    17,     692},
 244         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     882,    2,      709},
 245         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     883,    1,      711},
 246         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     884,    9,      712},
 247         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     885,    6,      721},
 248         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     886,    6,      727},
 249         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     887,    2,      733},
 250         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     888,    2,      735},
 251         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     889,    3,      737},
 252         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     925,    2,      740},
 253         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     961,    6,      742},
 254         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     962,    2,      748},
 255         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     970,    2,      750},
 256         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     971,    3,      752},
 257         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     972,    5,      755},
 258         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     980,    3,      760},
 259         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     981,    2,      763},
 260         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     982,    2,      765},
 261         {"cvmx_key_bist_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     983,    4,      767},
 262         {"cvmx_key_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     984,    3,      771},
 263         {"cvmx_key_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     985,    5,      774},
 264         {"cvmx_key_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     986,    5,      779},
 265         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     987,    5,      784},
 266         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     988,    5,      789},
 267         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     989,    8,      794},
 268         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     990,    9,      802},
 269         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     991,    8,      811},
 270         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     992,    5,      819},
 271         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     993,    4,      824},
 272         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     994,    2,      828},
 273         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     995,    14,     830},
 274         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     996,    19,     844},
 275         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     997,    3,      863},
 276         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     998,    3,      866},
 277         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     999,    2,      869},
 278         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1003,   17,     871},
 279         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1004,   5,      888},
 280         {"cvmx_l2c_spar1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1005,   5,      893},
 281         {"cvmx_l2c_spar2"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1006,   5,      898},
 282         {"cvmx_l2c_spar3"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1007,   5,      903},
 283         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1008,   2,      908},
 284         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1009,   3,      910},
 285         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1010,   2,      913},
 286         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1011,   2,      915},
 287         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1012,   2,      917},
 288         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1013,   7,      919},
 289         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1014,   4,      926},
 290         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1015,   3,      930},
 291         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1016,   3,      933},
 292         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1017,   2,      936},
 293         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1018,   2,      938},
 294         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1019,   2,      940},
 295         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1020,   4,      942},
 296         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1021,   13,     946},
 297         {"cvmx_led_blink"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1022,   2,      959},
 298         {"cvmx_led_clk_phase"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1023,   2,      961},
 299         {"cvmx_led_cylon"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1024,   2,      963},
 300         {"cvmx_led_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1025,   2,      965},
 301         {"cvmx_led_en"                 ,        CVMX_CSR_DB_TYPE_RSL,   64,     1026,   2,      967},
 302         {"cvmx_led_polarity"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1027,   2,      969},
 303         {"cvmx_led_prt"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1028,   2,      971},
 304         {"cvmx_led_prt_fmt"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1029,   2,      973},
 305         {"cvmx_led_prt_status#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1030,   2,      975},
 306         {"cvmx_led_udd_cnt#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1038,   2,      977},
 307         {"cvmx_led_udd_dat#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1040,   2,      979},
 308         {"cvmx_led_udd_dat_clr#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1042,   2,      981},
 309         {"cvmx_led_udd_dat_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1044,   2,      983},
 310         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1046,   9,      985},
 311         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1047,   19,     994},
 312         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1048,   2,      1013},
 313         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1049,   2,      1015},
 314         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1050,   18,     1017},
 315         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1051,   5,      1035},
 316         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1052,   6,      1040},
 317         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1053,   2,      1046},
 318         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1054,   2,      1048},
 319         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1055,   14,     1050},
 320         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1056,   9,      1064},
 321         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1057,   2,      1073},
 322         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1058,   2,      1075},
 323         {"cvmx_lmc#_pll_bwctl"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1059,   3,      1077},
 324         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1060,   9,      1080},
 325         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1061,   9,      1089},
 326         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1062,   4,      1098},
 327         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1063,   3,      1102},
 328         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1064,   3,      1105},
 329         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1065,   3,      1108},
 330         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1066,   5,      1111},
 331         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1068,   1,      1116},
 332         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1069,   6,      1117},
 333         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1077,   13,     1123},
 334         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1085,   4,      1136},
 335         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1086,   2,      1140},
 336         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1087,   2,      1142},
 337         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1088,   8,      1144},
 338         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1089,   7,      1152},
 339         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1090,   2,      1159},
 340         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1091,   8,      1161},
 341         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1092,   2,      1169},
 342         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1093,   8,      1171},
 343         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1094,   12,     1179},
 344         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1095,   3,      1191},
 345         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1096,   3,      1194},
 346         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1097,   2,      1197},
 347         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1099,   2,      1199},
 348         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1101,   2,      1201},
 349         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1103,   7,      1203},
 350         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1105,   2,      1210},
 351         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1107,   7,      1212},
 352         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1109,   4,      1219},
 353         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1111,   8,      1223},
 354         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1113,   9,      1231},
 355         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1115,   7,      1240},
 356         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1117,   9,      1247},
 357         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1119,   2,      1256},
 358         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1121,   2,      1258},
 359         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1123,   4,      1260},
 360         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1125,   2,      1264},
 361         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1127,   2,      1266},
 362         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1129,   2,      1268},
 363         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1131,   4,      1270},
 364         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1133,   2,      1274},
 365         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1135,   2,      1276},
 366         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1137,   2,      1278},
 367         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1139,   2,      1280},
 368         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1141,   2,      1282},
 369         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1143,   2,      1284},
 370         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1145,   6,      1286},
 371         {"cvmx_npi_base_addr_input#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1147,   2,      1292},
 372         {"cvmx_npi_base_addr_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1151,   2,      1294},
 373         {"cvmx_npi_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1155,   21,     1296},
 374         {"cvmx_npi_buff_size_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1156,   3,      1317},
 375         {"cvmx_npi_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1160,   21,     1320},
 376         {"cvmx_npi_dbg_select"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1161,   2,      1341},
 377         {"cvmx_npi_dma_control"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1162,   13,     1343},
 378         {"cvmx_npi_dma_highp_counts"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1163,   3,      1356},
 379         {"cvmx_npi_dma_highp_naddr"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1164,   3,      1359},
 380         {"cvmx_npi_dma_lowp_counts"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1165,   3,      1362},
 381         {"cvmx_npi_dma_lowp_naddr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1166,   3,      1365},
 382         {"cvmx_npi_highp_dbell"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1167,   2,      1368},
 383         {"cvmx_npi_highp_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1168,   2,      1370},
 384         {"cvmx_npi_input_control"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1169,   9,      1372},
 385         {"cvmx_npi_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1170,   43,     1381},
 386         {"cvmx_npi_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1171,   43,     1424},
 387         {"cvmx_npi_lowp_dbell"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1172,   2,      1467},
 388         {"cvmx_npi_lowp_ibuff_saddr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1173,   2,      1469},
 389         {"cvmx_npi_mem_access_subid#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1174,   8,      1471},
 390         {"cvmx_npi_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1178,   1,      1479},
 391         {"cvmx_npi_num_desc_output#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1179,   2,      1480},
 392         {"cvmx_npi_output_control"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1183,   38,     1482},
 393         {"cvmx_npi_p#_dbpair_addr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1184,   3,      1520},
 394         {"cvmx_npi_p#_instr_addr"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1188,   2,      1523},
 395         {"cvmx_npi_p#_instr_cnts"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1192,   3,      1525},
 396         {"cvmx_npi_p#_pair_cnts"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1196,   3,      1528},
 397         {"cvmx_npi_pci_burst_size"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1200,   3,      1531},
 398         {"cvmx_npi_pci_int_arb_cfg"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1201,   4,      1534},
 399         {"cvmx_npi_pci_read_cmd"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1202,   2,      1538},
 400         {"cvmx_npi_port32_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1203,   13,     1540},
 401         {"cvmx_npi_port33_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1204,   13,     1553},
 402         {"cvmx_npi_port34_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1205,   13,     1566},
 403         {"cvmx_npi_port35_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1206,   13,     1579},
 404         {"cvmx_npi_port_bp_control"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1207,   3,      1592},
 405         {"cvmx_npi_rsl_int_blocks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1208,   33,     1595},
 406         {"cvmx_npi_size_input#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1209,   2,      1628},
 407         {"cvmx_npi_win_read_to"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1213,   2,      1630},
 408         {"cvmx_pci_bar1_index#"        ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1214,   5,      1632},
 409         {"cvmx_pci_cfg00"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1246,   2,      1637},
 410         {"cvmx_pci_cfg01"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1247,   24,     1639},
 411         {"cvmx_pci_cfg02"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1248,   2,      1663},
 412         {"cvmx_pci_cfg03"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1249,   7,      1665},
 413         {"cvmx_pci_cfg04"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1250,   5,      1672},
 414         {"cvmx_pci_cfg05"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1251,   1,      1677},
 415         {"cvmx_pci_cfg06"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1252,   5,      1678},
 416         {"cvmx_pci_cfg07"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1253,   1,      1683},
 417         {"cvmx_pci_cfg08"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1254,   4,      1684},
 418         {"cvmx_pci_cfg09"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1255,   2,      1688},
 419         {"cvmx_pci_cfg10"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1256,   1,      1690},
 420         {"cvmx_pci_cfg11"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1257,   2,      1691},
 421         {"cvmx_pci_cfg12"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1258,   4,      1693},
 422         {"cvmx_pci_cfg13"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1259,   2,      1697},
 423         {"cvmx_pci_cfg15"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1260,   4,      1699},
 424         {"cvmx_pci_cfg16"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1261,   16,     1703},
 425         {"cvmx_pci_cfg17"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1262,   1,      1719},
 426         {"cvmx_pci_cfg18"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1263,   1,      1720},
 427         {"cvmx_pci_cfg19"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1264,   18,     1721},
 428         {"cvmx_pci_cfg20"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1265,   1,      1739},
 429         {"cvmx_pci_cfg21"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1266,   1,      1740},
 430         {"cvmx_pci_cfg22"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1267,   7,      1741},
 431         {"cvmx_pci_cfg56"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1268,   7,      1748},
 432         {"cvmx_pci_cfg57"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1269,   13,     1755},
 433         {"cvmx_pci_cfg58"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1270,   10,     1768},
 434         {"cvmx_pci_cfg59"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1271,   10,     1778},
 435         {"cvmx_pci_cfg60"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1272,   7,      1788},
 436         {"cvmx_pci_cfg61"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1273,   2,      1795},
 437         {"cvmx_pci_cfg62"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1274,   1,      1797},
 438         {"cvmx_pci_cfg63"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1275,   2,      1798},
 439         {"cvmx_pci_ctl_status_2"       ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1276,   16,     1800},
 440         {"cvmx_pci_dbell#"             ,        CVMX_CSR_DB_TYPE_PCI,   32,     1277,   2,      1816},
 441         {"cvmx_pci_dma_cnt#"           ,        CVMX_CSR_DB_TYPE_PCI,   32,     1281,   1,      1818},
 442         {"cvmx_pci_dma_int_lev#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1283,   1,      1819},
 443         {"cvmx_pci_dma_time#"          ,        CVMX_CSR_DB_TYPE_PCI,   32,     1285,   1,      1820},
 444         {"cvmx_pci_instr_count#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1287,   1,      1821},
 445         {"cvmx_pci_int_enb"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     1291,   35,     1822},
 446         {"cvmx_pci_int_enb2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1292,   35,     1857},
 447         {"cvmx_pci_int_sum"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     1293,   35,     1892},
 448         {"cvmx_pci_int_sum2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1294,   35,     1927},
 449         {"cvmx_pci_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI,   32,     1295,   2,      1962},
 450         {"cvmx_pci_pkt_credits#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1296,   2,      1964},
 451         {"cvmx_pci_pkts_sent#"         ,        CVMX_CSR_DB_TYPE_PCI,   32,     1300,   1,      1966},
 452         {"cvmx_pci_pkts_sent_int_lev#" ,        CVMX_CSR_DB_TYPE_PCI,   32,     1304,   1,      1967},
 453         {"cvmx_pci_pkts_sent_time#"    ,        CVMX_CSR_DB_TYPE_PCI,   32,     1308,   1,      1968},
 454         {"cvmx_pci_read_cmd_6"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1312,   3,      1969},
 455         {"cvmx_pci_read_cmd_c"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1313,   3,      1972},
 456         {"cvmx_pci_read_cmd_e"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1314,   3,      1975},
 457         {"cvmx_pci_read_timeout"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1315,   3,      1978},
 458         {"cvmx_pci_scm_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1316,   2,      1981},
 459         {"cvmx_pci_tsr_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1317,   2,      1983},
 460         {"cvmx_pci_win_rd_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1318,   4,      1985},
 461         {"cvmx_pci_win_rd_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1319,   1,      1989},
 462         {"cvmx_pci_win_wr_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1320,   4,      1990},
 463         {"cvmx_pci_win_wr_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1321,   1,      1994},
 464         {"cvmx_pci_win_wr_mask"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1322,   2,      1995},
 465         {"cvmx_pip_bck_prs"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1323,   5,      1997},
 466         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1324,   2,      2002},
 467         {"cvmx_pip_crc_ctl#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1325,   3,      2004},
 468         {"cvmx_pip_crc_iv#"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1327,   2,      2007},
 469         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1329,   4,      2009},
 470         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1333,   8,      2013},
 471         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1334,   16,     2021},
 472         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1335,   10,     2037},
 473         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1336,   10,     2047},
 474         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1337,   2,      2057},
 475         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1338,   18,     2059},
 476         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1374,   25,     2077},
 477         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1410,   2,      2102},
 478         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1474,   2,      2104},
 479         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1482,   9,      2106},
 480         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1486,   2,      2115},
 481         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1487,   2,      2117},
 482         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1523,   2,      2119},
 483         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1559,   2,      2121},
 484         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1595,   2,      2123},
 485         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1631,   2,      2125},
 486         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1667,   2,      2127},
 487         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1703,   2,      2129},
 488         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1739,   2,      2131},
 489         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1775,   2,      2133},
 490         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1811,   2,      2135},
 491         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1847,   2,      2137},
 492         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1848,   2,      2139},
 493         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1884,   2,      2141},
 494         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1920,   2,      2143},
 495         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1956,   2,      2145},
 496         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2020,   2,      2147},
 497         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2021,   3,      2149},
 498         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2022,   3,      2152},
 499         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2023,   2,      2155},
 500         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2024,   2,      2157},
 501         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2025,   4,      2159},
 502         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2026,   5,      2163},
 503         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2027,   4,      2168},
 504         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2028,   5,      2172},
 505         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2029,   1,      2177},
 506         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2030,   4,      2178},
 507         {"cvmx_pko_mem_debug14"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2031,   2,      2182},
 508         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2032,   5,      2184},
 509         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2033,   5,      2189},
 510         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2034,   1,      2194},
 511         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2035,   19,     2195},
 512         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2036,   7,      2214},
 513         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2037,   4,      2221},
 514         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2038,   6,      2225},
 515         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2039,   7,      2231},
 516         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2040,   9,      2238},
 517         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2041,   5,      2247},
 518         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2042,   13,     2252},
 519         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2043,   4,      2265},
 520         {"cvmx_pko_reg_crc_ctl#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2044,   3,      2269},
 521         {"cvmx_pko_reg_crc_enable"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2046,   2,      2272},
 522         {"cvmx_pko_reg_crc_iv#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2047,   2,      2274},
 523         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2049,   2,      2276},
 524         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2050,   3,      2278},
 525         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2051,   5,      2281},
 526         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2052,   3,      2286},
 527         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2053,   3,      2289},
 528         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2054,   2,      2292},
 529         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2055,   3,      2294},
 530         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2056,   13,     2297},
 531         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2057,   2,      2310},
 532         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2058,   9,      2312},
 533         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2059,   3,      2321},
 534         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2060,   2,      2324},
 535         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2068,   2,      2326},
 536         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2069,   2,      2328},
 537         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2070,   2,      2330},
 538         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2071,   2,      2332},
 539         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2087,   5,      2334},
 540         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2095,   8,      2339},
 541         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2103,   2,      2347},
 542         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2104,   2,      2349},
 543         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2105,   2,      2351},
 544         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2113,   3,      2353},
 545         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2114,   4,      2356},
 546         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2130,   5,      2360},
 547         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2131,   7,      2365},
 548         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2147,   2,      2372},
 549         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2163,   3,      2374},
 550         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2164,   5,      2377},
 551         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2165,   8,      2382},
 552         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2166,   6,      2390},
 553         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2167,   2,      2396},
 554         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2168,   4,      2398},
 555         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2169,   4,      2402},
 556         {"cvmx_spx#_bckprs_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2170,   2,      2406},
 557         {"cvmx_spx#_bist_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2172,   4,      2408},
 558         {"cvmx_spx#_clk_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2174,   11,     2412},
 559         {"cvmx_spx#_clk_stat"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2176,   9,      2423},
 560         {"cvmx_spx#_dbg_deskew_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2178,   16,     2432},
 561         {"cvmx_spx#_dbg_deskew_state"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2180,   5,      2448},
 562         {"cvmx_spx#_drv_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2182,   4,      2453},
 563         {"cvmx_spx#_err_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2184,   6,      2457},
 564         {"cvmx_spx#_int_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2186,   6,      2463},
 565         {"cvmx_spx#_int_msk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2188,   12,     2469},
 566         {"cvmx_spx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2190,   14,     2481},
 567         {"cvmx_spx#_int_sync"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2192,   12,     2495},
 568         {"cvmx_spx#_tpa_acc"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2194,   2,      2507},
 569         {"cvmx_spx#_tpa_max"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2196,   2,      2509},
 570         {"cvmx_spx#_tpa_sel"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2198,   2,      2511},
 571         {"cvmx_spx#_trn4_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2200,   8,      2513},
 572         {"cvmx_spx0_pll_bw_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2202,   2,      2521},
 573         {"cvmx_spx0_pll_setting"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2203,   2,      2523},
 574         {"cvmx_srx#_com_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2204,   5,      2525},
 575         {"cvmx_srx#_ign_rx_full"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2206,   2,      2530},
 576         {"cvmx_srx#_spi4_cal#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2208,   6,      2532},
 577         {"cvmx_srx#_spi4_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2272,   4,      2538},
 578         {"cvmx_stx#_arb_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2274,   5,      2542},
 579         {"cvmx_stx#_bckprs_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2276,   2,      2547},
 580         {"cvmx_stx#_com_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2278,   4,      2549},
 581         {"cvmx_stx#_dip_cnt"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2280,   3,      2553},
 582         {"cvmx_stx#_ign_cal"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2282,   2,      2556},
 583         {"cvmx_stx#_int_msk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2284,   9,      2558},
 584         {"cvmx_stx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2286,   10,     2567},
 585         {"cvmx_stx#_int_sync"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2288,   9,      2577},
 586         {"cvmx_stx#_min_bst"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2290,   2,      2586},
 587         {"cvmx_stx#_spi4_cal#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2292,   6,      2588},
 588         {"cvmx_stx#_spi4_dat"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2356,   3,      2594},
 589         {"cvmx_stx#_spi4_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2358,   4,      2597},
 590         {"cvmx_stx#_stat_bytes_hi"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2360,   2,      2601},
 591         {"cvmx_stx#_stat_bytes_lo"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2362,   2,      2603},
 592         {"cvmx_stx#_stat_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2364,   3,      2605},
 593         {"cvmx_stx#_stat_pkt_xmt"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2366,   2,      2608},
 594         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2368,   6,      2610},
 595         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2369,   3,      2616},
 596         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2370,   5,      2619},
 597         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2371,   4,      2624},
 598         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2372,   6,      2628},
 599         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2373,   4,      2634},
 600         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2374,   2,      2638},
 601         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2375,   4,      2640},
 602         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2376,   2,      2644},
 603         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2377,   3,      2646},
 604         {"cvmx_tra_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2378,   4,      2649},
 605         {"cvmx_tra_ctl"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2379,   12,     2653},
 606         {"cvmx_tra_cycles_since"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2380,   3,      2665},
 607         {"cvmx_tra_filt_adr_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2381,   2,      2668},
 608         {"cvmx_tra_filt_adr_msk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2382,   2,      2670},
 609         {"cvmx_tra_filt_cmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2383,   17,     2672},
 610         {"cvmx_tra_filt_did"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2384,   12,     2689},
 611         {"cvmx_tra_filt_sid"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2385,   6,      2701},
 612         {"cvmx_tra_int_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2386,   5,      2707},
 613         {"cvmx_tra_read_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2387,   1,      2712},
 614         {"cvmx_tra_trig0_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2388,   2,      2713},
 615         {"cvmx_tra_trig0_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2389,   2,      2715},
 616         {"cvmx_tra_trig0_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2390,   17,     2717},
 617         {"cvmx_tra_trig0_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2391,   12,     2734},
 618         {"cvmx_tra_trig0_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2392,   6,      2746},
 619         {"cvmx_tra_trig1_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2393,   2,      2752},
 620         {"cvmx_tra_trig1_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2394,   2,      2754},
 621         {"cvmx_tra_trig1_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2395,   17,     2756},
 622         {"cvmx_tra_trig1_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2396,   12,     2773},
 623         {"cvmx_tra_trig1_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2397,   6,      2785},
 624         {"cvmx_zip_cmd_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2398,   3,      2791},
 625         {"cvmx_zip_cmd_buf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2399,   5,      2794},
 626         {"cvmx_zip_cmd_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2400,   3,      2799},
 627         {"cvmx_zip_constants"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2401,   6,      2802},
 628         {"cvmx_zip_debug0"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     2402,   2,      2808},
 629         {"cvmx_zip_error"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     2403,   2,      2810},
 630         {"cvmx_zip_int_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2404,   2,      2812},
 631         {NULL,0,0,0,0,0}
 632 };
 633 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xxp2[] = {
 634         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
 635         {"ASX0_INT_EN"                 ,           0x11800B0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
 636         {"ASX1_INT_EN"                 ,           0x11800B8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
 637         {"ASX0_INT_REG"                ,           0x11800B0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
 638         {"ASX1_INT_REG"                ,           0x11800B8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
 639         {"ASX0_PRT_LOOP"               ,           0x11800B0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
 640         {"ASX1_PRT_LOOP"               ,           0x11800B8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
 641         {"ASX0_RLD_BYPASS"             ,           0x11800B0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
 642         {"ASX1_RLD_BYPASS"             ,           0x11800B8000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
 643         {"ASX0_RLD_BYPASS_SETTING"     ,           0x11800B0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
 644         {"ASX1_RLD_BYPASS_SETTING"     ,           0x11800B8000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
 645         {"ASX0_RLD_COMP"               ,           0x11800B0000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
 646         {"ASX1_RLD_COMP"               ,           0x11800B8000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
 647         {"ASX0_RLD_DATA_DRV"           ,           0x11800B0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
 648         {"ASX1_RLD_DATA_DRV"           ,           0x11800B8000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
 649         {"ASX0_RLD_FCRAM_MODE"         ,           0x11800B0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
 650         {"ASX1_RLD_FCRAM_MODE"         ,           0x11800B8000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
 651         {"ASX0_RLD_NCTL_STRONG"        ,           0x11800B0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
 652         {"ASX1_RLD_NCTL_STRONG"        ,           0x11800B8000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
 653         {"ASX0_RLD_NCTL_WEAK"          ,           0x11800B0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
 654         {"ASX1_RLD_NCTL_WEAK"          ,           0x11800B8000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
 655         {"ASX0_RLD_PCTL_STRONG"        ,           0x11800B0000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
 656         {"ASX1_RLD_PCTL_STRONG"        ,           0x11800B8000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
 657         {"ASX0_RLD_PCTL_WEAK"          ,           0x11800B0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
 658         {"ASX1_RLD_PCTL_WEAK"          ,           0x11800B8000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
 659         {"ASX0_RLD_SETTING"            ,           0x11800B0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
 660         {"ASX1_RLD_SETTING"            ,           0x11800B8000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
 661         {"ASX0_RX_CLK_SET000"          ,           0x11800B0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
 662         {"ASX0_RX_CLK_SET001"          ,           0x11800B0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
 663         {"ASX0_RX_CLK_SET002"          ,           0x11800B0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
 664         {"ASX0_RX_CLK_SET003"          ,           0x11800B0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
 665         {"ASX1_RX_CLK_SET000"          ,           0x11800B8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
 666         {"ASX1_RX_CLK_SET001"          ,           0x11800B8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
 667         {"ASX1_RX_CLK_SET002"          ,           0x11800B8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
 668         {"ASX1_RX_CLK_SET003"          ,           0x11800B8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
 669         {"ASX0_RX_PRT_EN"              ,           0x11800B0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
 670         {"ASX1_RX_PRT_EN"              ,           0x11800B8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
 671         {"ASX0_RX_WOL"                 ,           0x11800B0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
 672         {"ASX1_RX_WOL"                 ,           0x11800B8000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
 673         {"ASX0_RX_WOL_MSK"             ,           0x11800B0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
 674         {"ASX1_RX_WOL_MSK"             ,           0x11800B8000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
 675         {"ASX0_RX_WOL_POWOK"           ,           0x11800B0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
 676         {"ASX1_RX_WOL_POWOK"           ,           0x11800B8000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
 677         {"ASX0_RX_WOL_SIG"             ,           0x11800B0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
 678         {"ASX1_RX_WOL_SIG"             ,           0x11800B8000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
 679         {"ASX0_TX_CLK_SET000"          ,           0x11800B0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
 680         {"ASX0_TX_CLK_SET001"          ,           0x11800B0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
 681         {"ASX0_TX_CLK_SET002"          ,           0x11800B0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
 682         {"ASX0_TX_CLK_SET003"          ,           0x11800B0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
 683         {"ASX1_TX_CLK_SET000"          ,           0x11800B8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
 684         {"ASX1_TX_CLK_SET001"          ,           0x11800B8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
 685         {"ASX1_TX_CLK_SET002"          ,           0x11800B8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
 686         {"ASX1_TX_CLK_SET003"          ,           0x11800B8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
 687         {"ASX0_TX_COMP_BYP"            ,           0x11800B0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
 688         {"ASX1_TX_COMP_BYP"            ,           0x11800B8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
 689         {"ASX0_TX_HI_WATER000"         ,           0x11800B0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
 690         {"ASX0_TX_HI_WATER001"         ,           0x11800B0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
 691         {"ASX0_TX_HI_WATER002"         ,           0x11800B0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
 692         {"ASX0_TX_HI_WATER003"         ,           0x11800B0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
 693         {"ASX1_TX_HI_WATER000"         ,           0x11800B8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
 694         {"ASX1_TX_HI_WATER001"         ,           0x11800B8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
 695         {"ASX1_TX_HI_WATER002"         ,           0x11800B8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
 696         {"ASX1_TX_HI_WATER003"         ,           0x11800B8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
 697         {"ASX0_TX_PRT_EN"              ,           0x11800B0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
 698         {"ASX1_TX_PRT_EN"              ,           0x11800B8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
 699         {"ASX0_DBG_DATA_DRV"           ,           0x11800B0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     23},
 700         {"ASX0_DBG_DATA_ENABLE"        ,           0x11800B0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     24},
 701         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
 702         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
 703         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
 704         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
 705         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 706         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 707         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 708         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 709         {"CIU_INT4_EN0"                ,           0x1070000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 710         {"CIU_INT5_EN0"                ,           0x1070000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 711         {"CIU_INT6_EN0"                ,           0x1070000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 712         {"CIU_INT7_EN0"                ,           0x1070000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 713         {"CIU_INT8_EN0"                ,           0x1070000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 714         {"CIU_INT9_EN0"                ,           0x1070000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 715         {"CIU_INT10_EN0"               ,           0x10700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 716         {"CIU_INT11_EN0"               ,           0x10700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 717         {"CIU_INT12_EN0"               ,           0x10700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 718         {"CIU_INT13_EN0"               ,           0x10700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 719         {"CIU_INT14_EN0"               ,           0x10700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 720         {"CIU_INT15_EN0"               ,           0x10700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 721         {"CIU_INT16_EN0"               ,           0x1070000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 722         {"CIU_INT17_EN0"               ,           0x1070000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 723         {"CIU_INT18_EN0"               ,           0x1070000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 724         {"CIU_INT19_EN0"               ,           0x1070000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 725         {"CIU_INT20_EN0"               ,           0x1070000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 726         {"CIU_INT21_EN0"               ,           0x1070000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 727         {"CIU_INT22_EN0"               ,           0x1070000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 728         {"CIU_INT23_EN0"               ,           0x1070000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 729         {"CIU_INT24_EN0"               ,           0x1070000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 730         {"CIU_INT25_EN0"               ,           0x1070000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 731         {"CIU_INT26_EN0"               ,           0x10700000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 732         {"CIU_INT27_EN0"               ,           0x10700000003B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 733         {"CIU_INT28_EN0"               ,           0x10700000003C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 734         {"CIU_INT29_EN0"               ,           0x10700000003D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 735         {"CIU_INT30_EN0"               ,           0x10700000003E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 736         {"CIU_INT31_EN0"               ,           0x10700000003F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 737         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
 738         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 739         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 740         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 741         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 742         {"CIU_INT4_EN1"                ,           0x1070000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 743         {"CIU_INT5_EN1"                ,           0x1070000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 744         {"CIU_INT6_EN1"                ,           0x1070000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 745         {"CIU_INT7_EN1"                ,           0x1070000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 746         {"CIU_INT8_EN1"                ,           0x1070000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 747         {"CIU_INT9_EN1"                ,           0x1070000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 748         {"CIU_INT10_EN1"               ,           0x10700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 749         {"CIU_INT11_EN1"               ,           0x10700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 750         {"CIU_INT12_EN1"               ,           0x10700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 751         {"CIU_INT13_EN1"               ,           0x10700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 752         {"CIU_INT14_EN1"               ,           0x10700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 753         {"CIU_INT15_EN1"               ,           0x10700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 754         {"CIU_INT16_EN1"               ,           0x1070000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 755         {"CIU_INT17_EN1"               ,           0x1070000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 756         {"CIU_INT18_EN1"               ,           0x1070000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 757         {"CIU_INT19_EN1"               ,           0x1070000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 758         {"CIU_INT20_EN1"               ,           0x1070000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 759         {"CIU_INT21_EN1"               ,           0x1070000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 760         {"CIU_INT22_EN1"               ,           0x1070000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 761         {"CIU_INT23_EN1"               ,           0x1070000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 762         {"CIU_INT24_EN1"               ,           0x1070000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 763         {"CIU_INT25_EN1"               ,           0x1070000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 764         {"CIU_INT26_EN1"               ,           0x10700000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 765         {"CIU_INT27_EN1"               ,           0x10700000003B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 766         {"CIU_INT28_EN1"               ,           0x10700000003C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 767         {"CIU_INT29_EN1"               ,           0x10700000003D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 768         {"CIU_INT30_EN1"               ,           0x10700000003E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 769         {"CIU_INT31_EN1"               ,           0x10700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 770         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
 771         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 772         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 773         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 774         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 775         {"CIU_INT4_SUM0"               ,           0x1070000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 776         {"CIU_INT5_SUM0"               ,           0x1070000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 777         {"CIU_INT6_SUM0"               ,           0x1070000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 778         {"CIU_INT7_SUM0"               ,           0x1070000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 779         {"CIU_INT8_SUM0"               ,           0x1070000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 780         {"CIU_INT9_SUM0"               ,           0x1070000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 781         {"CIU_INT10_SUM0"              ,           0x1070000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 782         {"CIU_INT11_SUM0"              ,           0x1070000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 783         {"CIU_INT12_SUM0"              ,           0x1070000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 784         {"CIU_INT13_SUM0"              ,           0x1070000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 785         {"CIU_INT14_SUM0"              ,           0x1070000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 786         {"CIU_INT15_SUM0"              ,           0x1070000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 787         {"CIU_INT16_SUM0"              ,           0x1070000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 788         {"CIU_INT17_SUM0"              ,           0x1070000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 789         {"CIU_INT18_SUM0"              ,           0x1070000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 790         {"CIU_INT19_SUM0"              ,           0x1070000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 791         {"CIU_INT20_SUM0"              ,           0x10700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 792         {"CIU_INT21_SUM0"              ,           0x10700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 793         {"CIU_INT22_SUM0"              ,           0x10700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 794         {"CIU_INT23_SUM0"              ,           0x10700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 795         {"CIU_INT24_SUM0"              ,           0x10700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 796         {"CIU_INT25_SUM0"              ,           0x10700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 797         {"CIU_INT26_SUM0"              ,           0x10700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 798         {"CIU_INT27_SUM0"              ,           0x10700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 799         {"CIU_INT28_SUM0"              ,           0x10700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 800         {"CIU_INT29_SUM0"              ,           0x10700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 801         {"CIU_INT30_SUM0"              ,           0x10700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 802         {"CIU_INT31_SUM0"              ,           0x10700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 803         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
 804         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
 805         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 806         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 807         {"CIU_MBOX_CLR2"               ,           0x1070000000690ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 808         {"CIU_MBOX_CLR3"               ,           0x1070000000698ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 809         {"CIU_MBOX_CLR4"               ,           0x10700000006A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 810         {"CIU_MBOX_CLR5"               ,           0x10700000006A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 811         {"CIU_MBOX_CLR6"               ,           0x10700000006B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 812         {"CIU_MBOX_CLR7"               ,           0x10700000006B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 813         {"CIU_MBOX_CLR8"               ,           0x10700000006C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 814         {"CIU_MBOX_CLR9"               ,           0x10700000006C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 815         {"CIU_MBOX_CLR10"              ,           0x10700000006D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 816         {"CIU_MBOX_CLR11"              ,           0x10700000006D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 817         {"CIU_MBOX_CLR12"              ,           0x10700000006E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 818         {"CIU_MBOX_CLR13"              ,           0x10700000006E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 819         {"CIU_MBOX_CLR14"              ,           0x10700000006F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 820         {"CIU_MBOX_CLR15"              ,           0x10700000006F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
 821         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 822         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 823         {"CIU_MBOX_SET2"               ,           0x1070000000610ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 824         {"CIU_MBOX_SET3"               ,           0x1070000000618ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 825         {"CIU_MBOX_SET4"               ,           0x1070000000620ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 826         {"CIU_MBOX_SET5"               ,           0x1070000000628ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 827         {"CIU_MBOX_SET6"               ,           0x1070000000630ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 828         {"CIU_MBOX_SET7"               ,           0x1070000000638ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 829         {"CIU_MBOX_SET8"               ,           0x1070000000640ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 830         {"CIU_MBOX_SET9"               ,           0x1070000000648ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 831         {"CIU_MBOX_SET10"              ,           0x1070000000650ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 832         {"CIU_MBOX_SET11"              ,           0x1070000000658ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 833         {"CIU_MBOX_SET12"              ,           0x1070000000660ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 834         {"CIU_MBOX_SET13"              ,           0x1070000000668ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 835         {"CIU_MBOX_SET14"              ,           0x1070000000670ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 836         {"CIU_MBOX_SET15"              ,           0x1070000000678ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
 837         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
 838         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
 839         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
 840         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 841         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 842         {"CIU_PP_POKE2"                ,           0x1070000000590ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 843         {"CIU_PP_POKE3"                ,           0x1070000000598ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 844         {"CIU_PP_POKE4"                ,           0x10700000005A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 845         {"CIU_PP_POKE5"                ,           0x10700000005A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 846         {"CIU_PP_POKE6"                ,           0x10700000005B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 847         {"CIU_PP_POKE7"                ,           0x10700000005B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 848         {"CIU_PP_POKE8"                ,           0x10700000005C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 849         {"CIU_PP_POKE9"                ,           0x10700000005C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 850         {"CIU_PP_POKE10"               ,           0x10700000005D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 851         {"CIU_PP_POKE11"               ,           0x10700000005D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 852         {"CIU_PP_POKE12"               ,           0x10700000005E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 853         {"CIU_PP_POKE13"               ,           0x10700000005E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 854         {"CIU_PP_POKE14"               ,           0x10700000005F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 855         {"CIU_PP_POKE15"               ,           0x10700000005F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
 856         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
 857         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
 858         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     41},
 859         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
 860         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
 861         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
 862         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
 863         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
 864         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 865         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 866         {"CIU_WDOG2"                   ,           0x1070000000510ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 867         {"CIU_WDOG3"                   ,           0x1070000000518ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 868         {"CIU_WDOG4"                   ,           0x1070000000520ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 869         {"CIU_WDOG5"                   ,           0x1070000000528ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 870         {"CIU_WDOG6"                   ,           0x1070000000530ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 871         {"CIU_WDOG7"                   ,           0x1070000000538ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 872         {"CIU_WDOG8"                   ,           0x1070000000540ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 873         {"CIU_WDOG9"                   ,           0x1070000000548ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 874         {"CIU_WDOG10"                  ,           0x1070000000550ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 875         {"CIU_WDOG11"                  ,           0x1070000000558ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 876         {"CIU_WDOG12"                  ,           0x1070000000560ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 877         {"CIU_WDOG13"                  ,           0x1070000000568ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 878         {"CIU_WDOG14"                  ,           0x1070000000570ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 879         {"CIU_WDOG15"                  ,           0x1070000000578ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
 880         {"DBG_DATA"                    ,           0x11F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     45},
 881         {"DFA_BST0"                    ,           0x11800300007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
 882         {"DFA_BST1"                    ,           0x11800300007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
 883         {"DFA_CFG"                     ,           0x1180030000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
 884         {"DFA_DBELL"                   ,           0x1370000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     49},
 885         {"DFA_DIFCTL"                  ,           0x1370600000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
 886         {"DFA_DIFRDPTR"                ,           0x1370200000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     51},
 887         {"DFA_ERR"                     ,           0x1180030000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
 888         {"DFA_MEMCFG0"                 ,           0x1180030000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
 889         {"DFA_MEMCFG1"                 ,           0x1180030000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
 890         {"DFA_MEMCFG2"                 ,           0x1180030000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
 891         {"DFA_MEMFADR"                 ,           0x1180030000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
 892         {"DFA_MEMFCR"                  ,           0x1180030000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
 893         {"DFA_MEMRLD"                  ,           0x1180030000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
 894         {"DFA_NCBCTL"                  ,           0x1180030000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
 895         {"DFA_SBD_DBG0"                ,           0x1180030000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
 896         {"DFA_SBD_DBG1"                ,           0x1180030000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
 897         {"DFA_SBD_DBG2"                ,           0x1180030000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
 898         {"DFA_SBD_DBG3"                ,           0x1180030000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
 899         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
 900         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
 901         {"FPA_FPF1_MARKS"              ,           0x1180028000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
 902         {"FPA_FPF2_MARKS"              ,           0x1180028000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
 903         {"FPA_FPF3_MARKS"              ,           0x1180028000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
 904         {"FPA_FPF4_MARKS"              ,           0x1180028000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
 905         {"FPA_FPF5_MARKS"              ,           0x1180028000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
 906         {"FPA_FPF6_MARKS"              ,           0x1180028000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
 907         {"FPA_FPF7_MARKS"              ,           0x1180028000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
 908         {"FPA_FPF1_SIZE"               ,           0x1180028000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
 909         {"FPA_FPF2_SIZE"               ,           0x1180028000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
 910         {"FPA_FPF3_SIZE"               ,           0x1180028000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
 911         {"FPA_FPF4_SIZE"               ,           0x1180028000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
 912         {"FPA_FPF5_SIZE"               ,           0x1180028000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
 913         {"FPA_FPF6_SIZE"               ,           0x1180028000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
 914         {"FPA_FPF7_SIZE"               ,           0x1180028000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
 915         {"FPA_FPF0_MARKS"              ,           0x1180028000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
 916         {"FPA_FPF0_SIZE"               ,           0x1180028000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
 917         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
 918         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
 919         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
 920         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
 921         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
 922         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
 923         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
 924         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
 925         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
 926         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
 927         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
 928         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
 929         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
 930         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
 931         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
 932         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
 933         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
 934         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
 935         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
 936         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
 937         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
 938         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
 939         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
 940         {"GMX1_BAD_REG"                ,           0x1180010000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
 941         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
 942         {"GMX1_BIST"                   ,           0x1180010000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
 943         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
 944         {"GMX1_INF_MODE"               ,           0x11800100007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
 945         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
 946         {"GMX1_NXA_ADR"                ,           0x1180010000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
 947         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
 948         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
 949         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
 950         {"GMX0_PRT003_CFG"             ,           0x1180008001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
 951         {"GMX1_PRT000_CFG"             ,           0x1180010000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
 952         {"GMX1_PRT001_CFG"             ,           0x1180010000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
 953         {"GMX1_PRT002_CFG"             ,           0x1180010001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
 954         {"GMX1_PRT003_CFG"             ,           0x1180010001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
 955         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
 956         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
 957         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
 958         {"GMX0_RX003_ADR_CAM0"         ,           0x1180008001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
 959         {"GMX1_RX000_ADR_CAM0"         ,           0x1180010000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
 960         {"GMX1_RX001_ADR_CAM0"         ,           0x1180010000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
 961         {"GMX1_RX002_ADR_CAM0"         ,           0x1180010001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
 962         {"GMX1_RX003_ADR_CAM0"         ,           0x1180010001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
 963         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
 964         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
 965         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
 966         {"GMX0_RX003_ADR_CAM1"         ,           0x1180008001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
 967         {"GMX1_RX000_ADR_CAM1"         ,           0x1180010000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
 968         {"GMX1_RX001_ADR_CAM1"         ,           0x1180010000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
 969         {"GMX1_RX002_ADR_CAM1"         ,           0x1180010001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
 970         {"GMX1_RX003_ADR_CAM1"         ,           0x1180010001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
 971         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
 972         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
 973         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
 974         {"GMX0_RX003_ADR_CAM2"         ,           0x1180008001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
 975         {"GMX1_RX000_ADR_CAM2"         ,           0x1180010000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
 976         {"GMX1_RX001_ADR_CAM2"         ,           0x1180010000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
 977         {"GMX1_RX002_ADR_CAM2"         ,           0x1180010001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
 978         {"GMX1_RX003_ADR_CAM2"         ,           0x1180010001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
 979         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
 980         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
 981         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
 982         {"GMX0_RX003_ADR_CAM3"         ,           0x1180008001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
 983         {"GMX1_RX000_ADR_CAM3"         ,           0x1180010000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
 984         {"GMX1_RX001_ADR_CAM3"         ,           0x1180010000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
 985         {"GMX1_RX002_ADR_CAM3"         ,           0x1180010001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
 986         {"GMX1_RX003_ADR_CAM3"         ,           0x1180010001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
 987         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
 988         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
 989         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
 990         {"GMX0_RX003_ADR_CAM4"         ,           0x11800080019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
 991         {"GMX1_RX000_ADR_CAM4"         ,           0x11800100001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
 992         {"GMX1_RX001_ADR_CAM4"         ,           0x11800100009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
 993         {"GMX1_RX002_ADR_CAM4"         ,           0x11800100011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
 994         {"GMX1_RX003_ADR_CAM4"         ,           0x11800100019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
 995         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
 996         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
 997         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
 998         {"GMX0_RX003_ADR_CAM5"         ,           0x11800080019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
 999         {"GMX1_RX000_ADR_CAM5"         ,           0x11800100001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
1000         {"GMX1_RX001_ADR_CAM5"         ,           0x11800100009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
1001         {"GMX1_RX002_ADR_CAM5"         ,           0x11800100011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
1002         {"GMX1_RX003_ADR_CAM5"         ,           0x11800100019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
1003         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
1004         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
1005         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
1006         {"GMX0_RX003_ADR_CAM_EN"       ,           0x1180008001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
1007         {"GMX1_RX000_ADR_CAM_EN"       ,           0x1180010000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
1008         {"GMX1_RX001_ADR_CAM_EN"       ,           0x1180010000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
1009         {"GMX1_RX002_ADR_CAM_EN"       ,           0x1180010001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
1010         {"GMX1_RX003_ADR_CAM_EN"       ,           0x1180010001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
1011         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
1012         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
1013         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
1014         {"GMX0_RX003_ADR_CTL"          ,           0x1180008001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
1015         {"GMX1_RX000_ADR_CTL"          ,           0x1180010000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
1016         {"GMX1_RX001_ADR_CTL"          ,           0x1180010000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
1017         {"GMX1_RX002_ADR_CTL"          ,           0x1180010001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
1018         {"GMX1_RX003_ADR_CTL"          ,           0x1180010001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
1019         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
1020         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
1021         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
1022         {"GMX0_RX003_DECISION"         ,           0x1180008001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
1023         {"GMX1_RX000_DECISION"         ,           0x1180010000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
1024         {"GMX1_RX001_DECISION"         ,           0x1180010000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
1025         {"GMX1_RX002_DECISION"         ,           0x1180010001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
1026         {"GMX1_RX003_DECISION"         ,           0x1180010001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
1027         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
1028         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
1029         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
1030         {"GMX0_RX003_FRM_CHK"          ,           0x1180008001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
1031         {"GMX1_RX000_FRM_CHK"          ,           0x1180010000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
1032         {"GMX1_RX001_FRM_CHK"          ,           0x1180010000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
1033         {"GMX1_RX002_FRM_CHK"          ,           0x1180010001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
1034         {"GMX1_RX003_FRM_CHK"          ,           0x1180010001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
1035         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
1036         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
1037         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
1038         {"GMX0_RX003_FRM_CTL"          ,           0x1180008001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
1039         {"GMX1_RX000_FRM_CTL"          ,           0x1180010000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
1040         {"GMX1_RX001_FRM_CTL"          ,           0x1180010000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
1041         {"GMX1_RX002_FRM_CTL"          ,           0x1180010001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
1042         {"GMX1_RX003_FRM_CTL"          ,           0x1180010001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
1043         {"GMX0_RX000_FRM_MAX"          ,           0x1180008000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
1044         {"GMX0_RX001_FRM_MAX"          ,           0x1180008000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
1045         {"GMX0_RX002_FRM_MAX"          ,           0x1180008001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
1046         {"GMX0_RX003_FRM_MAX"          ,           0x1180008001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
1047         {"GMX1_RX000_FRM_MAX"          ,           0x1180010000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
1048         {"GMX1_RX001_FRM_MAX"          ,           0x1180010000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
1049         {"GMX1_RX002_FRM_MAX"          ,           0x1180010001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
1050         {"GMX1_RX003_FRM_MAX"          ,           0x1180010001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
1051         {"GMX0_RX000_FRM_MIN"          ,           0x1180008000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
1052         {"GMX0_RX001_FRM_MIN"          ,           0x1180008000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
1053         {"GMX0_RX002_FRM_MIN"          ,           0x1180008001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
1054         {"GMX0_RX003_FRM_MIN"          ,           0x1180008001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
1055         {"GMX1_RX000_FRM_MIN"          ,           0x1180010000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
1056         {"GMX1_RX001_FRM_MIN"          ,           0x1180010000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
1057         {"GMX1_RX002_FRM_MIN"          ,           0x1180010001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
1058         {"GMX1_RX003_FRM_MIN"          ,           0x1180010001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
1059         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
1060         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
1061         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
1062         {"GMX0_RX003_IFG"              ,           0x1180008001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
1063         {"GMX1_RX000_IFG"              ,           0x1180010000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
1064         {"GMX1_RX001_IFG"              ,           0x1180010000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
1065         {"GMX1_RX002_IFG"              ,           0x1180010001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
1066         {"GMX1_RX003_IFG"              ,           0x1180010001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
1067         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
1068         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
1069         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
1070         {"GMX0_RX003_INT_EN"           ,           0x1180008001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
1071         {"GMX1_RX000_INT_EN"           ,           0x1180010000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
1072         {"GMX1_RX001_INT_EN"           ,           0x1180010000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
1073         {"GMX1_RX002_INT_EN"           ,           0x1180010001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
1074         {"GMX1_RX003_INT_EN"           ,           0x1180010001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
1075         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
1076         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
1077         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
1078         {"GMX0_RX003_INT_REG"          ,           0x1180008001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
1079         {"GMX1_RX000_INT_REG"          ,           0x1180010000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
1080         {"GMX1_RX001_INT_REG"          ,           0x1180010000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
1081         {"GMX1_RX002_INT_REG"          ,           0x1180010001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
1082         {"GMX1_RX003_INT_REG"          ,           0x1180010001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
1083         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
1084         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
1085         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
1086         {"GMX0_RX003_JABBER"           ,           0x1180008001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
1087         {"GMX1_RX000_JABBER"           ,           0x1180010000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
1088         {"GMX1_RX001_JABBER"           ,           0x1180010000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
1089         {"GMX1_RX002_JABBER"           ,           0x1180010001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
1090         {"GMX1_RX003_JABBER"           ,           0x1180010001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
1091         {"GMX0_RX000_RX_INBND"         ,           0x1180008000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
1092         {"GMX0_RX001_RX_INBND"         ,           0x1180008000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
1093         {"GMX0_RX002_RX_INBND"         ,           0x1180008001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
1094         {"GMX0_RX003_RX_INBND"         ,           0x1180008001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
1095         {"GMX1_RX000_RX_INBND"         ,           0x1180010000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
1096         {"GMX1_RX001_RX_INBND"         ,           0x1180010000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
1097         {"GMX1_RX002_RX_INBND"         ,           0x1180010001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
1098         {"GMX1_RX003_RX_INBND"         ,           0x1180010001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
1099         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
1100         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
1101         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
1102         {"GMX0_RX003_STATS_CTL"        ,           0x1180008001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
1103         {"GMX1_RX000_STATS_CTL"        ,           0x1180010000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
1104         {"GMX1_RX001_STATS_CTL"        ,           0x1180010000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
1105         {"GMX1_RX002_STATS_CTL"        ,           0x1180010001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
1106         {"GMX1_RX003_STATS_CTL"        ,           0x1180010001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
1107         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
1108         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
1109         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
1110         {"GMX0_RX003_STATS_OCTS"       ,           0x1180008001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
1111         {"GMX1_RX000_STATS_OCTS"       ,           0x1180010000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
1112         {"GMX1_RX001_STATS_OCTS"       ,           0x1180010000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
1113         {"GMX1_RX002_STATS_OCTS"       ,           0x1180010001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
1114         {"GMX1_RX003_STATS_OCTS"       ,           0x1180010001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
1115         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
1116         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
1117         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
1118         {"GMX0_RX003_STATS_OCTS_CTL"   ,           0x1180008001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
1119         {"GMX1_RX000_STATS_OCTS_CTL"   ,           0x1180010000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
1120         {"GMX1_RX001_STATS_OCTS_CTL"   ,           0x1180010000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
1121         {"GMX1_RX002_STATS_OCTS_CTL"   ,           0x1180010001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
1122         {"GMX1_RX003_STATS_OCTS_CTL"   ,           0x1180010001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
1123         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
1124         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
1125         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
1126         {"GMX0_RX003_STATS_OCTS_DMAC"  ,           0x11800080018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
1127         {"GMX1_RX000_STATS_OCTS_DMAC"  ,           0x11800100000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
1128         {"GMX1_RX001_STATS_OCTS_DMAC"  ,           0x11800100008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
1129         {"GMX1_RX002_STATS_OCTS_DMAC"  ,           0x11800100010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
1130         {"GMX1_RX003_STATS_OCTS_DMAC"  ,           0x11800100018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
1131         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
1132         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
1133         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
1134         {"GMX0_RX003_STATS_OCTS_DRP"   ,           0x11800080018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
1135         {"GMX1_RX000_STATS_OCTS_DRP"   ,           0x11800100000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
1136         {"GMX1_RX001_STATS_OCTS_DRP"   ,           0x11800100008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
1137         {"GMX1_RX002_STATS_OCTS_DRP"   ,           0x11800100010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
1138         {"GMX1_RX003_STATS_OCTS_DRP"   ,           0x11800100018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
1139         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
1140         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
1141         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
1142         {"GMX0_RX003_STATS_PKTS"       ,           0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
1143         {"GMX1_RX000_STATS_PKTS"       ,           0x1180010000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
1144         {"GMX1_RX001_STATS_PKTS"       ,           0x1180010000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
1145         {"GMX1_RX002_STATS_PKTS"       ,           0x1180010001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
1146         {"GMX1_RX003_STATS_PKTS"       ,           0x1180010001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
1147         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
1148         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
1149         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
1150         {"GMX0_RX003_STATS_PKTS_BAD"   ,           0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
1151         {"GMX1_RX000_STATS_PKTS_BAD"   ,           0x11800100000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
1152         {"GMX1_RX001_STATS_PKTS_BAD"   ,           0x11800100008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
1153         {"GMX1_RX002_STATS_PKTS_BAD"   ,           0x11800100010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
1154         {"GMX1_RX003_STATS_PKTS_BAD"   ,           0x11800100018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
1155         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
1156         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
1157         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
1158         {"GMX0_RX003_STATS_PKTS_CTL"   ,           0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
1159         {"GMX1_RX000_STATS_PKTS_CTL"   ,           0x1180010000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
1160         {"GMX1_RX001_STATS_PKTS_CTL"   ,           0x1180010000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
1161         {"GMX1_RX002_STATS_PKTS_CTL"   ,           0x1180010001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
1162         {"GMX1_RX003_STATS_PKTS_CTL"   ,           0x1180010001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
1163         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
1164         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
1165         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
1166         {"GMX0_RX003_STATS_PKTS_DMAC"  ,           0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
1167         {"GMX1_RX000_STATS_PKTS_DMAC"  ,           0x11800100000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
1168         {"GMX1_RX001_STATS_PKTS_DMAC"  ,           0x11800100008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
1169         {"GMX1_RX002_STATS_PKTS_DMAC"  ,           0x11800100010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
1170         {"GMX1_RX003_STATS_PKTS_DMAC"  ,           0x11800100018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
1171         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
1172         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
1173         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
1174         {"GMX0_RX003_STATS_PKTS_DRP"   ,           0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
1175         {"GMX1_RX000_STATS_PKTS_DRP"   ,           0x11800100000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
1176         {"GMX1_RX001_STATS_PKTS_DRP"   ,           0x11800100008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
1177         {"GMX1_RX002_STATS_PKTS_DRP"   ,           0x11800100010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
1178         {"GMX1_RX003_STATS_PKTS_DRP"   ,           0x11800100018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
1179         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
1180         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
1181         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
1182         {"GMX0_RX003_UDD_SKP"          ,           0x1180008001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
1183         {"GMX1_RX000_UDD_SKP"          ,           0x1180010000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
1184         {"GMX1_RX001_UDD_SKP"          ,           0x1180010000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
1185         {"GMX1_RX002_UDD_SKP"          ,           0x1180010001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
1186         {"GMX1_RX003_UDD_SKP"          ,           0x1180010001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
1187         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
1188         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
1189         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
1190         {"GMX0_RX_BP_DROP003"          ,           0x1180008000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
1191         {"GMX1_RX_BP_DROP000"          ,           0x1180010000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
1192         {"GMX1_RX_BP_DROP001"          ,           0x1180010000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
1193         {"GMX1_RX_BP_DROP002"          ,           0x1180010000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
1194         {"GMX1_RX_BP_DROP003"          ,           0x1180010000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
1195         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
1196         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
1197         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
1198         {"GMX0_RX_BP_OFF003"           ,           0x1180008000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
1199         {"GMX1_RX_BP_OFF000"           ,           0x1180010000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
1200         {"GMX1_RX_BP_OFF001"           ,           0x1180010000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
1201         {"GMX1_RX_BP_OFF002"           ,           0x1180010000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
1202         {"GMX1_RX_BP_OFF003"           ,           0x1180010000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
1203         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
1204         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
1205         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
1206         {"GMX0_RX_BP_ON003"            ,           0x1180008000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
1207         {"GMX1_RX_BP_ON000"            ,           0x1180010000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
1208         {"GMX1_RX_BP_ON001"            ,           0x1180010000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
1209         {"GMX1_RX_BP_ON002"            ,           0x1180010000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
1210         {"GMX1_RX_BP_ON003"            ,           0x1180010000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
1211         {"GMX0_RX_PASS_EN"             ,           0x11800080005F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
1212         {"GMX1_RX_PASS_EN"             ,           0x11800100005F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
1213         {"GMX0_RX_PASS_MAP000"         ,           0x1180008000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1214         {"GMX0_RX_PASS_MAP001"         ,           0x1180008000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1215         {"GMX0_RX_PASS_MAP002"         ,           0x1180008000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1216         {"GMX0_RX_PASS_MAP003"         ,           0x1180008000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1217         {"GMX0_RX_PASS_MAP004"         ,           0x1180008000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1218         {"GMX0_RX_PASS_MAP005"         ,           0x1180008000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1219         {"GMX0_RX_PASS_MAP006"         ,           0x1180008000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1220         {"GMX0_RX_PASS_MAP007"         ,           0x1180008000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1221         {"GMX0_RX_PASS_MAP008"         ,           0x1180008000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1222         {"GMX0_RX_PASS_MAP009"         ,           0x1180008000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1223         {"GMX0_RX_PASS_MAP010"         ,           0x1180008000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1224         {"GMX0_RX_PASS_MAP011"         ,           0x1180008000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1225         {"GMX0_RX_PASS_MAP012"         ,           0x1180008000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1226         {"GMX0_RX_PASS_MAP013"         ,           0x1180008000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1227         {"GMX0_RX_PASS_MAP014"         ,           0x1180008000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1228         {"GMX0_RX_PASS_MAP015"         ,           0x1180008000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1229         {"GMX1_RX_PASS_MAP000"         ,           0x1180010000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1230         {"GMX1_RX_PASS_MAP001"         ,           0x1180010000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1231         {"GMX1_RX_PASS_MAP002"         ,           0x1180010000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1232         {"GMX1_RX_PASS_MAP003"         ,           0x1180010000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1233         {"GMX1_RX_PASS_MAP004"         ,           0x1180010000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1234         {"GMX1_RX_PASS_MAP005"         ,           0x1180010000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1235         {"GMX1_RX_PASS_MAP006"         ,           0x1180010000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1236         {"GMX1_RX_PASS_MAP007"         ,           0x1180010000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1237         {"GMX1_RX_PASS_MAP008"         ,           0x1180010000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1238         {"GMX1_RX_PASS_MAP009"         ,           0x1180010000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1239         {"GMX1_RX_PASS_MAP010"         ,           0x1180010000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1240         {"GMX1_RX_PASS_MAP011"         ,           0x1180010000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1241         {"GMX1_RX_PASS_MAP012"         ,           0x1180010000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1242         {"GMX1_RX_PASS_MAP013"         ,           0x1180010000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1243         {"GMX1_RX_PASS_MAP014"         ,           0x1180010000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1244         {"GMX1_RX_PASS_MAP015"         ,           0x1180010000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
1245         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
1246         {"GMX1_RX_PRTS"                ,           0x1180010000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
1247         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
1248         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
1249         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
1250         {"GMX0_SMAC003"                ,           0x1180008001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
1251         {"GMX1_SMAC000"                ,           0x1180010000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
1252         {"GMX1_SMAC001"                ,           0x1180010000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
1253         {"GMX1_SMAC002"                ,           0x1180010001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
1254         {"GMX1_SMAC003"                ,           0x1180010001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
1255         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
1256         {"GMX1_STAT_BP"                ,           0x1180010000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
1257         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
1258         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
1259         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
1260         {"GMX0_TX003_APPEND"           ,           0x1180008001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
1261         {"GMX1_TX000_APPEND"           ,           0x1180010000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
1262         {"GMX1_TX001_APPEND"           ,           0x1180010000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
1263         {"GMX1_TX002_APPEND"           ,           0x1180010001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
1264         {"GMX1_TX003_APPEND"           ,           0x1180010001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
1265         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
1266         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
1267         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
1268         {"GMX0_TX003_BURST"            ,           0x1180008001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
1269         {"GMX1_TX000_BURST"            ,           0x1180010000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
1270         {"GMX1_TX001_BURST"            ,           0x1180010000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
1271         {"GMX1_TX002_BURST"            ,           0x1180010001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
1272         {"GMX1_TX003_BURST"            ,           0x1180010001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
1273         {"GMX0_TX000_CLK"              ,           0x1180008000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
1274         {"GMX0_TX001_CLK"              ,           0x1180008000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
1275         {"GMX0_TX002_CLK"              ,           0x1180008001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
1276         {"GMX0_TX003_CLK"              ,           0x1180008001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
1277         {"GMX1_TX000_CLK"              ,           0x1180010000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
1278         {"GMX1_TX001_CLK"              ,           0x1180010000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
1279         {"GMX1_TX002_CLK"              ,           0x1180010001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
1280         {"GMX1_TX003_CLK"              ,           0x1180010001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
1281         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
1282         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
1283         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
1284         {"GMX0_TX003_CTL"              ,           0x1180008001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
1285         {"GMX1_TX000_CTL"              ,           0x1180010000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
1286         {"GMX1_TX001_CTL"              ,           0x1180010000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
1287         {"GMX1_TX002_CTL"              ,           0x1180010001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
1288         {"GMX1_TX003_CTL"              ,           0x1180010001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
1289         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
1290         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
1291         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
1292         {"GMX0_TX003_MIN_PKT"          ,           0x1180008001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
1293         {"GMX1_TX000_MIN_PKT"          ,           0x1180010000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
1294         {"GMX1_TX001_MIN_PKT"          ,           0x1180010000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
1295         {"GMX1_TX002_MIN_PKT"          ,           0x1180010001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
1296         {"GMX1_TX003_MIN_PKT"          ,           0x1180010001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
1297         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
1298         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
1299         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
1300         {"GMX0_TX003_PAUSE_PKT_INTERVAL",          0x1180008001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
1301         {"GMX1_TX000_PAUSE_PKT_INTERVAL",          0x1180010000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
1302         {"GMX1_TX001_PAUSE_PKT_INTERVAL",          0x1180010000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
1303         {"GMX1_TX002_PAUSE_PKT_INTERVAL",          0x1180010001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
1304         {"GMX1_TX003_PAUSE_PKT_INTERVAL",          0x1180010001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
1305         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
1306         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
1307         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
1308         {"GMX0_TX003_PAUSE_PKT_TIME"   ,           0x1180008001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
1309         {"GMX1_TX000_PAUSE_PKT_TIME"   ,           0x1180010000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
1310         {"GMX1_TX001_PAUSE_PKT_TIME"   ,           0x1180010000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
1311         {"GMX1_TX002_PAUSE_PKT_TIME"   ,           0x1180010001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
1312         {"GMX1_TX003_PAUSE_PKT_TIME"   ,           0x1180010001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
1313         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
1314         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
1315         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
1316         {"GMX0_TX003_PAUSE_TOGO"       ,           0x1180008001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
1317         {"GMX1_TX000_PAUSE_TOGO"       ,           0x1180010000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
1318         {"GMX1_TX001_PAUSE_TOGO"       ,           0x1180010000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
1319         {"GMX1_TX002_PAUSE_TOGO"       ,           0x1180010001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
1320         {"GMX1_TX003_PAUSE_TOGO"       ,           0x1180010001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
1321         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
1322         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
1323         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
1324         {"GMX0_TX003_PAUSE_ZERO"       ,           0x1180008001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
1325         {"GMX1_TX000_PAUSE_ZERO"       ,           0x1180010000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
1326         {"GMX1_TX001_PAUSE_ZERO"       ,           0x1180010000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
1327         {"GMX1_TX002_PAUSE_ZERO"       ,           0x1180010001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
1328         {"GMX1_TX003_PAUSE_ZERO"       ,           0x1180010001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
1329         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
1330         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
1331         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
1332         {"GMX0_TX003_SLOT"             ,           0x1180008001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
1333         {"GMX1_TX000_SLOT"             ,           0x1180010000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
1334         {"GMX1_TX001_SLOT"             ,           0x1180010000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
1335         {"GMX1_TX002_SLOT"             ,           0x1180010001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
1336         {"GMX1_TX003_SLOT"             ,           0x1180010001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
1337         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
1338         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
1339         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
1340         {"GMX0_TX003_SOFT_PAUSE"       ,           0x1180008001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
1341         {"GMX1_TX000_SOFT_PAUSE"       ,           0x1180010000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
1342         {"GMX1_TX001_SOFT_PAUSE"       ,           0x1180010000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
1343         {"GMX1_TX002_SOFT_PAUSE"       ,           0x1180010001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
1344         {"GMX1_TX003_SOFT_PAUSE"       ,           0x1180010001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
1345         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
1346         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
1347         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
1348         {"GMX0_TX003_STAT0"            ,           0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
1349         {"GMX1_TX000_STAT0"            ,           0x1180010000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
1350         {"GMX1_TX001_STAT0"            ,           0x1180010000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
1351         {"GMX1_TX002_STAT0"            ,           0x1180010001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
1352         {"GMX1_TX003_STAT0"            ,           0x1180010001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
1353         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
1354         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
1355         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
1356         {"GMX0_TX003_STAT1"            ,           0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
1357         {"GMX1_TX000_STAT1"            ,           0x1180010000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
1358         {"GMX1_TX001_STAT1"            ,           0x1180010000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
1359         {"GMX1_TX002_STAT1"            ,           0x1180010001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
1360         {"GMX1_TX003_STAT1"            ,           0x1180010001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
1361         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
1362         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
1363         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
1364         {"GMX0_TX003_STAT2"            ,           0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
1365         {"GMX1_TX000_STAT2"            ,           0x1180010000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
1366         {"GMX1_TX001_STAT2"            ,           0x1180010000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
1367         {"GMX1_TX002_STAT2"            ,           0x1180010001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
1368         {"GMX1_TX003_STAT2"            ,           0x1180010001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
1369         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
1370         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
1371         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
1372         {"GMX0_TX003_STAT3"            ,           0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
1373         {"GMX1_TX000_STAT3"            ,           0x1180010000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
1374         {"GMX1_TX001_STAT3"            ,           0x1180010000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
1375         {"GMX1_TX002_STAT3"            ,           0x1180010001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
1376         {"GMX1_TX003_STAT3"            ,           0x1180010001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
1377         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
1378         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
1379         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
1380         {"GMX0_TX003_STAT4"            ,           0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
1381         {"GMX1_TX000_STAT4"            ,           0x11800100002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
1382         {"GMX1_TX001_STAT4"            ,           0x1180010000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
1383         {"GMX1_TX002_STAT4"            ,           0x11800100012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
1384         {"GMX1_TX003_STAT4"            ,           0x1180010001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
1385         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
1386         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
1387         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
1388         {"GMX0_TX003_STAT5"            ,           0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
1389         {"GMX1_TX000_STAT5"            ,           0x11800100002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
1390         {"GMX1_TX001_STAT5"            ,           0x1180010000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
1391         {"GMX1_TX002_STAT5"            ,           0x11800100012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
1392         {"GMX1_TX003_STAT5"            ,           0x1180010001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
1393         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
1394         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
1395         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
1396         {"GMX0_TX003_STAT6"            ,           0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
1397         {"GMX1_TX000_STAT6"            ,           0x11800100002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
1398         {"GMX1_TX001_STAT6"            ,           0x1180010000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
1399         {"GMX1_TX002_STAT6"            ,           0x11800100012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
1400         {"GMX1_TX003_STAT6"            ,           0x1180010001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
1401         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
1402         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
1403         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
1404         {"GMX0_TX003_STAT7"            ,           0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
1405         {"GMX1_TX000_STAT7"            ,           0x11800100002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
1406         {"GMX1_TX001_STAT7"            ,           0x1180010000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
1407         {"GMX1_TX002_STAT7"            ,           0x11800100012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
1408         {"GMX1_TX003_STAT7"            ,           0x1180010001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
1409         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
1410         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
1411         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
1412         {"GMX0_TX003_STAT8"            ,           0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
1413         {"GMX1_TX000_STAT8"            ,           0x11800100002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
1414         {"GMX1_TX001_STAT8"            ,           0x1180010000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
1415         {"GMX1_TX002_STAT8"            ,           0x11800100012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
1416         {"GMX1_TX003_STAT8"            ,           0x1180010001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
1417         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
1418         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
1419         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
1420         {"GMX0_TX003_STAT9"            ,           0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
1421         {"GMX1_TX000_STAT9"            ,           0x11800100002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
1422         {"GMX1_TX001_STAT9"            ,           0x1180010000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
1423         {"GMX1_TX002_STAT9"            ,           0x11800100012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
1424         {"GMX1_TX003_STAT9"            ,           0x1180010001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
1425         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
1426         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
1427         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
1428         {"GMX0_TX003_STATS_CTL"        ,           0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
1429         {"GMX1_TX000_STATS_CTL"        ,           0x1180010000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
1430         {"GMX1_TX001_STATS_CTL"        ,           0x1180010000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
1431         {"GMX1_TX002_STATS_CTL"        ,           0x1180010001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
1432         {"GMX1_TX003_STATS_CTL"        ,           0x1180010001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
1433         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
1434         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
1435         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
1436         {"GMX0_TX003_THRESH"           ,           0x1180008001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
1437         {"GMX1_TX000_THRESH"           ,           0x1180010000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
1438         {"GMX1_TX001_THRESH"           ,           0x1180010000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
1439         {"GMX1_TX002_THRESH"           ,           0x1180010001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
1440         {"GMX1_TX003_THRESH"           ,           0x1180010001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
1441         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
1442         {"GMX1_TX_BP"                  ,           0x11800100004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
1443         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
1444         {"GMX1_TX_COL_ATTEMPT"         ,           0x1180010000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
1445         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
1446         {"GMX1_TX_CORRUPT"             ,           0x11800100004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
1447         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
1448         {"GMX1_TX_IFG"                 ,           0x1180010000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
1449         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
1450         {"GMX1_TX_INT_EN"              ,           0x1180010000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
1451         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
1452         {"GMX1_TX_INT_REG"             ,           0x1180010000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
1453         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
1454         {"GMX1_TX_JAM"                 ,           0x1180010000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
1455         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
1456         {"GMX1_TX_LFSR"                ,           0x11800100004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
1457         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
1458         {"GMX1_TX_OVR_BP"              ,           0x11800100004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
1459         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
1460         {"GMX1_TX_PAUSE_PKT_DMAC"      ,           0x11800100004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
1461         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
1462         {"GMX1_TX_PAUSE_PKT_TYPE"      ,           0x11800100004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
1463         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
1464         {"GMX1_TX_PRTS"                ,           0x1180010000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
1465         {"GMX0_TX_SPI_CTL"             ,           0x11800080004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
1466         {"GMX1_TX_SPI_CTL"             ,           0x11800100004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
1467         {"GMX0_TX_SPI_MAX"             ,           0x11800080004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
1468         {"GMX1_TX_SPI_MAX"             ,           0x11800100004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
1469         {"GMX0_TX_SPI_THRESH"          ,           0x11800080004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
1470         {"GMX1_TX_SPI_THRESH"          ,           0x11800100004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
1471         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1472         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1473         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1474         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1475         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1476         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1477         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1478         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1479         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1480         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1481         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1482         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1483         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1484         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1485         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1486         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
1487         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     159},
1488         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
1489         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
1490         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     162},
1491         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
1492         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
1493         {"IOB_DWB_PRI_CNT"             ,           0x11800F0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
1494         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
1495         {"IOB_I2C_PRI_CNT"             ,           0x11800F0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
1496         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
1497         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
1498         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
1499         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
1500         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
1501         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
1502         {"IOB_N2C_L2C_PRI_CNT"         ,           0x11800F0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
1503         {"IOB_N2C_RSP_PRI_CNT"         ,           0x11800F0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
1504         {"IOB_OUTB_COM_PRI_CNT"        ,           0x11800F0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
1505         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
1506         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
1507         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
1508         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
1509         {"IOB_OUTB_FPA_PRI_CNT"        ,           0x11800F0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
1510         {"IOB_OUTB_REQ_PRI_CNT"        ,           0x11800F0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
1511         {"IOB_P2C_REQ_PRI_CNT"         ,           0x11800F0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
1512         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
1513         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     185},
1514         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     186},
1515         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     187},
1516         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     188},
1517         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     189},
1518         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     190},
1519         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
1520         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
1521         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     193},
1522         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     194},
1523         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     195},
1524         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1525         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1526         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1527         {"IPD_PORT3_BP_PAGE_CNT"       ,           0x14F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1528         {"IPD_PORT4_BP_PAGE_CNT"       ,           0x14F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1529         {"IPD_PORT5_BP_PAGE_CNT"       ,           0x14F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1530         {"IPD_PORT6_BP_PAGE_CNT"       ,           0x14F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1531         {"IPD_PORT7_BP_PAGE_CNT"       ,           0x14F0000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1532         {"IPD_PORT8_BP_PAGE_CNT"       ,           0x14F0000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1533         {"IPD_PORT9_BP_PAGE_CNT"       ,           0x14F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1534         {"IPD_PORT10_BP_PAGE_CNT"      ,           0x14F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1535         {"IPD_PORT11_BP_PAGE_CNT"      ,           0x14F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1536         {"IPD_PORT12_BP_PAGE_CNT"      ,           0x14F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1537         {"IPD_PORT13_BP_PAGE_CNT"      ,           0x14F0000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1538         {"IPD_PORT14_BP_PAGE_CNT"      ,           0x14F0000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1539         {"IPD_PORT15_BP_PAGE_CNT"      ,           0x14F00000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1540         {"IPD_PORT16_BP_PAGE_CNT"      ,           0x14F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1541         {"IPD_PORT17_BP_PAGE_CNT"      ,           0x14F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1542         {"IPD_PORT18_BP_PAGE_CNT"      ,           0x14F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1543         {"IPD_PORT19_BP_PAGE_CNT"      ,           0x14F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1544         {"IPD_PORT20_BP_PAGE_CNT"      ,           0x14F00000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1545         {"IPD_PORT21_BP_PAGE_CNT"      ,           0x14F00000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1546         {"IPD_PORT22_BP_PAGE_CNT"      ,           0x14F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1547         {"IPD_PORT23_BP_PAGE_CNT"      ,           0x14F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1548         {"IPD_PORT24_BP_PAGE_CNT"      ,           0x14F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1549         {"IPD_PORT25_BP_PAGE_CNT"      ,           0x14F00000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1550         {"IPD_PORT26_BP_PAGE_CNT"      ,           0x14F00000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1551         {"IPD_PORT27_BP_PAGE_CNT"      ,           0x14F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1552         {"IPD_PORT28_BP_PAGE_CNT"      ,           0x14F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1553         {"IPD_PORT29_BP_PAGE_CNT"      ,           0x14F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1554         {"IPD_PORT30_BP_PAGE_CNT"      ,           0x14F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1555         {"IPD_PORT31_BP_PAGE_CNT"      ,           0x14F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1556         {"IPD_PORT32_BP_PAGE_CNT"      ,           0x14F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1557         {"IPD_PORT33_BP_PAGE_CNT"      ,           0x14F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1558         {"IPD_PORT34_BP_PAGE_CNT"      ,           0x14F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1559         {"IPD_PORT35_BP_PAGE_CNT"      ,           0x14F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
1560         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1561         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1562         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1563         {"IPD_PORT_BP_COUNTERS_PAIR3"  ,           0x14F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1564         {"IPD_PORT_BP_COUNTERS_PAIR4"  ,           0x14F00000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1565         {"IPD_PORT_BP_COUNTERS_PAIR5"  ,           0x14F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1566         {"IPD_PORT_BP_COUNTERS_PAIR6"  ,           0x14F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1567         {"IPD_PORT_BP_COUNTERS_PAIR7"  ,           0x14F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1568         {"IPD_PORT_BP_COUNTERS_PAIR8"  ,           0x14F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1569         {"IPD_PORT_BP_COUNTERS_PAIR9"  ,           0x14F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1570         {"IPD_PORT_BP_COUNTERS_PAIR10" ,           0x14F0000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1571         {"IPD_PORT_BP_COUNTERS_PAIR11" ,           0x14F0000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1572         {"IPD_PORT_BP_COUNTERS_PAIR12" ,           0x14F0000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1573         {"IPD_PORT_BP_COUNTERS_PAIR13" ,           0x14F0000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1574         {"IPD_PORT_BP_COUNTERS_PAIR14" ,           0x14F0000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1575         {"IPD_PORT_BP_COUNTERS_PAIR15" ,           0x14F0000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1576         {"IPD_PORT_BP_COUNTERS_PAIR16" ,           0x14F0000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1577         {"IPD_PORT_BP_COUNTERS_PAIR17" ,           0x14F0000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1578         {"IPD_PORT_BP_COUNTERS_PAIR18" ,           0x14F0000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1579         {"IPD_PORT_BP_COUNTERS_PAIR19" ,           0x14F0000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1580         {"IPD_PORT_BP_COUNTERS_PAIR20" ,           0x14F0000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1581         {"IPD_PORT_BP_COUNTERS_PAIR21" ,           0x14F0000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1582         {"IPD_PORT_BP_COUNTERS_PAIR22" ,           0x14F0000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1583         {"IPD_PORT_BP_COUNTERS_PAIR23" ,           0x14F0000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1584         {"IPD_PORT_BP_COUNTERS_PAIR24" ,           0x14F0000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1585         {"IPD_PORT_BP_COUNTERS_PAIR25" ,           0x14F0000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1586         {"IPD_PORT_BP_COUNTERS_PAIR26" ,           0x14F0000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1587         {"IPD_PORT_BP_COUNTERS_PAIR27" ,           0x14F0000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1588         {"IPD_PORT_BP_COUNTERS_PAIR28" ,           0x14F0000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1589         {"IPD_PORT_BP_COUNTERS_PAIR29" ,           0x14F00000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1590         {"IPD_PORT_BP_COUNTERS_PAIR30" ,           0x14F00000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1591         {"IPD_PORT_BP_COUNTERS_PAIR31" ,           0x14F00000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1592         {"IPD_PORT_BP_COUNTERS_PAIR32" ,           0x14F00000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1593         {"IPD_PORT_BP_COUNTERS_PAIR33" ,           0x14F00000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1594         {"IPD_PORT_BP_COUNTERS_PAIR34" ,           0x14F00000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1595         {"IPD_PORT_BP_COUNTERS_PAIR35" ,           0x14F00000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
1596         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     198},
1597         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
1598         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
1599         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
1600         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
1601         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
1602         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
1603         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
1604         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
1605         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
1606         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
1607         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
1608         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
1609         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
1610         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
1611         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
1612         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
1613         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
1614         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
1615         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     203},
1616         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     204},
1617         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
1618         {"KEY_BIST_REG"                ,           0x1180020000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     206},
1619         {"KEY_CTL_STATUS"              ,           0x1180020000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     207},
1620         {"KEY_INT_ENB"                 ,           0x1180020000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     208},
1621         {"KEY_INT_SUM"                 ,           0x1180020000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     209},
1622         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     210},
1623         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     211},
1624         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     212},
1625         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     213},
1626         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
1627         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
1628         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
1629         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
1630         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
1631         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     219},
1632         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     220},
1633         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     221},
1634         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
1635         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
1636         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
1637         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
1638         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
1639         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
1640         {"L2C_SPAR1"                   ,           0x1180080000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     225},
1641         {"L2C_SPAR2"                   ,           0x1180080000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     226},
1642         {"L2C_SPAR3"                   ,           0x1180080000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     227},
1643         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
1644         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
1645         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
1646         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
1647         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     232},
1648         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
1649         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     234},
1650         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     235},
1651         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     236},
1652         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     237},
1653         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
1654         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     239},
1655         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     240},
1656         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
1657         {"LED_BLINK"                   ,           0x1180000001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
1658         {"LED_CLK_PHASE"               ,           0x1180000001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     243},
1659         {"LED_CYLON"                   ,           0x1180000001AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     244},
1660         {"LED_DBG"                     ,           0x1180000001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     245},
1661         {"LED_EN"                      ,           0x1180000001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     246},
1662         {"LED_POLARITY"                ,           0x1180000001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     247},
1663         {"LED_PRT"                     ,           0x1180000001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     248},
1664         {"LED_PRT_FMT"                 ,           0x1180000001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     249},
1665         {"LED_PRT_STATUS0"             ,           0x1180000001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
1666         {"LED_PRT_STATUS1"             ,           0x1180000001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
1667         {"LED_PRT_STATUS2"             ,           0x1180000001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
1668         {"LED_PRT_STATUS3"             ,           0x1180000001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
1669         {"LED_PRT_STATUS4"             ,           0x1180000001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
1670         {"LED_PRT_STATUS5"             ,           0x1180000001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
1671         {"LED_PRT_STATUS6"             ,           0x1180000001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
1672         {"LED_PRT_STATUS7"             ,           0x1180000001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
1673         {"LED_UDD_CNT0"                ,           0x1180000001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
1674         {"LED_UDD_CNT1"                ,           0x1180000001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
1675         {"LED_UDD_DAT0"                ,           0x1180000001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
1676         {"LED_UDD_DAT1"                ,           0x1180000001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
1677         {"LED_UDD_DAT_CLR0"            ,           0x1180000001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
1678         {"LED_UDD_DAT_CLR1"            ,           0x1180000001AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
1679         {"LED_UDD_DAT_SET0"            ,           0x1180000001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
1680         {"LED_UDD_DAT_SET1"            ,           0x1180000001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
1681         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
1682         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
1683         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
1684         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
1685         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
1686         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
1687         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
1688         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
1689         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
1690         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
1691         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
1692         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
1693         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
1694         {"LMC0_PLL_BWCTL"              ,           0x1180088000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
1695         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
1696         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
1697         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
1698         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
1699         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
1700         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
1701         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
1702         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
1703         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
1704         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
1705         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
1706         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
1707         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
1708         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
1709         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
1710         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
1711         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
1712         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
1713         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
1714         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
1715         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
1716         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
1717         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
1718         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
1719         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
1720         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
1721         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
1722         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
1723         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
1724         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
1725         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
1726         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
1727         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
1728         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     287},
1729         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     288},
1730         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     289},
1731         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
1732         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
1733         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
1734         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     292},
1735         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     292},
1736         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
1737         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
1738         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     294},
1739         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     294},
1740         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     295},
1741         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     295},
1742         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     296},
1743         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     296},
1744         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
1745         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
1746         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     298},
1747         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     298},
1748         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
1749         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
1750         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
1751         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
1752         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
1753         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
1754         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
1755         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
1756         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
1757         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
1758         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
1759         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
1760         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
1761         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
1762         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
1763         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
1764         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
1765         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
1766         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
1767         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
1768         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
1769         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
1770         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
1771         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
1772         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
1773         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
1774         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
1775         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
1776         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
1777         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
1778         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
1779         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
1780         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
1781         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
1782         {"NPI_BASE_ADDR_INPUT0"        ,           0x11F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     316},
1783         {"NPI_BASE_ADDR_INPUT1"        ,           0x11F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     316},
1784         {"NPI_BASE_ADDR_INPUT2"        ,           0x11F0000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     316},
1785         {"NPI_BASE_ADDR_INPUT3"        ,           0x11F00000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     316},
1786         {"NPI_BASE_ADDR_OUTPUT0"       ,           0x11F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     317},
1787         {"NPI_BASE_ADDR_OUTPUT1"       ,           0x11F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     317},
1788         {"NPI_BASE_ADDR_OUTPUT2"       ,           0x11F00000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     317},
1789         {"NPI_BASE_ADDR_OUTPUT3"       ,           0x11F00000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     317},
1790         {"NPI_BIST_STATUS"             ,           0x11F00000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     318},
1791         {"NPI_BUFF_SIZE_OUTPUT0"       ,           0x11F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     319},
1792         {"NPI_BUFF_SIZE_OUTPUT1"       ,           0x11F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     319},
1793         {"NPI_BUFF_SIZE_OUTPUT2"       ,           0x11F00000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     319},
1794         {"NPI_BUFF_SIZE_OUTPUT3"       ,           0x11F00000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     319},
1795         {"NPI_CTL_STATUS"              ,           0x11F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     320},
1796         {"NPI_DBG_SELECT"              ,           0x11F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     321},
1797         {"NPI_DMA_CONTROL"             ,           0x11F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     322},
1798         {"NPI_DMA_HIGHP_COUNTS"        ,           0x11F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     323},
1799         {"NPI_DMA_HIGHP_NADDR"         ,           0x11F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     324},
1800         {"NPI_DMA_LOWP_COUNTS"         ,           0x11F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     325},
1801         {"NPI_DMA_LOWP_NADDR"          ,           0x11F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     326},
1802         {"NPI_HIGHP_DBELL"             ,           0x11F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     327},
1803         {"NPI_HIGHP_IBUFF_SADDR"       ,           0x11F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     328},
1804         {"NPI_INPUT_CONTROL"           ,           0x11F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     329},
1805         {"NPI_INT_ENB"                 ,           0x11F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     330},
1806         {"NPI_INT_SUM"                 ,           0x11F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     331},
1807         {"NPI_LOWP_DBELL"              ,           0x11F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     332},
1808         {"NPI_LOWP_IBUFF_SADDR"        ,           0x11F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     333},
1809         {"NPI_MEM_ACCESS_SUBID3"       ,           0x11F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     334},
1810         {"NPI_MEM_ACCESS_SUBID4"       ,           0x11F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     334},
1811         {"NPI_MEM_ACCESS_SUBID5"       ,           0x11F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     334},
1812         {"NPI_MEM_ACCESS_SUBID6"       ,           0x11F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     334},
1813         {"NPI_MSI_RCV"                 ,           0x11F0000001190ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     335},
1814         {"NPI_NUM_DESC_OUTPUT0"        ,           0x11F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     336},
1815         {"NPI_NUM_DESC_OUTPUT1"        ,           0x11F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     336},
1816         {"NPI_NUM_DESC_OUTPUT2"        ,           0x11F0000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     336},
1817         {"NPI_NUM_DESC_OUTPUT3"        ,           0x11F0000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     336},
1818         {"NPI_OUTPUT_CONTROL"          ,           0x11F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     337},
1819         {"NPI_P0_DBPAIR_ADDR"          ,           0x11F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     338},
1820         {"NPI_P1_DBPAIR_ADDR"          ,           0x11F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     338},
1821         {"NPI_P2_DBPAIR_ADDR"          ,           0x11F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     338},
1822         {"NPI_P3_DBPAIR_ADDR"          ,           0x11F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     338},
1823         {"NPI_P0_INSTR_ADDR"           ,           0x11F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     339},
1824         {"NPI_P1_INSTR_ADDR"           ,           0x11F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     339},
1825         {"NPI_P2_INSTR_ADDR"           ,           0x11F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     339},
1826         {"NPI_P3_INSTR_ADDR"           ,           0x11F00000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     339},
1827         {"NPI_P0_INSTR_CNTS"           ,           0x11F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     340},
1828         {"NPI_P1_INSTR_CNTS"           ,           0x11F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     340},
1829         {"NPI_P2_INSTR_CNTS"           ,           0x11F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     340},
1830         {"NPI_P3_INSTR_CNTS"           ,           0x11F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     340},
1831         {"NPI_P0_PAIR_CNTS"            ,           0x11F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     341},
1832         {"NPI_P1_PAIR_CNTS"            ,           0x11F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     341},
1833         {"NPI_P2_PAIR_CNTS"            ,           0x11F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     341},
1834         {"NPI_P3_PAIR_CNTS"            ,           0x11F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     341},
1835         {"NPI_PCI_BURST_SIZE"          ,           0x11F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     342},
1836         {"NPI_PCI_INT_ARB_CFG"         ,           0x11F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     343},
1837         {"NPI_PCI_READ_CMD"            ,           0x11F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     344},
1838         {"NPI_PORT32_INSTR_HDR"        ,           0x11F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     345},
1839         {"NPI_PORT33_INSTR_HDR"        ,           0x11F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
1840         {"NPI_PORT34_INSTR_HDR"        ,           0x11F0000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     347},
1841         {"NPI_PORT35_INSTR_HDR"        ,           0x11F0000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
1842         {"NPI_PORT_BP_CONTROL"         ,           0x11F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     349},
1843         {"NPI_RSL_INT_BLOCKS"          ,           0x11F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     350},
1844         {"NPI_SIZE_INPUT0"             ,           0x11F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
1845         {"NPI_SIZE_INPUT1"             ,           0x11F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
1846         {"NPI_SIZE_INPUT2"             ,           0x11F0000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
1847         {"NPI_SIZE_INPUT3"             ,           0x11F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
1848         {"NPI_WIN_READ_TO"             ,           0x11F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     352},
1849         {"PCI_BAR1_INDEX0"             ,           0x11F0000001100ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1850         {"PCI_BAR1_INDEX1"             ,           0x11F0000001104ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1851         {"PCI_BAR1_INDEX2"             ,           0x11F0000001108ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1852         {"PCI_BAR1_INDEX3"             ,           0x11F000000110Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1853         {"PCI_BAR1_INDEX4"             ,           0x11F0000001110ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1854         {"PCI_BAR1_INDEX5"             ,           0x11F0000001114ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1855         {"PCI_BAR1_INDEX6"             ,           0x11F0000001118ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1856         {"PCI_BAR1_INDEX7"             ,           0x11F000000111Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1857         {"PCI_BAR1_INDEX8"             ,           0x11F0000001120ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1858         {"PCI_BAR1_INDEX9"             ,           0x11F0000001124ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1859         {"PCI_BAR1_INDEX10"            ,           0x11F0000001128ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1860         {"PCI_BAR1_INDEX11"            ,           0x11F000000112Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1861         {"PCI_BAR1_INDEX12"            ,           0x11F0000001130ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1862         {"PCI_BAR1_INDEX13"            ,           0x11F0000001134ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1863         {"PCI_BAR1_INDEX14"            ,           0x11F0000001138ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1864         {"PCI_BAR1_INDEX15"            ,           0x11F000000113Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1865         {"PCI_BAR1_INDEX16"            ,           0x11F0000001140ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1866         {"PCI_BAR1_INDEX17"            ,           0x11F0000001144ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1867         {"PCI_BAR1_INDEX18"            ,           0x11F0000001148ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1868         {"PCI_BAR1_INDEX19"            ,           0x11F000000114Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1869         {"PCI_BAR1_INDEX20"            ,           0x11F0000001150ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1870         {"PCI_BAR1_INDEX21"            ,           0x11F0000001154ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1871         {"PCI_BAR1_INDEX22"            ,           0x11F0000001158ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1872         {"PCI_BAR1_INDEX23"            ,           0x11F000000115Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1873         {"PCI_BAR1_INDEX24"            ,           0x11F0000001160ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1874         {"PCI_BAR1_INDEX25"            ,           0x11F0000001164ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1875         {"PCI_BAR1_INDEX26"            ,           0x11F0000001168ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1876         {"PCI_BAR1_INDEX27"            ,           0x11F000000116Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1877         {"PCI_BAR1_INDEX28"            ,           0x11F0000001170ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1878         {"PCI_BAR1_INDEX29"            ,           0x11F0000001174ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1879         {"PCI_BAR1_INDEX30"            ,           0x11F0000001178ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1880         {"PCI_BAR1_INDEX31"            ,           0x11F000000117Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
1881         {"PCI_CFG00"                   ,           0x11F0000001800ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     354},
1882         {"PCI_CFG01"                   ,           0x11F0000001804ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     355},
1883         {"PCI_CFG02"                   ,           0x11F0000001808ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     356},
1884         {"PCI_CFG03"                   ,           0x11F000000180Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     357},
1885         {"PCI_CFG04"                   ,           0x11F0000001810ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     358},
1886         {"PCI_CFG05"                   ,           0x11F0000001814ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     359},
1887         {"PCI_CFG06"                   ,           0x11F0000001818ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     360},
1888         {"PCI_CFG07"                   ,           0x11F000000181Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     361},
1889         {"PCI_CFG08"                   ,           0x11F0000001820ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     362},
1890         {"PCI_CFG09"                   ,           0x11F0000001824ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     363},
1891         {"PCI_CFG10"                   ,           0x11F0000001828ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     364},
1892         {"PCI_CFG11"                   ,           0x11F000000182Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     365},
1893         {"PCI_CFG12"                   ,           0x11F0000001830ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     366},
1894         {"PCI_CFG13"                   ,           0x11F0000001834ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     367},
1895         {"PCI_CFG15"                   ,           0x11F000000183Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     368},
1896         {"PCI_CFG16"                   ,           0x11F0000001840ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     369},
1897         {"PCI_CFG17"                   ,           0x11F0000001844ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     370},
1898         {"PCI_CFG18"                   ,           0x11F0000001848ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     371},
1899         {"PCI_CFG19"                   ,           0x11F000000184Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     372},
1900         {"PCI_CFG20"                   ,           0x11F0000001850ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     373},
1901         {"PCI_CFG21"                   ,           0x11F0000001854ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     374},
1902         {"PCI_CFG22"                   ,           0x11F0000001858ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     375},
1903         {"PCI_CFG56"                   ,           0x11F00000018E0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     376},
1904         {"PCI_CFG57"                   ,           0x11F00000018E4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     377},
1905         {"PCI_CFG58"                   ,           0x11F00000018E8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     378},
1906         {"PCI_CFG59"                   ,           0x11F00000018ECull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     379},
1907         {"PCI_CFG60"                   ,           0x11F00000018F0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     380},
1908         {"PCI_CFG61"                   ,           0x11F00000018F4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     381},
1909         {"PCI_CFG62"                   ,           0x11F00000018F8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     382},
1910         {"PCI_CFG63"                   ,           0x11F00000018FCull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     383},
1911         {"PCI_CTL_STATUS_2"            ,           0x11F000000118Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     384},
1912         {"PCI_DBELL0"                  ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCI,   32,     385},
1913         {"PCI_DBELL1"                  ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCI,   32,     385},
1914         {"PCI_DBELL2"                  ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCI,   32,     385},
1915         {"PCI_DBELL3"                  ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCI,   32,     385},
1916         {"PCI_DMA_CNT0"                ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     386},
1917         {"PCI_DMA_CNT1"                ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCI,   32,     386},
1918         {"PCI_DMA_INT_LEV0"            ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     387},
1919         {"PCI_DMA_INT_LEV1"            ,                      0xACull,  CVMX_CSR_DB_TYPE_PCI,   32,     387},
1920         {"PCI_DMA_TIME0"               ,                      0xB0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     388},
1921         {"PCI_DMA_TIME1"               ,                      0xB4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     388},
1922         {"PCI_INSTR_COUNT0"            ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCI,   32,     389},
1923         {"PCI_INSTR_COUNT1"            ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     389},
1924         {"PCI_INSTR_COUNT2"            ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCI,   32,     389},
1925         {"PCI_INSTR_COUNT3"            ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     389},
1926         {"PCI_INT_ENB"                 ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCI,   64,     390},
1927         {"PCI_INT_ENB2"                ,           0x11F00000011A0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     391},
1928         {"PCI_INT_SUM"                 ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCI,   64,     392},
1929         {"PCI_INT_SUM2"                ,           0x11F0000001198ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     393},
1930         {"PCI_MSI_RCV"                 ,                      0xF0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     394},
1931         {"PCI_PKT_CREDITS0"            ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCI,   32,     395},
1932         {"PCI_PKT_CREDITS1"            ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCI,   32,     395},
1933         {"PCI_PKT_CREDITS2"            ,                      0x64ull,  CVMX_CSR_DB_TYPE_PCI,   32,     395},
1934         {"PCI_PKT_CREDITS3"            ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCI,   32,     395},
1935         {"PCI_PKTS_SENT0"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCI,   32,     396},
1936         {"PCI_PKTS_SENT1"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCI,   32,     396},
1937         {"PCI_PKTS_SENT2"              ,                      0x60ull,  CVMX_CSR_DB_TYPE_PCI,   32,     396},
1938         {"PCI_PKTS_SENT3"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCI,   32,     396},
1939         {"PCI_PKTS_SENT_INT_LEV0"      ,                      0x48ull,  CVMX_CSR_DB_TYPE_PCI,   32,     397},
1940         {"PCI_PKTS_SENT_INT_LEV1"      ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCI,   32,     397},
1941         {"PCI_PKTS_SENT_INT_LEV2"      ,                      0x68ull,  CVMX_CSR_DB_TYPE_PCI,   32,     397},
1942         {"PCI_PKTS_SENT_INT_LEV3"      ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCI,   32,     397},
1943         {"PCI_PKTS_SENT_TIME0"         ,                      0x4Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     398},
1944         {"PCI_PKTS_SENT_TIME1"         ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     398},
1945         {"PCI_PKTS_SENT_TIME2"         ,                      0x6Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     398},
1946         {"PCI_PKTS_SENT_TIME3"         ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     398},
1947         {"PCI_READ_CMD_6"              ,           0x11F0000001180ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     399},
1948         {"PCI_READ_CMD_C"              ,           0x11F0000001184ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     400},
1949         {"PCI_READ_CMD_E"              ,           0x11F0000001188ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     401},
1950         {"PCI_READ_TIMEOUT"            ,           0x11F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
1951         {"PCI_SCM_REG"                 ,           0x11F00000011A8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     403},
1952         {"PCI_TSR_REG"                 ,           0x11F00000011B0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     404},
1953         {"PCI_WIN_RD_ADDR"             ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCI,   64,     405},
1954         {"PCI_WIN_RD_DATA"             ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCI,   64,     406},
1955         {"PCI_WIN_WR_ADDR"             ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCI,   64,     407},
1956         {"PCI_WIN_WR_DATA"             ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCI,   64,     408},
1957         {"PCI_WIN_WR_MASK"             ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCI,   64,     409},
1958         {"PIP_BCK_PRS"                 ,           0x11800A0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
1959         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
1960         {"PIP_CRC_CTL0"                ,           0x11800A0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
1961         {"PIP_CRC_CTL1"                ,           0x11800A0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
1962         {"PIP_CRC_IV0"                 ,           0x11800A0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
1963         {"PIP_CRC_IV1"                 ,           0x11800A0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
1964         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
1965         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
1966         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
1967         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
1968         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
1969         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
1970         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
1971         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
1972         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
1973         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1974         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1975         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1976         {"PIP_PRT_CFG3"                ,           0x11800A0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1977         {"PIP_PRT_CFG4"                ,           0x11800A0000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1978         {"PIP_PRT_CFG5"                ,           0x11800A0000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1979         {"PIP_PRT_CFG6"                ,           0x11800A0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1980         {"PIP_PRT_CFG7"                ,           0x11800A0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1981         {"PIP_PRT_CFG8"                ,           0x11800A0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1982         {"PIP_PRT_CFG9"                ,           0x11800A0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1983         {"PIP_PRT_CFG10"               ,           0x11800A0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1984         {"PIP_PRT_CFG11"               ,           0x11800A0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1985         {"PIP_PRT_CFG12"               ,           0x11800A0000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1986         {"PIP_PRT_CFG13"               ,           0x11800A0000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1987         {"PIP_PRT_CFG14"               ,           0x11800A0000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1988         {"PIP_PRT_CFG15"               ,           0x11800A0000278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1989         {"PIP_PRT_CFG16"               ,           0x11800A0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1990         {"PIP_PRT_CFG17"               ,           0x11800A0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1991         {"PIP_PRT_CFG18"               ,           0x11800A0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1992         {"PIP_PRT_CFG19"               ,           0x11800A0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1993         {"PIP_PRT_CFG20"               ,           0x11800A00002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1994         {"PIP_PRT_CFG21"               ,           0x11800A00002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1995         {"PIP_PRT_CFG22"               ,           0x11800A00002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1996         {"PIP_PRT_CFG23"               ,           0x11800A00002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1997         {"PIP_PRT_CFG24"               ,           0x11800A00002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1998         {"PIP_PRT_CFG25"               ,           0x11800A00002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
1999         {"PIP_PRT_CFG26"               ,           0x11800A00002D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2000         {"PIP_PRT_CFG27"               ,           0x11800A00002D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2001         {"PIP_PRT_CFG28"               ,           0x11800A00002E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2002         {"PIP_PRT_CFG29"               ,           0x11800A00002E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2003         {"PIP_PRT_CFG30"               ,           0x11800A00002F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2004         {"PIP_PRT_CFG31"               ,           0x11800A00002F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2005         {"PIP_PRT_CFG32"               ,           0x11800A0000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2006         {"PIP_PRT_CFG33"               ,           0x11800A0000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2007         {"PIP_PRT_CFG34"               ,           0x11800A0000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2008         {"PIP_PRT_CFG35"               ,           0x11800A0000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
2009         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2010         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2011         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2012         {"PIP_PRT_TAG3"                ,           0x11800A0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2013         {"PIP_PRT_TAG4"                ,           0x11800A0000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2014         {"PIP_PRT_TAG5"                ,           0x11800A0000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2015         {"PIP_PRT_TAG6"                ,           0x11800A0000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2016         {"PIP_PRT_TAG7"                ,           0x11800A0000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2017         {"PIP_PRT_TAG8"                ,           0x11800A0000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2018         {"PIP_PRT_TAG9"                ,           0x11800A0000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2019         {"PIP_PRT_TAG10"               ,           0x11800A0000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2020         {"PIP_PRT_TAG11"               ,           0x11800A0000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2021         {"PIP_PRT_TAG12"               ,           0x11800A0000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2022         {"PIP_PRT_TAG13"               ,           0x11800A0000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2023         {"PIP_PRT_TAG14"               ,           0x11800A0000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2024         {"PIP_PRT_TAG15"               ,           0x11800A0000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2025         {"PIP_PRT_TAG16"               ,           0x11800A0000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2026         {"PIP_PRT_TAG17"               ,           0x11800A0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2027         {"PIP_PRT_TAG18"               ,           0x11800A0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2028         {"PIP_PRT_TAG19"               ,           0x11800A0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2029         {"PIP_PRT_TAG20"               ,           0x11800A00004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2030         {"PIP_PRT_TAG21"               ,           0x11800A00004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2031         {"PIP_PRT_TAG22"               ,           0x11800A00004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2032         {"PIP_PRT_TAG23"               ,           0x11800A00004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2033         {"PIP_PRT_TAG24"               ,           0x11800A00004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2034         {"PIP_PRT_TAG25"               ,           0x11800A00004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2035         {"PIP_PRT_TAG26"               ,           0x11800A00004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2036         {"PIP_PRT_TAG27"               ,           0x11800A00004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2037         {"PIP_PRT_TAG28"               ,           0x11800A00004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2038         {"PIP_PRT_TAG29"               ,           0x11800A00004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2039         {"PIP_PRT_TAG30"               ,           0x11800A00004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2040         {"PIP_PRT_TAG31"               ,           0x11800A00004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2041         {"PIP_PRT_TAG32"               ,           0x11800A0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2042         {"PIP_PRT_TAG33"               ,           0x11800A0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2043         {"PIP_PRT_TAG34"               ,           0x11800A0000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2044         {"PIP_PRT_TAG35"               ,           0x11800A0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
2045         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2046         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2047         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2048         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2049         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2050         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2051         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2052         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2053         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2054         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2055         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2056         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2057         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2058         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2059         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2060         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2061         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2062         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2063         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2064         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2065         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2066         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2067         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2068         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2069         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2070         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2071         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2072         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2073         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2074         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2075         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2076         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2077         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2078         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2079         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2080         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2081         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2082         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2083         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2084         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2085         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2086         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2087         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2088         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2089         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2090         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2091         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2092         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2093         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2094         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2095         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2096         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2097         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2098         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2099         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2100         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2101         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2102         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2103         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2104         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2105         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2106         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2107         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2108         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
2109         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
2110         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
2111         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
2112         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
2113         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
2114         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
2115         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
2116         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
2117         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
2118         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
2119         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
2120         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
2121         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
2122         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2123         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2124         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2125         {"PIP_STAT0_PRT3"              ,           0x11800A00008F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2126         {"PIP_STAT0_PRT4"              ,           0x11800A0000940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2127         {"PIP_STAT0_PRT5"              ,           0x11800A0000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2128         {"PIP_STAT0_PRT6"              ,           0x11800A00009E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2129         {"PIP_STAT0_PRT7"              ,           0x11800A0000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2130         {"PIP_STAT0_PRT8"              ,           0x11800A0000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2131         {"PIP_STAT0_PRT9"              ,           0x11800A0000AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2132         {"PIP_STAT0_PRT10"             ,           0x11800A0000B20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2133         {"PIP_STAT0_PRT11"             ,           0x11800A0000B70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2134         {"PIP_STAT0_PRT12"             ,           0x11800A0000BC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2135         {"PIP_STAT0_PRT13"             ,           0x11800A0000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2136         {"PIP_STAT0_PRT14"             ,           0x11800A0000C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2137         {"PIP_STAT0_PRT15"             ,           0x11800A0000CB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2138         {"PIP_STAT0_PRT16"             ,           0x11800A0000D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2139         {"PIP_STAT0_PRT17"             ,           0x11800A0000D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2140         {"PIP_STAT0_PRT18"             ,           0x11800A0000DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2141         {"PIP_STAT0_PRT19"             ,           0x11800A0000DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2142         {"PIP_STAT0_PRT20"             ,           0x11800A0000E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2143         {"PIP_STAT0_PRT21"             ,           0x11800A0000E90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2144         {"PIP_STAT0_PRT22"             ,           0x11800A0000EE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2145         {"PIP_STAT0_PRT23"             ,           0x11800A0000F30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2146         {"PIP_STAT0_PRT24"             ,           0x11800A0000F80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2147         {"PIP_STAT0_PRT25"             ,           0x11800A0000FD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2148         {"PIP_STAT0_PRT26"             ,           0x11800A0001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2149         {"PIP_STAT0_PRT27"             ,           0x11800A0001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2150         {"PIP_STAT0_PRT28"             ,           0x11800A00010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2151         {"PIP_STAT0_PRT29"             ,           0x11800A0001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2152         {"PIP_STAT0_PRT30"             ,           0x11800A0001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2153         {"PIP_STAT0_PRT31"             ,           0x11800A00011B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2154         {"PIP_STAT0_PRT32"             ,           0x11800A0001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2155         {"PIP_STAT0_PRT33"             ,           0x11800A0001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2156         {"PIP_STAT0_PRT34"             ,           0x11800A00012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2157         {"PIP_STAT0_PRT35"             ,           0x11800A00012F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
2158         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2159         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2160         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2161         {"PIP_STAT1_PRT3"              ,           0x11800A00008F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2162         {"PIP_STAT1_PRT4"              ,           0x11800A0000948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2163         {"PIP_STAT1_PRT5"              ,           0x11800A0000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2164         {"PIP_STAT1_PRT6"              ,           0x11800A00009E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2165         {"PIP_STAT1_PRT7"              ,           0x11800A0000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2166         {"PIP_STAT1_PRT8"              ,           0x11800A0000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2167         {"PIP_STAT1_PRT9"              ,           0x11800A0000AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2168         {"PIP_STAT1_PRT10"             ,           0x11800A0000B28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2169         {"PIP_STAT1_PRT11"             ,           0x11800A0000B78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2170         {"PIP_STAT1_PRT12"             ,           0x11800A0000BC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2171         {"PIP_STAT1_PRT13"             ,           0x11800A0000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2172         {"PIP_STAT1_PRT14"             ,           0x11800A0000C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2173         {"PIP_STAT1_PRT15"             ,           0x11800A0000CB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2174         {"PIP_STAT1_PRT16"             ,           0x11800A0000D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2175         {"PIP_STAT1_PRT17"             ,           0x11800A0000D58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2176         {"PIP_STAT1_PRT18"             ,           0x11800A0000DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2177         {"PIP_STAT1_PRT19"             ,           0x11800A0000DF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2178         {"PIP_STAT1_PRT20"             ,           0x11800A0000E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2179         {"PIP_STAT1_PRT21"             ,           0x11800A0000E98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2180         {"PIP_STAT1_PRT22"             ,           0x11800A0000EE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2181         {"PIP_STAT1_PRT23"             ,           0x11800A0000F38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2182         {"PIP_STAT1_PRT24"             ,           0x11800A0000F88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2183         {"PIP_STAT1_PRT25"             ,           0x11800A0000FD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2184         {"PIP_STAT1_PRT26"             ,           0x11800A0001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2185         {"PIP_STAT1_PRT27"             ,           0x11800A0001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2186         {"PIP_STAT1_PRT28"             ,           0x11800A00010C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2187         {"PIP_STAT1_PRT29"             ,           0x11800A0001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2188         {"PIP_STAT1_PRT30"             ,           0x11800A0001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2189         {"PIP_STAT1_PRT31"             ,           0x11800A00011B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2190         {"PIP_STAT1_PRT32"             ,           0x11800A0001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2191         {"PIP_STAT1_PRT33"             ,           0x11800A0001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2192         {"PIP_STAT1_PRT34"             ,           0x11800A00012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2193         {"PIP_STAT1_PRT35"             ,           0x11800A00012F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
2194         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2195         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2196         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2197         {"PIP_STAT2_PRT3"              ,           0x11800A0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2198         {"PIP_STAT2_PRT4"              ,           0x11800A0000950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2199         {"PIP_STAT2_PRT5"              ,           0x11800A00009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2200         {"PIP_STAT2_PRT6"              ,           0x11800A00009F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2201         {"PIP_STAT2_PRT7"              ,           0x11800A0000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2202         {"PIP_STAT2_PRT8"              ,           0x11800A0000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2203         {"PIP_STAT2_PRT9"              ,           0x11800A0000AE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2204         {"PIP_STAT2_PRT10"             ,           0x11800A0000B30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2205         {"PIP_STAT2_PRT11"             ,           0x11800A0000B80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2206         {"PIP_STAT2_PRT12"             ,           0x11800A0000BD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2207         {"PIP_STAT2_PRT13"             ,           0x11800A0000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2208         {"PIP_STAT2_PRT14"             ,           0x11800A0000C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2209         {"PIP_STAT2_PRT15"             ,           0x11800A0000CC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2210         {"PIP_STAT2_PRT16"             ,           0x11800A0000D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2211         {"PIP_STAT2_PRT17"             ,           0x11800A0000D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2212         {"PIP_STAT2_PRT18"             ,           0x11800A0000DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2213         {"PIP_STAT2_PRT19"             ,           0x11800A0000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2214         {"PIP_STAT2_PRT20"             ,           0x11800A0000E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2215         {"PIP_STAT2_PRT21"             ,           0x11800A0000EA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2216         {"PIP_STAT2_PRT22"             ,           0x11800A0000EF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2217         {"PIP_STAT2_PRT23"             ,           0x11800A0000F40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2218         {"PIP_STAT2_PRT24"             ,           0x11800A0000F90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2219         {"PIP_STAT2_PRT25"             ,           0x11800A0000FE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2220         {"PIP_STAT2_PRT26"             ,           0x11800A0001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2221         {"PIP_STAT2_PRT27"             ,           0x11800A0001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2222         {"PIP_STAT2_PRT28"             ,           0x11800A00010D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2223         {"PIP_STAT2_PRT29"             ,           0x11800A0001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2224         {"PIP_STAT2_PRT30"             ,           0x11800A0001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2225         {"PIP_STAT2_PRT31"             ,           0x11800A00011C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2226         {"PIP_STAT2_PRT32"             ,           0x11800A0001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2227         {"PIP_STAT2_PRT33"             ,           0x11800A0001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2228         {"PIP_STAT2_PRT34"             ,           0x11800A00012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2229         {"PIP_STAT2_PRT35"             ,           0x11800A0001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
2230         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2231         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2232         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2233         {"PIP_STAT3_PRT3"              ,           0x11800A0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2234         {"PIP_STAT3_PRT4"              ,           0x11800A0000958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2235         {"PIP_STAT3_PRT5"              ,           0x11800A00009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2236         {"PIP_STAT3_PRT6"              ,           0x11800A00009F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2237         {"PIP_STAT3_PRT7"              ,           0x11800A0000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2238         {"PIP_STAT3_PRT8"              ,           0x11800A0000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2239         {"PIP_STAT3_PRT9"              ,           0x11800A0000AE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2240         {"PIP_STAT3_PRT10"             ,           0x11800A0000B38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2241         {"PIP_STAT3_PRT11"             ,           0x11800A0000B88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2242         {"PIP_STAT3_PRT12"             ,           0x11800A0000BD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2243         {"PIP_STAT3_PRT13"             ,           0x11800A0000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2244         {"PIP_STAT3_PRT14"             ,           0x11800A0000C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2245         {"PIP_STAT3_PRT15"             ,           0x11800A0000CC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2246         {"PIP_STAT3_PRT16"             ,           0x11800A0000D18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2247         {"PIP_STAT3_PRT17"             ,           0x11800A0000D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2248         {"PIP_STAT3_PRT18"             ,           0x11800A0000DB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2249         {"PIP_STAT3_PRT19"             ,           0x11800A0000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2250         {"PIP_STAT3_PRT20"             ,           0x11800A0000E58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2251         {"PIP_STAT3_PRT21"             ,           0x11800A0000EA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2252         {"PIP_STAT3_PRT22"             ,           0x11800A0000EF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2253         {"PIP_STAT3_PRT23"             ,           0x11800A0000F48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2254         {"PIP_STAT3_PRT24"             ,           0x11800A0000F98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2255         {"PIP_STAT3_PRT25"             ,           0x11800A0000FE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2256         {"PIP_STAT3_PRT26"             ,           0x11800A0001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2257         {"PIP_STAT3_PRT27"             ,           0x11800A0001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2258         {"PIP_STAT3_PRT28"             ,           0x11800A00010D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2259         {"PIP_STAT3_PRT29"             ,           0x11800A0001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2260         {"PIP_STAT3_PRT30"             ,           0x11800A0001178ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2261         {"PIP_STAT3_PRT31"             ,           0x11800A00011C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2262         {"PIP_STAT3_PRT32"             ,           0x11800A0001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2263         {"PIP_STAT3_PRT33"             ,           0x11800A0001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2264         {"PIP_STAT3_PRT34"             ,           0x11800A00012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2265         {"PIP_STAT3_PRT35"             ,           0x11800A0001308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
2266         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2267         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2268         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2269         {"PIP_STAT4_PRT3"              ,           0x11800A0000910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2270         {"PIP_STAT4_PRT4"              ,           0x11800A0000960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2271         {"PIP_STAT4_PRT5"              ,           0x11800A00009B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2272         {"PIP_STAT4_PRT6"              ,           0x11800A0000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2273         {"PIP_STAT4_PRT7"              ,           0x11800A0000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2274         {"PIP_STAT4_PRT8"              ,           0x11800A0000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2275         {"PIP_STAT4_PRT9"              ,           0x11800A0000AF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2276         {"PIP_STAT4_PRT10"             ,           0x11800A0000B40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2277         {"PIP_STAT4_PRT11"             ,           0x11800A0000B90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2278         {"PIP_STAT4_PRT12"             ,           0x11800A0000BE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2279         {"PIP_STAT4_PRT13"             ,           0x11800A0000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2280         {"PIP_STAT4_PRT14"             ,           0x11800A0000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2281         {"PIP_STAT4_PRT15"             ,           0x11800A0000CD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2282         {"PIP_STAT4_PRT16"             ,           0x11800A0000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2283         {"PIP_STAT4_PRT17"             ,           0x11800A0000D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2284         {"PIP_STAT4_PRT18"             ,           0x11800A0000DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2285         {"PIP_STAT4_PRT19"             ,           0x11800A0000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2286         {"PIP_STAT4_PRT20"             ,           0x11800A0000E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2287         {"PIP_STAT4_PRT21"             ,           0x11800A0000EB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2288         {"PIP_STAT4_PRT22"             ,           0x11800A0000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2289         {"PIP_STAT4_PRT23"             ,           0x11800A0000F50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2290         {"PIP_STAT4_PRT24"             ,           0x11800A0000FA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2291         {"PIP_STAT4_PRT25"             ,           0x11800A0000FF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2292         {"PIP_STAT4_PRT26"             ,           0x11800A0001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2293         {"PIP_STAT4_PRT27"             ,           0x11800A0001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2294         {"PIP_STAT4_PRT28"             ,           0x11800A00010E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2295         {"PIP_STAT4_PRT29"             ,           0x11800A0001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2296         {"PIP_STAT4_PRT30"             ,           0x11800A0001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2297         {"PIP_STAT4_PRT31"             ,           0x11800A00011D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2298         {"PIP_STAT4_PRT32"             ,           0x11800A0001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2299         {"PIP_STAT4_PRT33"             ,           0x11800A0001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2300         {"PIP_STAT4_PRT34"             ,           0x11800A00012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2301         {"PIP_STAT4_PRT35"             ,           0x11800A0001310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
2302         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2303         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2304         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2305         {"PIP_STAT5_PRT3"              ,           0x11800A0000918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2306         {"PIP_STAT5_PRT4"              ,           0x11800A0000968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2307         {"PIP_STAT5_PRT5"              ,           0x11800A00009B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2308         {"PIP_STAT5_PRT6"              ,           0x11800A0000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2309         {"PIP_STAT5_PRT7"              ,           0x11800A0000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2310         {"PIP_STAT5_PRT8"              ,           0x11800A0000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2311         {"PIP_STAT5_PRT9"              ,           0x11800A0000AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2312         {"PIP_STAT5_PRT10"             ,           0x11800A0000B48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2313         {"PIP_STAT5_PRT11"             ,           0x11800A0000B98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2314         {"PIP_STAT5_PRT12"             ,           0x11800A0000BE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2315         {"PIP_STAT5_PRT13"             ,           0x11800A0000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2316         {"PIP_STAT5_PRT14"             ,           0x11800A0000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2317         {"PIP_STAT5_PRT15"             ,           0x11800A0000CD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2318         {"PIP_STAT5_PRT16"             ,           0x11800A0000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2319         {"PIP_STAT5_PRT17"             ,           0x11800A0000D78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2320         {"PIP_STAT5_PRT18"             ,           0x11800A0000DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2321         {"PIP_STAT5_PRT19"             ,           0x11800A0000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2322         {"PIP_STAT5_PRT20"             ,           0x11800A0000E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2323         {"PIP_STAT5_PRT21"             ,           0x11800A0000EB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2324         {"PIP_STAT5_PRT22"             ,           0x11800A0000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2325         {"PIP_STAT5_PRT23"             ,           0x11800A0000F58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2326         {"PIP_STAT5_PRT24"             ,           0x11800A0000FA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2327         {"PIP_STAT5_PRT25"             ,           0x11800A0000FF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2328         {"PIP_STAT5_PRT26"             ,           0x11800A0001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2329         {"PIP_STAT5_PRT27"             ,           0x11800A0001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2330         {"PIP_STAT5_PRT28"             ,           0x11800A00010E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2331         {"PIP_STAT5_PRT29"             ,           0x11800A0001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2332         {"PIP_STAT5_PRT30"             ,           0x11800A0001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2333         {"PIP_STAT5_PRT31"             ,           0x11800A00011D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2334         {"PIP_STAT5_PRT32"             ,           0x11800A0001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2335         {"PIP_STAT5_PRT33"             ,           0x11800A0001278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2336         {"PIP_STAT5_PRT34"             ,           0x11800A00012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2337         {"PIP_STAT5_PRT35"             ,           0x11800A0001318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
2338         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2339         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2340         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2341         {"PIP_STAT6_PRT3"              ,           0x11800A0000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2342         {"PIP_STAT6_PRT4"              ,           0x11800A0000970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2343         {"PIP_STAT6_PRT5"              ,           0x11800A00009C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2344         {"PIP_STAT6_PRT6"              ,           0x11800A0000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2345         {"PIP_STAT6_PRT7"              ,           0x11800A0000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2346         {"PIP_STAT6_PRT8"              ,           0x11800A0000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2347         {"PIP_STAT6_PRT9"              ,           0x11800A0000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2348         {"PIP_STAT6_PRT10"             ,           0x11800A0000B50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2349         {"PIP_STAT6_PRT11"             ,           0x11800A0000BA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2350         {"PIP_STAT6_PRT12"             ,           0x11800A0000BF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2351         {"PIP_STAT6_PRT13"             ,           0x11800A0000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2352         {"PIP_STAT6_PRT14"             ,           0x11800A0000C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2353         {"PIP_STAT6_PRT15"             ,           0x11800A0000CE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2354         {"PIP_STAT6_PRT16"             ,           0x11800A0000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2355         {"PIP_STAT6_PRT17"             ,           0x11800A0000D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2356         {"PIP_STAT6_PRT18"             ,           0x11800A0000DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2357         {"PIP_STAT6_PRT19"             ,           0x11800A0000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2358         {"PIP_STAT6_PRT20"             ,           0x11800A0000E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2359         {"PIP_STAT6_PRT21"             ,           0x11800A0000EC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2360         {"PIP_STAT6_PRT22"             ,           0x11800A0000F10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2361         {"PIP_STAT6_PRT23"             ,           0x11800A0000F60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2362         {"PIP_STAT6_PRT24"             ,           0x11800A0000FB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2363         {"PIP_STAT6_PRT25"             ,           0x11800A0001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2364         {"PIP_STAT6_PRT26"             ,           0x11800A0001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2365         {"PIP_STAT6_PRT27"             ,           0x11800A00010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2366         {"PIP_STAT6_PRT28"             ,           0x11800A00010F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2367         {"PIP_STAT6_PRT29"             ,           0x11800A0001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2368         {"PIP_STAT6_PRT30"             ,           0x11800A0001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2369         {"PIP_STAT6_PRT31"             ,           0x11800A00011E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2370         {"PIP_STAT6_PRT32"             ,           0x11800A0001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2371         {"PIP_STAT6_PRT33"             ,           0x11800A0001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2372         {"PIP_STAT6_PRT34"             ,           0x11800A00012D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2373         {"PIP_STAT6_PRT35"             ,           0x11800A0001320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
2374         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2375         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2376         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2377         {"PIP_STAT7_PRT3"              ,           0x11800A0000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2378         {"PIP_STAT7_PRT4"              ,           0x11800A0000978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2379         {"PIP_STAT7_PRT5"              ,           0x11800A00009C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2380         {"PIP_STAT7_PRT6"              ,           0x11800A0000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2381         {"PIP_STAT7_PRT7"              ,           0x11800A0000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2382         {"PIP_STAT7_PRT8"              ,           0x11800A0000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2383         {"PIP_STAT7_PRT9"              ,           0x11800A0000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2384         {"PIP_STAT7_PRT10"             ,           0x11800A0000B58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2385         {"PIP_STAT7_PRT11"             ,           0x11800A0000BA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2386         {"PIP_STAT7_PRT12"             ,           0x11800A0000BF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2387         {"PIP_STAT7_PRT13"             ,           0x11800A0000C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2388         {"PIP_STAT7_PRT14"             ,           0x11800A0000C98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2389         {"PIP_STAT7_PRT15"             ,           0x11800A0000CE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2390         {"PIP_STAT7_PRT16"             ,           0x11800A0000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2391         {"PIP_STAT7_PRT17"             ,           0x11800A0000D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2392         {"PIP_STAT7_PRT18"             ,           0x11800A0000DD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2393         {"PIP_STAT7_PRT19"             ,           0x11800A0000E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2394         {"PIP_STAT7_PRT20"             ,           0x11800A0000E78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2395         {"PIP_STAT7_PRT21"             ,           0x11800A0000EC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2396         {"PIP_STAT7_PRT22"             ,           0x11800A0000F18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2397         {"PIP_STAT7_PRT23"             ,           0x11800A0000F68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2398         {"PIP_STAT7_PRT24"             ,           0x11800A0000FB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2399         {"PIP_STAT7_PRT25"             ,           0x11800A0001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2400         {"PIP_STAT7_PRT26"             ,           0x11800A0001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2401         {"PIP_STAT7_PRT27"             ,           0x11800A00010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2402         {"PIP_STAT7_PRT28"             ,           0x11800A00010F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2403         {"PIP_STAT7_PRT29"             ,           0x11800A0001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2404         {"PIP_STAT7_PRT30"             ,           0x11800A0001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2405         {"PIP_STAT7_PRT31"             ,           0x11800A00011E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2406         {"PIP_STAT7_PRT32"             ,           0x11800A0001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2407         {"PIP_STAT7_PRT33"             ,           0x11800A0001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2408         {"PIP_STAT7_PRT34"             ,           0x11800A00012D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2409         {"PIP_STAT7_PRT35"             ,           0x11800A0001328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
2410         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2411         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2412         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2413         {"PIP_STAT8_PRT3"              ,           0x11800A0000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2414         {"PIP_STAT8_PRT4"              ,           0x11800A0000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2415         {"PIP_STAT8_PRT5"              ,           0x11800A00009D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2416         {"PIP_STAT8_PRT6"              ,           0x11800A0000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2417         {"PIP_STAT8_PRT7"              ,           0x11800A0000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2418         {"PIP_STAT8_PRT8"              ,           0x11800A0000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2419         {"PIP_STAT8_PRT9"              ,           0x11800A0000B10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2420         {"PIP_STAT8_PRT10"             ,           0x11800A0000B60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2421         {"PIP_STAT8_PRT11"             ,           0x11800A0000BB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2422         {"PIP_STAT8_PRT12"             ,           0x11800A0000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2423         {"PIP_STAT8_PRT13"             ,           0x11800A0000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2424         {"PIP_STAT8_PRT14"             ,           0x11800A0000CA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2425         {"PIP_STAT8_PRT15"             ,           0x11800A0000CF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2426         {"PIP_STAT8_PRT16"             ,           0x11800A0000D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2427         {"PIP_STAT8_PRT17"             ,           0x11800A0000D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2428         {"PIP_STAT8_PRT18"             ,           0x11800A0000DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2429         {"PIP_STAT8_PRT19"             ,           0x11800A0000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2430         {"PIP_STAT8_PRT20"             ,           0x11800A0000E80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2431         {"PIP_STAT8_PRT21"             ,           0x11800A0000ED0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2432         {"PIP_STAT8_PRT22"             ,           0x11800A0000F20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2433         {"PIP_STAT8_PRT23"             ,           0x11800A0000F70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2434         {"PIP_STAT8_PRT24"             ,           0x11800A0000FC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2435         {"PIP_STAT8_PRT25"             ,           0x11800A0001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2436         {"PIP_STAT8_PRT26"             ,           0x11800A0001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2437         {"PIP_STAT8_PRT27"             ,           0x11800A00010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2438         {"PIP_STAT8_PRT28"             ,           0x11800A0001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2439         {"PIP_STAT8_PRT29"             ,           0x11800A0001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2440         {"PIP_STAT8_PRT30"             ,           0x11800A00011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2441         {"PIP_STAT8_PRT31"             ,           0x11800A00011F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2442         {"PIP_STAT8_PRT32"             ,           0x11800A0001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2443         {"PIP_STAT8_PRT33"             ,           0x11800A0001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2444         {"PIP_STAT8_PRT34"             ,           0x11800A00012E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2445         {"PIP_STAT8_PRT35"             ,           0x11800A0001330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
2446         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2447         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2448         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2449         {"PIP_STAT9_PRT3"              ,           0x11800A0000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2450         {"PIP_STAT9_PRT4"              ,           0x11800A0000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2451         {"PIP_STAT9_PRT5"              ,           0x11800A00009D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2452         {"PIP_STAT9_PRT6"              ,           0x11800A0000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2453         {"PIP_STAT9_PRT7"              ,           0x11800A0000A78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2454         {"PIP_STAT9_PRT8"              ,           0x11800A0000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2455         {"PIP_STAT9_PRT9"              ,           0x11800A0000B18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2456         {"PIP_STAT9_PRT10"             ,           0x11800A0000B68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2457         {"PIP_STAT9_PRT11"             ,           0x11800A0000BB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2458         {"PIP_STAT9_PRT12"             ,           0x11800A0000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2459         {"PIP_STAT9_PRT13"             ,           0x11800A0000C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2460         {"PIP_STAT9_PRT14"             ,           0x11800A0000CA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2461         {"PIP_STAT9_PRT15"             ,           0x11800A0000CF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2462         {"PIP_STAT9_PRT16"             ,           0x11800A0000D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2463         {"PIP_STAT9_PRT17"             ,           0x11800A0000D98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2464         {"PIP_STAT9_PRT18"             ,           0x11800A0000DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2465         {"PIP_STAT9_PRT19"             ,           0x11800A0000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2466         {"PIP_STAT9_PRT20"             ,           0x11800A0000E88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2467         {"PIP_STAT9_PRT21"             ,           0x11800A0000ED8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2468         {"PIP_STAT9_PRT22"             ,           0x11800A0000F28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2469         {"PIP_STAT9_PRT23"             ,           0x11800A0000F78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2470         {"PIP_STAT9_PRT24"             ,           0x11800A0000FC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2471         {"PIP_STAT9_PRT25"             ,           0x11800A0001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2472         {"PIP_STAT9_PRT26"             ,           0x11800A0001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2473         {"PIP_STAT9_PRT27"             ,           0x11800A00010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2474         {"PIP_STAT9_PRT28"             ,           0x11800A0001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2475         {"PIP_STAT9_PRT29"             ,           0x11800A0001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2476         {"PIP_STAT9_PRT30"             ,           0x11800A00011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2477         {"PIP_STAT9_PRT31"             ,           0x11800A00011F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2478         {"PIP_STAT9_PRT32"             ,           0x11800A0001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2479         {"PIP_STAT9_PRT33"             ,           0x11800A0001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2480         {"PIP_STAT9_PRT34"             ,           0x11800A00012E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2481         {"PIP_STAT9_PRT35"             ,           0x11800A0001338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
2482         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
2483         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2484         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2485         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2486         {"PIP_STAT_INB_ERRS3"          ,           0x11800A0001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2487         {"PIP_STAT_INB_ERRS4"          ,           0x11800A0001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2488         {"PIP_STAT_INB_ERRS5"          ,           0x11800A0001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2489         {"PIP_STAT_INB_ERRS6"          ,           0x11800A0001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2490         {"PIP_STAT_INB_ERRS7"          ,           0x11800A0001AF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2491         {"PIP_STAT_INB_ERRS8"          ,           0x11800A0001B10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2492         {"PIP_STAT_INB_ERRS9"          ,           0x11800A0001B30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2493         {"PIP_STAT_INB_ERRS10"         ,           0x11800A0001B50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2494         {"PIP_STAT_INB_ERRS11"         ,           0x11800A0001B70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2495         {"PIP_STAT_INB_ERRS12"         ,           0x11800A0001B90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2496         {"PIP_STAT_INB_ERRS13"         ,           0x11800A0001BB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2497         {"PIP_STAT_INB_ERRS14"         ,           0x11800A0001BD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2498         {"PIP_STAT_INB_ERRS15"         ,           0x11800A0001BF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2499         {"PIP_STAT_INB_ERRS16"         ,           0x11800A0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2500         {"PIP_STAT_INB_ERRS17"         ,           0x11800A0001C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2501         {"PIP_STAT_INB_ERRS18"         ,           0x11800A0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2502         {"PIP_STAT_INB_ERRS19"         ,           0x11800A0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2503         {"PIP_STAT_INB_ERRS20"         ,           0x11800A0001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2504         {"PIP_STAT_INB_ERRS21"         ,           0x11800A0001CB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2505         {"PIP_STAT_INB_ERRS22"         ,           0x11800A0001CD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2506         {"PIP_STAT_INB_ERRS23"         ,           0x11800A0001CF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2507         {"PIP_STAT_INB_ERRS24"         ,           0x11800A0001D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2508         {"PIP_STAT_INB_ERRS25"         ,           0x11800A0001D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2509         {"PIP_STAT_INB_ERRS26"         ,           0x11800A0001D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2510         {"PIP_STAT_INB_ERRS27"         ,           0x11800A0001D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2511         {"PIP_STAT_INB_ERRS28"         ,           0x11800A0001D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2512         {"PIP_STAT_INB_ERRS29"         ,           0x11800A0001DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2513         {"PIP_STAT_INB_ERRS30"         ,           0x11800A0001DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2514         {"PIP_STAT_INB_ERRS31"         ,           0x11800A0001DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2515         {"PIP_STAT_INB_ERRS32"         ,           0x11800A0001E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2516         {"PIP_STAT_INB_ERRS33"         ,           0x11800A0001E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2517         {"PIP_STAT_INB_ERRS34"         ,           0x11800A0001E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2518         {"PIP_STAT_INB_ERRS35"         ,           0x11800A0001E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
2519         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2520         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2521         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2522         {"PIP_STAT_INB_OCTS3"          ,           0x11800A0001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2523         {"PIP_STAT_INB_OCTS4"          ,           0x11800A0001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2524         {"PIP_STAT_INB_OCTS5"          ,           0x11800A0001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2525         {"PIP_STAT_INB_OCTS6"          ,           0x11800A0001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2526         {"PIP_STAT_INB_OCTS7"          ,           0x11800A0001AE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2527         {"PIP_STAT_INB_OCTS8"          ,           0x11800A0001B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2528         {"PIP_STAT_INB_OCTS9"          ,           0x11800A0001B28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2529         {"PIP_STAT_INB_OCTS10"         ,           0x11800A0001B48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2530         {"PIP_STAT_INB_OCTS11"         ,           0x11800A0001B68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2531         {"PIP_STAT_INB_OCTS12"         ,           0x11800A0001B88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2532         {"PIP_STAT_INB_OCTS13"         ,           0x11800A0001BA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2533         {"PIP_STAT_INB_OCTS14"         ,           0x11800A0001BC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2534         {"PIP_STAT_INB_OCTS15"         ,           0x11800A0001BE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2535         {"PIP_STAT_INB_OCTS16"         ,           0x11800A0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2536         {"PIP_STAT_INB_OCTS17"         ,           0x11800A0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2537         {"PIP_STAT_INB_OCTS18"         ,           0x11800A0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2538         {"PIP_STAT_INB_OCTS19"         ,           0x11800A0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2539         {"PIP_STAT_INB_OCTS20"         ,           0x11800A0001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2540         {"PIP_STAT_INB_OCTS21"         ,           0x11800A0001CA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2541         {"PIP_STAT_INB_OCTS22"         ,           0x11800A0001CC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2542         {"PIP_STAT_INB_OCTS23"         ,           0x11800A0001CE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2543         {"PIP_STAT_INB_OCTS24"         ,           0x11800A0001D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2544         {"PIP_STAT_INB_OCTS25"         ,           0x11800A0001D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2545         {"PIP_STAT_INB_OCTS26"         ,           0x11800A0001D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2546         {"PIP_STAT_INB_OCTS27"         ,           0x11800A0001D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2547         {"PIP_STAT_INB_OCTS28"         ,           0x11800A0001D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2548         {"PIP_STAT_INB_OCTS29"         ,           0x11800A0001DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2549         {"PIP_STAT_INB_OCTS30"         ,           0x11800A0001DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2550         {"PIP_STAT_INB_OCTS31"         ,           0x11800A0001DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2551         {"PIP_STAT_INB_OCTS32"         ,           0x11800A0001E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2552         {"PIP_STAT_INB_OCTS33"         ,           0x11800A0001E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2553         {"PIP_STAT_INB_OCTS34"         ,           0x11800A0001E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2554         {"PIP_STAT_INB_OCTS35"         ,           0x11800A0001E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
2555         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2556         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2557         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2558         {"PIP_STAT_INB_PKTS3"          ,           0x11800A0001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2559         {"PIP_STAT_INB_PKTS4"          ,           0x11800A0001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2560         {"PIP_STAT_INB_PKTS5"          ,           0x11800A0001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2561         {"PIP_STAT_INB_PKTS6"          ,           0x11800A0001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2562         {"PIP_STAT_INB_PKTS7"          ,           0x11800A0001AE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2563         {"PIP_STAT_INB_PKTS8"          ,           0x11800A0001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2564         {"PIP_STAT_INB_PKTS9"          ,           0x11800A0001B20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2565         {"PIP_STAT_INB_PKTS10"         ,           0x11800A0001B40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2566         {"PIP_STAT_INB_PKTS11"         ,           0x11800A0001B60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2567         {"PIP_STAT_INB_PKTS12"         ,           0x11800A0001B80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2568         {"PIP_STAT_INB_PKTS13"         ,           0x11800A0001BA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2569         {"PIP_STAT_INB_PKTS14"         ,           0x11800A0001BC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2570         {"PIP_STAT_INB_PKTS15"         ,           0x11800A0001BE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2571         {"PIP_STAT_INB_PKTS16"         ,           0x11800A0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2572         {"PIP_STAT_INB_PKTS17"         ,           0x11800A0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2573         {"PIP_STAT_INB_PKTS18"         ,           0x11800A0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2574         {"PIP_STAT_INB_PKTS19"         ,           0x11800A0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2575         {"PIP_STAT_INB_PKTS20"         ,           0x11800A0001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2576         {"PIP_STAT_INB_PKTS21"         ,           0x11800A0001CA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2577         {"PIP_STAT_INB_PKTS22"         ,           0x11800A0001CC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2578         {"PIP_STAT_INB_PKTS23"         ,           0x11800A0001CE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2579         {"PIP_STAT_INB_PKTS24"         ,           0x11800A0001D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2580         {"PIP_STAT_INB_PKTS25"         ,           0x11800A0001D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2581         {"PIP_STAT_INB_PKTS26"         ,           0x11800A0001D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2582         {"PIP_STAT_INB_PKTS27"         ,           0x11800A0001D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2583         {"PIP_STAT_INB_PKTS28"         ,           0x11800A0001D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2584         {"PIP_STAT_INB_PKTS29"         ,           0x11800A0001DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2585         {"PIP_STAT_INB_PKTS30"         ,           0x11800A0001DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2586         {"PIP_STAT_INB_PKTS31"         ,           0x11800A0001DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2587         {"PIP_STAT_INB_PKTS32"         ,           0x11800A0001E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2588         {"PIP_STAT_INB_PKTS33"         ,           0x11800A0001E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2589         {"PIP_STAT_INB_PKTS34"         ,           0x11800A0001E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2590         {"PIP_STAT_INB_PKTS35"         ,           0x11800A0001E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
2591         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2592         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2593         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2594         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2595         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2596         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2597         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2598         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2599         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2600         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2601         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2602         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2603         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2604         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2605         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2606         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2607         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2608         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2609         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2610         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2611         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2612         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2613         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2614         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2615         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2616         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2617         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2618         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2619         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2620         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2621         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2622         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2623         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2624         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2625         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2626         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2627         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2628         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2629         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2630         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2631         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2632         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2633         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2634         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2635         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2636         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2637         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2638         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2639         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2640         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2641         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2642         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2643         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2644         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2645         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2646         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2647         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2648         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2649         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2650         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2651         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2652         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2653         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2654         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
2655         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
2656         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
2657         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
2658         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
2659         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
2660         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
2661         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     447},
2662         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
2663         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
2664         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
2665         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
2666         {"PKO_MEM_DEBUG14"             ,           0x1180050001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
2667         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
2668         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
2669         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
2670         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
2671         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
2672         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
2673         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
2674         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
2675         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
2676         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
2677         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
2678         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
2679         {"PKO_REG_CRC_CTL0"            ,           0x1180050000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
2680         {"PKO_REG_CRC_CTL1"            ,           0x1180050000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
2681         {"PKO_REG_CRC_ENABLE"          ,           0x1180050000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
2682         {"PKO_REG_CRC_IV0"             ,           0x1180050000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
2683         {"PKO_REG_CRC_IV1"             ,           0x1180050000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
2684         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     468},
2685         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
2686         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
2687         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
2688         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
2689         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     473},
2690         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     474},
2691         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
2692         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     476},
2693         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     477},
2694         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     478},
2695         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
2696         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
2697         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
2698         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
2699         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
2700         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
2701         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
2702         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
2703         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
2704         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
2705         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     482},
2706         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2707         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2708         {"POW_PP_GRP_MSK2"             ,           0x1670000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2709         {"POW_PP_GRP_MSK3"             ,           0x1670000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2710         {"POW_PP_GRP_MSK4"             ,           0x1670000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2711         {"POW_PP_GRP_MSK5"             ,           0x1670000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2712         {"POW_PP_GRP_MSK6"             ,           0x1670000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2713         {"POW_PP_GRP_MSK7"             ,           0x1670000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2714         {"POW_PP_GRP_MSK8"             ,           0x1670000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2715         {"POW_PP_GRP_MSK9"             ,           0x1670000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2716         {"POW_PP_GRP_MSK10"            ,           0x1670000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2717         {"POW_PP_GRP_MSK11"            ,           0x1670000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2718         {"POW_PP_GRP_MSK12"            ,           0x1670000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2719         {"POW_PP_GRP_MSK13"            ,           0x1670000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2720         {"POW_PP_GRP_MSK14"            ,           0x1670000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2721         {"POW_PP_GRP_MSK15"            ,           0x1670000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
2722         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
2723         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
2724         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
2725         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
2726         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
2727         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
2728         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
2729         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
2730         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
2731         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
2732         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
2733         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
2734         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
2735         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
2736         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
2737         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
2738         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
2739         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
2740         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
2741         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
2742         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
2743         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
2744         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
2745         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
2746         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
2747         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
2748         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
2749         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2750         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2751         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2752         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2753         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2754         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2755         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2756         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2757         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2758         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2759         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2760         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2761         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2762         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2763         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2764         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
2765         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     491},
2766         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2767         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2768         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2769         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2770         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2771         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2772         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2773         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2774         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2775         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2776         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2777         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2778         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2779         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2780         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2781         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
2782         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2783         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2784         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2785         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2786         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2787         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2788         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2789         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2790         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2791         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2792         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2793         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2794         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2795         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2796         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2797         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
2798         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     494},
2799         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     495},
2800         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     496},
2801         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     497},
2802         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     498},
2803         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     499},
2804         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     500},
2805         {"SPX0_BCKPRS_CNT"             ,           0x1180090000340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     501},
2806         {"SPX1_BCKPRS_CNT"             ,           0x1180098000340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     501},
2807         {"SPX0_BIST_STAT"              ,           0x11800900007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     502},
2808         {"SPX1_BIST_STAT"              ,           0x11800980007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     502},
2809         {"SPX0_CLK_CTL"                ,           0x1180090000348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     503},
2810         {"SPX1_CLK_CTL"                ,           0x1180098000348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     503},
2811         {"SPX0_CLK_STAT"               ,           0x1180090000350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     504},
2812         {"SPX1_CLK_STAT"               ,           0x1180098000350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     504},
2813         {"SPX0_DBG_DESKEW_CTL"         ,           0x1180090000368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     505},
2814         {"SPX1_DBG_DESKEW_CTL"         ,           0x1180098000368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     505},
2815         {"SPX0_DBG_DESKEW_STATE"       ,           0x1180090000370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     506},
2816         {"SPX1_DBG_DESKEW_STATE"       ,           0x1180098000370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     506},
2817         {"SPX0_DRV_CTL"                ,           0x1180090000358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     507},
2818         {"SPX1_DRV_CTL"                ,           0x1180098000358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     507},
2819         {"SPX0_ERR_CTL"                ,           0x1180090000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     508},
2820         {"SPX1_ERR_CTL"                ,           0x1180098000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     508},
2821         {"SPX0_INT_DAT"                ,           0x1180090000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     509},
2822         {"SPX1_INT_DAT"                ,           0x1180098000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     509},
2823         {"SPX0_INT_MSK"                ,           0x1180090000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     510},
2824         {"SPX1_INT_MSK"                ,           0x1180098000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     510},
2825         {"SPX0_INT_REG"                ,           0x1180090000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     511},
2826         {"SPX1_INT_REG"                ,           0x1180098000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     511},
2827         {"SPX0_INT_SYNC"               ,           0x1180090000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     512},
2828         {"SPX1_INT_SYNC"               ,           0x1180098000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     512},
2829         {"SPX0_TPA_ACC"                ,           0x1180090000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     513},
2830         {"SPX1_TPA_ACC"                ,           0x1180098000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     513},
2831         {"SPX0_TPA_MAX"                ,           0x1180090000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     514},
2832         {"SPX1_TPA_MAX"                ,           0x1180098000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     514},
2833         {"SPX0_TPA_SEL"                ,           0x1180090000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     515},
2834         {"SPX1_TPA_SEL"                ,           0x1180098000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     515},
2835         {"SPX0_TRN4_CTL"               ,           0x1180090000360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     516},
2836         {"SPX1_TRN4_CTL"               ,           0x1180098000360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     516},
2837         {"SPX0_PLL_BW_CTL"             ,           0x1180090000388ull,  CVMX_CSR_DB_TYPE_RSL,   64,     517},
2838         {"SPX0_PLL_SETTING"            ,           0x1180090000380ull,  CVMX_CSR_DB_TYPE_RSL,   64,     518},
2839         {"SRX0_COM_CTL"                ,           0x1180090000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     519},
2840         {"SRX1_COM_CTL"                ,           0x1180098000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     519},
2841         {"SRX0_IGN_RX_FULL"            ,           0x1180090000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     520},
2842         {"SRX1_IGN_RX_FULL"            ,           0x1180098000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     520},
2843         {"SRX0_SPI4_CAL000"            ,           0x1180090000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2844         {"SRX0_SPI4_CAL001"            ,           0x1180090000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2845         {"SRX0_SPI4_CAL002"            ,           0x1180090000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2846         {"SRX0_SPI4_CAL003"            ,           0x1180090000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2847         {"SRX0_SPI4_CAL004"            ,           0x1180090000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2848         {"SRX0_SPI4_CAL005"            ,           0x1180090000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2849         {"SRX0_SPI4_CAL006"            ,           0x1180090000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2850         {"SRX0_SPI4_CAL007"            ,           0x1180090000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2851         {"SRX0_SPI4_CAL008"            ,           0x1180090000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2852         {"SRX0_SPI4_CAL009"            ,           0x1180090000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2853         {"SRX0_SPI4_CAL010"            ,           0x1180090000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2854         {"SRX0_SPI4_CAL011"            ,           0x1180090000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2855         {"SRX0_SPI4_CAL012"            ,           0x1180090000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2856         {"SRX0_SPI4_CAL013"            ,           0x1180090000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2857         {"SRX0_SPI4_CAL014"            ,           0x1180090000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2858         {"SRX0_SPI4_CAL015"            ,           0x1180090000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2859         {"SRX0_SPI4_CAL016"            ,           0x1180090000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2860         {"SRX0_SPI4_CAL017"            ,           0x1180090000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2861         {"SRX0_SPI4_CAL018"            ,           0x1180090000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2862         {"SRX0_SPI4_CAL019"            ,           0x1180090000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2863         {"SRX0_SPI4_CAL020"            ,           0x11800900000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2864         {"SRX0_SPI4_CAL021"            ,           0x11800900000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2865         {"SRX0_SPI4_CAL022"            ,           0x11800900000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2866         {"SRX0_SPI4_CAL023"            ,           0x11800900000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2867         {"SRX0_SPI4_CAL024"            ,           0x11800900000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2868         {"SRX0_SPI4_CAL025"            ,           0x11800900000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2869         {"SRX0_SPI4_CAL026"            ,           0x11800900000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2870         {"SRX0_SPI4_CAL027"            ,           0x11800900000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2871         {"SRX0_SPI4_CAL028"            ,           0x11800900000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2872         {"SRX0_SPI4_CAL029"            ,           0x11800900000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2873         {"SRX0_SPI4_CAL030"            ,           0x11800900000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2874         {"SRX0_SPI4_CAL031"            ,           0x11800900000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2875         {"SRX1_SPI4_CAL000"            ,           0x1180098000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2876         {"SRX1_SPI4_CAL001"            ,           0x1180098000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2877         {"SRX1_SPI4_CAL002"            ,           0x1180098000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2878         {"SRX1_SPI4_CAL003"            ,           0x1180098000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2879         {"SRX1_SPI4_CAL004"            ,           0x1180098000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2880         {"SRX1_SPI4_CAL005"            ,           0x1180098000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2881         {"SRX1_SPI4_CAL006"            ,           0x1180098000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2882         {"SRX1_SPI4_CAL007"            ,           0x1180098000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2883         {"SRX1_SPI4_CAL008"            ,           0x1180098000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2884         {"SRX1_SPI4_CAL009"            ,           0x1180098000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2885         {"SRX1_SPI4_CAL010"            ,           0x1180098000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2886         {"SRX1_SPI4_CAL011"            ,           0x1180098000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2887         {"SRX1_SPI4_CAL012"            ,           0x1180098000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2888         {"SRX1_SPI4_CAL013"            ,           0x1180098000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2889         {"SRX1_SPI4_CAL014"            ,           0x1180098000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2890         {"SRX1_SPI4_CAL015"            ,           0x1180098000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2891         {"SRX1_SPI4_CAL016"            ,           0x1180098000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2892         {"SRX1_SPI4_CAL017"            ,           0x1180098000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2893         {"SRX1_SPI4_CAL018"            ,           0x1180098000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2894         {"SRX1_SPI4_CAL019"            ,           0x1180098000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2895         {"SRX1_SPI4_CAL020"            ,           0x11800980000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2896         {"SRX1_SPI4_CAL021"            ,           0x11800980000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2897         {"SRX1_SPI4_CAL022"            ,           0x11800980000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2898         {"SRX1_SPI4_CAL023"            ,           0x11800980000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2899         {"SRX1_SPI4_CAL024"            ,           0x11800980000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2900         {"SRX1_SPI4_CAL025"            ,           0x11800980000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2901         {"SRX1_SPI4_CAL026"            ,           0x11800980000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2902         {"SRX1_SPI4_CAL027"            ,           0x11800980000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2903         {"SRX1_SPI4_CAL028"            ,           0x11800980000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2904         {"SRX1_SPI4_CAL029"            ,           0x11800980000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2905         {"SRX1_SPI4_CAL030"            ,           0x11800980000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2906         {"SRX1_SPI4_CAL031"            ,           0x11800980000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
2907         {"SRX0_SPI4_STAT"              ,           0x1180090000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     522},
2908         {"SRX1_SPI4_STAT"              ,           0x1180098000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     522},
2909         {"STX0_ARB_CTL"                ,           0x1180090000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     523},
2910         {"STX1_ARB_CTL"                ,           0x1180098000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     523},
2911         {"STX0_BCKPRS_CNT"             ,           0x1180090000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     524},
2912         {"STX1_BCKPRS_CNT"             ,           0x1180098000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     524},
2913         {"STX0_COM_CTL"                ,           0x1180090000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     525},
2914         {"STX1_COM_CTL"                ,           0x1180098000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     525},
2915         {"STX0_DIP_CNT"                ,           0x1180090000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     526},
2916         {"STX1_DIP_CNT"                ,           0x1180098000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     526},
2917         {"STX0_IGN_CAL"                ,           0x1180090000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     527},
2918         {"STX1_IGN_CAL"                ,           0x1180098000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     527},
2919         {"STX0_INT_MSK"                ,           0x11800900006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     528},
2920         {"STX1_INT_MSK"                ,           0x11800980006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     528},
2921         {"STX0_INT_REG"                ,           0x1180090000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     529},
2922         {"STX1_INT_REG"                ,           0x1180098000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     529},
2923         {"STX0_INT_SYNC"               ,           0x11800900006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     530},
2924         {"STX1_INT_SYNC"               ,           0x11800980006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     530},
2925         {"STX0_MIN_BST"                ,           0x1180090000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     531},
2926         {"STX1_MIN_BST"                ,           0x1180098000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     531},
2927         {"STX0_SPI4_CAL000"            ,           0x1180090000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2928         {"STX0_SPI4_CAL001"            ,           0x1180090000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2929         {"STX0_SPI4_CAL002"            ,           0x1180090000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2930         {"STX0_SPI4_CAL003"            ,           0x1180090000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2931         {"STX0_SPI4_CAL004"            ,           0x1180090000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2932         {"STX0_SPI4_CAL005"            ,           0x1180090000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2933         {"STX0_SPI4_CAL006"            ,           0x1180090000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2934         {"STX0_SPI4_CAL007"            ,           0x1180090000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2935         {"STX0_SPI4_CAL008"            ,           0x1180090000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2936         {"STX0_SPI4_CAL009"            ,           0x1180090000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2937         {"STX0_SPI4_CAL010"            ,           0x1180090000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2938         {"STX0_SPI4_CAL011"            ,           0x1180090000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2939         {"STX0_SPI4_CAL012"            ,           0x1180090000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2940         {"STX0_SPI4_CAL013"            ,           0x1180090000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2941         {"STX0_SPI4_CAL014"            ,           0x1180090000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2942         {"STX0_SPI4_CAL015"            ,           0x1180090000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2943         {"STX0_SPI4_CAL016"            ,           0x1180090000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2944         {"STX0_SPI4_CAL017"            ,           0x1180090000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2945         {"STX0_SPI4_CAL018"            ,           0x1180090000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2946         {"STX0_SPI4_CAL019"            ,           0x1180090000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2947         {"STX0_SPI4_CAL020"            ,           0x11800900004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2948         {"STX0_SPI4_CAL021"            ,           0x11800900004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2949         {"STX0_SPI4_CAL022"            ,           0x11800900004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2950         {"STX0_SPI4_CAL023"            ,           0x11800900004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2951         {"STX0_SPI4_CAL024"            ,           0x11800900004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2952         {"STX0_SPI4_CAL025"            ,           0x11800900004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2953         {"STX0_SPI4_CAL026"            ,           0x11800900004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2954         {"STX0_SPI4_CAL027"            ,           0x11800900004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2955         {"STX0_SPI4_CAL028"            ,           0x11800900004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2956         {"STX0_SPI4_CAL029"            ,           0x11800900004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2957         {"STX0_SPI4_CAL030"            ,           0x11800900004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2958         {"STX0_SPI4_CAL031"            ,           0x11800900004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2959         {"STX1_SPI4_CAL000"            ,           0x1180098000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2960         {"STX1_SPI4_CAL001"            ,           0x1180098000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2961         {"STX1_SPI4_CAL002"            ,           0x1180098000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2962         {"STX1_SPI4_CAL003"            ,           0x1180098000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2963         {"STX1_SPI4_CAL004"            ,           0x1180098000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2964         {"STX1_SPI4_CAL005"            ,           0x1180098000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2965         {"STX1_SPI4_CAL006"            ,           0x1180098000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2966         {"STX1_SPI4_CAL007"            ,           0x1180098000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2967         {"STX1_SPI4_CAL008"            ,           0x1180098000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2968         {"STX1_SPI4_CAL009"            ,           0x1180098000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2969         {"STX1_SPI4_CAL010"            ,           0x1180098000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2970         {"STX1_SPI4_CAL011"            ,           0x1180098000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2971         {"STX1_SPI4_CAL012"            ,           0x1180098000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2972         {"STX1_SPI4_CAL013"            ,           0x1180098000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2973         {"STX1_SPI4_CAL014"            ,           0x1180098000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2974         {"STX1_SPI4_CAL015"            ,           0x1180098000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2975         {"STX1_SPI4_CAL016"            ,           0x1180098000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2976         {"STX1_SPI4_CAL017"            ,           0x1180098000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2977         {"STX1_SPI4_CAL018"            ,           0x1180098000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2978         {"STX1_SPI4_CAL019"            ,           0x1180098000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2979         {"STX1_SPI4_CAL020"            ,           0x11800980004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2980         {"STX1_SPI4_CAL021"            ,           0x11800980004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2981         {"STX1_SPI4_CAL022"            ,           0x11800980004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2982         {"STX1_SPI4_CAL023"            ,           0x11800980004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2983         {"STX1_SPI4_CAL024"            ,           0x11800980004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2984         {"STX1_SPI4_CAL025"            ,           0x11800980004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2985         {"STX1_SPI4_CAL026"            ,           0x11800980004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2986         {"STX1_SPI4_CAL027"            ,           0x11800980004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2987         {"STX1_SPI4_CAL028"            ,           0x11800980004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2988         {"STX1_SPI4_CAL029"            ,           0x11800980004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2989         {"STX1_SPI4_CAL030"            ,           0x11800980004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2990         {"STX1_SPI4_CAL031"            ,           0x11800980004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
2991         {"STX0_SPI4_DAT"               ,           0x1180090000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     533},
2992         {"STX1_SPI4_DAT"               ,           0x1180098000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     533},
2993         {"STX0_SPI4_STAT"              ,           0x1180090000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     534},
2994         {"STX1_SPI4_STAT"              ,           0x1180098000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     534},
2995         {"STX0_STAT_BYTES_HI"          ,           0x1180090000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     535},
2996         {"STX1_STAT_BYTES_HI"          ,           0x1180098000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     535},
2997         {"STX0_STAT_BYTES_LO"          ,           0x1180090000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     536},
2998         {"STX1_STAT_BYTES_LO"          ,           0x1180098000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     536},
2999         {"STX0_STAT_CTL"               ,           0x1180090000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     537},
3000         {"STX1_STAT_CTL"               ,           0x1180098000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     537},
3001         {"STX0_STAT_PKT_XMT"           ,           0x1180090000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     538},
3002         {"STX1_STAT_PKT_XMT"           ,           0x1180098000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     538},
3003         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     539},
3004         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     540},
3005         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     541},
3006         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     542},
3007         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     543},
3008         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     544},
3009         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
3010         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     546},
3011         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     547},
3012         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     548},
3013         {"TRA_BIST_STATUS"             ,           0x11800A8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     549},
3014         {"TRA_CTL"                     ,           0x11800A8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     550},
3015         {"TRA_CYCLES_SINCE"            ,           0x11800A8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     551},
3016         {"TRA_FILT_ADR_ADR"            ,           0x11800A8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     552},
3017         {"TRA_FILT_ADR_MSK"            ,           0x11800A8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     553},
3018         {"TRA_FILT_CMD"                ,           0x11800A8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     554},
3019         {"TRA_FILT_DID"                ,           0x11800A8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
3020         {"TRA_FILT_SID"                ,           0x11800A8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     556},
3021         {"TRA_INT_STATUS"              ,           0x11800A8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     557},
3022         {"TRA_READ_DAT"                ,           0x11800A8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
3023         {"TRA_TRIG0_ADR_ADR"           ,           0x11800A8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     559},
3024         {"TRA_TRIG0_ADR_MSK"           ,           0x11800A80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     560},
3025         {"TRA_TRIG0_CMD"               ,           0x11800A8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     561},
3026         {"TRA_TRIG0_DID"               ,           0x11800A8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     562},
3027         {"TRA_TRIG0_SID"               ,           0x11800A8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     563},
3028         {"TRA_TRIG1_ADR_ADR"           ,           0x11800A80000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     564},
3029         {"TRA_TRIG1_ADR_MSK"           ,           0x11800A80000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     565},
3030         {"TRA_TRIG1_CMD"               ,           0x11800A80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     566},
3031         {"TRA_TRIG1_DID"               ,           0x11800A80000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     567},
3032         {"TRA_TRIG1_SID"               ,           0x11800A80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
3033         {"ZIP_CMD_BIST_RESULT"         ,           0x1180038000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     569},
3034         {"ZIP_CMD_BUF"                 ,           0x1180038000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     570},
3035         {"ZIP_CMD_CTL"                 ,           0x1180038000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     571},
3036         {"ZIP_CONSTANTS"               ,           0x11800380000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     572},
3037         {"ZIP_DEBUG0"                  ,           0x1180038000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     573},
3038         {"ZIP_ERROR"                   ,           0x1180038000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     574},
3039         {"ZIP_INT_MASK"                ,           0x1180038000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     575},
3040         {NULL,0,0,0,0}
3041 };
3042 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xxp2[] = {
3043         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
3044         {"OVRFLW"                      ,        0,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
3045         {"TXPOP"                       ,        4,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
3046         {"TXPSH"                       ,        8,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
3047         {"RESERVED_12_63"              ,        12,     52,     0,      "RAZ",  1,      1,      0,      0},
3048         {"OVRFLW"                      ,        0,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
3049         {"TXPOP"                       ,        4,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
3050         {"TXPSH"                       ,        8,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
3051         {"RESERVED_12_63"              ,        12,     52,     1,      "RAZ",  1,      1,      0,      0},
3052         {"INT_LOOP"                    ,        0,      4,      2,      "R/W",  0,      0,      0ull,   0ull},
3053         {"EXT_LOOP"                    ,        4,      4,      2,      "R/W",  0,      0,      0ull,   0ull},
3054         {"RESERVED_8_63"               ,        8,      56,     2,      "RAZ",  1,      1,      0,      0},
3055         {"BYPASS"                      ,        0,      1,      3,      "R/W",  0,      1,      0ull,   0},
3056         {"RESERVED_1_63"               ,        1,      63,     3,      "RAZ",  1,      1,      0,      0},
3057         {"SETTING"                     ,        0,      5,      4,      "R/W",  0,      1,      0ull,   0},
3058         {"RESERVED_5_63"               ,        5,      59,     4,      "RAZ",  1,      1,      0,      0},
3059         {"NCTL"                        ,        0,      4,      5,      "RO",   0,      1,      0ull,   0},
3060         {"PCTL"                        ,        4,      4,      5,      "RO",   0,      1,      0ull,   0},
3061         {"RESERVED_8_63"               ,        8,      56,     5,      "RAZ",  1,      1,      0,      0},
3062         {"NCTL"                        ,        0,      4,      6,      "R/W",  0,      1,      0ull,   0},
3063         {"PCTL"                        ,        4,      4,      6,      "R/W",  0,      1,      0ull,   0},
3064         {"RESERVED_8_63"               ,        8,      56,     6,      "RAZ",  1,      1,      0,      0},
3065         {"MODE"                        ,        0,      1,      7,      "R/W",  0,      1,      0ull,   0},
3066         {"RESERVED_1_63"               ,        1,      63,     7,      "RAZ",  1,      1,      0,      0},
3067         {"NCTL"                        ,        0,      5,      8,      "R/W",  0,      1,      0ull,   0},
3068         {"RESERVED_5_63"               ,        5,      59,     8,      "RAZ",  1,      1,      0,      0},
3069         {"NCTL"                        ,        0,      5,      9,      "R/W",  0,      1,      0ull,   0},
3070         {"RESERVED_5_63"               ,        5,      59,     9,      "RAZ",  1,      1,      0,      0},
3071         {"PCTL"                        ,        0,      5,      10,     "R/W",  0,      1,      0ull,   0},
3072         {"RESERVED_5_63"               ,        5,      59,     10,     "RAZ",  1,      1,      0,      0},
3073         {"PCTL"                        ,        0,      5,      11,     "R/W",  0,      1,      0ull,   0},
3074         {"RESERVED_5_63"               ,        5,      59,     11,     "RAZ",  1,      1,      0,      0},
3075         {"SETTING"                     ,        0,      5,      12,     "RO",   1,      1,      0,      0},
3076         {"RESERVED_5_63"               ,        5,      59,     12,     "RAZ",  1,      1,      0,      0},
3077         {"SETTING"                     ,        0,      5,      13,     "R/W",  0,      0,      24ull,  24ull},
3078         {"RESERVED_5_63"               ,        5,      59,     13,     "RAZ",  1,      1,      0,      0},
3079         {"PRT_EN"                      ,        0,      4,      14,     "R/W",  0,      0,      0ull,   1ull},
3080         {"RESERVED_4_63"               ,        4,      60,     14,     "RAZ",  1,      1,      0,      0},
3081         {"ENABLE"                      ,        0,      1,      15,     "RO",   1,      1,      0,      0},
3082         {"STATUS"                      ,        1,      1,      15,     "RO",   1,      1,      0,      0},
3083         {"RESERVED_2_63"               ,        2,      62,     15,     "RAZ",  1,      1,      0,      0},
3084         {"MSK"                         ,        0,      64,     16,     "R/W",  0,      1,      0ull,   0},
3085         {"POWEROK"                     ,        0,      1,      17,     "R/W",  0,      1,      1ull,   0},
3086         {"RESERVED_1_63"               ,        1,      63,     17,     "RAZ",  1,      1,      0,      0},
3087         {"SIG"                         ,        0,      32,     18,     "R/W",  0,      1,      0ull,   0},
3088         {"RESERVED_32_63"              ,        32,     32,     18,     "RAZ",  1,      1,      0,      0},
3089         {"SETTING"                     ,        0,      5,      19,     "R/W",  0,      0,      24ull,  24ull},
3090         {"RESERVED_5_63"               ,        5,      59,     19,     "RAZ",  1,      1,      0,      0},
3091         {"NCTL"                        ,        0,      4,      20,     "R/W",  0,      0,      8ull,   8ull},
3092         {"PCTL"                        ,        4,      4,      20,     "R/W",  0,      0,      8ull,   8ull},
3093         {"RESERVED_8_63"               ,        8,      56,     20,     "RAZ",  1,      1,      0,      0},
3094         {"MARK"                        ,        0,      4,      21,     "R/W",  0,      0,      0ull,   0ull},
3095         {"RESERVED_4_63"               ,        4,      60,     21,     "RAZ",  1,      1,      0,      0},
3096         {"PRT_EN"                      ,        0,      4,      22,     "R/W",  0,      0,      0ull,   1ull},
3097         {"RESERVED_4_63"               ,        4,      60,     22,     "RAZ",  1,      1,      0,      0},
3098         {"NCTL"                        ,        0,      4,      23,     "R/W",  0,      1,      15ull,  0},
3099         {"PCTL"                        ,        4,      4,      23,     "R/W",  0,      1,      15ull,  0},
3100         {"RESERVED_8_63"               ,        8,      56,     23,     "RAZ",  1,      1,      0,      0},
3101         {"EN"                          ,        0,      1,      24,     "R/W",  0,      1,      1ull,   0},
3102         {"RESERVED_1_63"               ,        1,      63,     24,     "RAZ",  1,      1,      0,      0},
3103         {"BIST"                        ,        0,      4,      25,     "RO",   0,      0,      0ull,   0ull},
3104         {"RESERVED_4_63"               ,        4,      60,     25,     "RAZ",  1,      1,      0,      0},
3105         {"DINT"                        ,        0,      16,     26,     "WO",   0,      0,      0ull,   0ull},
3106         {"RESERVED_16_63"              ,        16,     48,     26,     "RAZ",  1,      1,      0,      0},
3107         {"FUSE"                        ,        0,      16,     27,     "RO",   1,      1,      0,      0},
3108         {"RESERVED_16_63"              ,        16,     48,     27,     "RAZ",  1,      1,      0,      0},
3109         {"GSTOP"                       ,        0,      1,      28,     "R/W",  0,      0,      0ull,   0ull},
3110         {"RESERVED_1_63"               ,        1,      63,     28,     "RAZ",  1,      1,      0,      0},
3111         {"WORKQ"                       ,        0,      16,     29,     "R/W",  0,      0,      0ull,   0ull},
3112         {"GPIO"                        ,        16,     16,     29,     "R/W",  0,      0,      0ull,   0ull},
3113         {"MBOX"                        ,        32,     2,      29,     "R/W",  0,      0,      0ull,   0ull},
3114         {"UART"                        ,        34,     2,      29,     "R/W",  0,      0,      0ull,   0ull},
3115         {"PCI_INT"                     ,        36,     4,      29,     "R/W",  0,      0,      0ull,   0ull},
3116         {"PCI_MSI"                     ,        40,     4,      29,     "R/W",  0,      0,      0ull,   0ull},
3117         {"RESERVED_44_44"              ,        44,     1,      29,     "RAZ",  1,      1,      0,      0},
3118         {"TWSI"                        ,        45,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
3119         {"RML"                         ,        46,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
3120         {"TRACE"                       ,        47,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
3121         {"GMX_DRP"                     ,        48,     2,      29,     "R/W",  0,      0,      0ull,   0ull},
3122         {"IPD_DRP"                     ,        50,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
3123         {"KEY_ZERO"                    ,        51,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
3124         {"TIMER"                       ,        52,     4,      29,     "R/W",  0,      0,      0ull,   0ull},
3125         {"RESERVED_56_63"              ,        56,     8,      29,     "RAZ",  1,      1,      0,      0},
3126         {"WDOG"                        ,        0,      16,     30,     "R/W",  0,      0,      0ull,   0ull},
3127         {"RESERVED_16_63"              ,        16,     48,     30,     "RAZ",  1,      1,      0,      0},
3128         {"WORKQ"                       ,        0,      16,     31,     "RO",   0,      0,      0ull,   0ull},
3129         {"GPIO"                        ,        16,     16,     31,     "RO",   0,      0,      0ull,   0ull},
3130         {"MBOX"                        ,        32,     2,      31,     "RO",   0,      0,      0ull,   0ull},
3131         {"UART"                        ,        34,     2,      31,     "RO",   0,      0,      0ull,   0ull},
3132         {"PCI_INT"                     ,        36,     4,      31,     "RO",   0,      0,      0ull,   0ull},
3133         {"PCI_MSI"                     ,        40,     4,      31,     "RO",   0,      0,      0ull,   0ull},
3134         {"WDOG_SUM"                    ,        44,     1,      31,     "RO",   0,      0,      0ull,   0ull},
3135         {"TWSI"                        ,        45,     1,      31,     "RO",   0,      0,      0ull,   0ull},
3136         {"RML"                         ,        46,     1,      31,     "RO",   0,      0,      0ull,   0ull},
3137         {"TRACE"                       ,        47,     1,      31,     "RO",   0,      0,      0ull,   0ull},
3138         {"GMX_DRP"                     ,        48,     2,      31,     "R/W1C",        0,      0,      0ull,   0ull},
3139         {"IPD_DRP"                     ,        50,     1,      31,     "R/W1C",        0,      0,      0ull,   0ull},
3140         {"KEY_ZERO"                    ,        51,     1,      31,     "R/W1C",        0,      0,      0ull,   0ull},
3141         {"TIMER"                       ,        52,     4,      31,     "R/W1C",        0,      0,      0ull,   0ull},
3142         {"RESERVED_56_63"              ,        56,     8,      31,     "RAZ",  1,      1,      0,      0},
3143         {"WDOG"                        ,        0,      16,     32,     "RO",   0,      0,      0ull,   0ull},
3144         {"RESERVED_16_63"              ,        16,     48,     32,     "RAZ",  1,      1,      0,      0},
3145         {"BITS"                        ,        0,      32,     33,     "R/W1C",        0,      0,      0ull,   0ull},
3146         {"RESERVED_32_63"              ,        32,     32,     33,     "RAZ",  1,      1,      0,      0},
3147         {"BITS"                        ,        0,      32,     34,     "R/W1", 0,      0,      0ull,   0ull},
3148         {"RESERVED_32_63"              ,        32,     32,     34,     "RAZ",  1,      1,      0,      0},
3149         {"NMI"                         ,        0,      16,     35,     "WO",   0,      0,      0ull,   0ull},
3150         {"RESERVED_16_63"              ,        16,     48,     35,     "RAZ",  1,      1,      0,      0},
3151         {"INTR"                        ,        0,      2,      36,     "R/W",  0,      0,      0ull,   0ull},
3152         {"RESERVED_2_63"               ,        2,      62,     36,     "RAZ",  1,      1,      0,      0},
3153         {"PPDBG"                       ,        0,      16,     37,     "RO",   0,      0,      0ull,   0ull},
3154         {"RESERVED_16_63"              ,        16,     48,     37,     "RAZ",  1,      1,      0,      0},
3155         {"POKE"                        ,        0,      64,     38,     "RAZ",  1,      1,      0,      0},
3156         {"RST0"                        ,        0,      1,      39,     "R/W",  1,      1,      0,      0},
3157         {"RST"                         ,        1,      15,     39,     "R/W",  0,      0,      32767ull,       0ull},
3158         {"RESERVED_16_63"              ,        16,     48,     39,     "RAZ",  1,      1,      0,      0},
3159         {"SOFT_BIST"                   ,        0,      1,      40,     "R/W",  0,      0,      0ull,   0ull},
3160         {"RESERVED_1_63"               ,        1,      63,     40,     "RAZ",  1,      1,      0,      0},
3161         {"SOFT_PRST"                   ,        0,      1,      41,     "R/W",  0,      0,      1ull,   0ull},
3162         {"NPI"                         ,        1,      1,      41,     "R/W",  0,      0,      0ull,   0ull},
3163         {"HOST64"                      ,        2,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
3164         {"RESERVED_3_63"               ,        3,      61,     41,     "RAZ",  1,      1,      0,      0},
3165         {"SOFT_RST"                    ,        0,      1,      42,     "WO",   0,      0,      0ull,   0ull},
3166         {"RESERVED_1_63"               ,        1,      63,     42,     "RAZ",  1,      1,      0,      0},
3167         {"LEN"                         ,        0,      36,     43,     "R/W",  0,      0,      0ull,   0ull},
3168         {"ONE_SHOT"                    ,        36,     1,      43,     "R/W",  0,      0,      0ull,   0ull},
3169         {"RESERVED_37_63"              ,        37,     27,     43,     "RAZ",  1,      1,      0,      0},
3170         {"MODE"                        ,        0,      2,      44,     "R/W",  0,      0,      0ull,   0ull},
3171         {"STATE"                       ,        2,      2,      44,     "RO",   0,      0,      0ull,   0ull},
3172         {"LEN"                         ,        4,      16,     44,     "R/W",  0,      0,      0ull,   0ull},
3173         {"CNT"                         ,        20,     24,     44,     "RO",   0,      0,      0ull,   0ull},
3174         {"DSTOP"                       ,        44,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
3175         {"GSTOPEN"                     ,        45,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
3176         {"RESERVED_46_63"              ,        46,     18,     44,     "RAZ",  1,      1,      0,      0},
3177         {"DATA"                        ,        0,      17,     45,     "RO",   0,      1,      0ull,   0},
3178         {"DSEL_EXT"                    ,        17,     1,      45,     "R/W",  0,      0,      1ull,   0ull},
3179         {"C_MUL"                       ,        18,     5,      45,     "RO",   1,      1,      0,      0},
3180         {"CCLK_DIV2"                   ,        23,     1,      45,     "RO",   1,      1,      0,      0},
3181         {"DCLK_MUL2"                   ,        24,     1,      45,     "RO",   1,      1,      0,      0},
3182         {"D_MUL"                       ,        25,     4,      45,     "RO",   1,      1,      0,      0},
3183         {"RESERVED_29_63"              ,        29,     35,     45,     "RAZ",  1,      1,      0,      0},
3184         {"PDF"                         ,        0,      16,     46,     "RO",   0,      0,      0ull,   0ull},
3185         {"RDF"                         ,        16,     16,     46,     "RO",   0,      0,      0ull,   0ull},
3186         {"RESERVED_32_63"              ,        32,     32,     46,     "RAZ",  0,      0,      0ull,   0ull},
3187         {"P1_BRF"                      ,        0,      8,      47,     "RO",   0,      0,      0ull,   0ull},
3188         {"P0_BRF"                      ,        8,      8,      47,     "RO",   0,      0,      0ull,   0ull},
3189         {"P1_BWB"                      ,        16,     1,      47,     "RO",   0,      0,      0ull,   0ull},
3190         {"P0_BWB"                      ,        17,     1,      47,     "RO",   0,      0,      0ull,   0ull},
3191         {"CRF"                         ,        18,     1,      47,     "RO",   0,      0,      0ull,   0ull},
3192         {"DRF"                         ,        19,     1,      47,     "RO",   0,      0,      0ull,   0ull},
3193         {"GFU"                         ,        20,     1,      47,     "RO",   0,      0,      0ull,   0ull},
3194         {"IFU"                         ,        21,     1,      47,     "RO",   0,      0,      0ull,   0ull},
3195         {"CRQ"                         ,        22,     1,      47,     "RO",   0,      0,      0ull,   0ull},
3196         {"RESERVED_23_63"              ,        23,     41,     47,     "RAZ",  0,      0,      0ull,   0ull},
3197         {"SARB"                        ,        0,      1,      48,     "R/W",  0,      0,      1ull,   1ull},
3198         {"RESERVED_1_63"               ,        1,      63,     48,     "RAZ",  1,      1,      0,      0},
3199         {"DBELL"                       ,        0,      20,     49,     "R/W",  0,      1,      0ull,   0},
3200         {"RESERVED_20_63"              ,        20,     44,     49,     "RAZ",  1,      1,      0,      0},
3201         {"SIZE"                        ,        0,      9,      50,     "R/W",  0,      1,      3ull,   0},
3202         {"POOL"                        ,        9,      3,      50,     "R/W",  0,      1,      0ull,   0},
3203         {"DWBCNT"                      ,        12,     8,      50,     "R/W",  0,      1,      1ull,   0},
3204         {"RESERVED_20_63"              ,        20,     44,     50,     "RAZ",  1,      1,      0,      0},
3205         {"RESERVED_0_4"                ,        0,      5,      51,     "RAZ",  1,      1,      0,      0},
3206         {"RDPTR"                       ,        5,      31,     51,     "R/W",  0,      1,      0ull,   0},
3207         {"RESERVED_36_63"              ,        36,     28,     51,     "RAZ",  1,      1,      0,      0},
3208         {"CP2ECCENA"                   ,        0,      1,      52,     "R/W",  0,      0,      0ull,   0ull},
3209         {"CP2SBE"                      ,        1,      1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
3210         {"CP2DBE"                      ,        2,      1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
3211         {"CP2SBINA"                    ,        3,      1,      52,     "R/W",  0,      0,      0ull,   0ull},
3212         {"CP2DBINA"                    ,        4,      1,      52,     "R/W",  0,      0,      0ull,   0ull},
3213         {"CP2SYN"                      ,        5,      8,      52,     "RO",   0,      0,      0ull,   0ull},
3214         {"DTEECCENA"                   ,        13,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
3215         {"DTESBE"                      ,        14,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
3216         {"DTEDBE"                      ,        15,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
3217         {"DTESBINA"                    ,        16,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
3218         {"DTEDBINA"                    ,        17,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
3219         {"DTESYN"                      ,        18,     7,      52,     "RO",   0,      0,      0ull,   0ull},
3220         {"DTEPARENA"                   ,        25,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
3221         {"DTEPERR"                     ,        26,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
3222         {"DTEPINA"                     ,        27,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
3223         {"CP2PARENA"                   ,        28,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
3224         {"CP2PERR"                     ,        29,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
3225         {"CP2PINA"                     ,        30,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
3226         {"DBLOVF"                      ,        31,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
3227         {"DBLINA"                      ,        32,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
3228         {"RESERVED_33_63"              ,        33,     31,     52,     "RAZ",  1,      1,      0,      0},
3229         {"ENA_P1"                      ,        0,      1,      53,     "R/W",  0,      0,      1ull,   1ull},
3230         {"ENA_P0"                      ,        1,      1,      53,     "R/W",  0,      0,      1ull,   1ull},
3231         {"RESERVED_2_2"                ,        2,      1,      53,     "RAZ",  1,      1,      0,      0},
3232         {"MTYPE"                       ,        3,      1,      53,     "R/W",  0,      0,      0ull,   0ull},
3233         {"SIL_LAT"                     ,        4,      2,      53,     "R/W",  0,      0,      0ull,   0ull},
3234         {"RW_DLY"                      ,        6,      4,      53,     "R/W",  0,      0,      1ull,   1ull},
3235         {"WR_DLY"                      ,        10,     4,      53,     "R/W",  0,      0,      2ull,   2ull},
3236         {"FPRCH"                       ,        14,     2,      53,     "R/W",  0,      0,      0ull,   0ull},
3237         {"BPRCH"                       ,        16,     2,      53,     "R/W",  0,      0,      0ull,   0ull},
3238         {"BLEN"                        ,        18,     1,      53,     "R/W",  0,      0,      0ull,   0ull},
3239         {"PBUNK"                       ,        19,     3,      53,     "R/W",  0,      0,      2ull,   2ull},
3240         {"R2R_PBUNK"                   ,        22,     1,      53,     "R/W",  0,      0,      1ull,   1ull},
3241         {"INIT_P1"                     ,        23,     1,      53,     "R/W",  0,      0,      0ull,   0ull},
3242         {"INIT_P0"                     ,        24,     1,      53,     "R/W",  0,      0,      0ull,   0ull},
3243         {"BUNK_INIT"                   ,        25,     2,      53,     "R/W",  0,      0,      3ull,   3ull},
3244         {"RESERVED_27_63"              ,        27,     37,     53,     "RAZ",  1,      1,      0,      0},
3245         {"REF_INT"                     ,        0,      4,      54,     "R/W",  0,      0,      3ull,   3ull},
3246         {"TSKW"                        ,        4,      2,      54,     "R/W",  0,      0,      0ull,   0ull},
3247         {"RESERVED_6_7"                ,        6,      2,      54,     "RAZ",  0,      0,      0ull,   0ull},
3248         {"TRL"                         ,        8,      4,      54,     "R/W",  0,      0,      6ull,   6ull},
3249         {"TWL"                         ,        12,     4,      54,     "R/W",  0,      0,      7ull,   7ull},
3250         {"TRC"                         ,        16,     4,      54,     "R/W",  0,      0,      6ull,   6ull},
3251         {"TMRSC"                       ,        20,     3,      54,     "R/W",  0,      0,      6ull,   6ull},
3252         {"MRS_ENA"                     ,        23,     1,      54,     "R/W",  0,      0,      0ull,   0ull},
3253         {"AREF_ENA"                    ,        24,     1,      54,     "R/W",  0,      0,      0ull,   0ull},
3254         {"REF_INTLO"                   ,        25,     9,      54,     "R/W",  0,      0,      0ull,   0ull},
3255         {"RESERVED_34_63"              ,        34,     30,     54,     "RAZ",  1,      1,      0,      0},
3256         {"FCRAM2P"                     ,        0,      1,      55,     "R/W",  0,      0,      0ull,   0ull},
3257         {"MAXBNK"                      ,        1,      1,      55,     "R/W",  0,      0,      1ull,   1ull},
3258         {"UA_START"                    ,        2,      2,      55,     "R/W",  0,      0,      1ull,   1ull},
3259         {"REFSHORT"                    ,        4,      1,      55,     "R/W",  0,      0,      0ull,   0ull},
3260         {"TRFC"                        ,        5,      5,      55,     "R/W",  0,      0,      9ull,   9ull},
3261         {"SILRST"                      ,        10,     1,      55,     "R/W",  0,      0,      0ull,   0ull},
3262         {"DTECLKDIS"                   ,        11,     1,      55,     "R/W",  0,      0,      0ull,   0ull},
3263         {"RESERVED_12_63"              ,        12,     52,     55,     "RAZ",  1,      1,      0,      0},
3264         {"MADDR"                       ,        0,      24,     56,     "RO",   0,      0,      0ull,   0ull},
3265         {"BNUM"                        ,        24,     3,      56,     "RO",   0,      0,      0ull,   0ull},
3266         {"PNUM"                        ,        27,     1,      56,     "RO",   0,      0,      0ull,   0ull},
3267         {"FSRC"                        ,        28,     2,      56,     "RO",   0,      0,      0ull,   0ull},
3268         {"FDST"                        ,        30,     9,      56,     "RO",   0,      0,      0ull,   0ull},
3269         {"RESERVED_39_63"              ,        39,     25,     56,     "RAZ",  1,      1,      0,      0},
3270         {"MRS"                         ,        0,      15,     57,     "R/W",  0,      0,      66ull,  66ull},
3271         {"RESERVED_15_15"              ,        15,     1,      57,     "RAZ",  1,      1,      0,      0},
3272         {"EMRS"                        ,        16,     15,     57,     "R/W",  0,      0,      64ull,  64ull},
3273         {"RESERVED_31_31"              ,        31,     1,      57,     "RAZ",  1,      1,      0,      0},
3274         {"EMRS2"                       ,        32,     15,     57,     "R/W",  0,      0,      0ull,   0ull},
3275         {"RESERVED_47_63"              ,        47,     17,     57,     "RAZ",  1,      1,      0,      0},
3276         {"MRSDAT"                      ,        0,      23,     58,     "R/W",  0,      0,      2ull,   2ull},
3277         {"RESERVED_23_63"              ,        23,     41,     58,     "RAZ",  1,      1,      0,      0},
3278         {"IMODE"                       ,        0,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
3279         {"QMODE"                       ,        1,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
3280         {"PMODE"                       ,        2,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
3281         {"DTMODE"                      ,        3,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
3282         {"DCMODE"                      ,        4,      1,      59,     "R/W",  0,      0,      0ull,   0ull},
3283         {"SBDLCK"                      ,        5,      1,      59,     "R/W",  0,      0,      0ull,   0ull},
3284         {"SBDNUM"                      ,        6,      4,      59,     "R/W",  0,      0,      0ull,   0ull},
3285         {"RESERVED_10_63"              ,        10,     54,     59,     "RAZ",  1,      1,      0,      0},
3286         {"SBD0"                        ,        0,      64,     60,     "RO",   1,      1,      0,      0},
3287         {"SBD1"                        ,        0,      64,     61,     "RO",   1,      1,      0,      0},
3288         {"SBD2"                        ,        0,      64,     62,     "RO",   1,      1,      0,      0},
3289         {"SBD3"                        ,        0,      64,     63,     "RO",   1,      1,      0,      0},
3290         {"FDR"                         ,        0,      1,      64,     "RO",   0,      0,      0ull,   0ull},
3291         {"FFR"                         ,        1,      1,      64,     "RO",   0,      0,      0ull,   0ull},
3292         {"FPF1"                        ,        2,      1,      64,     "RO",   0,      0,      0ull,   0ull},
3293         {"FPF0"                        ,        3,      1,      64,     "RO",   0,      0,      0ull,   0ull},
3294         {"FRD"                         ,        4,      1,      64,     "RO",   0,      0,      0ull,   0ull},
3295         {"RESERVED_5_63"               ,        5,      59,     64,     "RAZ",  1,      1,      0,      0},
3296         {"MEM0_ERR"                    ,        0,      7,      65,     "R/W",  0,      0,      0ull,   0ull},
3297         {"MEM1_ERR"                    ,        7,      7,      65,     "R/W",  0,      0,      0ull,   0ull},
3298         {"ENB"                         ,        14,     1,      65,     "R/W",  0,      0,      0ull,   0ull},
3299         {"USE_STT"                     ,        15,     1,      65,     "R/W",  0,      0,      0ull,   0ull},
3300         {"USE_LDT"                     ,        16,     1,      65,     "R/W",  0,      0,      0ull,   0ull},
3301         {"RESET"                       ,        17,     1,      65,     "R/W",  0,      0,      0ull,   0ull},
3302         {"RESERVED_18_63"              ,        18,     46,     65,     "RAZ",  1,      1,      0,      0},
3303         {"FPF_RD"                      ,        0,      11,     66,     "R/W",  0,      0,      64ull,  0ull},
3304         {"FPF_WR"                      ,        11,     11,     66,     "R/W",  0,      0,      196ull, 0ull},
3305         {"RESERVED_22_63"              ,        22,     42,     66,     "RAZ",  1,      1,      0,      0},
3306         {"FPF_SIZ"                     ,        0,      11,     67,     "R/W",  0,      0,      256ull, 0ull},
3307         {"RESERVED_11_63"              ,        11,     53,     67,     "RAZ",  1,      1,      0,      0},
3308         {"FPF_RD"                      ,        0,      12,     68,     "R/W",  0,      0,      64ull,  0ull},
3309         {"FPF_WR"                      ,        12,     12,     68,     "R/W",  0,      0,      196ull, 0ull},
3310         {"RESERVED_24_63"              ,        24,     40,     68,     "RAZ",  1,      1,      0,      0},
3311         {"FPF_SIZ"                     ,        0,      12,     69,     "R/W",  0,      0,      256ull, 0ull},
3312         {"RESERVED_12_63"              ,        12,     52,     69,     "RAZ",  1,      1,      0,      0},
3313         {"FED0_SBE"                    ,        0,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3314         {"FED0_DBE"                    ,        1,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3315         {"FED1_SBE"                    ,        2,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3316         {"FED1_DBE"                    ,        3,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3317         {"Q0_UND"                      ,        4,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3318         {"Q0_COFF"                     ,        5,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3319         {"Q0_PERR"                     ,        6,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3320         {"Q1_UND"                      ,        7,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3321         {"Q1_COFF"                     ,        8,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3322         {"Q1_PERR"                     ,        9,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
3323         {"Q2_UND"                      ,        10,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3324         {"Q2_COFF"                     ,        11,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3325         {"Q2_PERR"                     ,        12,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3326         {"Q3_UND"                      ,        13,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3327         {"Q3_COFF"                     ,        14,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3328         {"Q3_PERR"                     ,        15,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3329         {"Q4_UND"                      ,        16,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3330         {"Q4_COFF"                     ,        17,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3331         {"Q4_PERR"                     ,        18,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3332         {"Q5_UND"                      ,        19,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3333         {"Q5_COFF"                     ,        20,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3334         {"Q5_PERR"                     ,        21,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3335         {"Q6_UND"                      ,        22,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3336         {"Q6_COFF"                     ,        23,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3337         {"Q6_PERR"                     ,        24,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3338         {"Q7_UND"                      ,        25,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3339         {"Q7_COFF"                     ,        26,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3340         {"Q7_PERR"                     ,        27,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
3341         {"RESERVED_28_63"              ,        28,     36,     70,     "RAZ",  1,      1,      0,      0},
3342         {"FED0_SBE"                    ,        0,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3343         {"FED0_DBE"                    ,        1,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3344         {"FED1_SBE"                    ,        2,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3345         {"FED1_DBE"                    ,        3,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3346         {"Q0_UND"                      ,        4,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3347         {"Q0_COFF"                     ,        5,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3348         {"Q0_PERR"                     ,        6,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3349         {"Q1_UND"                      ,        7,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3350         {"Q1_COFF"                     ,        8,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3351         {"Q1_PERR"                     ,        9,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3352         {"Q2_UND"                      ,        10,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3353         {"Q2_COFF"                     ,        11,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3354         {"Q2_PERR"                     ,        12,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3355         {"Q3_UND"                      ,        13,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3356         {"Q3_COFF"                     ,        14,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3357         {"Q3_PERR"                     ,        15,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3358         {"Q4_UND"                      ,        16,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3359         {"Q4_COFF"                     ,        17,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3360         {"Q4_PERR"                     ,        18,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3361         {"Q5_UND"                      ,        19,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3362         {"Q5_COFF"                     ,        20,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3363         {"Q5_PERR"                     ,        21,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3364         {"Q6_UND"                      ,        22,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3365         {"Q6_COFF"                     ,        23,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3366         {"Q6_PERR"                     ,        24,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3367         {"Q7_UND"                      ,        25,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3368         {"Q7_COFF"                     ,        26,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3369         {"Q7_PERR"                     ,        27,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
3370         {"RESERVED_28_63"              ,        28,     36,     71,     "RAZ",  1,      1,      0,      0},
3371         {"QUE_SIZ"                     ,        0,      29,     72,     "RO",   0,      0,      0ull,   0ull},
3372         {"RESERVED_29_63"              ,        29,     35,     72,     "RAZ",  1,      1,      0,      0},
3373         {"PG_NUM"                      ,        0,      25,     73,     "RO",   0,      1,      0ull,   0},
3374         {"RESERVED_25_63"              ,        25,     39,     73,     "RAZ",  1,      1,      0,      0},
3375         {"ACT_INDX"                    ,        0,      26,     74,     "RO",   0,      1,      0ull,   0},
3376         {"ACT_QUE"                     ,        26,     3,      74,     "RO",   0,      1,      0ull,   0},
3377         {"RESERVED_29_63"              ,        29,     35,     74,     "RAZ",  0,      0,      0ull,   7ull},
3378         {"EXP_INDX"                    ,        0,      26,     75,     "RO",   0,      1,      0ull,   0},
3379         {"EXP_QUE"                     ,        26,     3,      75,     "RO",   0,      1,      0ull,   0},
3380         {"RESERVED_29_63"              ,        29,     35,     75,     "RAZ",  0,      0,      0ull,   7ull},
3381         {"CTL"                         ,        0,      16,     76,     "R/W",  1,      0,      0,      0ull},
3382         {"RESERVED_16_63"              ,        16,     48,     76,     "RAZ",  1,      1,      0,      0},
3383         {"STATUS"                      ,        0,      32,     77,     "RO",   0,      0,      0ull,   0ull},
3384         {"RESERVED_32_63"              ,        32,     32,     77,     "RAZ",  1,      1,      0,      0},
3385         {"OUT_COL"                     ,        0,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
3386         {"NCB_OVR"                     ,        1,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
3387         {"OUT_OVR"                     ,        2,      16,     78,     "R/W1C",        0,      0,      0ull,   0ull},
3388         {"RESERVED_18_21"              ,        18,     4,      78,     "RAZ",  0,      0,      0ull,   0ull},
3389         {"LOSTSTAT"                    ,        22,     4,      78,     "R/W1C",        0,      0,      0ull,   0ull},
3390         {"STATOVR"                     ,        26,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
3391         {"INB_NXA"                     ,        27,     4,      78,     "R/W1C",        0,      0,      0ull,   0ull},
3392         {"RESERVED_31_63"              ,        31,     33,     78,     "RAZ",  1,      1,      0,      0},
3393         {"STATUS"                      ,        0,      10,     79,     "RO",   0,      0,      0ull,   0ull},
3394         {"RESERVED_10_63"              ,        10,     54,     79,     "RAZ",  1,      1,      0,      0},
3395         {"TYPE"                        ,        0,      1,      80,     "RO",   1,      1,      0,      0},
3396         {"EN"                          ,        1,      1,      80,     "RO",   1,      1,      0,      0},
3397         {"RESERVED_2_63"               ,        2,      62,     80,     "RAZ",  1,      1,      0,      0},
3398         {"PRT"                         ,        0,      6,      81,     "RO",   0,      1,      0ull,   0},
3399         {"RESERVED_6_63"               ,        6,      58,     81,     "RAZ",  1,      1,      0,      0},
3400         {"EN"                          ,        0,      1,      82,     "R/W",  0,      1,      0ull,   0},
3401         {"SPEED"                       ,        1,      1,      82,     "R/W",  0,      1,      1ull,   0},
3402         {"DUPLEX"                      ,        2,      1,      82,     "R/W",  0,      1,      1ull,   0},
3403         {"SLOTTIME"                    ,        3,      1,      82,     "R/W",  0,      1,      1ull,   0},
3404         {"RESERVED_4_63"               ,        4,      60,     82,     "RAZ",  1,      1,      0,      0},
3405         {"ADR"                         ,        0,      64,     83,     "R/W",  0,      1,      0ull,   0},
3406         {"ADR"                         ,        0,      64,     84,     "R/W",  0,      1,      0ull,   0},
3407         {"ADR"                         ,        0,      64,     85,     "R/W",  0,      1,      0ull,   0},
3408         {"ADR"                         ,        0,      64,     86,     "R/W",  0,      1,      0ull,   0},
3409         {"ADR"                         ,        0,      64,     87,     "R/W",  0,      1,      0ull,   0},
3410         {"ADR"                         ,        0,      64,     88,     "R/W",  0,      1,      0ull,   0},
3411         {"EN"                          ,        0,      8,      89,     "R/W",  0,      1,      0ull,   0},
3412         {"RESERVED_8_63"               ,        8,      56,     89,     "RAZ",  1,      1,      0,      0},
3413         {"BCST"                        ,        0,      1,      90,     "R/W",  0,      1,      1ull,   0},
3414         {"MCST"                        ,        1,      2,      90,     "R/W",  0,      1,      0ull,   0},
3415         {"CAM_MODE"                    ,        3,      1,      90,     "R/W",  0,      1,      0ull,   0},
3416         {"RESERVED_4_63"               ,        4,      60,     90,     "RAZ",  1,      1,      0,      0},
3417         {"CNT"                         ,        0,      5,      91,     "R/W",  0,      0,      24ull,  24ull},
3418         {"RESERVED_5_63"               ,        5,      59,     91,     "RAZ",  1,      1,      0,      0},
3419         {"MINERR"                      ,        0,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3420         {"CAREXT"                      ,        1,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3421         {"MAXERR"                      ,        2,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3422         {"JABBER"                      ,        3,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3423         {"FCSERR"                      ,        4,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3424         {"ALNERR"                      ,        5,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3425         {"LENERR"                      ,        6,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3426         {"RCVERR"                      ,        7,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3427         {"SKPERR"                      ,        8,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3428         {"NIBERR"                      ,        9,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
3429         {"RESERVED_10_63"              ,        10,     54,     92,     "RAZ",  1,      1,      0,      0},
3430         {"PRE_CHK"                     ,        0,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
3431         {"PRE_STRP"                    ,        1,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
3432         {"CTL_DRP"                     ,        2,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
3433         {"CTL_BCK"                     ,        3,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
3434         {"CTL_MCST"                    ,        4,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
3435         {"CTL_SMAC"                    ,        5,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
3436         {"PRE_FREE"                    ,        6,      1,      93,     "R/W",  0,      0,      0ull,   0ull},
3437         {"VLAN_LEN"                    ,        7,      1,      93,     "R/W",  0,      0,      0ull,   0ull},
3438         {"RESERVED_8_63"               ,        8,      56,     93,     "RAZ",  1,      1,      0,      0},
3439         {"LEN"                         ,        0,      16,     94,     "R/W",  0,      0,      1536ull,        1536ull},
3440         {"RESERVED_16_63"              ,        16,     48,     94,     "RAZ",  1,      1,      0,      0},
3441         {"LEN"                         ,        0,      16,     95,     "R/W",  0,      0,      64ull,  64ull},
3442         {"RESERVED_16_63"              ,        16,     48,     95,     "RAZ",  1,      1,      0,      0},
3443         {"IFG"                         ,        0,      4,      96,     "R/W",  0,      0,      12ull,  12ull},
3444         {"RESERVED_4_63"               ,        4,      60,     96,     "RAZ",  1,      1,      0,      0},
3445         {"MINERR"                      ,        0,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3446         {"CAREXT"                      ,        1,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3447         {"MAXERR"                      ,        2,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3448         {"JABBER"                      ,        3,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3449         {"FCSERR"                      ,        4,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3450         {"ALNERR"                      ,        5,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3451         {"LENERR"                      ,        6,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3452         {"RCVERR"                      ,        7,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3453         {"SKPERR"                      ,        8,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3454         {"NIBERR"                      ,        9,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
3455         {"OVRERR"                      ,        10,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
3456         {"PCTERR"                      ,        11,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
3457         {"RSVERR"                      ,        12,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
3458         {"FALERR"                      ,        13,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
3459         {"COLDET"                      ,        14,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
3460         {"IFGERR"                      ,        15,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
3461         {"PHY_LINK"                    ,        16,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
3462         {"PHY_SPD"                     ,        17,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
3463         {"PHY_DUPX"                    ,        18,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
3464         {"RESERVED_19_63"              ,        19,     45,     97,     "RAZ",  1,      1,      0,      0},
3465         {"MINERR"                      ,        0,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3466         {"CAREXT"                      ,        1,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3467         {"MAXERR"                      ,        2,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3468         {"JABBER"                      ,        3,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3469         {"FCSERR"                      ,        4,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3470         {"ALNERR"                      ,        5,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3471         {"LENERR"                      ,        6,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3472         {"RCVERR"                      ,        7,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3473         {"SKPERR"                      ,        8,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3474         {"NIBERR"                      ,        9,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3475         {"OVRERR"                      ,        10,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3476         {"PCTERR"                      ,        11,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3477         {"RSVERR"                      ,        12,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3478         {"FALERR"                      ,        13,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3479         {"COLDET"                      ,        14,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3480         {"IFGERR"                      ,        15,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3481         {"PHY_LINK"                    ,        16,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3482         {"PHY_SPD"                     ,        17,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3483         {"PHY_DUPX"                    ,        18,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
3484         {"RESERVED_19_63"              ,        19,     45,     98,     "RAZ",  1,      1,      0,      0},
3485         {"CNT"                         ,        0,      16,     99,     "R/W",  0,      0,      10240ull,       10240ull},
3486         {"RESERVED_16_63"              ,        16,     48,     99,     "RAZ",  1,      1,      0,      0},
3487         {"STATUS"                      ,        0,      1,      100,    "RO",   0,      1,      0ull,   0},
3488         {"SPEED"                       ,        1,      2,      100,    "RO",   0,      1,      0ull,   0},
3489         {"DUPLEX"                      ,        3,      1,      100,    "RO",   0,      1,      0ull,   0},
3490         {"RESERVED_4_63"               ,        4,      60,     100,    "RAZ",  1,      1,      0,      0},
3491         {"RD_CLR"                      ,        0,      1,      101,    "R/W",  0,      0,      0ull,   0ull},
3492         {"RESERVED_1_63"               ,        1,      63,     101,    "RAZ",  1,      1,      0,      0},
3493         {"CNT"                         ,        0,      48,     102,    "RC/W", 0,      1,      0ull,   0},
3494         {"RESERVED_48_63"              ,        48,     16,     102,    "RAZ",  1,      1,      0,      0},
3495         {"CNT"                         ,        0,      48,     103,    "RC/W", 0,      1,      0ull,   0},
3496         {"RESERVED_48_63"              ,        48,     16,     103,    "RAZ",  1,      1,      0,      0},
3497         {"CNT"                         ,        0,      48,     104,    "RC/W", 0,      1,      0ull,   0},
3498         {"RESERVED_48_63"              ,        48,     16,     104,    "RAZ",  1,      1,      0,      0},
3499         {"CNT"                         ,        0,      48,     105,    "RC/W", 0,      1,      0ull,   0},
3500         {"RESERVED_48_63"              ,        48,     16,     105,    "RAZ",  1,      1,      0,      0},
3501         {"CNT"                         ,        0,      32,     106,    "RC/W", 0,      1,      0ull,   0},
3502         {"RESERVED_32_63"              ,        32,     32,     106,    "RAZ",  1,      1,      0,      0},
3503         {"CNT"                         ,        0,      32,     107,    "RC/W", 0,      1,      0ull,   0},
3504         {"RESERVED_32_63"              ,        32,     32,     107,    "RAZ",  1,      1,      0,      0},
3505         {"CNT"                         ,        0,      32,     108,    "RC/W", 0,      1,      0ull,   0},
3506         {"RESERVED_32_63"              ,        32,     32,     108,    "RAZ",  1,      1,      0,      0},
3507         {"CNT"                         ,        0,      32,     109,    "RC/W", 0,      1,      0ull,   0},
3508         {"RESERVED_32_63"              ,        32,     32,     109,    "RAZ",  1,      1,      0,      0},
3509         {"CNT"                         ,        0,      32,     110,    "RC/W", 0,      1,      0ull,   0},
3510         {"RESERVED_32_63"              ,        32,     32,     110,    "RAZ",  1,      1,      0,      0},
3511         {"LEN"                         ,        0,      7,      111,    "R/W",  0,      0,      0ull,   0ull},
3512         {"RESERVED_7_7"                ,        7,      1,      111,    "RAZ",  1,      1,      0,      0},
3513         {"FCSSEL"                      ,        8,      1,      111,    "R/W",  0,      0,      0ull,   0ull},
3514         {"RESERVED_9_63"               ,        9,      55,     111,    "RAZ",  1,      1,      0,      0},
3515         {"MARK"                        ,        0,      6,      112,    "R/W",  1,      1,      0,      0},
3516         {"RESERVED_6_63"               ,        6,      58,     112,    "RAZ",  1,      1,      0,      0},
3517         {"MARK"                        ,        0,      6,      113,    "R/W",  0,      0,      16ull,  16ull},
3518         {"RESERVED_6_63"               ,        6,      58,     113,    "RAZ",  1,      1,      0,      0},
3519         {"MARK"                        ,        0,      9,      114,    "R/W",  1,      1,      0,      0},
3520         {"RESERVED_9_63"               ,        9,      55,     114,    "RAZ",  1,      1,      0,      0},
3521         {"EN"                          ,        0,      16,     115,    "R/W",  0,      0,      0ull,   0ull},
3522         {"RESERVED_16_63"              ,        16,     48,     115,    "RAZ",  1,      1,      0,      0},
3523         {"DPRT"                        ,        0,      4,      116,    "R/W",  0,      0,      0ull,   0ull},
3524         {"RESERVED_4_63"               ,        4,      60,     116,    "RAZ",  1,      1,      0,      0},
3525         {"PRTS"                        ,        0,      3,      117,    "R/W",  0,      0,      4ull,   4ull},
3526         {"RESERVED_3_63"               ,        3,      61,     117,    "RAZ",  1,      1,      0,      0},
3527         {"SMAC"                        ,        0,      48,     118,    "R/W",  0,      1,      0ull,   0},
3528         {"RESERVED_48_63"              ,        48,     16,     118,    "RAZ",  1,      1,      0,      0},
3529         {"CNT"                         ,        0,      16,     119,    "R/W1C",        0,      0,      0ull,   0ull},
3530         {"BP"                          ,        16,     1,      119,    "RO",   0,      0,      0ull,   0ull},
3531         {"RESERVED_17_63"              ,        17,     47,     119,    "RAZ",  1,      1,      0,      0},
3532         {"PREAMBLE"                    ,        0,      1,      120,    "R/W",  0,      0,      1ull,   1ull},
3533         {"PAD"                         ,        1,      1,      120,    "R/W",  0,      0,      1ull,   1ull},
3534         {"FCS"                         ,        2,      1,      120,    "R/W",  0,      0,      1ull,   1ull},
3535         {"FORCE_FCS"                   ,        3,      1,      120,    "R/W",  0,      0,      1ull,   1ull},
3536         {"RESERVED_4_63"               ,        4,      60,     120,    "RAZ",  1,      1,      0,      0},
3537         {"BURST"                       ,        0,      16,     121,    "R/W",  0,      0,      8192ull,        8192ull},
3538         {"RESERVED_16_63"              ,        16,     48,     121,    "RAZ",  1,      1,      0,      0},
3539         {"CLK_CNT"                     ,        0,      6,      122,    "R/W",  0,      0,      1ull,   1ull},
3540         {"RESERVED_6_63"               ,        6,      58,     122,    "RAZ",  1,      1,      0,      0},
3541         {"XSCOL_EN"                    ,        0,      1,      123,    "R/W",  0,      0,      1ull,   1ull},
3542         {"XSDEF_EN"                    ,        1,      1,      123,    "R/W",  0,      0,      1ull,   1ull},
3543         {"RESERVED_2_63"               ,        2,      62,     123,    "RAZ",  1,      1,      0,      0},
3544         {"MIN_SIZE"                    ,        0,      8,      124,    "R/W",  0,      0,      59ull,  59ull},
3545         {"RESERVED_8_63"               ,        8,      56,     124,    "RAZ",  1,      1,      0,      0},
3546         {"INTERVAL"                    ,        0,      16,     125,    "R/W",  0,      1,      16ull,  0},
3547         {"RESERVED_16_63"              ,        16,     48,     125,    "RAZ",  1,      1,      0,      0},
3548         {"TIME"                        ,        0,      16,     126,    "R/W",  0,      1,      96ull,  0},
3549         {"RESERVED_16_63"              ,        16,     48,     126,    "RAZ",  1,      1,      0,      0},
3550         {"TIME"                        ,        0,      16,     127,    "RO",   1,      1,      0,      0},
3551         {"RESERVED_16_63"              ,        16,     48,     127,    "RAZ",  1,      1,      0,      0},
3552         {"SEND"                        ,        0,      1,      128,    "R/W",  0,      0,      1ull,   1ull},
3553         {"RESERVED_1_63"               ,        1,      63,     128,    "RAZ",  1,      1,      0,      0},
3554         {"SLOT"                        ,        0,      10,     129,    "R/W",  0,      0,      512ull, 512ull},
3555         {"RESERVED_10_63"              ,        10,     54,     129,    "RAZ",  1,      1,      0,      0},
3556         {"TIME"                        ,        0,      16,     130,    "R/W",  0,      1,      0ull,   0},
3557         {"RESERVED_16_63"              ,        16,     48,     130,    "RAZ",  1,      1,      0,      0},
3558         {"XSCOL"                       ,        0,      32,     131,    "RC/W", 0,      1,      0ull,   0},
3559         {"XSDEF"                       ,        32,     32,     131,    "RC/W", 0,      1,      0ull,   0},
3560         {"MCOL"                        ,        0,      32,     132,    "RC/W", 0,      1,      0ull,   0},
3561         {"SCOL"                        ,        32,     32,     132,    "RC/W", 0,      1,      0ull,   0},
3562         {"OCTS"                        ,        0,      48,     133,    "RC/W", 0,      1,      0ull,   0},
3563         {"RESERVED_48_63"              ,        48,     16,     133,    "RAZ",  1,      1,      0,      0},
3564         {"PKTS"                        ,        0,      32,     134,    "RC/W", 0,      1,      0ull,   0},
3565         {"RESERVED_32_63"              ,        32,     32,     134,    "RAZ",  1,      1,      0,      0},
3566         {"HIST0"                       ,        0,      32,     135,    "RC/W", 0,      1,      0ull,   0},
3567         {"HIST1"                       ,        32,     32,     135,    "RC/W", 0,      1,      0ull,   0},
3568         {"HIST2"                       ,        0,      32,     136,    "RC/W", 0,      1,      0ull,   0},
3569         {"HIST3"                       ,        32,     32,     136,    "RC/W", 0,      1,      0ull,   0},
3570         {"HIST4"                       ,        0,      32,     137,    "RC/W", 0,      1,      0ull,   0},
3571         {"HIST5"                       ,        32,     32,     137,    "RC/W", 0,      1,      0ull,   0},
3572         {"HIST6"                       ,        0,      32,     138,    "RC/W", 0,      1,      0ull,   0},
3573         {"HIST7"                       ,        32,     32,     138,    "RC/W", 0,      1,      0ull,   0},
3574         {"BCST"                        ,        0,      32,     139,    "RC/W", 0,      1,      0ull,   0},
3575         {"MCST"                        ,        32,     32,     139,    "RC/W", 0,      1,      0ull,   0},
3576         {"CTL"                         ,        0,      32,     140,    "RC/W", 0,      1,      0ull,   0},
3577         {"UNDFLW"                      ,        32,     32,     140,    "RC/W", 0,      1,      0ull,   0},
3578         {"RD_CLR"                      ,        0,      1,      141,    "R/W",  0,      0,      0ull,   0ull},
3579         {"RESERVED_1_63"               ,        1,      63,     141,    "RAZ",  1,      1,      0,      0},
3580         {"CNT"                         ,        0,      9,      142,    "R/W",  0,      0,      32ull,  32ull},
3581         {"RESERVED_9_63"               ,        9,      55,     142,    "RAZ",  1,      1,      0,      0},
3582         {"BP"                          ,        0,      4,      143,    "RO",   0,      0,      0ull,   0ull},
3583         {"RESERVED_4_63"               ,        4,      60,     143,    "RAZ",  1,      1,      0,      0},
3584         {"LIMIT"                       ,        0,      5,      144,    "R/W",  0,      0,      16ull,  16ull},
3585         {"RESERVED_5_63"               ,        5,      59,     144,    "RAZ",  1,      1,      0,      0},
3586         {"CORRUPT"                     ,        0,      4,      145,    "R/W",  0,      0,      15ull,  15ull},
3587         {"RESERVED_4_63"               ,        4,      60,     145,    "RAZ",  1,      1,      0,      0},
3588         {"IFG1"                        ,        0,      4,      146,    "R/W",  0,      1,      8ull,   0},
3589         {"IFG2"                        ,        4,      4,      146,    "R/W",  0,      1,      4ull,   0},
3590         {"RESERVED_8_63"               ,        8,      56,     146,    "RAZ",  1,      1,      0,      0},
3591         {"PKO_NXA"                     ,        0,      1,      147,    "R/W",  0,      0,      0ull,   0ull},
3592         {"NCB_NXA"                     ,        1,      1,      147,    "R/W",  0,      0,      0ull,   0ull},
3593         {"UNDFLW"                      ,        2,      4,      147,    "R/W",  0,      0,      0ull,   0ull},
3594         {"RESERVED_6_7"                ,        6,      2,      147,    "RAZ",  0,      0,      0ull,   0ull},
3595         {"XSCOL"                       ,        8,      4,      147,    "R/W",  0,      0,      0ull,   0ull},
3596         {"XSDEF"                       ,        12,     4,      147,    "R/W",  0,      0,      0ull,   0ull},
3597         {"RESERVED_16_63"              ,        16,     48,     147,    "RAZ",  1,      1,      0,      0},
3598         {"PKO_NXA"                     ,        0,      1,      148,    "R/W1C",        0,      0,      0ull,   0ull},
3599         {"NCB_NXA"                     ,        1,      1,      148,    "R/W1C",        0,      0,      0ull,   0ull},
3600         {"UNDFLW"                      ,        2,      4,      148,    "R/W1C",        0,      0,      0ull,   0ull},
3601         {"RESERVED_6_7"                ,        6,      2,      148,    "RAZ",  0,      0,      0ull,   0ull},
3602         {"XSCOL"                       ,        8,      4,      148,    "R/W1C",        0,      0,      0ull,   0ull},
3603         {"XSDEF"                       ,        12,     4,      148,    "R/W1C",        0,      0,      0ull,   0ull},
3604         {"RESERVED_16_63"              ,        16,     48,     148,    "RAZ",  1,      1,      0,      0},
3605         {"JAM"                         ,        0,      8,      149,    "R/W",  0,      1,      238ull, 0},
3606         {"RESERVED_8_63"               ,        8,      56,     149,    "RAZ",  1,      1,      0,      0},
3607         {"LFSR"                        ,        0,      16,     150,    "R/W",  0,      1,      65535ull,       0},
3608         {"RESERVED_16_63"              ,        16,     48,     150,    "RAZ",  1,      1,      0,      0},
3609         {"IGN_FULL"                    ,        0,      4,      151,    "R/W",  0,      0,      0ull,   0ull},
3610         {"BP"                          ,        4,      4,      151,    "R/W",  0,      0,      0ull,   0ull},
3611         {"EN"                          ,        8,      4,      151,    "R/W",  0,      0,      0ull,   0ull},
3612         {"RESERVED_12_63"              ,        12,     52,     151,    "RAZ",  1,      1,      0,      0},
3613         {"DMAC"                        ,        0,      48,     152,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
3614         {"RESERVED_48_63"              ,        48,     16,     152,    "RAZ",  1,      1,      0,      0},
3615         {"TYPE"                        ,        0,      16,     153,    "R/W",  0,      0,      34824ull,       34824ull},
3616         {"RESERVED_16_63"              ,        16,     48,     153,    "RAZ",  1,      1,      0,      0},
3617         {"PRTS"                        ,        0,      5,      154,    "R/W",  0,      1,      1ull,   0},
3618         {"RESERVED_5_63"               ,        5,      59,     154,    "RAZ",  1,      1,      0,      0},
3619         {"CONT_PKT"                    ,        0,      1,      155,    "R/W",  0,      1,      0ull,   0},
3620         {"TPA_CLR"                     ,        1,      1,      155,    "R/W",  0,      1,      0ull,   0},
3621         {"RESERVED_2_63"               ,        2,      62,     155,    "RAZ",  0,      0,      0ull,   0ull},
3622         {"MAX1"                        ,        0,      8,      156,    "R/W",  0,      1,      8ull,   0},
3623         {"MAX2"                        ,        8,      8,      156,    "R/W",  0,      1,      4ull,   0},
3624         {"RESERVED_16_63"              ,        16,     48,     156,    "RAZ",  1,      1,      0,      0},
3625         {"THRESH"                      ,        0,      6,      157,    "R/W",  0,      1,      4ull,   0},
3626         {"RESERVED_6_63"               ,        6,      58,     157,    "RAZ",  1,      1,      0,      0},
3627         {"TX_OE"                       ,        0,      1,      158,    "R/W",  0,      0,      0ull,   0ull},
3628         {"RX_XOR"                      ,        1,      1,      158,    "R/W",  0,      0,      0ull,   0ull},
3629         {"INT_EN"                      ,        2,      1,      158,    "R/W",  0,      0,      0ull,   0ull},
3630         {"INT_TYPE"                    ,        3,      1,      158,    "R/W",  0,      0,      0ull,   0ull},
3631         {"FIL_CNT"                     ,        4,      4,      158,    "R/W",  0,      0,      0ull,   0ull},
3632         {"FIL_SEL"                     ,        8,      4,      158,    "R/W",  0,      0,      0ull,   0ull},
3633         {"RESERVED_12_63"              ,        12,     52,     158,    "RAZ",  1,      1,      0,      0},
3634         {"TYPE"                        ,        0,      16,     159,    "WO",   0,      0,      0ull,   0ull},
3635         {"RESERVED_16_63"              ,        16,     48,     159,    "RAZ",  1,      1,      0,      0},
3636         {"DAT"                         ,        0,      16,     160,    "RO",   0,      0,      0ull,   0ull},
3637         {"RESERVED_16_63"              ,        16,     48,     160,    "RAZ",  1,      1,      0,      0},
3638         {"CLR"                         ,        0,      16,     161,    "WO",   0,      0,      0ull,   0ull},
3639         {"RESERVED_16_63"              ,        16,     48,     161,    "RAZ",  1,      1,      0,      0},
3640         {"SET"                         ,        0,      16,     162,    "WO",   0,      0,      0ull,   0ull},
3641         {"RESERVED_16_63"              ,        16,     48,     162,    "RAZ",  1,      1,      0,      0},
3642         {"ICD"                         ,        0,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3643         {"IBD"                         ,        1,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3644         {"ICRP1"                       ,        2,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3645         {"ICRP0"                       ,        3,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3646         {"ICRN1"                       ,        4,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3647         {"ICRN0"                       ,        5,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3648         {"IBRQ1"                       ,        6,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3649         {"IBRQ0"                       ,        7,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3650         {"ICNRT"                       ,        8,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3651         {"IBR1"                        ,        9,      1,      163,    "RO",   0,      0,      0ull,   0ull},
3652         {"IBR0"                        ,        10,     1,      163,    "RO",   0,      0,      0ull,   0ull},
3653         {"IBDR1"                       ,        11,     1,      163,    "RO",   0,      0,      0ull,   0ull},
3654         {"IBDR0"                       ,        12,     1,      163,    "RO",   0,      0,      0ull,   0ull},
3655         {"ICNR0"                       ,        13,     1,      163,    "RO",   0,      0,      0ull,   0ull},
3656         {"ICNR1"                       ,        14,     1,      163,    "RO",   0,      0,      0ull,   0ull},
3657         {"ICR1"                        ,        15,     1,      163,    "RO",   0,      0,      0ull,   0ull},
3658         {"ICR0"                        ,        16,     1,      163,    "RO",   0,      0,      0ull,   0ull},
3659         {"ICNRCB"                      ,        17,     1,      163,    "RO",   0,      0,      0ull,   0ull},
3660         {"RESERVED_18_63"              ,        18,     46,     163,    "RAZ",  1,      1,      0,      0},
3661         {"FAU_END"                     ,        0,      1,      164,    "R/W",  0,      0,      0ull,   0ull},
3662         {"DWB_ENB"                     ,        1,      1,      164,    "R/W",  0,      0,      1ull,   1ull},
3663         {"PKO_ENB"                     ,        2,      1,      164,    "R/W",  0,      0,      0ull,   0ull},
3664         {"INB_MAT"                     ,        3,      1,      164,    "R/W1C",        0,      0,      0ull,   0ull},
3665         {"OUTB_MAT"                    ,        4,      1,      164,    "R/W1C",        0,      0,      0ull,   0ull},
3666         {"RESERVED_5_63"               ,        5,      59,     164,    "RAZ",  1,      1,      0,      0},
3667         {"CNT_VAL"                     ,        0,      15,     165,    "R/W",  0,      0,      0ull,   0ull},
3668         {"CNT_ENB"                     ,        15,     1,      165,    "R/W",  0,      0,      0ull,   0ull},
3669         {"RESERVED_16_63"              ,        16,     48,     165,    "RAZ",  1,      1,      0,      0},
3670         {"TOUT_VAL"                    ,        0,      12,     166,    "R/W",  0,      0,      4ull,   4ull},
3671         {"TOUT_ENB"                    ,        12,     1,      166,    "R/W",  0,      0,      1ull,   0ull},
3672         {"RESERVED_13_63"              ,        13,     51,     166,    "RAZ",  1,      1,      0,      0},
3673         {"CNT_VAL"                     ,        0,      15,     167,    "R/W",  0,      0,      0ull,   0ull},
3674         {"CNT_ENB"                     ,        15,     1,      167,    "R/W",  0,      0,      0ull,   0ull},
3675         {"RESERVED_16_63"              ,        16,     48,     167,    "RAZ",  1,      1,      0,      0},
3676         {"SRC"                         ,        0,      8,      168,    "R/W",  0,      1,      0ull,   0},
3677         {"DST"                         ,        8,      9,      168,    "R/W",  0,      1,      0ull,   0},
3678         {"OPC"                         ,        17,     4,      168,    "R/W",  0,      1,      0ull,   0},
3679         {"MASK"                        ,        21,     8,      168,    "R/W",  0,      1,      0ull,   0},
3680         {"RESERVED_29_63"              ,        29,     35,     168,    "RAZ",  1,      1,      0,      0},
3681         {"SRC"                         ,        0,      8,      169,    "R/W",  0,      1,      0ull,   0},
3682         {"DST"                         ,        8,      9,      169,    "R/W",  0,      1,      0ull,   0},
3683         {"OPC"                         ,        17,     4,      169,    "R/W",  0,      1,      0ull,   0},
3684         {"MASK"                        ,        21,     8,      169,    "R/W",  0,      1,      0ull,   0},
3685         {"RESERVED_29_63"              ,        29,     35,     169,    "RAZ",  1,      1,      0,      0},
3686         {"DATA"                        ,        0,      64,     170,    "R/W",  0,      1,      0ull,   0},
3687         {"DATA"                        ,        0,      64,     171,    "R/W",  0,      1,      0ull,   0},
3688         {"NP_SOP"                      ,        0,      1,      172,    "R/W",  0,      0,      0ull,   0ull},
3689         {"NP_EOP"                      ,        1,      1,      172,    "R/W",  0,      0,      0ull,   0ull},
3690         {"P_SOP"                       ,        2,      1,      172,    "R/W",  0,      0,      0ull,   0ull},
3691         {"P_EOP"                       ,        3,      1,      172,    "R/W",  0,      0,      0ull,   0ull},
3692         {"RESERVED_4_63"               ,        4,      60,     172,    "RAZ",  1,      1,      0,      0},
3693         {"NP_SOP"                      ,        0,      1,      173,    "R/W1C",        0,      0,      0ull,   0ull},
3694         {"NP_EOP"                      ,        1,      1,      173,    "R/W1C",        0,      0,      0ull,   0ull},
3695         {"P_SOP"                       ,        2,      1,      173,    "R/W1C",        0,      0,      0ull,   0ull},
3696         {"P_EOP"                       ,        3,      1,      173,    "R/W1C",        0,      0,      0ull,   0ull},
3697         {"RESERVED_4_63"               ,        4,      60,     173,    "RAZ",  1,      1,      0,      0},
3698         {"CNT_VAL"                     ,        0,      15,     174,    "R/W",  0,      0,      0ull,   0ull},
3699         {"CNT_ENB"                     ,        15,     1,      174,    "R/W",  0,      0,      0ull,   0ull},
3700         {"RESERVED_16_63"              ,        16,     48,     174,    "RAZ",  1,      1,      0,      0},
3701         {"CNT_VAL"                     ,        0,      15,     175,    "R/W",  0,      0,      0ull,   0ull},
3702         {"CNT_ENB"                     ,        15,     1,      175,    "R/W",  0,      0,      0ull,   0ull},
3703         {"RESERVED_16_63"              ,        16,     48,     175,    "RAZ",  1,      1,      0,      0},
3704         {"CNT_VAL"                     ,        0,      15,     176,    "R/W",  0,      0,      0ull,   0ull},
3705         {"CNT_ENB"                     ,        15,     1,      176,    "R/W",  0,      0,      0ull,   0ull},
3706         {"RESERVED_16_63"              ,        16,     48,     176,    "RAZ",  1,      1,      0,      0},
3707         {"SRC"                         ,        0,      9,      177,    "R/W",  0,      1,      0ull,   0},
3708         {"DST"                         ,        9,      8,      177,    "R/W",  0,      1,      0ull,   0},
3709         {"EOT"                         ,        17,     1,      177,    "R/W",  0,      1,      0ull,   0},
3710         {"MASK"                        ,        18,     8,      177,    "R/W",  0,      1,      0ull,   0},
3711         {"RESERVED_26_63"              ,        26,     38,     177,    "RAZ",  1,      1,      0,      0},
3712         {"SRC"                         ,        0,      9,      178,    "R/W",  0,      1,      0ull,   0},
3713         {"DST"                         ,        9,      8,      178,    "R/W",  0,      1,      0ull,   0},
3714         {"EOT"                         ,        17,     1,      178,    "R/W",  0,      1,      0ull,   0},
3715         {"MASK"                        ,        18,     8,      178,    "R/W",  0,      1,      0ull,   0},
3716         {"RESERVED_26_63"              ,        26,     38,     178,    "RAZ",  1,      1,      0,      0},
3717         {"DATA"                        ,        0,      64,     179,    "R/W",  0,      1,      0ull,   0},
3718         {"DATA"                        ,        0,      64,     180,    "R/W",  0,      1,      0ull,   0},
3719         {"CNT_VAL"                     ,        0,      15,     181,    "R/W",  0,      0,      0ull,   0ull},
3720         {"CNT_ENB"                     ,        15,     1,      181,    "R/W",  0,      0,      0ull,   0ull},
3721         {"RESERVED_16_63"              ,        16,     48,     181,    "RAZ",  1,      1,      0,      0},
3722         {"CNT_VAL"                     ,        0,      15,     182,    "R/W",  0,      0,      0ull,   0ull},
3723         {"CNT_ENB"                     ,        15,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
3724         {"RESERVED_16_63"              ,        16,     48,     182,    "RAZ",  1,      1,      0,      0},
3725         {"CNT_VAL"                     ,        0,      15,     183,    "R/W",  0,      0,      0ull,   0ull},
3726         {"CNT_ENB"                     ,        15,     1,      183,    "R/W",  0,      0,      0ull,   0ull},
3727         {"RESERVED_16_63"              ,        16,     48,     183,    "RAZ",  1,      1,      0,      0},
3728         {"PORT"                        ,        0,      6,      184,    "RO",   0,      1,      0ull,   0},
3729         {"RESERVED_6_63"               ,        6,      58,     184,    "RAZ",  1,      1,      0,      0},
3730         {"SKIP_SZ"                     ,        0,      6,      185,    "R/W",  0,      0,      0ull,   0ull},
3731         {"RESERVED_6_63"               ,        6,      58,     185,    "RAZ",  1,      1,      0,      0},
3732         {"BACK"                        ,        0,      4,      186,    "R/W",  0,      0,      0ull,   0ull},
3733         {"RESERVED_4_63"               ,        4,      60,     186,    "RAZ",  1,      1,      0,      0},
3734         {"BACK"                        ,        0,      4,      187,    "R/W",  0,      0,      0ull,   0ull},
3735         {"RESERVED_4_63"               ,        4,      60,     187,    "RAZ",  1,      1,      0,      0},
3736         {"PWP"                         ,        0,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3737         {"IPD_NEW"                     ,        1,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3738         {"IPD_OLD"                     ,        2,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3739         {"PRC_OFF"                     ,        3,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3740         {"PWQ0"                        ,        4,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3741         {"PWQ1"                        ,        5,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3742         {"PBM_WORD"                    ,        6,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3743         {"PBM0"                        ,        7,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3744         {"PBM1"                        ,        8,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3745         {"PBM2"                        ,        9,      1,      188,    "RO",   0,      0,      0ull,   0ull},
3746         {"PBM3"                        ,        10,     1,      188,    "RO",   0,      0,      0ull,   0ull},
3747         {"IPQ_PBE0"                    ,        11,     1,      188,    "RO",   0,      0,      0ull,   0ull},
3748         {"IPQ_PBE1"                    ,        12,     1,      188,    "RO",   0,      0,      0ull,   0ull},
3749         {"PWQ_POW"                     ,        13,     1,      188,    "RO",   0,      0,      0ull,   0ull},
3750         {"PWQ_WP1"                     ,        14,     1,      188,    "RO",   0,      0,      0ull,   0ull},
3751         {"PWQ_WQED"                    ,        15,     1,      188,    "RO",   0,      0,      0ull,   0ull},
3752         {"RESERVED_16_63"              ,        16,     48,     188,    "RAZ",  1,      1,      0,      0},
3753         {"PRT_ENB"                     ,        0,      36,     189,    "R/W",  0,      0,      0ull,   0ull},
3754         {"RESERVED_36_63"              ,        36,     28,     189,    "RAZ",  1,      1,      0,      0},
3755         {"CLK_CNT"                     ,        0,      64,     190,    "RO",   0,      0,      0ull,   0ull},
3756         {"IPD_EN"                      ,        0,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
3757         {"OPC_MODE"                    ,        1,      2,      191,    "R/W",  0,      0,      0ull,   0ull},
3758         {"PBP_EN"                      ,        3,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
3759         {"WQE_LEND"                    ,        4,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
3760         {"PKT_LEND"                    ,        5,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
3761         {"NADDBUF"                     ,        6,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
3762         {"ADDPKT"                      ,        7,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
3763         {"RESET"                       ,        8,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
3764         {"RESERVED_9_63"               ,        9,      55,     191,    "RAZ",  1,      1,      0,      0},
3765         {"PRC_PAR0"                    ,        0,      1,      192,    "R/W",  0,      0,      0ull,   0ull},
3766         {"PRC_PAR1"                    ,        1,      1,      192,    "R/W",  0,      0,      0ull,   0ull},
3767         {"PRC_PAR2"                    ,        2,      1,      192,    "R/W",  0,      0,      0ull,   0ull},
3768         {"PRC_PAR3"                    ,        3,      1,      192,    "R/W",  0,      0,      0ull,   0ull},
3769         {"BP_SUB"                      ,        4,      1,      192,    "R/W",  0,      0,      0ull,   0ull},
3770         {"RESERVED_5_63"               ,        5,      59,     192,    "RAZ",  1,      1,      0,      0},
3771         {"PRC_PAR0"                    ,        0,      1,      193,    "R/W1C",        0,      0,      0ull,   0ull},
3772         {"PRC_PAR1"                    ,        1,      1,      193,    "R/W1C",        0,      0,      0ull,   0ull},
3773         {"PRC_PAR2"                    ,        2,      1,      193,    "R/W1C",        0,      0,      0ull,   0ull},
3774         {"PRC_PAR3"                    ,        3,      1,      193,    "R/W1C",        0,      0,      0ull,   0ull},
3775         {"BP_SUB"                      ,        4,      1,      193,    "R/W1C",        0,      0,      0ull,   0ull},
3776         {"RESERVED_5_63"               ,        5,      59,     193,    "RAZ",  1,      1,      0,      0},
3777         {"SKIP_SZ"                     ,        0,      6,      194,    "R/W",  0,      0,      0ull,   0ull},
3778         {"RESERVED_6_63"               ,        6,      58,     194,    "RAZ",  1,      1,      0,      0},
3779         {"MB_SIZE"                     ,        0,      12,     195,    "R/W",  0,      0,      32ull,  32ull},
3780         {"RESERVED_12_63"              ,        12,     52,     195,    "RAZ",  1,      1,      0,      0},
3781         {"PAGE_CNT"                    ,        0,      17,     196,    "R/W",  0,      0,      0ull,   0ull},
3782         {"BP_ENB"                      ,        17,     1,      196,    "R/W",  0,      0,      0ull,   0ull},
3783         {"RESERVED_18_63"              ,        18,     46,     196,    "RAZ",  1,      1,      0,      0},
3784         {"CNT_VAL"                     ,        0,      25,     197,    "RO",   0,      1,      0ull,   0},
3785         {"RESERVED_25_63"              ,        25,     39,     197,    "RAZ",  1,      1,      0,      0},
3786         {"WQE_PCNT"                    ,        0,      7,      198,    "RO",   0,      0,      0ull,   0ull},
3787         {"PKT_PCNT"                    ,        7,      7,      198,    "RO",   0,      0,      0ull,   0ull},
3788         {"PFIF_CNT"                    ,        14,     3,      198,    "RO",   0,      0,      0ull,   0ull},
3789         {"WQEV_CNT"                    ,        17,     1,      198,    "RO",   0,      0,      0ull,   0ull},
3790         {"PKTV_CNT"                    ,        18,     1,      198,    "RO",   0,      0,      0ull,   0ull},
3791         {"RESERVED_19_63"              ,        19,     45,     198,    "RAZ",  1,      1,      0,      0},
3792         {"PASS"                        ,        0,      32,     199,    "R/W",  0,      1,      0ull,   0},
3793         {"DROP"                        ,        32,     32,     199,    "R/W",  0,      1,      0ull,   0},
3794         {"Q0_PCNT"                     ,        0,      32,     200,    "RO",   0,      0,      0ull,   0ull},
3795         {"RESERVED_32_63"              ,        32,     32,     200,    "RAZ",  1,      1,      0,      0},
3796         {"PRT_ENB"                     ,        0,      36,     201,    "R/W",  0,      0,      0ull,   0ull},
3797         {"AVG_DLY"                     ,        36,     14,     201,    "R/W",  0,      1,      0ull,   0},
3798         {"PRB_DLY"                     ,        50,     14,     201,    "R/W",  0,      0,      0ull,   0ull},
3799         {"PRB_CON"                     ,        0,      32,     202,    "R/W",  0,      1,      0ull,   0},
3800         {"AVG_CON"                     ,        32,     8,      202,    "R/W",  0,      1,      0ull,   0},
3801         {"NEW_CON"                     ,        40,     8,      202,    "R/W",  0,      1,      0ull,   0},
3802         {"USE_PCNT"                    ,        48,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
3803         {"RESERVED_49_63"              ,        49,     15,     202,    "RAZ",  1,      1,      0,      0},
3804         {"PAGE_CNT"                    ,        0,      25,     203,    "R/W",  1,      0,      0,      0ull},
3805         {"PORT"                        ,        25,     6,      203,    "R/W",  1,      0,      0,      0ull},
3806         {"RESERVED_31_63"              ,        31,     33,     203,    "RAZ",  1,      1,      0,      0},
3807         {"PORT_BIT"                    ,        0,      32,     204,    "R/W",  0,      0,      4294967295ull,  4294967295ull},
3808         {"RESERVED_32_63"              ,        32,     32,     204,    "RAZ",  1,      1,      0,      0},
3809         {"WQE_POOL"                    ,        0,      3,      205,    "R/W",  0,      0,      1ull,   1ull},
3810         {"RESERVED_3_63"               ,        3,      61,     205,    "RAZ",  1,      1,      0,      0},
3811         {"MEM0"                        ,        0,      1,      206,    "RO",   0,      0,      0ull,   0ull},
3812         {"MEM1"                        ,        1,      1,      206,    "RO",   0,      0,      0ull,   0ull},
3813         {"RRC"                         ,        2,      1,      206,    "RO",   0,      0,      0ull,   0ull},
3814         {"RESERVED_3_63"               ,        3,      61,     206,    "RAZ",  1,      1,      0,      0},
3815         {"MEM0_ERR"                    ,        0,      7,      207,    "R/W",  0,      0,      0ull,   0ull},
3816         {"MEM1_ERR"                    ,        7,      7,      207,    "R/W",  0,      0,      0ull,   0ull},
3817         {"RESERVED_14_63"              ,        14,     50,     207,    "RAZ",  1,      1,      0,      0},
3818         {"KED0_SBE"                    ,        0,      1,      208,    "R/W",  0,      0,      0ull,   0ull},
3819         {"KED0_DBE"                    ,        1,      1,      208,    "R/W",  0,      0,      0ull,   0ull},
3820         {"KED1_SBE"                    ,        2,      1,      208,    "R/W",  0,      0,      0ull,   0ull},
3821         {"KED1_DBE"                    ,        3,      1,      208,    "R/W",  0,      0,      0ull,   0ull},
3822         {"RESERVED_4_63"               ,        4,      60,     208,    "RAZ",  1,      1,      0,      0},
3823         {"KED0_SBE"                    ,        0,      1,      209,    "R/W1C",        0,      0,      0ull,   0ull},
3824         {"KED0_DBE"                    ,        1,      1,      209,    "R/W1C",        0,      0,      0ull,   0ull},
3825         {"KED1_SBE"                    ,        2,      1,      209,    "R/W1C",        0,      0,      0ull,   0ull},
3826         {"KED1_DBE"                    ,        3,      1,      209,    "R/W1C",        0,      0,      0ull,   0ull},
3827         {"RESERVED_4_63"               ,        4,      60,     209,    "RAZ",  1,      1,      0,      0},
3828         {"WLB_DAT"                     ,        0,      4,      210,    "RO",   0,      0,      0ull,   0ull},
3829         {"STIN_MSK"                    ,        4,      1,      210,    "RO",   0,      0,      0ull,   0ull},
3830         {"DT"                          ,        5,      1,      210,    "RO",   0,      0,      0ull,   0ull},
3831         {"DTCNT"                       ,        6,      13,     210,    "RO",   0,      0,      0ull,   0ull},
3832         {"RESERVED_19_63"              ,        19,     45,     210,    "RAZ",  0,      0,      0ull,   0ull},
3833         {"L2T"                         ,        0,      9,      211,    "RO",   0,      0,      0ull,   0ull},
3834         {"VAB_VWCF"                    ,        9,      1,      211,    "RO",   0,      0,      0ull,   0ull},
3835         {"LRF"                         ,        10,     2,      211,    "RO",   0,      0,      0ull,   0ull},
3836         {"VWDF"                        ,        12,     4,      211,    "RO",   0,      0,      0ull,   0ull},
3837         {"RESERVED_16_63"              ,        16,     48,     211,    "RAZ",  0,      0,      0ull,   0ull},
3838         {"XRDDAT"                      ,        0,      1,      212,    "RO",   0,      0,      0ull,   0ull},
3839         {"XRDMSK"                      ,        1,      1,      212,    "RO",   0,      0,      0ull,   0ull},
3840         {"PICBST"                      ,        2,      1,      212,    "RO",   0,      0,      0ull,   0ull},
3841         {"IPCBST"                      ,        3,      1,      212,    "RO",   0,      0,      0ull,   0ull},
3842         {"RHDF"                        ,        4,      4,      212,    "RO",   0,      0,      0ull,   0ull},
3843         {"RMDF"                        ,        8,      4,      212,    "RO",   0,      0,      0ull,   0ull},
3844         {"MRB"                         ,        12,     4,      212,    "RO",   0,      0,      0ull,   0ull},
3845         {"RESERVED_16_63"              ,        16,     48,     212,    "RAZ",  0,      0,      0ull,   0ull},
3846         {"LRF_ARB_MODE"                ,        0,      1,      213,    "R/W",  0,      0,      1ull,   1ull},
3847         {"RFB_ARB_MODE"                ,        1,      1,      213,    "R/W",  0,      0,      1ull,   1ull},
3848         {"RSP_ARB_MODE"                ,        2,      1,      213,    "R/W",  0,      0,      1ull,   1ull},
3849         {"MWF_CRD"                     ,        3,      4,      213,    "R/W",  0,      0,      2ull,   2ull},
3850         {"IDXALIAS"                    ,        7,      1,      213,    "R/W",  0,      0,      0ull,   1ull},
3851         {"FPEN"                        ,        8,      1,      213,    "R/W",  0,      0,      0ull,   0ull},
3852         {"FPEMPTY"                     ,        9,      1,      213,    "R/W",  0,      0,      0ull,   0ull},
3853         {"FPEXP"                       ,        10,     4,      213,    "R/W",  0,      0,      0ull,   0ull},
3854         {"RESERVED_14_63"              ,        14,     50,     213,    "RAZ",  1,      1,      0,      0},
3855         {"L2T"                         ,        0,      1,      214,    "R/W",  0,      0,      0ull,   0ull},
3856         {"L2D"                         ,        1,      1,      214,    "R/W",  0,      0,      0ull,   0ull},
3857         {"FINV"                        ,        2,      1,      214,    "R/W",  0,      0,      0ull,   0ull},
3858         {"SET"                         ,        3,      3,      214,    "R/W",  0,      0,      0ull,   0ull},
3859         {"PPNUM"                       ,        6,      4,      214,    "R/W",  0,      0,      0ull,   0ull},
3860         {"LFB_DMP"                     ,        10,     1,      214,    "R/W",  0,      0,      0ull,   0ull},
3861         {"LFB_ENUM"                    ,        11,     4,      214,    "R/W",  0,      0,      0ull,   0ull},
3862         {"RESERVED_15_63"              ,        15,     49,     214,    "RAZ",  0,      0,      0ull,   0ull},
3863         {"DT_TAG"                      ,        0,      29,     215,    "RO",   0,      0,      0ull,   0ull},
3864         {"DT_VLD"                      ,        29,     1,      215,    "RO",   0,      0,      0ull,   0ull},
3865         {"RESERVED_30_30"              ,        30,     1,      215,    "RAZ",  0,      0,      0ull,   0ull},
3866         {"DTENA"                       ,        31,     1,      215,    "R/W",  0,      0,      0ull,   0ull},
3867         {"RESERVED_32_63"              ,        32,     32,     215,    "RAZ",  0,      0,      0ull,   0ull},
3868         {"LCK_ENA"                     ,        0,      1,      216,    "R/W",  0,      0,      0ull,   0ull},
3869         {"RESERVED_1_3"                ,        1,      3,      216,    "RAZ",  0,      0,      0ull,   0ull},
3870         {"LCK_BASE"                    ,        4,      27,     216,    "R/W",  0,      0,      0ull,   0ull},
3871         {"RESERVED_31_63"              ,        31,     33,     216,    "RAZ",  0,      0,      0ull,   0ull},
3872         {"LCK_OFFSET"                  ,        0,      10,     217,    "R/W",  0,      0,      0ull,   0ull},
3873         {"RESERVED_10_63"              ,        10,     54,     217,    "RAZ",  0,      0,      0ull,   0ull},
3874         {"VLD"                         ,        0,      1,      218,    "RO",   0,      0,      0ull,   0ull},
3875         {"CMD"                         ,        1,      4,      218,    "RO",   0,      0,      0ull,   0ull},
3876         {"SID"                         ,        5,      9,      218,    "RO",   0,      0,      0ull,   0ull},
3877         {"VABNUM"                      ,        14,     4,      218,    "RO",   0,      0,      0ull,   0ull},
3878         {"SET"                         ,        18,     3,      218,    "RO",   0,      0,      0ull,   0ull},
3879         {"IHD"                         ,        21,     1,      218,    "RO",   0,      0,      0ull,   0ull},
3880         {"ITL"                         ,        22,     1,      218,    "RO",   0,      0,      0ull,   0ull},
3881         {"INXT"                        ,        23,     4,      218,    "RO",   0,      0,      0ull,   0ull},
3882         {"VAM"                         ,        27,     1,      218,    "RO",   0,      0,      0ull,   0ull},
3883         {"STCFL"                       ,        28,     1,      218,    "RO",   0,      0,      0ull,   0ull},
3884         {"STINV"                       ,        29,     1,      218,    "RO",   0,      0,      0ull,   0ull},
3885         {"STPND"                       ,        30,     1,      218,    "RO",   0,      0,      0ull,   0ull},
3886         {"STCPND"                      ,        31,     1,      218,    "RO",   0,      0,      0ull,   0ull},
3887         {"RESERVED_32_63"              ,        32,     32,     218,    "RAZ",  0,      0,      0ull,   0ull},
3888         {"VLD"                         ,        0,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3889         {"WTPRB"                       ,        1,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3890         {"PRBRTY"                      ,        2,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3891         {"WTMFL"                       ,        3,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3892         {"WTVTM"                       ,        4,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3893         {"WTSTRSC"                     ,        5,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3894         {"WTSTRSP"                     ,        6,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3895         {"WTSTDT"                      ,        7,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3896         {"WTRDA"                       ,        8,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3897         {"WTSTM"                       ,        9,      1,      219,    "RO",   0,      0,      0ull,   0ull},
3898         {"WTWRM"                       ,        10,     1,      219,    "RO",   0,      0,      0ull,   0ull},
3899         {"WTWHF"                       ,        11,     1,      219,    "RO",   0,      0,      0ull,   0ull},
3900         {"WTWHP"                       ,        12,     1,      219,    "RO",   0,      0,      0ull,   0ull},
3901         {"WTDQ"                        ,        13,     1,      219,    "RO",   0,      0,      0ull,   0ull},
3902         {"WTDW"                        ,        14,     1,      219,    "RO",   0,      0,      0ull,   0ull},
3903         {"WTRSP"                       ,        15,     1,      219,    "RO",   0,      0,      0ull,   0ull},
3904         {"BID"                         ,        16,     2,      219,    "RO",   0,      0,      0ull,   0ull},
3905         {"DSGOING"                     ,        18,     1,      219,    "RO",   0,      0,      0ull,   0ull},
3906         {"RESERVED_19_63"              ,        19,     45,     219,    "RAZ",  0,      0,      0ull,   0ull},
3907         {"LFB_IDX"                     ,        0,      10,     220,    "RO",   0,      0,      0ull,   0ull},
3908         {"LFB_TAG"                     ,        10,     17,     220,    "RO",   0,      0,      0ull,   0ull},
3909         {"RESERVED_27_63"              ,        27,     37,     220,    "RAZ",  0,      0,      0ull,   0ull},
3910         {"LFB_HWM"                     ,        0,      4,      221,    "R/W",  0,      0,      15ull,  15ull},
3911         {"STPARTDIS"                   ,        4,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
3912         {"RESERVED_5_63"               ,        5,      59,     221,    "RAZ",  0,      0,      0ull,   0ull},
3913         {"PFCNT0"                      ,        0,      36,     222,    "RO",   0,      0,      0ull,   0ull},
3914         {"RESERVED_36_63"              ,        36,     28,     222,    "RAZ",  0,      0,      0ull,   0ull},
3915         {"CNT0SEL"                     ,        0,      6,      223,    "R/W",  0,      0,      0ull,   0ull},
3916         {"CNT0CLR"                     ,        6,      1,      223,    "R/W",  0,      0,      0ull,   0ull},
3917         {"CNT0ENA"                     ,        7,      1,      223,    "R/W",  0,      0,      0ull,   0ull},
3918         {"CNT1SEL"                     ,        8,      6,      223,    "R/W",  0,      0,      0ull,   0ull},
3919         {"CNT1CLR"                     ,        14,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3920         {"CNT1ENA"                     ,        15,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3921         {"CNT2SEL"                     ,        16,     6,      223,    "R/W",  0,      0,      0ull,   0ull},
3922         {"CNT2CLR"                     ,        22,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3923         {"CNT2ENA"                     ,        23,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3924         {"CNT3SEL"                     ,        24,     6,      223,    "R/W",  0,      0,      0ull,   0ull},
3925         {"CNT3CLR"                     ,        30,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3926         {"CNT3ENA"                     ,        31,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3927         {"CNT0RDCLR"                   ,        32,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3928         {"CNT1RDCLR"                   ,        33,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3929         {"CNT2RDCLR"                   ,        34,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3930         {"CNT3RDCLR"                   ,        35,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
3931         {"RESERVED_36_63"              ,        36,     28,     223,    "RAZ",  0,      0,      0ull,   0ull},
3932         {"UMSK0"                       ,        0,      8,      224,    "R/W",  0,      0,      0ull,   0ull},
3933         {"UMSK1"                       ,        8,      8,      224,    "R/W",  0,      0,      0ull,   0ull},
3934         {"UMSK2"                       ,        16,     8,      224,    "R/W",  0,      0,      0ull,   0ull},
3935         {"UMSK3"                       ,        24,     8,      224,    "R/W",  0,      0,      0ull,   0ull},
3936         {"RESERVED_32_63"              ,        32,     32,     224,    "RAZ",  0,      0,      0ull,   0ull},
3937         {"UMSK4"                       ,        0,      8,      225,    "R/W",  0,      0,      0ull,   0ull},
3938         {"UMSK5"                       ,        8,      8,      225,    "R/W",  0,      0,      0ull,   0ull},
3939         {"UMSK6"                       ,        16,     8,      225,    "R/W",  0,      0,      0ull,   0ull},
3940         {"UMSK7"                       ,        24,     8,      225,    "R/W",  0,      0,      0ull,   0ull},
3941         {"RESERVED_32_63"              ,        32,     32,     225,    "RAZ",  0,      0,      0ull,   0ull},
3942         {"UMSK8"                       ,        0,      8,      226,    "R/W",  0,      0,      0ull,   0ull},
3943         {"UMSK9"                       ,        8,      8,      226,    "R/W",  0,      0,      0ull,   0ull},
3944         {"UMSK10"                      ,        16,     8,      226,    "R/W",  0,      0,      0ull,   0ull},
3945         {"UMSK11"                      ,        24,     8,      226,    "R/W",  0,      0,      0ull,   0ull},
3946         {"RESERVED_32_63"              ,        32,     32,     226,    "RAZ",  0,      0,      0ull,   0ull},
3947         {"UMSK12"                      ,        0,      8,      227,    "R/W",  0,      0,      0ull,   0ull},
3948         {"UMSK13"                      ,        8,      8,      227,    "R/W",  0,      0,      0ull,   0ull},
3949         {"UMSK14"                      ,        16,     8,      227,    "R/W",  0,      0,      0ull,   0ull},
3950         {"UMSK15"                      ,        24,     8,      227,    "R/W",  0,      0,      0ull,   0ull},
3951         {"RESERVED_32_63"              ,        32,     32,     227,    "RAZ",  0,      0,      0ull,   0ull},
3952         {"UMSKIOB"                     ,        0,      8,      228,    "R/W",  0,      0,      0ull,   0ull},
3953         {"RESERVED_8_63"               ,        8,      56,     228,    "RAZ",  0,      0,      0ull,   0ull},
3954         {"Q0STAT"                      ,        0,      34,     229,    "RO",   0,      0,      0ull,   0ull},
3955         {"FTL"                         ,        34,     1,      229,    "RO",   0,      0,      0ull,   0ull},
3956         {"RESERVED_35_63"              ,        35,     29,     229,    "RAZ",  0,      0,      0ull,   0ull},
3957         {"Q1STAT"                      ,        0,      34,     230,    "RO",   0,      0,      0ull,   0ull},
3958         {"RESERVED_34_63"              ,        34,     30,     230,    "RAZ",  0,      0,      0ull,   0ull},
3959         {"Q2STAT"                      ,        0,      34,     231,    "RO",   0,      0,      0ull,   0ull},
3960         {"RESERVED_34_63"              ,        34,     30,     231,    "RAZ",  0,      0,      0ull,   0ull},
3961         {"Q3STAT"                      ,        0,      34,     232,    "RO",   0,      0,      0ull,   0ull},
3962         {"RESERVED_34_63"              ,        34,     30,     232,    "RAZ",  0,      0,      0ull,   0ull},
3963         {"ECC_ENA"                     ,        0,      1,      233,    "R/W",  0,      0,      0ull,   1ull},
3964         {"SEC_INTENA"                  ,        1,      1,      233,    "R/W",  0,      0,      0ull,   1ull},
3965         {"DED_INTENA"                  ,        2,      1,      233,    "R/W",  0,      0,      0ull,   1ull},
3966         {"SEC_ERR"                     ,        3,      1,      233,    "R/W1C",        0,      0,      0ull,   0ull},
3967         {"DED_ERR"                     ,        4,      1,      233,    "R/W1C",        0,      0,      0ull,   0ull},
3968         {"BMHCLSEL"                    ,        5,      1,      233,    "R/W",  0,      0,      0ull,   0ull},
3969         {"RESERVED_6_63"               ,        6,      58,     233,    "RAZ",  0,      0,      0ull,   0ull},
3970         {"FADR"                        ,        0,      11,     234,    "RO",   0,      0,      0ull,   0ull},
3971         {"FSET"                        ,        11,     3,      234,    "RO",   0,      0,      0ull,   0ull},
3972         {"FOWMSK"                      ,        14,     4,      234,    "RO",   0,      0,      0ull,   0ull},
3973         {"RESERVED_18_63"              ,        18,     46,     234,    "RAZ",  0,      0,      0ull,   0ull},
3974         {"FSYN_OW0"                    ,        0,      10,     235,    "RO",   0,      0,      0ull,   0ull},
3975         {"FSYN_OW1"                    ,        10,     10,     235,    "RO",   0,      0,      0ull,   0ull},
3976         {"RESERVED_20_63"              ,        20,     44,     235,    "RAZ",  0,      0,      0ull,   0ull},
3977         {"FSYN_OW2"                    ,        0,      10,     236,    "RO",   0,      0,      0ull,   0ull},
3978         {"FSYN_OW3"                    ,        10,     10,     236,    "RO",   0,      0,      0ull,   0ull},
3979         {"RESERVED_20_63"              ,        20,     44,     236,    "RAZ",  0,      0,      0ull,   0ull},
3980         {"Q0FUS"                       ,        0,      34,     237,    "RO",   0,      0,      0ull,   0ull},
3981         {"RESERVED_34_63"              ,        34,     30,     237,    "RAZ",  0,      0,      0ull,   0ull},
3982         {"Q1FUS"                       ,        0,      34,     238,    "RO",   0,      0,      0ull,   0ull},
3983         {"RESERVED_34_63"              ,        34,     30,     238,    "RAZ",  0,      0,      0ull,   0ull},
3984         {"Q2FUS"                       ,        0,      34,     239,    "RO",   0,      0,      0ull,   0ull},
3985         {"RESERVED_34_63"              ,        34,     30,     239,    "RAZ",  0,      0,      0ull,   0ull},
3986         {"Q3FUS"                       ,        0,      34,     240,    "RO",   0,      0,      0ull,   0ull},
3987         {"CRIP_512K"                   ,        34,     1,      240,    "RO",   0,      0,      0ull,   0ull},
3988         {"CRIP_256K"                   ,        35,     1,      240,    "RO",   0,      0,      0ull,   0ull},
3989         {"RESERVED_36_63"              ,        36,     28,     240,    "RAZ",  0,      0,      0ull,   0ull},
3990         {"ECC_ENA"                     ,        0,      1,      241,    "R/W",  0,      0,      0ull,   1ull},
3991         {"SEC_INTENA"                  ,        1,      1,      241,    "R/W",  0,      0,      0ull,   1ull},
3992         {"DED_INTENA"                  ,        2,      1,      241,    "R/W",  0,      0,      0ull,   1ull},
3993         {"SEC_ERR"                     ,        3,      1,      241,    "R/W1C",        0,      0,      0ull,   0ull},
3994         {"DED_ERR"                     ,        4,      1,      241,    "R/W1C",        0,      0,      0ull,   0ull},
3995         {"FSYN"                        ,        5,      6,      241,    "RO",   0,      0,      0ull,   0ull},
3996         {"FADR"                        ,        11,     10,     241,    "RO",   0,      0,      0ull,   0ull},
3997         {"FSET"                        ,        21,     3,      241,    "RO",   0,      0,      0ull,   0ull},
3998         {"LCKERR"                      ,        24,     1,      241,    "R/W1C",        0,      0,      0ull,   0ull},
3999         {"LCK_INTENA"                  ,        25,     1,      241,    "R/W",  0,      0,      0ull,   1ull},
4000         {"LCKERR2"                     ,        26,     1,      241,    "R/W1C",        0,      0,      0ull,   0ull},
4001         {"LCK_INTENA2"                 ,        27,     1,      241,    "R/W",  0,      0,      0ull,   1ull},
4002         {"RESERVED_28_63"              ,        28,     36,     241,    "RAZ",  0,      0,      0ull,   0ull},
4003         {"RATE"                        ,        0,      8,      242,    "R/W",  0,      0,      4ull,   4ull},
4004         {"RESERVED_8_63"               ,        8,      56,     242,    "RAZ",  1,      1,      0,      0},
4005         {"PHASE"                       ,        0,      7,      243,    "R/W",  0,      0,      4ull,   4ull},
4006         {"RESERVED_7_63"               ,        7,      57,     243,    "RAZ",  1,      1,      0,      0},
4007         {"RATE"                        ,        0,      16,     244,    "R/W",  0,      0,      0ull,   0ull},
4008         {"RESERVED_16_63"              ,        16,     48,     244,    "RAZ",  1,      1,      0,      0},
4009         {"DBG_EN"                      ,        0,      1,      245,    "R/W",  0,      0,      0ull,   0ull},
4010         {"RESERVED_1_63"               ,        1,      63,     245,    "RAZ",  1,      1,      0,      0},
4011         {"EN"                          ,        0,      1,      246,    "R/W",  0,      0,      0ull,   1ull},
4012         {"RESERVED_1_63"               ,        1,      63,     246,    "RAZ",  1,      1,      0,      0},
4013         {"POLARITY"                    ,        0,      1,      247,    "R/W",  0,      0,      0ull,   0ull},
4014         {"RESERVED_1_63"               ,        1,      63,     247,    "RAZ",  1,      1,      0,      0},
4015         {"PRT_EN"                      ,        0,      8,      248,    "R/W",  0,      1,      0ull,   0},
4016         {"RESERVED_8_63"               ,        8,      56,     248,    "RAZ",  1,      1,      0,      0},
4017         {"FORMAT"                      ,        0,      4,      249,    "R/W",  0,      1,      0ull,   0},
4018         {"RESERVED_4_63"               ,        4,      60,     249,    "RAZ",  1,      1,      0,      0},
4019         {"STATUS"                      ,        0,      6,      250,    "R/W",  0,      0,      0ull,   0ull},
4020         {"RESERVED_6_63"               ,        6,      58,     250,    "RAZ",  1,      1,      0,      0},
4021         {"CNT"                         ,        0,      6,      251,    "R/W",  0,      0,      0ull,   0ull},
4022         {"RESERVED_6_63"               ,        6,      58,     251,    "RAZ",  1,      1,      0,      0},
4023         {"DAT"                         ,        0,      32,     252,    "R/W",  0,      1,      0ull,   0},
4024         {"RESERVED_32_63"              ,        32,     32,     252,    "RAZ",  1,      1,      0,      0},
4025         {"CLR"                         ,        0,      32,     253,    "WO",   0,      1,      0ull,   0},
4026         {"RESERVED_32_63"              ,        32,     32,     253,    "RAZ",  1,      1,      0,      0},
4027         {"SET"                         ,        0,      32,     254,    "WO",   0,      1,      0ull,   0},
4028         {"RESERVED_32_63"              ,        32,     32,     254,    "RAZ",  1,      1,      0,      0},
4029         {"PCTL_DAT"                    ,        0,      4,      255,    "R/W",  0,      1,      0ull,   0},
4030         {"PCTL_CMD"                    ,        4,      4,      255,    "R/W",  0,      1,      0ull,   0},
4031         {"PCTL_CLK"                    ,        8,      4,      255,    "R/W",  0,      1,      0ull,   0},
4032         {"PCTL_CSR"                    ,        12,     4,      255,    "R/W",  0,      1,      15ull,  0},
4033         {"NCTL_DAT"                    ,        16,     4,      255,    "R/W",  0,      1,      0ull,   0},
4034         {"NCTL_CMD"                    ,        20,     4,      255,    "R/W",  0,      1,      0ull,   0},
4035         {"NCTL_CLK"                    ,        24,     4,      255,    "R/W",  0,      1,      0ull,   0},
4036         {"NCTL_CSR"                    ,        28,     4,      255,    "R/W",  0,      1,      15ull,  0},
4037         {"RESERVED_32_63"              ,        32,     32,     255,    "RAZ",  0,      0,      0ull,   0ull},
4038         {"DIC"                         ,        0,      2,      256,    "R/W",  0,      0,      0ull,   0ull},
4039         {"QS_DIC"                      ,        2,      2,      256,    "R/W",  0,      0,      2ull,   2ull},
4040         {"TSKW"                        ,        4,      2,      256,    "R/W",  0,      0,      0ull,   1ull},
4041         {"SIL_LAT"                     ,        6,      2,      256,    "R/W",  0,      0,      1ull,   1ull},
4042         {"BPRCH"                       ,        8,      1,      256,    "R/W",  0,      1,      0ull,   0},
4043         {"FPRCH2"                      ,        9,      1,      256,    "R/W",  0,      0,      0ull,   1ull},
4044         {"MODE128B"                    ,        10,     1,      256,    "R/W",  0,      0,      1ull,   1ull},
4045         {"SET_ZERO"                    ,        11,     1,      256,    "R/W",  0,      0,      0ull,   0ull},
4046         {"INORDER_MRF"                 ,        12,     1,      256,    "R/W",  0,      0,      0ull,   0ull},
4047         {"INORDER_MWF"                 ,        13,     1,      256,    "R/W",  0,      0,      0ull,   0ull},
4048         {"R2R_SLOT"                    ,        14,     1,      256,    "R/W",  0,      0,      0ull,   0ull},
4049         {"RDIMM_ENA"                   ,        15,     1,      256,    "R/W",  0,      1,      0ull,   0},
4050         {"RESERVED_16_17"              ,        16,     2,      256,    "RAZ",  0,      0,      0ull,   0ull},
4051         {"MAX_WRITE_BATCH"             ,        18,     4,      256,    "R/W",  0,      0,      8ull,   8ull},
4052         {"XOR_BANK"                    ,        22,     1,      256,    "R/W",  0,      0,      0ull,   1ull},
4053         {"SLOW_SCF"                    ,        23,     1,      256,    "R/W",  0,      0,      0ull,   0ull},
4054         {"DDR__PCTL"                   ,        24,     4,      256,    "RO",   1,      1,      0,      0},
4055         {"DDR__NCTL"                   ,        28,     4,      256,    "RO",   1,      1,      0,      0},
4056         {"RESERVED_32_63"              ,        32,     32,     256,    "RAZ",  1,      1,      0,      0},
4057         {"DCLKCNT_HI"                  ,        0,      32,     257,    "RO",   0,      0,      0ull,   0ull},
4058         {"RESERVED_32_63"              ,        32,     32,     257,    "RAZ",  1,      1,      0,      0},
4059         {"DCLKCNT_LO"                  ,        0,      32,     258,    "RO",   0,      0,      0ull,   0ull},
4060         {"RESERVED_32_63"              ,        32,     32,     258,    "RAZ",  1,      1,      0,      0},
4061         {"DDR2"                        ,        0,      1,      259,    "R/W",  0,      0,      1ull,   1ull},
4062         {"RDQS"                        ,        1,      1,      259,    "R/W",  0,      0,      0ull,   0ull},
4063         {"DLL90_BYP"                   ,        2,      1,      259,    "R/W",  0,      0,      0ull,   0ull},
4064         {"DLL90_VLU"                   ,        3,      5,      259,    "R/W",  0,      1,      0ull,   0},
4065         {"QDLL_ENA"                    ,        8,      1,      259,    "R/W",  0,      0,      0ull,   0ull},
4066         {"ODT_ENA"                     ,        9,      1,      259,    "R/W",  0,      0,      0ull,   0ull},
4067         {"DDR2T"                       ,        10,     1,      259,    "R/W",  0,      1,      0ull,   0},
4068         {"CRIP_MODE"                   ,        11,     1,      259,    "R/W",  0,      0,      0ull,   0ull},
4069         {"TFAW"                        ,        12,     5,      259,    "R/W",  0,      0,      0ull,   9ull},
4070         {"DDR_EOF"                     ,        17,     4,      259,    "R/W",  0,      0,      2ull,   2ull},
4071         {"SILO_HC"                     ,        21,     1,      259,    "R/W",  0,      1,      1ull,   0},
4072         {"TWR"                         ,        22,     3,      259,    "R/W",  0,      0,      3ull,   1ull},
4073         {"BWCNT"                       ,        25,     1,      259,    "R/W",  0,      0,      0ull,   0ull},
4074         {"POCAS"                       ,        26,     1,      259,    "R/W",  0,      0,      0ull,   0ull},
4075         {"ADDLAT"                      ,        27,     3,      259,    "R/W",  0,      0,      0ull,   0ull},
4076         {"BURST8"                      ,        30,     1,      259,    "R/W",  0,      0,      0ull,   1ull},
4077         {"BANK8"                       ,        31,     1,      259,    "R/W",  0,      1,      0ull,   0},
4078         {"RESERVED_32_63"              ,        32,     32,     259,    "RAZ",  0,      0,      0ull,   0ull},
4079         {"MRDSYN0"                     ,        0,      8,      260,    "RO",   0,      0,      0ull,   0ull},
4080         {"MRDSYN1"                     ,        8,      8,      260,    "RO",   0,      0,      0ull,   0ull},
4081         {"MRDSYN2"                     ,        16,     8,      260,    "RO",   0,      0,      0ull,   0ull},
4082         {"MRDSYN3"                     ,        24,     8,      260,    "RO",   0,      0,      0ull,   0ull},
4083         {"RESERVED_32_63"              ,        32,     32,     260,    "RAZ",  1,      1,      0,      0},
4084         {"FCOL"                        ,        0,      12,     261,    "RO",   0,      0,      0ull,   0ull},
4085         {"FROW"                        ,        12,     14,     261,    "RO",   0,      0,      0ull,   0ull},
4086         {"FBANK"                       ,        26,     3,      261,    "RO",   0,      0,      0ull,   0ull},
4087         {"FBUNK"                       ,        29,     1,      261,    "RO",   0,      0,      0ull,   0ull},
4088         {"FDIMM"                       ,        30,     2,      261,    "RO",   0,      0,      0ull,   0ull},
4089         {"RESERVED_32_63"              ,        32,     32,     261,    "RAZ",  1,      1,      0,      0},
4090         {"IFBCNT_HI"                   ,        0,      32,     262,    "RO",   0,      0,      0ull,   0ull},
4091         {"RESERVED_32_63"              ,        32,     32,     262,    "RAZ",  1,      1,      0,      0},
4092         {"IFBCNT_LO"                   ,        0,      32,     263,    "RO",   0,      0,      0ull,   0ull},
4093         {"RESERVED_32_63"              ,        32,     32,     263,    "RAZ",  1,      1,      0,      0},
4094         {"INIT_START"                  ,        0,      1,      264,    "R/W",  0,      0,      0ull,   0ull},
4095         {"ECC_ENA"                     ,        1,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
4096         {"ROW_LSB"                     ,        2,      3,      264,    "R/W",  0,      1,      3ull,   0},
4097         {"PBANK_LSB"                   ,        5,      4,      264,    "R/W",  0,      1,      5ull,   0},
4098         {"REF_INT"                     ,        9,      6,      264,    "R/W",  0,      0,      1ull,   2ull},
4099         {"TCL"                         ,        15,     4,      264,    "R/W",  0,      1,      3ull,   0},
4100         {"INTR_SEC_ENA"                ,        19,     1,      264,    "R/W",  0,      0,      0ull,   1ull},
4101         {"INTR_DED_ENA"                ,        20,     1,      264,    "R/W",  0,      0,      0ull,   1ull},
4102         {"SEC_ERR"                     ,        21,     4,      264,    "R/W1C",        0,      0,      0ull,   0ull},
4103         {"DED_ERR"                     ,        25,     4,      264,    "R/W1C",        0,      0,      0ull,   0ull},
4104         {"BUNK_ENA"                    ,        29,     1,      264,    "R/W",  0,      1,      0ull,   0},
4105         {"SILO_QC"                     ,        30,     1,      264,    "R/W",  0,      1,      0ull,   0},
4106         {"RESET"                       ,        31,     1,      264,    "RAZ",  1,      1,      0,      0},
4107         {"RESERVED_32_63"              ,        32,     32,     264,    "RAZ",  1,      1,      0,      0},
4108         {"TRAS"                        ,        0,      5,      265,    "R/W",  0,      0,      12ull,  12ull},
4109         {"TRCD"                        ,        5,      4,      265,    "R/W",  0,      0,      4ull,   4ull},
4110         {"TWTR"                        ,        9,      4,      265,    "R/W",  0,      0,      2ull,   2ull},
4111         {"TRP"                         ,        13,     4,      265,    "R/W",  0,      0,      5ull,   4ull},
4112         {"TRFC"                        ,        17,     5,      265,    "R/W",  0,      0,      6ull,   7ull},
4113         {"TMRD"                        ,        22,     3,      265,    "R/W",  0,      0,      2ull,   2ull},
4114         {"CASLAT"                      ,        25,     3,      265,    "R/W",  0,      0,      4ull,   4ull},
4115         {"TRRD"                        ,        28,     3,      265,    "R/W",  0,      0,      2ull,   2ull},
4116         {"RESERVED_31_63"              ,        31,     33,     265,    "RAZ",  1,      1,      0,      0},
4117         {"OPSCNT_HI"                   ,        0,      32,     266,    "RO",   0,      0,      0ull,   0ull},
4118         {"RESERVED_32_63"              ,        32,     32,     266,    "RAZ",  1,      1,      0,      0},
4119         {"OPSCNT_LO"                   ,        0,      32,     267,    "RO",   0,      0,      0ull,   0ull},
4120         {"RESERVED_32_63"              ,        32,     32,     267,    "RAZ",  1,      1,      0,      0},
4121         {"BWCTL"                       ,        0,      4,      268,    "R/W",  0,      0,      0ull,   0ull},
4122         {"BWUPD"                       ,        4,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
4123         {"RESERVED_5_63"               ,        5,      59,     268,    "RAZ",  1,      1,      0,      0},
4124         {"RODT_LO0"                    ,        0,      4,      269,    "R/W",  0,      0,      15ull,  15ull},
4125         {"RODT_LO1"                    ,        4,      4,      269,    "R/W",  0,      0,      15ull,  15ull},
4126         {"RODT_LO2"                    ,        8,      4,      269,    "R/W",  0,      0,      15ull,  15ull},
4127         {"RODT_LO3"                    ,        12,     4,      269,    "R/W",  0,      0,      15ull,  15ull},
4128         {"RODT_HI0"                    ,        16,     4,      269,    "R/W",  0,      0,      15ull,  15ull},
4129         {"RODT_HI1"                    ,        20,     4,      269,    "R/W",  0,      0,      15ull,  15ull},
4130         {"RODT_HI2"                    ,        24,     4,      269,    "R/W",  0,      0,      15ull,  15ull},
4131         {"RODT_HI3"                    ,        28,     4,      269,    "R/W",  0,      0,      15ull,  15ull},
4132         {"RESERVED_32_63"              ,        32,     32,     269,    "RAZ",  1,      1,      0,      0},
4133         {"WODT_LO0"                    ,        0,      4,      270,    "R/W",  0,      0,      15ull,  15ull},
4134         {"WODT_LO1"                    ,        4,      4,      270,    "R/W",  0,      0,      15ull,  15ull},
4135         {"WODT_LO2"                    ,        8,      4,      270,    "R/W",  0,      0,      15ull,  15ull},
4136         {"WODT_LO3"                    ,        12,     4,      270,    "R/W",  0,      0,      15ull,  15ull},
4137         {"WODT_HI0"                    ,        16,     4,      270,    "R/W",  0,      0,      15ull,  15ull},
4138         {"WODT_HI1"                    ,        20,     4,      270,    "R/W",  0,      0,      15ull,  15ull},
4139         {"WODT_HI2"                    ,        24,     4,      270,    "R/W",  0,      0,      15ull,  15ull},
4140         {"WODT_HI3"                    ,        28,     4,      270,    "R/W",  0,      0,      15ull,  15ull},
4141         {"RESERVED_32_63"              ,        32,     32,     270,    "RAZ",  1,      1,      0,      0},
4142         {"NCBI"                        ,        0,      1,      271,    "RO",   0,      0,      0ull,   0ull},
4143         {"LOC"                         ,        1,      1,      271,    "RO",   0,      0,      0ull,   0ull},
4144         {"NCBO_0"                      ,        2,      1,      271,    "RO",   0,      0,      0ull,   0ull},
4145         {"RESERVED_3_63"               ,        3,      61,     271,    "RAZ",  1,      1,      0,      0},
4146         {"ADR_ERR"                     ,        0,      1,      272,    "R/W1C",        0,      0,      0ull,   0ull},
4147         {"WAIT_ERR"                    ,        1,      1,      272,    "R/W1C",        0,      0,      0ull,   0ull},
4148         {"RESERVED_2_63"               ,        2,      62,     272,    "RAZ",  1,      1,      0,      0},
4149         {"ADR_INT"                     ,        0,      1,      273,    "R/W",  0,      1,      0ull,   0},
4150         {"WAIT_INT"                    ,        1,      1,      273,    "R/W",  0,      1,      0ull,   0},
4151         {"RESERVED_2_63"               ,        2,      62,     273,    "RAZ",  1,      1,      0,      0},
4152         {"RESERVED_0_2"                ,        0,      3,      274,    "RAZ",  1,      1,      0,      0},
4153         {"ADR"                         ,        3,      5,      274,    "R/W",  0,      1,      0ull,   0},
4154         {"RESERVED_8_63"               ,        8,      56,     274,    "RAZ",  1,      1,      0,      0},
4155         {"RESERVED_0_2"                ,        0,      3,      275,    "RAZ",  1,      1,      0,      0},
4156         {"BASE"                        ,        3,      25,     275,    "R/W",  0,      1,      0ull,   0},
4157         {"RESERVED_28_30"              ,        28,     3,      275,    "RAZ",  1,      1,      0,      0},
4158         {"EN"                          ,        31,     1,      275,    "R/W",  0,      1,      0ull,   0},
4159         {"RESERVED_32_63"              ,        32,     32,     275,    "RAZ",  1,      1,      0,      0},
4160         {"DATA"                        ,        0,      64,     276,    "R/W",  1,      1,      0,      0},
4161         {"BASE"                        ,        0,      16,     277,    "R/W",  0,      1,      0ull,   0},
4162         {"SIZE"                        ,        16,     12,     277,    "R/W",  0,      1,      0ull,   0},
4163         {"RESERVED_28_29"              ,        28,     2,      277,    "RAZ",  1,      1,      0,      0},
4164         {"ORBIT"                       ,        30,     1,      277,    "R/W",  0,      1,      0ull,   0},
4165         {"EN"                          ,        31,     1,      277,    "R/W",  0,      1,      0ull,   0},
4166         {"RESERVED_32_63"              ,        32,     32,     277,    "RAZ",  1,      1,      0,      0},
4167         {"ADR"                         ,        0,      6,      278,    "R/W",  0,      1,      63ull,  0},
4168         {"CE"                          ,        6,      6,      278,    "R/W",  0,      1,      63ull,  0},
4169         {"OE"                          ,        12,     6,      278,    "R/W",  0,      1,      63ull,  0},
4170         {"WE"                          ,        18,     6,      278,    "R/W",  0,      1,      63ull,  0},
4171         {"RD_HLD"                      ,        24,     6,      278,    "R/W",  0,      1,      63ull,  0},
4172         {"WR_HLD"                      ,        30,     6,      278,    "R/W",  0,      1,      63ull,  0},
4173         {"PAUSE"                       ,        36,     6,      278,    "R/W",  0,      1,      63ull,  0},
4174         {"WAIT"                        ,        42,     6,      278,    "R/W",  0,      1,      63ull,  0},
4175         {"PAGE"                        ,        48,     6,      278,    "R/W",  0,      1,      63ull,  0},
4176         {"RESERVED_54_59"              ,        54,     6,      278,    "RAZ",  1,      1,      0,      0},
4177         {"PAGES"                       ,        60,     2,      278,    "R/W",  0,      1,      0ull,   0},
4178         {"WAITM"                       ,        62,     1,      278,    "R/W",  0,      1,      0ull,   0},
4179         {"PAGEM"                       ,        63,     1,      278,    "R/W",  0,      1,      0ull,   0},
4180         {"FIF_THR"                     ,        0,      6,      279,    "R/W",  0,      0,      26ull,  26ull},
4181         {"RESERVED_6_7"                ,        6,      2,      279,    "RAZ",  1,      1,      0,      0},
4182         {"FIF_CNT"                     ,        8,      6,      279,    "RO",   0,      1,      0ull,   0},
4183         {"RESERVED_14_63"              ,        14,     50,     279,    "RAZ",  1,      1,      0,      0},
4184         {"MAN_INFO"                    ,        0,      32,     280,    "RO",   1,      1,      0,      0},
4185         {"RESERVED_32_63"              ,        32,     32,     280,    "RAZ",  1,      1,      0,      0},
4186         {"MAN_INFO"                    ,        0,      32,     281,    "RO",   1,      1,      0,      0},
4187         {"RESERVED_32_63"              ,        32,     32,     281,    "RAZ",  1,      1,      0,      0},
4188         {"PP_DIS"                      ,        0,      16,     282,    "RO",   1,      1,      0,      0},
4189         {"CHIP_ID"                     ,        16,     8,      282,    "RO",   1,      1,      0,      0},
4190         {"BIST_DIS"                    ,        24,     1,      282,    "RO",   1,      1,      0,      0},
4191         {"RST_SHT"                     ,        25,     1,      282,    "RO",   1,      1,      0,      0},
4192         {"NOCRYPTO"                    ,        26,     1,      282,    "RO",   1,      1,      0,      0},
4193         {"NOMUL"                       ,        27,     1,      282,    "RO",   1,      1,      0,      0},
4194         {"NODFA_CP2"                   ,        28,     1,      282,    "RO",   1,      1,      0,      0},
4195         {"RESERVED_29_63"              ,        29,     35,     282,    "RAZ",  1,      1,      0,      0},
4196         {"ICACHE"                      ,        0,      24,     283,    "RO",   1,      1,      0,      0},
4197         {"NODFA_DTE"                   ,        24,     1,      283,    "RO",   1,      1,      0,      0},
4198         {"NOZIP"                       ,        25,     1,      283,    "RO",   1,      1,      0,      0},
4199         {"EFUS_IGN"                    ,        26,     1,      283,    "RO",   1,      1,      0,      0},
4200         {"EFUS_LCK"                    ,        27,     1,      283,    "RO",   1,      1,      0,      0},
4201         {"BAR2_EN"                     ,        28,     1,      283,    "RO",   1,      1,      0,      0},
4202         {"RESERVED_29_63"              ,        29,     35,     283,    "RAZ",  1,      1,      0,      0},
4203         {"PROG"                        ,        0,      1,      284,    "R/W",  1,      1,      0,      0},
4204         {"RESERVED_1_63"               ,        1,      63,     284,    "RAZ",  1,      1,      0,      0},
4205         {"ADDR"                        ,        0,      7,      285,    "R/W",  0,      0,      0ull,   0ull},
4206         {"RESERVED_7_7"                ,        7,      1,      285,    "RAZ",  1,      1,      0,      0},
4207         {"EFUSE"                       ,        8,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
4208         {"RESERVED_9_11"               ,        9,      3,      285,    "RAZ",  1,      1,      0,      0},
4209         {"PEND"                        ,        12,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
4210         {"RESERVED_13_15"              ,        13,     3,      285,    "RAZ",  1,      1,      0,      0},
4211         {"DAT"                         ,        16,     8,      285,    "RO",   1,      1,      0,      0},
4212         {"RESERVED_24_63"              ,        24,     40,     285,    "RAZ",  1,      1,      0,      0},
4213         {"ADDR"                        ,        0,      10,     286,    "R/W",  1,      1,      0,      0},
4214         {"RESERVED_10_63"              ,        10,     54,     286,    "RAZ",  1,      1,      0,      0},
4215         {"ST_INT"                      ,        0,      1,      287,    "R/W1C",        0,      1,      0ull,   0},
4216         {"TS_INT"                      ,        1,      1,      287,    "R/W1C",        0,      1,      0ull,   0},
4217         {"CORE_INT"                    ,        2,      1,      287,    "RO",   0,      1,      0ull,   0},
4218         {"RESERVED_3_3"                ,        3,      1,      287,    "RAZ",  1,      1,      0,      0},
4219         {"ST_EN"                       ,        4,      1,      287,    "R/W",  0,      1,      0ull,   0},
4220         {"TS_EN"                       ,        5,      1,      287,    "R/W",  0,      1,      0ull,   0},
4221         {"CORE_EN"                     ,        6,      1,      287,    "R/W",  0,      1,      0ull,   0},
4222         {"RESERVED_7_63"               ,        7,      57,     287,    "RAZ",  1,      1,      0,      0},
4223         {"D"                           ,        0,      32,     288,    "R/W",  0,      1,      0ull,   0},
4224         {"EOP_IA"                      ,        32,     3,      288,    "R/W",  0,      1,      0ull,   0},
4225         {"IA"                          ,        35,     5,      288,    "R/W",  0,      1,      0ull,   0},
4226         {"A"                           ,        40,     10,     288,    "R/W",  0,      1,      0ull,   0},
4227         {"SCR"                         ,        50,     2,      288,    "R/W",  0,      1,      0ull,   0},
4228         {"SIZE"                        ,        52,     3,      288,    "R/W",  0,      1,      0ull,   0},
4229         {"SOVR"                        ,        55,     1,      288,    "R/W",  0,      1,      0ull,   0},
4230         {"R"                           ,        56,     1,      288,    "R/W",  0,      1,      0ull,   0},
4231         {"OP"                          ,        57,     4,      288,    "R/W",  0,      1,      0ull,   0},
4232         {"EIA"                         ,        61,     1,      288,    "R/W",  0,      1,      0ull,   0},
4233         {"SLONLY"                      ,        62,     1,      288,    "R/W",  0,      1,      0ull,   0},
4234         {"V"                           ,        63,     1,      288,    "RC/W", 0,      1,      0ull,   0},
4235         {"D"                           ,        0,      32,     289,    "R/W",  0,      1,      0ull,   0},
4236         {"IA"                          ,        32,     8,      289,    "R/W",  0,      1,      0ull,   0},
4237         {"RESERVED_40_63"              ,        40,     24,     289,    "RAZ",  1,      1,      0,      0},
4238         {"D"                           ,        0,      32,     290,    "R/W",  1,      1,      0,      0},
4239         {"RESERVED_32_61"              ,        32,     30,     290,    "RAZ",  1,      1,      0,      0},
4240         {"V"                           ,        62,     2,      290,    "RC/W", 0,      1,      0ull,   0},
4241         {"DLH"                         ,        0,      8,      291,    "R/W",  0,      1,      0ull,   0},
4242         {"RESERVED_8_63"               ,        8,      56,     291,    "RAZ",  1,      1,      0,      0},
4243         {"DLL"                         ,        0,      8,      292,    "R/W",  0,      1,      0ull,   0},
4244         {"RESERVED_8_63"               ,        8,      56,     292,    "RAZ",  1,      1,      0,      0},
4245         {"FAR"                         ,        0,      1,      293,    "R/W",  0,      1,      0ull,   0},
4246         {"RESERVED_1_63"               ,        1,      63,     293,    "RAZ",  1,      1,      0,      0},
4247         {"EN"                          ,        0,      1,      294,    "WO",   0,      1,      0ull,   0},
4248         {"RXFR"                        ,        1,      1,      294,    "WO",   0,      1,      0ull,   0},
4249         {"TXFR"                        ,        2,      1,      294,    "WO",   0,      1,      0ull,   0},
4250         {"RESERVED_3_3"                ,        3,      1,      294,    "RAZ",  0,      1,      0ull,   0},
4251         {"TXTRIG"                      ,        4,      2,      294,    "WO",   0,      1,      0ull,   0},
4252         {"RXTRIG"                      ,        6,      2,      294,    "WO",   0,      1,      0ull,   0},
4253         {"RESERVED_8_63"               ,        8,      56,     294,    "RAZ",  1,      1,      0,      0},
4254         {"HTX"                         ,        0,      1,      295,    "R/W",  0,      1,      0ull,   0},
4255         {"RESERVED_1_63"               ,        1,      63,     295,    "RAZ",  1,      1,      0,      0},
4256         {"ERBFI"                       ,        0,      1,      296,    "R/W",  0,      1,      0ull,   0},
4257         {"ETBEI"                       ,        1,      1,      296,    "R/W",  0,      1,      0ull,   0},
4258         {"ELSI"                        ,        2,      1,      296,    "R/W",  0,      1,      0ull,   0},
4259         {"EDSSI"                       ,        3,      1,      296,    "R/W",  0,      1,      0ull,   0},
4260         {"RESERVED_4_6"                ,        4,      3,      296,    "RAZ",  0,      1,      0ull,   0},
4261         {"PTIME"                       ,        7,      1,      296,    "R/W",  0,      1,      0ull,   0},
4262         {"RESERVED_8_63"               ,        8,      56,     296,    "RAZ",  1,      1,      0,      0},
4263         {"IID"                         ,        0,      4,      297,    "RO",   0,      1,      1ull,   0},
4264         {"RESERVED_4_5"                ,        4,      2,      297,    "RAZ",  0,      1,      0ull,   0},
4265         {"FEN"                         ,        6,      2,      297,    "RO",   0,      1,      0ull,   0},
4266         {"RESERVED_8_63"               ,        8,      56,     297,    "RAZ",  1,      1,      0,      0},
4267         {"CLS"                         ,        0,      2,      298,    "R/W",  0,      1,      0ull,   0},
4268         {"STOP"                        ,        2,      1,      298,    "R/W",  0,      1,      0ull,   0},
4269         {"PEN"                         ,        3,      1,      298,    "R/W",  0,      1,      0ull,   0},
4270         {"EPS"                         ,        4,      1,      298,    "R/W",  0,      1,      0ull,   0},
4271         {"RESERVED_5_5"                ,        5,      1,      298,    "RAZ",  0,      1,      0ull,   0},
4272         {"BRK"                         ,        6,      1,      298,    "R/W",  0,      1,      0ull,   0},
4273         {"DLAB"                        ,        7,      1,      298,    "R/W",  0,      1,      0ull,   0},
4274         {"RESERVED_8_63"               ,        8,      56,     298,    "RAZ",  1,      1,      0,      0},
4275         {"DR"                          ,        0,      1,      299,    "RO",   0,      1,      0ull,   0},
4276         {"OE"                          ,        1,      1,      299,    "RC",   0,      1,      0ull,   0},
4277         {"PE"                          ,        2,      1,      299,    "RC",   0,      1,      0ull,   0},
4278         {"FE"                          ,        3,      1,      299,    "RC",   0,      1,      0ull,   0},
4279         {"BI"                          ,        4,      1,      299,    "RC",   0,      1,      0ull,   0},
4280         {"THRE"                        ,        5,      1,      299,    "RO",   0,      1,      1ull,   0},
4281         {"TEMT"                        ,        6,      1,      299,    "RO",   0,      1,      1ull,   0},
4282         {"FERR"                        ,        7,      1,      299,    "RC",   0,      1,      0ull,   0},
4283         {"RESERVED_8_63"               ,        8,      56,     299,    "RAZ",  1,      1,      0,      0},
4284         {"DTR"                         ,        0,      1,      300,    "R/W",  0,      1,      0ull,   0},
4285         {"RTS"                         ,        1,      1,      300,    "R/W",  0,      1,      0ull,   0},
4286         {"OUT1"                        ,        2,      1,      300,    "R/W",  0,      1,      0ull,   0},
4287         {"OUT2"                        ,        3,      1,      300,    "R/W",  0,      1,      0ull,   0},
4288         {"LOOP"                        ,        4,      1,      300,    "R/W",  0,      1,      0ull,   0},
4289         {"AFCE"                        ,        5,      1,      300,    "R/W",  0,      1,      0ull,   0},
4290         {"RESERVED_6_63"               ,        6,      58,     300,    "RAZ",  0,      1,      0ull,   0},
4291         {"DCTS"                        ,        0,      1,      301,    "RC",   0,      1,      0ull,   0},
4292         {"DDSR"                        ,        1,      1,      301,    "RC",   0,      1,      0ull,   0},
4293         {"TERI"                        ,        2,      1,      301,    "RC",   0,      1,      0ull,   0},
4294         {"DDCD"                        ,        3,      1,      301,    "RC",   0,      1,      0ull,   0},
4295         {"CTS"                         ,        4,      1,      301,    "RO",   1,      1,      0,      0},
4296         {"DSR"                         ,        5,      1,      301,    "RO",   0,      1,      0ull,   0},
4297         {"RI"                          ,        6,      1,      301,    "RO",   0,      1,      0ull,   0},
4298         {"DCD"                         ,        7,      1,      301,    "RO",   0,      1,      0ull,   0},
4299         {"RESERVED_8_63"               ,        8,      56,     301,    "RAZ",  1,      1,      0,      0},
4300         {"RBR"                         ,        0,      8,      302,    "RO",   0,      1,      0ull,   0},
4301         {"RESERVED_8_63"               ,        8,      56,     302,    "RAZ",  1,      1,      0,      0},
4302         {"RFL"                         ,        0,      7,      303,    "RO",   0,      1,      0ull,   0},
4303         {"RESERVED_7_63"               ,        7,      57,     303,    "RAZ",  1,      1,      0,      0},
4304         {"RFWD"                        ,        0,      8,      304,    "WO",   0,      1,      0ull,   0},
4305         {"RFPE"                        ,        8,      1,      304,    "WO",   0,      1,      0ull,   0},
4306         {"RFFE"                        ,        9,      1,      304,    "WO",   0,      1,      0ull,   0},
4307         {"RESERVED_10_63"              ,        10,     54,     304,    "RAZ",  1,      1,      0,      0},
4308         {"SBCR"                        ,        0,      1,      305,    "R/W",  0,      1,      0ull,   0},
4309         {"RESERVED_1_63"               ,        1,      63,     305,    "RAZ",  1,      1,      0,      0},
4310         {"SCR"                         ,        0,      8,      306,    "R/W",  0,      1,      0ull,   0},
4311         {"RESERVED_8_63"               ,        8,      56,     306,    "RAZ",  1,      1,      0,      0},
4312         {"SFE"                         ,        0,      1,      307,    "R/W",  0,      1,      0ull,   0},
4313         {"RESERVED_1_63"               ,        1,      63,     307,    "RAZ",  1,      1,      0,      0},
4314         {"USR"                         ,        0,      1,      308,    "WO",   0,      1,      0ull,   0},
4315         {"SRFR"                        ,        1,      1,      308,    "WO",   0,      1,      0ull,   0},
4316         {"STFR"                        ,        2,      1,      308,    "WO",   0,      1,      0ull,   0},
4317         {"RESERVED_3_63"               ,        3,      61,     308,    "RAZ",  1,      1,      0,      0},
4318         {"SRT"                         ,        0,      2,      309,    "R/W",  0,      1,      0ull,   0},
4319         {"RESERVED_2_63"               ,        2,      62,     309,    "RAZ",  1,      1,      0,      0},
4320         {"SRTS"                        ,        0,      1,      310,    "R/W",  0,      1,      0ull,   0},
4321         {"RESERVED_1_63"               ,        1,      63,     310,    "RAZ",  1,      1,      0,      0},
4322         {"STT"                         ,        0,      2,      311,    "R/W",  0,      1,      0ull,   0},
4323         {"RESERVED_2_63"               ,        2,      62,     311,    "RAZ",  1,      1,      0,      0},
4324         {"TFL"                         ,        0,      7,      312,    "RO",   0,      1,      0ull,   0},
4325         {"RESERVED_7_63"               ,        7,      57,     312,    "RAZ",  1,      1,      0,      0},
4326         {"TFR"                         ,        0,      8,      313,    "RO",   0,      1,      0ull,   0},
4327         {"RESERVED_8_63"               ,        8,      56,     313,    "RAZ",  1,      1,      0,      0},
4328         {"THR"                         ,        0,      8,      314,    "WO",   0,      1,      0ull,   0},
4329         {"RESERVED_8_63"               ,        8,      56,     314,    "RAZ",  1,      1,      0,      0},
4330         {"BUSY"                        ,        0,      1,      315,    "RO",   0,      1,      0ull,   0},
4331         {"TFNF"                        ,        1,      1,      315,    "RO",   0,      1,      1ull,   0},
4332         {"TFE"                         ,        2,      1,      315,    "RO",   0,      1,      1ull,   0},
4333         {"RFNE"                        ,        3,      1,      315,    "RO",   0,      1,      0ull,   0},
4334         {"RFF"                         ,        4,      1,      315,    "RO",   0,      1,      0ull,   0},
4335         {"RESERVED_5_63"               ,        5,      59,     315,    "RAZ",  1,      1,      0,      0},
4336         {"RESERVED_0_2"                ,        0,      3,      316,    "RAZ",  1,      1,      0,      0},
4337         {"BADDR"                       ,        3,      61,     316,    "R/W",  0,      1,      0ull,   0},
4338         {"RESERVED_0_2"                ,        0,      3,      317,    "RAZ",  1,      1,      0,      0},
4339         {"BADDR"                       ,        3,      61,     317,    "R/W",  0,      1,      0ull,   0},
4340         {"DPI_BS"                      ,        0,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4341         {"PDF_BS"                      ,        1,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4342         {"DOB_BS"                      ,        2,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4343         {"NUS_BS"                      ,        3,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4344         {"POS_BS"                      ,        4,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4345         {"POF3_BS"                     ,        5,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4346         {"POF2_BS"                     ,        6,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4347         {"POF1_BS"                     ,        7,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4348         {"POF0_BS"                     ,        8,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4349         {"PIG_BS"                      ,        9,      1,      318,    "RO",   0,      0,      0ull,   0ull},
4350         {"PGF_BS"                      ,        10,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4351         {"RDNL_BS"                     ,        11,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4352         {"PCAD_BS"                     ,        12,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4353         {"PCAC_BS"                     ,        13,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4354         {"RDN_BS"                      ,        14,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4355         {"PCN_BS"                      ,        15,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4356         {"PCNC_BS"                     ,        16,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4357         {"RDP_BS"                      ,        17,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4358         {"DIF_BS"                      ,        18,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4359         {"CSR_BS"                      ,        19,     1,      318,    "RO",   0,      0,      0ull,   0ull},
4360         {"RESERVED_20_63"              ,        20,     44,     318,    "RAZ",  1,      1,      0,      0},
4361         {"BSIZE"                       ,        0,      16,     319,    "R/W",  0,      1,      1024ull,        0},
4362         {"ISIZE"                       ,        16,     7,      319,    "R/W",  0,      1,      0ull,   0},
4363         {"RESERVED_23_63"              ,        23,     41,     319,    "RAZ",  1,      1,      0,      0},
4364         {"TIMER"                       ,        0,      10,     320,    "R/W",  0,      0,      0ull,   50ull},
4365         {"RESERVED_10_31"              ,        10,     22,     320,    "RAZ",  0,      0,      0ull,   0ull},
4366         {"MAX_WORD"                    ,        32,     5,      320,    "R/W",  0,      0,      2ull,   0ull},
4367         {"RESERVED_37_39"              ,        37,     3,      320,    "RAZ",  0,      0,      0ull,   0ull},
4368         {"WAIT_COM"                    ,        40,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4369         {"PCI_WDIS"                    ,        41,     1,      320,    "R/W",  0,      0,      0ull,   0ull},
4370         {"INS0_64B"                    ,        42,     1,      320,    "R/W",  0,      1,      0ull,   0},
4371         {"INS1_64B"                    ,        43,     1,      320,    "R/W",  0,      1,      0ull,   0},
4372         {"INS2_64B"                    ,        44,     1,      320,    "R/W",  0,      1,      0ull,   0},
4373         {"INS3_64B"                    ,        45,     1,      320,    "R/W",  0,      1,      0ull,   0},
4374         {"INS0_ENB"                    ,        46,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4375         {"INS1_ENB"                    ,        47,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4376         {"INS2_ENB"                    ,        48,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4377         {"INS3_ENB"                    ,        49,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4378         {"OUT0_ENB"                    ,        50,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4379         {"OUT1_ENB"                    ,        51,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4380         {"OUT2_ENB"                    ,        52,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4381         {"OUT3_ENB"                    ,        53,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4382         {"DIS_PNIW"                    ,        54,     1,      320,    "R/W",  0,      0,      0ull,   1ull},
4383         {"CHIP_REV"                    ,        55,     8,      320,    "RO",   1,      1,      0,      0},
4384         {"RESERVED_63_63"              ,        63,     1,      320,    "RAZ",  1,      1,      0,      0},
4385         {"DBG_SEL"                     ,        0,      16,     321,    "R/W",  0,      1,      0ull,   0},
4386         {"RESERVED_16_63"              ,        16,     48,     321,    "RAZ",  1,      1,      0,      0},
4387         {"CSIZE"                       ,        0,      14,     322,    "R/W",  0,      1,      0ull,   0},
4388         {"LP_ENB"                      ,        14,     1,      322,    "R/W",  0,      0,      0ull,   1ull},
4389         {"HP_ENB"                      ,        15,     1,      322,    "R/W",  0,      0,      0ull,   1ull},
4390         {"O_MODE"                      ,        16,     1,      322,    "R/W",  0,      0,      0ull,   1ull},
4391         {"O_ES"                        ,        17,     2,      322,    "R/W",  0,      1,      0ull,   0},
4392         {"O_NS"                        ,        19,     1,      322,    "R/W",  0,      1,      0ull,   0},
4393         {"O_RO"                        ,        20,     1,      322,    "R/W",  0,      1,      0ull,   0},
4394         {"O_ADD1"                      ,        21,     1,      322,    "R/W",  0,      0,      0ull,   1ull},
4395         {"FPA_QUE"                     ,        22,     3,      322,    "R/W",  0,      1,      0ull,   0},
4396         {"DWB_ICHK"                    ,        25,     9,      322,    "R/W",  0,      1,      0ull,   0},
4397         {"DWB_DENB"                    ,        34,     1,      322,    "R/W",  0,      0,      0ull,   1ull},
4398         {"B0_LEND"                     ,        35,     1,      322,    "R/W",  0,      0,      0ull,   0ull},
4399         {"RESERVED_36_63"              ,        36,     28,     322,    "RAZ",  1,      1,      0,      0},
4400         {"DBELL"                       ,        0,      32,     323,    "RO",   0,      0,      0ull,   0ull},
4401         {"FCNT"                        ,        32,     7,      323,    "RO",   0,      0,      0ull,   0ull},
4402         {"RESERVED_39_63"              ,        39,     25,     323,    "RAZ",  1,      1,      0,      0},
4403         {"ADDR"                        ,        0,      36,     324,    "RO",   0,      1,      0ull,   0},
4404         {"STATE"                       ,        36,     4,      324,    "RO",   0,      0,      0ull,   0ull},
4405         {"RESERVED_40_63"              ,        40,     24,     324,    "RAZ",  1,      1,      0,      0},
4406         {"DBELL"                       ,        0,      32,     325,    "RO",   0,      0,      0ull,   0ull},
4407         {"FCNT"                        ,        32,     7,      325,    "RO",   0,      0,      0ull,   0ull},
4408         {"RESERVED_39_63"              ,        39,     25,     325,    "RAZ",  1,      1,      0,      0},
4409         {"ADDR"                        ,        0,      36,     326,    "RO",   0,      1,      0ull,   0},
4410         {"STATE"                       ,        36,     4,      326,    "RO",   0,      0,      0ull,   0ull},
4411         {"RESERVED_40_63"              ,        40,     24,     326,    "RAZ",  1,      1,      0,      0},
4412         {"DBELL"                       ,        0,      16,     327,    "R/W",  0,      1,      0ull,   0},
4413         {"RESERVED_16_63"              ,        16,     48,     327,    "RAZ",  1,      1,      0,      0},
4414         {"SADDR"                       ,        0,      36,     328,    "R/W",  0,      1,      0ull,   0},
4415         {"RESERVED_36_63"              ,        36,     28,     328,    "RAZ",  1,      1,      0,      0},
4416         {"ROR"                         ,        0,      1,      329,    "R/W",  0,      1,      0ull,   0},
4417         {"ESR"                         ,        1,      2,      329,    "R/W",  0,      1,      0ull,   0},
4418         {"NSR"                         ,        3,      1,      329,    "R/W",  0,      1,      0ull,   0},
4419         {"USE_CSR"                     ,        4,      1,      329,    "R/W",  0,      0,      0ull,   1ull},
4420         {"D_ROR"                       ,        5,      1,      329,    "R/W",  0,      1,      0ull,   0},
4421         {"D_ESR"                       ,        6,      2,      329,    "R/W",  0,      1,      0ull,   0},
4422         {"D_NSR"                       ,        8,      1,      329,    "R/W",  0,      1,      0ull,   0},
4423         {"PBP_DHI"                     ,        9,      13,     329,    "R/W",  0,      1,      0ull,   0},
4424         {"RESERVED_22_63"              ,        22,     42,     329,    "RAZ",  1,      1,      0,      0},
4425         {"RML_RTO"                     ,        0,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4426         {"RML_WTO"                     ,        1,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4427         {"PCI_RSL"                     ,        2,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4428         {"PO0_2SML"                    ,        3,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4429         {"PO1_2SML"                    ,        4,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4430         {"PO2_2SML"                    ,        5,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4431         {"PO3_2SML"                    ,        6,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4432         {"I0_RTOUT"                    ,        7,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4433         {"I1_RTOUT"                    ,        8,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4434         {"I2_RTOUT"                    ,        9,      1,      330,    "R/W",  0,      0,      0ull,   1ull},
4435         {"I3_RTOUT"                    ,        10,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4436         {"I0_OVERF"                    ,        11,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4437         {"I1_OVERF"                    ,        12,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4438         {"I2_OVERF"                    ,        13,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4439         {"I3_OVERF"                    ,        14,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4440         {"P0_RTOUT"                    ,        15,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4441         {"P1_RTOUT"                    ,        16,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4442         {"P2_RTOUT"                    ,        17,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4443         {"P3_RTOUT"                    ,        18,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4444         {"P0_PERR"                     ,        19,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4445         {"P1_PERR"                     ,        20,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4446         {"P2_PERR"                     ,        21,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4447         {"P3_PERR"                     ,        22,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4448         {"G0_RTOUT"                    ,        23,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4449         {"G1_RTOUT"                    ,        24,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4450         {"G2_RTOUT"                    ,        25,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4451         {"G3_RTOUT"                    ,        26,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4452         {"P0_PPERR"                    ,        27,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4453         {"P1_PPERR"                    ,        28,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4454         {"P2_PPERR"                    ,        29,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4455         {"P3_PPERR"                    ,        30,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4456         {"P0_PTOUT"                    ,        31,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4457         {"P1_PTOUT"                    ,        32,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4458         {"P2_PTOUT"                    ,        33,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4459         {"P3_PTOUT"                    ,        34,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4460         {"I0_PPERR"                    ,        35,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4461         {"I1_PPERR"                    ,        36,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4462         {"I2_PPERR"                    ,        37,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4463         {"I3_PPERR"                    ,        38,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4464         {"WIN_RTO"                     ,        39,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4465         {"P_DPERR"                     ,        40,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4466         {"IOBDMA"                      ,        41,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
4467         {"RESERVED_42_63"              ,        42,     22,     330,    "RAZ",  1,      1,      0,      0},
4468         {"RML_RTO"                     ,        0,      1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4469         {"RML_WTO"                     ,        1,      1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4470         {"PCI_RSL"                     ,        2,      1,      331,    "RO",   0,      0,      0ull,   0ull},
4471         {"PO0_2SML"                    ,        3,      1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4472         {"PO1_2SML"                    ,        4,      1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4473         {"PO2_2SML"                    ,        5,      1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4474         {"PO3_2SML"                    ,        6,      1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4475         {"I0_RTOUT"                    ,        7,      1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4476         {"I1_RTOUT"                    ,        8,      1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4477         {"I2_RTOUT"                    ,        9,      1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4478         {"I3_RTOUT"                    ,        10,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4479         {"I0_OVERF"                    ,        11,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4480         {"I1_OVERF"                    ,        12,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4481         {"I2_OVERF"                    ,        13,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4482         {"I3_OVERF"                    ,        14,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4483         {"P0_RTOUT"                    ,        15,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4484         {"P1_RTOUT"                    ,        16,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4485         {"P2_RTOUT"                    ,        17,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4486         {"P3_RTOUT"                    ,        18,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4487         {"P0_PERR"                     ,        19,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4488         {"P1_PERR"                     ,        20,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4489         {"P2_PERR"                     ,        21,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4490         {"P3_PERR"                     ,        22,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4491         {"G0_RTOUT"                    ,        23,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4492         {"G1_RTOUT"                    ,        24,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4493         {"G2_RTOUT"                    ,        25,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4494         {"G3_RTOUT"                    ,        26,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4495         {"P0_PPERR"                    ,        27,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4496         {"P1_PPERR"                    ,        28,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4497         {"P2_PPERR"                    ,        29,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4498         {"P3_PPERR"                    ,        30,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4499         {"P0_PTOUT"                    ,        31,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4500         {"P1_PTOUT"                    ,        32,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4501         {"P2_PTOUT"                    ,        33,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4502         {"P3_PTOUT"                    ,        34,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4503         {"I0_PPERR"                    ,        35,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4504         {"I1_PPERR"                    ,        36,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4505         {"I2_PPERR"                    ,        37,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4506         {"I3_PPERR"                    ,        38,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4507         {"WIN_RTO"                     ,        39,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4508         {"P_DPERR"                     ,        40,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4509         {"IOBDMA"                      ,        41,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
4510         {"RESERVED_42_63"              ,        42,     22,     331,    "RAZ",  1,      1,      0,      0},
4511         {"DBELL"                       ,        0,      16,     332,    "R/W",  0,      1,      0ull,   0},
4512         {"RESERVED_16_63"              ,        16,     48,     332,    "RAZ",  1,      1,      0,      0},
4513         {"SADDR"                       ,        0,      36,     333,    "R/W",  0,      1,      0ull,   0},
4514         {"RESERVED_36_63"              ,        36,     28,     333,    "RAZ",  1,      1,      0,      0},
4515         {"BA"                          ,        0,      28,     334,    "R/W",  0,      1,      0ull,   0},
4516         {"ROW"                         ,        28,     1,      334,    "R/W",  0,      1,      0ull,   0},
4517         {"ROR"                         ,        29,     1,      334,    "R/W",  0,      1,      0ull,   0},
4518         {"NSW"                         ,        30,     1,      334,    "R/W",  0,      1,      0ull,   0},
4519         {"NSR"                         ,        31,     1,      334,    "R/W",  0,      1,      0ull,   0},
4520         {"ESW"                         ,        32,     2,      334,    "R/W",  0,      1,      0ull,   0},
4521         {"ESR"                         ,        34,     2,      334,    "R/W",  0,      1,      0ull,   0},
4522         {"RESERVED_36_63"              ,        36,     28,     334,    "RAZ",  1,      1,      0,      0},
4523         {"INT_VEC"                     ,        0,      64,     335,    "R/W1C",        0,      0,      0ull,   0ull},
4524         {"SIZE"                        ,        0,      32,     336,    "R/W",  0,      1,      0ull,   0},
4525         {"RESERVED_32_63"              ,        32,     32,     336,    "RAZ",  1,      1,      0,      0},
4526         {"ROR_SL0"                     ,        0,      1,      337,    "R/W",  0,      1,      0ull,   0},
4527         {"NSR_SL0"                     ,        1,      1,      337,    "R/W",  0,      1,      0ull,   0},
4528         {"ESR_SL0"                     ,        2,      2,      337,    "R/W",  0,      1,      0ull,   0},
4529         {"ROR_SL1"                     ,        4,      1,      337,    "R/W",  0,      1,      0ull,   0},
4530         {"NSR_SL1"                     ,        5,      1,      337,    "R/W",  0,      1,      0ull,   0},
4531         {"ESR_SL1"                     ,        6,      2,      337,    "R/W",  0,      1,      0ull,   0},
4532         {"ROR_SL2"                     ,        8,      1,      337,    "R/W",  0,      1,      0ull,   0},
4533         {"NSR_SL2"                     ,        9,      1,      337,    "R/W",  0,      1,      0ull,   0},
4534         {"ESR_SL2"                     ,        10,     2,      337,    "R/W",  0,      1,      0ull,   0},
4535         {"ROR_SL3"                     ,        12,     1,      337,    "R/W",  0,      1,      0ull,   0},
4536         {"NSR_SL3"                     ,        13,     1,      337,    "R/W",  0,      1,      0ull,   0},
4537         {"ESR_SL3"                     ,        14,     2,      337,    "R/W",  0,      1,      0ull,   0},
4538         {"IPTR_O0"                     ,        16,     1,      337,    "R/W",  0,      0,      0ull,   1ull},
4539         {"IPTR_O1"                     ,        17,     1,      337,    "R/W",  0,      0,      0ull,   1ull},
4540         {"IPTR_O2"                     ,        18,     1,      337,    "R/W",  0,      0,      0ull,   1ull},
4541         {"IPTR_O3"                     ,        19,     1,      337,    "R/W",  0,      0,      0ull,   1ull},
4542         {"RESERVED_20_23"              ,        20,     4,      337,    "RAZ",  0,      0,      0ull,   0ull},
4543         {"O0_CSRM"                     ,        24,     1,      337,    "R/W",  0,      0,      0ull,   1ull},
4544         {"O1_CSRM"                     ,        25,     1,      337,    "R/W",  0,      0,      0ull,   1ull},
4545         {"O2_CSRM"                     ,        26,     1,      337,    "R/W",  0,      0,      0ull,   1ull},
4546         {"O3_CSRM"                     ,        27,     1,      337,    "R/W",  0,      0,      0ull,   1ull},
4547         {"O0_RO"                       ,        28,     1,      337,    "R/W",  0,      1,      0ull,   0},
4548         {"O0_NS"                       ,        29,     1,      337,    "R/W",  0,      1,      0ull,   0},
4549         {"O0_ES"                       ,        30,     2,      337,    "R/W",  0,      1,      0ull,   0},
4550         {"O1_RO"                       ,        32,     1,      337,    "R/W",  0,      1,      0ull,   0},
4551         {"O1_NS"                       ,        33,     1,      337,    "R/W",  0,      1,      0ull,   0},
4552         {"O1_ES"                       ,        34,     2,      337,    "R/W",  0,      1,      0ull,   0},
4553         {"O2_RO"                       ,        36,     1,      337,    "R/W",  0,      1,      0ull,   0},
4554         {"O2_NS"                       ,        37,     1,      337,    "R/W",  0,      1,      0ull,   0},
4555         {"O2_ES"                       ,        38,     2,      337,    "R/W",  0,      1,      0ull,   0},
4556         {"O3_RO"                       ,        40,     1,      337,    "R/W",  0,      1,      0ull,   0},
4557         {"O3_NS"                       ,        41,     1,      337,    "R/W",  0,      1,      0ull,   0},
4558         {"O3_ES"                       ,        42,     2,      337,    "R/W",  0,      1,      0ull,   0},
4559         {"P0_BMODE"                    ,        44,     1,      337,    "R/W",  0,      0,      0ull,   0ull},
4560         {"P1_BMODE"                    ,        45,     1,      337,    "R/W",  0,      0,      0ull,   0ull},
4561         {"P2_BMODE"                    ,        46,     1,      337,    "R/W",  0,      0,      0ull,   0ull},
4562         {"P3_BMODE"                    ,        47,     1,      337,    "R/W",  0,      0,      0ull,   0ull},
4563         {"RESERVED_48_63"              ,        48,     16,     337,    "RAZ",  1,      1,      0,      0},
4564         {"NADDR"                       ,        0,      61,     338,    "RO",   0,      1,      0ull,   0},
4565         {"STATE"                       ,        61,     2,      338,    "RO",   0,      0,      0ull,   0ull},
4566         {"RESERVED_63_63"              ,        63,     1,      338,    "RAZ",  1,      1,      0,      0},
4567         {"NADDR"                       ,        0,      61,     339,    "RO",   0,      1,      0ull,   0},
4568         {"STATE"                       ,        61,     3,      339,    "RO",   0,      0,      0ull,   0ull},
4569         {"AVAIL"                       ,        0,      32,     340,    "RO",   0,      0,      0ull,   0ull},
4570         {"FCNT"                        ,        32,     6,      340,    "RO",   0,      0,      0ull,   0ull},
4571         {"RESERVED_38_63"              ,        38,     26,     340,    "RAZ",  1,      1,      0,      0},
4572         {"AVAIL"                       ,        0,      32,     341,    "RO",   0,      0,      0ull,   0ull},
4573         {"FCNT"                        ,        32,     5,      341,    "RO",   0,      0,      0ull,   0ull},
4574         {"RESERVED_37_63"              ,        37,     27,     341,    "RAZ",  1,      1,      0,      0},
4575         {"RD_BRST"                     ,        0,      7,      342,    "R/W",  0,      0,      17ull,  64ull},
4576         {"WR_BRST"                     ,        7,      7,      342,    "R/W",  0,      0,      16ull,  64ull},
4577         {"RESERVED_14_63"              ,        14,     50,     342,    "RAZ",  1,      1,      0,      0},
4578         {"PARK_DEV"                    ,        0,      3,      343,    "R/W",  0,      1,      0ull,   0},
4579         {"PARK_MOD"                    ,        3,      1,      343,    "R/W",  0,      1,      0ull,   0},
4580         {"EN"                          ,        4,      1,      343,    "R/W",  0,      1,      0ull,   0},
4581         {"RESERVED_5_63"               ,        5,      59,     343,    "RAZ",  1,      1,      0,      0},
4582         {"CMD_SIZE"                    ,        0,      11,     344,    "R/W",  0,      0,      9ull,   9ull},
4583         {"RESERVED_11_63"              ,        11,     53,     344,    "RAZ",  1,      1,      0,      0},
4584         {"RSV_A"                       ,        0,      6,      345,    "R/W",  0,      1,      0ull,   0},
4585         {"SKP_LEN"                     ,        6,      7,      345,    "R/W",  0,      1,      0ull,   0},
4586         {"RSV_B"                       ,        13,     1,      345,    "R/W",  0,      1,      0ull,   0},
4587         {"PAR_MODE"                    ,        14,     2,      345,    "R/W",  0,      1,      0ull,   0},
4588         {"RSV_C"                       ,        16,     5,      345,    "R/W",  0,      1,      0ull,   0},
4589         {"USE_IHDR"                    ,        21,     1,      345,    "R/W",  0,      1,      0ull,   0},
4590         {"RSV_D"                       ,        22,     6,      345,    "R/W",  0,      1,      0ull,   0},
4591         {"RSKP_LEN"                    ,        28,     7,      345,    "R/W",  0,      1,      8ull,   0},
4592         {"RSV_E"                       ,        35,     1,      345,    "R/W",  0,      1,      0ull,   0},
4593         {"RPARMODE"                    ,        36,     2,      345,    "R/W",  0,      1,      0ull,   0},
4594         {"RSV_F"                       ,        38,     5,      345,    "R/W",  0,      1,      0ull,   0},
4595         {"PBP"                         ,        43,     1,      345,    "R/W",  0,      1,      0ull,   0},
4596         {"RESERVED_44_63"              ,        44,     20,     345,    "RAZ",  1,      1,      0,      0},
4597         {"RSV_A"                       ,        0,      6,      346,    "R/W",  0,      1,      0ull,   0},
4598         {"SKP_LEN"                     ,        6,      7,      346,    "R/W",  0,      1,      0ull,   0},
4599         {"RSV_B"                       ,        13,     1,      346,    "R/W",  0,      1,      0ull,   0},
4600         {"PAR_MODE"                    ,        14,     2,      346,    "R/W",  0,      1,      0ull,   0},
4601         {"RSV_C"                       ,        16,     5,      346,    "R/W",  0,      1,      0ull,   0},
4602         {"USE_IHDR"                    ,        21,     1,      346,    "R/W",  0,      1,      0ull,   0},
4603         {"RSV_D"                       ,        22,     6,      346,    "R/W",  0,      1,      0ull,   0},
4604         {"RSKP_LEN"                    ,        28,     7,      346,    "R/W",  0,      1,      8ull,   0},
4605         {"RSV_E"                       ,        35,     1,      346,    "R/W",  0,      1,      0ull,   0},
4606         {"RPARMODE"                    ,        36,     2,      346,    "R/W",  0,      1,      0ull,   0},
4607         {"RSV_F"                       ,        38,     5,      346,    "R/W",  0,      1,      0ull,   0},
4608         {"PBP"                         ,        43,     1,      346,    "R/W",  0,      1,      0ull,   0},
4609         {"RESERVED_44_63"              ,        44,     20,     346,    "RAZ",  1,      1,      0,      0},
4610         {"RSV_A"                       ,        0,      6,      347,    "R/W",  0,      1,      0ull,   0},
4611         {"SKP_LEN"                     ,        6,      7,      347,    "R/W",  0,      1,      0ull,   0},
4612         {"RSV_B"                       ,        13,     1,      347,    "R/W",  0,      1,      0ull,   0},
4613         {"PAR_MODE"                    ,        14,     2,      347,    "R/W",  0,      1,      0ull,   0},
4614         {"RSV_C"                       ,        16,     5,      347,    "R/W",  0,      1,      0ull,   0},
4615         {"USE_IHDR"                    ,        21,     1,      347,    "R/W",  0,      1,      0ull,   0},
4616         {"RSV_D"                       ,        22,     6,      347,    "R/W",  0,      1,      0ull,   0},
4617         {"RSKP_LEN"                    ,        28,     7,      347,    "R/W",  0,      1,      8ull,   0},
4618         {"RSV_E"                       ,        35,     1,      347,    "R/W",  0,      1,      0ull,   0},
4619         {"RPARMODE"                    ,        36,     2,      347,    "R/W",  0,      1,      0ull,   0},
4620         {"RSV_F"                       ,        38,     5,      347,    "R/W",  0,      1,      0ull,   0},
4621         {"PBP"                         ,        43,     1,      347,    "R/W",  0,      1,      0ull,   0},
4622         {"RESERVED_44_63"              ,        44,     20,     347,    "RAZ",  1,      1,      0,      0},
4623         {"RSV_A"                       ,        0,      6,      348,    "R/W",  0,      1,      0ull,   0},
4624         {"SKP_LEN"                     ,        6,      7,      348,    "R/W",  0,      1,      0ull,   0},
4625         {"RSV_B"                       ,        13,     1,      348,    "R/W",  0,      1,      0ull,   0},
4626         {"PAR_MODE"                    ,        14,     2,      348,    "R/W",  0,      1,      0ull,   0},
4627         {"RSV_C"                       ,        16,     5,      348,    "R/W",  0,      1,      0ull,   0},
4628         {"USE_IHDR"                    ,        21,     1,      348,    "R/W",  0,      1,      0ull,   0},
4629         {"RSV_D"                       ,        22,     6,      348,    "R/W",  0,      1,      0ull,   0},
4630         {"RSKP_LEN"                    ,        28,     7,      348,    "R/W",  0,      1,      8ull,   0},
4631         {"RSV_E"                       ,        35,     1,      348,    "R/W",  0,      1,      0ull,   0},
4632         {"RPARMODE"                    ,        36,     2,      348,    "R/W",  0,      1,      0ull,   0},
4633         {"RSV_F"                       ,        38,     5,      348,    "R/W",  0,      1,      0ull,   0},
4634         {"PBP"                         ,        43,     1,      348,    "R/W",  0,      1,      0ull,   0},
4635         {"RESERVED_44_63"              ,        44,     20,     348,    "RAZ",  1,      1,      0,      0},
4636         {"ENB"                         ,        0,      4,      349,    "R/W",  0,      0,      15ull,  15ull},
4637         {"BP_ON"                       ,        4,      4,      349,    "RO",   0,      0,      0ull,   0ull},
4638         {"RESERVED_8_63"               ,        8,      56,     349,    "RAZ",  1,      1,      0,      0},
4639         {"MIO"                         ,        0,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4640         {"GMX0"                        ,        1,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4641         {"GMX1"                        ,        2,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4642         {"NPI"                         ,        3,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4643         {"KEY"                         ,        4,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4644         {"FPA"                         ,        5,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4645         {"DFA"                         ,        6,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4646         {"ZIP"                         ,        7,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4647         {"RINT_8"                      ,        8,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4648         {"IPD"                         ,        9,      1,      350,    "RO",   0,      0,      0ull,   0ull},
4649         {"PKO"                         ,        10,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4650         {"TIM"                         ,        11,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4651         {"POW"                         ,        12,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4652         {"RINT_13"                     ,        13,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4653         {"RINT_14"                     ,        14,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4654         {"RINT_15"                     ,        15,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4655         {"L2C"                         ,        16,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4656         {"LMC"                         ,        17,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4657         {"SPX0"                        ,        18,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4658         {"SPX1"                        ,        19,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4659         {"PIP"                         ,        20,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4660         {"RINT_21"                     ,        21,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4661         {"ASX0"                        ,        22,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4662         {"ASX1"                        ,        23,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4663         {"RINT_24"                     ,        24,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4664         {"RINT_25"                     ,        25,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4665         {"RINT_26"                     ,        26,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4666         {"RINT_27"                     ,        27,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4667         {"RINT_28"                     ,        28,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4668         {"RINT_29"                     ,        29,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4669         {"IOB"                         ,        30,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4670         {"RINT_31"                     ,        31,     1,      350,    "RO",   0,      0,      0ull,   0ull},
4671         {"RESERVED_32_63"              ,        32,     32,     350,    "RAZ",  1,      1,      0,      0},
4672         {"SIZE"                        ,        0,      32,     351,    "R/W",  0,      1,      0ull,   0},
4673         {"RESERVED_32_63"              ,        32,     32,     351,    "RAZ",  1,      1,      0,      0},
4674         {"TIME"                        ,        0,      32,     352,    "R/W",  0,      0,      0ull,   131072ull},
4675         {"RESERVED_32_63"              ,        32,     32,     352,    "RAZ",  1,      1,      0,      0},
4676         {"ADDR_V"                      ,        0,      1,      353,    "R/W",  0,      1,      0ull,   0},
4677         {"END_SWP"                     ,        1,      2,      353,    "R/W",  0,      1,      0ull,   0},
4678         {"CA"                          ,        3,      1,      353,    "R/W",  0,      0,      0ull,   0ull},
4679         {"ADDR_IDX"                    ,        4,      14,     353,    "R/W",  0,      1,      0ull,   0},
4680         {"RESERVED_18_31"              ,        18,     14,     353,    "RAZ",  1,      1,      0,      0},
4681         {"VENDID"                      ,        0,      16,     354,    "RO",   0,      0,      6013ull,        6013ull},
4682         {"DEVID"                       ,        16,     16,     354,    "RO",   0,      0,      4ull,   4ull},
4683         {"ISAE"                        ,        0,      1,      355,    "RO",   0,      0,      0ull,   0ull},
4684         {"MSAE"                        ,        1,      1,      355,    "R/W",  0,      0,      0ull,   1ull},
4685         {"ME"                          ,        2,      1,      355,    "R/W",  0,      0,      0ull,   1ull},
4686         {"SCSE"                        ,        3,      1,      355,    "RO",   0,      0,      0ull,   0ull},
4687         {"MWICE"                       ,        4,      1,      355,    "R/W",  0,      0,      0ull,   0ull},
4688         {"VPS"                         ,        5,      1,      355,    "RO",   0,      0,      0ull,   0ull},
4689         {"PEE"                         ,        6,      1,      355,    "R/W",  0,      0,      0ull,   1ull},
4690         {"ADS"                         ,        7,      1,      355,    "RO",   0,      0,      0ull,   0ull},
4691         {"SEE"                         ,        8,      1,      355,    "R/W",  0,      0,      0ull,   1ull},
4692         {"FBBE"                        ,        9,      1,      355,    "R/W",  0,      0,      0ull,   1ull},
4693         {"I_DIS"                       ,        10,     1,      355,    "R/W",  0,      0,      0ull,   0ull},
4694         {"RESERVED_11_18"              ,        11,     8,      355,    "RAZ",  1,      1,      0,      0},
4695         {"I_STAT"                      ,        19,     1,      355,    "RO",   0,      0,      0ull,   0ull},
4696         {"CLE"                         ,        20,     1,      355,    "RO",   0,      0,      1ull,   1ull},
4697         {"M66"                         ,        21,     1,      355,    "RO",   0,      0,      1ull,   1ull},
4698         {"RESERVED_22_22"              ,        22,     1,      355,    "RAZ",  1,      1,      0,      0},
4699         {"FBB"                         ,        23,     1,      355,    "RO",   0,      1,      1ull,   0},
4700         {"MDPE"                        ,        24,     1,      355,    "R/W1C",        0,      0,      0ull,   0ull},
4701         {"DEVT"                        ,        25,     2,      355,    "RO",   0,      0,      1ull,   1ull},
4702         {"STA"                         ,        27,     1,      355,    "R/W1C",        0,      0,      0ull,   0ull},
4703         {"RTA"                         ,        28,     1,      355,    "R/W1C",        0,      0,      0ull,   0ull},
4704         {"RMA"                         ,        29,     1,      355,    "R/W1C",        0,      0,      0ull,   0ull},
4705         {"SSE"                         ,        30,     1,      355,    "R/W1C",        0,      0,      0ull,   0ull},
4706         {"DPE"                         ,        31,     1,      355,    "R/W1C",        0,      0,      0ull,   0ull},
4707         {"RID"                         ,        0,      8,      356,    "RO",   0,      0,      1ull,   1ull},
4708         {"CC"                          ,        8,      24,     356,    "RO",   0,      0,      1048576ull,     1048576ull},
4709         {"CLS"                         ,        0,      8,      357,    "R/W",  0,      1,      0ull,   0},
4710         {"LT"                          ,        8,      8,      357,    "R/W",  0,      0,      0ull,   64ull},
4711         {"HT"                          ,        16,     8,      357,    "RO",   0,      0,      0ull,   0ull},
4712         {"BCOD"                        ,        24,     4,      357,    "RO",   0,      0,      0ull,   0ull},
4713         {"RESERVED_28_29"              ,        28,     2,      357,    "RAZ",  1,      1,      0,      0},
4714         {"BRB"                         ,        30,     1,      357,    "R/W",  0,      0,      0ull,   0ull},
4715         {"BCAP"                        ,        31,     1,      357,    "RO",   0,      0,      0ull,   0ull},
4716         {"MSPC"                        ,        0,      1,      358,    "RO",   0,      0,      0ull,   0ull},
4717         {"TYP"                         ,        1,      2,      358,    "RO",   0,      0,      2ull,   2ull},
4718         {"PF"                          ,        3,      1,      358,    "RO",   0,      0,      1ull,   1ull},
4719         {"LBASEZ"                      ,        4,      8,      358,    "RO",   0,      0,      0ull,   0ull},
4720         {"LBASE"                       ,        12,     20,     358,    "R/W",  0,      1,      0ull,   0},
4721         {"HBASE"                       ,        0,      32,     359,    "R/W",  0,      1,      0ull,   0},
4722         {"MSPC"                        ,        0,      1,      360,    "RO",   0,      0,      0ull,   0ull},
4723         {"TYP"                         ,        1,      2,      360,    "RO",   0,      0,      2ull,   2ull},
4724         {"PF"                          ,        3,      1,      360,    "RO",   0,      0,      1ull,   1ull},
4725         {"LBASEZ"                      ,        4,      23,     360,    "RO",   0,      0,      0ull,   0ull},
4726         {"LBASE"                       ,        27,     5,      360,    "R/W",  0,      1,      0ull,   0},
4727         {"HBASE"                       ,        0,      32,     361,    "R/W",  0,      1,      0ull,   0},
4728         {"MSPC"                        ,        0,      1,      362,    "RO",   0,      0,      0ull,   0ull},
4729         {"TYP"                         ,        1,      2,      362,    "RO",   0,      0,      2ull,   2ull},
4730         {"PF"                          ,        3,      1,      362,    "RO",   0,      0,      1ull,   1ull},
4731         {"LBASEZ"                      ,        4,      28,     362,    "RO",   0,      0,      0ull,   0ull},
4732         {"HBASEZ"                      ,        0,      7,      363,    "RO",   0,      0,      0ull,   0ull},
4733         {"HBASE"                       ,        7,      25,     363,    "R/W",  0,      1,      0ull,   0},
4734         {"CISP"                        ,        0,      32,     364,    "RO",   0,      0,      0ull,   0ull},
4735         {"SSVID"                       ,        0,      16,     365,    "RO",   0,      0,      6013ull,        6013ull},
4736         {"SSID"                        ,        16,     16,     365,    "RO",   0,      0,      1ull,   1ull},
4737         {"ERBAR_EN"                    ,        0,      1,      366,    "R/W",  0,      0,      0ull,   0ull},
4738         {"RESERVED_1_10"               ,        1,      10,     366,    "RAZ",  1,      1,      0,      0},
4739         {"ERBARZ"                      ,        11,     5,      366,    "RO",   0,      0,      0ull,   0ull},
4740         {"ERBAR"                       ,        16,     16,     366,    "R/W",  0,      1,      0ull,   0},
4741         {"CP"                          ,        0,      8,      367,    "RO",   0,      0,      224ull, 224ull},
4742         {"RESERVED_8_31"               ,        8,      24,     367,    "RAZ",  1,      1,      0,      0},
4743         {"IL"                          ,        0,      8,      368,    "R/W",  0,      1,      0ull,   0},
4744         {"INTA"                        ,        8,      8,      368,    "RO",   0,      0,      1ull,   1ull},
4745         {"MG"                          ,        16,     8,      368,    "RO",   0,      0,      64ull,  64ull},
4746         {"ML"                          ,        24,     8,      368,    "RO",   0,      0,      64ull,  64ull},
4747         {"MLTD"                        ,        0,      1,      369,    "R/W",  0,      0,      0ull,   1ull},
4748         {"TSWC"                        ,        1,      1,      369,    "R/W",  0,      0,      0ull,   0ull},
4749         {"RESERVED_2_2"                ,        2,      1,      369,    "RAZ",  1,      1,      0,      0},
4750         {"DPPMR"                       ,        3,      1,      369,    "R/W",  0,      0,      0ull,   0ull},
4751         {"PBE"                         ,        4,      12,     369,    "R/W",  0,      0,      0ull,   0ull},
4752         {"TILT"                        ,        16,     4,      369,    "R/W",  0,      0,      0ull,   0ull},
4753         {"TSLTE"                       ,        20,     3,      369,    "R/W",  0,      0,      0ull,   0ull},
4754         {"TMAE"                        ,        23,     1,      369,    "R/W",  0,      0,      0ull,   0ull},
4755         {"TWTAE"                       ,        24,     1,      369,    "R/W",  0,      0,      0ull,   0ull},
4756         {"TWSEN"                       ,        25,     1,      369,    "R/W",  0,      0,      0ull,   0ull},
4757         {"TWSEI"                       ,        26,     1,      369,    "R/W",  0,      0,      0ull,   0ull},
4758         {"TRTAE"                       ,        27,     1,      369,    "R/W",  0,      0,      0ull,   0ull},
4759         {"TRDRS"                       ,        28,     1,      369,    "R/W",  0,      0,      0ull,   0ull},
4760         {"RDSATI"                      ,        29,     1,      369,    "R/W",  0,      0,      0ull,   0ull},
4761         {"TRDARD"                      ,        30,     1,      369,    "R/W1C",        0,      0,      0ull,   0ull},
4762         {"TRDNPR"                      ,        31,     1,      369,    "R/W1C",        0,      0,      0ull,   0ull},
4763         {"TSCME"                       ,        0,      32,     370,    "R/W1C",        0,      1,      0ull,   0},
4764         {"TDSRPS"                      ,        0,      32,     371,    "R/W1C",        0,      0,      0ull,   0ull},
4765         {"TDOMC"                       ,        0,      5,      372,    "R/W",  0,      0,      1ull,   1ull},
4766         {"TIDOMC"                      ,        5,      1,      372,    "R/W",  0,      0,      0ull,   0ull},
4767         {"RESERVED_6_6"                ,        6,      1,      372,    "RAZ",  1,      1,      0,      0},
4768         {"TIBDE"                       ,        7,      1,      372,    "R/W",  0,      0,      0ull,   0ull},
4769         {"TIBCD"                       ,        8,      1,      372,    "R/W1C",        0,      0,      0ull,   0ull},
4770         {"RESERVED_9_10"               ,        9,      2,      372,    "RAZ",  1,      1,      0,      0},
4771         {"TMAPES"                      ,        11,     1,      372,    "R/W1C",        0,      0,      0ull,   0ull},
4772         {"TMDPES"                      ,        12,     1,      372,    "R/W1C",        0,      0,      0ull,   0ull},
4773         {"TMSE"                        ,        13,     1,      372,    "R/W1C",        0,      0,      0ull,   0ull},
4774         {"TMEI"                        ,        14,     1,      372,    "RO",   0,      0,      0ull,   0ull},
4775         {"TECI"                        ,        15,     1,      372,    "RO",   0,      0,      0ull,   0ull},
4776         {"TMES"                        ,        16,     8,      372,    "RO",   0,      0,      0ull,   0ull},
4777         {"MDRRMC"                      ,        24,     3,      372,    "R/W",  0,      0,      2ull,   2ull},
4778         {"MDRIMC"                      ,        27,     1,      372,    "R/W",  0,      0,      0ull,   0ull},
4779         {"MDRE"                        ,        28,     1,      372,    "R/W",  0,      0,      0ull,   0ull},
4780         {"MDWE"                        ,        29,     1,      372,    "R/W",  0,      0,      0ull,   0ull},
4781         {"MRBCI"                       ,        30,     1,      372,    "R/W",  0,      0,      0ull,   0ull},
4782         {"MRBCM"                       ,        31,     1,      372,    "R/W",  0,      0,      1ull,   1ull},
4783         {"MDSP"                        ,        0,      32,     373,    "R/W1C",        0,      1,      0ull,   0},
4784         {"SCMRE"                       ,        0,      32,     374,    "R/W1C",        0,      1,      0ull,   0},
4785         {"MTTV"                        ,        0,      8,      375,    "R/W",  0,      0,      0ull,   0ull},
4786         {"MRV"                         ,        8,      8,      375,    "R/W",  0,      0,      0ull,   255ull},
4787         {"MTTA"                        ,        16,     1,      375,    "R/W1C",        0,      0,      0ull,   0ull},
4788         {"MRA"                         ,        17,     1,      375,    "R/W1C",        0,      0,      0ull,   0ull},
4789         {"FLUSH"                       ,        18,     1,      375,    "R/W",  0,      0,      1ull,   1ull},
4790         {"RESERVED_19_24"              ,        19,     6,      375,    "RAZ",  1,      1,      0,      0},
4791         {"MAC"                         ,        25,     7,      375,    "R/W",  0,      0,      0ull,   0ull},
4792         {"PXCID"                       ,        0,      8,      376,    "RO",   0,      0,      7ull,   7ull},
4793         {"NCP"                         ,        8,      8,      376,    "RO",   0,      0,      232ull, 232ull},
4794         {"DPERE"                       ,        16,     1,      376,    "R/W",  0,      0,      0ull,   0ull},
4795         {"ROE"                         ,        17,     1,      376,    "R/W",  0,      0,      1ull,   1ull},
4796         {"MMBC"                        ,        18,     2,      376,    "R/W",  0,      0,      0ull,   0ull},
4797         {"MOST"                        ,        20,     3,      376,    "R/W",  0,      0,      3ull,   3ull},
4798         {"RESERVED_23_31"              ,        23,     9,      376,    "RAZ",  1,      1,      0,      0},
4799         {"FN"                          ,        0,      3,      377,    "RO",   0,      0,      0ull,   0ull},
4800         {"DN"                          ,        3,      5,      377,    "RO",   0,      0,      31ull,  31ull},
4801         {"BN"                          ,        8,      8,      377,    "RO",   0,      1,      17ull,  0},
4802         {"W64"                         ,        16,     1,      377,    "RO",   0,      0,      1ull,   1ull},
4803         {"M133"                        ,        17,     1,      377,    "RO",   0,      0,      1ull,   1ull},
4804         {"SCD"                         ,        18,     1,      377,    "R/W1C",        0,      1,      0ull,   0},
4805         {"USC"                         ,        19,     1,      377,    "R/W1C",        0,      1,      0ull,   0},
4806         {"DC"                          ,        20,     1,      377,    "RO",   0,      0,      0ull,   0ull},
4807         {"MMRBCD"                      ,        21,     2,      377,    "RO",   0,      0,      2ull,   2ull},
4808         {"MOSTD"                       ,        23,     3,      377,    "RO",   0,      0,      3ull,   3ull},
4809         {"MCRSD"                       ,        26,     3,      377,    "RO",   0,      0,      7ull,   7ull},
4810         {"SCEMR"                       ,        29,     1,      377,    "R/W1C",        0,      1,      0ull,   0},
4811         {"RESERVED_30_31"              ,        30,     2,      377,    "RAZ",  1,      1,      0,      0},
4812         {"PMCID"                       ,        0,      8,      378,    "RO",   0,      0,      1ull,   1ull},
4813         {"NCP"                         ,        8,      8,      378,    "RO",   0,      0,      240ull, 240ull},
4814         {"PCIMIV"                      ,        16,     3,      378,    "RO",   0,      0,      2ull,   2ull},
4815         {"PMEC"                        ,        19,     1,      378,    "RO",   0,      0,      0ull,   0ull},
4816         {"RESERVED_20_20"              ,        20,     1,      378,    "RAZ",  1,      1,      0,      0},
4817         {"DSI"                         ,        21,     1,      378,    "RO",   0,      0,      0ull,   0ull},
4818         {"AUXC"                        ,        22,     3,      378,    "RO",   0,      0,      0ull,   0ull},
4819         {"D1S"                         ,        25,     1,      378,    "RO",   0,      0,      0ull,   0ull},
4820         {"D2S"                         ,        26,     1,      378,    "RO",   0,      0,      0ull,   0ull},
4821         {"PMES"                        ,        27,     5,      378,    "RO",   0,      0,      0ull,   0ull},
4822         {"PS"                          ,        0,      2,      379,    "R/W",  0,      0,      0ull,   0ull},
4823         {"RESERVED_2_7"                ,        2,      6,      379,    "RAZ",  1,      1,      0,      0},
4824         {"PMEENS"                      ,        8,      1,      379,    "R/W",  0,      0,      0ull,   0ull},
4825         {"PMDS"                        ,        9,      4,      379,    "R/W",  0,      0,      0ull,   0ull},
4826         {"PMEDSIA"                     ,        13,     2,      379,    "RO",   0,      0,      0ull,   0ull},
4827         {"PMESS"                       ,        15,     1,      379,    "R/W1C",        0,      0,      0ull,   0ull},
4828         {"RESERVED_16_21"              ,        16,     6,      379,    "RAZ",  1,      1,      0,      0},
4829         {"BD3H"                        ,        22,     1,      379,    "RO",   0,      0,      0ull,   0ull},
4830         {"BPCCEN"                      ,        23,     1,      379,    "RO",   0,      0,      0ull,   0ull},
4831         {"PMDIA"                       ,        24,     8,      379,    "RO",   0,      0,      0ull,   0ull},
4832         {"MSICID"                      ,        0,      8,      380,    "RO",   0,      0,      5ull,   5ull},
4833         {"NCP"                         ,        8,      8,      380,    "RO",   0,      0,      0ull,   0ull},
4834         {"MSIEN"                       ,        16,     1,      380,    "R/W",  0,      0,      0ull,   0ull},
4835         {"MMC"                         ,        17,     3,      380,    "RO",   0,      0,      0ull,   0ull},
4836         {"MME"                         ,        20,     3,      380,    "R/W",  0,      0,      0ull,   0ull},
4837         {"M64"                         ,        23,     1,      380,    "RO",   0,      0,      1ull,   1ull},
4838         {"RESERVED_24_31"              ,        24,     8,      380,    "RAZ",  1,      1,      0,      0},
4839         {"RESERVED_0_1"                ,        0,      2,      381,    "RAZ",  1,      1,      0,      0},
4840         {"MSI31T2"                     ,        2,      30,     381,    "R/W",  0,      1,      0ull,   0},
4841         {"MSI"                         ,        0,      32,     382,    "R/W",  0,      1,      0ull,   0},
4842         {"MSIMD"                       ,        0,      16,     383,    "R/W",  0,      1,      0ull,   0},
4843         {"RESERVED_16_31"              ,        16,     16,     383,    "RAZ",  1,      1,      0,      0},
4844         {"BAR2_CAX"                    ,        0,      1,      384,    "R/W",  0,      0,      0ull,   0ull},
4845         {"BAR2_ESX"                    ,        1,      2,      384,    "R/W",  0,      1,      0ull,   0},
4846         {"BAR2_ENB"                    ,        3,      1,      384,    "R/W",  0,      0,      0ull,   1ull},
4847         {"TSR_HWM"                     ,        4,      3,      384,    "R/W",  0,      1,      1ull,   0},
4848         {"PMO_FPC"                     ,        7,      3,      384,    "R/W",  0,      0,      0ull,   0ull},
4849         {"PMO_AMOD"                    ,        10,     1,      384,    "R/W",  0,      0,      0ull,   0ull},
4850         {"B12_BIST"                    ,        11,     1,      384,    "RO",   0,      0,      0ull,   0ull},
4851         {"AP_64AD"                     ,        12,     1,      384,    "RO",   1,      1,      0,      0},
4852         {"AP_PCIX"                     ,        13,     1,      384,    "RO",   1,      1,      0,      0},
4853         {"RESERVED_14_14"              ,        14,     1,      384,    "RAZ",  0,      0,      0ull,   0ull},
4854         {"EN_WFILT"                    ,        15,     1,      384,    "R/W",  0,      0,      0ull,   1ull},
4855         {"SCM"                         ,        16,     1,      384,    "RO",   0,      1,      0ull,   0},
4856         {"SCMTYP"                      ,        17,     1,      384,    "RO",   0,      1,      0ull,   0},
4857         {"BAR2PRES"                    ,        18,     1,      384,    "R/W",  1,      1,      0,      0},
4858         {"ERST_N"                      ,        19,     1,      384,    "RO",   0,      0,      1ull,   1ull},
4859         {"RESERVED_20_31"              ,        20,     12,     384,    "RAZ",  1,      1,      0,      0},
4860         {"INC_VAL"                     ,        0,      16,     385,    "R/W",  0,      1,      0ull,   0},
4861         {"RESERVED_16_31"              ,        16,     16,     385,    "RAZ",  1,      1,      0,      0},
4862         {"DMA_CNT"                     ,        0,      32,     386,    "R/W",  0,      0,      0ull,   0ull},
4863         {"PKT_CNT"                     ,        0,      32,     387,    "R/W",  0,      1,      0ull,   0},
4864         {"DMA_TIME"                    ,        0,      32,     388,    "R/W",  0,      1,      0ull,   0},
4865         {"ICNT"                        ,        0,      32,     389,    "RO",   0,      0,      0ull,   0ull},
4866         {"ITR_WABT"                    ,        0,      1,      390,    "R/W",  0,      1,      0ull,   0},
4867         {"IMR_WABT"                    ,        1,      1,      390,    "R/W",  0,      1,      0ull,   0},
4868         {"IMR_WTTO"                    ,        2,      1,      390,    "R/W",  0,      1,      0ull,   0},
4869         {"ITR_ABT"                     ,        3,      1,      390,    "R/W",  0,      1,      0ull,   0},
4870         {"IMR_ABT"                     ,        4,      1,      390,    "R/W",  0,      1,      0ull,   0},
4871         {"IMR_TTO"                     ,        5,      1,      390,    "R/W",  0,      1,      0ull,   0},
4872         {"IMSI_PER"                    ,        6,      1,      390,    "R/W",  0,      1,      0ull,   0},
4873         {"IMSI_TABT"                   ,        7,      1,      390,    "R/W",  0,      1,      0ull,   0},
4874         {"IMSI_MABT"                   ,        8,      1,      390,    "R/W",  0,      1,      0ull,   0},
4875         {"IMSC_MSG"                    ,        9,      1,      390,    "R/W",  0,      1,      0ull,   0},
4876         {"ITSR_ABT"                    ,        10,     1,      390,    "R/W",  0,      1,      0ull,   0},
4877         {"ISERR"                       ,        11,     1,      390,    "R/W",  0,      1,      0ull,   0},
4878         {"IAPERR"                      ,        12,     1,      390,    "R/W",  0,      1,      0ull,   0},
4879         {"IDPERR"                      ,        13,     1,      390,    "R/W",  0,      1,      0ull,   0},
4880         {"ILL_RWR"                     ,        14,     1,      390,    "R/W",  0,      1,      0ull,   0},
4881         {"ILL_RRD"                     ,        15,     1,      390,    "R/W",  0,      1,      0ull,   0},
4882         {"IRSL_INT"                    ,        16,     1,      390,    "R/W",  0,      1,      0ull,   0},
4883         {"IPCNT0"                      ,        17,     1,      390,    "R/W",  0,      1,      0ull,   0},
4884         {"IPCNT1"                      ,        18,     1,      390,    "R/W",  0,      1,      0ull,   0},
4885         {"IPCNT2"                      ,        19,     1,      390,    "R/W",  0,      1,      0ull,   0},
4886         {"IPCNT3"                      ,        20,     1,      390,    "R/W",  0,      1,      0ull,   0},
4887         {"IPTIME0"                     ,        21,     1,      390,    "R/W",  0,      1,      0ull,   0},
4888         {"IPTIME1"                     ,        22,     1,      390,    "R/W",  0,      1,      0ull,   0},
4889         {"IPTIME2"                     ,        23,     1,      390,    "R/W",  0,      1,      0ull,   0},
4890         {"IPTIME3"                     ,        24,     1,      390,    "R/W",  0,      1,      0ull,   0},
4891         {"IDCNT0"                      ,        25,     1,      390,    "R/W",  0,      1,      0ull,   0},
4892         {"IDCNT1"                      ,        26,     1,      390,    "R/W",  0,      1,      0ull,   0},
4893         {"IDTIME0"                     ,        27,     1,      390,    "R/W",  0,      1,      0ull,   0},
4894         {"IDTIME1"                     ,        28,     1,      390,    "R/W",  0,      1,      0ull,   0},
4895         {"DMA0_FI"                     ,        29,     1,      390,    "R/W",  0,      1,      0ull,   0},
4896         {"DMA1_FI"                     ,        30,     1,      390,    "R/W",  0,      1,      0ull,   0},
4897         {"WIN_WR"                      ,        31,     1,      390,    "R/W",  0,      1,      0ull,   0},
4898         {"ILL_WR"                      ,        32,     1,      390,    "R/W",  0,      1,      0ull,   0},
4899         {"ILL_RD"                      ,        33,     1,      390,    "R/W",  0,      1,      0ull,   0},
4900         {"RESERVED_34_63"              ,        34,     30,     390,    "RAZ",  1,      1,      0,      0},
4901         {"RTR_WABT"                    ,        0,      1,      391,    "R/W",  0,      1,      0ull,   0},
4902         {"RMR_WABT"                    ,        1,      1,      391,    "R/W",  0,      1,      0ull,   0},
4903         {"RMR_WTTO"                    ,        2,      1,      391,    "R/W",  0,      1,      0ull,   0},
4904         {"RTR_ABT"                     ,        3,      1,      391,    "R/W",  0,      1,      0ull,   0},
4905         {"RMR_ABT"                     ,        4,      1,      391,    "R/W",  0,      1,      0ull,   0},
4906         {"RMR_TTO"                     ,        5,      1,      391,    "R/W",  0,      1,      0ull,   0},
4907         {"RMSI_PER"                    ,        6,      1,      391,    "R/W",  0,      1,      0ull,   0},
4908         {"RMSI_TABT"                   ,        7,      1,      391,    "R/W",  0,      1,      0ull,   0},
4909         {"RMSI_MABT"                   ,        8,      1,      391,    "R/W",  0,      1,      0ull,   0},
4910         {"RMSC_MSG"                    ,        9,      1,      391,    "R/W",  0,      1,      0ull,   0},
4911         {"RTSR_ABT"                    ,        10,     1,      391,    "R/W",  0,      1,      0ull,   0},
4912         {"RSERR"                       ,        11,     1,      391,    "R/W",  0,      1,      0ull,   0},
4913         {"RAPERR"                      ,        12,     1,      391,    "R/W",  0,      1,      0ull,   0},
4914         {"RDPERR"                      ,        13,     1,      391,    "R/W",  0,      1,      0ull,   0},
4915         {"ILL_RWR"                     ,        14,     1,      391,    "R/W",  0,      1,      0ull,   0},
4916         {"ILL_RRD"                     ,        15,     1,      391,    "R/W",  0,      1,      0ull,   0},
4917         {"RRSL_INT"                    ,        16,     1,      391,    "R/W",  0,      1,      0ull,   0},
4918         {"RPCNT0"                      ,        17,     1,      391,    "R/W",  0,      1,      0ull,   0},
4919         {"RPCNT1"                      ,        18,     1,      391,    "R/W",  0,      1,      0ull,   0},
4920         {"RPCNT2"                      ,        19,     1,      391,    "R/W",  0,      1,      0ull,   0},
4921         {"RPCNT3"                      ,        20,     1,      391,    "R/W",  0,      1,      0ull,   0},
4922         {"RPTIME0"                     ,        21,     1,      391,    "R/W",  0,      1,      0ull,   0},
4923         {"RPTIME1"                     ,        22,     1,      391,    "R/W",  0,      1,      0ull,   0},
4924         {"RPTIME2"                     ,        23,     1,      391,    "R/W",  0,      1,      0ull,   0},
4925         {"RPTIME3"                     ,        24,     1,      391,    "R/W",  0,      1,      0ull,   0},
4926         {"RDCNT0"                      ,        25,     1,      391,    "R/W",  0,      1,      0ull,   0},
4927         {"RDCNT1"                      ,        26,     1,      391,    "R/W",  0,      1,      0ull,   0},
4928         {"RDTIME0"                     ,        27,     1,      391,    "R/W",  0,      1,      0ull,   0},
4929         {"RDTIME1"                     ,        28,     1,      391,    "R/W",  0,      1,      0ull,   0},
4930         {"DMA0_FI"                     ,        29,     1,      391,    "R/W",  0,      1,      0ull,   0},
4931         {"DMA1_FI"                     ,        30,     1,      391,    "R/W",  0,      1,      0ull,   0},
4932         {"WIN_WR"                      ,        31,     1,      391,    "R/W",  0,      1,      0ull,   0},
4933         {"ILL_WR"                      ,        32,     1,      391,    "R/W",  0,      1,      0ull,   0},
4934         {"ILL_RD"                      ,        33,     1,      391,    "R/W",  0,      1,      0ull,   0},
4935         {"RESERVED_34_63"              ,        34,     30,     391,    "RAZ",  1,      1,      0,      0},
4936         {"TR_WABT"                     ,        0,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4937         {"MR_WABT"                     ,        1,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4938         {"MR_WTTO"                     ,        2,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4939         {"TR_ABT"                      ,        3,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4940         {"MR_ABT"                      ,        4,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4941         {"MR_TTO"                      ,        5,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4942         {"MSI_PER"                     ,        6,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4943         {"MSI_TABT"                    ,        7,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4944         {"MSI_MABT"                    ,        8,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4945         {"MSC_MSG"                     ,        9,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4946         {"TSR_ABT"                     ,        10,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4947         {"SERR"                        ,        11,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4948         {"APERR"                       ,        12,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4949         {"DPERR"                       ,        13,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4950         {"ILL_RWR"                     ,        14,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4951         {"ILL_RRD"                     ,        15,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4952         {"RSL_INT"                     ,        16,     1,      392,    "RO",   0,      0,      0ull,   0ull},
4953         {"PCNT0"                       ,        17,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4954         {"PCNT1"                       ,        18,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4955         {"PCNT2"                       ,        19,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4956         {"PCNT3"                       ,        20,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4957         {"PTIME0"                      ,        21,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4958         {"PTIME1"                      ,        22,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4959         {"PTIME2"                      ,        23,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4960         {"PTIME3"                      ,        24,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4961         {"DCNT0"                       ,        25,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4962         {"DCNT1"                       ,        26,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4963         {"DTIME0"                      ,        27,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4964         {"DTIME1"                      ,        28,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4965         {"DMA0_FI"                     ,        29,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4966         {"DMA1_FI"                     ,        30,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4967         {"WIN_WR"                      ,        31,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4968         {"ILL_WR"                      ,        32,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4969         {"ILL_RD"                      ,        33,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
4970         {"RESERVED_34_63"              ,        34,     30,     392,    "RAZ",  1,      1,      0,      0},
4971         {"TR_WABT"                     ,        0,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4972         {"MR_WABT"                     ,        1,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4973         {"MR_WTTO"                     ,        2,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4974         {"TR_ABT"                      ,        3,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4975         {"MR_ABT"                      ,        4,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4976         {"MR_TTO"                      ,        5,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4977         {"MSI_PER"                     ,        6,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4978         {"MSI_TABT"                    ,        7,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4979         {"MSI_MABT"                    ,        8,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4980         {"MSC_MSG"                     ,        9,      1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4981         {"TSR_ABT"                     ,        10,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4982         {"SERR"                        ,        11,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4983         {"APERR"                       ,        12,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4984         {"DPERR"                       ,        13,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4985         {"ILL_RWR"                     ,        14,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4986         {"ILL_RRD"                     ,        15,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4987         {"RSL_INT"                     ,        16,     1,      393,    "RO",   0,      0,      0ull,   0ull},
4988         {"PCNT0"                       ,        17,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4989         {"PCNT1"                       ,        18,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4990         {"PCNT2"                       ,        19,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4991         {"PCNT3"                       ,        20,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4992         {"PTIME0"                      ,        21,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4993         {"PTIME1"                      ,        22,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4994         {"PTIME2"                      ,        23,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4995         {"PTIME3"                      ,        24,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4996         {"DCNT0"                       ,        25,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4997         {"DCNT1"                       ,        26,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4998         {"DTIME0"                      ,        27,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
4999         {"DTIME1"                      ,        28,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
5000         {"DMA0_FI"                     ,        29,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
5001         {"DMA1_FI"                     ,        30,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
5002         {"WIN_WR"                      ,        31,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
5003         {"ILL_WR"                      ,        32,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
5004         {"ILL_RD"                      ,        33,     1,      393,    "R/W1C",        0,      0,      0ull,   0ull},
5005         {"RESERVED_34_63"              ,        34,     30,     393,    "RAZ",  1,      1,      0,      0},
5006         {"INTR"                        ,        0,      6,      394,    "WO",   0,      1,      0ull,   0},
5007         {"RESERVED_6_31"               ,        6,      26,     394,    "R/W",  1,      1,      0,      0},
5008         {"PTR_CNT"                     ,        0,      16,     395,    "R/W",  0,      1,      0ull,   0},
5009         {"PKT_CNT"                     ,        16,     16,     395,    "R/W",  0,      1,      0ull,   0},
5010         {"PKT_CNT"                     ,        0,      32,     396,    "RO",   0,      0,      0ull,   0ull},
5011         {"PKT_CNT"                     ,        0,      32,     397,    "R/W",  0,      1,      0ull,   0},
5012         {"PKT_TIME"                    ,        0,      32,     398,    "R/W",  0,      1,      0ull,   0},
5013         {"PREFETCH"                    ,        0,      3,      399,    "R/W",  0,      0,      0ull,   2ull},
5014         {"MIN_DATA"                    ,        3,      6,      399,    "R/W",  0,      0,      0ull,   4ull},
5015         {"RESERVED_9_31"               ,        9,      23,     399,    "RAZ",  1,      1,      0,      0},
5016         {"PREFETCH"                    ,        0,      3,      400,    "R/W",  0,      0,      0ull,   3ull},
5017         {"MIN_DATA"                    ,        3,      6,      400,    "R/W",  0,      0,      0ull,   6ull},
5018         {"RESERVED_9_31"               ,        9,      23,     400,    "RAZ",  1,      1,      0,      0},
5019         {"PREFETCH"                    ,        0,      3,      401,    "R/W",  0,      0,      0ull,   3ull},
5020         {"MIN_DATA"                    ,        3,      6,      401,    "R/W",  0,      0,      0ull,   6ull},
5021         {"RESERVED_9_31"               ,        9,      23,     401,    "RAZ",  1,      1,      0,      0},
5022         {"CNT"                         ,        0,      31,     402,    "R/W",  0,      0,      10000ull,       10000ull},
5023         {"ENB"                         ,        31,     1,      402,    "R/W",  0,      0,      0ull,   1ull},
5024         {"RESERVED_32_63"              ,        32,     32,     402,    "RAZ",  1,      1,      0,      0},
5025         {"SCM"                         ,        0,      32,     403,    "RO",   0,      1,      0ull,   0},
5026         {"RESERVED_32_63"              ,        32,     32,     403,    "RAZ",  1,      1,      0,      0},
5027         {"TSR"                         ,        0,      36,     404,    "RO",   0,      1,      0ull,   0},
5028         {"RESERVED_36_63"              ,        36,     28,     404,    "RAZ",  1,      1,      0,      0},
5029         {"RESERVED_0_2"                ,        0,      3,      405,    "RAZ",  1,      1,      0,      0},
5030         {"RD_ADDR"                     ,        3,      45,     405,    "R/W",  0,      1,      0ull,   0},
5031         {"IOBIT"                       ,        48,     1,      405,    "RAZ",  0,      0,      0ull,   0ull},
5032         {"RESERVED_49_63"              ,        49,     15,     405,    "RAZ",  1,      1,      0,      0},
5033         {"RD_DATA"                     ,        0,      64,     406,    "RO",   0,      1,      0ull,   0},
5034         {"RESERVED_0_2"                ,        0,      3,      407,    "RAZ",  1,      1,      0,      0},
5035         {"WR_ADDR"                     ,        3,      45,     407,    "R/W",  0,      1,      0ull,   0},
5036         {"IOBIT"                       ,        48,     1,      407,    "RAZ",  0,      0,      0ull,   0ull},
5037         {"RESERVED_49_63"              ,        49,     15,     407,    "RAZ",  1,      1,      0,      0},
5038         {"WR_DATA"                     ,        0,      64,     408,    "R/W",  0,      1,      0ull,   0},
5039         {"WR_MASK"                     ,        0,      8,      409,    "R/W",  0,      0,      0ull,   0ull},
5040         {"RESERVED_8_63"               ,        8,      56,     409,    "RAZ",  1,      1,      0,      0},
5041         {"LOWATER"                     ,        0,      5,      410,    "R/W",  0,      0,      4ull,   4ull},
5042         {"RESERVED_5_7"                ,        5,      3,      410,    "RAZ",  0,      1,      0ull,   0},
5043         {"HIWATER"                     ,        8,      5,      410,    "R/W",  0,      0,      24ull,  24ull},
5044         {"RESERVED_13_62"              ,        13,     50,     410,    "RAZ",  0,      1,      0ull,   0},
5045         {"BCKPRS"                      ,        63,     1,      410,    "RO",   0,      0,      0ull,   0ull},
5046         {"BIST"                        ,        0,      18,     411,    "RO",   0,      0,      0ull,   0ull},
5047         {"RESERVED_18_63"              ,        18,     46,     411,    "RAZ",  1,      1,      0,      0},
5048         {"REFLECT"                     ,        0,      1,      412,    "R/W",  0,      0,      1ull,   1ull},
5049         {"INVRES"                      ,        1,      1,      412,    "R/W",  0,      0,      1ull,   1ull},
5050         {"RESERVED_2_63"               ,        2,      62,     412,    "RAZ",  1,      1,      0,      0},
5051         {"IV"                          ,        0,      32,     413,    "R/W",  0,      0,      1185899593ull,  1185899593ull},
5052         {"RESERVED_32_63"              ,        32,     32,     413,    "RAZ",  1,      1,      0,      0},
5053         {"DPRT"                        ,        0,      16,     414,    "R/W",  0,      0,      0ull,   0ull},
5054         {"UDP"                         ,        16,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
5055         {"TCP"                         ,        17,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
5056         {"RESERVED_18_63"              ,        18,     46,     414,    "RAZ",  1,      1,      0,      0},
5057         {"NIP_SHF"                     ,        0,      3,      415,    "R/W",  0,      0,      0ull,   0ull},
5058         {"RESERVED_3_7"                ,        3,      5,      415,    "RAZ",  1,      1,      0,      0},
5059         {"RAW_SHF"                     ,        8,      3,      415,    "R/W",  0,      0,      0ull,   0ull},
5060         {"RESERVED_11_15"              ,        11,     5,      415,    "RAZ",  1,      1,      0,      0},
5061         {"MAX_L2"                      ,        16,     1,      415,    "R/W",  0,      0,      0ull,   0ull},
5062         {"IP6_UDP"                     ,        17,     1,      415,    "R/W",  0,      0,      1ull,   1ull},
5063         {"TAG_SYN"                     ,        18,     1,      415,    "R/W",  0,      0,      0ull,   0ull},
5064         {"RESERVED_19_63"              ,        19,     45,     415,    "RAZ",  1,      1,      0,      0},
5065         {"IP_CHK"                      ,        0,      1,      416,    "R/W",  0,      0,      1ull,   1ull},
5066         {"IP_MAL"                      ,        1,      1,      416,    "R/W",  0,      0,      1ull,   1ull},
5067         {"IP_HOP"                      ,        2,      1,      416,    "R/W",  0,      0,      1ull,   1ull},
5068         {"IP4_OPTS"                    ,        3,      1,      416,    "R/W",  0,      0,      1ull,   1ull},
5069         {"IP6_EEXT"                    ,        4,      2,      416,    "R/W",  0,      0,      1ull,   3ull},
5070         {"RESERVED_6_7"                ,        6,      2,      416,    "RAZ",  0,      1,      0ull,   0},
5071         {"L4_MAL"                      ,        8,      1,      416,    "R/W",  0,      0,      1ull,   1ull},
5072         {"L4_PRT"                      ,        9,      1,      416,    "R/W",  0,      0,      1ull,   1ull},
5073         {"L4_CHK"                      ,        10,     1,      416,    "R/W",  0,      0,      1ull,   1ull},
5074         {"L4_LEN"                      ,        11,     1,      416,    "R/W",  0,      0,      1ull,   1ull},
5075         {"TCP_FLAG"                    ,        12,     1,      416,    "R/W",  0,      0,      1ull,   1ull},
5076         {"L2_MAL"                      ,        13,     1,      416,    "R/W",  0,      0,      1ull,   1ull},
5077         {"VS_QOS"                      ,        14,     1,      416,    "R/W",  0,      0,      0ull,   0ull},
5078         {"VS_WQE"                      ,        15,     1,      416,    "R/W",  0,      0,      0ull,   0ull},
5079         {"IGNRS"                       ,        16,     1,      416,    "R/W",  0,      0,      0ull,   0ull},
5080         {"RESERVED_17_63"              ,        17,     47,     416,    "RAZ",  0,      1,      0ull,   0},
5081         {"PKTDRP"                      ,        0,      1,      417,    "R/W",  0,      0,      0ull,   0ull},
5082         {"CRCERR"                      ,        1,      1,      417,    "R/W",  0,      0,      0ull,   0ull},
5083         {"BCKPRS"                      ,        2,      1,      417,    "R/W",  0,      0,      0ull,   0ull},
5084         {"PRTNXA"                      ,        3,      1,      417,    "R/W",  0,      0,      0ull,   0ull},
5085         {"BADTAG"                      ,        4,      1,      417,    "R/W",  0,      0,      0ull,   0ull},
5086         {"SKPRUNT"                     ,        5,      1,      417,    "R/W",  0,      0,      0ull,   0ull},
5087         {"TODOOVR"                     ,        6,      1,      417,    "R/W",  0,      0,      0ull,   0ull},
5088         {"FEPERR"                      ,        7,      1,      417,    "R/W",  0,      0,      0ull,   0ull},
5089         {"BEPERR"                      ,        8,      1,      417,    "R/W",  0,      0,      0ull,   0ull},
5090         {"RESERVED_9_63"               ,        9,      55,     417,    "RAZ",  1,      1,      0,      0},
5091         {"PKTDRP"                      ,        0,      1,      418,    "R/W1C",        0,      0,      0ull,   0ull},
5092         {"CRCERR"                      ,        1,      1,      418,    "R/W1C",        0,      0,      0ull,   0ull},
5093         {"BCKPRS"                      ,        2,      1,      418,    "R/W1C",        0,      0,      0ull,   0ull},
5094         {"PRTNXA"                      ,        3,      1,      418,    "R/W1C",        0,      0,      0ull,   0ull},
5095         {"BADTAG"                      ,        4,      1,      418,    "R/W1C",        0,      0,      0ull,   0ull},
5096         {"SKPRUNT"                     ,        5,      1,      418,    "R/W1C",        0,      0,      0ull,   0ull},
5097         {"TODOOVR"                     ,        6,      1,      418,    "R/W1C",        0,      0,      0ull,   0ull},
5098         {"FEPERR"                      ,        7,      1,      418,    "R/W1C",        0,      0,      0ull,   0ull},
5099         {"BEPERR"                      ,        8,      1,      418,    "R/W1C",        0,      0,      0ull,   0ull},
5100         {"RESERVED_9_63"               ,        9,      55,     418,    "RAZ",  1,      1,      0,      0},
5101         {"OFFSET"                      ,        0,      3,      419,    "R/W",  0,      0,      0ull,   0ull},
5102         {"RESERVED_3_63"               ,        3,      61,     419,    "RAZ",  1,      1,      0,      0},
5103         {"SKIP"                        ,        0,      7,      420,    "R/W",  0,      0,      0ull,   0ull},
5104         {"RESERVED_7_7"                ,        7,      1,      420,    "RAZ",  1,      1,      0,      0},
5105         {"MODE"                        ,        8,      2,      420,    "R/W",  0,      0,      0ull,   0ull},
5106         {"RESERVED_10_11"              ,        10,     2,      420,    "RAZ",  1,      1,      0,      0},
5107         {"CRC_EN"                      ,        12,     1,      420,    "R/W",  0,      0,      1ull,   1ull},
5108         {"RESERVED_13_15"              ,        13,     3,      420,    "RAZ",  1,      1,      0,      0},
5109         {"QOS_VLAN"                    ,        16,     1,      420,    "R/W",  0,      0,      0ull,   0ull},
5110         {"QOS_DIFF"                    ,        17,     1,      420,    "R/W",  0,      0,      0ull,   0ull},
5111         {"RESERVED_18_19"              ,        18,     2,      420,    "RAZ",  0,      0,      0ull,   0ull},
5112         {"QOS_WAT"                     ,        20,     4,      420,    "R/W",  0,      0,      0ull,   0ull},
5113         {"QOS"                         ,        24,     3,      420,    "R/W",  0,      0,      0ull,   0ull},
5114         {"RESERVED_27_27"              ,        27,     1,      420,    "RAZ",  1,      1,      0,      0},
5115         {"GRP_WAT"                     ,        28,     4,      420,    "R/W",  0,      0,      0ull,   0ull},
5116         {"INST_HDR"                    ,        32,     1,      420,    "R/W",  0,      0,      0ull,   0ull},
5117         {"DYN_RS"                      ,        33,     1,      420,    "R/W",  0,      0,      0ull,   0ull},
5118         {"TAG_INC"                     ,        34,     2,      420,    "R/W",  0,      0,      0ull,   0ull},
5119         {"RAWDRP"                      ,        36,     1,      420,    "R/W",  0,      0,      0ull,   0ull},
5120         {"RESERVED_37_63"              ,        37,     27,     420,    "RAZ",  1,      1,      0,      0},
5121         {"GRP"                         ,        0,      4,      421,    "R/W",  0,      0,      0ull,   0ull},
5122         {"NON_TAG_TYPE"                ,        4,      2,      421,    "R/W",  0,      0,      0ull,   0ull},
5123         {"IP4_TAG_TYPE"                ,        6,      2,      421,    "R/W",  0,      0,      0ull,   0ull},
5124         {"IP6_TAG_TYPE"                ,        8,      2,      421,    "R/W",  0,      0,      0ull,   0ull},
5125         {"TCP4_TAG_TYPE"               ,        10,     2,      421,    "R/W",  0,      0,      0ull,   0ull},
5126         {"TCP6_TAG_TYPE"               ,        12,     2,      421,    "R/W",  0,      0,      0ull,   0ull},
5127         {"IP4_SRC_FLAG"                ,        14,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5128         {"IP6_SRC_FLAG"                ,        15,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5129         {"IP4_DST_FLAG"                ,        16,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5130         {"IP6_DST_FLAG"                ,        17,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5131         {"IP4_PCTL_FLAG"               ,        18,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5132         {"IP6_NXTH_FLAG"               ,        19,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5133         {"IP4_SPRT_FLAG"               ,        20,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5134         {"IP6_SPRT_FLAG"               ,        21,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5135         {"IP4_DPRT_FLAG"               ,        22,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5136         {"IP6_DPRT_FLAG"               ,        23,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5137         {"INC_PRT_FLAG"                ,        24,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5138         {"INC_VLAN"                    ,        25,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5139         {"INC_VS"                      ,        26,     2,      421,    "R/W",  0,      0,      0ull,   0ull},
5140         {"TAG_MODE"                    ,        28,     2,      421,    "R/W",  0,      0,      0ull,   0ull},
5141         {"RESERVED_30_30"              ,        30,     1,      421,    "RAZ",  0,      0,      0ull,   0ull},
5142         {"GRPTAG"                      ,        31,     1,      421,    "R/W",  0,      0,      0ull,   0ull},
5143         {"GRPTAGMASK"                  ,        32,     4,      421,    "R/W",  0,      0,      0ull,   0ull},
5144         {"GRPTAGBASE"                  ,        36,     4,      421,    "R/W",  0,      0,      0ull,   0ull},
5145         {"RESERVED_40_63"              ,        40,     24,     421,    "RAZ",  1,      1,      0,      0},
5146         {"QOS"                         ,        0,      3,      422,    "R/W",  0,      0,      0ull,   0ull},
5147         {"RESERVED_3_63"               ,        3,      61,     422,    "RAZ",  1,      1,      0,      0},
5148         {"QOS"                         ,        0,      3,      423,    "R/W",  0,      0,      0ull,   0ull},
5149         {"RESERVED_3_63"               ,        3,      61,     423,    "RAZ",  1,      1,      0,      0},
5150         {"MATCH_VALUE"                 ,        0,      16,     424,    "R/W",  0,      0,      0ull,   0ull},
5151         {"MATCH_TYPE"                  ,        16,     2,      424,    "R/W",  0,      0,      0ull,   0ull},
5152         {"RESERVED_18_19"              ,        18,     2,      424,    "RAZ",  1,      1,      0,      0},
5153         {"QOS"                         ,        20,     3,      424,    "R/W",  0,      0,      0ull,   0ull},
5154         {"RESERVED_23_23"              ,        23,     1,      424,    "RAZ",  1,      1,      0,      0},
5155         {"GRP"                         ,        24,     4,      424,    "R/W",  0,      0,      0ull,   0ull},
5156         {"RESERVED_28_31"              ,        28,     4,      424,    "RAZ",  1,      1,      0,      0},
5157         {"MASK"                        ,        32,     16,     424,    "R/W",  0,      0,      0ull,   0ull},
5158         {"RESERVED_48_63"              ,        48,     16,     424,    "RAZ",  1,      1,      0,      0},
5159         {"WORD"                        ,        0,      56,     425,    "R/W",  0,      0,      0ull,   0ull},
5160         {"RESERVED_56_63"              ,        56,     8,      425,    "RAZ",  1,      1,      0,      0},
5161         {"DRP_OCTS"                    ,        0,      32,     426,    "R/W",  0,      1,      0ull,   0},
5162         {"DRP_PKTS"                    ,        32,     32,     426,    "R/W",  0,      1,      0ull,   0},
5163         {"OCTS"                        ,        0,      48,     427,    "R/W",  0,      1,      0ull,   0},
5164         {"RESERVED_48_63"              ,        48,     16,     427,    "RAZ",  1,      1,      0,      0},
5165         {"RAW"                         ,        0,      32,     428,    "R/W",  0,      1,      0ull,   0},
5166         {"PKTS"                        ,        32,     32,     428,    "R/W",  0,      1,      0ull,   0},
5167         {"MCST"                        ,        0,      32,     429,    "R/W",  0,      1,      0ull,   0},
5168         {"BCST"                        ,        32,     32,     429,    "R/W",  0,      1,      0ull,   0},
5169         {"H64"                         ,        0,      32,     430,    "R/W",  0,      1,      0ull,   0},
5170         {"H65TO127"                    ,        32,     32,     430,    "R/W",  0,      1,      0ull,   0},
5171         {"H128TO255"                   ,        0,      32,     431,    "R/W",  0,      1,      0ull,   0},
5172         {"H256TO511"                   ,        32,     32,     431,    "R/W",  0,      1,      0ull,   0},
5173         {"H512TO1023"                  ,        0,      32,     432,    "R/W",  0,      1,      0ull,   0},
5174         {"H1024TO1518"                 ,        32,     32,     432,    "R/W",  0,      1,      0ull,   0},
5175         {"H1519"                       ,        0,      32,     433,    "R/W",  0,      1,      0ull,   0},
5176         {"FCS"                         ,        32,     32,     433,    "R/W",  0,      1,      0ull,   0},
5177         {"UNDERSZ"                     ,        0,      32,     434,    "R/W",  0,      1,      0ull,   0},
5178         {"FRAG"                        ,        32,     32,     434,    "R/W",  0,      1,      0ull,   0},
5179         {"OVERSZ"                      ,        0,      32,     435,    "R/W",  0,      1,      0ull,   0},
5180         {"JABBER"                      ,        32,     32,     435,    "R/W",  0,      1,      0ull,   0},
5181         {"RDCLR"                       ,        0,      1,      436,    "R/W",  0,      0,      1ull,   1ull},
5182         {"RESERVED_1_63"               ,        1,      63,     436,    "RAZ",  1,      1,      0,      0},
5183         {"ERRS"                        ,        0,      16,     437,    "R/W",  0,      1,      0ull,   0},
5184         {"RESERVED_16_63"              ,        16,     48,     437,    "RAZ",  1,      1,      0,      0},
5185         {"OCTS"                        ,        0,      48,     438,    "R/W",  0,      1,      0ull,   0},
5186         {"RESERVED_48_63"              ,        48,     16,     438,    "RAZ",  1,      1,      0,      0},
5187         {"PKTS"                        ,        0,      32,     439,    "R/W",  0,      1,      0ull,   0},
5188         {"RESERVED_32_63"              ,        32,     32,     439,    "RAZ",  1,      1,      0,      0},
5189         {"EN"                          ,        0,      8,      440,    "R/W",  0,      0,      0ull,   0ull},
5190         {"RESERVED_8_63"               ,        8,      56,     440,    "RAZ",  1,      1,      0,      0},
5191         {"MASK"                        ,        0,      16,     441,    "R/W",  0,      0,      0ull,   0ull},
5192         {"RESERVED_16_63"              ,        16,     48,     441,    "RAZ",  1,      1,      0,      0},
5193         {"SRC"                         ,        0,      16,     442,    "R/W",  0,      0,      0ull,   0ull},
5194         {"DST"                         ,        16,     16,     442,    "R/W",  0,      0,      0ull,   0ull},
5195         {"RESERVED_32_63"              ,        32,     32,     442,    "RAZ",  1,      1,      0,      0},
5196         {"ENTRY"                       ,        0,      62,     443,    "RO",   1,      1,      0,      0},
5197         {"RESERVED_62_62"              ,        62,     1,      443,    "RAZ",  1,      1,      0,      0},
5198         {"VAL"                         ,        63,     1,      443,    "RO",   1,      1,      0,      0},
5199         {"COUNT"                       ,        0,      32,     444,    "R/W1C",        1,      0,      0,      0ull},
5200         {"RESERVED_32_63"              ,        32,     32,     444,    "RAZ",  1,      1,      0,      0},
5201         {"COUNT"                       ,        0,      48,     445,    "R/W1C",        1,      0,      0,      0ull},
5202         {"RESERVED_48_63"              ,        48,     16,     445,    "RAZ",  1,      1,      0,      0},
5203         {"SIZE"                        ,        0,      16,     446,    "RO",   1,      0,      0,      0ull},
5204         {"SEGS"                        ,        16,     6,      446,    "RO",   1,      0,      0,      0ull},
5205         {"CMD"                         ,        22,     14,     446,    "RO",   1,      0,      0,      0ull},
5206         {"FAU"                         ,        36,     28,     446,    "RO",   1,      0,      0,      0ull},
5207         {"PTR"                         ,        0,      40,     447,    "RO",   1,      0,      0,      0ull},
5208         {"SIZE"                        ,        40,     16,     447,    "RO",   1,      0,      0,      0ull},
5209         {"POOL"                        ,        56,     3,      447,    "RO",   1,      0,      0,      0ull},
5210         {"BACK"                        ,        59,     4,      447,    "RO",   1,      0,      0,      0ull},
5211         {"I"                           ,        63,     1,      447,    "RO",   1,      0,      0,      0ull},
5212         {"SIZE"                        ,        0,      16,     448,    "RO",   1,      0,      0,      0ull},
5213         {"SEGS"                        ,        16,     6,      448,    "RO",   1,      0,      0,      0ull},
5214         {"CMD"                         ,        22,     14,     448,    "RO",   1,      0,      0,      0ull},
5215         {"FAU"                         ,        36,     28,     448,    "RO",   1,      0,      0,      0ull},
5216         {"PTR"                         ,        0,      40,     449,    "RO",   1,      0,      0,      0ull},
5217         {"SIZE"                        ,        40,     16,     449,    "RO",   1,      0,      0,      0ull},
5218         {"POOL"                        ,        56,     3,      449,    "RO",   1,      0,      0,      0ull},
5219         {"BACK"                        ,        59,     4,      449,    "RO",   1,      0,      0,      0ull},
5220         {"I"                           ,        63,     1,      449,    "RO",   1,      0,      0,      0ull},
5221         {"DATA"                        ,        0,      64,     450,    "RO",   1,      0,      0,      0ull},
5222         {"WIDX2"                       ,        0,      17,     451,    "RO",   1,      0,      0,      0ull},
5223         {"RIDX2"                       ,        17,     17,     451,    "RO",   1,      0,      0,      0ull},
5224         {"WIDX"                        ,        34,     17,     451,    "RO",   1,      0,      0,      0ull},
5225         {"RESERVED_51_63"              ,        51,     13,     451,    "RAZ",  1,      0,      0,      0ull},
5226         {"RIDX"                        ,        0,      17,     452,    "RO",   1,      0,      0,      0ull},
5227         {"RESERVED_17_63"              ,        17,     47,     452,    "RAZ",  1,      0,      0,      0ull},
5228         {"PTR"                         ,        0,      40,     453,    "RO",   1,      0,      0,      0ull},
5229         {"SIZE"                        ,        40,     16,     453,    "RO",   1,      0,      0,      0ull},
5230         {"POOL"                        ,        56,     3,      453,    "RO",   1,      0,      0,      0ull},
5231         {"BACK"                        ,        59,     4,      453,    "RO",   1,      0,      0,      0ull},
5232         {"I"                           ,        63,     1,      453,    "RO",   1,      0,      0,      0ull},
5233         {"PTR"                         ,        0,      40,     454,    "RO",   1,      0,      0,      0ull},
5234         {"SIZE"                        ,        40,     16,     454,    "RO",   1,      0,      0,      0ull},
5235         {"POOL"                        ,        56,     3,      454,    "RO",   1,      0,      0,      0ull},
5236         {"BACK"                        ,        59,     4,      454,    "RO",   1,      0,      0,      0ull},
5237         {"I"                           ,        63,     1,      454,    "RO",   1,      0,      0,      0ull},
5238         {"DATA"                        ,        0,      64,     455,    "RO",   1,      0,      0,      0ull},
5239         {"MAJOR"                       ,        0,      4,      456,    "RO",   1,      0,      0,      0ull},
5240         {"MINOR"                       ,        4,      2,      456,    "RO",   1,      0,      0,      0ull},
5241         {"WAIT"                        ,        6,      1,      456,    "RO",   1,      0,      0,      0ull},
5242         {"QID_BASE"                    ,        7,      7,      456,    "RO",   1,      0,      0,      0ull},
5243         {"QID_OFF"                     ,        14,     3,      456,    "RO",   1,      0,      0,      0ull},
5244         {"QCB_RIDX"                    ,        17,     5,      456,    "RO",   1,      0,      0,      0ull},
5245         {"QOS"                         ,        22,     3,      456,    "RO",   1,      0,      0,      0ull},
5246         {"ACTIVE"                      ,        25,     1,      456,    "RO",   1,      0,      0,      0ull},
5247         {"CHK_MODE"                    ,        26,     1,      456,    "RO",   1,      0,      0,      0ull},
5248         {"RESERVED_27_27"              ,        27,     1,      456,    "RAZ",  1,      0,      0,      0ull},
5249         {"CBUF_FRE"                    ,        28,     1,      456,    "RO",   1,      0,      0,      0ull},
5250         {"XFER_DWR"                    ,        29,     1,      456,    "RO",   1,      0,      0,      0ull},
5251         {"XFER_WOR"                    ,        30,     1,      456,    "RO",   1,      0,      0,      0ull},
5252         {"UID"                         ,        31,     1,      456,    "RO",   1,      0,      0,      0ull},
5253         {"CMND_SIZ"                    ,        32,     16,     456,    "RO",   1,      0,      0,      0ull},
5254         {"DWRI_CNT"                    ,        48,     13,     456,    "RO",   1,      0,      0,      0ull},
5255         {"DWRI_LEN"                    ,        61,     1,      456,    "RO",   1,      0,      0,      0ull},
5256         {"DWRI_SOP"                    ,        62,     1,      456,    "RO",   1,      0,      0,      0ull},
5257         {"DWRI_MOD"                    ,        63,     1,      456,    "RO",   1,      0,      0,      0ull},
5258         {"DWRI_MOD"                    ,        0,      2,      457,    "RO",   1,      0,      0,      0ull},
5259         {"DWRI_UID"                    ,        2,      1,      457,    "RO",   1,      0,      0,      0ull},
5260         {"DWRI_CHK"                    ,        3,      1,      457,    "RO",   1,      0,      0,      0ull},
5261         {"WORK_MIN"                    ,        4,      3,      457,    "RO",   1,      0,      0,      0ull},
5262         {"STATIC_P"                    ,        7,      1,      457,    "RO",   1,      0,      0,      0ull},
5263         {"QID_OFFM"                    ,        8,      3,      457,    "RO",   1,      0,      0,      0ull},
5264         {"RESERVED_11_63"              ,        11,     53,     457,    "RAZ",  1,      0,      0,      0ull},
5265         {"SIZE"                        ,        0,      16,     458,    "RO",   1,      0,      0,      0ull},
5266         {"START"                       ,        16,     33,     458,    "RO",   1,      0,      0,      0ull},
5267         {"DWB"                         ,        49,     9,      458,    "RO",   1,      0,      0,      0ull},
5268         {"RESERVED_58_63"              ,        58,     6,      458,    "RAZ",  1,      0,      0,      0ull},
5269         {"QCB_RIDX"                    ,        0,      6,      459,    "RO",   1,      0,      0,      0ull},
5270         {"QCB_WIDX"                    ,        6,      6,      459,    "RO",   1,      0,      0,      0ull},
5271         {"BUF_PTR"                     ,        12,     33,     459,    "RO",   1,      0,      0,      0ull},
5272         {"BUF_SIZ"                     ,        45,     13,     459,    "RO",   1,      0,      0,      0ull},
5273         {"TAIL"                        ,        58,     1,      459,    "RO",   1,      0,      0,      0ull},
5274         {"QOS"                         ,        59,     5,      459,    "RO",   1,      0,      0,      0ull},
5275         {"QOS"                         ,        0,      3,      460,    "RO",   1,      0,      0,      0ull},
5276         {"STATIC_Q"                    ,        3,      1,      460,    "RO",   1,      0,      0,      0ull},
5277         {"S_TAIL"                      ,        4,      1,      460,    "RO",   1,      0,      0,      0ull},
5278         {"STATIC_P"                    ,        5,      1,      460,    "RO",   1,      0,      0,      0ull},
5279         {"RESERVED_6_7"                ,        6,      2,      460,    "RAZ",  1,      0,      0,      0ull},
5280         {"DOORBELL"                    ,        8,      20,     460,    "RO",   1,      0,      0,      0ull},
5281         {"RESERVED_28_63"              ,        28,     36,     460,    "RAZ",  1,      0,      0,      0ull},
5282         {"QUEUE"                       ,        0,      7,      461,    "R/W",  1,      0,      0,      0ull},
5283         {"PORT"                        ,        7,      6,      461,    "WR0",  1,      0,      0,      0ull},
5284         {"INDEX"                       ,        13,     3,      461,    "WR0",  1,      0,      0,      0ull},
5285         {"TAIL"                        ,        16,     1,      461,    "R/W",  1,      0,      0,      0ull},
5286         {"BUF_PTR"                     ,        17,     36,     461,    "R/W",  1,      0,      0,      0ull},
5287         {"QOS_MASK"                    ,        53,     8,      461,    "R/W",  1,      0,      0,      0ull},
5288         {"STATIC_Q"                    ,        61,     1,      461,    "WR0",  1,      0,      0,      0ull},
5289         {"STATIC_P"                    ,        62,     1,      461,    "WR0",  1,      0,      0,      0ull},
5290         {"S_TAIL"                      ,        63,     1,      461,    "WR0",  1,      0,      0,      0ull},
5291         {"QID"                         ,        0,      7,      462,    "R/W",  1,      0,      0,      0ull},
5292         {"PID"                         ,        7,      6,      462,    "WR0",  1,      0,      0,      0ull},
5293         {"RESERVED_13_52"              ,        13,     40,     462,    "RAZ",  1,      0,      0,      0ull},
5294         {"QOS_MASK"                    ,        53,     8,      462,    "R/W",  1,      0,      0,      0ull},
5295         {"RESERVED_61_63"              ,        61,     3,      462,    "RAZ",  1,      0,      0,      0ull},
5296         {"PSB"                         ,        0,      7,      463,    "RO",   1,      0,      0,      0ull},
5297         {"PDB"                         ,        7,      4,      463,    "RO",   1,      0,      0,      0ull},
5298         {"QCB"                         ,        11,     2,      463,    "RO",   1,      0,      0,      0ull},
5299         {"QSB"                         ,        13,     2,      463,    "RO",   1,      0,      0,      0ull},
5300         {"CHK"                         ,        15,     1,      463,    "RO",   1,      0,      0,      0ull},
5301         {"CRC"                         ,        16,     1,      463,    "RO",   1,      0,      0,      0ull},
5302         {"OUT"                         ,        17,     1,      463,    "RO",   1,      0,      0,      0ull},
5303         {"NCB"                         ,        18,     1,      463,    "RO",   1,      0,      0,      0ull},
5304         {"WIF"                         ,        19,     1,      463,    "RO",   1,      0,      0,      0ull},
5305         {"RIF"                         ,        20,     1,      463,    "RO",   1,      0,      0,      0ull},
5306         {"COUNT"                       ,        21,     1,      463,    "RO",   1,      0,      0,      0ull},
5307         {"PSB2"                        ,        22,     5,      463,    "RO",   1,      0,      0,      0ull},
5308         {"RESERVED_27_63"              ,        27,     37,     463,    "RAZ",  1,      0,      0,      0ull},
5309         {"SIZE"                        ,        0,      13,     464,    "R/W",  0,      0,      0ull,   0ull},
5310         {"RESERVED_13_19"              ,        13,     7,      464,    "RAZ",  0,      0,      0ull,   0ull},
5311         {"POOL"                        ,        20,     3,      464,    "R/W",  0,      0,      0ull,   0ull},
5312         {"RESERVED_23_63"              ,        23,     41,     464,    "RAZ",  1,      0,      0,      0ull},
5313         {"REFIN"                       ,        0,      1,      465,    "R/W",  0,      0,      1ull,   1ull},
5314         {"INVRES"                      ,        1,      1,      465,    "R/W",  0,      0,      1ull,   1ull},
5315         {"RESERVED_2_63"               ,        2,      62,     465,    "RAZ",  1,      1,      0,      0},
5316         {"ENABLE"                      ,        0,      32,     466,    "R/W",  0,      0,      0ull,   0ull},
5317         {"RESERVED_32_63"              ,        32,     32,     466,    "RAZ",  1,      0,      0,      0ull},
5318         {"IV"                          ,        0,      32,     467,    "R/W",  0,      0,      1185899593ull,  1185899593ull},
5319         {"RESERVED_32_63"              ,        32,     32,     467,    "RAZ",  1,      1,      0,      0},
5320         {"ASSERTS"                     ,        0,      17,     468,    "RO",   0,      0,      0ull,   0ull},
5321         {"RESERVED_17_63"              ,        17,     47,     468,    "RAZ",  1,      0,      0,      0ull},
5322         {"PARITY"                      ,        0,      1,      469,    "R/W1C",        0,      0,      0ull,   0ull},
5323         {"DOORBELL"                    ,        1,      1,      469,    "R/W1C",        0,      0,      0ull,   0ull},
5324         {"RESERVED_2_63"               ,        2,      62,     469,    "RAZ",  1,      0,      0,      0ull},
5325         {"ENA_PKO"                     ,        0,      1,      470,    "R/W",  0,      0,      0ull,   0ull},
5326         {"ENA_DWB"                     ,        1,      1,      470,    "R/W",  0,      0,      0ull,   0ull},
5327         {"STORE_BE"                    ,        2,      1,      470,    "R/W",  0,      0,      0ull,   0ull},
5328         {"RESET"                       ,        3,      1,      470,    "RAZ",  0,      0,      0ull,   0ull},
5329         {"RESERVED_4_63"               ,        4,      60,     470,    "RAZ",  1,      0,      0,      0ull},
5330         {"MODE0"                       ,        0,      3,      471,    "R/W",  0,      0,      0ull,   0ull},
5331         {"MODE1"                       ,        3,      3,      471,    "R/W",  0,      0,      0ull,   0ull},
5332         {"RESERVED_6_63"               ,        6,      58,     471,    "RAZ",  1,      0,      0,      0ull},
5333         {"PARITY"                      ,        0,      1,      472,    "R/W",  0,      0,      0ull,   0ull},
5334         {"DOORBELL"                    ,        1,      1,      472,    "R/W",  0,      0,      0ull,   0ull},
5335         {"RESERVED_2_63"               ,        2,      62,     472,    "RAZ",  1,      0,      0,      0ull},
5336         {"MODE"                        ,        0,      2,      473,    "R/W",  0,      0,      0ull,   0ull},
5337         {"RESERVED_2_63"               ,        2,      62,     473,    "RAZ",  1,      0,      0,      0ull},
5338         {"INDEX"                       ,        0,      8,      474,    "R/W",  0,      0,      0ull,   0ull},
5339         {"INC"                         ,        8,      8,      474,    "R/W",  0,      0,      0ull,   0ull},
5340         {"RESERVED_16_63"              ,        16,     48,     474,    "RAZ",  1,      0,      0,      0ull},
5341         {"ADR0"                        ,        0,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5342         {"ADR1"                        ,        1,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5343         {"PEND0"                       ,        2,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5344         {"PEND1"                       ,        3,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5345         {"NBR0"                        ,        4,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5346         {"NBR1"                        ,        5,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5347         {"FIDX"                        ,        6,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5348         {"INDEX"                       ,        7,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5349         {"NBT"                         ,        8,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5350         {"CAM"                         ,        9,      1,      475,    "RO",   0,      0,      0ull,   0ull},
5351         {"RESERVED_10_15"              ,        10,     6,      475,    "RAZ",  1,      1,      0,      0},
5352         {"PP"                          ,        16,     16,     475,    "RO",   0,      0,      0ull,   0ull},
5353         {"RESERVED_32_63"              ,        32,     32,     475,    "RAZ",  1,      1,      0,      0},
5354         {"DS_PC"                       ,        0,      32,     476,    "R/W1C",        0,      1,      0ull,   0},
5355         {"RESERVED_32_63"              ,        32,     32,     476,    "RAZ",  1,      1,      0,      0},
5356         {"SBE"                         ,        0,      1,      477,    "R/W1C",        0,      0,      0ull,   0ull},
5357         {"DBE"                         ,        1,      1,      477,    "R/W1C",        0,      0,      0ull,   0ull},
5358         {"SBE_IE"                      ,        2,      1,      477,    "R/W",  0,      1,      0ull,   0},
5359         {"DBE_IE"                      ,        3,      1,      477,    "R/W",  0,      1,      0ull,   0},
5360         {"SYN"                         ,        4,      5,      477,    "RO",   1,      1,      0,      0},
5361         {"RESERVED_9_11"               ,        9,      3,      477,    "RAZ",  1,      1,      0,      0},
5362         {"RPE"                         ,        12,     1,      477,    "R/W1C",        0,      0,      0ull,   0ull},
5363         {"RPE_IE"                      ,        13,     1,      477,    "R/W",  0,      1,      0ull,   0},
5364         {"RESERVED_14_63"              ,        14,     50,     477,    "RAZ",  1,      1,      0,      0},
5365         {"NBR_THR"                     ,        0,      5,      478,    "R/W",  0,      0,      2ull,   2ull},
5366         {"PFR_DIS"                     ,        5,      1,      478,    "R/W",  0,      0,      0ull,   0ull},
5367         {"RESERVED_6_63"               ,        6,      58,     478,    "RAZ",  1,      1,      0,      0},
5368         {"IQ_CNT"                      ,        0,      32,     479,    "RO",   0,      1,      0ull,   0},
5369         {"RESERVED_32_63"              ,        32,     32,     479,    "RAZ",  1,      1,      0,      0},
5370         {"IQ_CNT"                      ,        0,      32,     480,    "RO",   0,      1,      0ull,   0},
5371         {"RESERVED_32_63"              ,        32,     32,     480,    "RAZ",  1,      1,      0,      0},
5372         {"NOS_CNT"                     ,        0,      12,     481,    "RO",   0,      1,      0ull,   0},
5373         {"RESERVED_12_63"              ,        12,     52,     481,    "RAZ",  1,      1,      0,      0},
5374         {"NW_TIM"                      ,        0,      10,     482,    "R/W",  0,      0,      0ull,   1023ull},
5375         {"RESERVED_10_63"              ,        10,     54,     482,    "RAZ",  1,      1,      0,      0},
5376         {"GRP_MSK"                     ,        0,      16,     483,    "R/W",  0,      0,      65535ull,       65535ull},
5377         {"RESERVED_16_63"              ,        16,     48,     483,    "RAZ",  1,      1,      0,      0},
5378         {"RND"                         ,        0,      8,      484,    "R/W",  0,      1,      255ull, 0},
5379         {"RND_P1"                      ,        8,      8,      484,    "R/W",  0,      1,      255ull, 0},
5380         {"RND_P2"                      ,        16,     8,      484,    "R/W",  0,      1,      255ull, 0},
5381         {"RND_P3"                      ,        24,     8,      484,    "R/W",  0,      1,      255ull, 0},
5382         {"RESERVED_32_63"              ,        32,     32,     484,    "RAZ",  1,      1,      0,      0},
5383         {"MIN_THR"                     ,        0,      11,     485,    "R/W",  0,      1,      0ull,   0},
5384         {"RESERVED_11_11"              ,        11,     1,      485,    "RAZ",  1,      1,      0,      0},
5385         {"MAX_THR"                     ,        12,     11,     485,    "R/W",  0,      1,      2047ull,        0},
5386         {"RESERVED_23_23"              ,        23,     1,      485,    "RAZ",  1,      1,      0,      0},
5387         {"FREE_CNT"                    ,        24,     12,     485,    "RO",   0,      1,      2027ull,        0},
5388         {"BUF_CNT"                     ,        36,     12,     485,    "RO",   0,      1,      0ull,   0},
5389         {"DES_CNT"                     ,        48,     12,     485,    "RO",   0,      1,      0ull,   0},
5390         {"RESERVED_60_63"              ,        60,     4,      485,    "RAZ",  1,      1,      0,      0},
5391         {"TS_PC"                       ,        0,      32,     486,    "R/W1C",        0,      1,      0ull,   0},
5392         {"RESERVED_32_63"              ,        32,     32,     486,    "RAZ",  1,      1,      0,      0},
5393         {"WA_PC"                       ,        0,      32,     487,    "R/W1C",        0,      1,      0ull,   0},
5394         {"RESERVED_32_63"              ,        32,     32,     487,    "RAZ",  1,      1,      0,      0},
5395         {"WA_PC"                       ,        0,      32,     488,    "R/W1C",        0,      1,      0ull,   0},
5396         {"RESERVED_32_63"              ,        32,     32,     488,    "RAZ",  1,      1,      0,      0},
5397         {"WQ_INT"                      ,        0,      16,     489,    "R/W1C",        0,      1,      0ull,   0},
5398         {"IQ_DIS"                      ,        16,     16,     489,    "R/W1", 0,      1,      0ull,   0},
5399         {"RESERVED_32_63"              ,        32,     32,     489,    "RAZ",  1,      1,      0,      0},
5400         {"IQ_CNT"                      ,        0,      12,     490,    "RO",   0,      1,      0ull,   0},
5401         {"DS_CNT"                      ,        12,     12,     490,    "RO",   0,      1,      0ull,   0},
5402         {"TC_CNT"                      ,        24,     4,      490,    "RO",   0,      1,      0ull,   0},
5403         {"RESERVED_28_63"              ,        28,     36,     490,    "RAZ",  1,      1,      0,      0},
5404         {"RESERVED_0_7"                ,        0,      8,      491,    "RAZ",  1,      1,      0,      0},
5405         {"PC_THR"                      ,        8,      20,     491,    "R/W",  0,      1,      0ull,   0},
5406         {"RESERVED_28_31"              ,        28,     4,      491,    "RAZ",  1,      1,      0,      0},
5407         {"PC"                          ,        32,     28,     491,    "RO",   0,      1,      0ull,   0},
5408         {"RESERVED_60_63"              ,        60,     4,      491,    "RAZ",  1,      1,      0,      0},
5409         {"IQ_THR"                      ,        0,      11,     492,    "R/W",  0,      1,      0ull,   0},
5410         {"RESERVED_11_11"              ,        11,     1,      492,    "RAZ",  1,      1,      0,      0},
5411         {"DS_THR"                      ,        12,     11,     492,    "R/W",  0,      1,      0ull,   0},
5412         {"RESERVED_23_23"              ,        23,     1,      492,    "RAZ",  1,      1,      0,      0},
5413         {"TC_THR"                      ,        24,     4,      492,    "R/W",  0,      1,      0ull,   0},
5414         {"TC_EN"                       ,        28,     1,      492,    "R/W",  0,      1,      0ull,   0},
5415         {"RESERVED_29_63"              ,        29,     35,     492,    "RAZ",  1,      1,      0,      0},
5416         {"WS_PC"                       ,        0,      32,     493,    "R/W1C",        0,      1,      0ull,   0},
5417         {"RESERVED_32_63"              ,        32,     32,     493,    "RAZ",  1,      1,      0,      0},
5418         {"MEM"                         ,        0,      1,      494,    "RO",   0,      0,      0ull,   0ull},
5419         {"RRC"                         ,        1,      1,      494,    "RO",   0,      0,      0ull,   0ull},
5420         {"RESERVED_2_63"               ,        2,      62,     494,    "RAZ",  1,      1,      0,      0},
5421         {"ENT_EN"                      ,        0,      1,      495,    "R/W",  0,      0,      0ull,   0ull},
5422         {"RNG_EN"                      ,        1,      1,      495,    "R/W",  0,      0,      0ull,   0ull},
5423         {"RNM_RST"                     ,        2,      1,      495,    "R/W",  0,      0,      0ull,   0ull},
5424         {"RNG_RST"                     ,        3,      1,      495,    "R/W",  0,      0,      0ull,   0ull},
5425         {"RESERVED_4_63"               ,        4,      60,     495,    "RAZ",  1,      1,      0,      0},
5426         {"PHASE"                       ,        0,      8,      496,    "R/W",  0,      0,      100ull, 100ull},
5427         {"SAMPLE"                      ,        8,      4,      496,    "R/W",  0,      0,      2ull,   2ull},
5428         {"PREAMBLE"                    ,        12,     1,      496,    "R/W",  0,      0,      1ull,   1ull},
5429         {"CLK_IDLE"                    ,        13,     1,      496,    "R/W",  0,      0,      0ull,   0ull},
5430         {"RESERVED_14_14"              ,        14,     1,      496,    "RAZ",  1,      1,      0,      0},
5431         {"SAMPLE_MODE"                 ,        15,     1,      496,    "RAZ",  0,      0,      0ull,   0ull},
5432         {"SAMPLE_HI"                   ,        16,     5,      496,    "R/W",  0,      0,      0ull,   0ull},
5433         {"RESERVED_21_63"              ,        21,     43,     496,    "RAZ",  1,      1,      0,      0},
5434         {"REG_ADR"                     ,        0,      5,      497,    "R/W",  0,      1,      0ull,   0},
5435         {"RESERVED_5_7"                ,        5,      3,      497,    "RAZ",  1,      1,      0,      0},
5436         {"PHY_ADR"                     ,        8,      5,      497,    "R/W",  0,      1,      0ull,   0},
5437         {"RESERVED_13_15"              ,        13,     3,      497,    "RAZ",  1,      1,      0,      0},
5438         {"PHY_OP"                      ,        16,     1,      497,    "R/W",  0,      1,      0ull,   0},
5439         {"RESERVED_17_63"              ,        17,     47,     497,    "RAZ",  1,      1,      0,      0},
5440         {"EN"                          ,        0,      1,      498,    "R/W",  0,      0,      0ull,   1ull},
5441         {"RESERVED_1_63"               ,        1,      63,     498,    "RAZ",  1,      1,      0,      0},
5442         {"DAT"                         ,        0,      16,     499,    "RO",   0,      1,      0ull,   0},
5443         {"VAL"                         ,        16,     1,      499,    "RO",   0,      1,      0ull,   0},
5444         {"PENDING"                     ,        17,     1,      499,    "RO",   0,      1,      0ull,   0},
5445         {"RESERVED_18_63"              ,        18,     46,     499,    "RAZ",  1,      1,      0,      0},
5446         {"DAT"                         ,        0,      16,     500,    "R/W",  0,      1,      0ull,   0},
5447         {"VAL"                         ,        16,     1,      500,    "RO",   0,      1,      0ull,   0},
5448         {"PENDING"                     ,        17,     1,      500,    "RO",   0,      1,      0ull,   0},
5449         {"RESERVED_18_63"              ,        18,     46,     500,    "RAZ",  1,      1,      0,      0},
5450         {"CNT"                         ,        0,      32,     501,    "R/W1C",        0,      0,      0ull,   0ull},
5451         {"RESERVED_32_63"              ,        32,     32,     501,    "RAZ",  0,      0,      0ull,   0ull},
5452         {"STAT0"                       ,        0,      1,      502,    "RO",   0,      0,      0ull,   0ull},
5453         {"STAT1"                       ,        1,      1,      502,    "RO",   0,      0,      0ull,   0ull},
5454         {"STAT2"                       ,        2,      1,      502,    "RO",   0,      0,      0ull,   0ull},
5455         {"RESERVED_3_63"               ,        3,      61,     502,    "RAZ",  0,      0,      0ull,   0ull},
5456         {"SRXDLCK"                     ,        0,      1,      503,    "R/W",  0,      0,      0ull,   1ull},
5457         {"RCVTRN"                      ,        1,      1,      503,    "R/W",  0,      0,      0ull,   1ull},
5458         {"DRPTRN"                      ,        2,      1,      503,    "R/W",  0,      0,      0ull,   1ull},
5459         {"SNDTRN"                      ,        3,      1,      503,    "R/W",  0,      0,      0ull,   1ull},
5460         {"STATRCV"                     ,        4,      1,      503,    "R/W",  0,      0,      0ull,   0ull},
5461         {"STATDRV"                     ,        5,      1,      503,    "R/W",  0,      0,      0ull,   0ull},
5462         {"RUNBIST"                     ,        6,      1,      503,    "R/W",  0,      0,      0ull,   0ull},
5463         {"CLKDLY"                      ,        7,      5,      503,    "R/W",  0,      0,      16ull,  16ull},
5464         {"RESERVED_12_15"              ,        12,     4,      503,    "RAZ",  0,      0,      0ull,   0ull},
5465         {"SEETRN"                      ,        16,     1,      503,    "R/W",  0,      0,      0ull,   0ull},
5466         {"RESERVED_17_63"              ,        17,     47,     503,    "RAZ",  0,      0,      0ull,   0ull},
5467         {"RESERVED_0_3"                ,        0,      4,      504,    "RAZ",  0,      1,      0ull,   0},
5468         {"D4CLK0"                      ,        4,      1,      504,    "R/W1C",        0,      1,      0ull,   0},
5469         {"D4CLK1"                      ,        5,      1,      504,    "R/W1C",        0,      1,      0ull,   0},
5470         {"S4CLK0"                      ,        6,      1,      504,    "R/W1C",        0,      1,      0ull,   0},
5471         {"S4CLK1"                      ,        7,      1,      504,    "R/W1C",        0,      1,      0ull,   0},
5472         {"SRXTRN"                      ,        8,      1,      504,    "R/W1C",        0,      1,      0ull,   0},
5473         {"RESERVED_9_9"                ,        9,      1,      504,    "RAZ",  0,      1,      0ull,   0},
5474         {"STXCAL"                      ,        10,     1,      504,    "R/W1C",        0,      1,      0ull,   0},
5475         {"RESERVED_11_63"              ,        11,     53,     504,    "RAZ",  0,      0,      0ull,   0ull},
5476         {"DLLDIS"                      ,        0,      1,      505,    "R/W",  1,      0,      0,      0ull},
5477         {"DLLFRC"                      ,        1,      1,      505,    "WR0",  1,      0,      0,      0ull},
5478         {"OFFDLY"                      ,        2,      6,      505,    "R/W",  1,      0,      0,      0ull},
5479         {"BITSEL"                      ,        8,      5,      505,    "R/W",  1,      1,      0,      0},
5480         {"OFFSET"                      ,        13,     5,      505,    "R/W",  1,      1,      0,      0},
5481         {"MUX"                         ,        18,     1,      505,    "WR0",  1,      1,      0,      0},
5482         {"INC"                         ,        19,     1,      505,    "WR0",  1,      1,      0,      0},
5483         {"DEC"                         ,        20,     1,      505,    "WR0",  1,      1,      0,      0},
5484         {"CLRDLY"                      ,        21,     1,      505,    "WR0",  1,      1,      0,      0},
5485         {"RESERVED_22_23"              ,        22,     2,      505,    "RAZ",  0,      0,      0ull,   0ull},
5486         {"SSTEP"                       ,        24,     1,      505,    "R/W",  1,      0,      0,      0ull},
5487         {"SSTEP_GO"                    ,        25,     1,      505,    "WR0",  1,      1,      0,      0},
5488         {"RESERVED_26_27"              ,        26,     2,      505,    "RAZ",  0,      0,      0ull,   0ull},
5489         {"FALL8"                       ,        28,     1,      505,    "R/W",  0,      0,      0ull,   0ull},
5490         {"FALLNOP"                     ,        29,     1,      505,    "R/W",  0,      0,      0ull,   0ull},
5491         {"RESERVED_30_63"              ,        30,     34,     505,    "RAZ",  0,      0,      0ull,   0ull},
5492         {"OFFSET"                      ,        0,      5,      506,    "RO",   0,      1,      0ull,   0},
5493         {"MUXSEL"                      ,        5,      2,      506,    "RO",   0,      1,      0ull,   0},
5494         {"UNXTERM"                     ,        7,      1,      506,    "R/W1C",        0,      0,      0ull,   0ull},
5495         {"TESTRES"                     ,        8,      1,      506,    "R/W1C",        0,      0,      0ull,   0ull},
5496         {"RESERVED_9_63"               ,        9,      55,     506,    "RAZ",  0,      0,      0ull,   0ull},
5497         {"SRX4CMP"                     ,        0,      8,      507,    "R/W",  0,      1,      0ull,   0},
5498         {"STX4PCMP"                    ,        8,      4,      507,    "R/W",  0,      1,      0ull,   0},
5499         {"STX4NCMP"                    ,        12,     4,      507,    "R/W",  0,      1,      0ull,   0},
5500         {"RESERVED_16_63"              ,        16,     48,     507,    "RAZ",  0,      0,      0ull,   0ull},
5501         {"ERRCNT"                      ,        0,      4,      508,    "R/W",  0,      0,      0ull,   3ull},
5502         {"RESERVED_4_5"                ,        4,      2,      508,    "RAZ",  0,      0,      0ull,   0ull},
5503         {"DIPPAY"                      ,        6,      1,      508,    "R/W",  0,      0,      0ull,   0ull},
5504         {"DIPCLS"                      ,        7,      1,      508,    "R/W",  0,      0,      0ull,   0ull},
5505         {"PRTNXA"                      ,        8,      1,      508,    "R/W",  0,      0,      0ull,   0ull},
5506         {"RESERVED_9_63"               ,        9,      55,     508,    "RAZ",  0,      0,      0ull,   0ull},
5507         {"PRT"                         ,        0,      8,      509,    "RO",   0,      0,      0ull,   0ull},
5508         {"RSVOP"                       ,        8,      4,      509,    "RO",   0,      0,      0ull,   0ull},
5509         {"CALBNK"                      ,        12,     2,      509,    "RO",   0,      0,      0ull,   0ull},
5510         {"RESERVED_14_30"              ,        14,     17,     509,    "RAZ",  0,      0,      0ull,   0ull},
5511         {"MUL"                         ,        31,     1,      509,    "RO",   0,      0,      0ull,   0ull},
5512         {"RESERVED_32_63"              ,        32,     32,     509,    "RAZ",  0,      0,      0ull,   0ull},
5513         {"PRTNXA"                      ,        0,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
5514         {"ABNORM"                      ,        1,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
5515         {"RESERVED_2_3"                ,        2,      2,      510,    "RAZ",  0,      0,      0ull,   0ull},
5516         {"SPIOVR"                      ,        4,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
5517         {"CLSERR"                      ,        5,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
5518         {"DRWNNG"                      ,        6,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
5519         {"RSVERR"                      ,        7,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
5520         {"TPAOVR"                      ,        8,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
5521         {"DIPERR"                      ,        9,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
5522         {"SYNCERR"                     ,        10,     1,      510,    "R/W",  0,      0,      0ull,   0ull},
5523         {"CALERR"                      ,        11,     1,      510,    "R/W",  0,      0,      0ull,   0ull},
5524         {"RESERVED_12_63"              ,        12,     52,     510,    "RAZ",  0,      0,      0ull,   0ull},
5525         {"PRTNXA"                      ,        0,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5526         {"ABNORM"                      ,        1,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5527         {"RESERVED_2_3"                ,        2,      2,      511,    "RAZ",  0,      0,      0ull,   0ull},
5528         {"SPIOVR"                      ,        4,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5529         {"CLSERR"                      ,        5,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5530         {"DRWNNG"                      ,        6,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5531         {"RSVERR"                      ,        7,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5532         {"TPAOVR"                      ,        8,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5533         {"DIPERR"                      ,        9,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5534         {"SYNCERR"                     ,        10,     1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5535         {"CALERR"                      ,        11,     1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
5536         {"RESERVED_12_30"              ,        12,     19,     511,    "RAZ",  0,      0,      0ull,   0ull},
5537         {"SPF"                         ,        31,     1,      511,    "RO",   0,      0,      0ull,   0ull},
5538         {"RESERVED_32_63"              ,        32,     32,     511,    "RAZ",  0,      0,      0ull,   0ull},
5539         {"PRTNXA"                      ,        0,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
5540         {"ABNORM"                      ,        1,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
5541         {"RESERVED_2_3"                ,        2,      2,      512,    "RAZ",  0,      0,      0ull,   0ull},
5542         {"SPIOVR"                      ,        4,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
5543         {"CLSERR"                      ,        5,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
5544         {"DRWNNG"                      ,        6,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
5545         {"RSVERR"                      ,        7,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
5546         {"TPAOVR"                      ,        8,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
5547         {"DIPERR"                      ,        9,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
5548         {"SYNCERR"                     ,        10,     1,      512,    "R/W",  0,      0,      0ull,   0ull},
5549         {"CALERR"                      ,        11,     1,      512,    "R/W",  0,      0,      0ull,   0ull},
5550         {"RESERVED_12_63"              ,        12,     52,     512,    "RAZ",  0,      0,      0ull,   0ull},
5551         {"CNT"                         ,        0,      32,     513,    "RO",   0,      1,      0ull,   0},
5552         {"RESERVED_32_63"              ,        32,     32,     513,    "RAZ",  0,      0,      0ull,   0ull},
5553         {"MAX"                         ,        0,      32,     514,    "R/W",  0,      0,      0ull,   0ull},
5554         {"RESERVED_32_63"              ,        32,     32,     514,    "RAZ",  0,      0,      0ull,   0ull},
5555         {"PRTSEL"                      ,        0,      4,      515,    "R/W",  0,      0,      0ull,   0ull},
5556         {"RESERVED_4_63"               ,        4,      60,     515,    "RAZ",  0,      0,      0ull,   0ull},
5557         {"MUX_EN"                      ,        0,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
5558         {"MACRO_EN"                    ,        1,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
5559         {"MAXDIST"                     ,        2,      5,      516,    "R/W",  0,      0,      0ull,   8ull},
5560         {"SET_BOOT"                    ,        7,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
5561         {"CLR_BOOT"                    ,        8,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
5562         {"JITTER"                      ,        9,      3,      516,    "R/W",  0,      0,      0ull,   1ull},
5563         {"TRNTEST"                     ,        12,     1,      516,    "R/W",  0,      0,      0ull,   0ull},
5564         {"RESERVED_13_63"              ,        13,     51,     516,    "RAZ",  0,      0,      0ull,   0ull},
5565         {"BW_CTL"                      ,        0,      5,      517,    "R/W",  0,      1,      0ull,   0},
5566         {"RESERVED_5_63"               ,        5,      59,     517,    "RAZ",  0,      0,      0ull,   0ull},
5567         {"SETTING"                     ,        0,      17,     518,    "RO",   1,      1,      0,      0},
5568         {"RESERVED_17_63"              ,        17,     47,     518,    "RAZ",  0,      0,      0ull,   0ull},
5569         {"INF_EN"                      ,        0,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
5570         {"RESERVED_1_2"                ,        1,      2,      519,    "RAZ",  0,      0,      0ull,   0ull},
5571         {"ST_EN"                       ,        3,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
5572         {"PRTS"                        ,        4,      4,      519,    "R/W",  0,      1,      0ull,   0},
5573         {"RESERVED_8_63"               ,        8,      56,     519,    "RAZ",  0,      0,      0ull,   0ull},
5574         {"IGNORE"                      ,        0,      16,     520,    "R/W",  0,      0,      0ull,   0ull},
5575         {"RESERVED_16_63"              ,        16,     48,     520,    "RAZ",  0,      0,      0ull,   0ull},
5576         {"PRT0"                        ,        0,      4,      521,    "R/W",  1,      1,      0,      0},
5577         {"PRT1"                        ,        4,      4,      521,    "R/W",  1,      1,      0,      0},
5578         {"PRT2"                        ,        8,      4,      521,    "R/W",  1,      1,      0,      0},
5579         {"PRT3"                        ,        12,     4,      521,    "R/W",  1,      1,      0,      0},
5580         {"ODDPAR"                      ,        16,     1,      521,    "R/W",  1,      1,      0,      0},
5581         {"RESERVED_17_63"              ,        17,     47,     521,    "RAZ",  0,      0,      0ull,   0ull},
5582         {"LEN"                         ,        0,      7,      522,    "R/W",  0,      1,      0ull,   0},
5583         {"RESERVED_7_7"                ,        7,      1,      522,    "RAZ",  0,      0,      0ull,   0ull},
5584         {"M"                           ,        8,      8,      522,    "R/W",  0,      1,      0ull,   0},
5585         {"RESERVED_16_63"              ,        16,     48,     522,    "RAZ",  0,      0,      0ull,   0ull},
5586         {"RESERVED_0_2"                ,        0,      3,      523,    "R/W",  0,      0,      0ull,   0ull},
5587         {"IGNTPA"                      ,        3,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
5588         {"RESERVED_4_4"                ,        4,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
5589         {"MINTRN"                      ,        5,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
5590         {"RESERVED_6_63"               ,        6,      58,     523,    "RAZ",  0,      0,      0ull,   0ull},
5591         {"CNT"                         ,        0,      32,     524,    "R/W1C",        0,      0,      0ull,   0ull},
5592         {"RESERVED_32_63"              ,        32,     32,     524,    "RAZ",  0,      0,      0ull,   0ull},
5593         {"INF_EN"                      ,        0,      1,      525,    "R/W",  0,      0,      0ull,   1ull},
5594         {"RESERVED_1_2"                ,        1,      2,      525,    "RAZ",  0,      0,      0ull,   0ull},
5595         {"ST_EN"                       ,        3,      1,      525,    "R/W",  0,      0,      0ull,   1ull},
5596         {"RESERVED_4_63"               ,        4,      60,     525,    "RAZ",  0,      0,      0ull,   0ull},
5597         {"DIPMAX"                      ,        0,      4,      526,    "R/W",  0,      0,      0ull,   0ull},
5598         {"FRMMAX"                      ,        4,      4,      526,    "R/W",  0,      0,      0ull,   0ull},
5599         {"RESERVED_8_63"               ,        8,      56,     526,    "RAZ",  0,      0,      0ull,   0ull},
5600         {"IGNTPA"                      ,        0,      16,     527,    "R/W",  0,      0,      0ull,   0ull},
5601         {"RESERVED_16_63"              ,        16,     48,     527,    "RAZ",  0,      0,      0ull,   0ull},
5602         {"CALPAR0"                     ,        0,      1,      528,    "R/W",  0,      0,      0ull,   0ull},
5603         {"CALPAR1"                     ,        1,      1,      528,    "R/W",  0,      0,      0ull,   0ull},
5604         {"OVRBST"                      ,        2,      1,      528,    "R/W",  0,      0,      0ull,   0ull},
5605         {"DATOVR"                      ,        3,      1,      528,    "R/W",  0,      0,      0ull,   0ull},
5606         {"DIPERR"                      ,        4,      1,      528,    "R/W",  0,      0,      0ull,   0ull},
5607         {"NOSYNC"                      ,        5,      1,      528,    "R/W",  0,      0,      0ull,   0ull},
5608         {"UNXFRM"                      ,        6,      1,      528,    "R/W",  0,      0,      0ull,   0ull},
5609         {"FRMERR"                      ,        7,      1,      528,    "R/W",  0,      0,      0ull,   0ull},
5610         {"RESERVED_8_63"               ,        8,      56,     528,    "RAZ",  0,      0,      0ull,   0ull},
5611         {"CALPAR0"                     ,        0,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
5612         {"CALPAR1"                     ,        1,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
5613         {"OVRBST"                      ,        2,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
5614         {"DATOVR"                      ,        3,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
5615         {"DIPERR"                      ,        4,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
5616         {"NOSYNC"                      ,        5,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
5617         {"UNXFRM"                      ,        6,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
5618         {"FRMERR"                      ,        7,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
5619         {"SYNCERR"                     ,        8,      1,      529,    "RO",   0,      0,      0ull,   0ull},
5620         {"RESERVED_9_63"               ,        9,      55,     529,    "RAZ",  0,      0,      0ull,   0ull},
5621         {"CALPAR0"                     ,        0,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
5622         {"CALPAR1"                     ,        1,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
5623         {"OVRBST"                      ,        2,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
5624         {"DATOVR"                      ,        3,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
5625         {"DIPERR"                      ,        4,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
5626         {"NOSYNC"                      ,        5,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
5627         {"UNXFRM"                      ,        6,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
5628         {"FRMERR"                      ,        7,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
5629         {"RESERVED_8_63"               ,        8,      56,     530,    "RAZ",  0,      0,      0ull,   0ull},
5630         {"MINB"                        ,        0,      9,      531,    "R/W",  0,      0,      0ull,   0ull},
5631         {"RESERVED_9_63"               ,        9,      55,     531,    "RAZ",  0,      0,      0ull,   0ull},
5632         {"PRT0"                        ,        0,      4,      532,    "R/W",  1,      1,      0,      0},
5633         {"PRT1"                        ,        4,      4,      532,    "R/W",  1,      1,      0,      0},
5634         {"PRT2"                        ,        8,      4,      532,    "R/W",  1,      1,      0,      0},
5635         {"PRT3"                        ,        12,     4,      532,    "R/W",  1,      1,      0,      0},
5636         {"ODDPAR"                      ,        16,     1,      532,    "R/W",  1,      1,      0,      0},
5637         {"RESERVED_17_63"              ,        17,     47,     532,    "RAZ",  0,      0,      0ull,   0ull},
5638         {"MAX_T"                       ,        0,      16,     533,    "R/W",  0,      1,      0ull,   0},
5639         {"ALPHA"                       ,        16,     16,     533,    "R/W",  0,      1,      0ull,   0},
5640         {"RESERVED_32_63"              ,        32,     32,     533,    "RAZ",  0,      0,      0ull,   0ull},
5641         {"LEN"                         ,        0,      7,      534,    "R/W",  0,      1,      0ull,   0},
5642         {"RESERVED_7_7"                ,        7,      1,      534,    "RAZ",  0,      0,      0ull,   0ull},
5643         {"M"                           ,        8,      8,      534,    "R/W",  0,      1,      0ull,   0},
5644         {"RESERVED_16_63"              ,        16,     48,     534,    "RAZ",  0,      0,      0ull,   0ull},
5645         {"CNT"                         ,        0,      32,     535,    "RO",   0,      0,      0ull,   0ull},
5646         {"RESERVED_32_63"              ,        32,     32,     535,    "RAZ",  0,      0,      0ull,   0ull},
5647         {"CNT"                         ,        0,      32,     536,    "RO",   0,      0,      0ull,   0ull},
5648         {"RESERVED_32_63"              ,        32,     32,     536,    "RAZ",  0,      0,      0ull,   0ull},
5649         {"BCKPRS"                      ,        0,      4,      537,    "R/W",  0,      0,      0ull,   0ull},
5650         {"CLR"                         ,        4,      1,      537,    "WR0",  0,      0,      0ull,   0ull},
5651         {"RESERVED_5_63"               ,        5,      59,     537,    "RAZ",  0,      0,      0ull,   0ull},
5652         {"CNT"                         ,        0,      32,     538,    "RO",   0,      0,      0ull,   0ull},
5653         {"RESERVED_32_63"              ,        32,     32,     538,    "RAZ",  0,      0,      0ull,   0ull},
5654         {"INTERVAL"                    ,        0,      22,     539,    "RO",   1,      0,      0,      0ull},
5655         {"RESERVED_22_23"              ,        22,     2,      539,    "RAZ",  1,      0,      0,      0ull},
5656         {"COUNT"                       ,        24,     22,     539,    "RO",   1,      0,      0,      0ull},
5657         {"RESERVED_46_46"              ,        46,     1,      539,    "RAZ",  1,      0,      0,      0ull},
5658         {"ENA"                         ,        47,     1,      539,    "RO",   1,      0,      0,      0ull},
5659         {"RESERVED_48_63"              ,        48,     16,     539,    "RAZ",  1,      0,      0,      0ull},
5660         {"BSIZE"                       ,        0,      20,     540,    "RO",   1,      0,      0,      0ull},
5661         {"BASE"                        ,        20,     31,     540,    "RO",   1,      0,      0,      0ull},
5662         {"BUCKET"                      ,        51,     13,     540,    "RO",   1,      0,      0,      0ull},
5663         {"BUCKET"                      ,        0,      7,      541,    "RO",   1,      0,      0,      0ull},
5664         {"RESERVED_7_7"                ,        7,      1,      541,    "RAZ",  1,      0,      0,      0ull},
5665         {"CSIZE"                       ,        8,      13,     541,    "RO",   1,      0,      0,      0ull},
5666         {"CPOOL"                       ,        21,     3,      541,    "RO",   1,      0,      0,      0ull},
5667         {"RESERVED_24_63"              ,        24,     40,     541,    "RAZ",  1,      0,      0,      0ull},
5668         {"RING"                        ,        0,      4,      542,    "R/W",  0,      0,      0ull,   0ull},
5669         {"NUM_BUCKETS"                 ,        4,      20,     542,    "R/W",  0,      0,      0ull,   0ull},
5670         {"FIRST_BUCKET"                ,        24,     31,     542,    "R/W",  0,      0,      0ull,   0ull},
5671         {"RESERVED_55_63"              ,        55,     9,      542,    "RAZ",  1,      0,      0,      0ull},
5672         {"RING"                        ,        0,      4,      543,    "R/W",  0,      0,      0ull,   0ull},
5673         {"INTERVAL"                    ,        4,      22,     543,    "R/W",  0,      0,      0ull,   0ull},
5674         {"WORDS_PER_CHUNK"             ,        26,     13,     543,    "R/W",  0,      0,      0ull,   0ull},
5675         {"POOL"                        ,        39,     3,      543,    "R/W",  0,      0,      0ull,   0ull},
5676         {"ENABLE"                      ,        42,     1,      543,    "R/W",  0,      0,      0ull,   0ull},
5677         {"RESERVED_43_63"              ,        43,     21,     543,    "RAZ",  1,      0,      0,      0ull},
5678         {"CTL"                         ,        0,      1,      544,    "RO",   1,      0,      0,      0ull},
5679         {"NCB"                         ,        1,      1,      544,    "RO",   1,      0,      0,      0ull},
5680         {"STA"                         ,        2,      2,      544,    "RO",   1,      0,      0,      0ull},
5681         {"RESERVED_4_63"               ,        4,      60,     544,    "RAZ",  1,      0,      0,      0ull},
5682         {"MASK"                        ,        0,      16,     545,    "R/W1C",        0,      0,      0ull,   0ull},
5683         {"RESERVED_16_63"              ,        16,     48,     545,    "RAZ",  1,      0,      0,      0ull},
5684         {"ENABLE_TIMERS"               ,        0,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
5685         {"ENABLE_DWB"                  ,        1,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
5686         {"RESET"                       ,        2,      1,      546,    "RAZ",  0,      0,      0ull,   0ull},
5687         {"RESERVED_3_63"               ,        3,      61,     546,    "RAZ",  1,      0,      0,      0ull},
5688         {"MASK"                        ,        0,      16,     547,    "R/W",  0,      0,      0ull,   0ull},
5689         {"RESERVED_16_63"              ,        16,     48,     547,    "RAZ",  1,      0,      0,      0ull},
5690         {"INDEX"                       ,        0,      8,      548,    "R/W",  0,      0,      0ull,   0ull},
5691         {"INC"                         ,        8,      8,      548,    "R/W",  0,      0,      0ull,   0ull},
5692         {"RESERVED_16_63"              ,        16,     48,     548,    "RAZ",  1,      0,      0,      0ull},
5693         {"TDF0"                        ,        0,      1,      549,    "RO",   0,      0,      0ull,   0ull},
5694         {"TDF1"                        ,        1,      1,      549,    "RO",   0,      0,      0ull,   0ull},
5695         {"TCF"                         ,        2,      1,      549,    "RO",   0,      0,      0ull,   0ull},
5696         {"RESERVED_3_63"               ,        3,      61,     549,    "RAZ",  0,      0,      0ull,   0ull},
5697         {"ENA"                         ,        0,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
5698         {"WRAP"                        ,        1,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
5699         {"TRIG_CTL"                    ,        2,      2,      550,    "R/W",  0,      0,      0ull,   0ull},
5700         {"TIME_GRN"                    ,        4,      3,      550,    "R/W",  0,      0,      0ull,   0ull},
5701         {"FULL_THR"                    ,        7,      2,      550,    "R/W",  0,      0,      0ull,   0ull},
5702         {"CIU_TRG"                     ,        9,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
5703         {"CIU_THR"                     ,        10,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
5704         {"MCD0_TRG"                    ,        11,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
5705         {"MCD0_THR"                    ,        12,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
5706         {"MCD0_ENA"                    ,        13,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
5707         {"IGNORE_O"                    ,        14,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
5708         {"RESERVED_15_63"              ,        15,     49,     550,    "RAZ",  0,      0,      0ull,   0ull},
5709         {"WPTR"                        ,        0,      8,      551,    "RO",   0,      0,      0ull,   0ull},
5710         {"RPTR"                        ,        8,      8,      551,    "RO",   0,      0,      0ull,   0ull},
5711         {"CYCLES"                      ,        16,     48,     551,    "RO",   0,      0,      0ull,   0ull},
5712         {"ADR"                         ,        0,      36,     552,    "R/W",  0,      1,      0ull,   0},
5713         {"RESERVED_36_63"              ,        36,     28,     552,    "RAZ",  0,      0,      0ull,   0ull},
5714         {"ADR"                         ,        0,      36,     553,    "R/W",  0,      0,      0ull,   0ull},
5715         {"RESERVED_36_63"              ,        36,     28,     553,    "RAZ",  0,      0,      0ull,   0ull},
5716         {"DWB"                         ,        0,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5717         {"PL2"                         ,        1,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5718         {"PSL1"                        ,        2,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5719         {"LDD"                         ,        3,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5720         {"LDI"                         ,        4,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5721         {"LDT"                         ,        5,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5722         {"STF"                         ,        6,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5723         {"STC"                         ,        7,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5724         {"STP"                         ,        8,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5725         {"STT"                         ,        9,      1,      554,    "R/W",  0,      0,      0ull,   1ull},
5726         {"IOBLD8"                      ,        10,     1,      554,    "R/W",  0,      0,      0ull,   1ull},
5727         {"IOBLD16"                     ,        11,     1,      554,    "R/W",  0,      0,      0ull,   1ull},
5728         {"IOBLD32"                     ,        12,     1,      554,    "R/W",  0,      0,      0ull,   1ull},
5729         {"IOBLD64"                     ,        13,     1,      554,    "R/W",  0,      0,      0ull,   1ull},
5730         {"IOBST"                       ,        14,     1,      554,    "R/W",  0,      0,      0ull,   1ull},
5731         {"IOBDMA"                      ,        15,     1,      554,    "R/W",  0,      0,      0ull,   1ull},
5732         {"RESERVED_16_63"              ,        16,     48,     554,    "RAZ",  0,      0,      0ull,   0ull},
5733         {"MIO"                         ,        0,      1,      555,    "R/W",  0,      0,      0ull,   1ull},
5734         {"ILLEGAL3"                    ,        1,      2,      555,    "R/W",  0,      0,      0ull,   3ull},
5735         {"PCI"                         ,        3,      1,      555,    "R/W",  0,      0,      0ull,   1ull},
5736         {"KEY"                         ,        4,      1,      555,    "R/W",  0,      0,      0ull,   1ull},
5737         {"FPA"                         ,        5,      1,      555,    "R/W",  0,      0,      0ull,   1ull},
5738         {"DFA"                         ,        6,      1,      555,    "R/W",  0,      0,      0ull,   1ull},
5739         {"ZIP"                         ,        7,      1,      555,    "R/W",  0,      0,      0ull,   1ull},
5740         {"RNG"                         ,        8,      1,      555,    "R/W",  0,      0,      0ull,   1ull},
5741         {"ILLEGAL2"                    ,        9,      3,      555,    "R/W",  0,      0,      0ull,   7ull},
5742         {"POW"                         ,        12,     1,      555,    "R/W",  0,      0,      0ull,   1ull},
5743         {"ILLEGAL"                     ,        13,     19,     555,    "R/W",  0,      0,      0ull,   524287ull},
5744         {"RESERVED_32_63"              ,        32,     32,     555,    "RAZ",  0,      0,      0ull,   0ull},
5745         {"PP"                          ,        0,      16,     556,    "R/W",  0,      0,      0ull,   0ull},
5746         {"PKI"                         ,        16,     1,      556,    "R/W",  0,      0,      0ull,   0ull},
5747         {"PKO"                         ,        17,     1,      556,    "R/W",  0,      0,      0ull,   0ull},
5748         {"IOBREQ"                      ,        18,     1,      556,    "R/W",  0,      0,      0ull,   0ull},
5749         {"DWB"                         ,        19,     1,      556,    "R/W",  0,      0,      0ull,   0ull},
5750         {"RESERVED_20_63"              ,        20,     44,     556,    "RAZ",  0,      0,      0ull,   0ull},
5751         {"CIU_TRG"                     ,        0,      1,      557,    "R/W1C",        0,      0,      0ull,   0ull},
5752         {"CIU_THR"                     ,        1,      1,      557,    "R/W1C",        0,      0,      0ull,   0ull},
5753         {"MCD0_TRG"                    ,        2,      1,      557,    "R/W1C",        0,      0,      0ull,   0ull},
5754         {"MCD0_THR"                    ,        3,      1,      557,    "R/W1C",        0,      0,      0ull,   0ull},
5755         {"RESERVED_4_63"               ,        4,      60,     557,    "RAZ",  0,      0,      0ull,   0ull},
5756         {"DATA"                        ,        0,      64,     558,    "RO",   0,      0,      0ull,   0ull},
5757         {"ADR"                         ,        0,      36,     559,    "R/W",  0,      1,      0ull,   0},
5758         {"RESERVED_36_63"              ,        36,     28,     559,    "RAZ",  0,      0,      0ull,   0ull},
5759         {"ADR"                         ,        0,      36,     560,    "R/W",  0,      0,      0ull,   0ull},
5760         {"RESERVED_36_63"              ,        36,     28,     560,    "RAZ",  0,      0,      0ull,   0ull},
5761         {"DWB"                         ,        0,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5762         {"PL2"                         ,        1,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5763         {"PSL1"                        ,        2,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5764         {"LDD"                         ,        3,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5765         {"LDI"                         ,        4,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5766         {"LDT"                         ,        5,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5767         {"STF"                         ,        6,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5768         {"STC"                         ,        7,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5769         {"STP"                         ,        8,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5770         {"STT"                         ,        9,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
5771         {"IOBLD8"                      ,        10,     1,      561,    "R/W",  0,      0,      0ull,   1ull},
5772         {"IOBLD16"                     ,        11,     1,      561,    "R/W",  0,      0,      0ull,   1ull},
5773         {"IOBLD32"                     ,        12,     1,      561,    "R/W",  0,      0,      0ull,   1ull},
5774         {"IOBLD64"                     ,        13,     1,      561,    "R/W",  0,      0,      0ull,   1ull},
5775         {"IOBST"                       ,        14,     1,      561,    "R/W",  0,      0,      0ull,   1ull},
5776         {"IOBDMA"                      ,        15,     1,      561,    "R/W",  0,      0,      0ull,   1ull},
5777         {"RESERVED_16_63"              ,        16,     48,     561,    "RAZ",  0,      0,      0ull,   0ull},
5778         {"MIO"                         ,        0,      1,      562,    "R/W",  0,      0,      0ull,   1ull},
5779         {"ILLEGAL3"                    ,        1,      2,      562,    "R/W",  0,      0,      0ull,   3ull},
5780         {"PCI"                         ,        3,      1,      562,    "R/W",  0,      0,      0ull,   1ull},
5781         {"KEY"                         ,        4,      1,      562,    "R/W",  0,      0,      0ull,   1ull},
5782         {"FPA"                         ,        5,      1,      562,    "R/W",  0,      0,      0ull,   1ull},
5783         {"DFA"                         ,        6,      1,      562,    "R/W",  0,      0,      0ull,   1ull},
5784         {"ZIP"                         ,        7,      1,      562,    "R/W",  0,      0,      0ull,   1ull},
5785         {"RNG"                         ,        8,      1,      562,    "R/W",  0,      0,      0ull,   1ull},
5786         {"ILLEGAL2"                    ,        9,      3,      562,    "R/W",  0,      0,      0ull,   7ull},
5787         {"POW"                         ,        12,     1,      562,    "R/W",  0,      0,      0ull,   1ull},
5788         {"ILLEGAL"                     ,        13,     19,     562,    "R/W",  0,      0,      0ull,   524287ull},
5789         {"RESERVED_32_63"              ,        32,     32,     562,    "RAZ",  0,      0,      0ull,   0ull},
5790         {"PP"                          ,        0,      16,     563,    "R/W",  0,      0,      0ull,   0ull},
5791         {"PKI"                         ,        16,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
5792         {"PKO"                         ,        17,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
5793         {"IOBREQ"                      ,        18,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
5794         {"DWB"                         ,        19,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
5795         {"RESERVED_20_63"              ,        20,     44,     563,    "RAZ",  0,      0,      0ull,   0ull},
5796         {"ADR"                         ,        0,      36,     564,    "R/W",  0,      1,      0ull,   0},
5797         {"RESERVED_36_63"              ,        36,     28,     564,    "RAZ",  0,      0,      0ull,   0ull},
5798         {"ADR"                         ,        0,      36,     565,    "R/W",  0,      0,      0ull,   0ull},
5799         {"RESERVED_36_63"              ,        36,     28,     565,    "RAZ",  0,      0,      0ull,   0ull},
5800         {"DWB"                         ,        0,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5801         {"PL2"                         ,        1,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5802         {"PSL1"                        ,        2,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5803         {"LDD"                         ,        3,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5804         {"LDI"                         ,        4,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5805         {"LDT"                         ,        5,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5806         {"STF"                         ,        6,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5807         {"STC"                         ,        7,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5808         {"STP"                         ,        8,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5809         {"STT"                         ,        9,      1,      566,    "R/W",  0,      0,      0ull,   1ull},
5810         {"IOBLD8"                      ,        10,     1,      566,    "R/W",  0,      0,      0ull,   1ull},
5811         {"IOBLD16"                     ,        11,     1,      566,    "R/W",  0,      0,      0ull,   1ull},
5812         {"IOBLD32"                     ,        12,     1,      566,    "R/W",  0,      0,      0ull,   1ull},
5813         {"IOBLD64"                     ,        13,     1,      566,    "R/W",  0,      0,      0ull,   1ull},
5814         {"IOBST"                       ,        14,     1,      566,    "R/W",  0,      0,      0ull,   1ull},
5815         {"IOBDMA"                      ,        15,     1,      566,    "R/W",  0,      0,      0ull,   1ull},
5816         {"RESERVED_16_63"              ,        16,     48,     566,    "RAZ",  0,      0,      0ull,   0ull},
5817         {"MIO"                         ,        0,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
5818         {"ILLEGAL3"                    ,        1,      2,      567,    "R/W",  0,      0,      0ull,   3ull},
5819         {"PCI"                         ,        3,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
5820         {"KEY"                         ,        4,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
5821         {"FPA"                         ,        5,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
5822         {"DFA"                         ,        6,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
5823         {"ZIP"                         ,        7,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
5824         {"RNG"                         ,        8,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
5825         {"ILLEGAL2"                    ,        9,      3,      567,    "R/W",  0,      0,      0ull,   7ull},
5826         {"POW"                         ,        12,     1,      567,    "R/W",  0,      0,      0ull,   1ull},
5827         {"ILLEGAL"                     ,        13,     19,     567,    "R/W",  0,      0,      0ull,   524287ull},
5828         {"RESERVED_32_63"              ,        32,     32,     567,    "RAZ",  0,      0,      0ull,   0ull},
5829         {"PP"                          ,        0,      16,     568,    "R/W",  0,      0,      0ull,   0ull},
5830         {"PKI"                         ,        16,     1,      568,    "R/W",  0,      0,      0ull,   0ull},
5831         {"PKO"                         ,        17,     1,      568,    "R/W",  0,      0,      0ull,   0ull},
5832         {"IOBREQ"                      ,        18,     1,      568,    "R/W",  0,      0,      0ull,   0ull},
5833         {"DWB"                         ,        19,     1,      568,    "R/W",  0,      0,      0ull,   0ull},
5834         {"RESERVED_20_63"              ,        20,     44,     568,    "RAZ",  0,      0,      0ull,   0ull},
5835         {"ZIP_CTL"                     ,        0,      4,      569,    "RO",   1,      0,      0,      0ull},
5836         {"ZIP_CORE"                    ,        4,      27,     569,    "RO",   1,      0,      0,      0ull},
5837         {"RESERVED_31_63"              ,        31,     33,     569,    "RAZ",  1,      0,      0,      0ull},
5838         {"PTR"                         ,        0,      33,     570,    "R/W",  0,      0,      0ull,   0ull},
5839         {"SIZE"                        ,        33,     13,     570,    "R/W",  0,      0,      0ull,   0ull},
5840         {"POOL"                        ,        46,     3,      570,    "R/W",  0,      0,      0ull,   0ull},
5841         {"DWB"                         ,        49,     9,      570,    "R/W",  0,      0,      0ull,   0ull},
5842         {"RESERVED_58_63"              ,        58,     6,      570,    "RAZ",  0,      0,      0ull,   0ull},
5843         {"RESET"                       ,        0,      1,      571,    "RAZ",  0,      0,      0ull,   0ull},
5844         {"FORCECLK"                    ,        1,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
5845         {"RESERVED_2_63"               ,        2,      62,     571,    "RAZ",  0,      0,      0ull,   0ull},
5846         {"DISABLED"                    ,        0,      1,      572,    "RO",   0,      0,      0ull,   0ull},
5847         {"RESERVED_1_7"                ,        1,      7,      572,    "RAZ",  0,      0,      0ull,   0ull},
5848         {"CTXSIZE"                     ,        8,      12,     572,    "RO",   0,      0,      1536ull,        1536ull},
5849         {"ONFSIZE"                     ,        20,     12,     572,    "RO",   0,      0,      512ull, 512ull},
5850         {"DEPTH"                       ,        32,     16,     572,    "RO",   0,      0,      15360ull,       15360ull},
5851         {"RESERVED_48_63"              ,        48,     16,     572,    "RAZ",  1,      0,      0,      0ull},
5852         {"ASSERTS"                     ,        0,      14,     573,    "RO",   0,      0,      0ull,   0ull},
5853         {"RESERVED_14_63"              ,        14,     50,     573,    "RAZ",  1,      0,      0,      0ull},
5854         {"DOORBELL"                    ,        0,      1,      574,    "R/W1C",        0,      0,      0ull,   0ull},
5855         {"RESERVED_1_63"               ,        1,      63,     574,    "RAZ",  1,      0,      0,      0ull},
5856         {"DOORBELL"                    ,        0,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
5857         {"RESERVED_1_63"               ,        1,      63,     575,    "RAZ",  1,      0,      0,      0ull},
5858         {NULL,0,0,0,0,0,0,0,0}
5859 };
5860 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn31xx[] = {
5861          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
5862         {"cvmx_asx#_gmii_rx_clk_set"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      2,      0},
5863         {"cvmx_asx#_gmii_rx_dat_set"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1,      2,      2},
5864         {"cvmx_asx#_int_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      6,      4},
5865         {"cvmx_asx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     3,      6,      10},
5866         {"cvmx_asx#_prt_loop"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      4,      16},
5867         {"cvmx_asx#_rx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     5,      2,      20},
5868         {"cvmx_asx#_rx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     8,      2,      22},
5869         {"cvmx_asx#_tx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     9,      2,      24},
5870         {"cvmx_asx#_tx_comp_byp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     12,     4,      26},
5871         {"cvmx_asx#_tx_hi_water#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     13,     2,      30},
5872         {"cvmx_asx#_tx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     16,     2,      32},
5873         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     17,     2,      34},
5874         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     18,     2,      36},
5875         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     19,     2,      38},
5876         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     20,     2,      40},
5877         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     21,     19,     42},
5878         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     26,     2,      61},
5879         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     31,     19,     63},
5880         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     36,     2,      82},
5881         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     37,     2,      84},
5882         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     39,     2,      86},
5883         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     41,     2,      88},
5884         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     42,     2,      90},
5885         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     43,     2,      92},
5886         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     44,     1,      94},
5887         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     46,     3,      95},
5888         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     47,     2,      98},
5889         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     48,     4,      100},
5890         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     49,     2,      104},
5891         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     50,     3,      106},
5892         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     54,     7,      109},
5893         {"cvmx_dbg_data"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     56,     6,      116},
5894         {"cvmx_dfa_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     57,     3,      122},
5895         {"cvmx_dfa_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     58,     7,      125},
5896         {"cvmx_dfa_dbell"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     59,     2,      132},
5897         {"cvmx_dfa_ddr2_addr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     60,     6,      134},
5898         {"cvmx_dfa_ddr2_bus"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     61,     2,      140},
5899         {"cvmx_dfa_ddr2_cfg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     62,     16,     142},
5900         {"cvmx_dfa_ddr2_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     63,     6,      158},
5901         {"cvmx_dfa_ddr2_emrs"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     64,     4,      164},
5902         {"cvmx_dfa_ddr2_fcnt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     65,     2,      168},
5903         {"cvmx_dfa_ddr2_mrs"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     66,     4,      170},
5904         {"cvmx_dfa_ddr2_opt"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     67,     3,      174},
5905         {"cvmx_dfa_ddr2_pll"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     68,     14,     177},
5906         {"cvmx_dfa_ddr2_tmg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     69,     21,     191},
5907         {"cvmx_dfa_difctl"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     70,     4,      212},
5908         {"cvmx_dfa_difrdptr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     71,     3,      216},
5909         {"cvmx_dfa_eclkcfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     72,     14,     219},
5910         {"cvmx_dfa_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     73,     21,     233},
5911         {"cvmx_dfa_memfadr"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     74,     6,      254},
5912         {"cvmx_dfa_sbd_dbg0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     75,     1,      260},
5913         {"cvmx_dfa_sbd_dbg1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     76,     1,      261},
5914         {"cvmx_dfa_sbd_dbg2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     77,     1,      262},
5915         {"cvmx_dfa_sbd_dbg3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     78,     1,      263},
5916         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     79,     6,      264},
5917         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     80,     7,      270},
5918         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     81,     29,     277},
5919         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     82,     29,     306},
5920         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     83,     2,      335},
5921         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     91,     2,      337},
5922         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     99,     3,      339},
5923         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     100,    3,      342},
5924         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     101,    2,      345},
5925         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     102,    2,      347},
5926         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     103,    8,      349},
5927         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     104,    2,      357},
5928         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     105,    3,      359},
5929         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     106,    2,      362},
5930         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     107,    5,      364},
5931         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     110,    1,      369},
5932         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     113,    1,      370},
5933         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     116,    1,      371},
5934         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     119,    1,      372},
5935         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     122,    1,      373},
5936         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     125,    1,      374},
5937         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     128,    2,      375},
5938         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     131,    4,      377},
5939         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     134,    2,      381},
5940         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     137,    11,     383},
5941         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     140,    9,      394},
5942         {"cvmx_gmx#_rx#_frm_max"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     143,    2,      403},
5943         {"cvmx_gmx#_rx#_frm_min"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     146,    2,      405},
5944         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     149,    2,      407},
5945         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     152,    20,     409},
5946         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     155,    20,     429},
5947         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     158,    2,      449},
5948         {"cvmx_gmx#_rx#_rx_inbnd"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     161,    4,      451},
5949         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     164,    2,      455},
5950         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     167,    2,      457},
5951         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     170,    2,      459},
5952         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     173,    2,      461},
5953         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     176,    2,      463},
5954         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     179,    2,      465},
5955         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     182,    2,      467},
5956         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     185,    2,      469},
5957         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     188,    2,      471},
5958         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     191,    2,      473},
5959         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     194,    4,      475},
5960         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     197,    2,      479},
5961         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     200,    2,      481},
5962         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     203,    2,      483},
5963         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     206,    4,      485},
5964         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     207,    2,      489},
5965         {"cvmx_gmx#_rx_tx_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     208,    4,      491},
5966         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     209,    2,      495},
5967         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     212,    3,      497},
5968         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     213,    5,      500},
5969         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     216,    2,      505},
5970         {"cvmx_gmx#_tx#_clk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     219,    2,      507},
5971         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     222,    3,      509},
5972         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     225,    2,      512},
5973         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     228,    2,      514},
5974         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     231,    2,      516},
5975         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     234,    2,      518},
5976         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     237,    2,      520},
5977         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     240,    2,      522},
5978         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     243,    2,      524},
5979         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     246,    2,      526},
5980         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     249,    2,      528},
5981         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     252,    2,      530},
5982         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     255,    2,      532},
5983         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     258,    2,      534},
5984         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     261,    2,      536},
5985         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     264,    2,      538},
5986         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     267,    2,      540},
5987         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     270,    2,      542},
5988         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     273,    2,      544},
5989         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     276,    2,      546},
5990         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     279,    2,      548},
5991         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     282,    2,      550},
5992         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     283,    2,      552},
5993         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     284,    2,      554},
5994         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     285,    3,      556},
5995         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     286,    8,      559},
5996         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     287,    8,      567},
5997         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     288,    2,      575},
5998         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     289,    2,      577},
5999         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     290,    6,      579},
6000         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     291,    2,      585},
6001         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     292,    2,      587},
6002         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     293,    2,      589},
6003         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     294,    7,      591},
6004         {"cvmx_gpio_boot_ena"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     310,    3,      598},
6005         {"cvmx_gpio_dbg_ena"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     311,    2,      601},
6006         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     312,    2,      603},
6007         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     313,    2,      605},
6008         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     314,    2,      607},
6009         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     315,    2,      609},
6010         {"cvmx_gpio_xbit_cfg#"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     316,    6,      611},
6011         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     324,    19,     617},
6012         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     325,    6,      636},
6013         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     326,    3,      642},
6014         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     327,    5,      645},
6015         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     328,    5,      650},
6016         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     329,    1,      655},
6017         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     330,    1,      656},
6018         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     331,    5,      657},
6019         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     332,    5,      662},
6020         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     333,    5,      667},
6021         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     334,    5,      672},
6022         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     335,    1,      677},
6023         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     336,    1,      678},
6024         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     337,    2,      679},
6025         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     338,    2,      681},
6026         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     339,    2,      683},
6027         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     340,    2,      685},
6028         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     341,    17,     687},
6029         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     342,    2,      704},
6030         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     343,    1,      706},
6031         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     344,    10,     707},
6032         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     345,    6,      717},
6033         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     346,    6,      723},
6034         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     347,    2,      729},
6035         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     348,    2,      731},
6036         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     349,    2,      733},
6037         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     350,    3,      735},
6038         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     355,    2,      738},
6039         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     360,    6,      740},
6040         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     361,    5,      746},
6041         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     362,    6,      751},
6042         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     363,    7,      757},
6043         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     364,    2,      764},
6044         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     372,    2,      766},
6045         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     373,    3,      768},
6046         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     374,    5,      771},
6047         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     382,    3,      776},
6048         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     383,    2,      779},
6049         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     384,    2,      781},
6050         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     385,    2,      783},
6051         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     386,    7,      785},
6052         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     387,    6,      792},
6053         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     388,    8,      798},
6054         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     389,    9,      806},
6055         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     390,    10,     815},
6056         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     391,    5,      825},
6057         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     392,    4,      830},
6058         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     393,    2,      834},
6059         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     394,    17,     836},
6060         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     395,    19,     853},
6061         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     396,    3,      872},
6062         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     397,    4,      875},
6063         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     398,    2,      879},
6064         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     402,    17,     881},
6065         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     403,    4,      898},
6066         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     404,    2,      902},
6067         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     405,    3,      904},
6068         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     406,    2,      907},
6069         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     407,    2,      909},
6070         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     408,    2,      911},
6071         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     409,    7,      913},
6072         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     410,    6,      920},
6073         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     411,    3,      926},
6074         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     412,    3,      929},
6075         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     413,    2,      932},
6076         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     414,    2,      934},
6077         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     415,    2,      936},
6078         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     416,    3,      938},
6079         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     417,    15,     941},
6080         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     418,    9,      956},
6081         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     419,    20,     965},
6082         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     420,    2,      985},
6083         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     421,    2,      987},
6084         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     422,    18,     989},
6085         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     423,    5,      1007},
6086         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     424,    6,      1012},
6087         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     425,    2,      1018},
6088         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     426,    2,      1020},
6089         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     427,    14,     1022},
6090         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     428,    10,     1036},
6091         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     429,    2,      1046},
6092         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     430,    2,      1048},
6093         {"cvmx_lmc#_pll_bwctl"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     431,    3,      1050},
6094         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     432,    9,      1053},
6095         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     433,    5,      1062},
6096         {"cvmx_lmc#_wodt_ctl1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     434,    5,      1067},
6097         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     435,    5,      1072},
6098         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     436,    3,      1077},
6099         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     437,    3,      1080},
6100         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     438,    3,      1083},
6101         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     439,    5,      1086},
6102         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     441,    1,      1091},
6103         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     442,    10,     1092},
6104         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     450,    13,     1102},
6105         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     458,    4,      1115},
6106         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     459,    2,      1119},
6107         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     460,    2,      1121},
6108         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     461,    10,     1123},
6109         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     462,    9,      1133},
6110         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     463,    2,      1142},
6111         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     464,    8,      1144},
6112         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     465,    4,      1152},
6113         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     466,    2,      1156},
6114         {"cvmx_mio_fus_unlock"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     467,    2,      1158},
6115         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     468,    2,      1160},
6116         {"cvmx_mio_pll_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     469,    2,      1162},
6117         {"cvmx_mio_pll_setting"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     470,    2,      1164},
6118         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     471,    13,     1166},
6119         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     472,    12,     1179},
6120         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     473,    3,      1191},
6121         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     474,    3,      1194},
6122         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     475,    2,      1197},
6123         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     477,    2,      1199},
6124         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     479,    2,      1201},
6125         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     481,    7,      1203},
6126         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     483,    2,      1210},
6127         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     485,    7,      1212},
6128         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     487,    4,      1219},
6129         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     489,    8,      1223},
6130         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     491,    9,      1231},
6131         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     493,    7,      1240},
6132         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     495,    9,      1247},
6133         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     497,    2,      1256},
6134         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     499,    2,      1258},
6135         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     501,    4,      1260},
6136         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     503,    2,      1264},
6137         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     505,    2,      1266},
6138         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     507,    2,      1268},
6139         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     509,    4,      1270},
6140         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     511,    2,      1274},
6141         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     513,    2,      1276},
6142         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     515,    2,      1278},
6143         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     517,    2,      1280},
6144         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     519,    2,      1282},
6145         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     521,    2,      1284},
6146         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     523,    6,      1286},
6147         {"cvmx_mpi_cfg"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     525,    13,     1292},
6148         {"cvmx_mpi_dat#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     526,    2,      1305},
6149         {"cvmx_mpi_sts"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     535,    4,      1307},
6150         {"cvmx_mpi_tx"                 ,        CVMX_CSR_DB_TYPE_NCB,   64,     536,    6,      1311},
6151         {"cvmx_npi_base_addr_input#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     537,    2,      1317},
6152         {"cvmx_npi_base_addr_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     539,    2,      1319},
6153         {"cvmx_npi_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     541,    21,     1321},
6154         {"cvmx_npi_buff_size_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     542,    3,      1342},
6155         {"cvmx_npi_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     544,    18,     1345},
6156         {"cvmx_npi_dbg_select"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     545,    2,      1363},
6157         {"cvmx_npi_dma_control"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     546,    13,     1365},
6158         {"cvmx_npi_dma_highp_counts"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     547,    3,      1378},
6159         {"cvmx_npi_dma_highp_naddr"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     548,    3,      1381},
6160         {"cvmx_npi_dma_lowp_counts"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     549,    3,      1384},
6161         {"cvmx_npi_dma_lowp_naddr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     550,    3,      1387},
6162         {"cvmx_npi_highp_dbell"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     551,    2,      1390},
6163         {"cvmx_npi_highp_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     552,    2,      1392},
6164         {"cvmx_npi_input_control"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     553,    9,      1394},
6165         {"cvmx_npi_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     554,    54,     1403},
6166         {"cvmx_npi_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     555,    54,     1457},
6167         {"cvmx_npi_lowp_dbell"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     556,    2,      1511},
6168         {"cvmx_npi_lowp_ibuff_saddr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     557,    2,      1513},
6169         {"cvmx_npi_mem_access_subid#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     558,    8,      1515},
6170         {"cvmx_npi_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     562,    1,      1523},
6171         {"cvmx_npi_num_desc_output#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     563,    2,      1524},
6172         {"cvmx_npi_output_control"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     565,    23,     1526},
6173         {"cvmx_npi_p#_dbpair_addr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     566,    3,      1549},
6174         {"cvmx_npi_p#_instr_addr"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     568,    2,      1552},
6175         {"cvmx_npi_p#_instr_cnts"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     570,    3,      1554},
6176         {"cvmx_npi_p#_pair_cnts"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     572,    3,      1557},
6177         {"cvmx_npi_pci_burst_size"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     574,    3,      1560},
6178         {"cvmx_npi_pci_int_arb_cfg"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     575,    4,      1563},
6179         {"cvmx_npi_pci_read_cmd"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     576,    2,      1567},
6180         {"cvmx_npi_port32_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     577,    13,     1569},
6181         {"cvmx_npi_port33_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     578,    13,     1582},
6182         {"cvmx_npi_port_bp_control"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     579,    3,      1595},
6183         {"cvmx_npi_rsl_int_blocks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     580,    33,     1598},
6184         {"cvmx_npi_size_input#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     581,    2,      1631},
6185         {"cvmx_npi_win_read_to"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     583,    2,      1633},
6186         {"cvmx_pci_bar1_index#"        ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     584,    5,      1635},
6187         {"cvmx_pci_cfg00"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     616,    2,      1640},
6188         {"cvmx_pci_cfg01"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     617,    24,     1642},
6189         {"cvmx_pci_cfg02"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     618,    2,      1666},
6190         {"cvmx_pci_cfg03"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     619,    7,      1668},
6191         {"cvmx_pci_cfg04"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     620,    5,      1675},
6192         {"cvmx_pci_cfg05"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     621,    1,      1680},
6193         {"cvmx_pci_cfg06"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     622,    5,      1681},
6194         {"cvmx_pci_cfg07"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     623,    1,      1686},
6195         {"cvmx_pci_cfg08"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     624,    4,      1687},
6196         {"cvmx_pci_cfg09"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     625,    2,      1691},
6197         {"cvmx_pci_cfg10"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     626,    1,      1693},
6198         {"cvmx_pci_cfg11"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     627,    2,      1694},
6199         {"cvmx_pci_cfg12"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     628,    4,      1696},
6200         {"cvmx_pci_cfg13"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     629,    2,      1700},
6201         {"cvmx_pci_cfg15"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     630,    4,      1702},
6202         {"cvmx_pci_cfg16"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     631,    16,     1706},
6203         {"cvmx_pci_cfg17"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     632,    1,      1722},
6204         {"cvmx_pci_cfg18"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     633,    1,      1723},
6205         {"cvmx_pci_cfg19"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     634,    18,     1724},
6206         {"cvmx_pci_cfg20"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     635,    1,      1742},
6207         {"cvmx_pci_cfg21"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     636,    1,      1743},
6208         {"cvmx_pci_cfg22"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     637,    7,      1744},
6209         {"cvmx_pci_cfg56"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     638,    7,      1751},
6210         {"cvmx_pci_cfg57"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     639,    13,     1758},
6211         {"cvmx_pci_cfg58"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     640,    10,     1771},
6212         {"cvmx_pci_cfg59"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     641,    10,     1781},
6213         {"cvmx_pci_cfg60"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     642,    7,      1791},
6214         {"cvmx_pci_cfg61"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     643,    2,      1798},
6215         {"cvmx_pci_cfg62"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     644,    1,      1800},
6216         {"cvmx_pci_cfg63"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     645,    2,      1801},
6217         {"cvmx_pci_ctl_status_2"       ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     646,    16,     1803},
6218         {"cvmx_pci_dbell#"             ,        CVMX_CSR_DB_TYPE_PCI,   32,     647,    2,      1819},
6219         {"cvmx_pci_dma_cnt#"           ,        CVMX_CSR_DB_TYPE_PCI,   32,     649,    1,      1821},
6220         {"cvmx_pci_dma_int_lev#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     651,    1,      1822},
6221         {"cvmx_pci_dma_time#"          ,        CVMX_CSR_DB_TYPE_PCI,   32,     653,    1,      1823},
6222         {"cvmx_pci_instr_count#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     655,    1,      1824},
6223         {"cvmx_pci_int_enb"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     657,    33,     1825},
6224         {"cvmx_pci_int_enb2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     658,    33,     1858},
6225         {"cvmx_pci_int_sum"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     659,    33,     1891},
6226         {"cvmx_pci_int_sum2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     660,    33,     1924},
6227         {"cvmx_pci_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI,   32,     661,    2,      1957},
6228         {"cvmx_pci_pkt_credits#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     662,    2,      1959},
6229         {"cvmx_pci_pkts_sent#"         ,        CVMX_CSR_DB_TYPE_PCI,   32,     664,    1,      1961},
6230         {"cvmx_pci_pkts_sent_int_lev#" ,        CVMX_CSR_DB_TYPE_PCI,   32,     666,    1,      1962},
6231         {"cvmx_pci_pkts_sent_time#"    ,        CVMX_CSR_DB_TYPE_PCI,   32,     668,    1,      1963},
6232         {"cvmx_pci_read_cmd_6"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     670,    3,      1964},
6233         {"cvmx_pci_read_cmd_c"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     671,    3,      1967},
6234         {"cvmx_pci_read_cmd_e"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     672,    3,      1970},
6235         {"cvmx_pci_read_timeout"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     673,    3,      1973},
6236         {"cvmx_pci_scm_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     674,    2,      1976},
6237         {"cvmx_pci_tsr_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     675,    2,      1978},
6238         {"cvmx_pci_win_rd_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     676,    4,      1980},
6239         {"cvmx_pci_win_rd_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     677,    1,      1984},
6240         {"cvmx_pci_win_wr_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     678,    4,      1985},
6241         {"cvmx_pci_win_wr_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     679,    1,      1989},
6242         {"cvmx_pci_win_wr_mask"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     680,    2,      1990},
6243         {"cvmx_pcm#_dma_cfg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     681,    12,     1992},
6244         {"cvmx_pcm#_int_ena"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     685,    9,      2004},
6245         {"cvmx_pcm#_int_sum"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     689,    9,      2013},
6246         {"cvmx_pcm#_rxaddr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     693,    2,      2022},
6247         {"cvmx_pcm#_rxcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     697,    2,      2024},
6248         {"cvmx_pcm#_rxmsk0"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     701,    1,      2026},
6249         {"cvmx_pcm#_rxmsk1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     705,    1,      2027},
6250         {"cvmx_pcm#_rxmsk2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     709,    1,      2028},
6251         {"cvmx_pcm#_rxmsk3"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     713,    1,      2029},
6252         {"cvmx_pcm#_rxmsk4"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     717,    1,      2030},
6253         {"cvmx_pcm#_rxmsk5"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     721,    1,      2031},
6254         {"cvmx_pcm#_rxmsk6"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     725,    1,      2032},
6255         {"cvmx_pcm#_rxmsk7"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     729,    1,      2033},
6256         {"cvmx_pcm#_rxstart"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     733,    3,      2034},
6257         {"cvmx_pcm#_tdm_cfg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     737,    6,      2037},
6258         {"cvmx_pcm#_tdm_dbg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     741,    1,      2043},
6259         {"cvmx_pcm#_txaddr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     745,    3,      2044},
6260         {"cvmx_pcm#_txcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     749,    2,      2047},
6261         {"cvmx_pcm#_txmsk0"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     753,    1,      2049},
6262         {"cvmx_pcm#_txmsk1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     757,    1,      2050},
6263         {"cvmx_pcm#_txmsk2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     761,    1,      2051},
6264         {"cvmx_pcm#_txmsk3"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     765,    1,      2052},
6265         {"cvmx_pcm#_txmsk4"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     769,    1,      2053},
6266         {"cvmx_pcm#_txmsk5"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     773,    1,      2054},
6267         {"cvmx_pcm#_txmsk6"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     777,    1,      2055},
6268         {"cvmx_pcm#_txmsk7"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     781,    1,      2056},
6269         {"cvmx_pcm#_txstart"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     785,    3,      2057},
6270         {"cvmx_pcm_clk#_cfg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     789,    12,     2060},
6271         {"cvmx_pcm_clk#_dbg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     791,    1,      2072},
6272         {"cvmx_pcm_clk#_gen"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     793,    3,      2073},
6273         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     795,    2,      2076},
6274         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     796,    4,      2078},
6275         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     800,    8,      2082},
6276         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     801,    16,     2090},
6277         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     802,    10,     2106},
6278         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     803,    10,     2116},
6279         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     804,    2,      2126},
6280         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     805,    16,     2128},
6281         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     810,    25,     2144},
6282         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     815,    2,      2169},
6283         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     879,    2,      2171},
6284         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     887,    9,      2173},
6285         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     891,    2,      2182},
6286         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     892,    2,      2184},
6287         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     893,    2,      2186},
6288         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     898,    2,      2188},
6289         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     903,    2,      2190},
6290         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     908,    2,      2192},
6291         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     913,    2,      2194},
6292         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     918,    2,      2196},
6293         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     923,    2,      2198},
6294         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     928,    2,      2200},
6295         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     933,    2,      2202},
6296         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     938,    2,      2204},
6297         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     943,    2,      2206},
6298         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     944,    2,      2208},
6299         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     949,    2,      2210},
6300         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     954,    2,      2212},
6301         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     959,    2,      2214},
6302         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1023,   2,      2216},
6303         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1024,   3,      2218},
6304         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1025,   3,      2221},
6305         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1026,   2,      2224},
6306         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1027,   2,      2226},
6307         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1028,   4,      2228},
6308         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1029,   5,      2232},
6309         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1030,   4,      2237},
6310         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1031,   5,      2241},
6311         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1032,   1,      2246},
6312         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1033,   4,      2247},
6313         {"cvmx_pko_mem_debug14"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1034,   2,      2251},
6314         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1035,   5,      2253},
6315         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1036,   5,      2258},
6316         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1037,   1,      2263},
6317         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1038,   19,     2264},
6318         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1039,   7,      2283},
6319         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1040,   4,      2290},
6320         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1041,   6,      2294},
6321         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1042,   6,      2300},
6322         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1043,   9,      2306},
6323         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1044,   5,      2315},
6324         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1045,   13,     2320},
6325         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1046,   4,      2333},
6326         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1047,   2,      2337},
6327         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1048,   3,      2339},
6328         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1049,   5,      2342},
6329         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1050,   3,      2347},
6330         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1051,   3,      2350},
6331         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1052,   2,      2353},
6332         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1053,   3,      2355},
6333         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1054,   12,     2358},
6334         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1055,   2,      2370},
6335         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1056,   9,      2372},
6336         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1057,   3,      2381},
6337         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1058,   2,      2384},
6338         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1066,   2,      2386},
6339         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1067,   2,      2388},
6340         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1068,   2,      2390},
6341         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1069,   2,      2392},
6342         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1071,   5,      2394},
6343         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1079,   10,     2399},
6344         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1087,   2,      2409},
6345         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1088,   2,      2411},
6346         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1089,   2,      2413},
6347         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1097,   3,      2415},
6348         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1098,   6,      2418},
6349         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1114,   5,      2424},
6350         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1115,   7,      2429},
6351         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1131,   2,      2436},
6352         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1147,   3,      2438},
6353         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1148,   5,      2441},
6354         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1149,   8,      2446},
6355         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1150,   6,      2454},
6356         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1151,   2,      2460},
6357         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1152,   4,      2462},
6358         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1153,   4,      2466},
6359         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1154,   6,      2470},
6360         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1155,   3,      2476},
6361         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1156,   5,      2479},
6362         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1157,   4,      2484},
6363         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1158,   6,      2488},
6364         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1159,   4,      2494},
6365         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1160,   2,      2498},
6366         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1161,   4,      2500},
6367         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1162,   2,      2504},
6368         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1163,   3,      2506},
6369         {"cvmx_tra_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1164,   4,      2509},
6370         {"cvmx_tra_ctl"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1165,   12,     2513},
6371         {"cvmx_tra_cycles_since"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1166,   3,      2525},
6372         {"cvmx_tra_filt_adr_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1167,   2,      2528},
6373         {"cvmx_tra_filt_adr_msk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1168,   2,      2530},
6374         {"cvmx_tra_filt_cmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1169,   17,     2532},
6375         {"cvmx_tra_filt_did"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1170,   12,     2549},
6376         {"cvmx_tra_filt_sid"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1171,   6,      2561},
6377         {"cvmx_tra_int_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1172,   5,      2567},
6378         {"cvmx_tra_read_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1173,   1,      2572},
6379         {"cvmx_tra_trig0_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1174,   2,      2573},
6380         {"cvmx_tra_trig0_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1175,   2,      2575},
6381         {"cvmx_tra_trig0_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1176,   17,     2577},
6382         {"cvmx_tra_trig0_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1177,   12,     2594},
6383         {"cvmx_tra_trig0_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1178,   6,      2606},
6384         {"cvmx_tra_trig1_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1179,   2,      2612},
6385         {"cvmx_tra_trig1_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1180,   2,      2614},
6386         {"cvmx_tra_trig1_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1181,   17,     2616},
6387         {"cvmx_tra_trig1_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1182,   12,     2633},
6388         {"cvmx_tra_trig1_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1183,   6,      2645},
6389         {"cvmx_usbc#_daint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1184,   2,      2651},
6390         {"cvmx_usbc#_daintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1185,   2,      2653},
6391         {"cvmx_usbc#_dcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1186,   8,      2655},
6392         {"cvmx_usbc#_dctl"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1187,   11,     2663},
6393         {"cvmx_usbc#_diepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1188,   15,     2674},
6394         {"cvmx_usbc#_diepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1193,   8,      2689},
6395         {"cvmx_usbc#_diepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1198,   8,      2697},
6396         {"cvmx_usbc#_dieptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1199,   4,      2705},
6397         {"cvmx_usbc#_doepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1204,   15,     2709},
6398         {"cvmx_usbc#_doepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1209,   6,      2724},
6399         {"cvmx_usbc#_doepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1214,   6,      2730},
6400         {"cvmx_usbc#_doeptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1215,   4,      2736},
6401         {"cvmx_usbc#_dptxfsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1220,   2,      2740},
6402         {"cvmx_usbc#_dsts"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1224,   6,      2742},
6403         {"cvmx_usbc#_dtknqr1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1225,   4,      2748},
6404         {"cvmx_usbc#_dtknqr2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1226,   1,      2752},
6405         {"cvmx_usbc#_dtknqr3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1227,   1,      2753},
6406         {"cvmx_usbc#_dtknqr4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1228,   1,      2754},
6407         {"cvmx_usbc#_gahbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1229,   7,      2755},
6408         {"cvmx_usbc#_ghwcfg1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1230,   1,      2762},
6409         {"cvmx_usbc#_ghwcfg2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1231,   14,     2763},
6410         {"cvmx_usbc#_ghwcfg3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1232,   10,     2777},
6411         {"cvmx_usbc#_ghwcfg4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1233,   12,     2787},
6412         {"cvmx_usbc#_gintmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1234,   32,     2799},
6413         {"cvmx_usbc#_gintsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1235,   32,     2831},
6414         {"cvmx_usbc#_gnptxfsiz"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1236,   2,      2863},
6415         {"cvmx_usbc#_gnptxsts"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1237,   4,      2865},
6416         {"cvmx_usbc#_gotgctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1238,   13,     2869},
6417         {"cvmx_usbc#_gotgint"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1239,   10,     2882},
6418         {"cvmx_usbc#_grstctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1240,   10,     2892},
6419         {"cvmx_usbc#_grxfsiz"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1241,   2,      2902},
6420         {"cvmx_usbc#_grxstspd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1242,   6,      2904},
6421         {"cvmx_usbc#_grxstsph"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1243,   5,      2910},
6422         {"cvmx_usbc#_grxstsrd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1244,   6,      2915},
6423         {"cvmx_usbc#_grxstsrh"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1245,   5,      2921},
6424         {"cvmx_usbc#_gsnpsid"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1246,   1,      2926},
6425         {"cvmx_usbc#_gusbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1247,   13,     2927},
6426         {"cvmx_usbc#_haint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1248,   2,      2940},
6427         {"cvmx_usbc#_haintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1249,   2,      2942},
6428         {"cvmx_usbc#_hcchar#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1250,   11,     2944},
6429         {"cvmx_usbc#_hcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1258,   3,      2955},
6430         {"cvmx_usbc#_hcint#"           ,        CVMX_CSR_DB_TYPE_NCB,   32,     1259,   12,     2958},
6431         {"cvmx_usbc#_hcintmsk#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1267,   12,     2970},
6432         {"cvmx_usbc#_hcsplt#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1275,   6,      2982},
6433         {"cvmx_usbc#_hctsiz#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1283,   4,      2988},
6434         {"cvmx_usbc#_hfir"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1291,   2,      2992},
6435         {"cvmx_usbc#_hfnum"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1292,   2,      2994},
6436         {"cvmx_usbc#_hprt"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1293,   15,     2996},
6437         {"cvmx_usbc#_hptxfsiz"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1294,   2,      3011},
6438         {"cvmx_usbc#_hptxsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1295,   3,      3013},
6439         {"cvmx_usbc#_nptxdfifo#"       ,        CVMX_CSR_DB_TYPE_NCB,   32,     1296,   1,      3016},
6440         {"cvmx_usbc#_pcgcctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1304,   6,      3017},
6441         {"cvmx_usbn#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1305,   4,      3023},
6442         {"cvmx_usbn#_clk_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1306,   15,     3027},
6443         {"cvmx_usbn#_ctl_status"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1307,   6,      3042},
6444         {"cvmx_usbn#_dma0_inb_chn0"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1308,   2,      3048},
6445         {"cvmx_usbn#_dma0_inb_chn1"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1309,   2,      3050},
6446         {"cvmx_usbn#_dma0_inb_chn2"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1310,   2,      3052},
6447         {"cvmx_usbn#_dma0_inb_chn3"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1311,   2,      3054},
6448         {"cvmx_usbn#_dma0_inb_chn4"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1312,   2,      3056},
6449         {"cvmx_usbn#_dma0_inb_chn5"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1313,   2,      3058},
6450         {"cvmx_usbn#_dma0_inb_chn6"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1314,   2,      3060},
6451         {"cvmx_usbn#_dma0_inb_chn7"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1315,   2,      3062},
6452         {"cvmx_usbn#_dma0_outb_chn0"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1316,   2,      3064},
6453         {"cvmx_usbn#_dma0_outb_chn1"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1317,   2,      3066},
6454         {"cvmx_usbn#_dma0_outb_chn2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1318,   2,      3068},
6455         {"cvmx_usbn#_dma0_outb_chn3"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1319,   2,      3070},
6456         {"cvmx_usbn#_dma0_outb_chn4"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1320,   2,      3072},
6457         {"cvmx_usbn#_dma0_outb_chn5"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1321,   2,      3074},
6458         {"cvmx_usbn#_dma0_outb_chn6"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1322,   2,      3076},
6459         {"cvmx_usbn#_dma0_outb_chn7"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1323,   2,      3078},
6460         {"cvmx_usbn#_dma_test"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1324,   7,      3080},
6461         {"cvmx_usbn#_int_enb"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1325,   39,     3087},
6462         {"cvmx_usbn#_int_sum"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1326,   39,     3126},
6463         {"cvmx_usbn#_usbp_ctl_status"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1327,   22,     3165},
6464         {"cvmx_zip_cmd_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1328,   3,      3187},
6465         {"cvmx_zip_cmd_buf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1329,   5,      3190},
6466         {"cvmx_zip_cmd_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1330,   3,      3195},
6467         {"cvmx_zip_constants"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1331,   6,      3198},
6468         {"cvmx_zip_debug0"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1332,   2,      3204},
6469         {"cvmx_zip_error"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1333,   2,      3206},
6470         {"cvmx_zip_int_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1334,   2,      3208},
6471         {NULL,0,0,0,0,0}
6472 };
6473 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn31xx[] = {
6474         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
6475         {"ASX0_GMII_RX_CLK_SET"        ,           0x11800B0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
6476         {"ASX0_GMII_RX_DAT_SET"        ,           0x11800B0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
6477         {"ASX0_INT_EN"                 ,           0x11800B0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
6478         {"ASX0_INT_REG"                ,           0x11800B0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
6479         {"ASX0_PRT_LOOP"               ,           0x11800B0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
6480         {"ASX0_RX_CLK_SET000"          ,           0x11800B0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
6481         {"ASX0_RX_CLK_SET001"          ,           0x11800B0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
6482         {"ASX0_RX_CLK_SET002"          ,           0x11800B0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
6483         {"ASX0_RX_PRT_EN"              ,           0x11800B0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
6484         {"ASX0_TX_CLK_SET000"          ,           0x11800B0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
6485         {"ASX0_TX_CLK_SET001"          ,           0x11800B0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
6486         {"ASX0_TX_CLK_SET002"          ,           0x11800B0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
6487         {"ASX0_TX_COMP_BYP"            ,           0x11800B0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
6488         {"ASX0_TX_HI_WATER000"         ,           0x11800B0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
6489         {"ASX0_TX_HI_WATER001"         ,           0x11800B0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
6490         {"ASX0_TX_HI_WATER002"         ,           0x11800B0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
6491         {"ASX0_TX_PRT_EN"              ,           0x11800B0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
6492         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     11},
6493         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     12},
6494         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     13},
6495         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     14},
6496         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     15},
6497         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     15},
6498         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     15},
6499         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     15},
6500         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     15},
6501         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
6502         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
6503         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
6504         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
6505         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
6506         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
6507         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
6508         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
6509         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
6510         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
6511         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     18},
6512         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     19},
6513         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     19},
6514         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
6515         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
6516         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     21},
6517         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     22},
6518         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     23},
6519         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
6520         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
6521         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
6522         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
6523         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
6524         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
6525         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
6526         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
6527         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
6528         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
6529         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
6530         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
6531         {"DBG_DATA"                    ,           0x11F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
6532         {"DFA_BST0"                    ,           0x11800300007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     32},
6533         {"DFA_BST1"                    ,           0x11800300007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     33},
6534         {"DFA_DBELL"                   ,           0x1370000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
6535         {"DFA_DDR2_ADDR"               ,           0x1180030000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     35},
6536         {"DFA_DDR2_BUS"                ,           0x1180030000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     36},
6537         {"DFA_DDR2_CFG"                ,           0x1180030000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
6538         {"DFA_DDR2_COMP"               ,           0x1180030000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
6539         {"DFA_DDR2_EMRS"               ,           0x1180030000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     39},
6540         {"DFA_DDR2_FCNT"               ,           0x1180030000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
6541         {"DFA_DDR2_MRS"                ,           0x1180030000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
6542         {"DFA_DDR2_OPT"                ,           0x1180030000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     42},
6543         {"DFA_DDR2_PLL"                ,           0x1180030000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     43},
6544         {"DFA_DDR2_TMG"                ,           0x1180030000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
6545         {"DFA_DIFCTL"                  ,           0x1370600000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     45},
6546         {"DFA_DIFRDPTR"                ,           0x1370200000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     46},
6547         {"DFA_ECLKCFG"                 ,           0x1180030000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
6548         {"DFA_ERR"                     ,           0x1180030000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
6549         {"DFA_MEMFADR"                 ,           0x1180030000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
6550         {"DFA_SBD_DBG0"                ,           0x1180030000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
6551         {"DFA_SBD_DBG1"                ,           0x1180030000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
6552         {"DFA_SBD_DBG2"                ,           0x1180030000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
6553         {"DFA_SBD_DBG3"                ,           0x1180030000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
6554         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
6555         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
6556         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
6557         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
6558         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
6559         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
6560         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
6561         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
6562         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
6563         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
6564         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
6565         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
6566         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
6567         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
6568         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
6569         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
6570         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
6571         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
6572         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
6573         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
6574         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
6575         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
6576         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
6577         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
6578         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
6579         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
6580         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
6581         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
6582         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
6583         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
6584         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
6585         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
6586         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
6587         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
6588         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
6589         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
6590         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
6591         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
6592         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
6593         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
6594         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
6595         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
6596         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
6597         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
6598         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
6599         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
6600         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
6601         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
6602         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
6603         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
6604         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
6605         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
6606         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
6607         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
6608         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
6609         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
6610         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
6611         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
6612         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
6613         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
6614         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
6615         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
6616         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
6617         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
6618         {"GMX0_RX000_FRM_MAX"          ,           0x1180008000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
6619         {"GMX0_RX001_FRM_MAX"          ,           0x1180008000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
6620         {"GMX0_RX002_FRM_MAX"          ,           0x1180008001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
6621         {"GMX0_RX000_FRM_MIN"          ,           0x1180008000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
6622         {"GMX0_RX001_FRM_MIN"          ,           0x1180008000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
6623         {"GMX0_RX002_FRM_MIN"          ,           0x1180008001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
6624         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
6625         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
6626         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
6627         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
6628         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
6629         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
6630         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
6631         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
6632         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
6633         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
6634         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
6635         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
6636         {"GMX0_RX000_RX_INBND"         ,           0x1180008000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
6637         {"GMX0_RX001_RX_INBND"         ,           0x1180008000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
6638         {"GMX0_RX002_RX_INBND"         ,           0x1180008001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
6639         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
6640         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
6641         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
6642         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
6643         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
6644         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
6645         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
6646         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
6647         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
6648         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
6649         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
6650         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
6651         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
6652         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
6653         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
6654         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
6655         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
6656         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
6657         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
6658         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
6659         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
6660         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
6661         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
6662         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
6663         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
6664         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
6665         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
6666         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
6667         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
6668         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
6669         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
6670         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
6671         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
6672         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
6673         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
6674         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
6675         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
6676         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
6677         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
6678         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
6679         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
6680         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
6681         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
6682         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
6683         {"GMX0_RX_TX_STATUS"           ,           0x11800080007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
6684         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
6685         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
6686         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
6687         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
6688         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
6689         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
6690         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
6691         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
6692         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
6693         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
6694         {"GMX0_TX000_CLK"              ,           0x1180008000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
6695         {"GMX0_TX001_CLK"              ,           0x1180008000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
6696         {"GMX0_TX002_CLK"              ,           0x1180008001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
6697         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
6698         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
6699         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
6700         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
6701         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
6702         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
6703         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
6704         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
6705         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
6706         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
6707         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
6708         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
6709         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
6710         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
6711         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
6712         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
6713         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
6714         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
6715         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
6716         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
6717         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
6718         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
6719         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
6720         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
6721         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
6722         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
6723         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
6724         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
6725         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
6726         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
6727         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
6728         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
6729         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
6730         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
6731         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
6732         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
6733         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
6734         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
6735         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
6736         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
6737         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
6738         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
6739         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
6740         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
6741         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
6742         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
6743         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
6744         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
6745         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
6746         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
6747         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
6748         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
6749         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
6750         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
6751         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
6752         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
6753         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
6754         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
6755         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
6756         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
6757         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
6758         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
6759         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
6760         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
6761         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
6762         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
6763         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
6764         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
6765         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
6766         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
6767         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
6768         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
6769         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6770         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6771         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6772         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6773         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6774         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6775         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6776         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6777         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6778         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6779         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6780         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6781         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6782         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6783         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6784         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     141},
6785         {"GPIO_BOOT_ENA"               ,           0x10700000008A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     142},
6786         {"GPIO_DBG_ENA"                ,           0x10700000008A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     143},
6787         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     144},
6788         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     145},
6789         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     146},
6790         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     147},
6791         {"GPIO_XBIT_CFG16"             ,           0x1070000000900ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
6792         {"GPIO_XBIT_CFG17"             ,           0x1070000000908ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
6793         {"GPIO_XBIT_CFG18"             ,           0x1070000000910ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
6794         {"GPIO_XBIT_CFG19"             ,           0x1070000000918ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
6795         {"GPIO_XBIT_CFG20"             ,           0x1070000000920ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
6796         {"GPIO_XBIT_CFG21"             ,           0x1070000000928ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
6797         {"GPIO_XBIT_CFG22"             ,           0x1070000000930ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
6798         {"GPIO_XBIT_CFG23"             ,           0x1070000000938ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
6799         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
6800         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
6801         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
6802         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
6803         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
6804         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
6805         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
6806         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
6807         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
6808         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
6809         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
6810         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
6811         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
6812         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
6813         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
6814         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
6815         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     165},
6816         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
6817         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     167},
6818         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     168},
6819         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
6820         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     170},
6821         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     171},
6822         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     172},
6823         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     173},
6824         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     174},
6825         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     175},
6826         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     175},
6827         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     175},
6828         {"IPD_PORT32_BP_PAGE_CNT"      ,           0x14F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     175},
6829         {"IPD_PORT33_BP_PAGE_CNT"      ,           0x14F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     175},
6830         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     176},
6831         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     176},
6832         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     176},
6833         {"IPD_PORT_BP_COUNTERS_PAIR32" ,           0x14F00000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     176},
6834         {"IPD_PORT_BP_COUNTERS_PAIR33" ,           0x14F00000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     176},
6835         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     177},
6836         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     178},
6837         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     179},
6838         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     180},
6839         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     181},
6840         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     181},
6841         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     181},
6842         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     181},
6843         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     181},
6844         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     181},
6845         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     181},
6846         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     181},
6847         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     182},
6848         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     183},
6849         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     184},
6850         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     184},
6851         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     184},
6852         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     184},
6853         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     184},
6854         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     184},
6855         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     184},
6856         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     184},
6857         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     185},
6858         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     186},
6859         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     187},
6860         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     188},
6861         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
6862         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
6863         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     191},
6864         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     192},
6865         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     193},
6866         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     194},
6867         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     195},
6868         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     196},
6869         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     197},
6870         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     198},
6871         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     199},
6872         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     200},
6873         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
6874         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
6875         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
6876         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
6877         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     202},
6878         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     203},
6879         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     204},
6880         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     205},
6881         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     206},
6882         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     207},
6883         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     208},
6884         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     209},
6885         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     210},
6886         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     211},
6887         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     212},
6888         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     213},
6889         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
6890         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
6891         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
6892         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
6893         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
6894         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     219},
6895         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     220},
6896         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     221},
6897         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
6898         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
6899         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
6900         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     225},
6901         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     226},
6902         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     227},
6903         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
6904         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
6905         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
6906         {"LMC0_PLL_BWCTL"              ,           0x1180088000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
6907         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     232},
6908         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
6909         {"LMC0_WODT_CTL1"              ,           0x1180088000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     234},
6910         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     235},
6911         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     236},
6912         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     237},
6913         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
6914         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     239},
6915         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     239},
6916         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     240},
6917         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
6918         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
6919         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
6920         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
6921         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
6922         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
6923         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
6924         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
6925         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
6926         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
6927         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
6928         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
6929         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
6930         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
6931         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
6932         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
6933         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     243},
6934         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     244},
6935         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     245},
6936         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     246},
6937         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     247},
6938         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     248},
6939         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     249},
6940         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
6941         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
6942         {"MIO_FUS_UNLOCK"              ,           0x1180000001578ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
6943         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
6944         {"MIO_PLL_CTL"                 ,           0x1180000001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
6945         {"MIO_PLL_SETTING"             ,           0x1180000001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
6946         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
6947         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
6948         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
6949         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
6950         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
6951         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
6952         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
6953         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
6954         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
6955         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
6956         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
6957         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
6958         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
6959         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
6960         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
6961         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
6962         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
6963         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
6964         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
6965         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
6966         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
6967         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
6968         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
6969         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
6970         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
6971         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
6972         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
6973         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
6974         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
6975         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
6976         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
6977         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
6978         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
6979         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
6980         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
6981         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
6982         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
6983         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
6984         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
6985         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
6986         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
6987         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
6988         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
6989         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
6990         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
6991         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
6992         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
6993         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
6994         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
6995         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
6996         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
6997         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
6998         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
6999         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
7000         {"MPI_CFG"                     ,           0x1070000001000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     285},
7001         {"MPI_DAT0"                    ,           0x1070000001080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
7002         {"MPI_DAT1"                    ,           0x1070000001088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
7003         {"MPI_DAT2"                    ,           0x1070000001090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
7004         {"MPI_DAT3"                    ,           0x1070000001098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
7005         {"MPI_DAT4"                    ,           0x10700000010A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
7006         {"MPI_DAT5"                    ,           0x10700000010A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
7007         {"MPI_DAT6"                    ,           0x10700000010B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
7008         {"MPI_DAT7"                    ,           0x10700000010B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
7009         {"MPI_DAT8"                    ,           0x10700000010C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
7010         {"MPI_STS"                     ,           0x1070000001008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     287},
7011         {"MPI_TX"                      ,           0x1070000001010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     288},
7012         {"NPI_BASE_ADDR_INPUT0"        ,           0x11F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     289},
7013         {"NPI_BASE_ADDR_INPUT1"        ,           0x11F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     289},
7014         {"NPI_BASE_ADDR_OUTPUT0"       ,           0x11F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     290},
7015         {"NPI_BASE_ADDR_OUTPUT1"       ,           0x11F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     290},
7016         {"NPI_BIST_STATUS"             ,           0x11F00000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     291},
7017         {"NPI_BUFF_SIZE_OUTPUT0"       ,           0x11F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     292},
7018         {"NPI_BUFF_SIZE_OUTPUT1"       ,           0x11F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     292},
7019         {"NPI_CTL_STATUS"              ,           0x11F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     293},
7020         {"NPI_DBG_SELECT"              ,           0x11F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     294},
7021         {"NPI_DMA_CONTROL"             ,           0x11F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     295},
7022         {"NPI_DMA_HIGHP_COUNTS"        ,           0x11F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     296},
7023         {"NPI_DMA_HIGHP_NADDR"         ,           0x11F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     297},
7024         {"NPI_DMA_LOWP_COUNTS"         ,           0x11F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     298},
7025         {"NPI_DMA_LOWP_NADDR"          ,           0x11F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     299},
7026         {"NPI_HIGHP_DBELL"             ,           0x11F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     300},
7027         {"NPI_HIGHP_IBUFF_SADDR"       ,           0x11F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     301},
7028         {"NPI_INPUT_CONTROL"           ,           0x11F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     302},
7029         {"NPI_INT_ENB"                 ,           0x11F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     303},
7030         {"NPI_INT_SUM"                 ,           0x11F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     304},
7031         {"NPI_LOWP_DBELL"              ,           0x11F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     305},
7032         {"NPI_LOWP_IBUFF_SADDR"        ,           0x11F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     306},
7033         {"NPI_MEM_ACCESS_SUBID3"       ,           0x11F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     307},
7034         {"NPI_MEM_ACCESS_SUBID4"       ,           0x11F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     307},
7035         {"NPI_MEM_ACCESS_SUBID5"       ,           0x11F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     307},
7036         {"NPI_MEM_ACCESS_SUBID6"       ,           0x11F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     307},
7037         {"NPI_MSI_RCV"                 ,           0x11F0000001190ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     308},
7038         {"NPI_NUM_DESC_OUTPUT0"        ,           0x11F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     309},
7039         {"NPI_NUM_DESC_OUTPUT1"        ,           0x11F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     309},
7040         {"NPI_OUTPUT_CONTROL"          ,           0x11F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     310},
7041         {"NPI_P0_DBPAIR_ADDR"          ,           0x11F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     311},
7042         {"NPI_P1_DBPAIR_ADDR"          ,           0x11F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     311},
7043         {"NPI_P0_INSTR_ADDR"           ,           0x11F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     312},
7044         {"NPI_P1_INSTR_ADDR"           ,           0x11F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     312},
7045         {"NPI_P0_INSTR_CNTS"           ,           0x11F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     313},
7046         {"NPI_P1_INSTR_CNTS"           ,           0x11F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     313},
7047         {"NPI_P0_PAIR_CNTS"            ,           0x11F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     314},
7048         {"NPI_P1_PAIR_CNTS"            ,           0x11F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     314},
7049         {"NPI_PCI_BURST_SIZE"          ,           0x11F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     315},
7050         {"NPI_PCI_INT_ARB_CFG"         ,           0x11F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     316},
7051         {"NPI_PCI_READ_CMD"            ,           0x11F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     317},
7052         {"NPI_PORT32_INSTR_HDR"        ,           0x11F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     318},
7053         {"NPI_PORT33_INSTR_HDR"        ,           0x11F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     319},
7054         {"NPI_PORT_BP_CONTROL"         ,           0x11F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     320},
7055         {"NPI_RSL_INT_BLOCKS"          ,           0x11F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     321},
7056         {"NPI_SIZE_INPUT0"             ,           0x11F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     322},
7057         {"NPI_SIZE_INPUT1"             ,           0x11F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     322},
7058         {"NPI_WIN_READ_TO"             ,           0x11F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     323},
7059         {"PCI_BAR1_INDEX0"             ,           0x11F0000001100ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7060         {"PCI_BAR1_INDEX1"             ,           0x11F0000001104ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7061         {"PCI_BAR1_INDEX2"             ,           0x11F0000001108ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7062         {"PCI_BAR1_INDEX3"             ,           0x11F000000110Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7063         {"PCI_BAR1_INDEX4"             ,           0x11F0000001110ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7064         {"PCI_BAR1_INDEX5"             ,           0x11F0000001114ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7065         {"PCI_BAR1_INDEX6"             ,           0x11F0000001118ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7066         {"PCI_BAR1_INDEX7"             ,           0x11F000000111Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7067         {"PCI_BAR1_INDEX8"             ,           0x11F0000001120ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7068         {"PCI_BAR1_INDEX9"             ,           0x11F0000001124ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7069         {"PCI_BAR1_INDEX10"            ,           0x11F0000001128ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7070         {"PCI_BAR1_INDEX11"            ,           0x11F000000112Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7071         {"PCI_BAR1_INDEX12"            ,           0x11F0000001130ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7072         {"PCI_BAR1_INDEX13"            ,           0x11F0000001134ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7073         {"PCI_BAR1_INDEX14"            ,           0x11F0000001138ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7074         {"PCI_BAR1_INDEX15"            ,           0x11F000000113Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7075         {"PCI_BAR1_INDEX16"            ,           0x11F0000001140ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7076         {"PCI_BAR1_INDEX17"            ,           0x11F0000001144ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7077         {"PCI_BAR1_INDEX18"            ,           0x11F0000001148ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7078         {"PCI_BAR1_INDEX19"            ,           0x11F000000114Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7079         {"PCI_BAR1_INDEX20"            ,           0x11F0000001150ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7080         {"PCI_BAR1_INDEX21"            ,           0x11F0000001154ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7081         {"PCI_BAR1_INDEX22"            ,           0x11F0000001158ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7082         {"PCI_BAR1_INDEX23"            ,           0x11F000000115Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7083         {"PCI_BAR1_INDEX24"            ,           0x11F0000001160ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7084         {"PCI_BAR1_INDEX25"            ,           0x11F0000001164ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7085         {"PCI_BAR1_INDEX26"            ,           0x11F0000001168ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7086         {"PCI_BAR1_INDEX27"            ,           0x11F000000116Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7087         {"PCI_BAR1_INDEX28"            ,           0x11F0000001170ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7088         {"PCI_BAR1_INDEX29"            ,           0x11F0000001174ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7089         {"PCI_BAR1_INDEX30"            ,           0x11F0000001178ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7090         {"PCI_BAR1_INDEX31"            ,           0x11F000000117Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     324},
7091         {"PCI_CFG00"                   ,           0x11F0000001800ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     325},
7092         {"PCI_CFG01"                   ,           0x11F0000001804ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     326},
7093         {"PCI_CFG02"                   ,           0x11F0000001808ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     327},
7094         {"PCI_CFG03"                   ,           0x11F000000180Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     328},
7095         {"PCI_CFG04"                   ,           0x11F0000001810ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     329},
7096         {"PCI_CFG05"                   ,           0x11F0000001814ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     330},
7097         {"PCI_CFG06"                   ,           0x11F0000001818ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     331},
7098         {"PCI_CFG07"                   ,           0x11F000000181Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     332},
7099         {"PCI_CFG08"                   ,           0x11F0000001820ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     333},
7100         {"PCI_CFG09"                   ,           0x11F0000001824ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     334},
7101         {"PCI_CFG10"                   ,           0x11F0000001828ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     335},
7102         {"PCI_CFG11"                   ,           0x11F000000182Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     336},
7103         {"PCI_CFG12"                   ,           0x11F0000001830ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     337},
7104         {"PCI_CFG13"                   ,           0x11F0000001834ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     338},
7105         {"PCI_CFG15"                   ,           0x11F000000183Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     339},
7106         {"PCI_CFG16"                   ,           0x11F0000001840ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     340},
7107         {"PCI_CFG17"                   ,           0x11F0000001844ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     341},
7108         {"PCI_CFG18"                   ,           0x11F0000001848ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     342},
7109         {"PCI_CFG19"                   ,           0x11F000000184Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     343},
7110         {"PCI_CFG20"                   ,           0x11F0000001850ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     344},
7111         {"PCI_CFG21"                   ,           0x11F0000001854ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     345},
7112         {"PCI_CFG22"                   ,           0x11F0000001858ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     346},
7113         {"PCI_CFG56"                   ,           0x11F00000018E0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     347},
7114         {"PCI_CFG57"                   ,           0x11F00000018E4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     348},
7115         {"PCI_CFG58"                   ,           0x11F00000018E8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     349},
7116         {"PCI_CFG59"                   ,           0x11F00000018ECull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     350},
7117         {"PCI_CFG60"                   ,           0x11F00000018F0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     351},
7118         {"PCI_CFG61"                   ,           0x11F00000018F4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     352},
7119         {"PCI_CFG62"                   ,           0x11F00000018F8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     353},
7120         {"PCI_CFG63"                   ,           0x11F00000018FCull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     354},
7121         {"PCI_CTL_STATUS_2"            ,           0x11F000000118Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     355},
7122         {"PCI_DBELL0"                  ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCI,   32,     356},
7123         {"PCI_DBELL1"                  ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCI,   32,     356},
7124         {"PCI_DMA_CNT0"                ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     357},
7125         {"PCI_DMA_CNT1"                ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCI,   32,     357},
7126         {"PCI_DMA_INT_LEV0"            ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     358},
7127         {"PCI_DMA_INT_LEV1"            ,                      0xACull,  CVMX_CSR_DB_TYPE_PCI,   32,     358},
7128         {"PCI_DMA_TIME0"               ,                      0xB0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     359},
7129         {"PCI_DMA_TIME1"               ,                      0xB4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     359},
7130         {"PCI_INSTR_COUNT0"            ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCI,   32,     360},
7131         {"PCI_INSTR_COUNT1"            ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     360},
7132         {"PCI_INT_ENB"                 ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCI,   64,     361},
7133         {"PCI_INT_ENB2"                ,           0x11F00000011A0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     362},
7134         {"PCI_INT_SUM"                 ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCI,   64,     363},
7135         {"PCI_INT_SUM2"                ,           0x11F0000001198ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     364},
7136         {"PCI_MSI_RCV"                 ,                      0xF0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     365},
7137         {"PCI_PKT_CREDITS0"            ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCI,   32,     366},
7138         {"PCI_PKT_CREDITS1"            ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCI,   32,     366},
7139         {"PCI_PKTS_SENT0"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCI,   32,     367},
7140         {"PCI_PKTS_SENT1"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCI,   32,     367},
7141         {"PCI_PKTS_SENT_INT_LEV0"      ,                      0x48ull,  CVMX_CSR_DB_TYPE_PCI,   32,     368},
7142         {"PCI_PKTS_SENT_INT_LEV1"      ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCI,   32,     368},
7143         {"PCI_PKTS_SENT_TIME0"         ,                      0x4Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     369},
7144         {"PCI_PKTS_SENT_TIME1"         ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     369},
7145         {"PCI_READ_CMD_6"              ,           0x11F0000001180ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     370},
7146         {"PCI_READ_CMD_C"              ,           0x11F0000001184ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     371},
7147         {"PCI_READ_CMD_E"              ,           0x11F0000001188ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     372},
7148         {"PCI_READ_TIMEOUT"            ,           0x11F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     373},
7149         {"PCI_SCM_REG"                 ,           0x11F00000011A8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     374},
7150         {"PCI_TSR_REG"                 ,           0x11F00000011B0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     375},
7151         {"PCI_WIN_RD_ADDR"             ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCI,   64,     376},
7152         {"PCI_WIN_RD_DATA"             ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCI,   64,     377},
7153         {"PCI_WIN_WR_ADDR"             ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCI,   64,     378},
7154         {"PCI_WIN_WR_DATA"             ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCI,   64,     379},
7155         {"PCI_WIN_WR_MASK"             ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCI,   64,     380},
7156         {"PCM0_DMA_CFG"                ,           0x1070000010018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
7157         {"PCM1_DMA_CFG"                ,           0x1070000014018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
7158         {"PCM2_DMA_CFG"                ,           0x1070000018018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
7159         {"PCM3_DMA_CFG"                ,           0x107000001C018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
7160         {"PCM0_INT_ENA"                ,           0x1070000010020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
7161         {"PCM1_INT_ENA"                ,           0x1070000014020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
7162         {"PCM2_INT_ENA"                ,           0x1070000018020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
7163         {"PCM3_INT_ENA"                ,           0x107000001C020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
7164         {"PCM0_INT_SUM"                ,           0x1070000010028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
7165         {"PCM1_INT_SUM"                ,           0x1070000014028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
7166         {"PCM2_INT_SUM"                ,           0x1070000018028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
7167         {"PCM3_INT_SUM"                ,           0x107000001C028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
7168         {"PCM0_RXADDR"                 ,           0x1070000010068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
7169         {"PCM1_RXADDR"                 ,           0x1070000014068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
7170         {"PCM2_RXADDR"                 ,           0x1070000018068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
7171         {"PCM3_RXADDR"                 ,           0x107000001C068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
7172         {"PCM0_RXCNT"                  ,           0x1070000010060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
7173         {"PCM1_RXCNT"                  ,           0x1070000014060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
7174         {"PCM2_RXCNT"                  ,           0x1070000018060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
7175         {"PCM3_RXCNT"                  ,           0x107000001C060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
7176         {"PCM0_RXMSK0"                 ,           0x10700000100C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
7177         {"PCM1_RXMSK0"                 ,           0x10700000140C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
7178         {"PCM2_RXMSK0"                 ,           0x10700000180C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
7179         {"PCM3_RXMSK0"                 ,           0x107000001C0C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
7180         {"PCM0_RXMSK1"                 ,           0x10700000100C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
7181         {"PCM1_RXMSK1"                 ,           0x10700000140C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
7182         {"PCM2_RXMSK1"                 ,           0x10700000180C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
7183         {"PCM3_RXMSK1"                 ,           0x107000001C0C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
7184         {"PCM0_RXMSK2"                 ,           0x10700000100D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
7185         {"PCM1_RXMSK2"                 ,           0x10700000140D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
7186         {"PCM2_RXMSK2"                 ,           0x10700000180D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
7187         {"PCM3_RXMSK2"                 ,           0x107000001C0D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
7188         {"PCM0_RXMSK3"                 ,           0x10700000100D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
7189         {"PCM1_RXMSK3"                 ,           0x10700000140D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
7190         {"PCM2_RXMSK3"                 ,           0x10700000180D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
7191         {"PCM3_RXMSK3"                 ,           0x107000001C0D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
7192         {"PCM0_RXMSK4"                 ,           0x10700000100E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
7193         {"PCM1_RXMSK4"                 ,           0x10700000140E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
7194         {"PCM2_RXMSK4"                 ,           0x10700000180E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
7195         {"PCM3_RXMSK4"                 ,           0x107000001C0E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
7196         {"PCM0_RXMSK5"                 ,           0x10700000100E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
7197         {"PCM1_RXMSK5"                 ,           0x10700000140E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
7198         {"PCM2_RXMSK5"                 ,           0x10700000180E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
7199         {"PCM3_RXMSK5"                 ,           0x107000001C0E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
7200         {"PCM0_RXMSK6"                 ,           0x10700000100F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     392},
7201         {"PCM1_RXMSK6"                 ,           0x10700000140F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     392},
7202         {"PCM2_RXMSK6"                 ,           0x10700000180F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     392},
7203         {"PCM3_RXMSK6"                 ,           0x107000001C0F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     392},
7204         {"PCM0_RXMSK7"                 ,           0x10700000100F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     393},
7205         {"PCM1_RXMSK7"                 ,           0x10700000140F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     393},
7206         {"PCM2_RXMSK7"                 ,           0x10700000180F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     393},
7207         {"PCM3_RXMSK7"                 ,           0x107000001C0F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     393},
7208         {"PCM0_RXSTART"                ,           0x1070000010058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     394},
7209         {"PCM1_RXSTART"                ,           0x1070000014058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     394},
7210         {"PCM2_RXSTART"                ,           0x1070000018058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     394},
7211         {"PCM3_RXSTART"                ,           0x107000001C058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     394},
7212         {"PCM0_TDM_CFG"                ,           0x1070000010010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     395},
7213         {"PCM1_TDM_CFG"                ,           0x1070000014010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     395},
7214         {"PCM2_TDM_CFG"                ,           0x1070000018010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     395},
7215         {"PCM3_TDM_CFG"                ,           0x107000001C010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     395},
7216         {"PCM0_TDM_DBG"                ,           0x1070000010030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     396},
7217         {"PCM1_TDM_DBG"                ,           0x1070000014030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     396},
7218         {"PCM2_TDM_DBG"                ,           0x1070000018030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     396},
7219         {"PCM3_TDM_DBG"                ,           0x107000001C030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     396},
7220         {"PCM0_TXADDR"                 ,           0x1070000010050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     397},
7221         {"PCM1_TXADDR"                 ,           0x1070000014050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     397},
7222         {"PCM2_TXADDR"                 ,           0x1070000018050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     397},
7223         {"PCM3_TXADDR"                 ,           0x107000001C050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     397},
7224         {"PCM0_TXCNT"                  ,           0x1070000010048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     398},
7225         {"PCM1_TXCNT"                  ,           0x1070000014048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     398},
7226         {"PCM2_TXCNT"                  ,           0x1070000018048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     398},
7227         {"PCM3_TXCNT"                  ,           0x107000001C048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     398},
7228         {"PCM0_TXMSK0"                 ,           0x1070000010080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     399},
7229         {"PCM1_TXMSK0"                 ,           0x1070000014080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     399},
7230         {"PCM2_TXMSK0"                 ,           0x1070000018080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     399},
7231         {"PCM3_TXMSK0"                 ,           0x107000001C080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     399},
7232         {"PCM0_TXMSK1"                 ,           0x1070000010088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
7233         {"PCM1_TXMSK1"                 ,           0x1070000014088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
7234         {"PCM2_TXMSK1"                 ,           0x1070000018088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
7235         {"PCM3_TXMSK1"                 ,           0x107000001C088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
7236         {"PCM0_TXMSK2"                 ,           0x1070000010090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
7237         {"PCM1_TXMSK2"                 ,           0x1070000014090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
7238         {"PCM2_TXMSK2"                 ,           0x1070000018090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
7239         {"PCM3_TXMSK2"                 ,           0x107000001C090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
7240         {"PCM0_TXMSK3"                 ,           0x1070000010098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
7241         {"PCM1_TXMSK3"                 ,           0x1070000014098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
7242         {"PCM2_TXMSK3"                 ,           0x1070000018098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
7243         {"PCM3_TXMSK3"                 ,           0x107000001C098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
7244         {"PCM0_TXMSK4"                 ,           0x10700000100A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     403},
7245         {"PCM1_TXMSK4"                 ,           0x10700000140A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     403},
7246         {"PCM2_TXMSK4"                 ,           0x10700000180A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     403},
7247         {"PCM3_TXMSK4"                 ,           0x107000001C0A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     403},
7248         {"PCM0_TXMSK5"                 ,           0x10700000100A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     404},
7249         {"PCM1_TXMSK5"                 ,           0x10700000140A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     404},
7250         {"PCM2_TXMSK5"                 ,           0x10700000180A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     404},
7251         {"PCM3_TXMSK5"                 ,           0x107000001C0A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     404},
7252         {"PCM0_TXMSK6"                 ,           0x10700000100B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     405},
7253         {"PCM1_TXMSK6"                 ,           0x10700000140B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     405},
7254         {"PCM2_TXMSK6"                 ,           0x10700000180B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     405},
7255         {"PCM3_TXMSK6"                 ,           0x107000001C0B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     405},
7256         {"PCM0_TXMSK7"                 ,           0x10700000100B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     406},
7257         {"PCM1_TXMSK7"                 ,           0x10700000140B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     406},
7258         {"PCM2_TXMSK7"                 ,           0x10700000180B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     406},
7259         {"PCM3_TXMSK7"                 ,           0x107000001C0B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     406},
7260         {"PCM0_TXSTART"                ,           0x1070000010040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     407},
7261         {"PCM1_TXSTART"                ,           0x1070000014040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     407},
7262         {"PCM2_TXSTART"                ,           0x1070000018040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     407},
7263         {"PCM3_TXSTART"                ,           0x107000001C040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     407},
7264         {"PCM_CLK0_CFG"                ,           0x1070000010000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     408},
7265         {"PCM_CLK1_CFG"                ,           0x1070000014000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     408},
7266         {"PCM_CLK0_DBG"                ,           0x1070000010038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     409},
7267         {"PCM_CLK1_DBG"                ,           0x1070000014038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     409},
7268         {"PCM_CLK0_GEN"                ,           0x1070000010008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     410},
7269         {"PCM_CLK1_GEN"                ,           0x1070000014008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     410},
7270         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
7271         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
7272         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
7273         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
7274         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
7275         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
7276         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
7277         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
7278         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
7279         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
7280         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
7281         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
7282         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
7283         {"PIP_PRT_CFG32"               ,           0x11800A0000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
7284         {"PIP_PRT_CFG33"               ,           0x11800A0000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
7285         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
7286         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
7287         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
7288         {"PIP_PRT_TAG32"               ,           0x11800A0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
7289         {"PIP_PRT_TAG33"               ,           0x11800A0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
7290         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7291         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7292         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7293         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7294         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7295         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7296         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7297         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7298         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7299         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7300         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7301         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7302         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7303         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7304         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7305         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7306         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7307         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7308         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7309         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7310         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7311         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7312         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7313         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7314         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7315         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7316         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7317         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7318         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7319         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7320         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7321         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7322         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7323         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7324         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7325         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7326         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7327         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7328         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7329         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7330         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7331         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7332         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7333         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7334         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7335         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7336         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7337         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7338         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7339         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7340         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7341         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7342         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7343         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7344         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7345         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7346         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7347         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7348         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7349         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7350         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7351         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7352         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7353         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
7354         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
7355         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
7356         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
7357         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
7358         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
7359         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
7360         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
7361         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
7362         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
7363         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
7364         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
7365         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
7366         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
7367         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
7368         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
7369         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
7370         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
7371         {"PIP_STAT0_PRT32"             ,           0x11800A0001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
7372         {"PIP_STAT0_PRT33"             ,           0x11800A0001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
7373         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
7374         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
7375         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
7376         {"PIP_STAT1_PRT32"             ,           0x11800A0001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
7377         {"PIP_STAT1_PRT33"             ,           0x11800A0001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
7378         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
7379         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
7380         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
7381         {"PIP_STAT2_PRT32"             ,           0x11800A0001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
7382         {"PIP_STAT2_PRT33"             ,           0x11800A0001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
7383         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
7384         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
7385         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
7386         {"PIP_STAT3_PRT32"             ,           0x11800A0001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
7387         {"PIP_STAT3_PRT33"             ,           0x11800A0001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
7388         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
7389         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
7390         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
7391         {"PIP_STAT4_PRT32"             ,           0x11800A0001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
7392         {"PIP_STAT4_PRT33"             ,           0x11800A0001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
7393         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
7394         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
7395         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
7396         {"PIP_STAT5_PRT32"             ,           0x11800A0001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
7397         {"PIP_STAT5_PRT33"             ,           0x11800A0001278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
7398         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
7399         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
7400         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
7401         {"PIP_STAT6_PRT32"             ,           0x11800A0001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
7402         {"PIP_STAT6_PRT33"             ,           0x11800A0001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
7403         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
7404         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
7405         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
7406         {"PIP_STAT7_PRT32"             ,           0x11800A0001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
7407         {"PIP_STAT7_PRT33"             ,           0x11800A0001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
7408         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
7409         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
7410         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
7411         {"PIP_STAT8_PRT32"             ,           0x11800A0001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
7412         {"PIP_STAT8_PRT33"             ,           0x11800A0001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
7413         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
7414         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
7415         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
7416         {"PIP_STAT9_PRT32"             ,           0x11800A0001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
7417         {"PIP_STAT9_PRT33"             ,           0x11800A0001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
7418         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
7419         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
7420         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
7421         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
7422         {"PIP_STAT_INB_ERRS32"         ,           0x11800A0001E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
7423         {"PIP_STAT_INB_ERRS33"         ,           0x11800A0001E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
7424         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
7425         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
7426         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
7427         {"PIP_STAT_INB_OCTS32"         ,           0x11800A0001E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
7428         {"PIP_STAT_INB_OCTS33"         ,           0x11800A0001E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
7429         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
7430         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
7431         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
7432         {"PIP_STAT_INB_PKTS32"         ,           0x11800A0001E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
7433         {"PIP_STAT_INB_PKTS33"         ,           0x11800A0001E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
7434         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7435         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7436         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7437         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7438         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7439         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7440         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7441         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7442         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7443         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7444         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7445         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7446         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7447         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7448         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7449         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7450         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7451         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7452         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7453         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7454         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7455         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7456         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7457         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7458         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7459         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7460         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7461         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7462         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7463         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7464         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7465         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7466         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7467         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7468         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7469         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7470         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7471         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7472         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7473         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7474         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7475         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7476         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7477         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7478         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7479         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7480         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7481         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7482         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7483         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7484         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7485         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7486         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7487         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7488         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7489         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7490         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7491         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7492         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7493         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7494         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7495         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7496         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7497         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
7498         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
7499         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
7500         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
7501         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
7502         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
7503         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
7504         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
7505         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     447},
7506         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
7507         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
7508         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
7509         {"PKO_MEM_DEBUG14"             ,           0x1180050001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
7510         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
7511         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
7512         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
7513         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
7514         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
7515         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
7516         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
7517         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
7518         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
7519         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
7520         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
7521         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
7522         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
7523         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
7524         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
7525         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
7526         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     468},
7527         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
7528         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
7529         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     471},
7530         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     472},
7531         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     473},
7532         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     474},
7533         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
7534         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
7535         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
7536         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
7537         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
7538         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
7539         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
7540         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
7541         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     476},
7542         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     477},
7543         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     478},
7544         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
7545         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
7546         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
7547         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
7548         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
7549         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
7550         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
7551         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
7552         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
7553         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
7554         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
7555         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
7556         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
7557         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
7558         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
7559         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
7560         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
7561         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
7562         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     482},
7563         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
7564         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
7565         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
7566         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
7567         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
7568         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
7569         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
7570         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
7571         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
7572         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
7573         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7574         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7575         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7576         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7577         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7578         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7579         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7580         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7581         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7582         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7583         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7584         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7585         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7586         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7587         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7588         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
7589         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
7590         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7591         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7592         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7593         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7594         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7595         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7596         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7597         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7598         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7599         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7600         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7601         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7602         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7603         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7604         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7605         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
7606         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7607         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7608         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7609         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7610         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7611         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7612         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7613         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7614         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7615         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7616         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7617         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7618         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7619         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7620         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7621         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
7622         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     490},
7623         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     491},
7624         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     492},
7625         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     493},
7626         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     494},
7627         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     495},
7628         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     496},
7629         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     497},
7630         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     498},
7631         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     499},
7632         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     500},
7633         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     501},
7634         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     502},
7635         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     503},
7636         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     504},
7637         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     505},
7638         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     506},
7639         {"TRA_BIST_STATUS"             ,           0x11800A8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     507},
7640         {"TRA_CTL"                     ,           0x11800A8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     508},
7641         {"TRA_CYCLES_SINCE"            ,           0x11800A8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     509},
7642         {"TRA_FILT_ADR_ADR"            ,           0x11800A8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     510},
7643         {"TRA_FILT_ADR_MSK"            ,           0x11800A8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     511},
7644         {"TRA_FILT_CMD"                ,           0x11800A8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     512},
7645         {"TRA_FILT_DID"                ,           0x11800A8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     513},
7646         {"TRA_FILT_SID"                ,           0x11800A8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     514},
7647         {"TRA_INT_STATUS"              ,           0x11800A8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     515},
7648         {"TRA_READ_DAT"                ,           0x11800A8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     516},
7649         {"TRA_TRIG0_ADR_ADR"           ,           0x11800A8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     517},
7650         {"TRA_TRIG0_ADR_MSK"           ,           0x11800A80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     518},
7651         {"TRA_TRIG0_CMD"               ,           0x11800A8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     519},
7652         {"TRA_TRIG0_DID"               ,           0x11800A8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     520},
7653         {"TRA_TRIG0_SID"               ,           0x11800A8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
7654         {"TRA_TRIG1_ADR_ADR"           ,           0x11800A80000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     522},
7655         {"TRA_TRIG1_ADR_MSK"           ,           0x11800A80000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     523},
7656         {"TRA_TRIG1_CMD"               ,           0x11800A80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     524},
7657         {"TRA_TRIG1_DID"               ,           0x11800A80000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     525},
7658         {"TRA_TRIG1_SID"               ,           0x11800A80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     526},
7659         {"USBC0_DAINT"                 ,           0x16F0010000818ull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
7660         {"USBC0_DAINTMSK"              ,           0x16F001000081Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     528},
7661         {"USBC0_DCFG"                  ,           0x16F0010000800ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
7662         {"USBC0_DCTL"                  ,           0x16F0010000804ull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
7663         {"USBC0_DIEPCTL000"            ,           0x16F0010000900ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
7664         {"USBC0_DIEPCTL001"            ,           0x16F0010000920ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
7665         {"USBC0_DIEPCTL002"            ,           0x16F0010000940ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
7666         {"USBC0_DIEPCTL003"            ,           0x16F0010000960ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
7667         {"USBC0_DIEPCTL004"            ,           0x16F0010000980ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
7668         {"USBC0_DIEPINT000"            ,           0x16F0010000908ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
7669         {"USBC0_DIEPINT001"            ,           0x16F0010000928ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
7670         {"USBC0_DIEPINT002"            ,           0x16F0010000948ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
7671         {"USBC0_DIEPINT003"            ,           0x16F0010000968ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
7672         {"USBC0_DIEPINT004"            ,           0x16F0010000988ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
7673         {"USBC0_DIEPMSK"               ,           0x16F0010000810ull,  CVMX_CSR_DB_TYPE_NCB,   32,     533},
7674         {"USBC0_DIEPTSIZ000"           ,           0x16F0010000910ull,  CVMX_CSR_DB_TYPE_NCB,   32,     534},
7675         {"USBC0_DIEPTSIZ001"           ,           0x16F0010000930ull,  CVMX_CSR_DB_TYPE_NCB,   32,     534},
7676         {"USBC0_DIEPTSIZ002"           ,           0x16F0010000950ull,  CVMX_CSR_DB_TYPE_NCB,   32,     534},
7677         {"USBC0_DIEPTSIZ003"           ,           0x16F0010000970ull,  CVMX_CSR_DB_TYPE_NCB,   32,     534},
7678         {"USBC0_DIEPTSIZ004"           ,           0x16F0010000990ull,  CVMX_CSR_DB_TYPE_NCB,   32,     534},
7679         {"USBC0_DOEPCTL000"            ,           0x16F0010000B00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     535},
7680         {"USBC0_DOEPCTL001"            ,           0x16F0010000B20ull,  CVMX_CSR_DB_TYPE_NCB,   32,     535},
7681         {"USBC0_DOEPCTL002"            ,           0x16F0010000B40ull,  CVMX_CSR_DB_TYPE_NCB,   32,     535},
7682         {"USBC0_DOEPCTL003"            ,           0x16F0010000B60ull,  CVMX_CSR_DB_TYPE_NCB,   32,     535},
7683         {"USBC0_DOEPCTL004"            ,           0x16F0010000B80ull,  CVMX_CSR_DB_TYPE_NCB,   32,     535},
7684         {"USBC0_DOEPINT000"            ,           0x16F0010000B08ull,  CVMX_CSR_DB_TYPE_NCB,   32,     536},
7685         {"USBC0_DOEPINT001"            ,           0x16F0010000B28ull,  CVMX_CSR_DB_TYPE_NCB,   32,     536},
7686         {"USBC0_DOEPINT002"            ,           0x16F0010000B48ull,  CVMX_CSR_DB_TYPE_NCB,   32,     536},
7687         {"USBC0_DOEPINT003"            ,           0x16F0010000B68ull,  CVMX_CSR_DB_TYPE_NCB,   32,     536},
7688         {"USBC0_DOEPINT004"            ,           0x16F0010000B88ull,  CVMX_CSR_DB_TYPE_NCB,   32,     536},
7689         {"USBC0_DOEPMSK"               ,           0x16F0010000814ull,  CVMX_CSR_DB_TYPE_NCB,   32,     537},
7690         {"USBC0_DOEPTSIZ000"           ,           0x16F0010000B10ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
7691         {"USBC0_DOEPTSIZ001"           ,           0x16F0010000B30ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
7692         {"USBC0_DOEPTSIZ002"           ,           0x16F0010000B50ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
7693         {"USBC0_DOEPTSIZ003"           ,           0x16F0010000B70ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
7694         {"USBC0_DOEPTSIZ004"           ,           0x16F0010000B90ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
7695         {"USBC0_DPTXFSIZ001"           ,           0x16F0010000104ull,  CVMX_CSR_DB_TYPE_NCB,   32,     539},
7696         {"USBC0_DPTXFSIZ002"           ,           0x16F0010000108ull,  CVMX_CSR_DB_TYPE_NCB,   32,     539},
7697         {"USBC0_DPTXFSIZ003"           ,           0x16F001000010Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     539},
7698         {"USBC0_DPTXFSIZ004"           ,           0x16F0010000110ull,  CVMX_CSR_DB_TYPE_NCB,   32,     539},
7699         {"USBC0_DSTS"                  ,           0x16F0010000808ull,  CVMX_CSR_DB_TYPE_NCB,   32,     540},
7700         {"USBC0_DTKNQR1"               ,           0x16F0010000820ull,  CVMX_CSR_DB_TYPE_NCB,   32,     541},
7701         {"USBC0_DTKNQR2"               ,           0x16F0010000824ull,  CVMX_CSR_DB_TYPE_NCB,   32,     542},
7702         {"USBC0_DTKNQR3"               ,           0x16F0010000830ull,  CVMX_CSR_DB_TYPE_NCB,   32,     543},
7703         {"USBC0_DTKNQR4"               ,           0x16F0010000834ull,  CVMX_CSR_DB_TYPE_NCB,   32,     544},
7704         {"USBC0_GAHBCFG"               ,           0x16F0010000008ull,  CVMX_CSR_DB_TYPE_NCB,   32,     545},
7705         {"USBC0_GHWCFG1"               ,           0x16F0010000044ull,  CVMX_CSR_DB_TYPE_NCB,   32,     546},
7706         {"USBC0_GHWCFG2"               ,           0x16F0010000048ull,  CVMX_CSR_DB_TYPE_NCB,   32,     547},
7707         {"USBC0_GHWCFG3"               ,           0x16F001000004Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     548},
7708         {"USBC0_GHWCFG4"               ,           0x16F0010000050ull,  CVMX_CSR_DB_TYPE_NCB,   32,     549},
7709         {"USBC0_GINTMSK"               ,           0x16F0010000018ull,  CVMX_CSR_DB_TYPE_NCB,   32,     550},
7710         {"USBC0_GINTSTS"               ,           0x16F0010000014ull,  CVMX_CSR_DB_TYPE_NCB,   32,     551},
7711         {"USBC0_GNPTXFSIZ"             ,           0x16F0010000028ull,  CVMX_CSR_DB_TYPE_NCB,   32,     552},
7712         {"USBC0_GNPTXSTS"              ,           0x16F001000002Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     553},
7713         {"USBC0_GOTGCTL"               ,           0x16F0010000000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     554},
7714         {"USBC0_GOTGINT"               ,           0x16F0010000004ull,  CVMX_CSR_DB_TYPE_NCB,   32,     555},
7715         {"USBC0_GRSTCTL"               ,           0x16F0010000010ull,  CVMX_CSR_DB_TYPE_NCB,   32,     556},
7716         {"USBC0_GRXFSIZ"               ,           0x16F0010000024ull,  CVMX_CSR_DB_TYPE_NCB,   32,     557},
7717         {"USBC0_GRXSTSPD"              ,           0x16F0010040020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     558},
7718         {"USBC0_GRXSTSPH"              ,           0x16F0010000020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     559},
7719         {"USBC0_GRXSTSRD"              ,           0x16F001004001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     560},
7720         {"USBC0_GRXSTSRH"              ,           0x16F001000001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     561},
7721         {"USBC0_GSNPSID"               ,           0x16F0010000040ull,  CVMX_CSR_DB_TYPE_NCB,   32,     562},
7722         {"USBC0_GUSBCFG"               ,           0x16F001000000Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     563},
7723         {"USBC0_HAINT"                 ,           0x16F0010000414ull,  CVMX_CSR_DB_TYPE_NCB,   32,     564},
7724         {"USBC0_HAINTMSK"              ,           0x16F0010000418ull,  CVMX_CSR_DB_TYPE_NCB,   32,     565},
7725         {"USBC0_HCCHAR000"             ,           0x16F0010000500ull,  CVMX_CSR_DB_TYPE_NCB,   32,     566},
7726         {"USBC0_HCCHAR001"             ,           0x16F0010000520ull,  CVMX_CSR_DB_TYPE_NCB,   32,     566},
7727         {"USBC0_HCCHAR002"             ,           0x16F0010000540ull,  CVMX_CSR_DB_TYPE_NCB,   32,     566},
7728         {"USBC0_HCCHAR003"             ,           0x16F0010000560ull,  CVMX_CSR_DB_TYPE_NCB,   32,     566},
7729         {"USBC0_HCCHAR004"             ,           0x16F0010000580ull,  CVMX_CSR_DB_TYPE_NCB,   32,     566},
7730         {"USBC0_HCCHAR005"             ,           0x16F00100005A0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     566},
7731         {"USBC0_HCCHAR006"             ,           0x16F00100005C0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     566},
7732         {"USBC0_HCCHAR007"             ,           0x16F00100005E0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     566},
7733         {"USBC0_HCFG"                  ,           0x16F0010000400ull,  CVMX_CSR_DB_TYPE_NCB,   32,     567},
7734         {"USBC0_HCINT000"              ,           0x16F0010000508ull,  CVMX_CSR_DB_TYPE_NCB,   32,     568},
7735         {"USBC0_HCINT001"              ,           0x16F0010000528ull,  CVMX_CSR_DB_TYPE_NCB,   32,     568},
7736         {"USBC0_HCINT002"              ,           0x16F0010000548ull,  CVMX_CSR_DB_TYPE_NCB,   32,     568},
7737         {"USBC0_HCINT003"              ,           0x16F0010000568ull,  CVMX_CSR_DB_TYPE_NCB,   32,     568},
7738         {"USBC0_HCINT004"              ,           0x16F0010000588ull,  CVMX_CSR_DB_TYPE_NCB,   32,     568},
7739         {"USBC0_HCINT005"              ,           0x16F00100005A8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     568},
7740         {"USBC0_HCINT006"              ,           0x16F00100005C8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     568},
7741         {"USBC0_HCINT007"              ,           0x16F00100005E8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     568},
7742         {"USBC0_HCINTMSK000"           ,           0x16F001000050Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     569},
7743         {"USBC0_HCINTMSK001"           ,           0x16F001000052Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     569},
7744         {"USBC0_HCINTMSK002"           ,           0x16F001000054Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     569},
7745         {"USBC0_HCINTMSK003"           ,           0x16F001000056Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     569},
7746         {"USBC0_HCINTMSK004"           ,           0x16F001000058Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     569},
7747         {"USBC0_HCINTMSK005"           ,           0x16F00100005ACull,  CVMX_CSR_DB_TYPE_NCB,   32,     569},
7748         {"USBC0_HCINTMSK006"           ,           0x16F00100005CCull,  CVMX_CSR_DB_TYPE_NCB,   32,     569},
7749         {"USBC0_HCINTMSK007"           ,           0x16F00100005ECull,  CVMX_CSR_DB_TYPE_NCB,   32,     569},
7750         {"USBC0_HCSPLT000"             ,           0x16F0010000504ull,  CVMX_CSR_DB_TYPE_NCB,   32,     570},
7751         {"USBC0_HCSPLT001"             ,           0x16F0010000524ull,  CVMX_CSR_DB_TYPE_NCB,   32,     570},
7752         {"USBC0_HCSPLT002"             ,           0x16F0010000544ull,  CVMX_CSR_DB_TYPE_NCB,   32,     570},
7753         {"USBC0_HCSPLT003"             ,           0x16F0010000564ull,  CVMX_CSR_DB_TYPE_NCB,   32,     570},
7754         {"USBC0_HCSPLT004"             ,           0x16F0010000584ull,  CVMX_CSR_DB_TYPE_NCB,   32,     570},
7755         {"USBC0_HCSPLT005"             ,           0x16F00100005A4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     570},
7756         {"USBC0_HCSPLT006"             ,           0x16F00100005C4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     570},
7757         {"USBC0_HCSPLT007"             ,           0x16F00100005E4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     570},
7758         {"USBC0_HCTSIZ000"             ,           0x16F0010000510ull,  CVMX_CSR_DB_TYPE_NCB,   32,     571},
7759         {"USBC0_HCTSIZ001"             ,           0x16F0010000530ull,  CVMX_CSR_DB_TYPE_NCB,   32,     571},
7760         {"USBC0_HCTSIZ002"             ,           0x16F0010000550ull,  CVMX_CSR_DB_TYPE_NCB,   32,     571},
7761         {"USBC0_HCTSIZ003"             ,           0x16F0010000570ull,  CVMX_CSR_DB_TYPE_NCB,   32,     571},
7762         {"USBC0_HCTSIZ004"             ,           0x16F0010000590ull,  CVMX_CSR_DB_TYPE_NCB,   32,     571},
7763         {"USBC0_HCTSIZ005"             ,           0x16F00100005B0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     571},
7764         {"USBC0_HCTSIZ006"             ,           0x16F00100005D0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     571},
7765         {"USBC0_HCTSIZ007"             ,           0x16F00100005F0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     571},
7766         {"USBC0_HFIR"                  ,           0x16F0010000404ull,  CVMX_CSR_DB_TYPE_NCB,   32,     572},
7767         {"USBC0_HFNUM"                 ,           0x16F0010000408ull,  CVMX_CSR_DB_TYPE_NCB,   32,     573},
7768         {"USBC0_HPRT"                  ,           0x16F0010000440ull,  CVMX_CSR_DB_TYPE_NCB,   32,     574},
7769         {"USBC0_HPTXFSIZ"              ,           0x16F0010000100ull,  CVMX_CSR_DB_TYPE_NCB,   32,     575},
7770         {"USBC0_HPTXSTS"               ,           0x16F0010000410ull,  CVMX_CSR_DB_TYPE_NCB,   32,     576},
7771         {"USBC0_NPTXDFIFO000"          ,           0x16F0010001000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     577},
7772         {"USBC0_NPTXDFIFO001"          ,           0x16F0010002000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     577},
7773         {"USBC0_NPTXDFIFO002"          ,           0x16F0010003000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     577},
7774         {"USBC0_NPTXDFIFO003"          ,           0x16F0010004000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     577},
7775         {"USBC0_NPTXDFIFO004"          ,           0x16F0010005000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     577},
7776         {"USBC0_NPTXDFIFO005"          ,           0x16F0010006000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     577},
7777         {"USBC0_NPTXDFIFO006"          ,           0x16F0010007000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     577},
7778         {"USBC0_NPTXDFIFO007"          ,           0x16F0010008000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     577},
7779         {"USBC0_PCGCCTL"               ,           0x16F0010000E00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     578},
7780         {"USBN0_BIST_STATUS"           ,           0x11800680007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     579},
7781         {"USBN0_CLK_CTL"               ,           0x1180068000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     580},
7782         {"USBN0_CTL_STATUS"            ,           0x16F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     581},
7783         {"USBN0_DMA0_INB_CHN0"         ,           0x16F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     582},
7784         {"USBN0_DMA0_INB_CHN1"         ,           0x16F0000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     583},
7785         {"USBN0_DMA0_INB_CHN2"         ,           0x16F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     584},
7786         {"USBN0_DMA0_INB_CHN3"         ,           0x16F0000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     585},
7787         {"USBN0_DMA0_INB_CHN4"         ,           0x16F0000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     586},
7788         {"USBN0_DMA0_INB_CHN5"         ,           0x16F0000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     587},
7789         {"USBN0_DMA0_INB_CHN6"         ,           0x16F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     588},
7790         {"USBN0_DMA0_INB_CHN7"         ,           0x16F0000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     589},
7791         {"USBN0_DMA0_OUTB_CHN0"        ,           0x16F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     590},
7792         {"USBN0_DMA0_OUTB_CHN1"        ,           0x16F0000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     591},
7793         {"USBN0_DMA0_OUTB_CHN2"        ,           0x16F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     592},
7794         {"USBN0_DMA0_OUTB_CHN3"        ,           0x16F0000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     593},
7795         {"USBN0_DMA0_OUTB_CHN4"        ,           0x16F0000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     594},
7796         {"USBN0_DMA0_OUTB_CHN5"        ,           0x16F0000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     595},
7797         {"USBN0_DMA0_OUTB_CHN6"        ,           0x16F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     596},
7798         {"USBN0_DMA0_OUTB_CHN7"        ,           0x16F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     597},
7799         {"USBN0_DMA_TEST"              ,           0x16F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     598},
7800         {"USBN0_INT_ENB"               ,           0x1180068000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     599},
7801         {"USBN0_INT_SUM"               ,           0x1180068000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     600},
7802         {"USBN0_USBP_CTL_STATUS"       ,           0x1180068000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     601},
7803         {"ZIP_CMD_BIST_RESULT"         ,           0x1180038000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     602},
7804         {"ZIP_CMD_BUF"                 ,           0x1180038000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     603},
7805         {"ZIP_CMD_CTL"                 ,           0x1180038000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     604},
7806         {"ZIP_CONSTANTS"               ,           0x11800380000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     605},
7807         {"ZIP_DEBUG0"                  ,           0x1180038000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     606},
7808         {"ZIP_ERROR"                   ,           0x1180038000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     607},
7809         {"ZIP_INT_MASK"                ,           0x1180038000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     608},
7810         {NULL,0,0,0,0}
7811 };
7812 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn31xx[] = {
7813         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
7814         {"SETTING"                     ,        0,      5,      0,      "R/W",  0,      0,      0ull,   0ull},
7815         {"RESERVED_5_63"               ,        5,      59,     0,      "RAZ",  1,      1,      0,      0},
7816         {"SETTING"                     ,        0,      5,      1,      "R/W",  0,      0,      0ull,   0ull},
7817         {"RESERVED_5_63"               ,        5,      59,     1,      "RAZ",  1,      1,      0,      0},
7818         {"OVRFLW"                      ,        0,      3,      2,      "R/W",  0,      0,      0ull,   1ull},
7819         {"RESERVED_3_3"                ,        3,      1,      2,      "RAZ",  1,      1,      0,      0},
7820         {"TXPOP"                       ,        4,      3,      2,      "R/W",  0,      0,      0ull,   1ull},
7821         {"RESERVED_7_7"                ,        7,      1,      2,      "RAZ",  1,      1,      0,      0},
7822         {"TXPSH"                       ,        8,      3,      2,      "R/W",  0,      0,      0ull,   1ull},
7823         {"RESERVED_11_63"              ,        11,     53,     2,      "RAZ",  1,      1,      0,      0},
7824         {"OVRFLW"                      ,        0,      3,      3,      "R/W1C",        0,      0,      0ull,   0ull},
7825         {"RESERVED_3_3"                ,        3,      1,      3,      "RAZ",  1,      1,      0,      0},
7826         {"TXPOP"                       ,        4,      3,      3,      "R/W1C",        0,      0,      0ull,   0ull},
7827         {"RESERVED_7_7"                ,        7,      1,      3,      "RAZ",  1,      1,      0,      0},
7828         {"TXPSH"                       ,        8,      3,      3,      "R/W1C",        0,      0,      0ull,   0ull},
7829         {"RESERVED_11_63"              ,        11,     53,     3,      "RAZ",  1,      1,      0,      0},
7830         {"INT_LOOP"                    ,        0,      3,      4,      "R/W",  0,      0,      0ull,   0ull},
7831         {"RESERVED_3_3"                ,        3,      1,      4,      "RAZ",  1,      1,      0,      0},
7832         {"EXT_LOOP"                    ,        4,      3,      4,      "R/W",  0,      0,      0ull,   0ull},
7833         {"RESERVED_7_63"               ,        7,      57,     4,      "RAZ",  1,      1,      0,      0},
7834         {"SETTING"                     ,        0,      5,      5,      "R/W",  0,      0,      24ull,  24ull},
7835         {"RESERVED_5_63"               ,        5,      59,     5,      "RAZ",  1,      1,      0,      0},
7836         {"PRT_EN"                      ,        0,      3,      6,      "R/W",  0,      0,      0ull,   1ull},
7837         {"RESERVED_3_63"               ,        3,      61,     6,      "RAZ",  1,      1,      0,      0},
7838         {"SETTING"                     ,        0,      5,      7,      "R/W",  0,      0,      24ull,  24ull},
7839         {"RESERVED_5_63"               ,        5,      59,     7,      "RAZ",  1,      1,      0,      0},
7840         {"NCTL"                        ,        0,      4,      8,      "R/W",  0,      0,      8ull,   8ull},
7841         {"PCTL"                        ,        4,      4,      8,      "R/W",  0,      0,      8ull,   8ull},
7842         {"BYPASS"                      ,        8,      1,      8,      "R/W",  0,      0,      0ull,   0ull},
7843         {"RESERVED_9_63"               ,        9,      55,     8,      "RAZ",  1,      1,      0,      0},
7844         {"MARK"                        ,        0,      3,      9,      "R/W",  0,      0,      0ull,   0ull},
7845         {"RESERVED_3_63"               ,        3,      61,     9,      "RAZ",  1,      1,      0,      0},
7846         {"PRT_EN"                      ,        0,      3,      10,     "R/W",  0,      0,      0ull,   1ull},
7847         {"RESERVED_3_63"               ,        3,      61,     10,     "RAZ",  1,      1,      0,      0},
7848         {"BIST"                        ,        0,      4,      11,     "RO",   0,      0,      0ull,   0ull},
7849         {"RESERVED_4_63"               ,        4,      60,     11,     "RAZ",  1,      1,      0,      0},
7850         {"DINT"                        ,        0,      2,      12,     "WO",   0,      0,      0ull,   0ull},
7851         {"RESERVED_2_63"               ,        2,      62,     12,     "RAZ",  1,      1,      0,      0},
7852         {"FUSE"                        ,        0,      2,      13,     "RO",   1,      1,      0,      0},
7853         {"RESERVED_2_63"               ,        2,      62,     13,     "RAZ",  1,      1,      0,      0},
7854         {"GSTOP"                       ,        0,      1,      14,     "R/W",  0,      0,      0ull,   0ull},
7855         {"RESERVED_1_63"               ,        1,      63,     14,     "RAZ",  1,      1,      0,      0},
7856         {"WORKQ"                       ,        0,      16,     15,     "R/W",  0,      0,      0ull,   0ull},
7857         {"GPIO"                        ,        16,     16,     15,     "R/W",  0,      0,      0ull,   0ull},
7858         {"MBOX"                        ,        32,     2,      15,     "R/W",  0,      0,      0ull,   0ull},
7859         {"UART"                        ,        34,     2,      15,     "R/W",  0,      0,      0ull,   0ull},
7860         {"PCI_INT"                     ,        36,     4,      15,     "R/W",  0,      0,      0ull,   0ull},
7861         {"PCI_MSI"                     ,        40,     4,      15,     "R/W",  0,      0,      0ull,   0ull},
7862         {"RESERVED_44_44"              ,        44,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7863         {"TWSI"                        ,        45,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7864         {"RML"                         ,        46,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7865         {"TRACE"                       ,        47,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7866         {"GMX_DRP"                     ,        48,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7867         {"RESERVED_49_49"              ,        49,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7868         {"IPD_DRP"                     ,        50,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7869         {"RESERVED_51_51"              ,        51,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7870         {"TIMER"                       ,        52,     4,      15,     "R/W",  0,      0,      0ull,   0ull},
7871         {"USB"                         ,        56,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7872         {"PCM"                         ,        57,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7873         {"MPI"                         ,        58,     1,      15,     "R/W",  0,      0,      0ull,   0ull},
7874         {"RESERVED_59_63"              ,        59,     5,      15,     "RAZ",  1,      1,      0,      0},
7875         {"WDOG"                        ,        0,      2,      16,     "R/W",  0,      0,      0ull,   0ull},
7876         {"RESERVED_2_63"               ,        2,      62,     16,     "RAZ",  1,      1,      0,      0},
7877         {"WORKQ"                       ,        0,      16,     17,     "RO",   0,      0,      0ull,   0ull},
7878         {"GPIO"                        ,        16,     16,     17,     "RO",   0,      0,      0ull,   0ull},
7879         {"MBOX"                        ,        32,     2,      17,     "RO",   0,      0,      0ull,   0ull},
7880         {"UART"                        ,        34,     2,      17,     "RO",   0,      0,      0ull,   0ull},
7881         {"PCI_INT"                     ,        36,     4,      17,     "RO",   0,      0,      0ull,   0ull},
7882         {"PCI_MSI"                     ,        40,     4,      17,     "RO",   0,      0,      0ull,   0ull},
7883         {"WDOG_SUM"                    ,        44,     1,      17,     "RO",   0,      0,      0ull,   0ull},
7884         {"TWSI"                        ,        45,     1,      17,     "RO",   0,      0,      0ull,   0ull},
7885         {"RML"                         ,        46,     1,      17,     "RO",   0,      0,      0ull,   0ull},
7886         {"TRACE"                       ,        47,     1,      17,     "RO",   0,      0,      0ull,   0ull},
7887         {"GMX_DRP"                     ,        48,     1,      17,     "R/W1C",        0,      0,      0ull,   0ull},
7888         {"RESERVED_49_49"              ,        49,     1,      17,     "RAZ",  1,      1,      0,      0},
7889         {"IPD_DRP"                     ,        50,     1,      17,     "R/W1C",        0,      0,      0ull,   0ull},
7890         {"RESERVED_51_51"              ,        51,     1,      17,     "RAZ",  1,      1,      0,      0},
7891         {"TIMER"                       ,        52,     4,      17,     "R/W1C",        0,      0,      0ull,   0ull},
7892         {"USB"                         ,        56,     1,      17,     "RO",   0,      0,      0ull,   0ull},
7893         {"PCM"                         ,        57,     1,      17,     "RO",   0,      0,      0ull,   0ull},
7894         {"MPI"                         ,        58,     1,      17,     "R/W1C",        0,      0,      0ull,   0ull},
7895         {"RESERVED_59_63"              ,        59,     5,      17,     "RAZ",  1,      1,      0,      0},
7896         {"WDOG"                        ,        0,      2,      18,     "RO",   0,      0,      0ull,   0ull},
7897         {"RESERVED_2_63"               ,        2,      62,     18,     "RAZ",  1,      1,      0,      0},
7898         {"BITS"                        ,        0,      32,     19,     "R/W1C",        0,      0,      0ull,   0ull},
7899         {"RESERVED_32_63"              ,        32,     32,     19,     "RAZ",  1,      1,      0,      0},
7900         {"BITS"                        ,        0,      32,     20,     "R/W1", 0,      0,      0ull,   0ull},
7901         {"RESERVED_32_63"              ,        32,     32,     20,     "RAZ",  1,      1,      0,      0},
7902         {"NMI"                         ,        0,      2,      21,     "WO",   0,      0,      0ull,   0ull},
7903         {"RESERVED_2_63"               ,        2,      62,     21,     "RAZ",  1,      1,      0,      0},
7904         {"INTR"                        ,        0,      2,      22,     "R/W",  0,      0,      0ull,   0ull},
7905         {"RESERVED_2_63"               ,        2,      62,     22,     "RAZ",  1,      1,      0,      0},
7906         {"PPDBG"                       ,        0,      2,      23,     "RO",   0,      0,      0ull,   0ull},
7907         {"RESERVED_2_63"               ,        2,      62,     23,     "RAZ",  1,      1,      0,      0},
7908         {"POKE"                        ,        0,      64,     24,     "RAZ",  1,      1,      0,      0},
7909         {"RST0"                        ,        0,      1,      25,     "R/W",  1,      1,      0,      0},
7910         {"RST"                         ,        1,      1,      25,     "R/W",  0,      0,      1ull,   0ull},
7911         {"RESERVED_2_63"               ,        2,      62,     25,     "RAZ",  1,      1,      0,      0},
7912         {"SOFT_BIST"                   ,        0,      1,      26,     "R/W",  0,      0,      0ull,   0ull},
7913         {"RESERVED_1_63"               ,        1,      63,     26,     "RAZ",  1,      1,      0,      0},
7914         {"SOFT_PRST"                   ,        0,      1,      27,     "R/W",  0,      0,      1ull,   0ull},
7915         {"NPI"                         ,        1,      1,      27,     "R/W",  0,      0,      0ull,   0ull},
7916         {"HOST64"                      ,        2,      1,      27,     "RO",   0,      0,      0ull,   0ull},
7917         {"RESERVED_3_63"               ,        3,      61,     27,     "RAZ",  1,      1,      0,      0},
7918         {"SOFT_RST"                    ,        0,      1,      28,     "WO",   0,      0,      0ull,   0ull},
7919         {"RESERVED_1_63"               ,        1,      63,     28,     "RAZ",  1,      1,      0,      0},
7920         {"LEN"                         ,        0,      36,     29,     "R/W",  0,      0,      0ull,   0ull},
7921         {"ONE_SHOT"                    ,        36,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
7922         {"RESERVED_37_63"              ,        37,     27,     29,     "RAZ",  1,      1,      0,      0},
7923         {"MODE"                        ,        0,      2,      30,     "R/W",  0,      0,      0ull,   0ull},
7924         {"STATE"                       ,        2,      2,      30,     "RO",   0,      0,      0ull,   0ull},
7925         {"LEN"                         ,        4,      16,     30,     "R/W",  0,      0,      0ull,   0ull},
7926         {"CNT"                         ,        20,     24,     30,     "RO",   0,      0,      0ull,   0ull},
7927         {"DSTOP"                       ,        44,     1,      30,     "R/W",  0,      0,      0ull,   0ull},
7928         {"GSTOPEN"                     ,        45,     1,      30,     "R/W",  0,      0,      0ull,   0ull},
7929         {"RESERVED_46_63"              ,        46,     18,     30,     "RAZ",  1,      1,      0,      0},
7930         {"DATA"                        ,        0,      17,     31,     "RO",   0,      1,      0ull,   0},
7931         {"DSEL_EXT"                    ,        17,     1,      31,     "R/W",  0,      0,      1ull,   0ull},
7932         {"C_MUL"                       ,        18,     5,      31,     "RO",   1,      1,      0,      0},
7933         {"RESERVED_23_27"              ,        23,     5,      31,     "RAZ",  1,      1,      0,      0},
7934         {"PLL_MUL"                     ,        28,     3,      31,     "RO",   1,      1,      0,      0},
7935         {"RESERVED_31_63"              ,        31,     33,     31,     "RAZ",  1,      1,      0,      0},
7936         {"PDF"                         ,        0,      16,     32,     "RO",   0,      0,      0ull,   0ull},
7937         {"RDF"                         ,        16,     16,     32,     "RO",   0,      0,      0ull,   0ull},
7938         {"RESERVED_32_63"              ,        32,     32,     32,     "RAZ",  0,      0,      0ull,   0ull},
7939         {"RESERVED_0_17"               ,        0,      18,     33,     "RAZ",  0,      0,      0ull,   0ull},
7940         {"CRF"                         ,        18,     1,      33,     "RO",   0,      0,      0ull,   0ull},
7941         {"DRF"                         ,        19,     1,      33,     "RO",   0,      0,      0ull,   0ull},
7942         {"GFU"                         ,        20,     1,      33,     "RO",   0,      0,      0ull,   0ull},
7943         {"IFU"                         ,        21,     1,      33,     "RO",   0,      0,      0ull,   0ull},
7944         {"CRQ"                         ,        22,     1,      33,     "RO",   0,      0,      0ull,   0ull},
7945         {"RESERVED_23_63"              ,        23,     41,     33,     "RAZ",  0,      0,      0ull,   0ull},
7946         {"DBELL"                       ,        0,      20,     34,     "R/W",  0,      1,      0ull,   0},
7947         {"RESERVED_20_63"              ,        20,     44,     34,     "RAZ",  1,      1,      0,      0},
7948         {"NUM_COLS"                    ,        0,      2,      35,     "R/W",  0,      0,      1ull,   1ull},
7949         {"NUM_COLROWS"                 ,        2,      3,      35,     "R/W",  0,      0,      1ull,   1ull},
7950         {"RNK_LO"                      ,        5,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
7951         {"NUM_RNKS"                    ,        6,      2,      35,     "R/W",  0,      0,      0ull,   0ull},
7952         {"RDIMM_ENA"                   ,        8,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
7953         {"RESERVED_9_63"               ,        9,      55,     35,     "RAZ",  1,      1,      0,      0},
7954         {"BUS_CNT"                     ,        0,      47,     36,     "RO",   0,      0,      0ull,   0ull},
7955         {"RESERVED_47_63"              ,        47,     17,     36,     "RAZ",  1,      1,      0,      0},
7956         {"PRTENA"                      ,        0,      1,      37,     "R/W",  0,      0,      0ull,   1ull},
7957         {"INIT"                        ,        1,      1,      37,     "R/W",  0,      0,      0ull,   0ull},
7958         {"FPRCH"                       ,        2,      1,      37,     "R/W",  0,      0,      0ull,   0ull},
7959         {"BPRCH"                       ,        3,      1,      37,     "R/W",  0,      0,      0ull,   0ull},
7960         {"SIL_LAT"                     ,        4,      2,      37,     "R/W",  0,      0,      1ull,   1ull},
7961         {"SILO_HC"                     ,        6,      1,      37,     "R/W",  0,      0,      0ull,   0ull},
7962         {"SILO_QC"                     ,        7,      1,      37,     "R/W",  0,      0,      0ull,   0ull},
7963         {"RNK_MSK"                     ,        8,      4,      37,     "R/W",  0,      0,      0ull,   15ull},
7964         {"TSKW"                        ,        12,     2,      37,     "R/W",  0,      0,      0ull,   0ull},
7965         {"RESERVED_14_15"              ,        14,     2,      37,     "RAZ",  0,      0,      0ull,   0ull},
7966         {"REF_INT"                     ,        16,     13,     37,     "R/W",  0,      0,      780ull, 780ull},
7967         {"RESERVED_29_31"              ,        29,     3,      37,     "RAZ",  1,      1,      0,      0},
7968         {"FPIP"                        ,        32,     3,      37,     "R/W",  0,      0,      0ull,   0ull},
7969         {"MRS_PGM"                     ,        35,     1,      37,     "R/W",  0,      0,      0ull,   0ull},
7970         {"TRFC"                        ,        36,     5,      37,     "R/W",  0,      0,      9ull,   9ull},
7971         {"RESERVED_41_63"              ,        41,     23,     37,     "RAZ",  1,      1,      0,      0},
7972         {"COMP_BYPASS"                 ,        0,      1,      38,     "R/W",  0,      0,      0ull,   1ull},
7973         {"NCTL_CSR"                    ,        1,      4,      38,     "R/W",  0,      1,      13ull,  0},
7974         {"PCTL_CSR"                    ,        5,      4,      38,     "R/W",  0,      1,      13ull,  0},
7975         {"RESERVED_9_55"               ,        9,      47,     38,     "RAZ",  1,      1,      0,      0},
7976         {"DFA__NCTL"                   ,        56,     4,      38,     "RO",   1,      1,      0,      0},
7977         {"DFA__PCTL"                   ,        60,     4,      38,     "RO",   1,      1,      0,      0},
7978         {"EMRS1"                       ,        0,      15,     39,     "R/W",  0,      0,      0ull,   0ull},
7979         {"RESERVED_15_15"              ,        15,     1,      39,     "RAZ",  1,      1,      0,      0},
7980         {"EMRS1_OCD"                   ,        16,     15,     39,     "R/W",  0,      0,      896ull, 896ull},
7981         {"RESERVED_31_63"              ,        31,     33,     39,     "RAZ",  1,      1,      0,      0},
7982         {"FCYC_CNT"                    ,        0,      47,     40,     "RO",   0,      0,      0ull,   0ull},
7983         {"RESERVED_47_63"              ,        47,     17,     40,     "RAZ",  1,      1,      0,      0},
7984         {"MRS_DLL"                     ,        0,      15,     41,     "R/W",  0,      0,      1858ull,        1858ull},
7985         {"RESERVED_15_15"              ,        15,     1,      41,     "RAZ",  1,      1,      0,      0},
7986         {"MRS"                         ,        16,     15,     41,     "R/W",  0,      0,      1602ull,        1602ull},
7987         {"RESERVED_31_63"              ,        31,     33,     41,     "RAZ",  1,      1,      0,      0},
7988         {"MAX_WRITE_BATCH"             ,        0,      5,      42,     "R/W",  0,      0,      31ull,  31ull},
7989         {"MAX_READ_BATCH"              ,        5,      5,      42,     "R/W",  0,      0,      31ull,  31ull},
7990         {"RESERVED_10_63"              ,        10,     54,     42,     "RAZ",  1,      1,      0,      0},
7991         {"PLL_INIT"                    ,        0,      1,      43,     "R/W",  0,      0,      0ull,   1ull},
7992         {"PLL_BYPASS"                  ,        1,      1,      43,     "R/W",  0,      0,      0ull,   0ull},
7993         {"PLL_RATIO"                   ,        2,      5,      43,     "R/W",  0,      1,      0ull,   0},
7994         {"RESERVED_7_7"                ,        7,      1,      43,     "RAZ",  1,      1,      0,      0},
7995         {"PLL_DIV2"                    ,        8,      1,      43,     "R/W",  0,      0,      0ull,   0ull},
7996         {"BW_UPD"                      ,        9,      1,      43,     "R/W",  0,      0,      0ull,   0ull},
7997         {"BW_CTL"                      ,        10,     4,      43,     "R/W",  0,      1,      0ull,   0},
7998         {"QDLL_ENA"                    ,        14,     1,      43,     "R/W",  0,      0,      0ull,   1ull},
7999         {"DLL_BYP"                     ,        15,     1,      43,     "R/W",  0,      1,      0ull,   0},
8000         {"DLL_SETTING"                 ,        16,     5,      43,     "R/W",  0,      1,      0ull,   0},
8001         {"RESERVED_21_26"              ,        21,     6,      43,     "RAZ",  1,      1,      0,      0},
8002         {"SETTING90"                   ,        27,     5,      43,     "RO",   0,      0,      0ull,   0ull},
8003         {"RESERVED_32_46"              ,        32,     15,     43,     "RAZ",  1,      1,      0,      0},
8004         {"PLL_SETTING"                 ,        47,     17,     43,     "RO",   0,      0,      0ull,   0ull},
8005         {"DDR2T"                       ,        0,      1,      44,     "R/W",  0,      0,      0ull,   0ull},
8006         {"TMRD"                        ,        1,      2,      44,     "R/W",  0,      0,      2ull,   2ull},
8007         {"CASLAT"                      ,        3,      3,      44,     "R/W",  0,      0,      4ull,   4ull},
8008         {"POCAS"                       ,        6,      1,      44,     "R/W",  0,      0,      0ull,   0ull},
8009         {"ADDLAT"                      ,        7,      3,      44,     "R/W",  0,      0,      0ull,   0ull},
8010         {"TRCD"                        ,        10,     4,      44,     "R/W",  0,      0,      2ull,   2ull},
8011         {"TRRD"                        ,        14,     3,      44,     "R/W",  0,      0,      2ull,   2ull},
8012         {"TRAS"                        ,        17,     5,      44,     "R/W",  0,      0,      10ull,  10ull},
8013         {"TRP"                         ,        22,     4,      44,     "R/W",  0,      0,      4ull,   4ull},
8014         {"TWR"                         ,        26,     3,      44,     "R/W",  0,      0,      3ull,   3ull},
8015         {"TWTR"                        ,        29,     4,      44,     "R/W",  0,      0,      2ull,   2ull},
8016         {"TFAW"                        ,        33,     5,      44,     "R/W",  0,      0,      9ull,   9ull},
8017         {"R2R_SLOT"                    ,        38,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
8018         {"DIC"                         ,        39,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
8019         {"DQSN_ENA"                    ,        40,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
8020         {"ODT_RTT"                     ,        41,     2,      44,     "R/W",  0,      0,      2ull,   2ull},
8021         {"CTR_RST"                     ,        43,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
8022         {"CAVMIPO"                     ,        44,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
8023         {"CNT_CLR"                     ,        45,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
8024         {"FCNT_MODE"                   ,        46,     1,      44,     "R/W",  0,      0,      1ull,   0ull},
8025         {"RESERVED_47_63"              ,        47,     17,     44,     "RAZ",  0,      0,      0ull,   0ull},
8026         {"SIZE"                        ,        0,      9,      45,     "R/W",  0,      1,      3ull,   0},
8027         {"POOL"                        ,        9,      3,      45,     "R/W",  0,      1,      0ull,   0},
8028         {"DWBCNT"                      ,        12,     8,      45,     "R/W",  0,      1,      1ull,   0},
8029         {"RESERVED_20_63"              ,        20,     44,     45,     "RAZ",  1,      1,      0,      0},
8030         {"RESERVED_0_4"                ,        0,      5,      46,     "RAZ",  1,      1,      0,      0},
8031         {"RDPTR"                       ,        5,      31,     46,     "R/W",  0,      1,      0ull,   0},
8032         {"RESERVED_36_63"              ,        36,     28,     46,     "RAZ",  1,      1,      0,      0},
8033         {"DFA_FRSTN"                   ,        0,      1,      47,     "R/W",  0,      0,      0ull,   1ull},
8034         {"MAXBNK"                      ,        1,      1,      47,     "R/W",  0,      0,      1ull,   1ull},
8035         {"DTECLKDIS"                   ,        2,      1,      47,     "R/W",  0,      0,      0ull,   0ull},
8036         {"RESERVED_3_7"                ,        3,      5,      47,     "RAZ",  0,      0,      0ull,   9ull},
8037         {"SARB"                        ,        8,      1,      47,     "R/W",  0,      0,      1ull,   1ull},
8038         {"IMODE"                       ,        9,      1,      47,     "R/W",  0,      0,      1ull,   1ull},
8039         {"QMODE"                       ,        10,     1,      47,     "R/W",  0,      0,      1ull,   1ull},
8040         {"PMODE"                       ,        11,     1,      47,     "R/W",  0,      0,      1ull,   1ull},
8041         {"DTMODE"                      ,        12,     1,      47,     "R/W",  0,      0,      1ull,   1ull},
8042         {"DCMODE"                      ,        13,     1,      47,     "R/W",  0,      0,      0ull,   0ull},
8043         {"SBDLCK"                      ,        14,     1,      47,     "R/W",  0,      0,      0ull,   0ull},
8044         {"RESERVED_15_15"              ,        15,     1,      47,     "RAZ",  1,      1,      0,      0},
8045         {"SBDNUM"                      ,        16,     3,      47,     "R/W",  0,      0,      0ull,   0ull},
8046         {"RESERVED_19_63"              ,        19,     45,     47,     "RAZ",  1,      1,      0,      0},
8047         {"CP2ECCENA"                   ,        0,      1,      48,     "R/W",  0,      0,      0ull,   0ull},
8048         {"CP2SBE"                      ,        1,      1,      48,     "R/W1C",        0,      0,      0ull,   0ull},
8049         {"CP2DBE"                      ,        2,      1,      48,     "R/W1C",        0,      0,      0ull,   0ull},
8050         {"CP2SBINA"                    ,        3,      1,      48,     "R/W",  0,      0,      0ull,   0ull},
8051         {"CP2DBINA"                    ,        4,      1,      48,     "R/W",  0,      0,      0ull,   0ull},
8052         {"CP2SYN"                      ,        5,      8,      48,     "RO",   0,      0,      0ull,   0ull},
8053         {"DTEECCENA"                   ,        13,     1,      48,     "R/W",  0,      0,      0ull,   0ull},
8054         {"DTESBE"                      ,        14,     1,      48,     "R/W1C",        0,      0,      0ull,   0ull},
8055         {"DTEDBE"                      ,        15,     1,      48,     "R/W1C",        0,      0,      0ull,   0ull},
8056         {"DTESBINA"                    ,        16,     1,      48,     "R/W",  0,      0,      0ull,   0ull},
8057         {"DTEDBINA"                    ,        17,     1,      48,     "R/W",  0,      0,      0ull,   0ull},
8058         {"DTESYN"                      ,        18,     7,      48,     "RO",   0,      0,      0ull,   0ull},
8059         {"DTEPARENA"                   ,        25,     1,      48,     "R/W",  0,      0,      0ull,   0ull},
8060         {"DTEPERR"                     ,        26,     1,      48,     "R/W1C",        0,      0,      0ull,   0ull},
8061         {"DTEPINA"                     ,        27,     1,      48,     "R/W",  0,      0,      0ull,   0ull},
8062         {"CP2PARENA"                   ,        28,     1,      48,     "R/W",  0,      0,      0ull,   0ull},
8063         {"CP2PERR"                     ,        29,     1,      48,     "R/W1C",        0,      0,      0ull,   0ull},
8064         {"CP2PINA"                     ,        30,     1,      48,     "R/W",  0,      0,      0ull,   0ull},
8065         {"DBLOVF"                      ,        31,     1,      48,     "R/W1C",        0,      0,      0ull,   0ull},
8066         {"DBLINA"                      ,        32,     1,      48,     "R/W",  0,      0,      0ull,   0ull},
8067         {"RESERVED_33_63"              ,        33,     31,     48,     "RAZ",  1,      1,      0,      0},
8068         {"MADDR"                       ,        0,      25,     49,     "RO",   0,      0,      0ull,   0ull},
8069         {"BNUM"                        ,        25,     3,      49,     "RO",   0,      0,      0ull,   0ull},
8070         {"PNUM"                        ,        28,     1,      49,     "RO",   0,      0,      0ull,   0ull},
8071         {"FSRC"                        ,        29,     2,      49,     "RO",   0,      0,      0ull,   0ull},
8072         {"FDST"                        ,        31,     9,      49,     "RO",   0,      0,      0ull,   0ull},
8073         {"RESERVED_40_63"              ,        40,     24,     49,     "RAZ",  1,      1,      0,      0},
8074         {"SBD0"                        ,        0,      64,     50,     "RO",   1,      1,      0,      0},
8075         {"SBD1"                        ,        0,      64,     51,     "RO",   1,      1,      0,      0},
8076         {"SBD2"                        ,        0,      64,     52,     "RO",   1,      1,      0,      0},
8077         {"SBD3"                        ,        0,      64,     53,     "RO",   1,      1,      0,      0},
8078         {"FDR"                         ,        0,      1,      54,     "RO",   0,      0,      0ull,   0ull},
8079         {"FFR"                         ,        1,      1,      54,     "RO",   0,      0,      0ull,   0ull},
8080         {"FPF1"                        ,        2,      1,      54,     "RO",   0,      0,      0ull,   0ull},
8081         {"FPF0"                        ,        3,      1,      54,     "RO",   0,      0,      0ull,   0ull},
8082         {"FRD"                         ,        4,      1,      54,     "RO",   0,      0,      0ull,   0ull},
8083         {"RESERVED_5_63"               ,        5,      59,     54,     "RAZ",  1,      1,      0,      0},
8084         {"MEM0_ERR"                    ,        0,      7,      55,     "R/W",  0,      0,      0ull,   0ull},
8085         {"MEM1_ERR"                    ,        7,      7,      55,     "R/W",  0,      0,      0ull,   0ull},
8086         {"ENB"                         ,        14,     1,      55,     "R/W",  0,      0,      0ull,   0ull},
8087         {"USE_STT"                     ,        15,     1,      55,     "R/W",  0,      0,      0ull,   0ull},
8088         {"USE_LDT"                     ,        16,     1,      55,     "R/W",  0,      0,      0ull,   0ull},
8089         {"RESET"                       ,        17,     1,      55,     "R/W",  0,      0,      0ull,   0ull},
8090         {"RESERVED_18_63"              ,        18,     46,     55,     "RAZ",  1,      1,      0,      0},
8091         {"FED0_SBE"                    ,        0,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8092         {"FED0_DBE"                    ,        1,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8093         {"FED1_SBE"                    ,        2,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8094         {"FED1_DBE"                    ,        3,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8095         {"Q0_UND"                      ,        4,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8096         {"Q0_COFF"                     ,        5,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8097         {"Q0_PERR"                     ,        6,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8098         {"Q1_UND"                      ,        7,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8099         {"Q1_COFF"                     ,        8,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8100         {"Q1_PERR"                     ,        9,      1,      56,     "R/W",  0,      0,      0ull,   0ull},
8101         {"Q2_UND"                      ,        10,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8102         {"Q2_COFF"                     ,        11,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8103         {"Q2_PERR"                     ,        12,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8104         {"Q3_UND"                      ,        13,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8105         {"Q3_COFF"                     ,        14,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8106         {"Q3_PERR"                     ,        15,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8107         {"Q4_UND"                      ,        16,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8108         {"Q4_COFF"                     ,        17,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8109         {"Q4_PERR"                     ,        18,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8110         {"Q5_UND"                      ,        19,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8111         {"Q5_COFF"                     ,        20,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8112         {"Q5_PERR"                     ,        21,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8113         {"Q6_UND"                      ,        22,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8114         {"Q6_COFF"                     ,        23,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8115         {"Q6_PERR"                     ,        24,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8116         {"Q7_UND"                      ,        25,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8117         {"Q7_COFF"                     ,        26,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8118         {"Q7_PERR"                     ,        27,     1,      56,     "R/W",  0,      0,      0ull,   0ull},
8119         {"RESERVED_28_63"              ,        28,     36,     56,     "RAZ",  1,      1,      0,      0},
8120         {"FED0_SBE"                    ,        0,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8121         {"FED0_DBE"                    ,        1,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8122         {"FED1_SBE"                    ,        2,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8123         {"FED1_DBE"                    ,        3,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8124         {"Q0_UND"                      ,        4,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8125         {"Q0_COFF"                     ,        5,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8126         {"Q0_PERR"                     ,        6,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8127         {"Q1_UND"                      ,        7,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8128         {"Q1_COFF"                     ,        8,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8129         {"Q1_PERR"                     ,        9,      1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8130         {"Q2_UND"                      ,        10,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8131         {"Q2_COFF"                     ,        11,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8132         {"Q2_PERR"                     ,        12,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8133         {"Q3_UND"                      ,        13,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8134         {"Q3_COFF"                     ,        14,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8135         {"Q3_PERR"                     ,        15,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8136         {"Q4_UND"                      ,        16,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8137         {"Q4_COFF"                     ,        17,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8138         {"Q4_PERR"                     ,        18,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8139         {"Q5_UND"                      ,        19,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8140         {"Q5_COFF"                     ,        20,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8141         {"Q5_PERR"                     ,        21,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8142         {"Q6_UND"                      ,        22,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8143         {"Q6_COFF"                     ,        23,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8144         {"Q6_PERR"                     ,        24,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8145         {"Q7_UND"                      ,        25,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8146         {"Q7_COFF"                     ,        26,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8147         {"Q7_PERR"                     ,        27,     1,      57,     "R/W1C",        0,      0,      0ull,   0ull},
8148         {"RESERVED_28_63"              ,        28,     36,     57,     "RAZ",  1,      1,      0,      0},
8149         {"QUE_SIZ"                     ,        0,      29,     58,     "RO",   0,      0,      0ull,   0ull},
8150         {"RESERVED_29_63"              ,        29,     35,     58,     "RAZ",  1,      1,      0,      0},
8151         {"PG_NUM"                      ,        0,      25,     59,     "RO",   0,      1,      0ull,   0},
8152         {"RESERVED_25_63"              ,        25,     39,     59,     "RAZ",  1,      1,      0,      0},
8153         {"ACT_INDX"                    ,        0,      26,     60,     "RO",   0,      1,      0ull,   0},
8154         {"ACT_QUE"                     ,        26,     3,      60,     "RO",   0,      1,      0ull,   0},
8155         {"RESERVED_29_63"              ,        29,     35,     60,     "RAZ",  0,      0,      0ull,   7ull},
8156         {"EXP_INDX"                    ,        0,      26,     61,     "RO",   0,      1,      0ull,   0},
8157         {"EXP_QUE"                     ,        26,     3,      61,     "RO",   0,      1,      0ull,   0},
8158         {"RESERVED_29_63"              ,        29,     35,     61,     "RAZ",  0,      0,      0ull,   7ull},
8159         {"CTL"                         ,        0,      16,     62,     "R/W",  1,      0,      0,      0ull},
8160         {"RESERVED_16_63"              ,        16,     48,     62,     "RAZ",  1,      1,      0,      0},
8161         {"STATUS"                      ,        0,      32,     63,     "RO",   0,      0,      0ull,   0ull},
8162         {"RESERVED_32_63"              ,        32,     32,     63,     "RAZ",  1,      1,      0,      0},
8163         {"RESERVED_0_1"                ,        0,      2,      64,     "RAZ",  0,      0,      0ull,   0ull},
8164         {"OUT_OVR"                     ,        2,      3,      64,     "R/W1C",        0,      0,      0ull,   0ull},
8165         {"RESERVED_5_21"               ,        5,      17,     64,     "RAZ",  0,      0,      0ull,   0ull},
8166         {"LOSTSTAT"                    ,        22,     3,      64,     "R/W1C",        0,      0,      0ull,   0ull},
8167         {"RESERVED_25_25"              ,        25,     1,      64,     "RAZ",  0,      0,      0ull,   0ull},
8168         {"STATOVR"                     ,        26,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
8169         {"INB_NXA"                     ,        27,     4,      64,     "R/W1C",        0,      0,      0ull,   0ull},
8170         {"RESERVED_31_63"              ,        31,     33,     64,     "RAZ",  1,      1,      0,      0},
8171         {"STATUS"                      ,        0,      10,     65,     "RO",   0,      0,      0ull,   0ull},
8172         {"RESERVED_10_63"              ,        10,     54,     65,     "RAZ",  1,      1,      0,      0},
8173         {"TYPE"                        ,        0,      1,      66,     "R/W",  0,      1,      0ull,   0},
8174         {"EN"                          ,        1,      1,      66,     "R/W",  0,      0,      0ull,   1ull},
8175         {"RESERVED_2_63"               ,        2,      62,     66,     "RAZ",  1,      1,      0,      0},
8176         {"PRT"                         ,        0,      6,      67,     "RO",   0,      1,      0ull,   0},
8177         {"RESERVED_6_63"               ,        6,      58,     67,     "RAZ",  1,      1,      0,      0},
8178         {"EN"                          ,        0,      1,      68,     "R/W",  0,      1,      0ull,   0},
8179         {"SPEED"                       ,        1,      1,      68,     "R/W",  0,      1,      1ull,   0},
8180         {"DUPLEX"                      ,        2,      1,      68,     "R/W",  0,      1,      1ull,   0},
8181         {"SLOTTIME"                    ,        3,      1,      68,     "R/W",  0,      1,      1ull,   0},
8182         {"RESERVED_4_63"               ,        4,      60,     68,     "RAZ",  1,      1,      0,      0},
8183         {"ADR"                         ,        0,      64,     69,     "R/W",  0,      1,      0ull,   0},
8184         {"ADR"                         ,        0,      64,     70,     "R/W",  0,      1,      0ull,   0},
8185         {"ADR"                         ,        0,      64,     71,     "R/W",  0,      1,      0ull,   0},
8186         {"ADR"                         ,        0,      64,     72,     "R/W",  0,      1,      0ull,   0},
8187         {"ADR"                         ,        0,      64,     73,     "R/W",  0,      1,      0ull,   0},
8188         {"ADR"                         ,        0,      64,     74,     "R/W",  0,      1,      0ull,   0},
8189         {"EN"                          ,        0,      8,      75,     "R/W",  0,      1,      0ull,   0},
8190         {"RESERVED_8_63"               ,        8,      56,     75,     "RAZ",  1,      1,      0,      0},
8191         {"BCST"                        ,        0,      1,      76,     "R/W",  0,      1,      1ull,   0},
8192         {"MCST"                        ,        1,      2,      76,     "R/W",  0,      1,      0ull,   0},
8193         {"CAM_MODE"                    ,        3,      1,      76,     "R/W",  0,      1,      0ull,   0},
8194         {"RESERVED_4_63"               ,        4,      60,     76,     "RAZ",  1,      1,      0,      0},
8195         {"CNT"                         ,        0,      5,      77,     "R/W",  0,      0,      24ull,  24ull},
8196         {"RESERVED_5_63"               ,        5,      59,     77,     "RAZ",  1,      1,      0,      0},
8197         {"MINERR"                      ,        0,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8198         {"CAREXT"                      ,        1,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8199         {"MAXERR"                      ,        2,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8200         {"JABBER"                      ,        3,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8201         {"FCSERR"                      ,        4,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8202         {"ALNERR"                      ,        5,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8203         {"LENERR"                      ,        6,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8204         {"RCVERR"                      ,        7,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8205         {"SKPERR"                      ,        8,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8206         {"NIBERR"                      ,        9,      1,      78,     "R/W",  0,      0,      1ull,   1ull},
8207         {"RESERVED_10_63"              ,        10,     54,     78,     "RAZ",  1,      1,      0,      0},
8208         {"PRE_CHK"                     ,        0,      1,      79,     "R/W",  0,      0,      1ull,   1ull},
8209         {"PRE_STRP"                    ,        1,      1,      79,     "R/W",  0,      0,      1ull,   1ull},
8210         {"CTL_DRP"                     ,        2,      1,      79,     "R/W",  0,      0,      1ull,   1ull},
8211         {"CTL_BCK"                     ,        3,      1,      79,     "R/W",  0,      0,      1ull,   1ull},
8212         {"CTL_MCST"                    ,        4,      1,      79,     "R/W",  0,      0,      1ull,   1ull},
8213         {"CTL_SMAC"                    ,        5,      1,      79,     "R/W",  0,      0,      1ull,   1ull},
8214         {"PRE_FREE"                    ,        6,      1,      79,     "R/W",  0,      0,      0ull,   0ull},
8215         {"VLAN_LEN"                    ,        7,      1,      79,     "R/W",  0,      0,      0ull,   0ull},
8216         {"RESERVED_8_63"               ,        8,      56,     79,     "RAZ",  1,      1,      0,      0},
8217         {"LEN"                         ,        0,      16,     80,     "R/W",  0,      0,      1536ull,        1536ull},
8218         {"RESERVED_16_63"              ,        16,     48,     80,     "RAZ",  1,      1,      0,      0},
8219         {"LEN"                         ,        0,      16,     81,     "R/W",  0,      0,      64ull,  64ull},
8220         {"RESERVED_16_63"              ,        16,     48,     81,     "RAZ",  1,      1,      0,      0},
8221         {"IFG"                         ,        0,      4,      82,     "R/W",  0,      0,      12ull,  12ull},
8222         {"RESERVED_4_63"               ,        4,      60,     82,     "RAZ",  1,      1,      0,      0},
8223         {"MINERR"                      ,        0,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8224         {"CAREXT"                      ,        1,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8225         {"MAXERR"                      ,        2,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8226         {"JABBER"                      ,        3,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8227         {"FCSERR"                      ,        4,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8228         {"ALNERR"                      ,        5,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8229         {"LENERR"                      ,        6,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8230         {"RCVERR"                      ,        7,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8231         {"SKPERR"                      ,        8,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8232         {"NIBERR"                      ,        9,      1,      83,     "R/W",  0,      0,      0ull,   0ull},
8233         {"OVRERR"                      ,        10,     1,      83,     "R/W",  0,      0,      0ull,   0ull},
8234         {"PCTERR"                      ,        11,     1,      83,     "R/W",  0,      0,      0ull,   0ull},
8235         {"RSVERR"                      ,        12,     1,      83,     "R/W",  0,      0,      0ull,   0ull},
8236         {"FALERR"                      ,        13,     1,      83,     "R/W",  0,      0,      0ull,   0ull},
8237         {"COLDET"                      ,        14,     1,      83,     "R/W",  0,      0,      0ull,   0ull},
8238         {"IFGERR"                      ,        15,     1,      83,     "R/W",  0,      0,      0ull,   0ull},
8239         {"PHY_LINK"                    ,        16,     1,      83,     "R/W",  0,      0,      0ull,   0ull},
8240         {"PHY_SPD"                     ,        17,     1,      83,     "R/W",  0,      0,      0ull,   0ull},
8241         {"PHY_DUPX"                    ,        18,     1,      83,     "R/W",  0,      0,      0ull,   0ull},
8242         {"RESERVED_19_63"              ,        19,     45,     83,     "RAZ",  1,      1,      0,      0},
8243         {"MINERR"                      ,        0,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8244         {"CAREXT"                      ,        1,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8245         {"MAXERR"                      ,        2,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8246         {"JABBER"                      ,        3,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8247         {"FCSERR"                      ,        4,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8248         {"ALNERR"                      ,        5,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8249         {"LENERR"                      ,        6,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8250         {"RCVERR"                      ,        7,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8251         {"SKPERR"                      ,        8,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8252         {"NIBERR"                      ,        9,      1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8253         {"OVRERR"                      ,        10,     1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8254         {"PCTERR"                      ,        11,     1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8255         {"RSVERR"                      ,        12,     1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8256         {"FALERR"                      ,        13,     1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8257         {"COLDET"                      ,        14,     1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8258         {"IFGERR"                      ,        15,     1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8259         {"PHY_LINK"                    ,        16,     1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8260         {"PHY_SPD"                     ,        17,     1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8261         {"PHY_DUPX"                    ,        18,     1,      84,     "R/W1C",        0,      0,      0ull,   0ull},
8262         {"RESERVED_19_63"              ,        19,     45,     84,     "RAZ",  1,      1,      0,      0},
8263         {"CNT"                         ,        0,      16,     85,     "R/W",  0,      0,      10240ull,       10240ull},
8264         {"RESERVED_16_63"              ,        16,     48,     85,     "RAZ",  1,      1,      0,      0},
8265         {"STATUS"                      ,        0,      1,      86,     "RO",   0,      1,      0ull,   0},
8266         {"SPEED"                       ,        1,      2,      86,     "RO",   0,      1,      0ull,   0},
8267         {"DUPLEX"                      ,        3,      1,      86,     "RO",   0,      1,      0ull,   0},
8268         {"RESERVED_4_63"               ,        4,      60,     86,     "RAZ",  1,      1,      0,      0},
8269         {"RD_CLR"                      ,        0,      1,      87,     "R/W",  0,      0,      0ull,   0ull},
8270         {"RESERVED_1_63"               ,        1,      63,     87,     "RAZ",  1,      1,      0,      0},
8271         {"CNT"                         ,        0,      48,     88,     "RC/W", 0,      1,      0ull,   0},
8272         {"RESERVED_48_63"              ,        48,     16,     88,     "RAZ",  1,      1,      0,      0},
8273         {"CNT"                         ,        0,      48,     89,     "RC/W", 0,      1,      0ull,   0},
8274         {"RESERVED_48_63"              ,        48,     16,     89,     "RAZ",  1,      1,      0,      0},
8275         {"CNT"                         ,        0,      48,     90,     "RC/W", 0,      1,      0ull,   0},
8276         {"RESERVED_48_63"              ,        48,     16,     90,     "RAZ",  1,      1,      0,      0},
8277         {"CNT"                         ,        0,      48,     91,     "RC/W", 0,      1,      0ull,   0},
8278         {"RESERVED_48_63"              ,        48,     16,     91,     "RAZ",  1,      1,      0,      0},
8279         {"CNT"                         ,        0,      32,     92,     "RC/W", 0,      1,      0ull,   0},
8280         {"RESERVED_32_63"              ,        32,     32,     92,     "RAZ",  1,      1,      0,      0},
8281         {"CNT"                         ,        0,      32,     93,     "RC/W", 0,      1,      0ull,   0},
8282         {"RESERVED_32_63"              ,        32,     32,     93,     "RAZ",  1,      1,      0,      0},
8283         {"CNT"                         ,        0,      32,     94,     "RC/W", 0,      1,      0ull,   0},
8284         {"RESERVED_32_63"              ,        32,     32,     94,     "RAZ",  1,      1,      0,      0},
8285         {"CNT"                         ,        0,      32,     95,     "RC/W", 0,      1,      0ull,   0},
8286         {"RESERVED_32_63"              ,        32,     32,     95,     "RAZ",  1,      1,      0,      0},
8287         {"CNT"                         ,        0,      32,     96,     "RC/W", 0,      1,      0ull,   0},
8288         {"RESERVED_32_63"              ,        32,     32,     96,     "RAZ",  1,      1,      0,      0},
8289         {"LEN"                         ,        0,      7,      97,     "R/W",  0,      0,      0ull,   0ull},
8290         {"RESERVED_7_7"                ,        7,      1,      97,     "RAZ",  1,      1,      0,      0},
8291         {"FCSSEL"                      ,        8,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
8292         {"RESERVED_9_63"               ,        9,      55,     97,     "RAZ",  1,      1,      0,      0},
8293         {"MARK"                        ,        0,      6,      98,     "R/W",  1,      1,      0,      0},
8294         {"RESERVED_6_63"               ,        6,      58,     98,     "RAZ",  1,      1,      0,      0},
8295         {"MARK"                        ,        0,      6,      99,     "R/W",  0,      0,      16ull,  16ull},
8296         {"RESERVED_6_63"               ,        6,      58,     99,     "RAZ",  1,      1,      0,      0},
8297         {"MARK"                        ,        0,      9,      100,    "R/W",  1,      1,      0,      0},
8298         {"RESERVED_9_63"               ,        9,      55,     100,    "RAZ",  1,      1,      0,      0},
8299         {"COMMIT"                      ,        0,      3,      101,    "RO",   0,      0,      0ull,   0ull},
8300         {"RESERVED_3_15"               ,        3,      13,     101,    "RAZ",  1,      1,      0,      0},
8301         {"DROP"                        ,        16,     3,      101,    "RO",   0,      0,      0ull,   0ull},
8302         {"RESERVED_19_63"              ,        19,     45,     101,    "RAZ",  1,      1,      0,      0},
8303         {"PRTS"                        ,        0,      3,      102,    "R/W",  0,      0,      3ull,   3ull},
8304         {"RESERVED_3_63"               ,        3,      61,     102,    "RAZ",  1,      1,      0,      0},
8305         {"RX"                          ,        0,      3,      103,    "RC",   0,      0,      0ull,   0ull},
8306         {"RESERVED_3_3"                ,        3,      1,      103,    "RAZ",  1,      1,      0,      0},
8307         {"TX"                          ,        4,      3,      103,    "RC",   0,      0,      0ull,   0ull},
8308         {"RESERVED_7_63"               ,        7,      57,     103,    "RAZ",  1,      1,      0,      0},
8309         {"SMAC"                        ,        0,      48,     104,    "R/W",  0,      1,      0ull,   0},
8310         {"RESERVED_48_63"              ,        48,     16,     104,    "RAZ",  1,      1,      0,      0},
8311         {"CNT"                         ,        0,      16,     105,    "R/W1C",        0,      0,      0ull,   0ull},
8312         {"BP"                          ,        16,     1,      105,    "RO",   0,      0,      0ull,   0ull},
8313         {"RESERVED_17_63"              ,        17,     47,     105,    "RAZ",  1,      1,      0,      0},
8314         {"PREAMBLE"                    ,        0,      1,      106,    "R/W",  0,      0,      1ull,   1ull},
8315         {"PAD"                         ,        1,      1,      106,    "R/W",  0,      0,      1ull,   1ull},
8316         {"FCS"                         ,        2,      1,      106,    "R/W",  0,      0,      1ull,   1ull},
8317         {"FORCE_FCS"                   ,        3,      1,      106,    "R/W",  0,      0,      1ull,   1ull},
8318         {"RESERVED_4_63"               ,        4,      60,     106,    "RAZ",  1,      1,      0,      0},
8319         {"BURST"                       ,        0,      16,     107,    "R/W",  0,      0,      8192ull,        8192ull},
8320         {"RESERVED_16_63"              ,        16,     48,     107,    "RAZ",  1,      1,      0,      0},
8321         {"CLK_CNT"                     ,        0,      6,      108,    "R/W",  0,      0,      1ull,   1ull},
8322         {"RESERVED_6_63"               ,        6,      58,     108,    "RAZ",  1,      1,      0,      0},
8323         {"XSCOL_EN"                    ,        0,      1,      109,    "R/W",  0,      0,      1ull,   1ull},
8324         {"XSDEF_EN"                    ,        1,      1,      109,    "R/W",  0,      0,      1ull,   1ull},
8325         {"RESERVED_2_63"               ,        2,      62,     109,    "RAZ",  1,      1,      0,      0},
8326         {"MIN_SIZE"                    ,        0,      8,      110,    "R/W",  0,      0,      59ull,  59ull},
8327         {"RESERVED_8_63"               ,        8,      56,     110,    "RAZ",  1,      1,      0,      0},
8328         {"INTERVAL"                    ,        0,      16,     111,    "R/W",  0,      1,      16ull,  0},
8329         {"RESERVED_16_63"              ,        16,     48,     111,    "RAZ",  1,      1,      0,      0},
8330         {"TIME"                        ,        0,      16,     112,    "R/W",  0,      1,      96ull,  0},
8331         {"RESERVED_16_63"              ,        16,     48,     112,    "RAZ",  1,      1,      0,      0},
8332         {"TIME"                        ,        0,      16,     113,    "RO",   1,      1,      0,      0},
8333         {"RESERVED_16_63"              ,        16,     48,     113,    "RAZ",  1,      1,      0,      0},
8334         {"SEND"                        ,        0,      1,      114,    "R/W",  0,      0,      1ull,   1ull},
8335         {"RESERVED_1_63"               ,        1,      63,     114,    "RAZ",  1,      1,      0,      0},
8336         {"SLOT"                        ,        0,      10,     115,    "R/W",  0,      0,      512ull, 512ull},
8337         {"RESERVED_10_63"              ,        10,     54,     115,    "RAZ",  1,      1,      0,      0},
8338         {"TIME"                        ,        0,      16,     116,    "R/W",  0,      1,      0ull,   0},
8339         {"RESERVED_16_63"              ,        16,     48,     116,    "RAZ",  1,      1,      0,      0},
8340         {"XSCOL"                       ,        0,      32,     117,    "RC/W", 0,      1,      0ull,   0},
8341         {"XSDEF"                       ,        32,     32,     117,    "RC/W", 0,      1,      0ull,   0},
8342         {"MCOL"                        ,        0,      32,     118,    "RC/W", 0,      1,      0ull,   0},
8343         {"SCOL"                        ,        32,     32,     118,    "RC/W", 0,      1,      0ull,   0},
8344         {"OCTS"                        ,        0,      48,     119,    "RC/W", 0,      1,      0ull,   0},
8345         {"RESERVED_48_63"              ,        48,     16,     119,    "RAZ",  1,      1,      0,      0},
8346         {"PKTS"                        ,        0,      32,     120,    "RC/W", 0,      1,      0ull,   0},
8347         {"RESERVED_32_63"              ,        32,     32,     120,    "RAZ",  1,      1,      0,      0},
8348         {"HIST0"                       ,        0,      32,     121,    "RC/W", 0,      1,      0ull,   0},
8349         {"HIST1"                       ,        32,     32,     121,    "RC/W", 0,      1,      0ull,   0},
8350         {"HIST2"                       ,        0,      32,     122,    "RC/W", 0,      1,      0ull,   0},
8351         {"HIST3"                       ,        32,     32,     122,    "RC/W", 0,      1,      0ull,   0},
8352         {"HIST4"                       ,        0,      32,     123,    "RC/W", 0,      1,      0ull,   0},
8353         {"HIST5"                       ,        32,     32,     123,    "RC/W", 0,      1,      0ull,   0},
8354         {"HIST6"                       ,        0,      32,     124,    "RC/W", 0,      1,      0ull,   0},
8355         {"HIST7"                       ,        32,     32,     124,    "RC/W", 0,      1,      0ull,   0},
8356         {"BCST"                        ,        0,      32,     125,    "RC/W", 0,      1,      0ull,   0},
8357         {"MCST"                        ,        32,     32,     125,    "RC/W", 0,      1,      0ull,   0},
8358         {"CTL"                         ,        0,      32,     126,    "RC/W", 0,      1,      0ull,   0},
8359         {"UNDFLW"                      ,        32,     32,     126,    "RC/W", 0,      1,      0ull,   0},
8360         {"RD_CLR"                      ,        0,      1,      127,    "R/W",  0,      0,      0ull,   0ull},
8361         {"RESERVED_1_63"               ,        1,      63,     127,    "RAZ",  1,      1,      0,      0},
8362         {"CNT"                         ,        0,      7,      128,    "R/W",  0,      0,      32ull,  32ull},
8363         {"RESERVED_7_63"               ,        7,      57,     128,    "RAZ",  1,      1,      0,      0},
8364         {"BP"                          ,        0,      3,      129,    "RO",   0,      0,      0ull,   0ull},
8365         {"RESERVED_3_63"               ,        3,      61,     129,    "RAZ",  1,      1,      0,      0},
8366         {"LIMIT"                       ,        0,      5,      130,    "R/W",  0,      0,      16ull,  16ull},
8367         {"RESERVED_5_63"               ,        5,      59,     130,    "RAZ",  1,      1,      0,      0},
8368         {"CORRUPT"                     ,        0,      3,      131,    "R/W",  0,      0,      15ull,  15ull},
8369         {"RESERVED_3_63"               ,        3,      61,     131,    "RAZ",  1,      1,      0,      0},
8370         {"IFG1"                        ,        0,      4,      132,    "R/W",  0,      1,      8ull,   0},
8371         {"IFG2"                        ,        4,      4,      132,    "R/W",  0,      1,      4ull,   0},
8372         {"RESERVED_8_63"               ,        8,      56,     132,    "RAZ",  1,      1,      0,      0},
8373         {"PKO_NXA"                     ,        0,      1,      133,    "R/W",  0,      0,      0ull,   0ull},
8374         {"RESERVED_1_1"                ,        1,      1,      133,    "RAZ",  0,      0,      0ull,   0ull},
8375         {"UNDFLW"                      ,        2,      3,      133,    "R/W",  0,      0,      0ull,   0ull},
8376         {"RESERVED_5_7"                ,        5,      3,      133,    "RAZ",  0,      0,      0ull,   0ull},
8377         {"XSCOL"                       ,        8,      3,      133,    "R/W",  0,      0,      0ull,   0ull},
8378         {"RESERVED_11_11"              ,        11,     1,      133,    "RAZ",  0,      0,      0ull,   0ull},
8379         {"XSDEF"                       ,        12,     3,      133,    "R/W",  0,      0,      0ull,   0ull},
8380         {"RESERVED_15_63"              ,        15,     49,     133,    "RAZ",  0,      0,      0ull,   0ull},
8381         {"PKO_NXA"                     ,        0,      1,      134,    "R/W1C",        0,      0,      0ull,   0ull},
8382         {"RESERVED_1_1"                ,        1,      1,      134,    "RAZ",  0,      0,      0ull,   0ull},
8383         {"UNDFLW"                      ,        2,      3,      134,    "R/W1C",        0,      0,      0ull,   0ull},
8384         {"RESERVED_5_7"                ,        5,      3,      134,    "RAZ",  0,      0,      0ull,   0ull},
8385         {"XSCOL"                       ,        8,      3,      134,    "R/W1C",        0,      0,      0ull,   0ull},
8386         {"RESERVED_11_11"              ,        11,     1,      134,    "RAZ",  0,      0,      0ull,   0ull},
8387         {"XSDEF"                       ,        12,     3,      134,    "R/W1C",        0,      0,      0ull,   0ull},
8388         {"RESERVED_15_63"              ,        15,     49,     134,    "RAZ",  0,      0,      0ull,   0ull},
8389         {"JAM"                         ,        0,      8,      135,    "R/W",  0,      1,      238ull, 0},
8390         {"RESERVED_8_63"               ,        8,      56,     135,    "RAZ",  1,      1,      0,      0},
8391         {"LFSR"                        ,        0,      16,     136,    "R/W",  0,      1,      65535ull,       0},
8392         {"RESERVED_16_63"              ,        16,     48,     136,    "RAZ",  1,      1,      0,      0},
8393         {"IGN_FULL"                    ,        0,      3,      137,    "R/W",  0,      0,      0ull,   0ull},
8394         {"RESERVED_3_3"                ,        3,      1,      137,    "RAZ",  0,      0,      0ull,   0ull},
8395         {"BP"                          ,        4,      3,      137,    "R/W",  0,      0,      0ull,   0ull},
8396         {"RESERVED_7_7"                ,        7,      1,      137,    "RAZ",  0,      0,      0ull,   0ull},
8397         {"EN"                          ,        8,      3,      137,    "R/W",  0,      0,      0ull,   0ull},
8398         {"RESERVED_11_63"              ,        11,     53,     137,    "RAZ",  0,      0,      0ull,   0ull},
8399         {"DMAC"                        ,        0,      48,     138,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
8400         {"RESERVED_48_63"              ,        48,     16,     138,    "RAZ",  1,      1,      0,      0},
8401         {"TYPE"                        ,        0,      16,     139,    "R/W",  0,      0,      34824ull,       34824ull},
8402         {"RESERVED_16_63"              ,        16,     48,     139,    "RAZ",  1,      1,      0,      0},
8403         {"PRTS"                        ,        0,      5,      140,    "R/W",  0,      1,      3ull,   0},
8404         {"RESERVED_5_63"               ,        5,      59,     140,    "RAZ",  1,      1,      0,      0},
8405         {"TX_OE"                       ,        0,      1,      141,    "R/W",  0,      0,      0ull,   0ull},
8406         {"RX_XOR"                      ,        1,      1,      141,    "R/W",  0,      0,      0ull,   0ull},
8407         {"INT_EN"                      ,        2,      1,      141,    "R/W",  0,      0,      0ull,   0ull},
8408         {"INT_TYPE"                    ,        3,      1,      141,    "R/W",  0,      0,      0ull,   0ull},
8409         {"FIL_CNT"                     ,        4,      4,      141,    "R/W",  0,      0,      0ull,   0ull},
8410         {"FIL_SEL"                     ,        8,      4,      141,    "R/W",  0,      0,      0ull,   0ull},
8411         {"RESERVED_12_63"              ,        12,     52,     141,    "RAZ",  1,      1,      0,      0},
8412         {"RESERVED_0_7"                ,        0,      8,      142,    "RAZ",  1,      1,      0,      0},
8413         {"BOOT_ENA"                    ,        8,      4,      142,    "R/W",  0,      1,      0ull,   0},
8414         {"RESERVED_12_63"              ,        12,     52,     142,    "RAZ",  1,      1,      0,      0},
8415         {"DBG_ENA"                     ,        0,      21,     143,    "R/W",  0,      0,      0ull,   0ull},
8416         {"RESERVED_21_63"              ,        21,     43,     143,    "RAZ",  1,      1,      0,      0},
8417         {"TYPE"                        ,        0,      16,     144,    "WO",   0,      0,      0ull,   0ull},
8418         {"RESERVED_16_63"              ,        16,     48,     144,    "RAZ",  1,      1,      0,      0},
8419         {"DAT"                         ,        0,      24,     145,    "RO",   0,      0,      0ull,   0ull},
8420         {"RESERVED_24_63"              ,        24,     40,     145,    "RAZ",  1,      1,      0,      0},
8421         {"CLR"                         ,        0,      24,     146,    "WO",   0,      0,      0ull,   0ull},
8422         {"RESERVED_24_63"              ,        24,     40,     146,    "RAZ",  1,      1,      0,      0},
8423         {"SET"                         ,        0,      24,     147,    "WO",   0,      0,      0ull,   0ull},
8424         {"RESERVED_24_63"              ,        24,     40,     147,    "RAZ",  1,      1,      0,      0},
8425         {"TX_OE"                       ,        0,      1,      148,    "R/W",  0,      0,      0ull,   0ull},
8426         {"RX_XOR"                      ,        1,      1,      148,    "R/W",  0,      0,      0ull,   0ull},
8427         {"RESERVED_2_3"                ,        2,      2,      148,    "RAZ",  1,      1,      0,      0},
8428         {"FIL_CNT"                     ,        4,      4,      148,    "R/W",  0,      0,      0ull,   0ull},
8429         {"FIL_SEL"                     ,        8,      4,      148,    "R/W",  0,      0,      0ull,   0ull},
8430         {"RESERVED_12_63"              ,        12,     52,     148,    "RAZ",  1,      1,      0,      0},
8431         {"ICD"                         ,        0,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8432         {"IBD"                         ,        1,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8433         {"ICRP1"                       ,        2,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8434         {"ICRP0"                       ,        3,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8435         {"ICRN1"                       ,        4,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8436         {"ICRN0"                       ,        5,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8437         {"IBRQ1"                       ,        6,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8438         {"IBRQ0"                       ,        7,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8439         {"ICNRT"                       ,        8,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8440         {"IBR1"                        ,        9,      1,      149,    "RO",   0,      0,      0ull,   0ull},
8441         {"IBR0"                        ,        10,     1,      149,    "RO",   0,      0,      0ull,   0ull},
8442         {"IBDR1"                       ,        11,     1,      149,    "RO",   0,      0,      0ull,   0ull},
8443         {"IBDR0"                       ,        12,     1,      149,    "RO",   0,      0,      0ull,   0ull},
8444         {"ICNR0"                       ,        13,     1,      149,    "RO",   0,      0,      0ull,   0ull},
8445         {"ICNR1"                       ,        14,     1,      149,    "RO",   0,      0,      0ull,   0ull},
8446         {"ICR1"                        ,        15,     1,      149,    "RO",   0,      0,      0ull,   0ull},
8447         {"ICR0"                        ,        16,     1,      149,    "RO",   0,      0,      0ull,   0ull},
8448         {"ICNRCB"                      ,        17,     1,      149,    "RO",   0,      0,      0ull,   0ull},
8449         {"RESERVED_18_63"              ,        18,     46,     149,    "RAZ",  1,      1,      0,      0},
8450         {"FAU_END"                     ,        0,      1,      150,    "R/W",  0,      0,      0ull,   0ull},
8451         {"DWB_ENB"                     ,        1,      1,      150,    "R/W",  0,      0,      1ull,   1ull},
8452         {"PKO_ENB"                     ,        2,      1,      150,    "R/W",  0,      0,      0ull,   0ull},
8453         {"INB_MAT"                     ,        3,      1,      150,    "R/W1C",        0,      0,      0ull,   0ull},
8454         {"OUTB_MAT"                    ,        4,      1,      150,    "R/W1C",        0,      0,      0ull,   0ull},
8455         {"RESERVED_5_63"               ,        5,      59,     150,    "RAZ",  1,      1,      0,      0},
8456         {"TOUT_VAL"                    ,        0,      12,     151,    "R/W",  0,      0,      4ull,   4ull},
8457         {"TOUT_ENB"                    ,        12,     1,      151,    "R/W",  0,      0,      1ull,   0ull},
8458         {"RESERVED_13_63"              ,        13,     51,     151,    "RAZ",  1,      1,      0,      0},
8459         {"SRC"                         ,        0,      8,      152,    "R/W",  0,      1,      0ull,   0},
8460         {"DST"                         ,        8,      9,      152,    "R/W",  0,      1,      0ull,   0},
8461         {"OPC"                         ,        17,     4,      152,    "R/W",  0,      1,      0ull,   0},
8462         {"MASK"                        ,        21,     8,      152,    "R/W",  0,      1,      0ull,   0},
8463         {"RESERVED_29_63"              ,        29,     35,     152,    "RAZ",  1,      1,      0,      0},
8464         {"SRC"                         ,        0,      8,      153,    "R/W",  0,      1,      0ull,   0},
8465         {"DST"                         ,        8,      9,      153,    "R/W",  0,      1,      0ull,   0},
8466         {"OPC"                         ,        17,     4,      153,    "R/W",  0,      1,      0ull,   0},
8467         {"MASK"                        ,        21,     8,      153,    "R/W",  0,      1,      0ull,   0},
8468         {"RESERVED_29_63"              ,        29,     35,     153,    "RAZ",  1,      1,      0,      0},
8469         {"DATA"                        ,        0,      64,     154,    "R/W",  0,      1,      0ull,   0},
8470         {"DATA"                        ,        0,      64,     155,    "R/W",  0,      1,      0ull,   0},
8471         {"NP_SOP"                      ,        0,      1,      156,    "R/W",  0,      0,      0ull,   0ull},
8472         {"NP_EOP"                      ,        1,      1,      156,    "R/W",  0,      0,      0ull,   0ull},
8473         {"P_SOP"                       ,        2,      1,      156,    "R/W",  0,      0,      0ull,   0ull},
8474         {"P_EOP"                       ,        3,      1,      156,    "R/W",  0,      0,      0ull,   0ull},
8475         {"RESERVED_4_63"               ,        4,      60,     156,    "RAZ",  1,      1,      0,      0},
8476         {"NP_SOP"                      ,        0,      1,      157,    "R/W1C",        0,      0,      0ull,   0ull},
8477         {"NP_EOP"                      ,        1,      1,      157,    "R/W1C",        0,      0,      0ull,   0ull},
8478         {"P_SOP"                       ,        2,      1,      157,    "R/W1C",        0,      0,      0ull,   0ull},
8479         {"P_EOP"                       ,        3,      1,      157,    "R/W1C",        0,      0,      0ull,   0ull},
8480         {"RESERVED_4_63"               ,        4,      60,     157,    "RAZ",  1,      1,      0,      0},
8481         {"SRC"                         ,        0,      9,      158,    "R/W",  0,      1,      0ull,   0},
8482         {"DST"                         ,        9,      8,      158,    "R/W",  0,      1,      0ull,   0},
8483         {"EOT"                         ,        17,     1,      158,    "R/W",  0,      1,      0ull,   0},
8484         {"MASK"                        ,        18,     8,      158,    "R/W",  0,      1,      0ull,   0},
8485         {"RESERVED_26_63"              ,        26,     38,     158,    "RAZ",  1,      1,      0,      0},
8486         {"SRC"                         ,        0,      9,      159,    "R/W",  0,      1,      0ull,   0},
8487         {"DST"                         ,        9,      8,      159,    "R/W",  0,      1,      0ull,   0},
8488         {"EOT"                         ,        17,     1,      159,    "R/W",  0,      1,      0ull,   0},
8489         {"MASK"                        ,        18,     8,      159,    "R/W",  0,      1,      0ull,   0},
8490         {"RESERVED_26_63"              ,        26,     38,     159,    "RAZ",  1,      1,      0,      0},
8491         {"DATA"                        ,        0,      64,     160,    "R/W",  0,      1,      0ull,   0},
8492         {"DATA"                        ,        0,      64,     161,    "R/W",  0,      1,      0ull,   0},
8493         {"PORT"                        ,        0,      6,      162,    "RO",   0,      1,      0ull,   0},
8494         {"RESERVED_6_63"               ,        6,      58,     162,    "RAZ",  1,      1,      0,      0},
8495         {"SKIP_SZ"                     ,        0,      6,      163,    "R/W",  0,      0,      0ull,   0ull},
8496         {"RESERVED_6_63"               ,        6,      58,     163,    "RAZ",  1,      1,      0,      0},
8497         {"BACK"                        ,        0,      4,      164,    "R/W",  0,      0,      0ull,   0ull},
8498         {"RESERVED_4_63"               ,        4,      60,     164,    "RAZ",  1,      1,      0,      0},
8499         {"BACK"                        ,        0,      4,      165,    "R/W",  0,      0,      0ull,   0ull},
8500         {"RESERVED_4_63"               ,        4,      60,     165,    "RAZ",  1,      1,      0,      0},
8501         {"PWP"                         ,        0,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8502         {"IPD_NEW"                     ,        1,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8503         {"IPD_OLD"                     ,        2,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8504         {"PRC_OFF"                     ,        3,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8505         {"PWQ0"                        ,        4,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8506         {"PWQ1"                        ,        5,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8507         {"PBM_WORD"                    ,        6,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8508         {"PBM0"                        ,        7,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8509         {"PBM1"                        ,        8,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8510         {"PBM2"                        ,        9,      1,      166,    "RO",   0,      0,      0ull,   0ull},
8511         {"PBM3"                        ,        10,     1,      166,    "RO",   0,      0,      0ull,   0ull},
8512         {"IPQ_PBE0"                    ,        11,     1,      166,    "RO",   0,      0,      0ull,   0ull},
8513         {"IPQ_PBE1"                    ,        12,     1,      166,    "RO",   0,      0,      0ull,   0ull},
8514         {"PWQ_POW"                     ,        13,     1,      166,    "RO",   0,      0,      0ull,   0ull},
8515         {"PWQ_WP1"                     ,        14,     1,      166,    "RO",   0,      0,      0ull,   0ull},
8516         {"PWQ_WQED"                    ,        15,     1,      166,    "RO",   0,      0,      0ull,   0ull},
8517         {"RESERVED_16_63"              ,        16,     48,     166,    "RAZ",  1,      1,      0,      0},
8518         {"PRT_ENB"                     ,        0,      36,     167,    "R/W",  0,      0,      0ull,   0ull},
8519         {"RESERVED_36_63"              ,        36,     28,     167,    "RAZ",  1,      1,      0,      0},
8520         {"CLK_CNT"                     ,        0,      64,     168,    "RO",   0,      0,      0ull,   0ull},
8521         {"IPD_EN"                      ,        0,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
8522         {"OPC_MODE"                    ,        1,      2,      169,    "R/W",  0,      0,      0ull,   0ull},
8523         {"PBP_EN"                      ,        3,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
8524         {"WQE_LEND"                    ,        4,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
8525         {"PKT_LEND"                    ,        5,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
8526         {"NADDBUF"                     ,        6,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
8527         {"ADDPKT"                      ,        7,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
8528         {"RESET"                       ,        8,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
8529         {"LEN_M8"                      ,        9,      1,      169,    "R/W",  0,      0,      0ull,   1ull},
8530         {"RESERVED_10_63"              ,        10,     54,     169,    "RAZ",  1,      1,      0,      0},
8531         {"PRC_PAR0"                    ,        0,      1,      170,    "R/W",  0,      0,      0ull,   0ull},
8532         {"PRC_PAR1"                    ,        1,      1,      170,    "R/W",  0,      0,      0ull,   0ull},
8533         {"PRC_PAR2"                    ,        2,      1,      170,    "R/W",  0,      0,      0ull,   0ull},
8534         {"PRC_PAR3"                    ,        3,      1,      170,    "R/W",  0,      0,      0ull,   0ull},
8535         {"BP_SUB"                      ,        4,      1,      170,    "R/W",  0,      0,      0ull,   0ull},
8536         {"RESERVED_5_63"               ,        5,      59,     170,    "RAZ",  1,      1,      0,      0},
8537         {"PRC_PAR0"                    ,        0,      1,      171,    "R/W1C",        0,      0,      0ull,   0ull},
8538         {"PRC_PAR1"                    ,        1,      1,      171,    "R/W1C",        0,      0,      0ull,   0ull},
8539         {"PRC_PAR2"                    ,        2,      1,      171,    "R/W1C",        0,      0,      0ull,   0ull},
8540         {"PRC_PAR3"                    ,        3,      1,      171,    "R/W1C",        0,      0,      0ull,   0ull},
8541         {"BP_SUB"                      ,        4,      1,      171,    "R/W1C",        0,      0,      0ull,   0ull},
8542         {"RESERVED_5_63"               ,        5,      59,     171,    "RAZ",  1,      1,      0,      0},
8543         {"SKIP_SZ"                     ,        0,      6,      172,    "R/W",  0,      0,      0ull,   0ull},
8544         {"RESERVED_6_63"               ,        6,      58,     172,    "RAZ",  1,      1,      0,      0},
8545         {"MB_SIZE"                     ,        0,      12,     173,    "R/W",  0,      0,      32ull,  32ull},
8546         {"RESERVED_12_63"              ,        12,     52,     173,    "RAZ",  1,      1,      0,      0},
8547         {"PTR"                         ,        0,      29,     174,    "RO",   1,      1,      0,      0},
8548         {"RESERVED_29_63"              ,        29,     35,     174,    "RAZ",  1,      1,      0,      0},
8549         {"PAGE_CNT"                    ,        0,      17,     175,    "R/W",  0,      0,      0ull,   0ull},
8550         {"BP_ENB"                      ,        17,     1,      175,    "R/W",  0,      0,      0ull,   0ull},
8551         {"RESERVED_18_63"              ,        18,     46,     175,    "RAZ",  1,      1,      0,      0},
8552         {"CNT_VAL"                     ,        0,      25,     176,    "RO",   0,      1,      0ull,   0},
8553         {"RESERVED_25_63"              ,        25,     39,     176,    "RAZ",  1,      1,      0,      0},
8554         {"RADDR"                       ,        0,      3,      177,    "R/W",  0,      0,      0ull,   0ull},
8555         {"CENA"                        ,        3,      1,      177,    "R/W",  0,      0,      1ull,   1ull},
8556         {"PTR"                         ,        4,      29,     177,    "RO",   1,      1,      0,      0},
8557         {"PRADDR"                      ,        33,     3,      177,    "RO",   1,      1,      0,      0},
8558         {"MAX_PKT"                     ,        36,     3,      177,    "RO",   0,      0,      5ull,   5ull},
8559         {"RESERVED_39_63"              ,        39,     25,     177,    "RAZ",  1,      1,      0,      0},
8560         {"RADDR"                       ,        0,      7,      178,    "R/W",  0,      0,      0ull,   0ull},
8561         {"CENA"                        ,        7,      1,      178,    "R/W",  0,      0,      1ull,   1ull},
8562         {"PTR"                         ,        8,      29,     178,    "RO",   1,      1,      0,      0},
8563         {"MAX_PKT"                     ,        37,     7,      178,    "RO",   0,      0,      5ull,   5ull},
8564         {"RESERVED_44_63"              ,        44,     20,     178,    "RAZ",  1,      1,      0,      0},
8565         {"WQE_PCNT"                    ,        0,      7,      179,    "RO",   0,      0,      0ull,   0ull},
8566         {"PKT_PCNT"                    ,        7,      7,      179,    "RO",   0,      0,      0ull,   0ull},
8567         {"PFIF_CNT"                    ,        14,     3,      179,    "RO",   0,      0,      0ull,   0ull},
8568         {"WQEV_CNT"                    ,        17,     1,      179,    "RO",   0,      0,      0ull,   0ull},
8569         {"PKTV_CNT"                    ,        18,     1,      179,    "RO",   0,      0,      0ull,   0ull},
8570         {"RESERVED_19_63"              ,        19,     45,     179,    "RAZ",  1,      1,      0,      0},
8571         {"RADDR"                       ,        0,      8,      180,    "R/W",  0,      0,      0ull,   0ull},
8572         {"CENA"                        ,        8,      1,      180,    "R/W",  0,      0,      1ull,   1ull},
8573         {"PTR"                         ,        9,      29,     180,    "RO",   1,      1,      0,      0},
8574         {"PRADDR"                      ,        38,     8,      180,    "RO",   1,      1,      0,      0},
8575         {"WRADDR"                      ,        46,     8,      180,    "RO",   1,      1,      0,      0},
8576         {"MAX_CNTS"                    ,        54,     7,      180,    "RO",   0,      0,      8ull,   8ull},
8577         {"RESERVED_61_63"              ,        61,     3,      180,    "RAZ",  1,      1,      0,      0},
8578         {"PASS"                        ,        0,      32,     181,    "R/W",  0,      1,      0ull,   0},
8579         {"DROP"                        ,        32,     32,     181,    "R/W",  0,      1,      0ull,   0},
8580         {"Q0_PCNT"                     ,        0,      32,     182,    "RO",   0,      0,      0ull,   0ull},
8581         {"RESERVED_32_63"              ,        32,     32,     182,    "RAZ",  1,      1,      0,      0},
8582         {"PRT_ENB"                     ,        0,      36,     183,    "R/W",  0,      0,      0ull,   0ull},
8583         {"AVG_DLY"                     ,        36,     14,     183,    "R/W",  0,      1,      0ull,   0},
8584         {"PRB_DLY"                     ,        50,     14,     183,    "R/W",  0,      0,      0ull,   0ull},
8585         {"PRB_CON"                     ,        0,      32,     184,    "R/W",  0,      1,      0ull,   0},
8586         {"AVG_CON"                     ,        32,     8,      184,    "R/W",  0,      1,      0ull,   0},
8587         {"NEW_CON"                     ,        40,     8,      184,    "R/W",  0,      1,      0ull,   0},
8588         {"USE_PCNT"                    ,        48,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
8589         {"RESERVED_49_63"              ,        49,     15,     184,    "RAZ",  1,      1,      0,      0},
8590         {"PAGE_CNT"                    ,        0,      25,     185,    "R/W",  1,      0,      0,      0ull},
8591         {"PORT"                        ,        25,     6,      185,    "R/W",  1,      0,      0,      0ull},
8592         {"RESERVED_31_63"              ,        31,     33,     185,    "RAZ",  1,      1,      0,      0},
8593         {"PORT_BIT"                    ,        0,      3,      186,    "R/W",  0,      0,      7ull,   7ull},
8594         {"RESERVED_3_63"               ,        3,      61,     186,    "RAZ",  1,      1,      0,      0},
8595         {"WQE_POOL"                    ,        0,      3,      187,    "R/W",  0,      0,      1ull,   1ull},
8596         {"RESERVED_3_63"               ,        3,      61,     187,    "RAZ",  1,      1,      0,      0},
8597         {"PTR"                         ,        0,      29,     188,    "RO",   1,      1,      0,      0},
8598         {"RESERVED_29_63"              ,        29,     35,     188,    "RAZ",  1,      1,      0,      0},
8599         {"WLB_DAT"                     ,        0,      4,      189,    "RO",   0,      0,      0ull,   0ull},
8600         {"STIN_MSK"                    ,        4,      1,      189,    "RO",   0,      0,      0ull,   0ull},
8601         {"DT"                          ,        5,      1,      189,    "RO",   0,      0,      0ull,   0ull},
8602         {"DTCNT"                       ,        6,      10,     189,    "RO",   0,      0,      0ull,   0ull},
8603         {"RESERVED_16_18"              ,        16,     3,      189,    "RAZ",  0,      0,      0ull,   0ull},
8604         {"WLB_MSK"                     ,        19,     4,      189,    "RO",   0,      0,      0ull,   0ull},
8605         {"RESERVED_23_63"              ,        23,     41,     189,    "RAZ",  0,      0,      0ull,   0ull},
8606         {"L2T"                         ,        0,      5,      190,    "RO",   0,      0,      0ull,   0ull},
8607         {"RESERVED_5_8"                ,        5,      4,      190,    "RAZ",  0,      0,      0ull,   0ull},
8608         {"VAB_VWCF"                    ,        9,      1,      190,    "RO",   0,      0,      0ull,   0ull},
8609         {"LRF"                         ,        10,     2,      190,    "RO",   0,      0,      0ull,   0ull},
8610         {"VWDF"                        ,        12,     4,      190,    "RO",   0,      0,      0ull,   0ull},
8611         {"RESERVED_16_63"              ,        16,     48,     190,    "RAZ",  0,      0,      0ull,   0ull},
8612         {"XRDDAT"                      ,        0,      1,      191,    "RO",   0,      0,      0ull,   0ull},
8613         {"XRDMSK"                      ,        1,      1,      191,    "RO",   0,      0,      0ull,   0ull},
8614         {"RESERVED_2_2"                ,        2,      1,      191,    "RAZ",  0,      0,      0ull,   0ull},
8615         {"IPCBST"                      ,        3,      1,      191,    "RO",   0,      0,      0ull,   0ull},
8616         {"RESERVED_4_7"                ,        4,      4,      191,    "RAZ",  0,      0,      0ull,   0ull},
8617         {"RMDF"                        ,        8,      4,      191,    "RO",   0,      0,      0ull,   0ull},
8618         {"MRB"                         ,        12,     4,      191,    "RO",   0,      0,      0ull,   0ull},
8619         {"RESERVED_16_63"              ,        16,     48,     191,    "RAZ",  0,      0,      0ull,   0ull},
8620         {"LRF_ARB_MODE"                ,        0,      1,      192,    "R/W",  0,      0,      1ull,   1ull},
8621         {"RFB_ARB_MODE"                ,        1,      1,      192,    "R/W",  0,      0,      1ull,   1ull},
8622         {"RSP_ARB_MODE"                ,        2,      1,      192,    "R/W",  0,      0,      1ull,   1ull},
8623         {"MWF_CRD"                     ,        3,      4,      192,    "R/W",  0,      0,      2ull,   2ull},
8624         {"IDXALIAS"                    ,        7,      1,      192,    "R/W",  0,      0,      0ull,   1ull},
8625         {"FPEN"                        ,        8,      1,      192,    "R/W",  0,      0,      0ull,   0ull},
8626         {"FPEMPTY"                     ,        9,      1,      192,    "R/W",  0,      0,      0ull,   0ull},
8627         {"FPEXP"                       ,        10,     4,      192,    "R/W",  0,      0,      0ull,   0ull},
8628         {"RESERVED_14_63"              ,        14,     50,     192,    "RAZ",  1,      1,      0,      0},
8629         {"L2T"                         ,        0,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
8630         {"L2D"                         ,        1,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
8631         {"FINV"                        ,        2,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
8632         {"SET"                         ,        3,      2,      193,    "R/W",  0,      0,      0ull,   0ull},
8633         {"RESERVED_5_5"                ,        5,      1,      193,    "RAZ",  0,      0,      0ull,   0ull},
8634         {"PPNUM"                       ,        6,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
8635         {"RESERVED_7_9"                ,        7,      3,      193,    "RAZ",  0,      0,      0ull,   0ull},
8636         {"LFB_DMP"                     ,        10,     1,      193,    "R/W",  0,      0,      0ull,   0ull},
8637         {"LFB_ENUM"                    ,        11,     3,      193,    "R/W",  0,      0,      0ull,   0ull},
8638         {"RESERVED_14_63"              ,        14,     50,     193,    "RAZ",  0,      0,      0ull,   0ull},
8639         {"DT_TAG"                      ,        0,      29,     194,    "RO",   0,      0,      0ull,   0ull},
8640         {"DT_VLD"                      ,        29,     1,      194,    "RO",   0,      0,      0ull,   0ull},
8641         {"RESERVED_30_30"              ,        30,     1,      194,    "RAZ",  0,      0,      0ull,   0ull},
8642         {"DTENA"                       ,        31,     1,      194,    "R/W",  0,      0,      0ull,   0ull},
8643         {"RESERVED_32_63"              ,        32,     32,     194,    "RAZ",  0,      0,      0ull,   0ull},
8644         {"LCK_ENA"                     ,        0,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
8645         {"RESERVED_1_3"                ,        1,      3,      195,    "RAZ",  0,      0,      0ull,   0ull},
8646         {"LCK_BASE"                    ,        4,      27,     195,    "R/W",  0,      0,      0ull,   0ull},
8647         {"RESERVED_31_63"              ,        31,     33,     195,    "RAZ",  0,      0,      0ull,   0ull},
8648         {"LCK_OFFSET"                  ,        0,      10,     196,    "R/W",  0,      0,      0ull,   0ull},
8649         {"RESERVED_10_63"              ,        10,     54,     196,    "RAZ",  0,      0,      0ull,   0ull},
8650         {"VLD"                         ,        0,      1,      197,    "RO",   0,      0,      0ull,   0ull},
8651         {"CMD"                         ,        1,      4,      197,    "RO",   0,      0,      0ull,   0ull},
8652         {"SID"                         ,        5,      9,      197,    "RO",   0,      0,      0ull,   0ull},
8653         {"VABNUM"                      ,        14,     3,      197,    "RO",   0,      0,      0ull,   0ull},
8654         {"RESERVED_17_17"              ,        17,     1,      197,    "RAZ",  0,      0,      0ull,   0ull},
8655         {"SET"                         ,        18,     2,      197,    "RO",   0,      0,      0ull,   0ull},
8656         {"RESERVED_20_20"              ,        20,     1,      197,    "RAZ",  0,      0,      0ull,   0ull},
8657         {"IHD"                         ,        21,     1,      197,    "RO",   0,      0,      0ull,   0ull},
8658         {"ITL"                         ,        22,     1,      197,    "RO",   0,      0,      0ull,   0ull},
8659         {"INXT"                        ,        23,     3,      197,    "RO",   0,      0,      0ull,   0ull},
8660         {"RESERVED_26_26"              ,        26,     1,      197,    "RAZ",  0,      0,      0ull,   0ull},
8661         {"VAM"                         ,        27,     1,      197,    "RO",   0,      0,      0ull,   0ull},
8662         {"STCFL"                       ,        28,     1,      197,    "RO",   0,      0,      0ull,   0ull},
8663         {"STINV"                       ,        29,     1,      197,    "RO",   0,      0,      0ull,   0ull},
8664         {"STPND"                       ,        30,     1,      197,    "RO",   0,      0,      0ull,   0ull},
8665         {"STCPND"                      ,        31,     1,      197,    "RO",   0,      0,      0ull,   0ull},
8666         {"RESERVED_32_63"              ,        32,     32,     197,    "RAZ",  0,      0,      0ull,   0ull},
8667         {"VLD"                         ,        0,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8668         {"WTPRB"                       ,        1,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8669         {"PRBRTY"                      ,        2,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8670         {"WTMFL"                       ,        3,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8671         {"WTVTM"                       ,        4,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8672         {"WTSTRSC"                     ,        5,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8673         {"WTSTRSP"                     ,        6,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8674         {"WTSTDT"                      ,        7,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8675         {"WTRDA"                       ,        8,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8676         {"WTSTM"                       ,        9,      1,      198,    "RO",   0,      0,      0ull,   0ull},
8677         {"WTWRM"                       ,        10,     1,      198,    "RO",   0,      0,      0ull,   0ull},
8678         {"WTWHF"                       ,        11,     1,      198,    "RO",   0,      0,      0ull,   0ull},
8679         {"WTWHP"                       ,        12,     1,      198,    "RO",   0,      0,      0ull,   0ull},
8680         {"WTDQ"                        ,        13,     1,      198,    "RO",   0,      0,      0ull,   0ull},
8681         {"WTDW"                        ,        14,     1,      198,    "RO",   0,      0,      0ull,   0ull},
8682         {"WTRSP"                       ,        15,     1,      198,    "RO",   0,      0,      0ull,   0ull},
8683         {"BID"                         ,        16,     2,      198,    "RO",   0,      0,      0ull,   0ull},
8684         {"DSGOING"                     ,        18,     1,      198,    "RO",   0,      0,      0ull,   0ull},
8685         {"RESERVED_19_63"              ,        19,     45,     198,    "RAZ",  0,      0,      0ull,   0ull},
8686         {"LFB_IDX"                     ,        0,      10,     199,    "RO",   0,      0,      0ull,   0ull},
8687         {"LFB_TAG"                     ,        10,     17,     199,    "RO",   0,      0,      0ull,   0ull},
8688         {"RESERVED_27_63"              ,        27,     37,     199,    "RAZ",  0,      0,      0ull,   0ull},
8689         {"LFB_HWM"                     ,        0,      3,      200,    "R/W",  0,      0,      7ull,   7ull},
8690         {"RESERVED_3_3"                ,        3,      1,      200,    "RAZ",  0,      0,      0ull,   0ull},
8691         {"STPARTDIS"                   ,        4,      1,      200,    "R/W",  0,      0,      0ull,   0ull},
8692         {"RESERVED_5_63"               ,        5,      59,     200,    "RAZ",  0,      0,      0ull,   0ull},
8693         {"PFCNT0"                      ,        0,      36,     201,    "RO",   0,      0,      0ull,   0ull},
8694         {"RESERVED_36_63"              ,        36,     28,     201,    "RAZ",  0,      0,      0ull,   0ull},
8695         {"CNT0SEL"                     ,        0,      6,      202,    "R/W",  0,      0,      0ull,   0ull},
8696         {"CNT0CLR"                     ,        6,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
8697         {"CNT0ENA"                     ,        7,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
8698         {"CNT1SEL"                     ,        8,      6,      202,    "R/W",  0,      0,      0ull,   0ull},
8699         {"CNT1CLR"                     ,        14,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8700         {"CNT1ENA"                     ,        15,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8701         {"CNT2SEL"                     ,        16,     6,      202,    "R/W",  0,      0,      0ull,   0ull},
8702         {"CNT2CLR"                     ,        22,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8703         {"CNT2ENA"                     ,        23,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8704         {"CNT3SEL"                     ,        24,     6,      202,    "R/W",  0,      0,      0ull,   0ull},
8705         {"CNT3CLR"                     ,        30,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8706         {"CNT3ENA"                     ,        31,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8707         {"CNT0RDCLR"                   ,        32,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8708         {"CNT1RDCLR"                   ,        33,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8709         {"CNT2RDCLR"                   ,        34,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8710         {"CNT3RDCLR"                   ,        35,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
8711         {"RESERVED_36_63"              ,        36,     28,     202,    "RAZ",  0,      0,      0ull,   0ull},
8712         {"UMSK0"                       ,        0,      4,      203,    "R/W",  0,      0,      0ull,   0ull},
8713         {"RESERVED_4_7"                ,        4,      4,      203,    "RAZ",  0,      0,      0ull,   0ull},
8714         {"UMSK1"                       ,        8,      4,      203,    "R/W",  0,      0,      0ull,   0ull},
8715         {"RESERVED_12_63"              ,        12,     52,     203,    "RAZ",  0,      0,      0ull,   0ull},
8716         {"UMSKIOB"                     ,        0,      4,      204,    "R/W",  0,      0,      0ull,   0ull},
8717         {"RESERVED_4_63"               ,        4,      60,     204,    "RAZ",  0,      0,      0ull,   0ull},
8718         {"Q0STAT"                      ,        0,      34,     205,    "RO",   0,      0,      0ull,   0ull},
8719         {"FTL"                         ,        34,     1,      205,    "RO",   0,      0,      0ull,   0ull},
8720         {"RESERVED_35_63"              ,        35,     29,     205,    "RAZ",  0,      0,      0ull,   0ull},
8721         {"Q1STAT"                      ,        0,      34,     206,    "RO",   0,      0,      0ull,   0ull},
8722         {"RESERVED_34_63"              ,        34,     30,     206,    "RAZ",  0,      0,      0ull,   0ull},
8723         {"Q2STAT"                      ,        0,      34,     207,    "RO",   0,      0,      0ull,   0ull},
8724         {"RESERVED_34_63"              ,        34,     30,     207,    "RAZ",  0,      0,      0ull,   0ull},
8725         {"Q3STAT"                      ,        0,      34,     208,    "RO",   0,      0,      0ull,   0ull},
8726         {"RESERVED_34_63"              ,        34,     30,     208,    "RAZ",  0,      0,      0ull,   0ull},
8727         {"ECC_ENA"                     ,        0,      1,      209,    "R/W",  0,      0,      0ull,   1ull},
8728         {"SEC_INTENA"                  ,        1,      1,      209,    "R/W",  0,      0,      0ull,   1ull},
8729         {"DED_INTENA"                  ,        2,      1,      209,    "R/W",  0,      0,      0ull,   1ull},
8730         {"SEC_ERR"                     ,        3,      1,      209,    "R/W1C",        0,      0,      0ull,   0ull},
8731         {"DED_ERR"                     ,        4,      1,      209,    "R/W1C",        0,      0,      0ull,   0ull},
8732         {"BMHCLSEL"                    ,        5,      1,      209,    "R/W",  0,      0,      0ull,   0ull},
8733         {"RESERVED_6_63"               ,        6,      58,     209,    "RAZ",  0,      0,      0ull,   0ull},
8734         {"FADR"                        ,        0,      10,     210,    "RO",   0,      0,      0ull,   0ull},
8735         {"RESERVED_10_10"              ,        10,     1,      210,    "RAZ",  0,      0,      0ull,   0ull},
8736         {"FSET"                        ,        11,     2,      210,    "RO",   0,      0,      0ull,   0ull},
8737         {"RESERVED_13_13"              ,        13,     1,      210,    "RAZ",  0,      0,      0ull,   0ull},
8738         {"FOWMSK"                      ,        14,     4,      210,    "RO",   0,      0,      0ull,   0ull},
8739         {"RESERVED_18_63"              ,        18,     46,     210,    "RAZ",  0,      0,      0ull,   0ull},
8740         {"FSYN_OW0"                    ,        0,      10,     211,    "RO",   0,      0,      0ull,   0ull},
8741         {"FSYN_OW1"                    ,        10,     10,     211,    "RO",   0,      0,      0ull,   0ull},
8742         {"RESERVED_20_63"              ,        20,     44,     211,    "RAZ",  0,      0,      0ull,   0ull},
8743         {"FSYN_OW2"                    ,        0,      10,     212,    "RO",   0,      0,      0ull,   0ull},
8744         {"FSYN_OW3"                    ,        10,     10,     212,    "RO",   0,      0,      0ull,   0ull},
8745         {"RESERVED_20_63"              ,        20,     44,     212,    "RAZ",  0,      0,      0ull,   0ull},
8746         {"Q0FUS"                       ,        0,      34,     213,    "RO",   0,      0,      0ull,   0ull},
8747         {"RESERVED_34_63"              ,        34,     30,     213,    "RAZ",  0,      0,      0ull,   0ull},
8748         {"Q1FUS"                       ,        0,      34,     214,    "RO",   0,      0,      0ull,   0ull},
8749         {"RESERVED_34_63"              ,        34,     30,     214,    "RAZ",  0,      0,      0ull,   0ull},
8750         {"Q2FUS"                       ,        0,      34,     215,    "RO",   0,      0,      0ull,   0ull},
8751         {"RESERVED_34_63"              ,        34,     30,     215,    "RAZ",  0,      0,      0ull,   0ull},
8752         {"Q3FUS"                       ,        0,      34,     216,    "RO",   0,      0,      0ull,   0ull},
8753         {"CRIP_128K"                   ,        34,     1,      216,    "RO",   0,      0,      0ull,   0ull},
8754         {"RESERVED_35_63"              ,        35,     29,     216,    "RAZ",  0,      0,      0ull,   0ull},
8755         {"ECC_ENA"                     ,        0,      1,      217,    "R/W",  0,      0,      0ull,   1ull},
8756         {"SEC_INTENA"                  ,        1,      1,      217,    "R/W",  0,      0,      0ull,   1ull},
8757         {"DED_INTENA"                  ,        2,      1,      217,    "R/W",  0,      0,      0ull,   1ull},
8758         {"SEC_ERR"                     ,        3,      1,      217,    "R/W1C",        0,      0,      0ull,   0ull},
8759         {"DED_ERR"                     ,        4,      1,      217,    "R/W1C",        0,      0,      0ull,   0ull},
8760         {"FSYN"                        ,        5,      6,      217,    "RO",   0,      0,      0ull,   0ull},
8761         {"FADR"                        ,        11,     9,      217,    "RO",   0,      0,      0ull,   0ull},
8762         {"RESERVED_20_20"              ,        20,     1,      217,    "RAZ",  0,      0,      0ull,   0ull},
8763         {"FSET"                        ,        21,     2,      217,    "RO",   0,      0,      0ull,   0ull},
8764         {"RESERVED_23_23"              ,        23,     1,      217,    "RAZ",  0,      0,      0ull,   0ull},
8765         {"LCKERR"                      ,        24,     1,      217,    "R/W1C",        0,      0,      0ull,   0ull},
8766         {"LCK_INTENA"                  ,        25,     1,      217,    "R/W",  0,      0,      0ull,   1ull},
8767         {"LCKERR2"                     ,        26,     1,      217,    "R/W1C",        0,      0,      0ull,   0ull},
8768         {"LCK_INTENA2"                 ,        27,     1,      217,    "R/W",  0,      0,      0ull,   1ull},
8769         {"RESERVED_28_63"              ,        28,     36,     217,    "RAZ",  0,      0,      0ull,   0ull},
8770         {"PCTL_DAT"                    ,        0,      4,      218,    "R/W",  0,      1,      0ull,   0},
8771         {"PCTL_CMD"                    ,        4,      4,      218,    "R/W",  0,      1,      0ull,   0},
8772         {"PCTL_CLK"                    ,        8,      4,      218,    "R/W",  0,      1,      0ull,   0},
8773         {"PCTL_CSR"                    ,        12,     4,      218,    "R/W",  0,      1,      15ull,  0},
8774         {"NCTL_DAT"                    ,        16,     4,      218,    "R/W",  0,      1,      0ull,   0},
8775         {"NCTL_CMD"                    ,        20,     4,      218,    "R/W",  0,      1,      0ull,   0},
8776         {"NCTL_CLK"                    ,        24,     4,      218,    "R/W",  0,      1,      0ull,   0},
8777         {"NCTL_CSR"                    ,        28,     4,      218,    "R/W",  0,      1,      15ull,  0},
8778         {"RESERVED_32_63"              ,        32,     32,     218,    "RAZ",  0,      0,      0ull,   0ull},
8779         {"DIC"                         ,        0,      2,      219,    "R/W",  0,      0,      0ull,   0ull},
8780         {"QS_DIC"                      ,        2,      2,      219,    "R/W",  0,      0,      2ull,   2ull},
8781         {"TSKW"                        ,        4,      2,      219,    "R/W",  0,      0,      0ull,   1ull},
8782         {"SIL_LAT"                     ,        6,      2,      219,    "R/W",  0,      0,      1ull,   1ull},
8783         {"BPRCH"                       ,        8,      1,      219,    "R/W",  0,      1,      0ull,   0},
8784         {"FPRCH2"                      ,        9,      1,      219,    "R/W",  0,      0,      0ull,   1ull},
8785         {"MODE32B"                     ,        10,     1,      219,    "R/W",  0,      0,      0ull,   0ull},
8786         {"DRESET"                      ,        11,     1,      219,    "R/W",  0,      0,      1ull,   0ull},
8787         {"INORDER_MRF"                 ,        12,     1,      219,    "R/W",  0,      0,      0ull,   0ull},
8788         {"INORDER_MWF"                 ,        13,     1,      219,    "RAZ",  0,      0,      0ull,   0ull},
8789         {"R2R_SLOT"                    ,        14,     1,      219,    "R/W",  0,      0,      0ull,   0ull},
8790         {"RDIMM_ENA"                   ,        15,     1,      219,    "R/W",  0,      1,      0ull,   0},
8791         {"PLL_BYPASS"                  ,        16,     1,      219,    "R/W",  0,      0,      1ull,   1ull},
8792         {"PLL_DIV2"                    ,        17,     1,      219,    "R/W",  0,      0,      0ull,   0ull},
8793         {"MAX_WRITE_BATCH"             ,        18,     4,      219,    "R/W",  0,      0,      8ull,   8ull},
8794         {"XOR_BANK"                    ,        22,     1,      219,    "R/W",  0,      0,      0ull,   1ull},
8795         {"SLOW_SCF"                    ,        23,     1,      219,    "R/W",  0,      0,      0ull,   0ull},
8796         {"DDR__PCTL"                   ,        24,     4,      219,    "RO",   1,      1,      0,      0},
8797         {"DDR__NCTL"                   ,        28,     4,      219,    "RO",   1,      1,      0,      0},
8798         {"RESERVED_32_63"              ,        32,     32,     219,    "RAZ",  1,      1,      0,      0},
8799         {"DCLKCNT_HI"                  ,        0,      32,     220,    "RO",   0,      0,      0ull,   0ull},
8800         {"RESERVED_32_63"              ,        32,     32,     220,    "RAZ",  1,      1,      0,      0},
8801         {"DCLKCNT_LO"                  ,        0,      32,     221,    "RO",   0,      0,      0ull,   0ull},
8802         {"RESERVED_32_63"              ,        32,     32,     221,    "RAZ",  1,      1,      0,      0},
8803         {"DDR2"                        ,        0,      1,      222,    "R/W",  0,      0,      1ull,   1ull},
8804         {"RESERVED_1_1"                ,        1,      1,      222,    "RAZ",  0,      0,      0ull,   0ull},
8805         {"DLL90_BYP"                   ,        2,      1,      222,    "R/W",  0,      0,      0ull,   0ull},
8806         {"DLL90_VLU"                   ,        3,      5,      222,    "R/W",  0,      1,      0ull,   0},
8807         {"QDLL_ENA"                    ,        8,      1,      222,    "R/W",  0,      0,      0ull,   0ull},
8808         {"ODT_ENA"                     ,        9,      1,      222,    "R/W",  0,      0,      0ull,   0ull},
8809         {"DDR2T"                       ,        10,     1,      222,    "R/W",  0,      1,      0ull,   0},
8810         {"CRIP_MODE"                   ,        11,     1,      222,    "R/W",  0,      0,      0ull,   0ull},
8811         {"TFAW"                        ,        12,     5,      222,    "R/W",  0,      0,      0ull,   9ull},
8812         {"DDR_EOF"                     ,        17,     4,      222,    "R/W",  0,      0,      2ull,   2ull},
8813         {"SILO_HC"                     ,        21,     1,      222,    "R/W",  0,      1,      1ull,   0},
8814         {"TWR"                         ,        22,     3,      222,    "R/W",  0,      0,      3ull,   1ull},
8815         {"BWCNT"                       ,        25,     1,      222,    "R/W",  0,      0,      0ull,   0ull},
8816         {"POCAS"                       ,        26,     1,      222,    "R/W",  0,      0,      0ull,   0ull},
8817         {"ADDLAT"                      ,        27,     3,      222,    "R/W",  0,      0,      0ull,   0ull},
8818         {"BURST8"                      ,        30,     1,      222,    "R/W",  0,      0,      0ull,   1ull},
8819         {"BANK8"                       ,        31,     1,      222,    "R/W",  0,      1,      0ull,   0},
8820         {"RESERVED_32_63"              ,        32,     32,     222,    "RAZ",  0,      0,      0ull,   0ull},
8821         {"MRDSYN0"                     ,        0,      8,      223,    "RO",   0,      0,      0ull,   0ull},
8822         {"MRDSYN1"                     ,        8,      8,      223,    "RO",   0,      0,      0ull,   0ull},
8823         {"MRDSYN2"                     ,        16,     8,      223,    "RO",   0,      0,      0ull,   0ull},
8824         {"MRDSYN3"                     ,        24,     8,      223,    "RO",   0,      0,      0ull,   0ull},
8825         {"RESERVED_32_63"              ,        32,     32,     223,    "RAZ",  1,      1,      0,      0},
8826         {"FCOL"                        ,        0,      12,     224,    "RO",   0,      0,      0ull,   0ull},
8827         {"FROW"                        ,        12,     14,     224,    "RO",   0,      0,      0ull,   0ull},
8828         {"FBANK"                       ,        26,     3,      224,    "RO",   0,      0,      0ull,   0ull},
8829         {"FBUNK"                       ,        29,     1,      224,    "RO",   0,      0,      0ull,   0ull},
8830         {"FDIMM"                       ,        30,     2,      224,    "RO",   0,      0,      0ull,   0ull},
8831         {"RESERVED_32_63"              ,        32,     32,     224,    "RAZ",  1,      1,      0,      0},
8832         {"IFBCNT_HI"                   ,        0,      32,     225,    "RO",   0,      0,      0ull,   0ull},
8833         {"RESERVED_32_63"              ,        32,     32,     225,    "RAZ",  1,      1,      0,      0},
8834         {"IFBCNT_LO"                   ,        0,      32,     226,    "RO",   0,      0,      0ull,   0ull},
8835         {"RESERVED_32_63"              ,        32,     32,     226,    "RAZ",  1,      1,      0,      0},
8836         {"INIT_START"                  ,        0,      1,      227,    "R/W",  0,      0,      0ull,   0ull},
8837         {"ECC_ENA"                     ,        1,      1,      227,    "R/W",  0,      0,      0ull,   1ull},
8838         {"ROW_LSB"                     ,        2,      3,      227,    "R/W",  0,      1,      3ull,   0},
8839         {"PBANK_LSB"                   ,        5,      4,      227,    "R/W",  0,      1,      5ull,   0},
8840         {"REF_INT"                     ,        9,      6,      227,    "R/W",  0,      0,      1ull,   2ull},
8841         {"TCL"                         ,        15,     4,      227,    "R/W",  0,      1,      3ull,   0},
8842         {"INTR_SEC_ENA"                ,        19,     1,      227,    "R/W",  0,      0,      0ull,   1ull},
8843         {"INTR_DED_ENA"                ,        20,     1,      227,    "R/W",  0,      0,      0ull,   1ull},
8844         {"SEC_ERR"                     ,        21,     4,      227,    "R/W1C",        0,      0,      0ull,   0ull},
8845         {"DED_ERR"                     ,        25,     4,      227,    "R/W1C",        0,      0,      0ull,   0ull},
8846         {"BUNK_ENA"                    ,        29,     1,      227,    "R/W",  0,      1,      0ull,   0},
8847         {"SILO_QC"                     ,        30,     1,      227,    "R/W",  0,      1,      0ull,   0},
8848         {"RESET"                       ,        31,     1,      227,    "RAZ",  1,      1,      0,      0},
8849         {"RESERVED_32_63"              ,        32,     32,     227,    "RAZ",  1,      1,      0,      0},
8850         {"TRAS"                        ,        0,      5,      228,    "R/W",  0,      0,      12ull,  12ull},
8851         {"TRCD"                        ,        5,      4,      228,    "R/W",  0,      0,      4ull,   4ull},
8852         {"TWTR"                        ,        9,      4,      228,    "R/W",  0,      0,      2ull,   2ull},
8853         {"TRP"                         ,        13,     4,      228,    "R/W",  0,      0,      5ull,   4ull},
8854         {"TRFC"                        ,        17,     5,      228,    "R/W",  0,      0,      6ull,   7ull},
8855         {"TMRD"                        ,        22,     3,      228,    "R/W",  0,      0,      2ull,   2ull},
8856         {"CASLAT"                      ,        25,     3,      228,    "R/W",  0,      0,      4ull,   4ull},
8857         {"TRRD"                        ,        28,     3,      228,    "R/W",  0,      0,      2ull,   2ull},
8858         {"COMP_BYPASS"                 ,        31,     1,      228,    "R/W",  0,      0,      0ull,   0ull},
8859         {"RESERVED_32_63"              ,        32,     32,     228,    "RAZ",  1,      1,      0,      0},
8860         {"OPSCNT_HI"                   ,        0,      32,     229,    "RO",   0,      0,      0ull,   0ull},
8861         {"RESERVED_32_63"              ,        32,     32,     229,    "RAZ",  1,      1,      0,      0},
8862         {"OPSCNT_LO"                   ,        0,      32,     230,    "RO",   0,      0,      0ull,   0ull},
8863         {"RESERVED_32_63"              ,        32,     32,     230,    "RAZ",  1,      1,      0,      0},
8864         {"BWCTL"                       ,        0,      4,      231,    "R/W",  0,      0,      0ull,   0ull},
8865         {"BWUPD"                       ,        4,      1,      231,    "R/W",  0,      0,      0ull,   0ull},
8866         {"RESERVED_5_63"               ,        5,      59,     231,    "RAZ",  1,      1,      0,      0},
8867         {"RODT_LO0"                    ,        0,      4,      232,    "R/W",  0,      0,      15ull,  15ull},
8868         {"RODT_LO1"                    ,        4,      4,      232,    "R/W",  0,      0,      15ull,  15ull},
8869         {"RODT_LO2"                    ,        8,      4,      232,    "R/W",  0,      0,      15ull,  15ull},
8870         {"RODT_LO3"                    ,        12,     4,      232,    "R/W",  0,      0,      15ull,  15ull},
8871         {"RODT_HI0"                    ,        16,     4,      232,    "R/W",  0,      0,      15ull,  15ull},
8872         {"RODT_HI1"                    ,        20,     4,      232,    "R/W",  0,      0,      15ull,  15ull},
8873         {"RODT_HI2"                    ,        24,     4,      232,    "R/W",  0,      0,      15ull,  15ull},
8874         {"RODT_HI3"                    ,        28,     4,      232,    "R/W",  0,      0,      15ull,  15ull},
8875         {"RESERVED_32_63"              ,        32,     32,     232,    "RAZ",  1,      1,      0,      0},
8876         {"WODT_D0_R0"                  ,        0,      8,      233,    "R/W",  0,      0,      255ull, 255ull},
8877         {"WODT_D0_R1"                  ,        8,      8,      233,    "R/W",  0,      0,      255ull, 255ull},
8878         {"WODT_D1_R0"                  ,        16,     8,      233,    "R/W",  0,      0,      255ull, 255ull},
8879         {"WODT_D1_R1"                  ,        24,     8,      233,    "R/W",  0,      0,      255ull, 255ull},
8880         {"RESERVED_32_63"              ,        32,     32,     233,    "RAZ",  0,      0,      0ull,   0ull},
8881         {"WODT_D2_R0"                  ,        0,      8,      234,    "R/W",  0,      0,      255ull, 255ull},
8882         {"WODT_D2_R1"                  ,        8,      8,      234,    "R/W",  0,      0,      255ull, 255ull},
8883         {"WODT_D3_R0"                  ,        16,     8,      234,    "R/W",  0,      0,      255ull, 255ull},
8884         {"WODT_D3_R1"                  ,        24,     8,      234,    "R/W",  0,      0,      255ull, 255ull},
8885         {"RESERVED_32_63"              ,        32,     32,     234,    "RAZ",  0,      0,      0ull,   0ull},
8886         {"NCBI"                        ,        0,      1,      235,    "RO",   0,      0,      0ull,   0ull},
8887         {"LOC"                         ,        1,      1,      235,    "RO",   0,      0,      0ull,   0ull},
8888         {"NCBO_0"                      ,        2,      1,      235,    "RO",   0,      0,      0ull,   0ull},
8889         {"NCBO_1"                      ,        3,      1,      235,    "RO",   0,      0,      0ull,   0ull},
8890         {"RESERVED_4_63"               ,        4,      60,     235,    "RAZ",  1,      1,      0,      0},
8891         {"ADR_ERR"                     ,        0,      1,      236,    "R/W1C",        0,      0,      0ull,   0ull},
8892         {"WAIT_ERR"                    ,        1,      1,      236,    "R/W1C",        0,      0,      0ull,   0ull},
8893         {"RESERVED_2_63"               ,        2,      62,     236,    "RAZ",  1,      1,      0,      0},
8894         {"ADR_INT"                     ,        0,      1,      237,    "R/W",  0,      1,      0ull,   0},
8895         {"WAIT_INT"                    ,        1,      1,      237,    "R/W",  0,      1,      0ull,   0},
8896         {"RESERVED_2_63"               ,        2,      62,     237,    "RAZ",  1,      1,      0,      0},
8897         {"RESERVED_0_2"                ,        0,      3,      238,    "RAZ",  1,      1,      0,      0},
8898         {"ADR"                         ,        3,      5,      238,    "R/W",  0,      1,      0ull,   0},
8899         {"RESERVED_8_63"               ,        8,      56,     238,    "RAZ",  1,      1,      0,      0},
8900         {"RESERVED_0_2"                ,        0,      3,      239,    "RAZ",  1,      1,      0,      0},
8901         {"BASE"                        ,        3,      25,     239,    "R/W",  0,      1,      0ull,   0},
8902         {"RESERVED_28_30"              ,        28,     3,      239,    "RAZ",  1,      1,      0,      0},
8903         {"EN"                          ,        31,     1,      239,    "R/W",  0,      1,      0ull,   0},
8904         {"RESERVED_32_63"              ,        32,     32,     239,    "RAZ",  1,      1,      0,      0},
8905         {"DATA"                        ,        0,      64,     240,    "R/W",  1,      1,      0,      0},
8906         {"BASE"                        ,        0,      16,     241,    "R/W",  0,      1,      0ull,   0},
8907         {"SIZE"                        ,        16,     12,     241,    "R/W",  0,      1,      0ull,   0},
8908         {"WIDTH"                       ,        28,     1,      241,    "R/W",  0,      1,      0ull,   0},
8909         {"ALE"                         ,        29,     1,      241,    "R/W",  0,      1,      0ull,   0},
8910         {"ORBIT"                       ,        30,     1,      241,    "R/W",  0,      1,      0ull,   0},
8911         {"EN"                          ,        31,     1,      241,    "R/W",  0,      1,      0ull,   0},
8912         {"OE_EXT"                      ,        32,     2,      241,    "R/W",  0,      1,      0ull,   0},
8913         {"WE_EXT"                      ,        34,     2,      241,    "R/W",  0,      1,      0ull,   0},
8914         {"SAM"                         ,        36,     1,      241,    "R/W",  0,      1,      0ull,   0},
8915         {"RESERVED_37_63"              ,        37,     27,     241,    "RAZ",  1,      1,      0,      0},
8916         {"ADR"                         ,        0,      6,      242,    "R/W",  0,      1,      63ull,  0},
8917         {"CE"                          ,        6,      6,      242,    "R/W",  0,      1,      63ull,  0},
8918         {"OE"                          ,        12,     6,      242,    "R/W",  0,      1,      63ull,  0},
8919         {"WE"                          ,        18,     6,      242,    "R/W",  0,      1,      63ull,  0},
8920         {"RD_HLD"                      ,        24,     6,      242,    "R/W",  0,      1,      63ull,  0},
8921         {"WR_HLD"                      ,        30,     6,      242,    "R/W",  0,      1,      63ull,  0},
8922         {"PAUSE"                       ,        36,     6,      242,    "R/W",  0,      1,      63ull,  0},
8923         {"WAIT"                        ,        42,     6,      242,    "R/W",  0,      1,      63ull,  0},
8924         {"PAGE"                        ,        48,     6,      242,    "R/W",  0,      1,      63ull,  0},
8925         {"ALE"                         ,        54,     6,      242,    "R/W",  0,      1,      63ull,  0},
8926         {"PAGES"                       ,        60,     2,      242,    "R/W",  0,      1,      0ull,   0},
8927         {"WAITM"                       ,        62,     1,      242,    "R/W",  0,      1,      0ull,   0},
8928         {"PAGEM"                       ,        63,     1,      242,    "R/W",  0,      1,      0ull,   0},
8929         {"FIF_THR"                     ,        0,      6,      243,    "R/W",  0,      0,      26ull,  26ull},
8930         {"RESERVED_6_7"                ,        6,      2,      243,    "RAZ",  1,      1,      0,      0},
8931         {"FIF_CNT"                     ,        8,      6,      243,    "RO",   0,      1,      0ull,   0},
8932         {"RESERVED_14_63"              ,        14,     50,     243,    "RAZ",  1,      1,      0,      0},
8933         {"MAN_INFO"                    ,        0,      32,     244,    "RO",   1,      1,      0,      0},
8934         {"RESERVED_32_63"              ,        32,     32,     244,    "RAZ",  1,      1,      0,      0},
8935         {"MAN_INFO"                    ,        0,      32,     245,    "RO",   1,      1,      0,      0},
8936         {"RESERVED_32_63"              ,        32,     32,     245,    "RAZ",  1,      1,      0,      0},
8937         {"PP_DIS"                      ,        0,      2,      246,    "RO",   1,      1,      0,      0},
8938         {"RESERVED_2_11"               ,        2,      10,     246,    "RAZ",  1,      1,      0,      0},
8939         {"PLL_OFF"                     ,        12,     4,      246,    "RO",   1,      1,      0,      0},
8940         {"CHIP_ID"                     ,        16,     8,      246,    "RO",   1,      1,      0,      0},
8941         {"BIST_DIS"                    ,        24,     1,      246,    "RO",   1,      1,      0,      0},
8942         {"RST_SHT"                     ,        25,     1,      246,    "RO",   1,      1,      0,      0},
8943         {"NOCRYPTO"                    ,        26,     1,      246,    "RO",   1,      1,      0,      0},
8944         {"NOMUL"                       ,        27,     1,      246,    "RO",   1,      1,      0,      0},
8945         {"NODFA_CP2"                   ,        28,     1,      246,    "RO",   1,      1,      0,      0},
8946         {"RESERVED_29_63"              ,        29,     35,     246,    "RAZ",  1,      1,      0,      0},
8947         {"ICACHE"                      ,        0,      24,     247,    "RO",   1,      1,      0,      0},
8948         {"NODFA_DTE"                   ,        24,     1,      247,    "RO",   1,      1,      0,      0},
8949         {"NOZIP"                       ,        25,     1,      247,    "RO",   1,      1,      0,      0},
8950         {"EFUS_IGN"                    ,        26,     1,      247,    "RO",   1,      1,      0,      0},
8951         {"EFUS_LCK"                    ,        27,     1,      247,    "RO",   1,      1,      0,      0},
8952         {"BAR2_EN"                     ,        28,     1,      247,    "RO",   1,      1,      0,      0},
8953         {"ZIP_CRIP"                    ,        29,     2,      247,    "RO",   1,      1,      0,      0},
8954         {"PLL_DIV4"                    ,        31,     1,      247,    "RO",   1,      1,      0,      0},
8955         {"RESERVED_32_63"              ,        32,     32,     247,    "RAZ",  1,      1,      0,      0},
8956         {"PROG"                        ,        0,      1,      248,    "R/W",  1,      1,      0,      0},
8957         {"RESERVED_1_63"               ,        1,      63,     248,    "RAZ",  1,      1,      0,      0},
8958         {"ADDR"                        ,        0,      7,      249,    "R/W",  0,      0,      0ull,   0ull},
8959         {"RESERVED_7_7"                ,        7,      1,      249,    "RAZ",  1,      1,      0,      0},
8960         {"EFUSE"                       ,        8,      1,      249,    "R/W",  0,      0,      0ull,   0ull},
8961         {"RESERVED_9_11"               ,        9,      3,      249,    "RAZ",  1,      1,      0,      0},
8962         {"PEND"                        ,        12,     1,      249,    "R/W",  0,      0,      0ull,   0ull},
8963         {"RESERVED_13_15"              ,        13,     3,      249,    "RAZ",  1,      1,      0,      0},
8964         {"DAT"                         ,        16,     8,      249,    "RO",   1,      1,      0,      0},
8965         {"RESERVED_24_63"              ,        24,     40,     249,    "RAZ",  1,      1,      0,      0},
8966         {"REPAIR0"                     ,        0,      14,     250,    "RO",   0,      0,      0ull,   0ull},
8967         {"REPAIR1"                     ,        14,     14,     250,    "RO",   0,      0,      0ull,   0ull},
8968         {"REPAIR2"                     ,        28,     14,     250,    "RO",   0,      0,      0ull,   0ull},
8969         {"RESERVED_42_63"              ,        42,     22,     250,    "RAZ",  1,      1,      0,      0},
8970         {"TOO_MANY"                    ,        0,      1,      251,    "RO",   0,      0,      0ull,   0ull},
8971         {"RESERVED_1_63"               ,        1,      63,     251,    "RAZ",  1,      1,      0,      0},
8972         {"KEY"                         ,        0,      24,     252,    "R/W",  0,      0,      0ull,   5071723ull},
8973         {"RESERVED_24_63"              ,        24,     40,     252,    "RAZ",  1,      1,      0,      0},
8974         {"ADDR"                        ,        0,      10,     253,    "R/W",  1,      1,      0,      0},
8975         {"RESERVED_10_63"              ,        10,     54,     253,    "RAZ",  1,      1,      0,      0},
8976         {"BW_CTL"                      ,        0,      5,      254,    "R/W",  0,      1,      0ull,   0},
8977         {"RESERVED_5_63"               ,        5,      59,     254,    "RAZ",  0,      0,      0ull,   0ull},
8978         {"SETTING"                     ,        0,      17,     255,    "RO",   1,      1,      0,      0},
8979         {"RESERVED_17_63"              ,        17,     47,     255,    "RAZ",  0,      0,      0ull,   0ull},
8980         {"ST_INT"                      ,        0,      1,      256,    "R/W1C",        0,      1,      0ull,   0},
8981         {"TS_INT"                      ,        1,      1,      256,    "R/W1C",        0,      1,      0ull,   0},
8982         {"CORE_INT"                    ,        2,      1,      256,    "RO",   0,      1,      0ull,   0},
8983         {"RESERVED_3_3"                ,        3,      1,      256,    "RAZ",  1,      1,      0,      0},
8984         {"ST_EN"                       ,        4,      1,      256,    "R/W",  0,      1,      0ull,   0},
8985         {"TS_EN"                       ,        5,      1,      256,    "R/W",  0,      1,      0ull,   0},
8986         {"CORE_EN"                     ,        6,      1,      256,    "R/W",  0,      1,      0ull,   0},
8987         {"RESERVED_7_7"                ,        7,      1,      256,    "RAZ",  1,      1,      0,      0},
8988         {"SDA_OVR"                     ,        8,      1,      256,    "R/W",  0,      1,      0ull,   0},
8989         {"SCL_OVR"                     ,        9,      1,      256,    "R/W",  0,      1,      0ull,   0},
8990         {"SDA"                         ,        10,     1,      256,    "RO",   1,      1,      0,      0},
8991         {"SCL"                         ,        11,     1,      256,    "RO",   1,      1,      0,      0},
8992         {"RESERVED_12_63"              ,        12,     52,     256,    "RAZ",  1,      1,      0,      0},
8993         {"D"                           ,        0,      32,     257,    "R/W",  0,      1,      0ull,   0},
8994         {"EOP_IA"                      ,        32,     3,      257,    "R/W",  0,      1,      0ull,   0},
8995         {"IA"                          ,        35,     5,      257,    "R/W",  0,      1,      0ull,   0},
8996         {"A"                           ,        40,     10,     257,    "R/W",  0,      1,      0ull,   0},
8997         {"SCR"                         ,        50,     2,      257,    "R/W",  0,      1,      0ull,   0},
8998         {"SIZE"                        ,        52,     3,      257,    "R/W",  0,      1,      0ull,   0},
8999         {"SOVR"                        ,        55,     1,      257,    "R/W",  0,      1,      0ull,   0},
9000         {"R"                           ,        56,     1,      257,    "R/W",  0,      1,      0ull,   0},
9001         {"OP"                          ,        57,     4,      257,    "R/W",  0,      1,      0ull,   0},
9002         {"EIA"                         ,        61,     1,      257,    "R/W",  0,      1,      0ull,   0},
9003         {"SLONLY"                      ,        62,     1,      257,    "R/W",  0,      1,      0ull,   0},
9004         {"V"                           ,        63,     1,      257,    "RC/W", 0,      1,      0ull,   0},
9005         {"D"                           ,        0,      32,     258,    "R/W",  0,      1,      0ull,   0},
9006         {"IA"                          ,        32,     8,      258,    "R/W",  0,      1,      0ull,   0},
9007         {"RESERVED_40_63"              ,        40,     24,     258,    "RAZ",  1,      1,      0,      0},
9008         {"D"                           ,        0,      32,     259,    "R/W",  1,      1,      0,      0},
9009         {"RESERVED_32_61"              ,        32,     30,     259,    "RAZ",  1,      1,      0,      0},
9010         {"V"                           ,        62,     2,      259,    "RC/W", 0,      1,      0ull,   0},
9011         {"DLH"                         ,        0,      8,      260,    "R/W",  0,      1,      0ull,   0},
9012         {"RESERVED_8_63"               ,        8,      56,     260,    "RAZ",  1,      1,      0,      0},
9013         {"DLL"                         ,        0,      8,      261,    "R/W",  0,      1,      0ull,   0},
9014         {"RESERVED_8_63"               ,        8,      56,     261,    "RAZ",  1,      1,      0,      0},
9015         {"FAR"                         ,        0,      1,      262,    "R/W",  0,      1,      0ull,   0},
9016         {"RESERVED_1_63"               ,        1,      63,     262,    "RAZ",  1,      1,      0,      0},
9017         {"EN"                          ,        0,      1,      263,    "WO",   0,      1,      0ull,   0},
9018         {"RXFR"                        ,        1,      1,      263,    "WO",   0,      1,      0ull,   0},
9019         {"TXFR"                        ,        2,      1,      263,    "WO",   0,      1,      0ull,   0},
9020         {"RESERVED_3_3"                ,        3,      1,      263,    "RAZ",  0,      1,      0ull,   0},
9021         {"TXTRIG"                      ,        4,      2,      263,    "WO",   0,      1,      0ull,   0},
9022         {"RXTRIG"                      ,        6,      2,      263,    "WO",   0,      1,      0ull,   0},
9023         {"RESERVED_8_63"               ,        8,      56,     263,    "RAZ",  1,      1,      0,      0},
9024         {"HTX"                         ,        0,      1,      264,    "R/W",  0,      1,      0ull,   0},
9025         {"RESERVED_1_63"               ,        1,      63,     264,    "RAZ",  1,      1,      0,      0},
9026         {"ERBFI"                       ,        0,      1,      265,    "R/W",  0,      1,      0ull,   0},
9027         {"ETBEI"                       ,        1,      1,      265,    "R/W",  0,      1,      0ull,   0},
9028         {"ELSI"                        ,        2,      1,      265,    "R/W",  0,      1,      0ull,   0},
9029         {"EDSSI"                       ,        3,      1,      265,    "R/W",  0,      1,      0ull,   0},
9030         {"RESERVED_4_6"                ,        4,      3,      265,    "RAZ",  0,      1,      0ull,   0},
9031         {"PTIME"                       ,        7,      1,      265,    "R/W",  0,      1,      0ull,   0},
9032         {"RESERVED_8_63"               ,        8,      56,     265,    "RAZ",  1,      1,      0,      0},
9033         {"IID"                         ,        0,      4,      266,    "RO",   0,      1,      1ull,   0},
9034         {"RESERVED_4_5"                ,        4,      2,      266,    "RAZ",  0,      1,      0ull,   0},
9035         {"FEN"                         ,        6,      2,      266,    "RO",   0,      1,      0ull,   0},
9036         {"RESERVED_8_63"               ,        8,      56,     266,    "RAZ",  1,      1,      0,      0},
9037         {"CLS"                         ,        0,      2,      267,    "R/W",  0,      1,      0ull,   0},
9038         {"STOP"                        ,        2,      1,      267,    "R/W",  0,      1,      0ull,   0},
9039         {"PEN"                         ,        3,      1,      267,    "R/W",  0,      1,      0ull,   0},
9040         {"EPS"                         ,        4,      1,      267,    "R/W",  0,      1,      0ull,   0},
9041         {"RESERVED_5_5"                ,        5,      1,      267,    "RAZ",  0,      1,      0ull,   0},
9042         {"BRK"                         ,        6,      1,      267,    "R/W",  0,      1,      0ull,   0},
9043         {"DLAB"                        ,        7,      1,      267,    "R/W",  0,      1,      0ull,   0},
9044         {"RESERVED_8_63"               ,        8,      56,     267,    "RAZ",  1,      1,      0,      0},
9045         {"DR"                          ,        0,      1,      268,    "RO",   0,      1,      0ull,   0},
9046         {"OE"                          ,        1,      1,      268,    "RC",   0,      1,      0ull,   0},
9047         {"PE"                          ,        2,      1,      268,    "RC",   0,      1,      0ull,   0},
9048         {"FE"                          ,        3,      1,      268,    "RC",   0,      1,      0ull,   0},
9049         {"BI"                          ,        4,      1,      268,    "RC",   0,      1,      0ull,   0},
9050         {"THRE"                        ,        5,      1,      268,    "RO",   0,      1,      1ull,   0},
9051         {"TEMT"                        ,        6,      1,      268,    "RO",   0,      1,      1ull,   0},
9052         {"FERR"                        ,        7,      1,      268,    "RC",   0,      1,      0ull,   0},
9053         {"RESERVED_8_63"               ,        8,      56,     268,    "RAZ",  1,      1,      0,      0},
9054         {"DTR"                         ,        0,      1,      269,    "R/W",  0,      1,      0ull,   0},
9055         {"RTS"                         ,        1,      1,      269,    "R/W",  0,      1,      0ull,   0},
9056         {"OUT1"                        ,        2,      1,      269,    "R/W",  0,      1,      0ull,   0},
9057         {"OUT2"                        ,        3,      1,      269,    "R/W",  0,      1,      0ull,   0},
9058         {"LOOP"                        ,        4,      1,      269,    "R/W",  0,      1,      0ull,   0},
9059         {"AFCE"                        ,        5,      1,      269,    "R/W",  0,      1,      0ull,   0},
9060         {"RESERVED_6_63"               ,        6,      58,     269,    "RAZ",  0,      1,      0ull,   0},
9061         {"DCTS"                        ,        0,      1,      270,    "RC",   0,      1,      0ull,   0},
9062         {"DDSR"                        ,        1,      1,      270,    "RC",   0,      1,      0ull,   0},
9063         {"TERI"                        ,        2,      1,      270,    "RC",   0,      1,      0ull,   0},
9064         {"DDCD"                        ,        3,      1,      270,    "RC",   0,      1,      0ull,   0},
9065         {"CTS"                         ,        4,      1,      270,    "RO",   1,      1,      0,      0},
9066         {"DSR"                         ,        5,      1,      270,    "RO",   0,      1,      0ull,   0},
9067         {"RI"                          ,        6,      1,      270,    "RO",   0,      1,      0ull,   0},
9068         {"DCD"                         ,        7,      1,      270,    "RO",   0,      1,      0ull,   0},
9069         {"RESERVED_8_63"               ,        8,      56,     270,    "RAZ",  1,      1,      0,      0},
9070         {"RBR"                         ,        0,      8,      271,    "RO",   0,      1,      0ull,   0},
9071         {"RESERVED_8_63"               ,        8,      56,     271,    "RAZ",  1,      1,      0,      0},
9072         {"RFL"                         ,        0,      7,      272,    "RO",   0,      1,      0ull,   0},
9073         {"RESERVED_7_63"               ,        7,      57,     272,    "RAZ",  1,      1,      0,      0},
9074         {"RFWD"                        ,        0,      8,      273,    "WO",   0,      1,      0ull,   0},
9075         {"RFPE"                        ,        8,      1,      273,    "WO",   0,      1,      0ull,   0},
9076         {"RFFE"                        ,        9,      1,      273,    "WO",   0,      1,      0ull,   0},
9077         {"RESERVED_10_63"              ,        10,     54,     273,    "RAZ",  1,      1,      0,      0},
9078         {"SBCR"                        ,        0,      1,      274,    "R/W",  0,      1,      0ull,   0},
9079         {"RESERVED_1_63"               ,        1,      63,     274,    "RAZ",  1,      1,      0,      0},
9080         {"SCR"                         ,        0,      8,      275,    "R/W",  0,      1,      0ull,   0},
9081         {"RESERVED_8_63"               ,        8,      56,     275,    "RAZ",  1,      1,      0,      0},
9082         {"SFE"                         ,        0,      1,      276,    "R/W",  0,      1,      0ull,   0},
9083         {"RESERVED_1_63"               ,        1,      63,     276,    "RAZ",  1,      1,      0,      0},
9084         {"USR"                         ,        0,      1,      277,    "WO",   0,      1,      0ull,   0},
9085         {"SRFR"                        ,        1,      1,      277,    "WO",   0,      1,      0ull,   0},
9086         {"STFR"                        ,        2,      1,      277,    "WO",   0,      1,      0ull,   0},
9087         {"RESERVED_3_63"               ,        3,      61,     277,    "RAZ",  1,      1,      0,      0},
9088         {"SRT"                         ,        0,      2,      278,    "R/W",  0,      1,      0ull,   0},
9089         {"RESERVED_2_63"               ,        2,      62,     278,    "RAZ",  1,      1,      0,      0},
9090         {"SRTS"                        ,        0,      1,      279,    "R/W",  0,      1,      0ull,   0},
9091         {"RESERVED_1_63"               ,        1,      63,     279,    "RAZ",  1,      1,      0,      0},
9092         {"STT"                         ,        0,      2,      280,    "R/W",  0,      1,      0ull,   0},
9093         {"RESERVED_2_63"               ,        2,      62,     280,    "RAZ",  1,      1,      0,      0},
9094         {"TFL"                         ,        0,      7,      281,    "RO",   0,      1,      0ull,   0},
9095         {"RESERVED_7_63"               ,        7,      57,     281,    "RAZ",  1,      1,      0,      0},
9096         {"TFR"                         ,        0,      8,      282,    "RO",   0,      1,      0ull,   0},
9097         {"RESERVED_8_63"               ,        8,      56,     282,    "RAZ",  1,      1,      0,      0},
9098         {"THR"                         ,        0,      8,      283,    "WO",   0,      1,      0ull,   0},
9099         {"RESERVED_8_63"               ,        8,      56,     283,    "RAZ",  1,      1,      0,      0},
9100         {"BUSY"                        ,        0,      1,      284,    "RO",   0,      1,      0ull,   0},
9101         {"TFNF"                        ,        1,      1,      284,    "RO",   0,      1,      1ull,   0},
9102         {"TFE"                         ,        2,      1,      284,    "RO",   0,      1,      1ull,   0},
9103         {"RFNE"                        ,        3,      1,      284,    "RO",   0,      1,      0ull,   0},
9104         {"RFF"                         ,        4,      1,      284,    "RO",   0,      1,      0ull,   0},
9105         {"RESERVED_5_63"               ,        5,      59,     284,    "RAZ",  1,      1,      0,      0},
9106         {"ENABLE"                      ,        0,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
9107         {"IDLELO"                      ,        1,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
9108         {"CLK_CONT"                    ,        2,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
9109         {"WIREOR"                      ,        3,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
9110         {"LSBFIRST"                    ,        4,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
9111         {"INT_ENA"                     ,        5,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
9112         {"CSENA"                       ,        6,      1,      285,    "R/W",  0,      0,      0ull,   1ull},
9113         {"CSHI"                        ,        7,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
9114         {"IDLECLKS"                    ,        8,      2,      285,    "R/W",  0,      0,      0ull,   0ull},
9115         {"TRITX"                       ,        10,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
9116         {"RESERVED_11_15"              ,        11,     5,      285,    "RAZ",  1,      1,      0,      0},
9117         {"CLKDIV"                      ,        16,     13,     285,    "R/W",  0,      0,      0ull,   0ull},
9118         {"RESERVED_29_63"              ,        29,     35,     285,    "RAZ",  1,      1,      0,      0},
9119         {"DATA"                        ,        0,      8,      286,    "R/W",  1,      1,      0,      0},
9120         {"RESERVED_8_63"               ,        8,      56,     286,    "RAZ",  1,      1,      0,      0},
9121         {"BUSY"                        ,        0,      1,      287,    "RO",   0,      0,      0ull,   0ull},
9122         {"RESERVED_1_7"                ,        1,      7,      287,    "RAZ",  1,      1,      0,      0},
9123         {"RXNUM"                       ,        8,      5,      287,    "RO",   0,      0,      0ull,   0ull},
9124         {"RESERVED_13_63"              ,        13,     51,     287,    "RAZ",  1,      1,      0,      0},
9125         {"TOTNUM"                      ,        0,      5,      288,    "WO",   1,      0,      0,      2ull},
9126         {"RESERVED_5_7"                ,        5,      3,      288,    "RAZ",  1,      1,      0,      0},
9127         {"TXNUM"                       ,        8,      5,      288,    "WO",   1,      0,      0,      1ull},
9128         {"RESERVED_13_15"              ,        13,     3,      288,    "RAZ",  1,      1,      0,      0},
9129         {"LEAVECS"                     ,        16,     1,      288,    "WO",   1,      0,      0,      0ull},
9130         {"RESERVED_17_63"              ,        17,     47,     288,    "RAZ",  1,      1,      0,      0},
9131         {"RESERVED_0_2"                ,        0,      3,      289,    "RAZ",  1,      1,      0,      0},
9132         {"BADDR"                       ,        3,      61,     289,    "R/W",  0,      1,      0ull,   0},
9133         {"RESERVED_0_2"                ,        0,      3,      290,    "RAZ",  1,      1,      0,      0},
9134         {"BADDR"                       ,        3,      61,     290,    "R/W",  0,      1,      0ull,   0},
9135         {"DPI_BS"                      ,        0,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9136         {"PDF_BS"                      ,        1,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9137         {"DOB_BS"                      ,        2,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9138         {"NUS_BS"                      ,        3,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9139         {"POS_BS"                      ,        4,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9140         {"POF3_BS"                     ,        5,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9141         {"POF2_BS"                     ,        6,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9142         {"POF1_BS"                     ,        7,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9143         {"POF0_BS"                     ,        8,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9144         {"PIG_BS"                      ,        9,      1,      291,    "RO",   0,      0,      0ull,   0ull},
9145         {"PGF_BS"                      ,        10,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9146         {"RDNL_BS"                     ,        11,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9147         {"PCAD_BS"                     ,        12,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9148         {"PCAC_BS"                     ,        13,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9149         {"RDN_BS"                      ,        14,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9150         {"PCN_BS"                      ,        15,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9151         {"PCNC_BS"                     ,        16,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9152         {"RDP_BS"                      ,        17,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9153         {"DIF_BS"                      ,        18,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9154         {"CSR_BS"                      ,        19,     1,      291,    "RO",   0,      0,      0ull,   0ull},
9155         {"RESERVED_20_63"              ,        20,     44,     291,    "RAZ",  1,      1,      0,      0},
9156         {"BSIZE"                       ,        0,      16,     292,    "R/W",  0,      1,      1024ull,        0},
9157         {"ISIZE"                       ,        16,     7,      292,    "R/W",  0,      1,      0ull,   0},
9158         {"RESERVED_23_63"              ,        23,     41,     292,    "RAZ",  1,      1,      0,      0},
9159         {"TIMER"                       ,        0,      10,     293,    "R/W",  0,      0,      0ull,   50ull},
9160         {"RESERVED_10_31"              ,        10,     22,     293,    "RAZ",  0,      0,      0ull,   0ull},
9161         {"MAX_WORD"                    ,        32,     5,      293,    "R/W",  0,      0,      2ull,   0ull},
9162         {"RESERVED_37_39"              ,        37,     3,      293,    "RAZ",  0,      0,      0ull,   0ull},
9163         {"WAIT_COM"                    ,        40,     1,      293,    "R/W",  0,      0,      0ull,   1ull},
9164         {"PCI_WDIS"                    ,        41,     1,      293,    "R/W",  0,      0,      0ull,   0ull},
9165         {"INS0_64B"                    ,        42,     1,      293,    "R/W",  0,      1,      0ull,   0},
9166         {"INS1_64B"                    ,        43,     1,      293,    "R/W",  0,      1,      0ull,   0},
9167         {"RESERVED_44_45"              ,        44,     2,      293,    "RAZ",  0,      0,      0ull,   0ull},
9168         {"INS0_ENB"                    ,        46,     1,      293,    "R/W",  0,      0,      0ull,   1ull},
9169         {"INS1_ENB"                    ,        47,     1,      293,    "R/W",  0,      0,      0ull,   1ull},
9170         {"RESERVED_48_49"              ,        48,     2,      293,    "RAZ",  0,      0,      0ull,   0ull},
9171         {"OUT0_ENB"                    ,        50,     1,      293,    "R/W",  0,      0,      0ull,   1ull},
9172         {"OUT1_ENB"                    ,        51,     1,      293,    "R/W",  0,      0,      0ull,   1ull},
9173         {"RESERVED_52_53"              ,        52,     2,      293,    "RAZ",  0,      0,      0ull,   0ull},
9174         {"DIS_PNIW"                    ,        54,     1,      293,    "R/W",  0,      0,      0ull,   1ull},
9175         {"CHIP_REV"                    ,        55,     8,      293,    "RO",   1,      1,      0,      0},
9176         {"RESERVED_63_63"              ,        63,     1,      293,    "RAZ",  1,      1,      0,      0},
9177         {"DBG_SEL"                     ,        0,      16,     294,    "R/W",  0,      1,      0ull,   0},
9178         {"RESERVED_16_63"              ,        16,     48,     294,    "RAZ",  1,      1,      0,      0},
9179         {"CSIZE"                       ,        0,      14,     295,    "R/W",  0,      1,      0ull,   0},
9180         {"LP_ENB"                      ,        14,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
9181         {"HP_ENB"                      ,        15,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
9182         {"O_MODE"                      ,        16,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
9183         {"O_ES"                        ,        17,     2,      295,    "R/W",  0,      1,      0ull,   0},
9184         {"O_NS"                        ,        19,     1,      295,    "R/W",  0,      1,      0ull,   0},
9185         {"O_RO"                        ,        20,     1,      295,    "R/W",  0,      1,      0ull,   0},
9186         {"O_ADD1"                      ,        21,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
9187         {"FPA_QUE"                     ,        22,     3,      295,    "R/W",  0,      1,      0ull,   0},
9188         {"DWB_ICHK"                    ,        25,     9,      295,    "R/W",  0,      1,      0ull,   0},
9189         {"DWB_DENB"                    ,        34,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
9190         {"B0_LEND"                     ,        35,     1,      295,    "R/W",  0,      0,      0ull,   0ull},
9191         {"RESERVED_36_63"              ,        36,     28,     295,    "RAZ",  1,      1,      0,      0},
9192         {"DBELL"                       ,        0,      32,     296,    "RO",   0,      0,      0ull,   0ull},
9193         {"FCNT"                        ,        32,     7,      296,    "RO",   0,      0,      0ull,   0ull},
9194         {"RESERVED_39_63"              ,        39,     25,     296,    "RAZ",  1,      1,      0,      0},
9195         {"ADDR"                        ,        0,      36,     297,    "RO",   0,      1,      0ull,   0},
9196         {"STATE"                       ,        36,     4,      297,    "RO",   0,      0,      0ull,   0ull},
9197         {"RESERVED_40_63"              ,        40,     24,     297,    "RAZ",  1,      1,      0,      0},
9198         {"DBELL"                       ,        0,      32,     298,    "RO",   0,      0,      0ull,   0ull},
9199         {"FCNT"                        ,        32,     7,      298,    "RO",   0,      0,      0ull,   0ull},
9200         {"RESERVED_39_63"              ,        39,     25,     298,    "RAZ",  1,      1,      0,      0},
9201         {"ADDR"                        ,        0,      36,     299,    "RO",   0,      1,      0ull,   0},
9202         {"STATE"                       ,        36,     4,      299,    "RO",   0,      0,      0ull,   0ull},
9203         {"RESERVED_40_63"              ,        40,     24,     299,    "RAZ",  1,      1,      0,      0},
9204         {"DBELL"                       ,        0,      16,     300,    "R/W",  0,      1,      0ull,   0},
9205         {"RESERVED_16_63"              ,        16,     48,     300,    "RAZ",  1,      1,      0,      0},
9206         {"SADDR"                       ,        0,      36,     301,    "R/W",  0,      1,      0ull,   0},
9207         {"RESERVED_36_63"              ,        36,     28,     301,    "RAZ",  1,      1,      0,      0},
9208         {"ROR"                         ,        0,      1,      302,    "R/W",  0,      1,      0ull,   0},
9209         {"ESR"                         ,        1,      2,      302,    "R/W",  0,      1,      0ull,   0},
9210         {"NSR"                         ,        3,      1,      302,    "R/W",  0,      1,      0ull,   0},
9211         {"USE_CSR"                     ,        4,      1,      302,    "R/W",  0,      0,      0ull,   1ull},
9212         {"D_ROR"                       ,        5,      1,      302,    "R/W",  0,      1,      0ull,   0},
9213         {"D_ESR"                       ,        6,      2,      302,    "R/W",  0,      1,      0ull,   0},
9214         {"D_NSR"                       ,        8,      1,      302,    "R/W",  0,      1,      0ull,   0},
9215         {"PBP_DHI"                     ,        9,      13,     302,    "R/W",  0,      1,      0ull,   0},
9216         {"RESERVED_22_63"              ,        22,     42,     302,    "RAZ",  1,      1,      0,      0},
9217         {"RML_RTO"                     ,        0,      1,      303,    "R/W",  0,      0,      0ull,   1ull},
9218         {"RML_WTO"                     ,        1,      1,      303,    "R/W",  0,      0,      0ull,   1ull},
9219         {"PCI_RSL"                     ,        2,      1,      303,    "R/W",  0,      0,      0ull,   1ull},
9220         {"PO0_2SML"                    ,        3,      1,      303,    "R/W",  0,      0,      0ull,   1ull},
9221         {"PO1_2SML"                    ,        4,      1,      303,    "R/W",  0,      0,      0ull,   1ull},
9222         {"RESERVED_5_6"                ,        5,      2,      303,    "RAZ",  0,      0,      0ull,   1ull},
9223         {"I0_RTOUT"                    ,        7,      1,      303,    "R/W",  0,      0,      0ull,   1ull},
9224         {"I1_RTOUT"                    ,        8,      1,      303,    "R/W",  0,      0,      0ull,   1ull},
9225         {"RESERVED_9_10"               ,        9,      2,      303,    "RAZ",  0,      0,      0ull,   1ull},
9226         {"I0_OVERF"                    ,        11,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9227         {"I1_OVERF"                    ,        12,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9228         {"RESERVED_13_14"              ,        13,     2,      303,    "RAZ",  0,      0,      0ull,   1ull},
9229         {"P0_RTOUT"                    ,        15,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9230         {"P1_RTOUT"                    ,        16,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9231         {"RESERVED_17_18"              ,        17,     2,      303,    "RAZ",  0,      0,      0ull,   1ull},
9232         {"P0_PERR"                     ,        19,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9233         {"P1_PERR"                     ,        20,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9234         {"RESERVED_21_22"              ,        21,     2,      303,    "RAZ",  0,      0,      0ull,   1ull},
9235         {"G0_RTOUT"                    ,        23,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9236         {"G1_RTOUT"                    ,        24,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9237         {"RESERVED_25_26"              ,        25,     2,      303,    "RAZ",  0,      0,      0ull,   1ull},
9238         {"P0_PPERR"                    ,        27,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9239         {"P1_PPERR"                    ,        28,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9240         {"RESERVED_29_30"              ,        29,     2,      303,    "RAZ",  0,      0,      0ull,   1ull},
9241         {"P0_PTOUT"                    ,        31,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9242         {"P1_PTOUT"                    ,        32,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9243         {"RESERVED_33_34"              ,        33,     2,      303,    "RAZ",  0,      0,      0ull,   1ull},
9244         {"I0_PPERR"                    ,        35,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9245         {"I1_PPERR"                    ,        36,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9246         {"RESERVED_37_38"              ,        37,     2,      303,    "RAZ",  0,      0,      0ull,   1ull},
9247         {"WIN_RTO"                     ,        39,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9248         {"P_DPERR"                     ,        40,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9249         {"IOBDMA"                      ,        41,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9250         {"FCR_S_E"                     ,        42,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9251         {"FCR_A_F"                     ,        43,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9252         {"PCR_S_E"                     ,        44,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9253         {"PCR_A_F"                     ,        45,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9254         {"Q2_S_E"                      ,        46,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9255         {"Q2_A_F"                      ,        47,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9256         {"Q3_S_E"                      ,        48,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9257         {"Q3_A_F"                      ,        49,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9258         {"COM_S_E"                     ,        50,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9259         {"COM_A_F"                     ,        51,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9260         {"PNC_S_E"                     ,        52,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9261         {"PNC_A_F"                     ,        53,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9262         {"RWX_S_E"                     ,        54,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9263         {"RDX_S_E"                     ,        55,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9264         {"PCF_P_E"                     ,        56,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9265         {"PCF_P_F"                     ,        57,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9266         {"PDF_P_E"                     ,        58,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9267         {"PDF_P_F"                     ,        59,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9268         {"Q1_S_E"                      ,        60,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9269         {"Q1_A_F"                      ,        61,     1,      303,    "R/W",  0,      0,      0ull,   1ull},
9270         {"RESERVED_62_63"              ,        62,     2,      303,    "RAZ",  1,      1,      0,      0},
9271         {"RML_RTO"                     ,        0,      1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9272         {"RML_WTO"                     ,        1,      1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9273         {"PCI_RSL"                     ,        2,      1,      304,    "RO",   0,      0,      0ull,   0ull},
9274         {"PO0_2SML"                    ,        3,      1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9275         {"PO1_2SML"                    ,        4,      1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9276         {"RESERVED_5_6"                ,        5,      2,      304,    "RAZ",  0,      0,      0ull,   0ull},
9277         {"I0_RTOUT"                    ,        7,      1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9278         {"I1_RTOUT"                    ,        8,      1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9279         {"RESERVED_9_10"               ,        9,      2,      304,    "RAZ",  0,      0,      0ull,   0ull},
9280         {"I0_OVERF"                    ,        11,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9281         {"I1_OVERF"                    ,        12,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9282         {"RESERVED_13_14"              ,        13,     2,      304,    "RAZ",  0,      0,      0ull,   0ull},
9283         {"P0_RTOUT"                    ,        15,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9284         {"P1_RTOUT"                    ,        16,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9285         {"RESERVED_17_18"              ,        17,     2,      304,    "RAZ",  0,      0,      0ull,   0ull},
9286         {"P0_PERR"                     ,        19,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9287         {"P1_PERR"                     ,        20,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9288         {"RESERVED_21_22"              ,        21,     2,      304,    "RAZ",  0,      0,      0ull,   0ull},
9289         {"G0_RTOUT"                    ,        23,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9290         {"G1_RTOUT"                    ,        24,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9291         {"RESERVED_25_26"              ,        25,     2,      304,    "RAZ",  0,      0,      0ull,   0ull},
9292         {"P0_PPERR"                    ,        27,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9293         {"P1_PPERR"                    ,        28,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9294         {"RESERVED_29_30"              ,        29,     2,      304,    "RAZ",  0,      0,      0ull,   0ull},
9295         {"P0_PTOUT"                    ,        31,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9296         {"P1_PTOUT"                    ,        32,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9297         {"RESERVED_33_34"              ,        33,     2,      304,    "RAZ",  0,      0,      0ull,   0ull},
9298         {"I0_PPERR"                    ,        35,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9299         {"I1_PPERR"                    ,        36,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9300         {"RESERVED_37_38"              ,        37,     2,      304,    "RAZ",  0,      0,      0ull,   0ull},
9301         {"WIN_RTO"                     ,        39,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9302         {"P_DPERR"                     ,        40,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9303         {"IOBDMA"                      ,        41,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9304         {"FCR_S_E"                     ,        42,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9305         {"FCR_A_F"                     ,        43,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9306         {"PCR_S_E"                     ,        44,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9307         {"PCR_A_F"                     ,        45,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9308         {"Q2_S_E"                      ,        46,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9309         {"Q2_A_F"                      ,        47,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9310         {"Q3_S_E"                      ,        48,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9311         {"Q3_A_F"                      ,        49,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9312         {"COM_S_E"                     ,        50,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9313         {"COM_A_F"                     ,        51,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9314         {"PNC_S_E"                     ,        52,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9315         {"PNC_A_F"                     ,        53,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9316         {"RWX_S_E"                     ,        54,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9317         {"RDX_S_E"                     ,        55,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9318         {"PCF_P_E"                     ,        56,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9319         {"PCF_P_F"                     ,        57,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9320         {"PDF_P_E"                     ,        58,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9321         {"PDF_P_F"                     ,        59,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9322         {"Q1_S_E"                      ,        60,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9323         {"Q1_A_F"                      ,        61,     1,      304,    "R/W1C",        0,      0,      0ull,   0ull},
9324         {"RESERVED_62_63"              ,        62,     2,      304,    "RAZ",  1,      1,      0,      0},
9325         {"DBELL"                       ,        0,      16,     305,    "R/W",  0,      1,      0ull,   0},
9326         {"RESERVED_16_63"              ,        16,     48,     305,    "RAZ",  1,      1,      0,      0},
9327         {"SADDR"                       ,        0,      36,     306,    "R/W",  0,      1,      0ull,   0},
9328         {"RESERVED_36_63"              ,        36,     28,     306,    "RAZ",  1,      1,      0,      0},
9329         {"BA"                          ,        0,      28,     307,    "R/W",  0,      1,      0ull,   0},
9330         {"ROW"                         ,        28,     1,      307,    "R/W",  0,      1,      0ull,   0},
9331         {"ROR"                         ,        29,     1,      307,    "R/W",  0,      1,      0ull,   0},
9332         {"NSW"                         ,        30,     1,      307,    "R/W",  0,      1,      0ull,   0},
9333         {"NSR"                         ,        31,     1,      307,    "R/W",  0,      1,      0ull,   0},
9334         {"ESW"                         ,        32,     2,      307,    "R/W",  0,      1,      0ull,   0},
9335         {"ESR"                         ,        34,     2,      307,    "R/W",  0,      1,      0ull,   0},
9336         {"RESERVED_36_63"              ,        36,     28,     307,    "RAZ",  1,      1,      0,      0},
9337         {"INT_VEC"                     ,        0,      64,     308,    "R/W1C",        0,      0,      0ull,   0ull},
9338         {"SIZE"                        ,        0,      32,     309,    "R/W",  0,      1,      0ull,   0},
9339         {"RESERVED_32_63"              ,        32,     32,     309,    "RAZ",  1,      1,      0,      0},
9340         {"ROR_SL0"                     ,        0,      1,      310,    "R/W",  0,      1,      0ull,   0},
9341         {"NSR_SL0"                     ,        1,      1,      310,    "R/W",  0,      1,      0ull,   0},
9342         {"ESR_SL0"                     ,        2,      2,      310,    "R/W",  0,      1,      0ull,   0},
9343         {"ROR_SL1"                     ,        4,      1,      310,    "R/W",  0,      1,      0ull,   0},
9344         {"NSR_SL1"                     ,        5,      1,      310,    "R/W",  0,      1,      0ull,   0},
9345         {"ESR_SL1"                     ,        6,      2,      310,    "R/W",  0,      1,      0ull,   0},
9346         {"RESERVED_8_15"               ,        8,      8,      310,    "RAZ",  0,      0,      0ull,   0ull},
9347         {"IPTR_O0"                     ,        16,     1,      310,    "R/W",  0,      0,      0ull,   1ull},
9348         {"IPTR_O1"                     ,        17,     1,      310,    "R/W",  0,      0,      0ull,   1ull},
9349         {"RESERVED_18_23"              ,        18,     6,      310,    "RAZ",  0,      0,      0ull,   0ull},
9350         {"O0_CSRM"                     ,        24,     1,      310,    "R/W",  0,      0,      0ull,   1ull},
9351         {"O1_CSRM"                     ,        25,     1,      310,    "R/W",  0,      0,      0ull,   1ull},
9352         {"RESERVED_26_27"              ,        26,     2,      310,    "RAZ",  0,      0,      0ull,   0ull},
9353         {"O0_RO"                       ,        28,     1,      310,    "R/W",  0,      1,      0ull,   0},
9354         {"O0_NS"                       ,        29,     1,      310,    "R/W",  0,      1,      0ull,   0},
9355         {"O0_ES"                       ,        30,     2,      310,    "R/W",  0,      1,      0ull,   0},
9356         {"O1_RO"                       ,        32,     1,      310,    "R/W",  0,      1,      0ull,   0},
9357         {"O1_NS"                       ,        33,     1,      310,    "R/W",  0,      1,      0ull,   0},
9358         {"O1_ES"                       ,        34,     2,      310,    "R/W",  0,      1,      0ull,   0},
9359         {"RESERVED_36_43"              ,        36,     8,      310,    "RAZ",  0,      0,      0ull,   0ull},
9360         {"P0_BMODE"                    ,        44,     1,      310,    "R/W",  0,      0,      0ull,   0ull},
9361         {"P1_BMODE"                    ,        45,     1,      310,    "R/W",  0,      0,      0ull,   0ull},
9362         {"RESERVED_46_63"              ,        46,     18,     310,    "RAZ",  0,      0,      0ull,   0ull},
9363         {"NADDR"                       ,        0,      61,     311,    "RO",   0,      1,      0ull,   0},
9364         {"STATE"                       ,        61,     2,      311,    "RO",   0,      0,      0ull,   0ull},
9365         {"RESERVED_63_63"              ,        63,     1,      311,    "RAZ",  1,      1,      0,      0},
9366         {"NADDR"                       ,        0,      61,     312,    "RO",   0,      1,      0ull,   0},
9367         {"STATE"                       ,        61,     3,      312,    "RO",   0,      0,      0ull,   0ull},
9368         {"AVAIL"                       ,        0,      32,     313,    "RO",   0,      0,      0ull,   0ull},
9369         {"FCNT"                        ,        32,     6,      313,    "RO",   0,      0,      0ull,   0ull},
9370         {"RESERVED_38_63"              ,        38,     26,     313,    "RAZ",  1,      1,      0,      0},
9371         {"AVAIL"                       ,        0,      32,     314,    "RO",   0,      0,      0ull,   0ull},
9372         {"FCNT"                        ,        32,     5,      314,    "RO",   0,      0,      0ull,   0ull},
9373         {"RESERVED_37_63"              ,        37,     27,     314,    "RAZ",  1,      1,      0,      0},
9374         {"RD_BRST"                     ,        0,      7,      315,    "R/W",  0,      0,      17ull,  64ull},
9375         {"WR_BRST"                     ,        7,      7,      315,    "R/W",  0,      0,      16ull,  64ull},
9376         {"RESERVED_14_63"              ,        14,     50,     315,    "RAZ",  1,      1,      0,      0},
9377         {"PARK_DEV"                    ,        0,      3,      316,    "R/W",  0,      1,      0ull,   0},
9378         {"PARK_MOD"                    ,        3,      1,      316,    "R/W",  0,      1,      0ull,   0},
9379         {"EN"                          ,        4,      1,      316,    "R/W",  0,      1,      0ull,   0},
9380         {"RESERVED_5_63"               ,        5,      59,     316,    "RAZ",  1,      1,      0,      0},
9381         {"CMD_SIZE"                    ,        0,      11,     317,    "R/W",  0,      0,      9ull,   9ull},
9382         {"RESERVED_11_63"              ,        11,     53,     317,    "RAZ",  1,      1,      0,      0},
9383         {"RSV_A"                       ,        0,      6,      318,    "R/W",  0,      1,      0ull,   0},
9384         {"SKP_LEN"                     ,        6,      7,      318,    "R/W",  0,      1,      0ull,   0},
9385         {"RSV_B"                       ,        13,     1,      318,    "R/W",  0,      1,      0ull,   0},
9386         {"PAR_MODE"                    ,        14,     2,      318,    "R/W",  0,      1,      0ull,   0},
9387         {"RSV_C"                       ,        16,     5,      318,    "R/W",  0,      1,      0ull,   0},
9388         {"USE_IHDR"                    ,        21,     1,      318,    "R/W",  0,      1,      0ull,   0},
9389         {"RSV_D"                       ,        22,     6,      318,    "R/W",  0,      1,      0ull,   0},
9390         {"RSKP_LEN"                    ,        28,     7,      318,    "R/W",  0,      1,      8ull,   0},
9391         {"RSV_E"                       ,        35,     1,      318,    "R/W",  0,      1,      0ull,   0},
9392         {"RPARMODE"                    ,        36,     2,      318,    "R/W",  0,      1,      0ull,   0},
9393         {"RSV_F"                       ,        38,     5,      318,    "R/W",  0,      1,      0ull,   0},
9394         {"PBP"                         ,        43,     1,      318,    "R/W",  0,      1,      0ull,   0},
9395         {"RESERVED_44_63"              ,        44,     20,     318,    "RAZ",  1,      1,      0,      0},
9396         {"RSV_A"                       ,        0,      6,      319,    "R/W",  0,      1,      0ull,   0},
9397         {"SKP_LEN"                     ,        6,      7,      319,    "R/W",  0,      1,      0ull,   0},
9398         {"RSV_B"                       ,        13,     1,      319,    "R/W",  0,      1,      0ull,   0},
9399         {"PAR_MODE"                    ,        14,     2,      319,    "R/W",  0,      1,      0ull,   0},
9400         {"RSV_C"                       ,        16,     5,      319,    "R/W",  0,      1,      0ull,   0},
9401         {"USE_IHDR"                    ,        21,     1,      319,    "R/W",  0,      1,      0ull,   0},
9402         {"RSV_D"                       ,        22,     6,      319,    "R/W",  0,      1,      0ull,   0},
9403         {"RSKP_LEN"                    ,        28,     7,      319,    "R/W",  0,      1,      8ull,   0},
9404         {"RSV_E"                       ,        35,     1,      319,    "R/W",  0,      1,      0ull,   0},
9405         {"RPARMODE"                    ,        36,     2,      319,    "R/W",  0,      1,      0ull,   0},
9406         {"RSV_F"                       ,        38,     5,      319,    "R/W",  0,      1,      0ull,   0},
9407         {"PBP"                         ,        43,     1,      319,    "R/W",  0,      1,      0ull,   0},
9408         {"RESERVED_44_63"              ,        44,     20,     319,    "RAZ",  1,      1,      0,      0},
9409         {"ENB"                         ,        0,      4,      320,    "R/W",  0,      0,      15ull,  15ull},
9410         {"BP_ON"                       ,        4,      4,      320,    "RO",   0,      0,      0ull,   0ull},
9411         {"RESERVED_8_63"               ,        8,      56,     320,    "RAZ",  1,      1,      0,      0},
9412         {"MIO"                         ,        0,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9413         {"GMX0"                        ,        1,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9414         {"GMX1"                        ,        2,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9415         {"NPI"                         ,        3,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9416         {"KEY"                         ,        4,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9417         {"FPA"                         ,        5,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9418         {"DFA"                         ,        6,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9419         {"ZIP"                         ,        7,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9420         {"RINT_8"                      ,        8,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9421         {"IPD"                         ,        9,      1,      321,    "RO",   0,      0,      0ull,   0ull},
9422         {"PKO"                         ,        10,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9423         {"TIM"                         ,        11,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9424         {"POW"                         ,        12,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9425         {"USB"                         ,        13,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9426         {"RINT_14"                     ,        14,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9427         {"RINT_15"                     ,        15,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9428         {"L2C"                         ,        16,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9429         {"LMC"                         ,        17,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9430         {"SPX0"                        ,        18,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9431         {"SPX1"                        ,        19,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9432         {"PIP"                         ,        20,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9433         {"RINT_21"                     ,        21,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9434         {"ASX0"                        ,        22,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9435         {"ASX1"                        ,        23,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9436         {"RINT_24"                     ,        24,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9437         {"RINT_25"                     ,        25,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9438         {"RINT_26"                     ,        26,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9439         {"RINT_27"                     ,        27,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9440         {"RINT_28"                     ,        28,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9441         {"RINT_29"                     ,        29,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9442         {"IOB"                         ,        30,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9443         {"RINT_31"                     ,        31,     1,      321,    "RO",   0,      0,      0ull,   0ull},
9444         {"RESERVED_32_63"              ,        32,     32,     321,    "RAZ",  1,      1,      0,      0},
9445         {"SIZE"                        ,        0,      32,     322,    "R/W",  0,      1,      0ull,   0},
9446         {"RESERVED_32_63"              ,        32,     32,     322,    "RAZ",  1,      1,      0,      0},
9447         {"TIME"                        ,        0,      32,     323,    "R/W",  0,      0,      0ull,   131072ull},
9448         {"RESERVED_32_63"              ,        32,     32,     323,    "RAZ",  1,      1,      0,      0},
9449         {"ADDR_V"                      ,        0,      1,      324,    "R/W",  0,      1,      0ull,   0},
9450         {"END_SWP"                     ,        1,      2,      324,    "R/W",  0,      1,      0ull,   0},
9451         {"CA"                          ,        3,      1,      324,    "R/W",  0,      0,      0ull,   0ull},
9452         {"ADDR_IDX"                    ,        4,      14,     324,    "R/W",  0,      1,      0ull,   0},
9453         {"RESERVED_18_31"              ,        18,     14,     324,    "RAZ",  1,      1,      0,      0},
9454         {"VENDID"                      ,        0,      16,     325,    "RO",   0,      0,      6013ull,        6013ull},
9455         {"DEVID"                       ,        16,     16,     325,    "RO",   0,      0,      32ull,  32ull},
9456         {"ISAE"                        ,        0,      1,      326,    "RO",   0,      0,      0ull,   0ull},
9457         {"MSAE"                        ,        1,      1,      326,    "R/W",  0,      0,      0ull,   1ull},
9458         {"ME"                          ,        2,      1,      326,    "R/W",  0,      0,      0ull,   1ull},
9459         {"SCSE"                        ,        3,      1,      326,    "RO",   0,      0,      0ull,   0ull},
9460         {"MWICE"                       ,        4,      1,      326,    "R/W",  0,      0,      0ull,   0ull},
9461         {"VPS"                         ,        5,      1,      326,    "RO",   0,      0,      0ull,   0ull},
9462         {"PEE"                         ,        6,      1,      326,    "R/W",  0,      0,      0ull,   1ull},
9463         {"ADS"                         ,        7,      1,      326,    "RO",   0,      0,      0ull,   0ull},
9464         {"SEE"                         ,        8,      1,      326,    "R/W",  0,      0,      0ull,   1ull},
9465         {"FBBE"                        ,        9,      1,      326,    "R/W",  0,      0,      0ull,   1ull},
9466         {"I_DIS"                       ,        10,     1,      326,    "R/W",  0,      0,      0ull,   0ull},
9467         {"RESERVED_11_18"              ,        11,     8,      326,    "RAZ",  1,      1,      0,      0},
9468         {"I_STAT"                      ,        19,     1,      326,    "RO",   0,      0,      0ull,   0ull},
9469         {"CLE"                         ,        20,     1,      326,    "RO",   0,      0,      1ull,   1ull},
9470         {"M66"                         ,        21,     1,      326,    "RO",   0,      0,      1ull,   1ull},
9471         {"RESERVED_22_22"              ,        22,     1,      326,    "RAZ",  1,      1,      0,      0},
9472         {"FBB"                         ,        23,     1,      326,    "RO",   0,      1,      1ull,   0},
9473         {"MDPE"                        ,        24,     1,      326,    "R/W1C",        0,      0,      0ull,   0ull},
9474         {"DEVT"                        ,        25,     2,      326,    "RO",   0,      0,      1ull,   1ull},
9475         {"STA"                         ,        27,     1,      326,    "R/W1C",        0,      0,      0ull,   0ull},
9476         {"RTA"                         ,        28,     1,      326,    "R/W1C",        0,      0,      0ull,   0ull},
9477         {"RMA"                         ,        29,     1,      326,    "R/W1C",        0,      0,      0ull,   0ull},
9478         {"SSE"                         ,        30,     1,      326,    "R/W1C",        0,      0,      0ull,   0ull},
9479         {"DPE"                         ,        31,     1,      326,    "R/W1C",        0,      0,      0ull,   0ull},
9480         {"RID"                         ,        0,      8,      327,    "RO",   0,      0,      0ull,   0ull},
9481         {"CC"                          ,        8,      24,     327,    "RO",   0,      0,      1048576ull,     1048576ull},
9482         {"CLS"                         ,        0,      8,      328,    "R/W",  0,      1,      0ull,   0},
9483         {"LT"                          ,        8,      8,      328,    "R/W",  0,      0,      0ull,   64ull},
9484         {"HT"                          ,        16,     8,      328,    "RO",   0,      0,      0ull,   0ull},
9485         {"BCOD"                        ,        24,     4,      328,    "RO",   0,      0,      0ull,   0ull},
9486         {"RESERVED_28_29"              ,        28,     2,      328,    "RAZ",  1,      1,      0,      0},
9487         {"BRB"                         ,        30,     1,      328,    "R/W",  0,      0,      0ull,   0ull},
9488         {"BCAP"                        ,        31,     1,      328,    "RO",   0,      0,      0ull,   0ull},
9489         {"MSPC"                        ,        0,      1,      329,    "RO",   0,      0,      0ull,   0ull},
9490         {"TYP"                         ,        1,      2,      329,    "RO",   0,      0,      2ull,   2ull},
9491         {"PF"                          ,        3,      1,      329,    "RO",   0,      0,      1ull,   1ull},
9492         {"LBASEZ"                      ,        4,      8,      329,    "RO",   0,      0,      0ull,   0ull},
9493         {"LBASE"                       ,        12,     20,     329,    "R/W",  0,      1,      0ull,   0},
9494         {"HBASE"                       ,        0,      32,     330,    "R/W",  0,      1,      0ull,   0},
9495         {"MSPC"                        ,        0,      1,      331,    "RO",   0,      0,      0ull,   0ull},
9496         {"TYP"                         ,        1,      2,      331,    "RO",   0,      0,      2ull,   2ull},
9497         {"PF"                          ,        3,      1,      331,    "RO",   0,      0,      1ull,   1ull},
9498         {"LBASEZ"                      ,        4,      23,     331,    "RO",   0,      0,      0ull,   0ull},
9499         {"LBASE"                       ,        27,     5,      331,    "R/W",  0,      1,      0ull,   0},
9500         {"HBASE"                       ,        0,      32,     332,    "R/W",  0,      1,      0ull,   0},
9501         {"MSPC"                        ,        0,      1,      333,    "RO",   0,      0,      0ull,   0ull},
9502         {"TYP"                         ,        1,      2,      333,    "RO",   0,      0,      2ull,   2ull},
9503         {"PF"                          ,        3,      1,      333,    "RO",   0,      0,      1ull,   1ull},
9504         {"LBASEZ"                      ,        4,      28,     333,    "RO",   0,      0,      0ull,   0ull},
9505         {"HBASEZ"                      ,        0,      7,      334,    "RO",   0,      0,      0ull,   0ull},
9506         {"HBASE"                       ,        7,      25,     334,    "R/W",  0,      1,      0ull,   0},
9507         {"CISP"                        ,        0,      32,     335,    "RO",   0,      0,      0ull,   0ull},
9508         {"SSVID"                       ,        0,      16,     336,    "RO",   0,      0,      6013ull,        6013ull},
9509         {"SSID"                        ,        16,     16,     336,    "RO",   0,      0,      1ull,   1ull},
9510         {"ERBAR_EN"                    ,        0,      1,      337,    "R/W",  0,      0,      0ull,   0ull},
9511         {"RESERVED_1_10"               ,        1,      10,     337,    "RAZ",  1,      1,      0,      0},
9512         {"ERBARZ"                      ,        11,     5,      337,    "RO",   0,      0,      0ull,   0ull},
9513         {"ERBAR"                       ,        16,     16,     337,    "R/W",  0,      1,      0ull,   0},
9514         {"CP"                          ,        0,      8,      338,    "RO",   0,      0,      224ull, 224ull},
9515         {"RESERVED_8_31"               ,        8,      24,     338,    "RAZ",  1,      1,      0,      0},
9516         {"IL"                          ,        0,      8,      339,    "R/W",  0,      1,      0ull,   0},
9517         {"INTA"                        ,        8,      8,      339,    "RO",   0,      0,      1ull,   1ull},
9518         {"MG"                          ,        16,     8,      339,    "RO",   0,      0,      64ull,  64ull},
9519         {"ML"                          ,        24,     8,      339,    "RO",   0,      0,      64ull,  64ull},
9520         {"MLTD"                        ,        0,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
9521         {"TSWC"                        ,        1,      1,      340,    "R/W",  0,      0,      0ull,   0ull},
9522         {"RESERVED_2_2"                ,        2,      1,      340,    "RAZ",  1,      1,      0,      0},
9523         {"DPPMR"                       ,        3,      1,      340,    "R/W",  0,      0,      0ull,   0ull},
9524         {"PBE"                         ,        4,      12,     340,    "R/W",  0,      0,      0ull,   0ull},
9525         {"TILT"                        ,        16,     4,      340,    "R/W",  0,      0,      0ull,   0ull},
9526         {"TSLTE"                       ,        20,     3,      340,    "R/W",  0,      0,      0ull,   0ull},
9527         {"TMAE"                        ,        23,     1,      340,    "R/W",  0,      0,      0ull,   0ull},
9528         {"TWTAE"                       ,        24,     1,      340,    "R/W",  0,      0,      0ull,   0ull},
9529         {"TWSEN"                       ,        25,     1,      340,    "R/W",  0,      0,      0ull,   0ull},
9530         {"TWSEI"                       ,        26,     1,      340,    "R/W",  0,      0,      0ull,   0ull},
9531         {"TRTAE"                       ,        27,     1,      340,    "R/W",  0,      0,      0ull,   0ull},
9532         {"TRDRS"                       ,        28,     1,      340,    "R/W",  0,      0,      0ull,   0ull},
9533         {"RDSATI"                      ,        29,     1,      340,    "R/W",  0,      0,      0ull,   0ull},
9534         {"TRDARD"                      ,        30,     1,      340,    "R/W1C",        0,      0,      0ull,   0ull},
9535         {"TRDNPR"                      ,        31,     1,      340,    "R/W1C",        0,      0,      0ull,   0ull},
9536         {"TSCME"                       ,        0,      32,     341,    "R/W1C",        0,      1,      0ull,   0},
9537         {"TDSRPS"                      ,        0,      32,     342,    "R/W1C",        0,      0,      0ull,   0ull},
9538         {"TDOMC"                       ,        0,      5,      343,    "R/W",  0,      0,      1ull,   1ull},
9539         {"TIDOMC"                      ,        5,      1,      343,    "R/W",  0,      0,      0ull,   0ull},
9540         {"RESERVED_6_6"                ,        6,      1,      343,    "RAZ",  1,      1,      0,      0},
9541         {"TIBDE"                       ,        7,      1,      343,    "R/W",  0,      0,      0ull,   0ull},
9542         {"TIBCD"                       ,        8,      1,      343,    "R/W1C",        0,      0,      0ull,   0ull},
9543         {"RESERVED_9_10"               ,        9,      2,      343,    "RAZ",  1,      1,      0,      0},
9544         {"TMAPES"                      ,        11,     1,      343,    "R/W1C",        0,      0,      0ull,   0ull},
9545         {"TMDPES"                      ,        12,     1,      343,    "R/W1C",        0,      0,      0ull,   0ull},
9546         {"TMSE"                        ,        13,     1,      343,    "R/W1C",        0,      0,      0ull,   0ull},
9547         {"TMEI"                        ,        14,     1,      343,    "RO",   0,      0,      0ull,   0ull},
9548         {"TECI"                        ,        15,     1,      343,    "RO",   0,      0,      0ull,   0ull},
9549         {"TMES"                        ,        16,     8,      343,    "RO",   0,      0,      0ull,   0ull},
9550         {"MDRRMC"                      ,        24,     3,      343,    "R/W",  0,      0,      2ull,   2ull},
9551         {"MDRIMC"                      ,        27,     1,      343,    "R/W",  0,      0,      0ull,   0ull},
9552         {"MDRE"                        ,        28,     1,      343,    "R/W",  0,      0,      0ull,   0ull},
9553         {"MDWE"                        ,        29,     1,      343,    "R/W",  0,      0,      0ull,   0ull},
9554         {"MRBCI"                       ,        30,     1,      343,    "R/W",  0,      0,      0ull,   0ull},
9555         {"MRBCM"                       ,        31,     1,      343,    "R/W",  0,      0,      1ull,   1ull},
9556         {"MDSP"                        ,        0,      32,     344,    "R/W1C",        0,      1,      0ull,   0},
9557         {"SCMRE"                       ,        0,      32,     345,    "R/W1C",        0,      1,      0ull,   0},
9558         {"MTTV"                        ,        0,      8,      346,    "R/W",  0,      0,      0ull,   0ull},
9559         {"MRV"                         ,        8,      8,      346,    "R/W",  0,      0,      0ull,   255ull},
9560         {"MTTA"                        ,        16,     1,      346,    "R/W1C",        0,      0,      0ull,   0ull},
9561         {"MRA"                         ,        17,     1,      346,    "R/W1C",        0,      0,      0ull,   0ull},
9562         {"FLUSH"                       ,        18,     1,      346,    "R/W",  0,      0,      1ull,   1ull},
9563         {"RESERVED_19_24"              ,        19,     6,      346,    "RAZ",  1,      1,      0,      0},
9564         {"MAC"                         ,        25,     7,      346,    "R/W",  0,      0,      0ull,   0ull},
9565         {"PXCID"                       ,        0,      8,      347,    "RO",   0,      0,      7ull,   7ull},
9566         {"NCP"                         ,        8,      8,      347,    "RO",   0,      0,      232ull, 232ull},
9567         {"DPERE"                       ,        16,     1,      347,    "R/W",  0,      0,      0ull,   0ull},
9568         {"ROE"                         ,        17,     1,      347,    "R/W",  0,      0,      1ull,   1ull},
9569         {"MMBC"                        ,        18,     2,      347,    "R/W",  0,      0,      0ull,   0ull},
9570         {"MOST"                        ,        20,     3,      347,    "R/W",  0,      0,      3ull,   3ull},
9571         {"RESERVED_23_31"              ,        23,     9,      347,    "RAZ",  1,      1,      0,      0},
9572         {"FN"                          ,        0,      3,      348,    "RO",   0,      0,      0ull,   0ull},
9573         {"DN"                          ,        3,      5,      348,    "RO",   0,      0,      31ull,  31ull},
9574         {"BN"                          ,        8,      8,      348,    "RO",   0,      1,      17ull,  0},
9575         {"W64"                         ,        16,     1,      348,    "RO",   0,      0,      1ull,   1ull},
9576         {"M133"                        ,        17,     1,      348,    "RO",   0,      0,      1ull,   1ull},
9577         {"SCD"                         ,        18,     1,      348,    "R/W1C",        0,      1,      0ull,   0},
9578         {"USC"                         ,        19,     1,      348,    "R/W1C",        0,      1,      0ull,   0},
9579         {"DC"                          ,        20,     1,      348,    "RO",   0,      0,      0ull,   0ull},
9580         {"MMRBCD"                      ,        21,     2,      348,    "RO",   0,      0,      2ull,   2ull},
9581         {"MOSTD"                       ,        23,     3,      348,    "RO",   0,      0,      3ull,   3ull},
9582         {"MCRSD"                       ,        26,     3,      348,    "RO",   0,      0,      7ull,   7ull},
9583         {"SCEMR"                       ,        29,     1,      348,    "R/W1C",        0,      1,      0ull,   0},
9584         {"RESERVED_30_31"              ,        30,     2,      348,    "RAZ",  1,      1,      0,      0},
9585         {"PMCID"                       ,        0,      8,      349,    "RO",   0,      0,      1ull,   1ull},
9586         {"NCP"                         ,        8,      8,      349,    "RO",   0,      0,      240ull, 240ull},
9587         {"PCIMIV"                      ,        16,     3,      349,    "RO",   0,      0,      2ull,   2ull},
9588         {"PMEC"                        ,        19,     1,      349,    "RO",   0,      0,      0ull,   0ull},
9589         {"RESERVED_20_20"              ,        20,     1,      349,    "RAZ",  1,      1,      0,      0},
9590         {"DSI"                         ,        21,     1,      349,    "RO",   0,      0,      0ull,   0ull},
9591         {"AUXC"                        ,        22,     3,      349,    "RO",   0,      0,      0ull,   0ull},
9592         {"D1S"                         ,        25,     1,      349,    "RO",   0,      0,      0ull,   0ull},
9593         {"D2S"                         ,        26,     1,      349,    "RO",   0,      0,      0ull,   0ull},
9594         {"PMES"                        ,        27,     5,      349,    "RO",   0,      0,      0ull,   0ull},
9595         {"PS"                          ,        0,      2,      350,    "R/W",  0,      0,      0ull,   0ull},
9596         {"RESERVED_2_7"                ,        2,      6,      350,    "RAZ",  1,      1,      0,      0},
9597         {"PMEENS"                      ,        8,      1,      350,    "R/W",  0,      0,      0ull,   0ull},
9598         {"PMDS"                        ,        9,      4,      350,    "R/W",  0,      0,      0ull,   0ull},
9599         {"PMEDSIA"                     ,        13,     2,      350,    "RO",   0,      0,      0ull,   0ull},
9600         {"PMESS"                       ,        15,     1,      350,    "R/W1C",        0,      0,      0ull,   0ull},
9601         {"RESERVED_16_21"              ,        16,     6,      350,    "RAZ",  1,      1,      0,      0},
9602         {"BD3H"                        ,        22,     1,      350,    "RO",   0,      0,      0ull,   0ull},
9603         {"BPCCEN"                      ,        23,     1,      350,    "RO",   0,      0,      0ull,   0ull},
9604         {"PMDIA"                       ,        24,     8,      350,    "RO",   0,      0,      0ull,   0ull},
9605         {"MSICID"                      ,        0,      8,      351,    "RO",   0,      0,      5ull,   5ull},
9606         {"NCP"                         ,        8,      8,      351,    "RO",   0,      0,      0ull,   0ull},
9607         {"MSIEN"                       ,        16,     1,      351,    "R/W",  0,      0,      0ull,   0ull},
9608         {"MMC"                         ,        17,     3,      351,    "RO",   0,      0,      0ull,   0ull},
9609         {"MME"                         ,        20,     3,      351,    "R/W",  0,      0,      0ull,   0ull},
9610         {"M64"                         ,        23,     1,      351,    "RO",   0,      0,      1ull,   1ull},
9611         {"RESERVED_24_31"              ,        24,     8,      351,    "RAZ",  1,      1,      0,      0},
9612         {"RESERVED_0_1"                ,        0,      2,      352,    "RAZ",  1,      1,      0,      0},
9613         {"MSI31T2"                     ,        2,      30,     352,    "R/W",  0,      1,      0ull,   0},
9614         {"MSI"                         ,        0,      32,     353,    "R/W",  0,      1,      0ull,   0},
9615         {"MSIMD"                       ,        0,      16,     354,    "R/W",  0,      1,      0ull,   0},
9616         {"RESERVED_16_31"              ,        16,     16,     354,    "RAZ",  1,      1,      0,      0},
9617         {"BAR2_CAX"                    ,        0,      1,      355,    "R/W",  0,      0,      0ull,   0ull},
9618         {"BAR2_ESX"                    ,        1,      2,      355,    "R/W",  0,      1,      0ull,   0},
9619         {"BAR2_ENB"                    ,        3,      1,      355,    "R/W",  0,      0,      0ull,   1ull},
9620         {"TSR_HWM"                     ,        4,      3,      355,    "R/W",  0,      1,      1ull,   0},
9621         {"PMO_FPC"                     ,        7,      3,      355,    "R/W",  0,      0,      0ull,   0ull},
9622         {"PMO_AMOD"                    ,        10,     1,      355,    "R/W",  0,      0,      0ull,   0ull},
9623         {"B12_BIST"                    ,        11,     1,      355,    "RO",   0,      0,      0ull,   0ull},
9624         {"AP_64AD"                     ,        12,     1,      355,    "RO",   0,      1,      0ull,   0},
9625         {"AP_PCIX"                     ,        13,     1,      355,    "RO",   0,      1,      0ull,   0},
9626         {"RESERVED_14_14"              ,        14,     1,      355,    "RAZ",  0,      0,      0ull,   0ull},
9627         {"EN_WFILT"                    ,        15,     1,      355,    "R/W",  0,      0,      0ull,   1ull},
9628         {"SCM"                         ,        16,     1,      355,    "RO",   0,      1,      0ull,   0},
9629         {"SCMTYP"                      ,        17,     1,      355,    "RO",   0,      1,      0ull,   0},
9630         {"BAR2PRES"                    ,        18,     1,      355,    "R/W",  1,      1,      0,      0},
9631         {"ERST_N"                      ,        19,     1,      355,    "RO",   0,      0,      1ull,   1ull},
9632         {"RESERVED_20_31"              ,        20,     12,     355,    "RAZ",  1,      1,      0,      0},
9633         {"INC_VAL"                     ,        0,      16,     356,    "R/W",  0,      1,      0ull,   0},
9634         {"RESERVED_16_31"              ,        16,     16,     356,    "RAZ",  1,      1,      0,      0},
9635         {"DMA_CNT"                     ,        0,      32,     357,    "R/W",  0,      0,      0ull,   0ull},
9636         {"PKT_CNT"                     ,        0,      32,     358,    "R/W",  0,      1,      0ull,   0},
9637         {"DMA_TIME"                    ,        0,      32,     359,    "R/W",  0,      1,      0ull,   0},
9638         {"ICNT"                        ,        0,      32,     360,    "RO",   0,      0,      0ull,   0ull},
9639         {"ITR_WABT"                    ,        0,      1,      361,    "R/W",  0,      1,      0ull,   0},
9640         {"IMR_WABT"                    ,        1,      1,      361,    "R/W",  0,      1,      0ull,   0},
9641         {"IMR_WTTO"                    ,        2,      1,      361,    "R/W",  0,      1,      0ull,   0},
9642         {"ITR_ABT"                     ,        3,      1,      361,    "R/W",  0,      1,      0ull,   0},
9643         {"IMR_ABT"                     ,        4,      1,      361,    "R/W",  0,      1,      0ull,   0},
9644         {"IMR_TTO"                     ,        5,      1,      361,    "R/W",  0,      1,      0ull,   0},
9645         {"IMSI_PER"                    ,        6,      1,      361,    "R/W",  0,      1,      0ull,   0},
9646         {"IMSI_TABT"                   ,        7,      1,      361,    "R/W",  0,      1,      0ull,   0},
9647         {"IMSI_MABT"                   ,        8,      1,      361,    "R/W",  0,      1,      0ull,   0},
9648         {"IMSC_MSG"                    ,        9,      1,      361,    "R/W",  0,      1,      0ull,   0},
9649         {"ITSR_ABT"                    ,        10,     1,      361,    "R/W",  0,      1,      0ull,   0},
9650         {"ISERR"                       ,        11,     1,      361,    "R/W",  0,      1,      0ull,   0},
9651         {"IAPERR"                      ,        12,     1,      361,    "R/W",  0,      1,      0ull,   0},
9652         {"IDPERR"                      ,        13,     1,      361,    "R/W",  0,      1,      0ull,   0},
9653         {"ILL_RWR"                     ,        14,     1,      361,    "R/W",  0,      1,      0ull,   0},
9654         {"ILL_RRD"                     ,        15,     1,      361,    "R/W",  0,      1,      0ull,   0},
9655         {"IRSL_INT"                    ,        16,     1,      361,    "R/W",  0,      1,      0ull,   0},
9656         {"IPCNT0"                      ,        17,     1,      361,    "R/W",  0,      1,      0ull,   0},
9657         {"IPCNT1"                      ,        18,     1,      361,    "R/W",  0,      1,      0ull,   0},
9658         {"RESERVED_19_20"              ,        19,     2,      361,    "RAZ",  0,      1,      0ull,   0},
9659         {"IPTIME0"                     ,        21,     1,      361,    "R/W",  0,      1,      0ull,   0},
9660         {"IPTIME1"                     ,        22,     1,      361,    "R/W",  0,      1,      0ull,   0},
9661         {"RESERVED_23_24"              ,        23,     2,      361,    "RAZ",  0,      1,      0ull,   0},
9662         {"IDCNT0"                      ,        25,     1,      361,    "R/W",  0,      1,      0ull,   0},
9663         {"IDCNT1"                      ,        26,     1,      361,    "R/W",  0,      1,      0ull,   0},
9664         {"IDTIME0"                     ,        27,     1,      361,    "R/W",  0,      1,      0ull,   0},
9665         {"IDTIME1"                     ,        28,     1,      361,    "R/W",  0,      1,      0ull,   0},
9666         {"DMA0_FI"                     ,        29,     1,      361,    "R/W",  0,      1,      0ull,   0},
9667         {"DMA1_FI"                     ,        30,     1,      361,    "R/W",  0,      1,      0ull,   0},
9668         {"WIN_WR"                      ,        31,     1,      361,    "R/W",  0,      1,      0ull,   0},
9669         {"ILL_WR"                      ,        32,     1,      361,    "R/W",  0,      1,      0ull,   0},
9670         {"ILL_RD"                      ,        33,     1,      361,    "R/W",  0,      1,      0ull,   0},
9671         {"RESERVED_34_63"              ,        34,     30,     361,    "RAZ",  1,      1,      0,      0},
9672         {"RTR_WABT"                    ,        0,      1,      362,    "R/W",  0,      1,      0ull,   0},
9673         {"RMR_WABT"                    ,        1,      1,      362,    "R/W",  0,      1,      0ull,   0},
9674         {"RMR_WTTO"                    ,        2,      1,      362,    "R/W",  0,      1,      0ull,   0},
9675         {"RTR_ABT"                     ,        3,      1,      362,    "R/W",  0,      1,      0ull,   0},
9676         {"RMR_ABT"                     ,        4,      1,      362,    "R/W",  0,      1,      0ull,   0},
9677         {"RMR_TTO"                     ,        5,      1,      362,    "R/W",  0,      1,      0ull,   0},
9678         {"RMSI_PER"                    ,        6,      1,      362,    "R/W",  0,      1,      0ull,   0},
9679         {"RMSI_TABT"                   ,        7,      1,      362,    "R/W",  0,      1,      0ull,   0},
9680         {"RMSI_MABT"                   ,        8,      1,      362,    "R/W",  0,      1,      0ull,   0},
9681         {"RMSC_MSG"                    ,        9,      1,      362,    "R/W",  0,      1,      0ull,   0},
9682         {"RTSR_ABT"                    ,        10,     1,      362,    "R/W",  0,      1,      0ull,   0},
9683         {"RSERR"                       ,        11,     1,      362,    "R/W",  0,      1,      0ull,   0},
9684         {"RAPERR"                      ,        12,     1,      362,    "R/W",  0,      1,      0ull,   0},
9685         {"RDPERR"                      ,        13,     1,      362,    "R/W",  0,      1,      0ull,   0},
9686         {"ILL_RWR"                     ,        14,     1,      362,    "R/W",  0,      1,      0ull,   0},
9687         {"ILL_RRD"                     ,        15,     1,      362,    "R/W",  0,      1,      0ull,   0},
9688         {"RRSL_INT"                    ,        16,     1,      362,    "R/W",  0,      1,      0ull,   0},
9689         {"RPCNT0"                      ,        17,     1,      362,    "R/W",  0,      1,      0ull,   0},
9690         {"RPCNT1"                      ,        18,     1,      362,    "R/W",  0,      1,      0ull,   0},
9691         {"RESERVED_19_20"              ,        19,     2,      362,    "RAZ",  0,      1,      0ull,   0},
9692         {"RPTIME0"                     ,        21,     1,      362,    "R/W",  0,      1,      0ull,   0},
9693         {"RPTIME1"                     ,        22,     1,      362,    "R/W",  0,      1,      0ull,   0},
9694         {"RESERVED_23_24"              ,        23,     2,      362,    "RAZ",  0,      1,      0ull,   0},
9695         {"RDCNT0"                      ,        25,     1,      362,    "R/W",  0,      1,      0ull,   0},
9696         {"RDCNT1"                      ,        26,     1,      362,    "R/W",  0,      1,      0ull,   0},
9697         {"RDTIME0"                     ,        27,     1,      362,    "R/W",  0,      1,      0ull,   0},
9698         {"RDTIME1"                     ,        28,     1,      362,    "R/W",  0,      1,      0ull,   0},
9699         {"DMA0_FI"                     ,        29,     1,      362,    "R/W",  0,      1,      0ull,   0},
9700         {"DMA1_FI"                     ,        30,     1,      362,    "R/W",  0,      1,      0ull,   0},
9701         {"WIN_WR"                      ,        31,     1,      362,    "R/W",  0,      1,      0ull,   0},
9702         {"ILL_WR"                      ,        32,     1,      362,    "R/W",  0,      1,      0ull,   0},
9703         {"ILL_RD"                      ,        33,     1,      362,    "R/W",  0,      1,      0ull,   0},
9704         {"RESERVED_34_63"              ,        34,     30,     362,    "RAZ",  1,      1,      0,      0},
9705         {"TR_WABT"                     ,        0,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9706         {"MR_WABT"                     ,        1,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9707         {"MR_WTTO"                     ,        2,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9708         {"TR_ABT"                      ,        3,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9709         {"MR_ABT"                      ,        4,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9710         {"MR_TTO"                      ,        5,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9711         {"MSI_PER"                     ,        6,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9712         {"MSI_TABT"                    ,        7,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9713         {"MSI_MABT"                    ,        8,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9714         {"MSC_MSG"                     ,        9,      1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9715         {"TSR_ABT"                     ,        10,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9716         {"SERR"                        ,        11,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9717         {"APERR"                       ,        12,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9718         {"DPERR"                       ,        13,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9719         {"ILL_RWR"                     ,        14,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9720         {"ILL_RRD"                     ,        15,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9721         {"RSL_INT"                     ,        16,     1,      363,    "RO",   0,      0,      0ull,   0ull},
9722         {"PCNT0"                       ,        17,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9723         {"PCNT1"                       ,        18,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9724         {"RESERVED_19_20"              ,        19,     2,      363,    "RAZ",  0,      0,      0ull,   0ull},
9725         {"PTIME0"                      ,        21,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9726         {"PTIME1"                      ,        22,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9727         {"RESERVED_23_24"              ,        23,     2,      363,    "RAZ",  0,      0,      0ull,   0ull},
9728         {"DCNT0"                       ,        25,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9729         {"DCNT1"                       ,        26,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9730         {"DTIME0"                      ,        27,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9731         {"DTIME1"                      ,        28,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9732         {"DMA0_FI"                     ,        29,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9733         {"DMA1_FI"                     ,        30,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9734         {"WIN_WR"                      ,        31,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9735         {"ILL_WR"                      ,        32,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9736         {"ILL_RD"                      ,        33,     1,      363,    "R/W1C",        0,      0,      0ull,   0ull},
9737         {"RESERVED_34_63"              ,        34,     30,     363,    "RAZ",  1,      1,      0,      0},
9738         {"TR_WABT"                     ,        0,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9739         {"MR_WABT"                     ,        1,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9740         {"MR_WTTO"                     ,        2,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9741         {"TR_ABT"                      ,        3,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9742         {"MR_ABT"                      ,        4,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9743         {"MR_TTO"                      ,        5,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9744         {"MSI_PER"                     ,        6,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9745         {"MSI_TABT"                    ,        7,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9746         {"MSI_MABT"                    ,        8,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9747         {"MSC_MSG"                     ,        9,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9748         {"TSR_ABT"                     ,        10,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9749         {"SERR"                        ,        11,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9750         {"APERR"                       ,        12,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9751         {"DPERR"                       ,        13,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9752         {"ILL_RWR"                     ,        14,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9753         {"ILL_RRD"                     ,        15,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9754         {"RSL_INT"                     ,        16,     1,      364,    "RO",   0,      0,      0ull,   0ull},
9755         {"PCNT0"                       ,        17,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9756         {"PCNT1"                       ,        18,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9757         {"RESERVED_19_20"              ,        19,     2,      364,    "RAZ",  0,      0,      0ull,   0ull},
9758         {"PTIME0"                      ,        21,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9759         {"PTIME1"                      ,        22,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9760         {"RESERVED_23_24"              ,        23,     2,      364,    "RAZ",  0,      0,      0ull,   0ull},
9761         {"DCNT0"                       ,        25,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9762         {"DCNT1"                       ,        26,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9763         {"DTIME0"                      ,        27,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9764         {"DTIME1"                      ,        28,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9765         {"DMA0_FI"                     ,        29,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9766         {"DMA1_FI"                     ,        30,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9767         {"WIN_WR"                      ,        31,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9768         {"ILL_WR"                      ,        32,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9769         {"ILL_RD"                      ,        33,     1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
9770         {"RESERVED_34_63"              ,        34,     30,     364,    "RAZ",  1,      1,      0,      0},
9771         {"INTR"                        ,        0,      6,      365,    "WO",   0,      1,      0ull,   0},
9772         {"RESERVED_6_31"               ,        6,      26,     365,    "R/W",  1,      1,      0,      0},
9773         {"PTR_CNT"                     ,        0,      16,     366,    "R/W",  0,      1,      0ull,   0},
9774         {"PKT_CNT"                     ,        16,     16,     366,    "R/W",  0,      1,      0ull,   0},
9775         {"PKT_CNT"                     ,        0,      32,     367,    "RO",   0,      0,      0ull,   0ull},
9776         {"PKT_CNT"                     ,        0,      32,     368,    "R/W",  0,      1,      0ull,   0},
9777         {"PKT_TIME"                    ,        0,      32,     369,    "R/W",  0,      1,      0ull,   0},
9778         {"PREFETCH"                    ,        0,      3,      370,    "R/W",  0,      0,      0ull,   2ull},
9779         {"MIN_DATA"                    ,        3,      6,      370,    "R/W",  0,      0,      0ull,   4ull},
9780         {"RESERVED_9_31"               ,        9,      23,     370,    "RAZ",  1,      1,      0,      0},
9781         {"PREFETCH"                    ,        0,      3,      371,    "R/W",  0,      0,      0ull,   3ull},
9782         {"MIN_DATA"                    ,        3,      6,      371,    "R/W",  0,      0,      0ull,   6ull},
9783         {"RESERVED_9_31"               ,        9,      23,     371,    "RAZ",  1,      1,      0,      0},
9784         {"PREFETCH"                    ,        0,      3,      372,    "R/W",  0,      0,      0ull,   3ull},
9785         {"MIN_DATA"                    ,        3,      6,      372,    "R/W",  0,      0,      0ull,   6ull},
9786         {"RESERVED_9_31"               ,        9,      23,     372,    "RAZ",  1,      1,      0,      0},
9787         {"CNT"                         ,        0,      31,     373,    "R/W",  0,      0,      10000ull,       10000ull},
9788         {"ENB"                         ,        31,     1,      373,    "R/W",  0,      0,      0ull,   1ull},
9789         {"RESERVED_32_63"              ,        32,     32,     373,    "RAZ",  1,      1,      0,      0},
9790         {"SCM"                         ,        0,      32,     374,    "RO",   0,      1,      0ull,   0},
9791         {"RESERVED_32_63"              ,        32,     32,     374,    "RAZ",  1,      1,      0,      0},
9792         {"TSR"                         ,        0,      36,     375,    "RO",   0,      1,      0ull,   0},
9793         {"RESERVED_36_63"              ,        36,     28,     375,    "RAZ",  1,      1,      0,      0},
9794         {"RESERVED_0_1"                ,        0,      2,      376,    "RAZ",  1,      1,      0,      0},
9795         {"RD_ADDR"                     ,        2,      46,     376,    "R/W",  0,      1,      0ull,   0},
9796         {"IOBIT"                       ,        48,     1,      376,    "RAZ",  0,      0,      0ull,   0ull},
9797         {"RESERVED_49_63"              ,        49,     15,     376,    "RAZ",  1,      1,      0,      0},
9798         {"RD_DATA"                     ,        0,      64,     377,    "RO",   0,      1,      0ull,   0},
9799         {"RESERVED_0_2"                ,        0,      3,      378,    "RAZ",  1,      1,      0,      0},
9800         {"WR_ADDR"                     ,        3,      45,     378,    "R/W",  0,      1,      0ull,   0},
9801         {"IOBIT"                       ,        48,     1,      378,    "RAZ",  0,      0,      0ull,   0ull},
9802         {"RESERVED_49_63"              ,        49,     15,     378,    "RAZ",  1,      1,      0,      0},
9803         {"WR_DATA"                     ,        0,      64,     379,    "R/W",  0,      1,      0ull,   0},
9804         {"WR_MASK"                     ,        0,      8,      380,    "R/W",  0,      0,      0ull,   0ull},
9805         {"RESERVED_8_63"               ,        8,      56,     380,    "RAZ",  1,      1,      0,      0},
9806         {"THRESH"                      ,        0,      4,      381,    "R/W",  0,      0,      0ull,   8ull},
9807         {"FETCHSIZ"                    ,        4,      4,      381,    "R/W",  0,      0,      0ull,   7ull},
9808         {"TXRD"                        ,        8,      10,     381,    "R/W",  0,      0,      0ull,   1ull},
9809         {"USELDT"                      ,        18,     1,      381,    "R/W",  0,      0,      0ull,   0ull},
9810         {"RESERVED_19_19"              ,        19,     1,      381,    "RAZ",  1,      1,      0,      0},
9811         {"RXST"                        ,        20,     10,     381,    "R/W",  0,      0,      0ull,   1ull},
9812         {"RESERVED_30_31"              ,        30,     2,      381,    "RAZ",  1,      1,      0,      0},
9813         {"TXSLOTS"                     ,        32,     10,     381,    "R/W",  0,      1,      0ull,   0},
9814         {"RESERVED_42_43"              ,        42,     2,      381,    "RAZ",  1,      1,      0,      0},
9815         {"RXSLOTS"                     ,        44,     10,     381,    "R/W",  0,      1,      0ull,   0},
9816         {"RESERVED_54_62"              ,        54,     9,      381,    "RAZ",  1,      1,      0,      0},
9817         {"RDPEND"                      ,        63,     1,      381,    "RO",   0,      0,      0ull,   0ull},
9818         {"FSYNCMISSED"                 ,        0,      1,      382,    "R/W",  0,      0,      0ull,   1ull},
9819         {"FSYNCEXTRA"                  ,        1,      1,      382,    "R/W",  0,      0,      0ull,   1ull},
9820         {"RXWRAP"                      ,        2,      1,      382,    "R/W",  0,      0,      0ull,   1ull},
9821         {"RXST"                        ,        3,      1,      382,    "R/W",  0,      0,      0ull,   1ull},
9822         {"TXWRAP"                      ,        4,      1,      382,    "R/W",  0,      0,      0ull,   1ull},
9823         {"TXRD"                        ,        5,      1,      382,    "R/W",  0,      0,      0ull,   1ull},
9824         {"TXEMPTY"                     ,        6,      1,      382,    "R/W",  0,      0,      0ull,   1ull},
9825         {"RXOVF"                       ,        7,      1,      382,    "R/W",  0,      0,      0ull,   1ull},
9826         {"RESERVED_8_63"               ,        8,      56,     382,    "RAZ",  1,      1,      0,      0},
9827         {"FSYNCMISSED"                 ,        0,      1,      383,    "R/W1C",        0,      0,      0ull,   0ull},
9828         {"FSYNCEXTRA"                  ,        1,      1,      383,    "R/W1C",        0,      0,      0ull,   0ull},
9829         {"RXWRAP"                      ,        2,      1,      383,    "R/W1C",        0,      0,      0ull,   0ull},
9830         {"RXST"                        ,        3,      1,      383,    "R/W1C",        0,      0,      0ull,   0ull},
9831         {"TXWRAP"                      ,        4,      1,      383,    "R/W1C",        0,      0,      0ull,   0ull},
9832         {"TXRD"                        ,        5,      1,      383,    "R/W1C",        0,      0,      0ull,   0ull},
9833         {"TXEMPTY"                     ,        6,      1,      383,    "R/W1C",        0,      0,      0ull,   0ull},
9834         {"RXOVF"                       ,        7,      1,      383,    "R/W1C",        0,      0,      0ull,   0ull},
9835         {"RESERVED_8_63"               ,        8,      56,     383,    "RAZ",  1,      1,      0,      0},
9836         {"ADDR"                        ,        0,      36,     384,    "R/W",  1,      1,      0,      0},
9837         {"RESERVED_36_63"              ,        36,     28,     384,    "RAZ",  1,      1,      0,      0},
9838         {"CNT"                         ,        0,      16,     385,    "R/W",  1,      1,      0,      0},
9839         {"RESERVED_16_63"              ,        16,     48,     385,    "RAZ",  1,      1,      0,      0},
9840         {"MASK"                        ,        0,      64,     386,    "R/W",  1,      1,      0,      0},
9841         {"MASK"                        ,        0,      64,     387,    "R/W",  1,      1,      0,      0},
9842         {"MASK"                        ,        0,      64,     388,    "R/W",  1,      1,      0,      0},
9843         {"MASK"                        ,        0,      64,     389,    "R/W",  1,      1,      0,      0},
9844         {"MASK"                        ,        0,      64,     390,    "R/W",  1,      1,      0,      0},
9845         {"MASK"                        ,        0,      64,     391,    "R/W",  1,      1,      0,      0},
9846         {"MASK"                        ,        0,      64,     392,    "R/W",  1,      1,      0,      0},
9847         {"MASK"                        ,        0,      64,     393,    "R/W",  1,      1,      0,      0},
9848         {"RESERVED_0_2"                ,        0,      3,      394,    "RAZ",  1,      1,      0,      0},
9849         {"ADDR"                        ,        3,      33,     394,    "R/W",  1,      1,      0,      0},
9850         {"RESERVED_36_63"              ,        36,     28,     394,    "RAZ",  1,      1,      0,      0},
9851         {"ENABLE"                      ,        0,      1,      395,    "R/W",  0,      0,      0ull,   0ull},
9852         {"USECLK1"                     ,        1,      1,      395,    "R/W",  0,      0,      0ull,   0ull},
9853         {"LSBFIRST"                    ,        2,      1,      395,    "R/W",  0,      0,      0ull,   0ull},
9854         {"RESERVED_3_31"               ,        3,      29,     395,    "RAZ",  1,      1,      0,      0},
9855         {"SAMPPT"                      ,        32,     16,     395,    "R/W",  0,      1,      0ull,   0},
9856         {"DRVTIM"                      ,        48,     16,     395,    "R/W",  0,      1,      0ull,   0},
9857         {"DEBUGINFO"                   ,        0,      64,     396,    "RO",   1,      1,      0,      0},
9858         {"FRAM"                        ,        0,      3,      397,    "R/W",  1,      1,      0,      0},
9859         {"ADDR"                        ,        3,      33,     397,    "R/W",  1,      1,      0,      0},
9860         {"RESERVED_36_63"              ,        36,     28,     397,    "RAZ",  1,      1,      0,      0},
9861         {"CNT"                         ,        0,      16,     398,    "R/W",  1,      1,      0,      0},
9862         {"RESERVED_16_63"              ,        16,     48,     398,    "RAZ",  1,      1,      0,      0},
9863         {"MASK"                        ,        0,      64,     399,    "R/W",  1,      1,      0,      0},
9864         {"MASK"                        ,        0,      64,     400,    "R/W",  1,      1,      0,      0},
9865         {"MASK"                        ,        0,      64,     401,    "R/W",  1,      1,      0,      0},
9866         {"MASK"                        ,        0,      64,     402,    "R/W",  1,      1,      0,      0},
9867         {"MASK"                        ,        0,      64,     403,    "R/W",  1,      1,      0,      0},
9868         {"MASK"                        ,        0,      64,     404,    "R/W",  1,      1,      0,      0},
9869         {"MASK"                        ,        0,      64,     405,    "R/W",  1,      1,      0,      0},
9870         {"MASK"                        ,        0,      64,     406,    "R/W",  1,      1,      0,      0},
9871         {"RESERVED_0_2"                ,        0,      3,      407,    "RAZ",  1,      1,      0,      0},
9872         {"ADDR"                        ,        3,      33,     407,    "R/W",  1,      1,      0,      0},
9873         {"RESERVED_36_63"              ,        36,     28,     407,    "RAZ",  1,      1,      0,      0},
9874         {"ENA"                         ,        0,      1,      408,    "R/W",  0,      0,      0ull,   0ull},
9875         {"FSYNCPOL"                    ,        1,      1,      408,    "R/W",  0,      0,      0ull,   0ull},
9876         {"BCLKPOL"                     ,        2,      1,      408,    "R/W",  0,      0,      0ull,   0ull},
9877         {"BITLEN"                      ,        3,      2,      408,    "R/W",  0,      0,      0ull,   0ull},
9878         {"EXTRABIT"                    ,        5,      1,      408,    "R/W",  0,      0,      0ull,   0ull},
9879         {"NUMSLOTS"                    ,        6,      10,     408,    "R/W",  0,      1,      0ull,   0},
9880         {"FSYNCLOC"                    ,        16,     5,      408,    "R/W",  0,      0,      0ull,   0ull},
9881         {"FSYNCLEN"                    ,        21,     5,      408,    "R/W",  0,      0,      0ull,   2ull},
9882         {"RESERVED_26_31"              ,        26,     6,      408,    "RAZ",  1,      1,      0,      0},
9883         {"FSYNCSAMP"                   ,        32,     16,     408,    "R/W",  0,      1,      0ull,   0},
9884         {"RESERVED_48_62"              ,        48,     15,     408,    "RAZ",  1,      1,      0,      0},
9885         {"FSYNCGOOD"                   ,        63,     1,      408,    "RO",   0,      0,      0ull,   1ull},
9886         {"DEBUGINFO"                   ,        0,      64,     409,    "RO",   1,      1,      0,      0},
9887         {"N"                           ,        0,      32,     410,    "R/W",  0,      1,      0ull,   0},
9888         {"NUMSAMP"                     ,        32,     16,     410,    "R/W",  0,      1,      0ull,   0},
9889         {"DELTASAMP"                   ,        48,     16,     410,    "R/W",  0,      0,      0ull,   0ull},
9890         {"BIST"                        ,        0,      18,     411,    "RO",   0,      0,      0ull,   0ull},
9891         {"RESERVED_18_63"              ,        18,     46,     411,    "RAZ",  1,      1,      0,      0},
9892         {"DPRT"                        ,        0,      16,     412,    "R/W",  0,      0,      0ull,   0ull},
9893         {"UDP"                         ,        16,     1,      412,    "R/W",  0,      0,      0ull,   0ull},
9894         {"TCP"                         ,        17,     1,      412,    "R/W",  0,      0,      0ull,   0ull},
9895         {"RESERVED_18_63"              ,        18,     46,     412,    "RAZ",  1,      1,      0,      0},
9896         {"NIP_SHF"                     ,        0,      3,      413,    "R/W",  0,      0,      0ull,   0ull},
9897         {"RESERVED_3_7"                ,        3,      5,      413,    "RAZ",  1,      1,      0,      0},
9898         {"RAW_SHF"                     ,        8,      3,      413,    "R/W",  0,      0,      0ull,   0ull},
9899         {"RESERVED_11_15"              ,        11,     5,      413,    "RAZ",  1,      1,      0,      0},
9900         {"MAX_L2"                      ,        16,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
9901         {"IP6_UDP"                     ,        17,     1,      413,    "R/W",  0,      0,      1ull,   1ull},
9902         {"TAG_SYN"                     ,        18,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
9903         {"RESERVED_19_63"              ,        19,     45,     413,    "RAZ",  1,      1,      0,      0},
9904         {"IP_CHK"                      ,        0,      1,      414,    "R/W",  0,      0,      1ull,   1ull},
9905         {"IP_MAL"                      ,        1,      1,      414,    "R/W",  0,      0,      1ull,   1ull},
9906         {"IP_HOP"                      ,        2,      1,      414,    "R/W",  0,      0,      1ull,   1ull},
9907         {"IP4_OPTS"                    ,        3,      1,      414,    "R/W",  0,      0,      1ull,   1ull},
9908         {"IP6_EEXT"                    ,        4,      2,      414,    "R/W",  0,      0,      1ull,   3ull},
9909         {"RESERVED_6_7"                ,        6,      2,      414,    "RAZ",  0,      1,      0ull,   0},
9910         {"L4_MAL"                      ,        8,      1,      414,    "R/W",  0,      0,      1ull,   1ull},
9911         {"L4_PRT"                      ,        9,      1,      414,    "R/W",  0,      0,      1ull,   1ull},
9912         {"L4_CHK"                      ,        10,     1,      414,    "R/W",  0,      0,      1ull,   1ull},
9913         {"L4_LEN"                      ,        11,     1,      414,    "R/W",  0,      0,      1ull,   1ull},
9914         {"TCP_FLAG"                    ,        12,     1,      414,    "R/W",  0,      0,      1ull,   1ull},
9915         {"L2_MAL"                      ,        13,     1,      414,    "R/W",  0,      0,      1ull,   1ull},
9916         {"VS_QOS"                      ,        14,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
9917         {"VS_WQE"                      ,        15,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
9918         {"IGNRS"                       ,        16,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
9919         {"RESERVED_17_63"              ,        17,     47,     414,    "RAZ",  0,      0,      0ull,   0ull},
9920         {"PKTDRP"                      ,        0,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
9921         {"CRCERR"                      ,        1,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
9922         {"BCKPRS"                      ,        2,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
9923         {"PRTNXA"                      ,        3,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
9924         {"BADTAG"                      ,        4,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
9925         {"SKPRUNT"                     ,        5,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
9926         {"TODOOVR"                     ,        6,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
9927         {"FEPERR"                      ,        7,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
9928         {"BEPERR"                      ,        8,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
9929         {"RESERVED_9_63"               ,        9,      55,     415,    "RAZ",  1,      1,      0,      0},
9930         {"PKTDRP"                      ,        0,      1,      416,    "R/W1C",        0,      0,      0ull,   0ull},
9931         {"CRCERR"                      ,        1,      1,      416,    "R/W1C",        0,      0,      0ull,   0ull},
9932         {"BCKPRS"                      ,        2,      1,      416,    "R/W1C",        0,      0,      0ull,   0ull},
9933         {"PRTNXA"                      ,        3,      1,      416,    "R/W1C",        0,      0,      0ull,   0ull},
9934         {"BADTAG"                      ,        4,      1,      416,    "R/W1C",        0,      0,      0ull,   0ull},
9935         {"SKPRUNT"                     ,        5,      1,      416,    "R/W1C",        0,      0,      0ull,   0ull},
9936         {"TODOOVR"                     ,        6,      1,      416,    "R/W1C",        0,      0,      0ull,   0ull},
9937         {"FEPERR"                      ,        7,      1,      416,    "R/W1C",        0,      0,      0ull,   0ull},
9938         {"BEPERR"                      ,        8,      1,      416,    "R/W1C",        0,      0,      0ull,   0ull},
9939         {"RESERVED_9_63"               ,        9,      55,     416,    "RAZ",  1,      1,      0,      0},
9940         {"OFFSET"                      ,        0,      3,      417,    "R/W",  0,      0,      0ull,   0ull},
9941         {"RESERVED_3_63"               ,        3,      61,     417,    "RAZ",  1,      1,      0,      0},
9942         {"SKIP"                        ,        0,      7,      418,    "R/W",  0,      0,      0ull,   0ull},
9943         {"RESERVED_7_7"                ,        7,      1,      418,    "RAZ",  1,      1,      0,      0},
9944         {"MODE"                        ,        8,      2,      418,    "R/W",  0,      0,      0ull,   0ull},
9945         {"RESERVED_10_15"              ,        10,     6,      418,    "RAZ",  1,      1,      0,      0},
9946         {"QOS_VLAN"                    ,        16,     1,      418,    "R/W",  0,      0,      0ull,   0ull},
9947         {"QOS_DIFF"                    ,        17,     1,      418,    "R/W",  0,      0,      0ull,   0ull},
9948         {"RESERVED_18_19"              ,        18,     2,      418,    "RAZ",  0,      0,      0ull,   0ull},
9949         {"QOS_WAT"                     ,        20,     4,      418,    "R/W",  0,      0,      0ull,   0ull},
9950         {"QOS"                         ,        24,     3,      418,    "R/W",  0,      0,      0ull,   0ull},
9951         {"RESERVED_27_27"              ,        27,     1,      418,    "RAZ",  1,      1,      0,      0},
9952         {"GRP_WAT"                     ,        28,     4,      418,    "R/W",  0,      0,      0ull,   0ull},
9953         {"INST_HDR"                    ,        32,     1,      418,    "R/W",  0,      0,      0ull,   0ull},
9954         {"DYN_RS"                      ,        33,     1,      418,    "R/W",  0,      0,      0ull,   0ull},
9955         {"TAG_INC"                     ,        34,     2,      418,    "R/W",  0,      0,      0ull,   0ull},
9956         {"RAWDRP"                      ,        36,     1,      418,    "R/W",  0,      0,      0ull,   0ull},
9957         {"RESERVED_37_63"              ,        37,     27,     418,    "RAZ",  1,      1,      0,      0},
9958         {"GRP"                         ,        0,      4,      419,    "R/W",  0,      0,      0ull,   0ull},
9959         {"NON_TAG_TYPE"                ,        4,      2,      419,    "R/W",  0,      0,      0ull,   0ull},
9960         {"IP4_TAG_TYPE"                ,        6,      2,      419,    "R/W",  0,      0,      0ull,   0ull},
9961         {"IP6_TAG_TYPE"                ,        8,      2,      419,    "R/W",  0,      0,      0ull,   0ull},
9962         {"TCP4_TAG_TYPE"               ,        10,     2,      419,    "R/W",  0,      0,      0ull,   0ull},
9963         {"TCP6_TAG_TYPE"               ,        12,     2,      419,    "R/W",  0,      0,      0ull,   0ull},
9964         {"IP4_SRC_FLAG"                ,        14,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9965         {"IP6_SRC_FLAG"                ,        15,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9966         {"IP4_DST_FLAG"                ,        16,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9967         {"IP6_DST_FLAG"                ,        17,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9968         {"IP4_PCTL_FLAG"               ,        18,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9969         {"IP6_NXTH_FLAG"               ,        19,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9970         {"IP4_SPRT_FLAG"               ,        20,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9971         {"IP6_SPRT_FLAG"               ,        21,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9972         {"IP4_DPRT_FLAG"               ,        22,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9973         {"IP6_DPRT_FLAG"               ,        23,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9974         {"INC_PRT_FLAG"                ,        24,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9975         {"INC_VLAN"                    ,        25,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9976         {"INC_VS"                      ,        26,     2,      419,    "R/W",  0,      0,      0ull,   0ull},
9977         {"TAG_MODE"                    ,        28,     2,      419,    "R/W",  0,      0,      0ull,   0ull},
9978         {"RESERVED_30_30"              ,        30,     1,      419,    "RAZ",  0,      0,      0ull,   0ull},
9979         {"GRPTAG"                      ,        31,     1,      419,    "R/W",  0,      0,      0ull,   0ull},
9980         {"GRPTAGMASK"                  ,        32,     4,      419,    "R/W",  0,      0,      0ull,   0ull},
9981         {"GRPTAGBASE"                  ,        36,     4,      419,    "R/W",  0,      0,      0ull,   0ull},
9982         {"RESERVED_40_63"              ,        40,     24,     419,    "RAZ",  1,      1,      0,      0},
9983         {"QOS"                         ,        0,      3,      420,    "R/W",  0,      0,      0ull,   0ull},
9984         {"RESERVED_3_63"               ,        3,      61,     420,    "RAZ",  1,      1,      0,      0},
9985         {"QOS"                         ,        0,      3,      421,    "R/W",  0,      0,      0ull,   0ull},
9986         {"RESERVED_3_63"               ,        3,      61,     421,    "RAZ",  1,      1,      0,      0},
9987         {"MATCH_VALUE"                 ,        0,      16,     422,    "R/W",  0,      0,      0ull,   0ull},
9988         {"MATCH_TYPE"                  ,        16,     2,      422,    "R/W",  0,      0,      0ull,   0ull},
9989         {"RESERVED_18_19"              ,        18,     2,      422,    "RAZ",  1,      1,      0,      0},
9990         {"QOS"                         ,        20,     3,      422,    "R/W",  0,      0,      0ull,   0ull},
9991         {"RESERVED_23_23"              ,        23,     1,      422,    "RAZ",  1,      1,      0,      0},
9992         {"GRP"                         ,        24,     4,      422,    "R/W",  0,      0,      0ull,   0ull},
9993         {"RESERVED_28_31"              ,        28,     4,      422,    "RAZ",  1,      1,      0,      0},
9994         {"MASK"                        ,        32,     16,     422,    "R/W",  0,      0,      0ull,   0ull},
9995         {"RESERVED_48_63"              ,        48,     16,     422,    "RAZ",  1,      1,      0,      0},
9996         {"WORD"                        ,        0,      56,     423,    "R/W",  0,      0,      0ull,   0ull},
9997         {"RESERVED_56_63"              ,        56,     8,      423,    "RAZ",  1,      1,      0,      0},
9998         {"RST"                         ,        0,      1,      424,    "R/W",  0,      0,      0ull,   0ull},
9999         {"RESERVED_1_63"               ,        1,      63,     424,    "RAZ",  1,      1,      0,      0},
10000         {"DRP_OCTS"                    ,        0,      32,     425,    "R/W",  0,      1,      0ull,   0},
10001         {"DRP_PKTS"                    ,        32,     32,     425,    "R/W",  0,      1,      0ull,   0},
10002         {"OCTS"                        ,        0,      48,     426,    "R/W",  0,      1,      0ull,   0},
10003         {"RESERVED_48_63"              ,        48,     16,     426,    "RAZ",  1,      1,      0,      0},
10004         {"RAW"                         ,        0,      32,     427,    "R/W",  0,      1,      0ull,   0},
10005         {"PKTS"                        ,        32,     32,     427,    "R/W",  0,      1,      0ull,   0},
10006         {"MCST"                        ,        0,      32,     428,    "R/W",  0,      1,      0ull,   0},
10007         {"BCST"                        ,        32,     32,     428,    "R/W",  0,      1,      0ull,   0},
10008         {"H64"                         ,        0,      32,     429,    "R/W",  0,      1,      0ull,   0},
10009         {"H65TO127"                    ,        32,     32,     429,    "R/W",  0,      1,      0ull,   0},
10010         {"H128TO255"                   ,        0,      32,     430,    "R/W",  0,      1,      0ull,   0},
10011         {"H256TO511"                   ,        32,     32,     430,    "R/W",  0,      1,      0ull,   0},
10012         {"H512TO1023"                  ,        0,      32,     431,    "R/W",  0,      1,      0ull,   0},
10013         {"H1024TO1518"                 ,        32,     32,     431,    "R/W",  0,      1,      0ull,   0},
10014         {"H1519"                       ,        0,      32,     432,    "R/W",  0,      1,      0ull,   0},
10015         {"FCS"                         ,        32,     32,     432,    "R/W",  0,      1,      0ull,   0},
10016         {"UNDERSZ"                     ,        0,      32,     433,    "R/W",  0,      1,      0ull,   0},
10017         {"FRAG"                        ,        32,     32,     433,    "R/W",  0,      1,      0ull,   0},
10018         {"OVERSZ"                      ,        0,      32,     434,    "R/W",  0,      1,      0ull,   0},
10019         {"JABBER"                      ,        32,     32,     434,    "R/W",  0,      1,      0ull,   0},
10020         {"RDCLR"                       ,        0,      1,      435,    "R/W",  0,      0,      1ull,   1ull},
10021         {"RESERVED_1_63"               ,        1,      63,     435,    "RAZ",  1,      1,      0,      0},
10022         {"ERRS"                        ,        0,      16,     436,    "R/W",  0,      1,      0ull,   0},
10023         {"RESERVED_16_63"              ,        16,     48,     436,    "RAZ",  1,      1,      0,      0},
10024         {"OCTS"                        ,        0,      48,     437,    "R/W",  0,      1,      0ull,   0},
10025         {"RESERVED_48_63"              ,        48,     16,     437,    "RAZ",  1,      1,      0,      0},
10026         {"PKTS"                        ,        0,      32,     438,    "R/W",  0,      1,      0ull,   0},
10027         {"RESERVED_32_63"              ,        32,     32,     438,    "RAZ",  1,      1,      0,      0},
10028         {"EN"                          ,        0,      8,      439,    "R/W",  0,      0,      0ull,   0ull},
10029         {"RESERVED_8_63"               ,        8,      56,     439,    "RAZ",  1,      1,      0,      0},
10030         {"MASK"                        ,        0,      16,     440,    "R/W",  0,      0,      0ull,   0ull},
10031         {"RESERVED_16_63"              ,        16,     48,     440,    "RAZ",  1,      1,      0,      0},
10032         {"SRC"                         ,        0,      16,     441,    "R/W",  0,      0,      0ull,   0ull},
10033         {"DST"                         ,        16,     16,     441,    "R/W",  0,      0,      0ull,   0ull},
10034         {"RESERVED_32_63"              ,        32,     32,     441,    "RAZ",  1,      1,      0,      0},
10035         {"ENTRY"                       ,        0,      62,     442,    "RO",   1,      1,      0,      0},
10036         {"RESERVED_62_62"              ,        62,     1,      442,    "RAZ",  1,      1,      0,      0},
10037         {"VAL"                         ,        63,     1,      442,    "RO",   1,      1,      0,      0},
10038         {"COUNT"                       ,        0,      32,     443,    "R/W1C",        1,      0,      0,      0ull},
10039         {"RESERVED_32_63"              ,        32,     32,     443,    "RAZ",  1,      1,      0,      0},
10040         {"COUNT"                       ,        0,      48,     444,    "R/W1C",        1,      0,      0,      0ull},
10041         {"RESERVED_48_63"              ,        48,     16,     444,    "RAZ",  1,      1,      0,      0},
10042         {"SIZE"                        ,        0,      16,     445,    "RO",   1,      0,      0,      0ull},
10043         {"SEGS"                        ,        16,     6,      445,    "RO",   1,      0,      0,      0ull},
10044         {"CMD"                         ,        22,     14,     445,    "RO",   1,      0,      0,      0ull},
10045         {"FAU"                         ,        36,     28,     445,    "RO",   1,      0,      0,      0ull},
10046         {"PTR"                         ,        0,      40,     446,    "RO",   1,      0,      0,      0ull},
10047         {"SIZE"                        ,        40,     16,     446,    "RO",   1,      0,      0,      0ull},
10048         {"POOL"                        ,        56,     3,      446,    "RO",   1,      0,      0,      0ull},
10049         {"BACK"                        ,        59,     4,      446,    "RO",   1,      0,      0,      0ull},
10050         {"I"                           ,        63,     1,      446,    "RO",   1,      0,      0,      0ull},
10051         {"SIZE"                        ,        0,      16,     447,    "RO",   1,      0,      0,      0ull},
10052         {"SEGS"                        ,        16,     6,      447,    "RO",   1,      0,      0,      0ull},
10053         {"CMD"                         ,        22,     14,     447,    "RO",   1,      0,      0,      0ull},
10054         {"FAU"                         ,        36,     28,     447,    "RO",   1,      0,      0,      0ull},
10055         {"PTR"                         ,        0,      40,     448,    "RO",   1,      0,      0,      0ull},
10056         {"SIZE"                        ,        40,     16,     448,    "RO",   1,      0,      0,      0ull},
10057         {"POOL"                        ,        56,     3,      448,    "RO",   1,      0,      0,      0ull},
10058         {"BACK"                        ,        59,     4,      448,    "RO",   1,      0,      0,      0ull},
10059         {"I"                           ,        63,     1,      448,    "RO",   1,      0,      0,      0ull},
10060         {"DATA"                        ,        0,      64,     449,    "RO",   1,      0,      0,      0ull},
10061         {"WIDX2"                       ,        0,      17,     450,    "RO",   1,      0,      0,      0ull},
10062         {"RIDX2"                       ,        17,     17,     450,    "RO",   1,      0,      0,      0ull},
10063         {"WIDX"                        ,        34,     17,     450,    "RO",   1,      0,      0,      0ull},
10064         {"RESERVED_51_63"              ,        51,     13,     450,    "RAZ",  1,      0,      0,      0ull},
10065         {"RIDX"                        ,        0,      17,     451,    "RO",   1,      0,      0,      0ull},
10066         {"RESERVED_17_63"              ,        17,     47,     451,    "RAZ",  1,      0,      0,      0ull},
10067         {"PTR"                         ,        0,      40,     452,    "RO",   1,      0,      0,      0ull},
10068         {"SIZE"                        ,        40,     16,     452,    "RO",   1,      0,      0,      0ull},
10069         {"POOL"                        ,        56,     3,      452,    "RO",   1,      0,      0,      0ull},
10070         {"BACK"                        ,        59,     4,      452,    "RO",   1,      0,      0,      0ull},
10071         {"I"                           ,        63,     1,      452,    "RO",   1,      0,      0,      0ull},
10072         {"PTR"                         ,        0,      40,     453,    "RO",   1,      0,      0,      0ull},
10073         {"SIZE"                        ,        40,     16,     453,    "RO",   1,      0,      0,      0ull},
10074         {"POOL"                        ,        56,     3,      453,    "RO",   1,      0,      0,      0ull},
10075         {"BACK"                        ,        59,     4,      453,    "RO",   1,      0,      0,      0ull},
10076         {"I"                           ,        63,     1,      453,    "RO",   1,      0,      0,      0ull},
10077         {"DATA"                        ,        0,      64,     454,    "RO",   1,      0,      0,      0ull},
10078         {"MAJOR"                       ,        0,      4,      455,    "RO",   1,      0,      0,      0ull},
10079         {"MINOR"                       ,        4,      2,      455,    "RO",   1,      0,      0,      0ull},
10080         {"WAIT"                        ,        6,      1,      455,    "RO",   1,      0,      0,      0ull},
10081         {"QID_BASE"                    ,        7,      7,      455,    "RO",   1,      0,      0,      0ull},
10082         {"QID_OFF"                     ,        14,     3,      455,    "RO",   1,      0,      0,      0ull},
10083         {"QCB_RIDX"                    ,        17,     5,      455,    "RO",   1,      0,      0,      0ull},
10084         {"QOS"                         ,        22,     3,      455,    "RO",   1,      0,      0,      0ull},
10085         {"ACTIVE"                      ,        25,     1,      455,    "RO",   1,      0,      0,      0ull},
10086         {"CHK_MODE"                    ,        26,     1,      455,    "RO",   1,      0,      0,      0ull},
10087         {"RESERVED_27_27"              ,        27,     1,      455,    "RAZ",  1,      0,      0,      0ull},
10088         {"CBUF_FRE"                    ,        28,     1,      455,    "RO",   1,      0,      0,      0ull},
10089         {"XFER_DWR"                    ,        29,     1,      455,    "RO",   1,      0,      0,      0ull},
10090         {"XFER_WOR"                    ,        30,     1,      455,    "RO",   1,      0,      0,      0ull},
10091         {"UID"                         ,        31,     1,      455,    "RO",   1,      0,      0,      0ull},
10092         {"CMND_SIZ"                    ,        32,     16,     455,    "RO",   1,      0,      0,      0ull},
10093         {"DWRI_CNT"                    ,        48,     13,     455,    "RO",   1,      0,      0,      0ull},
10094         {"DWRI_LEN"                    ,        61,     1,      455,    "RO",   1,      0,      0,      0ull},
10095         {"DWRI_SOP"                    ,        62,     1,      455,    "RO",   1,      0,      0,      0ull},
10096         {"DWRI_MOD"                    ,        63,     1,      455,    "RO",   1,      0,      0,      0ull},
10097         {"DWRI_MOD"                    ,        0,      2,      456,    "RO",   1,      0,      0,      0ull},
10098         {"DWRI_UID"                    ,        2,      1,      456,    "RO",   1,      0,      0,      0ull},
10099         {"DWRI_CHK"                    ,        3,      1,      456,    "RO",   1,      0,      0,      0ull},
10100         {"WORK_MIN"                    ,        4,      3,      456,    "RO",   1,      0,      0,      0ull},
10101         {"STATIC_P"                    ,        7,      1,      456,    "RO",   1,      0,      0,      0ull},
10102         {"QID_OFFM"                    ,        8,      3,      456,    "RO",   1,      0,      0,      0ull},
10103         {"RESERVED_11_63"              ,        11,     53,     456,    "RAZ",  1,      0,      0,      0ull},
10104         {"SIZE"                        ,        0,      16,     457,    "RO",   1,      0,      0,      0ull},
10105         {"START"                       ,        16,     33,     457,    "RO",   1,      0,      0,      0ull},
10106         {"DWB"                         ,        49,     9,      457,    "RO",   1,      0,      0,      0ull},
10107         {"RESERVED_58_63"              ,        58,     6,      457,    "RAZ",  1,      0,      0,      0ull},
10108         {"QCB_RIDX"                    ,        0,      6,      458,    "RO",   1,      0,      0,      0ull},
10109         {"QCB_WIDX"                    ,        6,      6,      458,    "RO",   1,      0,      0,      0ull},
10110         {"BUF_PTR"                     ,        12,     33,     458,    "RO",   1,      0,      0,      0ull},
10111         {"BUF_SIZ"                     ,        45,     13,     458,    "RO",   1,      0,      0,      0ull},
10112         {"TAIL"                        ,        58,     1,      458,    "RO",   1,      0,      0,      0ull},
10113         {"QOS"                         ,        59,     5,      458,    "RO",   1,      0,      0,      0ull},
10114         {"QOS"                         ,        0,      3,      459,    "RO",   1,      0,      0,      0ull},
10115         {"STATIC_Q"                    ,        3,      1,      459,    "RO",   1,      0,      0,      0ull},
10116         {"S_TAIL"                      ,        4,      1,      459,    "RO",   1,      0,      0,      0ull},
10117         {"RESERVED_5_7"                ,        5,      3,      459,    "RAZ",  1,      0,      0,      0ull},
10118         {"DOORBELL"                    ,        8,      20,     459,    "RO",   1,      0,      0,      0ull},
10119         {"RESERVED_28_63"              ,        28,     36,     459,    "RAZ",  1,      0,      0,      0ull},
10120         {"QUEUE"                       ,        0,      7,      460,    "R/W",  1,      0,      0,      0ull},
10121         {"PORT"                        ,        7,      6,      460,    "WR0",  1,      0,      0,      0ull},
10122         {"INDEX"                       ,        13,     3,      460,    "WR0",  1,      0,      0,      0ull},
10123         {"TAIL"                        ,        16,     1,      460,    "R/W",  1,      0,      0,      0ull},
10124         {"BUF_PTR"                     ,        17,     36,     460,    "R/W",  1,      0,      0,      0ull},
10125         {"QOS_MASK"                    ,        53,     8,      460,    "R/W",  1,      0,      0,      0ull},
10126         {"STATIC_Q"                    ,        61,     1,      460,    "WR0",  1,      0,      0,      0ull},
10127         {"STATIC_P"                    ,        62,     1,      460,    "WR0",  1,      0,      0,      0ull},
10128         {"S_TAIL"                      ,        63,     1,      460,    "WR0",  1,      0,      0,      0ull},
10129         {"QID"                         ,        0,      7,      461,    "R/W",  1,      0,      0,      0ull},
10130         {"PID"                         ,        7,      6,      461,    "WR0",  1,      0,      0,      0ull},
10131         {"RESERVED_13_52"              ,        13,     40,     461,    "RAZ",  1,      0,      0,      0ull},
10132         {"QOS_MASK"                    ,        53,     8,      461,    "R/W",  1,      0,      0,      0ull},
10133         {"RESERVED_61_63"              ,        61,     3,      461,    "RAZ",  1,      0,      0,      0ull},
10134         {"PSB"                         ,        0,      7,      462,    "RO",   1,      0,      0,      0ull},
10135         {"PDB"                         ,        7,      4,      462,    "RO",   1,      0,      0,      0ull},
10136         {"QCB"                         ,        11,     2,      462,    "RO",   1,      0,      0,      0ull},
10137         {"QSB"                         ,        13,     2,      462,    "RO",   1,      0,      0,      0ull},
10138         {"CHK"                         ,        15,     1,      462,    "RO",   1,      0,      0,      0ull},
10139         {"CRC"                         ,        16,     1,      462,    "RO",   1,      0,      0,      0ull},
10140         {"OUT"                         ,        17,     1,      462,    "RO",   1,      0,      0,      0ull},
10141         {"NCB"                         ,        18,     1,      462,    "RO",   1,      0,      0,      0ull},
10142         {"WIF"                         ,        19,     1,      462,    "RO",   1,      0,      0,      0ull},
10143         {"RIF"                         ,        20,     1,      462,    "RO",   1,      0,      0,      0ull},
10144         {"COUNT"                       ,        21,     1,      462,    "RO",   1,      0,      0,      0ull},
10145         {"PSB2"                        ,        22,     5,      462,    "RO",   1,      0,      0,      0ull},
10146         {"RESERVED_27_63"              ,        27,     37,     462,    "RAZ",  1,      0,      0,      0ull},
10147         {"SIZE"                        ,        0,      13,     463,    "R/W",  0,      0,      0ull,   0ull},
10148         {"RESERVED_13_19"              ,        13,     7,      463,    "RAZ",  0,      0,      0ull,   0ull},
10149         {"POOL"                        ,        20,     3,      463,    "R/W",  0,      0,      0ull,   0ull},
10150         {"RESERVED_23_63"              ,        23,     41,     463,    "RAZ",  1,      0,      0,      0ull},
10151         {"ASSERTS"                     ,        0,      17,     464,    "RO",   0,      0,      0ull,   0ull},
10152         {"RESERVED_17_63"              ,        17,     47,     464,    "RAZ",  1,      0,      0,      0ull},
10153         {"PARITY"                      ,        0,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
10154         {"DOORBELL"                    ,        1,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
10155         {"RESERVED_2_63"               ,        2,      62,     465,    "RAZ",  1,      0,      0,      0ull},
10156         {"ENA_PKO"                     ,        0,      1,      466,    "R/W",  0,      0,      0ull,   0ull},
10157         {"ENA_DWB"                     ,        1,      1,      466,    "R/W",  0,      0,      0ull,   0ull},
10158         {"STORE_BE"                    ,        2,      1,      466,    "R/W",  0,      0,      0ull,   0ull},
10159         {"RESET"                       ,        3,      1,      466,    "RAZ",  0,      0,      0ull,   0ull},
10160         {"RESERVED_4_63"               ,        4,      60,     466,    "RAZ",  1,      0,      0,      0ull},
10161         {"MODE0"                       ,        0,      3,      467,    "R/W",  0,      0,      0ull,   0ull},
10162         {"MODE1"                       ,        3,      3,      467,    "R/W",  0,      0,      0ull,   0ull},
10163         {"RESERVED_6_63"               ,        6,      58,     467,    "RAZ",  1,      0,      0,      0ull},
10164         {"PARITY"                      ,        0,      1,      468,    "R/W",  0,      0,      0ull,   0ull},
10165         {"DOORBELL"                    ,        1,      1,      468,    "R/W",  0,      0,      0ull,   0ull},
10166         {"RESERVED_2_63"               ,        2,      62,     468,    "RAZ",  1,      0,      0,      0ull},
10167         {"MODE"                        ,        0,      2,      469,    "R/W",  0,      0,      0ull,   0ull},
10168         {"RESERVED_2_63"               ,        2,      62,     469,    "RAZ",  1,      0,      0,      0ull},
10169         {"INDEX"                       ,        0,      8,      470,    "R/W",  0,      0,      0ull,   0ull},
10170         {"INC"                         ,        8,      8,      470,    "R/W",  0,      0,      0ull,   0ull},
10171         {"RESERVED_16_63"              ,        16,     48,     470,    "RAZ",  1,      0,      0,      0ull},
10172         {"ADR"                         ,        0,      1,      471,    "RO",   0,      0,      0ull,   0ull},
10173         {"PEND"                        ,        1,      1,      471,    "RO",   0,      0,      0ull,   0ull},
10174         {"NBR0"                        ,        2,      1,      471,    "RO",   0,      0,      0ull,   0ull},
10175         {"NBR1"                        ,        3,      1,      471,    "RO",   0,      0,      0ull,   0ull},
10176         {"FIDX"                        ,        4,      1,      471,    "RO",   0,      0,      0ull,   0ull},
10177         {"INDEX"                       ,        5,      1,      471,    "RO",   0,      0,      0ull,   0ull},
10178         {"NBT0"                        ,        6,      1,      471,    "RO",   0,      0,      0ull,   0ull},
10179         {"NBT1"                        ,        7,      1,      471,    "RO",   0,      0,      0ull,   0ull},
10180         {"CAM"                         ,        8,      1,      471,    "RO",   0,      0,      0ull,   0ull},
10181         {"RESERVED_9_15"               ,        9,      7,      471,    "RAZ",  1,      1,      0,      0},
10182         {"PP"                          ,        16,     2,      471,    "RO",   0,      0,      0ull,   0ull},
10183         {"RESERVED_18_63"              ,        18,     46,     471,    "RAZ",  1,      1,      0,      0},
10184         {"DS_PC"                       ,        0,      32,     472,    "R/W1C",        0,      1,      0ull,   0},
10185         {"RESERVED_32_63"              ,        32,     32,     472,    "RAZ",  1,      1,      0,      0},
10186         {"SBE"                         ,        0,      1,      473,    "R/W1C",        0,      0,      0ull,   0ull},
10187         {"DBE"                         ,        1,      1,      473,    "R/W1C",        0,      0,      0ull,   0ull},
10188         {"SBE_IE"                      ,        2,      1,      473,    "R/W",  0,      1,      0ull,   0},
10189         {"DBE_IE"                      ,        3,      1,      473,    "R/W",  0,      1,      0ull,   0},
10190         {"SYN"                         ,        4,      5,      473,    "RO",   1,      1,      0,      0},
10191         {"RESERVED_9_11"               ,        9,      3,      473,    "RAZ",  1,      1,      0,      0},
10192         {"RPE"                         ,        12,     1,      473,    "R/W1C",        0,      0,      0ull,   0ull},
10193         {"RPE_IE"                      ,        13,     1,      473,    "R/W",  0,      1,      0ull,   0},
10194         {"RESERVED_14_63"              ,        14,     50,     473,    "RAZ",  1,      1,      0,      0},
10195         {"NBR_THR"                     ,        0,      5,      474,    "R/W",  0,      0,      2ull,   2ull},
10196         {"PFR_DIS"                     ,        5,      1,      474,    "R/W",  0,      0,      0ull,   0ull},
10197         {"RESERVED_6_63"               ,        6,      58,     474,    "RAZ",  1,      1,      0,      0},
10198         {"IQ_CNT"                      ,        0,      32,     475,    "RO",   0,      1,      0ull,   0},
10199         {"RESERVED_32_63"              ,        32,     32,     475,    "RAZ",  1,      1,      0,      0},
10200         {"IQ_CNT"                      ,        0,      32,     476,    "RO",   0,      1,      0ull,   0},
10201         {"RESERVED_32_63"              ,        32,     32,     476,    "RAZ",  1,      1,      0,      0},
10202         {"NOS_CNT"                     ,        0,      9,      477,    "RO",   0,      1,      0ull,   0},
10203         {"RESERVED_9_63"               ,        9,      55,     477,    "RAZ",  1,      1,      0,      0},
10204         {"NW_TIM"                      ,        0,      10,     478,    "R/W",  0,      0,      0ull,   1023ull},
10205         {"RESERVED_10_63"              ,        10,     54,     478,    "RAZ",  1,      1,      0,      0},
10206         {"GRP_MSK"                     ,        0,      16,     479,    "R/W",  0,      0,      65535ull,       65535ull},
10207         {"RESERVED_16_63"              ,        16,     48,     479,    "RAZ",  1,      1,      0,      0},
10208         {"RND"                         ,        0,      8,      480,    "R/W",  0,      1,      255ull, 0},
10209         {"RND_P1"                      ,        8,      8,      480,    "R/W",  0,      1,      255ull, 0},
10210         {"RND_P2"                      ,        16,     8,      480,    "R/W",  0,      1,      255ull, 0},
10211         {"RND_P3"                      ,        24,     8,      480,    "R/W",  0,      1,      255ull, 0},
10212         {"RESERVED_32_63"              ,        32,     32,     480,    "RAZ",  1,      1,      0,      0},
10213         {"MIN_THR"                     ,        0,      8,      481,    "R/W",  0,      1,      0ull,   0},
10214         {"RESERVED_8_11"               ,        8,      4,      481,    "RAZ",  1,      1,      0,      0},
10215         {"MAX_THR"                     ,        12,     8,      481,    "R/W",  0,      1,      255ull, 0},
10216         {"RESERVED_20_23"              ,        20,     4,      481,    "RAZ",  1,      1,      0,      0},
10217         {"FREE_CNT"                    ,        24,     9,      481,    "RO",   0,      1,      249ull, 0},
10218         {"RESERVED_33_35"              ,        33,     3,      481,    "RAZ",  1,      1,      0,      0},
10219         {"BUF_CNT"                     ,        36,     9,      481,    "RO",   0,      1,      0ull,   0},
10220         {"RESERVED_45_47"              ,        45,     3,      481,    "RAZ",  1,      1,      0,      0},
10221         {"DES_CNT"                     ,        48,     9,      481,    "RO",   0,      1,      0ull,   0},
10222         {"RESERVED_57_63"              ,        57,     7,      481,    "RAZ",  1,      1,      0,      0},
10223         {"TS_PC"                       ,        0,      32,     482,    "R/W1C",        0,      1,      0ull,   0},
10224         {"RESERVED_32_63"              ,        32,     32,     482,    "RAZ",  1,      1,      0,      0},
10225         {"WA_PC"                       ,        0,      32,     483,    "R/W1C",        0,      1,      0ull,   0},
10226         {"RESERVED_32_63"              ,        32,     32,     483,    "RAZ",  1,      1,      0,      0},
10227         {"WA_PC"                       ,        0,      32,     484,    "R/W1C",        0,      1,      0ull,   0},
10228         {"RESERVED_32_63"              ,        32,     32,     484,    "RAZ",  1,      1,      0,      0},
10229         {"WQ_INT"                      ,        0,      16,     485,    "R/W1C",        0,      1,      0ull,   0},
10230         {"IQ_DIS"                      ,        16,     16,     485,    "R/W1", 0,      1,      0ull,   0},
10231         {"RESERVED_32_63"              ,        32,     32,     485,    "RAZ",  1,      1,      0,      0},
10232         {"IQ_CNT"                      ,        0,      9,      486,    "RO",   0,      1,      0ull,   0},
10233         {"RESERVED_9_11"               ,        9,      3,      486,    "RAZ",  1,      1,      0,      0},
10234         {"DS_CNT"                      ,        12,     9,      486,    "RO",   0,      1,      0ull,   0},
10235         {"RESERVED_21_23"              ,        21,     3,      486,    "RAZ",  1,      1,      0,      0},
10236         {"TC_CNT"                      ,        24,     4,      486,    "RO",   0,      1,      0ull,   0},
10237         {"RESERVED_28_63"              ,        28,     36,     486,    "RAZ",  1,      1,      0,      0},
10238         {"RESERVED_0_7"                ,        0,      8,      487,    "RAZ",  1,      1,      0,      0},
10239         {"PC_THR"                      ,        8,      20,     487,    "R/W",  0,      1,      0ull,   0},
10240         {"RESERVED_28_31"              ,        28,     4,      487,    "RAZ",  1,      1,      0,      0},
10241         {"PC"                          ,        32,     28,     487,    "RO",   0,      1,      0ull,   0},
10242         {"RESERVED_60_63"              ,        60,     4,      487,    "RAZ",  1,      1,      0,      0},
10243         {"IQ_THR"                      ,        0,      8,      488,    "R/W",  0,      1,      0ull,   0},
10244         {"RESERVED_8_11"               ,        8,      4,      488,    "RAZ",  1,      1,      0,      0},
10245         {"DS_THR"                      ,        12,     8,      488,    "R/W",  0,      1,      0ull,   0},
10246         {"RESERVED_20_23"              ,        20,     4,      488,    "RAZ",  1,      1,      0,      0},
10247         {"TC_THR"                      ,        24,     4,      488,    "R/W",  0,      1,      0ull,   0},
10248         {"TC_EN"                       ,        28,     1,      488,    "R/W",  0,      1,      0ull,   0},
10249         {"RESERVED_29_63"              ,        29,     35,     488,    "RAZ",  1,      1,      0,      0},
10250         {"WS_PC"                       ,        0,      32,     489,    "R/W1C",        0,      1,      0ull,   0},
10251         {"RESERVED_32_63"              ,        32,     32,     489,    "RAZ",  1,      1,      0,      0},
10252         {"MEM"                         ,        0,      1,      490,    "RO",   0,      0,      0ull,   0ull},
10253         {"RRC"                         ,        1,      1,      490,    "RO",   0,      0,      0ull,   0ull},
10254         {"RESERVED_2_63"               ,        2,      62,     490,    "RAZ",  1,      1,      0,      0},
10255         {"ENT_EN"                      ,        0,      1,      491,    "R/W",  0,      0,      0ull,   0ull},
10256         {"RNG_EN"                      ,        1,      1,      491,    "R/W",  0,      0,      0ull,   0ull},
10257         {"RNM_RST"                     ,        2,      1,      491,    "R/W",  0,      0,      0ull,   0ull},
10258         {"RNG_RST"                     ,        3,      1,      491,    "R/W",  0,      0,      0ull,   0ull},
10259         {"RESERVED_4_63"               ,        4,      60,     491,    "RAZ",  1,      1,      0,      0},
10260         {"PHASE"                       ,        0,      8,      492,    "R/W",  0,      0,      100ull, 100ull},
10261         {"SAMPLE"                      ,        8,      4,      492,    "R/W",  0,      0,      2ull,   2ull},
10262         {"PREAMBLE"                    ,        12,     1,      492,    "R/W",  0,      0,      1ull,   1ull},
10263         {"CLK_IDLE"                    ,        13,     1,      492,    "R/W",  0,      0,      0ull,   0ull},
10264         {"RESERVED_14_14"              ,        14,     1,      492,    "RAZ",  1,      1,      0,      0},
10265         {"SAMPLE_MODE"                 ,        15,     1,      492,    "RAZ",  0,      0,      0ull,   0ull},
10266         {"SAMPLE_HI"                   ,        16,     5,      492,    "R/W",  0,      0,      0ull,   0ull},
10267         {"RESERVED_21_63"              ,        21,     43,     492,    "RAZ",  1,      1,      0,      0},
10268         {"REG_ADR"                     ,        0,      5,      493,    "R/W",  0,      1,      0ull,   0},
10269         {"RESERVED_5_7"                ,        5,      3,      493,    "RAZ",  1,      1,      0,      0},
10270         {"PHY_ADR"                     ,        8,      5,      493,    "R/W",  0,      1,      0ull,   0},
10271         {"RESERVED_13_15"              ,        13,     3,      493,    "RAZ",  1,      1,      0,      0},
10272         {"PHY_OP"                      ,        16,     1,      493,    "R/W",  0,      1,      0ull,   0},
10273         {"RESERVED_17_63"              ,        17,     47,     493,    "RAZ",  1,      1,      0,      0},
10274         {"EN"                          ,        0,      1,      494,    "R/W",  0,      0,      0ull,   1ull},
10275         {"RESERVED_1_63"               ,        1,      63,     494,    "RAZ",  1,      1,      0,      0},
10276         {"DAT"                         ,        0,      16,     495,    "RO",   0,      1,      0ull,   0},
10277         {"VAL"                         ,        16,     1,      495,    "RO",   0,      1,      0ull,   0},
10278         {"PENDING"                     ,        17,     1,      495,    "RO",   0,      1,      0ull,   0},
10279         {"RESERVED_18_63"              ,        18,     46,     495,    "RAZ",  1,      1,      0,      0},
10280         {"DAT"                         ,        0,      16,     496,    "R/W",  0,      1,      0ull,   0},
10281         {"VAL"                         ,        16,     1,      496,    "RO",   0,      1,      0ull,   0},
10282         {"PENDING"                     ,        17,     1,      496,    "RO",   0,      1,      0ull,   0},
10283         {"RESERVED_18_63"              ,        18,     46,     496,    "RAZ",  1,      1,      0,      0},
10284         {"INTERVAL"                    ,        0,      22,     497,    "RO",   1,      0,      0,      0ull},
10285         {"RESERVED_22_23"              ,        22,     2,      497,    "RAZ",  1,      0,      0,      0ull},
10286         {"COUNT"                       ,        24,     22,     497,    "RO",   1,      0,      0,      0ull},
10287         {"RESERVED_46_46"              ,        46,     1,      497,    "RAZ",  1,      0,      0,      0ull},
10288         {"ENA"                         ,        47,     1,      497,    "RO",   1,      0,      0,      0ull},
10289         {"RESERVED_48_63"              ,        48,     16,     497,    "RAZ",  1,      0,      0,      0ull},
10290         {"BSIZE"                       ,        0,      20,     498,    "RO",   1,      0,      0,      0ull},
10291         {"BASE"                        ,        20,     31,     498,    "RO",   1,      0,      0,      0ull},
10292         {"BUCKET"                      ,        51,     13,     498,    "RO",   1,      0,      0,      0ull},
10293         {"BUCKET"                      ,        0,      7,      499,    "RO",   1,      0,      0,      0ull},
10294         {"RESERVED_7_7"                ,        7,      1,      499,    "RAZ",  1,      0,      0,      0ull},
10295         {"CSIZE"                       ,        8,      13,     499,    "RO",   1,      0,      0,      0ull},
10296         {"CPOOL"                       ,        21,     3,      499,    "RO",   1,      0,      0,      0ull},
10297         {"RESERVED_24_63"              ,        24,     40,     499,    "RAZ",  1,      0,      0,      0ull},
10298         {"RING"                        ,        0,      4,      500,    "R/W",  0,      0,      0ull,   0ull},
10299         {"NUM_BUCKETS"                 ,        4,      20,     500,    "R/W",  0,      0,      0ull,   0ull},
10300         {"FIRST_BUCKET"                ,        24,     31,     500,    "R/W",  0,      0,      0ull,   0ull},
10301         {"RESERVED_55_63"              ,        55,     9,      500,    "RAZ",  1,      0,      0,      0ull},
10302         {"RING"                        ,        0,      4,      501,    "R/W",  0,      0,      0ull,   0ull},
10303         {"INTERVAL"                    ,        4,      22,     501,    "R/W",  0,      0,      0ull,   0ull},
10304         {"WORDS_PER_CHUNK"             ,        26,     13,     501,    "R/W",  0,      0,      0ull,   0ull},
10305         {"POOL"                        ,        39,     3,      501,    "R/W",  0,      0,      0ull,   0ull},
10306         {"ENABLE"                      ,        42,     1,      501,    "R/W",  0,      0,      0ull,   0ull},
10307         {"RESERVED_43_63"              ,        43,     21,     501,    "RAZ",  1,      0,      0,      0ull},
10308         {"CTL"                         ,        0,      1,      502,    "RO",   1,      0,      0,      0ull},
10309         {"NCB"                         ,        1,      1,      502,    "RO",   1,      0,      0,      0ull},
10310         {"STA"                         ,        2,      2,      502,    "RO",   1,      0,      0,      0ull},
10311         {"RESERVED_4_63"               ,        4,      60,     502,    "RAZ",  1,      0,      0,      0ull},
10312         {"MASK"                        ,        0,      16,     503,    "R/W1C",        0,      0,      0ull,   0ull},
10313         {"RESERVED_16_63"              ,        16,     48,     503,    "RAZ",  1,      0,      0,      0ull},
10314         {"ENABLE_TIMERS"               ,        0,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
10315         {"ENABLE_DWB"                  ,        1,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
10316         {"RESET"                       ,        2,      1,      504,    "RAZ",  0,      0,      0ull,   0ull},
10317         {"RESERVED_3_63"               ,        3,      61,     504,    "RAZ",  1,      0,      0,      0ull},
10318         {"MASK"                        ,        0,      16,     505,    "R/W",  0,      0,      0ull,   0ull},
10319         {"RESERVED_16_63"              ,        16,     48,     505,    "RAZ",  1,      0,      0,      0ull},
10320         {"INDEX"                       ,        0,      8,      506,    "R/W",  0,      0,      0ull,   0ull},
10321         {"INC"                         ,        8,      8,      506,    "R/W",  0,      0,      0ull,   0ull},
10322         {"RESERVED_16_63"              ,        16,     48,     506,    "RAZ",  1,      0,      0,      0ull},
10323         {"TDF0"                        ,        0,      1,      507,    "RO",   0,      0,      0ull,   0ull},
10324         {"TDF1"                        ,        1,      1,      507,    "RO",   0,      0,      0ull,   0ull},
10325         {"TCF"                         ,        2,      1,      507,    "RO",   0,      0,      0ull,   0ull},
10326         {"RESERVED_3_63"               ,        3,      61,     507,    "RAZ",  0,      0,      0ull,   0ull},
10327         {"ENA"                         ,        0,      1,      508,    "R/W",  0,      0,      0ull,   0ull},
10328         {"WRAP"                        ,        1,      1,      508,    "R/W",  0,      0,      0ull,   0ull},
10329         {"TRIG_CTL"                    ,        2,      2,      508,    "R/W",  0,      0,      0ull,   0ull},
10330         {"TIME_GRN"                    ,        4,      3,      508,    "R/W",  0,      0,      0ull,   0ull},
10331         {"FULL_THR"                    ,        7,      2,      508,    "R/W",  0,      0,      0ull,   0ull},
10332         {"CIU_TRG"                     ,        9,      1,      508,    "R/W",  0,      0,      0ull,   0ull},
10333         {"CIU_THR"                     ,        10,     1,      508,    "R/W",  0,      0,      0ull,   0ull},
10334         {"MCD0_TRG"                    ,        11,     1,      508,    "R/W",  0,      0,      0ull,   0ull},
10335         {"MCD0_THR"                    ,        12,     1,      508,    "R/W",  0,      0,      0ull,   0ull},
10336         {"MCD0_ENA"                    ,        13,     1,      508,    "R/W",  0,      0,      0ull,   0ull},
10337         {"IGNORE_O"                    ,        14,     1,      508,    "R/W",  0,      0,      0ull,   0ull},
10338         {"RESERVED_15_63"              ,        15,     49,     508,    "RAZ",  0,      0,      0ull,   0ull},
10339         {"WPTR"                        ,        0,      8,      509,    "RO",   0,      0,      0ull,   0ull},
10340         {"RPTR"                        ,        8,      8,      509,    "RO",   0,      0,      0ull,   0ull},
10341         {"CYCLES"                      ,        16,     48,     509,    "RO",   0,      0,      0ull,   0ull},
10342         {"ADR"                         ,        0,      36,     510,    "R/W",  0,      1,      0ull,   0},
10343         {"RESERVED_36_63"              ,        36,     28,     510,    "RAZ",  0,      0,      0ull,   0ull},
10344         {"ADR"                         ,        0,      36,     511,    "R/W",  0,      0,      0ull,   0ull},
10345         {"RESERVED_36_63"              ,        36,     28,     511,    "RAZ",  0,      0,      0ull,   0ull},
10346         {"DWB"                         ,        0,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10347         {"PL2"                         ,        1,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10348         {"PSL1"                        ,        2,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10349         {"LDD"                         ,        3,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10350         {"LDI"                         ,        4,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10351         {"LDT"                         ,        5,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10352         {"STF"                         ,        6,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10353         {"STC"                         ,        7,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10354         {"STP"                         ,        8,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10355         {"STT"                         ,        9,      1,      512,    "R/W",  0,      0,      0ull,   1ull},
10356         {"IOBLD8"                      ,        10,     1,      512,    "R/W",  0,      0,      0ull,   1ull},
10357         {"IOBLD16"                     ,        11,     1,      512,    "R/W",  0,      0,      0ull,   1ull},
10358         {"IOBLD32"                     ,        12,     1,      512,    "R/W",  0,      0,      0ull,   1ull},
10359         {"IOBLD64"                     ,        13,     1,      512,    "R/W",  0,      0,      0ull,   1ull},
10360         {"IOBST"                       ,        14,     1,      512,    "R/W",  0,      0,      0ull,   1ull},
10361         {"IOBDMA"                      ,        15,     1,      512,    "R/W",  0,      0,      0ull,   1ull},
10362         {"RESERVED_16_63"              ,        16,     48,     512,    "RAZ",  0,      0,      0ull,   0ull},
10363         {"MIO"                         ,        0,      1,      513,    "R/W",  0,      0,      0ull,   1ull},
10364         {"ILLEGAL3"                    ,        1,      2,      513,    "R/W",  0,      0,      0ull,   3ull},
10365         {"PCI"                         ,        3,      1,      513,    "R/W",  0,      0,      0ull,   1ull},
10366         {"KEY"                         ,        4,      1,      513,    "R/W",  0,      0,      0ull,   1ull},
10367         {"FPA"                         ,        5,      1,      513,    "R/W",  0,      0,      0ull,   1ull},
10368         {"DFA"                         ,        6,      1,      513,    "R/W",  0,      0,      0ull,   1ull},
10369         {"ZIP"                         ,        7,      1,      513,    "R/W",  0,      0,      0ull,   1ull},
10370         {"RNG"                         ,        8,      1,      513,    "R/W",  0,      0,      0ull,   1ull},
10371         {"ILLEGAL2"                    ,        9,      3,      513,    "R/W",  0,      0,      0ull,   7ull},
10372         {"POW"                         ,        12,     1,      513,    "R/W",  0,      0,      0ull,   1ull},
10373         {"ILLEGAL"                     ,        13,     19,     513,    "R/W",  0,      0,      0ull,   524287ull},
10374         {"RESERVED_32_63"              ,        32,     32,     513,    "RAZ",  0,      0,      0ull,   0ull},
10375         {"PP"                          ,        0,      16,     514,    "R/W",  0,      0,      0ull,   0ull},
10376         {"PKI"                         ,        16,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
10377         {"PKO"                         ,        17,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
10378         {"IOBREQ"                      ,        18,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
10379         {"DWB"                         ,        19,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
10380         {"RESERVED_20_63"              ,        20,     44,     514,    "RAZ",  0,      0,      0ull,   0ull},
10381         {"CIU_TRG"                     ,        0,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
10382         {"CIU_THR"                     ,        1,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
10383         {"MCD0_TRG"                    ,        2,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
10384         {"MCD0_THR"                    ,        3,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
10385         {"RESERVED_4_63"               ,        4,      60,     515,    "RAZ",  0,      0,      0ull,   0ull},
10386         {"DATA"                        ,        0,      64,     516,    "RO",   0,      0,      0ull,   0ull},
10387         {"ADR"                         ,        0,      36,     517,    "R/W",  0,      1,      0ull,   0},
10388         {"RESERVED_36_63"              ,        36,     28,     517,    "RAZ",  0,      0,      0ull,   0ull},
10389         {"ADR"                         ,        0,      36,     518,    "R/W",  0,      0,      0ull,   0ull},
10390         {"RESERVED_36_63"              ,        36,     28,     518,    "RAZ",  0,      0,      0ull,   0ull},
10391         {"DWB"                         ,        0,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10392         {"PL2"                         ,        1,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10393         {"PSL1"                        ,        2,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10394         {"LDD"                         ,        3,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10395         {"LDI"                         ,        4,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10396         {"LDT"                         ,        5,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10397         {"STF"                         ,        6,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10398         {"STC"                         ,        7,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10399         {"STP"                         ,        8,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10400         {"STT"                         ,        9,      1,      519,    "R/W",  0,      0,      0ull,   1ull},
10401         {"IOBLD8"                      ,        10,     1,      519,    "R/W",  0,      0,      0ull,   1ull},
10402         {"IOBLD16"                     ,        11,     1,      519,    "R/W",  0,      0,      0ull,   1ull},
10403         {"IOBLD32"                     ,        12,     1,      519,    "R/W",  0,      0,      0ull,   1ull},
10404         {"IOBLD64"                     ,        13,     1,      519,    "R/W",  0,      0,      0ull,   1ull},
10405         {"IOBST"                       ,        14,     1,      519,    "R/W",  0,      0,      0ull,   1ull},
10406         {"IOBDMA"                      ,        15,     1,      519,    "R/W",  0,      0,      0ull,   1ull},
10407         {"RESERVED_16_63"              ,        16,     48,     519,    "RAZ",  0,      0,      0ull,   0ull},
10408         {"MIO"                         ,        0,      1,      520,    "R/W",  0,      0,      0ull,   1ull},
10409         {"ILLEGAL3"                    ,        1,      2,      520,    "R/W",  0,      0,      0ull,   3ull},
10410         {"PCI"                         ,        3,      1,      520,    "R/W",  0,      0,      0ull,   1ull},
10411         {"KEY"                         ,        4,      1,      520,    "R/W",  0,      0,      0ull,   1ull},
10412         {"FPA"                         ,        5,      1,      520,    "R/W",  0,      0,      0ull,   1ull},
10413         {"DFA"                         ,        6,      1,      520,    "R/W",  0,      0,      0ull,   1ull},
10414         {"ZIP"                         ,        7,      1,      520,    "R/W",  0,      0,      0ull,   1ull},
10415         {"RNG"                         ,        8,      1,      520,    "R/W",  0,      0,      0ull,   1ull},
10416         {"ILLEGAL2"                    ,        9,      3,      520,    "R/W",  0,      0,      0ull,   7ull},
10417         {"POW"                         ,        12,     1,      520,    "R/W",  0,      0,      0ull,   1ull},
10418         {"ILLEGAL"                     ,        13,     19,     520,    "R/W",  0,      0,      0ull,   524287ull},
10419         {"RESERVED_32_63"              ,        32,     32,     520,    "RAZ",  0,      0,      0ull,   0ull},
10420         {"PP"                          ,        0,      16,     521,    "R/W",  0,      0,      0ull,   0ull},
10421         {"PKI"                         ,        16,     1,      521,    "R/W",  0,      0,      0ull,   0ull},
10422         {"PKO"                         ,        17,     1,      521,    "R/W",  0,      0,      0ull,   0ull},
10423         {"IOBREQ"                      ,        18,     1,      521,    "R/W",  0,      0,      0ull,   0ull},
10424         {"DWB"                         ,        19,     1,      521,    "R/W",  0,      0,      0ull,   0ull},
10425         {"RESERVED_20_63"              ,        20,     44,     521,    "RAZ",  0,      0,      0ull,   0ull},
10426         {"ADR"                         ,        0,      36,     522,    "R/W",  0,      1,      0ull,   0},
10427         {"RESERVED_36_63"              ,        36,     28,     522,    "RAZ",  0,      0,      0ull,   0ull},
10428         {"ADR"                         ,        0,      36,     523,    "R/W",  0,      0,      0ull,   0ull},
10429         {"RESERVED_36_63"              ,        36,     28,     523,    "RAZ",  0,      0,      0ull,   0ull},
10430         {"DWB"                         ,        0,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10431         {"PL2"                         ,        1,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10432         {"PSL1"                        ,        2,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10433         {"LDD"                         ,        3,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10434         {"LDI"                         ,        4,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10435         {"LDT"                         ,        5,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10436         {"STF"                         ,        6,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10437         {"STC"                         ,        7,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10438         {"STP"                         ,        8,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10439         {"STT"                         ,        9,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
10440         {"IOBLD8"                      ,        10,     1,      524,    "R/W",  0,      0,      0ull,   1ull},
10441         {"IOBLD16"                     ,        11,     1,      524,    "R/W",  0,      0,      0ull,   1ull},
10442         {"IOBLD32"                     ,        12,     1,      524,    "R/W",  0,      0,      0ull,   1ull},
10443         {"IOBLD64"                     ,        13,     1,      524,    "R/W",  0,      0,      0ull,   1ull},
10444         {"IOBST"                       ,        14,     1,      524,    "R/W",  0,      0,      0ull,   1ull},
10445         {"IOBDMA"                      ,        15,     1,      524,    "R/W",  0,      0,      0ull,   1ull},
10446         {"RESERVED_16_63"              ,        16,     48,     524,    "RAZ",  0,      0,      0ull,   0ull},
10447         {"MIO"                         ,        0,      1,      525,    "R/W",  0,      0,      0ull,   1ull},
10448         {"ILLEGAL3"                    ,        1,      2,      525,    "R/W",  0,      0,      0ull,   3ull},
10449         {"PCI"                         ,        3,      1,      525,    "R/W",  0,      0,      0ull,   1ull},
10450         {"KEY"                         ,        4,      1,      525,    "R/W",  0,      0,      0ull,   1ull},
10451         {"FPA"                         ,        5,      1,      525,    "R/W",  0,      0,      0ull,   1ull},
10452         {"DFA"                         ,        6,      1,      525,    "R/W",  0,      0,      0ull,   1ull},
10453         {"ZIP"                         ,        7,      1,      525,    "R/W",  0,      0,      0ull,   1ull},
10454         {"RNG"                         ,        8,      1,      525,    "R/W",  0,      0,      0ull,   1ull},
10455         {"ILLEGAL2"                    ,        9,      3,      525,    "R/W",  0,      0,      0ull,   7ull},
10456         {"POW"                         ,        12,     1,      525,    "R/W",  0,      0,      0ull,   1ull},
10457         {"ILLEGAL"                     ,        13,     19,     525,    "R/W",  0,      0,      0ull,   524287ull},
10458         {"RESERVED_32_63"              ,        32,     32,     525,    "RAZ",  0,      0,      0ull,   0ull},
10459         {"PP"                          ,        0,      16,     526,    "R/W",  0,      0,      0ull,   0ull},
10460         {"PKI"                         ,        16,     1,      526,    "R/W",  0,      0,      0ull,   0ull},
10461         {"PKO"                         ,        17,     1,      526,    "R/W",  0,      0,      0ull,   0ull},
10462         {"IOBREQ"                      ,        18,     1,      526,    "R/W",  0,      0,      0ull,   0ull},
10463         {"DWB"                         ,        19,     1,      526,    "R/W",  0,      0,      0ull,   0ull},
10464         {"RESERVED_20_63"              ,        20,     44,     526,    "RAZ",  0,      0,      0ull,   0ull},
10465         {"INEPINT"                     ,        0,      16,     527,    "RO",   0,      0,      0ull,   0ull},
10466         {"OUTEPINT"                    ,        16,     16,     527,    "RO",   0,      0,      0ull,   0ull},
10467         {"INEPMSK"                     ,        0,      16,     528,    "R/W",  0,      0,      0ull,   0ull},
10468         {"OUTEPMSK"                    ,        16,     16,     528,    "R/W",  0,      0,      0ull,   0ull},
10469         {"DEVSPD"                      ,        0,      2,      529,    "R/W",  0,      0,      0ull,   0ull},
10470         {"NZSTSOUTHSHK"                ,        2,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
10471         {"RESERVED_3_3"                ,        3,      1,      529,    "RAZ",  1,      1,      0,      0},
10472         {"DEVADDR"                     ,        4,      7,      529,    "R/W",  0,      0,      0ull,   0ull},
10473         {"PERFRINT"                    ,        11,     2,      529,    "R/W",  0,      0,      0ull,   0ull},
10474         {"RESERVED_13_17"              ,        13,     5,      529,    "RAZ",  1,      1,      0,      0},
10475         {"EPMISCNT"                    ,        18,     5,      529,    "R/W",  0,      0,      8ull,   0ull},
10476         {"RESERVED_23_31"              ,        23,     9,      529,    "RAZ",  1,      1,      0,      0},
10477         {"RMTWKUPSIG"                  ,        0,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
10478         {"SFTDISCON"                   ,        1,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
10479         {"GNPINNAKSTS"                 ,        2,      1,      530,    "RO",   0,      0,      0ull,   0ull},
10480         {"GOUTNAKSTS"                  ,        3,      1,      530,    "RO",   0,      0,      0ull,   0ull},
10481         {"TSTCTL"                      ,        4,      3,      530,    "R/W",  0,      0,      0ull,   0ull},
10482         {"SGNPINNAK"                   ,        7,      1,      530,    "WO",   0,      0,      0ull,   0ull},
10483         {"CGNPINNAK"                   ,        8,      1,      530,    "WO",   0,      0,      0ull,   0ull},
10484         {"SGOUTNAK"                    ,        9,      1,      530,    "WO",   0,      0,      0ull,   0ull},
10485         {"CGOUTNAK"                    ,        10,     1,      530,    "WO",   0,      0,      0ull,   0ull},
10486         {"PWRONPRGDONE"                ,        11,     1,      530,    "R/W",  0,      0,      0ull,   0ull},
10487         {"RESERVED_12_31"              ,        12,     20,     530,    "RAZ",  1,      1,      0,      0},
10488         {"MPS"                         ,        0,      11,     531,    "R/W",  0,      0,      0ull,   0ull},
10489         {"NEXTEP"                      ,        11,     4,      531,    "R/W",  0,      0,      0ull,   0ull},
10490         {"USBACTEP"                    ,        15,     1,      531,    "R/W",  0,      0,      1ull,   0ull},
10491         {"DPID"                        ,        16,     1,      531,    "RO",   0,      0,      0ull,   0ull},
10492         {"NAKSTS"                      ,        17,     1,      531,    "RO",   0,      0,      0ull,   0ull},
10493         {"EPTYPE"                      ,        18,     2,      531,    "R/W",  0,      0,      0ull,   0ull},
10494         {"RESERVED_20_20"              ,        20,     1,      531,    "RAZ",  1,      1,      0,      0},
10495         {"STALL"                       ,        21,     1,      531,    "R/W",  0,      0,      0ull,   0ull},
10496         {"TXFNUM"                      ,        22,     4,      531,    "R/W",  0,      0,      0ull,   0ull},
10497         {"CNAK"                        ,        26,     1,      531,    "WO",   0,      0,      0ull,   0ull},
10498         {"SNAK"                        ,        27,     1,      531,    "WO",   0,      0,      0ull,   0ull},
10499         {"SETD0PID"                    ,        28,     1,      531,    "WO",   0,      0,      0ull,   0ull},
10500         {"SETD1PID"                    ,        29,     1,      531,    "WO",   0,      0,      0ull,   0ull},
10501         {"EPDIS"                       ,        30,     1,      531,    "R/W",  0,      0,      0ull,   0ull},
10502         {"EPENA"                       ,        31,     1,      531,    "R/W",  0,      0,      0ull,   0ull},
10503         {"XFERCOMPL"                   ,        0,      1,      532,    "R/W1C",        0,      0,      0ull,   0ull},
10504         {"EPDISBLD"                    ,        1,      1,      532,    "R/W1C",        0,      0,      0ull,   0ull},
10505         {"AHBERR"                      ,        2,      1,      532,    "R/W1C",        0,      0,      0ull,   0ull},
10506         {"TIMEOUT"                     ,        3,      1,      532,    "R/W1C",        0,      0,      0ull,   0ull},
10507         {"INTKNTXFEMP"                 ,        4,      1,      532,    "R/W1C",        0,      0,      0ull,   0ull},
10508         {"INTKNEPMIS"                  ,        5,      1,      532,    "R/W1C",        0,      0,      0ull,   0ull},
10509         {"INEPNAKEFF"                  ,        6,      1,      532,    "RO",   0,      0,      0ull,   0ull},
10510         {"RESERVED_7_31"               ,        7,      25,     532,    "RAZ",  1,      1,      0,      0},
10511         {"XFERCOMPLMSK"                ,        0,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
10512         {"EPDISBLDMSK"                 ,        1,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
10513         {"AHBERRMSK"                   ,        2,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
10514         {"TIMEOUTMSK"                  ,        3,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
10515         {"INTKNTXFEMPMSK"              ,        4,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
10516         {"INTKNEPMISMSK"               ,        5,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
10517         {"INEPNAKEFFMSK"               ,        6,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
10518         {"RESERVED_7_31"               ,        7,      25,     533,    "RAZ",  1,      1,      0,      0},
10519         {"XFERSIZE"                    ,        0,      19,     534,    "R/W",  0,      0,      0ull,   0ull},
10520         {"PKTCNT"                      ,        19,     10,     534,    "R/W",  0,      0,      0ull,   0ull},
10521         {"MC"                          ,        29,     2,      534,    "R/W",  0,      0,      0ull,   0ull},
10522         {"RESERVED_31_31"              ,        31,     1,      534,    "RAZ",  1,      1,      0,      0},
10523         {"MPS"                         ,        0,      11,     535,    "R/W",  0,      0,      0ull,   0ull},
10524         {"RESERVED_11_14"              ,        11,     4,      535,    "RAZ",  0,      0,      0ull,   0ull},
10525         {"USBACTEP"                    ,        15,     1,      535,    "R/W",  0,      0,      1ull,   0ull},
10526         {"DPID"                        ,        16,     1,      535,    "RO",   0,      0,      0ull,   0ull},
10527         {"NAKSTS"                      ,        17,     1,      535,    "RO",   0,      0,      0ull,   0ull},
10528         {"EPTYPE"                      ,        18,     2,      535,    "R/W",  0,      0,      0ull,   0ull},
10529         {"SNP"                         ,        20,     1,      535,    "R/W",  0,      0,      0ull,   0ull},
10530         {"STALL"                       ,        21,     1,      535,    "R/W",  0,      0,      0ull,   0ull},
10531         {"RESERVED_22_25"              ,        22,     4,      535,    "RAZ",  1,      1,      0,      0},
10532         {"CNAK"                        ,        26,     1,      535,    "WO",   0,      0,      0ull,   0ull},
10533         {"SNAK"                        ,        27,     1,      535,    "WO",   0,      0,      0ull,   0ull},
10534         {"SETD0PID"                    ,        28,     1,      535,    "WO",   0,      0,      0ull,   0ull},
10535         {"SETD1PID"                    ,        29,     1,      535,    "WO",   0,      0,      0ull,   0ull},
10536         {"EPDIS"                       ,        30,     1,      535,    "R/W",  0,      0,      0ull,   0ull},
10537         {"EPENA"                       ,        31,     1,      535,    "R/W",  0,      0,      0ull,   0ull},
10538         {"XFERCOMPL"                   ,        0,      1,      536,    "R/W1C",        0,      0,      0ull,   0ull},
10539         {"EPDISBLD"                    ,        1,      1,      536,    "R/W1C",        0,      0,      0ull,   0ull},
10540         {"AHBERR"                      ,        2,      1,      536,    "R/W1C",        0,      0,      0ull,   0ull},
10541         {"SETUP"                       ,        3,      1,      536,    "R/W1C",        0,      0,      0ull,   0ull},
10542         {"OUTTKNEPDIS"                 ,        4,      1,      536,    "R/W1C",        0,      0,      0ull,   0ull},
10543         {"RESERVED_5_31"               ,        5,      27,     536,    "RAZ",  1,      1,      0,      0},
10544         {"XFERCOMPLMSK"                ,        0,      1,      537,    "R/W",  0,      0,      0ull,   0ull},
10545         {"EPDISBLDMSK"                 ,        1,      1,      537,    "R/W",  0,      0,      0ull,   0ull},
10546         {"AHBERRMSK"                   ,        2,      1,      537,    "R/W",  0,      0,      0ull,   0ull},
10547         {"SETUPMSK"                    ,        3,      1,      537,    "R/W",  0,      0,      0ull,   0ull},
10548         {"OUTTKNEPDISMSK"              ,        4,      1,      537,    "R/W",  0,      0,      0ull,   0ull},
10549         {"RESERVED_5_31"               ,        5,      27,     537,    "RAZ",  1,      1,      0,      0},
10550         {"XFERSIZE"                    ,        0,      19,     538,    "R/W",  0,      0,      0ull,   0ull},
10551         {"PKTCNT"                      ,        19,     10,     538,    "R/W",  0,      0,      0ull,   0ull},
10552         {"MC"                          ,        29,     2,      538,    "R/W",  0,      0,      0ull,   0ull},
10553         {"RESERVED_31_31"              ,        31,     1,      538,    "RAZ",  1,      1,      0,      0},
10554         {"DPTXFSTADDR"                 ,        0,      16,     539,    "RO",   0,      0,      0ull,   0ull},
10555         {"DPTXFSIZE"                   ,        16,     16,     539,    "RO",   0,      0,      1896ull,        1896ull},
10556         {"SUSPSTS"                     ,        0,      1,      540,    "RO",   0,      0,      0ull,   0ull},
10557         {"ENUMSPD"                     ,        1,      2,      540,    "RO",   0,      0,      0ull,   0ull},
10558         {"ERRTICERR"                   ,        3,      1,      540,    "RO",   0,      0,      0ull,   0ull},
10559         {"RESERVED_4_7"                ,        4,      4,      540,    "RAZ",  1,      1,      0,      0},
10560         {"SOFFN"                       ,        8,      14,     540,    "RO",   0,      0,      0ull,   0ull},
10561         {"RESERVED_22_31"              ,        22,     10,     540,    "RAZ",  1,      1,      0,      0},
10562         {"INTKNWPTR"                   ,        0,      5,      541,    "RO",   0,      0,      0ull,   0ull},
10563         {"RESERVED_5_6"                ,        5,      2,      541,    "RAZ",  1,      1,      0,      0},
10564         {"WRAPBIT"                     ,        7,      1,      541,    "RO",   0,      0,      0ull,   0ull},
10565         {"EPTKN"                       ,        8,      24,     541,    "RO",   0,      0,      0ull,   0ull},
10566         {"EPTKN"                       ,        0,      32,     542,    "RO",   0,      0,      0ull,   0ull},
10567         {"EPTKN"                       ,        0,      32,     543,    "RO",   0,      0,      0ull,   0ull},
10568         {"EPTKN"                       ,        0,      32,     544,    "RO",   0,      0,      0ull,   0ull},
10569         {"GLBLINTRMSK"                 ,        0,      1,      545,    "R/W",  0,      0,      0ull,   1ull},
10570         {"HBSTLEN"                     ,        1,      4,      545,    "R/W",  0,      0,      0ull,   0ull},
10571         {"DMAEN"                       ,        5,      1,      545,    "R/W",  0,      0,      0ull,   0ull},
10572         {"RESERVED_6_6"                ,        6,      1,      545,    "RAZ",  1,      1,      0,      0},
10573         {"NPTXFEMPLVL"                 ,        7,      1,      545,    "R/W",  0,      0,      0ull,   1ull},
10574         {"PTXFEMPLVL"                  ,        8,      1,      545,    "R/W",  0,      0,      0ull,   1ull},
10575         {"RESERVED_9_31"               ,        9,      23,     545,    "RAZ",  1,      1,      0,      0},
10576         {"EPDIR"                       ,        0,      32,     546,    "RO",   0,      0,      0ull,   0ull},
10577         {"OTGMODE"                     ,        0,      3,      547,    "RO",   0,      0,      2ull,   2ull},
10578         {"OTGARCH"                     ,        3,      2,      547,    "RO",   0,      0,      1ull,   1ull},
10579         {"SINGPNT"                     ,        5,      1,      547,    "RO",   0,      0,      0ull,   0ull},
10580         {"HSPHYTYPE"                   ,        6,      2,      547,    "RO",   0,      0,      1ull,   1ull},
10581         {"FSPHYTYPE"                   ,        8,      2,      547,    "RO",   0,      0,      0ull,   0ull},
10582         {"NUMDEVEPS"                   ,        10,     4,      547,    "RO",   0,      0,      4ull,   4ull},
10583         {"NUMHSTCHNL"                  ,        14,     4,      547,    "RO",   0,      0,      7ull,   7ull},
10584         {"PERIOSUPPORT"                ,        18,     1,      547,    "RO",   0,      0,      1ull,   1ull},
10585         {"DYNFIFOSIZING"               ,        19,     1,      547,    "RO",   0,      0,      1ull,   1ull},
10586         {"RESERVED_20_21"              ,        20,     2,      547,    "RAZ",  1,      1,      0,      0},
10587         {"NPTXQDEPTH"                  ,        22,     2,      547,    "RO",   0,      0,      2ull,   2ull},
10588         {"PTXQDEPTH"                   ,        24,     2,      547,    "RO",   0,      0,      2ull,   2ull},
10589         {"TKNQDEPTH"                   ,        26,     5,      547,    "RO",   0,      0,      30ull,  30ull},
10590         {"RESERVED_31_31"              ,        31,     1,      547,    "RAZ",  1,      1,      0,      0},
10591         {"XFERSIZEWIDTH"               ,        0,      4,      548,    "RO",   0,      0,      8ull,   8ull},
10592         {"PKTSIZEWIDTH"                ,        4,      3,      548,    "RO",   0,      0,      6ull,   6ull},
10593         {"OTGEN"                       ,        7,      1,      548,    "RO",   0,      0,      1ull,   1ull},
10594         {"I2C_SELECTION"               ,        8,      1,      548,    "RO",   0,      0,      0ull,   0ull},
10595         {"VENDOR_CONTROL_INTERFACE_SUPPORT",    9,      1,      548,    "RO",   0,      0,      0ull,   0ull},
10596         {"OPTFEATURE"                  ,        10,     1,      548,    "RO",   0,      0,      1ull,   1ull},
10597         {"RSTTYPE"                     ,        11,     1,      548,    "RO",   0,      0,      1ull,   1ull},
10598         {"AHBPHYSYNC"                  ,        12,     1,      548,    "RO",   0,      0,      0ull,   0ull},
10599         {"RESERVED_13_15"              ,        13,     3,      548,    "RAZ",  1,      1,      0,      0},
10600         {"DFIFODEPTH"                  ,        16,     16,     548,    "RO",   0,      0,      1824ull,        1824ull},
10601         {"NUMDEVPERIOEPS"              ,        0,      4,      549,    "RO",   0,      0,      4ull,   4ull},
10602         {"ENABLEPWROPT"                ,        4,      1,      549,    "RO",   0,      0,      0ull,   0ull},
10603         {"AHBFREQ"                     ,        5,      1,      549,    "RO",   0,      0,      1ull,   1ull},
10604         {"RESERVED_6_13"               ,        6,      8,      549,    "RAZ",  1,      1,      0,      0},
10605         {"PHYDATAWIDTH"                ,        14,     2,      549,    "RO",   0,      0,      1ull,   1ull},
10606         {"NUMCTLEPS"                   ,        16,     4,      549,    "RO",   0,      0,      4ull,   4ull},
10607         {"IDDGFLTR"                    ,        20,     1,      549,    "RO",   0,      0,      0ull,   0ull},
10608         {"VBUSVALIDFLTR"               ,        21,     1,      549,    "RO",   0,      0,      0ull,   0ull},
10609         {"AVALIDFLTR"                  ,        22,     1,      549,    "RO",   0,      0,      1ull,   1ull},
10610         {"BVALIDFLTR"                  ,        23,     1,      549,    "RO",   0,      0,      1ull,   1ull},
10611         {"SESSENDFLTR"                 ,        24,     1,      549,    "RO",   0,      0,      1ull,   1ull},
10612         {"RESERVED_25_31"              ,        25,     7,      549,    "RAZ",  1,      1,      0,      0},
10613         {"RESERVED_0_0"                ,        0,      1,      550,    "RAZ",  1,      1,      0,      0},
10614         {"MODEMISMSK"                  ,        1,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
10615         {"OTGINTMSK"                   ,        2,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
10616         {"SOFMSK"                      ,        3,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
10617         {"RXFLVLMSK"                   ,        4,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
10618         {"NPTXFEMPMSK"                 ,        5,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
10619         {"GINNAKEFFMSK"                ,        6,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
10620         {"GOUTNAKEFFMSK"               ,        7,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
10621         {"ULPICKINTMSK"                ,        8,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
10622         {"I2CINT"                      ,        9,      1,      550,    "R/W",  0,      0,      0ull,   0ull},
10623         {"ERLYSUSPMSK"                 ,        10,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10624         {"USBSUSPMSK"                  ,        11,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10625         {"USBRSTMSK"                   ,        12,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10626         {"ENUMDONEMSK"                 ,        13,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10627         {"ISOOUTDROPMSK"               ,        14,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10628         {"EOPFMSK"                     ,        15,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10629         {"RESERVED_16_16"              ,        16,     1,      550,    "RAZ",  1,      1,      0,      0},
10630         {"EPMISMSK"                    ,        17,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10631         {"INEPINTMSK"                  ,        18,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10632         {"OEPINTMSK"                   ,        19,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10633         {"INCOMPISOINMSK"              ,        20,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10634         {"INCOMPLPMSK"                 ,        21,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10635         {"FETSUSPMSK"                  ,        22,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10636         {"RESERVED_23_23"              ,        23,     1,      550,    "RAZ",  1,      1,      0,      0},
10637         {"PRTINTMSK"                   ,        24,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10638         {"HCHINTMSK"                   ,        25,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10639         {"PTXFEMPMSK"                  ,        26,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10640         {"RESERVED_27_27"              ,        27,     1,      550,    "RAZ",  1,      1,      0,      0},
10641         {"CONIDSTSCHNGMSK"             ,        28,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10642         {"DISCONNINTMSK"               ,        29,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10643         {"SESSREQINTMSK"               ,        30,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10644         {"WKUPINTMSK"                  ,        31,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
10645         {"CURMOD"                      ,        0,      1,      551,    "RO",   0,      0,      0ull,   0ull},
10646         {"MODEMIS"                     ,        1,      1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10647         {"OTGINT"                      ,        2,      1,      551,    "RO",   0,      0,      0ull,   0ull},
10648         {"SOF"                         ,        3,      1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10649         {"RXFLVL"                      ,        4,      1,      551,    "RO",   0,      0,      0ull,   0ull},
10650         {"NPTXFEMP"                    ,        5,      1,      551,    "RO",   0,      0,      0ull,   0ull},
10651         {"GINNAKEFF"                   ,        6,      1,      551,    "RO",   0,      0,      0ull,   0ull},
10652         {"GOUTNAKEFF"                  ,        7,      1,      551,    "RO",   0,      0,      0ull,   0ull},
10653         {"ULPICKINT"                   ,        8,      1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10654         {"I2CINT"                      ,        9,      1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10655         {"ERLYSUSP"                    ,        10,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10656         {"USBSUSP"                     ,        11,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10657         {"USBRST"                      ,        12,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10658         {"ENUMDONE"                    ,        13,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10659         {"ISOOUTDROP"                  ,        14,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10660         {"EOPF"                        ,        15,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10661         {"RESERVED_16_16"              ,        16,     1,      551,    "RAZ",  1,      1,      0,      0},
10662         {"EPMIS"                       ,        17,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10663         {"IEPINT"                      ,        18,     1,      551,    "RO",   0,      0,      0ull,   0ull},
10664         {"OEPINT"                      ,        19,     1,      551,    "RO",   0,      0,      0ull,   0ull},
10665         {"INCOMPISOIN"                 ,        20,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10666         {"INCOMPLP"                    ,        21,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10667         {"FETSUSP"                     ,        22,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10668         {"RESERVED_23_23"              ,        23,     1,      551,    "RAZ",  1,      1,      0,      0},
10669         {"PRTINT"                      ,        24,     1,      551,    "RO",   0,      0,      0ull,   0ull},
10670         {"HCHINT"                      ,        25,     1,      551,    "RO",   0,      0,      0ull,   0ull},
10671         {"PTXFEMP"                     ,        26,     1,      551,    "RO",   0,      0,      0ull,   0ull},
10672         {"RESERVED_27_27"              ,        27,     1,      551,    "RAZ",  1,      1,      0,      0},
10673         {"CONIDSTSCHNG"                ,        28,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10674         {"DISCONNINT"                  ,        29,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10675         {"SESSREQINT"                  ,        30,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10676         {"WKUPINT"                     ,        31,     1,      551,    "R/W1C",        0,      0,      0ull,   0ull},
10677         {"NPTXFSTADDR"                 ,        0,      16,     552,    "R/W",  0,      0,      1824ull,        456ull},
10678         {"NPTXFDEP"                    ,        16,     16,     552,    "R/W",  0,      0,      1824ull,        912ull},
10679         {"NPTXFSPCAVAIL"               ,        0,      16,     553,    "RO",   0,      0,      0ull,   0ull},
10680         {"NPTXQSPCAVAIL"               ,        16,     8,      553,    "RO",   0,      0,      0ull,   0ull},
10681         {"NPTXQTOP"                    ,        24,     7,      553,    "RO",   0,      0,      0ull,   0ull},
10682         {"RESERVED_31_31"              ,        31,     1,      553,    "RAZ",  1,      1,      0,      0},
10683         {"SESREQSCS"                   ,        0,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
10684         {"SESREQ"                      ,        1,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
10685         {"RESERVED_2_7"                ,        2,      6,      554,    "RAZ",  1,      1,      0,      0},
10686         {"HSTNEGSCS"                   ,        8,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
10687         {"HNPREQ"                      ,        9,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
10688         {"HSTSETHNPEN"                 ,        10,     1,      554,    "R/W",  0,      0,      0ull,   0ull},
10689         {"DEVHNPEN"                    ,        11,     1,      554,    "R/W",  0,      0,      0ull,   0ull},
10690         {"RESERVED_12_15"              ,        12,     4,      554,    "RAZ",  1,      1,      0,      0},
10691         {"CONIDSTS"                    ,        16,     1,      554,    "RO",   1,      1,      0,      0},
10692         {"DBNCTIME"                    ,        17,     1,      554,    "RO",   0,      0,      0ull,   0ull},
10693         {"ASESVLD"                     ,        18,     1,      554,    "RO",   1,      1,      0,      0},
10694         {"BSESVLD"                     ,        19,     1,      554,    "RO",   1,      1,      0,      0},
10695         {"RESERVED_20_31"              ,        20,     12,     554,    "RAZ",  1,      1,      0,      0},
10696         {"RESERVED_0_1"                ,        0,      2,      555,    "RAZ",  1,      1,      0,      0},
10697         {"SESENDDET"                   ,        2,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
10698         {"RESERVED_3_7"                ,        3,      5,      555,    "RAZ",  1,      1,      0,      0},
10699         {"SESREQSUCSTSCHNG"            ,        8,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
10700         {"HSTNEGSUCSTSCHNG"            ,        9,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
10701         {"RESERVED_10_16"              ,        10,     7,      555,    "RAZ",  1,      1,      0,      0},
10702         {"HSTNEGDET"                   ,        17,     1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
10703         {"ADEVTOUTCHG"                 ,        18,     1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
10704         {"DBNCEDONE"                   ,        19,     1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
10705         {"RESERVED_20_31"              ,        20,     12,     555,    "RAZ",  1,      1,      0,      0},
10706         {"CSFTRST"                     ,        0,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
10707         {"HSFTRST"                     ,        1,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
10708         {"FRMCNTRRST"                  ,        2,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
10709         {"INTKNQFLSH"                  ,        3,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
10710         {"RXFFLSH"                     ,        4,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
10711         {"TXFFLSH"                     ,        5,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
10712         {"TXFNUM"                      ,        6,      5,      556,    "R/W",  0,      0,      0ull,   0ull},
10713         {"RESERVED_11_29"              ,        11,     19,     556,    "RAZ",  1,      1,      0,      0},
10714         {"DMAREQ"                      ,        30,     1,      556,    "RO",   0,      0,      0ull,   0ull},
10715         {"AHBIDLE"                     ,        31,     1,      556,    "RO",   0,      0,      1ull,   1ull},
10716         {"RXFDEP"                      ,        0,      16,     557,    "R/W",  0,      0,      1824ull,        456ull},
10717         {"RESERVED_16_31"              ,        16,     16,     557,    "RAZ",  1,      1,      0,      0},
10718         {"EPNUM"                       ,        0,      4,      558,    "RO",   0,      0,      0ull,   0ull},
10719         {"BCNT"                        ,        4,      11,     558,    "RO",   0,      0,      0ull,   0ull},
10720         {"DPID"                        ,        15,     2,      558,    "RO",   0,      0,      0ull,   0ull},
10721         {"PKTSTS"                      ,        17,     4,      558,    "RO",   0,      0,      0ull,   0ull},
10722         {"FN"                          ,        21,     4,      558,    "RO",   0,      0,      0ull,   0ull},
10723         {"RESERVED_25_31"              ,        25,     7,      558,    "RAZ",  1,      1,      0,      0},
10724         {"CHNUM"                       ,        0,      4,      559,    "RO",   0,      0,      0ull,   0ull},
10725         {"BCNT"                        ,        4,      11,     559,    "RO",   0,      0,      0ull,   0ull},
10726         {"DPID"                        ,        15,     2,      559,    "RO",   0,      0,      0ull,   0ull},
10727         {"PKTSTS"                      ,        17,     4,      559,    "RO",   0,      0,      0ull,   0ull},
10728         {"RESERVED_21_31"              ,        21,     11,     559,    "RAZ",  1,      1,      0,      0},
10729         {"EPNUM"                       ,        0,      4,      560,    "RO",   0,      0,      0ull,   0ull},
10730         {"BCNT"                        ,        4,      11,     560,    "RO",   0,      0,      0ull,   0ull},
10731         {"DPID"                        ,        15,     2,      560,    "RO",   0,      0,      0ull,   0ull},
10732         {"PKTSTS"                      ,        17,     4,      560,    "RO",   0,      0,      0ull,   0ull},
10733         {"FN"                          ,        21,     4,      560,    "RO",   0,      0,      0ull,   0ull},
10734         {"RESERVED_25_31"              ,        25,     7,      560,    "RAZ",  1,      1,      0,      0},
10735         {"CHNUM"                       ,        0,      4,      561,    "RO",   0,      0,      0ull,   0ull},
10736         {"BCNT"                        ,        4,      11,     561,    "RO",   0,      0,      0ull,   0ull},
10737         {"DPID"                        ,        15,     2,      561,    "RO",   0,      0,      0ull,   0ull},
10738         {"PKTSTS"                      ,        17,     4,      561,    "RO",   0,      0,      0ull,   0ull},
10739         {"RESERVED_21_31"              ,        21,     11,     561,    "RAZ",  1,      1,      0,      0},
10740         {"SYNOPSYSID"                  ,        0,      32,     562,    "RO",   1,      1,      0,      0},
10741         {"TOUTCAL"                     ,        0,      3,      563,    "R/W",  0,      0,      0ull,   0ull},
10742         {"PHYIF"                       ,        3,      1,      563,    "RO",   0,      0,      1ull,   1ull},
10743         {"ULPI_UTMI_SEL"               ,        4,      1,      563,    "RO",   0,      0,      0ull,   0ull},
10744         {"FSINTF"                      ,        5,      1,      563,    "WO",   0,      0,      0ull,   0ull},
10745         {"PHYSEL"                      ,        6,      1,      563,    "WO",   0,      0,      0ull,   0ull},
10746         {"DDRSEL"                      ,        7,      1,      563,    "R/W",  0,      0,      0ull,   0ull},
10747         {"SRPCAP"                      ,        8,      1,      563,    "RO",   0,      0,      0ull,   0ull},
10748         {"HNPCAP"                      ,        9,      1,      563,    "RO",   0,      0,      0ull,   0ull},
10749         {"USBTRDTIM"                   ,        10,     4,      563,    "R/W",  0,      0,      5ull,   5ull},
10750         {"RESERVED_14_14"              ,        14,     1,      563,    "RAZ",  1,      1,      0,      0},
10751         {"PHYLPWRCLKSEL"               ,        15,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
10752         {"OTGI2CSEL"                   ,        16,     1,      563,    "RO",   0,      0,      0ull,   0ull},
10753         {"RESERVED_17_31"              ,        17,     15,     563,    "RAZ",  1,      1,      0,      0},
10754         {"HAINT"                       ,        0,      16,     564,    "RO",   0,      0,      0ull,   0ull},
10755         {"RESERVED_16_31"              ,        16,     16,     564,    "RAZ",  1,      1,      0,      0},
10756         {"HAINTMSK"                    ,        0,      16,     565,    "R/W",  0,      0,      0ull,   0ull},
10757         {"RESERVED_16_31"              ,        16,     16,     565,    "RAZ",  1,      1,      0,      0},
10758         {"MPS"                         ,        0,      11,     566,    "R/W",  0,      0,      0ull,   0ull},
10759         {"EPNUM"                       ,        11,     4,      566,    "R/W",  0,      0,      0ull,   0ull},
10760         {"EPDIR"                       ,        15,     1,      566,    "R/W",  0,      0,      0ull,   0ull},
10761         {"RESERVED_16_16"              ,        16,     1,      566,    "RAZ",  1,      1,      0,      0},
10762         {"LSPDDEV"                     ,        17,     1,      566,    "R/W",  0,      0,      0ull,   0ull},
10763         {"EPTYPE"                      ,        18,     2,      566,    "R/W",  0,      0,      0ull,   0ull},
10764         {"EC"                          ,        20,     2,      566,    "R/W",  0,      0,      0ull,   0ull},
10765         {"DEVADDR"                     ,        22,     7,      566,    "R/W",  0,      0,      0ull,   0ull},
10766         {"ODDFRM"                      ,        29,     1,      566,    "R/W",  0,      0,      0ull,   0ull},
10767         {"CHDIS"                       ,        30,     1,      566,    "R/W",  0,      0,      0ull,   0ull},
10768         {"CHENA"                       ,        31,     1,      566,    "R/W",  0,      0,      0ull,   0ull},
10769         {"FSLSPCLKSEL"                 ,        0,      2,      567,    "R/W",  0,      0,      0ull,   0ull},
10770         {"FSLSSUPP"                    ,        2,      1,      567,    "R/W",  0,      0,      0ull,   0ull},
10771         {"RESERVED_3_31"               ,        3,      29,     567,    "RAZ",  1,      1,      0,      0},
10772         {"XFERCOMPL"                   ,        0,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10773         {"CHHLTD"                      ,        1,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10774         {"AHBERR"                      ,        2,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10775         {"STALL"                       ,        3,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10776         {"NAK"                         ,        4,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10777         {"ACK"                         ,        5,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10778         {"NYET"                        ,        6,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10779         {"XACTERR"                     ,        7,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10780         {"BBLERR"                      ,        8,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10781         {"FRMOVRUN"                    ,        9,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10782         {"DATATGLERR"                  ,        10,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
10783         {"RESERVED_11_31"              ,        11,     21,     568,    "RAZ",  1,      1,      0,      0},
10784         {"XFERCOMPLMSK"                ,        0,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10785         {"CHHLTDMSK"                   ,        1,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10786         {"AHBERRMSK"                   ,        2,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10787         {"STALLMSK"                    ,        3,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10788         {"NAKMSK"                      ,        4,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10789         {"ACKMSK"                      ,        5,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10790         {"NYETMSK"                     ,        6,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10791         {"XACTERRMSK"                  ,        7,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10792         {"BBLERRMSK"                   ,        8,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10793         {"FRMOVRUNMSK"                 ,        9,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
10794         {"DATATGLERRMSK"               ,        10,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
10795         {"RESERVED_11_31"              ,        11,     21,     569,    "RAZ",  1,      1,      0,      0},
10796         {"PRTADDR"                     ,        0,      7,      570,    "R/W",  0,      0,      0ull,   0ull},
10797         {"HUBADDR"                     ,        7,      7,      570,    "R/W",  0,      0,      0ull,   0ull},
10798         {"XACTPOS"                     ,        14,     2,      570,    "R/W",  0,      0,      0ull,   0ull},
10799         {"COMPSPLT"                    ,        16,     1,      570,    "R/W",  0,      0,      0ull,   0ull},
10800         {"RESERVED_17_30"              ,        17,     14,     570,    "RAZ",  1,      1,      0,      0},
10801         {"SPLTENA"                     ,        31,     1,      570,    "R/W",  0,      0,      0ull,   0ull},
10802         {"XFERSIZE"                    ,        0,      19,     571,    "R/W",  0,      0,      0ull,   0ull},
10803         {"PKTCNT"                      ,        19,     10,     571,    "R/W",  0,      0,      0ull,   0ull},
10804         {"PID"                         ,        29,     2,      571,    "R/W",  0,      0,      0ull,   0ull},
10805         {"DOPNG"                       ,        31,     1,      571,    "R/W",  0,      0,      0ull,   0ull},
10806         {"FRINT"                       ,        0,      16,     572,    "R/W",  0,      0,      2959ull,        3750ull},
10807         {"RESERVED_16_31"              ,        16,     16,     572,    "RAZ",  1,      1,      0,      0},
10808         {"FRNUM"                       ,        0,      16,     573,    "RO",   0,      0,      16383ull,       0ull},
10809         {"FRREM"                       ,        16,     16,     573,    "RO",   0,      0,      0ull,   0ull},
10810         {"PRTCONNSTS"                  ,        0,      1,      574,    "RO",   0,      0,      0ull,   0ull},
10811         {"PRTCONNDET"                  ,        1,      1,      574,    "R/W1C",        0,      0,      0ull,   0ull},
10812         {"PRTENA"                      ,        2,      1,      574,    "R/W1C",        0,      0,      0ull,   0ull},
10813         {"PRTENCHNG"                   ,        3,      1,      574,    "R/W1C",        0,      0,      0ull,   0ull},
10814         {"PRTOVRCURRACT"               ,        4,      1,      574,    "RO",   0,      0,      0ull,   0ull},
10815         {"PRTOVRCURRCHNG"              ,        5,      1,      574,    "R/W1C",        0,      0,      0ull,   0ull},
10816         {"PRTRES"                      ,        6,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
10817         {"PRTSUSP"                     ,        7,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
10818         {"PRTRST"                      ,        8,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
10819         {"RESERVED_9_9"                ,        9,      1,      574,    "RAZ",  1,      1,      0,      0},
10820         {"PRTLNSTS"                    ,        10,     2,      574,    "RO",   0,      0,      0ull,   0ull},
10821         {"PRTPWR"                      ,        12,     1,      574,    "R/W",  0,      0,      0ull,   0ull},
10822         {"PRTTSTCTL"                   ,        13,     4,      574,    "R/W",  0,      0,      0ull,   0ull},
10823         {"PRTSPD"                      ,        17,     2,      574,    "RO",   0,      0,      0ull,   0ull},
10824         {"RESERVED_19_31"              ,        19,     13,     574,    "RAZ",  1,      1,      0,      0},
10825         {"PTXFSTADDR"                  ,        0,      16,     575,    "R/W",  0,      0,      3648ull,        912ull},
10826         {"PTXFSIZE"                    ,        16,     16,     575,    "R/W",  0,      0,      1824ull,        456ull},
10827         {"PTXFSPCAVAIL"                ,        0,      16,     576,    "RO",   0,      0,      0ull,   0ull},
10828         {"PTXQSPCAVAIL"                ,        16,     8,      576,    "RO",   0,      0,      0ull,   0ull},
10829         {"PTXQTOP"                     ,        24,     8,      576,    "RO",   0,      0,      0ull,   0ull},
10830         {"DATA"                        ,        0,      32,     577,    "R/W",  0,      0,      0ull,   0ull},
10831         {"STOPPCLK"                    ,        0,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
10832         {"GATEHCLK"                    ,        1,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
10833         {"PWRCLMP"                     ,        2,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
10834         {"RSTPDWNMODULE"               ,        3,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
10835         {"PHYSUSPENDED"                ,        4,      1,      578,    "RO",   0,      0,      0ull,   0ull},
10836         {"RESERVED_5_31"               ,        5,      27,     578,    "RAZ",  1,      1,      0,      0},
10837         {"NOF_BIS"                     ,        0,      1,      579,    "RO",   0,      0,      0ull,   0ull},
10838         {"NIF_BIS"                     ,        1,      1,      579,    "RO",   0,      0,      0ull,   0ull},
10839         {"USBC_BIS"                    ,        2,      1,      579,    "RO",   0,      0,      0ull,   0ull},
10840         {"RESERVED_3_63"               ,        3,      61,     579,    "RAZ",  1,      1,      0,      0},
10841         {"DIVIDE"                      ,        0,      3,      580,    "R/W",  0,      0,      4ull,   4ull},
10842         {"HRST"                        ,        3,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
10843         {"PRST"                        ,        4,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
10844         {"ENABLE"                      ,        5,      1,      580,    "R/W",  0,      0,      1ull,   1ull},
10845         {"POR"                         ,        6,      1,      580,    "R/W",  0,      0,      1ull,   0ull},
10846         {"S_BIST"                      ,        7,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
10847         {"SD_MODE"                     ,        8,      2,      580,    "R/W",  0,      0,      0ull,   0ull},
10848         {"CDIV_BYP"                    ,        10,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
10849         {"P_C_SEL"                     ,        11,     2,      580,    "R/W",  0,      0,      2ull,   2ull},
10850         {"P_COM_ON"                    ,        13,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
10851         {"P_XENBN"                     ,        14,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
10852         {"P_RCLK"                      ,        15,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
10853         {"P_X_ON"                      ,        16,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
10854         {"HCLK_RST"                    ,        17,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
10855         {"RESERVED_18_63"              ,        18,     46,     580,    "RAZ",  1,      1,      0,      0},
10856         {"L2C_EMOD"                    ,        0,      2,      581,    "R/W",  0,      0,      1ull,   1ull},
10857         {"INV_A2"                      ,        2,      1,      581,    "R/W",  0,      0,      0ull,   0ull},
10858         {"DMA_TEST"                    ,        3,      1,      581,    "R/W",  0,      0,      0ull,   0ull},
10859         {"DMA_STT"                     ,        4,      1,      581,    "R/W",  0,      0,      0ull,   0ull},
10860         {"DMA_0PAG"                    ,        5,      1,      581,    "R/W",  0,      0,      0ull,   0ull},
10861         {"RESERVED_6_63"               ,        6,      58,     581,    "RAZ",  1,      1,      0,      0},
10862         {"ADDR"                        ,        0,      36,     582,    "R/W",  0,      1,      0ull,   0},
10863         {"RESERVED_36_63"              ,        36,     28,     582,    "RAZ",  1,      1,      0,      0},
10864         {"ADDR"                        ,        0,      36,     583,    "R/W",  0,      1,      0ull,   0},
10865         {"RESERVED_36_63"              ,        36,     28,     583,    "RAZ",  1,      1,      0,      0},
10866         {"ADDR"                        ,        0,      36,     584,    "R/W",  0,      1,      0ull,   0},
10867         {"RESERVED_36_63"              ,        36,     28,     584,    "RAZ",  1,      1,      0,      0},
10868         {"ADDR"                        ,        0,      36,     585,    "R/W",  0,      1,      0ull,   0},
10869         {"RESERVED_36_63"              ,        36,     28,     585,    "RAZ",  1,      1,      0,      0},
10870         {"ADDR"                        ,        0,      36,     586,    "R/W",  0,      1,      0ull,   0},
10871         {"RESERVED_36_63"              ,        36,     28,     586,    "RAZ",  1,      1,      0,      0},
10872         {"ADDR"                        ,        0,      36,     587,    "R/W",  0,      1,      0ull,   0},
10873         {"RESERVED_36_63"              ,        36,     28,     587,    "RAZ",  1,      1,      0,      0},
10874         {"ADDR"                        ,        0,      36,     588,    "R/W",  0,      1,      0ull,   0},
10875         {"RESERVED_36_63"              ,        36,     28,     588,    "RAZ",  1,      1,      0,      0},
10876         {"ADDR"                        ,        0,      36,     589,    "R/W",  0,      1,      0ull,   0},
10877         {"RESERVED_36_63"              ,        36,     28,     589,    "RAZ",  1,      1,      0,      0},
10878         {"ADDR"                        ,        0,      36,     590,    "R/W",  0,      1,      0ull,   0},
10879         {"RESERVED_36_63"              ,        36,     28,     590,    "RAZ",  1,      1,      0,      0},
10880         {"ADDR"                        ,        0,      36,     591,    "R/W",  0,      1,      0ull,   0},
10881         {"RESERVED_36_63"              ,        36,     28,     591,    "RAZ",  1,      1,      0,      0},
10882         {"ADDR"                        ,        0,      36,     592,    "R/W",  0,      1,      0ull,   0},
10883         {"RESERVED_36_63"              ,        36,     28,     592,    "RAZ",  1,      1,      0,      0},
10884         {"ADDR"                        ,        0,      36,     593,    "R/W",  0,      1,      0ull,   0},
10885         {"RESERVED_36_63"              ,        36,     28,     593,    "RAZ",  1,      1,      0,      0},
10886         {"ADDR"                        ,        0,      36,     594,    "R/W",  0,      1,      0ull,   0},
10887         {"RESERVED_36_63"              ,        36,     28,     594,    "RAZ",  1,      1,      0,      0},
10888         {"ADDR"                        ,        0,      36,     595,    "R/W",  0,      1,      0ull,   0},
10889         {"RESERVED_36_63"              ,        36,     28,     595,    "RAZ",  1,      1,      0,      0},
10890         {"ADDR"                        ,        0,      36,     596,    "R/W",  0,      1,      0ull,   0},
10891         {"RESERVED_36_63"              ,        36,     28,     596,    "RAZ",  1,      1,      0,      0},
10892         {"ADDR"                        ,        0,      36,     597,    "R/W",  0,      1,      0ull,   0},
10893         {"RESERVED_36_63"              ,        36,     28,     597,    "RAZ",  1,      1,      0,      0},
10894         {"BURST"                       ,        0,      4,      598,    "R/W",  0,      0,      0ull,   0ull},
10895         {"CHANNEL"                     ,        4,      5,      598,    "R/W",  0,      0,      0ull,   0ull},
10896         {"COUNT"                       ,        9,      11,     598,    "R/W",  0,      0,      0ull,   0ull},
10897         {"F_ADDR"                      ,        20,     18,     598,    "R/W",  0,      0,      0ull,   0ull},
10898         {"REQ"                         ,        38,     1,      598,    "R/W1C",        0,      0,      0ull,   0ull},
10899         {"DONE"                        ,        39,     1,      598,    "R/W1C",        0,      0,      0ull,   0ull},
10900         {"RESERVED_40_63"              ,        40,     24,     598,    "RAZ",  1,      1,      0,      0},
10901         {"PR_PO_E"                     ,        0,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10902         {"PR_PU_F"                     ,        1,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10903         {"NR_PO_E"                     ,        2,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10904         {"NR_PU_F"                     ,        3,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10905         {"LR_PO_E"                     ,        4,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10906         {"LR_PU_F"                     ,        5,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10907         {"PT_PO_E"                     ,        6,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10908         {"PT_PU_F"                     ,        7,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10909         {"NT_PO_E"                     ,        8,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10910         {"NT_PU_F"                     ,        9,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
10911         {"LT_PO_E"                     ,        10,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10912         {"LT_PU_F"                     ,        11,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10913         {"DCRED_E"                     ,        12,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10914         {"DCRED_F"                     ,        13,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10915         {"L2C_S_E"                     ,        14,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10916         {"L2C_A_F"                     ,        15,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10917         {"L2_FI_E"                     ,        16,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10918         {"L2_FI_F"                     ,        17,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10919         {"RG_FI_E"                     ,        18,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10920         {"RG_FI_F"                     ,        19,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10921         {"RQ_Q2_F"                     ,        20,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10922         {"RQ_Q2_E"                     ,        21,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10923         {"RQ_Q3_F"                     ,        22,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10924         {"RQ_Q3_E"                     ,        23,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10925         {"UOD_PE"                      ,        24,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10926         {"UOD_PF"                      ,        25,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10927         {"N2U_PF"                      ,        26,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10928         {"N2U_PE"                      ,        27,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10929         {"U2N_D_PE"                    ,        28,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10930         {"U2N_D_PF"                    ,        29,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10931         {"U2N_C_PF"                    ,        30,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10932         {"U2N_C_PE"                    ,        31,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10933         {"LTL_F_PE"                    ,        32,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10934         {"LTL_F_PF"                    ,        33,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10935         {"ND4O_RPE"                    ,        34,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10936         {"ND4O_RPF"                    ,        35,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10937         {"ND4O_DPE"                    ,        36,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10938         {"ND4O_DPF"                    ,        37,     1,      599,    "R/W",  0,      0,      0ull,   0ull},
10939         {"RESERVED_38_63"              ,        38,     26,     599,    "RAZ",  1,      1,      0,      0},
10940         {"PR_PO_E"                     ,        0,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10941         {"PR_PU_F"                     ,        1,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10942         {"NR_PO_E"                     ,        2,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10943         {"NR_PU_F"                     ,        3,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10944         {"LR_PO_E"                     ,        4,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10945         {"LR_PU_F"                     ,        5,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10946         {"PT_PO_E"                     ,        6,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10947         {"PT_PU_F"                     ,        7,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10948         {"NT_PO_E"                     ,        8,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10949         {"NT_PU_F"                     ,        9,      1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10950         {"LT_PO_E"                     ,        10,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10951         {"LT_PU_F"                     ,        11,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10952         {"DCRED_E"                     ,        12,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10953         {"DCRED_F"                     ,        13,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10954         {"L2C_S_E"                     ,        14,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10955         {"L2C_A_F"                     ,        15,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10956         {"LT_FI_E"                     ,        16,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10957         {"LT_FI_F"                     ,        17,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10958         {"RG_FI_E"                     ,        18,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10959         {"RG_FI_F"                     ,        19,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10960         {"RQ_Q2_F"                     ,        20,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10961         {"RQ_Q2_E"                     ,        21,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10962         {"RQ_Q3_F"                     ,        22,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10963         {"RQ_Q3_E"                     ,        23,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10964         {"UOD_PE"                      ,        24,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10965         {"UOD_PF"                      ,        25,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10966         {"N2U_PF"                      ,        26,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10967         {"N2U_PE"                      ,        27,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10968         {"U2N_D_PE"                    ,        28,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10969         {"U2N_D_PF"                    ,        29,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10970         {"U2N_C_PF"                    ,        30,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10971         {"U2N_C_PE"                    ,        31,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10972         {"LTL_F_PE"                    ,        32,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10973         {"LTL_F_PF"                    ,        33,     1,      600,    "R/W1C",        0,      0,      0ull,   0ull},
10974         {"ND4O_RPE"                    ,        34,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10975         {"ND4O_RPF"                    ,        35,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10976         {"ND4O_DPE"                    ,        36,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10977         {"ND4O_DPF"                    ,        37,     1,      600,    "R/W1C",        1,      0,      0,      0ull},
10978         {"RESERVED_38_63"              ,        38,     26,     600,    "RAZ",  1,      1,      0,      0},
10979         {"ATE_RESET"                   ,        0,      1,      601,    "R/W",  0,      0,      0ull,   0ull},
10980         {"TDATA_IN"                    ,        1,      8,      601,    "R/W",  0,      0,      0ull,   0ull},
10981         {"TADDR_IN"                    ,        9,      4,      601,    "R/W",  0,      0,      0ull,   0ull},
10982         {"TDATA_SEL"                   ,        13,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10983         {"BIST_ENB"                    ,        14,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10984         {"VTEST_ENB"                   ,        15,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10985         {"LOOP_ENB"                    ,        16,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10986         {"TX_BS_EN"                    ,        17,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10987         {"TX_BS_ENH"                   ,        18,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10988         {"TUNING"                      ,        19,     4,      601,    "R/W",  0,      0,      9ull,   0ull},
10989         {"HST_MODE"                    ,        23,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10990         {"DM_PULLD"                    ,        24,     1,      601,    "R/W",  0,      0,      1ull,   1ull},
10991         {"DP_PULLD"                    ,        25,     1,      601,    "R/W",  0,      0,      1ull,   1ull},
10992         {"TCLK"                        ,        26,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10993         {"USBP_BIST"                   ,        27,     1,      601,    "R/W",  0,      0,      1ull,   1ull},
10994         {"USBC_END"                    ,        28,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10995         {"DMA_BMODE"                   ,        29,     1,      601,    "R/W",  0,      0,      0ull,   0ull},
10996         {"RESERVED_30_31"              ,        30,     2,      601,    "RAZ",  0,      0,      0ull,   0ull},
10997         {"TDATA_OUT"                   ,        32,     4,      601,    "RO",   1,      1,      0,      0},
10998         {"BIST_ERR"                    ,        36,     1,      601,    "RO",   0,      0,      0ull,   0ull},
10999         {"BIST_DONE"                   ,        37,     1,      601,    "RO",   0,      0,      0ull,   0ull},
11000         {"RESERVED_38_63"              ,        38,     26,     601,    "RAZ",  1,      1,      0,      0},
11001         {"ZIP_CTL"                     ,        0,      4,      602,    "RO",   1,      0,      0,      0ull},
11002         {"ZIP_CORE"                    ,        4,      27,     602,    "RO",   1,      0,      0,      0ull},
11003         {"RESERVED_31_63"              ,        31,     33,     602,    "RAZ",  1,      0,      0,      0ull},
11004         {"PTR"                         ,        0,      33,     603,    "R/W",  0,      0,      0ull,   0ull},
11005         {"SIZE"                        ,        33,     13,     603,    "R/W",  0,      0,      0ull,   0ull},
11006         {"POOL"                        ,        46,     3,      603,    "R/W",  0,      0,      0ull,   0ull},
11007         {"DWB"                         ,        49,     9,      603,    "R/W",  0,      0,      0ull,   0ull},
11008         {"RESERVED_58_63"              ,        58,     6,      603,    "RAZ",  0,      0,      0ull,   0ull},
11009         {"RESET"                       ,        0,      1,      604,    "RAZ",  0,      0,      0ull,   0ull},
11010         {"FORCECLK"                    ,        1,      1,      604,    "R/W",  0,      0,      0ull,   0ull},
11011         {"RESERVED_2_63"               ,        2,      62,     604,    "RAZ",  0,      0,      0ull,   0ull},
11012         {"DISABLED"                    ,        0,      1,      605,    "RO",   0,      0,      0ull,   0ull},
11013         {"RESERVED_1_7"                ,        1,      7,      605,    "RAZ",  0,      0,      0ull,   0ull},
11014         {"CTXSIZE"                     ,        8,      12,     605,    "RO",   0,      0,      1536ull,        1536ull},
11015         {"ONFSIZE"                     ,        20,     12,     605,    "RO",   0,      0,      512ull, 512ull},
11016         {"DEPTH"                       ,        32,     16,     605,    "RO",   0,      0,      31744ull,       31744ull},
11017         {"RESERVED_48_63"              ,        48,     16,     605,    "RAZ",  1,      0,      0,      0ull},
11018         {"ASSERTS"                     ,        0,      14,     606,    "RO",   0,      0,      0ull,   0ull},
11019         {"RESERVED_14_63"              ,        14,     50,     606,    "RAZ",  1,      0,      0,      0ull},
11020         {"DOORBELL"                    ,        0,      1,      607,    "R/W1C",        0,      0,      0ull,   0ull},
11021         {"RESERVED_1_63"               ,        1,      63,     607,    "RAZ",  1,      0,      0,      0ull},
11022         {"DOORBELL"                    ,        0,      1,      608,    "R/W",  0,      0,      0ull,   0ull},
11023         {"RESERVED_1_63"               ,        1,      63,     608,    "RAZ",  1,      0,      0,      0ull},
11024         {NULL,0,0,0,0,0,0,0,0}
11025 };
11026 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn30xx[] = {
11027          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
11028         {"cvmx_asx#_gmii_rx_clk_set"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      2,      0},
11029         {"cvmx_asx#_gmii_rx_dat_set"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1,      2,      2},
11030         {"cvmx_asx#_int_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      6,      4},
11031         {"cvmx_asx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     3,      6,      10},
11032         {"cvmx_asx#_mii_rx_dat_set"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      2,      16},
11033         {"cvmx_asx#_prt_loop"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     5,      4,      18},
11034         {"cvmx_asx#_rx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      2,      22},
11035         {"cvmx_asx#_rx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     9,      2,      24},
11036         {"cvmx_asx#_tx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     2,      26},
11037         {"cvmx_asx#_tx_comp_byp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     13,     4,      28},
11038         {"cvmx_asx#_tx_hi_water#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     2,      32},
11039         {"cvmx_asx#_tx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     17,     2,      34},
11040         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     18,     2,      36},
11041         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     19,     2,      38},
11042         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     20,     2,      40},
11043         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     21,     2,      42},
11044         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     22,     19,     44},
11045         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     25,     2,      63},
11046         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     28,     19,     65},
11047         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     31,     2,      84},
11048         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     32,     2,      86},
11049         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     33,     2,      88},
11050         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     34,     2,      90},
11051         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     35,     2,      92},
11052         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     36,     2,      94},
11053         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     37,     1,      96},
11054         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     38,     2,      97},
11055         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     39,     2,      99},
11056         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     40,     4,      101},
11057         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     41,     2,      105},
11058         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     42,     3,      107},
11059         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     46,     7,      110},
11060         {"cvmx_dbg_data"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     47,     6,      117},
11061         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     48,     6,      123},
11062         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     49,     7,      129},
11063         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     50,     29,     136},
11064         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     51,     29,     165},
11065         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     52,     2,      194},
11066         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     60,     2,      196},
11067         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     68,     3,      198},
11068         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     69,     3,      201},
11069         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     70,     2,      204},
11070         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     71,     2,      206},
11071         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     72,     8,      208},
11072         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     73,     2,      216},
11073         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     74,     4,      218},
11074         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     75,     2,      222},
11075         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     76,     5,      224},
11076         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     79,     1,      229},
11077         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     82,     1,      230},
11078         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     85,     1,      231},
11079         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     88,     1,      232},
11080         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     91,     1,      233},
11081         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     94,     1,      234},
11082         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     97,     2,      235},
11083         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     100,    4,      237},
11084         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     103,    2,      241},
11085         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     106,    11,     243},
11086         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     109,    10,     254},
11087         {"cvmx_gmx#_rx#_frm_max"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     112,    2,      264},
11088         {"cvmx_gmx#_rx#_frm_min"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     115,    2,      266},
11089         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     118,    2,      268},
11090         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     121,    20,     270},
11091         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     124,    20,     290},
11092         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     127,    2,      310},
11093         {"cvmx_gmx#_rx#_rx_inbnd"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     130,    4,      312},
11094         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     133,    2,      316},
11095         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     136,    2,      318},
11096         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     139,    2,      320},
11097         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     142,    2,      322},
11098         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     145,    2,      324},
11099         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     148,    2,      326},
11100         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     151,    2,      328},
11101         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     154,    2,      330},
11102         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     157,    2,      332},
11103         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     160,    2,      334},
11104         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     163,    4,      336},
11105         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     166,    2,      340},
11106         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     169,    2,      342},
11107         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     172,    2,      344},
11108         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     175,    4,      346},
11109         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     176,    2,      350},
11110         {"cvmx_gmx#_rx_tx_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     177,    4,      352},
11111         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     178,    2,      356},
11112         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     181,    3,      358},
11113         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     182,    5,      361},
11114         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     185,    2,      366},
11115         {"cvmx_gmx#_tx#_clk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     188,    2,      368},
11116         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     191,    3,      370},
11117         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     194,    2,      373},
11118         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     197,    2,      375},
11119         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     200,    2,      377},
11120         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     203,    2,      379},
11121         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     206,    2,      381},
11122         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     209,    2,      383},
11123         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     212,    2,      385},
11124         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     215,    2,      387},
11125         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     218,    2,      389},
11126         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     221,    2,      391},
11127         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     224,    2,      393},
11128         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     227,    2,      395},
11129         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     230,    2,      397},
11130         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     233,    2,      399},
11131         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     236,    2,      401},
11132         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     239,    2,      403},
11133         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     242,    2,      405},
11134         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     245,    2,      407},
11135         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     248,    2,      409},
11136         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     251,    2,      411},
11137         {"cvmx_gmx#_tx_clk_msk#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     252,    2,      413},
11138         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     254,    2,      415},
11139         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     255,    2,      417},
11140         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     256,    3,      419},
11141         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     257,    10,     422},
11142         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     258,    10,     432},
11143         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     259,    2,      442},
11144         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     260,    2,      444},
11145         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     261,    6,      446},
11146         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     262,    2,      452},
11147         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     263,    2,      454},
11148         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     264,    2,      456},
11149         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     265,    7,      458},
11150         {"cvmx_gpio_boot_ena"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     281,    3,      465},
11151         {"cvmx_gpio_dbg_ena"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     282,    2,      468},
11152         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     283,    2,      470},
11153         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     284,    2,      472},
11154         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     285,    2,      474},
11155         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     286,    2,      476},
11156         {"cvmx_gpio_xbit_cfg#"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     287,    6,      478},
11157         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     295,    19,     484},
11158         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     296,    6,      503},
11159         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     297,    3,      509},
11160         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     298,    5,      512},
11161         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     299,    5,      517},
11162         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     300,    1,      522},
11163         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     301,    1,      523},
11164         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     302,    5,      524},
11165         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     303,    5,      529},
11166         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     304,    5,      534},
11167         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     305,    5,      539},
11168         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     306,    1,      544},
11169         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     307,    1,      545},
11170         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     308,    2,      546},
11171         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     309,    2,      548},
11172         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     310,    2,      550},
11173         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     311,    2,      552},
11174         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     312,    17,     554},
11175         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     313,    2,      571},
11176         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     314,    1,      573},
11177         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     315,    10,     574},
11178         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     316,    6,      584},
11179         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     317,    6,      590},
11180         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     318,    2,      596},
11181         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     319,    2,      598},
11182         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     320,    2,      600},
11183         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     321,    3,      602},
11184         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     325,    2,      605},
11185         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     329,    6,      607},
11186         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     330,    5,      613},
11187         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     331,    6,      618},
11188         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     332,    7,      624},
11189         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     333,    2,      631},
11190         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     341,    2,      633},
11191         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     342,    3,      635},
11192         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     343,    5,      638},
11193         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     351,    3,      643},
11194         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     352,    2,      646},
11195         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     353,    2,      648},
11196         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     354,    2,      650},
11197         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     355,    7,      652},
11198         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     356,    6,      659},
11199         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     357,    8,      665},
11200         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     358,    9,      673},
11201         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     359,    10,     682},
11202         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     360,    5,      692},
11203         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     361,    4,      697},
11204         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     362,    2,      701},
11205         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     363,    17,     703},
11206         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     364,    19,     720},
11207         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     365,    3,      739},
11208         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     366,    4,      742},
11209         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     367,    2,      746},
11210         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     371,    17,     748},
11211         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     372,    2,      765},
11212         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     373,    2,      767},
11213         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     374,    3,      769},
11214         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     375,    2,      772},
11215         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     376,    2,      774},
11216         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     377,    2,      776},
11217         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     378,    7,      778},
11218         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     379,    6,      785},
11219         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     380,    3,      791},
11220         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     381,    3,      794},
11221         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     382,    2,      797},
11222         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     383,    2,      799},
11223         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     384,    2,      801},
11224         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     385,    3,      803},
11225         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     386,    15,     806},
11226         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     387,    9,      821},
11227         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     388,    20,     830},
11228         {"cvmx_lmc#_ctl1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     389,    2,      850},
11229         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     390,    2,      852},
11230         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     391,    2,      854},
11231         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     392,    18,     856},
11232         {"cvmx_lmc#_delay_cfg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     393,    4,      874},
11233         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     394,    5,      878},
11234         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     395,    6,      883},
11235         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     396,    2,      889},
11236         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     397,    2,      891},
11237         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     398,    14,     893},
11238         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     399,    10,     907},
11239         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     400,    2,      917},
11240         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     401,    2,      919},
11241         {"cvmx_lmc#_pll_bwctl"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     402,    3,      921},
11242         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     403,    9,      924},
11243         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     404,    5,      933},
11244         {"cvmx_lmc#_wodt_ctl1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     405,    5,      938},
11245         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     406,    5,      943},
11246         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     407,    3,      948},
11247         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     408,    3,      951},
11248         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     409,    3,      954},
11249         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     410,    5,      957},
11250         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     412,    1,      962},
11251         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     413,    10,     963},
11252         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     421,    13,     973},
11253         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     429,    4,      986},
11254         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     430,    2,      990},
11255         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     431,    2,      992},
11256         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     432,    10,     994},
11257         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     433,    9,      1004},
11258         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     434,    2,      1013},
11259         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     435,    8,      1015},
11260         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     436,    4,      1023},
11261         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     437,    2,      1027},
11262         {"cvmx_mio_fus_unlock"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     438,    2,      1029},
11263         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     439,    2,      1031},
11264         {"cvmx_mio_pll_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     440,    2,      1033},
11265         {"cvmx_mio_pll_setting"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     441,    2,      1035},
11266         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     442,    13,     1037},
11267         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     443,    12,     1050},
11268         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     444,    3,      1062},
11269         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     445,    3,      1065},
11270         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     446,    2,      1068},
11271         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     448,    2,      1070},
11272         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     450,    2,      1072},
11273         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     452,    7,      1074},
11274         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     454,    2,      1081},
11275         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     456,    7,      1083},
11276         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     458,    4,      1090},
11277         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     460,    8,      1094},
11278         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     462,    9,      1102},
11279         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     464,    7,      1111},
11280         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     466,    9,      1118},
11281         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     468,    2,      1127},
11282         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     470,    2,      1129},
11283         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     472,    4,      1131},
11284         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     474,    2,      1135},
11285         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     476,    2,      1137},
11286         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     478,    2,      1139},
11287         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     480,    4,      1141},
11288         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     482,    2,      1145},
11289         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     484,    2,      1147},
11290         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     486,    2,      1149},
11291         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     488,    2,      1151},
11292         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     490,    2,      1153},
11293         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     492,    2,      1155},
11294         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     494,    6,      1157},
11295         {"cvmx_mpi_cfg"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     496,    14,     1163},
11296         {"cvmx_mpi_dat#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     497,    2,      1177},
11297         {"cvmx_mpi_sts"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     506,    4,      1179},
11298         {"cvmx_mpi_tx"                 ,        CVMX_CSR_DB_TYPE_NCB,   64,     507,    6,      1183},
11299         {"cvmx_npi_base_addr_input#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     508,    2,      1189},
11300         {"cvmx_npi_base_addr_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     509,    2,      1191},
11301         {"cvmx_npi_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     510,    19,     1193},
11302         {"cvmx_npi_buff_size_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     511,    3,      1212},
11303         {"cvmx_npi_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     512,    15,     1215},
11304         {"cvmx_npi_dbg_select"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     513,    2,      1230},
11305         {"cvmx_npi_dma_control"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     514,    13,     1232},
11306         {"cvmx_npi_dma_highp_counts"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     515,    3,      1245},
11307         {"cvmx_npi_dma_highp_naddr"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     516,    3,      1248},
11308         {"cvmx_npi_dma_lowp_counts"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     517,    3,      1251},
11309         {"cvmx_npi_dma_lowp_naddr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     518,    3,      1254},
11310         {"cvmx_npi_highp_dbell"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     519,    2,      1257},
11311         {"cvmx_npi_highp_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     520,    2,      1259},
11312         {"cvmx_npi_input_control"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     521,    9,      1261},
11313         {"cvmx_npi_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     522,    45,     1270},
11314         {"cvmx_npi_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     523,    45,     1315},
11315         {"cvmx_npi_lowp_dbell"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     524,    2,      1360},
11316         {"cvmx_npi_lowp_ibuff_saddr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     525,    2,      1362},
11317         {"cvmx_npi_mem_access_subid#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     526,    10,     1364},
11318         {"cvmx_npi_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     530,    1,      1374},
11319         {"cvmx_npi_num_desc_output#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     531,    2,      1375},
11320         {"cvmx_npi_output_control"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     532,    14,     1377},
11321         {"cvmx_npi_p#_dbpair_addr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     533,    3,      1391},
11322         {"cvmx_npi_p#_instr_addr"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     534,    2,      1394},
11323         {"cvmx_npi_p#_instr_cnts"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     535,    3,      1396},
11324         {"cvmx_npi_p#_pair_cnts"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     536,    3,      1399},
11325         {"cvmx_npi_pci_burst_size"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     537,    3,      1402},
11326         {"cvmx_npi_pci_int_arb_cfg"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     538,    4,      1405},
11327         {"cvmx_npi_pci_read_cmd"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     539,    2,      1409},
11328         {"cvmx_npi_port32_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     540,    13,     1411},
11329         {"cvmx_npi_port_bp_control"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     541,    3,      1424},
11330         {"cvmx_npi_rsl_int_blocks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     542,    33,     1427},
11331         {"cvmx_npi_size_input#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     543,    2,      1460},
11332         {"cvmx_npi_win_read_to"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     544,    2,      1462},
11333         {"cvmx_pci_bar1_index#"        ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     545,    5,      1464},
11334         {"cvmx_pci_cfg00"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     577,    2,      1469},
11335         {"cvmx_pci_cfg01"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     578,    24,     1471},
11336         {"cvmx_pci_cfg02"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     579,    2,      1495},
11337         {"cvmx_pci_cfg03"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     580,    7,      1497},
11338         {"cvmx_pci_cfg04"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     581,    5,      1504},
11339         {"cvmx_pci_cfg05"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     582,    1,      1509},
11340         {"cvmx_pci_cfg06"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     583,    5,      1510},
11341         {"cvmx_pci_cfg07"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     584,    1,      1515},
11342         {"cvmx_pci_cfg08"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     585,    4,      1516},
11343         {"cvmx_pci_cfg09"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     586,    2,      1520},
11344         {"cvmx_pci_cfg10"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     587,    1,      1522},
11345         {"cvmx_pci_cfg11"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     588,    2,      1523},
11346         {"cvmx_pci_cfg12"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     589,    4,      1525},
11347         {"cvmx_pci_cfg13"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     590,    2,      1529},
11348         {"cvmx_pci_cfg15"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     591,    4,      1531},
11349         {"cvmx_pci_cfg16"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     592,    16,     1535},
11350         {"cvmx_pci_cfg17"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     593,    1,      1551},
11351         {"cvmx_pci_cfg18"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     594,    1,      1552},
11352         {"cvmx_pci_cfg19"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     595,    18,     1553},
11353         {"cvmx_pci_cfg20"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     596,    1,      1571},
11354         {"cvmx_pci_cfg21"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     597,    1,      1572},
11355         {"cvmx_pci_cfg22"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     598,    7,      1573},
11356         {"cvmx_pci_cfg56"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     599,    7,      1580},
11357         {"cvmx_pci_cfg57"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     600,    13,     1587},
11358         {"cvmx_pci_cfg58"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     601,    10,     1600},
11359         {"cvmx_pci_cfg59"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     602,    10,     1610},
11360         {"cvmx_pci_cfg60"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     603,    7,      1620},
11361         {"cvmx_pci_cfg61"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     604,    2,      1627},
11362         {"cvmx_pci_cfg62"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     605,    1,      1629},
11363         {"cvmx_pci_cfg63"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     606,    2,      1630},
11364         {"cvmx_pci_ctl_status_2"       ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     607,    22,     1632},
11365         {"cvmx_pci_dbell#"             ,        CVMX_CSR_DB_TYPE_PCI,   32,     608,    2,      1654},
11366         {"cvmx_pci_dma_cnt#"           ,        CVMX_CSR_DB_TYPE_PCI,   32,     609,    1,      1656},
11367         {"cvmx_pci_dma_int_lev#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     611,    1,      1657},
11368         {"cvmx_pci_dma_time#"          ,        CVMX_CSR_DB_TYPE_PCI,   32,     613,    1,      1658},
11369         {"cvmx_pci_instr_count#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     615,    1,      1659},
11370         {"cvmx_pci_int_enb"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     616,    31,     1660},
11371         {"cvmx_pci_int_enb2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     617,    31,     1691},
11372         {"cvmx_pci_int_sum"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     618,    31,     1722},
11373         {"cvmx_pci_int_sum2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     619,    31,     1753},
11374         {"cvmx_pci_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI,   32,     620,    2,      1784},
11375         {"cvmx_pci_pkt_credits#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     621,    2,      1786},
11376         {"cvmx_pci_pkts_sent#"         ,        CVMX_CSR_DB_TYPE_PCI,   32,     622,    1,      1788},
11377         {"cvmx_pci_pkts_sent_int_lev#" ,        CVMX_CSR_DB_TYPE_PCI,   32,     623,    1,      1789},
11378         {"cvmx_pci_pkts_sent_time#"    ,        CVMX_CSR_DB_TYPE_PCI,   32,     624,    1,      1790},
11379         {"cvmx_pci_read_cmd_6"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     625,    3,      1791},
11380         {"cvmx_pci_read_cmd_c"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     626,    3,      1794},
11381         {"cvmx_pci_read_cmd_e"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     627,    3,      1797},
11382         {"cvmx_pci_read_timeout"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     628,    3,      1800},
11383         {"cvmx_pci_scm_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     629,    2,      1803},
11384         {"cvmx_pci_tsr_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     630,    2,      1805},
11385         {"cvmx_pci_win_rd_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     631,    4,      1807},
11386         {"cvmx_pci_win_rd_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     632,    1,      1811},
11387         {"cvmx_pci_win_wr_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     633,    4,      1812},
11388         {"cvmx_pci_win_wr_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     634,    1,      1816},
11389         {"cvmx_pci_win_wr_mask"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     635,    2,      1817},
11390         {"cvmx_pcm#_dma_cfg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     636,    12,     1819},
11391         {"cvmx_pcm#_int_ena"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     640,    9,      1831},
11392         {"cvmx_pcm#_int_sum"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     644,    9,      1840},
11393         {"cvmx_pcm#_rxaddr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     648,    2,      1849},
11394         {"cvmx_pcm#_rxcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     652,    2,      1851},
11395         {"cvmx_pcm#_rxmsk0"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     656,    1,      1853},
11396         {"cvmx_pcm#_rxmsk1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     660,    1,      1854},
11397         {"cvmx_pcm#_rxmsk2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     664,    1,      1855},
11398         {"cvmx_pcm#_rxmsk3"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     668,    1,      1856},
11399         {"cvmx_pcm#_rxmsk4"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     672,    1,      1857},
11400         {"cvmx_pcm#_rxmsk5"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     676,    1,      1858},
11401         {"cvmx_pcm#_rxmsk6"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     680,    1,      1859},
11402         {"cvmx_pcm#_rxmsk7"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     684,    1,      1860},
11403         {"cvmx_pcm#_rxstart"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     688,    3,      1861},
11404         {"cvmx_pcm#_tdm_cfg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     692,    6,      1864},
11405         {"cvmx_pcm#_tdm_dbg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     696,    1,      1870},
11406         {"cvmx_pcm#_txaddr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     700,    3,      1871},
11407         {"cvmx_pcm#_txcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     704,    2,      1874},
11408         {"cvmx_pcm#_txmsk0"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     708,    1,      1876},
11409         {"cvmx_pcm#_txmsk1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     712,    1,      1877},
11410         {"cvmx_pcm#_txmsk2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     716,    1,      1878},
11411         {"cvmx_pcm#_txmsk3"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     720,    1,      1879},
11412         {"cvmx_pcm#_txmsk4"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     724,    1,      1880},
11413         {"cvmx_pcm#_txmsk5"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     728,    1,      1881},
11414         {"cvmx_pcm#_txmsk6"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     732,    1,      1882},
11415         {"cvmx_pcm#_txmsk7"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     736,    1,      1883},
11416         {"cvmx_pcm#_txstart"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     740,    3,      1884},
11417         {"cvmx_pcm_clk#_cfg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     744,    12,     1887},
11418         {"cvmx_pcm_clk#_dbg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     746,    1,      1899},
11419         {"cvmx_pcm_clk#_gen"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     748,    3,      1900},
11420         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     750,    2,      1903},
11421         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     751,    4,      1905},
11422         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     755,    8,      1909},
11423         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     756,    16,     1917},
11424         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     757,    10,     1933},
11425         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     758,    10,     1943},
11426         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     759,    2,      1953},
11427         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     760,    16,     1955},
11428         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     765,    25,     1971},
11429         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     770,    2,      1996},
11430         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     834,    2,      1998},
11431         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     842,    9,      2000},
11432         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     846,    2,      2009},
11433         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     847,    2,      2011},
11434         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     848,    2,      2013},
11435         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     853,    2,      2015},
11436         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     858,    2,      2017},
11437         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     863,    2,      2019},
11438         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     868,    2,      2021},
11439         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     873,    2,      2023},
11440         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     878,    2,      2025},
11441         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     883,    2,      2027},
11442         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     888,    2,      2029},
11443         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     893,    2,      2031},
11444         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     898,    2,      2033},
11445         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     899,    2,      2035},
11446         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     904,    2,      2037},
11447         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     909,    2,      2039},
11448         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     914,    2,      2041},
11449         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     978,    2,      2043},
11450         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     979,    3,      2045},
11451         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     980,    3,      2048},
11452         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     981,    2,      2051},
11453         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     982,    2,      2053},
11454         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     983,    4,      2055},
11455         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     984,    5,      2059},
11456         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     985,    4,      2064},
11457         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     986,    5,      2068},
11458         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     987,    1,      2073},
11459         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     988,    4,      2074},
11460         {"cvmx_pko_mem_debug14"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     989,    2,      2078},
11461         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     990,    5,      2080},
11462         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     991,    5,      2085},
11463         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     992,    1,      2090},
11464         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     993,    19,     2091},
11465         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     994,    7,      2110},
11466         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     995,    4,      2117},
11467         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     996,    6,      2121},
11468         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     997,    6,      2127},
11469         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     998,    9,      2133},
11470         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     999,    5,      2142},
11471         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1000,   13,     2147},
11472         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1001,   4,      2160},
11473         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1002,   2,      2164},
11474         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1003,   3,      2166},
11475         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1004,   5,      2169},
11476         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1005,   3,      2174},
11477         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1006,   3,      2177},
11478         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1007,   2,      2180},
11479         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1008,   3,      2182},
11480         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1009,   12,     2185},
11481         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1010,   2,      2197},
11482         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1011,   13,     2199},
11483         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1012,   3,      2212},
11484         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1013,   2,      2215},
11485         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1021,   2,      2217},
11486         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1022,   2,      2219},
11487         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1023,   2,      2221},
11488         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1024,   2,      2223},
11489         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1025,   5,      2225},
11490         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1033,   10,     2230},
11491         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1041,   2,      2240},
11492         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1042,   2,      2242},
11493         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1043,   2,      2244},
11494         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1051,   3,      2246},
11495         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1052,   6,      2249},
11496         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1068,   5,      2255},
11497         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1069,   7,      2260},
11498         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1085,   2,      2267},
11499         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1101,   3,      2269},
11500         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1102,   5,      2272},
11501         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1103,   8,      2277},
11502         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1104,   6,      2285},
11503         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1105,   2,      2291},
11504         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1106,   4,      2293},
11505         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1107,   4,      2297},
11506         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1108,   6,      2301},
11507         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1109,   3,      2307},
11508         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1110,   5,      2310},
11509         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1111,   4,      2315},
11510         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1112,   6,      2319},
11511         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1113,   4,      2325},
11512         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1114,   2,      2329},
11513         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1115,   4,      2331},
11514         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1116,   2,      2335},
11515         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1117,   3,      2337},
11516         {"cvmx_usbc#_daint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1118,   2,      2340},
11517         {"cvmx_usbc#_daintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1119,   2,      2342},
11518         {"cvmx_usbc#_dcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1120,   8,      2344},
11519         {"cvmx_usbc#_dctl"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1121,   11,     2352},
11520         {"cvmx_usbc#_diepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1122,   15,     2363},
11521         {"cvmx_usbc#_diepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1127,   8,      2378},
11522         {"cvmx_usbc#_diepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1132,   8,      2386},
11523         {"cvmx_usbc#_dieptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1133,   4,      2394},
11524         {"cvmx_usbc#_doepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1138,   15,     2398},
11525         {"cvmx_usbc#_doepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1143,   6,      2413},
11526         {"cvmx_usbc#_doepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1148,   6,      2419},
11527         {"cvmx_usbc#_doeptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1149,   4,      2425},
11528         {"cvmx_usbc#_dptxfsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1154,   2,      2429},
11529         {"cvmx_usbc#_dsts"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1158,   6,      2431},
11530         {"cvmx_usbc#_dtknqr1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1159,   4,      2437},
11531         {"cvmx_usbc#_dtknqr2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1160,   1,      2441},
11532         {"cvmx_usbc#_dtknqr3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1161,   1,      2442},
11533         {"cvmx_usbc#_dtknqr4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1162,   1,      2443},
11534         {"cvmx_usbc#_gahbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1163,   7,      2444},
11535         {"cvmx_usbc#_ghwcfg1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1164,   1,      2451},
11536         {"cvmx_usbc#_ghwcfg2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1165,   14,     2452},
11537         {"cvmx_usbc#_ghwcfg3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1166,   10,     2466},
11538         {"cvmx_usbc#_ghwcfg4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1167,   12,     2476},
11539         {"cvmx_usbc#_gintmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1168,   32,     2488},
11540         {"cvmx_usbc#_gintsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1169,   32,     2520},
11541         {"cvmx_usbc#_gnptxfsiz"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1170,   2,      2552},
11542         {"cvmx_usbc#_gnptxsts"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1171,   4,      2554},
11543         {"cvmx_usbc#_gotgctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1172,   13,     2558},
11544         {"cvmx_usbc#_gotgint"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1173,   10,     2571},
11545         {"cvmx_usbc#_grstctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1174,   10,     2581},
11546         {"cvmx_usbc#_grxfsiz"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1175,   2,      2591},
11547         {"cvmx_usbc#_grxstspd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1176,   6,      2593},
11548         {"cvmx_usbc#_grxstsph"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1177,   5,      2599},
11549         {"cvmx_usbc#_grxstsrd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1178,   6,      2604},
11550         {"cvmx_usbc#_grxstsrh"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1179,   5,      2610},
11551         {"cvmx_usbc#_gsnpsid"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1180,   1,      2615},
11552         {"cvmx_usbc#_gusbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1181,   13,     2616},
11553         {"cvmx_usbc#_haint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1182,   2,      2629},
11554         {"cvmx_usbc#_haintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1183,   2,      2631},
11555         {"cvmx_usbc#_hcchar#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1184,   11,     2633},
11556         {"cvmx_usbc#_hcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1192,   3,      2644},
11557         {"cvmx_usbc#_hcint#"           ,        CVMX_CSR_DB_TYPE_NCB,   32,     1193,   12,     2647},
11558         {"cvmx_usbc#_hcintmsk#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1201,   12,     2659},
11559         {"cvmx_usbc#_hcsplt#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1209,   6,      2671},
11560         {"cvmx_usbc#_hctsiz#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1217,   4,      2677},
11561         {"cvmx_usbc#_hfir"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1225,   2,      2681},
11562         {"cvmx_usbc#_hfnum"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1226,   2,      2683},
11563         {"cvmx_usbc#_hprt"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1227,   15,     2685},
11564         {"cvmx_usbc#_hptxfsiz"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1228,   2,      2700},
11565         {"cvmx_usbc#_hptxsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1229,   3,      2702},
11566         {"cvmx_usbc#_nptxdfifo#"       ,        CVMX_CSR_DB_TYPE_NCB,   32,     1230,   1,      2705},
11567         {"cvmx_usbc#_pcgcctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1238,   6,      2706},
11568         {"cvmx_usbn#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1239,   4,      2712},
11569         {"cvmx_usbn#_clk_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1240,   15,     2716},
11570         {"cvmx_usbn#_ctl_status"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1241,   6,      2731},
11571         {"cvmx_usbn#_dma0_inb_chn0"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1242,   2,      2737},
11572         {"cvmx_usbn#_dma0_inb_chn1"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1243,   2,      2739},
11573         {"cvmx_usbn#_dma0_inb_chn2"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1244,   2,      2741},
11574         {"cvmx_usbn#_dma0_inb_chn3"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1245,   2,      2743},
11575         {"cvmx_usbn#_dma0_inb_chn4"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1246,   2,      2745},
11576         {"cvmx_usbn#_dma0_inb_chn5"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1247,   2,      2747},
11577         {"cvmx_usbn#_dma0_inb_chn6"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1248,   2,      2749},
11578         {"cvmx_usbn#_dma0_inb_chn7"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1249,   2,      2751},
11579         {"cvmx_usbn#_dma0_outb_chn0"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1250,   2,      2753},
11580         {"cvmx_usbn#_dma0_outb_chn1"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1251,   2,      2755},
11581         {"cvmx_usbn#_dma0_outb_chn2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1252,   2,      2757},
11582         {"cvmx_usbn#_dma0_outb_chn3"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1253,   2,      2759},
11583         {"cvmx_usbn#_dma0_outb_chn4"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1254,   2,      2761},
11584         {"cvmx_usbn#_dma0_outb_chn5"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1255,   2,      2763},
11585         {"cvmx_usbn#_dma0_outb_chn6"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1256,   2,      2765},
11586         {"cvmx_usbn#_dma0_outb_chn7"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1257,   2,      2767},
11587         {"cvmx_usbn#_dma_test"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1258,   7,      2769},
11588         {"cvmx_usbn#_int_enb"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1259,   39,     2776},
11589         {"cvmx_usbn#_int_sum"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1260,   39,     2815},
11590         {"cvmx_usbn#_usbp_ctl_status"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1261,   22,     2854},
11591         {NULL,0,0,0,0,0}
11592 };
11593 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn30xx[] = {
11594         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
11595         {"ASX0_GMII_RX_CLK_SET"        ,           0x11800B0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
11596         {"ASX0_GMII_RX_DAT_SET"        ,           0x11800B0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
11597         {"ASX0_INT_EN"                 ,           0x11800B0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
11598         {"ASX0_INT_REG"                ,           0x11800B0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
11599         {"ASX0_MII_RX_DAT_SET"         ,           0x11800B0000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
11600         {"ASX0_PRT_LOOP"               ,           0x11800B0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
11601         {"ASX0_RX_CLK_SET000"          ,           0x11800B0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
11602         {"ASX0_RX_CLK_SET001"          ,           0x11800B0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
11603         {"ASX0_RX_CLK_SET002"          ,           0x11800B0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
11604         {"ASX0_RX_PRT_EN"              ,           0x11800B0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
11605         {"ASX0_TX_CLK_SET000"          ,           0x11800B0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
11606         {"ASX0_TX_CLK_SET001"          ,           0x11800B0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
11607         {"ASX0_TX_CLK_SET002"          ,           0x11800B0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
11608         {"ASX0_TX_COMP_BYP"            ,           0x11800B0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
11609         {"ASX0_TX_HI_WATER000"         ,           0x11800B0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
11610         {"ASX0_TX_HI_WATER001"         ,           0x11800B0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
11611         {"ASX0_TX_HI_WATER002"         ,           0x11800B0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
11612         {"ASX0_TX_PRT_EN"              ,           0x11800B0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
11613         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     12},
11614         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     13},
11615         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     14},
11616         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     15},
11617         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
11618         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
11619         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
11620         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
11621         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
11622         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
11623         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     18},
11624         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     18},
11625         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     18},
11626         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     19},
11627         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
11628         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     21},
11629         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     22},
11630         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     23},
11631         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
11632         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
11633         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
11634         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
11635         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
11636         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
11637         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
11638         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
11639         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
11640         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
11641         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
11642         {"DBG_DATA"                    ,           0x11F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
11643         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     33},
11644         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     34},
11645         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     35},
11646         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     36},
11647         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
11648         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
11649         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
11650         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
11651         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
11652         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
11653         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
11654         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
11655         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
11656         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
11657         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
11658         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
11659         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
11660         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
11661         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
11662         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
11663         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     39},
11664         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
11665         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
11666         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     42},
11667         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     43},
11668         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
11669         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     45},
11670         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
11671         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
11672         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
11673         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
11674         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
11675         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
11676         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
11677         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
11678         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
11679         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
11680         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
11681         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
11682         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
11683         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
11684         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
11685         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
11686         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
11687         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
11688         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
11689         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
11690         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
11691         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
11692         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
11693         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
11694         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
11695         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
11696         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
11697         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
11698         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
11699         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
11700         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
11701         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
11702         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
11703         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
11704         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
11705         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
11706         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
11707         {"GMX0_RX000_FRM_MAX"          ,           0x1180008000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
11708         {"GMX0_RX001_FRM_MAX"          ,           0x1180008000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
11709         {"GMX0_RX002_FRM_MAX"          ,           0x1180008001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
11710         {"GMX0_RX000_FRM_MIN"          ,           0x1180008000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
11711         {"GMX0_RX001_FRM_MIN"          ,           0x1180008000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
11712         {"GMX0_RX002_FRM_MIN"          ,           0x1180008001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
11713         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
11714         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
11715         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
11716         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
11717         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
11718         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
11719         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
11720         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
11721         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
11722         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
11723         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
11724         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
11725         {"GMX0_RX000_RX_INBND"         ,           0x1180008000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
11726         {"GMX0_RX001_RX_INBND"         ,           0x1180008000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
11727         {"GMX0_RX002_RX_INBND"         ,           0x1180008001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
11728         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
11729         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
11730         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
11731         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
11732         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
11733         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
11734         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
11735         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
11736         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
11737         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
11738         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
11739         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
11740         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
11741         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
11742         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
11743         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
11744         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
11745         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
11746         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
11747         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
11748         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
11749         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
11750         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
11751         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
11752         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
11753         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
11754         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
11755         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
11756         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
11757         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
11758         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
11759         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
11760         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
11761         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
11762         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
11763         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
11764         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
11765         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
11766         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
11767         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
11768         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
11769         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
11770         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
11771         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
11772         {"GMX0_RX_TX_STATUS"           ,           0x11800080007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
11773         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
11774         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
11775         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
11776         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
11777         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
11778         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
11779         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
11780         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
11781         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
11782         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
11783         {"GMX0_TX000_CLK"              ,           0x1180008000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
11784         {"GMX0_TX001_CLK"              ,           0x1180008000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
11785         {"GMX0_TX002_CLK"              ,           0x1180008001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
11786         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
11787         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
11788         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
11789         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
11790         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
11791         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
11792         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
11793         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
11794         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
11795         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
11796         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
11797         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
11798         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
11799         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
11800         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
11801         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
11802         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
11803         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
11804         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
11805         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
11806         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
11807         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
11808         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
11809         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
11810         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
11811         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
11812         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
11813         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
11814         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
11815         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
11816         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
11817         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
11818         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
11819         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
11820         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
11821         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
11822         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
11823         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
11824         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
11825         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
11826         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
11827         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
11828         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
11829         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
11830         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
11831         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
11832         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
11833         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
11834         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
11835         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
11836         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
11837         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
11838         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
11839         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
11840         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
11841         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
11842         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
11843         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
11844         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
11845         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
11846         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
11847         {"GMX0_TX_CLK_MSK000"          ,           0x1180008000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
11848         {"GMX0_TX_CLK_MSK001"          ,           0x1180008000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
11849         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
11850         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
11851         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
11852         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
11853         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
11854         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
11855         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
11856         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
11857         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
11858         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
11859         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
11860         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11861         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11862         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11863         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11864         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11865         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11866         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11867         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11868         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11869         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11870         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11871         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11872         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11873         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11874         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11875         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     121},
11876         {"GPIO_BOOT_ENA"               ,           0x10700000008A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     122},
11877         {"GPIO_DBG_ENA"                ,           0x10700000008A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
11878         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     124},
11879         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     125},
11880         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     126},
11881         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     127},
11882         {"GPIO_XBIT_CFG16"             ,           0x1070000000900ull,  CVMX_CSR_DB_TYPE_NCB,   64,     128},
11883         {"GPIO_XBIT_CFG17"             ,           0x1070000000908ull,  CVMX_CSR_DB_TYPE_NCB,   64,     128},
11884         {"GPIO_XBIT_CFG18"             ,           0x1070000000910ull,  CVMX_CSR_DB_TYPE_NCB,   64,     128},
11885         {"GPIO_XBIT_CFG19"             ,           0x1070000000918ull,  CVMX_CSR_DB_TYPE_NCB,   64,     128},
11886         {"GPIO_XBIT_CFG20"             ,           0x1070000000920ull,  CVMX_CSR_DB_TYPE_NCB,   64,     128},
11887         {"GPIO_XBIT_CFG21"             ,           0x1070000000928ull,  CVMX_CSR_DB_TYPE_NCB,   64,     128},
11888         {"GPIO_XBIT_CFG22"             ,           0x1070000000930ull,  CVMX_CSR_DB_TYPE_NCB,   64,     128},
11889         {"GPIO_XBIT_CFG23"             ,           0x1070000000938ull,  CVMX_CSR_DB_TYPE_NCB,   64,     128},
11890         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
11891         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
11892         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
11893         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
11894         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
11895         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
11896         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
11897         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
11898         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
11899         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
11900         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
11901         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
11902         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
11903         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
11904         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     143},
11905         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     144},
11906         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     145},
11907         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     146},
11908         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     147},
11909         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
11910         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     149},
11911         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     150},
11912         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     151},
11913         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     152},
11914         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     153},
11915         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     154},
11916         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     155},
11917         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     155},
11918         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     155},
11919         {"IPD_PORT32_BP_PAGE_CNT"      ,           0x14F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     155},
11920         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     156},
11921         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     156},
11922         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     156},
11923         {"IPD_PORT_BP_COUNTERS_PAIR32" ,           0x14F00000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     156},
11924         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     157},
11925         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
11926         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     159},
11927         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
11928         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
11929         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
11930         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
11931         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
11932         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
11933         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
11934         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
11935         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
11936         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     162},
11937         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
11938         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
11939         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
11940         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
11941         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
11942         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
11943         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
11944         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
11945         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
11946         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     165},
11947         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
11948         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     167},
11949         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     168},
11950         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
11951         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
11952         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
11953         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
11954         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
11955         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
11956         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
11957         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
11958         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
11959         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
11960         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
11961         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
11962         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
11963         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
11964         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
11965         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
11966         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
11967         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
11968         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
11969         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
11970         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
11971         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
11972         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
11973         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
11974         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
11975         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     191},
11976         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     192},
11977         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     193},
11978         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     194},
11979         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     195},
11980         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     196},
11981         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     197},
11982         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     198},
11983         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     199},
11984         {"LMC0_CTL1"                   ,           0x1180088000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     200},
11985         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
11986         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     202},
11987         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     203},
11988         {"LMC0_DELAY_CFG"              ,           0x1180088000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     204},
11989         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     205},
11990         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     206},
11991         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     207},
11992         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     208},
11993         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     209},
11994         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     210},
11995         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     211},
11996         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     212},
11997         {"LMC0_PLL_BWCTL"              ,           0x1180088000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     213},
11998         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
11999         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
12000         {"LMC0_WODT_CTL1"              ,           0x1180088000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
12001         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
12002         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
12003         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     219},
12004         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     220},
12005         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     221},
12006         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     221},
12007         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
12008         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
12009         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
12010         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
12011         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
12012         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
12013         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
12014         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
12015         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
12016         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
12017         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
12018         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
12019         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
12020         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
12021         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
12022         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
12023         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
12024         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     225},
12025         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     226},
12026         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     227},
12027         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
12028         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
12029         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
12030         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
12031         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     232},
12032         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
12033         {"MIO_FUS_UNLOCK"              ,           0x1180000001578ull,  CVMX_CSR_DB_TYPE_RSL,   64,     234},
12034         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     235},
12035         {"MIO_PLL_CTL"                 ,           0x1180000001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     236},
12036         {"MIO_PLL_SETTING"             ,           0x1180000001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     237},
12037         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
12038         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     239},
12039         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     240},
12040         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
12041         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
12042         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
12043         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     243},
12044         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     243},
12045         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     244},
12046         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     244},
12047         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     245},
12048         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     245},
12049         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     246},
12050         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     246},
12051         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     247},
12052         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     247},
12053         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     248},
12054         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     248},
12055         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     249},
12056         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     249},
12057         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
12058         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
12059         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
12060         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
12061         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
12062         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
12063         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
12064         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
12065         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
12066         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
12067         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
12068         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
12069         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
12070         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
12071         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
12072         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
12073         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
12074         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
12075         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
12076         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
12077         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
12078         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
12079         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
12080         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
12081         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
12082         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
12083         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
12084         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
12085         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
12086         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
12087         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
12088         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
12089         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
12090         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
12091         {"MPI_CFG"                     ,           0x1070000001000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     267},
12092         {"MPI_DAT0"                    ,           0x1070000001080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     268},
12093         {"MPI_DAT1"                    ,           0x1070000001088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     268},
12094         {"MPI_DAT2"                    ,           0x1070000001090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     268},
12095         {"MPI_DAT3"                    ,           0x1070000001098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     268},
12096         {"MPI_DAT4"                    ,           0x10700000010A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     268},
12097         {"MPI_DAT5"                    ,           0x10700000010A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     268},
12098         {"MPI_DAT6"                    ,           0x10700000010B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     268},
12099         {"MPI_DAT7"                    ,           0x10700000010B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     268},
12100         {"MPI_DAT8"                    ,           0x10700000010C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     268},
12101         {"MPI_STS"                     ,           0x1070000001008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     269},
12102         {"MPI_TX"                      ,           0x1070000001010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     270},
12103         {"NPI_BASE_ADDR_INPUT0"        ,           0x11F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     271},
12104         {"NPI_BASE_ADDR_OUTPUT0"       ,           0x11F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     272},
12105         {"NPI_BIST_STATUS"             ,           0x11F00000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     273},
12106         {"NPI_BUFF_SIZE_OUTPUT0"       ,           0x11F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     274},
12107         {"NPI_CTL_STATUS"              ,           0x11F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     275},
12108         {"NPI_DBG_SELECT"              ,           0x11F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     276},
12109         {"NPI_DMA_CONTROL"             ,           0x11F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
12110         {"NPI_DMA_HIGHP_COUNTS"        ,           0x11F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     278},
12111         {"NPI_DMA_HIGHP_NADDR"         ,           0x11F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     279},
12112         {"NPI_DMA_LOWP_COUNTS"         ,           0x11F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     280},
12113         {"NPI_DMA_LOWP_NADDR"          ,           0x11F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     281},
12114         {"NPI_HIGHP_DBELL"             ,           0x11F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     282},
12115         {"NPI_HIGHP_IBUFF_SADDR"       ,           0x11F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     283},
12116         {"NPI_INPUT_CONTROL"           ,           0x11F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     284},
12117         {"NPI_INT_ENB"                 ,           0x11F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     285},
12118         {"NPI_INT_SUM"                 ,           0x11F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
12119         {"NPI_LOWP_DBELL"              ,           0x11F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     287},
12120         {"NPI_LOWP_IBUFF_SADDR"        ,           0x11F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     288},
12121         {"NPI_MEM_ACCESS_SUBID3"       ,           0x11F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     289},
12122         {"NPI_MEM_ACCESS_SUBID4"       ,           0x11F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     289},
12123         {"NPI_MEM_ACCESS_SUBID5"       ,           0x11F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     289},
12124         {"NPI_MEM_ACCESS_SUBID6"       ,           0x11F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     289},
12125         {"NPI_MSI_RCV"                 ,           0x11F0000001190ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     290},
12126         {"NPI_NUM_DESC_OUTPUT0"        ,           0x11F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     291},
12127         {"NPI_OUTPUT_CONTROL"          ,           0x11F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     292},
12128         {"NPI_P0_DBPAIR_ADDR"          ,           0x11F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     293},
12129         {"NPI_P0_INSTR_ADDR"           ,           0x11F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     294},
12130         {"NPI_P0_INSTR_CNTS"           ,           0x11F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     295},
12131         {"NPI_P0_PAIR_CNTS"            ,           0x11F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     296},
12132         {"NPI_PCI_BURST_SIZE"          ,           0x11F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     297},
12133         {"NPI_PCI_INT_ARB_CFG"         ,           0x11F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     298},
12134         {"NPI_PCI_READ_CMD"            ,           0x11F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     299},
12135         {"NPI_PORT32_INSTR_HDR"        ,           0x11F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     300},
12136         {"NPI_PORT_BP_CONTROL"         ,           0x11F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     301},
12137         {"NPI_RSL_INT_BLOCKS"          ,           0x11F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     302},
12138         {"NPI_SIZE_INPUT0"             ,           0x11F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     303},
12139         {"NPI_WIN_READ_TO"             ,           0x11F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     304},
12140         {"PCI_BAR1_INDEX0"             ,           0x11F0000001100ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12141         {"PCI_BAR1_INDEX1"             ,           0x11F0000001104ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12142         {"PCI_BAR1_INDEX2"             ,           0x11F0000001108ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12143         {"PCI_BAR1_INDEX3"             ,           0x11F000000110Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12144         {"PCI_BAR1_INDEX4"             ,           0x11F0000001110ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12145         {"PCI_BAR1_INDEX5"             ,           0x11F0000001114ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12146         {"PCI_BAR1_INDEX6"             ,           0x11F0000001118ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12147         {"PCI_BAR1_INDEX7"             ,           0x11F000000111Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12148         {"PCI_BAR1_INDEX8"             ,           0x11F0000001120ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12149         {"PCI_BAR1_INDEX9"             ,           0x11F0000001124ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12150         {"PCI_BAR1_INDEX10"            ,           0x11F0000001128ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12151         {"PCI_BAR1_INDEX11"            ,           0x11F000000112Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12152         {"PCI_BAR1_INDEX12"            ,           0x11F0000001130ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12153         {"PCI_BAR1_INDEX13"            ,           0x11F0000001134ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12154         {"PCI_BAR1_INDEX14"            ,           0x11F0000001138ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12155         {"PCI_BAR1_INDEX15"            ,           0x11F000000113Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12156         {"PCI_BAR1_INDEX16"            ,           0x11F0000001140ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12157         {"PCI_BAR1_INDEX17"            ,           0x11F0000001144ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12158         {"PCI_BAR1_INDEX18"            ,           0x11F0000001148ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12159         {"PCI_BAR1_INDEX19"            ,           0x11F000000114Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12160         {"PCI_BAR1_INDEX20"            ,           0x11F0000001150ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12161         {"PCI_BAR1_INDEX21"            ,           0x11F0000001154ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12162         {"PCI_BAR1_INDEX22"            ,           0x11F0000001158ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12163         {"PCI_BAR1_INDEX23"            ,           0x11F000000115Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12164         {"PCI_BAR1_INDEX24"            ,           0x11F0000001160ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12165         {"PCI_BAR1_INDEX25"            ,           0x11F0000001164ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12166         {"PCI_BAR1_INDEX26"            ,           0x11F0000001168ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12167         {"PCI_BAR1_INDEX27"            ,           0x11F000000116Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12168         {"PCI_BAR1_INDEX28"            ,           0x11F0000001170ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12169         {"PCI_BAR1_INDEX29"            ,           0x11F0000001174ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12170         {"PCI_BAR1_INDEX30"            ,           0x11F0000001178ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12171         {"PCI_BAR1_INDEX31"            ,           0x11F000000117Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     305},
12172         {"PCI_CFG00"                   ,           0x11F0000001800ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     306},
12173         {"PCI_CFG01"                   ,           0x11F0000001804ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     307},
12174         {"PCI_CFG02"                   ,           0x11F0000001808ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     308},
12175         {"PCI_CFG03"                   ,           0x11F000000180Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     309},
12176         {"PCI_CFG04"                   ,           0x11F0000001810ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     310},
12177         {"PCI_CFG05"                   ,           0x11F0000001814ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     311},
12178         {"PCI_CFG06"                   ,           0x11F0000001818ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     312},
12179         {"PCI_CFG07"                   ,           0x11F000000181Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     313},
12180         {"PCI_CFG08"                   ,           0x11F0000001820ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     314},
12181         {"PCI_CFG09"                   ,           0x11F0000001824ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     315},
12182         {"PCI_CFG10"                   ,           0x11F0000001828ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     316},
12183         {"PCI_CFG11"                   ,           0x11F000000182Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     317},
12184         {"PCI_CFG12"                   ,           0x11F0000001830ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     318},
12185         {"PCI_CFG13"                   ,           0x11F0000001834ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     319},
12186         {"PCI_CFG15"                   ,           0x11F000000183Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     320},
12187         {"PCI_CFG16"                   ,           0x11F0000001840ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     321},
12188         {"PCI_CFG17"                   ,           0x11F0000001844ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     322},
12189         {"PCI_CFG18"                   ,           0x11F0000001848ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     323},
12190         {"PCI_CFG19"                   ,           0x11F000000184Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     324},
12191         {"PCI_CFG20"                   ,           0x11F0000001850ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     325},
12192         {"PCI_CFG21"                   ,           0x11F0000001854ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     326},
12193         {"PCI_CFG22"                   ,           0x11F0000001858ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     327},
12194         {"PCI_CFG56"                   ,           0x11F00000018E0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     328},
12195         {"PCI_CFG57"                   ,           0x11F00000018E4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     329},
12196         {"PCI_CFG58"                   ,           0x11F00000018E8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     330},
12197         {"PCI_CFG59"                   ,           0x11F00000018ECull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     331},
12198         {"PCI_CFG60"                   ,           0x11F00000018F0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     332},
12199         {"PCI_CFG61"                   ,           0x11F00000018F4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     333},
12200         {"PCI_CFG62"                   ,           0x11F00000018F8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     334},
12201         {"PCI_CFG63"                   ,           0x11F00000018FCull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     335},
12202         {"PCI_CTL_STATUS_2"            ,           0x11F000000118Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     336},
12203         {"PCI_DBELL0"                  ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCI,   32,     337},
12204         {"PCI_DMA_CNT0"                ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     338},
12205         {"PCI_DMA_CNT1"                ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCI,   32,     338},
12206         {"PCI_DMA_INT_LEV0"            ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     339},
12207         {"PCI_DMA_INT_LEV1"            ,                      0xACull,  CVMX_CSR_DB_TYPE_PCI,   32,     339},
12208         {"PCI_DMA_TIME0"               ,                      0xB0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     340},
12209         {"PCI_DMA_TIME1"               ,                      0xB4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     340},
12210         {"PCI_INSTR_COUNT0"            ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCI,   32,     341},
12211         {"PCI_INT_ENB"                 ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCI,   64,     342},
12212         {"PCI_INT_ENB2"                ,           0x11F00000011A0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     343},
12213         {"PCI_INT_SUM"                 ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCI,   64,     344},
12214         {"PCI_INT_SUM2"                ,           0x11F0000001198ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     345},
12215         {"PCI_MSI_RCV"                 ,                      0xF0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     346},
12216         {"PCI_PKT_CREDITS0"            ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCI,   32,     347},
12217         {"PCI_PKTS_SENT0"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCI,   32,     348},
12218         {"PCI_PKTS_SENT_INT_LEV0"      ,                      0x48ull,  CVMX_CSR_DB_TYPE_PCI,   32,     349},
12219         {"PCI_PKTS_SENT_TIME0"         ,                      0x4Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     350},
12220         {"PCI_READ_CMD_6"              ,           0x11F0000001180ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     351},
12221         {"PCI_READ_CMD_C"              ,           0x11F0000001184ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     352},
12222         {"PCI_READ_CMD_E"              ,           0x11F0000001188ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     353},
12223         {"PCI_READ_TIMEOUT"            ,           0x11F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     354},
12224         {"PCI_SCM_REG"                 ,           0x11F00000011A8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     355},
12225         {"PCI_TSR_REG"                 ,           0x11F00000011B0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     356},
12226         {"PCI_WIN_RD_ADDR"             ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCI,   64,     357},
12227         {"PCI_WIN_RD_DATA"             ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCI,   64,     358},
12228         {"PCI_WIN_WR_ADDR"             ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCI,   64,     359},
12229         {"PCI_WIN_WR_DATA"             ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCI,   64,     360},
12230         {"PCI_WIN_WR_MASK"             ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCI,   64,     361},
12231         {"PCM0_DMA_CFG"                ,           0x1070000010018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     362},
12232         {"PCM1_DMA_CFG"                ,           0x1070000014018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     362},
12233         {"PCM2_DMA_CFG"                ,           0x1070000018018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     362},
12234         {"PCM3_DMA_CFG"                ,           0x107000001C018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     362},
12235         {"PCM0_INT_ENA"                ,           0x1070000010020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     363},
12236         {"PCM1_INT_ENA"                ,           0x1070000014020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     363},
12237         {"PCM2_INT_ENA"                ,           0x1070000018020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     363},
12238         {"PCM3_INT_ENA"                ,           0x107000001C020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     363},
12239         {"PCM0_INT_SUM"                ,           0x1070000010028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     364},
12240         {"PCM1_INT_SUM"                ,           0x1070000014028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     364},
12241         {"PCM2_INT_SUM"                ,           0x1070000018028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     364},
12242         {"PCM3_INT_SUM"                ,           0x107000001C028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     364},
12243         {"PCM0_RXADDR"                 ,           0x1070000010068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     365},
12244         {"PCM1_RXADDR"                 ,           0x1070000014068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     365},
12245         {"PCM2_RXADDR"                 ,           0x1070000018068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     365},
12246         {"PCM3_RXADDR"                 ,           0x107000001C068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     365},
12247         {"PCM0_RXCNT"                  ,           0x1070000010060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     366},
12248         {"PCM1_RXCNT"                  ,           0x1070000014060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     366},
12249         {"PCM2_RXCNT"                  ,           0x1070000018060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     366},
12250         {"PCM3_RXCNT"                  ,           0x107000001C060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     366},
12251         {"PCM0_RXMSK0"                 ,           0x10700000100C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     367},
12252         {"PCM1_RXMSK0"                 ,           0x10700000140C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     367},
12253         {"PCM2_RXMSK0"                 ,           0x10700000180C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     367},
12254         {"PCM3_RXMSK0"                 ,           0x107000001C0C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     367},
12255         {"PCM0_RXMSK1"                 ,           0x10700000100C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     368},
12256         {"PCM1_RXMSK1"                 ,           0x10700000140C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     368},
12257         {"PCM2_RXMSK1"                 ,           0x10700000180C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     368},
12258         {"PCM3_RXMSK1"                 ,           0x107000001C0C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     368},
12259         {"PCM0_RXMSK2"                 ,           0x10700000100D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     369},
12260         {"PCM1_RXMSK2"                 ,           0x10700000140D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     369},
12261         {"PCM2_RXMSK2"                 ,           0x10700000180D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     369},
12262         {"PCM3_RXMSK2"                 ,           0x107000001C0D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     369},
12263         {"PCM0_RXMSK3"                 ,           0x10700000100D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     370},
12264         {"PCM1_RXMSK3"                 ,           0x10700000140D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     370},
12265         {"PCM2_RXMSK3"                 ,           0x10700000180D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     370},
12266         {"PCM3_RXMSK3"                 ,           0x107000001C0D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     370},
12267         {"PCM0_RXMSK4"                 ,           0x10700000100E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
12268         {"PCM1_RXMSK4"                 ,           0x10700000140E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
12269         {"PCM2_RXMSK4"                 ,           0x10700000180E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
12270         {"PCM3_RXMSK4"                 ,           0x107000001C0E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
12271         {"PCM0_RXMSK5"                 ,           0x10700000100E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     372},
12272         {"PCM1_RXMSK5"                 ,           0x10700000140E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     372},
12273         {"PCM2_RXMSK5"                 ,           0x10700000180E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     372},
12274         {"PCM3_RXMSK5"                 ,           0x107000001C0E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     372},
12275         {"PCM0_RXMSK6"                 ,           0x10700000100F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     373},
12276         {"PCM1_RXMSK6"                 ,           0x10700000140F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     373},
12277         {"PCM2_RXMSK6"                 ,           0x10700000180F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     373},
12278         {"PCM3_RXMSK6"                 ,           0x107000001C0F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     373},
12279         {"PCM0_RXMSK7"                 ,           0x10700000100F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     374},
12280         {"PCM1_RXMSK7"                 ,           0x10700000140F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     374},
12281         {"PCM2_RXMSK7"                 ,           0x10700000180F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     374},
12282         {"PCM3_RXMSK7"                 ,           0x107000001C0F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     374},
12283         {"PCM0_RXSTART"                ,           0x1070000010058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     375},
12284         {"PCM1_RXSTART"                ,           0x1070000014058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     375},
12285         {"PCM2_RXSTART"                ,           0x1070000018058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     375},
12286         {"PCM3_RXSTART"                ,           0x107000001C058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     375},
12287         {"PCM0_TDM_CFG"                ,           0x1070000010010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     376},
12288         {"PCM1_TDM_CFG"                ,           0x1070000014010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     376},
12289         {"PCM2_TDM_CFG"                ,           0x1070000018010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     376},
12290         {"PCM3_TDM_CFG"                ,           0x107000001C010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     376},
12291         {"PCM0_TDM_DBG"                ,           0x1070000010030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     377},
12292         {"PCM1_TDM_DBG"                ,           0x1070000014030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     377},
12293         {"PCM2_TDM_DBG"                ,           0x1070000018030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     377},
12294         {"PCM3_TDM_DBG"                ,           0x107000001C030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     377},
12295         {"PCM0_TXADDR"                 ,           0x1070000010050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     378},
12296         {"PCM1_TXADDR"                 ,           0x1070000014050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     378},
12297         {"PCM2_TXADDR"                 ,           0x1070000018050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     378},
12298         {"PCM3_TXADDR"                 ,           0x107000001C050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     378},
12299         {"PCM0_TXCNT"                  ,           0x1070000010048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     379},
12300         {"PCM1_TXCNT"                  ,           0x1070000014048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     379},
12301         {"PCM2_TXCNT"                  ,           0x1070000018048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     379},
12302         {"PCM3_TXCNT"                  ,           0x107000001C048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     379},
12303         {"PCM0_TXMSK0"                 ,           0x1070000010080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     380},
12304         {"PCM1_TXMSK0"                 ,           0x1070000014080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     380},
12305         {"PCM2_TXMSK0"                 ,           0x1070000018080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     380},
12306         {"PCM3_TXMSK0"                 ,           0x107000001C080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     380},
12307         {"PCM0_TXMSK1"                 ,           0x1070000010088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
12308         {"PCM1_TXMSK1"                 ,           0x1070000014088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
12309         {"PCM2_TXMSK1"                 ,           0x1070000018088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
12310         {"PCM3_TXMSK1"                 ,           0x107000001C088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
12311         {"PCM0_TXMSK2"                 ,           0x1070000010090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
12312         {"PCM1_TXMSK2"                 ,           0x1070000014090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
12313         {"PCM2_TXMSK2"                 ,           0x1070000018090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
12314         {"PCM3_TXMSK2"                 ,           0x107000001C090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
12315         {"PCM0_TXMSK3"                 ,           0x1070000010098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
12316         {"PCM1_TXMSK3"                 ,           0x1070000014098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
12317         {"PCM2_TXMSK3"                 ,           0x1070000018098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
12318         {"PCM3_TXMSK3"                 ,           0x107000001C098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
12319         {"PCM0_TXMSK4"                 ,           0x10700000100A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
12320         {"PCM1_TXMSK4"                 ,           0x10700000140A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
12321         {"PCM2_TXMSK4"                 ,           0x10700000180A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
12322         {"PCM3_TXMSK4"                 ,           0x107000001C0A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
12323         {"PCM0_TXMSK5"                 ,           0x10700000100A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
12324         {"PCM1_TXMSK5"                 ,           0x10700000140A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
12325         {"PCM2_TXMSK5"                 ,           0x10700000180A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
12326         {"PCM3_TXMSK5"                 ,           0x107000001C0A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
12327         {"PCM0_TXMSK6"                 ,           0x10700000100B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
12328         {"PCM1_TXMSK6"                 ,           0x10700000140B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
12329         {"PCM2_TXMSK6"                 ,           0x10700000180B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
12330         {"PCM3_TXMSK6"                 ,           0x107000001C0B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
12331         {"PCM0_TXMSK7"                 ,           0x10700000100B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
12332         {"PCM1_TXMSK7"                 ,           0x10700000140B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
12333         {"PCM2_TXMSK7"                 ,           0x10700000180B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
12334         {"PCM3_TXMSK7"                 ,           0x107000001C0B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
12335         {"PCM0_TXSTART"                ,           0x1070000010040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
12336         {"PCM1_TXSTART"                ,           0x1070000014040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
12337         {"PCM2_TXSTART"                ,           0x1070000018040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
12338         {"PCM3_TXSTART"                ,           0x107000001C040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
12339         {"PCM_CLK0_CFG"                ,           0x1070000010000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
12340         {"PCM_CLK1_CFG"                ,           0x1070000014000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
12341         {"PCM_CLK0_DBG"                ,           0x1070000010038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
12342         {"PCM_CLK1_DBG"                ,           0x1070000014038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
12343         {"PCM_CLK0_GEN"                ,           0x1070000010008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
12344         {"PCM_CLK1_GEN"                ,           0x1070000014008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
12345         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     392},
12346         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
12347         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
12348         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
12349         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
12350         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     394},
12351         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     395},
12352         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     396},
12353         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     397},
12354         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     398},
12355         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     399},
12356         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     399},
12357         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     399},
12358         {"PIP_PRT_CFG32"               ,           0x11800A0000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     399},
12359         {"PIP_PRT_CFG33"               ,           0x11800A0000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     399},
12360         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     400},
12361         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     400},
12362         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     400},
12363         {"PIP_PRT_TAG32"               ,           0x11800A0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     400},
12364         {"PIP_PRT_TAG33"               ,           0x11800A0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     400},
12365         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12366         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12367         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12368         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12369         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12370         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12371         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12372         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12373         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12374         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12375         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12376         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12377         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12378         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12379         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12380         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12381         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12382         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12383         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12384         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12385         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12386         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12387         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12388         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12389         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12390         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12391         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12392         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12393         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12394         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12395         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12396         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12397         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12398         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12399         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12400         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12401         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12402         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12403         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12404         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12405         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12406         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12407         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12408         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12409         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12410         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12411         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12412         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12413         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12414         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12415         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12416         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12417         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12418         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12419         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12420         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12421         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12422         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12423         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12424         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12425         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12426         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12427         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12428         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
12429         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
12430         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
12431         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
12432         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
12433         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
12434         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
12435         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
12436         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
12437         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     403},
12438         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     403},
12439         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     403},
12440         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     403},
12441         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     404},
12442         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     405},
12443         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
12444         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
12445         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
12446         {"PIP_STAT0_PRT32"             ,           0x11800A0001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
12447         {"PIP_STAT0_PRT33"             ,           0x11800A0001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
12448         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
12449         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
12450         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
12451         {"PIP_STAT1_PRT32"             ,           0x11800A0001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
12452         {"PIP_STAT1_PRT33"             ,           0x11800A0001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
12453         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     408},
12454         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     408},
12455         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     408},
12456         {"PIP_STAT2_PRT32"             ,           0x11800A0001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     408},
12457         {"PIP_STAT2_PRT33"             ,           0x11800A0001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     408},
12458         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     409},
12459         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     409},
12460         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     409},
12461         {"PIP_STAT3_PRT32"             ,           0x11800A0001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     409},
12462         {"PIP_STAT3_PRT33"             ,           0x11800A0001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     409},
12463         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
12464         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
12465         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
12466         {"PIP_STAT4_PRT32"             ,           0x11800A0001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
12467         {"PIP_STAT4_PRT33"             ,           0x11800A0001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
12468         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
12469         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
12470         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
12471         {"PIP_STAT5_PRT32"             ,           0x11800A0001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
12472         {"PIP_STAT5_PRT33"             ,           0x11800A0001278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
12473         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
12474         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
12475         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
12476         {"PIP_STAT6_PRT32"             ,           0x11800A0001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
12477         {"PIP_STAT6_PRT33"             ,           0x11800A0001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
12478         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
12479         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
12480         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
12481         {"PIP_STAT7_PRT32"             ,           0x11800A0001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
12482         {"PIP_STAT7_PRT33"             ,           0x11800A0001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
12483         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
12484         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
12485         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
12486         {"PIP_STAT8_PRT32"             ,           0x11800A0001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
12487         {"PIP_STAT8_PRT33"             ,           0x11800A0001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
12488         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
12489         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
12490         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
12491         {"PIP_STAT9_PRT32"             ,           0x11800A0001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
12492         {"PIP_STAT9_PRT33"             ,           0x11800A0001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
12493         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
12494         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
12495         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
12496         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
12497         {"PIP_STAT_INB_ERRS32"         ,           0x11800A0001E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
12498         {"PIP_STAT_INB_ERRS33"         ,           0x11800A0001E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
12499         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
12500         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
12501         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
12502         {"PIP_STAT_INB_OCTS32"         ,           0x11800A0001E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
12503         {"PIP_STAT_INB_OCTS33"         ,           0x11800A0001E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
12504         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
12505         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
12506         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
12507         {"PIP_STAT_INB_PKTS32"         ,           0x11800A0001E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
12508         {"PIP_STAT_INB_PKTS33"         ,           0x11800A0001E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
12509         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12510         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12511         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12512         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12513         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12514         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12515         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12516         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12517         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12518         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12519         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12520         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12521         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12522         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12523         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12524         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12525         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12526         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12527         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12528         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12529         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12530         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12531         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12532         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12533         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12534         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12535         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12536         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12537         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12538         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12539         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12540         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12541         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12542         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12543         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12544         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12545         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12546         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12547         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12548         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12549         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12550         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12551         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12552         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12553         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12554         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12555         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12556         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12557         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12558         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12559         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12560         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12561         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12562         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12563         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12564         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12565         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12566         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12567         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12568         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12569         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12570         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12571         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12572         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
12573         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
12574         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
12575         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
12576         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
12577         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
12578         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
12579         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
12580         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
12581         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
12582         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
12583         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
12584         {"PKO_MEM_DEBUG14"             ,           0x1180050001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
12585         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
12586         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
12587         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
12588         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
12589         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
12590         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
12591         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
12592         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
12593         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
12594         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
12595         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
12596         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
12597         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
12598         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
12599         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     447},
12600         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
12601         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
12602         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
12603         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
12604         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     452},
12605         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     453},
12606         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     454},
12607         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     455},
12608         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     456},
12609         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     456},
12610         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     456},
12611         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     456},
12612         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     456},
12613         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     456},
12614         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     456},
12615         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     456},
12616         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     457},
12617         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     458},
12618         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     459},
12619         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     460},
12620         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     461},
12621         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     461},
12622         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     461},
12623         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     461},
12624         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     461},
12625         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     461},
12626         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     461},
12627         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     461},
12628         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     462},
12629         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     462},
12630         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     462},
12631         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     462},
12632         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     462},
12633         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     462},
12634         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     462},
12635         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     462},
12636         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     463},
12637         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     464},
12638         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     465},
12639         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     465},
12640         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     465},
12641         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     465},
12642         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     465},
12643         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     465},
12644         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     465},
12645         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     465},
12646         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     466},
12647         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12648         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12649         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12650         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12651         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12652         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12653         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12654         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12655         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12656         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12657         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12658         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12659         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12660         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12661         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12662         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     467},
12663         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     468},
12664         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12665         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12666         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12667         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12668         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12669         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12670         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12671         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12672         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12673         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12674         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12675         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12676         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12677         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12678         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12679         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
12680         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12681         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12682         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12683         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12684         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12685         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12686         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12687         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12688         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12689         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12690         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12691         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12692         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12693         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12694         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12695         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
12696         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
12697         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
12698         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     473},
12699         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     474},
12700         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     475},
12701         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     476},
12702         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     477},
12703         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     478},
12704         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     479},
12705         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     480},
12706         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     481},
12707         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     482},
12708         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     483},
12709         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     484},
12710         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     485},
12711         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     486},
12712         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     487},
12713         {"USBC0_DAINT"                 ,           0x16F0010000818ull,  CVMX_CSR_DB_TYPE_NCB,   32,     488},
12714         {"USBC0_DAINTMSK"              ,           0x16F001000081Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     489},
12715         {"USBC0_DCFG"                  ,           0x16F0010000800ull,  CVMX_CSR_DB_TYPE_NCB,   32,     490},
12716         {"USBC0_DCTL"                  ,           0x16F0010000804ull,  CVMX_CSR_DB_TYPE_NCB,   32,     491},
12717         {"USBC0_DIEPCTL000"            ,           0x16F0010000900ull,  CVMX_CSR_DB_TYPE_NCB,   32,     492},
12718         {"USBC0_DIEPCTL001"            ,           0x16F0010000920ull,  CVMX_CSR_DB_TYPE_NCB,   32,     492},
12719         {"USBC0_DIEPCTL002"            ,           0x16F0010000940ull,  CVMX_CSR_DB_TYPE_NCB,   32,     492},
12720         {"USBC0_DIEPCTL003"            ,           0x16F0010000960ull,  CVMX_CSR_DB_TYPE_NCB,   32,     492},
12721         {"USBC0_DIEPCTL004"            ,           0x16F0010000980ull,  CVMX_CSR_DB_TYPE_NCB,   32,     492},
12722         {"USBC0_DIEPINT000"            ,           0x16F0010000908ull,  CVMX_CSR_DB_TYPE_NCB,   32,     493},
12723         {"USBC0_DIEPINT001"            ,           0x16F0010000928ull,  CVMX_CSR_DB_TYPE_NCB,   32,     493},
12724         {"USBC0_DIEPINT002"            ,           0x16F0010000948ull,  CVMX_CSR_DB_TYPE_NCB,   32,     493},
12725         {"USBC0_DIEPINT003"            ,           0x16F0010000968ull,  CVMX_CSR_DB_TYPE_NCB,   32,     493},
12726         {"USBC0_DIEPINT004"            ,           0x16F0010000988ull,  CVMX_CSR_DB_TYPE_NCB,   32,     493},
12727         {"USBC0_DIEPMSK"               ,           0x16F0010000810ull,  CVMX_CSR_DB_TYPE_NCB,   32,     494},
12728         {"USBC0_DIEPTSIZ000"           ,           0x16F0010000910ull,  CVMX_CSR_DB_TYPE_NCB,   32,     495},
12729         {"USBC0_DIEPTSIZ001"           ,           0x16F0010000930ull,  CVMX_CSR_DB_TYPE_NCB,   32,     495},
12730         {"USBC0_DIEPTSIZ002"           ,           0x16F0010000950ull,  CVMX_CSR_DB_TYPE_NCB,   32,     495},
12731         {"USBC0_DIEPTSIZ003"           ,           0x16F0010000970ull,  CVMX_CSR_DB_TYPE_NCB,   32,     495},
12732         {"USBC0_DIEPTSIZ004"           ,           0x16F0010000990ull,  CVMX_CSR_DB_TYPE_NCB,   32,     495},
12733         {"USBC0_DOEPCTL000"            ,           0x16F0010000B00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     496},
12734         {"USBC0_DOEPCTL001"            ,           0x16F0010000B20ull,  CVMX_CSR_DB_TYPE_NCB,   32,     496},
12735         {"USBC0_DOEPCTL002"            ,           0x16F0010000B40ull,  CVMX_CSR_DB_TYPE_NCB,   32,     496},
12736         {"USBC0_DOEPCTL003"            ,           0x16F0010000B60ull,  CVMX_CSR_DB_TYPE_NCB,   32,     496},
12737         {"USBC0_DOEPCTL004"            ,           0x16F0010000B80ull,  CVMX_CSR_DB_TYPE_NCB,   32,     496},
12738         {"USBC0_DOEPINT000"            ,           0x16F0010000B08ull,  CVMX_CSR_DB_TYPE_NCB,   32,     497},
12739         {"USBC0_DOEPINT001"            ,           0x16F0010000B28ull,  CVMX_CSR_DB_TYPE_NCB,   32,     497},
12740         {"USBC0_DOEPINT002"            ,           0x16F0010000B48ull,  CVMX_CSR_DB_TYPE_NCB,   32,     497},
12741         {"USBC0_DOEPINT003"            ,           0x16F0010000B68ull,  CVMX_CSR_DB_TYPE_NCB,   32,     497},
12742         {"USBC0_DOEPINT004"            ,           0x16F0010000B88ull,  CVMX_CSR_DB_TYPE_NCB,   32,     497},
12743         {"USBC0_DOEPMSK"               ,           0x16F0010000814ull,  CVMX_CSR_DB_TYPE_NCB,   32,     498},
12744         {"USBC0_DOEPTSIZ000"           ,           0x16F0010000B10ull,  CVMX_CSR_DB_TYPE_NCB,   32,     499},
12745         {"USBC0_DOEPTSIZ001"           ,           0x16F0010000B30ull,  CVMX_CSR_DB_TYPE_NCB,   32,     499},
12746         {"USBC0_DOEPTSIZ002"           ,           0x16F0010000B50ull,  CVMX_CSR_DB_TYPE_NCB,   32,     499},
12747         {"USBC0_DOEPTSIZ003"           ,           0x16F0010000B70ull,  CVMX_CSR_DB_TYPE_NCB,   32,     499},
12748         {"USBC0_DOEPTSIZ004"           ,           0x16F0010000B90ull,  CVMX_CSR_DB_TYPE_NCB,   32,     499},
12749         {"USBC0_DPTXFSIZ001"           ,           0x16F0010000104ull,  CVMX_CSR_DB_TYPE_NCB,   32,     500},
12750         {"USBC0_DPTXFSIZ002"           ,           0x16F0010000108ull,  CVMX_CSR_DB_TYPE_NCB,   32,     500},
12751         {"USBC0_DPTXFSIZ003"           ,           0x16F001000010Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     500},
12752         {"USBC0_DPTXFSIZ004"           ,           0x16F0010000110ull,  CVMX_CSR_DB_TYPE_NCB,   32,     500},
12753         {"USBC0_DSTS"                  ,           0x16F0010000808ull,  CVMX_CSR_DB_TYPE_NCB,   32,     501},
12754         {"USBC0_DTKNQR1"               ,           0x16F0010000820ull,  CVMX_CSR_DB_TYPE_NCB,   32,     502},
12755         {"USBC0_DTKNQR2"               ,           0x16F0010000824ull,  CVMX_CSR_DB_TYPE_NCB,   32,     503},
12756         {"USBC0_DTKNQR3"               ,           0x16F0010000830ull,  CVMX_CSR_DB_TYPE_NCB,   32,     504},
12757         {"USBC0_DTKNQR4"               ,           0x16F0010000834ull,  CVMX_CSR_DB_TYPE_NCB,   32,     505},
12758         {"USBC0_GAHBCFG"               ,           0x16F0010000008ull,  CVMX_CSR_DB_TYPE_NCB,   32,     506},
12759         {"USBC0_GHWCFG1"               ,           0x16F0010000044ull,  CVMX_CSR_DB_TYPE_NCB,   32,     507},
12760         {"USBC0_GHWCFG2"               ,           0x16F0010000048ull,  CVMX_CSR_DB_TYPE_NCB,   32,     508},
12761         {"USBC0_GHWCFG3"               ,           0x16F001000004Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     509},
12762         {"USBC0_GHWCFG4"               ,           0x16F0010000050ull,  CVMX_CSR_DB_TYPE_NCB,   32,     510},
12763         {"USBC0_GINTMSK"               ,           0x16F0010000018ull,  CVMX_CSR_DB_TYPE_NCB,   32,     511},
12764         {"USBC0_GINTSTS"               ,           0x16F0010000014ull,  CVMX_CSR_DB_TYPE_NCB,   32,     512},
12765         {"USBC0_GNPTXFSIZ"             ,           0x16F0010000028ull,  CVMX_CSR_DB_TYPE_NCB,   32,     513},
12766         {"USBC0_GNPTXSTS"              ,           0x16F001000002Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     514},
12767         {"USBC0_GOTGCTL"               ,           0x16F0010000000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     515},
12768         {"USBC0_GOTGINT"               ,           0x16F0010000004ull,  CVMX_CSR_DB_TYPE_NCB,   32,     516},
12769         {"USBC0_GRSTCTL"               ,           0x16F0010000010ull,  CVMX_CSR_DB_TYPE_NCB,   32,     517},
12770         {"USBC0_GRXFSIZ"               ,           0x16F0010000024ull,  CVMX_CSR_DB_TYPE_NCB,   32,     518},
12771         {"USBC0_GRXSTSPD"              ,           0x16F0010040020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     519},
12772         {"USBC0_GRXSTSPH"              ,           0x16F0010000020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     520},
12773         {"USBC0_GRXSTSRD"              ,           0x16F001004001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     521},
12774         {"USBC0_GRXSTSRH"              ,           0x16F001000001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     522},
12775         {"USBC0_GSNPSID"               ,           0x16F0010000040ull,  CVMX_CSR_DB_TYPE_NCB,   32,     523},
12776         {"USBC0_GUSBCFG"               ,           0x16F001000000Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     524},
12777         {"USBC0_HAINT"                 ,           0x16F0010000414ull,  CVMX_CSR_DB_TYPE_NCB,   32,     525},
12778         {"USBC0_HAINTMSK"              ,           0x16F0010000418ull,  CVMX_CSR_DB_TYPE_NCB,   32,     526},
12779         {"USBC0_HCCHAR000"             ,           0x16F0010000500ull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
12780         {"USBC0_HCCHAR001"             ,           0x16F0010000520ull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
12781         {"USBC0_HCCHAR002"             ,           0x16F0010000540ull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
12782         {"USBC0_HCCHAR003"             ,           0x16F0010000560ull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
12783         {"USBC0_HCCHAR004"             ,           0x16F0010000580ull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
12784         {"USBC0_HCCHAR005"             ,           0x16F00100005A0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
12785         {"USBC0_HCCHAR006"             ,           0x16F00100005C0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
12786         {"USBC0_HCCHAR007"             ,           0x16F00100005E0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
12787         {"USBC0_HCFG"                  ,           0x16F0010000400ull,  CVMX_CSR_DB_TYPE_NCB,   32,     528},
12788         {"USBC0_HCINT000"              ,           0x16F0010000508ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
12789         {"USBC0_HCINT001"              ,           0x16F0010000528ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
12790         {"USBC0_HCINT002"              ,           0x16F0010000548ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
12791         {"USBC0_HCINT003"              ,           0x16F0010000568ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
12792         {"USBC0_HCINT004"              ,           0x16F0010000588ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
12793         {"USBC0_HCINT005"              ,           0x16F00100005A8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
12794         {"USBC0_HCINT006"              ,           0x16F00100005C8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
12795         {"USBC0_HCINT007"              ,           0x16F00100005E8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
12796         {"USBC0_HCINTMSK000"           ,           0x16F001000050Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
12797         {"USBC0_HCINTMSK001"           ,           0x16F001000052Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
12798         {"USBC0_HCINTMSK002"           ,           0x16F001000054Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
12799         {"USBC0_HCINTMSK003"           ,           0x16F001000056Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
12800         {"USBC0_HCINTMSK004"           ,           0x16F001000058Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
12801         {"USBC0_HCINTMSK005"           ,           0x16F00100005ACull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
12802         {"USBC0_HCINTMSK006"           ,           0x16F00100005CCull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
12803         {"USBC0_HCINTMSK007"           ,           0x16F00100005ECull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
12804         {"USBC0_HCSPLT000"             ,           0x16F0010000504ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
12805         {"USBC0_HCSPLT001"             ,           0x16F0010000524ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
12806         {"USBC0_HCSPLT002"             ,           0x16F0010000544ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
12807         {"USBC0_HCSPLT003"             ,           0x16F0010000564ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
12808         {"USBC0_HCSPLT004"             ,           0x16F0010000584ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
12809         {"USBC0_HCSPLT005"             ,           0x16F00100005A4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
12810         {"USBC0_HCSPLT006"             ,           0x16F00100005C4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
12811         {"USBC0_HCSPLT007"             ,           0x16F00100005E4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
12812         {"USBC0_HCTSIZ000"             ,           0x16F0010000510ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
12813         {"USBC0_HCTSIZ001"             ,           0x16F0010000530ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
12814         {"USBC0_HCTSIZ002"             ,           0x16F0010000550ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
12815         {"USBC0_HCTSIZ003"             ,           0x16F0010000570ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
12816         {"USBC0_HCTSIZ004"             ,           0x16F0010000590ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
12817         {"USBC0_HCTSIZ005"             ,           0x16F00100005B0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
12818         {"USBC0_HCTSIZ006"             ,           0x16F00100005D0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
12819         {"USBC0_HCTSIZ007"             ,           0x16F00100005F0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
12820         {"USBC0_HFIR"                  ,           0x16F0010000404ull,  CVMX_CSR_DB_TYPE_NCB,   32,     533},
12821         {"USBC0_HFNUM"                 ,           0x16F0010000408ull,  CVMX_CSR_DB_TYPE_NCB,   32,     534},
12822         {"USBC0_HPRT"                  ,           0x16F0010000440ull,  CVMX_CSR_DB_TYPE_NCB,   32,     535},
12823         {"USBC0_HPTXFSIZ"              ,           0x16F0010000100ull,  CVMX_CSR_DB_TYPE_NCB,   32,     536},
12824         {"USBC0_HPTXSTS"               ,           0x16F0010000410ull,  CVMX_CSR_DB_TYPE_NCB,   32,     537},
12825         {"USBC0_NPTXDFIFO000"          ,           0x16F0010001000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
12826         {"USBC0_NPTXDFIFO001"          ,           0x16F0010002000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
12827         {"USBC0_NPTXDFIFO002"          ,           0x16F0010003000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
12828         {"USBC0_NPTXDFIFO003"          ,           0x16F0010004000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
12829         {"USBC0_NPTXDFIFO004"          ,           0x16F0010005000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
12830         {"USBC0_NPTXDFIFO005"          ,           0x16F0010006000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
12831         {"USBC0_NPTXDFIFO006"          ,           0x16F0010007000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
12832         {"USBC0_NPTXDFIFO007"          ,           0x16F0010008000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
12833         {"USBC0_PCGCCTL"               ,           0x16F0010000E00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     539},
12834         {"USBN0_BIST_STATUS"           ,           0x11800680007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     540},
12835         {"USBN0_CLK_CTL"               ,           0x1180068000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     541},
12836         {"USBN0_CTL_STATUS"            ,           0x16F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     542},
12837         {"USBN0_DMA0_INB_CHN0"         ,           0x16F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     543},
12838         {"USBN0_DMA0_INB_CHN1"         ,           0x16F0000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     544},
12839         {"USBN0_DMA0_INB_CHN2"         ,           0x16F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     545},
12840         {"USBN0_DMA0_INB_CHN3"         ,           0x16F0000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     546},
12841         {"USBN0_DMA0_INB_CHN4"         ,           0x16F0000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     547},
12842         {"USBN0_DMA0_INB_CHN5"         ,           0x16F0000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     548},
12843         {"USBN0_DMA0_INB_CHN6"         ,           0x16F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     549},
12844         {"USBN0_DMA0_INB_CHN7"         ,           0x16F0000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     550},
12845         {"USBN0_DMA0_OUTB_CHN0"        ,           0x16F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     551},
12846         {"USBN0_DMA0_OUTB_CHN1"        ,           0x16F0000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     552},
12847         {"USBN0_DMA0_OUTB_CHN2"        ,           0x16F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     553},
12848         {"USBN0_DMA0_OUTB_CHN3"        ,           0x16F0000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     554},
12849         {"USBN0_DMA0_OUTB_CHN4"        ,           0x16F0000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     555},
12850         {"USBN0_DMA0_OUTB_CHN5"        ,           0x16F0000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     556},
12851         {"USBN0_DMA0_OUTB_CHN6"        ,           0x16F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     557},
12852         {"USBN0_DMA0_OUTB_CHN7"        ,           0x16F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     558},
12853         {"USBN0_DMA_TEST"              ,           0x16F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     559},
12854         {"USBN0_INT_ENB"               ,           0x1180068000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     560},
12855         {"USBN0_INT_SUM"               ,           0x1180068000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     561},
12856         {"USBN0_USBP_CTL_STATUS"       ,           0x1180068000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     562},
12857         {NULL,0,0,0,0}
12858 };
12859 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn30xx[] = {
12860         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
12861         {"SETTING"                     ,        0,      5,      0,      "R/W",  0,      0,      0ull,   0ull},
12862         {"RESERVED_5_63"               ,        5,      59,     0,      "RAZ",  1,      1,      0,      0},
12863         {"SETTING"                     ,        0,      5,      1,      "R/W",  0,      0,      0ull,   0ull},
12864         {"RESERVED_5_63"               ,        5,      59,     1,      "RAZ",  1,      1,      0,      0},
12865         {"OVRFLW"                      ,        0,      3,      2,      "R/W",  0,      0,      0ull,   1ull},
12866         {"RESERVED_3_3"                ,        3,      1,      2,      "RAZ",  1,      1,      0,      0},
12867         {"TXPOP"                       ,        4,      3,      2,      "R/W",  0,      0,      0ull,   1ull},
12868         {"RESERVED_7_7"                ,        7,      1,      2,      "RAZ",  1,      1,      0,      0},
12869         {"TXPSH"                       ,        8,      3,      2,      "R/W",  0,      0,      0ull,   1ull},
12870         {"RESERVED_11_63"              ,        11,     53,     2,      "RAZ",  1,      1,      0,      0},
12871         {"OVRFLW"                      ,        0,      3,      3,      "R/W1C",        0,      0,      0ull,   0ull},
12872         {"RESERVED_3_3"                ,        3,      1,      3,      "RAZ",  1,      1,      0,      0},
12873         {"TXPOP"                       ,        4,      3,      3,      "R/W1C",        0,      0,      0ull,   0ull},
12874         {"RESERVED_7_7"                ,        7,      1,      3,      "RAZ",  1,      1,      0,      0},
12875         {"TXPSH"                       ,        8,      3,      3,      "R/W1C",        0,      0,      0ull,   0ull},
12876         {"RESERVED_11_63"              ,        11,     53,     3,      "RAZ",  1,      1,      0,      0},
12877         {"SETTING"                     ,        0,      5,      4,      "R/W",  0,      0,      0ull,   0ull},
12878         {"RESERVED_5_63"               ,        5,      59,     4,      "RAZ",  1,      1,      0,      0},
12879         {"INT_LOOP"                    ,        0,      3,      5,      "R/W",  0,      0,      0ull,   0ull},
12880         {"RESERVED_3_3"                ,        3,      1,      5,      "RAZ",  1,      1,      0,      0},
12881         {"EXT_LOOP"                    ,        4,      3,      5,      "R/W",  0,      0,      0ull,   0ull},
12882         {"RESERVED_7_63"               ,        7,      57,     5,      "RAZ",  1,      1,      0,      0},
12883         {"SETTING"                     ,        0,      5,      6,      "R/W",  0,      0,      24ull,  24ull},
12884         {"RESERVED_5_63"               ,        5,      59,     6,      "RAZ",  1,      1,      0,      0},
12885         {"PRT_EN"                      ,        0,      3,      7,      "R/W",  0,      0,      0ull,   1ull},
12886         {"RESERVED_3_63"               ,        3,      61,     7,      "RAZ",  1,      1,      0,      0},
12887         {"SETTING"                     ,        0,      5,      8,      "R/W",  0,      0,      24ull,  24ull},
12888         {"RESERVED_5_63"               ,        5,      59,     8,      "RAZ",  1,      1,      0,      0},
12889         {"NCTL"                        ,        0,      4,      9,      "R/W",  0,      0,      8ull,   8ull},
12890         {"PCTL"                        ,        4,      4,      9,      "R/W",  0,      0,      8ull,   8ull},
12891         {"BYPASS"                      ,        8,      1,      9,      "R/W",  0,      0,      0ull,   0ull},
12892         {"RESERVED_9_63"               ,        9,      55,     9,      "RAZ",  1,      1,      0,      0},
12893         {"MARK"                        ,        0,      3,      10,     "R/W",  0,      0,      0ull,   0ull},
12894         {"RESERVED_3_63"               ,        3,      61,     10,     "RAZ",  1,      1,      0,      0},
12895         {"PRT_EN"                      ,        0,      3,      11,     "R/W",  0,      0,      0ull,   1ull},
12896         {"RESERVED_3_63"               ,        3,      61,     11,     "RAZ",  1,      1,      0,      0},
12897         {"BIST"                        ,        0,      4,      12,     "RO",   0,      0,      0ull,   0ull},
12898         {"RESERVED_4_63"               ,        4,      60,     12,     "RAZ",  1,      1,      0,      0},
12899         {"DINT"                        ,        0,      1,      13,     "WO",   0,      0,      0ull,   0ull},
12900         {"RESERVED_1_63"               ,        1,      63,     13,     "RAZ",  1,      1,      0,      0},
12901         {"FUSE"                        ,        0,      1,      14,     "RO",   1,      1,      0,      0},
12902         {"RESERVED_1_63"               ,        1,      63,     14,     "RAZ",  1,      1,      0,      0},
12903         {"GSTOP"                       ,        0,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
12904         {"RESERVED_1_63"               ,        1,      63,     15,     "RAZ",  1,      1,      0,      0},
12905         {"WORKQ"                       ,        0,      16,     16,     "R/W",  0,      0,      0ull,   0ull},
12906         {"GPIO"                        ,        16,     16,     16,     "R/W",  0,      0,      0ull,   0ull},
12907         {"MBOX"                        ,        32,     2,      16,     "R/W",  0,      0,      0ull,   0ull},
12908         {"UART"                        ,        34,     2,      16,     "R/W",  0,      0,      0ull,   0ull},
12909         {"PCI_INT"                     ,        36,     4,      16,     "R/W",  0,      0,      0ull,   0ull},
12910         {"PCI_MSI"                     ,        40,     4,      16,     "R/W",  0,      0,      0ull,   0ull},
12911         {"RESERVED_44_44"              ,        44,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12912         {"TWSI"                        ,        45,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12913         {"RML"                         ,        46,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12914         {"RESERVED_47_47"              ,        47,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12915         {"GMX_DRP"                     ,        48,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12916         {"RESERVED_49_49"              ,        49,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12917         {"IPD_DRP"                     ,        50,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12918         {"RESERVED_51_51"              ,        51,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12919         {"TIMER"                       ,        52,     4,      16,     "R/W",  0,      0,      0ull,   0ull},
12920         {"USB"                         ,        56,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12921         {"PCM"                         ,        57,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12922         {"MPI"                         ,        58,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
12923         {"RESERVED_59_63"              ,        59,     5,      16,     "RAZ",  1,      1,      0,      0},
12924         {"WDOG"                        ,        0,      1,      17,     "R/W",  0,      0,      0ull,   0ull},
12925         {"RESERVED_1_63"               ,        1,      63,     17,     "RAZ",  1,      1,      0,      0},
12926         {"WORKQ"                       ,        0,      16,     18,     "RO",   0,      0,      0ull,   0ull},
12927         {"GPIO"                        ,        16,     16,     18,     "RO",   0,      0,      0ull,   0ull},
12928         {"MBOX"                        ,        32,     2,      18,     "RO",   0,      0,      0ull,   0ull},
12929         {"UART"                        ,        34,     2,      18,     "RO",   0,      0,      0ull,   0ull},
12930         {"PCI_INT"                     ,        36,     4,      18,     "RO",   0,      0,      0ull,   0ull},
12931         {"PCI_MSI"                     ,        40,     4,      18,     "RO",   0,      0,      0ull,   0ull},
12932         {"WDOG_SUM"                    ,        44,     1,      18,     "RO",   0,      0,      0ull,   0ull},
12933         {"TWSI"                        ,        45,     1,      18,     "RO",   0,      0,      0ull,   0ull},
12934         {"RML"                         ,        46,     1,      18,     "RO",   0,      0,      0ull,   0ull},
12935         {"RESERVED_47_47"              ,        47,     1,      18,     "RAZ",  0,      0,      0ull,   0ull},
12936         {"GMX_DRP"                     ,        48,     1,      18,     "R/W1C",        0,      0,      0ull,   0ull},
12937         {"RESERVED_49_49"              ,        49,     1,      18,     "RAZ",  1,      1,      0,      0},
12938         {"IPD_DRP"                     ,        50,     1,      18,     "R/W1C",        0,      0,      0ull,   0ull},
12939         {"RESERVED_51_51"              ,        51,     1,      18,     "RAZ",  1,      1,      0,      0},
12940         {"TIMER"                       ,        52,     4,      18,     "R/W1C",        0,      0,      0ull,   0ull},
12941         {"USB"                         ,        56,     1,      18,     "RO",   0,      0,      0ull,   0ull},
12942         {"PCM"                         ,        57,     1,      18,     "RO",   0,      0,      0ull,   0ull},
12943         {"MPI"                         ,        58,     1,      18,     "R/W1C",        0,      0,      0ull,   0ull},
12944         {"RESERVED_59_63"              ,        59,     5,      18,     "RAZ",  1,      1,      0,      0},
12945         {"WDOG"                        ,        0,      1,      19,     "RO",   0,      0,      0ull,   0ull},
12946         {"RESERVED_1_63"               ,        1,      63,     19,     "RAZ",  1,      1,      0,      0},
12947         {"BITS"                        ,        0,      32,     20,     "R/W1C",        0,      0,      0ull,   0ull},
12948         {"RESERVED_32_63"              ,        32,     32,     20,     "RAZ",  1,      1,      0,      0},
12949         {"BITS"                        ,        0,      32,     21,     "R/W1", 0,      0,      0ull,   0ull},
12950         {"RESERVED_32_63"              ,        32,     32,     21,     "RAZ",  1,      1,      0,      0},
12951         {"NMI"                         ,        0,      1,      22,     "WO",   0,      0,      0ull,   0ull},
12952         {"RESERVED_1_63"               ,        1,      63,     22,     "RAZ",  1,      1,      0,      0},
12953         {"INTR"                        ,        0,      2,      23,     "R/W",  0,      0,      0ull,   0ull},
12954         {"RESERVED_2_63"               ,        2,      62,     23,     "RAZ",  1,      1,      0,      0},
12955         {"PPDBG"                       ,        0,      1,      24,     "RO",   0,      0,      0ull,   0ull},
12956         {"RESERVED_1_63"               ,        1,      63,     24,     "RAZ",  1,      1,      0,      0},
12957         {"POKE"                        ,        0,      64,     25,     "RAZ",  1,      1,      0,      0},
12958         {"RST0"                        ,        0,      1,      26,     "R/W",  1,      1,      0,      0},
12959         {"RESERVED_1_63"               ,        1,      63,     26,     "RAZ",  1,      1,      0,      0},
12960         {"SOFT_BIST"                   ,        0,      1,      27,     "R/W",  0,      0,      0ull,   0ull},
12961         {"RESERVED_1_63"               ,        1,      63,     27,     "RAZ",  1,      1,      0,      0},
12962         {"SOFT_PRST"                   ,        0,      1,      28,     "R/W",  0,      0,      1ull,   0ull},
12963         {"NPI"                         ,        1,      1,      28,     "R/W",  0,      0,      0ull,   0ull},
12964         {"HOST64"                      ,        2,      1,      28,     "RO",   0,      0,      0ull,   0ull},
12965         {"RESERVED_3_63"               ,        3,      61,     28,     "RAZ",  1,      1,      0,      0},
12966         {"SOFT_RST"                    ,        0,      1,      29,     "WO",   0,      0,      0ull,   0ull},
12967         {"RESERVED_1_63"               ,        1,      63,     29,     "RAZ",  1,      1,      0,      0},
12968         {"LEN"                         ,        0,      36,     30,     "R/W",  0,      0,      0ull,   0ull},
12969         {"ONE_SHOT"                    ,        36,     1,      30,     "R/W",  0,      0,      0ull,   0ull},
12970         {"RESERVED_37_63"              ,        37,     27,     30,     "RAZ",  1,      1,      0,      0},
12971         {"MODE"                        ,        0,      2,      31,     "R/W",  0,      0,      0ull,   0ull},
12972         {"STATE"                       ,        2,      2,      31,     "RO",   0,      0,      0ull,   0ull},
12973         {"LEN"                         ,        4,      16,     31,     "R/W",  0,      0,      0ull,   0ull},
12974         {"CNT"                         ,        20,     24,     31,     "RO",   0,      0,      0ull,   0ull},
12975         {"DSTOP"                       ,        44,     1,      31,     "R/W",  0,      0,      0ull,   0ull},
12976         {"GSTOPEN"                     ,        45,     1,      31,     "R/W",  0,      0,      0ull,   0ull},
12977         {"RESERVED_46_63"              ,        46,     18,     31,     "RAZ",  1,      1,      0,      0},
12978         {"DATA"                        ,        0,      17,     32,     "RO",   0,      1,      0ull,   0},
12979         {"DSEL_EXT"                    ,        17,     1,      32,     "R/W",  0,      0,      1ull,   0ull},
12980         {"C_MUL"                       ,        18,     5,      32,     "RO",   1,      1,      0,      0},
12981         {"RESERVED_23_27"              ,        23,     5,      32,     "RAZ",  1,      1,      0,      0},
12982         {"PLL_MUL"                     ,        28,     3,      32,     "RO",   1,      1,      0,      0},
12983         {"RESERVED_31_63"              ,        31,     33,     32,     "RAZ",  1,      1,      0,      0},
12984         {"FDR"                         ,        0,      1,      33,     "RO",   0,      0,      0ull,   0ull},
12985         {"FFR"                         ,        1,      1,      33,     "RO",   0,      0,      0ull,   0ull},
12986         {"FPF1"                        ,        2,      1,      33,     "RO",   0,      0,      0ull,   0ull},
12987         {"FPF0"                        ,        3,      1,      33,     "RO",   0,      0,      0ull,   0ull},
12988         {"FRD"                         ,        4,      1,      33,     "RO",   0,      0,      0ull,   0ull},
12989         {"RESERVED_5_63"               ,        5,      59,     33,     "RAZ",  1,      1,      0,      0},
12990         {"MEM0_ERR"                    ,        0,      7,      34,     "R/W",  0,      0,      0ull,   0ull},
12991         {"MEM1_ERR"                    ,        7,      7,      34,     "R/W",  0,      0,      0ull,   0ull},
12992         {"ENB"                         ,        14,     1,      34,     "R/W",  0,      0,      0ull,   0ull},
12993         {"USE_STT"                     ,        15,     1,      34,     "R/W",  0,      0,      0ull,   0ull},
12994         {"USE_LDT"                     ,        16,     1,      34,     "R/W",  0,      0,      0ull,   0ull},
12995         {"RESET"                       ,        17,     1,      34,     "R/W",  0,      0,      0ull,   0ull},
12996         {"RESERVED_18_63"              ,        18,     46,     34,     "RAZ",  1,      1,      0,      0},
12997         {"FED0_SBE"                    ,        0,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
12998         {"FED0_DBE"                    ,        1,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
12999         {"FED1_SBE"                    ,        2,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
13000         {"FED1_DBE"                    ,        3,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
13001         {"Q0_UND"                      ,        4,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
13002         {"Q0_COFF"                     ,        5,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
13003         {"Q0_PERR"                     ,        6,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
13004         {"Q1_UND"                      ,        7,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
13005         {"Q1_COFF"                     ,        8,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
13006         {"Q1_PERR"                     ,        9,      1,      35,     "R/W",  0,      0,      0ull,   0ull},
13007         {"Q2_UND"                      ,        10,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13008         {"Q2_COFF"                     ,        11,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13009         {"Q2_PERR"                     ,        12,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13010         {"Q3_UND"                      ,        13,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13011         {"Q3_COFF"                     ,        14,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13012         {"Q3_PERR"                     ,        15,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13013         {"Q4_UND"                      ,        16,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13014         {"Q4_COFF"                     ,        17,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13015         {"Q4_PERR"                     ,        18,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13016         {"Q5_UND"                      ,        19,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13017         {"Q5_COFF"                     ,        20,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13018         {"Q5_PERR"                     ,        21,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13019         {"Q6_UND"                      ,        22,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13020         {"Q6_COFF"                     ,        23,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13021         {"Q6_PERR"                     ,        24,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13022         {"Q7_UND"                      ,        25,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13023         {"Q7_COFF"                     ,        26,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13024         {"Q7_PERR"                     ,        27,     1,      35,     "R/W",  0,      0,      0ull,   0ull},
13025         {"RESERVED_28_63"              ,        28,     36,     35,     "RAZ",  1,      1,      0,      0},
13026         {"FED0_SBE"                    ,        0,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13027         {"FED0_DBE"                    ,        1,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13028         {"FED1_SBE"                    ,        2,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13029         {"FED1_DBE"                    ,        3,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13030         {"Q0_UND"                      ,        4,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13031         {"Q0_COFF"                     ,        5,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13032         {"Q0_PERR"                     ,        6,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13033         {"Q1_UND"                      ,        7,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13034         {"Q1_COFF"                     ,        8,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13035         {"Q1_PERR"                     ,        9,      1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13036         {"Q2_UND"                      ,        10,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13037         {"Q2_COFF"                     ,        11,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13038         {"Q2_PERR"                     ,        12,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13039         {"Q3_UND"                      ,        13,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13040         {"Q3_COFF"                     ,        14,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13041         {"Q3_PERR"                     ,        15,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13042         {"Q4_UND"                      ,        16,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13043         {"Q4_COFF"                     ,        17,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13044         {"Q4_PERR"                     ,        18,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13045         {"Q5_UND"                      ,        19,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13046         {"Q5_COFF"                     ,        20,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13047         {"Q5_PERR"                     ,        21,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13048         {"Q6_UND"                      ,        22,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13049         {"Q6_COFF"                     ,        23,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13050         {"Q6_PERR"                     ,        24,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13051         {"Q7_UND"                      ,        25,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13052         {"Q7_COFF"                     ,        26,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13053         {"Q7_PERR"                     ,        27,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
13054         {"RESERVED_28_63"              ,        28,     36,     36,     "RAZ",  1,      1,      0,      0},
13055         {"QUE_SIZ"                     ,        0,      29,     37,     "RO",   0,      0,      0ull,   0ull},
13056         {"RESERVED_29_63"              ,        29,     35,     37,     "RAZ",  1,      1,      0,      0},
13057         {"PG_NUM"                      ,        0,      25,     38,     "RO",   0,      1,      0ull,   0},
13058         {"RESERVED_25_63"              ,        25,     39,     38,     "RAZ",  1,      1,      0,      0},
13059         {"ACT_INDX"                    ,        0,      26,     39,     "RO",   0,      1,      0ull,   0},
13060         {"ACT_QUE"                     ,        26,     3,      39,     "RO",   0,      1,      0ull,   0},
13061         {"RESERVED_29_63"              ,        29,     35,     39,     "RAZ",  0,      0,      0ull,   7ull},
13062         {"EXP_INDX"                    ,        0,      26,     40,     "RO",   0,      1,      0ull,   0},
13063         {"EXP_QUE"                     ,        26,     3,      40,     "RO",   0,      1,      0ull,   0},
13064         {"RESERVED_29_63"              ,        29,     35,     40,     "RAZ",  0,      0,      0ull,   7ull},
13065         {"CTL"                         ,        0,      16,     41,     "R/W",  1,      0,      0,      0ull},
13066         {"RESERVED_16_63"              ,        16,     48,     41,     "RAZ",  1,      1,      0,      0},
13067         {"STATUS"                      ,        0,      32,     42,     "RO",   0,      0,      0ull,   0ull},
13068         {"RESERVED_32_63"              ,        32,     32,     42,     "RAZ",  1,      1,      0,      0},
13069         {"RESERVED_0_1"                ,        0,      2,      43,     "RAZ",  0,      0,      0ull,   0ull},
13070         {"OUT_OVR"                     ,        2,      3,      43,     "R/W1C",        0,      0,      0ull,   0ull},
13071         {"RESERVED_5_21"               ,        5,      17,     43,     "RAZ",  0,      0,      0ull,   0ull},
13072         {"LOSTSTAT"                    ,        22,     3,      43,     "R/W1C",        0,      0,      0ull,   0ull},
13073         {"RESERVED_25_25"              ,        25,     1,      43,     "RAZ",  0,      0,      0ull,   0ull},
13074         {"STATOVR"                     ,        26,     1,      43,     "R/W1C",        0,      0,      0ull,   0ull},
13075         {"INB_NXA"                     ,        27,     4,      43,     "R/W1C",        0,      0,      0ull,   0ull},
13076         {"RESERVED_31_63"              ,        31,     33,     43,     "RAZ",  1,      1,      0,      0},
13077         {"STATUS"                      ,        0,      10,     44,     "RO",   0,      0,      0ull,   0ull},
13078         {"RESERVED_10_63"              ,        10,     54,     44,     "RAZ",  1,      1,      0,      0},
13079         {"TYPE"                        ,        0,      1,      45,     "R/W",  0,      1,      0ull,   0},
13080         {"EN"                          ,        1,      1,      45,     "R/W",  0,      0,      0ull,   1ull},
13081         {"P0MII"                       ,        2,      1,      45,     "R/W",  0,      1,      0ull,   0},
13082         {"RESERVED_3_63"               ,        3,      61,     45,     "RAZ",  1,      1,      0,      0},
13083         {"PRT"                         ,        0,      6,      46,     "RO",   0,      1,      0ull,   0},
13084         {"RESERVED_6_63"               ,        6,      58,     46,     "RAZ",  1,      1,      0,      0},
13085         {"EN"                          ,        0,      1,      47,     "R/W",  0,      1,      0ull,   0},
13086         {"SPEED"                       ,        1,      1,      47,     "R/W",  0,      1,      1ull,   0},
13087         {"DUPLEX"                      ,        2,      1,      47,     "R/W",  0,      1,      1ull,   0},
13088         {"SLOTTIME"                    ,        3,      1,      47,     "R/W",  0,      1,      1ull,   0},
13089         {"RESERVED_4_63"               ,        4,      60,     47,     "RAZ",  1,      1,      0,      0},
13090         {"ADR"                         ,        0,      64,     48,     "R/W",  0,      1,      0ull,   0},
13091         {"ADR"                         ,        0,      64,     49,     "R/W",  0,      1,      0ull,   0},
13092         {"ADR"                         ,        0,      64,     50,     "R/W",  0,      1,      0ull,   0},
13093         {"ADR"                         ,        0,      64,     51,     "R/W",  0,      1,      0ull,   0},
13094         {"ADR"                         ,        0,      64,     52,     "R/W",  0,      1,      0ull,   0},
13095         {"ADR"                         ,        0,      64,     53,     "R/W",  0,      1,      0ull,   0},
13096         {"EN"                          ,        0,      8,      54,     "R/W",  0,      1,      0ull,   0},
13097         {"RESERVED_8_63"               ,        8,      56,     54,     "RAZ",  1,      1,      0,      0},
13098         {"BCST"                        ,        0,      1,      55,     "R/W",  0,      1,      1ull,   0},
13099         {"MCST"                        ,        1,      2,      55,     "R/W",  0,      1,      0ull,   0},
13100         {"CAM_MODE"                    ,        3,      1,      55,     "R/W",  0,      1,      0ull,   0},
13101         {"RESERVED_4_63"               ,        4,      60,     55,     "RAZ",  1,      1,      0,      0},
13102         {"CNT"                         ,        0,      5,      56,     "R/W",  0,      0,      24ull,  24ull},
13103         {"RESERVED_5_63"               ,        5,      59,     56,     "RAZ",  1,      1,      0,      0},
13104         {"MINERR"                      ,        0,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13105         {"CAREXT"                      ,        1,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13106         {"MAXERR"                      ,        2,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13107         {"JABBER"                      ,        3,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13108         {"FCSERR"                      ,        4,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13109         {"ALNERR"                      ,        5,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13110         {"LENERR"                      ,        6,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13111         {"RCVERR"                      ,        7,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13112         {"SKPERR"                      ,        8,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13113         {"NIBERR"                      ,        9,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
13114         {"RESERVED_10_63"              ,        10,     54,     57,     "RAZ",  1,      1,      0,      0},
13115         {"PRE_CHK"                     ,        0,      1,      58,     "R/W",  0,      0,      1ull,   1ull},
13116         {"PRE_STRP"                    ,        1,      1,      58,     "R/W",  0,      0,      1ull,   1ull},
13117         {"CTL_DRP"                     ,        2,      1,      58,     "R/W",  0,      0,      1ull,   1ull},
13118         {"CTL_BCK"                     ,        3,      1,      58,     "R/W",  0,      0,      1ull,   1ull},
13119         {"CTL_MCST"                    ,        4,      1,      58,     "R/W",  0,      0,      1ull,   1ull},
13120         {"CTL_SMAC"                    ,        5,      1,      58,     "R/W",  0,      0,      1ull,   1ull},
13121         {"PRE_FREE"                    ,        6,      1,      58,     "R/W",  0,      0,      0ull,   0ull},
13122         {"VLAN_LEN"                    ,        7,      1,      58,     "R/W",  0,      0,      0ull,   0ull},
13123         {"PAD_LEN"                     ,        8,      1,      58,     "R/W",  0,      0,      0ull,   0ull},
13124         {"RESERVED_9_63"               ,        9,      55,     58,     "RAZ",  1,      1,      0,      0},
13125         {"LEN"                         ,        0,      16,     59,     "R/W",  0,      0,      1536ull,        1536ull},
13126         {"RESERVED_16_63"              ,        16,     48,     59,     "RAZ",  1,      1,      0,      0},
13127         {"LEN"                         ,        0,      16,     60,     "R/W",  0,      0,      64ull,  64ull},
13128         {"RESERVED_16_63"              ,        16,     48,     60,     "RAZ",  1,      1,      0,      0},
13129         {"IFG"                         ,        0,      4,      61,     "R/W",  0,      0,      12ull,  12ull},
13130         {"RESERVED_4_63"               ,        4,      60,     61,     "RAZ",  1,      1,      0,      0},
13131         {"MINERR"                      ,        0,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13132         {"CAREXT"                      ,        1,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13133         {"MAXERR"                      ,        2,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13134         {"JABBER"                      ,        3,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13135         {"FCSERR"                      ,        4,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13136         {"ALNERR"                      ,        5,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13137         {"LENERR"                      ,        6,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13138         {"RCVERR"                      ,        7,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13139         {"SKPERR"                      ,        8,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13140         {"NIBERR"                      ,        9,      1,      62,     "R/W",  0,      0,      0ull,   0ull},
13141         {"OVRERR"                      ,        10,     1,      62,     "R/W",  0,      0,      0ull,   0ull},
13142         {"PCTERR"                      ,        11,     1,      62,     "R/W",  0,      0,      0ull,   0ull},
13143         {"RSVERR"                      ,        12,     1,      62,     "R/W",  0,      0,      0ull,   0ull},
13144         {"FALERR"                      ,        13,     1,      62,     "R/W",  0,      0,      0ull,   0ull},
13145         {"COLDET"                      ,        14,     1,      62,     "R/W",  0,      0,      0ull,   0ull},
13146         {"IFGERR"                      ,        15,     1,      62,     "R/W",  0,      0,      0ull,   0ull},
13147         {"PHY_LINK"                    ,        16,     1,      62,     "R/W",  0,      0,      0ull,   0ull},
13148         {"PHY_SPD"                     ,        17,     1,      62,     "R/W",  0,      0,      0ull,   0ull},
13149         {"PHY_DUPX"                    ,        18,     1,      62,     "R/W",  0,      0,      0ull,   0ull},
13150         {"RESERVED_19_63"              ,        19,     45,     62,     "RAZ",  1,      1,      0,      0},
13151         {"MINERR"                      ,        0,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13152         {"CAREXT"                      ,        1,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13153         {"MAXERR"                      ,        2,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13154         {"JABBER"                      ,        3,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13155         {"FCSERR"                      ,        4,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13156         {"ALNERR"                      ,        5,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13157         {"LENERR"                      ,        6,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13158         {"RCVERR"                      ,        7,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13159         {"SKPERR"                      ,        8,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13160         {"NIBERR"                      ,        9,      1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13161         {"OVRERR"                      ,        10,     1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13162         {"PCTERR"                      ,        11,     1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13163         {"RSVERR"                      ,        12,     1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13164         {"FALERR"                      ,        13,     1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13165         {"COLDET"                      ,        14,     1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13166         {"IFGERR"                      ,        15,     1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13167         {"PHY_LINK"                    ,        16,     1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13168         {"PHY_SPD"                     ,        17,     1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13169         {"PHY_DUPX"                    ,        18,     1,      63,     "R/W1C",        0,      0,      0ull,   0ull},
13170         {"RESERVED_19_63"              ,        19,     45,     63,     "RAZ",  1,      1,      0,      0},
13171         {"CNT"                         ,        0,      16,     64,     "R/W",  0,      0,      10240ull,       10240ull},
13172         {"RESERVED_16_63"              ,        16,     48,     64,     "RAZ",  1,      1,      0,      0},
13173         {"STATUS"                      ,        0,      1,      65,     "RO",   0,      1,      0ull,   0},
13174         {"SPEED"                       ,        1,      2,      65,     "RO",   0,      1,      0ull,   0},
13175         {"DUPLEX"                      ,        3,      1,      65,     "RO",   0,      1,      0ull,   0},
13176         {"RESERVED_4_63"               ,        4,      60,     65,     "RAZ",  1,      1,      0,      0},
13177         {"RD_CLR"                      ,        0,      1,      66,     "R/W",  0,      0,      0ull,   0ull},
13178         {"RESERVED_1_63"               ,        1,      63,     66,     "RAZ",  1,      1,      0,      0},
13179         {"CNT"                         ,        0,      48,     67,     "RC/W", 0,      1,      0ull,   0},
13180         {"RESERVED_48_63"              ,        48,     16,     67,     "RAZ",  1,      1,      0,      0},
13181         {"CNT"                         ,        0,      48,     68,     "RC/W", 0,      1,      0ull,   0},
13182         {"RESERVED_48_63"              ,        48,     16,     68,     "RAZ",  1,      1,      0,      0},
13183         {"CNT"                         ,        0,      48,     69,     "RC/W", 0,      1,      0ull,   0},
13184         {"RESERVED_48_63"              ,        48,     16,     69,     "RAZ",  1,      1,      0,      0},
13185         {"CNT"                         ,        0,      48,     70,     "RC/W", 0,      1,      0ull,   0},
13186         {"RESERVED_48_63"              ,        48,     16,     70,     "RAZ",  1,      1,      0,      0},
13187         {"CNT"                         ,        0,      32,     71,     "RC/W", 0,      1,      0ull,   0},
13188         {"RESERVED_32_63"              ,        32,     32,     71,     "RAZ",  1,      1,      0,      0},
13189         {"CNT"                         ,        0,      32,     72,     "RC/W", 0,      1,      0ull,   0},
13190         {"RESERVED_32_63"              ,        32,     32,     72,     "RAZ",  1,      1,      0,      0},
13191         {"CNT"                         ,        0,      32,     73,     "RC/W", 0,      1,      0ull,   0},
13192         {"RESERVED_32_63"              ,        32,     32,     73,     "RAZ",  1,      1,      0,      0},
13193         {"CNT"                         ,        0,      32,     74,     "RC/W", 0,      1,      0ull,   0},
13194         {"RESERVED_32_63"              ,        32,     32,     74,     "RAZ",  1,      1,      0,      0},
13195         {"CNT"                         ,        0,      32,     75,     "RC/W", 0,      1,      0ull,   0},
13196         {"RESERVED_32_63"              ,        32,     32,     75,     "RAZ",  1,      1,      0,      0},
13197         {"LEN"                         ,        0,      7,      76,     "R/W",  0,      0,      0ull,   0ull},
13198         {"RESERVED_7_7"                ,        7,      1,      76,     "RAZ",  1,      1,      0,      0},
13199         {"FCSSEL"                      ,        8,      1,      76,     "R/W",  0,      0,      0ull,   0ull},
13200         {"RESERVED_9_63"               ,        9,      55,     76,     "RAZ",  1,      1,      0,      0},
13201         {"MARK"                        ,        0,      6,      77,     "R/W",  1,      1,      0,      0},
13202         {"RESERVED_6_63"               ,        6,      58,     77,     "RAZ",  1,      1,      0,      0},
13203         {"MARK"                        ,        0,      6,      78,     "R/W",  0,      0,      16ull,  16ull},
13204         {"RESERVED_6_63"               ,        6,      58,     78,     "RAZ",  1,      1,      0,      0},
13205         {"MARK"                        ,        0,      9,      79,     "R/W",  1,      1,      0,      0},
13206         {"RESERVED_9_63"               ,        9,      55,     79,     "RAZ",  1,      1,      0,      0},
13207         {"COMMIT"                      ,        0,      3,      80,     "RO",   0,      0,      0ull,   0ull},
13208         {"RESERVED_3_15"               ,        3,      13,     80,     "RAZ",  1,      1,      0,      0},
13209         {"DROP"                        ,        16,     3,      80,     "RO",   0,      0,      0ull,   0ull},
13210         {"RESERVED_19_63"              ,        19,     45,     80,     "RAZ",  1,      1,      0,      0},
13211         {"PRTS"                        ,        0,      3,      81,     "R/W",  0,      0,      3ull,   3ull},
13212         {"RESERVED_3_63"               ,        3,      61,     81,     "RAZ",  1,      1,      0,      0},
13213         {"RX"                          ,        0,      3,      82,     "RC",   0,      0,      0ull,   0ull},
13214         {"RESERVED_3_3"                ,        3,      1,      82,     "RAZ",  1,      1,      0,      0},
13215         {"TX"                          ,        4,      3,      82,     "RC",   0,      0,      0ull,   0ull},
13216         {"RESERVED_7_63"               ,        7,      57,     82,     "RAZ",  1,      1,      0,      0},
13217         {"SMAC"                        ,        0,      48,     83,     "R/W",  0,      1,      0ull,   0},
13218         {"RESERVED_48_63"              ,        48,     16,     83,     "RAZ",  1,      1,      0,      0},
13219         {"CNT"                         ,        0,      16,     84,     "R/W1C",        0,      0,      0ull,   0ull},
13220         {"BP"                          ,        16,     1,      84,     "RO",   0,      0,      0ull,   0ull},
13221         {"RESERVED_17_63"              ,        17,     47,     84,     "RAZ",  1,      1,      0,      0},
13222         {"PREAMBLE"                    ,        0,      1,      85,     "R/W",  0,      0,      1ull,   1ull},
13223         {"PAD"                         ,        1,      1,      85,     "R/W",  0,      0,      1ull,   1ull},
13224         {"FCS"                         ,        2,      1,      85,     "R/W",  0,      0,      1ull,   1ull},
13225         {"FORCE_FCS"                   ,        3,      1,      85,     "R/W",  0,      0,      1ull,   1ull},
13226         {"RESERVED_4_63"               ,        4,      60,     85,     "RAZ",  1,      1,      0,      0},
13227         {"BURST"                       ,        0,      16,     86,     "R/W",  0,      0,      8192ull,        8192ull},
13228         {"RESERVED_16_63"              ,        16,     48,     86,     "RAZ",  1,      1,      0,      0},
13229         {"CLK_CNT"                     ,        0,      6,      87,     "R/W",  0,      0,      1ull,   1ull},
13230         {"RESERVED_6_63"               ,        6,      58,     87,     "RAZ",  1,      1,      0,      0},
13231         {"XSCOL_EN"                    ,        0,      1,      88,     "R/W",  0,      0,      1ull,   1ull},
13232         {"XSDEF_EN"                    ,        1,      1,      88,     "R/W",  0,      0,      1ull,   1ull},
13233         {"RESERVED_2_63"               ,        2,      62,     88,     "RAZ",  1,      1,      0,      0},
13234         {"MIN_SIZE"                    ,        0,      8,      89,     "R/W",  0,      0,      59ull,  59ull},
13235         {"RESERVED_8_63"               ,        8,      56,     89,     "RAZ",  1,      1,      0,      0},
13236         {"INTERVAL"                    ,        0,      16,     90,     "R/W",  0,      1,      16ull,  0},
13237         {"RESERVED_16_63"              ,        16,     48,     90,     "RAZ",  1,      1,      0,      0},
13238         {"TIME"                        ,        0,      16,     91,     "R/W",  0,      1,      96ull,  0},
13239         {"RESERVED_16_63"              ,        16,     48,     91,     "RAZ",  1,      1,      0,      0},
13240         {"TIME"                        ,        0,      16,     92,     "RO",   1,      1,      0,      0},
13241         {"RESERVED_16_63"              ,        16,     48,     92,     "RAZ",  1,      1,      0,      0},
13242         {"SEND"                        ,        0,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
13243         {"RESERVED_1_63"               ,        1,      63,     93,     "RAZ",  1,      1,      0,      0},
13244         {"SLOT"                        ,        0,      10,     94,     "R/W",  0,      0,      512ull, 512ull},
13245         {"RESERVED_10_63"              ,        10,     54,     94,     "RAZ",  1,      1,      0,      0},
13246         {"TIME"                        ,        0,      16,     95,     "R/W",  0,      1,      0ull,   0},
13247         {"RESERVED_16_63"              ,        16,     48,     95,     "RAZ",  1,      1,      0,      0},
13248         {"XSCOL"                       ,        0,      32,     96,     "RC/W", 0,      1,      0ull,   0},
13249         {"XSDEF"                       ,        32,     32,     96,     "RC/W", 0,      1,      0ull,   0},
13250         {"MCOL"                        ,        0,      32,     97,     "RC/W", 0,      1,      0ull,   0},
13251         {"SCOL"                        ,        32,     32,     97,     "RC/W", 0,      1,      0ull,   0},
13252         {"OCTS"                        ,        0,      48,     98,     "RC/W", 0,      1,      0ull,   0},
13253         {"RESERVED_48_63"              ,        48,     16,     98,     "RAZ",  1,      1,      0,      0},
13254         {"PKTS"                        ,        0,      32,     99,     "RC/W", 0,      1,      0ull,   0},
13255         {"RESERVED_32_63"              ,        32,     32,     99,     "RAZ",  1,      1,      0,      0},
13256         {"HIST0"                       ,        0,      32,     100,    "RC/W", 0,      1,      0ull,   0},
13257         {"HIST1"                       ,        32,     32,     100,    "RC/W", 0,      1,      0ull,   0},
13258         {"HIST2"                       ,        0,      32,     101,    "RC/W", 0,      1,      0ull,   0},
13259         {"HIST3"                       ,        32,     32,     101,    "RC/W", 0,      1,      0ull,   0},
13260         {"HIST4"                       ,        0,      32,     102,    "RC/W", 0,      1,      0ull,   0},
13261         {"HIST5"                       ,        32,     32,     102,    "RC/W", 0,      1,      0ull,   0},
13262         {"HIST6"                       ,        0,      32,     103,    "RC/W", 0,      1,      0ull,   0},
13263         {"HIST7"                       ,        32,     32,     103,    "RC/W", 0,      1,      0ull,   0},
13264         {"BCST"                        ,        0,      32,     104,    "RC/W", 0,      1,      0ull,   0},
13265         {"MCST"                        ,        32,     32,     104,    "RC/W", 0,      1,      0ull,   0},
13266         {"CTL"                         ,        0,      32,     105,    "RC/W", 0,      1,      0ull,   0},
13267         {"UNDFLW"                      ,        32,     32,     105,    "RC/W", 0,      1,      0ull,   0},
13268         {"RD_CLR"                      ,        0,      1,      106,    "R/W",  0,      0,      0ull,   0ull},
13269         {"RESERVED_1_63"               ,        1,      63,     106,    "RAZ",  1,      1,      0,      0},
13270         {"CNT"                         ,        0,      7,      107,    "R/W",  0,      0,      32ull,  32ull},
13271         {"RESERVED_7_63"               ,        7,      57,     107,    "RAZ",  1,      1,      0,      0},
13272         {"BP"                          ,        0,      3,      108,    "RO",   0,      0,      0ull,   0ull},
13273         {"RESERVED_3_63"               ,        3,      61,     108,    "RAZ",  1,      1,      0,      0},
13274         {"MSK"                         ,        0,      1,      109,    "R/W",  0,      1,      0ull,   0},
13275         {"RESERVED_1_63"               ,        1,      63,     109,    "RAZ",  1,      1,      0,      0},
13276         {"LIMIT"                       ,        0,      5,      110,    "R/W",  0,      0,      16ull,  16ull},
13277         {"RESERVED_5_63"               ,        5,      59,     110,    "RAZ",  1,      1,      0,      0},
13278         {"CORRUPT"                     ,        0,      3,      111,    "R/W",  0,      0,      15ull,  15ull},
13279         {"RESERVED_3_63"               ,        3,      61,     111,    "RAZ",  1,      1,      0,      0},
13280         {"IFG1"                        ,        0,      4,      112,    "R/W",  0,      1,      8ull,   0},
13281         {"IFG2"                        ,        4,      4,      112,    "R/W",  0,      1,      4ull,   0},
13282         {"RESERVED_8_63"               ,        8,      56,     112,    "RAZ",  1,      1,      0,      0},
13283         {"PKO_NXA"                     ,        0,      1,      113,    "R/W",  0,      0,      0ull,   0ull},
13284         {"RESERVED_1_1"                ,        1,      1,      113,    "RAZ",  0,      0,      0ull,   0ull},
13285         {"UNDFLW"                      ,        2,      3,      113,    "R/W",  0,      0,      0ull,   0ull},
13286         {"RESERVED_5_7"                ,        5,      3,      113,    "RAZ",  0,      0,      0ull,   0ull},
13287         {"XSCOL"                       ,        8,      3,      113,    "R/W",  0,      0,      0ull,   0ull},
13288         {"RESERVED_11_11"              ,        11,     1,      113,    "RAZ",  0,      0,      0ull,   0ull},
13289         {"XSDEF"                       ,        12,     3,      113,    "R/W",  0,      0,      0ull,   0ull},
13290         {"RESERVED_15_15"              ,        15,     1,      113,    "RAZ",  0,      0,      0ull,   0ull},
13291         {"LATE_COL"                    ,        16,     3,      113,    "R/W",  0,      0,      0ull,   0ull},
13292         {"RESERVED_19_63"              ,        19,     45,     113,    "RAZ",  0,      0,      0ull,   0ull},
13293         {"PKO_NXA"                     ,        0,      1,      114,    "R/W1C",        0,      0,      0ull,   0ull},
13294         {"RESERVED_1_1"                ,        1,      1,      114,    "RAZ",  0,      0,      0ull,   0ull},
13295         {"UNDFLW"                      ,        2,      3,      114,    "R/W1C",        0,      0,      0ull,   0ull},
13296         {"RESERVED_5_7"                ,        5,      3,      114,    "RAZ",  0,      0,      0ull,   0ull},
13297         {"XSCOL"                       ,        8,      3,      114,    "R/W1C",        0,      0,      0ull,   0ull},
13298         {"RESERVED_11_11"              ,        11,     1,      114,    "RAZ",  0,      0,      0ull,   0ull},
13299         {"XSDEF"                       ,        12,     3,      114,    "R/W1C",        0,      0,      0ull,   0ull},
13300         {"RESERVED_15_15"              ,        15,     1,      114,    "RAZ",  0,      0,      0ull,   0ull},
13301         {"LATE_COL"                    ,        16,     3,      114,    "R/W1C",        0,      0,      0ull,   0ull},
13302         {"RESERVED_19_63"              ,        19,     45,     114,    "RAZ",  0,      0,      0ull,   0ull},
13303         {"JAM"                         ,        0,      8,      115,    "R/W",  0,      1,      238ull, 0},
13304         {"RESERVED_8_63"               ,        8,      56,     115,    "RAZ",  1,      1,      0,      0},
13305         {"LFSR"                        ,        0,      16,     116,    "R/W",  0,      1,      65535ull,       0},
13306         {"RESERVED_16_63"              ,        16,     48,     116,    "RAZ",  1,      1,      0,      0},
13307         {"IGN_FULL"                    ,        0,      3,      117,    "R/W",  0,      0,      0ull,   0ull},
13308         {"RESERVED_3_3"                ,        3,      1,      117,    "RAZ",  0,      0,      0ull,   0ull},
13309         {"BP"                          ,        4,      3,      117,    "R/W",  0,      0,      0ull,   0ull},
13310         {"RESERVED_7_7"                ,        7,      1,      117,    "RAZ",  0,      0,      0ull,   0ull},
13311         {"EN"                          ,        8,      3,      117,    "R/W",  0,      0,      0ull,   0ull},
13312         {"RESERVED_11_63"              ,        11,     53,     117,    "RAZ",  0,      0,      0ull,   0ull},
13313         {"DMAC"                        ,        0,      48,     118,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
13314         {"RESERVED_48_63"              ,        48,     16,     118,    "RAZ",  1,      1,      0,      0},
13315         {"TYPE"                        ,        0,      16,     119,    "R/W",  0,      0,      34824ull,       34824ull},
13316         {"RESERVED_16_63"              ,        16,     48,     119,    "RAZ",  1,      1,      0,      0},
13317         {"PRTS"                        ,        0,      5,      120,    "R/W",  0,      1,      3ull,   0},
13318         {"RESERVED_5_63"               ,        5,      59,     120,    "RAZ",  1,      1,      0,      0},
13319         {"TX_OE"                       ,        0,      1,      121,    "R/W",  0,      0,      0ull,   0ull},
13320         {"RX_XOR"                      ,        1,      1,      121,    "R/W",  0,      0,      0ull,   0ull},
13321         {"INT_EN"                      ,        2,      1,      121,    "R/W",  0,      0,      0ull,   0ull},
13322         {"INT_TYPE"                    ,        3,      1,      121,    "R/W",  0,      0,      0ull,   0ull},
13323         {"FIL_CNT"                     ,        4,      4,      121,    "R/W",  0,      0,      0ull,   0ull},
13324         {"FIL_SEL"                     ,        8,      4,      121,    "R/W",  0,      0,      0ull,   0ull},
13325         {"RESERVED_12_63"              ,        12,     52,     121,    "RAZ",  1,      1,      0,      0},
13326         {"RESERVED_0_7"                ,        0,      8,      122,    "RAZ",  1,      1,      0,      0},
13327         {"BOOT_ENA"                    ,        8,      4,      122,    "R/W",  0,      1,      0ull,   0},
13328         {"RESERVED_12_63"              ,        12,     52,     122,    "RAZ",  1,      1,      0,      0},
13329         {"DBG_ENA"                     ,        0,      21,     123,    "R/W",  0,      0,      0ull,   0ull},
13330         {"RESERVED_21_63"              ,        21,     43,     123,    "RAZ",  1,      1,      0,      0},
13331         {"TYPE"                        ,        0,      16,     124,    "WO",   0,      0,      0ull,   0ull},
13332         {"RESERVED_16_63"              ,        16,     48,     124,    "RAZ",  1,      1,      0,      0},
13333         {"DAT"                         ,        0,      24,     125,    "RO",   0,      0,      0ull,   0ull},
13334         {"RESERVED_24_63"              ,        24,     40,     125,    "RAZ",  1,      1,      0,      0},
13335         {"CLR"                         ,        0,      24,     126,    "WO",   0,      0,      0ull,   0ull},
13336         {"RESERVED_24_63"              ,        24,     40,     126,    "RAZ",  1,      1,      0,      0},
13337         {"SET"                         ,        0,      24,     127,    "WO",   0,      0,      0ull,   0ull},
13338         {"RESERVED_24_63"              ,        24,     40,     127,    "RAZ",  1,      1,      0,      0},
13339         {"TX_OE"                       ,        0,      1,      128,    "R/W",  0,      0,      0ull,   0ull},
13340         {"RX_XOR"                      ,        1,      1,      128,    "R/W",  0,      0,      0ull,   0ull},
13341         {"RESERVED_2_3"                ,        2,      2,      128,    "RAZ",  1,      1,      0,      0},
13342         {"FIL_CNT"                     ,        4,      4,      128,    "R/W",  0,      0,      0ull,   0ull},
13343         {"FIL_SEL"                     ,        8,      4,      128,    "R/W",  0,      0,      0ull,   0ull},
13344         {"RESERVED_12_63"              ,        12,     52,     128,    "RAZ",  1,      1,      0,      0},
13345         {"ICD"                         ,        0,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13346         {"IBD"                         ,        1,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13347         {"ICRP1"                       ,        2,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13348         {"ICRP0"                       ,        3,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13349         {"ICRN1"                       ,        4,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13350         {"ICRN0"                       ,        5,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13351         {"IBRQ1"                       ,        6,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13352         {"IBRQ0"                       ,        7,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13353         {"ICNRT"                       ,        8,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13354         {"IBR1"                        ,        9,      1,      129,    "RO",   0,      0,      0ull,   0ull},
13355         {"IBR0"                        ,        10,     1,      129,    "RO",   0,      0,      0ull,   0ull},
13356         {"IBDR1"                       ,        11,     1,      129,    "RO",   0,      0,      0ull,   0ull},
13357         {"IBDR0"                       ,        12,     1,      129,    "RO",   0,      0,      0ull,   0ull},
13358         {"ICNR0"                       ,        13,     1,      129,    "RO",   0,      0,      0ull,   0ull},
13359         {"ICNR1"                       ,        14,     1,      129,    "RO",   0,      0,      0ull,   0ull},
13360         {"ICR1"                        ,        15,     1,      129,    "RO",   0,      0,      0ull,   0ull},
13361         {"ICR0"                        ,        16,     1,      129,    "RO",   0,      0,      0ull,   0ull},
13362         {"ICNRCB"                      ,        17,     1,      129,    "RO",   0,      0,      0ull,   0ull},
13363         {"RESERVED_18_63"              ,        18,     46,     129,    "RAZ",  1,      1,      0,      0},
13364         {"FAU_END"                     ,        0,      1,      130,    "R/W",  0,      0,      0ull,   0ull},
13365         {"DWB_ENB"                     ,        1,      1,      130,    "R/W",  0,      0,      1ull,   1ull},
13366         {"PKO_ENB"                     ,        2,      1,      130,    "R/W",  0,      0,      0ull,   0ull},
13367         {"INB_MAT"                     ,        3,      1,      130,    "R/W1C",        0,      0,      0ull,   0ull},
13368         {"OUTB_MAT"                    ,        4,      1,      130,    "R/W1C",        0,      0,      0ull,   0ull},
13369         {"RESERVED_5_63"               ,        5,      59,     130,    "RAZ",  1,      1,      0,      0},
13370         {"TOUT_VAL"                    ,        0,      12,     131,    "R/W",  0,      0,      4ull,   4ull},
13371         {"TOUT_ENB"                    ,        12,     1,      131,    "R/W",  0,      0,      1ull,   0ull},
13372         {"RESERVED_13_63"              ,        13,     51,     131,    "RAZ",  1,      1,      0,      0},
13373         {"SRC"                         ,        0,      8,      132,    "R/W",  0,      1,      0ull,   0},
13374         {"DST"                         ,        8,      9,      132,    "R/W",  0,      1,      0ull,   0},
13375         {"OPC"                         ,        17,     4,      132,    "R/W",  0,      1,      0ull,   0},
13376         {"MASK"                        ,        21,     8,      132,    "R/W",  0,      1,      0ull,   0},
13377         {"RESERVED_29_63"              ,        29,     35,     132,    "RAZ",  1,      1,      0,      0},
13378         {"SRC"                         ,        0,      8,      133,    "R/W",  0,      1,      0ull,   0},
13379         {"DST"                         ,        8,      9,      133,    "R/W",  0,      1,      0ull,   0},
13380         {"OPC"                         ,        17,     4,      133,    "R/W",  0,      1,      0ull,   0},
13381         {"MASK"                        ,        21,     8,      133,    "R/W",  0,      1,      0ull,   0},
13382         {"RESERVED_29_63"              ,        29,     35,     133,    "RAZ",  1,      1,      0,      0},
13383         {"DATA"                        ,        0,      64,     134,    "R/W",  0,      1,      0ull,   0},
13384         {"DATA"                        ,        0,      64,     135,    "R/W",  0,      1,      0ull,   0},
13385         {"NP_SOP"                      ,        0,      1,      136,    "R/W",  0,      0,      0ull,   0ull},
13386         {"NP_EOP"                      ,        1,      1,      136,    "R/W",  0,      0,      0ull,   0ull},
13387         {"P_SOP"                       ,        2,      1,      136,    "R/W",  0,      0,      0ull,   0ull},
13388         {"P_EOP"                       ,        3,      1,      136,    "R/W",  0,      0,      0ull,   0ull},
13389         {"RESERVED_4_63"               ,        4,      60,     136,    "RAZ",  1,      1,      0,      0},
13390         {"NP_SOP"                      ,        0,      1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
13391         {"NP_EOP"                      ,        1,      1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
13392         {"P_SOP"                       ,        2,      1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
13393         {"P_EOP"                       ,        3,      1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
13394         {"RESERVED_4_63"               ,        4,      60,     137,    "RAZ",  1,      1,      0,      0},
13395         {"SRC"                         ,        0,      9,      138,    "R/W",  0,      1,      0ull,   0},
13396         {"DST"                         ,        9,      8,      138,    "R/W",  0,      1,      0ull,   0},
13397         {"EOT"                         ,        17,     1,      138,    "R/W",  0,      1,      0ull,   0},
13398         {"MASK"                        ,        18,     8,      138,    "R/W",  0,      1,      0ull,   0},
13399         {"RESERVED_26_63"              ,        26,     38,     138,    "RAZ",  1,      1,      0,      0},
13400         {"SRC"                         ,        0,      9,      139,    "R/W",  0,      1,      0ull,   0},
13401         {"DST"                         ,        9,      8,      139,    "R/W",  0,      1,      0ull,   0},
13402         {"EOT"                         ,        17,     1,      139,    "R/W",  0,      1,      0ull,   0},
13403         {"MASK"                        ,        18,     8,      139,    "R/W",  0,      1,      0ull,   0},
13404         {"RESERVED_26_63"              ,        26,     38,     139,    "RAZ",  1,      1,      0,      0},
13405         {"DATA"                        ,        0,      64,     140,    "R/W",  0,      1,      0ull,   0},
13406         {"DATA"                        ,        0,      64,     141,    "R/W",  0,      1,      0ull,   0},
13407         {"PORT"                        ,        0,      6,      142,    "RO",   0,      1,      0ull,   0},
13408         {"RESERVED_6_63"               ,        6,      58,     142,    "RAZ",  1,      1,      0,      0},
13409         {"SKIP_SZ"                     ,        0,      6,      143,    "R/W",  0,      0,      0ull,   0ull},
13410         {"RESERVED_6_63"               ,        6,      58,     143,    "RAZ",  1,      1,      0,      0},
13411         {"BACK"                        ,        0,      4,      144,    "R/W",  0,      0,      0ull,   0ull},
13412         {"RESERVED_4_63"               ,        4,      60,     144,    "RAZ",  1,      1,      0,      0},
13413         {"BACK"                        ,        0,      4,      145,    "R/W",  0,      0,      0ull,   0ull},
13414         {"RESERVED_4_63"               ,        4,      60,     145,    "RAZ",  1,      1,      0,      0},
13415         {"PWP"                         ,        0,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13416         {"IPD_NEW"                     ,        1,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13417         {"IPD_OLD"                     ,        2,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13418         {"PRC_OFF"                     ,        3,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13419         {"PWQ0"                        ,        4,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13420         {"PWQ1"                        ,        5,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13421         {"PBM_WORD"                    ,        6,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13422         {"PBM0"                        ,        7,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13423         {"PBM1"                        ,        8,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13424         {"PBM2"                        ,        9,      1,      146,    "RO",   0,      0,      0ull,   0ull},
13425         {"PBM3"                        ,        10,     1,      146,    "RO",   0,      0,      0ull,   0ull},
13426         {"IPQ_PBE0"                    ,        11,     1,      146,    "RO",   0,      0,      0ull,   0ull},
13427         {"IPQ_PBE1"                    ,        12,     1,      146,    "RO",   0,      0,      0ull,   0ull},
13428         {"PWQ_POW"                     ,        13,     1,      146,    "RO",   0,      0,      0ull,   0ull},
13429         {"PWQ_WP1"                     ,        14,     1,      146,    "RO",   0,      0,      0ull,   0ull},
13430         {"PWQ_WQED"                    ,        15,     1,      146,    "RO",   0,      0,      0ull,   0ull},
13431         {"RESERVED_16_63"              ,        16,     48,     146,    "RAZ",  1,      1,      0,      0},
13432         {"PRT_ENB"                     ,        0,      36,     147,    "R/W",  0,      0,      0ull,   0ull},
13433         {"RESERVED_36_63"              ,        36,     28,     147,    "RAZ",  1,      1,      0,      0},
13434         {"CLK_CNT"                     ,        0,      64,     148,    "RO",   0,      0,      0ull,   0ull},
13435         {"IPD_EN"                      ,        0,      1,      149,    "R/W",  0,      0,      0ull,   0ull},
13436         {"OPC_MODE"                    ,        1,      2,      149,    "R/W",  0,      0,      0ull,   0ull},
13437         {"PBP_EN"                      ,        3,      1,      149,    "R/W",  0,      0,      0ull,   0ull},
13438         {"WQE_LEND"                    ,        4,      1,      149,    "R/W",  0,      0,      0ull,   0ull},
13439         {"PKT_LEND"                    ,        5,      1,      149,    "R/W",  0,      0,      0ull,   0ull},
13440         {"NADDBUF"                     ,        6,      1,      149,    "R/W",  0,      0,      0ull,   0ull},
13441         {"ADDPKT"                      ,        7,      1,      149,    "R/W",  0,      0,      0ull,   0ull},
13442         {"RESET"                       ,        8,      1,      149,    "R/W",  0,      0,      0ull,   0ull},
13443         {"LEN_M8"                      ,        9,      1,      149,    "R/W",  0,      0,      0ull,   1ull},
13444         {"RESERVED_10_63"              ,        10,     54,     149,    "RAZ",  1,      1,      0,      0},
13445         {"PRC_PAR0"                    ,        0,      1,      150,    "R/W",  0,      0,      0ull,   0ull},
13446         {"PRC_PAR1"                    ,        1,      1,      150,    "R/W",  0,      0,      0ull,   0ull},
13447         {"PRC_PAR2"                    ,        2,      1,      150,    "R/W",  0,      0,      0ull,   0ull},
13448         {"PRC_PAR3"                    ,        3,      1,      150,    "R/W",  0,      0,      0ull,   0ull},
13449         {"BP_SUB"                      ,        4,      1,      150,    "R/W",  0,      0,      0ull,   0ull},
13450         {"RESERVED_5_63"               ,        5,      59,     150,    "RAZ",  1,      1,      0,      0},
13451         {"PRC_PAR0"                    ,        0,      1,      151,    "R/W1C",        0,      0,      0ull,   0ull},
13452         {"PRC_PAR1"                    ,        1,      1,      151,    "R/W1C",        0,      0,      0ull,   0ull},
13453         {"PRC_PAR2"                    ,        2,      1,      151,    "R/W1C",        0,      0,      0ull,   0ull},
13454         {"PRC_PAR3"                    ,        3,      1,      151,    "R/W1C",        0,      0,      0ull,   0ull},
13455         {"BP_SUB"                      ,        4,      1,      151,    "R/W1C",        0,      0,      0ull,   0ull},
13456         {"RESERVED_5_63"               ,        5,      59,     151,    "RAZ",  1,      1,      0,      0},
13457         {"SKIP_SZ"                     ,        0,      6,      152,    "R/W",  0,      0,      0ull,   0ull},
13458         {"RESERVED_6_63"               ,        6,      58,     152,    "RAZ",  1,      1,      0,      0},
13459         {"MB_SIZE"                     ,        0,      12,     153,    "R/W",  0,      0,      32ull,  32ull},
13460         {"RESERVED_12_63"              ,        12,     52,     153,    "RAZ",  1,      1,      0,      0},
13461         {"PTR"                         ,        0,      29,     154,    "RO",   1,      1,      0,      0},
13462         {"RESERVED_29_63"              ,        29,     35,     154,    "RAZ",  1,      1,      0,      0},
13463         {"PAGE_CNT"                    ,        0,      17,     155,    "R/W",  0,      0,      0ull,   0ull},
13464         {"BP_ENB"                      ,        17,     1,      155,    "R/W",  0,      0,      0ull,   0ull},
13465         {"RESERVED_18_63"              ,        18,     46,     155,    "RAZ",  1,      1,      0,      0},
13466         {"CNT_VAL"                     ,        0,      25,     156,    "RO",   0,      1,      0ull,   0},
13467         {"RESERVED_25_63"              ,        25,     39,     156,    "RAZ",  1,      1,      0,      0},
13468         {"RADDR"                       ,        0,      3,      157,    "R/W",  0,      0,      0ull,   0ull},
13469         {"CENA"                        ,        3,      1,      157,    "R/W",  0,      0,      1ull,   1ull},
13470         {"PTR"                         ,        4,      29,     157,    "RO",   1,      1,      0,      0},
13471         {"PRADDR"                      ,        33,     3,      157,    "RO",   1,      1,      0,      0},
13472         {"MAX_PKT"                     ,        36,     3,      157,    "RO",   0,      0,      5ull,   5ull},
13473         {"RESERVED_39_63"              ,        39,     25,     157,    "RAZ",  1,      1,      0,      0},
13474         {"RADDR"                       ,        0,      7,      158,    "R/W",  0,      0,      0ull,   0ull},
13475         {"CENA"                        ,        7,      1,      158,    "R/W",  0,      0,      1ull,   1ull},
13476         {"PTR"                         ,        8,      29,     158,    "RO",   1,      1,      0,      0},
13477         {"MAX_PKT"                     ,        37,     7,      158,    "RO",   0,      0,      4ull,   4ull},
13478         {"RESERVED_44_63"              ,        44,     20,     158,    "RAZ",  1,      1,      0,      0},
13479         {"WQE_PCNT"                    ,        0,      7,      159,    "RO",   0,      0,      0ull,   0ull},
13480         {"PKT_PCNT"                    ,        7,      7,      159,    "RO",   0,      0,      0ull,   0ull},
13481         {"PFIF_CNT"                    ,        14,     3,      159,    "RO",   0,      0,      0ull,   0ull},
13482         {"WQEV_CNT"                    ,        17,     1,      159,    "RO",   0,      0,      0ull,   0ull},
13483         {"PKTV_CNT"                    ,        18,     1,      159,    "RO",   0,      0,      0ull,   0ull},
13484         {"RESERVED_19_63"              ,        19,     45,     159,    "RAZ",  1,      1,      0,      0},
13485         {"RADDR"                       ,        0,      8,      160,    "R/W",  0,      0,      0ull,   0ull},
13486         {"CENA"                        ,        8,      1,      160,    "R/W",  0,      0,      1ull,   1ull},
13487         {"PTR"                         ,        9,      29,     160,    "RO",   1,      1,      0,      0},
13488         {"PRADDR"                      ,        38,     8,      160,    "RO",   1,      1,      0,      0},
13489         {"WRADDR"                      ,        46,     8,      160,    "RO",   1,      1,      0,      0},
13490         {"MAX_CNTS"                    ,        54,     7,      160,    "RO",   0,      0,      8ull,   8ull},
13491         {"RESERVED_61_63"              ,        61,     3,      160,    "RAZ",  1,      1,      0,      0},
13492         {"PASS"                        ,        0,      32,     161,    "R/W",  0,      1,      0ull,   0},
13493         {"DROP"                        ,        32,     32,     161,    "R/W",  0,      1,      0ull,   0},
13494         {"Q0_PCNT"                     ,        0,      32,     162,    "RO",   0,      0,      0ull,   0ull},
13495         {"RESERVED_32_63"              ,        32,     32,     162,    "RAZ",  1,      1,      0,      0},
13496         {"PRT_ENB"                     ,        0,      36,     163,    "R/W",  0,      0,      0ull,   0ull},
13497         {"AVG_DLY"                     ,        36,     14,     163,    "R/W",  0,      1,      0ull,   0},
13498         {"PRB_DLY"                     ,        50,     14,     163,    "R/W",  0,      0,      0ull,   0ull},
13499         {"PRB_CON"                     ,        0,      32,     164,    "R/W",  0,      1,      0ull,   0},
13500         {"AVG_CON"                     ,        32,     8,      164,    "R/W",  0,      1,      0ull,   0},
13501         {"NEW_CON"                     ,        40,     8,      164,    "R/W",  0,      1,      0ull,   0},
13502         {"USE_PCNT"                    ,        48,     1,      164,    "R/W",  0,      0,      0ull,   0ull},
13503         {"RESERVED_49_63"              ,        49,     15,     164,    "RAZ",  1,      1,      0,      0},
13504         {"PAGE_CNT"                    ,        0,      25,     165,    "R/W",  1,      0,      0,      0ull},
13505         {"PORT"                        ,        25,     6,      165,    "R/W",  1,      0,      0,      0ull},
13506         {"RESERVED_31_63"              ,        31,     33,     165,    "RAZ",  1,      1,      0,      0},
13507         {"PORT_BIT"                    ,        0,      3,      166,    "R/W",  0,      0,      7ull,   7ull},
13508         {"RESERVED_3_63"               ,        3,      61,     166,    "RAZ",  1,      1,      0,      0},
13509         {"WQE_POOL"                    ,        0,      3,      167,    "R/W",  0,      0,      1ull,   1ull},
13510         {"RESERVED_3_63"               ,        3,      61,     167,    "RAZ",  1,      1,      0,      0},
13511         {"PTR"                         ,        0,      29,     168,    "RO",   1,      1,      0,      0},
13512         {"RESERVED_29_63"              ,        29,     35,     168,    "RAZ",  1,      1,      0,      0},
13513         {"WLB_DAT"                     ,        0,      4,      169,    "RO",   0,      0,      0ull,   0ull},
13514         {"RESERVED_4_4"                ,        4,      1,      169,    "RAZ",  0,      0,      0ull,   0ull},
13515         {"DT"                          ,        5,      1,      169,    "RO",   0,      0,      0ull,   0ull},
13516         {"DTCNT"                       ,        6,      9,      169,    "RO",   0,      0,      0ull,   0ull},
13517         {"RESERVED_15_18"              ,        15,     4,      169,    "RAZ",  0,      0,      0ull,   0ull},
13518         {"WLB_MSK"                     ,        19,     4,      169,    "RO",   0,      0,      0ull,   0ull},
13519         {"RESERVED_23_63"              ,        23,     41,     169,    "RAZ",  0,      0,      0ull,   0ull},
13520         {"L2T"                         ,        0,      5,      170,    "RO",   0,      0,      0ull,   0ull},
13521         {"RESERVED_5_8"                ,        5,      4,      170,    "RAZ",  0,      0,      0ull,   0ull},
13522         {"VAB_VWCF"                    ,        9,      1,      170,    "RO",   0,      0,      0ull,   0ull},
13523         {"LRF"                         ,        10,     2,      170,    "RO",   0,      0,      0ull,   0ull},
13524         {"VWDF"                        ,        12,     4,      170,    "RO",   0,      0,      0ull,   0ull},
13525         {"RESERVED_16_63"              ,        16,     48,     170,    "RAZ",  0,      0,      0ull,   0ull},
13526         {"XRDDAT"                      ,        0,      1,      171,    "RO",   0,      0,      0ull,   0ull},
13527         {"XRDMSK"                      ,        1,      1,      171,    "RO",   0,      0,      0ull,   0ull},
13528         {"RESERVED_2_2"                ,        2,      1,      171,    "RAZ",  0,      0,      0ull,   0ull},
13529         {"IPCBST"                      ,        3,      1,      171,    "RO",   0,      0,      0ull,   0ull},
13530         {"RESERVED_4_7"                ,        4,      4,      171,    "RAZ",  0,      0,      0ull,   0ull},
13531         {"RMDF"                        ,        8,      4,      171,    "RO",   0,      0,      0ull,   0ull},
13532         {"MRB"                         ,        12,     4,      171,    "RO",   0,      0,      0ull,   0ull},
13533         {"RESERVED_16_63"              ,        16,     48,     171,    "RAZ",  0,      0,      0ull,   0ull},
13534         {"LRF_ARB_MODE"                ,        0,      1,      172,    "R/W",  0,      0,      1ull,   1ull},
13535         {"RFB_ARB_MODE"                ,        1,      1,      172,    "R/W",  0,      0,      1ull,   1ull},
13536         {"RSP_ARB_MODE"                ,        2,      1,      172,    "R/W",  0,      0,      1ull,   1ull},
13537         {"MWF_CRD"                     ,        3,      4,      172,    "R/W",  0,      0,      2ull,   2ull},
13538         {"IDXALIAS"                    ,        7,      1,      172,    "R/W",  0,      0,      0ull,   1ull},
13539         {"FPEN"                        ,        8,      1,      172,    "R/W",  0,      0,      0ull,   0ull},
13540         {"FPEMPTY"                     ,        9,      1,      172,    "R/W",  0,      0,      0ull,   0ull},
13541         {"FPEXP"                       ,        10,     4,      172,    "R/W",  0,      0,      0ull,   0ull},
13542         {"RESERVED_14_63"              ,        14,     50,     172,    "RAZ",  1,      1,      0,      0},
13543         {"L2T"                         ,        0,      1,      173,    "R/W",  0,      0,      0ull,   0ull},
13544         {"L2D"                         ,        1,      1,      173,    "R/W",  0,      0,      0ull,   0ull},
13545         {"FINV"                        ,        2,      1,      173,    "R/W",  0,      0,      0ull,   0ull},
13546         {"SET"                         ,        3,      2,      173,    "R/W",  0,      0,      0ull,   0ull},
13547         {"RESERVED_5_5"                ,        5,      1,      173,    "RAZ",  0,      0,      0ull,   0ull},
13548         {"PPNUM"                       ,        6,      1,      173,    "RAZ",  0,      0,      0ull,   0ull},
13549         {"RESERVED_7_9"                ,        7,      3,      173,    "RAZ",  0,      0,      0ull,   0ull},
13550         {"LFB_DMP"                     ,        10,     1,      173,    "R/W",  0,      0,      0ull,   0ull},
13551         {"LFB_ENUM"                    ,        11,     2,      173,    "R/W",  0,      0,      0ull,   0ull},
13552         {"RESERVED_13_63"              ,        13,     51,     173,    "RAZ",  0,      0,      0ull,   0ull},
13553         {"DT_TAG"                      ,        0,      29,     174,    "RO",   0,      0,      0ull,   0ull},
13554         {"DT_VLD"                      ,        29,     1,      174,    "RO",   0,      0,      0ull,   0ull},
13555         {"RESERVED_30_30"              ,        30,     1,      174,    "RAZ",  0,      0,      0ull,   0ull},
13556         {"DTENA"                       ,        31,     1,      174,    "R/W",  0,      0,      0ull,   0ull},
13557         {"RESERVED_32_63"              ,        32,     32,     174,    "RAZ",  0,      0,      0ull,   0ull},
13558         {"LCK_ENA"                     ,        0,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
13559         {"RESERVED_1_3"                ,        1,      3,      175,    "RAZ",  0,      0,      0ull,   0ull},
13560         {"LCK_BASE"                    ,        4,      27,     175,    "R/W",  0,      0,      0ull,   0ull},
13561         {"RESERVED_31_63"              ,        31,     33,     175,    "RAZ",  0,      0,      0ull,   0ull},
13562         {"LCK_OFFSET"                  ,        0,      10,     176,    "R/W",  0,      0,      0ull,   0ull},
13563         {"RESERVED_10_63"              ,        10,     54,     176,    "RAZ",  0,      0,      0ull,   0ull},
13564         {"VLD"                         ,        0,      1,      177,    "RO",   0,      0,      0ull,   0ull},
13565         {"CMD"                         ,        1,      4,      177,    "RO",   0,      0,      0ull,   0ull},
13566         {"SID"                         ,        5,      9,      177,    "RO",   0,      0,      0ull,   0ull},
13567         {"VABNUM"                      ,        14,     2,      177,    "RO",   0,      0,      0ull,   0ull},
13568         {"RESERVED_16_17"              ,        16,     2,      177,    "RAZ",  0,      0,      0ull,   0ull},
13569         {"SET"                         ,        18,     2,      177,    "RO",   0,      0,      0ull,   0ull},
13570         {"RESERVED_20_20"              ,        20,     1,      177,    "RAZ",  0,      0,      0ull,   0ull},
13571         {"IHD"                         ,        21,     1,      177,    "RO",   0,      0,      0ull,   0ull},
13572         {"ITL"                         ,        22,     1,      177,    "RO",   0,      0,      0ull,   0ull},
13573         {"INXT"                        ,        23,     2,      177,    "RO",   0,      0,      0ull,   0ull},
13574         {"RESERVED_25_26"              ,        25,     2,      177,    "RAZ",  0,      0,      0ull,   0ull},
13575         {"VAM"                         ,        27,     1,      177,    "RO",   0,      0,      0ull,   0ull},
13576         {"STCFL"                       ,        28,     1,      177,    "RO",   0,      0,      0ull,   0ull},
13577         {"STINV"                       ,        29,     1,      177,    "RO",   0,      0,      0ull,   0ull},
13578         {"STPND"                       ,        30,     1,      177,    "RO",   0,      0,      0ull,   0ull},
13579         {"STCPND"                      ,        31,     1,      177,    "RO",   0,      0,      0ull,   0ull},
13580         {"RESERVED_32_63"              ,        32,     32,     177,    "RAZ",  0,      0,      0ull,   0ull},
13581         {"VLD"                         ,        0,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13582         {"WTPRB"                       ,        1,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13583         {"PRBRTY"                      ,        2,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13584         {"WTMFL"                       ,        3,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13585         {"WTVTM"                       ,        4,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13586         {"WTSTRSC"                     ,        5,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13587         {"WTSTRSP"                     ,        6,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13588         {"WTSTDT"                      ,        7,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13589         {"WTRDA"                       ,        8,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13590         {"WTSTM"                       ,        9,      1,      178,    "RO",   0,      0,      0ull,   0ull},
13591         {"WTWRM"                       ,        10,     1,      178,    "RO",   0,      0,      0ull,   0ull},
13592         {"WTWHF"                       ,        11,     1,      178,    "RO",   0,      0,      0ull,   0ull},
13593         {"WTWHP"                       ,        12,     1,      178,    "RO",   0,      0,      0ull,   0ull},
13594         {"WTDQ"                        ,        13,     1,      178,    "RO",   0,      0,      0ull,   0ull},
13595         {"WTDW"                        ,        14,     1,      178,    "RO",   0,      0,      0ull,   0ull},
13596         {"WTRSP"                       ,        15,     1,      178,    "RO",   0,      0,      0ull,   0ull},
13597         {"BID"                         ,        16,     2,      178,    "RO",   0,      0,      0ull,   0ull},
13598         {"DSGOING"                     ,        18,     1,      178,    "RO",   0,      0,      0ull,   0ull},
13599         {"RESERVED_19_63"              ,        19,     45,     178,    "RAZ",  0,      0,      0ull,   0ull},
13600         {"LFB_IDX"                     ,        0,      8,      179,    "RO",   0,      0,      0ull,   0ull},
13601         {"LFB_TAG"                     ,        8,      19,     179,    "RO",   0,      0,      0ull,   0ull},
13602         {"RESERVED_27_63"              ,        27,     37,     179,    "RAZ",  0,      0,      0ull,   0ull},
13603         {"LFB_HWM"                     ,        0,      2,      180,    "R/W",  0,      0,      3ull,   3ull},
13604         {"RESERVED_2_3"                ,        2,      2,      180,    "RAZ",  0,      0,      0ull,   0ull},
13605         {"STPARTDIS"                   ,        4,      1,      180,    "R/W",  0,      0,      0ull,   0ull},
13606         {"RESERVED_5_63"               ,        5,      59,     180,    "RAZ",  0,      0,      0ull,   0ull},
13607         {"PFCNT0"                      ,        0,      36,     181,    "RO",   0,      0,      0ull,   0ull},
13608         {"RESERVED_36_63"              ,        36,     28,     181,    "RAZ",  0,      0,      0ull,   0ull},
13609         {"CNT0SEL"                     ,        0,      6,      182,    "R/W",  0,      0,      0ull,   0ull},
13610         {"CNT0CLR"                     ,        6,      1,      182,    "R/W",  0,      0,      0ull,   0ull},
13611         {"CNT0ENA"                     ,        7,      1,      182,    "R/W",  0,      0,      0ull,   0ull},
13612         {"CNT1SEL"                     ,        8,      6,      182,    "R/W",  0,      0,      0ull,   0ull},
13613         {"CNT1CLR"                     ,        14,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13614         {"CNT1ENA"                     ,        15,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13615         {"CNT2SEL"                     ,        16,     6,      182,    "R/W",  0,      0,      0ull,   0ull},
13616         {"CNT2CLR"                     ,        22,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13617         {"CNT2ENA"                     ,        23,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13618         {"CNT3SEL"                     ,        24,     6,      182,    "R/W",  0,      0,      0ull,   0ull},
13619         {"CNT3CLR"                     ,        30,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13620         {"CNT3ENA"                     ,        31,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13621         {"CNT0RDCLR"                   ,        32,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13622         {"CNT1RDCLR"                   ,        33,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13623         {"CNT2RDCLR"                   ,        34,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13624         {"CNT3RDCLR"                   ,        35,     1,      182,    "R/W",  0,      0,      0ull,   0ull},
13625         {"RESERVED_36_63"              ,        36,     28,     182,    "RAZ",  0,      0,      0ull,   0ull},
13626         {"UMSK0"                       ,        0,      4,      183,    "R/W",  0,      0,      0ull,   0ull},
13627         {"RESERVED_4_63"               ,        4,      60,     183,    "RAZ",  0,      0,      0ull,   0ull},
13628         {"UMSKIOB"                     ,        0,      4,      184,    "R/W",  0,      0,      0ull,   0ull},
13629         {"RESERVED_4_63"               ,        4,      60,     184,    "RAZ",  0,      0,      0ull,   0ull},
13630         {"Q0STAT"                      ,        0,      34,     185,    "RO",   0,      0,      0ull,   0ull},
13631         {"FTL"                         ,        34,     1,      185,    "RO",   0,      0,      0ull,   0ull},
13632         {"RESERVED_35_63"              ,        35,     29,     185,    "RAZ",  0,      0,      0ull,   0ull},
13633         {"Q1STAT"                      ,        0,      34,     186,    "RO",   0,      0,      0ull,   0ull},
13634         {"RESERVED_34_63"              ,        34,     30,     186,    "RAZ",  0,      0,      0ull,   0ull},
13635         {"Q2STAT"                      ,        0,      34,     187,    "RO",   0,      0,      0ull,   0ull},
13636         {"RESERVED_34_63"              ,        34,     30,     187,    "RAZ",  0,      0,      0ull,   0ull},
13637         {"Q3STAT"                      ,        0,      34,     188,    "RO",   0,      0,      0ull,   0ull},
13638         {"RESERVED_34_63"              ,        34,     30,     188,    "RAZ",  0,      0,      0ull,   0ull},
13639         {"ECC_ENA"                     ,        0,      1,      189,    "R/W",  0,      0,      0ull,   1ull},
13640         {"SEC_INTENA"                  ,        1,      1,      189,    "R/W",  0,      0,      0ull,   1ull},
13641         {"DED_INTENA"                  ,        2,      1,      189,    "R/W",  0,      0,      0ull,   1ull},
13642         {"SEC_ERR"                     ,        3,      1,      189,    "R/W1C",        0,      0,      0ull,   0ull},
13643         {"DED_ERR"                     ,        4,      1,      189,    "R/W1C",        0,      0,      0ull,   0ull},
13644         {"BMHCLSEL"                    ,        5,      1,      189,    "R/W",  0,      0,      0ull,   0ull},
13645         {"RESERVED_6_63"               ,        6,      58,     189,    "RAZ",  0,      0,      0ull,   0ull},
13646         {"FADR"                        ,        0,      9,      190,    "RO",   0,      0,      0ull,   0ull},
13647         {"RESERVED_9_10"               ,        9,      2,      190,    "RAZ",  0,      0,      0ull,   0ull},
13648         {"FSET"                        ,        11,     2,      190,    "RO",   0,      0,      0ull,   0ull},
13649         {"RESERVED_13_13"              ,        13,     1,      190,    "RAZ",  0,      0,      0ull,   0ull},
13650         {"FOWMSK"                      ,        14,     4,      190,    "RO",   0,      0,      0ull,   0ull},
13651         {"RESERVED_18_63"              ,        18,     46,     190,    "RAZ",  0,      0,      0ull,   0ull},
13652         {"FSYN_OW0"                    ,        0,      10,     191,    "RO",   0,      0,      0ull,   0ull},
13653         {"FSYN_OW1"                    ,        10,     10,     191,    "RO",   0,      0,      0ull,   0ull},
13654         {"RESERVED_20_63"              ,        20,     44,     191,    "RAZ",  0,      0,      0ull,   0ull},
13655         {"FSYN_OW2"                    ,        0,      10,     192,    "RO",   0,      0,      0ull,   0ull},
13656         {"FSYN_OW3"                    ,        10,     10,     192,    "RO",   0,      0,      0ull,   0ull},
13657         {"RESERVED_20_63"              ,        20,     44,     192,    "RAZ",  0,      0,      0ull,   0ull},
13658         {"Q0FUS"                       ,        0,      34,     193,    "RO",   0,      0,      0ull,   0ull},
13659         {"RESERVED_34_63"              ,        34,     30,     193,    "RAZ",  0,      0,      0ull,   0ull},
13660         {"Q1FUS"                       ,        0,      34,     194,    "RO",   0,      0,      0ull,   0ull},
13661         {"RESERVED_34_63"              ,        34,     30,     194,    "RAZ",  0,      0,      0ull,   0ull},
13662         {"Q2FUS"                       ,        0,      34,     195,    "RO",   0,      0,      0ull,   0ull},
13663         {"RESERVED_34_63"              ,        34,     30,     195,    "RAZ",  0,      0,      0ull,   0ull},
13664         {"Q3FUS"                       ,        0,      34,     196,    "RO",   0,      0,      0ull,   0ull},
13665         {"CRIP_64K"                    ,        34,     1,      196,    "RO",   0,      0,      0ull,   0ull},
13666         {"RESERVED_35_63"              ,        35,     29,     196,    "RAZ",  0,      0,      0ull,   0ull},
13667         {"ECC_ENA"                     ,        0,      1,      197,    "R/W",  0,      0,      0ull,   1ull},
13668         {"SEC_INTENA"                  ,        1,      1,      197,    "R/W",  0,      0,      0ull,   1ull},
13669         {"DED_INTENA"                  ,        2,      1,      197,    "R/W",  0,      0,      0ull,   1ull},
13670         {"SEC_ERR"                     ,        3,      1,      197,    "R/W1C",        0,      0,      0ull,   0ull},
13671         {"DED_ERR"                     ,        4,      1,      197,    "R/W1C",        0,      0,      0ull,   0ull},
13672         {"FSYN"                        ,        5,      6,      197,    "RO",   0,      0,      0ull,   0ull},
13673         {"FADR"                        ,        11,     8,      197,    "RO",   0,      0,      0ull,   0ull},
13674         {"RESERVED_19_20"              ,        19,     2,      197,    "RAZ",  0,      0,      0ull,   0ull},
13675         {"FSET"                        ,        21,     2,      197,    "RO",   0,      0,      0ull,   0ull},
13676         {"RESERVED_23_23"              ,        23,     1,      197,    "RAZ",  0,      0,      0ull,   0ull},
13677         {"LCKERR"                      ,        24,     1,      197,    "R/W1C",        0,      0,      0ull,   0ull},
13678         {"LCK_INTENA"                  ,        25,     1,      197,    "R/W",  0,      0,      0ull,   1ull},
13679         {"LCKERR2"                     ,        26,     1,      197,    "R/W1C",        0,      0,      0ull,   0ull},
13680         {"LCK_INTENA2"                 ,        27,     1,      197,    "R/W",  0,      0,      0ull,   1ull},
13681         {"RESERVED_28_63"              ,        28,     36,     197,    "RAZ",  0,      0,      0ull,   0ull},
13682         {"PCTL_DAT"                    ,        0,      4,      198,    "R/W",  0,      1,      0ull,   0},
13683         {"PCTL_CMD"                    ,        4,      4,      198,    "R/W",  0,      1,      0ull,   0},
13684         {"PCTL_CLK"                    ,        8,      4,      198,    "R/W",  0,      1,      0ull,   0},
13685         {"PCTL_CSR"                    ,        12,     4,      198,    "R/W",  0,      1,      15ull,  0},
13686         {"NCTL_DAT"                    ,        16,     4,      198,    "R/W",  0,      1,      0ull,   0},
13687         {"NCTL_CMD"                    ,        20,     4,      198,    "R/W",  0,      1,      0ull,   0},
13688         {"NCTL_CLK"                    ,        24,     4,      198,    "R/W",  0,      1,      0ull,   0},
13689         {"NCTL_CSR"                    ,        28,     4,      198,    "R/W",  0,      1,      15ull,  0},
13690         {"RESERVED_32_63"              ,        32,     32,     198,    "RAZ",  0,      0,      0ull,   0ull},
13691         {"DIC"                         ,        0,      2,      199,    "R/W",  0,      0,      0ull,   0ull},
13692         {"QS_DIC"                      ,        2,      2,      199,    "R/W",  0,      0,      2ull,   2ull},
13693         {"TSKW"                        ,        4,      2,      199,    "R/W",  0,      0,      0ull,   1ull},
13694         {"SIL_LAT"                     ,        6,      2,      199,    "R/W",  0,      0,      1ull,   1ull},
13695         {"BPRCH"                       ,        8,      1,      199,    "R/W",  0,      1,      0ull,   0},
13696         {"FPRCH2"                      ,        9,      1,      199,    "R/W",  0,      0,      0ull,   1ull},
13697         {"MODE32B"                     ,        10,     1,      199,    "R/W",  0,      0,      0ull,   0ull},
13698         {"DRESET"                      ,        11,     1,      199,    "R/W",  0,      0,      1ull,   0ull},
13699         {"INORDER_MRF"                 ,        12,     1,      199,    "R/W",  0,      0,      0ull,   0ull},
13700         {"INORDER_MWF"                 ,        13,     1,      199,    "RAZ",  0,      0,      0ull,   0ull},
13701         {"R2R_SLOT"                    ,        14,     1,      199,    "R/W",  0,      0,      0ull,   0ull},
13702         {"RDIMM_ENA"                   ,        15,     1,      199,    "R/W",  0,      1,      0ull,   0},
13703         {"PLL_BYPASS"                  ,        16,     1,      199,    "R/W",  0,      0,      1ull,   1ull},
13704         {"PLL_DIV2"                    ,        17,     1,      199,    "R/W",  0,      0,      0ull,   0ull},
13705         {"MAX_WRITE_BATCH"             ,        18,     4,      199,    "R/W",  0,      0,      8ull,   8ull},
13706         {"XOR_BANK"                    ,        22,     1,      199,    "R/W",  0,      0,      0ull,   1ull},
13707         {"SLOW_SCF"                    ,        23,     1,      199,    "R/W",  0,      0,      0ull,   0ull},
13708         {"DDR__PCTL"                   ,        24,     4,      199,    "RO",   1,      1,      0,      0},
13709         {"DDR__NCTL"                   ,        28,     4,      199,    "RO",   1,      1,      0,      0},
13710         {"RESERVED_32_63"              ,        32,     32,     199,    "RAZ",  1,      1,      0,      0},
13711         {"DATA_LAYOUT"                 ,        0,      2,      200,    "R/W",  0,      0,      0ull,   0ull},
13712         {"RESERVED_2_63"               ,        2,      62,     200,    "RAZ",  1,      1,      0,      0},
13713         {"DCLKCNT_HI"                  ,        0,      32,     201,    "RO",   0,      0,      0ull,   0ull},
13714         {"RESERVED_32_63"              ,        32,     32,     201,    "RAZ",  1,      1,      0,      0},
13715         {"DCLKCNT_LO"                  ,        0,      32,     202,    "RO",   0,      0,      0ull,   0ull},
13716         {"RESERVED_32_63"              ,        32,     32,     202,    "RAZ",  1,      1,      0,      0},
13717         {"DDR2"                        ,        0,      1,      203,    "R/W",  0,      0,      1ull,   1ull},
13718         {"RESERVED_1_1"                ,        1,      1,      203,    "RAZ",  0,      0,      0ull,   0ull},
13719         {"DLL90_BYP"                   ,        2,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
13720         {"DLL90_VLU"                   ,        3,      5,      203,    "R/W",  0,      1,      0ull,   0},
13721         {"QDLL_ENA"                    ,        8,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
13722         {"ODT_ENA"                     ,        9,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
13723         {"DDR2T"                       ,        10,     1,      203,    "R/W",  0,      1,      0ull,   0},
13724         {"CRIP_MODE"                   ,        11,     1,      203,    "R/W",  0,      0,      0ull,   0ull},
13725         {"TFAW"                        ,        12,     5,      203,    "R/W",  0,      0,      0ull,   9ull},
13726         {"DDR_EOF"                     ,        17,     4,      203,    "R/W",  0,      0,      2ull,   2ull},
13727         {"SILO_HC"                     ,        21,     1,      203,    "R/W",  0,      1,      1ull,   0},
13728         {"TWR"                         ,        22,     3,      203,    "R/W",  0,      0,      3ull,   1ull},
13729         {"BWCNT"                       ,        25,     1,      203,    "R/W",  0,      0,      0ull,   0ull},
13730         {"POCAS"                       ,        26,     1,      203,    "R/W",  0,      0,      0ull,   0ull},
13731         {"ADDLAT"                      ,        27,     3,      203,    "R/W",  0,      0,      0ull,   0ull},
13732         {"BURST8"                      ,        30,     1,      203,    "R/W",  0,      0,      0ull,   1ull},
13733         {"BANK8"                       ,        31,     1,      203,    "R/W",  0,      1,      0ull,   0},
13734         {"RESERVED_32_63"              ,        32,     32,     203,    "RAZ",  0,      0,      0ull,   0ull},
13735         {"CLK"                         ,        0,      5,      204,    "R/W",  0,      0,      0ull,   0ull},
13736         {"CMD"                         ,        5,      5,      204,    "R/W",  0,      0,      0ull,   0ull},
13737         {"DQ"                          ,        10,     5,      204,    "R/W",  0,      0,      0ull,   0ull},
13738         {"RESERVED_15_63"              ,        15,     49,     204,    "RAZ",  1,      1,      0,      0},
13739         {"MRDSYN0"                     ,        0,      8,      205,    "RO",   0,      0,      0ull,   0ull},
13740         {"MRDSYN1"                     ,        8,      8,      205,    "RO",   0,      0,      0ull,   0ull},
13741         {"MRDSYN2"                     ,        16,     8,      205,    "RO",   0,      0,      0ull,   0ull},
13742         {"MRDSYN3"                     ,        24,     8,      205,    "RO",   0,      0,      0ull,   0ull},
13743         {"RESERVED_32_63"              ,        32,     32,     205,    "RAZ",  1,      1,      0,      0},
13744         {"FCOL"                        ,        0,      12,     206,    "RO",   0,      0,      0ull,   0ull},
13745         {"FROW"                        ,        12,     14,     206,    "RO",   0,      0,      0ull,   0ull},
13746         {"FBANK"                       ,        26,     3,      206,    "RO",   0,      0,      0ull,   0ull},
13747         {"FBUNK"                       ,        29,     1,      206,    "RO",   0,      0,      0ull,   0ull},
13748         {"FDIMM"                       ,        30,     2,      206,    "RO",   0,      0,      0ull,   0ull},
13749         {"RESERVED_32_63"              ,        32,     32,     206,    "RAZ",  1,      1,      0,      0},
13750         {"IFBCNT_HI"                   ,        0,      32,     207,    "RO",   0,      0,      0ull,   0ull},
13751         {"RESERVED_32_63"              ,        32,     32,     207,    "RAZ",  1,      1,      0,      0},
13752         {"IFBCNT_LO"                   ,        0,      32,     208,    "RO",   0,      0,      0ull,   0ull},
13753         {"RESERVED_32_63"              ,        32,     32,     208,    "RAZ",  1,      1,      0,      0},
13754         {"INIT_START"                  ,        0,      1,      209,    "R/W",  0,      0,      0ull,   0ull},
13755         {"ECC_ENA"                     ,        1,      1,      209,    "R/W",  0,      0,      0ull,   1ull},
13756         {"ROW_LSB"                     ,        2,      3,      209,    "R/W",  0,      1,      3ull,   0},
13757         {"PBANK_LSB"                   ,        5,      4,      209,    "R/W",  0,      1,      5ull,   0},
13758         {"REF_INT"                     ,        9,      6,      209,    "R/W",  0,      0,      1ull,   2ull},
13759         {"TCL"                         ,        15,     4,      209,    "R/W",  0,      1,      3ull,   0},
13760         {"INTR_SEC_ENA"                ,        19,     1,      209,    "R/W",  0,      0,      0ull,   1ull},
13761         {"INTR_DED_ENA"                ,        20,     1,      209,    "R/W",  0,      0,      0ull,   1ull},
13762         {"SEC_ERR"                     ,        21,     4,      209,    "R/W1C",        0,      0,      0ull,   0ull},
13763         {"DED_ERR"                     ,        25,     4,      209,    "R/W1C",        0,      0,      0ull,   0ull},
13764         {"BUNK_ENA"                    ,        29,     1,      209,    "R/W",  0,      1,      0ull,   0},
13765         {"SILO_QC"                     ,        30,     1,      209,    "R/W",  0,      1,      0ull,   0},
13766         {"RESET"                       ,        31,     1,      209,    "RAZ",  1,      1,      0,      0},
13767         {"RESERVED_32_63"              ,        32,     32,     209,    "RAZ",  1,      1,      0,      0},
13768         {"TRAS"                        ,        0,      5,      210,    "R/W",  0,      0,      12ull,  12ull},
13769         {"TRCD"                        ,        5,      4,      210,    "R/W",  0,      0,      4ull,   4ull},
13770         {"TWTR"                        ,        9,      4,      210,    "R/W",  0,      0,      2ull,   2ull},
13771         {"TRP"                         ,        13,     4,      210,    "R/W",  0,      0,      5ull,   4ull},
13772         {"TRFC"                        ,        17,     5,      210,    "R/W",  0,      0,      6ull,   7ull},
13773         {"TMRD"                        ,        22,     3,      210,    "R/W",  0,      0,      2ull,   2ull},
13774         {"CASLAT"                      ,        25,     3,      210,    "R/W",  0,      0,      4ull,   4ull},
13775         {"TRRD"                        ,        28,     3,      210,    "R/W",  0,      0,      2ull,   2ull},
13776         {"COMP_BYPASS"                 ,        31,     1,      210,    "R/W",  0,      0,      0ull,   0ull},
13777         {"RESERVED_32_63"              ,        32,     32,     210,    "RAZ",  1,      1,      0,      0},
13778         {"OPSCNT_HI"                   ,        0,      32,     211,    "RO",   0,      0,      0ull,   0ull},
13779         {"RESERVED_32_63"              ,        32,     32,     211,    "RAZ",  1,      1,      0,      0},
13780         {"OPSCNT_LO"                   ,        0,      32,     212,    "RO",   0,      0,      0ull,   0ull},
13781         {"RESERVED_32_63"              ,        32,     32,     212,    "RAZ",  1,      1,      0,      0},
13782         {"BWCTL"                       ,        0,      4,      213,    "R/W",  0,      0,      0ull,   0ull},
13783         {"BWUPD"                       ,        4,      1,      213,    "R/W",  0,      0,      0ull,   0ull},
13784         {"RESERVED_5_63"               ,        5,      59,     213,    "RAZ",  1,      1,      0,      0},
13785         {"RODT_LO0"                    ,        0,      4,      214,    "R/W",  0,      0,      15ull,  15ull},
13786         {"RODT_LO1"                    ,        4,      4,      214,    "R/W",  0,      0,      15ull,  15ull},
13787         {"RODT_LO2"                    ,        8,      4,      214,    "R/W",  0,      0,      15ull,  15ull},
13788         {"RODT_LO3"                    ,        12,     4,      214,    "R/W",  0,      0,      15ull,  15ull},
13789         {"RODT_HI0"                    ,        16,     4,      214,    "R/W",  0,      0,      15ull,  15ull},
13790         {"RODT_HI1"                    ,        20,     4,      214,    "R/W",  0,      0,      15ull,  15ull},
13791         {"RODT_HI2"                    ,        24,     4,      214,    "R/W",  0,      0,      15ull,  15ull},
13792         {"RODT_HI3"                    ,        28,     4,      214,    "R/W",  0,      0,      15ull,  15ull},
13793         {"RESERVED_32_63"              ,        32,     32,     214,    "RAZ",  1,      1,      0,      0},
13794         {"WODT_D0_R0"                  ,        0,      8,      215,    "R/W",  0,      0,      255ull, 255ull},
13795         {"WODT_D0_R1"                  ,        8,      8,      215,    "R/W",  0,      0,      255ull, 255ull},
13796         {"WODT_D1_R0"                  ,        16,     8,      215,    "R/W",  0,      0,      255ull, 255ull},
13797         {"WODT_D1_R1"                  ,        24,     8,      215,    "R/W",  0,      0,      255ull, 255ull},
13798         {"RESERVED_32_63"              ,        32,     32,     215,    "RAZ",  0,      0,      0ull,   0ull},
13799         {"WODT_D2_R0"                  ,        0,      8,      216,    "R/W",  0,      0,      255ull, 255ull},
13800         {"WODT_D2_R1"                  ,        8,      8,      216,    "R/W",  0,      0,      255ull, 255ull},
13801         {"WODT_D3_R0"                  ,        16,     8,      216,    "R/W",  0,      0,      255ull, 255ull},
13802         {"WODT_D3_R1"                  ,        24,     8,      216,    "R/W",  0,      0,      255ull, 255ull},
13803         {"RESERVED_32_63"              ,        32,     32,     216,    "RAZ",  0,      0,      0ull,   0ull},
13804         {"NCBI"                        ,        0,      1,      217,    "RO",   0,      0,      0ull,   0ull},
13805         {"LOC"                         ,        1,      1,      217,    "RO",   0,      0,      0ull,   0ull},
13806         {"NCBO_0"                      ,        2,      1,      217,    "RO",   0,      0,      0ull,   0ull},
13807         {"NCBO_1"                      ,        3,      1,      217,    "RO",   0,      0,      0ull,   0ull},
13808         {"RESERVED_4_63"               ,        4,      60,     217,    "RAZ",  1,      1,      0,      0},
13809         {"ADR_ERR"                     ,        0,      1,      218,    "R/W1C",        0,      0,      0ull,   0ull},
13810         {"WAIT_ERR"                    ,        1,      1,      218,    "R/W1C",        0,      0,      0ull,   0ull},
13811         {"RESERVED_2_63"               ,        2,      62,     218,    "RAZ",  1,      1,      0,      0},
13812         {"ADR_INT"                     ,        0,      1,      219,    "R/W",  0,      1,      0ull,   0},
13813         {"WAIT_INT"                    ,        1,      1,      219,    "R/W",  0,      1,      0ull,   0},
13814         {"RESERVED_2_63"               ,        2,      62,     219,    "RAZ",  1,      1,      0,      0},
13815         {"RESERVED_0_2"                ,        0,      3,      220,    "RAZ",  1,      1,      0,      0},
13816         {"ADR"                         ,        3,      5,      220,    "R/W",  0,      1,      0ull,   0},
13817         {"RESERVED_8_63"               ,        8,      56,     220,    "RAZ",  1,      1,      0,      0},
13818         {"RESERVED_0_2"                ,        0,      3,      221,    "RAZ",  1,      1,      0,      0},
13819         {"BASE"                        ,        3,      25,     221,    "R/W",  0,      1,      0ull,   0},
13820         {"RESERVED_28_30"              ,        28,     3,      221,    "RAZ",  1,      1,      0,      0},
13821         {"EN"                          ,        31,     1,      221,    "R/W",  0,      1,      0ull,   0},
13822         {"RESERVED_32_63"              ,        32,     32,     221,    "RAZ",  1,      1,      0,      0},
13823         {"DATA"                        ,        0,      64,     222,    "R/W",  1,      1,      0,      0},
13824         {"BASE"                        ,        0,      16,     223,    "R/W",  0,      1,      0ull,   0},
13825         {"SIZE"                        ,        16,     12,     223,    "R/W",  0,      1,      0ull,   0},
13826         {"WIDTH"                       ,        28,     1,      223,    "R/W",  0,      1,      0ull,   0},
13827         {"ALE"                         ,        29,     1,      223,    "R/W",  0,      1,      0ull,   0},
13828         {"ORBIT"                       ,        30,     1,      223,    "R/W",  0,      1,      0ull,   0},
13829         {"EN"                          ,        31,     1,      223,    "R/W",  0,      1,      0ull,   0},
13830         {"OE_EXT"                      ,        32,     2,      223,    "R/W",  0,      1,      0ull,   0},
13831         {"WE_EXT"                      ,        34,     2,      223,    "R/W",  0,      1,      0ull,   0},
13832         {"SAM"                         ,        36,     1,      223,    "R/W",  0,      1,      0ull,   0},
13833         {"RESERVED_37_63"              ,        37,     27,     223,    "RAZ",  1,      1,      0,      0},
13834         {"ADR"                         ,        0,      6,      224,    "R/W",  0,      1,      63ull,  0},
13835         {"CE"                          ,        6,      6,      224,    "R/W",  0,      1,      63ull,  0},
13836         {"OE"                          ,        12,     6,      224,    "R/W",  0,      1,      63ull,  0},
13837         {"WE"                          ,        18,     6,      224,    "R/W",  0,      1,      63ull,  0},
13838         {"RD_HLD"                      ,        24,     6,      224,    "R/W",  0,      1,      63ull,  0},
13839         {"WR_HLD"                      ,        30,     6,      224,    "R/W",  0,      1,      63ull,  0},
13840         {"PAUSE"                       ,        36,     6,      224,    "R/W",  0,      1,      63ull,  0},
13841         {"WAIT"                        ,        42,     6,      224,    "R/W",  0,      1,      63ull,  0},
13842         {"PAGE"                        ,        48,     6,      224,    "R/W",  0,      1,      63ull,  0},
13843         {"ALE"                         ,        54,     6,      224,    "R/W",  0,      1,      63ull,  0},
13844         {"PAGES"                       ,        60,     2,      224,    "R/W",  0,      1,      0ull,   0},
13845         {"WAITM"                       ,        62,     1,      224,    "R/W",  0,      1,      0ull,   0},
13846         {"PAGEM"                       ,        63,     1,      224,    "R/W",  0,      1,      0ull,   0},
13847         {"FIF_THR"                     ,        0,      6,      225,    "R/W",  0,      0,      26ull,  26ull},
13848         {"RESERVED_6_7"                ,        6,      2,      225,    "RAZ",  1,      1,      0,      0},
13849         {"FIF_CNT"                     ,        8,      6,      225,    "RO",   0,      1,      0ull,   0},
13850         {"RESERVED_14_63"              ,        14,     50,     225,    "RAZ",  1,      1,      0,      0},
13851         {"MAN_INFO"                    ,        0,      32,     226,    "RO",   1,      1,      0,      0},
13852         {"RESERVED_32_63"              ,        32,     32,     226,    "RAZ",  1,      1,      0,      0},
13853         {"MAN_INFO"                    ,        0,      32,     227,    "RO",   1,      1,      0,      0},
13854         {"RESERVED_32_63"              ,        32,     32,     227,    "RAZ",  1,      1,      0,      0},
13855         {"PP_DIS"                      ,        0,      1,      228,    "RO",   1,      1,      0,      0},
13856         {"RESERVED_1_11"               ,        1,      11,     228,    "RAZ",  1,      1,      0,      0},
13857         {"PLL_OFF"                     ,        12,     4,      228,    "RO",   1,      1,      0,      0},
13858         {"CHIP_ID"                     ,        16,     8,      228,    "RO",   1,      1,      0,      0},
13859         {"BIST_DIS"                    ,        24,     1,      228,    "RO",   1,      1,      0,      0},
13860         {"RST_SHT"                     ,        25,     1,      228,    "RO",   1,      1,      0,      0},
13861         {"NOCRYPTO"                    ,        26,     1,      228,    "RO",   1,      1,      0,      0},
13862         {"NOMUL"                       ,        27,     1,      228,    "RO",   1,      1,      0,      0},
13863         {"NODFA_CP2"                   ,        28,     1,      228,    "RO",   1,      1,      0,      0},
13864         {"RESERVED_29_63"              ,        29,     35,     228,    "RAZ",  1,      1,      0,      0},
13865         {"ICACHE"                      ,        0,      24,     229,    "RO",   1,      1,      0,      0},
13866         {"NODFA_DTE"                   ,        24,     1,      229,    "RO",   1,      1,      0,      0},
13867         {"NOZIP"                       ,        25,     1,      229,    "RO",   1,      1,      0,      0},
13868         {"EFUS_IGN"                    ,        26,     1,      229,    "RO",   1,      1,      0,      0},
13869         {"EFUS_LCK"                    ,        27,     1,      229,    "RO",   1,      1,      0,      0},
13870         {"BAR2_EN"                     ,        28,     1,      229,    "RO",   1,      1,      0,      0},
13871         {"RESERVED_29_30"              ,        29,     2,      229,    "RAZ",  1,      1,      0,      0},
13872         {"PLL_DIV4"                    ,        31,     1,      229,    "RO",   1,      1,      0,      0},
13873         {"RESERVED_32_63"              ,        32,     32,     229,    "RAZ",  1,      1,      0,      0},
13874         {"PROG"                        ,        0,      1,      230,    "R/W",  1,      1,      0,      0},
13875         {"RESERVED_1_63"               ,        1,      63,     230,    "RAZ",  1,      1,      0,      0},
13876         {"ADDR"                        ,        0,      7,      231,    "R/W",  0,      0,      0ull,   0ull},
13877         {"RESERVED_7_7"                ,        7,      1,      231,    "RAZ",  1,      1,      0,      0},
13878         {"EFUSE"                       ,        8,      1,      231,    "R/W",  0,      0,      0ull,   0ull},
13879         {"RESERVED_9_11"               ,        9,      3,      231,    "RAZ",  1,      1,      0,      0},
13880         {"PEND"                        ,        12,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
13881         {"RESERVED_13_15"              ,        13,     3,      231,    "RAZ",  1,      1,      0,      0},
13882         {"DAT"                         ,        16,     8,      231,    "RO",   1,      1,      0,      0},
13883         {"RESERVED_24_63"              ,        24,     40,     231,    "RAZ",  1,      1,      0,      0},
13884         {"REPAIR0"                     ,        0,      14,     232,    "RO",   0,      0,      0ull,   0ull},
13885         {"REPAIR1"                     ,        14,     14,     232,    "RO",   0,      0,      0ull,   0ull},
13886         {"REPAIR2"                     ,        28,     14,     232,    "RO",   0,      0,      0ull,   0ull},
13887         {"RESERVED_42_63"              ,        42,     22,     232,    "RAZ",  1,      1,      0,      0},
13888         {"TOO_MANY"                    ,        0,      1,      233,    "RO",   0,      0,      0ull,   0ull},
13889         {"RESERVED_1_63"               ,        1,      63,     233,    "RAZ",  1,      1,      0,      0},
13890         {"KEY"                         ,        0,      24,     234,    "R/W",  0,      0,      0ull,   5071723ull},
13891         {"RESERVED_24_63"              ,        24,     40,     234,    "RAZ",  1,      1,      0,      0},
13892         {"ADDR"                        ,        0,      10,     235,    "R/W",  1,      1,      0,      0},
13893         {"RESERVED_10_63"              ,        10,     54,     235,    "RAZ",  1,      1,      0,      0},
13894         {"BW_CTL"                      ,        0,      5,      236,    "R/W",  0,      1,      0ull,   0},
13895         {"RESERVED_5_63"               ,        5,      59,     236,    "RAZ",  0,      0,      0ull,   0ull},
13896         {"SETTING"                     ,        0,      17,     237,    "RO",   1,      1,      0,      0},
13897         {"RESERVED_17_63"              ,        17,     47,     237,    "RAZ",  0,      0,      0ull,   0ull},
13898         {"ST_INT"                      ,        0,      1,      238,    "R/W1C",        0,      1,      0ull,   0},
13899         {"TS_INT"                      ,        1,      1,      238,    "R/W1C",        0,      1,      0ull,   0},
13900         {"CORE_INT"                    ,        2,      1,      238,    "RO",   0,      1,      0ull,   0},
13901         {"RESERVED_3_3"                ,        3,      1,      238,    "RAZ",  1,      1,      0,      0},
13902         {"ST_EN"                       ,        4,      1,      238,    "R/W",  0,      1,      0ull,   0},
13903         {"TS_EN"                       ,        5,      1,      238,    "R/W",  0,      1,      0ull,   0},
13904         {"CORE_EN"                     ,        6,      1,      238,    "R/W",  0,      1,      0ull,   0},
13905         {"RESERVED_7_7"                ,        7,      1,      238,    "RAZ",  1,      1,      0,      0},
13906         {"SDA_OVR"                     ,        8,      1,      238,    "R/W",  0,      1,      0ull,   0},
13907         {"SCL_OVR"                     ,        9,      1,      238,    "R/W",  0,      1,      0ull,   0},
13908         {"SDA"                         ,        10,     1,      238,    "RO",   1,      1,      0,      0},
13909         {"SCL"                         ,        11,     1,      238,    "RO",   1,      1,      0,      0},
13910         {"RESERVED_12_63"              ,        12,     52,     238,    "RAZ",  1,      1,      0,      0},
13911         {"D"                           ,        0,      32,     239,    "R/W",  0,      1,      0ull,   0},
13912         {"EOP_IA"                      ,        32,     3,      239,    "R/W",  0,      1,      0ull,   0},
13913         {"IA"                          ,        35,     5,      239,    "R/W",  0,      1,      0ull,   0},
13914         {"A"                           ,        40,     10,     239,    "R/W",  0,      1,      0ull,   0},
13915         {"SCR"                         ,        50,     2,      239,    "R/W",  0,      1,      0ull,   0},
13916         {"SIZE"                        ,        52,     3,      239,    "R/W",  0,      1,      0ull,   0},
13917         {"SOVR"                        ,        55,     1,      239,    "R/W",  0,      1,      0ull,   0},
13918         {"R"                           ,        56,     1,      239,    "R/W",  0,      1,      0ull,   0},
13919         {"OP"                          ,        57,     4,      239,    "R/W",  0,      1,      0ull,   0},
13920         {"EIA"                         ,        61,     1,      239,    "R/W",  0,      1,      0ull,   0},
13921         {"SLONLY"                      ,        62,     1,      239,    "R/W",  0,      1,      0ull,   0},
13922         {"V"                           ,        63,     1,      239,    "RC/W", 0,      1,      0ull,   0},
13923         {"D"                           ,        0,      32,     240,    "R/W",  0,      1,      0ull,   0},
13924         {"IA"                          ,        32,     8,      240,    "R/W",  0,      1,      0ull,   0},
13925         {"RESERVED_40_63"              ,        40,     24,     240,    "RAZ",  1,      1,      0,      0},
13926         {"D"                           ,        0,      32,     241,    "R/W",  1,      1,      0,      0},
13927         {"RESERVED_32_61"              ,        32,     30,     241,    "RAZ",  1,      1,      0,      0},
13928         {"V"                           ,        62,     2,      241,    "RC/W", 0,      1,      0ull,   0},
13929         {"DLH"                         ,        0,      8,      242,    "R/W",  0,      1,      0ull,   0},
13930         {"RESERVED_8_63"               ,        8,      56,     242,    "RAZ",  1,      1,      0,      0},
13931         {"DLL"                         ,        0,      8,      243,    "R/W",  0,      1,      0ull,   0},
13932         {"RESERVED_8_63"               ,        8,      56,     243,    "RAZ",  1,      1,      0,      0},
13933         {"FAR"                         ,        0,      1,      244,    "R/W",  0,      1,      0ull,   0},
13934         {"RESERVED_1_63"               ,        1,      63,     244,    "RAZ",  1,      1,      0,      0},
13935         {"EN"                          ,        0,      1,      245,    "WO",   0,      1,      0ull,   0},
13936         {"RXFR"                        ,        1,      1,      245,    "WO",   0,      1,      0ull,   0},
13937         {"TXFR"                        ,        2,      1,      245,    "WO",   0,      1,      0ull,   0},
13938         {"RESERVED_3_3"                ,        3,      1,      245,    "RAZ",  0,      1,      0ull,   0},
13939         {"TXTRIG"                      ,        4,      2,      245,    "WO",   0,      1,      0ull,   0},
13940         {"RXTRIG"                      ,        6,      2,      245,    "WO",   0,      1,      0ull,   0},
13941         {"RESERVED_8_63"               ,        8,      56,     245,    "RAZ",  1,      1,      0,      0},
13942         {"HTX"                         ,        0,      1,      246,    "R/W",  0,      1,      0ull,   0},
13943         {"RESERVED_1_63"               ,        1,      63,     246,    "RAZ",  1,      1,      0,      0},
13944         {"ERBFI"                       ,        0,      1,      247,    "R/W",  0,      1,      0ull,   0},
13945         {"ETBEI"                       ,        1,      1,      247,    "R/W",  0,      1,      0ull,   0},
13946         {"ELSI"                        ,        2,      1,      247,    "R/W",  0,      1,      0ull,   0},
13947         {"EDSSI"                       ,        3,      1,      247,    "R/W",  0,      1,      0ull,   0},
13948         {"RESERVED_4_6"                ,        4,      3,      247,    "RAZ",  0,      1,      0ull,   0},
13949         {"PTIME"                       ,        7,      1,      247,    "R/W",  0,      1,      0ull,   0},
13950         {"RESERVED_8_63"               ,        8,      56,     247,    "RAZ",  1,      1,      0,      0},
13951         {"IID"                         ,        0,      4,      248,    "RO",   0,      1,      1ull,   0},
13952         {"RESERVED_4_5"                ,        4,      2,      248,    "RAZ",  0,      1,      0ull,   0},
13953         {"FEN"                         ,        6,      2,      248,    "RO",   0,      1,      0ull,   0},
13954         {"RESERVED_8_63"               ,        8,      56,     248,    "RAZ",  1,      1,      0,      0},
13955         {"CLS"                         ,        0,      2,      249,    "R/W",  0,      1,      0ull,   0},
13956         {"STOP"                        ,        2,      1,      249,    "R/W",  0,      1,      0ull,   0},
13957         {"PEN"                         ,        3,      1,      249,    "R/W",  0,      1,      0ull,   0},
13958         {"EPS"                         ,        4,      1,      249,    "R/W",  0,      1,      0ull,   0},
13959         {"RESERVED_5_5"                ,        5,      1,      249,    "RAZ",  0,      1,      0ull,   0},
13960         {"BRK"                         ,        6,      1,      249,    "R/W",  0,      1,      0ull,   0},
13961         {"DLAB"                        ,        7,      1,      249,    "R/W",  0,      1,      0ull,   0},
13962         {"RESERVED_8_63"               ,        8,      56,     249,    "RAZ",  1,      1,      0,      0},
13963         {"DR"                          ,        0,      1,      250,    "RO",   0,      1,      0ull,   0},
13964         {"OE"                          ,        1,      1,      250,    "RC",   0,      1,      0ull,   0},
13965         {"PE"                          ,        2,      1,      250,    "RC",   0,      1,      0ull,   0},
13966         {"FE"                          ,        3,      1,      250,    "RC",   0,      1,      0ull,   0},
13967         {"BI"                          ,        4,      1,      250,    "RC",   0,      1,      0ull,   0},
13968         {"THRE"                        ,        5,      1,      250,    "RO",   0,      1,      1ull,   0},
13969         {"TEMT"                        ,        6,      1,      250,    "RO",   0,      1,      1ull,   0},
13970         {"FERR"                        ,        7,      1,      250,    "RC",   0,      1,      0ull,   0},
13971         {"RESERVED_8_63"               ,        8,      56,     250,    "RAZ",  1,      1,      0,      0},
13972         {"DTR"                         ,        0,      1,      251,    "R/W",  0,      1,      0ull,   0},
13973         {"RTS"                         ,        1,      1,      251,    "R/W",  0,      1,      0ull,   0},
13974         {"OUT1"                        ,        2,      1,      251,    "R/W",  0,      1,      0ull,   0},
13975         {"OUT2"                        ,        3,      1,      251,    "R/W",  0,      1,      0ull,   0},
13976         {"LOOP"                        ,        4,      1,      251,    "R/W",  0,      1,      0ull,   0},
13977         {"AFCE"                        ,        5,      1,      251,    "R/W",  0,      1,      0ull,   0},
13978         {"RESERVED_6_63"               ,        6,      58,     251,    "RAZ",  0,      1,      0ull,   0},
13979         {"DCTS"                        ,        0,      1,      252,    "RC",   0,      1,      0ull,   0},
13980         {"DDSR"                        ,        1,      1,      252,    "RC",   0,      1,      0ull,   0},
13981         {"TERI"                        ,        2,      1,      252,    "RC",   0,      1,      0ull,   0},
13982         {"DDCD"                        ,        3,      1,      252,    "RC",   0,      1,      0ull,   0},
13983         {"CTS"                         ,        4,      1,      252,    "RO",   1,      1,      0,      0},
13984         {"DSR"                         ,        5,      1,      252,    "RO",   0,      1,      0ull,   0},
13985         {"RI"                          ,        6,      1,      252,    "RO",   0,      1,      0ull,   0},
13986         {"DCD"                         ,        7,      1,      252,    "RO",   0,      1,      0ull,   0},
13987         {"RESERVED_8_63"               ,        8,      56,     252,    "RAZ",  1,      1,      0,      0},
13988         {"RBR"                         ,        0,      8,      253,    "RO",   0,      1,      0ull,   0},
13989         {"RESERVED_8_63"               ,        8,      56,     253,    "RAZ",  1,      1,      0,      0},
13990         {"RFL"                         ,        0,      7,      254,    "RO",   0,      1,      0ull,   0},
13991         {"RESERVED_7_63"               ,        7,      57,     254,    "RAZ",  1,      1,      0,      0},
13992         {"RFWD"                        ,        0,      8,      255,    "WO",   0,      1,      0ull,   0},
13993         {"RFPE"                        ,        8,      1,      255,    "WO",   0,      1,      0ull,   0},
13994         {"RFFE"                        ,        9,      1,      255,    "WO",   0,      1,      0ull,   0},
13995         {"RESERVED_10_63"              ,        10,     54,     255,    "RAZ",  1,      1,      0,      0},
13996         {"SBCR"                        ,        0,      1,      256,    "R/W",  0,      1,      0ull,   0},
13997         {"RESERVED_1_63"               ,        1,      63,     256,    "RAZ",  1,      1,      0,      0},
13998         {"SCR"                         ,        0,      8,      257,    "R/W",  0,      1,      0ull,   0},
13999         {"RESERVED_8_63"               ,        8,      56,     257,    "RAZ",  1,      1,      0,      0},
14000         {"SFE"                         ,        0,      1,      258,    "R/W",  0,      1,      0ull,   0},
14001         {"RESERVED_1_63"               ,        1,      63,     258,    "RAZ",  1,      1,      0,      0},
14002         {"USR"                         ,        0,      1,      259,    "WO",   0,      1,      0ull,   0},
14003         {"SRFR"                        ,        1,      1,      259,    "WO",   0,      1,      0ull,   0},
14004         {"STFR"                        ,        2,      1,      259,    "WO",   0,      1,      0ull,   0},
14005         {"RESERVED_3_63"               ,        3,      61,     259,    "RAZ",  1,      1,      0,      0},
14006         {"SRT"                         ,        0,      2,      260,    "R/W",  0,      1,      0ull,   0},
14007         {"RESERVED_2_63"               ,        2,      62,     260,    "RAZ",  1,      1,      0,      0},
14008         {"SRTS"                        ,        0,      1,      261,    "R/W",  0,      1,      0ull,   0},
14009         {"RESERVED_1_63"               ,        1,      63,     261,    "RAZ",  1,      1,      0,      0},
14010         {"STT"                         ,        0,      2,      262,    "R/W",  0,      1,      0ull,   0},
14011         {"RESERVED_2_63"               ,        2,      62,     262,    "RAZ",  1,      1,      0,      0},
14012         {"TFL"                         ,        0,      7,      263,    "RO",   0,      1,      0ull,   0},
14013         {"RESERVED_7_63"               ,        7,      57,     263,    "RAZ",  1,      1,      0,      0},
14014         {"TFR"                         ,        0,      8,      264,    "RO",   0,      1,      0ull,   0},
14015         {"RESERVED_8_63"               ,        8,      56,     264,    "RAZ",  1,      1,      0,      0},
14016         {"THR"                         ,        0,      8,      265,    "WO",   0,      1,      0ull,   0},
14017         {"RESERVED_8_63"               ,        8,      56,     265,    "RAZ",  1,      1,      0,      0},
14018         {"BUSY"                        ,        0,      1,      266,    "RO",   0,      1,      0ull,   0},
14019         {"TFNF"                        ,        1,      1,      266,    "RO",   0,      1,      1ull,   0},
14020         {"TFE"                         ,        2,      1,      266,    "RO",   0,      1,      1ull,   0},
14021         {"RFNE"                        ,        3,      1,      266,    "RO",   0,      1,      0ull,   0},
14022         {"RFF"                         ,        4,      1,      266,    "RO",   0,      1,      0ull,   0},
14023         {"RESERVED_5_63"               ,        5,      59,     266,    "RAZ",  1,      1,      0,      0},
14024         {"ENABLE"                      ,        0,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
14025         {"IDLELO"                      ,        1,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
14026         {"CLK_CONT"                    ,        2,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
14027         {"WIREOR"                      ,        3,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
14028         {"LSBFIRST"                    ,        4,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
14029         {"INT_ENA"                     ,        5,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
14030         {"CSENA"                       ,        6,      1,      267,    "R/W",  0,      0,      0ull,   1ull},
14031         {"CSHI"                        ,        7,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
14032         {"IDLECLKS"                    ,        8,      2,      267,    "R/W",  0,      0,      0ull,   0ull},
14033         {"TRITX"                       ,        10,     1,      267,    "R/W",  0,      0,      0ull,   0ull},
14034         {"CSLATE"                      ,        11,     1,      267,    "R/W",  0,      0,      0ull,   0ull},
14035         {"RESERVED_12_15"              ,        12,     4,      267,    "RAZ",  1,      1,      0,      0},
14036         {"CLKDIV"                      ,        16,     13,     267,    "R/W",  0,      0,      0ull,   0ull},
14037         {"RESERVED_29_63"              ,        29,     35,     267,    "RAZ",  1,      1,      0,      0},
14038         {"DATA"                        ,        0,      8,      268,    "R/W",  1,      1,      0,      0},
14039         {"RESERVED_8_63"               ,        8,      56,     268,    "RAZ",  1,      1,      0,      0},
14040         {"BUSY"                        ,        0,      1,      269,    "RO",   0,      0,      0ull,   0ull},
14041         {"RESERVED_1_7"                ,        1,      7,      269,    "RAZ",  1,      1,      0,      0},
14042         {"RXNUM"                       ,        8,      5,      269,    "RO",   0,      0,      0ull,   0ull},
14043         {"RESERVED_13_63"              ,        13,     51,     269,    "RAZ",  1,      1,      0,      0},
14044         {"TOTNUM"                      ,        0,      5,      270,    "WO",   1,      0,      0,      2ull},
14045         {"RESERVED_5_7"                ,        5,      3,      270,    "RAZ",  1,      1,      0,      0},
14046         {"TXNUM"                       ,        8,      5,      270,    "WO",   1,      0,      0,      1ull},
14047         {"RESERVED_13_15"              ,        13,     3,      270,    "RAZ",  1,      1,      0,      0},
14048         {"LEAVECS"                     ,        16,     1,      270,    "WO",   1,      0,      0,      0ull},
14049         {"RESERVED_17_63"              ,        17,     47,     270,    "RAZ",  1,      1,      0,      0},
14050         {"RESERVED_0_2"                ,        0,      3,      271,    "RAZ",  1,      1,      0,      0},
14051         {"BADDR"                       ,        3,      61,     271,    "R/W",  0,      1,      0ull,   0},
14052         {"RESERVED_0_2"                ,        0,      3,      272,    "RAZ",  1,      1,      0,      0},
14053         {"BADDR"                       ,        3,      61,     272,    "R/W",  0,      1,      0ull,   0},
14054         {"DPI_BS"                      ,        0,      1,      273,    "RO",   0,      0,      0ull,   0ull},
14055         {"PDF_BS"                      ,        1,      1,      273,    "RO",   0,      0,      0ull,   0ull},
14056         {"DOB_BS"                      ,        2,      1,      273,    "RO",   0,      0,      0ull,   0ull},
14057         {"NUS_BS"                      ,        3,      1,      273,    "RO",   0,      0,      0ull,   0ull},
14058         {"POS_BS"                      ,        4,      1,      273,    "RO",   0,      0,      0ull,   0ull},
14059         {"RESERVED_5_7"                ,        5,      3,      273,    "RAZ",  1,      1,      0,      0},
14060         {"POF0_BS"                     ,        8,      1,      273,    "RO",   0,      0,      0ull,   0ull},
14061         {"PIG_BS"                      ,        9,      1,      273,    "RO",   0,      0,      0ull,   0ull},
14062         {"PGF_BS"                      ,        10,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14063         {"RDNL_BS"                     ,        11,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14064         {"PCAD_BS"                     ,        12,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14065         {"PCAC_BS"                     ,        13,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14066         {"RDN_BS"                      ,        14,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14067         {"PCN_BS"                      ,        15,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14068         {"PCNC_BS"                     ,        16,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14069         {"RDP_BS"                      ,        17,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14070         {"DIF_BS"                      ,        18,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14071         {"CSR_BS"                      ,        19,     1,      273,    "RO",   0,      0,      0ull,   0ull},
14072         {"RESERVED_20_63"              ,        20,     44,     273,    "RAZ",  1,      1,      0,      0},
14073         {"BSIZE"                       ,        0,      16,     274,    "R/W",  0,      1,      1024ull,        0},
14074         {"ISIZE"                       ,        16,     7,      274,    "R/W",  0,      1,      0ull,   0},
14075         {"RESERVED_23_63"              ,        23,     41,     274,    "RAZ",  1,      1,      0,      0},
14076         {"TIMER"                       ,        0,      10,     275,    "R/W",  0,      0,      0ull,   50ull},
14077         {"RESERVED_10_31"              ,        10,     22,     275,    "RAZ",  0,      0,      0ull,   0ull},
14078         {"MAX_WORD"                    ,        32,     5,      275,    "R/W",  0,      0,      2ull,   0ull},
14079         {"RESERVED_37_39"              ,        37,     3,      275,    "RAZ",  0,      0,      0ull,   0ull},
14080         {"WAIT_COM"                    ,        40,     1,      275,    "R/W",  0,      0,      0ull,   1ull},
14081         {"PCI_WDIS"                    ,        41,     1,      275,    "R/W",  0,      0,      0ull,   0ull},
14082         {"INS0_64B"                    ,        42,     1,      275,    "R/W",  0,      1,      0ull,   0},
14083         {"RESERVED_43_45"              ,        43,     3,      275,    "RAZ",  0,      0,      0ull,   0ull},
14084         {"INS0_ENB"                    ,        46,     1,      275,    "R/W",  0,      0,      0ull,   1ull},
14085         {"RESERVED_47_49"              ,        47,     3,      275,    "RAZ",  0,      0,      0ull,   0ull},
14086         {"OUT0_ENB"                    ,        50,     1,      275,    "R/W",  0,      0,      0ull,   1ull},
14087         {"RESERVED_51_53"              ,        51,     3,      275,    "RAZ",  0,      0,      0ull,   0ull},
14088         {"DIS_PNIW"                    ,        54,     1,      275,    "R/W",  0,      0,      0ull,   1ull},
14089         {"CHIP_REV"                    ,        55,     8,      275,    "RO",   1,      1,      0,      0},
14090         {"RESERVED_63_63"              ,        63,     1,      275,    "RAZ",  1,      1,      0,      0},
14091         {"DBG_SEL"                     ,        0,      16,     276,    "R/W",  0,      1,      0ull,   0},
14092         {"RESERVED_16_63"              ,        16,     48,     276,    "RAZ",  1,      1,      0,      0},
14093         {"CSIZE"                       ,        0,      14,     277,    "R/W",  0,      1,      0ull,   0},
14094         {"LP_ENB"                      ,        14,     1,      277,    "R/W",  0,      0,      0ull,   1ull},
14095         {"HP_ENB"                      ,        15,     1,      277,    "R/W",  0,      0,      0ull,   1ull},
14096         {"O_MODE"                      ,        16,     1,      277,    "R/W",  0,      0,      0ull,   1ull},
14097         {"O_ES"                        ,        17,     2,      277,    "R/W",  0,      1,      0ull,   0},
14098         {"O_NS"                        ,        19,     1,      277,    "R/W",  0,      1,      0ull,   0},
14099         {"O_RO"                        ,        20,     1,      277,    "R/W",  0,      1,      0ull,   0},
14100         {"O_ADD1"                      ,        21,     1,      277,    "R/W",  0,      0,      0ull,   1ull},
14101         {"FPA_QUE"                     ,        22,     3,      277,    "R/W",  0,      1,      0ull,   0},
14102         {"DWB_ICHK"                    ,        25,     9,      277,    "R/W",  0,      1,      0ull,   0},
14103         {"DWB_DENB"                    ,        34,     1,      277,    "R/W",  0,      0,      0ull,   1ull},
14104         {"B0_LEND"                     ,        35,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
14105         {"RESERVED_36_63"              ,        36,     28,     277,    "RAZ",  1,      1,      0,      0},
14106         {"DBELL"                       ,        0,      32,     278,    "RO",   0,      0,      0ull,   0ull},
14107         {"FCNT"                        ,        32,     7,      278,    "RO",   0,      0,      0ull,   0ull},
14108         {"RESERVED_39_63"              ,        39,     25,     278,    "RAZ",  1,      1,      0,      0},
14109         {"ADDR"                        ,        0,      36,     279,    "RO",   0,      1,      0ull,   0},
14110         {"STATE"                       ,        36,     4,      279,    "RO",   0,      0,      0ull,   0ull},
14111         {"RESERVED_40_63"              ,        40,     24,     279,    "RAZ",  1,      1,      0,      0},
14112         {"DBELL"                       ,        0,      32,     280,    "RO",   0,      0,      0ull,   0ull},
14113         {"FCNT"                        ,        32,     7,      280,    "RO",   0,      0,      0ull,   0ull},
14114         {"RESERVED_39_63"              ,        39,     25,     280,    "RAZ",  1,      1,      0,      0},
14115         {"ADDR"                        ,        0,      36,     281,    "RO",   0,      1,      0ull,   0},
14116         {"STATE"                       ,        36,     4,      281,    "RO",   0,      0,      0ull,   0ull},
14117         {"RESERVED_40_63"              ,        40,     24,     281,    "RAZ",  1,      1,      0,      0},
14118         {"DBELL"                       ,        0,      16,     282,    "R/W",  0,      1,      0ull,   0},
14119         {"RESERVED_16_63"              ,        16,     48,     282,    "RAZ",  1,      1,      0,      0},
14120         {"SADDR"                       ,        0,      36,     283,    "R/W",  0,      1,      0ull,   0},
14121         {"RESERVED_36_63"              ,        36,     28,     283,    "RAZ",  1,      1,      0,      0},
14122         {"ROR"                         ,        0,      1,      284,    "R/W",  0,      1,      0ull,   0},
14123         {"ESR"                         ,        1,      2,      284,    "R/W",  0,      1,      0ull,   0},
14124         {"NSR"                         ,        3,      1,      284,    "R/W",  0,      1,      0ull,   0},
14125         {"USE_CSR"                     ,        4,      1,      284,    "R/W",  0,      0,      0ull,   1ull},
14126         {"D_ROR"                       ,        5,      1,      284,    "R/W",  0,      1,      0ull,   0},
14127         {"D_ESR"                       ,        6,      2,      284,    "R/W",  0,      1,      0ull,   0},
14128         {"D_NSR"                       ,        8,      1,      284,    "R/W",  0,      1,      0ull,   0},
14129         {"PBP_DHI"                     ,        9,      13,     284,    "R/W",  0,      1,      0ull,   0},
14130         {"RESERVED_22_63"              ,        22,     42,     284,    "RAZ",  1,      1,      0,      0},
14131         {"RML_RTO"                     ,        0,      1,      285,    "R/W",  0,      0,      0ull,   1ull},
14132         {"RML_WTO"                     ,        1,      1,      285,    "R/W",  0,      0,      0ull,   1ull},
14133         {"PCI_RSL"                     ,        2,      1,      285,    "R/W",  0,      0,      0ull,   1ull},
14134         {"PO0_2SML"                    ,        3,      1,      285,    "R/W",  0,      0,      0ull,   1ull},
14135         {"RESERVED_4_6"                ,        4,      3,      285,    "RAZ",  0,      0,      0ull,   1ull},
14136         {"I0_RTOUT"                    ,        7,      1,      285,    "R/W",  0,      0,      0ull,   1ull},
14137         {"RESERVED_8_10"               ,        8,      3,      285,    "RAZ",  0,      0,      0ull,   1ull},
14138         {"I0_OVERF"                    ,        11,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14139         {"RESERVED_12_14"              ,        12,     3,      285,    "RAZ",  0,      0,      0ull,   1ull},
14140         {"P0_RTOUT"                    ,        15,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14141         {"RESERVED_16_18"              ,        16,     3,      285,    "RAZ",  0,      0,      0ull,   1ull},
14142         {"P0_PERR"                     ,        19,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14143         {"RESERVED_20_22"              ,        20,     3,      285,    "RAZ",  0,      0,      0ull,   1ull},
14144         {"G0_RTOUT"                    ,        23,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14145         {"RESERVED_24_26"              ,        24,     3,      285,    "RAZ",  0,      0,      0ull,   1ull},
14146         {"P0_PPERR"                    ,        27,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14147         {"RESERVED_28_30"              ,        28,     3,      285,    "RAZ",  0,      0,      0ull,   1ull},
14148         {"P0_PTOUT"                    ,        31,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14149         {"RESERVED_32_34"              ,        32,     3,      285,    "RAZ",  0,      0,      0ull,   1ull},
14150         {"I0_PPERR"                    ,        35,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14151         {"RESERVED_36_38"              ,        36,     3,      285,    "RAZ",  0,      0,      0ull,   1ull},
14152         {"WIN_RTO"                     ,        39,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14153         {"P_DPERR"                     ,        40,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14154         {"IOBDMA"                      ,        41,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14155         {"FCR_S_E"                     ,        42,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14156         {"FCR_A_F"                     ,        43,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14157         {"PCR_S_E"                     ,        44,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14158         {"PCR_A_F"                     ,        45,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14159         {"Q2_S_E"                      ,        46,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14160         {"Q2_A_F"                      ,        47,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14161         {"Q3_S_E"                      ,        48,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14162         {"Q3_A_F"                      ,        49,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14163         {"COM_S_E"                     ,        50,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14164         {"COM_A_F"                     ,        51,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14165         {"PNC_S_E"                     ,        52,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14166         {"PNC_A_F"                     ,        53,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14167         {"RWX_S_E"                     ,        54,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14168         {"RDX_S_E"                     ,        55,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14169         {"PCF_P_E"                     ,        56,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14170         {"PCF_P_F"                     ,        57,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14171         {"PDF_P_E"                     ,        58,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14172         {"PDF_P_F"                     ,        59,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14173         {"Q1_S_E"                      ,        60,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14174         {"Q1_A_F"                      ,        61,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
14175         {"RESERVED_62_63"              ,        62,     2,      285,    "RAZ",  1,      1,      0,      0},
14176         {"RML_RTO"                     ,        0,      1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14177         {"RML_WTO"                     ,        1,      1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14178         {"PCI_RSL"                     ,        2,      1,      286,    "RO",   0,      0,      0ull,   0ull},
14179         {"PO0_2SML"                    ,        3,      1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14180         {"RESERVED_4_6"                ,        4,      3,      286,    "RAZ",  0,      0,      0ull,   0ull},
14181         {"I0_RTOUT"                    ,        7,      1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14182         {"RESERVED_8_10"               ,        8,      3,      286,    "RAZ",  0,      0,      0ull,   0ull},
14183         {"I0_OVERF"                    ,        11,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14184         {"RESERVED_12_14"              ,        12,     3,      286,    "RAZ",  0,      0,      0ull,   0ull},
14185         {"P0_RTOUT"                    ,        15,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14186         {"RESERVED_16_18"              ,        16,     3,      286,    "RAZ",  0,      0,      0ull,   0ull},
14187         {"P0_PERR"                     ,        19,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14188         {"RESERVED_20_22"              ,        20,     3,      286,    "RAZ",  0,      0,      0ull,   0ull},
14189         {"G0_RTOUT"                    ,        23,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14190         {"RESERVED_24_26"              ,        24,     3,      286,    "RAZ",  0,      0,      0ull,   0ull},
14191         {"P0_PPERR"                    ,        27,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14192         {"RESERVED_28_30"              ,        28,     3,      286,    "RAZ",  0,      0,      0ull,   0ull},
14193         {"P0_PTOUT"                    ,        31,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14194         {"RESERVED_32_34"              ,        32,     3,      286,    "RAZ",  0,      0,      0ull,   0ull},
14195         {"I0_PPERR"                    ,        35,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14196         {"RESERVED_36_38"              ,        36,     3,      286,    "RAZ",  0,      0,      0ull,   0ull},
14197         {"WIN_RTO"                     ,        39,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14198         {"P_DPERR"                     ,        40,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14199         {"IOBDMA"                      ,        41,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14200         {"FCR_S_E"                     ,        42,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14201         {"FCR_A_F"                     ,        43,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14202         {"PCR_S_E"                     ,        44,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14203         {"PCR_A_F"                     ,        45,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14204         {"Q2_S_E"                      ,        46,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14205         {"Q2_A_F"                      ,        47,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14206         {"Q3_S_E"                      ,        48,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14207         {"Q3_A_F"                      ,        49,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14208         {"COM_S_E"                     ,        50,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14209         {"COM_A_F"                     ,        51,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14210         {"PNC_S_E"                     ,        52,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14211         {"PNC_A_F"                     ,        53,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14212         {"RWX_S_E"                     ,        54,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14213         {"RDX_S_E"                     ,        55,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14214         {"PCF_P_E"                     ,        56,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14215         {"PCF_P_F"                     ,        57,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14216         {"PDF_P_E"                     ,        58,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14217         {"PDF_P_F"                     ,        59,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14218         {"Q1_S_E"                      ,        60,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14219         {"Q1_A_F"                      ,        61,     1,      286,    "R/W1C",        0,      0,      0ull,   0ull},
14220         {"RESERVED_62_63"              ,        62,     2,      286,    "RAZ",  1,      1,      0,      0},
14221         {"DBELL"                       ,        0,      16,     287,    "R/W",  0,      1,      0ull,   0},
14222         {"RESERVED_16_63"              ,        16,     48,     287,    "RAZ",  1,      1,      0,      0},
14223         {"SADDR"                       ,        0,      36,     288,    "R/W",  0,      1,      0ull,   0},
14224         {"RESERVED_36_63"              ,        36,     28,     288,    "RAZ",  1,      1,      0,      0},
14225         {"BA"                          ,        0,      28,     289,    "R/W",  0,      1,      0ull,   0},
14226         {"ROW"                         ,        28,     1,      289,    "R/W",  0,      1,      0ull,   0},
14227         {"ROR"                         ,        29,     1,      289,    "R/W",  0,      1,      0ull,   0},
14228         {"NSW"                         ,        30,     1,      289,    "R/W",  0,      1,      0ull,   0},
14229         {"NSR"                         ,        31,     1,      289,    "R/W",  0,      1,      0ull,   0},
14230         {"ESW"                         ,        32,     2,      289,    "R/W",  0,      1,      0ull,   0},
14231         {"ESR"                         ,        34,     2,      289,    "R/W",  0,      1,      0ull,   0},
14232         {"NMERGE"                      ,        36,     1,      289,    "R/W",  0,      1,      0ull,   0},
14233         {"SHORTL"                      ,        37,     1,      289,    "R/W",  0,      1,      0ull,   0},
14234         {"RESERVED_38_63"              ,        38,     26,     289,    "RAZ",  1,      1,      0,      0},
14235         {"INT_VEC"                     ,        0,      64,     290,    "R/W1C",        0,      0,      0ull,   0ull},
14236         {"SIZE"                        ,        0,      32,     291,    "R/W",  0,      1,      0ull,   0},
14237         {"RESERVED_32_63"              ,        32,     32,     291,    "RAZ",  1,      1,      0,      0},
14238         {"ROR_SL0"                     ,        0,      1,      292,    "R/W",  0,      1,      0ull,   0},
14239         {"NSR_SL0"                     ,        1,      1,      292,    "R/W",  0,      1,      0ull,   0},
14240         {"ESR_SL0"                     ,        2,      2,      292,    "R/W",  0,      1,      0ull,   0},
14241         {"RESERVED_4_15"               ,        4,      12,     292,    "RAZ",  0,      0,      0ull,   0ull},
14242         {"IPTR_O0"                     ,        16,     1,      292,    "R/W",  0,      0,      0ull,   1ull},
14243         {"RESERVED_17_23"              ,        17,     7,      292,    "RAZ",  0,      0,      0ull,   0ull},
14244         {"O0_CSRM"                     ,        24,     1,      292,    "R/W",  0,      0,      0ull,   1ull},
14245         {"RESERVED_25_27"              ,        25,     3,      292,    "RAZ",  0,      0,      0ull,   0ull},
14246         {"O0_RO"                       ,        28,     1,      292,    "R/W",  0,      1,      0ull,   0},
14247         {"O0_NS"                       ,        29,     1,      292,    "R/W",  0,      1,      0ull,   0},
14248         {"O0_ES"                       ,        30,     2,      292,    "R/W",  0,      1,      0ull,   0},
14249         {"RESERVED_32_43"              ,        32,     12,     292,    "RAZ",  0,      0,      0ull,   0ull},
14250         {"P0_BMODE"                    ,        44,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
14251         {"RESERVED_45_63"              ,        45,     19,     292,    "RAZ",  0,      0,      0ull,   0ull},
14252         {"NADDR"                       ,        0,      61,     293,    "RO",   0,      1,      0ull,   0},
14253         {"STATE"                       ,        61,     2,      293,    "RO",   0,      0,      0ull,   0ull},
14254         {"RESERVED_63_63"              ,        63,     1,      293,    "RAZ",  1,      1,      0,      0},
14255         {"NADDR"                       ,        0,      61,     294,    "RO",   0,      1,      0ull,   0},
14256         {"STATE"                       ,        61,     3,      294,    "RO",   0,      0,      0ull,   0ull},
14257         {"AVAIL"                       ,        0,      32,     295,    "RO",   0,      0,      0ull,   0ull},
14258         {"FCNT"                        ,        32,     6,      295,    "RO",   0,      0,      0ull,   0ull},
14259         {"RESERVED_38_63"              ,        38,     26,     295,    "RAZ",  1,      1,      0,      0},
14260         {"AVAIL"                       ,        0,      32,     296,    "RO",   0,      0,      0ull,   0ull},
14261         {"FCNT"                        ,        32,     5,      296,    "RO",   0,      0,      0ull,   0ull},
14262         {"RESERVED_37_63"              ,        37,     27,     296,    "RAZ",  1,      1,      0,      0},
14263         {"RD_BRST"                     ,        0,      7,      297,    "R/W",  0,      0,      17ull,  64ull},
14264         {"WR_BRST"                     ,        7,      7,      297,    "R/W",  0,      0,      16ull,  64ull},
14265         {"RESERVED_14_63"              ,        14,     50,     297,    "RAZ",  1,      1,      0,      0},
14266         {"PARK_DEV"                    ,        0,      3,      298,    "R/W",  0,      1,      0ull,   0},
14267         {"PARK_MOD"                    ,        3,      1,      298,    "R/W",  0,      1,      0ull,   0},
14268         {"EN"                          ,        4,      1,      298,    "R/W",  0,      1,      0ull,   0},
14269         {"RESERVED_5_63"               ,        5,      59,     298,    "RAZ",  1,      1,      0,      0},
14270         {"CMD_SIZE"                    ,        0,      11,     299,    "R/W",  0,      0,      9ull,   9ull},
14271         {"RESERVED_11_63"              ,        11,     53,     299,    "RAZ",  1,      1,      0,      0},
14272         {"RSV_A"                       ,        0,      6,      300,    "R/W",  0,      1,      0ull,   0},
14273         {"SKP_LEN"                     ,        6,      7,      300,    "R/W",  0,      1,      0ull,   0},
14274         {"RSV_B"                       ,        13,     1,      300,    "R/W",  0,      1,      0ull,   0},
14275         {"PAR_MODE"                    ,        14,     2,      300,    "R/W",  0,      1,      0ull,   0},
14276         {"RSV_C"                       ,        16,     5,      300,    "R/W",  0,      1,      0ull,   0},
14277         {"USE_IHDR"                    ,        21,     1,      300,    "R/W",  0,      1,      0ull,   0},
14278         {"RSV_D"                       ,        22,     6,      300,    "R/W",  0,      1,      0ull,   0},
14279         {"RSKP_LEN"                    ,        28,     7,      300,    "R/W",  0,      1,      8ull,   0},
14280         {"RSV_E"                       ,        35,     1,      300,    "R/W",  0,      1,      0ull,   0},
14281         {"RPARMODE"                    ,        36,     2,      300,    "R/W",  0,      1,      0ull,   0},
14282         {"RSV_F"                       ,        38,     5,      300,    "R/W",  0,      1,      0ull,   0},
14283         {"PBP"                         ,        43,     1,      300,    "R/W",  0,      1,      0ull,   0},
14284         {"RESERVED_44_63"              ,        44,     20,     300,    "RAZ",  1,      1,      0,      0},
14285         {"ENB"                         ,        0,      4,      301,    "R/W",  0,      0,      15ull,  15ull},
14286         {"BP_ON"                       ,        4,      4,      301,    "RO",   0,      0,      0ull,   0ull},
14287         {"RESERVED_8_63"               ,        8,      56,     301,    "RAZ",  1,      1,      0,      0},
14288         {"MIO"                         ,        0,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14289         {"GMX0"                        ,        1,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14290         {"GMX1"                        ,        2,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14291         {"NPI"                         ,        3,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14292         {"KEY"                         ,        4,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14293         {"FPA"                         ,        5,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14294         {"DFA"                         ,        6,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14295         {"ZIP"                         ,        7,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14296         {"RINT_8"                      ,        8,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14297         {"IPD"                         ,        9,      1,      302,    "RO",   0,      0,      0ull,   0ull},
14298         {"PKO"                         ,        10,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14299         {"TIM"                         ,        11,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14300         {"POW"                         ,        12,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14301         {"USB"                         ,        13,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14302         {"RINT_14"                     ,        14,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14303         {"RINT_15"                     ,        15,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14304         {"L2C"                         ,        16,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14305         {"LMC"                         ,        17,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14306         {"SPX0"                        ,        18,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14307         {"SPX1"                        ,        19,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14308         {"PIP"                         ,        20,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14309         {"RINT_21"                     ,        21,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14310         {"ASX0"                        ,        22,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14311         {"ASX1"                        ,        23,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14312         {"RINT_24"                     ,        24,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14313         {"RINT_25"                     ,        25,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14314         {"RINT_26"                     ,        26,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14315         {"RINT_27"                     ,        27,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14316         {"RINT_28"                     ,        28,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14317         {"RINT_29"                     ,        29,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14318         {"IOB"                         ,        30,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14319         {"RINT_31"                     ,        31,     1,      302,    "RO",   0,      0,      0ull,   0ull},
14320         {"RESERVED_32_63"              ,        32,     32,     302,    "RAZ",  1,      1,      0,      0},
14321         {"SIZE"                        ,        0,      32,     303,    "R/W",  0,      1,      0ull,   0},
14322         {"RESERVED_32_63"              ,        32,     32,     303,    "RAZ",  1,      1,      0,      0},
14323         {"TIME"                        ,        0,      32,     304,    "R/W",  0,      0,      0ull,   131072ull},
14324         {"RESERVED_32_63"              ,        32,     32,     304,    "RAZ",  1,      1,      0,      0},
14325         {"ADDR_V"                      ,        0,      1,      305,    "R/W",  0,      1,      0ull,   0},
14326         {"END_SWP"                     ,        1,      2,      305,    "R/W",  0,      1,      0ull,   0},
14327         {"CA"                          ,        3,      1,      305,    "R/W",  0,      0,      0ull,   0ull},
14328         {"ADDR_IDX"                    ,        4,      14,     305,    "R/W",  0,      1,      0ull,   0},
14329         {"RESERVED_18_31"              ,        18,     14,     305,    "RAZ",  1,      1,      0,      0},
14330         {"VENDID"                      ,        0,      16,     306,    "RO",   0,      0,      6013ull,        6013ull},
14331         {"DEVID"                       ,        16,     16,     306,    "RO",   0,      0,      48ull,  48ull},
14332         {"ISAE"                        ,        0,      1,      307,    "RO",   0,      0,      0ull,   0ull},
14333         {"MSAE"                        ,        1,      1,      307,    "R/W",  0,      0,      0ull,   1ull},
14334         {"ME"                          ,        2,      1,      307,    "R/W",  0,      0,      0ull,   1ull},
14335         {"SCSE"                        ,        3,      1,      307,    "RO",   0,      0,      0ull,   0ull},
14336         {"MWICE"                       ,        4,      1,      307,    "R/W",  0,      0,      0ull,   0ull},
14337         {"VPS"                         ,        5,      1,      307,    "RO",   0,      0,      0ull,   0ull},
14338         {"PEE"                         ,        6,      1,      307,    "R/W",  0,      0,      0ull,   1ull},
14339         {"ADS"                         ,        7,      1,      307,    "RO",   0,      0,      0ull,   0ull},
14340         {"SEE"                         ,        8,      1,      307,    "R/W",  0,      0,      0ull,   1ull},
14341         {"FBBE"                        ,        9,      1,      307,    "R/W",  0,      0,      0ull,   1ull},
14342         {"I_DIS"                       ,        10,     1,      307,    "R/W",  0,      0,      0ull,   0ull},
14343         {"RESERVED_11_18"              ,        11,     8,      307,    "RAZ",  1,      1,      0,      0},
14344         {"I_STAT"                      ,        19,     1,      307,    "RO",   0,      0,      0ull,   0ull},
14345         {"CLE"                         ,        20,     1,      307,    "RO",   0,      0,      1ull,   1ull},
14346         {"M66"                         ,        21,     1,      307,    "RO",   0,      0,      1ull,   1ull},
14347         {"RESERVED_22_22"              ,        22,     1,      307,    "RAZ",  1,      1,      0,      0},
14348         {"FBB"                         ,        23,     1,      307,    "RO",   0,      1,      1ull,   0},
14349         {"MDPE"                        ,        24,     1,      307,    "R/W1C",        0,      0,      0ull,   0ull},
14350         {"DEVT"                        ,        25,     2,      307,    "RO",   0,      0,      1ull,   1ull},
14351         {"STA"                         ,        27,     1,      307,    "R/W1C",        0,      0,      0ull,   0ull},
14352         {"RTA"                         ,        28,     1,      307,    "R/W1C",        0,      0,      0ull,   0ull},
14353         {"RMA"                         ,        29,     1,      307,    "R/W1C",        0,      0,      0ull,   0ull},
14354         {"SSE"                         ,        30,     1,      307,    "R/W1C",        0,      0,      0ull,   0ull},
14355         {"DPE"                         ,        31,     1,      307,    "R/W1C",        0,      0,      0ull,   0ull},
14356         {"RID"                         ,        0,      8,      308,    "RO",   0,      0,      0ull,   0ull},
14357         {"CC"                          ,        8,      24,     308,    "RO",   0,      0,      733184ull,      733184ull},
14358         {"CLS"                         ,        0,      8,      309,    "R/W",  0,      1,      0ull,   0},
14359         {"LT"                          ,        8,      8,      309,    "R/W",  0,      0,      0ull,   64ull},
14360         {"HT"                          ,        16,     8,      309,    "RO",   0,      0,      0ull,   0ull},
14361         {"BCOD"                        ,        24,     4,      309,    "RO",   0,      0,      0ull,   0ull},
14362         {"RESERVED_28_29"              ,        28,     2,      309,    "RAZ",  1,      1,      0,      0},
14363         {"BRB"                         ,        30,     1,      309,    "R/W",  0,      0,      0ull,   0ull},
14364         {"BCAP"                        ,        31,     1,      309,    "RO",   0,      0,      0ull,   0ull},
14365         {"MSPC"                        ,        0,      1,      310,    "RO",   0,      0,      0ull,   0ull},
14366         {"TYP"                         ,        1,      2,      310,    "RO",   0,      0,      2ull,   2ull},
14367         {"PF"                          ,        3,      1,      310,    "RO",   0,      0,      1ull,   1ull},
14368         {"LBASEZ"                      ,        4,      8,      310,    "RO",   0,      0,      0ull,   0ull},
14369         {"LBASE"                       ,        12,     20,     310,    "R/W",  0,      1,      0ull,   0},
14370         {"HBASE"                       ,        0,      32,     311,    "R/W",  0,      1,      0ull,   0},
14371         {"MSPC"                        ,        0,      1,      312,    "RO",   0,      0,      0ull,   0ull},
14372         {"TYP"                         ,        1,      2,      312,    "RO",   0,      0,      2ull,   2ull},
14373         {"PF"                          ,        3,      1,      312,    "RO",   0,      0,      1ull,   1ull},
14374         {"LBASEZ"                      ,        4,      23,     312,    "RO",   0,      0,      0ull,   0ull},
14375         {"LBASE"                       ,        27,     5,      312,    "R/W",  0,      1,      0ull,   0},
14376         {"HBASE"                       ,        0,      32,     313,    "R/W",  0,      1,      0ull,   0},
14377         {"MSPC"                        ,        0,      1,      314,    "RO",   0,      0,      0ull,   0ull},
14378         {"TYP"                         ,        1,      2,      314,    "RO",   0,      0,      2ull,   2ull},
14379         {"PF"                          ,        3,      1,      314,    "RO",   0,      0,      1ull,   1ull},
14380         {"LBASEZ"                      ,        4,      28,     314,    "RO",   0,      0,      0ull,   0ull},
14381         {"HBASEZ"                      ,        0,      7,      315,    "RO",   0,      0,      0ull,   0ull},
14382         {"HBASE"                       ,        7,      25,     315,    "R/W",  0,      1,      0ull,   0},
14383         {"CISP"                        ,        0,      32,     316,    "RO",   0,      0,      0ull,   0ull},
14384         {"SSVID"                       ,        0,      16,     317,    "RO",   0,      0,      6013ull,        6013ull},
14385         {"SSID"                        ,        16,     16,     317,    "RO",   0,      0,      1ull,   1ull},
14386         {"ERBAR_EN"                    ,        0,      1,      318,    "R/W",  0,      0,      0ull,   0ull},
14387         {"RESERVED_1_10"               ,        1,      10,     318,    "RAZ",  1,      1,      0,      0},
14388         {"ERBARZ"                      ,        11,     5,      318,    "RO",   0,      0,      0ull,   0ull},
14389         {"ERBAR"                       ,        16,     16,     318,    "R/W",  0,      1,      0ull,   0},
14390         {"CP"                          ,        0,      8,      319,    "RO",   0,      0,      224ull, 224ull},
14391         {"RESERVED_8_31"               ,        8,      24,     319,    "RAZ",  1,      1,      0,      0},
14392         {"IL"                          ,        0,      8,      320,    "R/W",  0,      1,      0ull,   0},
14393         {"INTA"                        ,        8,      8,      320,    "RO",   0,      0,      1ull,   1ull},
14394         {"MG"                          ,        16,     8,      320,    "RO",   0,      0,      64ull,  64ull},
14395         {"ML"                          ,        24,     8,      320,    "RO",   0,      0,      64ull,  64ull},
14396         {"MLTD"                        ,        0,      1,      321,    "R/W",  0,      0,      0ull,   1ull},
14397         {"TSWC"                        ,        1,      1,      321,    "R/W",  0,      0,      0ull,   0ull},
14398         {"RESERVED_2_2"                ,        2,      1,      321,    "RAZ",  1,      1,      0,      0},
14399         {"DPPMR"                       ,        3,      1,      321,    "R/W",  0,      0,      0ull,   0ull},
14400         {"PBE"                         ,        4,      12,     321,    "R/W",  0,      0,      0ull,   0ull},
14401         {"TILT"                        ,        16,     4,      321,    "R/W",  0,      0,      0ull,   0ull},
14402         {"TSLTE"                       ,        20,     3,      321,    "R/W",  0,      0,      0ull,   0ull},
14403         {"TMAE"                        ,        23,     1,      321,    "R/W",  0,      0,      0ull,   0ull},
14404         {"TWTAE"                       ,        24,     1,      321,    "R/W",  0,      0,      0ull,   0ull},
14405         {"TWSEN"                       ,        25,     1,      321,    "R/W",  0,      0,      0ull,   0ull},
14406         {"TWSEI"                       ,        26,     1,      321,    "R/W",  0,      0,      0ull,   0ull},
14407         {"TRTAE"                       ,        27,     1,      321,    "R/W",  0,      0,      0ull,   0ull},
14408         {"TRDRS"                       ,        28,     1,      321,    "R/W",  0,      0,      0ull,   0ull},
14409         {"RDSATI"                      ,        29,     1,      321,    "R/W",  0,      0,      0ull,   0ull},
14410         {"TRDARD"                      ,        30,     1,      321,    "R/W1C",        0,      0,      0ull,   0ull},
14411         {"TRDNPR"                      ,        31,     1,      321,    "R/W1C",        0,      0,      0ull,   0ull},
14412         {"TSCME"                       ,        0,      32,     322,    "R/W1C",        0,      1,      0ull,   0},
14413         {"TDSRPS"                      ,        0,      32,     323,    "R/W1C",        0,      0,      0ull,   0ull},
14414         {"TDOMC"                       ,        0,      5,      324,    "R/W",  0,      0,      1ull,   1ull},
14415         {"TIDOMC"                      ,        5,      1,      324,    "R/W",  0,      0,      0ull,   0ull},
14416         {"RESERVED_6_6"                ,        6,      1,      324,    "RAZ",  1,      1,      0,      0},
14417         {"TIBDE"                       ,        7,      1,      324,    "R/W",  0,      0,      0ull,   0ull},
14418         {"TIBCD"                       ,        8,      1,      324,    "R/W1C",        0,      0,      0ull,   0ull},
14419         {"RESERVED_9_10"               ,        9,      2,      324,    "RAZ",  1,      1,      0,      0},
14420         {"TMAPES"                      ,        11,     1,      324,    "R/W1C",        0,      0,      0ull,   0ull},
14421         {"TMDPES"                      ,        12,     1,      324,    "R/W1C",        0,      0,      0ull,   0ull},
14422         {"TMSE"                        ,        13,     1,      324,    "R/W1C",        0,      0,      0ull,   0ull},
14423         {"TMEI"                        ,        14,     1,      324,    "RO",   0,      0,      0ull,   0ull},
14424         {"TECI"                        ,        15,     1,      324,    "RO",   0,      0,      0ull,   0ull},
14425         {"TMES"                        ,        16,     8,      324,    "RO",   0,      0,      0ull,   0ull},
14426         {"MDRRMC"                      ,        24,     3,      324,    "R/W",  0,      0,      2ull,   2ull},
14427         {"MDRIMC"                      ,        27,     1,      324,    "R/W",  0,      0,      0ull,   0ull},
14428         {"MDRE"                        ,        28,     1,      324,    "R/W",  0,      0,      0ull,   0ull},
14429         {"MDWE"                        ,        29,     1,      324,    "R/W",  0,      0,      0ull,   0ull},
14430         {"MRBCI"                       ,        30,     1,      324,    "R/W",  0,      0,      0ull,   0ull},
14431         {"MRBCM"                       ,        31,     1,      324,    "R/W",  0,      0,      1ull,   1ull},
14432         {"MDSP"                        ,        0,      32,     325,    "R/W1C",        0,      1,      0ull,   0},
14433         {"SCMRE"                       ,        0,      32,     326,    "R/W1C",        0,      1,      0ull,   0},
14434         {"MTTV"                        ,        0,      8,      327,    "R/W",  0,      0,      0ull,   0ull},
14435         {"MRV"                         ,        8,      8,      327,    "R/W",  0,      0,      0ull,   255ull},
14436         {"MTTA"                        ,        16,     1,      327,    "R/W1C",        0,      0,      0ull,   0ull},
14437         {"MRA"                         ,        17,     1,      327,    "R/W1C",        0,      0,      0ull,   0ull},
14438         {"FLUSH"                       ,        18,     1,      327,    "R/W",  0,      0,      1ull,   1ull},
14439         {"RESERVED_19_24"              ,        19,     6,      327,    "RAZ",  1,      1,      0,      0},
14440         {"MAC"                         ,        25,     7,      327,    "R/W",  0,      0,      0ull,   0ull},
14441         {"PXCID"                       ,        0,      8,      328,    "RO",   0,      0,      7ull,   7ull},
14442         {"NCP"                         ,        8,      8,      328,    "RO",   0,      0,      232ull, 232ull},
14443         {"DPERE"                       ,        16,     1,      328,    "R/W",  0,      0,      0ull,   0ull},
14444         {"ROE"                         ,        17,     1,      328,    "R/W",  0,      0,      1ull,   1ull},
14445         {"MMBC"                        ,        18,     2,      328,    "R/W",  0,      0,      0ull,   0ull},
14446         {"MOST"                        ,        20,     3,      328,    "R/W",  0,      0,      3ull,   3ull},
14447         {"RESERVED_23_31"              ,        23,     9,      328,    "RAZ",  1,      1,      0,      0},
14448         {"FN"                          ,        0,      3,      329,    "RO",   0,      0,      0ull,   0ull},
14449         {"DN"                          ,        3,      5,      329,    "RO",   0,      0,      31ull,  31ull},
14450         {"BN"                          ,        8,      8,      329,    "RO",   0,      1,      17ull,  0},
14451         {"W64"                         ,        16,     1,      329,    "RO",   0,      0,      1ull,   1ull},
14452         {"M133"                        ,        17,     1,      329,    "RO",   0,      0,      1ull,   1ull},
14453         {"SCD"                         ,        18,     1,      329,    "R/W1C",        0,      1,      0ull,   0},
14454         {"USC"                         ,        19,     1,      329,    "R/W1C",        0,      1,      0ull,   0},
14455         {"DC"                          ,        20,     1,      329,    "RO",   0,      0,      0ull,   0ull},
14456         {"MMRBCD"                      ,        21,     2,      329,    "RO",   0,      0,      2ull,   2ull},
14457         {"MOSTD"                       ,        23,     3,      329,    "RO",   0,      0,      3ull,   3ull},
14458         {"MCRSD"                       ,        26,     3,      329,    "RO",   0,      0,      7ull,   7ull},
14459         {"SCEMR"                       ,        29,     1,      329,    "R/W1C",        0,      1,      0ull,   0},
14460         {"RESERVED_30_31"              ,        30,     2,      329,    "RAZ",  1,      1,      0,      0},
14461         {"PMCID"                       ,        0,      8,      330,    "RO",   0,      0,      1ull,   1ull},
14462         {"NCP"                         ,        8,      8,      330,    "RO",   0,      0,      240ull, 240ull},
14463         {"PCIMIV"                      ,        16,     3,      330,    "RO",   0,      0,      2ull,   2ull},
14464         {"PMEC"                        ,        19,     1,      330,    "RO",   0,      0,      0ull,   0ull},
14465         {"RESERVED_20_20"              ,        20,     1,      330,    "RAZ",  1,      1,      0,      0},
14466         {"DSI"                         ,        21,     1,      330,    "RO",   0,      0,      0ull,   0ull},
14467         {"AUXC"                        ,        22,     3,      330,    "RO",   0,      0,      0ull,   0ull},
14468         {"D1S"                         ,        25,     1,      330,    "RO",   0,      0,      0ull,   0ull},
14469         {"D2S"                         ,        26,     1,      330,    "RO",   0,      0,      0ull,   0ull},
14470         {"PMES"                        ,        27,     5,      330,    "RO",   0,      0,      0ull,   0ull},
14471         {"PS"                          ,        0,      2,      331,    "R/W",  0,      0,      0ull,   0ull},
14472         {"RESERVED_2_7"                ,        2,      6,      331,    "RAZ",  1,      1,      0,      0},
14473         {"PMEENS"                      ,        8,      1,      331,    "R/W",  0,      0,      0ull,   0ull},
14474         {"PMDS"                        ,        9,      4,      331,    "R/W",  0,      0,      0ull,   0ull},
14475         {"PMEDSIA"                     ,        13,     2,      331,    "RO",   0,      0,      0ull,   0ull},
14476         {"PMESS"                       ,        15,     1,      331,    "R/W1C",        0,      0,      0ull,   0ull},
14477         {"RESERVED_16_21"              ,        16,     6,      331,    "RAZ",  1,      1,      0,      0},
14478         {"BD3H"                        ,        22,     1,      331,    "RO",   0,      0,      0ull,   0ull},
14479         {"BPCCEN"                      ,        23,     1,      331,    "RO",   0,      0,      0ull,   0ull},
14480         {"PMDIA"                       ,        24,     8,      331,    "RO",   0,      0,      0ull,   0ull},
14481         {"MSICID"                      ,        0,      8,      332,    "RO",   0,      0,      5ull,   5ull},
14482         {"NCP"                         ,        8,      8,      332,    "RO",   0,      0,      0ull,   0ull},
14483         {"MSIEN"                       ,        16,     1,      332,    "R/W",  0,      0,      0ull,   0ull},
14484         {"MMC"                         ,        17,     3,      332,    "RO",   0,      0,      0ull,   0ull},
14485         {"MME"                         ,        20,     3,      332,    "R/W",  0,      0,      0ull,   0ull},
14486         {"M64"                         ,        23,     1,      332,    "RO",   0,      0,      1ull,   1ull},
14487         {"RESERVED_24_31"              ,        24,     8,      332,    "RAZ",  1,      1,      0,      0},
14488         {"RESERVED_0_1"                ,        0,      2,      333,    "RAZ",  1,      1,      0,      0},
14489         {"MSI31T2"                     ,        2,      30,     333,    "R/W",  0,      1,      0ull,   0},
14490         {"MSI"                         ,        0,      32,     334,    "R/W",  0,      1,      0ull,   0},
14491         {"MSIMD"                       ,        0,      16,     335,    "R/W",  0,      1,      0ull,   0},
14492         {"RESERVED_16_31"              ,        16,     16,     335,    "RAZ",  1,      1,      0,      0},
14493         {"BAR2_CAX"                    ,        0,      1,      336,    "R/W",  0,      0,      0ull,   0ull},
14494         {"BAR2_ESX"                    ,        1,      2,      336,    "R/W",  0,      1,      0ull,   0},
14495         {"BAR2_ENB"                    ,        3,      1,      336,    "R/W",  0,      0,      0ull,   1ull},
14496         {"TSR_HWM"                     ,        4,      3,      336,    "R/W",  0,      1,      1ull,   0},
14497         {"PMO_FPC"                     ,        7,      3,      336,    "R/W",  0,      0,      0ull,   0ull},
14498         {"PMO_AMOD"                    ,        10,     1,      336,    "R/W",  0,      0,      0ull,   0ull},
14499         {"B12_BIST"                    ,        11,     1,      336,    "RO",   0,      0,      0ull,   0ull},
14500         {"AP_64AD"                     ,        12,     1,      336,    "RO",   0,      1,      0ull,   0},
14501         {"AP_PCIX"                     ,        13,     1,      336,    "RO",   0,      1,      0ull,   0},
14502         {"RESERVED_14_14"              ,        14,     1,      336,    "RAZ",  0,      0,      0ull,   0ull},
14503         {"EN_WFILT"                    ,        15,     1,      336,    "R/W",  0,      0,      0ull,   1ull},
14504         {"SCM"                         ,        16,     1,      336,    "RO",   0,      1,      0ull,   0},
14505         {"SCMTYP"                      ,        17,     1,      336,    "RO",   0,      1,      0ull,   0},
14506         {"BAR2PRES"                    ,        18,     1,      336,    "R/W",  1,      1,      0,      0},
14507         {"ERST_N"                      ,        19,     1,      336,    "RO",   0,      0,      1ull,   1ull},
14508         {"BB0"                         ,        20,     1,      336,    "R/W",  0,      0,      0ull,   0ull},
14509         {"BB1"                         ,        21,     1,      336,    "R/W",  0,      0,      0ull,   0ull},
14510         {"BB_ES"                       ,        22,     2,      336,    "R/W",  0,      0,      0ull,   0ull},
14511         {"BB_CA"                       ,        24,     1,      336,    "R/W",  0,      0,      0ull,   0ull},
14512         {"BB1_SIZ"                     ,        25,     1,      336,    "R/W",  0,      0,      0ull,   0ull},
14513         {"BB1_HOLE"                    ,        26,     3,      336,    "R/W",  0,      0,      0ull,   0ull},
14514         {"RESERVED_29_31"              ,        29,     3,      336,    "RAZ",  1,      1,      0,      0},
14515         {"INC_VAL"                     ,        0,      16,     337,    "R/W",  0,      1,      0ull,   0},
14516         {"RESERVED_16_31"              ,        16,     16,     337,    "RAZ",  1,      1,      0,      0},
14517         {"DMA_CNT"                     ,        0,      32,     338,    "R/W",  0,      0,      0ull,   0ull},
14518         {"PKT_CNT"                     ,        0,      32,     339,    "R/W",  0,      1,      0ull,   0},
14519         {"DMA_TIME"                    ,        0,      32,     340,    "R/W",  0,      1,      0ull,   0},
14520         {"ICNT"                        ,        0,      32,     341,    "R/W1C",        0,      0,      0ull,   0ull},
14521         {"ITR_WABT"                    ,        0,      1,      342,    "R/W",  0,      1,      0ull,   0},
14522         {"IMR_WABT"                    ,        1,      1,      342,    "R/W",  0,      1,      0ull,   0},
14523         {"IMR_WTTO"                    ,        2,      1,      342,    "R/W",  0,      1,      0ull,   0},
14524         {"ITR_ABT"                     ,        3,      1,      342,    "R/W",  0,      1,      0ull,   0},
14525         {"IMR_ABT"                     ,        4,      1,      342,    "R/W",  0,      1,      0ull,   0},
14526         {"IMR_TTO"                     ,        5,      1,      342,    "R/W",  0,      1,      0ull,   0},
14527         {"IMSI_PER"                    ,        6,      1,      342,    "R/W",  0,      1,      0ull,   0},
14528         {"IMSI_TABT"                   ,        7,      1,      342,    "R/W",  0,      1,      0ull,   0},
14529         {"IMSI_MABT"                   ,        8,      1,      342,    "R/W",  0,      1,      0ull,   0},
14530         {"IMSC_MSG"                    ,        9,      1,      342,    "R/W",  0,      1,      0ull,   0},
14531         {"ITSR_ABT"                    ,        10,     1,      342,    "R/W",  0,      1,      0ull,   0},
14532         {"ISERR"                       ,        11,     1,      342,    "R/W",  0,      1,      0ull,   0},
14533         {"IAPERR"                      ,        12,     1,      342,    "R/W",  0,      1,      0ull,   0},
14534         {"IDPERR"                      ,        13,     1,      342,    "R/W",  0,      1,      0ull,   0},
14535         {"ILL_RWR"                     ,        14,     1,      342,    "R/W",  0,      1,      0ull,   0},
14536         {"ILL_RRD"                     ,        15,     1,      342,    "R/W",  0,      1,      0ull,   0},
14537         {"IRSL_INT"                    ,        16,     1,      342,    "R/W",  0,      1,      0ull,   0},
14538         {"IPCNT0"                      ,        17,     1,      342,    "R/W",  0,      1,      0ull,   0},
14539         {"RESERVED_18_20"              ,        18,     3,      342,    "RAZ",  0,      1,      0ull,   0},
14540         {"IPTIME0"                     ,        21,     1,      342,    "R/W",  0,      1,      0ull,   0},
14541         {"RESERVED_22_24"              ,        22,     3,      342,    "RAZ",  0,      1,      0ull,   0},
14542         {"IDCNT0"                      ,        25,     1,      342,    "R/W",  0,      1,      0ull,   0},
14543         {"IDCNT1"                      ,        26,     1,      342,    "R/W",  0,      1,      0ull,   0},
14544         {"IDTIME0"                     ,        27,     1,      342,    "R/W",  0,      1,      0ull,   0},
14545         {"IDTIME1"                     ,        28,     1,      342,    "R/W",  0,      1,      0ull,   0},
14546         {"DMA0_FI"                     ,        29,     1,      342,    "R/W",  0,      1,      0ull,   0},
14547         {"DMA1_FI"                     ,        30,     1,      342,    "R/W",  0,      1,      0ull,   0},
14548         {"WIN_WR"                      ,        31,     1,      342,    "R/W",  0,      1,      0ull,   0},
14549         {"ILL_WR"                      ,        32,     1,      342,    "R/W",  0,      1,      0ull,   0},
14550         {"ILL_RD"                      ,        33,     1,      342,    "R/W",  0,      1,      0ull,   0},
14551         {"RESERVED_34_63"              ,        34,     30,     342,    "RAZ",  1,      1,      0,      0},
14552         {"RTR_WABT"                    ,        0,      1,      343,    "R/W",  0,      1,      0ull,   0},
14553         {"RMR_WABT"                    ,        1,      1,      343,    "R/W",  0,      1,      0ull,   0},
14554         {"RMR_WTTO"                    ,        2,      1,      343,    "R/W",  0,      1,      0ull,   0},
14555         {"RTR_ABT"                     ,        3,      1,      343,    "R/W",  0,      1,      0ull,   0},
14556         {"RMR_ABT"                     ,        4,      1,      343,    "R/W",  0,      1,      0ull,   0},
14557         {"RMR_TTO"                     ,        5,      1,      343,    "R/W",  0,      1,      0ull,   0},
14558         {"RMSI_PER"                    ,        6,      1,      343,    "R/W",  0,      1,      0ull,   0},
14559         {"RMSI_TABT"                   ,        7,      1,      343,    "R/W",  0,      1,      0ull,   0},
14560         {"RMSI_MABT"                   ,        8,      1,      343,    "R/W",  0,      1,      0ull,   0},
14561         {"RMSC_MSG"                    ,        9,      1,      343,    "R/W",  0,      1,      0ull,   0},
14562         {"RTSR_ABT"                    ,        10,     1,      343,    "R/W",  0,      1,      0ull,   0},
14563         {"RSERR"                       ,        11,     1,      343,    "R/W",  0,      1,      0ull,   0},
14564         {"RAPERR"                      ,        12,     1,      343,    "R/W",  0,      1,      0ull,   0},
14565         {"RDPERR"                      ,        13,     1,      343,    "R/W",  0,      1,      0ull,   0},
14566         {"ILL_RWR"                     ,        14,     1,      343,    "R/W",  0,      1,      0ull,   0},
14567         {"ILL_RRD"                     ,        15,     1,      343,    "R/W",  0,      1,      0ull,   0},
14568         {"RRSL_INT"                    ,        16,     1,      343,    "R/W",  0,      1,      0ull,   0},
14569         {"RPCNT0"                      ,        17,     1,      343,    "R/W",  0,      1,      0ull,   0},
14570         {"RESERVED_18_20"              ,        18,     3,      343,    "RAZ",  0,      1,      0ull,   0},
14571         {"RPTIME0"                     ,        21,     1,      343,    "R/W",  0,      1,      0ull,   0},
14572         {"RESERVED_22_24"              ,        22,     3,      343,    "RAZ",  0,      1,      0ull,   0},
14573         {"RDCNT0"                      ,        25,     1,      343,    "R/W",  0,      1,      0ull,   0},
14574         {"RDCNT1"                      ,        26,     1,      343,    "R/W",  0,      1,      0ull,   0},
14575         {"RDTIME0"                     ,        27,     1,      343,    "R/W",  0,      1,      0ull,   0},
14576         {"RDTIME1"                     ,        28,     1,      343,    "R/W",  0,      1,      0ull,   0},
14577         {"DMA0_FI"                     ,        29,     1,      343,    "R/W",  0,      1,      0ull,   0},
14578         {"DMA1_FI"                     ,        30,     1,      343,    "R/W",  0,      1,      0ull,   0},
14579         {"WIN_WR"                      ,        31,     1,      343,    "R/W",  0,      1,      0ull,   0},
14580         {"ILL_WR"                      ,        32,     1,      343,    "R/W",  0,      1,      0ull,   0},
14581         {"ILL_RD"                      ,        33,     1,      343,    "R/W",  0,      1,      0ull,   0},
14582         {"RESERVED_34_63"              ,        34,     30,     343,    "RAZ",  1,      1,      0,      0},
14583         {"TR_WABT"                     ,        0,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14584         {"MR_WABT"                     ,        1,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14585         {"MR_WTTO"                     ,        2,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14586         {"TR_ABT"                      ,        3,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14587         {"MR_ABT"                      ,        4,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14588         {"MR_TTO"                      ,        5,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14589         {"MSI_PER"                     ,        6,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14590         {"MSI_TABT"                    ,        7,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14591         {"MSI_MABT"                    ,        8,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14592         {"MSC_MSG"                     ,        9,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14593         {"TSR_ABT"                     ,        10,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14594         {"SERR"                        ,        11,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14595         {"APERR"                       ,        12,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14596         {"DPERR"                       ,        13,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14597         {"ILL_RWR"                     ,        14,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14598         {"ILL_RRD"                     ,        15,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14599         {"RSL_INT"                     ,        16,     1,      344,    "RO",   0,      0,      0ull,   0ull},
14600         {"PCNT0"                       ,        17,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14601         {"RESERVED_18_20"              ,        18,     3,      344,    "RAZ",  0,      0,      0ull,   0ull},
14602         {"PTIME0"                      ,        21,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14603         {"RESERVED_22_24"              ,        22,     3,      344,    "RAZ",  0,      0,      0ull,   0ull},
14604         {"DCNT0"                       ,        25,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14605         {"DCNT1"                       ,        26,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14606         {"DTIME0"                      ,        27,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14607         {"DTIME1"                      ,        28,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14608         {"DMA0_FI"                     ,        29,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14609         {"DMA1_FI"                     ,        30,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14610         {"WIN_WR"                      ,        31,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14611         {"ILL_WR"                      ,        32,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14612         {"ILL_RD"                      ,        33,     1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
14613         {"RESERVED_34_63"              ,        34,     30,     344,    "RAZ",  1,      1,      0,      0},
14614         {"TR_WABT"                     ,        0,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14615         {"MR_WABT"                     ,        1,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14616         {"MR_WTTO"                     ,        2,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14617         {"TR_ABT"                      ,        3,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14618         {"MR_ABT"                      ,        4,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14619         {"MR_TTO"                      ,        5,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14620         {"MSI_PER"                     ,        6,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14621         {"MSI_TABT"                    ,        7,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14622         {"MSI_MABT"                    ,        8,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14623         {"MSC_MSG"                     ,        9,      1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14624         {"TSR_ABT"                     ,        10,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14625         {"SERR"                        ,        11,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14626         {"APERR"                       ,        12,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14627         {"DPERR"                       ,        13,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14628         {"ILL_RWR"                     ,        14,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14629         {"ILL_RRD"                     ,        15,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14630         {"RSL_INT"                     ,        16,     1,      345,    "RO",   0,      0,      0ull,   0ull},
14631         {"PCNT0"                       ,        17,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14632         {"RESERVED_18_20"              ,        18,     3,      345,    "RAZ",  0,      0,      0ull,   0ull},
14633         {"PTIME0"                      ,        21,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14634         {"RESERVED_22_24"              ,        22,     3,      345,    "RAZ",  0,      0,      0ull,   0ull},
14635         {"DCNT0"                       ,        25,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14636         {"DCNT1"                       ,        26,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14637         {"DTIME0"                      ,        27,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14638         {"DTIME1"                      ,        28,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14639         {"DMA0_FI"                     ,        29,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14640         {"DMA1_FI"                     ,        30,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14641         {"WIN_WR"                      ,        31,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14642         {"ILL_WR"                      ,        32,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14643         {"ILL_RD"                      ,        33,     1,      345,    "R/W1C",        0,      0,      0ull,   0ull},
14644         {"RESERVED_34_63"              ,        34,     30,     345,    "RAZ",  1,      1,      0,      0},
14645         {"INTR"                        ,        0,      6,      346,    "WO",   0,      1,      0ull,   0},
14646         {"RESERVED_6_31"               ,        6,      26,     346,    "R/W",  1,      1,      0,      0},
14647         {"PTR_CNT"                     ,        0,      16,     347,    "R/W",  0,      1,      0ull,   0},
14648         {"PKT_CNT"                     ,        16,     16,     347,    "R/W",  0,      1,      0ull,   0},
14649         {"PKT_CNT"                     ,        0,      32,     348,    "RO",   0,      0,      0ull,   0ull},
14650         {"PKT_CNT"                     ,        0,      32,     349,    "R/W",  0,      1,      0ull,   0},
14651         {"PKT_TIME"                    ,        0,      32,     350,    "R/W",  0,      1,      0ull,   0},
14652         {"PREFETCH"                    ,        0,      3,      351,    "R/W",  0,      0,      0ull,   2ull},
14653         {"MIN_DATA"                    ,        3,      6,      351,    "R/W",  0,      0,      0ull,   4ull},
14654         {"RESERVED_9_31"               ,        9,      23,     351,    "RAZ",  1,      1,      0,      0},
14655         {"PREFETCH"                    ,        0,      3,      352,    "R/W",  0,      0,      0ull,   3ull},
14656         {"MIN_DATA"                    ,        3,      6,      352,    "R/W",  0,      0,      0ull,   6ull},
14657         {"RESERVED_9_31"               ,        9,      23,     352,    "RAZ",  1,      1,      0,      0},
14658         {"PREFETCH"                    ,        0,      3,      353,    "R/W",  0,      0,      0ull,   3ull},
14659         {"MIN_DATA"                    ,        3,      6,      353,    "R/W",  0,      0,      0ull,   6ull},
14660         {"RESERVED_9_31"               ,        9,      23,     353,    "RAZ",  1,      1,      0,      0},
14661         {"CNT"                         ,        0,      31,     354,    "R/W",  0,      0,      10000ull,       10000ull},
14662         {"ENB"                         ,        31,     1,      354,    "R/W",  0,      0,      0ull,   1ull},
14663         {"RESERVED_32_63"              ,        32,     32,     354,    "RAZ",  1,      1,      0,      0},
14664         {"SCM"                         ,        0,      32,     355,    "RO",   0,      1,      0ull,   0},
14665         {"RESERVED_32_63"              ,        32,     32,     355,    "RAZ",  1,      1,      0,      0},
14666         {"TSR"                         ,        0,      36,     356,    "RO",   0,      1,      0ull,   0},
14667         {"RESERVED_36_63"              ,        36,     28,     356,    "RAZ",  1,      1,      0,      0},
14668         {"RESERVED_0_1"                ,        0,      2,      357,    "RAZ",  1,      1,      0,      0},
14669         {"RD_ADDR"                     ,        2,      46,     357,    "R/W",  0,      1,      0ull,   0},
14670         {"IOBIT"                       ,        48,     1,      357,    "RAZ",  0,      0,      0ull,   0ull},
14671         {"RESERVED_49_63"              ,        49,     15,     357,    "RAZ",  1,      1,      0,      0},
14672         {"RD_DATA"                     ,        0,      64,     358,    "RO",   0,      1,      0ull,   0},
14673         {"RESERVED_0_2"                ,        0,      3,      359,    "RAZ",  1,      1,      0,      0},
14674         {"WR_ADDR"                     ,        3,      45,     359,    "R/W",  0,      1,      0ull,   0},
14675         {"IOBIT"                       ,        48,     1,      359,    "RAZ",  0,      0,      0ull,   0ull},
14676         {"RESERVED_49_63"              ,        49,     15,     359,    "RAZ",  1,      1,      0,      0},
14677         {"WR_DATA"                     ,        0,      64,     360,    "R/W",  0,      1,      0ull,   0},
14678         {"WR_MASK"                     ,        0,      8,      361,    "R/W",  0,      0,      0ull,   0ull},
14679         {"RESERVED_8_63"               ,        8,      56,     361,    "RAZ",  1,      1,      0,      0},
14680         {"THRESH"                      ,        0,      4,      362,    "R/W",  0,      0,      0ull,   8ull},
14681         {"FETCHSIZ"                    ,        4,      4,      362,    "R/W",  0,      0,      0ull,   7ull},
14682         {"TXRD"                        ,        8,      10,     362,    "R/W",  0,      0,      0ull,   1ull},
14683         {"USELDT"                      ,        18,     1,      362,    "R/W",  0,      0,      0ull,   0ull},
14684         {"RESERVED_19_19"              ,        19,     1,      362,    "RAZ",  1,      1,      0,      0},
14685         {"RXST"                        ,        20,     10,     362,    "R/W",  0,      0,      0ull,   1ull},
14686         {"RESERVED_30_31"              ,        30,     2,      362,    "RAZ",  1,      1,      0,      0},
14687         {"TXSLOTS"                     ,        32,     10,     362,    "R/W",  0,      1,      0ull,   0},
14688         {"RESERVED_42_43"              ,        42,     2,      362,    "RAZ",  1,      1,      0,      0},
14689         {"RXSLOTS"                     ,        44,     10,     362,    "R/W",  0,      1,      0ull,   0},
14690         {"RESERVED_54_62"              ,        54,     9,      362,    "RAZ",  1,      1,      0,      0},
14691         {"RDPEND"                      ,        63,     1,      362,    "RO",   0,      0,      0ull,   0ull},
14692         {"FSYNCMISSED"                 ,        0,      1,      363,    "R/W",  0,      0,      0ull,   1ull},
14693         {"FSYNCEXTRA"                  ,        1,      1,      363,    "R/W",  0,      0,      0ull,   1ull},
14694         {"RXWRAP"                      ,        2,      1,      363,    "R/W",  0,      0,      0ull,   1ull},
14695         {"RXST"                        ,        3,      1,      363,    "R/W",  0,      0,      0ull,   1ull},
14696         {"TXWRAP"                      ,        4,      1,      363,    "R/W",  0,      0,      0ull,   1ull},
14697         {"TXRD"                        ,        5,      1,      363,    "R/W",  0,      0,      0ull,   1ull},
14698         {"TXEMPTY"                     ,        6,      1,      363,    "R/W",  0,      0,      0ull,   1ull},
14699         {"RXOVF"                       ,        7,      1,      363,    "R/W",  0,      0,      0ull,   1ull},
14700         {"RESERVED_8_63"               ,        8,      56,     363,    "RAZ",  1,      1,      0,      0},
14701         {"FSYNCMISSED"                 ,        0,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
14702         {"FSYNCEXTRA"                  ,        1,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
14703         {"RXWRAP"                      ,        2,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
14704         {"RXST"                        ,        3,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
14705         {"TXWRAP"                      ,        4,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
14706         {"TXRD"                        ,        5,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
14707         {"TXEMPTY"                     ,        6,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
14708         {"RXOVF"                       ,        7,      1,      364,    "R/W1C",        0,      0,      0ull,   0ull},
14709         {"RESERVED_8_63"               ,        8,      56,     364,    "RAZ",  1,      1,      0,      0},
14710         {"ADDR"                        ,        0,      36,     365,    "R/W",  1,      1,      0,      0},
14711         {"RESERVED_36_63"              ,        36,     28,     365,    "RAZ",  1,      1,      0,      0},
14712         {"CNT"                         ,        0,      16,     366,    "R/W",  1,      1,      0,      0},
14713         {"RESERVED_16_63"              ,        16,     48,     366,    "RAZ",  1,      1,      0,      0},
14714         {"MASK"                        ,        0,      64,     367,    "R/W",  1,      1,      0,      0},
14715         {"MASK"                        ,        0,      64,     368,    "R/W",  1,      1,      0,      0},
14716         {"MASK"                        ,        0,      64,     369,    "R/W",  1,      1,      0,      0},
14717         {"MASK"                        ,        0,      64,     370,    "R/W",  1,      1,      0,      0},
14718         {"MASK"                        ,        0,      64,     371,    "R/W",  1,      1,      0,      0},
14719         {"MASK"                        ,        0,      64,     372,    "R/W",  1,      1,      0,      0},
14720         {"MASK"                        ,        0,      64,     373,    "R/W",  1,      1,      0,      0},
14721         {"MASK"                        ,        0,      64,     374,    "R/W",  1,      1,      0,      0},
14722         {"RESERVED_0_2"                ,        0,      3,      375,    "RAZ",  1,      1,      0,      0},
14723         {"ADDR"                        ,        3,      33,     375,    "R/W",  1,      1,      0,      0},
14724         {"RESERVED_36_63"              ,        36,     28,     375,    "RAZ",  1,      1,      0,      0},
14725         {"ENABLE"                      ,        0,      1,      376,    "R/W",  0,      0,      0ull,   0ull},
14726         {"USECLK1"                     ,        1,      1,      376,    "R/W",  0,      0,      0ull,   0ull},
14727         {"LSBFIRST"                    ,        2,      1,      376,    "R/W",  0,      0,      0ull,   0ull},
14728         {"RESERVED_3_31"               ,        3,      29,     376,    "RAZ",  1,      1,      0,      0},
14729         {"SAMPPT"                      ,        32,     16,     376,    "R/W",  0,      1,      0ull,   0},
14730         {"DRVTIM"                      ,        48,     16,     376,    "R/W",  0,      1,      0ull,   0},
14731         {"DEBUGINFO"                   ,        0,      64,     377,    "RO",   1,      1,      0,      0},
14732         {"FRAM"                        ,        0,      3,      378,    "R/W",  1,      1,      0,      0},
14733         {"ADDR"                        ,        3,      33,     378,    "R/W",  1,      1,      0,      0},
14734         {"RESERVED_36_63"              ,        36,     28,     378,    "RAZ",  1,      1,      0,      0},
14735         {"CNT"                         ,        0,      16,     379,    "R/W",  1,      1,      0,      0},
14736         {"RESERVED_16_63"              ,        16,     48,     379,    "RAZ",  1,      1,      0,      0},
14737         {"MASK"                        ,        0,      64,     380,    "R/W",  1,      1,      0,      0},
14738         {"MASK"                        ,        0,      64,     381,    "R/W",  1,      1,      0,      0},
14739         {"MASK"                        ,        0,      64,     382,    "R/W",  1,      1,      0,      0},
14740         {"MASK"                        ,        0,      64,     383,    "R/W",  1,      1,      0,      0},
14741         {"MASK"                        ,        0,      64,     384,    "R/W",  1,      1,      0,      0},
14742         {"MASK"                        ,        0,      64,     385,    "R/W",  1,      1,      0,      0},
14743         {"MASK"                        ,        0,      64,     386,    "R/W",  1,      1,      0,      0},
14744         {"MASK"                        ,        0,      64,     387,    "R/W",  1,      1,      0,      0},
14745         {"RESERVED_0_2"                ,        0,      3,      388,    "RAZ",  1,      1,      0,      0},
14746         {"ADDR"                        ,        3,      33,     388,    "R/W",  1,      1,      0,      0},
14747         {"RESERVED_36_63"              ,        36,     28,     388,    "RAZ",  1,      1,      0,      0},
14748         {"ENA"                         ,        0,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
14749         {"FSYNCPOL"                    ,        1,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
14750         {"BCLKPOL"                     ,        2,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
14751         {"BITLEN"                      ,        3,      2,      389,    "R/W",  0,      0,      0ull,   0ull},
14752         {"EXTRABIT"                    ,        5,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
14753         {"NUMSLOTS"                    ,        6,      10,     389,    "R/W",  0,      1,      0ull,   0},
14754         {"FSYNCLOC"                    ,        16,     5,      389,    "R/W",  0,      0,      0ull,   0ull},
14755         {"FSYNCLEN"                    ,        21,     5,      389,    "R/W",  0,      0,      0ull,   2ull},
14756         {"RESERVED_26_31"              ,        26,     6,      389,    "RAZ",  1,      1,      0,      0},
14757         {"FSYNCSAMP"                   ,        32,     16,     389,    "R/W",  0,      1,      0ull,   0},
14758         {"RESERVED_48_62"              ,        48,     15,     389,    "RAZ",  1,      1,      0,      0},
14759         {"FSYNCGOOD"                   ,        63,     1,      389,    "RO",   0,      0,      0ull,   1ull},
14760         {"DEBUGINFO"                   ,        0,      64,     390,    "RO",   1,      1,      0,      0},
14761         {"N"                           ,        0,      32,     391,    "R/W",  0,      1,      0ull,   0},
14762         {"NUMSAMP"                     ,        32,     16,     391,    "R/W",  0,      1,      0ull,   0},
14763         {"DELTASAMP"                   ,        48,     16,     391,    "R/W",  0,      0,      0ull,   0ull},
14764         {"BIST"                        ,        0,      18,     392,    "RO",   0,      0,      0ull,   0ull},
14765         {"RESERVED_18_63"              ,        18,     46,     392,    "RAZ",  1,      1,      0,      0},
14766         {"DPRT"                        ,        0,      16,     393,    "R/W",  0,      0,      0ull,   0ull},
14767         {"UDP"                         ,        16,     1,      393,    "R/W",  0,      0,      0ull,   0ull},
14768         {"TCP"                         ,        17,     1,      393,    "R/W",  0,      0,      0ull,   0ull},
14769         {"RESERVED_18_63"              ,        18,     46,     393,    "RAZ",  1,      1,      0,      0},
14770         {"NIP_SHF"                     ,        0,      3,      394,    "R/W",  0,      0,      0ull,   0ull},
14771         {"RESERVED_3_7"                ,        3,      5,      394,    "RAZ",  1,      1,      0,      0},
14772         {"RAW_SHF"                     ,        8,      3,      394,    "R/W",  0,      0,      0ull,   0ull},
14773         {"RESERVED_11_15"              ,        11,     5,      394,    "RAZ",  1,      1,      0,      0},
14774         {"MAX_L2"                      ,        16,     1,      394,    "R/W",  0,      0,      0ull,   0ull},
14775         {"IP6_UDP"                     ,        17,     1,      394,    "R/W",  0,      0,      1ull,   1ull},
14776         {"TAG_SYN"                     ,        18,     1,      394,    "R/W",  0,      0,      0ull,   0ull},
14777         {"RESERVED_19_63"              ,        19,     45,     394,    "RAZ",  1,      1,      0,      0},
14778         {"IP_CHK"                      ,        0,      1,      395,    "R/W",  0,      0,      1ull,   1ull},
14779         {"IP_MAL"                      ,        1,      1,      395,    "R/W",  0,      0,      1ull,   1ull},
14780         {"IP_HOP"                      ,        2,      1,      395,    "R/W",  0,      0,      1ull,   1ull},
14781         {"IP4_OPTS"                    ,        3,      1,      395,    "R/W",  0,      0,      1ull,   1ull},
14782         {"IP6_EEXT"                    ,        4,      2,      395,    "R/W",  0,      0,      1ull,   3ull},
14783         {"RESERVED_6_7"                ,        6,      2,      395,    "RAZ",  0,      1,      0ull,   0},
14784         {"L4_MAL"                      ,        8,      1,      395,    "R/W",  0,      0,      1ull,   1ull},
14785         {"L4_PRT"                      ,        9,      1,      395,    "R/W",  0,      0,      1ull,   1ull},
14786         {"L4_CHK"                      ,        10,     1,      395,    "R/W",  0,      0,      1ull,   1ull},
14787         {"L4_LEN"                      ,        11,     1,      395,    "R/W",  0,      0,      1ull,   1ull},
14788         {"TCP_FLAG"                    ,        12,     1,      395,    "R/W",  0,      0,      1ull,   1ull},
14789         {"L2_MAL"                      ,        13,     1,      395,    "R/W",  0,      0,      1ull,   1ull},
14790         {"VS_QOS"                      ,        14,     1,      395,    "R/W",  0,      0,      0ull,   0ull},
14791         {"VS_WQE"                      ,        15,     1,      395,    "R/W",  0,      0,      0ull,   0ull},
14792         {"IGNRS"                       ,        16,     1,      395,    "R/W",  0,      0,      0ull,   0ull},
14793         {"RESERVED_17_63"              ,        17,     47,     395,    "RAZ",  0,      0,      0ull,   0ull},
14794         {"PKTDRP"                      ,        0,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
14795         {"CRCERR"                      ,        1,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
14796         {"BCKPRS"                      ,        2,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
14797         {"PRTNXA"                      ,        3,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
14798         {"BADTAG"                      ,        4,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
14799         {"SKPRUNT"                     ,        5,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
14800         {"TODOOVR"                     ,        6,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
14801         {"FEPERR"                      ,        7,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
14802         {"BEPERR"                      ,        8,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
14803         {"RESERVED_9_63"               ,        9,      55,     396,    "RAZ",  1,      1,      0,      0},
14804         {"PKTDRP"                      ,        0,      1,      397,    "R/W1C",        0,      0,      0ull,   0ull},
14805         {"CRCERR"                      ,        1,      1,      397,    "R/W1C",        0,      0,      0ull,   0ull},
14806         {"BCKPRS"                      ,        2,      1,      397,    "R/W1C",        0,      0,      0ull,   0ull},
14807         {"PRTNXA"                      ,        3,      1,      397,    "R/W1C",        0,      0,      0ull,   0ull},
14808         {"BADTAG"                      ,        4,      1,      397,    "R/W1C",        0,      0,      0ull,   0ull},
14809         {"SKPRUNT"                     ,        5,      1,      397,    "R/W1C",        0,      0,      0ull,   0ull},
14810         {"TODOOVR"                     ,        6,      1,      397,    "R/W1C",        0,      0,      0ull,   0ull},
14811         {"FEPERR"                      ,        7,      1,      397,    "R/W1C",        0,      0,      0ull,   0ull},
14812         {"BEPERR"                      ,        8,      1,      397,    "R/W1C",        0,      0,      0ull,   0ull},
14813         {"RESERVED_9_63"               ,        9,      55,     397,    "RAZ",  1,      1,      0,      0},
14814         {"OFFSET"                      ,        0,      3,      398,    "R/W",  0,      0,      0ull,   0ull},
14815         {"RESERVED_3_63"               ,        3,      61,     398,    "RAZ",  1,      1,      0,      0},
14816         {"SKIP"                        ,        0,      7,      399,    "R/W",  0,      0,      0ull,   0ull},
14817         {"RESERVED_7_7"                ,        7,      1,      399,    "RAZ",  1,      1,      0,      0},
14818         {"MODE"                        ,        8,      2,      399,    "R/W",  0,      0,      0ull,   0ull},
14819         {"RESERVED_10_15"              ,        10,     6,      399,    "RAZ",  1,      1,      0,      0},
14820         {"QOS_VLAN"                    ,        16,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
14821         {"QOS_DIFF"                    ,        17,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
14822         {"RESERVED_18_19"              ,        18,     2,      399,    "RAZ",  0,      0,      0ull,   0ull},
14823         {"QOS_WAT"                     ,        20,     4,      399,    "R/W",  0,      0,      0ull,   0ull},
14824         {"QOS"                         ,        24,     3,      399,    "R/W",  0,      0,      0ull,   0ull},
14825         {"RESERVED_27_27"              ,        27,     1,      399,    "RAZ",  1,      1,      0,      0},
14826         {"GRP_WAT"                     ,        28,     4,      399,    "R/W",  0,      0,      0ull,   0ull},
14827         {"INST_HDR"                    ,        32,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
14828         {"DYN_RS"                      ,        33,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
14829         {"TAG_INC"                     ,        34,     2,      399,    "R/W",  0,      0,      0ull,   0ull},
14830         {"RAWDRP"                      ,        36,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
14831         {"RESERVED_37_63"              ,        37,     27,     399,    "RAZ",  1,      1,      0,      0},
14832         {"GRP"                         ,        0,      4,      400,    "R/W",  0,      0,      0ull,   0ull},
14833         {"NON_TAG_TYPE"                ,        4,      2,      400,    "R/W",  0,      0,      0ull,   0ull},
14834         {"IP4_TAG_TYPE"                ,        6,      2,      400,    "R/W",  0,      0,      0ull,   0ull},
14835         {"IP6_TAG_TYPE"                ,        8,      2,      400,    "R/W",  0,      0,      0ull,   0ull},
14836         {"TCP4_TAG_TYPE"               ,        10,     2,      400,    "R/W",  0,      0,      0ull,   0ull},
14837         {"TCP6_TAG_TYPE"               ,        12,     2,      400,    "R/W",  0,      0,      0ull,   0ull},
14838         {"IP4_SRC_FLAG"                ,        14,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14839         {"IP6_SRC_FLAG"                ,        15,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14840         {"IP4_DST_FLAG"                ,        16,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14841         {"IP6_DST_FLAG"                ,        17,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14842         {"IP4_PCTL_FLAG"               ,        18,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14843         {"IP6_NXTH_FLAG"               ,        19,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14844         {"IP4_SPRT_FLAG"               ,        20,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14845         {"IP6_SPRT_FLAG"               ,        21,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14846         {"IP4_DPRT_FLAG"               ,        22,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14847         {"IP6_DPRT_FLAG"               ,        23,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14848         {"INC_PRT_FLAG"                ,        24,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14849         {"INC_VLAN"                    ,        25,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14850         {"INC_VS"                      ,        26,     2,      400,    "R/W",  0,      0,      0ull,   0ull},
14851         {"TAG_MODE"                    ,        28,     2,      400,    "R/W",  0,      0,      0ull,   0ull},
14852         {"RESERVED_30_30"              ,        30,     1,      400,    "RAZ",  0,      0,      0ull,   0ull},
14853         {"GRPTAG"                      ,        31,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
14854         {"GRPTAGMASK"                  ,        32,     4,      400,    "R/W",  0,      0,      0ull,   0ull},
14855         {"GRPTAGBASE"                  ,        36,     4,      400,    "R/W",  0,      0,      0ull,   0ull},
14856         {"RESERVED_40_63"              ,        40,     24,     400,    "RAZ",  1,      1,      0,      0},
14857         {"QOS"                         ,        0,      3,      401,    "R/W",  0,      0,      0ull,   0ull},
14858         {"RESERVED_3_63"               ,        3,      61,     401,    "RAZ",  1,      1,      0,      0},
14859         {"QOS"                         ,        0,      3,      402,    "R/W",  0,      0,      0ull,   0ull},
14860         {"RESERVED_3_63"               ,        3,      61,     402,    "RAZ",  1,      1,      0,      0},
14861         {"MATCH_VALUE"                 ,        0,      16,     403,    "R/W",  0,      0,      0ull,   0ull},
14862         {"MATCH_TYPE"                  ,        16,     2,      403,    "R/W",  0,      0,      0ull,   0ull},
14863         {"RESERVED_18_19"              ,        18,     2,      403,    "RAZ",  1,      1,      0,      0},
14864         {"QOS"                         ,        20,     3,      403,    "R/W",  0,      0,      0ull,   0ull},
14865         {"RESERVED_23_23"              ,        23,     1,      403,    "RAZ",  1,      1,      0,      0},
14866         {"GRP"                         ,        24,     4,      403,    "R/W",  0,      0,      0ull,   0ull},
14867         {"RESERVED_28_31"              ,        28,     4,      403,    "RAZ",  1,      1,      0,      0},
14868         {"MASK"                        ,        32,     16,     403,    "R/W",  0,      0,      0ull,   0ull},
14869         {"RESERVED_48_63"              ,        48,     16,     403,    "RAZ",  1,      1,      0,      0},
14870         {"WORD"                        ,        0,      56,     404,    "R/W",  0,      0,      0ull,   0ull},
14871         {"RESERVED_56_63"              ,        56,     8,      404,    "RAZ",  1,      1,      0,      0},
14872         {"RST"                         ,        0,      1,      405,    "R/W",  0,      0,      0ull,   0ull},
14873         {"RESERVED_1_63"               ,        1,      63,     405,    "RAZ",  1,      1,      0,      0},
14874         {"DRP_OCTS"                    ,        0,      32,     406,    "R/W",  0,      1,      0ull,   0},
14875         {"DRP_PKTS"                    ,        32,     32,     406,    "R/W",  0,      1,      0ull,   0},
14876         {"OCTS"                        ,        0,      48,     407,    "R/W",  0,      1,      0ull,   0},
14877         {"RESERVED_48_63"              ,        48,     16,     407,    "RAZ",  1,      1,      0,      0},
14878         {"RAW"                         ,        0,      32,     408,    "R/W",  0,      1,      0ull,   0},
14879         {"PKTS"                        ,        32,     32,     408,    "R/W",  0,      1,      0ull,   0},
14880         {"MCST"                        ,        0,      32,     409,    "R/W",  0,      1,      0ull,   0},
14881         {"BCST"                        ,        32,     32,     409,    "R/W",  0,      1,      0ull,   0},
14882         {"H64"                         ,        0,      32,     410,    "R/W",  0,      1,      0ull,   0},
14883         {"H65TO127"                    ,        32,     32,     410,    "R/W",  0,      1,      0ull,   0},
14884         {"H128TO255"                   ,        0,      32,     411,    "R/W",  0,      1,      0ull,   0},
14885         {"H256TO511"                   ,        32,     32,     411,    "R/W",  0,      1,      0ull,   0},
14886         {"H512TO1023"                  ,        0,      32,     412,    "R/W",  0,      1,      0ull,   0},
14887         {"H1024TO1518"                 ,        32,     32,     412,    "R/W",  0,      1,      0ull,   0},
14888         {"H1519"                       ,        0,      32,     413,    "R/W",  0,      1,      0ull,   0},
14889         {"FCS"                         ,        32,     32,     413,    "R/W",  0,      1,      0ull,   0},
14890         {"UNDERSZ"                     ,        0,      32,     414,    "R/W",  0,      1,      0ull,   0},
14891         {"FRAG"                        ,        32,     32,     414,    "R/W",  0,      1,      0ull,   0},
14892         {"OVERSZ"                      ,        0,      32,     415,    "R/W",  0,      1,      0ull,   0},
14893         {"JABBER"                      ,        32,     32,     415,    "R/W",  0,      1,      0ull,   0},
14894         {"RDCLR"                       ,        0,      1,      416,    "R/W",  0,      0,      1ull,   1ull},
14895         {"RESERVED_1_63"               ,        1,      63,     416,    "RAZ",  1,      1,      0,      0},
14896         {"ERRS"                        ,        0,      16,     417,    "R/W",  0,      1,      0ull,   0},
14897         {"RESERVED_16_63"              ,        16,     48,     417,    "RAZ",  1,      1,      0,      0},
14898         {"OCTS"                        ,        0,      48,     418,    "R/W",  0,      1,      0ull,   0},
14899         {"RESERVED_48_63"              ,        48,     16,     418,    "RAZ",  1,      1,      0,      0},
14900         {"PKTS"                        ,        0,      32,     419,    "R/W",  0,      1,      0ull,   0},
14901         {"RESERVED_32_63"              ,        32,     32,     419,    "RAZ",  1,      1,      0,      0},
14902         {"EN"                          ,        0,      8,      420,    "R/W",  0,      0,      0ull,   0ull},
14903         {"RESERVED_8_63"               ,        8,      56,     420,    "RAZ",  1,      1,      0,      0},
14904         {"MASK"                        ,        0,      16,     421,    "R/W",  0,      0,      0ull,   0ull},
14905         {"RESERVED_16_63"              ,        16,     48,     421,    "RAZ",  1,      1,      0,      0},
14906         {"SRC"                         ,        0,      16,     422,    "R/W",  0,      0,      0ull,   0ull},
14907         {"DST"                         ,        16,     16,     422,    "R/W",  0,      0,      0ull,   0ull},
14908         {"RESERVED_32_63"              ,        32,     32,     422,    "RAZ",  1,      1,      0,      0},
14909         {"ENTRY"                       ,        0,      62,     423,    "RO",   1,      1,      0,      0},
14910         {"RESERVED_62_62"              ,        62,     1,      423,    "RAZ",  1,      1,      0,      0},
14911         {"VAL"                         ,        63,     1,      423,    "RO",   1,      1,      0,      0},
14912         {"COUNT"                       ,        0,      32,     424,    "R/W1C",        1,      0,      0,      0ull},
14913         {"RESERVED_32_63"              ,        32,     32,     424,    "RAZ",  1,      1,      0,      0},
14914         {"COUNT"                       ,        0,      48,     425,    "R/W1C",        1,      0,      0,      0ull},
14915         {"RESERVED_48_63"              ,        48,     16,     425,    "RAZ",  1,      1,      0,      0},
14916         {"SIZE"                        ,        0,      16,     426,    "RO",   1,      0,      0,      0ull},
14917         {"SEGS"                        ,        16,     6,      426,    "RO",   1,      0,      0,      0ull},
14918         {"CMD"                         ,        22,     14,     426,    "RO",   1,      0,      0,      0ull},
14919         {"FAU"                         ,        36,     28,     426,    "RO",   1,      0,      0,      0ull},
14920         {"PTR"                         ,        0,      40,     427,    "RO",   1,      0,      0,      0ull},
14921         {"SIZE"                        ,        40,     16,     427,    "RO",   1,      0,      0,      0ull},
14922         {"POOL"                        ,        56,     3,      427,    "RO",   1,      0,      0,      0ull},
14923         {"BACK"                        ,        59,     4,      427,    "RO",   1,      0,      0,      0ull},
14924         {"I"                           ,        63,     1,      427,    "RO",   1,      0,      0,      0ull},
14925         {"SIZE"                        ,        0,      16,     428,    "RO",   1,      0,      0,      0ull},
14926         {"SEGS"                        ,        16,     6,      428,    "RO",   1,      0,      0,      0ull},
14927         {"CMD"                         ,        22,     14,     428,    "RO",   1,      0,      0,      0ull},
14928         {"FAU"                         ,        36,     28,     428,    "RO",   1,      0,      0,      0ull},
14929         {"PTR"                         ,        0,      40,     429,    "RO",   1,      0,      0,      0ull},
14930         {"SIZE"                        ,        40,     16,     429,    "RO",   1,      0,      0,      0ull},
14931         {"POOL"                        ,        56,     3,      429,    "RO",   1,      0,      0,      0ull},
14932         {"BACK"                        ,        59,     4,      429,    "RO",   1,      0,      0,      0ull},
14933         {"I"                           ,        63,     1,      429,    "RO",   1,      0,      0,      0ull},
14934         {"DATA"                        ,        0,      64,     430,    "RO",   1,      0,      0,      0ull},
14935         {"WIDX2"                       ,        0,      17,     431,    "RO",   1,      0,      0,      0ull},
14936         {"RIDX2"                       ,        17,     17,     431,    "RO",   1,      0,      0,      0ull},
14937         {"WIDX"                        ,        34,     17,     431,    "RO",   1,      0,      0,      0ull},
14938         {"RESERVED_51_63"              ,        51,     13,     431,    "RAZ",  1,      0,      0,      0ull},
14939         {"RIDX"                        ,        0,      17,     432,    "RO",   1,      0,      0,      0ull},
14940         {"RESERVED_17_63"              ,        17,     47,     432,    "RAZ",  1,      0,      0,      0ull},
14941         {"PTR"                         ,        0,      40,     433,    "RO",   1,      0,      0,      0ull},
14942         {"SIZE"                        ,        40,     16,     433,    "RO",   1,      0,      0,      0ull},
14943         {"POOL"                        ,        56,     3,      433,    "RO",   1,      0,      0,      0ull},
14944         {"BACK"                        ,        59,     4,      433,    "RO",   1,      0,      0,      0ull},
14945         {"I"                           ,        63,     1,      433,    "RO",   1,      0,      0,      0ull},
14946         {"PTR"                         ,        0,      40,     434,    "RO",   1,      0,      0,      0ull},
14947         {"SIZE"                        ,        40,     16,     434,    "RO",   1,      0,      0,      0ull},
14948         {"POOL"                        ,        56,     3,      434,    "RO",   1,      0,      0,      0ull},
14949         {"BACK"                        ,        59,     4,      434,    "RO",   1,      0,      0,      0ull},
14950         {"I"                           ,        63,     1,      434,    "RO",   1,      0,      0,      0ull},
14951         {"DATA"                        ,        0,      64,     435,    "RO",   1,      0,      0,      0ull},
14952         {"MAJOR"                       ,        0,      4,      436,    "RO",   1,      0,      0,      0ull},
14953         {"MINOR"                       ,        4,      2,      436,    "RO",   1,      0,      0,      0ull},
14954         {"WAIT"                        ,        6,      1,      436,    "RO",   1,      0,      0,      0ull},
14955         {"QID_BASE"                    ,        7,      7,      436,    "RO",   1,      0,      0,      0ull},
14956         {"QID_OFF"                     ,        14,     3,      436,    "RO",   1,      0,      0,      0ull},
14957         {"QCB_RIDX"                    ,        17,     5,      436,    "RO",   1,      0,      0,      0ull},
14958         {"QOS"                         ,        22,     3,      436,    "RO",   1,      0,      0,      0ull},
14959         {"ACTIVE"                      ,        25,     1,      436,    "RO",   1,      0,      0,      0ull},
14960         {"CHK_MODE"                    ,        26,     1,      436,    "RO",   1,      0,      0,      0ull},
14961         {"RESERVED_27_27"              ,        27,     1,      436,    "RAZ",  1,      0,      0,      0ull},
14962         {"CBUF_FRE"                    ,        28,     1,      436,    "RO",   1,      0,      0,      0ull},
14963         {"XFER_DWR"                    ,        29,     1,      436,    "RO",   1,      0,      0,      0ull},
14964         {"XFER_WOR"                    ,        30,     1,      436,    "RO",   1,      0,      0,      0ull},
14965         {"UID"                         ,        31,     1,      436,    "RO",   1,      0,      0,      0ull},
14966         {"CMND_SIZ"                    ,        32,     16,     436,    "RO",   1,      0,      0,      0ull},
14967         {"DWRI_CNT"                    ,        48,     13,     436,    "RO",   1,      0,      0,      0ull},
14968         {"DWRI_LEN"                    ,        61,     1,      436,    "RO",   1,      0,      0,      0ull},
14969         {"DWRI_SOP"                    ,        62,     1,      436,    "RO",   1,      0,      0,      0ull},
14970         {"DWRI_MOD"                    ,        63,     1,      436,    "RO",   1,      0,      0,      0ull},
14971         {"DWRI_MOD"                    ,        0,      2,      437,    "RO",   1,      0,      0,      0ull},
14972         {"DWRI_UID"                    ,        2,      1,      437,    "RO",   1,      0,      0,      0ull},
14973         {"DWRI_CHK"                    ,        3,      1,      437,    "RO",   1,      0,      0,      0ull},
14974         {"WORK_MIN"                    ,        4,      3,      437,    "RO",   1,      0,      0,      0ull},
14975         {"STATIC_P"                    ,        7,      1,      437,    "RO",   1,      0,      0,      0ull},
14976         {"QID_OFFM"                    ,        8,      3,      437,    "RO",   1,      0,      0,      0ull},
14977         {"RESERVED_11_63"              ,        11,     53,     437,    "RAZ",  1,      0,      0,      0ull},
14978         {"SIZE"                        ,        0,      16,     438,    "RO",   1,      0,      0,      0ull},
14979         {"START"                       ,        16,     33,     438,    "RO",   1,      0,      0,      0ull},
14980         {"DWB"                         ,        49,     9,      438,    "RO",   1,      0,      0,      0ull},
14981         {"RESERVED_58_63"              ,        58,     6,      438,    "RAZ",  1,      0,      0,      0ull},
14982         {"QCB_RIDX"                    ,        0,      6,      439,    "RO",   1,      0,      0,      0ull},
14983         {"QCB_WIDX"                    ,        6,      6,      439,    "RO",   1,      0,      0,      0ull},
14984         {"BUF_PTR"                     ,        12,     33,     439,    "RO",   1,      0,      0,      0ull},
14985         {"BUF_SIZ"                     ,        45,     13,     439,    "RO",   1,      0,      0,      0ull},
14986         {"TAIL"                        ,        58,     1,      439,    "RO",   1,      0,      0,      0ull},
14987         {"QOS"                         ,        59,     5,      439,    "RO",   1,      0,      0,      0ull},
14988         {"QOS"                         ,        0,      3,      440,    "RO",   1,      0,      0,      0ull},
14989         {"STATIC_Q"                    ,        3,      1,      440,    "RO",   1,      0,      0,      0ull},
14990         {"S_TAIL"                      ,        4,      1,      440,    "RO",   1,      0,      0,      0ull},
14991         {"RESERVED_5_7"                ,        5,      3,      440,    "RAZ",  1,      0,      0,      0ull},
14992         {"DOORBELL"                    ,        8,      20,     440,    "RO",   1,      0,      0,      0ull},
14993         {"RESERVED_28_63"              ,        28,     36,     440,    "RAZ",  1,      0,      0,      0ull},
14994         {"QUEUE"                       ,        0,      7,      441,    "R/W",  1,      0,      0,      0ull},
14995         {"PORT"                        ,        7,      6,      441,    "WR0",  1,      0,      0,      0ull},
14996         {"INDEX"                       ,        13,     3,      441,    "WR0",  1,      0,      0,      0ull},
14997         {"TAIL"                        ,        16,     1,      441,    "R/W",  1,      0,      0,      0ull},
14998         {"BUF_PTR"                     ,        17,     36,     441,    "R/W",  1,      0,      0,      0ull},
14999         {"QOS_MASK"                    ,        53,     8,      441,    "R/W",  1,      0,      0,      0ull},
15000         {"STATIC_Q"                    ,        61,     1,      441,    "WR0",  1,      0,      0,      0ull},
15001         {"STATIC_P"                    ,        62,     1,      441,    "WR0",  1,      0,      0,      0ull},
15002         {"S_TAIL"                      ,        63,     1,      441,    "WR0",  1,      0,      0,      0ull},
15003         {"QID"                         ,        0,      7,      442,    "R/W",  1,      0,      0,      0ull},
15004         {"PID"                         ,        7,      6,      442,    "WR0",  1,      0,      0,      0ull},
15005         {"RESERVED_13_52"              ,        13,     40,     442,    "RAZ",  1,      0,      0,      0ull},
15006         {"QOS_MASK"                    ,        53,     8,      442,    "R/W",  1,      0,      0,      0ull},
15007         {"RESERVED_61_63"              ,        61,     3,      442,    "RAZ",  1,      0,      0,      0ull},
15008         {"PSB"                         ,        0,      7,      443,    "RO",   1,      0,      0,      0ull},
15009         {"PDB"                         ,        7,      4,      443,    "RO",   1,      0,      0,      0ull},
15010         {"QCB"                         ,        11,     2,      443,    "RO",   1,      0,      0,      0ull},
15011         {"QSB"                         ,        13,     2,      443,    "RO",   1,      0,      0,      0ull},
15012         {"CHK"                         ,        15,     1,      443,    "RO",   1,      0,      0,      0ull},
15013         {"CRC"                         ,        16,     1,      443,    "RO",   1,      0,      0,      0ull},
15014         {"OUT"                         ,        17,     1,      443,    "RO",   1,      0,      0,      0ull},
15015         {"NCB"                         ,        18,     1,      443,    "RO",   1,      0,      0,      0ull},
15016         {"WIF"                         ,        19,     1,      443,    "RO",   1,      0,      0,      0ull},
15017         {"RIF"                         ,        20,     1,      443,    "RO",   1,      0,      0,      0ull},
15018         {"COUNT"                       ,        21,     1,      443,    "RO",   1,      0,      0,      0ull},
15019         {"PSB2"                        ,        22,     5,      443,    "RO",   1,      0,      0,      0ull},
15020         {"RESERVED_27_63"              ,        27,     37,     443,    "RAZ",  1,      0,      0,      0ull},
15021         {"SIZE"                        ,        0,      13,     444,    "R/W",  0,      0,      0ull,   0ull},
15022         {"RESERVED_13_19"              ,        13,     7,      444,    "RAZ",  0,      0,      0ull,   0ull},
15023         {"POOL"                        ,        20,     3,      444,    "R/W",  0,      0,      0ull,   0ull},
15024         {"RESERVED_23_63"              ,        23,     41,     444,    "RAZ",  1,      0,      0,      0ull},
15025         {"ASSERTS"                     ,        0,      17,     445,    "RO",   0,      0,      0ull,   0ull},
15026         {"RESERVED_17_63"              ,        17,     47,     445,    "RAZ",  1,      0,      0,      0ull},
15027         {"PARITY"                      ,        0,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
15028         {"DOORBELL"                    ,        1,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
15029         {"RESERVED_2_63"               ,        2,      62,     446,    "RAZ",  1,      0,      0,      0ull},
15030         {"ENA_PKO"                     ,        0,      1,      447,    "R/W",  0,      0,      0ull,   0ull},
15031         {"ENA_DWB"                     ,        1,      1,      447,    "R/W",  0,      0,      0ull,   0ull},
15032         {"STORE_BE"                    ,        2,      1,      447,    "R/W",  0,      0,      0ull,   0ull},
15033         {"RESET"                       ,        3,      1,      447,    "RAZ",  0,      0,      0ull,   0ull},
15034         {"RESERVED_4_63"               ,        4,      60,     447,    "RAZ",  1,      0,      0,      0ull},
15035         {"MODE0"                       ,        0,      3,      448,    "R/W",  0,      0,      0ull,   0ull},
15036         {"MODE1"                       ,        3,      3,      448,    "R/W",  0,      0,      0ull,   0ull},
15037         {"RESERVED_6_63"               ,        6,      58,     448,    "RAZ",  1,      0,      0,      0ull},
15038         {"PARITY"                      ,        0,      1,      449,    "R/W",  0,      0,      0ull,   0ull},
15039         {"DOORBELL"                    ,        1,      1,      449,    "R/W",  0,      0,      0ull,   0ull},
15040         {"RESERVED_2_63"               ,        2,      62,     449,    "RAZ",  1,      0,      0,      0ull},
15041         {"MODE"                        ,        0,      2,      450,    "R/W",  0,      0,      0ull,   0ull},
15042         {"RESERVED_2_63"               ,        2,      62,     450,    "RAZ",  1,      0,      0,      0ull},
15043         {"INDEX"                       ,        0,      8,      451,    "R/W",  0,      0,      0ull,   0ull},
15044         {"INC"                         ,        8,      8,      451,    "R/W",  0,      0,      0ull,   0ull},
15045         {"RESERVED_16_63"              ,        16,     48,     451,    "RAZ",  1,      0,      0,      0ull},
15046         {"ADR"                         ,        0,      1,      452,    "RO",   0,      0,      0ull,   0ull},
15047         {"PEND"                        ,        1,      1,      452,    "RO",   0,      0,      0ull,   0ull},
15048         {"NBR0"                        ,        2,      1,      452,    "RO",   0,      0,      0ull,   0ull},
15049         {"NBR1"                        ,        3,      1,      452,    "RO",   0,      0,      0ull,   0ull},
15050         {"FIDX"                        ,        4,      1,      452,    "RO",   0,      0,      0ull,   0ull},
15051         {"INDEX"                       ,        5,      1,      452,    "RO",   0,      0,      0ull,   0ull},
15052         {"NBT0"                        ,        6,      1,      452,    "RO",   0,      0,      0ull,   0ull},
15053         {"NBT1"                        ,        7,      1,      452,    "RO",   0,      0,      0ull,   0ull},
15054         {"CAM"                         ,        8,      1,      452,    "RO",   0,      0,      0ull,   0ull},
15055         {"RESERVED_9_15"               ,        9,      7,      452,    "RAZ",  1,      1,      0,      0},
15056         {"PP"                          ,        16,     1,      452,    "RO",   0,      0,      0ull,   0ull},
15057         {"RESERVED_17_63"              ,        17,     47,     452,    "RAZ",  1,      1,      0,      0},
15058         {"DS_PC"                       ,        0,      32,     453,    "R/W1C",        0,      1,      0ull,   0},
15059         {"RESERVED_32_63"              ,        32,     32,     453,    "RAZ",  1,      1,      0,      0},
15060         {"SBE"                         ,        0,      1,      454,    "R/W1C",        0,      0,      0ull,   0ull},
15061         {"DBE"                         ,        1,      1,      454,    "R/W1C",        0,      0,      0ull,   0ull},
15062         {"SBE_IE"                      ,        2,      1,      454,    "R/W",  0,      1,      0ull,   0},
15063         {"DBE_IE"                      ,        3,      1,      454,    "R/W",  0,      1,      0ull,   0},
15064         {"SYN"                         ,        4,      5,      454,    "RO",   1,      1,      0,      0},
15065         {"RESERVED_9_11"               ,        9,      3,      454,    "RAZ",  1,      1,      0,      0},
15066         {"RPE"                         ,        12,     1,      454,    "R/W1C",        0,      0,      0ull,   0ull},
15067         {"RPE_IE"                      ,        13,     1,      454,    "R/W",  0,      1,      0ull,   0},
15068         {"RESERVED_14_15"              ,        14,     2,      454,    "RAZ",  1,      1,      0,      0},
15069         {"IOP"                         ,        16,     13,     454,    "R/W1C",        0,      0,      0ull,   0ull},
15070         {"RESERVED_29_31"              ,        29,     3,      454,    "RAZ",  1,      1,      0,      0},
15071         {"IOP_IE"                      ,        32,     13,     454,    "R/W",  0,      1,      0ull,   0},
15072         {"RESERVED_45_63"              ,        45,     19,     454,    "RAZ",  1,      1,      0,      0},
15073         {"NBR_THR"                     ,        0,      5,      455,    "R/W",  0,      0,      2ull,   2ull},
15074         {"PFR_DIS"                     ,        5,      1,      455,    "R/W",  0,      0,      0ull,   0ull},
15075         {"RESERVED_6_63"               ,        6,      58,     455,    "RAZ",  1,      1,      0,      0},
15076         {"IQ_CNT"                      ,        0,      32,     456,    "RO",   0,      1,      0ull,   0},
15077         {"RESERVED_32_63"              ,        32,     32,     456,    "RAZ",  1,      1,      0,      0},
15078         {"IQ_CNT"                      ,        0,      32,     457,    "RO",   0,      1,      0ull,   0},
15079         {"RESERVED_32_63"              ,        32,     32,     457,    "RAZ",  1,      1,      0,      0},
15080         {"NOS_CNT"                     ,        0,      7,      458,    "RO",   0,      1,      0ull,   0},
15081         {"RESERVED_7_63"               ,        7,      57,     458,    "RAZ",  1,      1,      0,      0},
15082         {"NW_TIM"                      ,        0,      10,     459,    "R/W",  0,      0,      0ull,   1023ull},
15083         {"RESERVED_10_63"              ,        10,     54,     459,    "RAZ",  1,      1,      0,      0},
15084         {"GRP_MSK"                     ,        0,      16,     460,    "R/W",  0,      0,      65535ull,       65535ull},
15085         {"RESERVED_16_63"              ,        16,     48,     460,    "RAZ",  1,      1,      0,      0},
15086         {"RND"                         ,        0,      8,      461,    "R/W",  0,      1,      255ull, 0},
15087         {"RND_P1"                      ,        8,      8,      461,    "R/W",  0,      1,      255ull, 0},
15088         {"RND_P2"                      ,        16,     8,      461,    "R/W",  0,      1,      255ull, 0},
15089         {"RND_P3"                      ,        24,     8,      461,    "R/W",  0,      1,      255ull, 0},
15090         {"RESERVED_32_63"              ,        32,     32,     461,    "RAZ",  1,      1,      0,      0},
15091         {"MIN_THR"                     ,        0,      6,      462,    "R/W",  0,      1,      0ull,   0},
15092         {"RESERVED_6_11"               ,        6,      6,      462,    "RAZ",  1,      1,      0,      0},
15093         {"MAX_THR"                     ,        12,     6,      462,    "R/W",  0,      1,      63ull,  0},
15094         {"RESERVED_18_23"              ,        18,     6,      462,    "RAZ",  1,      1,      0,      0},
15095         {"FREE_CNT"                    ,        24,     7,      462,    "RO",   0,      1,      58ull,  0},
15096         {"RESERVED_31_35"              ,        31,     5,      462,    "RAZ",  1,      1,      0,      0},
15097         {"BUF_CNT"                     ,        36,     7,      462,    "RO",   0,      1,      0ull,   0},
15098         {"RESERVED_43_47"              ,        43,     5,      462,    "RAZ",  1,      1,      0,      0},
15099         {"DES_CNT"                     ,        48,     7,      462,    "RO",   0,      1,      0ull,   0},
15100         {"RESERVED_55_63"              ,        55,     9,      462,    "RAZ",  1,      1,      0,      0},
15101         {"TS_PC"                       ,        0,      32,     463,    "R/W1C",        0,      1,      0ull,   0},
15102         {"RESERVED_32_63"              ,        32,     32,     463,    "RAZ",  1,      1,      0,      0},
15103         {"WA_PC"                       ,        0,      32,     464,    "R/W1C",        0,      1,      0ull,   0},
15104         {"RESERVED_32_63"              ,        32,     32,     464,    "RAZ",  1,      1,      0,      0},
15105         {"WA_PC"                       ,        0,      32,     465,    "R/W1C",        0,      1,      0ull,   0},
15106         {"RESERVED_32_63"              ,        32,     32,     465,    "RAZ",  1,      1,      0,      0},
15107         {"WQ_INT"                      ,        0,      16,     466,    "R/W1C",        0,      1,      0ull,   0},
15108         {"IQ_DIS"                      ,        16,     16,     466,    "R/W1", 0,      1,      0ull,   0},
15109         {"RESERVED_32_63"              ,        32,     32,     466,    "RAZ",  1,      1,      0,      0},
15110         {"IQ_CNT"                      ,        0,      7,      467,    "RO",   0,      1,      0ull,   0},
15111         {"RESERVED_7_11"               ,        7,      5,      467,    "RAZ",  1,      1,      0,      0},
15112         {"DS_CNT"                      ,        12,     7,      467,    "RO",   0,      1,      0ull,   0},
15113         {"RESERVED_19_23"              ,        19,     5,      467,    "RAZ",  1,      1,      0,      0},
15114         {"TC_CNT"                      ,        24,     4,      467,    "RO",   0,      1,      0ull,   0},
15115         {"RESERVED_28_63"              ,        28,     36,     467,    "RAZ",  1,      1,      0,      0},
15116         {"RESERVED_0_7"                ,        0,      8,      468,    "RAZ",  1,      1,      0,      0},
15117         {"PC_THR"                      ,        8,      20,     468,    "R/W",  0,      1,      0ull,   0},
15118         {"RESERVED_28_31"              ,        28,     4,      468,    "RAZ",  1,      1,      0,      0},
15119         {"PC"                          ,        32,     28,     468,    "RO",   0,      1,      0ull,   0},
15120         {"RESERVED_60_63"              ,        60,     4,      468,    "RAZ",  1,      1,      0,      0},
15121         {"IQ_THR"                      ,        0,      6,      469,    "R/W",  0,      1,      0ull,   0},
15122         {"RESERVED_6_11"               ,        6,      6,      469,    "RAZ",  1,      1,      0,      0},
15123         {"DS_THR"                      ,        12,     6,      469,    "R/W",  0,      1,      0ull,   0},
15124         {"RESERVED_18_23"              ,        18,     6,      469,    "RAZ",  1,      1,      0,      0},
15125         {"TC_THR"                      ,        24,     4,      469,    "R/W",  0,      1,      0ull,   0},
15126         {"TC_EN"                       ,        28,     1,      469,    "R/W",  0,      1,      0ull,   0},
15127         {"RESERVED_29_63"              ,        29,     35,     469,    "RAZ",  1,      1,      0,      0},
15128         {"WS_PC"                       ,        0,      32,     470,    "R/W1C",        0,      1,      0ull,   0},
15129         {"RESERVED_32_63"              ,        32,     32,     470,    "RAZ",  1,      1,      0,      0},
15130         {"MEM"                         ,        0,      1,      471,    "RO",   0,      0,      0ull,   0ull},
15131         {"RRC"                         ,        1,      1,      471,    "RO",   0,      0,      0ull,   0ull},
15132         {"RESERVED_2_63"               ,        2,      62,     471,    "RAZ",  1,      1,      0,      0},
15133         {"ENT_EN"                      ,        0,      1,      472,    "R/W",  0,      0,      0ull,   0ull},
15134         {"RNG_EN"                      ,        1,      1,      472,    "R/W",  0,      0,      0ull,   0ull},
15135         {"RNM_RST"                     ,        2,      1,      472,    "R/W",  0,      0,      0ull,   0ull},
15136         {"RNG_RST"                     ,        3,      1,      472,    "R/W",  0,      0,      0ull,   0ull},
15137         {"RESERVED_4_63"               ,        4,      60,     472,    "RAZ",  1,      1,      0,      0},
15138         {"PHASE"                       ,        0,      8,      473,    "R/W",  0,      0,      100ull, 100ull},
15139         {"SAMPLE"                      ,        8,      4,      473,    "R/W",  0,      0,      2ull,   2ull},
15140         {"PREAMBLE"                    ,        12,     1,      473,    "R/W",  0,      0,      1ull,   1ull},
15141         {"CLK_IDLE"                    ,        13,     1,      473,    "R/W",  0,      0,      0ull,   0ull},
15142         {"RESERVED_14_14"              ,        14,     1,      473,    "RAZ",  1,      1,      0,      0},
15143         {"SAMPLE_MODE"                 ,        15,     1,      473,    "RAZ",  0,      0,      0ull,   0ull},
15144         {"SAMPLE_HI"                   ,        16,     5,      473,    "R/W",  0,      0,      0ull,   0ull},
15145         {"RESERVED_21_63"              ,        21,     43,     473,    "RAZ",  1,      1,      0,      0},
15146         {"REG_ADR"                     ,        0,      5,      474,    "R/W",  0,      1,      0ull,   0},
15147         {"RESERVED_5_7"                ,        5,      3,      474,    "RAZ",  1,      1,      0,      0},
15148         {"PHY_ADR"                     ,        8,      5,      474,    "R/W",  0,      1,      0ull,   0},
15149         {"RESERVED_13_15"              ,        13,     3,      474,    "RAZ",  1,      1,      0,      0},
15150         {"PHY_OP"                      ,        16,     1,      474,    "R/W",  0,      1,      0ull,   0},
15151         {"RESERVED_17_63"              ,        17,     47,     474,    "RAZ",  1,      1,      0,      0},
15152         {"EN"                          ,        0,      1,      475,    "R/W",  0,      0,      0ull,   1ull},
15153         {"RESERVED_1_63"               ,        1,      63,     475,    "RAZ",  1,      1,      0,      0},
15154         {"DAT"                         ,        0,      16,     476,    "RO",   0,      1,      0ull,   0},
15155         {"VAL"                         ,        16,     1,      476,    "RO",   0,      1,      0ull,   0},
15156         {"PENDING"                     ,        17,     1,      476,    "RO",   0,      1,      0ull,   0},
15157         {"RESERVED_18_63"              ,        18,     46,     476,    "RAZ",  1,      1,      0,      0},
15158         {"DAT"                         ,        0,      16,     477,    "R/W",  0,      1,      0ull,   0},
15159         {"VAL"                         ,        16,     1,      477,    "RO",   0,      1,      0ull,   0},
15160         {"PENDING"                     ,        17,     1,      477,    "RO",   0,      1,      0ull,   0},
15161         {"RESERVED_18_63"              ,        18,     46,     477,    "RAZ",  1,      1,      0,      0},
15162         {"INTERVAL"                    ,        0,      22,     478,    "RO",   1,      0,      0,      0ull},
15163         {"RESERVED_22_23"              ,        22,     2,      478,    "RAZ",  1,      0,      0,      0ull},
15164         {"COUNT"                       ,        24,     22,     478,    "RO",   1,      0,      0,      0ull},
15165         {"RESERVED_46_46"              ,        46,     1,      478,    "RAZ",  1,      0,      0,      0ull},
15166         {"ENA"                         ,        47,     1,      478,    "RO",   1,      0,      0,      0ull},
15167         {"RESERVED_48_63"              ,        48,     16,     478,    "RAZ",  1,      0,      0,      0ull},
15168         {"BSIZE"                       ,        0,      20,     479,    "RO",   1,      0,      0,      0ull},
15169         {"BASE"                        ,        20,     31,     479,    "RO",   1,      0,      0,      0ull},
15170         {"BUCKET"                      ,        51,     13,     479,    "RO",   1,      0,      0,      0ull},
15171         {"BUCKET"                      ,        0,      7,      480,    "RO",   1,      0,      0,      0ull},
15172         {"RESERVED_7_7"                ,        7,      1,      480,    "RAZ",  1,      0,      0,      0ull},
15173         {"CSIZE"                       ,        8,      13,     480,    "RO",   1,      0,      0,      0ull},
15174         {"CPOOL"                       ,        21,     3,      480,    "RO",   1,      0,      0,      0ull},
15175         {"RESERVED_24_63"              ,        24,     40,     480,    "RAZ",  1,      0,      0,      0ull},
15176         {"RING"                        ,        0,      4,      481,    "R/W",  0,      0,      0ull,   0ull},
15177         {"NUM_BUCKETS"                 ,        4,      20,     481,    "R/W",  0,      0,      0ull,   0ull},
15178         {"FIRST_BUCKET"                ,        24,     31,     481,    "R/W",  0,      0,      0ull,   0ull},
15179         {"RESERVED_55_63"              ,        55,     9,      481,    "RAZ",  1,      0,      0,      0ull},
15180         {"RING"                        ,        0,      4,      482,    "R/W",  0,      0,      0ull,   0ull},
15181         {"INTERVAL"                    ,        4,      22,     482,    "R/W",  0,      0,      0ull,   0ull},
15182         {"WORDS_PER_CHUNK"             ,        26,     13,     482,    "R/W",  0,      0,      0ull,   0ull},
15183         {"POOL"                        ,        39,     3,      482,    "R/W",  0,      0,      0ull,   0ull},
15184         {"ENABLE"                      ,        42,     1,      482,    "R/W",  0,      0,      0ull,   0ull},
15185         {"RESERVED_43_63"              ,        43,     21,     482,    "RAZ",  1,      0,      0,      0ull},
15186         {"CTL"                         ,        0,      1,      483,    "RO",   1,      0,      0,      0ull},
15187         {"NCB"                         ,        1,      1,      483,    "RO",   1,      0,      0,      0ull},
15188         {"STA"                         ,        2,      2,      483,    "RO",   1,      0,      0,      0ull},
15189         {"RESERVED_4_63"               ,        4,      60,     483,    "RAZ",  1,      0,      0,      0ull},
15190         {"MASK"                        ,        0,      16,     484,    "R/W1C",        0,      0,      0ull,   0ull},
15191         {"RESERVED_16_63"              ,        16,     48,     484,    "RAZ",  1,      0,      0,      0ull},
15192         {"ENABLE_TIMERS"               ,        0,      1,      485,    "R/W",  0,      0,      0ull,   0ull},
15193         {"ENABLE_DWB"                  ,        1,      1,      485,    "R/W",  0,      0,      0ull,   0ull},
15194         {"RESET"                       ,        2,      1,      485,    "RAZ",  0,      0,      0ull,   0ull},
15195         {"RESERVED_3_63"               ,        3,      61,     485,    "RAZ",  1,      0,      0,      0ull},
15196         {"MASK"                        ,        0,      16,     486,    "R/W",  0,      0,      0ull,   0ull},
15197         {"RESERVED_16_63"              ,        16,     48,     486,    "RAZ",  1,      0,      0,      0ull},
15198         {"INDEX"                       ,        0,      8,      487,    "R/W",  0,      0,      0ull,   0ull},
15199         {"INC"                         ,        8,      8,      487,    "R/W",  0,      0,      0ull,   0ull},
15200         {"RESERVED_16_63"              ,        16,     48,     487,    "RAZ",  1,      0,      0,      0ull},
15201         {"INEPINT"                     ,        0,      16,     488,    "RO",   0,      0,      0ull,   0ull},
15202         {"OUTEPINT"                    ,        16,     16,     488,    "RO",   0,      0,      0ull,   0ull},
15203         {"INEPMSK"                     ,        0,      16,     489,    "R/W",  0,      0,      0ull,   0ull},
15204         {"OUTEPMSK"                    ,        16,     16,     489,    "R/W",  0,      0,      0ull,   0ull},
15205         {"DEVSPD"                      ,        0,      2,      490,    "R/W",  0,      0,      0ull,   0ull},
15206         {"NZSTSOUTHSHK"                ,        2,      1,      490,    "R/W",  0,      0,      0ull,   0ull},
15207         {"RESERVED_3_3"                ,        3,      1,      490,    "RAZ",  1,      1,      0,      0},
15208         {"DEVADDR"                     ,        4,      7,      490,    "R/W",  0,      0,      0ull,   0ull},
15209         {"PERFRINT"                    ,        11,     2,      490,    "R/W",  0,      0,      0ull,   0ull},
15210         {"RESERVED_13_17"              ,        13,     5,      490,    "RAZ",  1,      1,      0,      0},
15211         {"EPMISCNT"                    ,        18,     5,      490,    "R/W",  0,      0,      8ull,   0ull},
15212         {"RESERVED_23_31"              ,        23,     9,      490,    "RAZ",  1,      1,      0,      0},
15213         {"RMTWKUPSIG"                  ,        0,      1,      491,    "R/W",  0,      0,      0ull,   0ull},
15214         {"SFTDISCON"                   ,        1,      1,      491,    "R/W",  0,      0,      0ull,   0ull},
15215         {"GNPINNAKSTS"                 ,        2,      1,      491,    "RO",   0,      0,      0ull,   0ull},
15216         {"GOUTNAKSTS"                  ,        3,      1,      491,    "RO",   0,      0,      0ull,   0ull},
15217         {"TSTCTL"                      ,        4,      3,      491,    "R/W",  0,      0,      0ull,   0ull},
15218         {"SGNPINNAK"                   ,        7,      1,      491,    "WO",   0,      0,      0ull,   0ull},
15219         {"CGNPINNAK"                   ,        8,      1,      491,    "WO",   0,      0,      0ull,   0ull},
15220         {"SGOUTNAK"                    ,        9,      1,      491,    "WO",   0,      0,      0ull,   0ull},
15221         {"CGOUTNAK"                    ,        10,     1,      491,    "WO",   0,      0,      0ull,   0ull},
15222         {"PWRONPRGDONE"                ,        11,     1,      491,    "R/W",  0,      0,      0ull,   0ull},
15223         {"RESERVED_12_31"              ,        12,     20,     491,    "RAZ",  1,      1,      0,      0},
15224         {"MPS"                         ,        0,      11,     492,    "R/W",  0,      0,      0ull,   0ull},
15225         {"NEXTEP"                      ,        11,     4,      492,    "R/W",  0,      0,      0ull,   0ull},
15226         {"USBACTEP"                    ,        15,     1,      492,    "R/W",  0,      0,      1ull,   0ull},
15227         {"DPID"                        ,        16,     1,      492,    "RO",   0,      0,      0ull,   0ull},
15228         {"NAKSTS"                      ,        17,     1,      492,    "RO",   0,      0,      0ull,   0ull},
15229         {"EPTYPE"                      ,        18,     2,      492,    "R/W",  0,      0,      0ull,   0ull},
15230         {"RESERVED_20_20"              ,        20,     1,      492,    "RAZ",  1,      1,      0,      0},
15231         {"STALL"                       ,        21,     1,      492,    "R/W",  0,      0,      0ull,   0ull},
15232         {"TXFNUM"                      ,        22,     4,      492,    "R/W",  0,      0,      0ull,   0ull},
15233         {"CNAK"                        ,        26,     1,      492,    "WO",   0,      0,      0ull,   0ull},
15234         {"SNAK"                        ,        27,     1,      492,    "WO",   0,      0,      0ull,   0ull},
15235         {"SETD0PID"                    ,        28,     1,      492,    "WO",   0,      0,      0ull,   0ull},
15236         {"SETD1PID"                    ,        29,     1,      492,    "WO",   0,      0,      0ull,   0ull},
15237         {"EPDIS"                       ,        30,     1,      492,    "R/W",  0,      0,      0ull,   0ull},
15238         {"EPENA"                       ,        31,     1,      492,    "R/W",  0,      0,      0ull,   0ull},
15239         {"XFERCOMPL"                   ,        0,      1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
15240         {"EPDISBLD"                    ,        1,      1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
15241         {"AHBERR"                      ,        2,      1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
15242         {"TIMEOUT"                     ,        3,      1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
15243         {"INTKNTXFEMP"                 ,        4,      1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
15244         {"INTKNEPMIS"                  ,        5,      1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
15245         {"INEPNAKEFF"                  ,        6,      1,      493,    "RO",   0,      0,      0ull,   0ull},
15246         {"RESERVED_7_31"               ,        7,      25,     493,    "RAZ",  1,      1,      0,      0},
15247         {"XFERCOMPLMSK"                ,        0,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
15248         {"EPDISBLDMSK"                 ,        1,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
15249         {"AHBERRMSK"                   ,        2,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
15250         {"TIMEOUTMSK"                  ,        3,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
15251         {"INTKNTXFEMPMSK"              ,        4,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
15252         {"INTKNEPMISMSK"               ,        5,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
15253         {"INEPNAKEFFMSK"               ,        6,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
15254         {"RESERVED_7_31"               ,        7,      25,     494,    "RAZ",  1,      1,      0,      0},
15255         {"XFERSIZE"                    ,        0,      19,     495,    "R/W",  0,      0,      0ull,   0ull},
15256         {"PKTCNT"                      ,        19,     10,     495,    "R/W",  0,      0,      0ull,   0ull},
15257         {"MC"                          ,        29,     2,      495,    "R/W",  0,      0,      0ull,   0ull},
15258         {"RESERVED_31_31"              ,        31,     1,      495,    "RAZ",  1,      1,      0,      0},
15259         {"MPS"                         ,        0,      11,     496,    "R/W",  0,      0,      0ull,   0ull},
15260         {"RESERVED_11_14"              ,        11,     4,      496,    "RAZ",  0,      0,      0ull,   0ull},
15261         {"USBACTEP"                    ,        15,     1,      496,    "R/W",  0,      0,      1ull,   0ull},
15262         {"DPID"                        ,        16,     1,      496,    "RO",   0,      0,      0ull,   0ull},
15263         {"NAKSTS"                      ,        17,     1,      496,    "RO",   0,      0,      0ull,   0ull},
15264         {"EPTYPE"                      ,        18,     2,      496,    "R/W",  0,      0,      0ull,   0ull},
15265         {"SNP"                         ,        20,     1,      496,    "R/W",  0,      0,      0ull,   0ull},
15266         {"STALL"                       ,        21,     1,      496,    "R/W",  0,      0,      0ull,   0ull},
15267         {"RESERVED_22_25"              ,        22,     4,      496,    "RAZ",  1,      1,      0,      0},
15268         {"CNAK"                        ,        26,     1,      496,    "WO",   0,      0,      0ull,   0ull},
15269         {"SNAK"                        ,        27,     1,      496,    "WO",   0,      0,      0ull,   0ull},
15270         {"SETD0PID"                    ,        28,     1,      496,    "WO",   0,      0,      0ull,   0ull},
15271         {"SETD1PID"                    ,        29,     1,      496,    "WO",   0,      0,      0ull,   0ull},
15272         {"EPDIS"                       ,        30,     1,      496,    "R/W",  0,      0,      0ull,   0ull},
15273         {"EPENA"                       ,        31,     1,      496,    "R/W",  0,      0,      0ull,   0ull},
15274         {"XFERCOMPL"                   ,        0,      1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
15275         {"EPDISBLD"                    ,        1,      1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
15276         {"AHBERR"                      ,        2,      1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
15277         {"SETUP"                       ,        3,      1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
15278         {"OUTTKNEPDIS"                 ,        4,      1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
15279         {"RESERVED_5_31"               ,        5,      27,     497,    "RAZ",  1,      1,      0,      0},
15280         {"XFERCOMPLMSK"                ,        0,      1,      498,    "R/W",  0,      0,      0ull,   0ull},
15281         {"EPDISBLDMSK"                 ,        1,      1,      498,    "R/W",  0,      0,      0ull,   0ull},
15282         {"AHBERRMSK"                   ,        2,      1,      498,    "R/W",  0,      0,      0ull,   0ull},
15283         {"SETUPMSK"                    ,        3,      1,      498,    "R/W",  0,      0,      0ull,   0ull},
15284         {"OUTTKNEPDISMSK"              ,        4,      1,      498,    "R/W",  0,      0,      0ull,   0ull},
15285         {"RESERVED_5_31"               ,        5,      27,     498,    "RAZ",  1,      1,      0,      0},
15286         {"XFERSIZE"                    ,        0,      19,     499,    "R/W",  0,      0,      0ull,   0ull},
15287         {"PKTCNT"                      ,        19,     10,     499,    "R/W",  0,      0,      0ull,   0ull},
15288         {"MC"                          ,        29,     2,      499,    "R/W",  0,      0,      0ull,   0ull},
15289         {"RESERVED_31_31"              ,        31,     1,      499,    "RAZ",  1,      1,      0,      0},
15290         {"DPTXFSTADDR"                 ,        0,      16,     500,    "RO",   0,      0,      0ull,   0ull},
15291         {"DPTXFSIZE"                   ,        16,     16,     500,    "RO",   0,      0,      1896ull,        1896ull},
15292         {"SUSPSTS"                     ,        0,      1,      501,    "RO",   0,      0,      0ull,   0ull},
15293         {"ENUMSPD"                     ,        1,      2,      501,    "RO",   0,      0,      0ull,   0ull},
15294         {"ERRTICERR"                   ,        3,      1,      501,    "RO",   0,      0,      0ull,   0ull},
15295         {"RESERVED_4_7"                ,        4,      4,      501,    "RAZ",  1,      1,      0,      0},
15296         {"SOFFN"                       ,        8,      14,     501,    "RO",   0,      0,      0ull,   0ull},
15297         {"RESERVED_22_31"              ,        22,     10,     501,    "RAZ",  1,      1,      0,      0},
15298         {"INTKNWPTR"                   ,        0,      5,      502,    "RO",   0,      0,      0ull,   0ull},
15299         {"RESERVED_5_6"                ,        5,      2,      502,    "RAZ",  1,      1,      0,      0},
15300         {"WRAPBIT"                     ,        7,      1,      502,    "RO",   0,      0,      0ull,   0ull},
15301         {"EPTKN"                       ,        8,      24,     502,    "RO",   0,      0,      0ull,   0ull},
15302         {"EPTKN"                       ,        0,      32,     503,    "RO",   0,      0,      0ull,   0ull},
15303         {"EPTKN"                       ,        0,      32,     504,    "RO",   0,      0,      0ull,   0ull},
15304         {"EPTKN"                       ,        0,      32,     505,    "RO",   0,      0,      0ull,   0ull},
15305         {"GLBLINTRMSK"                 ,        0,      1,      506,    "R/W",  0,      0,      0ull,   1ull},
15306         {"HBSTLEN"                     ,        1,      4,      506,    "R/W",  0,      0,      0ull,   0ull},
15307         {"DMAEN"                       ,        5,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
15308         {"RESERVED_6_6"                ,        6,      1,      506,    "RAZ",  1,      1,      0,      0},
15309         {"NPTXFEMPLVL"                 ,        7,      1,      506,    "R/W",  0,      0,      0ull,   1ull},
15310         {"PTXFEMPLVL"                  ,        8,      1,      506,    "R/W",  0,      0,      0ull,   1ull},
15311         {"RESERVED_9_31"               ,        9,      23,     506,    "RAZ",  1,      1,      0,      0},
15312         {"EPDIR"                       ,        0,      32,     507,    "RO",   0,      0,      0ull,   0ull},
15313         {"OTGMODE"                     ,        0,      3,      508,    "RO",   0,      0,      2ull,   2ull},
15314         {"OTGARCH"                     ,        3,      2,      508,    "RO",   0,      0,      1ull,   1ull},
15315         {"SINGPNT"                     ,        5,      1,      508,    "RO",   0,      0,      0ull,   0ull},
15316         {"HSPHYTYPE"                   ,        6,      2,      508,    "RO",   0,      0,      1ull,   1ull},
15317         {"FSPHYTYPE"                   ,        8,      2,      508,    "RO",   0,      0,      0ull,   0ull},
15318         {"NUMDEVEPS"                   ,        10,     4,      508,    "RO",   0,      0,      4ull,   4ull},
15319         {"NUMHSTCHNL"                  ,        14,     4,      508,    "RO",   0,      0,      7ull,   7ull},
15320         {"PERIOSUPPORT"                ,        18,     1,      508,    "RO",   0,      0,      1ull,   1ull},
15321         {"DYNFIFOSIZING"               ,        19,     1,      508,    "RO",   0,      0,      1ull,   1ull},
15322         {"RESERVED_20_21"              ,        20,     2,      508,    "RAZ",  1,      1,      0,      0},
15323         {"NPTXQDEPTH"                  ,        22,     2,      508,    "RO",   0,      0,      2ull,   2ull},
15324         {"PTXQDEPTH"                   ,        24,     2,      508,    "RO",   0,      0,      2ull,   2ull},
15325         {"TKNQDEPTH"                   ,        26,     5,      508,    "RO",   0,      0,      30ull,  30ull},
15326         {"RESERVED_31_31"              ,        31,     1,      508,    "RAZ",  1,      1,      0,      0},
15327         {"XFERSIZEWIDTH"               ,        0,      4,      509,    "RO",   0,      0,      8ull,   8ull},
15328         {"PKTSIZEWIDTH"                ,        4,      3,      509,    "RO",   0,      0,      6ull,   6ull},
15329         {"OTGEN"                       ,        7,      1,      509,    "RO",   0,      0,      1ull,   1ull},
15330         {"I2C_SELECTION"               ,        8,      1,      509,    "RO",   0,      0,      0ull,   0ull},
15331         {"VENDOR_CONTROL_INTERFACE_SUPPORT",    9,      1,      509,    "RO",   0,      0,      0ull,   0ull},
15332         {"OPTFEATURE"                  ,        10,     1,      509,    "RO",   0,      0,      1ull,   1ull},
15333         {"RSTTYPE"                     ,        11,     1,      509,    "RO",   0,      0,      1ull,   1ull},
15334         {"AHBPHYSYNC"                  ,        12,     1,      509,    "RO",   0,      0,      0ull,   0ull},
15335         {"RESERVED_13_15"              ,        13,     3,      509,    "RAZ",  1,      1,      0,      0},
15336         {"DFIFODEPTH"                  ,        16,     16,     509,    "RO",   0,      0,      1824ull,        1824ull},
15337         {"NUMDEVPERIOEPS"              ,        0,      4,      510,    "RO",   0,      0,      4ull,   4ull},
15338         {"ENABLEPWROPT"                ,        4,      1,      510,    "RO",   0,      0,      0ull,   0ull},
15339         {"AHBFREQ"                     ,        5,      1,      510,    "RO",   0,      0,      1ull,   1ull},
15340         {"RESERVED_6_13"               ,        6,      8,      510,    "RAZ",  1,      1,      0,      0},
15341         {"PHYDATAWIDTH"                ,        14,     2,      510,    "RO",   0,      0,      1ull,   1ull},
15342         {"NUMCTLEPS"                   ,        16,     4,      510,    "RO",   0,      0,      4ull,   4ull},
15343         {"IDDGFLTR"                    ,        20,     1,      510,    "RO",   0,      0,      0ull,   0ull},
15344         {"VBUSVALIDFLTR"               ,        21,     1,      510,    "RO",   0,      0,      0ull,   0ull},
15345         {"AVALIDFLTR"                  ,        22,     1,      510,    "RO",   0,      0,      1ull,   1ull},
15346         {"BVALIDFLTR"                  ,        23,     1,      510,    "RO",   0,      0,      1ull,   1ull},
15347         {"SESSENDFLTR"                 ,        24,     1,      510,    "RO",   0,      0,      1ull,   1ull},
15348         {"RESERVED_25_31"              ,        25,     7,      510,    "RAZ",  1,      1,      0,      0},
15349         {"RESERVED_0_0"                ,        0,      1,      511,    "RAZ",  1,      1,      0,      0},
15350         {"MODEMISMSK"                  ,        1,      1,      511,    "R/W",  0,      0,      0ull,   0ull},
15351         {"OTGINTMSK"                   ,        2,      1,      511,    "R/W",  0,      0,      0ull,   0ull},
15352         {"SOFMSK"                      ,        3,      1,      511,    "R/W",  0,      0,      0ull,   0ull},
15353         {"RXFLVLMSK"                   ,        4,      1,      511,    "R/W",  0,      0,      0ull,   0ull},
15354         {"NPTXFEMPMSK"                 ,        5,      1,      511,    "R/W",  0,      0,      0ull,   0ull},
15355         {"GINNAKEFFMSK"                ,        6,      1,      511,    "R/W",  0,      0,      0ull,   0ull},
15356         {"GOUTNAKEFFMSK"               ,        7,      1,      511,    "R/W",  0,      0,      0ull,   0ull},
15357         {"ULPICKINTMSK"                ,        8,      1,      511,    "R/W",  0,      0,      0ull,   0ull},
15358         {"I2CINT"                      ,        9,      1,      511,    "R/W",  0,      0,      0ull,   0ull},
15359         {"ERLYSUSPMSK"                 ,        10,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15360         {"USBSUSPMSK"                  ,        11,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15361         {"USBRSTMSK"                   ,        12,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15362         {"ENUMDONEMSK"                 ,        13,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15363         {"ISOOUTDROPMSK"               ,        14,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15364         {"EOPFMSK"                     ,        15,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15365         {"RESERVED_16_16"              ,        16,     1,      511,    "RAZ",  1,      1,      0,      0},
15366         {"EPMISMSK"                    ,        17,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15367         {"INEPINTMSK"                  ,        18,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15368         {"OEPINTMSK"                   ,        19,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15369         {"INCOMPISOINMSK"              ,        20,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15370         {"INCOMPLPMSK"                 ,        21,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15371         {"FETSUSPMSK"                  ,        22,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15372         {"RESERVED_23_23"              ,        23,     1,      511,    "RAZ",  1,      1,      0,      0},
15373         {"PRTINTMSK"                   ,        24,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15374         {"HCHINTMSK"                   ,        25,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15375         {"PTXFEMPMSK"                  ,        26,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15376         {"RESERVED_27_27"              ,        27,     1,      511,    "RAZ",  1,      1,      0,      0},
15377         {"CONIDSTSCHNGMSK"             ,        28,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15378         {"DISCONNINTMSK"               ,        29,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15379         {"SESSREQINTMSK"               ,        30,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15380         {"WKUPINTMSK"                  ,        31,     1,      511,    "R/W",  0,      0,      0ull,   0ull},
15381         {"CURMOD"                      ,        0,      1,      512,    "RO",   0,      0,      0ull,   0ull},
15382         {"MODEMIS"                     ,        1,      1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15383         {"OTGINT"                      ,        2,      1,      512,    "RO",   0,      0,      0ull,   0ull},
15384         {"SOF"                         ,        3,      1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15385         {"RXFLVL"                      ,        4,      1,      512,    "RO",   0,      0,      0ull,   0ull},
15386         {"NPTXFEMP"                    ,        5,      1,      512,    "RO",   0,      0,      0ull,   0ull},
15387         {"GINNAKEFF"                   ,        6,      1,      512,    "RO",   0,      0,      0ull,   0ull},
15388         {"GOUTNAKEFF"                  ,        7,      1,      512,    "RO",   0,      0,      0ull,   0ull},
15389         {"ULPICKINT"                   ,        8,      1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15390         {"I2CINT"                      ,        9,      1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15391         {"ERLYSUSP"                    ,        10,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15392         {"USBSUSP"                     ,        11,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15393         {"USBRST"                      ,        12,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15394         {"ENUMDONE"                    ,        13,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15395         {"ISOOUTDROP"                  ,        14,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15396         {"EOPF"                        ,        15,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15397         {"RESERVED_16_16"              ,        16,     1,      512,    "RAZ",  1,      1,      0,      0},
15398         {"EPMIS"                       ,        17,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15399         {"IEPINT"                      ,        18,     1,      512,    "RO",   0,      0,      0ull,   0ull},
15400         {"OEPINT"                      ,        19,     1,      512,    "RO",   0,      0,      0ull,   0ull},
15401         {"INCOMPISOIN"                 ,        20,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15402         {"INCOMPLP"                    ,        21,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15403         {"FETSUSP"                     ,        22,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15404         {"RESERVED_23_23"              ,        23,     1,      512,    "RAZ",  1,      1,      0,      0},
15405         {"PRTINT"                      ,        24,     1,      512,    "RO",   0,      0,      0ull,   0ull},
15406         {"HCHINT"                      ,        25,     1,      512,    "RO",   0,      0,      0ull,   0ull},
15407         {"PTXFEMP"                     ,        26,     1,      512,    "RO",   0,      0,      0ull,   0ull},
15408         {"RESERVED_27_27"              ,        27,     1,      512,    "RAZ",  1,      1,      0,      0},
15409         {"CONIDSTSCHNG"                ,        28,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15410         {"DISCONNINT"                  ,        29,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15411         {"SESSREQINT"                  ,        30,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15412         {"WKUPINT"                     ,        31,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
15413         {"NPTXFSTADDR"                 ,        0,      16,     513,    "R/W",  0,      0,      1824ull,        456ull},
15414         {"NPTXFDEP"                    ,        16,     16,     513,    "R/W",  0,      0,      1824ull,        912ull},
15415         {"NPTXFSPCAVAIL"               ,        0,      16,     514,    "RO",   0,      0,      0ull,   0ull},
15416         {"NPTXQSPCAVAIL"               ,        16,     8,      514,    "RO",   0,      0,      0ull,   0ull},
15417         {"NPTXQTOP"                    ,        24,     7,      514,    "RO",   0,      0,      0ull,   0ull},
15418         {"RESERVED_31_31"              ,        31,     1,      514,    "RAZ",  1,      1,      0,      0},
15419         {"SESREQSCS"                   ,        0,      1,      515,    "R/W",  0,      0,      0ull,   0ull},
15420         {"SESREQ"                      ,        1,      1,      515,    "R/W",  0,      0,      0ull,   0ull},
15421         {"RESERVED_2_7"                ,        2,      6,      515,    "RAZ",  1,      1,      0,      0},
15422         {"HSTNEGSCS"                   ,        8,      1,      515,    "R/W",  0,      0,      0ull,   0ull},
15423         {"HNPREQ"                      ,        9,      1,      515,    "R/W",  0,      0,      0ull,   0ull},
15424         {"HSTSETHNPEN"                 ,        10,     1,      515,    "R/W",  0,      0,      0ull,   0ull},
15425         {"DEVHNPEN"                    ,        11,     1,      515,    "R/W",  0,      0,      0ull,   0ull},
15426         {"RESERVED_12_15"              ,        12,     4,      515,    "RAZ",  1,      1,      0,      0},
15427         {"CONIDSTS"                    ,        16,     1,      515,    "RO",   1,      1,      0,      0},
15428         {"DBNCTIME"                    ,        17,     1,      515,    "RO",   0,      0,      0ull,   0ull},
15429         {"ASESVLD"                     ,        18,     1,      515,    "RO",   1,      1,      0,      0},
15430         {"BSESVLD"                     ,        19,     1,      515,    "RO",   1,      1,      0,      0},
15431         {"RESERVED_20_31"              ,        20,     12,     515,    "RAZ",  1,      1,      0,      0},
15432         {"RESERVED_0_1"                ,        0,      2,      516,    "RAZ",  1,      1,      0,      0},
15433         {"SESENDDET"                   ,        2,      1,      516,    "R/W1C",        0,      0,      0ull,   0ull},
15434         {"RESERVED_3_7"                ,        3,      5,      516,    "RAZ",  1,      1,      0,      0},
15435         {"SESREQSUCSTSCHNG"            ,        8,      1,      516,    "R/W1C",        0,      0,      0ull,   0ull},
15436         {"HSTNEGSUCSTSCHNG"            ,        9,      1,      516,    "R/W1C",        0,      0,      0ull,   0ull},
15437         {"RESERVED_10_16"              ,        10,     7,      516,    "RAZ",  1,      1,      0,      0},
15438         {"HSTNEGDET"                   ,        17,     1,      516,    "R/W1C",        0,      0,      0ull,   0ull},
15439         {"ADEVTOUTCHG"                 ,        18,     1,      516,    "R/W1C",        0,      0,      0ull,   0ull},
15440         {"DBNCEDONE"                   ,        19,     1,      516,    "R/W1C",        0,      0,      0ull,   0ull},
15441         {"RESERVED_20_31"              ,        20,     12,     516,    "RAZ",  1,      1,      0,      0},
15442         {"CSFTRST"                     ,        0,      1,      517,    "R/W",  0,      0,      0ull,   0ull},
15443         {"HSFTRST"                     ,        1,      1,      517,    "R/W",  0,      0,      0ull,   0ull},
15444         {"FRMCNTRRST"                  ,        2,      1,      517,    "R/W",  0,      0,      0ull,   0ull},
15445         {"INTKNQFLSH"                  ,        3,      1,      517,    "R/W",  0,      0,      0ull,   0ull},
15446         {"RXFFLSH"                     ,        4,      1,      517,    "R/W",  0,      0,      0ull,   0ull},
15447         {"TXFFLSH"                     ,        5,      1,      517,    "R/W",  0,      0,      0ull,   0ull},
15448         {"TXFNUM"                      ,        6,      5,      517,    "R/W",  0,      0,      0ull,   0ull},
15449         {"RESERVED_11_29"              ,        11,     19,     517,    "RAZ",  1,      1,      0,      0},
15450         {"DMAREQ"                      ,        30,     1,      517,    "RO",   0,      0,      0ull,   0ull},
15451         {"AHBIDLE"                     ,        31,     1,      517,    "RO",   0,      0,      1ull,   1ull},
15452         {"RXFDEP"                      ,        0,      16,     518,    "R/W",  0,      0,      1824ull,        456ull},
15453         {"RESERVED_16_31"              ,        16,     16,     518,    "RAZ",  1,      1,      0,      0},
15454         {"EPNUM"                       ,        0,      4,      519,    "RO",   0,      0,      0ull,   0ull},
15455         {"BCNT"                        ,        4,      11,     519,    "RO",   0,      0,      0ull,   0ull},
15456         {"DPID"                        ,        15,     2,      519,    "RO",   0,      0,      0ull,   0ull},
15457         {"PKTSTS"                      ,        17,     4,      519,    "RO",   0,      0,      0ull,   0ull},
15458         {"FN"                          ,        21,     4,      519,    "RO",   0,      0,      0ull,   0ull},
15459         {"RESERVED_25_31"              ,        25,     7,      519,    "RAZ",  1,      1,      0,      0},
15460         {"CHNUM"                       ,        0,      4,      520,    "RO",   0,      0,      0ull,   0ull},
15461         {"BCNT"                        ,        4,      11,     520,    "RO",   0,      0,      0ull,   0ull},
15462         {"DPID"                        ,        15,     2,      520,    "RO",   0,      0,      0ull,   0ull},
15463         {"PKTSTS"                      ,        17,     4,      520,    "RO",   0,      0,      0ull,   0ull},
15464         {"RESERVED_21_31"              ,        21,     11,     520,    "RAZ",  1,      1,      0,      0},
15465         {"EPNUM"                       ,        0,      4,      521,    "RO",   0,      0,      0ull,   0ull},
15466         {"BCNT"                        ,        4,      11,     521,    "RO",   0,      0,      0ull,   0ull},
15467         {"DPID"                        ,        15,     2,      521,    "RO",   0,      0,      0ull,   0ull},
15468         {"PKTSTS"                      ,        17,     4,      521,    "RO",   0,      0,      0ull,   0ull},
15469         {"FN"                          ,        21,     4,      521,    "RO",   0,      0,      0ull,   0ull},
15470         {"RESERVED_25_31"              ,        25,     7,      521,    "RAZ",  1,      1,      0,      0},
15471         {"CHNUM"                       ,        0,      4,      522,    "RO",   0,      0,      0ull,   0ull},
15472         {"BCNT"                        ,        4,      11,     522,    "RO",   0,      0,      0ull,   0ull},
15473         {"DPID"                        ,        15,     2,      522,    "RO",   0,      0,      0ull,   0ull},
15474         {"PKTSTS"                      ,        17,     4,      522,    "RO",   0,      0,      0ull,   0ull},
15475         {"RESERVED_21_31"              ,        21,     11,     522,    "RAZ",  1,      1,      0,      0},
15476         {"SYNOPSYSID"                  ,        0,      32,     523,    "RO",   1,      1,      0,      0},
15477         {"TOUTCAL"                     ,        0,      3,      524,    "R/W",  0,      0,      0ull,   0ull},
15478         {"PHYIF"                       ,        3,      1,      524,    "RO",   0,      0,      1ull,   1ull},
15479         {"ULPI_UTMI_SEL"               ,        4,      1,      524,    "RO",   0,      0,      0ull,   0ull},
15480         {"FSINTF"                      ,        5,      1,      524,    "WO",   0,      0,      0ull,   0ull},
15481         {"PHYSEL"                      ,        6,      1,      524,    "WO",   0,      0,      0ull,   0ull},
15482         {"DDRSEL"                      ,        7,      1,      524,    "R/W",  0,      0,      0ull,   0ull},
15483         {"SRPCAP"                      ,        8,      1,      524,    "RO",   0,      0,      0ull,   0ull},
15484         {"HNPCAP"                      ,        9,      1,      524,    "RO",   0,      0,      0ull,   0ull},
15485         {"USBTRDTIM"                   ,        10,     4,      524,    "R/W",  0,      0,      5ull,   5ull},
15486         {"RESERVED_14_14"              ,        14,     1,      524,    "RAZ",  1,      1,      0,      0},
15487         {"PHYLPWRCLKSEL"               ,        15,     1,      524,    "R/W",  0,      0,      0ull,   0ull},
15488         {"OTGI2CSEL"                   ,        16,     1,      524,    "RO",   0,      0,      0ull,   0ull},
15489         {"RESERVED_17_31"              ,        17,     15,     524,    "RAZ",  1,      1,      0,      0},
15490         {"HAINT"                       ,        0,      16,     525,    "RO",   0,      0,      0ull,   0ull},
15491         {"RESERVED_16_31"              ,        16,     16,     525,    "RAZ",  1,      1,      0,      0},
15492         {"HAINTMSK"                    ,        0,      16,     526,    "R/W",  0,      0,      0ull,   0ull},
15493         {"RESERVED_16_31"              ,        16,     16,     526,    "RAZ",  1,      1,      0,      0},
15494         {"MPS"                         ,        0,      11,     527,    "R/W",  0,      0,      0ull,   0ull},
15495         {"EPNUM"                       ,        11,     4,      527,    "R/W",  0,      0,      0ull,   0ull},
15496         {"EPDIR"                       ,        15,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
15497         {"RESERVED_16_16"              ,        16,     1,      527,    "RAZ",  1,      1,      0,      0},
15498         {"LSPDDEV"                     ,        17,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
15499         {"EPTYPE"                      ,        18,     2,      527,    "R/W",  0,      0,      0ull,   0ull},
15500         {"EC"                          ,        20,     2,      527,    "R/W",  0,      0,      0ull,   0ull},
15501         {"DEVADDR"                     ,        22,     7,      527,    "R/W",  0,      0,      0ull,   0ull},
15502         {"ODDFRM"                      ,        29,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
15503         {"CHDIS"                       ,        30,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
15504         {"CHENA"                       ,        31,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
15505         {"FSLSPCLKSEL"                 ,        0,      2,      528,    "R/W",  0,      0,      0ull,   0ull},
15506         {"FSLSSUPP"                    ,        2,      1,      528,    "R/W",  0,      0,      0ull,   0ull},
15507         {"RESERVED_3_31"               ,        3,      29,     528,    "RAZ",  1,      1,      0,      0},
15508         {"XFERCOMPL"                   ,        0,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15509         {"CHHLTD"                      ,        1,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15510         {"AHBERR"                      ,        2,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15511         {"STALL"                       ,        3,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15512         {"NAK"                         ,        4,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15513         {"ACK"                         ,        5,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15514         {"NYET"                        ,        6,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15515         {"XACTERR"                     ,        7,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15516         {"BBLERR"                      ,        8,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15517         {"FRMOVRUN"                    ,        9,      1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15518         {"DATATGLERR"                  ,        10,     1,      529,    "R/W1C",        0,      0,      0ull,   0ull},
15519         {"RESERVED_11_31"              ,        11,     21,     529,    "RAZ",  1,      1,      0,      0},
15520         {"XFERCOMPLMSK"                ,        0,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15521         {"CHHLTDMSK"                   ,        1,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15522         {"AHBERRMSK"                   ,        2,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15523         {"STALLMSK"                    ,        3,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15524         {"NAKMSK"                      ,        4,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15525         {"ACKMSK"                      ,        5,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15526         {"NYETMSK"                     ,        6,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15527         {"XACTERRMSK"                  ,        7,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15528         {"BBLERRMSK"                   ,        8,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15529         {"FRMOVRUNMSK"                 ,        9,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
15530         {"DATATGLERRMSK"               ,        10,     1,      530,    "R/W",  0,      0,      0ull,   0ull},
15531         {"RESERVED_11_31"              ,        11,     21,     530,    "RAZ",  1,      1,      0,      0},
15532         {"PRTADDR"                     ,        0,      7,      531,    "R/W",  0,      0,      0ull,   0ull},
15533         {"HUBADDR"                     ,        7,      7,      531,    "R/W",  0,      0,      0ull,   0ull},
15534         {"XACTPOS"                     ,        14,     2,      531,    "R/W",  0,      0,      0ull,   0ull},
15535         {"COMPSPLT"                    ,        16,     1,      531,    "R/W",  0,      0,      0ull,   0ull},
15536         {"RESERVED_17_30"              ,        17,     14,     531,    "RAZ",  1,      1,      0,      0},
15537         {"SPLTENA"                     ,        31,     1,      531,    "R/W",  0,      0,      0ull,   0ull},
15538         {"XFERSIZE"                    ,        0,      19,     532,    "R/W",  0,      0,      0ull,   0ull},
15539         {"PKTCNT"                      ,        19,     10,     532,    "R/W",  0,      0,      0ull,   0ull},
15540         {"PID"                         ,        29,     2,      532,    "R/W",  0,      0,      0ull,   0ull},
15541         {"DOPNG"                       ,        31,     1,      532,    "R/W",  0,      0,      0ull,   0ull},
15542         {"FRINT"                       ,        0,      16,     533,    "R/W",  0,      0,      2959ull,        3750ull},
15543         {"RESERVED_16_31"              ,        16,     16,     533,    "RAZ",  1,      1,      0,      0},
15544         {"FRNUM"                       ,        0,      16,     534,    "RO",   0,      0,      16383ull,       0ull},
15545         {"FRREM"                       ,        16,     16,     534,    "RO",   0,      0,      0ull,   0ull},
15546         {"PRTCONNSTS"                  ,        0,      1,      535,    "RO",   0,      0,      0ull,   0ull},
15547         {"PRTCONNDET"                  ,        1,      1,      535,    "R/W1C",        0,      0,      0ull,   0ull},
15548         {"PRTENA"                      ,        2,      1,      535,    "R/W1C",        0,      0,      0ull,   0ull},
15549         {"PRTENCHNG"                   ,        3,      1,      535,    "R/W1C",        0,      0,      0ull,   0ull},
15550         {"PRTOVRCURRACT"               ,        4,      1,      535,    "RO",   0,      0,      0ull,   0ull},
15551         {"PRTOVRCURRCHNG"              ,        5,      1,      535,    "R/W1C",        0,      0,      0ull,   0ull},
15552         {"PRTRES"                      ,        6,      1,      535,    "R/W",  0,      0,      0ull,   0ull},
15553         {"PRTSUSP"                     ,        7,      1,      535,    "R/W",  0,      0,      0ull,   0ull},
15554         {"PRTRST"                      ,        8,      1,      535,    "R/W",  0,      0,      0ull,   0ull},
15555         {"RESERVED_9_9"                ,        9,      1,      535,    "RAZ",  1,      1,      0,      0},
15556         {"PRTLNSTS"                    ,        10,     2,      535,    "RO",   0,      0,      0ull,   0ull},
15557         {"PRTPWR"                      ,        12,     1,      535,    "R/W",  0,      0,      0ull,   0ull},
15558         {"PRTTSTCTL"                   ,        13,     4,      535,    "R/W",  0,      0,      0ull,   0ull},
15559         {"PRTSPD"                      ,        17,     2,      535,    "RO",   0,      0,      0ull,   0ull},
15560         {"RESERVED_19_31"              ,        19,     13,     535,    "RAZ",  1,      1,      0,      0},
15561         {"PTXFSTADDR"                  ,        0,      16,     536,    "R/W",  0,      0,      3648ull,        912ull},
15562         {"PTXFSIZE"                    ,        16,     16,     536,    "R/W",  0,      0,      1824ull,        456ull},
15563         {"PTXFSPCAVAIL"                ,        0,      16,     537,    "RO",   0,      0,      0ull,   0ull},
15564         {"PTXQSPCAVAIL"                ,        16,     8,      537,    "RO",   0,      0,      0ull,   0ull},
15565         {"PTXQTOP"                     ,        24,     8,      537,    "RO",   0,      0,      0ull,   0ull},
15566         {"DATA"                        ,        0,      32,     538,    "R/W",  0,      0,      0ull,   0ull},
15567         {"STOPPCLK"                    ,        0,      1,      539,    "R/W",  0,      0,      0ull,   0ull},
15568         {"GATEHCLK"                    ,        1,      1,      539,    "R/W",  0,      0,      0ull,   0ull},
15569         {"PWRCLMP"                     ,        2,      1,      539,    "R/W",  0,      0,      0ull,   0ull},
15570         {"RSTPDWNMODULE"               ,        3,      1,      539,    "R/W",  0,      0,      0ull,   0ull},
15571         {"PHYSUSPENDED"                ,        4,      1,      539,    "RO",   0,      0,      0ull,   0ull},
15572         {"RESERVED_5_31"               ,        5,      27,     539,    "RAZ",  1,      1,      0,      0},
15573         {"NOF_BIS"                     ,        0,      1,      540,    "RO",   0,      0,      0ull,   0ull},
15574         {"NIF_BIS"                     ,        1,      1,      540,    "RO",   0,      0,      0ull,   0ull},
15575         {"USBC_BIS"                    ,        2,      1,      540,    "RO",   0,      0,      0ull,   0ull},
15576         {"RESERVED_3_63"               ,        3,      61,     540,    "RAZ",  1,      1,      0,      0},
15577         {"DIVIDE"                      ,        0,      3,      541,    "R/W",  0,      0,      4ull,   4ull},
15578         {"HRST"                        ,        3,      1,      541,    "R/W",  0,      0,      0ull,   1ull},
15579         {"PRST"                        ,        4,      1,      541,    "R/W",  0,      0,      0ull,   1ull},
15580         {"ENABLE"                      ,        5,      1,      541,    "R/W",  0,      0,      1ull,   1ull},
15581         {"POR"                         ,        6,      1,      541,    "R/W",  0,      0,      1ull,   0ull},
15582         {"S_BIST"                      ,        7,      1,      541,    "R/W",  0,      0,      0ull,   1ull},
15583         {"SD_MODE"                     ,        8,      2,      541,    "R/W",  0,      0,      0ull,   0ull},
15584         {"CDIV_BYP"                    ,        10,     1,      541,    "R/W",  0,      0,      0ull,   0ull},
15585         {"P_C_SEL"                     ,        11,     2,      541,    "R/W",  0,      0,      2ull,   2ull},
15586         {"P_COM_ON"                    ,        13,     1,      541,    "R/W",  0,      0,      1ull,   1ull},
15587         {"P_XENBN"                     ,        14,     1,      541,    "R/W",  0,      0,      0ull,   0ull},
15588         {"P_RCLK"                      ,        15,     1,      541,    "R/W",  0,      0,      0ull,   0ull},
15589         {"P_X_ON"                      ,        16,     1,      541,    "R/W",  0,      0,      1ull,   1ull},
15590         {"HCLK_RST"                    ,        17,     1,      541,    "R/W",  0,      0,      1ull,   1ull},
15591         {"RESERVED_18_63"              ,        18,     46,     541,    "RAZ",  1,      1,      0,      0},
15592         {"L2C_EMOD"                    ,        0,      2,      542,    "R/W",  0,      0,      1ull,   1ull},
15593         {"INV_A2"                      ,        2,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
15594         {"DMA_TEST"                    ,        3,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
15595         {"DMA_STT"                     ,        4,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
15596         {"DMA_0PAG"                    ,        5,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
15597         {"RESERVED_6_63"               ,        6,      58,     542,    "RAZ",  1,      1,      0,      0},
15598         {"ADDR"                        ,        0,      36,     543,    "R/W",  0,      1,      0ull,   0},
15599         {"RESERVED_36_63"              ,        36,     28,     543,    "RAZ",  1,      1,      0,      0},
15600         {"ADDR"                        ,        0,      36,     544,    "R/W",  0,      1,      0ull,   0},
15601         {"RESERVED_36_63"              ,        36,     28,     544,    "RAZ",  1,      1,      0,      0},
15602         {"ADDR"                        ,        0,      36,     545,    "R/W",  0,      1,      0ull,   0},
15603         {"RESERVED_36_63"              ,        36,     28,     545,    "RAZ",  1,      1,      0,      0},
15604         {"ADDR"                        ,        0,      36,     546,    "R/W",  0,      1,      0ull,   0},
15605         {"RESERVED_36_63"              ,        36,     28,     546,    "RAZ",  1,      1,      0,      0},
15606         {"ADDR"                        ,        0,      36,     547,    "R/W",  0,      1,      0ull,   0},
15607         {"RESERVED_36_63"              ,        36,     28,     547,    "RAZ",  1,      1,      0,      0},
15608         {"ADDR"                        ,        0,      36,     548,    "R/W",  0,      1,      0ull,   0},
15609         {"RESERVED_36_63"              ,        36,     28,     548,    "RAZ",  1,      1,      0,      0},
15610         {"ADDR"                        ,        0,      36,     549,    "R/W",  0,      1,      0ull,   0},
15611         {"RESERVED_36_63"              ,        36,     28,     549,    "RAZ",  1,      1,      0,      0},
15612         {"ADDR"                        ,        0,      36,     550,    "R/W",  0,      1,      0ull,   0},
15613         {"RESERVED_36_63"              ,        36,     28,     550,    "RAZ",  1,      1,      0,      0},
15614         {"ADDR"                        ,        0,      36,     551,    "R/W",  0,      1,      0ull,   0},
15615         {"RESERVED_36_63"              ,        36,     28,     551,    "RAZ",  1,      1,      0,      0},
15616         {"ADDR"                        ,        0,      36,     552,    "R/W",  0,      1,      0ull,   0},
15617         {"RESERVED_36_63"              ,        36,     28,     552,    "RAZ",  1,      1,      0,      0},
15618         {"ADDR"                        ,        0,      36,     553,    "R/W",  0,      1,      0ull,   0},
15619         {"RESERVED_36_63"              ,        36,     28,     553,    "RAZ",  1,      1,      0,      0},
15620         {"ADDR"                        ,        0,      36,     554,    "R/W",  0,      1,      0ull,   0},
15621         {"RESERVED_36_63"              ,        36,     28,     554,    "RAZ",  1,      1,      0,      0},
15622         {"ADDR"                        ,        0,      36,     555,    "R/W",  0,      1,      0ull,   0},
15623         {"RESERVED_36_63"              ,        36,     28,     555,    "RAZ",  1,      1,      0,      0},
15624         {"ADDR"                        ,        0,      36,     556,    "R/W",  0,      1,      0ull,   0},
15625         {"RESERVED_36_63"              ,        36,     28,     556,    "RAZ",  1,      1,      0,      0},
15626         {"ADDR"                        ,        0,      36,     557,    "R/W",  0,      1,      0ull,   0},
15627         {"RESERVED_36_63"              ,        36,     28,     557,    "RAZ",  1,      1,      0,      0},
15628         {"ADDR"                        ,        0,      36,     558,    "R/W",  0,      1,      0ull,   0},
15629         {"RESERVED_36_63"              ,        36,     28,     558,    "RAZ",  1,      1,      0,      0},
15630         {"BURST"                       ,        0,      4,      559,    "R/W",  0,      0,      0ull,   0ull},
15631         {"CHANNEL"                     ,        4,      5,      559,    "R/W",  0,      0,      0ull,   0ull},
15632         {"COUNT"                       ,        9,      11,     559,    "R/W",  0,      0,      0ull,   0ull},
15633         {"F_ADDR"                      ,        20,     18,     559,    "R/W",  0,      0,      0ull,   0ull},
15634         {"REQ"                         ,        38,     1,      559,    "R/W1C",        0,      0,      0ull,   0ull},
15635         {"DONE"                        ,        39,     1,      559,    "R/W1C",        0,      0,      0ull,   0ull},
15636         {"RESERVED_40_63"              ,        40,     24,     559,    "RAZ",  1,      1,      0,      0},
15637         {"PR_PO_E"                     ,        0,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15638         {"PR_PU_F"                     ,        1,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15639         {"NR_PO_E"                     ,        2,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15640         {"NR_PU_F"                     ,        3,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15641         {"LR_PO_E"                     ,        4,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15642         {"LR_PU_F"                     ,        5,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15643         {"PT_PO_E"                     ,        6,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15644         {"PT_PU_F"                     ,        7,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15645         {"NT_PO_E"                     ,        8,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15646         {"NT_PU_F"                     ,        9,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
15647         {"LT_PO_E"                     ,        10,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15648         {"LT_PU_F"                     ,        11,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15649         {"DCRED_E"                     ,        12,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15650         {"DCRED_F"                     ,        13,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15651         {"L2C_S_E"                     ,        14,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15652         {"L2C_A_F"                     ,        15,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15653         {"L2_FI_E"                     ,        16,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15654         {"L2_FI_F"                     ,        17,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15655         {"RG_FI_E"                     ,        18,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15656         {"RG_FI_F"                     ,        19,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15657         {"RQ_Q2_F"                     ,        20,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15658         {"RQ_Q2_E"                     ,        21,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15659         {"RQ_Q3_F"                     ,        22,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15660         {"RQ_Q3_E"                     ,        23,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15661         {"UOD_PE"                      ,        24,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15662         {"UOD_PF"                      ,        25,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15663         {"N2U_PF"                      ,        26,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15664         {"N2U_PE"                      ,        27,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15665         {"U2N_D_PE"                    ,        28,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15666         {"U2N_D_PF"                    ,        29,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15667         {"U2N_C_PF"                    ,        30,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15668         {"U2N_C_PE"                    ,        31,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15669         {"LTL_F_PE"                    ,        32,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15670         {"LTL_F_PF"                    ,        33,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15671         {"ND4O_RPE"                    ,        34,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15672         {"ND4O_RPF"                    ,        35,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15673         {"ND4O_DPE"                    ,        36,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15674         {"ND4O_DPF"                    ,        37,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
15675         {"RESERVED_38_63"              ,        38,     26,     560,    "RAZ",  1,      1,      0,      0},
15676         {"PR_PO_E"                     ,        0,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15677         {"PR_PU_F"                     ,        1,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15678         {"NR_PO_E"                     ,        2,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15679         {"NR_PU_F"                     ,        3,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15680         {"LR_PO_E"                     ,        4,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15681         {"LR_PU_F"                     ,        5,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15682         {"PT_PO_E"                     ,        6,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15683         {"PT_PU_F"                     ,        7,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15684         {"NT_PO_E"                     ,        8,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15685         {"NT_PU_F"                     ,        9,      1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15686         {"LT_PO_E"                     ,        10,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15687         {"LT_PU_F"                     ,        11,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15688         {"DCRED_E"                     ,        12,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15689         {"DCRED_F"                     ,        13,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15690         {"L2C_S_E"                     ,        14,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15691         {"L2C_A_F"                     ,        15,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15692         {"LT_FI_E"                     ,        16,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15693         {"LT_FI_F"                     ,        17,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15694         {"RG_FI_E"                     ,        18,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15695         {"RG_FI_F"                     ,        19,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15696         {"RQ_Q2_F"                     ,        20,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15697         {"RQ_Q2_E"                     ,        21,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15698         {"RQ_Q3_F"                     ,        22,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15699         {"RQ_Q3_E"                     ,        23,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15700         {"UOD_PE"                      ,        24,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15701         {"UOD_PF"                      ,        25,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15702         {"N2U_PF"                      ,        26,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15703         {"N2U_PE"                      ,        27,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15704         {"U2N_D_PE"                    ,        28,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15705         {"U2N_D_PF"                    ,        29,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15706         {"U2N_C_PF"                    ,        30,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15707         {"U2N_C_PE"                    ,        31,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15708         {"LTL_F_PE"                    ,        32,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15709         {"LTL_F_PF"                    ,        33,     1,      561,    "R/W1C",        0,      0,      0ull,   0ull},
15710         {"ND4O_RPE"                    ,        34,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15711         {"ND4O_RPF"                    ,        35,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15712         {"ND4O_DPE"                    ,        36,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15713         {"ND4O_DPF"                    ,        37,     1,      561,    "R/W1C",        1,      0,      0,      0ull},
15714         {"RESERVED_38_63"              ,        38,     26,     561,    "RAZ",  1,      1,      0,      0},
15715         {"ATE_RESET"                   ,        0,      1,      562,    "R/W",  0,      0,      0ull,   0ull},
15716         {"TDATA_IN"                    ,        1,      8,      562,    "R/W",  0,      0,      0ull,   0ull},
15717         {"TADDR_IN"                    ,        9,      4,      562,    "R/W",  0,      0,      0ull,   0ull},
15718         {"TDATA_SEL"                   ,        13,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15719         {"BIST_ENB"                    ,        14,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15720         {"VTEST_ENB"                   ,        15,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15721         {"LOOP_ENB"                    ,        16,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15722         {"TX_BS_EN"                    ,        17,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15723         {"TX_BS_ENH"                   ,        18,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15724         {"TUNING"                      ,        19,     4,      562,    "R/W",  0,      0,      9ull,   0ull},
15725         {"HST_MODE"                    ,        23,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15726         {"DM_PULLD"                    ,        24,     1,      562,    "R/W",  0,      0,      1ull,   1ull},
15727         {"DP_PULLD"                    ,        25,     1,      562,    "R/W",  0,      0,      1ull,   1ull},
15728         {"TCLK"                        ,        26,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15729         {"USBP_BIST"                   ,        27,     1,      562,    "R/W",  0,      0,      1ull,   1ull},
15730         {"USBC_END"                    ,        28,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15731         {"DMA_BMODE"                   ,        29,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
15732         {"RESERVED_30_31"              ,        30,     2,      562,    "RAZ",  0,      0,      0ull,   0ull},
15733         {"TDATA_OUT"                   ,        32,     4,      562,    "RO",   1,      1,      0,      0},
15734         {"BIST_ERR"                    ,        36,     1,      562,    "RO",   0,      0,      0ull,   0ull},
15735         {"BIST_DONE"                   ,        37,     1,      562,    "RO",   0,      0,      0ull,   0ull},
15736         {"RESERVED_38_63"              ,        38,     26,     562,    "RAZ",  1,      1,      0,      0},
15737         {NULL,0,0,0,0,0,0,0,0}
15738 };
15739 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn38xx[] = {
15740          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
15741         {"cvmx_asx#_int_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      4,      0},
15742         {"cvmx_asx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      4,      4},
15743         {"cvmx_asx#_prt_loop"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      3,      8},
15744         {"cvmx_asx#_rld_bypass"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      2,      11},
15745         {"cvmx_asx#_rld_bypass_setting",        CVMX_CSR_DB_TYPE_RSL,   64,     8,      2,      13},
15746         {"cvmx_asx#_rld_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     3,      15},
15747         {"cvmx_asx#_rld_data_drv"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     12,     3,      18},
15748         {"cvmx_asx#_rld_fcram_mode"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     2,      21},
15749         {"cvmx_asx#_rld_nctl_strong"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     16,     2,      23},
15750         {"cvmx_asx#_rld_nctl_weak"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     18,     2,      25},
15751         {"cvmx_asx#_rld_pctl_strong"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     20,     2,      27},
15752         {"cvmx_asx#_rld_pctl_weak"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     22,     2,      29},
15753         {"cvmx_asx#_rld_setting"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     24,     2,      31},
15754         {"cvmx_asx#_rx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     26,     2,      33},
15755         {"cvmx_asx#_rx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     34,     2,      35},
15756         {"cvmx_asx#_rx_wol"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     36,     3,      37},
15757         {"cvmx_asx#_rx_wol_msk"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     38,     1,      40},
15758         {"cvmx_asx#_rx_wol_powok"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     40,     2,      41},
15759         {"cvmx_asx#_rx_wol_sig"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     42,     2,      43},
15760         {"cvmx_asx#_tx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     44,     2,      45},
15761         {"cvmx_asx#_tx_comp_byp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     52,     3,      47},
15762         {"cvmx_asx#_tx_hi_water#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     54,     2,      50},
15763         {"cvmx_asx#_tx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     62,     2,      52},
15764         {"cvmx_asx0_dbg_data_drv"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     64,     3,      54},
15765         {"cvmx_asx0_dbg_data_enable"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     65,     2,      57},
15766         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     66,     2,      59},
15767         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     67,     2,      61},
15768         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     68,     2,      63},
15769         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     69,     2,      65},
15770         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     70,     15,     67},
15771         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     103,    2,      82},
15772         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     136,    15,     84},
15773         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     169,    2,      99},
15774         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     170,    2,      101},
15775         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     186,    2,      103},
15776         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     202,    2,      105},
15777         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     203,    2,      107},
15778         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     204,    2,      109},
15779         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     205,    1,      111},
15780         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     221,    3,      112},
15781         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     222,    2,      115},
15782         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     223,    4,      117},
15783         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     224,    2,      121},
15784         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     225,    3,      123},
15785         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     229,    7,      126},
15786         {"cvmx_dbg_data"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     245,    7,      133},
15787         {"cvmx_dfa_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     246,    3,      140},
15788         {"cvmx_dfa_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     247,    10,     143},
15789         {"cvmx_dfa_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     248,    5,      153},
15790         {"cvmx_dfa_dbell"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     249,    2,      158},
15791         {"cvmx_dfa_difctl"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     250,    4,      160},
15792         {"cvmx_dfa_difrdptr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     251,    3,      164},
15793         {"cvmx_dfa_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     252,    21,     167},
15794         {"cvmx_dfa_memcfg0"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     253,    17,     188},
15795         {"cvmx_dfa_memcfg1"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     254,    11,     205},
15796         {"cvmx_dfa_memcfg2"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     255,    8,      216},
15797         {"cvmx_dfa_memfadr"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     256,    6,      224},
15798         {"cvmx_dfa_memfcr"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     257,    6,      230},
15799         {"cvmx_dfa_memrld"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     258,    2,      236},
15800         {"cvmx_dfa_ncbctl"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     259,    8,      238},
15801         {"cvmx_dfa_sbd_dbg0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     260,    1,      246},
15802         {"cvmx_dfa_sbd_dbg1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     261,    1,      247},
15803         {"cvmx_dfa_sbd_dbg2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     262,    1,      248},
15804         {"cvmx_dfa_sbd_dbg3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     263,    1,      249},
15805         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     264,    6,      250},
15806         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     265,    7,      256},
15807         {"cvmx_fpa_fpf#_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     266,    3,      263},
15808         {"cvmx_fpa_fpf#_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     273,    2,      266},
15809         {"cvmx_fpa_fpf0_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     280,    3,      268},
15810         {"cvmx_fpa_fpf0_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     281,    2,      271},
15811         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     282,    29,     273},
15812         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     283,    29,     302},
15813         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     284,    2,      331},
15814         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     292,    2,      333},
15815         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     300,    3,      335},
15816         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     301,    3,      338},
15817         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     302,    2,      341},
15818         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     303,    2,      343},
15819         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     304,    8,      345},
15820         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     306,    2,      353},
15821         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     308,    3,      355},
15822         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     310,    2,      358},
15823         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     312,    5,      360},
15824         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     320,    1,      365},
15825         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     328,    1,      366},
15826         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     336,    1,      367},
15827         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     344,    1,      368},
15828         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     352,    1,      369},
15829         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     360,    1,      370},
15830         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     368,    2,      371},
15831         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     376,    4,      373},
15832         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     384,    2,      377},
15833         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     392,    11,     379},
15834         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     400,    10,     390},
15835         {"cvmx_gmx#_rx#_frm_max"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     408,    2,      400},
15836         {"cvmx_gmx#_rx#_frm_min"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     416,    2,      402},
15837         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     424,    2,      404},
15838         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     432,    20,     406},
15839         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     440,    20,     426},
15840         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     448,    2,      446},
15841         {"cvmx_gmx#_rx#_rx_inbnd"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     456,    4,      448},
15842         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     464,    2,      452},
15843         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     472,    2,      454},
15844         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     480,    2,      456},
15845         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     488,    2,      458},
15846         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     496,    2,      460},
15847         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     504,    2,      462},
15848         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     512,    2,      464},
15849         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     520,    2,      466},
15850         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     528,    2,      468},
15851         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     536,    2,      470},
15852         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     544,    4,      472},
15853         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     552,    2,      476},
15854         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     560,    2,      478},
15855         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     568,    2,      480},
15856         {"cvmx_gmx#_rx_pass_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     576,    2,      482},
15857         {"cvmx_gmx#_rx_pass_map#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     578,    2,      484},
15858         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     610,    3,      486},
15859         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     612,    2,      489},
15860         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     614,    2,      491},
15861         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     622,    3,      493},
15862         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     624,    5,      496},
15863         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     632,    2,      501},
15864         {"cvmx_gmx#_tx#_clk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     640,    2,      503},
15865         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     648,    3,      505},
15866         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     656,    2,      508},
15867         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     664,    2,      510},
15868         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     672,    2,      512},
15869         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     680,    2,      514},
15870         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     688,    2,      516},
15871         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     696,    2,      518},
15872         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     704,    2,      520},
15873         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     712,    2,      522},
15874         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     720,    2,      524},
15875         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     728,    2,      526},
15876         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     736,    2,      528},
15877         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     744,    2,      530},
15878         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     752,    2,      532},
15879         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     760,    2,      534},
15880         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     768,    2,      536},
15881         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     776,    2,      538},
15882         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     784,    2,      540},
15883         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     792,    2,      542},
15884         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     800,    2,      544},
15885         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     808,    2,      546},
15886         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     810,    2,      548},
15887         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     812,    2,      550},
15888         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     814,    3,      552},
15889         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     816,    8,      555},
15890         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     818,    8,      563},
15891         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     820,    2,      571},
15892         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     822,    2,      573},
15893         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     824,    4,      575},
15894         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     826,    2,      579},
15895         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     828,    2,      581},
15896         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     830,    2,      583},
15897         {"cvmx_gmx#_tx_spi_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     832,    3,      585},
15898         {"cvmx_gmx#_tx_spi_drain"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     834,    2,      588},
15899         {"cvmx_gmx#_tx_spi_max"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     836,    3,      590},
15900         {"cvmx_gmx#_tx_spi_thresh"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     838,    2,      593},
15901         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     840,    7,      595},
15902         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     856,    2,      602},
15903         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     857,    2,      604},
15904         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     858,    2,      606},
15905         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     859,    2,      608},
15906         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     860,    19,     610},
15907         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     861,    6,      629},
15908         {"cvmx_iob_dwb_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     862,    3,      635},
15909         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     863,    3,      638},
15910         {"cvmx_iob_i2c_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     864,    3,      641},
15911         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     865,    5,      644},
15912         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     866,    5,      649},
15913         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     867,    1,      654},
15914         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     868,    1,      655},
15915         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     869,    5,      656},
15916         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     870,    5,      661},
15917         {"cvmx_iob_n2c_l2c_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     871,    3,      666},
15918         {"cvmx_iob_n2c_rsp_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     872,    3,      669},
15919         {"cvmx_iob_outb_com_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     873,    3,      672},
15920         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     874,    5,      675},
15921         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     875,    5,      680},
15922         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     876,    1,      685},
15923         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     877,    1,      686},
15924         {"cvmx_iob_outb_fpa_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     878,    3,      687},
15925         {"cvmx_iob_outb_req_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     879,    3,      690},
15926         {"cvmx_iob_p2c_req_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     880,    3,      693},
15927         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     881,    2,      696},
15928         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     882,    2,      698},
15929         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     883,    2,      700},
15930         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     884,    2,      702},
15931         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     885,    17,     704},
15932         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     886,    2,      721},
15933         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     887,    1,      723},
15934         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     888,    10,     724},
15935         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     889,    11,     734},
15936         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     890,    11,     745},
15937         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     891,    2,      756},
15938         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     892,    2,      758},
15939         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     893,    2,      760},
15940         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     894,    3,      762},
15941         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     930,    2,      765},
15942         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     966,    6,      767},
15943         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     967,    5,      773},
15944         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     968,    6,      778},
15945         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     969,    7,      784},
15946         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     970,    2,      791},
15947         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     978,    2,      793},
15948         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     979,    3,      795},
15949         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     980,    5,      798},
15950         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     988,    3,      803},
15951         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     989,    2,      806},
15952         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     990,    2,      808},
15953         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     991,    2,      810},
15954         {"cvmx_key_bist_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     992,    4,      812},
15955         {"cvmx_key_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     993,    3,      816},
15956         {"cvmx_key_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     994,    5,      819},
15957         {"cvmx_key_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     995,    5,      824},
15958         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     996,    5,      829},
15959         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     997,    5,      834},
15960         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     998,    8,      839},
15961         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     999,    9,      847},
15962         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1000,   8,      856},
15963         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1001,   5,      864},
15964         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1002,   4,      869},
15965         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1003,   2,      873},
15966         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1004,   14,     875},
15967         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1005,   19,     889},
15968         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1006,   3,      908},
15969         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1007,   3,      911},
15970         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1008,   2,      914},
15971         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1012,   17,     916},
15972         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1013,   5,      933},
15973         {"cvmx_l2c_spar1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1014,   5,      938},
15974         {"cvmx_l2c_spar2"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1015,   5,      943},
15975         {"cvmx_l2c_spar3"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1016,   5,      948},
15976         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1017,   2,      953},
15977         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1018,   3,      955},
15978         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1019,   2,      958},
15979         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1020,   2,      960},
15980         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1021,   2,      962},
15981         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1022,   7,      964},
15982         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1023,   4,      971},
15983         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1024,   3,      975},
15984         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1025,   3,      978},
15985         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1026,   2,      981},
15986         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1027,   2,      983},
15987         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1028,   2,      985},
15988         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1029,   4,      987},
15989         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1030,   13,     991},
15990         {"cvmx_led_blink"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1031,   2,      1004},
15991         {"cvmx_led_clk_phase"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1032,   2,      1006},
15992         {"cvmx_led_cylon"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1033,   2,      1008},
15993         {"cvmx_led_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1034,   2,      1010},
15994         {"cvmx_led_en"                 ,        CVMX_CSR_DB_TYPE_RSL,   64,     1035,   2,      1012},
15995         {"cvmx_led_polarity"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1036,   2,      1014},
15996         {"cvmx_led_prt"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1037,   2,      1016},
15997         {"cvmx_led_prt_fmt"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1038,   2,      1018},
15998         {"cvmx_led_prt_status#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1039,   2,      1020},
15999         {"cvmx_led_udd_cnt#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1047,   2,      1022},
16000         {"cvmx_led_udd_dat#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1049,   2,      1024},
16001         {"cvmx_led_udd_dat_clr#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1051,   2,      1026},
16002         {"cvmx_led_udd_dat_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1053,   2,      1028},
16003         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1055,   9,      1030},
16004         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1056,   19,     1039},
16005         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1057,   2,      1058},
16006         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1058,   2,      1060},
16007         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1059,   18,     1062},
16008         {"cvmx_lmc#_delay_cfg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1060,   6,      1080},
16009         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1061,   5,      1086},
16010         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1062,   6,      1091},
16011         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1063,   2,      1097},
16012         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1064,   2,      1099},
16013         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1065,   14,     1101},
16014         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1066,   9,      1115},
16015         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1067,   2,      1124},
16016         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1068,   2,      1126},
16017         {"cvmx_lmc#_pll_bwctl"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1069,   3,      1128},
16018         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1070,   9,      1131},
16019         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1071,   9,      1140},
16020         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1072,   4,      1149},
16021         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1073,   3,      1153},
16022         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1074,   3,      1156},
16023         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1075,   3,      1159},
16024         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1076,   5,      1162},
16025         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1078,   1,      1167},
16026         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1079,   6,      1168},
16027         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1087,   13,     1174},
16028         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1095,   4,      1187},
16029         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1096,   2,      1191},
16030         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1097,   2,      1193},
16031         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1098,   8,      1195},
16032         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1099,   8,      1203},
16033         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1100,   2,      1211},
16034         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1101,   8,      1213},
16035         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1102,   4,      1221},
16036         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1103,   2,      1225},
16037         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1104,   2,      1227},
16038         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1105,   13,     1229},
16039         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1106,   12,     1242},
16040         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1107,   3,      1254},
16041         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1108,   3,      1257},
16042         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1109,   2,      1260},
16043         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1111,   2,      1262},
16044         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1113,   2,      1264},
16045         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1115,   7,      1266},
16046         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1117,   2,      1273},
16047         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1119,   7,      1275},
16048         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1121,   4,      1282},
16049         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1123,   8,      1286},
16050         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1125,   9,      1294},
16051         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1127,   7,      1303},
16052         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1129,   9,      1310},
16053         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1131,   2,      1319},
16054         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1133,   2,      1321},
16055         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1135,   4,      1323},
16056         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1137,   2,      1327},
16057         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1139,   2,      1329},
16058         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1141,   2,      1331},
16059         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1143,   4,      1333},
16060         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1145,   2,      1337},
16061         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1147,   2,      1339},
16062         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1149,   2,      1341},
16063         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1151,   2,      1343},
16064         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1153,   2,      1345},
16065         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1155,   2,      1347},
16066         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1157,   6,      1349},
16067         {"cvmx_npi_base_addr_input#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1159,   2,      1355},
16068         {"cvmx_npi_base_addr_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1163,   2,      1357},
16069         {"cvmx_npi_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1167,   21,     1359},
16070         {"cvmx_npi_buff_size_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1168,   3,      1380},
16071         {"cvmx_npi_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1172,   21,     1383},
16072         {"cvmx_npi_dbg_select"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1173,   2,      1404},
16073         {"cvmx_npi_dma_control"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1174,   13,     1406},
16074         {"cvmx_npi_dma_highp_counts"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1175,   3,      1419},
16075         {"cvmx_npi_dma_highp_naddr"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1176,   3,      1422},
16076         {"cvmx_npi_dma_lowp_counts"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1177,   3,      1425},
16077         {"cvmx_npi_dma_lowp_naddr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1178,   3,      1428},
16078         {"cvmx_npi_highp_dbell"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1179,   2,      1431},
16079         {"cvmx_npi_highp_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1180,   2,      1433},
16080         {"cvmx_npi_input_control"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1181,   10,     1435},
16081         {"cvmx_npi_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1182,   63,     1445},
16082         {"cvmx_npi_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1183,   63,     1508},
16083         {"cvmx_npi_lowp_dbell"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1184,   2,      1571},
16084         {"cvmx_npi_lowp_ibuff_saddr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1185,   2,      1573},
16085         {"cvmx_npi_mem_access_subid#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1186,   10,     1575},
16086         {"cvmx_npi_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1190,   1,      1585},
16087         {"cvmx_npi_num_desc_output#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1191,   2,      1586},
16088         {"cvmx_npi_output_control"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1195,   39,     1588},
16089         {"cvmx_npi_p#_dbpair_addr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1196,   3,      1627},
16090         {"cvmx_npi_p#_instr_addr"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1200,   2,      1630},
16091         {"cvmx_npi_p#_instr_cnts"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1204,   3,      1632},
16092         {"cvmx_npi_p#_pair_cnts"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1208,   3,      1635},
16093         {"cvmx_npi_pci_burst_size"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1212,   3,      1638},
16094         {"cvmx_npi_pci_int_arb_cfg"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1213,   4,      1641},
16095         {"cvmx_npi_pci_read_cmd"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1214,   2,      1645},
16096         {"cvmx_npi_port32_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1215,   13,     1647},
16097         {"cvmx_npi_port33_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1216,   13,     1660},
16098         {"cvmx_npi_port34_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1217,   13,     1673},
16099         {"cvmx_npi_port35_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1218,   13,     1686},
16100         {"cvmx_npi_port_bp_control"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1219,   3,      1699},
16101         {"cvmx_npi_rsl_int_blocks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1220,   33,     1702},
16102         {"cvmx_npi_size_input#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1221,   2,      1735},
16103         {"cvmx_npi_win_read_to"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1225,   2,      1737},
16104         {"cvmx_pci_bar1_index#"        ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1226,   5,      1739},
16105         {"cvmx_pci_cfg00"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1258,   2,      1744},
16106         {"cvmx_pci_cfg01"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1259,   24,     1746},
16107         {"cvmx_pci_cfg02"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1260,   2,      1770},
16108         {"cvmx_pci_cfg03"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1261,   7,      1772},
16109         {"cvmx_pci_cfg04"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1262,   5,      1779},
16110         {"cvmx_pci_cfg05"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1263,   1,      1784},
16111         {"cvmx_pci_cfg06"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1264,   5,      1785},
16112         {"cvmx_pci_cfg07"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1265,   1,      1790},
16113         {"cvmx_pci_cfg08"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1266,   4,      1791},
16114         {"cvmx_pci_cfg09"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1267,   2,      1795},
16115         {"cvmx_pci_cfg10"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1268,   1,      1797},
16116         {"cvmx_pci_cfg11"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1269,   2,      1798},
16117         {"cvmx_pci_cfg12"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1270,   4,      1800},
16118         {"cvmx_pci_cfg13"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1271,   2,      1804},
16119         {"cvmx_pci_cfg15"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1272,   4,      1806},
16120         {"cvmx_pci_cfg16"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1273,   16,     1810},
16121         {"cvmx_pci_cfg17"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1274,   1,      1826},
16122         {"cvmx_pci_cfg18"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1275,   1,      1827},
16123         {"cvmx_pci_cfg19"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1276,   18,     1828},
16124         {"cvmx_pci_cfg20"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1277,   1,      1846},
16125         {"cvmx_pci_cfg21"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1278,   1,      1847},
16126         {"cvmx_pci_cfg22"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1279,   7,      1848},
16127         {"cvmx_pci_cfg56"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1280,   7,      1855},
16128         {"cvmx_pci_cfg57"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1281,   13,     1862},
16129         {"cvmx_pci_cfg58"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1282,   10,     1875},
16130         {"cvmx_pci_cfg59"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1283,   10,     1885},
16131         {"cvmx_pci_cfg60"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1284,   7,      1895},
16132         {"cvmx_pci_cfg61"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1285,   2,      1902},
16133         {"cvmx_pci_cfg62"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1286,   1,      1904},
16134         {"cvmx_pci_cfg63"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1287,   2,      1905},
16135         {"cvmx_pci_ctl_status_2"       ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1288,   22,     1907},
16136         {"cvmx_pci_dbell#"             ,        CVMX_CSR_DB_TYPE_PCI,   32,     1289,   2,      1929},
16137         {"cvmx_pci_dma_cnt#"           ,        CVMX_CSR_DB_TYPE_PCI,   32,     1293,   1,      1931},
16138         {"cvmx_pci_dma_int_lev#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1295,   1,      1932},
16139         {"cvmx_pci_dma_time#"          ,        CVMX_CSR_DB_TYPE_PCI,   32,     1297,   1,      1933},
16140         {"cvmx_pci_instr_count#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1299,   1,      1934},
16141         {"cvmx_pci_int_enb"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     1303,   35,     1935},
16142         {"cvmx_pci_int_enb2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1304,   35,     1970},
16143         {"cvmx_pci_int_sum"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     1305,   35,     2005},
16144         {"cvmx_pci_int_sum2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1306,   35,     2040},
16145         {"cvmx_pci_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI,   32,     1307,   2,      2075},
16146         {"cvmx_pci_pkt_credits#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1308,   2,      2077},
16147         {"cvmx_pci_pkts_sent#"         ,        CVMX_CSR_DB_TYPE_PCI,   32,     1312,   1,      2079},
16148         {"cvmx_pci_pkts_sent_int_lev#" ,        CVMX_CSR_DB_TYPE_PCI,   32,     1316,   1,      2080},
16149         {"cvmx_pci_pkts_sent_time#"    ,        CVMX_CSR_DB_TYPE_PCI,   32,     1320,   1,      2081},
16150         {"cvmx_pci_read_cmd_6"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1324,   3,      2082},
16151         {"cvmx_pci_read_cmd_c"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1325,   3,      2085},
16152         {"cvmx_pci_read_cmd_e"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1326,   3,      2088},
16153         {"cvmx_pci_read_timeout"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1327,   3,      2091},
16154         {"cvmx_pci_scm_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1328,   2,      2094},
16155         {"cvmx_pci_tsr_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1329,   2,      2096},
16156         {"cvmx_pci_win_rd_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1330,   4,      2098},
16157         {"cvmx_pci_win_rd_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1331,   1,      2102},
16158         {"cvmx_pci_win_wr_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1332,   4,      2103},
16159         {"cvmx_pci_win_wr_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1333,   1,      2107},
16160         {"cvmx_pci_win_wr_mask"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1334,   2,      2108},
16161         {"cvmx_pip_bck_prs"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1335,   5,      2110},
16162         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1336,   2,      2115},
16163         {"cvmx_pip_crc_ctl#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1337,   3,      2117},
16164         {"cvmx_pip_crc_iv#"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1339,   2,      2120},
16165         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1341,   4,      2122},
16166         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1345,   8,      2126},
16167         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1346,   16,     2134},
16168         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1347,   10,     2150},
16169         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1348,   10,     2160},
16170         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1349,   2,      2170},
16171         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1350,   18,     2172},
16172         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1386,   25,     2190},
16173         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1422,   2,      2215},
16174         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1486,   2,      2217},
16175         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1494,   9,      2219},
16176         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1498,   2,      2228},
16177         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1499,   2,      2230},
16178         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1500,   2,      2232},
16179         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1536,   2,      2234},
16180         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1572,   2,      2236},
16181         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1608,   2,      2238},
16182         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1644,   2,      2240},
16183         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1680,   2,      2242},
16184         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1716,   2,      2244},
16185         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1752,   2,      2246},
16186         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1788,   2,      2248},
16187         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1824,   2,      2250},
16188         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1860,   2,      2252},
16189         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1861,   2,      2254},
16190         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1897,   2,      2256},
16191         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1933,   2,      2258},
16192         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1969,   2,      2260},
16193         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2033,   2,      2262},
16194         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2034,   3,      2264},
16195         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2035,   3,      2267},
16196         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2036,   2,      2270},
16197         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2037,   2,      2272},
16198         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2038,   4,      2274},
16199         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2039,   5,      2278},
16200         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2040,   4,      2283},
16201         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2041,   5,      2287},
16202         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2042,   1,      2292},
16203         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2043,   4,      2293},
16204         {"cvmx_pko_mem_debug14"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2044,   2,      2297},
16205         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2045,   5,      2299},
16206         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2046,   5,      2304},
16207         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2047,   1,      2309},
16208         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2048,   19,     2310},
16209         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2049,   7,      2329},
16210         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2050,   4,      2336},
16211         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2051,   6,      2340},
16212         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2052,   7,      2346},
16213         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2053,   9,      2353},
16214         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2054,   5,      2362},
16215         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2055,   13,     2367},
16216         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2056,   4,      2380},
16217         {"cvmx_pko_reg_crc_ctl#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2057,   3,      2384},
16218         {"cvmx_pko_reg_crc_enable"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2059,   2,      2387},
16219         {"cvmx_pko_reg_crc_iv#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2060,   2,      2389},
16220         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2062,   2,      2391},
16221         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2063,   3,      2393},
16222         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2064,   5,      2396},
16223         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2065,   3,      2401},
16224         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2066,   3,      2404},
16225         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2067,   2,      2407},
16226         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2068,   3,      2409},
16227         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2069,   13,     2412},
16228         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2070,   2,      2425},
16229         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2071,   13,     2427},
16230         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2072,   3,      2440},
16231         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2073,   2,      2443},
16232         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2081,   2,      2445},
16233         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2082,   2,      2447},
16234         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2083,   2,      2449},
16235         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2084,   2,      2451},
16236         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2100,   5,      2453},
16237         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2108,   8,      2458},
16238         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2116,   2,      2466},
16239         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2117,   2,      2468},
16240         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2118,   2,      2470},
16241         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2126,   3,      2472},
16242         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2127,   4,      2475},
16243         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2143,   5,      2479},
16244         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2144,   7,      2484},
16245         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2160,   2,      2491},
16246         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2176,   3,      2493},
16247         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2177,   5,      2496},
16248         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2178,   8,      2501},
16249         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2179,   6,      2509},
16250         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2180,   2,      2515},
16251         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2181,   4,      2517},
16252         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2182,   4,      2521},
16253         {"cvmx_spx#_bckprs_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2183,   2,      2525},
16254         {"cvmx_spx#_bist_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2185,   4,      2527},
16255         {"cvmx_spx#_clk_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2187,   11,     2531},
16256         {"cvmx_spx#_clk_stat"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2189,   9,      2542},
16257         {"cvmx_spx#_dbg_deskew_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2191,   16,     2551},
16258         {"cvmx_spx#_dbg_deskew_state"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2193,   5,      2567},
16259         {"cvmx_spx#_drv_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2195,   4,      2572},
16260         {"cvmx_spx#_err_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2197,   6,      2576},
16261         {"cvmx_spx#_int_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2199,   6,      2582},
16262         {"cvmx_spx#_int_msk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2201,   12,     2588},
16263         {"cvmx_spx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2203,   14,     2600},
16264         {"cvmx_spx#_int_sync"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2205,   12,     2614},
16265         {"cvmx_spx#_tpa_acc"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2207,   2,      2626},
16266         {"cvmx_spx#_tpa_max"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2209,   2,      2628},
16267         {"cvmx_spx#_tpa_sel"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2211,   2,      2630},
16268         {"cvmx_spx#_trn4_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2213,   8,      2632},
16269         {"cvmx_spx0_pll_bw_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2215,   2,      2640},
16270         {"cvmx_spx0_pll_setting"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2216,   2,      2642},
16271         {"cvmx_srx#_com_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2217,   5,      2644},
16272         {"cvmx_srx#_ign_rx_full"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2219,   2,      2649},
16273         {"cvmx_srx#_spi4_cal#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2221,   6,      2651},
16274         {"cvmx_srx#_spi4_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2285,   4,      2657},
16275         {"cvmx_srx#_sw_tick_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2287,   6,      2661},
16276         {"cvmx_srx#_sw_tick_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2289,   1,      2667},
16277         {"cvmx_stx#_arb_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2291,   5,      2668},
16278         {"cvmx_stx#_bckprs_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2293,   2,      2673},
16279         {"cvmx_stx#_com_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2295,   4,      2675},
16280         {"cvmx_stx#_dip_cnt"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2297,   3,      2679},
16281         {"cvmx_stx#_ign_cal"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2299,   2,      2682},
16282         {"cvmx_stx#_int_msk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2301,   9,      2684},
16283         {"cvmx_stx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2303,   10,     2693},
16284         {"cvmx_stx#_int_sync"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2305,   9,      2703},
16285         {"cvmx_stx#_min_bst"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2307,   2,      2712},
16286         {"cvmx_stx#_spi4_cal#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2309,   6,      2714},
16287         {"cvmx_stx#_spi4_dat"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2373,   3,      2720},
16288         {"cvmx_stx#_spi4_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2375,   4,      2723},
16289         {"cvmx_stx#_stat_bytes_hi"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2377,   2,      2727},
16290         {"cvmx_stx#_stat_bytes_lo"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2379,   2,      2729},
16291         {"cvmx_stx#_stat_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2381,   3,      2731},
16292         {"cvmx_stx#_stat_pkt_xmt"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2383,   2,      2734},
16293         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2385,   6,      2736},
16294         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2386,   3,      2742},
16295         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2387,   5,      2745},
16296         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2388,   4,      2750},
16297         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2389,   6,      2754},
16298         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2390,   4,      2760},
16299         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2391,   2,      2764},
16300         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2392,   4,      2766},
16301         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2393,   2,      2770},
16302         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2394,   3,      2772},
16303         {"cvmx_tra_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2395,   4,      2775},
16304         {"cvmx_tra_ctl"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2396,   12,     2779},
16305         {"cvmx_tra_cycles_since"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2397,   3,      2791},
16306         {"cvmx_tra_filt_adr_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2398,   2,      2794},
16307         {"cvmx_tra_filt_adr_msk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2399,   2,      2796},
16308         {"cvmx_tra_filt_cmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2400,   17,     2798},
16309         {"cvmx_tra_filt_did"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2401,   12,     2815},
16310         {"cvmx_tra_filt_sid"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2402,   6,      2827},
16311         {"cvmx_tra_int_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2403,   5,      2833},
16312         {"cvmx_tra_read_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2404,   1,      2838},
16313         {"cvmx_tra_trig0_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2405,   2,      2839},
16314         {"cvmx_tra_trig0_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2406,   2,      2841},
16315         {"cvmx_tra_trig0_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2407,   17,     2843},
16316         {"cvmx_tra_trig0_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2408,   12,     2860},
16317         {"cvmx_tra_trig0_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2409,   6,      2872},
16318         {"cvmx_tra_trig1_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2410,   2,      2878},
16319         {"cvmx_tra_trig1_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2411,   2,      2880},
16320         {"cvmx_tra_trig1_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2412,   17,     2882},
16321         {"cvmx_tra_trig1_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2413,   12,     2899},
16322         {"cvmx_tra_trig1_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2414,   6,      2911},
16323         {"cvmx_zip_cmd_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2415,   3,      2917},
16324         {"cvmx_zip_cmd_buf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2416,   5,      2920},
16325         {"cvmx_zip_cmd_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2417,   3,      2925},
16326         {"cvmx_zip_constants"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2418,   6,      2928},
16327         {"cvmx_zip_debug0"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     2419,   2,      2934},
16328         {"cvmx_zip_error"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     2420,   2,      2936},
16329         {"cvmx_zip_int_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2421,   2,      2938},
16330         {NULL,0,0,0,0,0}
16331 };
16332 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn38xx[] = {
16333         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
16334         {"ASX0_INT_EN"                 ,           0x11800B0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
16335         {"ASX1_INT_EN"                 ,           0x11800B8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
16336         {"ASX0_INT_REG"                ,           0x11800B0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
16337         {"ASX1_INT_REG"                ,           0x11800B8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
16338         {"ASX0_PRT_LOOP"               ,           0x11800B0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
16339         {"ASX1_PRT_LOOP"               ,           0x11800B8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
16340         {"ASX0_RLD_BYPASS"             ,           0x11800B0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
16341         {"ASX1_RLD_BYPASS"             ,           0x11800B8000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
16342         {"ASX0_RLD_BYPASS_SETTING"     ,           0x11800B0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
16343         {"ASX1_RLD_BYPASS_SETTING"     ,           0x11800B8000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
16344         {"ASX0_RLD_COMP"               ,           0x11800B0000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
16345         {"ASX1_RLD_COMP"               ,           0x11800B8000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
16346         {"ASX0_RLD_DATA_DRV"           ,           0x11800B0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
16347         {"ASX1_RLD_DATA_DRV"           ,           0x11800B8000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
16348         {"ASX0_RLD_FCRAM_MODE"         ,           0x11800B0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
16349         {"ASX1_RLD_FCRAM_MODE"         ,           0x11800B8000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
16350         {"ASX0_RLD_NCTL_STRONG"        ,           0x11800B0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
16351         {"ASX1_RLD_NCTL_STRONG"        ,           0x11800B8000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
16352         {"ASX0_RLD_NCTL_WEAK"          ,           0x11800B0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
16353         {"ASX1_RLD_NCTL_WEAK"          ,           0x11800B8000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
16354         {"ASX0_RLD_PCTL_STRONG"        ,           0x11800B0000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
16355         {"ASX1_RLD_PCTL_STRONG"        ,           0x11800B8000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
16356         {"ASX0_RLD_PCTL_WEAK"          ,           0x11800B0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
16357         {"ASX1_RLD_PCTL_WEAK"          ,           0x11800B8000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
16358         {"ASX0_RLD_SETTING"            ,           0x11800B0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
16359         {"ASX1_RLD_SETTING"            ,           0x11800B8000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
16360         {"ASX0_RX_CLK_SET000"          ,           0x11800B0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
16361         {"ASX0_RX_CLK_SET001"          ,           0x11800B0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
16362         {"ASX0_RX_CLK_SET002"          ,           0x11800B0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
16363         {"ASX0_RX_CLK_SET003"          ,           0x11800B0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
16364         {"ASX1_RX_CLK_SET000"          ,           0x11800B8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
16365         {"ASX1_RX_CLK_SET001"          ,           0x11800B8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
16366         {"ASX1_RX_CLK_SET002"          ,           0x11800B8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
16367         {"ASX1_RX_CLK_SET003"          ,           0x11800B8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
16368         {"ASX0_RX_PRT_EN"              ,           0x11800B0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
16369         {"ASX1_RX_PRT_EN"              ,           0x11800B8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
16370         {"ASX0_RX_WOL"                 ,           0x11800B0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
16371         {"ASX1_RX_WOL"                 ,           0x11800B8000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
16372         {"ASX0_RX_WOL_MSK"             ,           0x11800B0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
16373         {"ASX1_RX_WOL_MSK"             ,           0x11800B8000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
16374         {"ASX0_RX_WOL_POWOK"           ,           0x11800B0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
16375         {"ASX1_RX_WOL_POWOK"           ,           0x11800B8000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
16376         {"ASX0_RX_WOL_SIG"             ,           0x11800B0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
16377         {"ASX1_RX_WOL_SIG"             ,           0x11800B8000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
16378         {"ASX0_TX_CLK_SET000"          ,           0x11800B0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
16379         {"ASX0_TX_CLK_SET001"          ,           0x11800B0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
16380         {"ASX0_TX_CLK_SET002"          ,           0x11800B0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
16381         {"ASX0_TX_CLK_SET003"          ,           0x11800B0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
16382         {"ASX1_TX_CLK_SET000"          ,           0x11800B8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
16383         {"ASX1_TX_CLK_SET001"          ,           0x11800B8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
16384         {"ASX1_TX_CLK_SET002"          ,           0x11800B8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
16385         {"ASX1_TX_CLK_SET003"          ,           0x11800B8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
16386         {"ASX0_TX_COMP_BYP"            ,           0x11800B0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
16387         {"ASX1_TX_COMP_BYP"            ,           0x11800B8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
16388         {"ASX0_TX_HI_WATER000"         ,           0x11800B0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
16389         {"ASX0_TX_HI_WATER001"         ,           0x11800B0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
16390         {"ASX0_TX_HI_WATER002"         ,           0x11800B0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
16391         {"ASX0_TX_HI_WATER003"         ,           0x11800B0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
16392         {"ASX1_TX_HI_WATER000"         ,           0x11800B8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
16393         {"ASX1_TX_HI_WATER001"         ,           0x11800B8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
16394         {"ASX1_TX_HI_WATER002"         ,           0x11800B8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
16395         {"ASX1_TX_HI_WATER003"         ,           0x11800B8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
16396         {"ASX0_TX_PRT_EN"              ,           0x11800B0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
16397         {"ASX1_TX_PRT_EN"              ,           0x11800B8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
16398         {"ASX0_DBG_DATA_DRV"           ,           0x11800B0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     23},
16399         {"ASX0_DBG_DATA_ENABLE"        ,           0x11800B0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     24},
16400         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
16401         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
16402         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
16403         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
16404         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16405         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16406         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16407         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16408         {"CIU_INT4_EN0"                ,           0x1070000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16409         {"CIU_INT5_EN0"                ,           0x1070000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16410         {"CIU_INT6_EN0"                ,           0x1070000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16411         {"CIU_INT7_EN0"                ,           0x1070000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16412         {"CIU_INT8_EN0"                ,           0x1070000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16413         {"CIU_INT9_EN0"                ,           0x1070000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16414         {"CIU_INT10_EN0"               ,           0x10700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16415         {"CIU_INT11_EN0"               ,           0x10700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16416         {"CIU_INT12_EN0"               ,           0x10700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16417         {"CIU_INT13_EN0"               ,           0x10700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16418         {"CIU_INT14_EN0"               ,           0x10700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16419         {"CIU_INT15_EN0"               ,           0x10700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16420         {"CIU_INT16_EN0"               ,           0x1070000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16421         {"CIU_INT17_EN0"               ,           0x1070000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16422         {"CIU_INT18_EN0"               ,           0x1070000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16423         {"CIU_INT19_EN0"               ,           0x1070000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16424         {"CIU_INT20_EN0"               ,           0x1070000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16425         {"CIU_INT21_EN0"               ,           0x1070000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16426         {"CIU_INT22_EN0"               ,           0x1070000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16427         {"CIU_INT23_EN0"               ,           0x1070000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16428         {"CIU_INT24_EN0"               ,           0x1070000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16429         {"CIU_INT25_EN0"               ,           0x1070000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16430         {"CIU_INT26_EN0"               ,           0x10700000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16431         {"CIU_INT27_EN0"               ,           0x10700000003B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16432         {"CIU_INT28_EN0"               ,           0x10700000003C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16433         {"CIU_INT29_EN0"               ,           0x10700000003D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16434         {"CIU_INT30_EN0"               ,           0x10700000003E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16435         {"CIU_INT31_EN0"               ,           0x10700000003F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16436         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
16437         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16438         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16439         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16440         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16441         {"CIU_INT4_EN1"                ,           0x1070000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16442         {"CIU_INT5_EN1"                ,           0x1070000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16443         {"CIU_INT6_EN1"                ,           0x1070000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16444         {"CIU_INT7_EN1"                ,           0x1070000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16445         {"CIU_INT8_EN1"                ,           0x1070000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16446         {"CIU_INT9_EN1"                ,           0x1070000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16447         {"CIU_INT10_EN1"               ,           0x10700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16448         {"CIU_INT11_EN1"               ,           0x10700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16449         {"CIU_INT12_EN1"               ,           0x10700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16450         {"CIU_INT13_EN1"               ,           0x10700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16451         {"CIU_INT14_EN1"               ,           0x10700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16452         {"CIU_INT15_EN1"               ,           0x10700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16453         {"CIU_INT16_EN1"               ,           0x1070000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16454         {"CIU_INT17_EN1"               ,           0x1070000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16455         {"CIU_INT18_EN1"               ,           0x1070000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16456         {"CIU_INT19_EN1"               ,           0x1070000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16457         {"CIU_INT20_EN1"               ,           0x1070000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16458         {"CIU_INT21_EN1"               ,           0x1070000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16459         {"CIU_INT22_EN1"               ,           0x1070000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16460         {"CIU_INT23_EN1"               ,           0x1070000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16461         {"CIU_INT24_EN1"               ,           0x1070000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16462         {"CIU_INT25_EN1"               ,           0x1070000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16463         {"CIU_INT26_EN1"               ,           0x10700000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16464         {"CIU_INT27_EN1"               ,           0x10700000003B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16465         {"CIU_INT28_EN1"               ,           0x10700000003C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16466         {"CIU_INT29_EN1"               ,           0x10700000003D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16467         {"CIU_INT30_EN1"               ,           0x10700000003E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16468         {"CIU_INT31_EN1"               ,           0x10700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16469         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
16470         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16471         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16472         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16473         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16474         {"CIU_INT4_SUM0"               ,           0x1070000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16475         {"CIU_INT5_SUM0"               ,           0x1070000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16476         {"CIU_INT6_SUM0"               ,           0x1070000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16477         {"CIU_INT7_SUM0"               ,           0x1070000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16478         {"CIU_INT8_SUM0"               ,           0x1070000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16479         {"CIU_INT9_SUM0"               ,           0x1070000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16480         {"CIU_INT10_SUM0"              ,           0x1070000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16481         {"CIU_INT11_SUM0"              ,           0x1070000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16482         {"CIU_INT12_SUM0"              ,           0x1070000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16483         {"CIU_INT13_SUM0"              ,           0x1070000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16484         {"CIU_INT14_SUM0"              ,           0x1070000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16485         {"CIU_INT15_SUM0"              ,           0x1070000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16486         {"CIU_INT16_SUM0"              ,           0x1070000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16487         {"CIU_INT17_SUM0"              ,           0x1070000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16488         {"CIU_INT18_SUM0"              ,           0x1070000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16489         {"CIU_INT19_SUM0"              ,           0x1070000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16490         {"CIU_INT20_SUM0"              ,           0x10700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16491         {"CIU_INT21_SUM0"              ,           0x10700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16492         {"CIU_INT22_SUM0"              ,           0x10700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16493         {"CIU_INT23_SUM0"              ,           0x10700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16494         {"CIU_INT24_SUM0"              ,           0x10700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16495         {"CIU_INT25_SUM0"              ,           0x10700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16496         {"CIU_INT26_SUM0"              ,           0x10700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16497         {"CIU_INT27_SUM0"              ,           0x10700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16498         {"CIU_INT28_SUM0"              ,           0x10700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16499         {"CIU_INT29_SUM0"              ,           0x10700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16500         {"CIU_INT30_SUM0"              ,           0x10700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16501         {"CIU_INT31_SUM0"              ,           0x10700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16502         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
16503         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
16504         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16505         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16506         {"CIU_MBOX_CLR2"               ,           0x1070000000690ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16507         {"CIU_MBOX_CLR3"               ,           0x1070000000698ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16508         {"CIU_MBOX_CLR4"               ,           0x10700000006A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16509         {"CIU_MBOX_CLR5"               ,           0x10700000006A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16510         {"CIU_MBOX_CLR6"               ,           0x10700000006B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16511         {"CIU_MBOX_CLR7"               ,           0x10700000006B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16512         {"CIU_MBOX_CLR8"               ,           0x10700000006C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16513         {"CIU_MBOX_CLR9"               ,           0x10700000006C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16514         {"CIU_MBOX_CLR10"              ,           0x10700000006D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16515         {"CIU_MBOX_CLR11"              ,           0x10700000006D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16516         {"CIU_MBOX_CLR12"              ,           0x10700000006E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16517         {"CIU_MBOX_CLR13"              ,           0x10700000006E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16518         {"CIU_MBOX_CLR14"              ,           0x10700000006F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16519         {"CIU_MBOX_CLR15"              ,           0x10700000006F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
16520         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16521         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16522         {"CIU_MBOX_SET2"               ,           0x1070000000610ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16523         {"CIU_MBOX_SET3"               ,           0x1070000000618ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16524         {"CIU_MBOX_SET4"               ,           0x1070000000620ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16525         {"CIU_MBOX_SET5"               ,           0x1070000000628ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16526         {"CIU_MBOX_SET6"               ,           0x1070000000630ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16527         {"CIU_MBOX_SET7"               ,           0x1070000000638ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16528         {"CIU_MBOX_SET8"               ,           0x1070000000640ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16529         {"CIU_MBOX_SET9"               ,           0x1070000000648ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16530         {"CIU_MBOX_SET10"              ,           0x1070000000650ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16531         {"CIU_MBOX_SET11"              ,           0x1070000000658ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16532         {"CIU_MBOX_SET12"              ,           0x1070000000660ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16533         {"CIU_MBOX_SET13"              ,           0x1070000000668ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16534         {"CIU_MBOX_SET14"              ,           0x1070000000670ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16535         {"CIU_MBOX_SET15"              ,           0x1070000000678ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
16536         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
16537         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
16538         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
16539         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16540         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16541         {"CIU_PP_POKE2"                ,           0x1070000000590ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16542         {"CIU_PP_POKE3"                ,           0x1070000000598ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16543         {"CIU_PP_POKE4"                ,           0x10700000005A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16544         {"CIU_PP_POKE5"                ,           0x10700000005A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16545         {"CIU_PP_POKE6"                ,           0x10700000005B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16546         {"CIU_PP_POKE7"                ,           0x10700000005B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16547         {"CIU_PP_POKE8"                ,           0x10700000005C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16548         {"CIU_PP_POKE9"                ,           0x10700000005C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16549         {"CIU_PP_POKE10"               ,           0x10700000005D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16550         {"CIU_PP_POKE11"               ,           0x10700000005D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16551         {"CIU_PP_POKE12"               ,           0x10700000005E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16552         {"CIU_PP_POKE13"               ,           0x10700000005E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16553         {"CIU_PP_POKE14"               ,           0x10700000005F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16554         {"CIU_PP_POKE15"               ,           0x10700000005F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
16555         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
16556         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
16557         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     41},
16558         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
16559         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
16560         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
16561         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
16562         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
16563         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16564         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16565         {"CIU_WDOG2"                   ,           0x1070000000510ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16566         {"CIU_WDOG3"                   ,           0x1070000000518ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16567         {"CIU_WDOG4"                   ,           0x1070000000520ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16568         {"CIU_WDOG5"                   ,           0x1070000000528ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16569         {"CIU_WDOG6"                   ,           0x1070000000530ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16570         {"CIU_WDOG7"                   ,           0x1070000000538ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16571         {"CIU_WDOG8"                   ,           0x1070000000540ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16572         {"CIU_WDOG9"                   ,           0x1070000000548ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16573         {"CIU_WDOG10"                  ,           0x1070000000550ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16574         {"CIU_WDOG11"                  ,           0x1070000000558ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16575         {"CIU_WDOG12"                  ,           0x1070000000560ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16576         {"CIU_WDOG13"                  ,           0x1070000000568ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16577         {"CIU_WDOG14"                  ,           0x1070000000570ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16578         {"CIU_WDOG15"                  ,           0x1070000000578ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
16579         {"DBG_DATA"                    ,           0x11F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     45},
16580         {"DFA_BST0"                    ,           0x11800300007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
16581         {"DFA_BST1"                    ,           0x11800300007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
16582         {"DFA_CFG"                     ,           0x1180030000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
16583         {"DFA_DBELL"                   ,           0x1370000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     49},
16584         {"DFA_DIFCTL"                  ,           0x1370600000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
16585         {"DFA_DIFRDPTR"                ,           0x1370200000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     51},
16586         {"DFA_ERR"                     ,           0x1180030000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
16587         {"DFA_MEMCFG0"                 ,           0x1180030000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
16588         {"DFA_MEMCFG1"                 ,           0x1180030000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
16589         {"DFA_MEMCFG2"                 ,           0x1180030000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
16590         {"DFA_MEMFADR"                 ,           0x1180030000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
16591         {"DFA_MEMFCR"                  ,           0x1180030000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
16592         {"DFA_MEMRLD"                  ,           0x1180030000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
16593         {"DFA_NCBCTL"                  ,           0x1180030000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
16594         {"DFA_SBD_DBG0"                ,           0x1180030000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
16595         {"DFA_SBD_DBG1"                ,           0x1180030000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
16596         {"DFA_SBD_DBG2"                ,           0x1180030000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
16597         {"DFA_SBD_DBG3"                ,           0x1180030000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
16598         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
16599         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
16600         {"FPA_FPF1_MARKS"              ,           0x1180028000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
16601         {"FPA_FPF2_MARKS"              ,           0x1180028000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
16602         {"FPA_FPF3_MARKS"              ,           0x1180028000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
16603         {"FPA_FPF4_MARKS"              ,           0x1180028000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
16604         {"FPA_FPF5_MARKS"              ,           0x1180028000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
16605         {"FPA_FPF6_MARKS"              ,           0x1180028000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
16606         {"FPA_FPF7_MARKS"              ,           0x1180028000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
16607         {"FPA_FPF1_SIZE"               ,           0x1180028000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
16608         {"FPA_FPF2_SIZE"               ,           0x1180028000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
16609         {"FPA_FPF3_SIZE"               ,           0x1180028000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
16610         {"FPA_FPF4_SIZE"               ,           0x1180028000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
16611         {"FPA_FPF5_SIZE"               ,           0x1180028000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
16612         {"FPA_FPF6_SIZE"               ,           0x1180028000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
16613         {"FPA_FPF7_SIZE"               ,           0x1180028000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
16614         {"FPA_FPF0_MARKS"              ,           0x1180028000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
16615         {"FPA_FPF0_SIZE"               ,           0x1180028000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
16616         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
16617         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
16618         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
16619         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
16620         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
16621         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
16622         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
16623         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
16624         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
16625         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
16626         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
16627         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
16628         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
16629         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
16630         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
16631         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
16632         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
16633         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
16634         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
16635         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
16636         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
16637         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
16638         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
16639         {"GMX1_BAD_REG"                ,           0x1180010000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
16640         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
16641         {"GMX1_BIST"                   ,           0x1180010000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
16642         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
16643         {"GMX1_INF_MODE"               ,           0x11800100007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
16644         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
16645         {"GMX1_NXA_ADR"                ,           0x1180010000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
16646         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
16647         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
16648         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
16649         {"GMX0_PRT003_CFG"             ,           0x1180008001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
16650         {"GMX1_PRT000_CFG"             ,           0x1180010000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
16651         {"GMX1_PRT001_CFG"             ,           0x1180010000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
16652         {"GMX1_PRT002_CFG"             ,           0x1180010001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
16653         {"GMX1_PRT003_CFG"             ,           0x1180010001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
16654         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
16655         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
16656         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
16657         {"GMX0_RX003_ADR_CAM0"         ,           0x1180008001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
16658         {"GMX1_RX000_ADR_CAM0"         ,           0x1180010000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
16659         {"GMX1_RX001_ADR_CAM0"         ,           0x1180010000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
16660         {"GMX1_RX002_ADR_CAM0"         ,           0x1180010001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
16661         {"GMX1_RX003_ADR_CAM0"         ,           0x1180010001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
16662         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
16663         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
16664         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
16665         {"GMX0_RX003_ADR_CAM1"         ,           0x1180008001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
16666         {"GMX1_RX000_ADR_CAM1"         ,           0x1180010000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
16667         {"GMX1_RX001_ADR_CAM1"         ,           0x1180010000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
16668         {"GMX1_RX002_ADR_CAM1"         ,           0x1180010001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
16669         {"GMX1_RX003_ADR_CAM1"         ,           0x1180010001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
16670         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
16671         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
16672         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
16673         {"GMX0_RX003_ADR_CAM2"         ,           0x1180008001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
16674         {"GMX1_RX000_ADR_CAM2"         ,           0x1180010000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
16675         {"GMX1_RX001_ADR_CAM2"         ,           0x1180010000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
16676         {"GMX1_RX002_ADR_CAM2"         ,           0x1180010001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
16677         {"GMX1_RX003_ADR_CAM2"         ,           0x1180010001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
16678         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
16679         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
16680         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
16681         {"GMX0_RX003_ADR_CAM3"         ,           0x1180008001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
16682         {"GMX1_RX000_ADR_CAM3"         ,           0x1180010000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
16683         {"GMX1_RX001_ADR_CAM3"         ,           0x1180010000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
16684         {"GMX1_RX002_ADR_CAM3"         ,           0x1180010001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
16685         {"GMX1_RX003_ADR_CAM3"         ,           0x1180010001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
16686         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
16687         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
16688         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
16689         {"GMX0_RX003_ADR_CAM4"         ,           0x11800080019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
16690         {"GMX1_RX000_ADR_CAM4"         ,           0x11800100001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
16691         {"GMX1_RX001_ADR_CAM4"         ,           0x11800100009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
16692         {"GMX1_RX002_ADR_CAM4"         ,           0x11800100011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
16693         {"GMX1_RX003_ADR_CAM4"         ,           0x11800100019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
16694         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
16695         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
16696         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
16697         {"GMX0_RX003_ADR_CAM5"         ,           0x11800080019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
16698         {"GMX1_RX000_ADR_CAM5"         ,           0x11800100001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
16699         {"GMX1_RX001_ADR_CAM5"         ,           0x11800100009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
16700         {"GMX1_RX002_ADR_CAM5"         ,           0x11800100011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
16701         {"GMX1_RX003_ADR_CAM5"         ,           0x11800100019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
16702         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
16703         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
16704         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
16705         {"GMX0_RX003_ADR_CAM_EN"       ,           0x1180008001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
16706         {"GMX1_RX000_ADR_CAM_EN"       ,           0x1180010000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
16707         {"GMX1_RX001_ADR_CAM_EN"       ,           0x1180010000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
16708         {"GMX1_RX002_ADR_CAM_EN"       ,           0x1180010001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
16709         {"GMX1_RX003_ADR_CAM_EN"       ,           0x1180010001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
16710         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
16711         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
16712         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
16713         {"GMX0_RX003_ADR_CTL"          ,           0x1180008001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
16714         {"GMX1_RX000_ADR_CTL"          ,           0x1180010000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
16715         {"GMX1_RX001_ADR_CTL"          ,           0x1180010000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
16716         {"GMX1_RX002_ADR_CTL"          ,           0x1180010001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
16717         {"GMX1_RX003_ADR_CTL"          ,           0x1180010001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
16718         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
16719         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
16720         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
16721         {"GMX0_RX003_DECISION"         ,           0x1180008001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
16722         {"GMX1_RX000_DECISION"         ,           0x1180010000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
16723         {"GMX1_RX001_DECISION"         ,           0x1180010000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
16724         {"GMX1_RX002_DECISION"         ,           0x1180010001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
16725         {"GMX1_RX003_DECISION"         ,           0x1180010001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
16726         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
16727         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
16728         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
16729         {"GMX0_RX003_FRM_CHK"          ,           0x1180008001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
16730         {"GMX1_RX000_FRM_CHK"          ,           0x1180010000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
16731         {"GMX1_RX001_FRM_CHK"          ,           0x1180010000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
16732         {"GMX1_RX002_FRM_CHK"          ,           0x1180010001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
16733         {"GMX1_RX003_FRM_CHK"          ,           0x1180010001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
16734         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
16735         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
16736         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
16737         {"GMX0_RX003_FRM_CTL"          ,           0x1180008001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
16738         {"GMX1_RX000_FRM_CTL"          ,           0x1180010000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
16739         {"GMX1_RX001_FRM_CTL"          ,           0x1180010000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
16740         {"GMX1_RX002_FRM_CTL"          ,           0x1180010001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
16741         {"GMX1_RX003_FRM_CTL"          ,           0x1180010001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
16742         {"GMX0_RX000_FRM_MAX"          ,           0x1180008000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
16743         {"GMX0_RX001_FRM_MAX"          ,           0x1180008000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
16744         {"GMX0_RX002_FRM_MAX"          ,           0x1180008001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
16745         {"GMX0_RX003_FRM_MAX"          ,           0x1180008001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
16746         {"GMX1_RX000_FRM_MAX"          ,           0x1180010000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
16747         {"GMX1_RX001_FRM_MAX"          ,           0x1180010000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
16748         {"GMX1_RX002_FRM_MAX"          ,           0x1180010001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
16749         {"GMX1_RX003_FRM_MAX"          ,           0x1180010001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
16750         {"GMX0_RX000_FRM_MIN"          ,           0x1180008000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
16751         {"GMX0_RX001_FRM_MIN"          ,           0x1180008000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
16752         {"GMX0_RX002_FRM_MIN"          ,           0x1180008001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
16753         {"GMX0_RX003_FRM_MIN"          ,           0x1180008001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
16754         {"GMX1_RX000_FRM_MIN"          ,           0x1180010000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
16755         {"GMX1_RX001_FRM_MIN"          ,           0x1180010000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
16756         {"GMX1_RX002_FRM_MIN"          ,           0x1180010001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
16757         {"GMX1_RX003_FRM_MIN"          ,           0x1180010001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
16758         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
16759         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
16760         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
16761         {"GMX0_RX003_IFG"              ,           0x1180008001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
16762         {"GMX1_RX000_IFG"              ,           0x1180010000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
16763         {"GMX1_RX001_IFG"              ,           0x1180010000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
16764         {"GMX1_RX002_IFG"              ,           0x1180010001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
16765         {"GMX1_RX003_IFG"              ,           0x1180010001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
16766         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
16767         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
16768         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
16769         {"GMX0_RX003_INT_EN"           ,           0x1180008001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
16770         {"GMX1_RX000_INT_EN"           ,           0x1180010000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
16771         {"GMX1_RX001_INT_EN"           ,           0x1180010000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
16772         {"GMX1_RX002_INT_EN"           ,           0x1180010001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
16773         {"GMX1_RX003_INT_EN"           ,           0x1180010001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
16774         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
16775         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
16776         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
16777         {"GMX0_RX003_INT_REG"          ,           0x1180008001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
16778         {"GMX1_RX000_INT_REG"          ,           0x1180010000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
16779         {"GMX1_RX001_INT_REG"          ,           0x1180010000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
16780         {"GMX1_RX002_INT_REG"          ,           0x1180010001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
16781         {"GMX1_RX003_INT_REG"          ,           0x1180010001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
16782         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
16783         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
16784         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
16785         {"GMX0_RX003_JABBER"           ,           0x1180008001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
16786         {"GMX1_RX000_JABBER"           ,           0x1180010000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
16787         {"GMX1_RX001_JABBER"           ,           0x1180010000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
16788         {"GMX1_RX002_JABBER"           ,           0x1180010001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
16789         {"GMX1_RX003_JABBER"           ,           0x1180010001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
16790         {"GMX0_RX000_RX_INBND"         ,           0x1180008000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
16791         {"GMX0_RX001_RX_INBND"         ,           0x1180008000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
16792         {"GMX0_RX002_RX_INBND"         ,           0x1180008001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
16793         {"GMX0_RX003_RX_INBND"         ,           0x1180008001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
16794         {"GMX1_RX000_RX_INBND"         ,           0x1180010000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
16795         {"GMX1_RX001_RX_INBND"         ,           0x1180010000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
16796         {"GMX1_RX002_RX_INBND"         ,           0x1180010001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
16797         {"GMX1_RX003_RX_INBND"         ,           0x1180010001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
16798         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
16799         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
16800         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
16801         {"GMX0_RX003_STATS_CTL"        ,           0x1180008001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
16802         {"GMX1_RX000_STATS_CTL"        ,           0x1180010000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
16803         {"GMX1_RX001_STATS_CTL"        ,           0x1180010000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
16804         {"GMX1_RX002_STATS_CTL"        ,           0x1180010001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
16805         {"GMX1_RX003_STATS_CTL"        ,           0x1180010001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
16806         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
16807         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
16808         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
16809         {"GMX0_RX003_STATS_OCTS"       ,           0x1180008001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
16810         {"GMX1_RX000_STATS_OCTS"       ,           0x1180010000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
16811         {"GMX1_RX001_STATS_OCTS"       ,           0x1180010000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
16812         {"GMX1_RX002_STATS_OCTS"       ,           0x1180010001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
16813         {"GMX1_RX003_STATS_OCTS"       ,           0x1180010001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
16814         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
16815         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
16816         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
16817         {"GMX0_RX003_STATS_OCTS_CTL"   ,           0x1180008001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
16818         {"GMX1_RX000_STATS_OCTS_CTL"   ,           0x1180010000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
16819         {"GMX1_RX001_STATS_OCTS_CTL"   ,           0x1180010000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
16820         {"GMX1_RX002_STATS_OCTS_CTL"   ,           0x1180010001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
16821         {"GMX1_RX003_STATS_OCTS_CTL"   ,           0x1180010001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
16822         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
16823         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
16824         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
16825         {"GMX0_RX003_STATS_OCTS_DMAC"  ,           0x11800080018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
16826         {"GMX1_RX000_STATS_OCTS_DMAC"  ,           0x11800100000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
16827         {"GMX1_RX001_STATS_OCTS_DMAC"  ,           0x11800100008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
16828         {"GMX1_RX002_STATS_OCTS_DMAC"  ,           0x11800100010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
16829         {"GMX1_RX003_STATS_OCTS_DMAC"  ,           0x11800100018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
16830         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
16831         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
16832         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
16833         {"GMX0_RX003_STATS_OCTS_DRP"   ,           0x11800080018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
16834         {"GMX1_RX000_STATS_OCTS_DRP"   ,           0x11800100000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
16835         {"GMX1_RX001_STATS_OCTS_DRP"   ,           0x11800100008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
16836         {"GMX1_RX002_STATS_OCTS_DRP"   ,           0x11800100010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
16837         {"GMX1_RX003_STATS_OCTS_DRP"   ,           0x11800100018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
16838         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
16839         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
16840         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
16841         {"GMX0_RX003_STATS_PKTS"       ,           0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
16842         {"GMX1_RX000_STATS_PKTS"       ,           0x1180010000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
16843         {"GMX1_RX001_STATS_PKTS"       ,           0x1180010000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
16844         {"GMX1_RX002_STATS_PKTS"       ,           0x1180010001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
16845         {"GMX1_RX003_STATS_PKTS"       ,           0x1180010001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
16846         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
16847         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
16848         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
16849         {"GMX0_RX003_STATS_PKTS_BAD"   ,           0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
16850         {"GMX1_RX000_STATS_PKTS_BAD"   ,           0x11800100000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
16851         {"GMX1_RX001_STATS_PKTS_BAD"   ,           0x11800100008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
16852         {"GMX1_RX002_STATS_PKTS_BAD"   ,           0x11800100010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
16853         {"GMX1_RX003_STATS_PKTS_BAD"   ,           0x11800100018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
16854         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
16855         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
16856         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
16857         {"GMX0_RX003_STATS_PKTS_CTL"   ,           0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
16858         {"GMX1_RX000_STATS_PKTS_CTL"   ,           0x1180010000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
16859         {"GMX1_RX001_STATS_PKTS_CTL"   ,           0x1180010000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
16860         {"GMX1_RX002_STATS_PKTS_CTL"   ,           0x1180010001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
16861         {"GMX1_RX003_STATS_PKTS_CTL"   ,           0x1180010001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
16862         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
16863         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
16864         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
16865         {"GMX0_RX003_STATS_PKTS_DMAC"  ,           0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
16866         {"GMX1_RX000_STATS_PKTS_DMAC"  ,           0x11800100000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
16867         {"GMX1_RX001_STATS_PKTS_DMAC"  ,           0x11800100008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
16868         {"GMX1_RX002_STATS_PKTS_DMAC"  ,           0x11800100010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
16869         {"GMX1_RX003_STATS_PKTS_DMAC"  ,           0x11800100018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
16870         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
16871         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
16872         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
16873         {"GMX0_RX003_STATS_PKTS_DRP"   ,           0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
16874         {"GMX1_RX000_STATS_PKTS_DRP"   ,           0x11800100000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
16875         {"GMX1_RX001_STATS_PKTS_DRP"   ,           0x11800100008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
16876         {"GMX1_RX002_STATS_PKTS_DRP"   ,           0x11800100010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
16877         {"GMX1_RX003_STATS_PKTS_DRP"   ,           0x11800100018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
16878         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
16879         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
16880         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
16881         {"GMX0_RX003_UDD_SKP"          ,           0x1180008001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
16882         {"GMX1_RX000_UDD_SKP"          ,           0x1180010000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
16883         {"GMX1_RX001_UDD_SKP"          ,           0x1180010000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
16884         {"GMX1_RX002_UDD_SKP"          ,           0x1180010001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
16885         {"GMX1_RX003_UDD_SKP"          ,           0x1180010001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
16886         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
16887         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
16888         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
16889         {"GMX0_RX_BP_DROP003"          ,           0x1180008000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
16890         {"GMX1_RX_BP_DROP000"          ,           0x1180010000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
16891         {"GMX1_RX_BP_DROP001"          ,           0x1180010000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
16892         {"GMX1_RX_BP_DROP002"          ,           0x1180010000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
16893         {"GMX1_RX_BP_DROP003"          ,           0x1180010000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
16894         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
16895         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
16896         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
16897         {"GMX0_RX_BP_OFF003"           ,           0x1180008000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
16898         {"GMX1_RX_BP_OFF000"           ,           0x1180010000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
16899         {"GMX1_RX_BP_OFF001"           ,           0x1180010000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
16900         {"GMX1_RX_BP_OFF002"           ,           0x1180010000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
16901         {"GMX1_RX_BP_OFF003"           ,           0x1180010000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
16902         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
16903         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
16904         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
16905         {"GMX0_RX_BP_ON003"            ,           0x1180008000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
16906         {"GMX1_RX_BP_ON000"            ,           0x1180010000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
16907         {"GMX1_RX_BP_ON001"            ,           0x1180010000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
16908         {"GMX1_RX_BP_ON002"            ,           0x1180010000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
16909         {"GMX1_RX_BP_ON003"            ,           0x1180010000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
16910         {"GMX0_RX_PASS_EN"             ,           0x11800080005F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
16911         {"GMX1_RX_PASS_EN"             ,           0x11800100005F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
16912         {"GMX0_RX_PASS_MAP000"         ,           0x1180008000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16913         {"GMX0_RX_PASS_MAP001"         ,           0x1180008000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16914         {"GMX0_RX_PASS_MAP002"         ,           0x1180008000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16915         {"GMX0_RX_PASS_MAP003"         ,           0x1180008000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16916         {"GMX0_RX_PASS_MAP004"         ,           0x1180008000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16917         {"GMX0_RX_PASS_MAP005"         ,           0x1180008000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16918         {"GMX0_RX_PASS_MAP006"         ,           0x1180008000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16919         {"GMX0_RX_PASS_MAP007"         ,           0x1180008000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16920         {"GMX0_RX_PASS_MAP008"         ,           0x1180008000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16921         {"GMX0_RX_PASS_MAP009"         ,           0x1180008000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16922         {"GMX0_RX_PASS_MAP010"         ,           0x1180008000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16923         {"GMX0_RX_PASS_MAP011"         ,           0x1180008000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16924         {"GMX0_RX_PASS_MAP012"         ,           0x1180008000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16925         {"GMX0_RX_PASS_MAP013"         ,           0x1180008000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16926         {"GMX0_RX_PASS_MAP014"         ,           0x1180008000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16927         {"GMX0_RX_PASS_MAP015"         ,           0x1180008000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16928         {"GMX1_RX_PASS_MAP000"         ,           0x1180010000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16929         {"GMX1_RX_PASS_MAP001"         ,           0x1180010000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16930         {"GMX1_RX_PASS_MAP002"         ,           0x1180010000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16931         {"GMX1_RX_PASS_MAP003"         ,           0x1180010000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16932         {"GMX1_RX_PASS_MAP004"         ,           0x1180010000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16933         {"GMX1_RX_PASS_MAP005"         ,           0x1180010000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16934         {"GMX1_RX_PASS_MAP006"         ,           0x1180010000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16935         {"GMX1_RX_PASS_MAP007"         ,           0x1180010000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16936         {"GMX1_RX_PASS_MAP008"         ,           0x1180010000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16937         {"GMX1_RX_PASS_MAP009"         ,           0x1180010000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16938         {"GMX1_RX_PASS_MAP010"         ,           0x1180010000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16939         {"GMX1_RX_PASS_MAP011"         ,           0x1180010000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16940         {"GMX1_RX_PASS_MAP012"         ,           0x1180010000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16941         {"GMX1_RX_PASS_MAP013"         ,           0x1180010000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16942         {"GMX1_RX_PASS_MAP014"         ,           0x1180010000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16943         {"GMX1_RX_PASS_MAP015"         ,           0x1180010000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
16944         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
16945         {"GMX1_RX_PRT_INFO"            ,           0x11800100004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
16946         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
16947         {"GMX1_RX_PRTS"                ,           0x1180010000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
16948         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
16949         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
16950         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
16951         {"GMX0_SMAC003"                ,           0x1180008001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
16952         {"GMX1_SMAC000"                ,           0x1180010000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
16953         {"GMX1_SMAC001"                ,           0x1180010000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
16954         {"GMX1_SMAC002"                ,           0x1180010001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
16955         {"GMX1_SMAC003"                ,           0x1180010001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
16956         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
16957         {"GMX1_STAT_BP"                ,           0x1180010000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
16958         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
16959         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
16960         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
16961         {"GMX0_TX003_APPEND"           ,           0x1180008001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
16962         {"GMX1_TX000_APPEND"           ,           0x1180010000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
16963         {"GMX1_TX001_APPEND"           ,           0x1180010000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
16964         {"GMX1_TX002_APPEND"           ,           0x1180010001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
16965         {"GMX1_TX003_APPEND"           ,           0x1180010001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
16966         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
16967         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
16968         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
16969         {"GMX0_TX003_BURST"            ,           0x1180008001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
16970         {"GMX1_TX000_BURST"            ,           0x1180010000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
16971         {"GMX1_TX001_BURST"            ,           0x1180010000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
16972         {"GMX1_TX002_BURST"            ,           0x1180010001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
16973         {"GMX1_TX003_BURST"            ,           0x1180010001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
16974         {"GMX0_TX000_CLK"              ,           0x1180008000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
16975         {"GMX0_TX001_CLK"              ,           0x1180008000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
16976         {"GMX0_TX002_CLK"              ,           0x1180008001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
16977         {"GMX0_TX003_CLK"              ,           0x1180008001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
16978         {"GMX1_TX000_CLK"              ,           0x1180010000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
16979         {"GMX1_TX001_CLK"              ,           0x1180010000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
16980         {"GMX1_TX002_CLK"              ,           0x1180010001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
16981         {"GMX1_TX003_CLK"              ,           0x1180010001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
16982         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
16983         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
16984         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
16985         {"GMX0_TX003_CTL"              ,           0x1180008001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
16986         {"GMX1_TX000_CTL"              ,           0x1180010000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
16987         {"GMX1_TX001_CTL"              ,           0x1180010000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
16988         {"GMX1_TX002_CTL"              ,           0x1180010001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
16989         {"GMX1_TX003_CTL"              ,           0x1180010001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
16990         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
16991         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
16992         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
16993         {"GMX0_TX003_MIN_PKT"          ,           0x1180008001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
16994         {"GMX1_TX000_MIN_PKT"          ,           0x1180010000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
16995         {"GMX1_TX001_MIN_PKT"          ,           0x1180010000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
16996         {"GMX1_TX002_MIN_PKT"          ,           0x1180010001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
16997         {"GMX1_TX003_MIN_PKT"          ,           0x1180010001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
16998         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
16999         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
17000         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
17001         {"GMX0_TX003_PAUSE_PKT_INTERVAL",          0x1180008001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
17002         {"GMX1_TX000_PAUSE_PKT_INTERVAL",          0x1180010000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
17003         {"GMX1_TX001_PAUSE_PKT_INTERVAL",          0x1180010000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
17004         {"GMX1_TX002_PAUSE_PKT_INTERVAL",          0x1180010001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
17005         {"GMX1_TX003_PAUSE_PKT_INTERVAL",          0x1180010001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
17006         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
17007         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
17008         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
17009         {"GMX0_TX003_PAUSE_PKT_TIME"   ,           0x1180008001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
17010         {"GMX1_TX000_PAUSE_PKT_TIME"   ,           0x1180010000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
17011         {"GMX1_TX001_PAUSE_PKT_TIME"   ,           0x1180010000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
17012         {"GMX1_TX002_PAUSE_PKT_TIME"   ,           0x1180010001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
17013         {"GMX1_TX003_PAUSE_PKT_TIME"   ,           0x1180010001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
17014         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
17015         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
17016         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
17017         {"GMX0_TX003_PAUSE_TOGO"       ,           0x1180008001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
17018         {"GMX1_TX000_PAUSE_TOGO"       ,           0x1180010000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
17019         {"GMX1_TX001_PAUSE_TOGO"       ,           0x1180010000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
17020         {"GMX1_TX002_PAUSE_TOGO"       ,           0x1180010001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
17021         {"GMX1_TX003_PAUSE_TOGO"       ,           0x1180010001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
17022         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
17023         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
17024         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
17025         {"GMX0_TX003_PAUSE_ZERO"       ,           0x1180008001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
17026         {"GMX1_TX000_PAUSE_ZERO"       ,           0x1180010000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
17027         {"GMX1_TX001_PAUSE_ZERO"       ,           0x1180010000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
17028         {"GMX1_TX002_PAUSE_ZERO"       ,           0x1180010001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
17029         {"GMX1_TX003_PAUSE_ZERO"       ,           0x1180010001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
17030         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
17031         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
17032         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
17033         {"GMX0_TX003_SLOT"             ,           0x1180008001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
17034         {"GMX1_TX000_SLOT"             ,           0x1180010000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
17035         {"GMX1_TX001_SLOT"             ,           0x1180010000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
17036         {"GMX1_TX002_SLOT"             ,           0x1180010001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
17037         {"GMX1_TX003_SLOT"             ,           0x1180010001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
17038         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
17039         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
17040         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
17041         {"GMX0_TX003_SOFT_PAUSE"       ,           0x1180008001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
17042         {"GMX1_TX000_SOFT_PAUSE"       ,           0x1180010000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
17043         {"GMX1_TX001_SOFT_PAUSE"       ,           0x1180010000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
17044         {"GMX1_TX002_SOFT_PAUSE"       ,           0x1180010001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
17045         {"GMX1_TX003_SOFT_PAUSE"       ,           0x1180010001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
17046         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
17047         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
17048         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
17049         {"GMX0_TX003_STAT0"            ,           0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
17050         {"GMX1_TX000_STAT0"            ,           0x1180010000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
17051         {"GMX1_TX001_STAT0"            ,           0x1180010000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
17052         {"GMX1_TX002_STAT0"            ,           0x1180010001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
17053         {"GMX1_TX003_STAT0"            ,           0x1180010001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
17054         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
17055         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
17056         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
17057         {"GMX0_TX003_STAT1"            ,           0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
17058         {"GMX1_TX000_STAT1"            ,           0x1180010000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
17059         {"GMX1_TX001_STAT1"            ,           0x1180010000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
17060         {"GMX1_TX002_STAT1"            ,           0x1180010001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
17061         {"GMX1_TX003_STAT1"            ,           0x1180010001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
17062         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
17063         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
17064         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
17065         {"GMX0_TX003_STAT2"            ,           0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
17066         {"GMX1_TX000_STAT2"            ,           0x1180010000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
17067         {"GMX1_TX001_STAT2"            ,           0x1180010000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
17068         {"GMX1_TX002_STAT2"            ,           0x1180010001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
17069         {"GMX1_TX003_STAT2"            ,           0x1180010001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
17070         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
17071         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
17072         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
17073         {"GMX0_TX003_STAT3"            ,           0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
17074         {"GMX1_TX000_STAT3"            ,           0x1180010000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
17075         {"GMX1_TX001_STAT3"            ,           0x1180010000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
17076         {"GMX1_TX002_STAT3"            ,           0x1180010001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
17077         {"GMX1_TX003_STAT3"            ,           0x1180010001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
17078         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
17079         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
17080         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
17081         {"GMX0_TX003_STAT4"            ,           0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
17082         {"GMX1_TX000_STAT4"            ,           0x11800100002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
17083         {"GMX1_TX001_STAT4"            ,           0x1180010000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
17084         {"GMX1_TX002_STAT4"            ,           0x11800100012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
17085         {"GMX1_TX003_STAT4"            ,           0x1180010001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
17086         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
17087         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
17088         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
17089         {"GMX0_TX003_STAT5"            ,           0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
17090         {"GMX1_TX000_STAT5"            ,           0x11800100002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
17091         {"GMX1_TX001_STAT5"            ,           0x1180010000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
17092         {"GMX1_TX002_STAT5"            ,           0x11800100012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
17093         {"GMX1_TX003_STAT5"            ,           0x1180010001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
17094         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
17095         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
17096         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
17097         {"GMX0_TX003_STAT6"            ,           0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
17098         {"GMX1_TX000_STAT6"            ,           0x11800100002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
17099         {"GMX1_TX001_STAT6"            ,           0x1180010000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
17100         {"GMX1_TX002_STAT6"            ,           0x11800100012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
17101         {"GMX1_TX003_STAT6"            ,           0x1180010001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
17102         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
17103         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
17104         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
17105         {"GMX0_TX003_STAT7"            ,           0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
17106         {"GMX1_TX000_STAT7"            ,           0x11800100002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
17107         {"GMX1_TX001_STAT7"            ,           0x1180010000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
17108         {"GMX1_TX002_STAT7"            ,           0x11800100012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
17109         {"GMX1_TX003_STAT7"            ,           0x1180010001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
17110         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
17111         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
17112         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
17113         {"GMX0_TX003_STAT8"            ,           0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
17114         {"GMX1_TX000_STAT8"            ,           0x11800100002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
17115         {"GMX1_TX001_STAT8"            ,           0x1180010000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
17116         {"GMX1_TX002_STAT8"            ,           0x11800100012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
17117         {"GMX1_TX003_STAT8"            ,           0x1180010001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
17118         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
17119         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
17120         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
17121         {"GMX0_TX003_STAT9"            ,           0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
17122         {"GMX1_TX000_STAT9"            ,           0x11800100002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
17123         {"GMX1_TX001_STAT9"            ,           0x1180010000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
17124         {"GMX1_TX002_STAT9"            ,           0x11800100012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
17125         {"GMX1_TX003_STAT9"            ,           0x1180010001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
17126         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
17127         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
17128         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
17129         {"GMX0_TX003_STATS_CTL"        ,           0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
17130         {"GMX1_TX000_STATS_CTL"        ,           0x1180010000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
17131         {"GMX1_TX001_STATS_CTL"        ,           0x1180010000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
17132         {"GMX1_TX002_STATS_CTL"        ,           0x1180010001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
17133         {"GMX1_TX003_STATS_CTL"        ,           0x1180010001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
17134         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
17135         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
17136         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
17137         {"GMX0_TX003_THRESH"           ,           0x1180008001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
17138         {"GMX1_TX000_THRESH"           ,           0x1180010000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
17139         {"GMX1_TX001_THRESH"           ,           0x1180010000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
17140         {"GMX1_TX002_THRESH"           ,           0x1180010001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
17141         {"GMX1_TX003_THRESH"           ,           0x1180010001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
17142         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
17143         {"GMX1_TX_BP"                  ,           0x11800100004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
17144         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
17145         {"GMX1_TX_COL_ATTEMPT"         ,           0x1180010000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
17146         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
17147         {"GMX1_TX_CORRUPT"             ,           0x11800100004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
17148         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
17149         {"GMX1_TX_IFG"                 ,           0x1180010000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
17150         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
17151         {"GMX1_TX_INT_EN"              ,           0x1180010000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
17152         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
17153         {"GMX1_TX_INT_REG"             ,           0x1180010000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
17154         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
17155         {"GMX1_TX_JAM"                 ,           0x1180010000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
17156         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
17157         {"GMX1_TX_LFSR"                ,           0x11800100004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
17158         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
17159         {"GMX1_TX_OVR_BP"              ,           0x11800100004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
17160         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
17161         {"GMX1_TX_PAUSE_PKT_DMAC"      ,           0x11800100004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
17162         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
17163         {"GMX1_TX_PAUSE_PKT_TYPE"      ,           0x11800100004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
17164         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
17165         {"GMX1_TX_PRTS"                ,           0x1180010000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
17166         {"GMX0_TX_SPI_CTL"             ,           0x11800080004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
17167         {"GMX1_TX_SPI_CTL"             ,           0x11800100004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
17168         {"GMX0_TX_SPI_DRAIN"           ,           0x11800080004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
17169         {"GMX1_TX_SPI_DRAIN"           ,           0x11800100004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
17170         {"GMX0_TX_SPI_MAX"             ,           0x11800080004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
17171         {"GMX1_TX_SPI_MAX"             ,           0x11800100004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
17172         {"GMX0_TX_SPI_THRESH"          ,           0x11800080004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
17173         {"GMX1_TX_SPI_THRESH"          ,           0x11800100004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
17174         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17175         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17176         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17177         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17178         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17179         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17180         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17181         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17182         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17183         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17184         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17185         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17186         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17187         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17188         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17189         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
17190         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
17191         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     162},
17192         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
17193         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
17194         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
17195         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
17196         {"IOB_DWB_PRI_CNT"             ,           0x11800F0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
17197         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
17198         {"IOB_I2C_PRI_CNT"             ,           0x11800F0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
17199         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
17200         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
17201         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
17202         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
17203         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
17204         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
17205         {"IOB_N2C_L2C_PRI_CNT"         ,           0x11800F0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
17206         {"IOB_N2C_RSP_PRI_CNT"         ,           0x11800F0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
17207         {"IOB_OUTB_COM_PRI_CNT"        ,           0x11800F0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
17208         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
17209         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
17210         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
17211         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
17212         {"IOB_OUTB_FPA_PRI_CNT"        ,           0x11800F0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
17213         {"IOB_OUTB_REQ_PRI_CNT"        ,           0x11800F0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
17214         {"IOB_P2C_REQ_PRI_CNT"         ,           0x11800F0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
17215         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
17216         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     187},
17217         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     188},
17218         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     189},
17219         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     190},
17220         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
17221         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
17222         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     193},
17223         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     194},
17224         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     195},
17225         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
17226         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
17227         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     198},
17228         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17229         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17230         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17231         {"IPD_PORT3_BP_PAGE_CNT"       ,           0x14F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17232         {"IPD_PORT4_BP_PAGE_CNT"       ,           0x14F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17233         {"IPD_PORT5_BP_PAGE_CNT"       ,           0x14F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17234         {"IPD_PORT6_BP_PAGE_CNT"       ,           0x14F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17235         {"IPD_PORT7_BP_PAGE_CNT"       ,           0x14F0000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17236         {"IPD_PORT8_BP_PAGE_CNT"       ,           0x14F0000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17237         {"IPD_PORT9_BP_PAGE_CNT"       ,           0x14F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17238         {"IPD_PORT10_BP_PAGE_CNT"      ,           0x14F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17239         {"IPD_PORT11_BP_PAGE_CNT"      ,           0x14F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17240         {"IPD_PORT12_BP_PAGE_CNT"      ,           0x14F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17241         {"IPD_PORT13_BP_PAGE_CNT"      ,           0x14F0000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17242         {"IPD_PORT14_BP_PAGE_CNT"      ,           0x14F0000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17243         {"IPD_PORT15_BP_PAGE_CNT"      ,           0x14F00000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17244         {"IPD_PORT16_BP_PAGE_CNT"      ,           0x14F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17245         {"IPD_PORT17_BP_PAGE_CNT"      ,           0x14F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17246         {"IPD_PORT18_BP_PAGE_CNT"      ,           0x14F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17247         {"IPD_PORT19_BP_PAGE_CNT"      ,           0x14F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17248         {"IPD_PORT20_BP_PAGE_CNT"      ,           0x14F00000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17249         {"IPD_PORT21_BP_PAGE_CNT"      ,           0x14F00000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17250         {"IPD_PORT22_BP_PAGE_CNT"      ,           0x14F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17251         {"IPD_PORT23_BP_PAGE_CNT"      ,           0x14F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17252         {"IPD_PORT24_BP_PAGE_CNT"      ,           0x14F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17253         {"IPD_PORT25_BP_PAGE_CNT"      ,           0x14F00000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17254         {"IPD_PORT26_BP_PAGE_CNT"      ,           0x14F00000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17255         {"IPD_PORT27_BP_PAGE_CNT"      ,           0x14F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17256         {"IPD_PORT28_BP_PAGE_CNT"      ,           0x14F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17257         {"IPD_PORT29_BP_PAGE_CNT"      ,           0x14F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17258         {"IPD_PORT30_BP_PAGE_CNT"      ,           0x14F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17259         {"IPD_PORT31_BP_PAGE_CNT"      ,           0x14F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17260         {"IPD_PORT32_BP_PAGE_CNT"      ,           0x14F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17261         {"IPD_PORT33_BP_PAGE_CNT"      ,           0x14F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17262         {"IPD_PORT34_BP_PAGE_CNT"      ,           0x14F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17263         {"IPD_PORT35_BP_PAGE_CNT"      ,           0x14F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
17264         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17265         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17266         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17267         {"IPD_PORT_BP_COUNTERS_PAIR3"  ,           0x14F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17268         {"IPD_PORT_BP_COUNTERS_PAIR4"  ,           0x14F00000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17269         {"IPD_PORT_BP_COUNTERS_PAIR5"  ,           0x14F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17270         {"IPD_PORT_BP_COUNTERS_PAIR6"  ,           0x14F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17271         {"IPD_PORT_BP_COUNTERS_PAIR7"  ,           0x14F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17272         {"IPD_PORT_BP_COUNTERS_PAIR8"  ,           0x14F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17273         {"IPD_PORT_BP_COUNTERS_PAIR9"  ,           0x14F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17274         {"IPD_PORT_BP_COUNTERS_PAIR10" ,           0x14F0000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17275         {"IPD_PORT_BP_COUNTERS_PAIR11" ,           0x14F0000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17276         {"IPD_PORT_BP_COUNTERS_PAIR12" ,           0x14F0000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17277         {"IPD_PORT_BP_COUNTERS_PAIR13" ,           0x14F0000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17278         {"IPD_PORT_BP_COUNTERS_PAIR14" ,           0x14F0000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17279         {"IPD_PORT_BP_COUNTERS_PAIR15" ,           0x14F0000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17280         {"IPD_PORT_BP_COUNTERS_PAIR16" ,           0x14F0000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17281         {"IPD_PORT_BP_COUNTERS_PAIR17" ,           0x14F0000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17282         {"IPD_PORT_BP_COUNTERS_PAIR18" ,           0x14F0000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17283         {"IPD_PORT_BP_COUNTERS_PAIR19" ,           0x14F0000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17284         {"IPD_PORT_BP_COUNTERS_PAIR20" ,           0x14F0000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17285         {"IPD_PORT_BP_COUNTERS_PAIR21" ,           0x14F0000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17286         {"IPD_PORT_BP_COUNTERS_PAIR22" ,           0x14F0000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17287         {"IPD_PORT_BP_COUNTERS_PAIR23" ,           0x14F0000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17288         {"IPD_PORT_BP_COUNTERS_PAIR24" ,           0x14F0000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17289         {"IPD_PORT_BP_COUNTERS_PAIR25" ,           0x14F0000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17290         {"IPD_PORT_BP_COUNTERS_PAIR26" ,           0x14F0000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17291         {"IPD_PORT_BP_COUNTERS_PAIR27" ,           0x14F0000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17292         {"IPD_PORT_BP_COUNTERS_PAIR28" ,           0x14F0000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17293         {"IPD_PORT_BP_COUNTERS_PAIR29" ,           0x14F00000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17294         {"IPD_PORT_BP_COUNTERS_PAIR30" ,           0x14F00000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17295         {"IPD_PORT_BP_COUNTERS_PAIR31" ,           0x14F00000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17296         {"IPD_PORT_BP_COUNTERS_PAIR32" ,           0x14F00000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17297         {"IPD_PORT_BP_COUNTERS_PAIR33" ,           0x14F00000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17298         {"IPD_PORT_BP_COUNTERS_PAIR34" ,           0x14F00000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17299         {"IPD_PORT_BP_COUNTERS_PAIR35" ,           0x14F00000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
17300         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
17301         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
17302         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     203},
17303         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     204},
17304         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
17305         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
17306         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
17307         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
17308         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
17309         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
17310         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
17311         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
17312         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
17313         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     207},
17314         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
17315         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
17316         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
17317         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
17318         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
17319         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
17320         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
17321         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
17322         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
17323         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     210},
17324         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     211},
17325         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     212},
17326         {"KEY_BIST_REG"                ,           0x1180020000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     213},
17327         {"KEY_CTL_STATUS"              ,           0x1180020000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
17328         {"KEY_INT_ENB"                 ,           0x1180020000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
17329         {"KEY_INT_SUM"                 ,           0x1180020000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
17330         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
17331         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
17332         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     219},
17333         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     220},
17334         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     221},
17335         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
17336         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
17337         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
17338         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     225},
17339         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     226},
17340         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     227},
17341         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
17342         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
17343         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
17344         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
17345         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
17346         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
17347         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
17348         {"L2C_SPAR1"                   ,           0x1180080000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     232},
17349         {"L2C_SPAR2"                   ,           0x1180080000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
17350         {"L2C_SPAR3"                   ,           0x1180080000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     234},
17351         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     235},
17352         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     236},
17353         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     237},
17354         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
17355         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     239},
17356         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     240},
17357         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
17358         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
17359         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     243},
17360         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     244},
17361         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     245},
17362         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     246},
17363         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     247},
17364         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     248},
17365         {"LED_BLINK"                   ,           0x1180000001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     249},
17366         {"LED_CLK_PHASE"               ,           0x1180000001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
17367         {"LED_CYLON"                   ,           0x1180000001AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
17368         {"LED_DBG"                     ,           0x1180000001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
17369         {"LED_EN"                      ,           0x1180000001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
17370         {"LED_POLARITY"                ,           0x1180000001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
17371         {"LED_PRT"                     ,           0x1180000001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
17372         {"LED_PRT_FMT"                 ,           0x1180000001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
17373         {"LED_PRT_STATUS0"             ,           0x1180000001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
17374         {"LED_PRT_STATUS1"             ,           0x1180000001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
17375         {"LED_PRT_STATUS2"             ,           0x1180000001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
17376         {"LED_PRT_STATUS3"             ,           0x1180000001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
17377         {"LED_PRT_STATUS4"             ,           0x1180000001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
17378         {"LED_PRT_STATUS5"             ,           0x1180000001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
17379         {"LED_PRT_STATUS6"             ,           0x1180000001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
17380         {"LED_PRT_STATUS7"             ,           0x1180000001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
17381         {"LED_UDD_CNT0"                ,           0x1180000001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
17382         {"LED_UDD_CNT1"                ,           0x1180000001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
17383         {"LED_UDD_DAT0"                ,           0x1180000001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
17384         {"LED_UDD_DAT1"                ,           0x1180000001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
17385         {"LED_UDD_DAT_CLR0"            ,           0x1180000001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
17386         {"LED_UDD_DAT_CLR1"            ,           0x1180000001AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
17387         {"LED_UDD_DAT_SET0"            ,           0x1180000001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
17388         {"LED_UDD_DAT_SET1"            ,           0x1180000001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
17389         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
17390         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
17391         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
17392         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
17393         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
17394         {"LMC0_DELAY_CFG"              ,           0x1180088000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
17395         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
17396         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
17397         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
17398         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
17399         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
17400         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
17401         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
17402         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
17403         {"LMC0_PLL_BWCTL"              ,           0x1180088000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
17404         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
17405         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
17406         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
17407         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
17408         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
17409         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
17410         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
17411         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
17412         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
17413         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
17414         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
17415         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
17416         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
17417         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
17418         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
17419         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
17420         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
17421         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
17422         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
17423         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
17424         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
17425         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
17426         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
17427         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
17428         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
17429         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     287},
17430         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     288},
17431         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     289},
17432         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
17433         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
17434         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     292},
17435         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
17436         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     294},
17437         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     295},
17438         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     296},
17439         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
17440         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     298},
17441         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
17442         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
17443         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
17444         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
17445         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
17446         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
17447         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
17448         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
17449         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
17450         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
17451         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
17452         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
17453         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
17454         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
17455         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
17456         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
17457         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
17458         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
17459         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
17460         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
17461         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
17462         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
17463         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
17464         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
17465         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
17466         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
17467         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
17468         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
17469         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
17470         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
17471         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
17472         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
17473         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
17474         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
17475         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
17476         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
17477         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
17478         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
17479         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
17480         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
17481         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
17482         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
17483         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
17484         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
17485         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
17486         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
17487         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
17488         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
17489         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
17490         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
17491         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
17492         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
17493         {"NPI_BASE_ADDR_INPUT0"        ,           0x11F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     326},
17494         {"NPI_BASE_ADDR_INPUT1"        ,           0x11F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     326},
17495         {"NPI_BASE_ADDR_INPUT2"        ,           0x11F0000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     326},
17496         {"NPI_BASE_ADDR_INPUT3"        ,           0x11F00000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     326},
17497         {"NPI_BASE_ADDR_OUTPUT0"       ,           0x11F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     327},
17498         {"NPI_BASE_ADDR_OUTPUT1"       ,           0x11F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     327},
17499         {"NPI_BASE_ADDR_OUTPUT2"       ,           0x11F00000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     327},
17500         {"NPI_BASE_ADDR_OUTPUT3"       ,           0x11F00000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     327},
17501         {"NPI_BIST_STATUS"             ,           0x11F00000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     328},
17502         {"NPI_BUFF_SIZE_OUTPUT0"       ,           0x11F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     329},
17503         {"NPI_BUFF_SIZE_OUTPUT1"       ,           0x11F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     329},
17504         {"NPI_BUFF_SIZE_OUTPUT2"       ,           0x11F00000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     329},
17505         {"NPI_BUFF_SIZE_OUTPUT3"       ,           0x11F00000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     329},
17506         {"NPI_CTL_STATUS"              ,           0x11F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     330},
17507         {"NPI_DBG_SELECT"              ,           0x11F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     331},
17508         {"NPI_DMA_CONTROL"             ,           0x11F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     332},
17509         {"NPI_DMA_HIGHP_COUNTS"        ,           0x11F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     333},
17510         {"NPI_DMA_HIGHP_NADDR"         ,           0x11F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     334},
17511         {"NPI_DMA_LOWP_COUNTS"         ,           0x11F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     335},
17512         {"NPI_DMA_LOWP_NADDR"          ,           0x11F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     336},
17513         {"NPI_HIGHP_DBELL"             ,           0x11F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     337},
17514         {"NPI_HIGHP_IBUFF_SADDR"       ,           0x11F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     338},
17515         {"NPI_INPUT_CONTROL"           ,           0x11F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     339},
17516         {"NPI_INT_ENB"                 ,           0x11F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     340},
17517         {"NPI_INT_SUM"                 ,           0x11F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     341},
17518         {"NPI_LOWP_DBELL"              ,           0x11F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     342},
17519         {"NPI_LOWP_IBUFF_SADDR"        ,           0x11F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     343},
17520         {"NPI_MEM_ACCESS_SUBID3"       ,           0x11F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     344},
17521         {"NPI_MEM_ACCESS_SUBID4"       ,           0x11F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     344},
17522         {"NPI_MEM_ACCESS_SUBID5"       ,           0x11F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     344},
17523         {"NPI_MEM_ACCESS_SUBID6"       ,           0x11F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     344},
17524         {"NPI_MSI_RCV"                 ,           0x11F0000001190ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     345},
17525         {"NPI_NUM_DESC_OUTPUT0"        ,           0x11F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
17526         {"NPI_NUM_DESC_OUTPUT1"        ,           0x11F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
17527         {"NPI_NUM_DESC_OUTPUT2"        ,           0x11F0000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
17528         {"NPI_NUM_DESC_OUTPUT3"        ,           0x11F0000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
17529         {"NPI_OUTPUT_CONTROL"          ,           0x11F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     347},
17530         {"NPI_P0_DBPAIR_ADDR"          ,           0x11F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
17531         {"NPI_P1_DBPAIR_ADDR"          ,           0x11F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
17532         {"NPI_P2_DBPAIR_ADDR"          ,           0x11F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
17533         {"NPI_P3_DBPAIR_ADDR"          ,           0x11F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
17534         {"NPI_P0_INSTR_ADDR"           ,           0x11F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     349},
17535         {"NPI_P1_INSTR_ADDR"           ,           0x11F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     349},
17536         {"NPI_P2_INSTR_ADDR"           ,           0x11F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     349},
17537         {"NPI_P3_INSTR_ADDR"           ,           0x11F00000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     349},
17538         {"NPI_P0_INSTR_CNTS"           ,           0x11F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     350},
17539         {"NPI_P1_INSTR_CNTS"           ,           0x11F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     350},
17540         {"NPI_P2_INSTR_CNTS"           ,           0x11F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     350},
17541         {"NPI_P3_INSTR_CNTS"           ,           0x11F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     350},
17542         {"NPI_P0_PAIR_CNTS"            ,           0x11F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
17543         {"NPI_P1_PAIR_CNTS"            ,           0x11F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
17544         {"NPI_P2_PAIR_CNTS"            ,           0x11F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
17545         {"NPI_P3_PAIR_CNTS"            ,           0x11F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
17546         {"NPI_PCI_BURST_SIZE"          ,           0x11F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     352},
17547         {"NPI_PCI_INT_ARB_CFG"         ,           0x11F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     353},
17548         {"NPI_PCI_READ_CMD"            ,           0x11F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     354},
17549         {"NPI_PORT32_INSTR_HDR"        ,           0x11F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     355},
17550         {"NPI_PORT33_INSTR_HDR"        ,           0x11F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     356},
17551         {"NPI_PORT34_INSTR_HDR"        ,           0x11F0000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     357},
17552         {"NPI_PORT35_INSTR_HDR"        ,           0x11F0000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     358},
17553         {"NPI_PORT_BP_CONTROL"         ,           0x11F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     359},
17554         {"NPI_RSL_INT_BLOCKS"          ,           0x11F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     360},
17555         {"NPI_SIZE_INPUT0"             ,           0x11F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     361},
17556         {"NPI_SIZE_INPUT1"             ,           0x11F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     361},
17557         {"NPI_SIZE_INPUT2"             ,           0x11F0000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     361},
17558         {"NPI_SIZE_INPUT3"             ,           0x11F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     361},
17559         {"NPI_WIN_READ_TO"             ,           0x11F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     362},
17560         {"PCI_BAR1_INDEX0"             ,           0x11F0000001100ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17561         {"PCI_BAR1_INDEX1"             ,           0x11F0000001104ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17562         {"PCI_BAR1_INDEX2"             ,           0x11F0000001108ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17563         {"PCI_BAR1_INDEX3"             ,           0x11F000000110Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17564         {"PCI_BAR1_INDEX4"             ,           0x11F0000001110ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17565         {"PCI_BAR1_INDEX5"             ,           0x11F0000001114ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17566         {"PCI_BAR1_INDEX6"             ,           0x11F0000001118ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17567         {"PCI_BAR1_INDEX7"             ,           0x11F000000111Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17568         {"PCI_BAR1_INDEX8"             ,           0x11F0000001120ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17569         {"PCI_BAR1_INDEX9"             ,           0x11F0000001124ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17570         {"PCI_BAR1_INDEX10"            ,           0x11F0000001128ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17571         {"PCI_BAR1_INDEX11"            ,           0x11F000000112Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17572         {"PCI_BAR1_INDEX12"            ,           0x11F0000001130ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17573         {"PCI_BAR1_INDEX13"            ,           0x11F0000001134ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17574         {"PCI_BAR1_INDEX14"            ,           0x11F0000001138ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17575         {"PCI_BAR1_INDEX15"            ,           0x11F000000113Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17576         {"PCI_BAR1_INDEX16"            ,           0x11F0000001140ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17577         {"PCI_BAR1_INDEX17"            ,           0x11F0000001144ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17578         {"PCI_BAR1_INDEX18"            ,           0x11F0000001148ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17579         {"PCI_BAR1_INDEX19"            ,           0x11F000000114Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17580         {"PCI_BAR1_INDEX20"            ,           0x11F0000001150ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17581         {"PCI_BAR1_INDEX21"            ,           0x11F0000001154ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17582         {"PCI_BAR1_INDEX22"            ,           0x11F0000001158ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17583         {"PCI_BAR1_INDEX23"            ,           0x11F000000115Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17584         {"PCI_BAR1_INDEX24"            ,           0x11F0000001160ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17585         {"PCI_BAR1_INDEX25"            ,           0x11F0000001164ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17586         {"PCI_BAR1_INDEX26"            ,           0x11F0000001168ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17587         {"PCI_BAR1_INDEX27"            ,           0x11F000000116Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17588         {"PCI_BAR1_INDEX28"            ,           0x11F0000001170ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17589         {"PCI_BAR1_INDEX29"            ,           0x11F0000001174ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17590         {"PCI_BAR1_INDEX30"            ,           0x11F0000001178ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17591         {"PCI_BAR1_INDEX31"            ,           0x11F000000117Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     363},
17592         {"PCI_CFG00"                   ,           0x11F0000001800ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     364},
17593         {"PCI_CFG01"                   ,           0x11F0000001804ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     365},
17594         {"PCI_CFG02"                   ,           0x11F0000001808ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     366},
17595         {"PCI_CFG03"                   ,           0x11F000000180Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     367},
17596         {"PCI_CFG04"                   ,           0x11F0000001810ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     368},
17597         {"PCI_CFG05"                   ,           0x11F0000001814ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     369},
17598         {"PCI_CFG06"                   ,           0x11F0000001818ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     370},
17599         {"PCI_CFG07"                   ,           0x11F000000181Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     371},
17600         {"PCI_CFG08"                   ,           0x11F0000001820ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     372},
17601         {"PCI_CFG09"                   ,           0x11F0000001824ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     373},
17602         {"PCI_CFG10"                   ,           0x11F0000001828ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     374},
17603         {"PCI_CFG11"                   ,           0x11F000000182Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     375},
17604         {"PCI_CFG12"                   ,           0x11F0000001830ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     376},
17605         {"PCI_CFG13"                   ,           0x11F0000001834ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     377},
17606         {"PCI_CFG15"                   ,           0x11F000000183Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     378},
17607         {"PCI_CFG16"                   ,           0x11F0000001840ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     379},
17608         {"PCI_CFG17"                   ,           0x11F0000001844ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     380},
17609         {"PCI_CFG18"                   ,           0x11F0000001848ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     381},
17610         {"PCI_CFG19"                   ,           0x11F000000184Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     382},
17611         {"PCI_CFG20"                   ,           0x11F0000001850ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     383},
17612         {"PCI_CFG21"                   ,           0x11F0000001854ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     384},
17613         {"PCI_CFG22"                   ,           0x11F0000001858ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     385},
17614         {"PCI_CFG56"                   ,           0x11F00000018E0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     386},
17615         {"PCI_CFG57"                   ,           0x11F00000018E4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     387},
17616         {"PCI_CFG58"                   ,           0x11F00000018E8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     388},
17617         {"PCI_CFG59"                   ,           0x11F00000018ECull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     389},
17618         {"PCI_CFG60"                   ,           0x11F00000018F0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     390},
17619         {"PCI_CFG61"                   ,           0x11F00000018F4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     391},
17620         {"PCI_CFG62"                   ,           0x11F00000018F8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     392},
17621         {"PCI_CFG63"                   ,           0x11F00000018FCull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     393},
17622         {"PCI_CTL_STATUS_2"            ,           0x11F000000118Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     394},
17623         {"PCI_DBELL0"                  ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCI,   32,     395},
17624         {"PCI_DBELL1"                  ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCI,   32,     395},
17625         {"PCI_DBELL2"                  ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCI,   32,     395},
17626         {"PCI_DBELL3"                  ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCI,   32,     395},
17627         {"PCI_DMA_CNT0"                ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     396},
17628         {"PCI_DMA_CNT1"                ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCI,   32,     396},
17629         {"PCI_DMA_INT_LEV0"            ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     397},
17630         {"PCI_DMA_INT_LEV1"            ,                      0xACull,  CVMX_CSR_DB_TYPE_PCI,   32,     397},
17631         {"PCI_DMA_TIME0"               ,                      0xB0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     398},
17632         {"PCI_DMA_TIME1"               ,                      0xB4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     398},
17633         {"PCI_INSTR_COUNT0"            ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCI,   32,     399},
17634         {"PCI_INSTR_COUNT1"            ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     399},
17635         {"PCI_INSTR_COUNT2"            ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCI,   32,     399},
17636         {"PCI_INSTR_COUNT3"            ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     399},
17637         {"PCI_INT_ENB"                 ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCI,   64,     400},
17638         {"PCI_INT_ENB2"                ,           0x11F00000011A0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     401},
17639         {"PCI_INT_SUM"                 ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCI,   64,     402},
17640         {"PCI_INT_SUM2"                ,           0x11F0000001198ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     403},
17641         {"PCI_MSI_RCV"                 ,                      0xF0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     404},
17642         {"PCI_PKT_CREDITS0"            ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCI,   32,     405},
17643         {"PCI_PKT_CREDITS1"            ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCI,   32,     405},
17644         {"PCI_PKT_CREDITS2"            ,                      0x64ull,  CVMX_CSR_DB_TYPE_PCI,   32,     405},
17645         {"PCI_PKT_CREDITS3"            ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCI,   32,     405},
17646         {"PCI_PKTS_SENT0"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCI,   32,     406},
17647         {"PCI_PKTS_SENT1"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCI,   32,     406},
17648         {"PCI_PKTS_SENT2"              ,                      0x60ull,  CVMX_CSR_DB_TYPE_PCI,   32,     406},
17649         {"PCI_PKTS_SENT3"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCI,   32,     406},
17650         {"PCI_PKTS_SENT_INT_LEV0"      ,                      0x48ull,  CVMX_CSR_DB_TYPE_PCI,   32,     407},
17651         {"PCI_PKTS_SENT_INT_LEV1"      ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCI,   32,     407},
17652         {"PCI_PKTS_SENT_INT_LEV2"      ,                      0x68ull,  CVMX_CSR_DB_TYPE_PCI,   32,     407},
17653         {"PCI_PKTS_SENT_INT_LEV3"      ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCI,   32,     407},
17654         {"PCI_PKTS_SENT_TIME0"         ,                      0x4Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     408},
17655         {"PCI_PKTS_SENT_TIME1"         ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     408},
17656         {"PCI_PKTS_SENT_TIME2"         ,                      0x6Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     408},
17657         {"PCI_PKTS_SENT_TIME3"         ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     408},
17658         {"PCI_READ_CMD_6"              ,           0x11F0000001180ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     409},
17659         {"PCI_READ_CMD_C"              ,           0x11F0000001184ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     410},
17660         {"PCI_READ_CMD_E"              ,           0x11F0000001188ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     411},
17661         {"PCI_READ_TIMEOUT"            ,           0x11F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     412},
17662         {"PCI_SCM_REG"                 ,           0x11F00000011A8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     413},
17663         {"PCI_TSR_REG"                 ,           0x11F00000011B0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     414},
17664         {"PCI_WIN_RD_ADDR"             ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCI,   64,     415},
17665         {"PCI_WIN_RD_DATA"             ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCI,   64,     416},
17666         {"PCI_WIN_WR_ADDR"             ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCI,   64,     417},
17667         {"PCI_WIN_WR_DATA"             ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCI,   64,     418},
17668         {"PCI_WIN_WR_MASK"             ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCI,   64,     419},
17669         {"PIP_BCK_PRS"                 ,           0x11800A0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
17670         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
17671         {"PIP_CRC_CTL0"                ,           0x11800A0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
17672         {"PIP_CRC_CTL1"                ,           0x11800A0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
17673         {"PIP_CRC_IV0"                 ,           0x11800A0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
17674         {"PIP_CRC_IV1"                 ,           0x11800A0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
17675         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
17676         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
17677         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
17678         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
17679         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
17680         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
17681         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
17682         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
17683         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
17684         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17685         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17686         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17687         {"PIP_PRT_CFG3"                ,           0x11800A0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17688         {"PIP_PRT_CFG4"                ,           0x11800A0000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17689         {"PIP_PRT_CFG5"                ,           0x11800A0000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17690         {"PIP_PRT_CFG6"                ,           0x11800A0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17691         {"PIP_PRT_CFG7"                ,           0x11800A0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17692         {"PIP_PRT_CFG8"                ,           0x11800A0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17693         {"PIP_PRT_CFG9"                ,           0x11800A0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17694         {"PIP_PRT_CFG10"               ,           0x11800A0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17695         {"PIP_PRT_CFG11"               ,           0x11800A0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17696         {"PIP_PRT_CFG12"               ,           0x11800A0000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17697         {"PIP_PRT_CFG13"               ,           0x11800A0000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17698         {"PIP_PRT_CFG14"               ,           0x11800A0000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17699         {"PIP_PRT_CFG15"               ,           0x11800A0000278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17700         {"PIP_PRT_CFG16"               ,           0x11800A0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17701         {"PIP_PRT_CFG17"               ,           0x11800A0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17702         {"PIP_PRT_CFG18"               ,           0x11800A0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17703         {"PIP_PRT_CFG19"               ,           0x11800A0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17704         {"PIP_PRT_CFG20"               ,           0x11800A00002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17705         {"PIP_PRT_CFG21"               ,           0x11800A00002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17706         {"PIP_PRT_CFG22"               ,           0x11800A00002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17707         {"PIP_PRT_CFG23"               ,           0x11800A00002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17708         {"PIP_PRT_CFG24"               ,           0x11800A00002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17709         {"PIP_PRT_CFG25"               ,           0x11800A00002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17710         {"PIP_PRT_CFG26"               ,           0x11800A00002D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17711         {"PIP_PRT_CFG27"               ,           0x11800A00002D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17712         {"PIP_PRT_CFG28"               ,           0x11800A00002E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17713         {"PIP_PRT_CFG29"               ,           0x11800A00002E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17714         {"PIP_PRT_CFG30"               ,           0x11800A00002F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17715         {"PIP_PRT_CFG31"               ,           0x11800A00002F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17716         {"PIP_PRT_CFG32"               ,           0x11800A0000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17717         {"PIP_PRT_CFG33"               ,           0x11800A0000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17718         {"PIP_PRT_CFG34"               ,           0x11800A0000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17719         {"PIP_PRT_CFG35"               ,           0x11800A0000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
17720         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17721         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17722         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17723         {"PIP_PRT_TAG3"                ,           0x11800A0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17724         {"PIP_PRT_TAG4"                ,           0x11800A0000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17725         {"PIP_PRT_TAG5"                ,           0x11800A0000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17726         {"PIP_PRT_TAG6"                ,           0x11800A0000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17727         {"PIP_PRT_TAG7"                ,           0x11800A0000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17728         {"PIP_PRT_TAG8"                ,           0x11800A0000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17729         {"PIP_PRT_TAG9"                ,           0x11800A0000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17730         {"PIP_PRT_TAG10"               ,           0x11800A0000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17731         {"PIP_PRT_TAG11"               ,           0x11800A0000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17732         {"PIP_PRT_TAG12"               ,           0x11800A0000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17733         {"PIP_PRT_TAG13"               ,           0x11800A0000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17734         {"PIP_PRT_TAG14"               ,           0x11800A0000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17735         {"PIP_PRT_TAG15"               ,           0x11800A0000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17736         {"PIP_PRT_TAG16"               ,           0x11800A0000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17737         {"PIP_PRT_TAG17"               ,           0x11800A0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17738         {"PIP_PRT_TAG18"               ,           0x11800A0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17739         {"PIP_PRT_TAG19"               ,           0x11800A0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17740         {"PIP_PRT_TAG20"               ,           0x11800A00004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17741         {"PIP_PRT_TAG21"               ,           0x11800A00004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17742         {"PIP_PRT_TAG22"               ,           0x11800A00004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17743         {"PIP_PRT_TAG23"               ,           0x11800A00004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17744         {"PIP_PRT_TAG24"               ,           0x11800A00004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17745         {"PIP_PRT_TAG25"               ,           0x11800A00004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17746         {"PIP_PRT_TAG26"               ,           0x11800A00004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17747         {"PIP_PRT_TAG27"               ,           0x11800A00004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17748         {"PIP_PRT_TAG28"               ,           0x11800A00004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17749         {"PIP_PRT_TAG29"               ,           0x11800A00004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17750         {"PIP_PRT_TAG30"               ,           0x11800A00004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17751         {"PIP_PRT_TAG31"               ,           0x11800A00004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17752         {"PIP_PRT_TAG32"               ,           0x11800A0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17753         {"PIP_PRT_TAG33"               ,           0x11800A0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17754         {"PIP_PRT_TAG34"               ,           0x11800A0000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17755         {"PIP_PRT_TAG35"               ,           0x11800A0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
17756         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17757         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17758         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17759         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17760         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17761         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17762         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17763         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17764         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17765         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17766         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17767         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17768         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17769         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17770         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17771         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17772         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17773         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17774         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17775         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17776         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17777         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17778         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17779         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17780         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17781         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17782         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17783         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17784         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17785         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17786         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17787         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17788         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17789         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17790         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17791         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17792         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17793         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17794         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17795         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17796         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17797         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17798         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17799         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17800         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17801         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17802         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17803         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17804         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17805         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17806         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17807         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17808         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17809         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17810         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17811         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17812         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17813         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17814         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17815         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17816         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17817         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17818         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17819         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
17820         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
17821         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
17822         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
17823         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
17824         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
17825         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
17826         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
17827         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
17828         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
17829         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
17830         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
17831         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
17832         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
17833         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
17834         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17835         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17836         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17837         {"PIP_STAT0_PRT3"              ,           0x11800A00008F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17838         {"PIP_STAT0_PRT4"              ,           0x11800A0000940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17839         {"PIP_STAT0_PRT5"              ,           0x11800A0000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17840         {"PIP_STAT0_PRT6"              ,           0x11800A00009E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17841         {"PIP_STAT0_PRT7"              ,           0x11800A0000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17842         {"PIP_STAT0_PRT8"              ,           0x11800A0000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17843         {"PIP_STAT0_PRT9"              ,           0x11800A0000AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17844         {"PIP_STAT0_PRT10"             ,           0x11800A0000B20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17845         {"PIP_STAT0_PRT11"             ,           0x11800A0000B70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17846         {"PIP_STAT0_PRT12"             ,           0x11800A0000BC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17847         {"PIP_STAT0_PRT13"             ,           0x11800A0000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17848         {"PIP_STAT0_PRT14"             ,           0x11800A0000C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17849         {"PIP_STAT0_PRT15"             ,           0x11800A0000CB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17850         {"PIP_STAT0_PRT16"             ,           0x11800A0000D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17851         {"PIP_STAT0_PRT17"             ,           0x11800A0000D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17852         {"PIP_STAT0_PRT18"             ,           0x11800A0000DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17853         {"PIP_STAT0_PRT19"             ,           0x11800A0000DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17854         {"PIP_STAT0_PRT20"             ,           0x11800A0000E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17855         {"PIP_STAT0_PRT21"             ,           0x11800A0000E90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17856         {"PIP_STAT0_PRT22"             ,           0x11800A0000EE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17857         {"PIP_STAT0_PRT23"             ,           0x11800A0000F30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17858         {"PIP_STAT0_PRT24"             ,           0x11800A0000F80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17859         {"PIP_STAT0_PRT25"             ,           0x11800A0000FD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17860         {"PIP_STAT0_PRT26"             ,           0x11800A0001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17861         {"PIP_STAT0_PRT27"             ,           0x11800A0001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17862         {"PIP_STAT0_PRT28"             ,           0x11800A00010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17863         {"PIP_STAT0_PRT29"             ,           0x11800A0001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17864         {"PIP_STAT0_PRT30"             ,           0x11800A0001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17865         {"PIP_STAT0_PRT31"             ,           0x11800A00011B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17866         {"PIP_STAT0_PRT32"             ,           0x11800A0001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17867         {"PIP_STAT0_PRT33"             ,           0x11800A0001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17868         {"PIP_STAT0_PRT34"             ,           0x11800A00012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17869         {"PIP_STAT0_PRT35"             ,           0x11800A00012F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
17870         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17871         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17872         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17873         {"PIP_STAT1_PRT3"              ,           0x11800A00008F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17874         {"PIP_STAT1_PRT4"              ,           0x11800A0000948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17875         {"PIP_STAT1_PRT5"              ,           0x11800A0000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17876         {"PIP_STAT1_PRT6"              ,           0x11800A00009E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17877         {"PIP_STAT1_PRT7"              ,           0x11800A0000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17878         {"PIP_STAT1_PRT8"              ,           0x11800A0000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17879         {"PIP_STAT1_PRT9"              ,           0x11800A0000AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17880         {"PIP_STAT1_PRT10"             ,           0x11800A0000B28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17881         {"PIP_STAT1_PRT11"             ,           0x11800A0000B78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17882         {"PIP_STAT1_PRT12"             ,           0x11800A0000BC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17883         {"PIP_STAT1_PRT13"             ,           0x11800A0000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17884         {"PIP_STAT1_PRT14"             ,           0x11800A0000C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17885         {"PIP_STAT1_PRT15"             ,           0x11800A0000CB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17886         {"PIP_STAT1_PRT16"             ,           0x11800A0000D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17887         {"PIP_STAT1_PRT17"             ,           0x11800A0000D58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17888         {"PIP_STAT1_PRT18"             ,           0x11800A0000DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17889         {"PIP_STAT1_PRT19"             ,           0x11800A0000DF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17890         {"PIP_STAT1_PRT20"             ,           0x11800A0000E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17891         {"PIP_STAT1_PRT21"             ,           0x11800A0000E98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17892         {"PIP_STAT1_PRT22"             ,           0x11800A0000EE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17893         {"PIP_STAT1_PRT23"             ,           0x11800A0000F38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17894         {"PIP_STAT1_PRT24"             ,           0x11800A0000F88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17895         {"PIP_STAT1_PRT25"             ,           0x11800A0000FD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17896         {"PIP_STAT1_PRT26"             ,           0x11800A0001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17897         {"PIP_STAT1_PRT27"             ,           0x11800A0001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17898         {"PIP_STAT1_PRT28"             ,           0x11800A00010C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17899         {"PIP_STAT1_PRT29"             ,           0x11800A0001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17900         {"PIP_STAT1_PRT30"             ,           0x11800A0001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17901         {"PIP_STAT1_PRT31"             ,           0x11800A00011B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17902         {"PIP_STAT1_PRT32"             ,           0x11800A0001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17903         {"PIP_STAT1_PRT33"             ,           0x11800A0001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17904         {"PIP_STAT1_PRT34"             ,           0x11800A00012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17905         {"PIP_STAT1_PRT35"             ,           0x11800A00012F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
17906         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17907         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17908         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17909         {"PIP_STAT2_PRT3"              ,           0x11800A0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17910         {"PIP_STAT2_PRT4"              ,           0x11800A0000950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17911         {"PIP_STAT2_PRT5"              ,           0x11800A00009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17912         {"PIP_STAT2_PRT6"              ,           0x11800A00009F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17913         {"PIP_STAT2_PRT7"              ,           0x11800A0000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17914         {"PIP_STAT2_PRT8"              ,           0x11800A0000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17915         {"PIP_STAT2_PRT9"              ,           0x11800A0000AE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17916         {"PIP_STAT2_PRT10"             ,           0x11800A0000B30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17917         {"PIP_STAT2_PRT11"             ,           0x11800A0000B80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17918         {"PIP_STAT2_PRT12"             ,           0x11800A0000BD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17919         {"PIP_STAT2_PRT13"             ,           0x11800A0000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17920         {"PIP_STAT2_PRT14"             ,           0x11800A0000C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17921         {"PIP_STAT2_PRT15"             ,           0x11800A0000CC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17922         {"PIP_STAT2_PRT16"             ,           0x11800A0000D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17923         {"PIP_STAT2_PRT17"             ,           0x11800A0000D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17924         {"PIP_STAT2_PRT18"             ,           0x11800A0000DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17925         {"PIP_STAT2_PRT19"             ,           0x11800A0000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17926         {"PIP_STAT2_PRT20"             ,           0x11800A0000E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17927         {"PIP_STAT2_PRT21"             ,           0x11800A0000EA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17928         {"PIP_STAT2_PRT22"             ,           0x11800A0000EF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17929         {"PIP_STAT2_PRT23"             ,           0x11800A0000F40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17930         {"PIP_STAT2_PRT24"             ,           0x11800A0000F90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17931         {"PIP_STAT2_PRT25"             ,           0x11800A0000FE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17932         {"PIP_STAT2_PRT26"             ,           0x11800A0001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17933         {"PIP_STAT2_PRT27"             ,           0x11800A0001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17934         {"PIP_STAT2_PRT28"             ,           0x11800A00010D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17935         {"PIP_STAT2_PRT29"             ,           0x11800A0001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17936         {"PIP_STAT2_PRT30"             ,           0x11800A0001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17937         {"PIP_STAT2_PRT31"             ,           0x11800A00011C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17938         {"PIP_STAT2_PRT32"             ,           0x11800A0001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17939         {"PIP_STAT2_PRT33"             ,           0x11800A0001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17940         {"PIP_STAT2_PRT34"             ,           0x11800A00012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17941         {"PIP_STAT2_PRT35"             ,           0x11800A0001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
17942         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17943         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17944         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17945         {"PIP_STAT3_PRT3"              ,           0x11800A0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17946         {"PIP_STAT3_PRT4"              ,           0x11800A0000958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17947         {"PIP_STAT3_PRT5"              ,           0x11800A00009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17948         {"PIP_STAT3_PRT6"              ,           0x11800A00009F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17949         {"PIP_STAT3_PRT7"              ,           0x11800A0000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17950         {"PIP_STAT3_PRT8"              ,           0x11800A0000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17951         {"PIP_STAT3_PRT9"              ,           0x11800A0000AE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17952         {"PIP_STAT3_PRT10"             ,           0x11800A0000B38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17953         {"PIP_STAT3_PRT11"             ,           0x11800A0000B88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17954         {"PIP_STAT3_PRT12"             ,           0x11800A0000BD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17955         {"PIP_STAT3_PRT13"             ,           0x11800A0000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17956         {"PIP_STAT3_PRT14"             ,           0x11800A0000C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17957         {"PIP_STAT3_PRT15"             ,           0x11800A0000CC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17958         {"PIP_STAT3_PRT16"             ,           0x11800A0000D18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17959         {"PIP_STAT3_PRT17"             ,           0x11800A0000D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17960         {"PIP_STAT3_PRT18"             ,           0x11800A0000DB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17961         {"PIP_STAT3_PRT19"             ,           0x11800A0000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17962         {"PIP_STAT3_PRT20"             ,           0x11800A0000E58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17963         {"PIP_STAT3_PRT21"             ,           0x11800A0000EA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17964         {"PIP_STAT3_PRT22"             ,           0x11800A0000EF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17965         {"PIP_STAT3_PRT23"             ,           0x11800A0000F48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17966         {"PIP_STAT3_PRT24"             ,           0x11800A0000F98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17967         {"PIP_STAT3_PRT25"             ,           0x11800A0000FE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17968         {"PIP_STAT3_PRT26"             ,           0x11800A0001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17969         {"PIP_STAT3_PRT27"             ,           0x11800A0001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17970         {"PIP_STAT3_PRT28"             ,           0x11800A00010D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17971         {"PIP_STAT3_PRT29"             ,           0x11800A0001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17972         {"PIP_STAT3_PRT30"             ,           0x11800A0001178ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17973         {"PIP_STAT3_PRT31"             ,           0x11800A00011C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17974         {"PIP_STAT3_PRT32"             ,           0x11800A0001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17975         {"PIP_STAT3_PRT33"             ,           0x11800A0001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17976         {"PIP_STAT3_PRT34"             ,           0x11800A00012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17977         {"PIP_STAT3_PRT35"             ,           0x11800A0001308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
17978         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17979         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17980         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17981         {"PIP_STAT4_PRT3"              ,           0x11800A0000910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17982         {"PIP_STAT4_PRT4"              ,           0x11800A0000960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17983         {"PIP_STAT4_PRT5"              ,           0x11800A00009B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17984         {"PIP_STAT4_PRT6"              ,           0x11800A0000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17985         {"PIP_STAT4_PRT7"              ,           0x11800A0000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17986         {"PIP_STAT4_PRT8"              ,           0x11800A0000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17987         {"PIP_STAT4_PRT9"              ,           0x11800A0000AF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17988         {"PIP_STAT4_PRT10"             ,           0x11800A0000B40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17989         {"PIP_STAT4_PRT11"             ,           0x11800A0000B90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17990         {"PIP_STAT4_PRT12"             ,           0x11800A0000BE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17991         {"PIP_STAT4_PRT13"             ,           0x11800A0000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17992         {"PIP_STAT4_PRT14"             ,           0x11800A0000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17993         {"PIP_STAT4_PRT15"             ,           0x11800A0000CD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17994         {"PIP_STAT4_PRT16"             ,           0x11800A0000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17995         {"PIP_STAT4_PRT17"             ,           0x11800A0000D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17996         {"PIP_STAT4_PRT18"             ,           0x11800A0000DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17997         {"PIP_STAT4_PRT19"             ,           0x11800A0000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17998         {"PIP_STAT4_PRT20"             ,           0x11800A0000E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
17999         {"PIP_STAT4_PRT21"             ,           0x11800A0000EB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18000         {"PIP_STAT4_PRT22"             ,           0x11800A0000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18001         {"PIP_STAT4_PRT23"             ,           0x11800A0000F50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18002         {"PIP_STAT4_PRT24"             ,           0x11800A0000FA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18003         {"PIP_STAT4_PRT25"             ,           0x11800A0000FF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18004         {"PIP_STAT4_PRT26"             ,           0x11800A0001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18005         {"PIP_STAT4_PRT27"             ,           0x11800A0001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18006         {"PIP_STAT4_PRT28"             ,           0x11800A00010E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18007         {"PIP_STAT4_PRT29"             ,           0x11800A0001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18008         {"PIP_STAT4_PRT30"             ,           0x11800A0001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18009         {"PIP_STAT4_PRT31"             ,           0x11800A00011D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18010         {"PIP_STAT4_PRT32"             ,           0x11800A0001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18011         {"PIP_STAT4_PRT33"             ,           0x11800A0001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18012         {"PIP_STAT4_PRT34"             ,           0x11800A00012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18013         {"PIP_STAT4_PRT35"             ,           0x11800A0001310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
18014         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18015         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18016         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18017         {"PIP_STAT5_PRT3"              ,           0x11800A0000918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18018         {"PIP_STAT5_PRT4"              ,           0x11800A0000968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18019         {"PIP_STAT5_PRT5"              ,           0x11800A00009B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18020         {"PIP_STAT5_PRT6"              ,           0x11800A0000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18021         {"PIP_STAT5_PRT7"              ,           0x11800A0000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18022         {"PIP_STAT5_PRT8"              ,           0x11800A0000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18023         {"PIP_STAT5_PRT9"              ,           0x11800A0000AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18024         {"PIP_STAT5_PRT10"             ,           0x11800A0000B48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18025         {"PIP_STAT5_PRT11"             ,           0x11800A0000B98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18026         {"PIP_STAT5_PRT12"             ,           0x11800A0000BE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18027         {"PIP_STAT5_PRT13"             ,           0x11800A0000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18028         {"PIP_STAT5_PRT14"             ,           0x11800A0000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18029         {"PIP_STAT5_PRT15"             ,           0x11800A0000CD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18030         {"PIP_STAT5_PRT16"             ,           0x11800A0000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18031         {"PIP_STAT5_PRT17"             ,           0x11800A0000D78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18032         {"PIP_STAT5_PRT18"             ,           0x11800A0000DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18033         {"PIP_STAT5_PRT19"             ,           0x11800A0000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18034         {"PIP_STAT5_PRT20"             ,           0x11800A0000E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18035         {"PIP_STAT5_PRT21"             ,           0x11800A0000EB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18036         {"PIP_STAT5_PRT22"             ,           0x11800A0000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18037         {"PIP_STAT5_PRT23"             ,           0x11800A0000F58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18038         {"PIP_STAT5_PRT24"             ,           0x11800A0000FA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18039         {"PIP_STAT5_PRT25"             ,           0x11800A0000FF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18040         {"PIP_STAT5_PRT26"             ,           0x11800A0001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18041         {"PIP_STAT5_PRT27"             ,           0x11800A0001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18042         {"PIP_STAT5_PRT28"             ,           0x11800A00010E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18043         {"PIP_STAT5_PRT29"             ,           0x11800A0001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18044         {"PIP_STAT5_PRT30"             ,           0x11800A0001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18045         {"PIP_STAT5_PRT31"             ,           0x11800A00011D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18046         {"PIP_STAT5_PRT32"             ,           0x11800A0001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18047         {"PIP_STAT5_PRT33"             ,           0x11800A0001278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18048         {"PIP_STAT5_PRT34"             ,           0x11800A00012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18049         {"PIP_STAT5_PRT35"             ,           0x11800A0001318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
18050         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18051         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18052         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18053         {"PIP_STAT6_PRT3"              ,           0x11800A0000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18054         {"PIP_STAT6_PRT4"              ,           0x11800A0000970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18055         {"PIP_STAT6_PRT5"              ,           0x11800A00009C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18056         {"PIP_STAT6_PRT6"              ,           0x11800A0000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18057         {"PIP_STAT6_PRT7"              ,           0x11800A0000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18058         {"PIP_STAT6_PRT8"              ,           0x11800A0000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18059         {"PIP_STAT6_PRT9"              ,           0x11800A0000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18060         {"PIP_STAT6_PRT10"             ,           0x11800A0000B50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18061         {"PIP_STAT6_PRT11"             ,           0x11800A0000BA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18062         {"PIP_STAT6_PRT12"             ,           0x11800A0000BF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18063         {"PIP_STAT6_PRT13"             ,           0x11800A0000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18064         {"PIP_STAT6_PRT14"             ,           0x11800A0000C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18065         {"PIP_STAT6_PRT15"             ,           0x11800A0000CE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18066         {"PIP_STAT6_PRT16"             ,           0x11800A0000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18067         {"PIP_STAT6_PRT17"             ,           0x11800A0000D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18068         {"PIP_STAT6_PRT18"             ,           0x11800A0000DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18069         {"PIP_STAT6_PRT19"             ,           0x11800A0000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18070         {"PIP_STAT6_PRT20"             ,           0x11800A0000E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18071         {"PIP_STAT6_PRT21"             ,           0x11800A0000EC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18072         {"PIP_STAT6_PRT22"             ,           0x11800A0000F10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18073         {"PIP_STAT6_PRT23"             ,           0x11800A0000F60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18074         {"PIP_STAT6_PRT24"             ,           0x11800A0000FB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18075         {"PIP_STAT6_PRT25"             ,           0x11800A0001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18076         {"PIP_STAT6_PRT26"             ,           0x11800A0001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18077         {"PIP_STAT6_PRT27"             ,           0x11800A00010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18078         {"PIP_STAT6_PRT28"             ,           0x11800A00010F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18079         {"PIP_STAT6_PRT29"             ,           0x11800A0001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18080         {"PIP_STAT6_PRT30"             ,           0x11800A0001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18081         {"PIP_STAT6_PRT31"             ,           0x11800A00011E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18082         {"PIP_STAT6_PRT32"             ,           0x11800A0001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18083         {"PIP_STAT6_PRT33"             ,           0x11800A0001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18084         {"PIP_STAT6_PRT34"             ,           0x11800A00012D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18085         {"PIP_STAT6_PRT35"             ,           0x11800A0001320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
18086         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18087         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18088         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18089         {"PIP_STAT7_PRT3"              ,           0x11800A0000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18090         {"PIP_STAT7_PRT4"              ,           0x11800A0000978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18091         {"PIP_STAT7_PRT5"              ,           0x11800A00009C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18092         {"PIP_STAT7_PRT6"              ,           0x11800A0000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18093         {"PIP_STAT7_PRT7"              ,           0x11800A0000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18094         {"PIP_STAT7_PRT8"              ,           0x11800A0000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18095         {"PIP_STAT7_PRT9"              ,           0x11800A0000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18096         {"PIP_STAT7_PRT10"             ,           0x11800A0000B58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18097         {"PIP_STAT7_PRT11"             ,           0x11800A0000BA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18098         {"PIP_STAT7_PRT12"             ,           0x11800A0000BF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18099         {"PIP_STAT7_PRT13"             ,           0x11800A0000C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18100         {"PIP_STAT7_PRT14"             ,           0x11800A0000C98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18101         {"PIP_STAT7_PRT15"             ,           0x11800A0000CE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18102         {"PIP_STAT7_PRT16"             ,           0x11800A0000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18103         {"PIP_STAT7_PRT17"             ,           0x11800A0000D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18104         {"PIP_STAT7_PRT18"             ,           0x11800A0000DD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18105         {"PIP_STAT7_PRT19"             ,           0x11800A0000E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18106         {"PIP_STAT7_PRT20"             ,           0x11800A0000E78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18107         {"PIP_STAT7_PRT21"             ,           0x11800A0000EC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18108         {"PIP_STAT7_PRT22"             ,           0x11800A0000F18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18109         {"PIP_STAT7_PRT23"             ,           0x11800A0000F68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18110         {"PIP_STAT7_PRT24"             ,           0x11800A0000FB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18111         {"PIP_STAT7_PRT25"             ,           0x11800A0001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18112         {"PIP_STAT7_PRT26"             ,           0x11800A0001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18113         {"PIP_STAT7_PRT27"             ,           0x11800A00010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18114         {"PIP_STAT7_PRT28"             ,           0x11800A00010F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18115         {"PIP_STAT7_PRT29"             ,           0x11800A0001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18116         {"PIP_STAT7_PRT30"             ,           0x11800A0001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18117         {"PIP_STAT7_PRT31"             ,           0x11800A00011E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18118         {"PIP_STAT7_PRT32"             ,           0x11800A0001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18119         {"PIP_STAT7_PRT33"             ,           0x11800A0001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18120         {"PIP_STAT7_PRT34"             ,           0x11800A00012D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18121         {"PIP_STAT7_PRT35"             ,           0x11800A0001328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
18122         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18123         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18124         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18125         {"PIP_STAT8_PRT3"              ,           0x11800A0000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18126         {"PIP_STAT8_PRT4"              ,           0x11800A0000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18127         {"PIP_STAT8_PRT5"              ,           0x11800A00009D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18128         {"PIP_STAT8_PRT6"              ,           0x11800A0000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18129         {"PIP_STAT8_PRT7"              ,           0x11800A0000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18130         {"PIP_STAT8_PRT8"              ,           0x11800A0000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18131         {"PIP_STAT8_PRT9"              ,           0x11800A0000B10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18132         {"PIP_STAT8_PRT10"             ,           0x11800A0000B60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18133         {"PIP_STAT8_PRT11"             ,           0x11800A0000BB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18134         {"PIP_STAT8_PRT12"             ,           0x11800A0000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18135         {"PIP_STAT8_PRT13"             ,           0x11800A0000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18136         {"PIP_STAT8_PRT14"             ,           0x11800A0000CA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18137         {"PIP_STAT8_PRT15"             ,           0x11800A0000CF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18138         {"PIP_STAT8_PRT16"             ,           0x11800A0000D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18139         {"PIP_STAT8_PRT17"             ,           0x11800A0000D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18140         {"PIP_STAT8_PRT18"             ,           0x11800A0000DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18141         {"PIP_STAT8_PRT19"             ,           0x11800A0000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18142         {"PIP_STAT8_PRT20"             ,           0x11800A0000E80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18143         {"PIP_STAT8_PRT21"             ,           0x11800A0000ED0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18144         {"PIP_STAT8_PRT22"             ,           0x11800A0000F20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18145         {"PIP_STAT8_PRT23"             ,           0x11800A0000F70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18146         {"PIP_STAT8_PRT24"             ,           0x11800A0000FC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18147         {"PIP_STAT8_PRT25"             ,           0x11800A0001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18148         {"PIP_STAT8_PRT26"             ,           0x11800A0001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18149         {"PIP_STAT8_PRT27"             ,           0x11800A00010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18150         {"PIP_STAT8_PRT28"             ,           0x11800A0001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18151         {"PIP_STAT8_PRT29"             ,           0x11800A0001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18152         {"PIP_STAT8_PRT30"             ,           0x11800A00011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18153         {"PIP_STAT8_PRT31"             ,           0x11800A00011F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18154         {"PIP_STAT8_PRT32"             ,           0x11800A0001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18155         {"PIP_STAT8_PRT33"             ,           0x11800A0001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18156         {"PIP_STAT8_PRT34"             ,           0x11800A00012E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18157         {"PIP_STAT8_PRT35"             ,           0x11800A0001330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
18158         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18159         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18160         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18161         {"PIP_STAT9_PRT3"              ,           0x11800A0000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18162         {"PIP_STAT9_PRT4"              ,           0x11800A0000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18163         {"PIP_STAT9_PRT5"              ,           0x11800A00009D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18164         {"PIP_STAT9_PRT6"              ,           0x11800A0000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18165         {"PIP_STAT9_PRT7"              ,           0x11800A0000A78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18166         {"PIP_STAT9_PRT8"              ,           0x11800A0000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18167         {"PIP_STAT9_PRT9"              ,           0x11800A0000B18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18168         {"PIP_STAT9_PRT10"             ,           0x11800A0000B68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18169         {"PIP_STAT9_PRT11"             ,           0x11800A0000BB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18170         {"PIP_STAT9_PRT12"             ,           0x11800A0000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18171         {"PIP_STAT9_PRT13"             ,           0x11800A0000C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18172         {"PIP_STAT9_PRT14"             ,           0x11800A0000CA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18173         {"PIP_STAT9_PRT15"             ,           0x11800A0000CF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18174         {"PIP_STAT9_PRT16"             ,           0x11800A0000D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18175         {"PIP_STAT9_PRT17"             ,           0x11800A0000D98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18176         {"PIP_STAT9_PRT18"             ,           0x11800A0000DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18177         {"PIP_STAT9_PRT19"             ,           0x11800A0000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18178         {"PIP_STAT9_PRT20"             ,           0x11800A0000E88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18179         {"PIP_STAT9_PRT21"             ,           0x11800A0000ED8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18180         {"PIP_STAT9_PRT22"             ,           0x11800A0000F28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18181         {"PIP_STAT9_PRT23"             ,           0x11800A0000F78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18182         {"PIP_STAT9_PRT24"             ,           0x11800A0000FC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18183         {"PIP_STAT9_PRT25"             ,           0x11800A0001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18184         {"PIP_STAT9_PRT26"             ,           0x11800A0001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18185         {"PIP_STAT9_PRT27"             ,           0x11800A00010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18186         {"PIP_STAT9_PRT28"             ,           0x11800A0001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18187         {"PIP_STAT9_PRT29"             ,           0x11800A0001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18188         {"PIP_STAT9_PRT30"             ,           0x11800A00011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18189         {"PIP_STAT9_PRT31"             ,           0x11800A00011F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18190         {"PIP_STAT9_PRT32"             ,           0x11800A0001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18191         {"PIP_STAT9_PRT33"             ,           0x11800A0001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18192         {"PIP_STAT9_PRT34"             ,           0x11800A00012E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18193         {"PIP_STAT9_PRT35"             ,           0x11800A0001338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
18194         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     447},
18195         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18196         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18197         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18198         {"PIP_STAT_INB_ERRS3"          ,           0x11800A0001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18199         {"PIP_STAT_INB_ERRS4"          ,           0x11800A0001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18200         {"PIP_STAT_INB_ERRS5"          ,           0x11800A0001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18201         {"PIP_STAT_INB_ERRS6"          ,           0x11800A0001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18202         {"PIP_STAT_INB_ERRS7"          ,           0x11800A0001AF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18203         {"PIP_STAT_INB_ERRS8"          ,           0x11800A0001B10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18204         {"PIP_STAT_INB_ERRS9"          ,           0x11800A0001B30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18205         {"PIP_STAT_INB_ERRS10"         ,           0x11800A0001B50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18206         {"PIP_STAT_INB_ERRS11"         ,           0x11800A0001B70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18207         {"PIP_STAT_INB_ERRS12"         ,           0x11800A0001B90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18208         {"PIP_STAT_INB_ERRS13"         ,           0x11800A0001BB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18209         {"PIP_STAT_INB_ERRS14"         ,           0x11800A0001BD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18210         {"PIP_STAT_INB_ERRS15"         ,           0x11800A0001BF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18211         {"PIP_STAT_INB_ERRS16"         ,           0x11800A0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18212         {"PIP_STAT_INB_ERRS17"         ,           0x11800A0001C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18213         {"PIP_STAT_INB_ERRS18"         ,           0x11800A0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18214         {"PIP_STAT_INB_ERRS19"         ,           0x11800A0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18215         {"PIP_STAT_INB_ERRS20"         ,           0x11800A0001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18216         {"PIP_STAT_INB_ERRS21"         ,           0x11800A0001CB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18217         {"PIP_STAT_INB_ERRS22"         ,           0x11800A0001CD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18218         {"PIP_STAT_INB_ERRS23"         ,           0x11800A0001CF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18219         {"PIP_STAT_INB_ERRS24"         ,           0x11800A0001D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18220         {"PIP_STAT_INB_ERRS25"         ,           0x11800A0001D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18221         {"PIP_STAT_INB_ERRS26"         ,           0x11800A0001D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18222         {"PIP_STAT_INB_ERRS27"         ,           0x11800A0001D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18223         {"PIP_STAT_INB_ERRS28"         ,           0x11800A0001D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18224         {"PIP_STAT_INB_ERRS29"         ,           0x11800A0001DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18225         {"PIP_STAT_INB_ERRS30"         ,           0x11800A0001DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18226         {"PIP_STAT_INB_ERRS31"         ,           0x11800A0001DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18227         {"PIP_STAT_INB_ERRS32"         ,           0x11800A0001E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18228         {"PIP_STAT_INB_ERRS33"         ,           0x11800A0001E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18229         {"PIP_STAT_INB_ERRS34"         ,           0x11800A0001E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18230         {"PIP_STAT_INB_ERRS35"         ,           0x11800A0001E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
18231         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18232         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18233         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18234         {"PIP_STAT_INB_OCTS3"          ,           0x11800A0001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18235         {"PIP_STAT_INB_OCTS4"          ,           0x11800A0001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18236         {"PIP_STAT_INB_OCTS5"          ,           0x11800A0001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18237         {"PIP_STAT_INB_OCTS6"          ,           0x11800A0001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18238         {"PIP_STAT_INB_OCTS7"          ,           0x11800A0001AE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18239         {"PIP_STAT_INB_OCTS8"          ,           0x11800A0001B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18240         {"PIP_STAT_INB_OCTS9"          ,           0x11800A0001B28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18241         {"PIP_STAT_INB_OCTS10"         ,           0x11800A0001B48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18242         {"PIP_STAT_INB_OCTS11"         ,           0x11800A0001B68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18243         {"PIP_STAT_INB_OCTS12"         ,           0x11800A0001B88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18244         {"PIP_STAT_INB_OCTS13"         ,           0x11800A0001BA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18245         {"PIP_STAT_INB_OCTS14"         ,           0x11800A0001BC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18246         {"PIP_STAT_INB_OCTS15"         ,           0x11800A0001BE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18247         {"PIP_STAT_INB_OCTS16"         ,           0x11800A0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18248         {"PIP_STAT_INB_OCTS17"         ,           0x11800A0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18249         {"PIP_STAT_INB_OCTS18"         ,           0x11800A0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18250         {"PIP_STAT_INB_OCTS19"         ,           0x11800A0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18251         {"PIP_STAT_INB_OCTS20"         ,           0x11800A0001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18252         {"PIP_STAT_INB_OCTS21"         ,           0x11800A0001CA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18253         {"PIP_STAT_INB_OCTS22"         ,           0x11800A0001CC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18254         {"PIP_STAT_INB_OCTS23"         ,           0x11800A0001CE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18255         {"PIP_STAT_INB_OCTS24"         ,           0x11800A0001D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18256         {"PIP_STAT_INB_OCTS25"         ,           0x11800A0001D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18257         {"PIP_STAT_INB_OCTS26"         ,           0x11800A0001D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18258         {"PIP_STAT_INB_OCTS27"         ,           0x11800A0001D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18259         {"PIP_STAT_INB_OCTS28"         ,           0x11800A0001D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18260         {"PIP_STAT_INB_OCTS29"         ,           0x11800A0001DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18261         {"PIP_STAT_INB_OCTS30"         ,           0x11800A0001DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18262         {"PIP_STAT_INB_OCTS31"         ,           0x11800A0001DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18263         {"PIP_STAT_INB_OCTS32"         ,           0x11800A0001E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18264         {"PIP_STAT_INB_OCTS33"         ,           0x11800A0001E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18265         {"PIP_STAT_INB_OCTS34"         ,           0x11800A0001E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18266         {"PIP_STAT_INB_OCTS35"         ,           0x11800A0001E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
18267         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18268         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18269         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18270         {"PIP_STAT_INB_PKTS3"          ,           0x11800A0001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18271         {"PIP_STAT_INB_PKTS4"          ,           0x11800A0001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18272         {"PIP_STAT_INB_PKTS5"          ,           0x11800A0001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18273         {"PIP_STAT_INB_PKTS6"          ,           0x11800A0001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18274         {"PIP_STAT_INB_PKTS7"          ,           0x11800A0001AE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18275         {"PIP_STAT_INB_PKTS8"          ,           0x11800A0001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18276         {"PIP_STAT_INB_PKTS9"          ,           0x11800A0001B20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18277         {"PIP_STAT_INB_PKTS10"         ,           0x11800A0001B40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18278         {"PIP_STAT_INB_PKTS11"         ,           0x11800A0001B60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18279         {"PIP_STAT_INB_PKTS12"         ,           0x11800A0001B80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18280         {"PIP_STAT_INB_PKTS13"         ,           0x11800A0001BA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18281         {"PIP_STAT_INB_PKTS14"         ,           0x11800A0001BC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18282         {"PIP_STAT_INB_PKTS15"         ,           0x11800A0001BE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18283         {"PIP_STAT_INB_PKTS16"         ,           0x11800A0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18284         {"PIP_STAT_INB_PKTS17"         ,           0x11800A0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18285         {"PIP_STAT_INB_PKTS18"         ,           0x11800A0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18286         {"PIP_STAT_INB_PKTS19"         ,           0x11800A0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18287         {"PIP_STAT_INB_PKTS20"         ,           0x11800A0001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18288         {"PIP_STAT_INB_PKTS21"         ,           0x11800A0001CA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18289         {"PIP_STAT_INB_PKTS22"         ,           0x11800A0001CC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18290         {"PIP_STAT_INB_PKTS23"         ,           0x11800A0001CE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18291         {"PIP_STAT_INB_PKTS24"         ,           0x11800A0001D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18292         {"PIP_STAT_INB_PKTS25"         ,           0x11800A0001D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18293         {"PIP_STAT_INB_PKTS26"         ,           0x11800A0001D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18294         {"PIP_STAT_INB_PKTS27"         ,           0x11800A0001D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18295         {"PIP_STAT_INB_PKTS28"         ,           0x11800A0001D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18296         {"PIP_STAT_INB_PKTS29"         ,           0x11800A0001DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18297         {"PIP_STAT_INB_PKTS30"         ,           0x11800A0001DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18298         {"PIP_STAT_INB_PKTS31"         ,           0x11800A0001DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18299         {"PIP_STAT_INB_PKTS32"         ,           0x11800A0001E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18300         {"PIP_STAT_INB_PKTS33"         ,           0x11800A0001E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18301         {"PIP_STAT_INB_PKTS34"         ,           0x11800A0001E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18302         {"PIP_STAT_INB_PKTS35"         ,           0x11800A0001E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
18303         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18304         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18305         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18306         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18307         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18308         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18309         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18310         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18311         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18312         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18313         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18314         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18315         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18316         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18317         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18318         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18319         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18320         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18321         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18322         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18323         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18324         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18325         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18326         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18327         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18328         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18329         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18330         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18331         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18332         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18333         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18334         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18335         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18336         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18337         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18338         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18339         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18340         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18341         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18342         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18343         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18344         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18345         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18346         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18347         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18348         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18349         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18350         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18351         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18352         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18353         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18354         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18355         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18356         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18357         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18358         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18359         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18360         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18361         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18362         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18363         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18364         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18365         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18366         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
18367         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
18368         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
18369         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
18370         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
18371         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
18372         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
18373         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
18374         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
18375         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
18376         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
18377         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
18378         {"PKO_MEM_DEBUG14"             ,           0x1180050001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
18379         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
18380         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
18381         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
18382         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
18383         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     468},
18384         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
18385         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
18386         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
18387         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
18388         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     473},
18389         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     474},
18390         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     475},
18391         {"PKO_REG_CRC_CTL0"            ,           0x1180050000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     476},
18392         {"PKO_REG_CRC_CTL1"            ,           0x1180050000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     476},
18393         {"PKO_REG_CRC_ENABLE"          ,           0x1180050000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     477},
18394         {"PKO_REG_CRC_IV0"             ,           0x1180050000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     478},
18395         {"PKO_REG_CRC_IV1"             ,           0x1180050000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     478},
18396         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     479},
18397         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     480},
18398         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     481},
18399         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     482},
18400         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     483},
18401         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     484},
18402         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     485},
18403         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
18404         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
18405         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
18406         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     489},
18407         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
18408         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
18409         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
18410         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
18411         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
18412         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
18413         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
18414         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     490},
18415         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     491},
18416         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     492},
18417         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     493},
18418         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18419         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18420         {"POW_PP_GRP_MSK2"             ,           0x1670000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18421         {"POW_PP_GRP_MSK3"             ,           0x1670000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18422         {"POW_PP_GRP_MSK4"             ,           0x1670000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18423         {"POW_PP_GRP_MSK5"             ,           0x1670000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18424         {"POW_PP_GRP_MSK6"             ,           0x1670000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18425         {"POW_PP_GRP_MSK7"             ,           0x1670000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18426         {"POW_PP_GRP_MSK8"             ,           0x1670000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18427         {"POW_PP_GRP_MSK9"             ,           0x1670000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18428         {"POW_PP_GRP_MSK10"            ,           0x1670000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18429         {"POW_PP_GRP_MSK11"            ,           0x1670000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18430         {"POW_PP_GRP_MSK12"            ,           0x1670000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18431         {"POW_PP_GRP_MSK13"            ,           0x1670000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18432         {"POW_PP_GRP_MSK14"            ,           0x1670000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18433         {"POW_PP_GRP_MSK15"            ,           0x1670000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     494},
18434         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     495},
18435         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     495},
18436         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     495},
18437         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     495},
18438         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     495},
18439         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     495},
18440         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     495},
18441         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     495},
18442         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     496},
18443         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     496},
18444         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     496},
18445         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     496},
18446         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     496},
18447         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     496},
18448         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     496},
18449         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     496},
18450         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     497},
18451         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     498},
18452         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     499},
18453         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     499},
18454         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     499},
18455         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     499},
18456         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     499},
18457         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     499},
18458         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     499},
18459         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     499},
18460         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     500},
18461         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18462         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18463         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18464         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18465         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18466         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18467         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18468         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18469         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18470         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18471         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18472         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18473         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18474         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18475         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18476         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
18477         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     502},
18478         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18479         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18480         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18481         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18482         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18483         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18484         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18485         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18486         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18487         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18488         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18489         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18490         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18491         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18492         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18493         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
18494         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18495         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18496         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18497         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18498         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18499         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18500         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18501         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18502         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18503         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18504         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18505         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18506         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18507         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18508         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18509         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
18510         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     505},
18511         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     506},
18512         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     507},
18513         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     508},
18514         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     509},
18515         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     510},
18516         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     511},
18517         {"SPX0_BCKPRS_CNT"             ,           0x1180090000340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     512},
18518         {"SPX1_BCKPRS_CNT"             ,           0x1180098000340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     512},
18519         {"SPX0_BIST_STAT"              ,           0x11800900007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     513},
18520         {"SPX1_BIST_STAT"              ,           0x11800980007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     513},
18521         {"SPX0_CLK_CTL"                ,           0x1180090000348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     514},
18522         {"SPX1_CLK_CTL"                ,           0x1180098000348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     514},
18523         {"SPX0_CLK_STAT"               ,           0x1180090000350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     515},
18524         {"SPX1_CLK_STAT"               ,           0x1180098000350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     515},
18525         {"SPX0_DBG_DESKEW_CTL"         ,           0x1180090000368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     516},
18526         {"SPX1_DBG_DESKEW_CTL"         ,           0x1180098000368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     516},
18527         {"SPX0_DBG_DESKEW_STATE"       ,           0x1180090000370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     517},
18528         {"SPX1_DBG_DESKEW_STATE"       ,           0x1180098000370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     517},
18529         {"SPX0_DRV_CTL"                ,           0x1180090000358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     518},
18530         {"SPX1_DRV_CTL"                ,           0x1180098000358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     518},
18531         {"SPX0_ERR_CTL"                ,           0x1180090000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     519},
18532         {"SPX1_ERR_CTL"                ,           0x1180098000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     519},
18533         {"SPX0_INT_DAT"                ,           0x1180090000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     520},
18534         {"SPX1_INT_DAT"                ,           0x1180098000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     520},
18535         {"SPX0_INT_MSK"                ,           0x1180090000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
18536         {"SPX1_INT_MSK"                ,           0x1180098000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
18537         {"SPX0_INT_REG"                ,           0x1180090000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     522},
18538         {"SPX1_INT_REG"                ,           0x1180098000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     522},
18539         {"SPX0_INT_SYNC"               ,           0x1180090000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     523},
18540         {"SPX1_INT_SYNC"               ,           0x1180098000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     523},
18541         {"SPX0_TPA_ACC"                ,           0x1180090000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     524},
18542         {"SPX1_TPA_ACC"                ,           0x1180098000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     524},
18543         {"SPX0_TPA_MAX"                ,           0x1180090000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     525},
18544         {"SPX1_TPA_MAX"                ,           0x1180098000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     525},
18545         {"SPX0_TPA_SEL"                ,           0x1180090000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     526},
18546         {"SPX1_TPA_SEL"                ,           0x1180098000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     526},
18547         {"SPX0_TRN4_CTL"               ,           0x1180090000360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     527},
18548         {"SPX1_TRN4_CTL"               ,           0x1180098000360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     527},
18549         {"SPX0_PLL_BW_CTL"             ,           0x1180090000388ull,  CVMX_CSR_DB_TYPE_RSL,   64,     528},
18550         {"SPX0_PLL_SETTING"            ,           0x1180090000380ull,  CVMX_CSR_DB_TYPE_RSL,   64,     529},
18551         {"SRX0_COM_CTL"                ,           0x1180090000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     530},
18552         {"SRX1_COM_CTL"                ,           0x1180098000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     530},
18553         {"SRX0_IGN_RX_FULL"            ,           0x1180090000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     531},
18554         {"SRX1_IGN_RX_FULL"            ,           0x1180098000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     531},
18555         {"SRX0_SPI4_CAL000"            ,           0x1180090000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18556         {"SRX0_SPI4_CAL001"            ,           0x1180090000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18557         {"SRX0_SPI4_CAL002"            ,           0x1180090000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18558         {"SRX0_SPI4_CAL003"            ,           0x1180090000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18559         {"SRX0_SPI4_CAL004"            ,           0x1180090000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18560         {"SRX0_SPI4_CAL005"            ,           0x1180090000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18561         {"SRX0_SPI4_CAL006"            ,           0x1180090000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18562         {"SRX0_SPI4_CAL007"            ,           0x1180090000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18563         {"SRX0_SPI4_CAL008"            ,           0x1180090000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18564         {"SRX0_SPI4_CAL009"            ,           0x1180090000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18565         {"SRX0_SPI4_CAL010"            ,           0x1180090000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18566         {"SRX0_SPI4_CAL011"            ,           0x1180090000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18567         {"SRX0_SPI4_CAL012"            ,           0x1180090000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18568         {"SRX0_SPI4_CAL013"            ,           0x1180090000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18569         {"SRX0_SPI4_CAL014"            ,           0x1180090000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18570         {"SRX0_SPI4_CAL015"            ,           0x1180090000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18571         {"SRX0_SPI4_CAL016"            ,           0x1180090000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18572         {"SRX0_SPI4_CAL017"            ,           0x1180090000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18573         {"SRX0_SPI4_CAL018"            ,           0x1180090000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18574         {"SRX0_SPI4_CAL019"            ,           0x1180090000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18575         {"SRX0_SPI4_CAL020"            ,           0x11800900000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18576         {"SRX0_SPI4_CAL021"            ,           0x11800900000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18577         {"SRX0_SPI4_CAL022"            ,           0x11800900000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18578         {"SRX0_SPI4_CAL023"            ,           0x11800900000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18579         {"SRX0_SPI4_CAL024"            ,           0x11800900000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18580         {"SRX0_SPI4_CAL025"            ,           0x11800900000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18581         {"SRX0_SPI4_CAL026"            ,           0x11800900000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18582         {"SRX0_SPI4_CAL027"            ,           0x11800900000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18583         {"SRX0_SPI4_CAL028"            ,           0x11800900000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18584         {"SRX0_SPI4_CAL029"            ,           0x11800900000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18585         {"SRX0_SPI4_CAL030"            ,           0x11800900000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18586         {"SRX0_SPI4_CAL031"            ,           0x11800900000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18587         {"SRX1_SPI4_CAL000"            ,           0x1180098000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18588         {"SRX1_SPI4_CAL001"            ,           0x1180098000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18589         {"SRX1_SPI4_CAL002"            ,           0x1180098000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18590         {"SRX1_SPI4_CAL003"            ,           0x1180098000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18591         {"SRX1_SPI4_CAL004"            ,           0x1180098000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18592         {"SRX1_SPI4_CAL005"            ,           0x1180098000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18593         {"SRX1_SPI4_CAL006"            ,           0x1180098000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18594         {"SRX1_SPI4_CAL007"            ,           0x1180098000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18595         {"SRX1_SPI4_CAL008"            ,           0x1180098000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18596         {"SRX1_SPI4_CAL009"            ,           0x1180098000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18597         {"SRX1_SPI4_CAL010"            ,           0x1180098000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18598         {"SRX1_SPI4_CAL011"            ,           0x1180098000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18599         {"SRX1_SPI4_CAL012"            ,           0x1180098000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18600         {"SRX1_SPI4_CAL013"            ,           0x1180098000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18601         {"SRX1_SPI4_CAL014"            ,           0x1180098000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18602         {"SRX1_SPI4_CAL015"            ,           0x1180098000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18603         {"SRX1_SPI4_CAL016"            ,           0x1180098000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18604         {"SRX1_SPI4_CAL017"            ,           0x1180098000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18605         {"SRX1_SPI4_CAL018"            ,           0x1180098000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18606         {"SRX1_SPI4_CAL019"            ,           0x1180098000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18607         {"SRX1_SPI4_CAL020"            ,           0x11800980000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18608         {"SRX1_SPI4_CAL021"            ,           0x11800980000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18609         {"SRX1_SPI4_CAL022"            ,           0x11800980000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18610         {"SRX1_SPI4_CAL023"            ,           0x11800980000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18611         {"SRX1_SPI4_CAL024"            ,           0x11800980000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18612         {"SRX1_SPI4_CAL025"            ,           0x11800980000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18613         {"SRX1_SPI4_CAL026"            ,           0x11800980000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18614         {"SRX1_SPI4_CAL027"            ,           0x11800980000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18615         {"SRX1_SPI4_CAL028"            ,           0x11800980000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18616         {"SRX1_SPI4_CAL029"            ,           0x11800980000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18617         {"SRX1_SPI4_CAL030"            ,           0x11800980000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18618         {"SRX1_SPI4_CAL031"            ,           0x11800980000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
18619         {"SRX0_SPI4_STAT"              ,           0x1180090000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     533},
18620         {"SRX1_SPI4_STAT"              ,           0x1180098000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     533},
18621         {"SRX0_SW_TICK_CTL"            ,           0x1180090000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     534},
18622         {"SRX1_SW_TICK_CTL"            ,           0x1180098000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     534},
18623         {"SRX0_SW_TICK_DAT"            ,           0x1180090000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     535},
18624         {"SRX1_SW_TICK_DAT"            ,           0x1180098000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     535},
18625         {"STX0_ARB_CTL"                ,           0x1180090000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     536},
18626         {"STX1_ARB_CTL"                ,           0x1180098000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     536},
18627         {"STX0_BCKPRS_CNT"             ,           0x1180090000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     537},
18628         {"STX1_BCKPRS_CNT"             ,           0x1180098000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     537},
18629         {"STX0_COM_CTL"                ,           0x1180090000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     538},
18630         {"STX1_COM_CTL"                ,           0x1180098000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     538},
18631         {"STX0_DIP_CNT"                ,           0x1180090000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     539},
18632         {"STX1_DIP_CNT"                ,           0x1180098000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     539},
18633         {"STX0_IGN_CAL"                ,           0x1180090000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     540},
18634         {"STX1_IGN_CAL"                ,           0x1180098000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     540},
18635         {"STX0_INT_MSK"                ,           0x11800900006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     541},
18636         {"STX1_INT_MSK"                ,           0x11800980006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     541},
18637         {"STX0_INT_REG"                ,           0x1180090000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     542},
18638         {"STX1_INT_REG"                ,           0x1180098000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     542},
18639         {"STX0_INT_SYNC"               ,           0x11800900006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     543},
18640         {"STX1_INT_SYNC"               ,           0x11800980006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     543},
18641         {"STX0_MIN_BST"                ,           0x1180090000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     544},
18642         {"STX1_MIN_BST"                ,           0x1180098000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     544},
18643         {"STX0_SPI4_CAL000"            ,           0x1180090000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18644         {"STX0_SPI4_CAL001"            ,           0x1180090000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18645         {"STX0_SPI4_CAL002"            ,           0x1180090000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18646         {"STX0_SPI4_CAL003"            ,           0x1180090000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18647         {"STX0_SPI4_CAL004"            ,           0x1180090000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18648         {"STX0_SPI4_CAL005"            ,           0x1180090000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18649         {"STX0_SPI4_CAL006"            ,           0x1180090000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18650         {"STX0_SPI4_CAL007"            ,           0x1180090000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18651         {"STX0_SPI4_CAL008"            ,           0x1180090000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18652         {"STX0_SPI4_CAL009"            ,           0x1180090000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18653         {"STX0_SPI4_CAL010"            ,           0x1180090000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18654         {"STX0_SPI4_CAL011"            ,           0x1180090000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18655         {"STX0_SPI4_CAL012"            ,           0x1180090000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18656         {"STX0_SPI4_CAL013"            ,           0x1180090000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18657         {"STX0_SPI4_CAL014"            ,           0x1180090000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18658         {"STX0_SPI4_CAL015"            ,           0x1180090000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18659         {"STX0_SPI4_CAL016"            ,           0x1180090000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18660         {"STX0_SPI4_CAL017"            ,           0x1180090000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18661         {"STX0_SPI4_CAL018"            ,           0x1180090000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18662         {"STX0_SPI4_CAL019"            ,           0x1180090000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18663         {"STX0_SPI4_CAL020"            ,           0x11800900004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18664         {"STX0_SPI4_CAL021"            ,           0x11800900004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18665         {"STX0_SPI4_CAL022"            ,           0x11800900004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18666         {"STX0_SPI4_CAL023"            ,           0x11800900004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18667         {"STX0_SPI4_CAL024"            ,           0x11800900004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18668         {"STX0_SPI4_CAL025"            ,           0x11800900004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18669         {"STX0_SPI4_CAL026"            ,           0x11800900004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18670         {"STX0_SPI4_CAL027"            ,           0x11800900004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18671         {"STX0_SPI4_CAL028"            ,           0x11800900004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18672         {"STX0_SPI4_CAL029"            ,           0x11800900004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18673         {"STX0_SPI4_CAL030"            ,           0x11800900004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18674         {"STX0_SPI4_CAL031"            ,           0x11800900004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18675         {"STX1_SPI4_CAL000"            ,           0x1180098000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18676         {"STX1_SPI4_CAL001"            ,           0x1180098000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18677         {"STX1_SPI4_CAL002"            ,           0x1180098000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18678         {"STX1_SPI4_CAL003"            ,           0x1180098000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18679         {"STX1_SPI4_CAL004"            ,           0x1180098000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18680         {"STX1_SPI4_CAL005"            ,           0x1180098000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18681         {"STX1_SPI4_CAL006"            ,           0x1180098000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18682         {"STX1_SPI4_CAL007"            ,           0x1180098000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18683         {"STX1_SPI4_CAL008"            ,           0x1180098000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18684         {"STX1_SPI4_CAL009"            ,           0x1180098000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18685         {"STX1_SPI4_CAL010"            ,           0x1180098000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18686         {"STX1_SPI4_CAL011"            ,           0x1180098000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18687         {"STX1_SPI4_CAL012"            ,           0x1180098000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18688         {"STX1_SPI4_CAL013"            ,           0x1180098000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18689         {"STX1_SPI4_CAL014"            ,           0x1180098000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18690         {"STX1_SPI4_CAL015"            ,           0x1180098000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18691         {"STX1_SPI4_CAL016"            ,           0x1180098000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18692         {"STX1_SPI4_CAL017"            ,           0x1180098000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18693         {"STX1_SPI4_CAL018"            ,           0x1180098000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18694         {"STX1_SPI4_CAL019"            ,           0x1180098000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18695         {"STX1_SPI4_CAL020"            ,           0x11800980004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18696         {"STX1_SPI4_CAL021"            ,           0x11800980004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18697         {"STX1_SPI4_CAL022"            ,           0x11800980004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18698         {"STX1_SPI4_CAL023"            ,           0x11800980004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18699         {"STX1_SPI4_CAL024"            ,           0x11800980004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18700         {"STX1_SPI4_CAL025"            ,           0x11800980004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18701         {"STX1_SPI4_CAL026"            ,           0x11800980004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18702         {"STX1_SPI4_CAL027"            ,           0x11800980004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18703         {"STX1_SPI4_CAL028"            ,           0x11800980004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18704         {"STX1_SPI4_CAL029"            ,           0x11800980004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18705         {"STX1_SPI4_CAL030"            ,           0x11800980004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18706         {"STX1_SPI4_CAL031"            ,           0x11800980004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
18707         {"STX0_SPI4_DAT"               ,           0x1180090000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     546},
18708         {"STX1_SPI4_DAT"               ,           0x1180098000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     546},
18709         {"STX0_SPI4_STAT"              ,           0x1180090000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     547},
18710         {"STX1_SPI4_STAT"              ,           0x1180098000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     547},
18711         {"STX0_STAT_BYTES_HI"          ,           0x1180090000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     548},
18712         {"STX1_STAT_BYTES_HI"          ,           0x1180098000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     548},
18713         {"STX0_STAT_BYTES_LO"          ,           0x1180090000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     549},
18714         {"STX1_STAT_BYTES_LO"          ,           0x1180098000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     549},
18715         {"STX0_STAT_CTL"               ,           0x1180090000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     550},
18716         {"STX1_STAT_CTL"               ,           0x1180098000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     550},
18717         {"STX0_STAT_PKT_XMT"           ,           0x1180090000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     551},
18718         {"STX1_STAT_PKT_XMT"           ,           0x1180098000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     551},
18719         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     552},
18720         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     553},
18721         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     554},
18722         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
18723         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     556},
18724         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     557},
18725         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
18726         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     559},
18727         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     560},
18728         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     561},
18729         {"TRA_BIST_STATUS"             ,           0x11800A8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     562},
18730         {"TRA_CTL"                     ,           0x11800A8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     563},
18731         {"TRA_CYCLES_SINCE"            ,           0x11800A8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     564},
18732         {"TRA_FILT_ADR_ADR"            ,           0x11800A8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     565},
18733         {"TRA_FILT_ADR_MSK"            ,           0x11800A8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     566},
18734         {"TRA_FILT_CMD"                ,           0x11800A8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     567},
18735         {"TRA_FILT_DID"                ,           0x11800A8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
18736         {"TRA_FILT_SID"                ,           0x11800A8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     569},
18737         {"TRA_INT_STATUS"              ,           0x11800A8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     570},
18738         {"TRA_READ_DAT"                ,           0x11800A8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     571},
18739         {"TRA_TRIG0_ADR_ADR"           ,           0x11800A8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     572},
18740         {"TRA_TRIG0_ADR_MSK"           ,           0x11800A80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     573},
18741         {"TRA_TRIG0_CMD"               ,           0x11800A8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     574},
18742         {"TRA_TRIG0_DID"               ,           0x11800A8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     575},
18743         {"TRA_TRIG0_SID"               ,           0x11800A8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     576},
18744         {"TRA_TRIG1_ADR_ADR"           ,           0x11800A80000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     577},
18745         {"TRA_TRIG1_ADR_MSK"           ,           0x11800A80000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     578},
18746         {"TRA_TRIG1_CMD"               ,           0x11800A80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     579},
18747         {"TRA_TRIG1_DID"               ,           0x11800A80000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     580},
18748         {"TRA_TRIG1_SID"               ,           0x11800A80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     581},
18749         {"ZIP_CMD_BIST_RESULT"         ,           0x1180038000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     582},
18750         {"ZIP_CMD_BUF"                 ,           0x1180038000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     583},
18751         {"ZIP_CMD_CTL"                 ,           0x1180038000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     584},
18752         {"ZIP_CONSTANTS"               ,           0x11800380000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     585},
18753         {"ZIP_DEBUG0"                  ,           0x1180038000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     586},
18754         {"ZIP_ERROR"                   ,           0x1180038000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     587},
18755         {"ZIP_INT_MASK"                ,           0x1180038000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     588},
18756         {NULL,0,0,0,0}
18757 };
18758 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn38xx[] = {
18759         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
18760         {"OVRFLW"                      ,        0,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
18761         {"TXPOP"                       ,        4,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
18762         {"TXPSH"                       ,        8,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
18763         {"RESERVED_12_63"              ,        12,     52,     0,      "RAZ",  1,      1,      0,      0},
18764         {"OVRFLW"                      ,        0,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
18765         {"TXPOP"                       ,        4,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
18766         {"TXPSH"                       ,        8,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
18767         {"RESERVED_12_63"              ,        12,     52,     1,      "RAZ",  1,      1,      0,      0},
18768         {"INT_LOOP"                    ,        0,      4,      2,      "R/W",  0,      0,      0ull,   0ull},
18769         {"EXT_LOOP"                    ,        4,      4,      2,      "R/W",  0,      0,      0ull,   0ull},
18770         {"RESERVED_8_63"               ,        8,      56,     2,      "RAZ",  1,      1,      0,      0},
18771         {"BYPASS"                      ,        0,      1,      3,      "R/W",  0,      1,      0ull,   0},
18772         {"RESERVED_1_63"               ,        1,      63,     3,      "RAZ",  1,      1,      0,      0},
18773         {"SETTING"                     ,        0,      5,      4,      "R/W",  0,      1,      0ull,   0},
18774         {"RESERVED_5_63"               ,        5,      59,     4,      "RAZ",  1,      1,      0,      0},
18775         {"NCTL"                        ,        0,      4,      5,      "RO",   0,      1,      0ull,   0},
18776         {"PCTL"                        ,        4,      4,      5,      "RO",   0,      1,      0ull,   0},
18777         {"RESERVED_8_63"               ,        8,      56,     5,      "RAZ",  1,      1,      0,      0},
18778         {"NCTL"                        ,        0,      4,      6,      "R/W",  0,      1,      0ull,   0},
18779         {"PCTL"                        ,        4,      4,      6,      "R/W",  0,      1,      0ull,   0},
18780         {"RESERVED_8_63"               ,        8,      56,     6,      "RAZ",  1,      1,      0,      0},
18781         {"MODE"                        ,        0,      1,      7,      "R/W",  0,      1,      0ull,   0},
18782         {"RESERVED_1_63"               ,        1,      63,     7,      "RAZ",  1,      1,      0,      0},
18783         {"NCTL"                        ,        0,      5,      8,      "R/W",  0,      1,      0ull,   0},
18784         {"RESERVED_5_63"               ,        5,      59,     8,      "RAZ",  1,      1,      0,      0},
18785         {"NCTL"                        ,        0,      5,      9,      "R/W",  0,      1,      0ull,   0},
18786         {"RESERVED_5_63"               ,        5,      59,     9,      "RAZ",  1,      1,      0,      0},
18787         {"PCTL"                        ,        0,      5,      10,     "R/W",  0,      1,      0ull,   0},
18788         {"RESERVED_5_63"               ,        5,      59,     10,     "RAZ",  1,      1,      0,      0},
18789         {"PCTL"                        ,        0,      5,      11,     "R/W",  0,      1,      0ull,   0},
18790         {"RESERVED_5_63"               ,        5,      59,     11,     "RAZ",  1,      1,      0,      0},
18791         {"SETTING"                     ,        0,      5,      12,     "RO",   1,      1,      0,      0},
18792         {"RESERVED_5_63"               ,        5,      59,     12,     "RAZ",  1,      1,      0,      0},
18793         {"SETTING"                     ,        0,      5,      13,     "R/W",  0,      0,      24ull,  24ull},
18794         {"RESERVED_5_63"               ,        5,      59,     13,     "RAZ",  1,      1,      0,      0},
18795         {"PRT_EN"                      ,        0,      4,      14,     "R/W",  0,      0,      0ull,   1ull},
18796         {"RESERVED_4_63"               ,        4,      60,     14,     "RAZ",  1,      1,      0,      0},
18797         {"ENABLE"                      ,        0,      1,      15,     "RO",   1,      1,      0,      0},
18798         {"STATUS"                      ,        1,      1,      15,     "RO",   1,      1,      0,      0},
18799         {"RESERVED_2_63"               ,        2,      62,     15,     "RAZ",  1,      1,      0,      0},
18800         {"MSK"                         ,        0,      64,     16,     "R/W",  0,      1,      0ull,   0},
18801         {"POWEROK"                     ,        0,      1,      17,     "R/W",  0,      1,      1ull,   0},
18802         {"RESERVED_1_63"               ,        1,      63,     17,     "RAZ",  1,      1,      0,      0},
18803         {"SIG"                         ,        0,      32,     18,     "R/W",  0,      1,      0ull,   0},
18804         {"RESERVED_32_63"              ,        32,     32,     18,     "RAZ",  1,      1,      0,      0},
18805         {"SETTING"                     ,        0,      5,      19,     "R/W",  0,      0,      24ull,  24ull},
18806         {"RESERVED_5_63"               ,        5,      59,     19,     "RAZ",  1,      1,      0,      0},
18807         {"NCTL"                        ,        0,      4,      20,     "R/W",  0,      0,      8ull,   8ull},
18808         {"PCTL"                        ,        4,      4,      20,     "R/W",  0,      0,      8ull,   8ull},
18809         {"RESERVED_8_63"               ,        8,      56,     20,     "RAZ",  1,      1,      0,      0},
18810         {"MARK"                        ,        0,      4,      21,     "R/W",  0,      0,      0ull,   0ull},
18811         {"RESERVED_4_63"               ,        4,      60,     21,     "RAZ",  1,      1,      0,      0},
18812         {"PRT_EN"                      ,        0,      4,      22,     "R/W",  0,      0,      0ull,   1ull},
18813         {"RESERVED_4_63"               ,        4,      60,     22,     "RAZ",  1,      1,      0,      0},
18814         {"NCTL"                        ,        0,      4,      23,     "R/W",  0,      1,      15ull,  0},
18815         {"PCTL"                        ,        4,      4,      23,     "R/W",  0,      1,      15ull,  0},
18816         {"RESERVED_8_63"               ,        8,      56,     23,     "RAZ",  1,      1,      0,      0},
18817         {"EN"                          ,        0,      1,      24,     "R/W",  0,      1,      1ull,   0},
18818         {"RESERVED_1_63"               ,        1,      63,     24,     "RAZ",  1,      1,      0,      0},
18819         {"BIST"                        ,        0,      4,      25,     "RO",   0,      0,      0ull,   0ull},
18820         {"RESERVED_4_63"               ,        4,      60,     25,     "RAZ",  1,      1,      0,      0},
18821         {"DINT"                        ,        0,      16,     26,     "WO",   0,      0,      0ull,   0ull},
18822         {"RESERVED_16_63"              ,        16,     48,     26,     "RAZ",  1,      1,      0,      0},
18823         {"FUSE"                        ,        0,      16,     27,     "RO",   1,      1,      0,      0},
18824         {"RESERVED_16_63"              ,        16,     48,     27,     "RAZ",  1,      1,      0,      0},
18825         {"GSTOP"                       ,        0,      1,      28,     "R/W",  0,      0,      0ull,   0ull},
18826         {"RESERVED_1_63"               ,        1,      63,     28,     "RAZ",  1,      1,      0,      0},
18827         {"WORKQ"                       ,        0,      16,     29,     "R/W",  0,      0,      0ull,   0ull},
18828         {"GPIO"                        ,        16,     16,     29,     "R/W",  0,      0,      0ull,   0ull},
18829         {"MBOX"                        ,        32,     2,      29,     "R/W",  0,      0,      0ull,   0ull},
18830         {"UART"                        ,        34,     2,      29,     "R/W",  0,      0,      0ull,   0ull},
18831         {"PCI_INT"                     ,        36,     4,      29,     "R/W",  0,      0,      0ull,   0ull},
18832         {"PCI_MSI"                     ,        40,     4,      29,     "R/W",  0,      0,      0ull,   0ull},
18833         {"RESERVED_44_44"              ,        44,     1,      29,     "RAZ",  1,      1,      0,      0},
18834         {"TWSI"                        ,        45,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
18835         {"RML"                         ,        46,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
18836         {"TRACE"                       ,        47,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
18837         {"GMX_DRP"                     ,        48,     2,      29,     "R/W",  0,      0,      0ull,   0ull},
18838         {"IPD_DRP"                     ,        50,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
18839         {"KEY_ZERO"                    ,        51,     1,      29,     "R/W",  0,      0,      0ull,   0ull},
18840         {"TIMER"                       ,        52,     4,      29,     "R/W",  0,      0,      0ull,   0ull},
18841         {"RESERVED_56_63"              ,        56,     8,      29,     "RAZ",  1,      1,      0,      0},
18842         {"WDOG"                        ,        0,      16,     30,     "R/W",  0,      0,      0ull,   0ull},
18843         {"RESERVED_16_63"              ,        16,     48,     30,     "RAZ",  1,      1,      0,      0},
18844         {"WORKQ"                       ,        0,      16,     31,     "RO",   0,      0,      0ull,   0ull},
18845         {"GPIO"                        ,        16,     16,     31,     "RO",   0,      0,      0ull,   0ull},
18846         {"MBOX"                        ,        32,     2,      31,     "RO",   0,      0,      0ull,   0ull},
18847         {"UART"                        ,        34,     2,      31,     "RO",   0,      0,      0ull,   0ull},
18848         {"PCI_INT"                     ,        36,     4,      31,     "RO",   0,      0,      0ull,   0ull},
18849         {"PCI_MSI"                     ,        40,     4,      31,     "RO",   0,      0,      0ull,   0ull},
18850         {"WDOG_SUM"                    ,        44,     1,      31,     "RO",   0,      0,      0ull,   0ull},
18851         {"TWSI"                        ,        45,     1,      31,     "RO",   0,      0,      0ull,   0ull},
18852         {"RML"                         ,        46,     1,      31,     "RO",   0,      0,      0ull,   0ull},
18853         {"TRACE"                       ,        47,     1,      31,     "RO",   0,      0,      0ull,   0ull},
18854         {"GMX_DRP"                     ,        48,     2,      31,     "R/W1C",        0,      0,      0ull,   0ull},
18855         {"IPD_DRP"                     ,        50,     1,      31,     "R/W1C",        0,      0,      0ull,   0ull},
18856         {"KEY_ZERO"                    ,        51,     1,      31,     "R/W1C",        0,      0,      0ull,   0ull},
18857         {"TIMER"                       ,        52,     4,      31,     "R/W1C",        0,      0,      0ull,   0ull},
18858         {"RESERVED_56_63"              ,        56,     8,      31,     "RAZ",  1,      1,      0,      0},
18859         {"WDOG"                        ,        0,      16,     32,     "RO",   0,      0,      0ull,   0ull},
18860         {"RESERVED_16_63"              ,        16,     48,     32,     "RAZ",  1,      1,      0,      0},
18861         {"BITS"                        ,        0,      32,     33,     "R/W1C",        0,      0,      0ull,   0ull},
18862         {"RESERVED_32_63"              ,        32,     32,     33,     "RAZ",  1,      1,      0,      0},
18863         {"BITS"                        ,        0,      32,     34,     "R/W1", 0,      0,      0ull,   0ull},
18864         {"RESERVED_32_63"              ,        32,     32,     34,     "RAZ",  1,      1,      0,      0},
18865         {"NMI"                         ,        0,      16,     35,     "WO",   0,      0,      0ull,   0ull},
18866         {"RESERVED_16_63"              ,        16,     48,     35,     "RAZ",  1,      1,      0,      0},
18867         {"INTR"                        ,        0,      2,      36,     "R/W",  0,      0,      0ull,   0ull},
18868         {"RESERVED_2_63"               ,        2,      62,     36,     "RAZ",  1,      1,      0,      0},
18869         {"PPDBG"                       ,        0,      16,     37,     "RO",   0,      0,      0ull,   0ull},
18870         {"RESERVED_16_63"              ,        16,     48,     37,     "RAZ",  1,      1,      0,      0},
18871         {"POKE"                        ,        0,      64,     38,     "RAZ",  1,      1,      0,      0},
18872         {"RST0"                        ,        0,      1,      39,     "R/W",  1,      1,      0,      0},
18873         {"RST"                         ,        1,      15,     39,     "R/W",  0,      0,      32767ull,       0ull},
18874         {"RESERVED_16_63"              ,        16,     48,     39,     "RAZ",  1,      1,      0,      0},
18875         {"SOFT_BIST"                   ,        0,      1,      40,     "R/W",  0,      0,      0ull,   0ull},
18876         {"RESERVED_1_63"               ,        1,      63,     40,     "RAZ",  1,      1,      0,      0},
18877         {"SOFT_PRST"                   ,        0,      1,      41,     "R/W",  0,      0,      1ull,   0ull},
18878         {"NPI"                         ,        1,      1,      41,     "R/W",  0,      0,      0ull,   0ull},
18879         {"HOST64"                      ,        2,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
18880         {"RESERVED_3_63"               ,        3,      61,     41,     "RAZ",  1,      1,      0,      0},
18881         {"SOFT_RST"                    ,        0,      1,      42,     "WO",   0,      0,      0ull,   0ull},
18882         {"RESERVED_1_63"               ,        1,      63,     42,     "RAZ",  1,      1,      0,      0},
18883         {"LEN"                         ,        0,      36,     43,     "R/W",  0,      0,      0ull,   0ull},
18884         {"ONE_SHOT"                    ,        36,     1,      43,     "R/W",  0,      0,      0ull,   0ull},
18885         {"RESERVED_37_63"              ,        37,     27,     43,     "RAZ",  1,      1,      0,      0},
18886         {"MODE"                        ,        0,      2,      44,     "R/W",  0,      0,      0ull,   0ull},
18887         {"STATE"                       ,        2,      2,      44,     "RO",   0,      0,      0ull,   0ull},
18888         {"LEN"                         ,        4,      16,     44,     "R/W",  0,      0,      0ull,   0ull},
18889         {"CNT"                         ,        20,     24,     44,     "RO",   0,      0,      0ull,   0ull},
18890         {"DSTOP"                       ,        44,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
18891         {"GSTOPEN"                     ,        45,     1,      44,     "R/W",  0,      0,      0ull,   0ull},
18892         {"RESERVED_46_63"              ,        46,     18,     44,     "RAZ",  1,      1,      0,      0},
18893         {"DATA"                        ,        0,      17,     45,     "RO",   0,      1,      0ull,   0},
18894         {"DSEL_EXT"                    ,        17,     1,      45,     "R/W",  0,      0,      1ull,   0ull},
18895         {"C_MUL"                       ,        18,     5,      45,     "RO",   1,      1,      0,      0},
18896         {"CCLK_DIV2"                   ,        23,     1,      45,     "RO",   1,      1,      0,      0},
18897         {"DCLK_MUL2"                   ,        24,     1,      45,     "RO",   1,      1,      0,      0},
18898         {"D_MUL"                       ,        25,     4,      45,     "RO",   1,      1,      0,      0},
18899         {"RESERVED_29_63"              ,        29,     35,     45,     "RAZ",  1,      1,      0,      0},
18900         {"PDF"                         ,        0,      16,     46,     "RO",   0,      0,      0ull,   0ull},
18901         {"RDF"                         ,        16,     16,     46,     "RO",   0,      0,      0ull,   0ull},
18902         {"RESERVED_32_63"              ,        32,     32,     46,     "RAZ",  0,      0,      0ull,   0ull},
18903         {"P1_BRF"                      ,        0,      8,      47,     "RO",   0,      0,      0ull,   0ull},
18904         {"P0_BRF"                      ,        8,      8,      47,     "RO",   0,      0,      0ull,   0ull},
18905         {"P1_BWB"                      ,        16,     1,      47,     "RO",   0,      0,      0ull,   0ull},
18906         {"P0_BWB"                      ,        17,     1,      47,     "RO",   0,      0,      0ull,   0ull},
18907         {"CRF"                         ,        18,     1,      47,     "RO",   0,      0,      0ull,   0ull},
18908         {"DRF"                         ,        19,     1,      47,     "RO",   0,      0,      0ull,   0ull},
18909         {"GFU"                         ,        20,     1,      47,     "RO",   0,      0,      0ull,   0ull},
18910         {"IFU"                         ,        21,     1,      47,     "RO",   0,      0,      0ull,   0ull},
18911         {"CRQ"                         ,        22,     1,      47,     "RO",   0,      0,      0ull,   0ull},
18912         {"RESERVED_23_63"              ,        23,     41,     47,     "RAZ",  0,      0,      0ull,   0ull},
18913         {"SARB"                        ,        0,      1,      48,     "R/W",  0,      0,      1ull,   1ull},
18914         {"GXOR_ENA"                    ,        1,      1,      48,     "R/W",  0,      0,      0ull,   0ull},
18915         {"NXOR_ENA"                    ,        2,      1,      48,     "R/W",  0,      0,      0ull,   0ull},
18916         {"NRPL_ENA"                    ,        3,      1,      48,     "R/W",  0,      0,      0ull,   0ull},
18917         {"RESERVED_4_63"               ,        4,      60,     48,     "RAZ",  1,      1,      0,      0},
18918         {"DBELL"                       ,        0,      20,     49,     "R/W",  0,      1,      0ull,   0},
18919         {"RESERVED_20_63"              ,        20,     44,     49,     "RAZ",  1,      1,      0,      0},
18920         {"SIZE"                        ,        0,      9,      50,     "R/W",  0,      1,      3ull,   0},
18921         {"POOL"                        ,        9,      3,      50,     "R/W",  0,      1,      0ull,   0},
18922         {"DWBCNT"                      ,        12,     8,      50,     "R/W",  0,      1,      1ull,   0},
18923         {"RESERVED_20_63"              ,        20,     44,     50,     "RAZ",  1,      1,      0,      0},
18924         {"RESERVED_0_4"                ,        0,      5,      51,     "RAZ",  1,      1,      0,      0},
18925         {"RDPTR"                       ,        5,      31,     51,     "R/W",  0,      1,      0ull,   0},
18926         {"RESERVED_36_63"              ,        36,     28,     51,     "RAZ",  1,      1,      0,      0},
18927         {"CP2ECCENA"                   ,        0,      1,      52,     "R/W",  0,      0,      0ull,   0ull},
18928         {"CP2SBE"                      ,        1,      1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
18929         {"CP2DBE"                      ,        2,      1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
18930         {"CP2SBINA"                    ,        3,      1,      52,     "R/W",  0,      0,      0ull,   0ull},
18931         {"CP2DBINA"                    ,        4,      1,      52,     "R/W",  0,      0,      0ull,   0ull},
18932         {"CP2SYN"                      ,        5,      8,      52,     "RO",   0,      0,      0ull,   0ull},
18933         {"DTEECCENA"                   ,        13,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
18934         {"DTESBE"                      ,        14,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
18935         {"DTEDBE"                      ,        15,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
18936         {"DTESBINA"                    ,        16,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
18937         {"DTEDBINA"                    ,        17,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
18938         {"DTESYN"                      ,        18,     7,      52,     "RO",   0,      0,      0ull,   0ull},
18939         {"DTEPARENA"                   ,        25,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
18940         {"DTEPERR"                     ,        26,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
18941         {"DTEPINA"                     ,        27,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
18942         {"CP2PARENA"                   ,        28,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
18943         {"CP2PERR"                     ,        29,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
18944         {"CP2PINA"                     ,        30,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
18945         {"DBLOVF"                      ,        31,     1,      52,     "R/W1C",        0,      0,      0ull,   0ull},
18946         {"DBLINA"                      ,        32,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
18947         {"RESERVED_33_63"              ,        33,     31,     52,     "RAZ",  1,      1,      0,      0},
18948         {"ENA_P1"                      ,        0,      1,      53,     "R/W",  0,      0,      1ull,   1ull},
18949         {"ENA_P0"                      ,        1,      1,      53,     "R/W",  0,      0,      1ull,   1ull},
18950         {"RESERVED_2_2"                ,        2,      1,      53,     "RAZ",  1,      1,      0,      0},
18951         {"MTYPE"                       ,        3,      1,      53,     "R/W",  0,      0,      0ull,   0ull},
18952         {"SIL_LAT"                     ,        4,      2,      53,     "R/W",  0,      0,      0ull,   0ull},
18953         {"RW_DLY"                      ,        6,      4,      53,     "R/W",  0,      0,      1ull,   1ull},
18954         {"WR_DLY"                      ,        10,     4,      53,     "R/W",  0,      0,      2ull,   2ull},
18955         {"FPRCH"                       ,        14,     2,      53,     "R/W",  0,      0,      0ull,   0ull},
18956         {"BPRCH"                       ,        16,     2,      53,     "R/W",  0,      0,      0ull,   0ull},
18957         {"BLEN"                        ,        18,     1,      53,     "R/W",  0,      0,      0ull,   0ull},
18958         {"PBUNK"                       ,        19,     3,      53,     "R/W",  0,      0,      2ull,   2ull},
18959         {"R2R_PBUNK"                   ,        22,     1,      53,     "R/W",  0,      0,      1ull,   1ull},
18960         {"INIT_P1"                     ,        23,     1,      53,     "R/W",  0,      0,      0ull,   0ull},
18961         {"INIT_P0"                     ,        24,     1,      53,     "R/W",  0,      0,      0ull,   0ull},
18962         {"BUNK_INIT"                   ,        25,     2,      53,     "R/W",  0,      0,      3ull,   3ull},
18963         {"LPP_ENA"                     ,        27,     1,      53,     "R/W",  0,      0,      0ull,   0ull},
18964         {"RESERVED_28_63"              ,        28,     36,     53,     "RAZ",  1,      1,      0,      0},
18965         {"REF_INT"                     ,        0,      4,      54,     "R/W",  0,      0,      3ull,   3ull},
18966         {"TSKW"                        ,        4,      2,      54,     "R/W",  0,      0,      0ull,   0ull},
18967         {"RESERVED_6_7"                ,        6,      2,      54,     "RAZ",  0,      0,      0ull,   0ull},
18968         {"TRL"                         ,        8,      4,      54,     "R/W",  0,      0,      6ull,   6ull},
18969         {"TWL"                         ,        12,     4,      54,     "R/W",  0,      0,      7ull,   7ull},
18970         {"TRC"                         ,        16,     4,      54,     "R/W",  0,      0,      6ull,   6ull},
18971         {"TMRSC"                       ,        20,     3,      54,     "R/W",  0,      0,      6ull,   6ull},
18972         {"MRS_ENA"                     ,        23,     1,      54,     "R/W",  0,      0,      0ull,   0ull},
18973         {"AREF_ENA"                    ,        24,     1,      54,     "R/W",  0,      0,      0ull,   0ull},
18974         {"REF_INTLO"                   ,        25,     9,      54,     "R/W",  0,      0,      0ull,   0ull},
18975         {"RESERVED_34_63"              ,        34,     30,     54,     "RAZ",  1,      1,      0,      0},
18976         {"FCRAM2P"                     ,        0,      1,      55,     "R/W",  0,      0,      0ull,   0ull},
18977         {"MAXBNK"                      ,        1,      1,      55,     "R/W",  0,      0,      1ull,   1ull},
18978         {"UA_START"                    ,        2,      2,      55,     "R/W",  0,      0,      1ull,   1ull},
18979         {"REFSHORT"                    ,        4,      1,      55,     "R/W",  0,      0,      0ull,   0ull},
18980         {"TRFC"                        ,        5,      5,      55,     "R/W",  0,      0,      9ull,   9ull},
18981         {"SILRST"                      ,        10,     1,      55,     "R/W",  0,      0,      0ull,   0ull},
18982         {"DTECLKDIS"                   ,        11,     1,      55,     "R/W",  0,      0,      0ull,   0ull},
18983         {"RESERVED_12_63"              ,        12,     52,     55,     "RAZ",  1,      1,      0,      0},
18984         {"MADDR"                       ,        0,      24,     56,     "RO",   0,      0,      0ull,   0ull},
18985         {"BNUM"                        ,        24,     3,      56,     "RO",   0,      0,      0ull,   0ull},
18986         {"PNUM"                        ,        27,     1,      56,     "RO",   0,      0,      0ull,   0ull},
18987         {"FSRC"                        ,        28,     2,      56,     "RO",   0,      0,      0ull,   0ull},
18988         {"FDST"                        ,        30,     9,      56,     "RO",   0,      0,      0ull,   0ull},
18989         {"RESERVED_39_63"              ,        39,     25,     56,     "RAZ",  1,      1,      0,      0},
18990         {"MRS"                         ,        0,      15,     57,     "R/W",  0,      0,      66ull,  66ull},
18991         {"RESERVED_15_15"              ,        15,     1,      57,     "RAZ",  1,      1,      0,      0},
18992         {"EMRS"                        ,        16,     15,     57,     "R/W",  0,      0,      64ull,  64ull},
18993         {"RESERVED_31_31"              ,        31,     1,      57,     "RAZ",  1,      1,      0,      0},
18994         {"EMRS2"                       ,        32,     15,     57,     "R/W",  0,      0,      0ull,   0ull},
18995         {"RESERVED_47_63"              ,        47,     17,     57,     "RAZ",  1,      1,      0,      0},
18996         {"MRSDAT"                      ,        0,      23,     58,     "R/W",  0,      0,      2ull,   2ull},
18997         {"RESERVED_23_63"              ,        23,     41,     58,     "RAZ",  1,      1,      0,      0},
18998         {"IMODE"                       ,        0,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
18999         {"QMODE"                       ,        1,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
19000         {"PMODE"                       ,        2,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
19001         {"DTMODE"                      ,        3,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
19002         {"DCMODE"                      ,        4,      1,      59,     "R/W",  0,      0,      0ull,   0ull},
19003         {"SBDLCK"                      ,        5,      1,      59,     "R/W",  0,      0,      0ull,   0ull},
19004         {"SBDNUM"                      ,        6,      4,      59,     "R/W",  0,      0,      0ull,   0ull},
19005         {"RESERVED_10_63"              ,        10,     54,     59,     "RAZ",  1,      1,      0,      0},
19006         {"SBD0"                        ,        0,      64,     60,     "RO",   1,      1,      0,      0},
19007         {"SBD1"                        ,        0,      64,     61,     "RO",   1,      1,      0,      0},
19008         {"SBD2"                        ,        0,      64,     62,     "RO",   1,      1,      0,      0},
19009         {"SBD3"                        ,        0,      64,     63,     "RO",   1,      1,      0,      0},
19010         {"FDR"                         ,        0,      1,      64,     "RO",   0,      0,      0ull,   0ull},
19011         {"FFR"                         ,        1,      1,      64,     "RO",   0,      0,      0ull,   0ull},
19012         {"FPF1"                        ,        2,      1,      64,     "RO",   0,      0,      0ull,   0ull},
19013         {"FPF0"                        ,        3,      1,      64,     "RO",   0,      0,      0ull,   0ull},
19014         {"FRD"                         ,        4,      1,      64,     "RO",   0,      0,      0ull,   0ull},
19015         {"RESERVED_5_63"               ,        5,      59,     64,     "RAZ",  1,      1,      0,      0},
19016         {"MEM0_ERR"                    ,        0,      7,      65,     "R/W",  0,      0,      0ull,   0ull},
19017         {"MEM1_ERR"                    ,        7,      7,      65,     "R/W",  0,      0,      0ull,   0ull},
19018         {"ENB"                         ,        14,     1,      65,     "R/W",  0,      0,      0ull,   0ull},
19019         {"USE_STT"                     ,        15,     1,      65,     "R/W",  0,      0,      0ull,   0ull},
19020         {"USE_LDT"                     ,        16,     1,      65,     "R/W",  0,      0,      0ull,   0ull},
19021         {"RESET"                       ,        17,     1,      65,     "R/W",  0,      0,      0ull,   0ull},
19022         {"RESERVED_18_63"              ,        18,     46,     65,     "RAZ",  1,      1,      0,      0},
19023         {"FPF_RD"                      ,        0,      11,     66,     "R/W",  0,      0,      64ull,  0ull},
19024         {"FPF_WR"                      ,        11,     11,     66,     "R/W",  0,      0,      196ull, 0ull},
19025         {"RESERVED_22_63"              ,        22,     42,     66,     "RAZ",  1,      1,      0,      0},
19026         {"FPF_SIZ"                     ,        0,      11,     67,     "R/W",  0,      0,      256ull, 0ull},
19027         {"RESERVED_11_63"              ,        11,     53,     67,     "RAZ",  1,      1,      0,      0},
19028         {"FPF_RD"                      ,        0,      12,     68,     "R/W",  0,      0,      64ull,  0ull},
19029         {"FPF_WR"                      ,        12,     12,     68,     "R/W",  0,      0,      196ull, 0ull},
19030         {"RESERVED_24_63"              ,        24,     40,     68,     "RAZ",  1,      1,      0,      0},
19031         {"FPF_SIZ"                     ,        0,      12,     69,     "R/W",  0,      0,      256ull, 0ull},
19032         {"RESERVED_12_63"              ,        12,     52,     69,     "RAZ",  1,      1,      0,      0},
19033         {"FED0_SBE"                    ,        0,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19034         {"FED0_DBE"                    ,        1,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19035         {"FED1_SBE"                    ,        2,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19036         {"FED1_DBE"                    ,        3,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19037         {"Q0_UND"                      ,        4,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19038         {"Q0_COFF"                     ,        5,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19039         {"Q0_PERR"                     ,        6,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19040         {"Q1_UND"                      ,        7,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19041         {"Q1_COFF"                     ,        8,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19042         {"Q1_PERR"                     ,        9,      1,      70,     "R/W",  0,      0,      0ull,   0ull},
19043         {"Q2_UND"                      ,        10,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19044         {"Q2_COFF"                     ,        11,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19045         {"Q2_PERR"                     ,        12,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19046         {"Q3_UND"                      ,        13,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19047         {"Q3_COFF"                     ,        14,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19048         {"Q3_PERR"                     ,        15,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19049         {"Q4_UND"                      ,        16,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19050         {"Q4_COFF"                     ,        17,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19051         {"Q4_PERR"                     ,        18,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19052         {"Q5_UND"                      ,        19,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19053         {"Q5_COFF"                     ,        20,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19054         {"Q5_PERR"                     ,        21,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19055         {"Q6_UND"                      ,        22,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19056         {"Q6_COFF"                     ,        23,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19057         {"Q6_PERR"                     ,        24,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19058         {"Q7_UND"                      ,        25,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19059         {"Q7_COFF"                     ,        26,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19060         {"Q7_PERR"                     ,        27,     1,      70,     "R/W",  0,      0,      0ull,   0ull},
19061         {"RESERVED_28_63"              ,        28,     36,     70,     "RAZ",  1,      1,      0,      0},
19062         {"FED0_SBE"                    ,        0,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19063         {"FED0_DBE"                    ,        1,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19064         {"FED1_SBE"                    ,        2,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19065         {"FED1_DBE"                    ,        3,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19066         {"Q0_UND"                      ,        4,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19067         {"Q0_COFF"                     ,        5,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19068         {"Q0_PERR"                     ,        6,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19069         {"Q1_UND"                      ,        7,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19070         {"Q1_COFF"                     ,        8,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19071         {"Q1_PERR"                     ,        9,      1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19072         {"Q2_UND"                      ,        10,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19073         {"Q2_COFF"                     ,        11,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19074         {"Q2_PERR"                     ,        12,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19075         {"Q3_UND"                      ,        13,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19076         {"Q3_COFF"                     ,        14,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19077         {"Q3_PERR"                     ,        15,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19078         {"Q4_UND"                      ,        16,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19079         {"Q4_COFF"                     ,        17,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19080         {"Q4_PERR"                     ,        18,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19081         {"Q5_UND"                      ,        19,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19082         {"Q5_COFF"                     ,        20,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19083         {"Q5_PERR"                     ,        21,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19084         {"Q6_UND"                      ,        22,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19085         {"Q6_COFF"                     ,        23,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19086         {"Q6_PERR"                     ,        24,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19087         {"Q7_UND"                      ,        25,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19088         {"Q7_COFF"                     ,        26,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19089         {"Q7_PERR"                     ,        27,     1,      71,     "R/W1C",        0,      0,      0ull,   0ull},
19090         {"RESERVED_28_63"              ,        28,     36,     71,     "RAZ",  1,      1,      0,      0},
19091         {"QUE_SIZ"                     ,        0,      29,     72,     "RO",   0,      0,      0ull,   0ull},
19092         {"RESERVED_29_63"              ,        29,     35,     72,     "RAZ",  1,      1,      0,      0},
19093         {"PG_NUM"                      ,        0,      25,     73,     "RO",   0,      1,      0ull,   0},
19094         {"RESERVED_25_63"              ,        25,     39,     73,     "RAZ",  1,      1,      0,      0},
19095         {"ACT_INDX"                    ,        0,      26,     74,     "RO",   0,      1,      0ull,   0},
19096         {"ACT_QUE"                     ,        26,     3,      74,     "RO",   0,      1,      0ull,   0},
19097         {"RESERVED_29_63"              ,        29,     35,     74,     "RAZ",  0,      0,      0ull,   7ull},
19098         {"EXP_INDX"                    ,        0,      26,     75,     "RO",   0,      1,      0ull,   0},
19099         {"EXP_QUE"                     ,        26,     3,      75,     "RO",   0,      1,      0ull,   0},
19100         {"RESERVED_29_63"              ,        29,     35,     75,     "RAZ",  0,      0,      0ull,   7ull},
19101         {"CTL"                         ,        0,      16,     76,     "R/W",  1,      0,      0,      0ull},
19102         {"RESERVED_16_63"              ,        16,     48,     76,     "RAZ",  1,      1,      0,      0},
19103         {"STATUS"                      ,        0,      32,     77,     "RO",   0,      0,      0ull,   0ull},
19104         {"RESERVED_32_63"              ,        32,     32,     77,     "RAZ",  1,      1,      0,      0},
19105         {"OUT_COL"                     ,        0,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
19106         {"NCB_OVR"                     ,        1,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
19107         {"OUT_OVR"                     ,        2,      16,     78,     "R/W1C",        0,      0,      0ull,   0ull},
19108         {"RESERVED_18_21"              ,        18,     4,      78,     "RAZ",  0,      0,      0ull,   0ull},
19109         {"LOSTSTAT"                    ,        22,     4,      78,     "R/W1C",        0,      0,      0ull,   0ull},
19110         {"STATOVR"                     ,        26,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
19111         {"INB_NXA"                     ,        27,     4,      78,     "R/W1C",        0,      0,      0ull,   0ull},
19112         {"RESERVED_31_63"              ,        31,     33,     78,     "RAZ",  1,      1,      0,      0},
19113         {"STATUS"                      ,        0,      10,     79,     "RO",   0,      0,      0ull,   0ull},
19114         {"RESERVED_10_63"              ,        10,     54,     79,     "RAZ",  1,      1,      0,      0},
19115         {"TYPE"                        ,        0,      1,      80,     "RO",   1,      1,      0,      0},
19116         {"EN"                          ,        1,      1,      80,     "RO",   1,      1,      0,      0},
19117         {"RESERVED_2_63"               ,        2,      62,     80,     "RAZ",  1,      1,      0,      0},
19118         {"PRT"                         ,        0,      6,      81,     "RO",   0,      1,      0ull,   0},
19119         {"RESERVED_6_63"               ,        6,      58,     81,     "RAZ",  1,      1,      0,      0},
19120         {"EN"                          ,        0,      1,      82,     "R/W",  0,      1,      0ull,   0},
19121         {"SPEED"                       ,        1,      1,      82,     "R/W",  0,      1,      1ull,   0},
19122         {"DUPLEX"                      ,        2,      1,      82,     "R/W",  0,      1,      1ull,   0},
19123         {"SLOTTIME"                    ,        3,      1,      82,     "R/W",  0,      1,      1ull,   0},
19124         {"RESERVED_4_63"               ,        4,      60,     82,     "RAZ",  1,      1,      0,      0},
19125         {"ADR"                         ,        0,      64,     83,     "R/W",  0,      1,      0ull,   0},
19126         {"ADR"                         ,        0,      64,     84,     "R/W",  0,      1,      0ull,   0},
19127         {"ADR"                         ,        0,      64,     85,     "R/W",  0,      1,      0ull,   0},
19128         {"ADR"                         ,        0,      64,     86,     "R/W",  0,      1,      0ull,   0},
19129         {"ADR"                         ,        0,      64,     87,     "R/W",  0,      1,      0ull,   0},
19130         {"ADR"                         ,        0,      64,     88,     "R/W",  0,      1,      0ull,   0},
19131         {"EN"                          ,        0,      8,      89,     "R/W",  0,      1,      0ull,   0},
19132         {"RESERVED_8_63"               ,        8,      56,     89,     "RAZ",  1,      1,      0,      0},
19133         {"BCST"                        ,        0,      1,      90,     "R/W",  0,      1,      1ull,   0},
19134         {"MCST"                        ,        1,      2,      90,     "R/W",  0,      1,      0ull,   0},
19135         {"CAM_MODE"                    ,        3,      1,      90,     "R/W",  0,      1,      0ull,   0},
19136         {"RESERVED_4_63"               ,        4,      60,     90,     "RAZ",  1,      1,      0,      0},
19137         {"CNT"                         ,        0,      5,      91,     "R/W",  0,      0,      24ull,  24ull},
19138         {"RESERVED_5_63"               ,        5,      59,     91,     "RAZ",  1,      1,      0,      0},
19139         {"MINERR"                      ,        0,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19140         {"CAREXT"                      ,        1,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19141         {"MAXERR"                      ,        2,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19142         {"JABBER"                      ,        3,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19143         {"FCSERR"                      ,        4,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19144         {"ALNERR"                      ,        5,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19145         {"LENERR"                      ,        6,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19146         {"RCVERR"                      ,        7,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19147         {"SKPERR"                      ,        8,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19148         {"NIBERR"                      ,        9,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
19149         {"RESERVED_10_63"              ,        10,     54,     92,     "RAZ",  1,      1,      0,      0},
19150         {"PRE_CHK"                     ,        0,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
19151         {"PRE_STRP"                    ,        1,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
19152         {"CTL_DRP"                     ,        2,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
19153         {"CTL_BCK"                     ,        3,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
19154         {"CTL_MCST"                    ,        4,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
19155         {"CTL_SMAC"                    ,        5,      1,      93,     "R/W",  0,      0,      1ull,   1ull},
19156         {"PRE_FREE"                    ,        6,      1,      93,     "R/W",  0,      0,      0ull,   0ull},
19157         {"VLAN_LEN"                    ,        7,      1,      93,     "R/W",  0,      0,      0ull,   0ull},
19158         {"PAD_LEN"                     ,        8,      1,      93,     "R/W",  0,      0,      0ull,   0ull},
19159         {"RESERVED_9_63"               ,        9,      55,     93,     "RAZ",  1,      1,      0,      0},
19160         {"LEN"                         ,        0,      16,     94,     "R/W",  0,      0,      1536ull,        1536ull},
19161         {"RESERVED_16_63"              ,        16,     48,     94,     "RAZ",  1,      1,      0,      0},
19162         {"LEN"                         ,        0,      16,     95,     "R/W",  0,      0,      64ull,  64ull},
19163         {"RESERVED_16_63"              ,        16,     48,     95,     "RAZ",  1,      1,      0,      0},
19164         {"IFG"                         ,        0,      4,      96,     "R/W",  0,      0,      12ull,  12ull},
19165         {"RESERVED_4_63"               ,        4,      60,     96,     "RAZ",  1,      1,      0,      0},
19166         {"MINERR"                      ,        0,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19167         {"CAREXT"                      ,        1,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19168         {"MAXERR"                      ,        2,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19169         {"JABBER"                      ,        3,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19170         {"FCSERR"                      ,        4,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19171         {"ALNERR"                      ,        5,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19172         {"LENERR"                      ,        6,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19173         {"RCVERR"                      ,        7,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19174         {"SKPERR"                      ,        8,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19175         {"NIBERR"                      ,        9,      1,      97,     "R/W",  0,      0,      0ull,   0ull},
19176         {"OVRERR"                      ,        10,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
19177         {"PCTERR"                      ,        11,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
19178         {"RSVERR"                      ,        12,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
19179         {"FALERR"                      ,        13,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
19180         {"COLDET"                      ,        14,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
19181         {"IFGERR"                      ,        15,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
19182         {"PHY_LINK"                    ,        16,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
19183         {"PHY_SPD"                     ,        17,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
19184         {"PHY_DUPX"                    ,        18,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
19185         {"RESERVED_19_63"              ,        19,     45,     97,     "RAZ",  1,      1,      0,      0},
19186         {"MINERR"                      ,        0,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19187         {"CAREXT"                      ,        1,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19188         {"MAXERR"                      ,        2,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19189         {"JABBER"                      ,        3,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19190         {"FCSERR"                      ,        4,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19191         {"ALNERR"                      ,        5,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19192         {"LENERR"                      ,        6,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19193         {"RCVERR"                      ,        7,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19194         {"SKPERR"                      ,        8,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19195         {"NIBERR"                      ,        9,      1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19196         {"OVRERR"                      ,        10,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19197         {"PCTERR"                      ,        11,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19198         {"RSVERR"                      ,        12,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19199         {"FALERR"                      ,        13,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19200         {"COLDET"                      ,        14,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19201         {"IFGERR"                      ,        15,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19202         {"PHY_LINK"                    ,        16,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19203         {"PHY_SPD"                     ,        17,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19204         {"PHY_DUPX"                    ,        18,     1,      98,     "R/W1C",        0,      0,      0ull,   0ull},
19205         {"RESERVED_19_63"              ,        19,     45,     98,     "RAZ",  1,      1,      0,      0},
19206         {"CNT"                         ,        0,      16,     99,     "R/W",  0,      0,      10240ull,       10240ull},
19207         {"RESERVED_16_63"              ,        16,     48,     99,     "RAZ",  1,      1,      0,      0},
19208         {"STATUS"                      ,        0,      1,      100,    "RO",   0,      1,      0ull,   0},
19209         {"SPEED"                       ,        1,      2,      100,    "RO",   0,      1,      0ull,   0},
19210         {"DUPLEX"                      ,        3,      1,      100,    "RO",   0,      1,      0ull,   0},
19211         {"RESERVED_4_63"               ,        4,      60,     100,    "RAZ",  1,      1,      0,      0},
19212         {"RD_CLR"                      ,        0,      1,      101,    "R/W",  0,      0,      0ull,   0ull},
19213         {"RESERVED_1_63"               ,        1,      63,     101,    "RAZ",  1,      1,      0,      0},
19214         {"CNT"                         ,        0,      48,     102,    "RC/W", 0,      1,      0ull,   0},
19215         {"RESERVED_48_63"              ,        48,     16,     102,    "RAZ",  1,      1,      0,      0},
19216         {"CNT"                         ,        0,      48,     103,    "RC/W", 0,      1,      0ull,   0},
19217         {"RESERVED_48_63"              ,        48,     16,     103,    "RAZ",  1,      1,      0,      0},
19218         {"CNT"                         ,        0,      48,     104,    "RC/W", 0,      1,      0ull,   0},
19219         {"RESERVED_48_63"              ,        48,     16,     104,    "RAZ",  1,      1,      0,      0},
19220         {"CNT"                         ,        0,      48,     105,    "RC/W", 0,      1,      0ull,   0},
19221         {"RESERVED_48_63"              ,        48,     16,     105,    "RAZ",  1,      1,      0,      0},
19222         {"CNT"                         ,        0,      32,     106,    "RC/W", 0,      1,      0ull,   0},
19223         {"RESERVED_32_63"              ,        32,     32,     106,    "RAZ",  1,      1,      0,      0},
19224         {"CNT"                         ,        0,      32,     107,    "RC/W", 0,      1,      0ull,   0},
19225         {"RESERVED_32_63"              ,        32,     32,     107,    "RAZ",  1,      1,      0,      0},
19226         {"CNT"                         ,        0,      32,     108,    "RC/W", 0,      1,      0ull,   0},
19227         {"RESERVED_32_63"              ,        32,     32,     108,    "RAZ",  1,      1,      0,      0},
19228         {"CNT"                         ,        0,      32,     109,    "RC/W", 0,      1,      0ull,   0},
19229         {"RESERVED_32_63"              ,        32,     32,     109,    "RAZ",  1,      1,      0,      0},
19230         {"CNT"                         ,        0,      32,     110,    "RC/W", 0,      1,      0ull,   0},
19231         {"RESERVED_32_63"              ,        32,     32,     110,    "RAZ",  1,      1,      0,      0},
19232         {"LEN"                         ,        0,      7,      111,    "R/W",  0,      0,      0ull,   0ull},
19233         {"RESERVED_7_7"                ,        7,      1,      111,    "RAZ",  1,      1,      0,      0},
19234         {"FCSSEL"                      ,        8,      1,      111,    "R/W",  0,      0,      0ull,   0ull},
19235         {"RESERVED_9_63"               ,        9,      55,     111,    "RAZ",  1,      1,      0,      0},
19236         {"MARK"                        ,        0,      6,      112,    "R/W",  1,      1,      0,      0},
19237         {"RESERVED_6_63"               ,        6,      58,     112,    "RAZ",  1,      1,      0,      0},
19238         {"MARK"                        ,        0,      6,      113,    "R/W",  0,      0,      16ull,  16ull},
19239         {"RESERVED_6_63"               ,        6,      58,     113,    "RAZ",  1,      1,      0,      0},
19240         {"MARK"                        ,        0,      9,      114,    "R/W",  1,      1,      0,      0},
19241         {"RESERVED_9_63"               ,        9,      55,     114,    "RAZ",  1,      1,      0,      0},
19242         {"EN"                          ,        0,      16,     115,    "R/W",  0,      0,      0ull,   0ull},
19243         {"RESERVED_16_63"              ,        16,     48,     115,    "RAZ",  1,      1,      0,      0},
19244         {"DPRT"                        ,        0,      4,      116,    "R/W",  0,      0,      0ull,   0ull},
19245         {"RESERVED_4_63"               ,        4,      60,     116,    "RAZ",  1,      1,      0,      0},
19246         {"COMMIT"                      ,        0,      16,     117,    "RO",   0,      0,      0ull,   0ull},
19247         {"DROP"                        ,        16,     16,     117,    "RO",   0,      0,      0ull,   0ull},
19248         {"RESERVED_32_63"              ,        32,     32,     117,    "RAZ",  1,      1,      0,      0},
19249         {"PRTS"                        ,        0,      3,      118,    "R/W",  0,      0,      4ull,   4ull},
19250         {"RESERVED_3_63"               ,        3,      61,     118,    "RAZ",  1,      1,      0,      0},
19251         {"SMAC"                        ,        0,      48,     119,    "R/W",  0,      1,      0ull,   0},
19252         {"RESERVED_48_63"              ,        48,     16,     119,    "RAZ",  1,      1,      0,      0},
19253         {"CNT"                         ,        0,      16,     120,    "R/W1C",        0,      0,      0ull,   0ull},
19254         {"BP"                          ,        16,     1,      120,    "RO",   0,      0,      0ull,   0ull},
19255         {"RESERVED_17_63"              ,        17,     47,     120,    "RAZ",  1,      1,      0,      0},
19256         {"PREAMBLE"                    ,        0,      1,      121,    "R/W",  0,      0,      1ull,   1ull},
19257         {"PAD"                         ,        1,      1,      121,    "R/W",  0,      0,      1ull,   1ull},
19258         {"FCS"                         ,        2,      1,      121,    "R/W",  0,      0,      1ull,   1ull},
19259         {"FORCE_FCS"                   ,        3,      1,      121,    "R/W",  0,      0,      1ull,   1ull},
19260         {"RESERVED_4_63"               ,        4,      60,     121,    "RAZ",  1,      1,      0,      0},
19261         {"BURST"                       ,        0,      16,     122,    "R/W",  0,      0,      8192ull,        8192ull},
19262         {"RESERVED_16_63"              ,        16,     48,     122,    "RAZ",  1,      1,      0,      0},
19263         {"CLK_CNT"                     ,        0,      6,      123,    "R/W",  0,      0,      1ull,   1ull},
19264         {"RESERVED_6_63"               ,        6,      58,     123,    "RAZ",  1,      1,      0,      0},
19265         {"XSCOL_EN"                    ,        0,      1,      124,    "R/W",  0,      0,      1ull,   1ull},
19266         {"XSDEF_EN"                    ,        1,      1,      124,    "R/W",  0,      0,      1ull,   1ull},
19267         {"RESERVED_2_63"               ,        2,      62,     124,    "RAZ",  1,      1,      0,      0},
19268         {"MIN_SIZE"                    ,        0,      8,      125,    "R/W",  0,      0,      59ull,  59ull},
19269         {"RESERVED_8_63"               ,        8,      56,     125,    "RAZ",  1,      1,      0,      0},
19270         {"INTERVAL"                    ,        0,      16,     126,    "R/W",  0,      1,      16ull,  0},
19271         {"RESERVED_16_63"              ,        16,     48,     126,    "RAZ",  1,      1,      0,      0},
19272         {"TIME"                        ,        0,      16,     127,    "R/W",  0,      1,      96ull,  0},
19273         {"RESERVED_16_63"              ,        16,     48,     127,    "RAZ",  1,      1,      0,      0},
19274         {"TIME"                        ,        0,      16,     128,    "RO",   1,      1,      0,      0},
19275         {"RESERVED_16_63"              ,        16,     48,     128,    "RAZ",  1,      1,      0,      0},
19276         {"SEND"                        ,        0,      1,      129,    "R/W",  0,      0,      1ull,   1ull},
19277         {"RESERVED_1_63"               ,        1,      63,     129,    "RAZ",  1,      1,      0,      0},
19278         {"SLOT"                        ,        0,      10,     130,    "R/W",  0,      0,      512ull, 512ull},
19279         {"RESERVED_10_63"              ,        10,     54,     130,    "RAZ",  1,      1,      0,      0},
19280         {"TIME"                        ,        0,      16,     131,    "R/W",  0,      1,      0ull,   0},
19281         {"RESERVED_16_63"              ,        16,     48,     131,    "RAZ",  1,      1,      0,      0},
19282         {"XSCOL"                       ,        0,      32,     132,    "RC/W", 0,      1,      0ull,   0},
19283         {"XSDEF"                       ,        32,     32,     132,    "RC/W", 0,      1,      0ull,   0},
19284         {"MCOL"                        ,        0,      32,     133,    "RC/W", 0,      1,      0ull,   0},
19285         {"SCOL"                        ,        32,     32,     133,    "RC/W", 0,      1,      0ull,   0},
19286         {"OCTS"                        ,        0,      48,     134,    "RC/W", 0,      1,      0ull,   0},
19287         {"RESERVED_48_63"              ,        48,     16,     134,    "RAZ",  1,      1,      0,      0},
19288         {"PKTS"                        ,        0,      32,     135,    "RC/W", 0,      1,      0ull,   0},
19289         {"RESERVED_32_63"              ,        32,     32,     135,    "RAZ",  1,      1,      0,      0},
19290         {"HIST0"                       ,        0,      32,     136,    "RC/W", 0,      1,      0ull,   0},
19291         {"HIST1"                       ,        32,     32,     136,    "RC/W", 0,      1,      0ull,   0},
19292         {"HIST2"                       ,        0,      32,     137,    "RC/W", 0,      1,      0ull,   0},
19293         {"HIST3"                       ,        32,     32,     137,    "RC/W", 0,      1,      0ull,   0},
19294         {"HIST4"                       ,        0,      32,     138,    "RC/W", 0,      1,      0ull,   0},
19295         {"HIST5"                       ,        32,     32,     138,    "RC/W", 0,      1,      0ull,   0},
19296         {"HIST6"                       ,        0,      32,     139,    "RC/W", 0,      1,      0ull,   0},
19297         {"HIST7"                       ,        32,     32,     139,    "RC/W", 0,      1,      0ull,   0},
19298         {"BCST"                        ,        0,      32,     140,    "RC/W", 0,      1,      0ull,   0},
19299         {"MCST"                        ,        32,     32,     140,    "RC/W", 0,      1,      0ull,   0},
19300         {"CTL"                         ,        0,      32,     141,    "RC/W", 0,      1,      0ull,   0},
19301         {"UNDFLW"                      ,        32,     32,     141,    "RC/W", 0,      1,      0ull,   0},
19302         {"RD_CLR"                      ,        0,      1,      142,    "R/W",  0,      0,      0ull,   0ull},
19303         {"RESERVED_1_63"               ,        1,      63,     142,    "RAZ",  1,      1,      0,      0},
19304         {"CNT"                         ,        0,      9,      143,    "R/W",  0,      0,      32ull,  32ull},
19305         {"RESERVED_9_63"               ,        9,      55,     143,    "RAZ",  1,      1,      0,      0},
19306         {"BP"                          ,        0,      4,      144,    "RO",   0,      0,      0ull,   0ull},
19307         {"RESERVED_4_63"               ,        4,      60,     144,    "RAZ",  1,      1,      0,      0},
19308         {"LIMIT"                       ,        0,      5,      145,    "R/W",  0,      0,      16ull,  16ull},
19309         {"RESERVED_5_63"               ,        5,      59,     145,    "RAZ",  1,      1,      0,      0},
19310         {"CORRUPT"                     ,        0,      4,      146,    "R/W",  0,      0,      15ull,  15ull},
19311         {"RESERVED_4_63"               ,        4,      60,     146,    "RAZ",  1,      1,      0,      0},
19312         {"IFG1"                        ,        0,      4,      147,    "R/W",  0,      1,      8ull,   0},
19313         {"IFG2"                        ,        4,      4,      147,    "R/W",  0,      1,      4ull,   0},
19314         {"RESERVED_8_63"               ,        8,      56,     147,    "RAZ",  1,      1,      0,      0},
19315         {"PKO_NXA"                     ,        0,      1,      148,    "R/W",  0,      0,      0ull,   0ull},
19316         {"NCB_NXA"                     ,        1,      1,      148,    "R/W",  0,      0,      0ull,   0ull},
19317         {"UNDFLW"                      ,        2,      4,      148,    "R/W",  0,      0,      0ull,   0ull},
19318         {"RESERVED_6_7"                ,        6,      2,      148,    "RAZ",  0,      0,      0ull,   0ull},
19319         {"XSCOL"                       ,        8,      4,      148,    "R/W",  0,      0,      0ull,   0ull},
19320         {"XSDEF"                       ,        12,     4,      148,    "R/W",  0,      0,      0ull,   0ull},
19321         {"LATE_COL"                    ,        16,     4,      148,    "R/W",  0,      0,      0ull,   0ull},
19322         {"RESERVED_20_63"              ,        20,     44,     148,    "RAZ",  1,      1,      0,      0},
19323         {"PKO_NXA"                     ,        0,      1,      149,    "R/W1C",        0,      0,      0ull,   0ull},
19324         {"NCB_NXA"                     ,        1,      1,      149,    "R/W1C",        0,      0,      0ull,   0ull},
19325         {"UNDFLW"                      ,        2,      4,      149,    "R/W1C",        0,      0,      0ull,   0ull},
19326         {"RESERVED_6_7"                ,        6,      2,      149,    "RAZ",  0,      0,      0ull,   0ull},
19327         {"XSCOL"                       ,        8,      4,      149,    "R/W1C",        0,      0,      0ull,   0ull},
19328         {"XSDEF"                       ,        12,     4,      149,    "R/W1C",        0,      0,      0ull,   0ull},
19329         {"LATE_COL"                    ,        16,     4,      149,    "R/W1C",        0,      0,      0ull,   0ull},
19330         {"RESERVED_20_63"              ,        20,     44,     149,    "RAZ",  1,      1,      0,      0},
19331         {"JAM"                         ,        0,      8,      150,    "R/W",  0,      1,      238ull, 0},
19332         {"RESERVED_8_63"               ,        8,      56,     150,    "RAZ",  1,      1,      0,      0},
19333         {"LFSR"                        ,        0,      16,     151,    "R/W",  0,      1,      65535ull,       0},
19334         {"RESERVED_16_63"              ,        16,     48,     151,    "RAZ",  1,      1,      0,      0},
19335         {"IGN_FULL"                    ,        0,      4,      152,    "R/W",  0,      0,      0ull,   0ull},
19336         {"BP"                          ,        4,      4,      152,    "R/W",  0,      0,      0ull,   0ull},
19337         {"EN"                          ,        8,      4,      152,    "R/W",  0,      0,      0ull,   0ull},
19338         {"RESERVED_12_63"              ,        12,     52,     152,    "RAZ",  1,      1,      0,      0},
19339         {"DMAC"                        ,        0,      48,     153,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
19340         {"RESERVED_48_63"              ,        48,     16,     153,    "RAZ",  1,      1,      0,      0},
19341         {"TYPE"                        ,        0,      16,     154,    "R/W",  0,      0,      34824ull,       34824ull},
19342         {"RESERVED_16_63"              ,        16,     48,     154,    "RAZ",  1,      1,      0,      0},
19343         {"PRTS"                        ,        0,      5,      155,    "R/W",  0,      1,      1ull,   0},
19344         {"RESERVED_5_63"               ,        5,      59,     155,    "RAZ",  1,      1,      0,      0},
19345         {"CONT_PKT"                    ,        0,      1,      156,    "R/W",  0,      1,      0ull,   0},
19346         {"TPA_CLR"                     ,        1,      1,      156,    "R/W",  0,      1,      0ull,   0},
19347         {"RESERVED_2_63"               ,        2,      62,     156,    "RAZ",  0,      0,      0ull,   0ull},
19348         {"DRAIN"                       ,        0,      16,     157,    "R/W",  0,      0,      0ull,   0ull},
19349         {"RESERVED_16_63"              ,        16,     48,     157,    "RAZ",  1,      1,      0,      0},
19350         {"MAX1"                        ,        0,      8,      158,    "R/W",  0,      1,      8ull,   0},
19351         {"MAX2"                        ,        8,      8,      158,    "R/W",  0,      1,      4ull,   0},
19352         {"RESERVED_16_63"              ,        16,     48,     158,    "RAZ",  1,      1,      0,      0},
19353         {"THRESH"                      ,        0,      6,      159,    "R/W",  0,      1,      4ull,   0},
19354         {"RESERVED_6_63"               ,        6,      58,     159,    "RAZ",  1,      1,      0,      0},
19355         {"TX_OE"                       ,        0,      1,      160,    "R/W",  0,      0,      0ull,   0ull},
19356         {"RX_XOR"                      ,        1,      1,      160,    "R/W",  0,      0,      0ull,   0ull},
19357         {"INT_EN"                      ,        2,      1,      160,    "R/W",  0,      0,      0ull,   0ull},
19358         {"INT_TYPE"                    ,        3,      1,      160,    "R/W",  0,      0,      0ull,   0ull},
19359         {"FIL_CNT"                     ,        4,      4,      160,    "R/W",  0,      0,      0ull,   0ull},
19360         {"FIL_SEL"                     ,        8,      4,      160,    "R/W",  0,      0,      0ull,   0ull},
19361         {"RESERVED_12_63"              ,        12,     52,     160,    "RAZ",  1,      1,      0,      0},
19362         {"TYPE"                        ,        0,      16,     161,    "WO",   0,      0,      0ull,   0ull},
19363         {"RESERVED_16_63"              ,        16,     48,     161,    "RAZ",  1,      1,      0,      0},
19364         {"DAT"                         ,        0,      16,     162,    "RO",   0,      0,      0ull,   0ull},
19365         {"RESERVED_16_63"              ,        16,     48,     162,    "RAZ",  1,      1,      0,      0},
19366         {"CLR"                         ,        0,      16,     163,    "WO",   0,      0,      0ull,   0ull},
19367         {"RESERVED_16_63"              ,        16,     48,     163,    "RAZ",  1,      1,      0,      0},
19368         {"SET"                         ,        0,      16,     164,    "WO",   0,      0,      0ull,   0ull},
19369         {"RESERVED_16_63"              ,        16,     48,     164,    "RAZ",  1,      1,      0,      0},
19370         {"ICD"                         ,        0,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19371         {"IBD"                         ,        1,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19372         {"ICRP1"                       ,        2,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19373         {"ICRP0"                       ,        3,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19374         {"ICRN1"                       ,        4,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19375         {"ICRN0"                       ,        5,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19376         {"IBRQ1"                       ,        6,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19377         {"IBRQ0"                       ,        7,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19378         {"ICNRT"                       ,        8,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19379         {"IBR1"                        ,        9,      1,      165,    "RO",   0,      0,      0ull,   0ull},
19380         {"IBR0"                        ,        10,     1,      165,    "RO",   0,      0,      0ull,   0ull},
19381         {"IBDR1"                       ,        11,     1,      165,    "RO",   0,      0,      0ull,   0ull},
19382         {"IBDR0"                       ,        12,     1,      165,    "RO",   0,      0,      0ull,   0ull},
19383         {"ICNR0"                       ,        13,     1,      165,    "RO",   0,      0,      0ull,   0ull},
19384         {"ICNR1"                       ,        14,     1,      165,    "RO",   0,      0,      0ull,   0ull},
19385         {"ICR1"                        ,        15,     1,      165,    "RO",   0,      0,      0ull,   0ull},
19386         {"ICR0"                        ,        16,     1,      165,    "RO",   0,      0,      0ull,   0ull},
19387         {"ICNRCB"                      ,        17,     1,      165,    "RO",   0,      0,      0ull,   0ull},
19388         {"RESERVED_18_63"              ,        18,     46,     165,    "RAZ",  1,      1,      0,      0},
19389         {"FAU_END"                     ,        0,      1,      166,    "R/W",  0,      0,      0ull,   0ull},
19390         {"DWB_ENB"                     ,        1,      1,      166,    "R/W",  0,      0,      1ull,   1ull},
19391         {"PKO_ENB"                     ,        2,      1,      166,    "R/W",  0,      0,      0ull,   0ull},
19392         {"INB_MAT"                     ,        3,      1,      166,    "R/W1C",        0,      0,      0ull,   0ull},
19393         {"OUTB_MAT"                    ,        4,      1,      166,    "R/W1C",        0,      0,      0ull,   0ull},
19394         {"RESERVED_5_63"               ,        5,      59,     166,    "RAZ",  1,      1,      0,      0},
19395         {"CNT_VAL"                     ,        0,      15,     167,    "R/W",  0,      0,      0ull,   0ull},
19396         {"CNT_ENB"                     ,        15,     1,      167,    "R/W",  0,      0,      0ull,   0ull},
19397         {"RESERVED_16_63"              ,        16,     48,     167,    "RAZ",  1,      1,      0,      0},
19398         {"TOUT_VAL"                    ,        0,      12,     168,    "R/W",  0,      0,      4ull,   4ull},
19399         {"TOUT_ENB"                    ,        12,     1,      168,    "R/W",  0,      0,      1ull,   0ull},
19400         {"RESERVED_13_63"              ,        13,     51,     168,    "RAZ",  1,      1,      0,      0},
19401         {"CNT_VAL"                     ,        0,      15,     169,    "R/W",  0,      0,      0ull,   0ull},
19402         {"CNT_ENB"                     ,        15,     1,      169,    "R/W",  0,      0,      0ull,   0ull},
19403         {"RESERVED_16_63"              ,        16,     48,     169,    "RAZ",  1,      1,      0,      0},
19404         {"SRC"                         ,        0,      8,      170,    "R/W",  0,      1,      0ull,   0},
19405         {"DST"                         ,        8,      9,      170,    "R/W",  0,      1,      0ull,   0},
19406         {"OPC"                         ,        17,     4,      170,    "R/W",  0,      1,      0ull,   0},
19407         {"MASK"                        ,        21,     8,      170,    "R/W",  0,      1,      0ull,   0},
19408         {"RESERVED_29_63"              ,        29,     35,     170,    "RAZ",  1,      1,      0,      0},
19409         {"SRC"                         ,        0,      8,      171,    "R/W",  0,      1,      0ull,   0},
19410         {"DST"                         ,        8,      9,      171,    "R/W",  0,      1,      0ull,   0},
19411         {"OPC"                         ,        17,     4,      171,    "R/W",  0,      1,      0ull,   0},
19412         {"MASK"                        ,        21,     8,      171,    "R/W",  0,      1,      0ull,   0},
19413         {"RESERVED_29_63"              ,        29,     35,     171,    "RAZ",  1,      1,      0,      0},
19414         {"DATA"                        ,        0,      64,     172,    "R/W",  0,      1,      0ull,   0},
19415         {"DATA"                        ,        0,      64,     173,    "R/W",  0,      1,      0ull,   0},
19416         {"NP_SOP"                      ,        0,      1,      174,    "R/W",  0,      0,      0ull,   0ull},
19417         {"NP_EOP"                      ,        1,      1,      174,    "R/W",  0,      0,      0ull,   0ull},
19418         {"P_SOP"                       ,        2,      1,      174,    "R/W",  0,      0,      0ull,   0ull},
19419         {"P_EOP"                       ,        3,      1,      174,    "R/W",  0,      0,      0ull,   0ull},
19420         {"RESERVED_4_63"               ,        4,      60,     174,    "RAZ",  1,      1,      0,      0},
19421         {"NP_SOP"                      ,        0,      1,      175,    "R/W1C",        0,      0,      0ull,   0ull},
19422         {"NP_EOP"                      ,        1,      1,      175,    "R/W1C",        0,      0,      0ull,   0ull},
19423         {"P_SOP"                       ,        2,      1,      175,    "R/W1C",        0,      0,      0ull,   0ull},
19424         {"P_EOP"                       ,        3,      1,      175,    "R/W1C",        0,      0,      0ull,   0ull},
19425         {"RESERVED_4_63"               ,        4,      60,     175,    "RAZ",  1,      1,      0,      0},
19426         {"CNT_VAL"                     ,        0,      15,     176,    "R/W",  0,      0,      0ull,   0ull},
19427         {"CNT_ENB"                     ,        15,     1,      176,    "R/W",  0,      0,      0ull,   0ull},
19428         {"RESERVED_16_63"              ,        16,     48,     176,    "RAZ",  1,      1,      0,      0},
19429         {"CNT_VAL"                     ,        0,      15,     177,    "R/W",  0,      0,      0ull,   0ull},
19430         {"CNT_ENB"                     ,        15,     1,      177,    "R/W",  0,      0,      0ull,   0ull},
19431         {"RESERVED_16_63"              ,        16,     48,     177,    "RAZ",  1,      1,      0,      0},
19432         {"CNT_VAL"                     ,        0,      15,     178,    "R/W",  0,      0,      0ull,   0ull},
19433         {"CNT_ENB"                     ,        15,     1,      178,    "R/W",  0,      0,      0ull,   0ull},
19434         {"RESERVED_16_63"              ,        16,     48,     178,    "RAZ",  1,      1,      0,      0},
19435         {"SRC"                         ,        0,      9,      179,    "R/W",  0,      1,      0ull,   0},
19436         {"DST"                         ,        9,      8,      179,    "R/W",  0,      1,      0ull,   0},
19437         {"EOT"                         ,        17,     1,      179,    "R/W",  0,      1,      0ull,   0},
19438         {"MASK"                        ,        18,     8,      179,    "R/W",  0,      1,      0ull,   0},
19439         {"RESERVED_26_63"              ,        26,     38,     179,    "RAZ",  1,      1,      0,      0},
19440         {"SRC"                         ,        0,      9,      180,    "R/W",  0,      1,      0ull,   0},
19441         {"DST"                         ,        9,      8,      180,    "R/W",  0,      1,      0ull,   0},
19442         {"EOT"                         ,        17,     1,      180,    "R/W",  0,      1,      0ull,   0},
19443         {"MASK"                        ,        18,     8,      180,    "R/W",  0,      1,      0ull,   0},
19444         {"RESERVED_26_63"              ,        26,     38,     180,    "RAZ",  1,      1,      0,      0},
19445         {"DATA"                        ,        0,      64,     181,    "R/W",  0,      1,      0ull,   0},
19446         {"DATA"                        ,        0,      64,     182,    "R/W",  0,      1,      0ull,   0},
19447         {"CNT_VAL"                     ,        0,      15,     183,    "R/W",  0,      0,      0ull,   0ull},
19448         {"CNT_ENB"                     ,        15,     1,      183,    "R/W",  0,      0,      0ull,   0ull},
19449         {"RESERVED_16_63"              ,        16,     48,     183,    "RAZ",  1,      1,      0,      0},
19450         {"CNT_VAL"                     ,        0,      15,     184,    "R/W",  0,      0,      0ull,   0ull},
19451         {"CNT_ENB"                     ,        15,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
19452         {"RESERVED_16_63"              ,        16,     48,     184,    "RAZ",  1,      1,      0,      0},
19453         {"CNT_VAL"                     ,        0,      15,     185,    "R/W",  0,      0,      0ull,   0ull},
19454         {"CNT_ENB"                     ,        15,     1,      185,    "R/W",  0,      0,      0ull,   0ull},
19455         {"RESERVED_16_63"              ,        16,     48,     185,    "RAZ",  1,      1,      0,      0},
19456         {"PORT"                        ,        0,      6,      186,    "RO",   0,      1,      0ull,   0},
19457         {"RESERVED_6_63"               ,        6,      58,     186,    "RAZ",  1,      1,      0,      0},
19458         {"SKIP_SZ"                     ,        0,      6,      187,    "R/W",  0,      0,      0ull,   0ull},
19459         {"RESERVED_6_63"               ,        6,      58,     187,    "RAZ",  1,      1,      0,      0},
19460         {"BACK"                        ,        0,      4,      188,    "R/W",  0,      0,      0ull,   0ull},
19461         {"RESERVED_4_63"               ,        4,      60,     188,    "RAZ",  1,      1,      0,      0},
19462         {"BACK"                        ,        0,      4,      189,    "R/W",  0,      0,      0ull,   0ull},
19463         {"RESERVED_4_63"               ,        4,      60,     189,    "RAZ",  1,      1,      0,      0},
19464         {"PWP"                         ,        0,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19465         {"IPD_NEW"                     ,        1,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19466         {"IPD_OLD"                     ,        2,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19467         {"PRC_OFF"                     ,        3,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19468         {"PWQ0"                        ,        4,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19469         {"PWQ1"                        ,        5,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19470         {"PBM_WORD"                    ,        6,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19471         {"PBM0"                        ,        7,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19472         {"PBM1"                        ,        8,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19473         {"PBM2"                        ,        9,      1,      190,    "RO",   0,      0,      0ull,   0ull},
19474         {"PBM3"                        ,        10,     1,      190,    "RO",   0,      0,      0ull,   0ull},
19475         {"IPQ_PBE0"                    ,        11,     1,      190,    "RO",   0,      0,      0ull,   0ull},
19476         {"IPQ_PBE1"                    ,        12,     1,      190,    "RO",   0,      0,      0ull,   0ull},
19477         {"PWQ_POW"                     ,        13,     1,      190,    "RO",   0,      0,      0ull,   0ull},
19478         {"PWQ_WP1"                     ,        14,     1,      190,    "RO",   0,      0,      0ull,   0ull},
19479         {"PWQ_WQED"                    ,        15,     1,      190,    "RO",   0,      0,      0ull,   0ull},
19480         {"RESERVED_16_63"              ,        16,     48,     190,    "RAZ",  1,      1,      0,      0},
19481         {"PRT_ENB"                     ,        0,      36,     191,    "R/W",  0,      0,      0ull,   0ull},
19482         {"RESERVED_36_63"              ,        36,     28,     191,    "RAZ",  1,      1,      0,      0},
19483         {"CLK_CNT"                     ,        0,      64,     192,    "RO",   0,      0,      0ull,   0ull},
19484         {"IPD_EN"                      ,        0,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
19485         {"OPC_MODE"                    ,        1,      2,      193,    "R/W",  0,      0,      0ull,   0ull},
19486         {"PBP_EN"                      ,        3,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
19487         {"WQE_LEND"                    ,        4,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
19488         {"PKT_LEND"                    ,        5,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
19489         {"NADDBUF"                     ,        6,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
19490         {"ADDPKT"                      ,        7,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
19491         {"RESET"                       ,        8,      1,      193,    "R/W",  0,      0,      0ull,   0ull},
19492         {"LEN_M8"                      ,        9,      1,      193,    "R/W",  0,      0,      0ull,   1ull},
19493         {"RESERVED_10_63"              ,        10,     54,     193,    "RAZ",  1,      1,      0,      0},
19494         {"PRC_PAR0"                    ,        0,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19495         {"PRC_PAR1"                    ,        1,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19496         {"PRC_PAR2"                    ,        2,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19497         {"PRC_PAR3"                    ,        3,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19498         {"BP_SUB"                      ,        4,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19499         {"DC_OVR"                      ,        5,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19500         {"CC_OVR"                      ,        6,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19501         {"C_COLL"                      ,        7,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19502         {"D_COLL"                      ,        8,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19503         {"BC_OVR"                      ,        9,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
19504         {"RESERVED_10_63"              ,        10,     54,     194,    "RAZ",  1,      1,      0,      0},
19505         {"PRC_PAR0"                    ,        0,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19506         {"PRC_PAR1"                    ,        1,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19507         {"PRC_PAR2"                    ,        2,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19508         {"PRC_PAR3"                    ,        3,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19509         {"BP_SUB"                      ,        4,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19510         {"DC_OVR"                      ,        5,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19511         {"CC_OVR"                      ,        6,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19512         {"C_COLL"                      ,        7,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19513         {"D_COLL"                      ,        8,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19514         {"BC_OVR"                      ,        9,      1,      195,    "R/W1C",        0,      0,      0ull,   0ull},
19515         {"RESERVED_10_63"              ,        10,     54,     195,    "RAZ",  1,      1,      0,      0},
19516         {"SKIP_SZ"                     ,        0,      6,      196,    "R/W",  0,      0,      0ull,   0ull},
19517         {"RESERVED_6_63"               ,        6,      58,     196,    "RAZ",  1,      1,      0,      0},
19518         {"MB_SIZE"                     ,        0,      12,     197,    "R/W",  0,      0,      32ull,  32ull},
19519         {"RESERVED_12_63"              ,        12,     52,     197,    "RAZ",  1,      1,      0,      0},
19520         {"PTR"                         ,        0,      29,     198,    "RO",   1,      1,      0,      0},
19521         {"RESERVED_29_63"              ,        29,     35,     198,    "RAZ",  1,      1,      0,      0},
19522         {"PAGE_CNT"                    ,        0,      17,     199,    "R/W",  0,      0,      0ull,   0ull},
19523         {"BP_ENB"                      ,        17,     1,      199,    "R/W",  0,      0,      0ull,   0ull},
19524         {"RESERVED_18_63"              ,        18,     46,     199,    "RAZ",  1,      1,      0,      0},
19525         {"CNT_VAL"                     ,        0,      25,     200,    "RO",   0,      1,      0ull,   0},
19526         {"RESERVED_25_63"              ,        25,     39,     200,    "RAZ",  1,      1,      0,      0},
19527         {"RADDR"                       ,        0,      3,      201,    "R/W",  0,      0,      0ull,   0ull},
19528         {"CENA"                        ,        3,      1,      201,    "R/W",  0,      0,      1ull,   1ull},
19529         {"PTR"                         ,        4,      29,     201,    "RO",   1,      1,      0,      0},
19530         {"PRADDR"                      ,        33,     3,      201,    "RO",   1,      1,      0,      0},
19531         {"MAX_PKT"                     ,        36,     3,      201,    "RO",   0,      0,      5ull,   5ull},
19532         {"RESERVED_39_63"              ,        39,     25,     201,    "RAZ",  1,      1,      0,      0},
19533         {"RADDR"                       ,        0,      7,      202,    "R/W",  0,      0,      0ull,   0ull},
19534         {"CENA"                        ,        7,      1,      202,    "R/W",  0,      0,      1ull,   1ull},
19535         {"PTR"                         ,        8,      29,     202,    "RO",   1,      1,      0,      0},
19536         {"MAX_PKT"                     ,        37,     7,      202,    "RO",   0,      0,      36ull,  36ull},
19537         {"RESERVED_44_63"              ,        44,     20,     202,    "RAZ",  1,      1,      0,      0},
19538         {"WQE_PCNT"                    ,        0,      7,      203,    "RO",   0,      0,      0ull,   0ull},
19539         {"PKT_PCNT"                    ,        7,      7,      203,    "RO",   0,      0,      0ull,   0ull},
19540         {"PFIF_CNT"                    ,        14,     3,      203,    "RO",   0,      0,      0ull,   0ull},
19541         {"WQEV_CNT"                    ,        17,     1,      203,    "RO",   0,      0,      0ull,   0ull},
19542         {"PKTV_CNT"                    ,        18,     1,      203,    "RO",   0,      0,      0ull,   0ull},
19543         {"RESERVED_19_63"              ,        19,     45,     203,    "RAZ",  1,      1,      0,      0},
19544         {"RADDR"                       ,        0,      8,      204,    "R/W",  0,      0,      0ull,   0ull},
19545         {"CENA"                        ,        8,      1,      204,    "R/W",  0,      0,      1ull,   1ull},
19546         {"PTR"                         ,        9,      29,     204,    "RO",   1,      1,      0,      0},
19547         {"PRADDR"                      ,        38,     8,      204,    "RO",   1,      1,      0,      0},
19548         {"WRADDR"                      ,        46,     8,      204,    "RO",   1,      1,      0,      0},
19549         {"MAX_CNTS"                    ,        54,     7,      204,    "RO",   0,      0,      64ull,  64ull},
19550         {"RESERVED_61_63"              ,        61,     3,      204,    "RAZ",  1,      1,      0,      0},
19551         {"PASS"                        ,        0,      32,     205,    "R/W",  0,      1,      0ull,   0},
19552         {"DROP"                        ,        32,     32,     205,    "R/W",  0,      1,      0ull,   0},
19553         {"Q0_PCNT"                     ,        0,      32,     206,    "RO",   0,      0,      0ull,   0ull},
19554         {"RESERVED_32_63"              ,        32,     32,     206,    "RAZ",  1,      1,      0,      0},
19555         {"PRT_ENB"                     ,        0,      36,     207,    "R/W",  0,      0,      0ull,   0ull},
19556         {"AVG_DLY"                     ,        36,     14,     207,    "R/W",  0,      1,      0ull,   0},
19557         {"PRB_DLY"                     ,        50,     14,     207,    "R/W",  0,      0,      0ull,   0ull},
19558         {"PRB_CON"                     ,        0,      32,     208,    "R/W",  0,      1,      0ull,   0},
19559         {"AVG_CON"                     ,        32,     8,      208,    "R/W",  0,      1,      0ull,   0},
19560         {"NEW_CON"                     ,        40,     8,      208,    "R/W",  0,      1,      0ull,   0},
19561         {"USE_PCNT"                    ,        48,     1,      208,    "R/W",  0,      0,      0ull,   0ull},
19562         {"RESERVED_49_63"              ,        49,     15,     208,    "RAZ",  1,      1,      0,      0},
19563         {"PAGE_CNT"                    ,        0,      25,     209,    "R/W",  1,      0,      0,      0ull},
19564         {"PORT"                        ,        25,     6,      209,    "R/W",  1,      0,      0,      0ull},
19565         {"RESERVED_31_63"              ,        31,     33,     209,    "RAZ",  1,      1,      0,      0},
19566         {"PORT_BIT"                    ,        0,      32,     210,    "R/W",  0,      0,      4294967295ull,  4294967295ull},
19567         {"RESERVED_32_63"              ,        32,     32,     210,    "RAZ",  1,      1,      0,      0},
19568         {"WQE_POOL"                    ,        0,      3,      211,    "R/W",  0,      0,      1ull,   1ull},
19569         {"RESERVED_3_63"               ,        3,      61,     211,    "RAZ",  1,      1,      0,      0},
19570         {"PTR"                         ,        0,      29,     212,    "RO",   1,      1,      0,      0},
19571         {"RESERVED_29_63"              ,        29,     35,     212,    "RAZ",  1,      1,      0,      0},
19572         {"MEM0"                        ,        0,      1,      213,    "RO",   0,      0,      0ull,   0ull},
19573         {"MEM1"                        ,        1,      1,      213,    "RO",   0,      0,      0ull,   0ull},
19574         {"RRC"                         ,        2,      1,      213,    "RO",   0,      0,      0ull,   0ull},
19575         {"RESERVED_3_63"               ,        3,      61,     213,    "RAZ",  1,      1,      0,      0},
19576         {"MEM0_ERR"                    ,        0,      7,      214,    "R/W",  0,      0,      0ull,   0ull},
19577         {"MEM1_ERR"                    ,        7,      7,      214,    "R/W",  0,      0,      0ull,   0ull},
19578         {"RESERVED_14_63"              ,        14,     50,     214,    "RAZ",  1,      1,      0,      0},
19579         {"KED0_SBE"                    ,        0,      1,      215,    "R/W",  0,      0,      0ull,   0ull},
19580         {"KED0_DBE"                    ,        1,      1,      215,    "R/W",  0,      0,      0ull,   0ull},
19581         {"KED1_SBE"                    ,        2,      1,      215,    "R/W",  0,      0,      0ull,   0ull},
19582         {"KED1_DBE"                    ,        3,      1,      215,    "R/W",  0,      0,      0ull,   0ull},
19583         {"RESERVED_4_63"               ,        4,      60,     215,    "RAZ",  1,      1,      0,      0},
19584         {"KED0_SBE"                    ,        0,      1,      216,    "R/W1C",        0,      0,      0ull,   0ull},
19585         {"KED0_DBE"                    ,        1,      1,      216,    "R/W1C",        0,      0,      0ull,   0ull},
19586         {"KED1_SBE"                    ,        2,      1,      216,    "R/W1C",        0,      0,      0ull,   0ull},
19587         {"KED1_DBE"                    ,        3,      1,      216,    "R/W1C",        0,      0,      0ull,   0ull},
19588         {"RESERVED_4_63"               ,        4,      60,     216,    "RAZ",  1,      1,      0,      0},
19589         {"WLB_DAT"                     ,        0,      4,      217,    "RO",   0,      0,      0ull,   0ull},
19590         {"STIN_MSK"                    ,        4,      1,      217,    "RO",   0,      0,      0ull,   0ull},
19591         {"DT"                          ,        5,      1,      217,    "RO",   0,      0,      0ull,   0ull},
19592         {"DTCNT"                       ,        6,      13,     217,    "RO",   0,      0,      0ull,   0ull},
19593         {"RESERVED_19_63"              ,        19,     45,     217,    "RAZ",  0,      0,      0ull,   0ull},
19594         {"L2T"                         ,        0,      9,      218,    "RO",   0,      0,      0ull,   0ull},
19595         {"VAB_VWCF"                    ,        9,      1,      218,    "RO",   0,      0,      0ull,   0ull},
19596         {"LRF"                         ,        10,     2,      218,    "RO",   0,      0,      0ull,   0ull},
19597         {"VWDF"                        ,        12,     4,      218,    "RO",   0,      0,      0ull,   0ull},
19598         {"RESERVED_16_63"              ,        16,     48,     218,    "RAZ",  0,      0,      0ull,   0ull},
19599         {"XRDDAT"                      ,        0,      1,      219,    "RO",   0,      0,      0ull,   0ull},
19600         {"XRDMSK"                      ,        1,      1,      219,    "RO",   0,      0,      0ull,   0ull},
19601         {"PICBST"                      ,        2,      1,      219,    "RO",   0,      0,      0ull,   0ull},
19602         {"IPCBST"                      ,        3,      1,      219,    "RO",   0,      0,      0ull,   0ull},
19603         {"RHDF"                        ,        4,      4,      219,    "RO",   0,      0,      0ull,   0ull},
19604         {"RMDF"                        ,        8,      4,      219,    "RO",   0,      0,      0ull,   0ull},
19605         {"MRB"                         ,        12,     4,      219,    "RO",   0,      0,      0ull,   0ull},
19606         {"RESERVED_16_63"              ,        16,     48,     219,    "RAZ",  0,      0,      0ull,   0ull},
19607         {"LRF_ARB_MODE"                ,        0,      1,      220,    "R/W",  0,      0,      1ull,   1ull},
19608         {"RFB_ARB_MODE"                ,        1,      1,      220,    "R/W",  0,      0,      1ull,   1ull},
19609         {"RSP_ARB_MODE"                ,        2,      1,      220,    "R/W",  0,      0,      1ull,   1ull},
19610         {"MWF_CRD"                     ,        3,      4,      220,    "R/W",  0,      0,      2ull,   2ull},
19611         {"IDXALIAS"                    ,        7,      1,      220,    "R/W",  0,      0,      0ull,   1ull},
19612         {"FPEN"                        ,        8,      1,      220,    "R/W",  0,      0,      0ull,   0ull},
19613         {"FPEMPTY"                     ,        9,      1,      220,    "R/W",  0,      0,      0ull,   0ull},
19614         {"FPEXP"                       ,        10,     4,      220,    "R/W",  0,      0,      0ull,   0ull},
19615         {"RESERVED_14_63"              ,        14,     50,     220,    "RAZ",  1,      1,      0,      0},
19616         {"L2T"                         ,        0,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
19617         {"L2D"                         ,        1,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
19618         {"FINV"                        ,        2,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
19619         {"SET"                         ,        3,      3,      221,    "R/W",  0,      0,      0ull,   0ull},
19620         {"PPNUM"                       ,        6,      4,      221,    "R/W",  0,      0,      0ull,   0ull},
19621         {"LFB_DMP"                     ,        10,     1,      221,    "R/W",  0,      0,      0ull,   0ull},
19622         {"LFB_ENUM"                    ,        11,     4,      221,    "R/W",  0,      0,      0ull,   0ull},
19623         {"RESERVED_15_63"              ,        15,     49,     221,    "RAZ",  0,      0,      0ull,   0ull},
19624         {"DT_TAG"                      ,        0,      29,     222,    "RO",   0,      0,      0ull,   0ull},
19625         {"DT_VLD"                      ,        29,     1,      222,    "RO",   0,      0,      0ull,   0ull},
19626         {"RESERVED_30_30"              ,        30,     1,      222,    "RAZ",  0,      0,      0ull,   0ull},
19627         {"DTENA"                       ,        31,     1,      222,    "R/W",  0,      0,      0ull,   0ull},
19628         {"RESERVED_32_63"              ,        32,     32,     222,    "RAZ",  0,      0,      0ull,   0ull},
19629         {"LCK_ENA"                     ,        0,      1,      223,    "R/W",  0,      0,      0ull,   0ull},
19630         {"RESERVED_1_3"                ,        1,      3,      223,    "RAZ",  0,      0,      0ull,   0ull},
19631         {"LCK_BASE"                    ,        4,      27,     223,    "R/W",  0,      0,      0ull,   0ull},
19632         {"RESERVED_31_63"              ,        31,     33,     223,    "RAZ",  0,      0,      0ull,   0ull},
19633         {"LCK_OFFSET"                  ,        0,      10,     224,    "R/W",  0,      0,      0ull,   0ull},
19634         {"RESERVED_10_63"              ,        10,     54,     224,    "RAZ",  0,      0,      0ull,   0ull},
19635         {"VLD"                         ,        0,      1,      225,    "RO",   0,      0,      0ull,   0ull},
19636         {"CMD"                         ,        1,      4,      225,    "RO",   0,      0,      0ull,   0ull},
19637         {"SID"                         ,        5,      9,      225,    "RO",   0,      0,      0ull,   0ull},
19638         {"VABNUM"                      ,        14,     4,      225,    "RO",   0,      0,      0ull,   0ull},
19639         {"SET"                         ,        18,     3,      225,    "RO",   0,      0,      0ull,   0ull},
19640         {"IHD"                         ,        21,     1,      225,    "RO",   0,      0,      0ull,   0ull},
19641         {"ITL"                         ,        22,     1,      225,    "RO",   0,      0,      0ull,   0ull},
19642         {"INXT"                        ,        23,     4,      225,    "RO",   0,      0,      0ull,   0ull},
19643         {"VAM"                         ,        27,     1,      225,    "RO",   0,      0,      0ull,   0ull},
19644         {"STCFL"                       ,        28,     1,      225,    "RO",   0,      0,      0ull,   0ull},
19645         {"STINV"                       ,        29,     1,      225,    "RO",   0,      0,      0ull,   0ull},
19646         {"STPND"                       ,        30,     1,      225,    "RO",   0,      0,      0ull,   0ull},
19647         {"STCPND"                      ,        31,     1,      225,    "RO",   0,      0,      0ull,   0ull},
19648         {"RESERVED_32_63"              ,        32,     32,     225,    "RAZ",  0,      0,      0ull,   0ull},
19649         {"VLD"                         ,        0,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19650         {"WTPRB"                       ,        1,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19651         {"PRBRTY"                      ,        2,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19652         {"WTMFL"                       ,        3,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19653         {"WTVTM"                       ,        4,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19654         {"WTSTRSC"                     ,        5,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19655         {"WTSTRSP"                     ,        6,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19656         {"WTSTDT"                      ,        7,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19657         {"WTRDA"                       ,        8,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19658         {"WTSTM"                       ,        9,      1,      226,    "RO",   0,      0,      0ull,   0ull},
19659         {"WTWRM"                       ,        10,     1,      226,    "RO",   0,      0,      0ull,   0ull},
19660         {"WTWHF"                       ,        11,     1,      226,    "RO",   0,      0,      0ull,   0ull},
19661         {"WTWHP"                       ,        12,     1,      226,    "RO",   0,      0,      0ull,   0ull},
19662         {"WTDQ"                        ,        13,     1,      226,    "RO",   0,      0,      0ull,   0ull},
19663         {"WTDW"                        ,        14,     1,      226,    "RO",   0,      0,      0ull,   0ull},
19664         {"WTRSP"                       ,        15,     1,      226,    "RO",   0,      0,      0ull,   0ull},
19665         {"BID"                         ,        16,     2,      226,    "RO",   0,      0,      0ull,   0ull},
19666         {"DSGOING"                     ,        18,     1,      226,    "RO",   0,      0,      0ull,   0ull},
19667         {"RESERVED_19_63"              ,        19,     45,     226,    "RAZ",  0,      0,      0ull,   0ull},
19668         {"LFB_IDX"                     ,        0,      10,     227,    "RO",   0,      0,      0ull,   0ull},
19669         {"LFB_TAG"                     ,        10,     17,     227,    "RO",   0,      0,      0ull,   0ull},
19670         {"RESERVED_27_63"              ,        27,     37,     227,    "RAZ",  0,      0,      0ull,   0ull},
19671         {"LFB_HWM"                     ,        0,      4,      228,    "R/W",  0,      0,      15ull,  15ull},
19672         {"STPARTDIS"                   ,        4,      1,      228,    "R/W",  0,      0,      0ull,   0ull},
19673         {"RESERVED_5_63"               ,        5,      59,     228,    "RAZ",  0,      0,      0ull,   0ull},
19674         {"PFCNT0"                      ,        0,      36,     229,    "RO",   0,      0,      0ull,   0ull},
19675         {"RESERVED_36_63"              ,        36,     28,     229,    "RAZ",  0,      0,      0ull,   0ull},
19676         {"CNT0SEL"                     ,        0,      6,      230,    "R/W",  0,      0,      0ull,   0ull},
19677         {"CNT0CLR"                     ,        6,      1,      230,    "R/W",  0,      0,      0ull,   0ull},
19678         {"CNT0ENA"                     ,        7,      1,      230,    "R/W",  0,      0,      0ull,   0ull},
19679         {"CNT1SEL"                     ,        8,      6,      230,    "R/W",  0,      0,      0ull,   0ull},
19680         {"CNT1CLR"                     ,        14,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19681         {"CNT1ENA"                     ,        15,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19682         {"CNT2SEL"                     ,        16,     6,      230,    "R/W",  0,      0,      0ull,   0ull},
19683         {"CNT2CLR"                     ,        22,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19684         {"CNT2ENA"                     ,        23,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19685         {"CNT3SEL"                     ,        24,     6,      230,    "R/W",  0,      0,      0ull,   0ull},
19686         {"CNT3CLR"                     ,        30,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19687         {"CNT3ENA"                     ,        31,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19688         {"CNT0RDCLR"                   ,        32,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19689         {"CNT1RDCLR"                   ,        33,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19690         {"CNT2RDCLR"                   ,        34,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19691         {"CNT3RDCLR"                   ,        35,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
19692         {"RESERVED_36_63"              ,        36,     28,     230,    "RAZ",  0,      0,      0ull,   0ull},
19693         {"UMSK0"                       ,        0,      8,      231,    "R/W",  0,      0,      0ull,   0ull},
19694         {"UMSK1"                       ,        8,      8,      231,    "R/W",  0,      0,      0ull,   0ull},
19695         {"UMSK2"                       ,        16,     8,      231,    "R/W",  0,      0,      0ull,   0ull},
19696         {"UMSK3"                       ,        24,     8,      231,    "R/W",  0,      0,      0ull,   0ull},
19697         {"RESERVED_32_63"              ,        32,     32,     231,    "RAZ",  0,      0,      0ull,   0ull},
19698         {"UMSK4"                       ,        0,      8,      232,    "R/W",  0,      0,      0ull,   0ull},
19699         {"UMSK5"                       ,        8,      8,      232,    "R/W",  0,      0,      0ull,   0ull},
19700         {"UMSK6"                       ,        16,     8,      232,    "R/W",  0,      0,      0ull,   0ull},
19701         {"UMSK7"                       ,        24,     8,      232,    "R/W",  0,      0,      0ull,   0ull},
19702         {"RESERVED_32_63"              ,        32,     32,     232,    "RAZ",  0,      0,      0ull,   0ull},
19703         {"UMSK8"                       ,        0,      8,      233,    "R/W",  0,      0,      0ull,   0ull},
19704         {"UMSK9"                       ,        8,      8,      233,    "R/W",  0,      0,      0ull,   0ull},
19705         {"UMSK10"                      ,        16,     8,      233,    "R/W",  0,      0,      0ull,   0ull},
19706         {"UMSK11"                      ,        24,     8,      233,    "R/W",  0,      0,      0ull,   0ull},
19707         {"RESERVED_32_63"              ,        32,     32,     233,    "RAZ",  0,      0,      0ull,   0ull},
19708         {"UMSK12"                      ,        0,      8,      234,    "R/W",  0,      0,      0ull,   0ull},
19709         {"UMSK13"                      ,        8,      8,      234,    "R/W",  0,      0,      0ull,   0ull},
19710         {"UMSK14"                      ,        16,     8,      234,    "R/W",  0,      0,      0ull,   0ull},
19711         {"UMSK15"                      ,        24,     8,      234,    "R/W",  0,      0,      0ull,   0ull},
19712         {"RESERVED_32_63"              ,        32,     32,     234,    "RAZ",  0,      0,      0ull,   0ull},
19713         {"UMSKIOB"                     ,        0,      8,      235,    "R/W",  0,      0,      0ull,   0ull},
19714         {"RESERVED_8_63"               ,        8,      56,     235,    "RAZ",  0,      0,      0ull,   0ull},
19715         {"Q0STAT"                      ,        0,      34,     236,    "RO",   0,      0,      0ull,   0ull},
19716         {"FTL"                         ,        34,     1,      236,    "RO",   0,      0,      0ull,   0ull},
19717         {"RESERVED_35_63"              ,        35,     29,     236,    "RAZ",  0,      0,      0ull,   0ull},
19718         {"Q1STAT"                      ,        0,      34,     237,    "RO",   0,      0,      0ull,   0ull},
19719         {"RESERVED_34_63"              ,        34,     30,     237,    "RAZ",  0,      0,      0ull,   0ull},
19720         {"Q2STAT"                      ,        0,      34,     238,    "RO",   0,      0,      0ull,   0ull},
19721         {"RESERVED_34_63"              ,        34,     30,     238,    "RAZ",  0,      0,      0ull,   0ull},
19722         {"Q3STAT"                      ,        0,      34,     239,    "RO",   0,      0,      0ull,   0ull},
19723         {"RESERVED_34_63"              ,        34,     30,     239,    "RAZ",  0,      0,      0ull,   0ull},
19724         {"ECC_ENA"                     ,        0,      1,      240,    "R/W",  0,      0,      0ull,   1ull},
19725         {"SEC_INTENA"                  ,        1,      1,      240,    "R/W",  0,      0,      0ull,   1ull},
19726         {"DED_INTENA"                  ,        2,      1,      240,    "R/W",  0,      0,      0ull,   1ull},
19727         {"SEC_ERR"                     ,        3,      1,      240,    "R/W1C",        0,      0,      0ull,   0ull},
19728         {"DED_ERR"                     ,        4,      1,      240,    "R/W1C",        0,      0,      0ull,   0ull},
19729         {"BMHCLSEL"                    ,        5,      1,      240,    "R/W",  0,      0,      0ull,   0ull},
19730         {"RESERVED_6_63"               ,        6,      58,     240,    "RAZ",  0,      0,      0ull,   0ull},
19731         {"FADR"                        ,        0,      11,     241,    "RO",   0,      0,      0ull,   0ull},
19732         {"FSET"                        ,        11,     3,      241,    "RO",   0,      0,      0ull,   0ull},
19733         {"FOWMSK"                      ,        14,     4,      241,    "RO",   0,      0,      0ull,   0ull},
19734         {"RESERVED_18_63"              ,        18,     46,     241,    "RAZ",  0,      0,      0ull,   0ull},
19735         {"FSYN_OW0"                    ,        0,      10,     242,    "RO",   0,      0,      0ull,   0ull},
19736         {"FSYN_OW1"                    ,        10,     10,     242,    "RO",   0,      0,      0ull,   0ull},
19737         {"RESERVED_20_63"              ,        20,     44,     242,    "RAZ",  0,      0,      0ull,   0ull},
19738         {"FSYN_OW2"                    ,        0,      10,     243,    "RO",   0,      0,      0ull,   0ull},
19739         {"FSYN_OW3"                    ,        10,     10,     243,    "RO",   0,      0,      0ull,   0ull},
19740         {"RESERVED_20_63"              ,        20,     44,     243,    "RAZ",  0,      0,      0ull,   0ull},
19741         {"Q0FUS"                       ,        0,      34,     244,    "RO",   0,      0,      0ull,   0ull},
19742         {"RESERVED_34_63"              ,        34,     30,     244,    "RAZ",  0,      0,      0ull,   0ull},
19743         {"Q1FUS"                       ,        0,      34,     245,    "RO",   0,      0,      0ull,   0ull},
19744         {"RESERVED_34_63"              ,        34,     30,     245,    "RAZ",  0,      0,      0ull,   0ull},
19745         {"Q2FUS"                       ,        0,      34,     246,    "RO",   0,      0,      0ull,   0ull},
19746         {"RESERVED_34_63"              ,        34,     30,     246,    "RAZ",  0,      0,      0ull,   0ull},
19747         {"Q3FUS"                       ,        0,      34,     247,    "RO",   0,      0,      0ull,   0ull},
19748         {"CRIP_512K"                   ,        34,     1,      247,    "RO",   0,      0,      0ull,   0ull},
19749         {"CRIP_256K"                   ,        35,     1,      247,    "RO",   0,      0,      0ull,   0ull},
19750         {"RESERVED_36_63"              ,        36,     28,     247,    "RAZ",  0,      0,      0ull,   0ull},
19751         {"ECC_ENA"                     ,        0,      1,      248,    "R/W",  0,      0,      0ull,   1ull},
19752         {"SEC_INTENA"                  ,        1,      1,      248,    "R/W",  0,      0,      0ull,   1ull},
19753         {"DED_INTENA"                  ,        2,      1,      248,    "R/W",  0,      0,      0ull,   1ull},
19754         {"SEC_ERR"                     ,        3,      1,      248,    "R/W1C",        0,      0,      0ull,   0ull},
19755         {"DED_ERR"                     ,        4,      1,      248,    "R/W1C",        0,      0,      0ull,   0ull},
19756         {"FSYN"                        ,        5,      6,      248,    "RO",   0,      0,      0ull,   0ull},
19757         {"FADR"                        ,        11,     10,     248,    "RO",   0,      0,      0ull,   0ull},
19758         {"FSET"                        ,        21,     3,      248,    "RO",   0,      0,      0ull,   0ull},
19759         {"LCKERR"                      ,        24,     1,      248,    "R/W1C",        0,      0,      0ull,   0ull},
19760         {"LCK_INTENA"                  ,        25,     1,      248,    "R/W",  0,      0,      0ull,   1ull},
19761         {"LCKERR2"                     ,        26,     1,      248,    "R/W1C",        0,      0,      0ull,   0ull},
19762         {"LCK_INTENA2"                 ,        27,     1,      248,    "R/W",  0,      0,      0ull,   1ull},
19763         {"RESERVED_28_63"              ,        28,     36,     248,    "RAZ",  0,      0,      0ull,   0ull},
19764         {"RATE"                        ,        0,      8,      249,    "R/W",  0,      0,      4ull,   4ull},
19765         {"RESERVED_8_63"               ,        8,      56,     249,    "RAZ",  1,      1,      0,      0},
19766         {"PHASE"                       ,        0,      7,      250,    "R/W",  0,      0,      4ull,   4ull},
19767         {"RESERVED_7_63"               ,        7,      57,     250,    "RAZ",  1,      1,      0,      0},
19768         {"RATE"                        ,        0,      16,     251,    "R/W",  0,      0,      0ull,   0ull},
19769         {"RESERVED_16_63"              ,        16,     48,     251,    "RAZ",  1,      1,      0,      0},
19770         {"DBG_EN"                      ,        0,      1,      252,    "R/W",  0,      0,      0ull,   0ull},
19771         {"RESERVED_1_63"               ,        1,      63,     252,    "RAZ",  1,      1,      0,      0},
19772         {"EN"                          ,        0,      1,      253,    "R/W",  0,      0,      0ull,   1ull},
19773         {"RESERVED_1_63"               ,        1,      63,     253,    "RAZ",  1,      1,      0,      0},
19774         {"POLARITY"                    ,        0,      1,      254,    "R/W",  0,      0,      0ull,   0ull},
19775         {"RESERVED_1_63"               ,        1,      63,     254,    "RAZ",  1,      1,      0,      0},
19776         {"PRT_EN"                      ,        0,      8,      255,    "R/W",  0,      1,      0ull,   0},
19777         {"RESERVED_8_63"               ,        8,      56,     255,    "RAZ",  1,      1,      0,      0},
19778         {"FORMAT"                      ,        0,      4,      256,    "R/W",  0,      1,      0ull,   0},
19779         {"RESERVED_4_63"               ,        4,      60,     256,    "RAZ",  1,      1,      0,      0},
19780         {"STATUS"                      ,        0,      6,      257,    "R/W",  0,      0,      0ull,   0ull},
19781         {"RESERVED_6_63"               ,        6,      58,     257,    "RAZ",  1,      1,      0,      0},
19782         {"CNT"                         ,        0,      6,      258,    "R/W",  0,      0,      0ull,   0ull},
19783         {"RESERVED_6_63"               ,        6,      58,     258,    "RAZ",  1,      1,      0,      0},
19784         {"DAT"                         ,        0,      32,     259,    "R/W",  0,      1,      0ull,   0},
19785         {"RESERVED_32_63"              ,        32,     32,     259,    "RAZ",  1,      1,      0,      0},
19786         {"CLR"                         ,        0,      32,     260,    "WO",   0,      1,      0ull,   0},
19787         {"RESERVED_32_63"              ,        32,     32,     260,    "RAZ",  1,      1,      0,      0},
19788         {"SET"                         ,        0,      32,     261,    "WO",   0,      1,      0ull,   0},
19789         {"RESERVED_32_63"              ,        32,     32,     261,    "RAZ",  1,      1,      0,      0},
19790         {"PCTL_DAT"                    ,        0,      4,      262,    "R/W",  0,      1,      0ull,   0},
19791         {"PCTL_CMD"                    ,        4,      4,      262,    "R/W",  0,      1,      0ull,   0},
19792         {"PCTL_CLK"                    ,        8,      4,      262,    "R/W",  0,      1,      0ull,   0},
19793         {"PCTL_CSR"                    ,        12,     4,      262,    "R/W",  0,      1,      15ull,  0},
19794         {"NCTL_DAT"                    ,        16,     4,      262,    "R/W",  0,      1,      0ull,   0},
19795         {"NCTL_CMD"                    ,        20,     4,      262,    "R/W",  0,      1,      0ull,   0},
19796         {"NCTL_CLK"                    ,        24,     4,      262,    "R/W",  0,      1,      0ull,   0},
19797         {"NCTL_CSR"                    ,        28,     4,      262,    "R/W",  0,      1,      15ull,  0},
19798         {"RESERVED_32_63"              ,        32,     32,     262,    "RAZ",  0,      0,      0ull,   0ull},
19799         {"DIC"                         ,        0,      2,      263,    "R/W",  0,      0,      0ull,   0ull},
19800         {"QS_DIC"                      ,        2,      2,      263,    "R/W",  0,      0,      2ull,   2ull},
19801         {"TSKW"                        ,        4,      2,      263,    "R/W",  0,      0,      0ull,   1ull},
19802         {"SIL_LAT"                     ,        6,      2,      263,    "R/W",  0,      0,      1ull,   1ull},
19803         {"BPRCH"                       ,        8,      1,      263,    "R/W",  0,      1,      0ull,   0},
19804         {"FPRCH2"                      ,        9,      1,      263,    "R/W",  0,      0,      0ull,   1ull},
19805         {"MODE128B"                    ,        10,     1,      263,    "R/W",  0,      0,      1ull,   1ull},
19806         {"SET_ZERO"                    ,        11,     1,      263,    "R/W",  0,      0,      0ull,   0ull},
19807         {"INORDER_MRF"                 ,        12,     1,      263,    "R/W",  0,      0,      0ull,   0ull},
19808         {"INORDER_MWF"                 ,        13,     1,      263,    "R/W",  0,      0,      0ull,   0ull},
19809         {"R2R_SLOT"                    ,        14,     1,      263,    "R/W",  0,      0,      0ull,   0ull},
19810         {"RDIMM_ENA"                   ,        15,     1,      263,    "R/W",  0,      1,      0ull,   0},
19811         {"RESERVED_16_17"              ,        16,     2,      263,    "RAZ",  0,      0,      0ull,   0ull},
19812         {"MAX_WRITE_BATCH"             ,        18,     4,      263,    "R/W",  0,      0,      8ull,   8ull},
19813         {"XOR_BANK"                    ,        22,     1,      263,    "R/W",  0,      0,      0ull,   1ull},
19814         {"SLOW_SCF"                    ,        23,     1,      263,    "R/W",  0,      0,      0ull,   0ull},
19815         {"DDR__PCTL"                   ,        24,     4,      263,    "RO",   1,      1,      0,      0},
19816         {"DDR__NCTL"                   ,        28,     4,      263,    "RO",   1,      1,      0,      0},
19817         {"RESERVED_32_63"              ,        32,     32,     263,    "RAZ",  1,      1,      0,      0},
19818         {"DCLKCNT_HI"                  ,        0,      32,     264,    "RO",   0,      0,      0ull,   0ull},
19819         {"RESERVED_32_63"              ,        32,     32,     264,    "RAZ",  1,      1,      0,      0},
19820         {"DCLKCNT_LO"                  ,        0,      32,     265,    "RO",   0,      0,      0ull,   0ull},
19821         {"RESERVED_32_63"              ,        32,     32,     265,    "RAZ",  1,      1,      0,      0},
19822         {"DDR2"                        ,        0,      1,      266,    "R/W",  0,      0,      1ull,   1ull},
19823         {"RDQS"                        ,        1,      1,      266,    "R/W",  0,      0,      0ull,   0ull},
19824         {"DLL90_BYP"                   ,        2,      1,      266,    "R/W",  0,      0,      0ull,   0ull},
19825         {"DLL90_VLU"                   ,        3,      5,      266,    "R/W",  0,      1,      0ull,   0},
19826         {"QDLL_ENA"                    ,        8,      1,      266,    "R/W",  0,      0,      0ull,   0ull},
19827         {"ODT_ENA"                     ,        9,      1,      266,    "R/W",  0,      0,      0ull,   0ull},
19828         {"DDR2T"                       ,        10,     1,      266,    "R/W",  0,      1,      0ull,   0},
19829         {"CRIP_MODE"                   ,        11,     1,      266,    "R/W",  0,      0,      0ull,   0ull},
19830         {"TFAW"                        ,        12,     5,      266,    "R/W",  0,      0,      0ull,   9ull},
19831         {"DDR_EOF"                     ,        17,     4,      266,    "R/W",  0,      0,      2ull,   2ull},
19832         {"SILO_HC"                     ,        21,     1,      266,    "R/W",  0,      1,      1ull,   0},
19833         {"TWR"                         ,        22,     3,      266,    "R/W",  0,      0,      3ull,   1ull},
19834         {"BWCNT"                       ,        25,     1,      266,    "R/W",  0,      0,      0ull,   0ull},
19835         {"POCAS"                       ,        26,     1,      266,    "R/W",  0,      0,      0ull,   0ull},
19836         {"ADDLAT"                      ,        27,     3,      266,    "R/W",  0,      0,      0ull,   0ull},
19837         {"BURST8"                      ,        30,     1,      266,    "R/W",  0,      0,      0ull,   1ull},
19838         {"BANK8"                       ,        31,     1,      266,    "R/W",  0,      1,      0ull,   0},
19839         {"RESERVED_32_63"              ,        32,     32,     266,    "RAZ",  0,      0,      0ull,   0ull},
19840         {"CLK"                         ,        0,      4,      267,    "R/W",  0,      0,      0ull,   0ull},
19841         {"RESERVED_4_4"                ,        4,      1,      267,    "RAZ",  0,      0,      0ull,   0ull},
19842         {"CMD"                         ,        5,      4,      267,    "R/W",  0,      0,      0ull,   0ull},
19843         {"RESERVED_9_9"                ,        9,      1,      267,    "RAZ",  0,      0,      0ull,   0ull},
19844         {"DQ"                          ,        10,     4,      267,    "R/W",  0,      0,      0ull,   0ull},
19845         {"RESERVED_14_63"              ,        14,     50,     267,    "RAZ",  0,      0,      0ull,   0ull},
19846         {"MRDSYN0"                     ,        0,      8,      268,    "RO",   0,      0,      0ull,   0ull},
19847         {"MRDSYN1"                     ,        8,      8,      268,    "RO",   0,      0,      0ull,   0ull},
19848         {"MRDSYN2"                     ,        16,     8,      268,    "RO",   0,      0,      0ull,   0ull},
19849         {"MRDSYN3"                     ,        24,     8,      268,    "RO",   0,      0,      0ull,   0ull},
19850         {"RESERVED_32_63"              ,        32,     32,     268,    "RAZ",  1,      1,      0,      0},
19851         {"FCOL"                        ,        0,      12,     269,    "RO",   0,      0,      0ull,   0ull},
19852         {"FROW"                        ,        12,     14,     269,    "RO",   0,      0,      0ull,   0ull},
19853         {"FBANK"                       ,        26,     3,      269,    "RO",   0,      0,      0ull,   0ull},
19854         {"FBUNK"                       ,        29,     1,      269,    "RO",   0,      0,      0ull,   0ull},
19855         {"FDIMM"                       ,        30,     2,      269,    "RO",   0,      0,      0ull,   0ull},
19856         {"RESERVED_32_63"              ,        32,     32,     269,    "RAZ",  1,      1,      0,      0},
19857         {"IFBCNT_HI"                   ,        0,      32,     270,    "RO",   0,      0,      0ull,   0ull},
19858         {"RESERVED_32_63"              ,        32,     32,     270,    "RAZ",  1,      1,      0,      0},
19859         {"IFBCNT_LO"                   ,        0,      32,     271,    "RO",   0,      0,      0ull,   0ull},
19860         {"RESERVED_32_63"              ,        32,     32,     271,    "RAZ",  1,      1,      0,      0},
19861         {"INIT_START"                  ,        0,      1,      272,    "R/W",  0,      0,      0ull,   0ull},
19862         {"ECC_ENA"                     ,        1,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
19863         {"ROW_LSB"                     ,        2,      3,      272,    "R/W",  0,      1,      3ull,   0},
19864         {"PBANK_LSB"                   ,        5,      4,      272,    "R/W",  0,      1,      5ull,   0},
19865         {"REF_INT"                     ,        9,      6,      272,    "R/W",  0,      0,      1ull,   2ull},
19866         {"TCL"                         ,        15,     4,      272,    "R/W",  0,      1,      3ull,   0},
19867         {"INTR_SEC_ENA"                ,        19,     1,      272,    "R/W",  0,      0,      0ull,   1ull},
19868         {"INTR_DED_ENA"                ,        20,     1,      272,    "R/W",  0,      0,      0ull,   1ull},
19869         {"SEC_ERR"                     ,        21,     4,      272,    "R/W1C",        0,      0,      0ull,   0ull},
19870         {"DED_ERR"                     ,        25,     4,      272,    "R/W1C",        0,      0,      0ull,   0ull},
19871         {"BUNK_ENA"                    ,        29,     1,      272,    "R/W",  0,      1,      0ull,   0},
19872         {"SILO_QC"                     ,        30,     1,      272,    "R/W",  0,      1,      0ull,   0},
19873         {"RESET"                       ,        31,     1,      272,    "RAZ",  1,      1,      0,      0},
19874         {"RESERVED_32_63"              ,        32,     32,     272,    "RAZ",  1,      1,      0,      0},
19875         {"TRAS"                        ,        0,      5,      273,    "R/W",  0,      0,      12ull,  12ull},
19876         {"TRCD"                        ,        5,      4,      273,    "R/W",  0,      0,      4ull,   4ull},
19877         {"TWTR"                        ,        9,      4,      273,    "R/W",  0,      0,      2ull,   2ull},
19878         {"TRP"                         ,        13,     4,      273,    "R/W",  0,      0,      5ull,   4ull},
19879         {"TRFC"                        ,        17,     5,      273,    "R/W",  0,      0,      6ull,   7ull},
19880         {"TMRD"                        ,        22,     3,      273,    "R/W",  0,      0,      2ull,   2ull},
19881         {"CASLAT"                      ,        25,     3,      273,    "R/W",  0,      0,      4ull,   4ull},
19882         {"TRRD"                        ,        28,     3,      273,    "R/W",  0,      0,      2ull,   2ull},
19883         {"RESERVED_31_63"              ,        31,     33,     273,    "RAZ",  1,      1,      0,      0},
19884         {"OPSCNT_HI"                   ,        0,      32,     274,    "RO",   0,      0,      0ull,   0ull},
19885         {"RESERVED_32_63"              ,        32,     32,     274,    "RAZ",  1,      1,      0,      0},
19886         {"OPSCNT_LO"                   ,        0,      32,     275,    "RO",   0,      0,      0ull,   0ull},
19887         {"RESERVED_32_63"              ,        32,     32,     275,    "RAZ",  1,      1,      0,      0},
19888         {"BWCTL"                       ,        0,      4,      276,    "R/W",  0,      0,      0ull,   0ull},
19889         {"BWUPD"                       ,        4,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
19890         {"RESERVED_5_63"               ,        5,      59,     276,    "RAZ",  1,      1,      0,      0},
19891         {"RODT_LO0"                    ,        0,      4,      277,    "R/W",  0,      0,      15ull,  15ull},
19892         {"RODT_LO1"                    ,        4,      4,      277,    "R/W",  0,      0,      15ull,  15ull},
19893         {"RODT_LO2"                    ,        8,      4,      277,    "R/W",  0,      0,      15ull,  15ull},
19894         {"RODT_LO3"                    ,        12,     4,      277,    "R/W",  0,      0,      15ull,  15ull},
19895         {"RODT_HI0"                    ,        16,     4,      277,    "R/W",  0,      0,      15ull,  15ull},
19896         {"RODT_HI1"                    ,        20,     4,      277,    "R/W",  0,      0,      15ull,  15ull},
19897         {"RODT_HI2"                    ,        24,     4,      277,    "R/W",  0,      0,      15ull,  15ull},
19898         {"RODT_HI3"                    ,        28,     4,      277,    "R/W",  0,      0,      15ull,  15ull},
19899         {"RESERVED_32_63"              ,        32,     32,     277,    "RAZ",  1,      1,      0,      0},
19900         {"WODT_LO0"                    ,        0,      4,      278,    "R/W",  0,      0,      15ull,  15ull},
19901         {"WODT_LO1"                    ,        4,      4,      278,    "R/W",  0,      0,      15ull,  15ull},
19902         {"WODT_LO2"                    ,        8,      4,      278,    "R/W",  0,      0,      15ull,  15ull},
19903         {"WODT_LO3"                    ,        12,     4,      278,    "R/W",  0,      0,      15ull,  15ull},
19904         {"WODT_HI0"                    ,        16,     4,      278,    "R/W",  0,      0,      15ull,  15ull},
19905         {"WODT_HI1"                    ,        20,     4,      278,    "R/W",  0,      0,      15ull,  15ull},
19906         {"WODT_HI2"                    ,        24,     4,      278,    "R/W",  0,      0,      15ull,  15ull},
19907         {"WODT_HI3"                    ,        28,     4,      278,    "R/W",  0,      0,      15ull,  15ull},
19908         {"RESERVED_32_63"              ,        32,     32,     278,    "RAZ",  1,      1,      0,      0},
19909         {"NCBI"                        ,        0,      1,      279,    "RO",   0,      0,      0ull,   0ull},
19910         {"LOC"                         ,        1,      1,      279,    "RO",   0,      0,      0ull,   0ull},
19911         {"NCBO_0"                      ,        2,      1,      279,    "RO",   0,      0,      0ull,   0ull},
19912         {"RESERVED_3_63"               ,        3,      61,     279,    "RAZ",  1,      1,      0,      0},
19913         {"ADR_ERR"                     ,        0,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
19914         {"WAIT_ERR"                    ,        1,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
19915         {"RESERVED_2_63"               ,        2,      62,     280,    "RAZ",  1,      1,      0,      0},
19916         {"ADR_INT"                     ,        0,      1,      281,    "R/W",  0,      1,      0ull,   0},
19917         {"WAIT_INT"                    ,        1,      1,      281,    "R/W",  0,      1,      0ull,   0},
19918         {"RESERVED_2_63"               ,        2,      62,     281,    "RAZ",  1,      1,      0,      0},
19919         {"RESERVED_0_2"                ,        0,      3,      282,    "RAZ",  1,      1,      0,      0},
19920         {"ADR"                         ,        3,      5,      282,    "R/W",  0,      1,      0ull,   0},
19921         {"RESERVED_8_63"               ,        8,      56,     282,    "RAZ",  1,      1,      0,      0},
19922         {"RESERVED_0_2"                ,        0,      3,      283,    "RAZ",  1,      1,      0,      0},
19923         {"BASE"                        ,        3,      25,     283,    "R/W",  0,      1,      0ull,   0},
19924         {"RESERVED_28_30"              ,        28,     3,      283,    "RAZ",  1,      1,      0,      0},
19925         {"EN"                          ,        31,     1,      283,    "R/W",  0,      1,      0ull,   0},
19926         {"RESERVED_32_63"              ,        32,     32,     283,    "RAZ",  1,      1,      0,      0},
19927         {"DATA"                        ,        0,      64,     284,    "R/W",  1,      1,      0,      0},
19928         {"BASE"                        ,        0,      16,     285,    "R/W",  0,      1,      0ull,   0},
19929         {"SIZE"                        ,        16,     12,     285,    "R/W",  0,      1,      0ull,   0},
19930         {"RESERVED_28_29"              ,        28,     2,      285,    "RAZ",  1,      1,      0,      0},
19931         {"ORBIT"                       ,        30,     1,      285,    "R/W",  0,      1,      0ull,   0},
19932         {"EN"                          ,        31,     1,      285,    "R/W",  0,      1,      0ull,   0},
19933         {"RESERVED_32_63"              ,        32,     32,     285,    "RAZ",  1,      1,      0,      0},
19934         {"ADR"                         ,        0,      6,      286,    "R/W",  0,      1,      63ull,  0},
19935         {"CE"                          ,        6,      6,      286,    "R/W",  0,      1,      63ull,  0},
19936         {"OE"                          ,        12,     6,      286,    "R/W",  0,      1,      63ull,  0},
19937         {"WE"                          ,        18,     6,      286,    "R/W",  0,      1,      63ull,  0},
19938         {"RD_HLD"                      ,        24,     6,      286,    "R/W",  0,      1,      63ull,  0},
19939         {"WR_HLD"                      ,        30,     6,      286,    "R/W",  0,      1,      63ull,  0},
19940         {"PAUSE"                       ,        36,     6,      286,    "R/W",  0,      1,      63ull,  0},
19941         {"WAIT"                        ,        42,     6,      286,    "R/W",  0,      1,      63ull,  0},
19942         {"PAGE"                        ,        48,     6,      286,    "R/W",  0,      1,      63ull,  0},
19943         {"RESERVED_54_59"              ,        54,     6,      286,    "RAZ",  1,      1,      0,      0},
19944         {"PAGES"                       ,        60,     2,      286,    "R/W",  0,      1,      0ull,   0},
19945         {"WAITM"                       ,        62,     1,      286,    "R/W",  0,      1,      0ull,   0},
19946         {"PAGEM"                       ,        63,     1,      286,    "R/W",  0,      1,      0ull,   0},
19947         {"FIF_THR"                     ,        0,      6,      287,    "R/W",  0,      0,      26ull,  26ull},
19948         {"RESERVED_6_7"                ,        6,      2,      287,    "RAZ",  1,      1,      0,      0},
19949         {"FIF_CNT"                     ,        8,      6,      287,    "RO",   0,      1,      0ull,   0},
19950         {"RESERVED_14_63"              ,        14,     50,     287,    "RAZ",  1,      1,      0,      0},
19951         {"MAN_INFO"                    ,        0,      32,     288,    "RO",   1,      1,      0,      0},
19952         {"RESERVED_32_63"              ,        32,     32,     288,    "RAZ",  1,      1,      0,      0},
19953         {"MAN_INFO"                    ,        0,      32,     289,    "RO",   1,      1,      0,      0},
19954         {"RESERVED_32_63"              ,        32,     32,     289,    "RAZ",  1,      1,      0,      0},
19955         {"PP_DIS"                      ,        0,      16,     290,    "RO",   1,      1,      0,      0},
19956         {"CHIP_ID"                     ,        16,     8,      290,    "RO",   1,      1,      0,      0},
19957         {"BIST_DIS"                    ,        24,     1,      290,    "RO",   1,      1,      0,      0},
19958         {"RST_SHT"                     ,        25,     1,      290,    "RO",   1,      1,      0,      0},
19959         {"NOCRYPTO"                    ,        26,     1,      290,    "RO",   1,      1,      0,      0},
19960         {"NOMUL"                       ,        27,     1,      290,    "RO",   1,      1,      0,      0},
19961         {"NODFA_CP2"                   ,        28,     1,      290,    "RO",   1,      1,      0,      0},
19962         {"RESERVED_29_63"              ,        29,     35,     290,    "RAZ",  1,      1,      0,      0},
19963         {"ICACHE"                      ,        0,      24,     291,    "RO",   1,      1,      0,      0},
19964         {"NODFA_DTE"                   ,        24,     1,      291,    "RO",   1,      1,      0,      0},
19965         {"NOZIP"                       ,        25,     1,      291,    "RO",   1,      1,      0,      0},
19966         {"EFUS_IGN"                    ,        26,     1,      291,    "RO",   1,      1,      0,      0},
19967         {"EFUS_LCK"                    ,        27,     1,      291,    "RO",   1,      1,      0,      0},
19968         {"BAR2_EN"                     ,        28,     1,      291,    "RO",   1,      1,      0,      0},
19969         {"ZIP_CRIP"                    ,        29,     2,      291,    "RO",   1,      1,      0,      0},
19970         {"RESERVED_31_63"              ,        31,     33,     291,    "RAZ",  1,      1,      0,      0},
19971         {"PROG"                        ,        0,      1,      292,    "R/W",  1,      1,      0,      0},
19972         {"RESERVED_1_63"               ,        1,      63,     292,    "RAZ",  1,      1,      0,      0},
19973         {"ADDR"                        ,        0,      7,      293,    "R/W",  0,      0,      0ull,   0ull},
19974         {"RESERVED_7_7"                ,        7,      1,      293,    "RAZ",  1,      1,      0,      0},
19975         {"EFUSE"                       ,        8,      1,      293,    "R/W",  0,      0,      0ull,   0ull},
19976         {"RESERVED_9_11"               ,        9,      3,      293,    "RAZ",  1,      1,      0,      0},
19977         {"PEND"                        ,        12,     1,      293,    "R/W",  0,      0,      0ull,   0ull},
19978         {"RESERVED_13_15"              ,        13,     3,      293,    "RAZ",  1,      1,      0,      0},
19979         {"DAT"                         ,        16,     8,      293,    "RO",   1,      1,      0,      0},
19980         {"RESERVED_24_63"              ,        24,     40,     293,    "RAZ",  1,      1,      0,      0},
19981         {"REPAIR0"                     ,        0,      14,     294,    "RO",   0,      0,      0ull,   0ull},
19982         {"REPAIR1"                     ,        14,     14,     294,    "RO",   0,      0,      0ull,   0ull},
19983         {"REPAIR2"                     ,        28,     14,     294,    "RO",   0,      0,      0ull,   0ull},
19984         {"RESERVED_42_63"              ,        42,     22,     294,    "RAZ",  1,      1,      0,      0},
19985         {"TOO_MANY"                    ,        0,      1,      295,    "RO",   0,      0,      0ull,   0ull},
19986         {"RESERVED_1_63"               ,        1,      63,     295,    "RAZ",  1,      1,      0,      0},
19987         {"ADDR"                        ,        0,      10,     296,    "R/W",  1,      1,      0,      0},
19988         {"RESERVED_10_63"              ,        10,     54,     296,    "RAZ",  1,      1,      0,      0},
19989         {"ST_INT"                      ,        0,      1,      297,    "R/W1C",        0,      1,      0ull,   0},
19990         {"TS_INT"                      ,        1,      1,      297,    "R/W1C",        0,      1,      0ull,   0},
19991         {"CORE_INT"                    ,        2,      1,      297,    "RO",   0,      1,      0ull,   0},
19992         {"RESERVED_3_3"                ,        3,      1,      297,    "RAZ",  1,      1,      0,      0},
19993         {"ST_EN"                       ,        4,      1,      297,    "R/W",  0,      1,      0ull,   0},
19994         {"TS_EN"                       ,        5,      1,      297,    "R/W",  0,      1,      0ull,   0},
19995         {"CORE_EN"                     ,        6,      1,      297,    "R/W",  0,      1,      0ull,   0},
19996         {"RESERVED_7_7"                ,        7,      1,      297,    "RAZ",  1,      1,      0,      0},
19997         {"SDA_OVR"                     ,        8,      1,      297,    "R/W",  0,      1,      0ull,   0},
19998         {"SCL_OVR"                     ,        9,      1,      297,    "R/W",  0,      1,      0ull,   0},
19999         {"SDA"                         ,        10,     1,      297,    "RO",   1,      1,      0,      0},
20000         {"SCL"                         ,        11,     1,      297,    "RO",   1,      1,      0,      0},
20001         {"RESERVED_12_63"              ,        12,     52,     297,    "RAZ",  1,      1,      0,      0},
20002         {"D"                           ,        0,      32,     298,    "R/W",  0,      1,      0ull,   0},
20003         {"EOP_IA"                      ,        32,     3,      298,    "R/W",  0,      1,      0ull,   0},
20004         {"IA"                          ,        35,     5,      298,    "R/W",  0,      1,      0ull,   0},
20005         {"A"                           ,        40,     10,     298,    "R/W",  0,      1,      0ull,   0},
20006         {"SCR"                         ,        50,     2,      298,    "R/W",  0,      1,      0ull,   0},
20007         {"SIZE"                        ,        52,     3,      298,    "R/W",  0,      1,      0ull,   0},
20008         {"SOVR"                        ,        55,     1,      298,    "R/W",  0,      1,      0ull,   0},
20009         {"R"                           ,        56,     1,      298,    "R/W",  0,      1,      0ull,   0},
20010         {"OP"                          ,        57,     4,      298,    "R/W",  0,      1,      0ull,   0},
20011         {"EIA"                         ,        61,     1,      298,    "R/W",  0,      1,      0ull,   0},
20012         {"SLONLY"                      ,        62,     1,      298,    "R/W",  0,      1,      0ull,   0},
20013         {"V"                           ,        63,     1,      298,    "RC/W", 0,      1,      0ull,   0},
20014         {"D"                           ,        0,      32,     299,    "R/W",  0,      1,      0ull,   0},
20015         {"IA"                          ,        32,     8,      299,    "R/W",  0,      1,      0ull,   0},
20016         {"RESERVED_40_63"              ,        40,     24,     299,    "RAZ",  1,      1,      0,      0},
20017         {"D"                           ,        0,      32,     300,    "R/W",  1,      1,      0,      0},
20018         {"RESERVED_32_61"              ,        32,     30,     300,    "RAZ",  1,      1,      0,      0},
20019         {"V"                           ,        62,     2,      300,    "RC/W", 0,      1,      0ull,   0},
20020         {"DLH"                         ,        0,      8,      301,    "R/W",  0,      1,      0ull,   0},
20021         {"RESERVED_8_63"               ,        8,      56,     301,    "RAZ",  1,      1,      0,      0},
20022         {"DLL"                         ,        0,      8,      302,    "R/W",  0,      1,      0ull,   0},
20023         {"RESERVED_8_63"               ,        8,      56,     302,    "RAZ",  1,      1,      0,      0},
20024         {"FAR"                         ,        0,      1,      303,    "R/W",  0,      1,      0ull,   0},
20025         {"RESERVED_1_63"               ,        1,      63,     303,    "RAZ",  1,      1,      0,      0},
20026         {"EN"                          ,        0,      1,      304,    "WO",   0,      1,      0ull,   0},
20027         {"RXFR"                        ,        1,      1,      304,    "WO",   0,      1,      0ull,   0},
20028         {"TXFR"                        ,        2,      1,      304,    "WO",   0,      1,      0ull,   0},
20029         {"RESERVED_3_3"                ,        3,      1,      304,    "RAZ",  0,      1,      0ull,   0},
20030         {"TXTRIG"                      ,        4,      2,      304,    "WO",   0,      1,      0ull,   0},
20031         {"RXTRIG"                      ,        6,      2,      304,    "WO",   0,      1,      0ull,   0},
20032         {"RESERVED_8_63"               ,        8,      56,     304,    "RAZ",  1,      1,      0,      0},
20033         {"HTX"                         ,        0,      1,      305,    "R/W",  0,      1,      0ull,   0},
20034         {"RESERVED_1_63"               ,        1,      63,     305,    "RAZ",  1,      1,      0,      0},
20035         {"ERBFI"                       ,        0,      1,      306,    "R/W",  0,      1,      0ull,   0},
20036         {"ETBEI"                       ,        1,      1,      306,    "R/W",  0,      1,      0ull,   0},
20037         {"ELSI"                        ,        2,      1,      306,    "R/W",  0,      1,      0ull,   0},
20038         {"EDSSI"                       ,        3,      1,      306,    "R/W",  0,      1,      0ull,   0},
20039         {"RESERVED_4_6"                ,        4,      3,      306,    "RAZ",  0,      1,      0ull,   0},
20040         {"PTIME"                       ,        7,      1,      306,    "R/W",  0,      1,      0ull,   0},
20041         {"RESERVED_8_63"               ,        8,      56,     306,    "RAZ",  1,      1,      0,      0},
20042         {"IID"                         ,        0,      4,      307,    "RO",   0,      1,      1ull,   0},
20043         {"RESERVED_4_5"                ,        4,      2,      307,    "RAZ",  0,      1,      0ull,   0},
20044         {"FEN"                         ,        6,      2,      307,    "RO",   0,      1,      0ull,   0},
20045         {"RESERVED_8_63"               ,        8,      56,     307,    "RAZ",  1,      1,      0,      0},
20046         {"CLS"                         ,        0,      2,      308,    "R/W",  0,      1,      0ull,   0},
20047         {"STOP"                        ,        2,      1,      308,    "R/W",  0,      1,      0ull,   0},
20048         {"PEN"                         ,        3,      1,      308,    "R/W",  0,      1,      0ull,   0},
20049         {"EPS"                         ,        4,      1,      308,    "R/W",  0,      1,      0ull,   0},
20050         {"RESERVED_5_5"                ,        5,      1,      308,    "RAZ",  0,      1,      0ull,   0},
20051         {"BRK"                         ,        6,      1,      308,    "R/W",  0,      1,      0ull,   0},
20052         {"DLAB"                        ,        7,      1,      308,    "R/W",  0,      1,      0ull,   0},
20053         {"RESERVED_8_63"               ,        8,      56,     308,    "RAZ",  1,      1,      0,      0},
20054         {"DR"                          ,        0,      1,      309,    "RO",   0,      1,      0ull,   0},
20055         {"OE"                          ,        1,      1,      309,    "RC",   0,      1,      0ull,   0},
20056         {"PE"                          ,        2,      1,      309,    "RC",   0,      1,      0ull,   0},
20057         {"FE"                          ,        3,      1,      309,    "RC",   0,      1,      0ull,   0},
20058         {"BI"                          ,        4,      1,      309,    "RC",   0,      1,      0ull,   0},
20059         {"THRE"                        ,        5,      1,      309,    "RO",   0,      1,      1ull,   0},
20060         {"TEMT"                        ,        6,      1,      309,    "RO",   0,      1,      1ull,   0},
20061         {"FERR"                        ,        7,      1,      309,    "RC",   0,      1,      0ull,   0},
20062         {"RESERVED_8_63"               ,        8,      56,     309,    "RAZ",  1,      1,      0,      0},
20063         {"DTR"                         ,        0,      1,      310,    "R/W",  0,      1,      0ull,   0},
20064         {"RTS"                         ,        1,      1,      310,    "R/W",  0,      1,      0ull,   0},
20065         {"OUT1"                        ,        2,      1,      310,    "R/W",  0,      1,      0ull,   0},
20066         {"OUT2"                        ,        3,      1,      310,    "R/W",  0,      1,      0ull,   0},
20067         {"LOOP"                        ,        4,      1,      310,    "R/W",  0,      1,      0ull,   0},
20068         {"AFCE"                        ,        5,      1,      310,    "R/W",  0,      1,      0ull,   0},
20069         {"RESERVED_6_63"               ,        6,      58,     310,    "RAZ",  0,      1,      0ull,   0},
20070         {"DCTS"                        ,        0,      1,      311,    "RC",   0,      1,      0ull,   0},
20071         {"DDSR"                        ,        1,      1,      311,    "RC",   0,      1,      0ull,   0},
20072         {"TERI"                        ,        2,      1,      311,    "RC",   0,      1,      0ull,   0},
20073         {"DDCD"                        ,        3,      1,      311,    "RC",   0,      1,      0ull,   0},
20074         {"CTS"                         ,        4,      1,      311,    "RO",   1,      1,      0,      0},
20075         {"DSR"                         ,        5,      1,      311,    "RO",   0,      1,      0ull,   0},
20076         {"RI"                          ,        6,      1,      311,    "RO",   0,      1,      0ull,   0},
20077         {"DCD"                         ,        7,      1,      311,    "RO",   0,      1,      0ull,   0},
20078         {"RESERVED_8_63"               ,        8,      56,     311,    "RAZ",  1,      1,      0,      0},
20079         {"RBR"                         ,        0,      8,      312,    "RO",   0,      1,      0ull,   0},
20080         {"RESERVED_8_63"               ,        8,      56,     312,    "RAZ",  1,      1,      0,      0},
20081         {"RFL"                         ,        0,      7,      313,    "RO",   0,      1,      0ull,   0},
20082         {"RESERVED_7_63"               ,        7,      57,     313,    "RAZ",  1,      1,      0,      0},
20083         {"RFWD"                        ,        0,      8,      314,    "WO",   0,      1,      0ull,   0},
20084         {"RFPE"                        ,        8,      1,      314,    "WO",   0,      1,      0ull,   0},
20085         {"RFFE"                        ,        9,      1,      314,    "WO",   0,      1,      0ull,   0},
20086         {"RESERVED_10_63"              ,        10,     54,     314,    "RAZ",  1,      1,      0,      0},
20087         {"SBCR"                        ,        0,      1,      315,    "R/W",  0,      1,      0ull,   0},
20088         {"RESERVED_1_63"               ,        1,      63,     315,    "RAZ",  1,      1,      0,      0},
20089         {"SCR"                         ,        0,      8,      316,    "R/W",  0,      1,      0ull,   0},
20090         {"RESERVED_8_63"               ,        8,      56,     316,    "RAZ",  1,      1,      0,      0},
20091         {"SFE"                         ,        0,      1,      317,    "R/W",  0,      1,      0ull,   0},
20092         {"RESERVED_1_63"               ,        1,      63,     317,    "RAZ",  1,      1,      0,      0},
20093         {"USR"                         ,        0,      1,      318,    "WO",   0,      1,      0ull,   0},
20094         {"SRFR"                        ,        1,      1,      318,    "WO",   0,      1,      0ull,   0},
20095         {"STFR"                        ,        2,      1,      318,    "WO",   0,      1,      0ull,   0},
20096         {"RESERVED_3_63"               ,        3,      61,     318,    "RAZ",  1,      1,      0,      0},
20097         {"SRT"                         ,        0,      2,      319,    "R/W",  0,      1,      0ull,   0},
20098         {"RESERVED_2_63"               ,        2,      62,     319,    "RAZ",  1,      1,      0,      0},
20099         {"SRTS"                        ,        0,      1,      320,    "R/W",  0,      1,      0ull,   0},
20100         {"RESERVED_1_63"               ,        1,      63,     320,    "RAZ",  1,      1,      0,      0},
20101         {"STT"                         ,        0,      2,      321,    "R/W",  0,      1,      0ull,   0},
20102         {"RESERVED_2_63"               ,        2,      62,     321,    "RAZ",  1,      1,      0,      0},
20103         {"TFL"                         ,        0,      7,      322,    "RO",   0,      1,      0ull,   0},
20104         {"RESERVED_7_63"               ,        7,      57,     322,    "RAZ",  1,      1,      0,      0},
20105         {"TFR"                         ,        0,      8,      323,    "RO",   0,      1,      0ull,   0},
20106         {"RESERVED_8_63"               ,        8,      56,     323,    "RAZ",  1,      1,      0,      0},
20107         {"THR"                         ,        0,      8,      324,    "WO",   0,      1,      0ull,   0},
20108         {"RESERVED_8_63"               ,        8,      56,     324,    "RAZ",  1,      1,      0,      0},
20109         {"BUSY"                        ,        0,      1,      325,    "RO",   0,      1,      0ull,   0},
20110         {"TFNF"                        ,        1,      1,      325,    "RO",   0,      1,      1ull,   0},
20111         {"TFE"                         ,        2,      1,      325,    "RO",   0,      1,      1ull,   0},
20112         {"RFNE"                        ,        3,      1,      325,    "RO",   0,      1,      0ull,   0},
20113         {"RFF"                         ,        4,      1,      325,    "RO",   0,      1,      0ull,   0},
20114         {"RESERVED_5_63"               ,        5,      59,     325,    "RAZ",  1,      1,      0,      0},
20115         {"RESERVED_0_2"                ,        0,      3,      326,    "RAZ",  1,      1,      0,      0},
20116         {"BADDR"                       ,        3,      61,     326,    "R/W",  0,      1,      0ull,   0},
20117         {"RESERVED_0_2"                ,        0,      3,      327,    "RAZ",  1,      1,      0,      0},
20118         {"BADDR"                       ,        3,      61,     327,    "R/W",  0,      1,      0ull,   0},
20119         {"DPI_BS"                      ,        0,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20120         {"PDF_BS"                      ,        1,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20121         {"DOB_BS"                      ,        2,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20122         {"NUS_BS"                      ,        3,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20123         {"POS_BS"                      ,        4,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20124         {"POF3_BS"                     ,        5,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20125         {"POF2_BS"                     ,        6,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20126         {"POF1_BS"                     ,        7,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20127         {"POF0_BS"                     ,        8,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20128         {"PIG_BS"                      ,        9,      1,      328,    "RO",   0,      0,      0ull,   0ull},
20129         {"PGF_BS"                      ,        10,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20130         {"RDNL_BS"                     ,        11,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20131         {"PCAD_BS"                     ,        12,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20132         {"PCAC_BS"                     ,        13,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20133         {"RDN_BS"                      ,        14,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20134         {"PCN_BS"                      ,        15,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20135         {"PCNC_BS"                     ,        16,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20136         {"RDP_BS"                      ,        17,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20137         {"DIF_BS"                      ,        18,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20138         {"CSR_BS"                      ,        19,     1,      328,    "RO",   0,      0,      0ull,   0ull},
20139         {"RESERVED_20_63"              ,        20,     44,     328,    "RAZ",  1,      1,      0,      0},
20140         {"BSIZE"                       ,        0,      16,     329,    "R/W",  0,      1,      1024ull,        0},
20141         {"ISIZE"                       ,        16,     7,      329,    "R/W",  0,      1,      0ull,   0},
20142         {"RESERVED_23_63"              ,        23,     41,     329,    "RAZ",  1,      1,      0,      0},
20143         {"TIMER"                       ,        0,      10,     330,    "R/W",  0,      0,      0ull,   50ull},
20144         {"RESERVED_10_31"              ,        10,     22,     330,    "RAZ",  0,      0,      0ull,   0ull},
20145         {"MAX_WORD"                    ,        32,     5,      330,    "R/W",  0,      0,      2ull,   0ull},
20146         {"RESERVED_37_39"              ,        37,     3,      330,    "RAZ",  0,      0,      0ull,   0ull},
20147         {"WAIT_COM"                    ,        40,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20148         {"PCI_WDIS"                    ,        41,     1,      330,    "R/W",  0,      0,      0ull,   0ull},
20149         {"INS0_64B"                    ,        42,     1,      330,    "R/W",  0,      1,      0ull,   0},
20150         {"INS1_64B"                    ,        43,     1,      330,    "R/W",  0,      1,      0ull,   0},
20151         {"INS2_64B"                    ,        44,     1,      330,    "R/W",  0,      1,      0ull,   0},
20152         {"INS3_64B"                    ,        45,     1,      330,    "R/W",  0,      1,      0ull,   0},
20153         {"INS0_ENB"                    ,        46,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20154         {"INS1_ENB"                    ,        47,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20155         {"INS2_ENB"                    ,        48,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20156         {"INS3_ENB"                    ,        49,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20157         {"OUT0_ENB"                    ,        50,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20158         {"OUT1_ENB"                    ,        51,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20159         {"OUT2_ENB"                    ,        52,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20160         {"OUT3_ENB"                    ,        53,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20161         {"DIS_PNIW"                    ,        54,     1,      330,    "R/W",  0,      0,      0ull,   1ull},
20162         {"CHIP_REV"                    ,        55,     8,      330,    "RO",   1,      1,      0,      0},
20163         {"RESERVED_63_63"              ,        63,     1,      330,    "RAZ",  1,      1,      0,      0},
20164         {"DBG_SEL"                     ,        0,      16,     331,    "R/W",  0,      1,      0ull,   0},
20165         {"RESERVED_16_63"              ,        16,     48,     331,    "RAZ",  1,      1,      0,      0},
20166         {"CSIZE"                       ,        0,      14,     332,    "R/W",  0,      1,      0ull,   0},
20167         {"LP_ENB"                      ,        14,     1,      332,    "R/W",  0,      0,      0ull,   1ull},
20168         {"HP_ENB"                      ,        15,     1,      332,    "R/W",  0,      0,      0ull,   1ull},
20169         {"O_MODE"                      ,        16,     1,      332,    "R/W",  0,      0,      0ull,   1ull},
20170         {"O_ES"                        ,        17,     2,      332,    "R/W",  0,      1,      0ull,   0},
20171         {"O_NS"                        ,        19,     1,      332,    "R/W",  0,      1,      0ull,   0},
20172         {"O_RO"                        ,        20,     1,      332,    "R/W",  0,      1,      0ull,   0},
20173         {"O_ADD1"                      ,        21,     1,      332,    "R/W",  0,      0,      0ull,   1ull},
20174         {"FPA_QUE"                     ,        22,     3,      332,    "R/W",  0,      1,      0ull,   0},
20175         {"DWB_ICHK"                    ,        25,     9,      332,    "R/W",  0,      1,      0ull,   0},
20176         {"DWB_DENB"                    ,        34,     1,      332,    "R/W",  0,      0,      0ull,   1ull},
20177         {"B0_LEND"                     ,        35,     1,      332,    "R/W",  0,      0,      0ull,   0ull},
20178         {"RESERVED_36_63"              ,        36,     28,     332,    "RAZ",  1,      1,      0,      0},
20179         {"DBELL"                       ,        0,      32,     333,    "RO",   0,      0,      0ull,   0ull},
20180         {"FCNT"                        ,        32,     7,      333,    "RO",   0,      0,      0ull,   0ull},
20181         {"RESERVED_39_63"              ,        39,     25,     333,    "RAZ",  1,      1,      0,      0},
20182         {"ADDR"                        ,        0,      36,     334,    "RO",   0,      1,      0ull,   0},
20183         {"STATE"                       ,        36,     4,      334,    "RO",   0,      0,      0ull,   0ull},
20184         {"RESERVED_40_63"              ,        40,     24,     334,    "RAZ",  1,      1,      0,      0},
20185         {"DBELL"                       ,        0,      32,     335,    "RO",   0,      0,      0ull,   0ull},
20186         {"FCNT"                        ,        32,     7,      335,    "RO",   0,      0,      0ull,   0ull},
20187         {"RESERVED_39_63"              ,        39,     25,     335,    "RAZ",  1,      1,      0,      0},
20188         {"ADDR"                        ,        0,      36,     336,    "RO",   0,      1,      0ull,   0},
20189         {"STATE"                       ,        36,     4,      336,    "RO",   0,      0,      0ull,   0ull},
20190         {"RESERVED_40_63"              ,        40,     24,     336,    "RAZ",  1,      1,      0,      0},
20191         {"DBELL"                       ,        0,      16,     337,    "R/W",  0,      1,      0ull,   0},
20192         {"RESERVED_16_63"              ,        16,     48,     337,    "RAZ",  1,      1,      0,      0},
20193         {"SADDR"                       ,        0,      36,     338,    "R/W",  0,      1,      0ull,   0},
20194         {"RESERVED_36_63"              ,        36,     28,     338,    "RAZ",  1,      1,      0,      0},
20195         {"ROR"                         ,        0,      1,      339,    "R/W",  0,      1,      0ull,   0},
20196         {"ESR"                         ,        1,      2,      339,    "R/W",  0,      1,      0ull,   0},
20197         {"NSR"                         ,        3,      1,      339,    "R/W",  0,      1,      0ull,   0},
20198         {"USE_CSR"                     ,        4,      1,      339,    "R/W",  0,      0,      0ull,   1ull},
20199         {"D_ROR"                       ,        5,      1,      339,    "R/W",  0,      1,      0ull,   0},
20200         {"D_ESR"                       ,        6,      2,      339,    "R/W",  0,      1,      0ull,   0},
20201         {"D_NSR"                       ,        8,      1,      339,    "R/W",  0,      1,      0ull,   0},
20202         {"PBP_DHI"                     ,        9,      13,     339,    "R/W",  0,      1,      0ull,   0},
20203         {"PKT_RR"                      ,        22,     1,      339,    "R/W",  0,      0,      0ull,   0ull},
20204         {"RESERVED_23_63"              ,        23,     41,     339,    "RAZ",  1,      1,      0,      0},
20205         {"RML_RTO"                     ,        0,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20206         {"RML_WTO"                     ,        1,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20207         {"PCI_RSL"                     ,        2,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20208         {"PO0_2SML"                    ,        3,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20209         {"PO1_2SML"                    ,        4,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20210         {"PO2_2SML"                    ,        5,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20211         {"PO3_2SML"                    ,        6,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20212         {"I0_RTOUT"                    ,        7,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20213         {"I1_RTOUT"                    ,        8,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20214         {"I2_RTOUT"                    ,        9,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
20215         {"I3_RTOUT"                    ,        10,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20216         {"I0_OVERF"                    ,        11,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20217         {"I1_OVERF"                    ,        12,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20218         {"I2_OVERF"                    ,        13,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20219         {"I3_OVERF"                    ,        14,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20220         {"P0_RTOUT"                    ,        15,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20221         {"P1_RTOUT"                    ,        16,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20222         {"P2_RTOUT"                    ,        17,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20223         {"P3_RTOUT"                    ,        18,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20224         {"P0_PERR"                     ,        19,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20225         {"P1_PERR"                     ,        20,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20226         {"P2_PERR"                     ,        21,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20227         {"P3_PERR"                     ,        22,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20228         {"G0_RTOUT"                    ,        23,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20229         {"G1_RTOUT"                    ,        24,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20230         {"G2_RTOUT"                    ,        25,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20231         {"G3_RTOUT"                    ,        26,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20232         {"P0_PPERR"                    ,        27,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20233         {"P1_PPERR"                    ,        28,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20234         {"P2_PPERR"                    ,        29,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20235         {"P3_PPERR"                    ,        30,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20236         {"P0_PTOUT"                    ,        31,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20237         {"P1_PTOUT"                    ,        32,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20238         {"P2_PTOUT"                    ,        33,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20239         {"P3_PTOUT"                    ,        34,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20240         {"I0_PPERR"                    ,        35,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20241         {"I1_PPERR"                    ,        36,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20242         {"I2_PPERR"                    ,        37,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20243         {"I3_PPERR"                    ,        38,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20244         {"WIN_RTO"                     ,        39,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20245         {"P_DPERR"                     ,        40,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20246         {"IOBDMA"                      ,        41,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20247         {"FCR_S_E"                     ,        42,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20248         {"FCR_A_F"                     ,        43,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20249         {"PCR_S_E"                     ,        44,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20250         {"PCR_A_F"                     ,        45,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20251         {"Q2_S_E"                      ,        46,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20252         {"Q2_A_F"                      ,        47,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20253         {"Q3_S_E"                      ,        48,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20254         {"Q3_A_F"                      ,        49,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20255         {"COM_S_E"                     ,        50,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20256         {"COM_A_F"                     ,        51,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20257         {"PNC_S_E"                     ,        52,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20258         {"PNC_A_F"                     ,        53,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20259         {"RWX_S_E"                     ,        54,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20260         {"RDX_S_E"                     ,        55,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20261         {"PCF_P_E"                     ,        56,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20262         {"PCF_P_F"                     ,        57,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20263         {"PDF_P_E"                     ,        58,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20264         {"PDF_P_F"                     ,        59,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20265         {"Q1_S_E"                      ,        60,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20266         {"Q1_A_F"                      ,        61,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
20267         {"RESERVED_62_63"              ,        62,     2,      340,    "RAZ",  1,      1,      0,      0},
20268         {"RML_RTO"                     ,        0,      1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20269         {"RML_WTO"                     ,        1,      1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20270         {"PCI_RSL"                     ,        2,      1,      341,    "RO",   0,      0,      0ull,   0ull},
20271         {"PO0_2SML"                    ,        3,      1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20272         {"PO1_2SML"                    ,        4,      1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20273         {"PO2_2SML"                    ,        5,      1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20274         {"PO3_2SML"                    ,        6,      1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20275         {"I0_RTOUT"                    ,        7,      1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20276         {"I1_RTOUT"                    ,        8,      1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20277         {"I2_RTOUT"                    ,        9,      1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20278         {"I3_RTOUT"                    ,        10,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20279         {"I0_OVERF"                    ,        11,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20280         {"I1_OVERF"                    ,        12,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20281         {"I2_OVERF"                    ,        13,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20282         {"I3_OVERF"                    ,        14,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20283         {"P0_RTOUT"                    ,        15,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20284         {"P1_RTOUT"                    ,        16,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20285         {"P2_RTOUT"                    ,        17,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20286         {"P3_RTOUT"                    ,        18,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20287         {"P0_PERR"                     ,        19,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20288         {"P1_PERR"                     ,        20,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20289         {"P2_PERR"                     ,        21,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20290         {"P3_PERR"                     ,        22,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20291         {"G0_RTOUT"                    ,        23,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20292         {"G1_RTOUT"                    ,        24,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20293         {"G2_RTOUT"                    ,        25,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20294         {"G3_RTOUT"                    ,        26,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20295         {"P0_PPERR"                    ,        27,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20296         {"P1_PPERR"                    ,        28,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20297         {"P2_PPERR"                    ,        29,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20298         {"P3_PPERR"                    ,        30,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20299         {"P0_PTOUT"                    ,        31,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20300         {"P1_PTOUT"                    ,        32,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20301         {"P2_PTOUT"                    ,        33,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20302         {"P3_PTOUT"                    ,        34,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20303         {"I0_PPERR"                    ,        35,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20304         {"I1_PPERR"                    ,        36,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20305         {"I2_PPERR"                    ,        37,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20306         {"I3_PPERR"                    ,        38,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20307         {"WIN_RTO"                     ,        39,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20308         {"P_DPERR"                     ,        40,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20309         {"IOBDMA"                      ,        41,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20310         {"FCR_S_E"                     ,        42,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20311         {"FCR_A_F"                     ,        43,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20312         {"PCR_S_E"                     ,        44,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20313         {"PCR_A_F"                     ,        45,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20314         {"Q2_S_E"                      ,        46,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20315         {"Q2_A_F"                      ,        47,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20316         {"Q3_S_E"                      ,        48,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20317         {"Q3_A_F"                      ,        49,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20318         {"COM_S_E"                     ,        50,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20319         {"COM_A_F"                     ,        51,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20320         {"PNC_S_E"                     ,        52,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20321         {"PNC_A_F"                     ,        53,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20322         {"RWX_S_E"                     ,        54,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20323         {"RDX_S_E"                     ,        55,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20324         {"PCF_P_E"                     ,        56,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20325         {"PCF_P_F"                     ,        57,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20326         {"PDF_P_E"                     ,        58,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20327         {"PDF_P_F"                     ,        59,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20328         {"Q1_S_E"                      ,        60,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20329         {"Q1_A_F"                      ,        61,     1,      341,    "R/W1C",        0,      0,      0ull,   0ull},
20330         {"RESERVED_62_63"              ,        62,     2,      341,    "RAZ",  1,      1,      0,      0},
20331         {"DBELL"                       ,        0,      16,     342,    "R/W",  0,      1,      0ull,   0},
20332         {"RESERVED_16_63"              ,        16,     48,     342,    "RAZ",  1,      1,      0,      0},
20333         {"SADDR"                       ,        0,      36,     343,    "R/W",  0,      1,      0ull,   0},
20334         {"RESERVED_36_63"              ,        36,     28,     343,    "RAZ",  1,      1,      0,      0},
20335         {"BA"                          ,        0,      28,     344,    "R/W",  0,      1,      0ull,   0},
20336         {"ROW"                         ,        28,     1,      344,    "R/W",  0,      1,      0ull,   0},
20337         {"ROR"                         ,        29,     1,      344,    "R/W",  0,      1,      0ull,   0},
20338         {"NSW"                         ,        30,     1,      344,    "R/W",  0,      1,      0ull,   0},
20339         {"NSR"                         ,        31,     1,      344,    "R/W",  0,      1,      0ull,   0},
20340         {"ESW"                         ,        32,     2,      344,    "R/W",  0,      1,      0ull,   0},
20341         {"ESR"                         ,        34,     2,      344,    "R/W",  0,      1,      0ull,   0},
20342         {"NMERGE"                      ,        36,     1,      344,    "R/W",  0,      1,      0ull,   0},
20343         {"SHORTL"                      ,        37,     1,      344,    "R/W",  0,      1,      0ull,   0},
20344         {"RESERVED_38_63"              ,        38,     26,     344,    "RAZ",  1,      1,      0,      0},
20345         {"INT_VEC"                     ,        0,      64,     345,    "R/W1C",        0,      0,      0ull,   0ull},
20346         {"SIZE"                        ,        0,      32,     346,    "R/W",  0,      1,      0ull,   0},
20347         {"RESERVED_32_63"              ,        32,     32,     346,    "RAZ",  1,      1,      0,      0},
20348         {"ROR_SL0"                     ,        0,      1,      347,    "R/W",  0,      1,      0ull,   0},
20349         {"NSR_SL0"                     ,        1,      1,      347,    "R/W",  0,      1,      0ull,   0},
20350         {"ESR_SL0"                     ,        2,      2,      347,    "R/W",  0,      1,      0ull,   0},
20351         {"ROR_SL1"                     ,        4,      1,      347,    "R/W",  0,      1,      0ull,   0},
20352         {"NSR_SL1"                     ,        5,      1,      347,    "R/W",  0,      1,      0ull,   0},
20353         {"ESR_SL1"                     ,        6,      2,      347,    "R/W",  0,      1,      0ull,   0},
20354         {"ROR_SL2"                     ,        8,      1,      347,    "R/W",  0,      1,      0ull,   0},
20355         {"NSR_SL2"                     ,        9,      1,      347,    "R/W",  0,      1,      0ull,   0},
20356         {"ESR_SL2"                     ,        10,     2,      347,    "R/W",  0,      1,      0ull,   0},
20357         {"ROR_SL3"                     ,        12,     1,      347,    "R/W",  0,      1,      0ull,   0},
20358         {"NSR_SL3"                     ,        13,     1,      347,    "R/W",  0,      1,      0ull,   0},
20359         {"ESR_SL3"                     ,        14,     2,      347,    "R/W",  0,      1,      0ull,   0},
20360         {"IPTR_O0"                     ,        16,     1,      347,    "R/W",  0,      0,      0ull,   1ull},
20361         {"IPTR_O1"                     ,        17,     1,      347,    "R/W",  0,      0,      0ull,   1ull},
20362         {"IPTR_O2"                     ,        18,     1,      347,    "R/W",  0,      0,      0ull,   1ull},
20363         {"IPTR_O3"                     ,        19,     1,      347,    "R/W",  0,      0,      0ull,   1ull},
20364         {"RESERVED_20_23"              ,        20,     4,      347,    "RAZ",  0,      0,      0ull,   0ull},
20365         {"O0_CSRM"                     ,        24,     1,      347,    "R/W",  0,      0,      0ull,   1ull},
20366         {"O1_CSRM"                     ,        25,     1,      347,    "R/W",  0,      0,      0ull,   1ull},
20367         {"O2_CSRM"                     ,        26,     1,      347,    "R/W",  0,      0,      0ull,   1ull},
20368         {"O3_CSRM"                     ,        27,     1,      347,    "R/W",  0,      0,      0ull,   1ull},
20369         {"O0_RO"                       ,        28,     1,      347,    "R/W",  0,      1,      0ull,   0},
20370         {"O0_NS"                       ,        29,     1,      347,    "R/W",  0,      1,      0ull,   0},
20371         {"O0_ES"                       ,        30,     2,      347,    "R/W",  0,      1,      0ull,   0},
20372         {"O1_RO"                       ,        32,     1,      347,    "R/W",  0,      1,      0ull,   0},
20373         {"O1_NS"                       ,        33,     1,      347,    "R/W",  0,      1,      0ull,   0},
20374         {"O1_ES"                       ,        34,     2,      347,    "R/W",  0,      1,      0ull,   0},
20375         {"O2_RO"                       ,        36,     1,      347,    "R/W",  0,      1,      0ull,   0},
20376         {"O2_NS"                       ,        37,     1,      347,    "R/W",  0,      1,      0ull,   0},
20377         {"O2_ES"                       ,        38,     2,      347,    "R/W",  0,      1,      0ull,   0},
20378         {"O3_RO"                       ,        40,     1,      347,    "R/W",  0,      1,      0ull,   0},
20379         {"O3_NS"                       ,        41,     1,      347,    "R/W",  0,      1,      0ull,   0},
20380         {"O3_ES"                       ,        42,     2,      347,    "R/W",  0,      1,      0ull,   0},
20381         {"P0_BMODE"                    ,        44,     1,      347,    "R/W",  0,      0,      0ull,   0ull},
20382         {"P1_BMODE"                    ,        45,     1,      347,    "R/W",  0,      0,      0ull,   0ull},
20383         {"P2_BMODE"                    ,        46,     1,      347,    "R/W",  0,      0,      0ull,   0ull},
20384         {"P3_BMODE"                    ,        47,     1,      347,    "R/W",  0,      0,      0ull,   0ull},
20385         {"PKT_RR"                      ,        48,     1,      347,    "R/W",  0,      0,      0ull,   0ull},
20386         {"RESERVED_49_63"              ,        49,     15,     347,    "RAZ",  1,      1,      0,      0},
20387         {"NADDR"                       ,        0,      61,     348,    "RO",   0,      1,      0ull,   0},
20388         {"STATE"                       ,        61,     2,      348,    "RO",   0,      0,      0ull,   0ull},
20389         {"RESERVED_63_63"              ,        63,     1,      348,    "RAZ",  1,      1,      0,      0},
20390         {"NADDR"                       ,        0,      61,     349,    "RO",   0,      1,      0ull,   0},
20391         {"STATE"                       ,        61,     3,      349,    "RO",   0,      0,      0ull,   0ull},
20392         {"AVAIL"                       ,        0,      32,     350,    "RO",   0,      0,      0ull,   0ull},
20393         {"FCNT"                        ,        32,     6,      350,    "RO",   0,      0,      0ull,   0ull},
20394         {"RESERVED_38_63"              ,        38,     26,     350,    "RAZ",  1,      1,      0,      0},
20395         {"AVAIL"                       ,        0,      32,     351,    "RO",   0,      0,      0ull,   0ull},
20396         {"FCNT"                        ,        32,     5,      351,    "RO",   0,      0,      0ull,   0ull},
20397         {"RESERVED_37_63"              ,        37,     27,     351,    "RAZ",  1,      1,      0,      0},
20398         {"RD_BRST"                     ,        0,      7,      352,    "R/W",  0,      0,      17ull,  64ull},
20399         {"WR_BRST"                     ,        7,      7,      352,    "R/W",  0,      0,      16ull,  64ull},
20400         {"RESERVED_14_63"              ,        14,     50,     352,    "RAZ",  1,      1,      0,      0},
20401         {"PARK_DEV"                    ,        0,      3,      353,    "R/W",  0,      1,      0ull,   0},
20402         {"PARK_MOD"                    ,        3,      1,      353,    "R/W",  0,      1,      0ull,   0},
20403         {"EN"                          ,        4,      1,      353,    "R/W",  0,      1,      0ull,   0},
20404         {"RESERVED_5_63"               ,        5,      59,     353,    "RAZ",  1,      1,      0,      0},
20405         {"CMD_SIZE"                    ,        0,      11,     354,    "R/W",  0,      0,      9ull,   9ull},
20406         {"RESERVED_11_63"              ,        11,     53,     354,    "RAZ",  1,      1,      0,      0},
20407         {"RSV_A"                       ,        0,      6,      355,    "R/W",  0,      1,      0ull,   0},
20408         {"SKP_LEN"                     ,        6,      7,      355,    "R/W",  0,      1,      0ull,   0},
20409         {"RSV_B"                       ,        13,     1,      355,    "R/W",  0,      1,      0ull,   0},
20410         {"PAR_MODE"                    ,        14,     2,      355,    "R/W",  0,      1,      0ull,   0},
20411         {"RSV_C"                       ,        16,     5,      355,    "R/W",  0,      1,      0ull,   0},
20412         {"USE_IHDR"                    ,        21,     1,      355,    "R/W",  0,      1,      0ull,   0},
20413         {"RSV_D"                       ,        22,     6,      355,    "R/W",  0,      1,      0ull,   0},
20414         {"RSKP_LEN"                    ,        28,     7,      355,    "R/W",  0,      1,      8ull,   0},
20415         {"RSV_E"                       ,        35,     1,      355,    "R/W",  0,      1,      0ull,   0},
20416         {"RPARMODE"                    ,        36,     2,      355,    "R/W",  0,      1,      0ull,   0},
20417         {"RSV_F"                       ,        38,     5,      355,    "R/W",  0,      1,      0ull,   0},
20418         {"PBP"                         ,        43,     1,      355,    "R/W",  0,      1,      0ull,   0},
20419         {"RESERVED_44_63"              ,        44,     20,     355,    "RAZ",  1,      1,      0,      0},
20420         {"RSV_A"                       ,        0,      6,      356,    "R/W",  0,      1,      0ull,   0},
20421         {"SKP_LEN"                     ,        6,      7,      356,    "R/W",  0,      1,      0ull,   0},
20422         {"RSV_B"                       ,        13,     1,      356,    "R/W",  0,      1,      0ull,   0},
20423         {"PAR_MODE"                    ,        14,     2,      356,    "R/W",  0,      1,      0ull,   0},
20424         {"RSV_C"                       ,        16,     5,      356,    "R/W",  0,      1,      0ull,   0},
20425         {"USE_IHDR"                    ,        21,     1,      356,    "R/W",  0,      1,      0ull,   0},
20426         {"RSV_D"                       ,        22,     6,      356,    "R/W",  0,      1,      0ull,   0},
20427         {"RSKP_LEN"                    ,        28,     7,      356,    "R/W",  0,      1,      8ull,   0},
20428         {"RSV_E"                       ,        35,     1,      356,    "R/W",  0,      1,      0ull,   0},
20429         {"RPARMODE"                    ,        36,     2,      356,    "R/W",  0,      1,      0ull,   0},
20430         {"RSV_F"                       ,        38,     5,      356,    "R/W",  0,      1,      0ull,   0},
20431         {"PBP"                         ,        43,     1,      356,    "R/W",  0,      1,      0ull,   0},
20432         {"RESERVED_44_63"              ,        44,     20,     356,    "RAZ",  1,      1,      0,      0},
20433         {"RSV_A"                       ,        0,      6,      357,    "R/W",  0,      1,      0ull,   0},
20434         {"SKP_LEN"                     ,        6,      7,      357,    "R/W",  0,      1,      0ull,   0},
20435         {"RSV_B"                       ,        13,     1,      357,    "R/W",  0,      1,      0ull,   0},
20436         {"PAR_MODE"                    ,        14,     2,      357,    "R/W",  0,      1,      0ull,   0},
20437         {"RSV_C"                       ,        16,     5,      357,    "R/W",  0,      1,      0ull,   0},
20438         {"USE_IHDR"                    ,        21,     1,      357,    "R/W",  0,      1,      0ull,   0},
20439         {"RSV_D"                       ,        22,     6,      357,    "R/W",  0,      1,      0ull,   0},
20440         {"RSKP_LEN"                    ,        28,     7,      357,    "R/W",  0,      1,      8ull,   0},
20441         {"RSV_E"                       ,        35,     1,      357,    "R/W",  0,      1,      0ull,   0},
20442         {"RPARMODE"                    ,        36,     2,      357,    "R/W",  0,      1,      0ull,   0},
20443         {"RSV_F"                       ,        38,     5,      357,    "R/W",  0,      1,      0ull,   0},
20444         {"PBP"                         ,        43,     1,      357,    "R/W",  0,      1,      0ull,   0},
20445         {"RESERVED_44_63"              ,        44,     20,     357,    "RAZ",  1,      1,      0,      0},
20446         {"RSV_A"                       ,        0,      6,      358,    "R/W",  0,      1,      0ull,   0},
20447         {"SKP_LEN"                     ,        6,      7,      358,    "R/W",  0,      1,      0ull,   0},
20448         {"RSV_B"                       ,        13,     1,      358,    "R/W",  0,      1,      0ull,   0},
20449         {"PAR_MODE"                    ,        14,     2,      358,    "R/W",  0,      1,      0ull,   0},
20450         {"RSV_C"                       ,        16,     5,      358,    "R/W",  0,      1,      0ull,   0},
20451         {"USE_IHDR"                    ,        21,     1,      358,    "R/W",  0,      1,      0ull,   0},
20452         {"RSV_D"                       ,        22,     6,      358,    "R/W",  0,      1,      0ull,   0},
20453         {"RSKP_LEN"                    ,        28,     7,      358,    "R/W",  0,      1,      8ull,   0},
20454         {"RSV_E"                       ,        35,     1,      358,    "R/W",  0,      1,      0ull,   0},
20455         {"RPARMODE"                    ,        36,     2,      358,    "R/W",  0,      1,      0ull,   0},
20456         {"RSV_F"                       ,        38,     5,      358,    "R/W",  0,      1,      0ull,   0},
20457         {"PBP"                         ,        43,     1,      358,    "R/W",  0,      1,      0ull,   0},
20458         {"RESERVED_44_63"              ,        44,     20,     358,    "RAZ",  1,      1,      0,      0},
20459         {"ENB"                         ,        0,      4,      359,    "R/W",  0,      0,      15ull,  15ull},
20460         {"BP_ON"                       ,        4,      4,      359,    "RO",   0,      0,      0ull,   0ull},
20461         {"RESERVED_8_63"               ,        8,      56,     359,    "RAZ",  1,      1,      0,      0},
20462         {"MIO"                         ,        0,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20463         {"GMX0"                        ,        1,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20464         {"GMX1"                        ,        2,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20465         {"NPI"                         ,        3,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20466         {"KEY"                         ,        4,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20467         {"FPA"                         ,        5,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20468         {"DFA"                         ,        6,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20469         {"ZIP"                         ,        7,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20470         {"RINT_8"                      ,        8,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20471         {"IPD"                         ,        9,      1,      360,    "RO",   0,      0,      0ull,   0ull},
20472         {"PKO"                         ,        10,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20473         {"TIM"                         ,        11,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20474         {"POW"                         ,        12,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20475         {"RINT_13"                     ,        13,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20476         {"RINT_14"                     ,        14,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20477         {"RINT_15"                     ,        15,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20478         {"L2C"                         ,        16,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20479         {"LMC"                         ,        17,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20480         {"SPX0"                        ,        18,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20481         {"SPX1"                        ,        19,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20482         {"PIP"                         ,        20,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20483         {"RINT_21"                     ,        21,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20484         {"ASX0"                        ,        22,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20485         {"ASX1"                        ,        23,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20486         {"RINT_24"                     ,        24,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20487         {"RINT_25"                     ,        25,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20488         {"RINT_26"                     ,        26,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20489         {"RINT_27"                     ,        27,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20490         {"RINT_28"                     ,        28,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20491         {"RINT_29"                     ,        29,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20492         {"IOB"                         ,        30,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20493         {"RINT_31"                     ,        31,     1,      360,    "RO",   0,      0,      0ull,   0ull},
20494         {"RESERVED_32_63"              ,        32,     32,     360,    "RAZ",  1,      1,      0,      0},
20495         {"SIZE"                        ,        0,      32,     361,    "R/W",  0,      1,      0ull,   0},
20496         {"RESERVED_32_63"              ,        32,     32,     361,    "RAZ",  1,      1,      0,      0},
20497         {"TIME"                        ,        0,      32,     362,    "R/W",  0,      0,      0ull,   131072ull},
20498         {"RESERVED_32_63"              ,        32,     32,     362,    "RAZ",  1,      1,      0,      0},
20499         {"ADDR_V"                      ,        0,      1,      363,    "R/W",  0,      1,      0ull,   0},
20500         {"END_SWP"                     ,        1,      2,      363,    "R/W",  0,      1,      0ull,   0},
20501         {"CA"                          ,        3,      1,      363,    "R/W",  0,      0,      0ull,   0ull},
20502         {"ADDR_IDX"                    ,        4,      14,     363,    "R/W",  0,      1,      0ull,   0},
20503         {"RESERVED_18_31"              ,        18,     14,     363,    "RAZ",  1,      1,      0,      0},
20504         {"VENDID"                      ,        0,      16,     364,    "RO",   0,      0,      6013ull,        6013ull},
20505         {"DEVID"                       ,        16,     16,     364,    "RO",   0,      0,      5ull,   5ull},
20506         {"ISAE"                        ,        0,      1,      365,    "RO",   0,      0,      0ull,   0ull},
20507         {"MSAE"                        ,        1,      1,      365,    "R/W",  0,      0,      0ull,   1ull},
20508         {"ME"                          ,        2,      1,      365,    "R/W",  0,      0,      0ull,   1ull},
20509         {"SCSE"                        ,        3,      1,      365,    "RO",   0,      0,      0ull,   0ull},
20510         {"MWICE"                       ,        4,      1,      365,    "R/W",  0,      0,      0ull,   0ull},
20511         {"VPS"                         ,        5,      1,      365,    "RO",   0,      0,      0ull,   0ull},
20512         {"PEE"                         ,        6,      1,      365,    "R/W",  0,      0,      0ull,   1ull},
20513         {"ADS"                         ,        7,      1,      365,    "RO",   0,      0,      0ull,   0ull},
20514         {"SEE"                         ,        8,      1,      365,    "R/W",  0,      0,      0ull,   1ull},
20515         {"FBBE"                        ,        9,      1,      365,    "R/W",  0,      0,      0ull,   1ull},
20516         {"I_DIS"                       ,        10,     1,      365,    "R/W",  0,      0,      0ull,   0ull},
20517         {"RESERVED_11_18"              ,        11,     8,      365,    "RAZ",  1,      1,      0,      0},
20518         {"I_STAT"                      ,        19,     1,      365,    "RO",   0,      0,      0ull,   0ull},
20519         {"CLE"                         ,        20,     1,      365,    "RO",   0,      0,      1ull,   1ull},
20520         {"M66"                         ,        21,     1,      365,    "RO",   0,      0,      1ull,   1ull},
20521         {"RESERVED_22_22"              ,        22,     1,      365,    "RAZ",  1,      1,      0,      0},
20522         {"FBB"                         ,        23,     1,      365,    "RO",   0,      1,      1ull,   0},
20523         {"MDPE"                        ,        24,     1,      365,    "R/W1C",        0,      0,      0ull,   0ull},
20524         {"DEVT"                        ,        25,     2,      365,    "RO",   0,      0,      1ull,   1ull},
20525         {"STA"                         ,        27,     1,      365,    "R/W1C",        0,      0,      0ull,   0ull},
20526         {"RTA"                         ,        28,     1,      365,    "R/W1C",        0,      0,      0ull,   0ull},
20527         {"RMA"                         ,        29,     1,      365,    "R/W1C",        0,      0,      0ull,   0ull},
20528         {"SSE"                         ,        30,     1,      365,    "R/W1C",        0,      0,      0ull,   0ull},
20529         {"DPE"                         ,        31,     1,      365,    "R/W1C",        0,      0,      0ull,   0ull},
20530         {"RID"                         ,        0,      8,      366,    "RO",   0,      0,      3ull,   3ull},
20531         {"CC"                          ,        8,      24,     366,    "RO",   0,      0,      733184ull,      733184ull},
20532         {"CLS"                         ,        0,      8,      367,    "R/W",  0,      1,      0ull,   0},
20533         {"LT"                          ,        8,      8,      367,    "R/W",  0,      0,      0ull,   64ull},
20534         {"HT"                          ,        16,     8,      367,    "RO",   0,      0,      0ull,   0ull},
20535         {"BCOD"                        ,        24,     4,      367,    "RO",   0,      0,      0ull,   0ull},
20536         {"RESERVED_28_29"              ,        28,     2,      367,    "RAZ",  1,      1,      0,      0},
20537         {"BRB"                         ,        30,     1,      367,    "R/W",  0,      0,      0ull,   0ull},
20538         {"BCAP"                        ,        31,     1,      367,    "RO",   0,      0,      0ull,   0ull},
20539         {"MSPC"                        ,        0,      1,      368,    "RO",   0,      0,      0ull,   0ull},
20540         {"TYP"                         ,        1,      2,      368,    "RO",   0,      0,      2ull,   2ull},
20541         {"PF"                          ,        3,      1,      368,    "RO",   0,      0,      1ull,   1ull},
20542         {"LBASEZ"                      ,        4,      8,      368,    "RO",   0,      0,      0ull,   0ull},
20543         {"LBASE"                       ,        12,     20,     368,    "R/W",  0,      1,      0ull,   0},
20544         {"HBASE"                       ,        0,      32,     369,    "R/W",  0,      1,      0ull,   0},
20545         {"MSPC"                        ,        0,      1,      370,    "RO",   0,      0,      0ull,   0ull},
20546         {"TYP"                         ,        1,      2,      370,    "RO",   0,      0,      2ull,   2ull},
20547         {"PF"                          ,        3,      1,      370,    "RO",   0,      0,      1ull,   1ull},
20548         {"LBASEZ"                      ,        4,      23,     370,    "RO",   0,      0,      0ull,   0ull},
20549         {"LBASE"                       ,        27,     5,      370,    "R/W",  0,      1,      0ull,   0},
20550         {"HBASE"                       ,        0,      32,     371,    "R/W",  0,      1,      0ull,   0},
20551         {"MSPC"                        ,        0,      1,      372,    "RO",   0,      0,      0ull,   0ull},
20552         {"TYP"                         ,        1,      2,      372,    "RO",   0,      0,      2ull,   2ull},
20553         {"PF"                          ,        3,      1,      372,    "RO",   0,      0,      1ull,   1ull},
20554         {"LBASEZ"                      ,        4,      28,     372,    "RO",   0,      0,      0ull,   0ull},
20555         {"HBASEZ"                      ,        0,      7,      373,    "RO",   0,      0,      0ull,   0ull},
20556         {"HBASE"                       ,        7,      25,     373,    "R/W",  0,      1,      0ull,   0},
20557         {"CISP"                        ,        0,      32,     374,    "RO",   0,      0,      0ull,   0ull},
20558         {"SSVID"                       ,        0,      16,     375,    "RO",   0,      0,      6013ull,        6013ull},
20559         {"SSID"                        ,        16,     16,     375,    "RO",   0,      0,      1ull,   1ull},
20560         {"ERBAR_EN"                    ,        0,      1,      376,    "R/W",  0,      0,      0ull,   0ull},
20561         {"RESERVED_1_10"               ,        1,      10,     376,    "RAZ",  1,      1,      0,      0},
20562         {"ERBARZ"                      ,        11,     5,      376,    "RO",   0,      0,      0ull,   0ull},
20563         {"ERBAR"                       ,        16,     16,     376,    "R/W",  0,      1,      0ull,   0},
20564         {"CP"                          ,        0,      8,      377,    "RO",   0,      0,      224ull, 224ull},
20565         {"RESERVED_8_31"               ,        8,      24,     377,    "RAZ",  1,      1,      0,      0},
20566         {"IL"                          ,        0,      8,      378,    "R/W",  0,      1,      0ull,   0},
20567         {"INTA"                        ,        8,      8,      378,    "RO",   0,      0,      1ull,   1ull},
20568         {"MG"                          ,        16,     8,      378,    "RO",   0,      0,      64ull,  64ull},
20569         {"ML"                          ,        24,     8,      378,    "RO",   0,      0,      64ull,  64ull},
20570         {"MLTD"                        ,        0,      1,      379,    "R/W",  0,      0,      0ull,   1ull},
20571         {"TSWC"                        ,        1,      1,      379,    "R/W",  0,      0,      0ull,   0ull},
20572         {"RESERVED_2_2"                ,        2,      1,      379,    "RAZ",  1,      1,      0,      0},
20573         {"DPPMR"                       ,        3,      1,      379,    "R/W",  0,      0,      0ull,   0ull},
20574         {"PBE"                         ,        4,      12,     379,    "R/W",  0,      0,      0ull,   0ull},
20575         {"TILT"                        ,        16,     4,      379,    "R/W",  0,      0,      0ull,   0ull},
20576         {"TSLTE"                       ,        20,     3,      379,    "R/W",  0,      0,      0ull,   0ull},
20577         {"TMAE"                        ,        23,     1,      379,    "R/W",  0,      0,      0ull,   0ull},
20578         {"TWTAE"                       ,        24,     1,      379,    "R/W",  0,      0,      0ull,   0ull},
20579         {"TWSEN"                       ,        25,     1,      379,    "R/W",  0,      0,      0ull,   0ull},
20580         {"TWSEI"                       ,        26,     1,      379,    "R/W",  0,      0,      0ull,   0ull},
20581         {"TRTAE"                       ,        27,     1,      379,    "R/W",  0,      0,      0ull,   0ull},
20582         {"TRDRS"                       ,        28,     1,      379,    "R/W",  0,      0,      0ull,   0ull},
20583         {"RDSATI"                      ,        29,     1,      379,    "R/W",  0,      0,      0ull,   0ull},
20584         {"TRDARD"                      ,        30,     1,      379,    "R/W1C",        0,      0,      0ull,   0ull},
20585         {"TRDNPR"                      ,        31,     1,      379,    "R/W1C",        0,      0,      0ull,   0ull},
20586         {"TSCME"                       ,        0,      32,     380,    "R/W1C",        0,      1,      0ull,   0},
20587         {"TDSRPS"                      ,        0,      32,     381,    "R/W1C",        0,      0,      0ull,   0ull},
20588         {"TDOMC"                       ,        0,      5,      382,    "R/W",  0,      0,      1ull,   1ull},
20589         {"TIDOMC"                      ,        5,      1,      382,    "R/W",  0,      0,      0ull,   0ull},
20590         {"RESERVED_6_6"                ,        6,      1,      382,    "RAZ",  1,      1,      0,      0},
20591         {"TIBDE"                       ,        7,      1,      382,    "R/W",  0,      0,      0ull,   0ull},
20592         {"TIBCD"                       ,        8,      1,      382,    "R/W1C",        0,      0,      0ull,   0ull},
20593         {"RESERVED_9_10"               ,        9,      2,      382,    "RAZ",  1,      1,      0,      0},
20594         {"TMAPES"                      ,        11,     1,      382,    "R/W1C",        0,      0,      0ull,   0ull},
20595         {"TMDPES"                      ,        12,     1,      382,    "R/W1C",        0,      0,      0ull,   0ull},
20596         {"TMSE"                        ,        13,     1,      382,    "R/W1C",        0,      0,      0ull,   0ull},
20597         {"TMEI"                        ,        14,     1,      382,    "RO",   0,      0,      0ull,   0ull},
20598         {"TECI"                        ,        15,     1,      382,    "RO",   0,      0,      0ull,   0ull},
20599         {"TMES"                        ,        16,     8,      382,    "RO",   0,      0,      0ull,   0ull},
20600         {"MDRRMC"                      ,        24,     3,      382,    "R/W",  0,      0,      2ull,   2ull},
20601         {"MDRIMC"                      ,        27,     1,      382,    "R/W",  0,      0,      0ull,   0ull},
20602         {"MDRE"                        ,        28,     1,      382,    "R/W",  0,      0,      0ull,   0ull},
20603         {"MDWE"                        ,        29,     1,      382,    "R/W",  0,      0,      0ull,   0ull},
20604         {"MRBCI"                       ,        30,     1,      382,    "R/W",  0,      0,      0ull,   0ull},
20605         {"MRBCM"                       ,        31,     1,      382,    "R/W",  0,      0,      1ull,   1ull},
20606         {"MDSP"                        ,        0,      32,     383,    "R/W1C",        0,      1,      0ull,   0},
20607         {"SCMRE"                       ,        0,      32,     384,    "R/W1C",        0,      1,      0ull,   0},
20608         {"MTTV"                        ,        0,      8,      385,    "R/W",  0,      0,      0ull,   0ull},
20609         {"MRV"                         ,        8,      8,      385,    "R/W",  0,      0,      0ull,   255ull},
20610         {"MTTA"                        ,        16,     1,      385,    "R/W1C",        0,      0,      0ull,   0ull},
20611         {"MRA"                         ,        17,     1,      385,    "R/W1C",        0,      0,      0ull,   0ull},
20612         {"FLUSH"                       ,        18,     1,      385,    "R/W",  0,      0,      1ull,   1ull},
20613         {"RESERVED_19_24"              ,        19,     6,      385,    "RAZ",  1,      1,      0,      0},
20614         {"MAC"                         ,        25,     7,      385,    "R/W",  0,      0,      0ull,   0ull},
20615         {"PXCID"                       ,        0,      8,      386,    "RO",   0,      0,      7ull,   7ull},
20616         {"NCP"                         ,        8,      8,      386,    "RO",   0,      0,      232ull, 232ull},
20617         {"DPERE"                       ,        16,     1,      386,    "R/W",  0,      0,      0ull,   0ull},
20618         {"ROE"                         ,        17,     1,      386,    "R/W",  0,      0,      1ull,   1ull},
20619         {"MMBC"                        ,        18,     2,      386,    "R/W",  0,      0,      0ull,   0ull},
20620         {"MOST"                        ,        20,     3,      386,    "R/W",  0,      0,      3ull,   3ull},
20621         {"RESERVED_23_31"              ,        23,     9,      386,    "RAZ",  1,      1,      0,      0},
20622         {"FN"                          ,        0,      3,      387,    "RO",   0,      0,      0ull,   0ull},
20623         {"DN"                          ,        3,      5,      387,    "RO",   0,      0,      31ull,  31ull},
20624         {"BN"                          ,        8,      8,      387,    "RO",   0,      1,      17ull,  0},
20625         {"W64"                         ,        16,     1,      387,    "RO",   0,      0,      1ull,   1ull},
20626         {"M133"                        ,        17,     1,      387,    "RO",   0,      0,      1ull,   1ull},
20627         {"SCD"                         ,        18,     1,      387,    "R/W1C",        0,      1,      0ull,   0},
20628         {"USC"                         ,        19,     1,      387,    "R/W1C",        0,      1,      0ull,   0},
20629         {"DC"                          ,        20,     1,      387,    "RO",   0,      0,      0ull,   0ull},
20630         {"MMRBCD"                      ,        21,     2,      387,    "RO",   0,      0,      2ull,   2ull},
20631         {"MOSTD"                       ,        23,     3,      387,    "RO",   0,      0,      3ull,   3ull},
20632         {"MCRSD"                       ,        26,     3,      387,    "RO",   0,      0,      7ull,   7ull},
20633         {"SCEMR"                       ,        29,     1,      387,    "R/W1C",        0,      1,      0ull,   0},
20634         {"RESERVED_30_31"              ,        30,     2,      387,    "RAZ",  1,      1,      0,      0},
20635         {"PMCID"                       ,        0,      8,      388,    "RO",   0,      0,      1ull,   1ull},
20636         {"NCP"                         ,        8,      8,      388,    "RO",   0,      0,      240ull, 240ull},
20637         {"PCIMIV"                      ,        16,     3,      388,    "RO",   0,      0,      2ull,   2ull},
20638         {"PMEC"                        ,        19,     1,      388,    "RO",   0,      0,      0ull,   0ull},
20639         {"RESERVED_20_20"              ,        20,     1,      388,    "RAZ",  1,      1,      0,      0},
20640         {"DSI"                         ,        21,     1,      388,    "RO",   0,      0,      0ull,   0ull},
20641         {"AUXC"                        ,        22,     3,      388,    "RO",   0,      0,      0ull,   0ull},
20642         {"D1S"                         ,        25,     1,      388,    "RO",   0,      0,      0ull,   0ull},
20643         {"D2S"                         ,        26,     1,      388,    "RO",   0,      0,      0ull,   0ull},
20644         {"PMES"                        ,        27,     5,      388,    "RO",   0,      0,      0ull,   0ull},
20645         {"PS"                          ,        0,      2,      389,    "R/W",  0,      0,      0ull,   0ull},
20646         {"RESERVED_2_7"                ,        2,      6,      389,    "RAZ",  1,      1,      0,      0},
20647         {"PMEENS"                      ,        8,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
20648         {"PMDS"                        ,        9,      4,      389,    "R/W",  0,      0,      0ull,   0ull},
20649         {"PMEDSIA"                     ,        13,     2,      389,    "RO",   0,      0,      0ull,   0ull},
20650         {"PMESS"                       ,        15,     1,      389,    "R/W1C",        0,      0,      0ull,   0ull},
20651         {"RESERVED_16_21"              ,        16,     6,      389,    "RAZ",  1,      1,      0,      0},
20652         {"BD3H"                        ,        22,     1,      389,    "RO",   0,      0,      0ull,   0ull},
20653         {"BPCCEN"                      ,        23,     1,      389,    "RO",   0,      0,      0ull,   0ull},
20654         {"PMDIA"                       ,        24,     8,      389,    "RO",   0,      0,      0ull,   0ull},
20655         {"MSICID"                      ,        0,      8,      390,    "RO",   0,      0,      5ull,   5ull},
20656         {"NCP"                         ,        8,      8,      390,    "RO",   0,      0,      0ull,   0ull},
20657         {"MSIEN"                       ,        16,     1,      390,    "R/W",  0,      0,      0ull,   0ull},
20658         {"MMC"                         ,        17,     3,      390,    "RO",   0,      0,      0ull,   0ull},
20659         {"MME"                         ,        20,     3,      390,    "R/W",  0,      0,      0ull,   0ull},
20660         {"M64"                         ,        23,     1,      390,    "RO",   0,      0,      1ull,   1ull},
20661         {"RESERVED_24_31"              ,        24,     8,      390,    "RAZ",  1,      1,      0,      0},
20662         {"RESERVED_0_1"                ,        0,      2,      391,    "RAZ",  1,      1,      0,      0},
20663         {"MSI31T2"                     ,        2,      30,     391,    "R/W",  0,      1,      0ull,   0},
20664         {"MSI"                         ,        0,      32,     392,    "R/W",  0,      1,      0ull,   0},
20665         {"MSIMD"                       ,        0,      16,     393,    "R/W",  0,      1,      0ull,   0},
20666         {"RESERVED_16_31"              ,        16,     16,     393,    "RAZ",  1,      1,      0,      0},
20667         {"BAR2_CAX"                    ,        0,      1,      394,    "R/W",  0,      0,      0ull,   0ull},
20668         {"BAR2_ESX"                    ,        1,      2,      394,    "R/W",  0,      1,      0ull,   0},
20669         {"BAR2_ENB"                    ,        3,      1,      394,    "R/W",  0,      0,      0ull,   1ull},
20670         {"TSR_HWM"                     ,        4,      3,      394,    "R/W",  0,      1,      1ull,   0},
20671         {"PMO_FPC"                     ,        7,      3,      394,    "R/W",  0,      0,      0ull,   0ull},
20672         {"PMO_AMOD"                    ,        10,     1,      394,    "R/W",  0,      0,      0ull,   0ull},
20673         {"B12_BIST"                    ,        11,     1,      394,    "RO",   0,      0,      0ull,   0ull},
20674         {"AP_64AD"                     ,        12,     1,      394,    "RO",   1,      1,      0,      0},
20675         {"AP_PCIX"                     ,        13,     1,      394,    "RO",   1,      1,      0,      0},
20676         {"RESERVED_14_14"              ,        14,     1,      394,    "RAZ",  0,      0,      0ull,   0ull},
20677         {"EN_WFILT"                    ,        15,     1,      394,    "R/W",  0,      0,      0ull,   1ull},
20678         {"SCM"                         ,        16,     1,      394,    "RO",   0,      1,      0ull,   0},
20679         {"SCMTYP"                      ,        17,     1,      394,    "RO",   0,      1,      0ull,   0},
20680         {"BAR2PRES"                    ,        18,     1,      394,    "R/W",  1,      1,      0,      0},
20681         {"ERST_N"                      ,        19,     1,      394,    "RO",   0,      0,      1ull,   1ull},
20682         {"BB0"                         ,        20,     1,      394,    "R/W",  0,      0,      0ull,   0ull},
20683         {"BB1"                         ,        21,     1,      394,    "R/W",  0,      0,      0ull,   0ull},
20684         {"BB_ES"                       ,        22,     2,      394,    "R/W",  0,      0,      0ull,   0ull},
20685         {"BB_CA"                       ,        24,     1,      394,    "R/W",  0,      0,      0ull,   0ull},
20686         {"BB1_SIZ"                     ,        25,     1,      394,    "R/W",  0,      0,      0ull,   0ull},
20687         {"BB1_HOLE"                    ,        26,     3,      394,    "R/W",  0,      0,      0ull,   0ull},
20688         {"RESERVED_29_31"              ,        29,     3,      394,    "RAZ",  1,      1,      0,      0},
20689         {"INC_VAL"                     ,        0,      16,     395,    "R/W",  0,      1,      0ull,   0},
20690         {"RESERVED_16_31"              ,        16,     16,     395,    "RAZ",  1,      1,      0,      0},
20691         {"DMA_CNT"                     ,        0,      32,     396,    "R/W",  0,      0,      0ull,   0ull},
20692         {"PKT_CNT"                     ,        0,      32,     397,    "R/W",  0,      1,      0ull,   0},
20693         {"DMA_TIME"                    ,        0,      32,     398,    "R/W",  0,      1,      0ull,   0},
20694         {"ICNT"                        ,        0,      32,     399,    "R/W1C",        0,      0,      0ull,   0ull},
20695         {"ITR_WABT"                    ,        0,      1,      400,    "R/W",  0,      1,      0ull,   0},
20696         {"IMR_WABT"                    ,        1,      1,      400,    "R/W",  0,      1,      0ull,   0},
20697         {"IMR_WTTO"                    ,        2,      1,      400,    "R/W",  0,      1,      0ull,   0},
20698         {"ITR_ABT"                     ,        3,      1,      400,    "R/W",  0,      1,      0ull,   0},
20699         {"IMR_ABT"                     ,        4,      1,      400,    "R/W",  0,      1,      0ull,   0},
20700         {"IMR_TTO"                     ,        5,      1,      400,    "R/W",  0,      1,      0ull,   0},
20701         {"IMSI_PER"                    ,        6,      1,      400,    "R/W",  0,      1,      0ull,   0},
20702         {"IMSI_TABT"                   ,        7,      1,      400,    "R/W",  0,      1,      0ull,   0},
20703         {"IMSI_MABT"                   ,        8,      1,      400,    "R/W",  0,      1,      0ull,   0},
20704         {"IMSC_MSG"                    ,        9,      1,      400,    "R/W",  0,      1,      0ull,   0},
20705         {"ITSR_ABT"                    ,        10,     1,      400,    "R/W",  0,      1,      0ull,   0},
20706         {"ISERR"                       ,        11,     1,      400,    "R/W",  0,      1,      0ull,   0},
20707         {"IAPERR"                      ,        12,     1,      400,    "R/W",  0,      1,      0ull,   0},
20708         {"IDPERR"                      ,        13,     1,      400,    "R/W",  0,      1,      0ull,   0},
20709         {"ILL_RWR"                     ,        14,     1,      400,    "R/W",  0,      1,      0ull,   0},
20710         {"ILL_RRD"                     ,        15,     1,      400,    "R/W",  0,      1,      0ull,   0},
20711         {"IRSL_INT"                    ,        16,     1,      400,    "R/W",  0,      1,      0ull,   0},
20712         {"IPCNT0"                      ,        17,     1,      400,    "R/W",  0,      1,      0ull,   0},
20713         {"IPCNT1"                      ,        18,     1,      400,    "R/W",  0,      1,      0ull,   0},
20714         {"IPCNT2"                      ,        19,     1,      400,    "R/W",  0,      1,      0ull,   0},
20715         {"IPCNT3"                      ,        20,     1,      400,    "R/W",  0,      1,      0ull,   0},
20716         {"IPTIME0"                     ,        21,     1,      400,    "R/W",  0,      1,      0ull,   0},
20717         {"IPTIME1"                     ,        22,     1,      400,    "R/W",  0,      1,      0ull,   0},
20718         {"IPTIME2"                     ,        23,     1,      400,    "R/W",  0,      1,      0ull,   0},
20719         {"IPTIME3"                     ,        24,     1,      400,    "R/W",  0,      1,      0ull,   0},
20720         {"IDCNT0"                      ,        25,     1,      400,    "R/W",  0,      1,      0ull,   0},
20721         {"IDCNT1"                      ,        26,     1,      400,    "R/W",  0,      1,      0ull,   0},
20722         {"IDTIME0"                     ,        27,     1,      400,    "R/W",  0,      1,      0ull,   0},
20723         {"IDTIME1"                     ,        28,     1,      400,    "R/W",  0,      1,      0ull,   0},
20724         {"DMA0_FI"                     ,        29,     1,      400,    "R/W",  0,      1,      0ull,   0},
20725         {"DMA1_FI"                     ,        30,     1,      400,    "R/W",  0,      1,      0ull,   0},
20726         {"WIN_WR"                      ,        31,     1,      400,    "R/W",  0,      1,      0ull,   0},
20727         {"ILL_WR"                      ,        32,     1,      400,    "R/W",  0,      1,      0ull,   0},
20728         {"ILL_RD"                      ,        33,     1,      400,    "R/W",  0,      1,      0ull,   0},
20729         {"RESERVED_34_63"              ,        34,     30,     400,    "RAZ",  1,      1,      0,      0},
20730         {"RTR_WABT"                    ,        0,      1,      401,    "R/W",  0,      1,      0ull,   0},
20731         {"RMR_WABT"                    ,        1,      1,      401,    "R/W",  0,      1,      0ull,   0},
20732         {"RMR_WTTO"                    ,        2,      1,      401,    "R/W",  0,      1,      0ull,   0},
20733         {"RTR_ABT"                     ,        3,      1,      401,    "R/W",  0,      1,      0ull,   0},
20734         {"RMR_ABT"                     ,        4,      1,      401,    "R/W",  0,      1,      0ull,   0},
20735         {"RMR_TTO"                     ,        5,      1,      401,    "R/W",  0,      1,      0ull,   0},
20736         {"RMSI_PER"                    ,        6,      1,      401,    "R/W",  0,      1,      0ull,   0},
20737         {"RMSI_TABT"                   ,        7,      1,      401,    "R/W",  0,      1,      0ull,   0},
20738         {"RMSI_MABT"                   ,        8,      1,      401,    "R/W",  0,      1,      0ull,   0},
20739         {"RMSC_MSG"                    ,        9,      1,      401,    "R/W",  0,      1,      0ull,   0},
20740         {"RTSR_ABT"                    ,        10,     1,      401,    "R/W",  0,      1,      0ull,   0},
20741         {"RSERR"                       ,        11,     1,      401,    "R/W",  0,      1,      0ull,   0},
20742         {"RAPERR"                      ,        12,     1,      401,    "R/W",  0,      1,      0ull,   0},
20743         {"RDPERR"                      ,        13,     1,      401,    "R/W",  0,      1,      0ull,   0},
20744         {"ILL_RWR"                     ,        14,     1,      401,    "R/W",  0,      1,      0ull,   0},
20745         {"ILL_RRD"                     ,        15,     1,      401,    "R/W",  0,      1,      0ull,   0},
20746         {"RRSL_INT"                    ,        16,     1,      401,    "R/W",  0,      1,      0ull,   0},
20747         {"RPCNT0"                      ,        17,     1,      401,    "R/W",  0,      1,      0ull,   0},
20748         {"RPCNT1"                      ,        18,     1,      401,    "R/W",  0,      1,      0ull,   0},
20749         {"RPCNT2"                      ,        19,     1,      401,    "R/W",  0,      1,      0ull,   0},
20750         {"RPCNT3"                      ,        20,     1,      401,    "R/W",  0,      1,      0ull,   0},
20751         {"RPTIME0"                     ,        21,     1,      401,    "R/W",  0,      1,      0ull,   0},
20752         {"RPTIME1"                     ,        22,     1,      401,    "R/W",  0,      1,      0ull,   0},
20753         {"RPTIME2"                     ,        23,     1,      401,    "R/W",  0,      1,      0ull,   0},
20754         {"RPTIME3"                     ,        24,     1,      401,    "R/W",  0,      1,      0ull,   0},
20755         {"RDCNT0"                      ,        25,     1,      401,    "R/W",  0,      1,      0ull,   0},
20756         {"RDCNT1"                      ,        26,     1,      401,    "R/W",  0,      1,      0ull,   0},
20757         {"RDTIME0"                     ,        27,     1,      401,    "R/W",  0,      1,      0ull,   0},
20758         {"RDTIME1"                     ,        28,     1,      401,    "R/W",  0,      1,      0ull,   0},
20759         {"DMA0_FI"                     ,        29,     1,      401,    "R/W",  0,      1,      0ull,   0},
20760         {"DMA1_FI"                     ,        30,     1,      401,    "R/W",  0,      1,      0ull,   0},
20761         {"WIN_WR"                      ,        31,     1,      401,    "R/W",  0,      1,      0ull,   0},
20762         {"ILL_WR"                      ,        32,     1,      401,    "R/W",  0,      1,      0ull,   0},
20763         {"ILL_RD"                      ,        33,     1,      401,    "R/W",  0,      1,      0ull,   0},
20764         {"RESERVED_34_63"              ,        34,     30,     401,    "RAZ",  1,      1,      0,      0},
20765         {"TR_WABT"                     ,        0,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20766         {"MR_WABT"                     ,        1,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20767         {"MR_WTTO"                     ,        2,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20768         {"TR_ABT"                      ,        3,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20769         {"MR_ABT"                      ,        4,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20770         {"MR_TTO"                      ,        5,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20771         {"MSI_PER"                     ,        6,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20772         {"MSI_TABT"                    ,        7,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20773         {"MSI_MABT"                    ,        8,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20774         {"MSC_MSG"                     ,        9,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20775         {"TSR_ABT"                     ,        10,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20776         {"SERR"                        ,        11,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20777         {"APERR"                       ,        12,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20778         {"DPERR"                       ,        13,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20779         {"ILL_RWR"                     ,        14,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20780         {"ILL_RRD"                     ,        15,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20781         {"RSL_INT"                     ,        16,     1,      402,    "RO",   0,      0,      0ull,   0ull},
20782         {"PCNT0"                       ,        17,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20783         {"PCNT1"                       ,        18,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20784         {"PCNT2"                       ,        19,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20785         {"PCNT3"                       ,        20,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20786         {"PTIME0"                      ,        21,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20787         {"PTIME1"                      ,        22,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20788         {"PTIME2"                      ,        23,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20789         {"PTIME3"                      ,        24,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20790         {"DCNT0"                       ,        25,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20791         {"DCNT1"                       ,        26,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20792         {"DTIME0"                      ,        27,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20793         {"DTIME1"                      ,        28,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20794         {"DMA0_FI"                     ,        29,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20795         {"DMA1_FI"                     ,        30,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20796         {"WIN_WR"                      ,        31,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20797         {"ILL_WR"                      ,        32,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20798         {"ILL_RD"                      ,        33,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
20799         {"RESERVED_34_63"              ,        34,     30,     402,    "RAZ",  1,      1,      0,      0},
20800         {"TR_WABT"                     ,        0,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20801         {"MR_WABT"                     ,        1,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20802         {"MR_WTTO"                     ,        2,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20803         {"TR_ABT"                      ,        3,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20804         {"MR_ABT"                      ,        4,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20805         {"MR_TTO"                      ,        5,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20806         {"MSI_PER"                     ,        6,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20807         {"MSI_TABT"                    ,        7,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20808         {"MSI_MABT"                    ,        8,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20809         {"MSC_MSG"                     ,        9,      1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20810         {"TSR_ABT"                     ,        10,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20811         {"SERR"                        ,        11,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20812         {"APERR"                       ,        12,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20813         {"DPERR"                       ,        13,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20814         {"ILL_RWR"                     ,        14,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20815         {"ILL_RRD"                     ,        15,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20816         {"RSL_INT"                     ,        16,     1,      403,    "RO",   0,      0,      0ull,   0ull},
20817         {"PCNT0"                       ,        17,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20818         {"PCNT1"                       ,        18,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20819         {"PCNT2"                       ,        19,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20820         {"PCNT3"                       ,        20,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20821         {"PTIME0"                      ,        21,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20822         {"PTIME1"                      ,        22,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20823         {"PTIME2"                      ,        23,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20824         {"PTIME3"                      ,        24,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20825         {"DCNT0"                       ,        25,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20826         {"DCNT1"                       ,        26,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20827         {"DTIME0"                      ,        27,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20828         {"DTIME1"                      ,        28,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20829         {"DMA0_FI"                     ,        29,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20830         {"DMA1_FI"                     ,        30,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20831         {"WIN_WR"                      ,        31,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20832         {"ILL_WR"                      ,        32,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20833         {"ILL_RD"                      ,        33,     1,      403,    "R/W1C",        0,      0,      0ull,   0ull},
20834         {"RESERVED_34_63"              ,        34,     30,     403,    "RAZ",  1,      1,      0,      0},
20835         {"INTR"                        ,        0,      6,      404,    "WO",   0,      1,      0ull,   0},
20836         {"RESERVED_6_31"               ,        6,      26,     404,    "R/W",  1,      1,      0,      0},
20837         {"PTR_CNT"                     ,        0,      16,     405,    "R/W",  0,      1,      0ull,   0},
20838         {"PKT_CNT"                     ,        16,     16,     405,    "R/W",  0,      1,      0ull,   0},
20839         {"PKT_CNT"                     ,        0,      32,     406,    "RO",   0,      0,      0ull,   0ull},
20840         {"PKT_CNT"                     ,        0,      32,     407,    "R/W",  0,      1,      0ull,   0},
20841         {"PKT_TIME"                    ,        0,      32,     408,    "R/W",  0,      1,      0ull,   0},
20842         {"PREFETCH"                    ,        0,      3,      409,    "R/W",  0,      0,      0ull,   2ull},
20843         {"MIN_DATA"                    ,        3,      6,      409,    "R/W",  0,      0,      0ull,   4ull},
20844         {"RESERVED_9_31"               ,        9,      23,     409,    "RAZ",  1,      1,      0,      0},
20845         {"PREFETCH"                    ,        0,      3,      410,    "R/W",  0,      0,      0ull,   3ull},
20846         {"MIN_DATA"                    ,        3,      6,      410,    "R/W",  0,      0,      0ull,   6ull},
20847         {"RESERVED_9_31"               ,        9,      23,     410,    "RAZ",  1,      1,      0,      0},
20848         {"PREFETCH"                    ,        0,      3,      411,    "R/W",  0,      0,      0ull,   3ull},
20849         {"MIN_DATA"                    ,        3,      6,      411,    "R/W",  0,      0,      0ull,   6ull},
20850         {"RESERVED_9_31"               ,        9,      23,     411,    "RAZ",  1,      1,      0,      0},
20851         {"CNT"                         ,        0,      31,     412,    "R/W",  0,      0,      10000ull,       10000ull},
20852         {"ENB"                         ,        31,     1,      412,    "R/W",  0,      0,      0ull,   1ull},
20853         {"RESERVED_32_63"              ,        32,     32,     412,    "RAZ",  1,      1,      0,      0},
20854         {"SCM"                         ,        0,      32,     413,    "RO",   0,      1,      0ull,   0},
20855         {"RESERVED_32_63"              ,        32,     32,     413,    "RAZ",  1,      1,      0,      0},
20856         {"TSR"                         ,        0,      36,     414,    "RO",   0,      1,      0ull,   0},
20857         {"RESERVED_36_63"              ,        36,     28,     414,    "RAZ",  1,      1,      0,      0},
20858         {"RESERVED_0_2"                ,        0,      3,      415,    "RAZ",  1,      1,      0,      0},
20859         {"RD_ADDR"                     ,        3,      45,     415,    "R/W",  0,      1,      0ull,   0},
20860         {"IOBIT"                       ,        48,     1,      415,    "RAZ",  0,      0,      0ull,   0ull},
20861         {"RESERVED_49_63"              ,        49,     15,     415,    "RAZ",  1,      1,      0,      0},
20862         {"RD_DATA"                     ,        0,      64,     416,    "RO",   0,      1,      0ull,   0},
20863         {"RESERVED_0_2"                ,        0,      3,      417,    "RAZ",  1,      1,      0,      0},
20864         {"WR_ADDR"                     ,        3,      45,     417,    "R/W",  0,      1,      0ull,   0},
20865         {"IOBIT"                       ,        48,     1,      417,    "RAZ",  0,      0,      0ull,   0ull},
20866         {"RESERVED_49_63"              ,        49,     15,     417,    "RAZ",  1,      1,      0,      0},
20867         {"WR_DATA"                     ,        0,      64,     418,    "R/W",  0,      1,      0ull,   0},
20868         {"WR_MASK"                     ,        0,      8,      419,    "R/W",  0,      0,      0ull,   0ull},
20869         {"RESERVED_8_63"               ,        8,      56,     419,    "RAZ",  1,      1,      0,      0},
20870         {"LOWATER"                     ,        0,      5,      420,    "R/W",  0,      0,      4ull,   4ull},
20871         {"RESERVED_5_7"                ,        5,      3,      420,    "RAZ",  0,      1,      0ull,   0},
20872         {"HIWATER"                     ,        8,      5,      420,    "R/W",  0,      0,      24ull,  24ull},
20873         {"RESERVED_13_62"              ,        13,     50,     420,    "RAZ",  0,      1,      0ull,   0},
20874         {"BCKPRS"                      ,        63,     1,      420,    "RO",   0,      0,      0ull,   0ull},
20875         {"BIST"                        ,        0,      18,     421,    "RO",   0,      0,      0ull,   0ull},
20876         {"RESERVED_18_63"              ,        18,     46,     421,    "RAZ",  1,      1,      0,      0},
20877         {"REFLECT"                     ,        0,      1,      422,    "R/W",  0,      0,      1ull,   1ull},
20878         {"INVRES"                      ,        1,      1,      422,    "R/W",  0,      0,      1ull,   1ull},
20879         {"RESERVED_2_63"               ,        2,      62,     422,    "RAZ",  1,      1,      0,      0},
20880         {"IV"                          ,        0,      32,     423,    "R/W",  0,      0,      1185899593ull,  1185899593ull},
20881         {"RESERVED_32_63"              ,        32,     32,     423,    "RAZ",  1,      1,      0,      0},
20882         {"DPRT"                        ,        0,      16,     424,    "R/W",  0,      0,      0ull,   0ull},
20883         {"UDP"                         ,        16,     1,      424,    "R/W",  0,      0,      0ull,   0ull},
20884         {"TCP"                         ,        17,     1,      424,    "R/W",  0,      0,      0ull,   0ull},
20885         {"RESERVED_18_63"              ,        18,     46,     424,    "RAZ",  1,      1,      0,      0},
20886         {"NIP_SHF"                     ,        0,      3,      425,    "R/W",  0,      0,      0ull,   0ull},
20887         {"RESERVED_3_7"                ,        3,      5,      425,    "RAZ",  1,      1,      0,      0},
20888         {"RAW_SHF"                     ,        8,      3,      425,    "R/W",  0,      0,      0ull,   0ull},
20889         {"RESERVED_11_15"              ,        11,     5,      425,    "RAZ",  1,      1,      0,      0},
20890         {"MAX_L2"                      ,        16,     1,      425,    "R/W",  0,      0,      0ull,   0ull},
20891         {"IP6_UDP"                     ,        17,     1,      425,    "R/W",  0,      0,      1ull,   1ull},
20892         {"TAG_SYN"                     ,        18,     1,      425,    "R/W",  0,      0,      0ull,   0ull},
20893         {"RESERVED_19_63"              ,        19,     45,     425,    "RAZ",  1,      1,      0,      0},
20894         {"IP_CHK"                      ,        0,      1,      426,    "R/W",  0,      0,      1ull,   1ull},
20895         {"IP_MAL"                      ,        1,      1,      426,    "R/W",  0,      0,      1ull,   1ull},
20896         {"IP_HOP"                      ,        2,      1,      426,    "R/W",  0,      0,      1ull,   1ull},
20897         {"IP4_OPTS"                    ,        3,      1,      426,    "R/W",  0,      0,      1ull,   1ull},
20898         {"IP6_EEXT"                    ,        4,      2,      426,    "R/W",  0,      0,      1ull,   3ull},
20899         {"RESERVED_6_7"                ,        6,      2,      426,    "RAZ",  0,      1,      0ull,   0},
20900         {"L4_MAL"                      ,        8,      1,      426,    "R/W",  0,      0,      1ull,   1ull},
20901         {"L4_PRT"                      ,        9,      1,      426,    "R/W",  0,      0,      1ull,   1ull},
20902         {"L4_CHK"                      ,        10,     1,      426,    "R/W",  0,      0,      1ull,   1ull},
20903         {"L4_LEN"                      ,        11,     1,      426,    "R/W",  0,      0,      1ull,   1ull},
20904         {"TCP_FLAG"                    ,        12,     1,      426,    "R/W",  0,      0,      1ull,   1ull},
20905         {"L2_MAL"                      ,        13,     1,      426,    "R/W",  0,      0,      1ull,   1ull},
20906         {"VS_QOS"                      ,        14,     1,      426,    "R/W",  0,      0,      0ull,   0ull},
20907         {"VS_WQE"                      ,        15,     1,      426,    "R/W",  0,      0,      0ull,   0ull},
20908         {"IGNRS"                       ,        16,     1,      426,    "R/W",  0,      0,      0ull,   0ull},
20909         {"RESERVED_17_63"              ,        17,     47,     426,    "RAZ",  0,      0,      0ull,   0ull},
20910         {"PKTDRP"                      ,        0,      1,      427,    "R/W",  0,      0,      0ull,   0ull},
20911         {"CRCERR"                      ,        1,      1,      427,    "R/W",  0,      0,      0ull,   0ull},
20912         {"BCKPRS"                      ,        2,      1,      427,    "R/W",  0,      0,      0ull,   0ull},
20913         {"PRTNXA"                      ,        3,      1,      427,    "R/W",  0,      0,      0ull,   0ull},
20914         {"BADTAG"                      ,        4,      1,      427,    "R/W",  0,      0,      0ull,   0ull},
20915         {"SKPRUNT"                     ,        5,      1,      427,    "R/W",  0,      0,      0ull,   0ull},
20916         {"TODOOVR"                     ,        6,      1,      427,    "R/W",  0,      0,      0ull,   0ull},
20917         {"FEPERR"                      ,        7,      1,      427,    "R/W",  0,      0,      0ull,   0ull},
20918         {"BEPERR"                      ,        8,      1,      427,    "R/W",  0,      0,      0ull,   0ull},
20919         {"RESERVED_9_63"               ,        9,      55,     427,    "RAZ",  1,      1,      0,      0},
20920         {"PKTDRP"                      ,        0,      1,      428,    "R/W1C",        0,      0,      0ull,   0ull},
20921         {"CRCERR"                      ,        1,      1,      428,    "R/W1C",        0,      0,      0ull,   0ull},
20922         {"BCKPRS"                      ,        2,      1,      428,    "R/W1C",        0,      0,      0ull,   0ull},
20923         {"PRTNXA"                      ,        3,      1,      428,    "R/W1C",        0,      0,      0ull,   0ull},
20924         {"BADTAG"                      ,        4,      1,      428,    "R/W1C",        0,      0,      0ull,   0ull},
20925         {"SKPRUNT"                     ,        5,      1,      428,    "R/W1C",        0,      0,      0ull,   0ull},
20926         {"TODOOVR"                     ,        6,      1,      428,    "R/W1C",        0,      0,      0ull,   0ull},
20927         {"FEPERR"                      ,        7,      1,      428,    "R/W1C",        0,      0,      0ull,   0ull},
20928         {"BEPERR"                      ,        8,      1,      428,    "R/W1C",        0,      0,      0ull,   0ull},
20929         {"RESERVED_9_63"               ,        9,      55,     428,    "RAZ",  1,      1,      0,      0},
20930         {"OFFSET"                      ,        0,      3,      429,    "R/W",  0,      0,      0ull,   0ull},
20931         {"RESERVED_3_63"               ,        3,      61,     429,    "RAZ",  1,      1,      0,      0},
20932         {"SKIP"                        ,        0,      7,      430,    "R/W",  0,      0,      0ull,   0ull},
20933         {"RESERVED_7_7"                ,        7,      1,      430,    "RAZ",  1,      1,      0,      0},
20934         {"MODE"                        ,        8,      2,      430,    "R/W",  0,      0,      0ull,   0ull},
20935         {"RESERVED_10_11"              ,        10,     2,      430,    "RAZ",  1,      1,      0,      0},
20936         {"CRC_EN"                      ,        12,     1,      430,    "R/W",  0,      0,      1ull,   1ull},
20937         {"RESERVED_13_15"              ,        13,     3,      430,    "RAZ",  1,      1,      0,      0},
20938         {"QOS_VLAN"                    ,        16,     1,      430,    "R/W",  0,      0,      0ull,   0ull},
20939         {"QOS_DIFF"                    ,        17,     1,      430,    "R/W",  0,      0,      0ull,   0ull},
20940         {"RESERVED_18_19"              ,        18,     2,      430,    "RAZ",  0,      0,      0ull,   0ull},
20941         {"QOS_WAT"                     ,        20,     4,      430,    "R/W",  0,      0,      0ull,   0ull},
20942         {"QOS"                         ,        24,     3,      430,    "R/W",  0,      0,      0ull,   0ull},
20943         {"RESERVED_27_27"              ,        27,     1,      430,    "RAZ",  1,      1,      0,      0},
20944         {"GRP_WAT"                     ,        28,     4,      430,    "R/W",  0,      0,      0ull,   0ull},
20945         {"INST_HDR"                    ,        32,     1,      430,    "R/W",  0,      0,      0ull,   0ull},
20946         {"DYN_RS"                      ,        33,     1,      430,    "R/W",  0,      0,      0ull,   0ull},
20947         {"TAG_INC"                     ,        34,     2,      430,    "R/W",  0,      0,      0ull,   0ull},
20948         {"RAWDRP"                      ,        36,     1,      430,    "R/W",  0,      0,      0ull,   0ull},
20949         {"RESERVED_37_63"              ,        37,     27,     430,    "RAZ",  1,      1,      0,      0},
20950         {"GRP"                         ,        0,      4,      431,    "R/W",  0,      0,      0ull,   0ull},
20951         {"NON_TAG_TYPE"                ,        4,      2,      431,    "R/W",  0,      0,      0ull,   0ull},
20952         {"IP4_TAG_TYPE"                ,        6,      2,      431,    "R/W",  0,      0,      0ull,   0ull},
20953         {"IP6_TAG_TYPE"                ,        8,      2,      431,    "R/W",  0,      0,      0ull,   0ull},
20954         {"TCP4_TAG_TYPE"               ,        10,     2,      431,    "R/W",  0,      0,      0ull,   0ull},
20955         {"TCP6_TAG_TYPE"               ,        12,     2,      431,    "R/W",  0,      0,      0ull,   0ull},
20956         {"IP4_SRC_FLAG"                ,        14,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20957         {"IP6_SRC_FLAG"                ,        15,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20958         {"IP4_DST_FLAG"                ,        16,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20959         {"IP6_DST_FLAG"                ,        17,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20960         {"IP4_PCTL_FLAG"               ,        18,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20961         {"IP6_NXTH_FLAG"               ,        19,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20962         {"IP4_SPRT_FLAG"               ,        20,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20963         {"IP6_SPRT_FLAG"               ,        21,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20964         {"IP4_DPRT_FLAG"               ,        22,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20965         {"IP6_DPRT_FLAG"               ,        23,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20966         {"INC_PRT_FLAG"                ,        24,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20967         {"INC_VLAN"                    ,        25,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20968         {"INC_VS"                      ,        26,     2,      431,    "R/W",  0,      0,      0ull,   0ull},
20969         {"TAG_MODE"                    ,        28,     2,      431,    "R/W",  0,      0,      0ull,   0ull},
20970         {"RESERVED_30_30"              ,        30,     1,      431,    "RAZ",  0,      0,      0ull,   0ull},
20971         {"GRPTAG"                      ,        31,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
20972         {"GRPTAGMASK"                  ,        32,     4,      431,    "R/W",  0,      0,      0ull,   0ull},
20973         {"GRPTAGBASE"                  ,        36,     4,      431,    "R/W",  0,      0,      0ull,   0ull},
20974         {"RESERVED_40_63"              ,        40,     24,     431,    "RAZ",  1,      1,      0,      0},
20975         {"QOS"                         ,        0,      3,      432,    "R/W",  0,      0,      0ull,   0ull},
20976         {"RESERVED_3_63"               ,        3,      61,     432,    "RAZ",  1,      1,      0,      0},
20977         {"QOS"                         ,        0,      3,      433,    "R/W",  0,      0,      0ull,   0ull},
20978         {"RESERVED_3_63"               ,        3,      61,     433,    "RAZ",  1,      1,      0,      0},
20979         {"MATCH_VALUE"                 ,        0,      16,     434,    "R/W",  0,      0,      0ull,   0ull},
20980         {"MATCH_TYPE"                  ,        16,     2,      434,    "R/W",  0,      0,      0ull,   0ull},
20981         {"RESERVED_18_19"              ,        18,     2,      434,    "RAZ",  1,      1,      0,      0},
20982         {"QOS"                         ,        20,     3,      434,    "R/W",  0,      0,      0ull,   0ull},
20983         {"RESERVED_23_23"              ,        23,     1,      434,    "RAZ",  1,      1,      0,      0},
20984         {"GRP"                         ,        24,     4,      434,    "R/W",  0,      0,      0ull,   0ull},
20985         {"RESERVED_28_31"              ,        28,     4,      434,    "RAZ",  1,      1,      0,      0},
20986         {"MASK"                        ,        32,     16,     434,    "R/W",  0,      0,      0ull,   0ull},
20987         {"RESERVED_48_63"              ,        48,     16,     434,    "RAZ",  1,      1,      0,      0},
20988         {"WORD"                        ,        0,      56,     435,    "R/W",  0,      0,      0ull,   0ull},
20989         {"RESERVED_56_63"              ,        56,     8,      435,    "RAZ",  1,      1,      0,      0},
20990         {"RST"                         ,        0,      1,      436,    "R/W",  0,      0,      0ull,   0ull},
20991         {"RESERVED_1_63"               ,        1,      63,     436,    "RAZ",  1,      1,      0,      0},
20992         {"DRP_OCTS"                    ,        0,      32,     437,    "R/W",  0,      1,      0ull,   0},
20993         {"DRP_PKTS"                    ,        32,     32,     437,    "R/W",  0,      1,      0ull,   0},
20994         {"OCTS"                        ,        0,      48,     438,    "R/W",  0,      1,      0ull,   0},
20995         {"RESERVED_48_63"              ,        48,     16,     438,    "RAZ",  1,      1,      0,      0},
20996         {"RAW"                         ,        0,      32,     439,    "R/W",  0,      1,      0ull,   0},
20997         {"PKTS"                        ,        32,     32,     439,    "R/W",  0,      1,      0ull,   0},
20998         {"MCST"                        ,        0,      32,     440,    "R/W",  0,      1,      0ull,   0},
20999         {"BCST"                        ,        32,     32,     440,    "R/W",  0,      1,      0ull,   0},
21000         {"H64"                         ,        0,      32,     441,    "R/W",  0,      1,      0ull,   0},
21001         {"H65TO127"                    ,        32,     32,     441,    "R/W",  0,      1,      0ull,   0},
21002         {"H128TO255"                   ,        0,      32,     442,    "R/W",  0,      1,      0ull,   0},
21003         {"H256TO511"                   ,        32,     32,     442,    "R/W",  0,      1,      0ull,   0},
21004         {"H512TO1023"                  ,        0,      32,     443,    "R/W",  0,      1,      0ull,   0},
21005         {"H1024TO1518"                 ,        32,     32,     443,    "R/W",  0,      1,      0ull,   0},
21006         {"H1519"                       ,        0,      32,     444,    "R/W",  0,      1,      0ull,   0},
21007         {"FCS"                         ,        32,     32,     444,    "R/W",  0,      1,      0ull,   0},
21008         {"UNDERSZ"                     ,        0,      32,     445,    "R/W",  0,      1,      0ull,   0},
21009         {"FRAG"                        ,        32,     32,     445,    "R/W",  0,      1,      0ull,   0},
21010         {"OVERSZ"                      ,        0,      32,     446,    "R/W",  0,      1,      0ull,   0},
21011         {"JABBER"                      ,        32,     32,     446,    "R/W",  0,      1,      0ull,   0},
21012         {"RDCLR"                       ,        0,      1,      447,    "R/W",  0,      0,      1ull,   1ull},
21013         {"RESERVED_1_63"               ,        1,      63,     447,    "RAZ",  1,      1,      0,      0},
21014         {"ERRS"                        ,        0,      16,     448,    "R/W",  0,      1,      0ull,   0},
21015         {"RESERVED_16_63"              ,        16,     48,     448,    "RAZ",  1,      1,      0,      0},
21016         {"OCTS"                        ,        0,      48,     449,    "R/W",  0,      1,      0ull,   0},
21017         {"RESERVED_48_63"              ,        48,     16,     449,    "RAZ",  1,      1,      0,      0},
21018         {"PKTS"                        ,        0,      32,     450,    "R/W",  0,      1,      0ull,   0},
21019         {"RESERVED_32_63"              ,        32,     32,     450,    "RAZ",  1,      1,      0,      0},
21020         {"EN"                          ,        0,      8,      451,    "R/W",  0,      0,      0ull,   0ull},
21021         {"RESERVED_8_63"               ,        8,      56,     451,    "RAZ",  1,      1,      0,      0},
21022         {"MASK"                        ,        0,      16,     452,    "R/W",  0,      0,      0ull,   0ull},
21023         {"RESERVED_16_63"              ,        16,     48,     452,    "RAZ",  1,      1,      0,      0},
21024         {"SRC"                         ,        0,      16,     453,    "R/W",  0,      0,      0ull,   0ull},
21025         {"DST"                         ,        16,     16,     453,    "R/W",  0,      0,      0ull,   0ull},
21026         {"RESERVED_32_63"              ,        32,     32,     453,    "RAZ",  1,      1,      0,      0},
21027         {"ENTRY"                       ,        0,      62,     454,    "RO",   1,      1,      0,      0},
21028         {"RESERVED_62_62"              ,        62,     1,      454,    "RAZ",  1,      1,      0,      0},
21029         {"VAL"                         ,        63,     1,      454,    "RO",   1,      1,      0,      0},
21030         {"COUNT"                       ,        0,      32,     455,    "R/W1C",        1,      0,      0,      0ull},
21031         {"RESERVED_32_63"              ,        32,     32,     455,    "RAZ",  1,      1,      0,      0},
21032         {"COUNT"                       ,        0,      48,     456,    "R/W1C",        1,      0,      0,      0ull},
21033         {"RESERVED_48_63"              ,        48,     16,     456,    "RAZ",  1,      1,      0,      0},
21034         {"SIZE"                        ,        0,      16,     457,    "RO",   1,      0,      0,      0ull},
21035         {"SEGS"                        ,        16,     6,      457,    "RO",   1,      0,      0,      0ull},
21036         {"CMD"                         ,        22,     14,     457,    "RO",   1,      0,      0,      0ull},
21037         {"FAU"                         ,        36,     28,     457,    "RO",   1,      0,      0,      0ull},
21038         {"PTR"                         ,        0,      40,     458,    "RO",   1,      0,      0,      0ull},
21039         {"SIZE"                        ,        40,     16,     458,    "RO",   1,      0,      0,      0ull},
21040         {"POOL"                        ,        56,     3,      458,    "RO",   1,      0,      0,      0ull},
21041         {"BACK"                        ,        59,     4,      458,    "RO",   1,      0,      0,      0ull},
21042         {"I"                           ,        63,     1,      458,    "RO",   1,      0,      0,      0ull},
21043         {"SIZE"                        ,        0,      16,     459,    "RO",   1,      0,      0,      0ull},
21044         {"SEGS"                        ,        16,     6,      459,    "RO",   1,      0,      0,      0ull},
21045         {"CMD"                         ,        22,     14,     459,    "RO",   1,      0,      0,      0ull},
21046         {"FAU"                         ,        36,     28,     459,    "RO",   1,      0,      0,      0ull},
21047         {"PTR"                         ,        0,      40,     460,    "RO",   1,      0,      0,      0ull},
21048         {"SIZE"                        ,        40,     16,     460,    "RO",   1,      0,      0,      0ull},
21049         {"POOL"                        ,        56,     3,      460,    "RO",   1,      0,      0,      0ull},
21050         {"BACK"                        ,        59,     4,      460,    "RO",   1,      0,      0,      0ull},
21051         {"I"                           ,        63,     1,      460,    "RO",   1,      0,      0,      0ull},
21052         {"DATA"                        ,        0,      64,     461,    "RO",   1,      0,      0,      0ull},
21053         {"WIDX2"                       ,        0,      17,     462,    "RO",   1,      0,      0,      0ull},
21054         {"RIDX2"                       ,        17,     17,     462,    "RO",   1,      0,      0,      0ull},
21055         {"WIDX"                        ,        34,     17,     462,    "RO",   1,      0,      0,      0ull},
21056         {"RESERVED_51_63"              ,        51,     13,     462,    "RAZ",  1,      0,      0,      0ull},
21057         {"RIDX"                        ,        0,      17,     463,    "RO",   1,      0,      0,      0ull},
21058         {"RESERVED_17_63"              ,        17,     47,     463,    "RAZ",  1,      0,      0,      0ull},
21059         {"PTR"                         ,        0,      40,     464,    "RO",   1,      0,      0,      0ull},
21060         {"SIZE"                        ,        40,     16,     464,    "RO",   1,      0,      0,      0ull},
21061         {"POOL"                        ,        56,     3,      464,    "RO",   1,      0,      0,      0ull},
21062         {"BACK"                        ,        59,     4,      464,    "RO",   1,      0,      0,      0ull},
21063         {"I"                           ,        63,     1,      464,    "RO",   1,      0,      0,      0ull},
21064         {"PTR"                         ,        0,      40,     465,    "RO",   1,      0,      0,      0ull},
21065         {"SIZE"                        ,        40,     16,     465,    "RO",   1,      0,      0,      0ull},
21066         {"POOL"                        ,        56,     3,      465,    "RO",   1,      0,      0,      0ull},
21067         {"BACK"                        ,        59,     4,      465,    "RO",   1,      0,      0,      0ull},
21068         {"I"                           ,        63,     1,      465,    "RO",   1,      0,      0,      0ull},
21069         {"DATA"                        ,        0,      64,     466,    "RO",   1,      0,      0,      0ull},
21070         {"MAJOR"                       ,        0,      4,      467,    "RO",   1,      0,      0,      0ull},
21071         {"MINOR"                       ,        4,      2,      467,    "RO",   1,      0,      0,      0ull},
21072         {"WAIT"                        ,        6,      1,      467,    "RO",   1,      0,      0,      0ull},
21073         {"QID_BASE"                    ,        7,      7,      467,    "RO",   1,      0,      0,      0ull},
21074         {"QID_OFF"                     ,        14,     3,      467,    "RO",   1,      0,      0,      0ull},
21075         {"QCB_RIDX"                    ,        17,     5,      467,    "RO",   1,      0,      0,      0ull},
21076         {"QOS"                         ,        22,     3,      467,    "RO",   1,      0,      0,      0ull},
21077         {"ACTIVE"                      ,        25,     1,      467,    "RO",   1,      0,      0,      0ull},
21078         {"CHK_MODE"                    ,        26,     1,      467,    "RO",   1,      0,      0,      0ull},
21079         {"RESERVED_27_27"              ,        27,     1,      467,    "RAZ",  1,      0,      0,      0ull},
21080         {"CBUF_FRE"                    ,        28,     1,      467,    "RO",   1,      0,      0,      0ull},
21081         {"XFER_DWR"                    ,        29,     1,      467,    "RO",   1,      0,      0,      0ull},
21082         {"XFER_WOR"                    ,        30,     1,      467,    "RO",   1,      0,      0,      0ull},
21083         {"UID"                         ,        31,     1,      467,    "RO",   1,      0,      0,      0ull},
21084         {"CMND_SIZ"                    ,        32,     16,     467,    "RO",   1,      0,      0,      0ull},
21085         {"DWRI_CNT"                    ,        48,     13,     467,    "RO",   1,      0,      0,      0ull},
21086         {"DWRI_LEN"                    ,        61,     1,      467,    "RO",   1,      0,      0,      0ull},
21087         {"DWRI_SOP"                    ,        62,     1,      467,    "RO",   1,      0,      0,      0ull},
21088         {"DWRI_MOD"                    ,        63,     1,      467,    "RO",   1,      0,      0,      0ull},
21089         {"DWRI_MOD"                    ,        0,      2,      468,    "RO",   1,      0,      0,      0ull},
21090         {"DWRI_UID"                    ,        2,      1,      468,    "RO",   1,      0,      0,      0ull},
21091         {"DWRI_CHK"                    ,        3,      1,      468,    "RO",   1,      0,      0,      0ull},
21092         {"WORK_MIN"                    ,        4,      3,      468,    "RO",   1,      0,      0,      0ull},
21093         {"STATIC_P"                    ,        7,      1,      468,    "RO",   1,      0,      0,      0ull},
21094         {"QID_OFFM"                    ,        8,      3,      468,    "RO",   1,      0,      0,      0ull},
21095         {"RESERVED_11_63"              ,        11,     53,     468,    "RAZ",  1,      0,      0,      0ull},
21096         {"SIZE"                        ,        0,      16,     469,    "RO",   1,      0,      0,      0ull},
21097         {"START"                       ,        16,     33,     469,    "RO",   1,      0,      0,      0ull},
21098         {"DWB"                         ,        49,     9,      469,    "RO",   1,      0,      0,      0ull},
21099         {"RESERVED_58_63"              ,        58,     6,      469,    "RAZ",  1,      0,      0,      0ull},
21100         {"QCB_RIDX"                    ,        0,      6,      470,    "RO",   1,      0,      0,      0ull},
21101         {"QCB_WIDX"                    ,        6,      6,      470,    "RO",   1,      0,      0,      0ull},
21102         {"BUF_PTR"                     ,        12,     33,     470,    "RO",   1,      0,      0,      0ull},
21103         {"BUF_SIZ"                     ,        45,     13,     470,    "RO",   1,      0,      0,      0ull},
21104         {"TAIL"                        ,        58,     1,      470,    "RO",   1,      0,      0,      0ull},
21105         {"QOS"                         ,        59,     5,      470,    "RO",   1,      0,      0,      0ull},
21106         {"QOS"                         ,        0,      3,      471,    "RO",   1,      0,      0,      0ull},
21107         {"STATIC_Q"                    ,        3,      1,      471,    "RO",   1,      0,      0,      0ull},
21108         {"S_TAIL"                      ,        4,      1,      471,    "RO",   1,      0,      0,      0ull},
21109         {"STATIC_P"                    ,        5,      1,      471,    "RO",   1,      0,      0,      0ull},
21110         {"RESERVED_6_7"                ,        6,      2,      471,    "RAZ",  1,      0,      0,      0ull},
21111         {"DOORBELL"                    ,        8,      20,     471,    "RO",   1,      0,      0,      0ull},
21112         {"RESERVED_28_63"              ,        28,     36,     471,    "RAZ",  1,      0,      0,      0ull},
21113         {"QUEUE"                       ,        0,      7,      472,    "R/W",  1,      0,      0,      0ull},
21114         {"PORT"                        ,        7,      6,      472,    "WR0",  1,      0,      0,      0ull},
21115         {"INDEX"                       ,        13,     3,      472,    "WR0",  1,      0,      0,      0ull},
21116         {"TAIL"                        ,        16,     1,      472,    "R/W",  1,      0,      0,      0ull},
21117         {"BUF_PTR"                     ,        17,     36,     472,    "R/W",  1,      0,      0,      0ull},
21118         {"QOS_MASK"                    ,        53,     8,      472,    "R/W",  1,      0,      0,      0ull},
21119         {"STATIC_Q"                    ,        61,     1,      472,    "R/W",  1,      0,      0,      0ull},
21120         {"STATIC_P"                    ,        62,     1,      472,    "R/W",  1,      0,      0,      0ull},
21121         {"S_TAIL"                      ,        63,     1,      472,    "R/W",  1,      0,      0,      0ull},
21122         {"QID"                         ,        0,      7,      473,    "R/W",  1,      0,      0,      0ull},
21123         {"PID"                         ,        7,      6,      473,    "WR0",  1,      0,      0,      0ull},
21124         {"RESERVED_13_52"              ,        13,     40,     473,    "RAZ",  1,      0,      0,      0ull},
21125         {"QOS_MASK"                    ,        53,     8,      473,    "R/W",  1,      0,      0,      0ull},
21126         {"RESERVED_61_63"              ,        61,     3,      473,    "RAZ",  1,      0,      0,      0ull},
21127         {"PSB"                         ,        0,      7,      474,    "RO",   1,      0,      0,      0ull},
21128         {"PDB"                         ,        7,      4,      474,    "RO",   1,      0,      0,      0ull},
21129         {"QCB"                         ,        11,     2,      474,    "RO",   1,      0,      0,      0ull},
21130         {"QSB"                         ,        13,     2,      474,    "RO",   1,      0,      0,      0ull},
21131         {"CHK"                         ,        15,     1,      474,    "RO",   1,      0,      0,      0ull},
21132         {"CRC"                         ,        16,     1,      474,    "RO",   1,      0,      0,      0ull},
21133         {"OUT"                         ,        17,     1,      474,    "RO",   1,      0,      0,      0ull},
21134         {"NCB"                         ,        18,     1,      474,    "RO",   1,      0,      0,      0ull},
21135         {"WIF"                         ,        19,     1,      474,    "RO",   1,      0,      0,      0ull},
21136         {"RIF"                         ,        20,     1,      474,    "RO",   1,      0,      0,      0ull},
21137         {"COUNT"                       ,        21,     1,      474,    "RO",   1,      0,      0,      0ull},
21138         {"PSB2"                        ,        22,     5,      474,    "RO",   1,      0,      0,      0ull},
21139         {"RESERVED_27_63"              ,        27,     37,     474,    "RAZ",  1,      0,      0,      0ull},
21140         {"SIZE"                        ,        0,      13,     475,    "R/W",  0,      0,      0ull,   0ull},
21141         {"RESERVED_13_19"              ,        13,     7,      475,    "RAZ",  0,      0,      0ull,   0ull},
21142         {"POOL"                        ,        20,     3,      475,    "R/W",  0,      0,      0ull,   0ull},
21143         {"RESERVED_23_63"              ,        23,     41,     475,    "RAZ",  1,      0,      0,      0ull},
21144         {"REFIN"                       ,        0,      1,      476,    "R/W",  0,      0,      1ull,   1ull},
21145         {"INVRES"                      ,        1,      1,      476,    "R/W",  0,      0,      1ull,   1ull},
21146         {"RESERVED_2_63"               ,        2,      62,     476,    "RAZ",  1,      1,      0,      0},
21147         {"ENABLE"                      ,        0,      32,     477,    "R/W",  0,      0,      0ull,   0ull},
21148         {"RESERVED_32_63"              ,        32,     32,     477,    "RAZ",  1,      0,      0,      0ull},
21149         {"IV"                          ,        0,      32,     478,    "R/W",  0,      0,      1185899593ull,  1185899593ull},
21150         {"RESERVED_32_63"              ,        32,     32,     478,    "RAZ",  1,      1,      0,      0},
21151         {"ASSERTS"                     ,        0,      17,     479,    "RO",   0,      0,      0ull,   0ull},
21152         {"RESERVED_17_63"              ,        17,     47,     479,    "RAZ",  1,      0,      0,      0ull},
21153         {"PARITY"                      ,        0,      1,      480,    "R/W1C",        0,      0,      0ull,   0ull},
21154         {"DOORBELL"                    ,        1,      1,      480,    "R/W1C",        0,      0,      0ull,   0ull},
21155         {"RESERVED_2_63"               ,        2,      62,     480,    "RAZ",  1,      0,      0,      0ull},
21156         {"ENA_PKO"                     ,        0,      1,      481,    "R/W",  0,      0,      0ull,   0ull},
21157         {"ENA_DWB"                     ,        1,      1,      481,    "R/W",  0,      0,      0ull,   0ull},
21158         {"STORE_BE"                    ,        2,      1,      481,    "R/W",  0,      0,      0ull,   0ull},
21159         {"RESET"                       ,        3,      1,      481,    "RAZ",  0,      0,      0ull,   0ull},
21160         {"RESERVED_4_63"               ,        4,      60,     481,    "RAZ",  1,      0,      0,      0ull},
21161         {"MODE0"                       ,        0,      3,      482,    "R/W",  0,      0,      0ull,   0ull},
21162         {"MODE1"                       ,        3,      3,      482,    "R/W",  0,      0,      0ull,   0ull},
21163         {"RESERVED_6_63"               ,        6,      58,     482,    "RAZ",  1,      0,      0,      0ull},
21164         {"PARITY"                      ,        0,      1,      483,    "R/W",  0,      0,      0ull,   0ull},
21165         {"DOORBELL"                    ,        1,      1,      483,    "R/W",  0,      0,      0ull,   0ull},
21166         {"RESERVED_2_63"               ,        2,      62,     483,    "RAZ",  1,      0,      0,      0ull},
21167         {"MODE"                        ,        0,      2,      484,    "R/W",  0,      0,      0ull,   0ull},
21168         {"RESERVED_2_63"               ,        2,      62,     484,    "RAZ",  1,      0,      0,      0ull},
21169         {"INDEX"                       ,        0,      8,      485,    "R/W",  0,      0,      0ull,   0ull},
21170         {"INC"                         ,        8,      8,      485,    "R/W",  0,      0,      0ull,   0ull},
21171         {"RESERVED_16_63"              ,        16,     48,     485,    "RAZ",  1,      0,      0,      0ull},
21172         {"ADR0"                        ,        0,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21173         {"ADR1"                        ,        1,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21174         {"PEND0"                       ,        2,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21175         {"PEND1"                       ,        3,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21176         {"NBR0"                        ,        4,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21177         {"NBR1"                        ,        5,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21178         {"FIDX"                        ,        6,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21179         {"INDEX"                       ,        7,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21180         {"NBT"                         ,        8,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21181         {"CAM"                         ,        9,      1,      486,    "RO",   0,      0,      0ull,   0ull},
21182         {"RESERVED_10_15"              ,        10,     6,      486,    "RAZ",  1,      1,      0,      0},
21183         {"PP"                          ,        16,     16,     486,    "RO",   0,      0,      0ull,   0ull},
21184         {"RESERVED_32_63"              ,        32,     32,     486,    "RAZ",  1,      1,      0,      0},
21185         {"DS_PC"                       ,        0,      32,     487,    "R/W1C",        0,      1,      0ull,   0},
21186         {"RESERVED_32_63"              ,        32,     32,     487,    "RAZ",  1,      1,      0,      0},
21187         {"SBE"                         ,        0,      1,      488,    "R/W1C",        0,      0,      0ull,   0ull},
21188         {"DBE"                         ,        1,      1,      488,    "R/W1C",        0,      0,      0ull,   0ull},
21189         {"SBE_IE"                      ,        2,      1,      488,    "R/W",  0,      1,      0ull,   0},
21190         {"DBE_IE"                      ,        3,      1,      488,    "R/W",  0,      1,      0ull,   0},
21191         {"SYN"                         ,        4,      5,      488,    "RO",   1,      1,      0,      0},
21192         {"RESERVED_9_11"               ,        9,      3,      488,    "RAZ",  1,      1,      0,      0},
21193         {"RPE"                         ,        12,     1,      488,    "R/W1C",        0,      0,      0ull,   0ull},
21194         {"RPE_IE"                      ,        13,     1,      488,    "R/W",  0,      1,      0ull,   0},
21195         {"RESERVED_14_15"              ,        14,     2,      488,    "RAZ",  1,      1,      0,      0},
21196         {"IOP"                         ,        16,     13,     488,    "R/W1C",        0,      0,      0ull,   0ull},
21197         {"RESERVED_29_31"              ,        29,     3,      488,    "RAZ",  1,      1,      0,      0},
21198         {"IOP_IE"                      ,        32,     13,     488,    "R/W",  0,      1,      0ull,   0},
21199         {"RESERVED_45_63"              ,        45,     19,     488,    "RAZ",  1,      1,      0,      0},
21200         {"NBR_THR"                     ,        0,      5,      489,    "R/W",  0,      0,      2ull,   2ull},
21201         {"PFR_DIS"                     ,        5,      1,      489,    "R/W",  0,      0,      0ull,   0ull},
21202         {"RESERVED_6_63"               ,        6,      58,     489,    "RAZ",  1,      1,      0,      0},
21203         {"IQ_CNT"                      ,        0,      32,     490,    "RO",   0,      1,      0ull,   0},
21204         {"RESERVED_32_63"              ,        32,     32,     490,    "RAZ",  1,      1,      0,      0},
21205         {"IQ_CNT"                      ,        0,      32,     491,    "RO",   0,      1,      0ull,   0},
21206         {"RESERVED_32_63"              ,        32,     32,     491,    "RAZ",  1,      1,      0,      0},
21207         {"NOS_CNT"                     ,        0,      12,     492,    "RO",   0,      1,      0ull,   0},
21208         {"RESERVED_12_63"              ,        12,     52,     492,    "RAZ",  1,      1,      0,      0},
21209         {"NW_TIM"                      ,        0,      10,     493,    "R/W",  0,      0,      0ull,   1023ull},
21210         {"RESERVED_10_63"              ,        10,     54,     493,    "RAZ",  1,      1,      0,      0},
21211         {"GRP_MSK"                     ,        0,      16,     494,    "R/W",  0,      0,      65535ull,       65535ull},
21212         {"RESERVED_16_63"              ,        16,     48,     494,    "RAZ",  1,      1,      0,      0},
21213         {"RND"                         ,        0,      8,      495,    "R/W",  0,      1,      255ull, 0},
21214         {"RND_P1"                      ,        8,      8,      495,    "R/W",  0,      1,      255ull, 0},
21215         {"RND_P2"                      ,        16,     8,      495,    "R/W",  0,      1,      255ull, 0},
21216         {"RND_P3"                      ,        24,     8,      495,    "R/W",  0,      1,      255ull, 0},
21217         {"RESERVED_32_63"              ,        32,     32,     495,    "RAZ",  1,      1,      0,      0},
21218         {"MIN_THR"                     ,        0,      11,     496,    "R/W",  0,      1,      0ull,   0},
21219         {"RESERVED_11_11"              ,        11,     1,      496,    "RAZ",  1,      1,      0,      0},
21220         {"MAX_THR"                     ,        12,     11,     496,    "R/W",  0,      1,      2047ull,        0},
21221         {"RESERVED_23_23"              ,        23,     1,      496,    "RAZ",  1,      1,      0,      0},
21222         {"FREE_CNT"                    ,        24,     12,     496,    "RO",   0,      1,      2027ull,        0},
21223         {"BUF_CNT"                     ,        36,     12,     496,    "RO",   0,      1,      0ull,   0},
21224         {"DES_CNT"                     ,        48,     12,     496,    "RO",   0,      1,      0ull,   0},
21225         {"RESERVED_60_63"              ,        60,     4,      496,    "RAZ",  1,      1,      0,      0},
21226         {"TS_PC"                       ,        0,      32,     497,    "R/W1C",        0,      1,      0ull,   0},
21227         {"RESERVED_32_63"              ,        32,     32,     497,    "RAZ",  1,      1,      0,      0},
21228         {"WA_PC"                       ,        0,      32,     498,    "R/W1C",        0,      1,      0ull,   0},
21229         {"RESERVED_32_63"              ,        32,     32,     498,    "RAZ",  1,      1,      0,      0},
21230         {"WA_PC"                       ,        0,      32,     499,    "R/W1C",        0,      1,      0ull,   0},
21231         {"RESERVED_32_63"              ,        32,     32,     499,    "RAZ",  1,      1,      0,      0},
21232         {"WQ_INT"                      ,        0,      16,     500,    "R/W1C",        0,      1,      0ull,   0},
21233         {"IQ_DIS"                      ,        16,     16,     500,    "R/W1", 0,      1,      0ull,   0},
21234         {"RESERVED_32_63"              ,        32,     32,     500,    "RAZ",  1,      1,      0,      0},
21235         {"IQ_CNT"                      ,        0,      12,     501,    "RO",   0,      1,      0ull,   0},
21236         {"DS_CNT"                      ,        12,     12,     501,    "RO",   0,      1,      0ull,   0},
21237         {"TC_CNT"                      ,        24,     4,      501,    "RO",   0,      1,      0ull,   0},
21238         {"RESERVED_28_63"              ,        28,     36,     501,    "RAZ",  1,      1,      0,      0},
21239         {"RESERVED_0_7"                ,        0,      8,      502,    "RAZ",  1,      1,      0,      0},
21240         {"PC_THR"                      ,        8,      20,     502,    "R/W",  0,      1,      0ull,   0},
21241         {"RESERVED_28_31"              ,        28,     4,      502,    "RAZ",  1,      1,      0,      0},
21242         {"PC"                          ,        32,     28,     502,    "RO",   0,      1,      0ull,   0},
21243         {"RESERVED_60_63"              ,        60,     4,      502,    "RAZ",  1,      1,      0,      0},
21244         {"IQ_THR"                      ,        0,      11,     503,    "R/W",  0,      1,      0ull,   0},
21245         {"RESERVED_11_11"              ,        11,     1,      503,    "RAZ",  1,      1,      0,      0},
21246         {"DS_THR"                      ,        12,     11,     503,    "R/W",  0,      1,      0ull,   0},
21247         {"RESERVED_23_23"              ,        23,     1,      503,    "RAZ",  1,      1,      0,      0},
21248         {"TC_THR"                      ,        24,     4,      503,    "R/W",  0,      1,      0ull,   0},
21249         {"TC_EN"                       ,        28,     1,      503,    "R/W",  0,      1,      0ull,   0},
21250         {"RESERVED_29_63"              ,        29,     35,     503,    "RAZ",  1,      1,      0,      0},
21251         {"WS_PC"                       ,        0,      32,     504,    "R/W1C",        0,      1,      0ull,   0},
21252         {"RESERVED_32_63"              ,        32,     32,     504,    "RAZ",  1,      1,      0,      0},
21253         {"MEM"                         ,        0,      1,      505,    "RO",   0,      0,      0ull,   0ull},
21254         {"RRC"                         ,        1,      1,      505,    "RO",   0,      0,      0ull,   0ull},
21255         {"RESERVED_2_63"               ,        2,      62,     505,    "RAZ",  1,      1,      0,      0},
21256         {"ENT_EN"                      ,        0,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
21257         {"RNG_EN"                      ,        1,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
21258         {"RNM_RST"                     ,        2,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
21259         {"RNG_RST"                     ,        3,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
21260         {"RESERVED_4_63"               ,        4,      60,     506,    "RAZ",  1,      1,      0,      0},
21261         {"PHASE"                       ,        0,      8,      507,    "R/W",  0,      0,      100ull, 100ull},
21262         {"SAMPLE"                      ,        8,      4,      507,    "R/W",  0,      0,      2ull,   2ull},
21263         {"PREAMBLE"                    ,        12,     1,      507,    "R/W",  0,      0,      1ull,   1ull},
21264         {"CLK_IDLE"                    ,        13,     1,      507,    "R/W",  0,      0,      0ull,   0ull},
21265         {"RESERVED_14_14"              ,        14,     1,      507,    "RAZ",  1,      1,      0,      0},
21266         {"SAMPLE_MODE"                 ,        15,     1,      507,    "RAZ",  0,      0,      0ull,   0ull},
21267         {"SAMPLE_HI"                   ,        16,     5,      507,    "R/W",  0,      0,      0ull,   0ull},
21268         {"RESERVED_21_63"              ,        21,     43,     507,    "RAZ",  1,      1,      0,      0},
21269         {"REG_ADR"                     ,        0,      5,      508,    "R/W",  0,      1,      0ull,   0},
21270         {"RESERVED_5_7"                ,        5,      3,      508,    "RAZ",  1,      1,      0,      0},
21271         {"PHY_ADR"                     ,        8,      5,      508,    "R/W",  0,      1,      0ull,   0},
21272         {"RESERVED_13_15"              ,        13,     3,      508,    "RAZ",  1,      1,      0,      0},
21273         {"PHY_OP"                      ,        16,     1,      508,    "R/W",  0,      1,      0ull,   0},
21274         {"RESERVED_17_63"              ,        17,     47,     508,    "RAZ",  1,      1,      0,      0},
21275         {"EN"                          ,        0,      1,      509,    "R/W",  0,      0,      0ull,   1ull},
21276         {"RESERVED_1_63"               ,        1,      63,     509,    "RAZ",  1,      1,      0,      0},
21277         {"DAT"                         ,        0,      16,     510,    "RO",   0,      1,      0ull,   0},
21278         {"VAL"                         ,        16,     1,      510,    "RO",   0,      1,      0ull,   0},
21279         {"PENDING"                     ,        17,     1,      510,    "RO",   0,      1,      0ull,   0},
21280         {"RESERVED_18_63"              ,        18,     46,     510,    "RAZ",  1,      1,      0,      0},
21281         {"DAT"                         ,        0,      16,     511,    "R/W",  0,      1,      0ull,   0},
21282         {"VAL"                         ,        16,     1,      511,    "RO",   0,      1,      0ull,   0},
21283         {"PENDING"                     ,        17,     1,      511,    "RO",   0,      1,      0ull,   0},
21284         {"RESERVED_18_63"              ,        18,     46,     511,    "RAZ",  1,      1,      0,      0},
21285         {"CNT"                         ,        0,      32,     512,    "R/W1C",        0,      0,      0ull,   0ull},
21286         {"RESERVED_32_63"              ,        32,     32,     512,    "RAZ",  0,      0,      0ull,   0ull},
21287         {"STAT0"                       ,        0,      1,      513,    "RO",   0,      0,      0ull,   0ull},
21288         {"STAT1"                       ,        1,      1,      513,    "RO",   0,      0,      0ull,   0ull},
21289         {"STAT2"                       ,        2,      1,      513,    "RO",   0,      0,      0ull,   0ull},
21290         {"RESERVED_3_63"               ,        3,      61,     513,    "RAZ",  0,      0,      0ull,   0ull},
21291         {"SRXDLCK"                     ,        0,      1,      514,    "R/W",  0,      0,      0ull,   1ull},
21292         {"RCVTRN"                      ,        1,      1,      514,    "R/W",  0,      0,      0ull,   1ull},
21293         {"DRPTRN"                      ,        2,      1,      514,    "R/W",  0,      0,      0ull,   1ull},
21294         {"SNDTRN"                      ,        3,      1,      514,    "R/W",  0,      0,      0ull,   1ull},
21295         {"STATRCV"                     ,        4,      1,      514,    "R/W",  0,      0,      0ull,   0ull},
21296         {"STATDRV"                     ,        5,      1,      514,    "R/W",  0,      0,      0ull,   0ull},
21297         {"RUNBIST"                     ,        6,      1,      514,    "R/W",  0,      0,      0ull,   0ull},
21298         {"CLKDLY"                      ,        7,      5,      514,    "R/W",  0,      0,      16ull,  16ull},
21299         {"RESERVED_12_15"              ,        12,     4,      514,    "RAZ",  0,      0,      0ull,   0ull},
21300         {"SEETRN"                      ,        16,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
21301         {"RESERVED_17_63"              ,        17,     47,     514,    "RAZ",  0,      0,      0ull,   0ull},
21302         {"RESERVED_0_3"                ,        0,      4,      515,    "RAZ",  0,      1,      0ull,   0},
21303         {"D4CLK0"                      ,        4,      1,      515,    "R/W1C",        0,      1,      0ull,   0},
21304         {"D4CLK1"                      ,        5,      1,      515,    "R/W1C",        0,      1,      0ull,   0},
21305         {"S4CLK0"                      ,        6,      1,      515,    "R/W1C",        0,      1,      0ull,   0},
21306         {"S4CLK1"                      ,        7,      1,      515,    "R/W1C",        0,      1,      0ull,   0},
21307         {"SRXTRN"                      ,        8,      1,      515,    "R/W1C",        0,      1,      0ull,   0},
21308         {"RESERVED_9_9"                ,        9,      1,      515,    "RAZ",  0,      1,      0ull,   0},
21309         {"STXCAL"                      ,        10,     1,      515,    "R/W1C",        0,      1,      0ull,   0},
21310         {"RESERVED_11_63"              ,        11,     53,     515,    "RAZ",  0,      0,      0ull,   0ull},
21311         {"DLLDIS"                      ,        0,      1,      516,    "R/W",  1,      0,      0,      0ull},
21312         {"DLLFRC"                      ,        1,      1,      516,    "WR0",  1,      0,      0,      0ull},
21313         {"OFFDLY"                      ,        2,      6,      516,    "R/W",  1,      0,      0,      0ull},
21314         {"BITSEL"                      ,        8,      5,      516,    "R/W",  1,      1,      0,      0},
21315         {"OFFSET"                      ,        13,     5,      516,    "R/W",  1,      1,      0,      0},
21316         {"MUX"                         ,        18,     1,      516,    "WR0",  1,      1,      0,      0},
21317         {"INC"                         ,        19,     1,      516,    "WR0",  1,      1,      0,      0},
21318         {"DEC"                         ,        20,     1,      516,    "WR0",  1,      1,      0,      0},
21319         {"CLRDLY"                      ,        21,     1,      516,    "WR0",  1,      1,      0,      0},
21320         {"RESERVED_22_23"              ,        22,     2,      516,    "RAZ",  0,      0,      0ull,   0ull},
21321         {"SSTEP"                       ,        24,     1,      516,    "R/W",  1,      0,      0,      0ull},
21322         {"SSTEP_GO"                    ,        25,     1,      516,    "WR0",  1,      1,      0,      0},
21323         {"RESERVED_26_27"              ,        26,     2,      516,    "RAZ",  0,      0,      0ull,   0ull},
21324         {"FALL8"                       ,        28,     1,      516,    "R/W",  0,      0,      0ull,   0ull},
21325         {"FALLNOP"                     ,        29,     1,      516,    "R/W",  0,      0,      0ull,   0ull},
21326         {"RESERVED_30_63"              ,        30,     34,     516,    "RAZ",  0,      0,      0ull,   0ull},
21327         {"OFFSET"                      ,        0,      5,      517,    "RO",   0,      1,      0ull,   0},
21328         {"MUXSEL"                      ,        5,      2,      517,    "RO",   0,      1,      0ull,   0},
21329         {"UNXTERM"                     ,        7,      1,      517,    "R/W1C",        0,      0,      0ull,   0ull},
21330         {"TESTRES"                     ,        8,      1,      517,    "R/W1C",        0,      0,      0ull,   0ull},
21331         {"RESERVED_9_63"               ,        9,      55,     517,    "RAZ",  0,      0,      0ull,   0ull},
21332         {"SRX4CMP"                     ,        0,      8,      518,    "R/W",  0,      1,      0ull,   0},
21333         {"STX4PCMP"                    ,        8,      4,      518,    "R/W",  0,      1,      0ull,   0},
21334         {"STX4NCMP"                    ,        12,     4,      518,    "R/W",  0,      1,      0ull,   0},
21335         {"RESERVED_16_63"              ,        16,     48,     518,    "RAZ",  0,      0,      0ull,   0ull},
21336         {"ERRCNT"                      ,        0,      4,      519,    "R/W",  0,      0,      0ull,   3ull},
21337         {"RESERVED_4_5"                ,        4,      2,      519,    "RAZ",  0,      0,      0ull,   0ull},
21338         {"DIPPAY"                      ,        6,      1,      519,    "R/W",  0,      0,      0ull,   0ull},
21339         {"DIPCLS"                      ,        7,      1,      519,    "R/W",  0,      0,      0ull,   0ull},
21340         {"PRTNXA"                      ,        8,      1,      519,    "R/W",  0,      0,      0ull,   0ull},
21341         {"RESERVED_9_63"               ,        9,      55,     519,    "RAZ",  0,      0,      0ull,   0ull},
21342         {"PRT"                         ,        0,      8,      520,    "RO",   0,      0,      0ull,   0ull},
21343         {"RSVOP"                       ,        8,      4,      520,    "RO",   0,      0,      0ull,   0ull},
21344         {"CALBNK"                      ,        12,     2,      520,    "RO",   0,      0,      0ull,   0ull},
21345         {"RESERVED_14_30"              ,        14,     17,     520,    "RAZ",  0,      0,      0ull,   0ull},
21346         {"MUL"                         ,        31,     1,      520,    "RO",   0,      0,      0ull,   0ull},
21347         {"RESERVED_32_63"              ,        32,     32,     520,    "RAZ",  0,      0,      0ull,   0ull},
21348         {"PRTNXA"                      ,        0,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
21349         {"ABNORM"                      ,        1,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
21350         {"RESERVED_2_3"                ,        2,      2,      521,    "RAZ",  0,      0,      0ull,   0ull},
21351         {"SPIOVR"                      ,        4,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
21352         {"CLSERR"                      ,        5,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
21353         {"DRWNNG"                      ,        6,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
21354         {"RSVERR"                      ,        7,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
21355         {"TPAOVR"                      ,        8,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
21356         {"DIPERR"                      ,        9,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
21357         {"SYNCERR"                     ,        10,     1,      521,    "R/W",  0,      0,      0ull,   0ull},
21358         {"CALERR"                      ,        11,     1,      521,    "R/W",  0,      0,      0ull,   0ull},
21359         {"RESERVED_12_63"              ,        12,     52,     521,    "RAZ",  0,      0,      0ull,   0ull},
21360         {"PRTNXA"                      ,        0,      1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21361         {"ABNORM"                      ,        1,      1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21362         {"RESERVED_2_3"                ,        2,      2,      522,    "RAZ",  0,      0,      0ull,   0ull},
21363         {"SPIOVR"                      ,        4,      1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21364         {"CLSERR"                      ,        5,      1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21365         {"DRWNNG"                      ,        6,      1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21366         {"RSVERR"                      ,        7,      1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21367         {"TPAOVR"                      ,        8,      1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21368         {"DIPERR"                      ,        9,      1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21369         {"SYNCERR"                     ,        10,     1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21370         {"CALERR"                      ,        11,     1,      522,    "R/W1C",        0,      0,      0ull,   0ull},
21371         {"RESERVED_12_30"              ,        12,     19,     522,    "RAZ",  0,      0,      0ull,   0ull},
21372         {"SPF"                         ,        31,     1,      522,    "RO",   0,      0,      0ull,   0ull},
21373         {"RESERVED_32_63"              ,        32,     32,     522,    "RAZ",  0,      0,      0ull,   0ull},
21374         {"PRTNXA"                      ,        0,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
21375         {"ABNORM"                      ,        1,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
21376         {"RESERVED_2_3"                ,        2,      2,      523,    "RAZ",  0,      0,      0ull,   0ull},
21377         {"SPIOVR"                      ,        4,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
21378         {"CLSERR"                      ,        5,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
21379         {"DRWNNG"                      ,        6,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
21380         {"RSVERR"                      ,        7,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
21381         {"TPAOVR"                      ,        8,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
21382         {"DIPERR"                      ,        9,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
21383         {"SYNCERR"                     ,        10,     1,      523,    "R/W",  0,      0,      0ull,   0ull},
21384         {"CALERR"                      ,        11,     1,      523,    "R/W",  0,      0,      0ull,   0ull},
21385         {"RESERVED_12_63"              ,        12,     52,     523,    "RAZ",  0,      0,      0ull,   0ull},
21386         {"CNT"                         ,        0,      32,     524,    "RO",   0,      1,      0ull,   0},
21387         {"RESERVED_32_63"              ,        32,     32,     524,    "RAZ",  0,      0,      0ull,   0ull},
21388         {"MAX"                         ,        0,      32,     525,    "R/W",  0,      0,      0ull,   0ull},
21389         {"RESERVED_32_63"              ,        32,     32,     525,    "RAZ",  0,      0,      0ull,   0ull},
21390         {"PRTSEL"                      ,        0,      4,      526,    "R/W",  0,      0,      0ull,   0ull},
21391         {"RESERVED_4_63"               ,        4,      60,     526,    "RAZ",  0,      0,      0ull,   0ull},
21392         {"MUX_EN"                      ,        0,      1,      527,    "R/W",  0,      0,      0ull,   0ull},
21393         {"MACRO_EN"                    ,        1,      1,      527,    "R/W",  0,      0,      0ull,   0ull},
21394         {"MAXDIST"                     ,        2,      5,      527,    "R/W",  0,      0,      0ull,   8ull},
21395         {"SET_BOOT"                    ,        7,      1,      527,    "R/W",  0,      0,      0ull,   0ull},
21396         {"CLR_BOOT"                    ,        8,      1,      527,    "R/W",  0,      0,      0ull,   0ull},
21397         {"JITTER"                      ,        9,      3,      527,    "R/W",  0,      0,      0ull,   1ull},
21398         {"TRNTEST"                     ,        12,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
21399         {"RESERVED_13_63"              ,        13,     51,     527,    "RAZ",  0,      0,      0ull,   0ull},
21400         {"BW_CTL"                      ,        0,      5,      528,    "R/W",  0,      1,      0ull,   0},
21401         {"RESERVED_5_63"               ,        5,      59,     528,    "RAZ",  0,      0,      0ull,   0ull},
21402         {"SETTING"                     ,        0,      17,     529,    "RO",   1,      1,      0,      0},
21403         {"RESERVED_17_63"              ,        17,     47,     529,    "RAZ",  0,      0,      0ull,   0ull},
21404         {"INF_EN"                      ,        0,      1,      530,    "R/W",  0,      0,      0ull,   1ull},
21405         {"RESERVED_1_2"                ,        1,      2,      530,    "RAZ",  0,      0,      0ull,   0ull},
21406         {"ST_EN"                       ,        3,      1,      530,    "R/W",  0,      0,      0ull,   1ull},
21407         {"PRTS"                        ,        4,      4,      530,    "R/W",  0,      1,      0ull,   0},
21408         {"RESERVED_8_63"               ,        8,      56,     530,    "RAZ",  0,      0,      0ull,   0ull},
21409         {"IGNORE"                      ,        0,      16,     531,    "R/W",  0,      0,      0ull,   0ull},
21410         {"RESERVED_16_63"              ,        16,     48,     531,    "RAZ",  0,      0,      0ull,   0ull},
21411         {"PRT0"                        ,        0,      4,      532,    "R/W",  1,      1,      0,      0},
21412         {"PRT1"                        ,        4,      4,      532,    "R/W",  1,      1,      0,      0},
21413         {"PRT2"                        ,        8,      4,      532,    "R/W",  1,      1,      0,      0},
21414         {"PRT3"                        ,        12,     4,      532,    "R/W",  1,      1,      0,      0},
21415         {"ODDPAR"                      ,        16,     1,      532,    "R/W",  1,      1,      0,      0},
21416         {"RESERVED_17_63"              ,        17,     47,     532,    "RAZ",  0,      0,      0ull,   0ull},
21417         {"LEN"                         ,        0,      7,      533,    "R/W",  0,      1,      0ull,   0},
21418         {"RESERVED_7_7"                ,        7,      1,      533,    "RAZ",  0,      0,      0ull,   0ull},
21419         {"M"                           ,        8,      8,      533,    "R/W",  0,      1,      0ull,   0},
21420         {"RESERVED_16_63"              ,        16,     48,     533,    "RAZ",  0,      0,      0ull,   0ull},
21421         {"ADR"                         ,        0,      4,      534,    "R/W",  0,      0,      0ull,   0ull},
21422         {"OPC"                         ,        4,      4,      534,    "R/W",  0,      0,      0ull,   0ull},
21423         {"MOD"                         ,        8,      4,      534,    "R/W",  0,      0,      0ull,   0ull},
21424         {"SOP"                         ,        12,     1,      534,    "R/W",  0,      0,      0ull,   0ull},
21425         {"EOP"                         ,        13,     1,      534,    "R/W",  0,      0,      0ull,   0ull},
21426         {"RESERVED_14_63"              ,        14,     50,     534,    "RAZ",  0,      0,      0ull,   0ull},
21427         {"DAT"                         ,        0,      64,     535,    "R/W",  0,      0,      0ull,   0ull},
21428         {"RESERVED_0_2"                ,        0,      3,      536,    "R/W",  0,      0,      0ull,   0ull},
21429         {"IGNTPA"                      ,        3,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
21430         {"RESERVED_4_4"                ,        4,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
21431         {"MINTRN"                      ,        5,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
21432         {"RESERVED_6_63"               ,        6,      58,     536,    "RAZ",  0,      0,      0ull,   0ull},
21433         {"CNT"                         ,        0,      32,     537,    "R/W1C",        0,      0,      0ull,   0ull},
21434         {"RESERVED_32_63"              ,        32,     32,     537,    "RAZ",  0,      0,      0ull,   0ull},
21435         {"INF_EN"                      ,        0,      1,      538,    "R/W",  0,      0,      0ull,   1ull},
21436         {"RESERVED_1_2"                ,        1,      2,      538,    "RAZ",  0,      0,      0ull,   0ull},
21437         {"ST_EN"                       ,        3,      1,      538,    "R/W",  0,      0,      0ull,   1ull},
21438         {"RESERVED_4_63"               ,        4,      60,     538,    "RAZ",  0,      0,      0ull,   0ull},
21439         {"DIPMAX"                      ,        0,      4,      539,    "R/W",  0,      0,      0ull,   0ull},
21440         {"FRMMAX"                      ,        4,      4,      539,    "R/W",  0,      0,      0ull,   0ull},
21441         {"RESERVED_8_63"               ,        8,      56,     539,    "RAZ",  0,      0,      0ull,   0ull},
21442         {"IGNTPA"                      ,        0,      16,     540,    "R/W",  0,      0,      0ull,   0ull},
21443         {"RESERVED_16_63"              ,        16,     48,     540,    "RAZ",  0,      0,      0ull,   0ull},
21444         {"CALPAR0"                     ,        0,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
21445         {"CALPAR1"                     ,        1,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
21446         {"OVRBST"                      ,        2,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
21447         {"DATOVR"                      ,        3,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
21448         {"DIPERR"                      ,        4,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
21449         {"NOSYNC"                      ,        5,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
21450         {"UNXFRM"                      ,        6,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
21451         {"FRMERR"                      ,        7,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
21452         {"RESERVED_8_63"               ,        8,      56,     541,    "RAZ",  0,      0,      0ull,   0ull},
21453         {"CALPAR0"                     ,        0,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
21454         {"CALPAR1"                     ,        1,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
21455         {"OVRBST"                      ,        2,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
21456         {"DATOVR"                      ,        3,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
21457         {"DIPERR"                      ,        4,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
21458         {"NOSYNC"                      ,        5,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
21459         {"UNXFRM"                      ,        6,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
21460         {"FRMERR"                      ,        7,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
21461         {"SYNCERR"                     ,        8,      1,      542,    "RO",   0,      0,      0ull,   0ull},
21462         {"RESERVED_9_63"               ,        9,      55,     542,    "RAZ",  0,      0,      0ull,   0ull},
21463         {"CALPAR0"                     ,        0,      1,      543,    "R/W",  0,      0,      0ull,   0ull},
21464         {"CALPAR1"                     ,        1,      1,      543,    "R/W",  0,      0,      0ull,   0ull},
21465         {"OVRBST"                      ,        2,      1,      543,    "R/W",  0,      0,      0ull,   0ull},
21466         {"DATOVR"                      ,        3,      1,      543,    "R/W",  0,      0,      0ull,   0ull},
21467         {"DIPERR"                      ,        4,      1,      543,    "R/W",  0,      0,      0ull,   0ull},
21468         {"NOSYNC"                      ,        5,      1,      543,    "R/W",  0,      0,      0ull,   0ull},
21469         {"UNXFRM"                      ,        6,      1,      543,    "R/W",  0,      0,      0ull,   0ull},
21470         {"FRMERR"                      ,        7,      1,      543,    "R/W",  0,      0,      0ull,   0ull},
21471         {"RESERVED_8_63"               ,        8,      56,     543,    "RAZ",  0,      0,      0ull,   0ull},
21472         {"MINB"                        ,        0,      9,      544,    "R/W",  0,      0,      0ull,   0ull},
21473         {"RESERVED_9_63"               ,        9,      55,     544,    "RAZ",  0,      0,      0ull,   0ull},
21474         {"PRT0"                        ,        0,      4,      545,    "R/W",  1,      1,      0,      0},
21475         {"PRT1"                        ,        4,      4,      545,    "R/W",  1,      1,      0,      0},
21476         {"PRT2"                        ,        8,      4,      545,    "R/W",  1,      1,      0,      0},
21477         {"PRT3"                        ,        12,     4,      545,    "R/W",  1,      1,      0,      0},
21478         {"ODDPAR"                      ,        16,     1,      545,    "R/W",  1,      1,      0,      0},
21479         {"RESERVED_17_63"              ,        17,     47,     545,    "RAZ",  0,      0,      0ull,   0ull},
21480         {"MAX_T"                       ,        0,      16,     546,    "R/W",  0,      1,      0ull,   0},
21481         {"ALPHA"                       ,        16,     16,     546,    "R/W",  0,      1,      0ull,   0},
21482         {"RESERVED_32_63"              ,        32,     32,     546,    "RAZ",  0,      0,      0ull,   0ull},
21483         {"LEN"                         ,        0,      7,      547,    "R/W",  0,      1,      0ull,   0},
21484         {"RESERVED_7_7"                ,        7,      1,      547,    "RAZ",  0,      0,      0ull,   0ull},
21485         {"M"                           ,        8,      8,      547,    "R/W",  0,      1,      0ull,   0},
21486         {"RESERVED_16_63"              ,        16,     48,     547,    "RAZ",  0,      0,      0ull,   0ull},
21487         {"CNT"                         ,        0,      32,     548,    "RO",   0,      0,      0ull,   0ull},
21488         {"RESERVED_32_63"              ,        32,     32,     548,    "RAZ",  0,      0,      0ull,   0ull},
21489         {"CNT"                         ,        0,      32,     549,    "RO",   0,      0,      0ull,   0ull},
21490         {"RESERVED_32_63"              ,        32,     32,     549,    "RAZ",  0,      0,      0ull,   0ull},
21491         {"BCKPRS"                      ,        0,      4,      550,    "R/W",  0,      0,      0ull,   0ull},
21492         {"CLR"                         ,        4,      1,      550,    "WR0",  0,      0,      0ull,   0ull},
21493         {"RESERVED_5_63"               ,        5,      59,     550,    "RAZ",  0,      0,      0ull,   0ull},
21494         {"CNT"                         ,        0,      32,     551,    "RO",   0,      0,      0ull,   0ull},
21495         {"RESERVED_32_63"              ,        32,     32,     551,    "RAZ",  0,      0,      0ull,   0ull},
21496         {"INTERVAL"                    ,        0,      22,     552,    "RO",   1,      0,      0,      0ull},
21497         {"RESERVED_22_23"              ,        22,     2,      552,    "RAZ",  1,      0,      0,      0ull},
21498         {"COUNT"                       ,        24,     22,     552,    "RO",   1,      0,      0,      0ull},
21499         {"RESERVED_46_46"              ,        46,     1,      552,    "RAZ",  1,      0,      0,      0ull},
21500         {"ENA"                         ,        47,     1,      552,    "RO",   1,      0,      0,      0ull},
21501         {"RESERVED_48_63"              ,        48,     16,     552,    "RAZ",  1,      0,      0,      0ull},
21502         {"BSIZE"                       ,        0,      20,     553,    "RO",   1,      0,      0,      0ull},
21503         {"BASE"                        ,        20,     31,     553,    "RO",   1,      0,      0,      0ull},
21504         {"BUCKET"                      ,        51,     13,     553,    "RO",   1,      0,      0,      0ull},
21505         {"BUCKET"                      ,        0,      7,      554,    "RO",   1,      0,      0,      0ull},
21506         {"RESERVED_7_7"                ,        7,      1,      554,    "RAZ",  1,      0,      0,      0ull},
21507         {"CSIZE"                       ,        8,      13,     554,    "RO",   1,      0,      0,      0ull},
21508         {"CPOOL"                       ,        21,     3,      554,    "RO",   1,      0,      0,      0ull},
21509         {"RESERVED_24_63"              ,        24,     40,     554,    "RAZ",  1,      0,      0,      0ull},
21510         {"RING"                        ,        0,      4,      555,    "R/W",  0,      0,      0ull,   0ull},
21511         {"NUM_BUCKETS"                 ,        4,      20,     555,    "R/W",  0,      0,      0ull,   0ull},
21512         {"FIRST_BUCKET"                ,        24,     31,     555,    "R/W",  0,      0,      0ull,   0ull},
21513         {"RESERVED_55_63"              ,        55,     9,      555,    "RAZ",  1,      0,      0,      0ull},
21514         {"RING"                        ,        0,      4,      556,    "R/W",  0,      0,      0ull,   0ull},
21515         {"INTERVAL"                    ,        4,      22,     556,    "R/W",  0,      0,      0ull,   0ull},
21516         {"WORDS_PER_CHUNK"             ,        26,     13,     556,    "R/W",  0,      0,      0ull,   0ull},
21517         {"POOL"                        ,        39,     3,      556,    "R/W",  0,      0,      0ull,   0ull},
21518         {"ENABLE"                      ,        42,     1,      556,    "R/W",  0,      0,      0ull,   0ull},
21519         {"RESERVED_43_63"              ,        43,     21,     556,    "RAZ",  1,      0,      0,      0ull},
21520         {"CTL"                         ,        0,      1,      557,    "RO",   1,      0,      0,      0ull},
21521         {"NCB"                         ,        1,      1,      557,    "RO",   1,      0,      0,      0ull},
21522         {"STA"                         ,        2,      2,      557,    "RO",   1,      0,      0,      0ull},
21523         {"RESERVED_4_63"               ,        4,      60,     557,    "RAZ",  1,      0,      0,      0ull},
21524         {"MASK"                        ,        0,      16,     558,    "R/W1C",        0,      0,      0ull,   0ull},
21525         {"RESERVED_16_63"              ,        16,     48,     558,    "RAZ",  1,      0,      0,      0ull},
21526         {"ENABLE_TIMERS"               ,        0,      1,      559,    "R/W",  0,      0,      0ull,   0ull},
21527         {"ENABLE_DWB"                  ,        1,      1,      559,    "R/W",  0,      0,      0ull,   0ull},
21528         {"RESET"                       ,        2,      1,      559,    "RAZ",  0,      0,      0ull,   0ull},
21529         {"RESERVED_3_63"               ,        3,      61,     559,    "RAZ",  1,      0,      0,      0ull},
21530         {"MASK"                        ,        0,      16,     560,    "R/W",  0,      0,      0ull,   0ull},
21531         {"RESERVED_16_63"              ,        16,     48,     560,    "RAZ",  1,      0,      0,      0ull},
21532         {"INDEX"                       ,        0,      8,      561,    "R/W",  0,      0,      0ull,   0ull},
21533         {"INC"                         ,        8,      8,      561,    "R/W",  0,      0,      0ull,   0ull},
21534         {"RESERVED_16_63"              ,        16,     48,     561,    "RAZ",  1,      0,      0,      0ull},
21535         {"TDF0"                        ,        0,      1,      562,    "RO",   0,      0,      0ull,   0ull},
21536         {"TDF1"                        ,        1,      1,      562,    "RO",   0,      0,      0ull,   0ull},
21537         {"TCF"                         ,        2,      1,      562,    "RO",   0,      0,      0ull,   0ull},
21538         {"RESERVED_3_63"               ,        3,      61,     562,    "RAZ",  0,      0,      0ull,   0ull},
21539         {"ENA"                         ,        0,      1,      563,    "R/W",  0,      0,      0ull,   0ull},
21540         {"WRAP"                        ,        1,      1,      563,    "R/W",  0,      0,      0ull,   0ull},
21541         {"TRIG_CTL"                    ,        2,      2,      563,    "R/W",  0,      0,      0ull,   0ull},
21542         {"TIME_GRN"                    ,        4,      3,      563,    "R/W",  0,      0,      0ull,   0ull},
21543         {"FULL_THR"                    ,        7,      2,      563,    "R/W",  0,      0,      0ull,   0ull},
21544         {"CIU_TRG"                     ,        9,      1,      563,    "R/W",  0,      0,      0ull,   0ull},
21545         {"CIU_THR"                     ,        10,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
21546         {"MCD0_TRG"                    ,        11,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
21547         {"MCD0_THR"                    ,        12,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
21548         {"MCD0_ENA"                    ,        13,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
21549         {"IGNORE_O"                    ,        14,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
21550         {"RESERVED_15_63"              ,        15,     49,     563,    "RAZ",  0,      0,      0ull,   0ull},
21551         {"WPTR"                        ,        0,      8,      564,    "RO",   0,      0,      0ull,   0ull},
21552         {"RPTR"                        ,        8,      8,      564,    "RO",   0,      0,      0ull,   0ull},
21553         {"CYCLES"                      ,        16,     48,     564,    "RO",   0,      0,      0ull,   0ull},
21554         {"ADR"                         ,        0,      36,     565,    "R/W",  0,      1,      0ull,   0},
21555         {"RESERVED_36_63"              ,        36,     28,     565,    "RAZ",  0,      0,      0ull,   0ull},
21556         {"ADR"                         ,        0,      36,     566,    "R/W",  0,      0,      0ull,   0ull},
21557         {"RESERVED_36_63"              ,        36,     28,     566,    "RAZ",  0,      0,      0ull,   0ull},
21558         {"DWB"                         ,        0,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21559         {"PL2"                         ,        1,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21560         {"PSL1"                        ,        2,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21561         {"LDD"                         ,        3,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21562         {"LDI"                         ,        4,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21563         {"LDT"                         ,        5,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21564         {"STF"                         ,        6,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21565         {"STC"                         ,        7,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21566         {"STP"                         ,        8,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21567         {"STT"                         ,        9,      1,      567,    "R/W",  0,      0,      0ull,   1ull},
21568         {"IOBLD8"                      ,        10,     1,      567,    "R/W",  0,      0,      0ull,   1ull},
21569         {"IOBLD16"                     ,        11,     1,      567,    "R/W",  0,      0,      0ull,   1ull},
21570         {"IOBLD32"                     ,        12,     1,      567,    "R/W",  0,      0,      0ull,   1ull},
21571         {"IOBLD64"                     ,        13,     1,      567,    "R/W",  0,      0,      0ull,   1ull},
21572         {"IOBST"                       ,        14,     1,      567,    "R/W",  0,      0,      0ull,   1ull},
21573         {"IOBDMA"                      ,        15,     1,      567,    "R/W",  0,      0,      0ull,   1ull},
21574         {"RESERVED_16_63"              ,        16,     48,     567,    "RAZ",  0,      0,      0ull,   0ull},
21575         {"MIO"                         ,        0,      1,      568,    "R/W",  0,      0,      0ull,   1ull},
21576         {"ILLEGAL3"                    ,        1,      2,      568,    "R/W",  0,      0,      0ull,   3ull},
21577         {"PCI"                         ,        3,      1,      568,    "R/W",  0,      0,      0ull,   1ull},
21578         {"KEY"                         ,        4,      1,      568,    "R/W",  0,      0,      0ull,   1ull},
21579         {"FPA"                         ,        5,      1,      568,    "R/W",  0,      0,      0ull,   1ull},
21580         {"DFA"                         ,        6,      1,      568,    "R/W",  0,      0,      0ull,   1ull},
21581         {"ZIP"                         ,        7,      1,      568,    "R/W",  0,      0,      0ull,   1ull},
21582         {"RNG"                         ,        8,      1,      568,    "R/W",  0,      0,      0ull,   1ull},
21583         {"ILLEGAL2"                    ,        9,      3,      568,    "R/W",  0,      0,      0ull,   7ull},
21584         {"POW"                         ,        12,     1,      568,    "R/W",  0,      0,      0ull,   1ull},
21585         {"ILLEGAL"                     ,        13,     19,     568,    "R/W",  0,      0,      0ull,   524287ull},
21586         {"RESERVED_32_63"              ,        32,     32,     568,    "RAZ",  0,      0,      0ull,   0ull},
21587         {"PP"                          ,        0,      16,     569,    "R/W",  0,      0,      0ull,   0ull},
21588         {"PKI"                         ,        16,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
21589         {"PKO"                         ,        17,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
21590         {"IOBREQ"                      ,        18,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
21591         {"DWB"                         ,        19,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
21592         {"RESERVED_20_63"              ,        20,     44,     569,    "RAZ",  0,      0,      0ull,   0ull},
21593         {"CIU_TRG"                     ,        0,      1,      570,    "R/W1C",        0,      0,      0ull,   0ull},
21594         {"CIU_THR"                     ,        1,      1,      570,    "R/W1C",        0,      0,      0ull,   0ull},
21595         {"MCD0_TRG"                    ,        2,      1,      570,    "R/W1C",        0,      0,      0ull,   0ull},
21596         {"MCD0_THR"                    ,        3,      1,      570,    "R/W1C",        0,      0,      0ull,   0ull},
21597         {"RESERVED_4_63"               ,        4,      60,     570,    "RAZ",  0,      0,      0ull,   0ull},
21598         {"DATA"                        ,        0,      64,     571,    "RO",   0,      0,      0ull,   0ull},
21599         {"ADR"                         ,        0,      36,     572,    "R/W",  0,      1,      0ull,   0},
21600         {"RESERVED_36_63"              ,        36,     28,     572,    "RAZ",  0,      0,      0ull,   0ull},
21601         {"ADR"                         ,        0,      36,     573,    "R/W",  0,      0,      0ull,   0ull},
21602         {"RESERVED_36_63"              ,        36,     28,     573,    "RAZ",  0,      0,      0ull,   0ull},
21603         {"DWB"                         ,        0,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21604         {"PL2"                         ,        1,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21605         {"PSL1"                        ,        2,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21606         {"LDD"                         ,        3,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21607         {"LDI"                         ,        4,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21608         {"LDT"                         ,        5,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21609         {"STF"                         ,        6,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21610         {"STC"                         ,        7,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21611         {"STP"                         ,        8,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21612         {"STT"                         ,        9,      1,      574,    "R/W",  0,      0,      0ull,   1ull},
21613         {"IOBLD8"                      ,        10,     1,      574,    "R/W",  0,      0,      0ull,   1ull},
21614         {"IOBLD16"                     ,        11,     1,      574,    "R/W",  0,      0,      0ull,   1ull},
21615         {"IOBLD32"                     ,        12,     1,      574,    "R/W",  0,      0,      0ull,   1ull},
21616         {"IOBLD64"                     ,        13,     1,      574,    "R/W",  0,      0,      0ull,   1ull},
21617         {"IOBST"                       ,        14,     1,      574,    "R/W",  0,      0,      0ull,   1ull},
21618         {"IOBDMA"                      ,        15,     1,      574,    "R/W",  0,      0,      0ull,   1ull},
21619         {"RESERVED_16_63"              ,        16,     48,     574,    "RAZ",  0,      0,      0ull,   0ull},
21620         {"MIO"                         ,        0,      1,      575,    "R/W",  0,      0,      0ull,   1ull},
21621         {"ILLEGAL3"                    ,        1,      2,      575,    "R/W",  0,      0,      0ull,   3ull},
21622         {"PCI"                         ,        3,      1,      575,    "R/W",  0,      0,      0ull,   1ull},
21623         {"KEY"                         ,        4,      1,      575,    "R/W",  0,      0,      0ull,   1ull},
21624         {"FPA"                         ,        5,      1,      575,    "R/W",  0,      0,      0ull,   1ull},
21625         {"DFA"                         ,        6,      1,      575,    "R/W",  0,      0,      0ull,   1ull},
21626         {"ZIP"                         ,        7,      1,      575,    "R/W",  0,      0,      0ull,   1ull},
21627         {"RNG"                         ,        8,      1,      575,    "R/W",  0,      0,      0ull,   1ull},
21628         {"ILLEGAL2"                    ,        9,      3,      575,    "R/W",  0,      0,      0ull,   7ull},
21629         {"POW"                         ,        12,     1,      575,    "R/W",  0,      0,      0ull,   1ull},
21630         {"ILLEGAL"                     ,        13,     19,     575,    "R/W",  0,      0,      0ull,   524287ull},
21631         {"RESERVED_32_63"              ,        32,     32,     575,    "RAZ",  0,      0,      0ull,   0ull},
21632         {"PP"                          ,        0,      16,     576,    "R/W",  0,      0,      0ull,   0ull},
21633         {"PKI"                         ,        16,     1,      576,    "R/W",  0,      0,      0ull,   0ull},
21634         {"PKO"                         ,        17,     1,      576,    "R/W",  0,      0,      0ull,   0ull},
21635         {"IOBREQ"                      ,        18,     1,      576,    "R/W",  0,      0,      0ull,   0ull},
21636         {"DWB"                         ,        19,     1,      576,    "R/W",  0,      0,      0ull,   0ull},
21637         {"RESERVED_20_63"              ,        20,     44,     576,    "RAZ",  0,      0,      0ull,   0ull},
21638         {"ADR"                         ,        0,      36,     577,    "R/W",  0,      1,      0ull,   0},
21639         {"RESERVED_36_63"              ,        36,     28,     577,    "RAZ",  0,      0,      0ull,   0ull},
21640         {"ADR"                         ,        0,      36,     578,    "R/W",  0,      0,      0ull,   0ull},
21641         {"RESERVED_36_63"              ,        36,     28,     578,    "RAZ",  0,      0,      0ull,   0ull},
21642         {"DWB"                         ,        0,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21643         {"PL2"                         ,        1,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21644         {"PSL1"                        ,        2,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21645         {"LDD"                         ,        3,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21646         {"LDI"                         ,        4,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21647         {"LDT"                         ,        5,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21648         {"STF"                         ,        6,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21649         {"STC"                         ,        7,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21650         {"STP"                         ,        8,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21651         {"STT"                         ,        9,      1,      579,    "R/W",  0,      0,      0ull,   1ull},
21652         {"IOBLD8"                      ,        10,     1,      579,    "R/W",  0,      0,      0ull,   1ull},
21653         {"IOBLD16"                     ,        11,     1,      579,    "R/W",  0,      0,      0ull,   1ull},
21654         {"IOBLD32"                     ,        12,     1,      579,    "R/W",  0,      0,      0ull,   1ull},
21655         {"IOBLD64"                     ,        13,     1,      579,    "R/W",  0,      0,      0ull,   1ull},
21656         {"IOBST"                       ,        14,     1,      579,    "R/W",  0,      0,      0ull,   1ull},
21657         {"IOBDMA"                      ,        15,     1,      579,    "R/W",  0,      0,      0ull,   1ull},
21658         {"RESERVED_16_63"              ,        16,     48,     579,    "RAZ",  0,      0,      0ull,   0ull},
21659         {"MIO"                         ,        0,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
21660         {"ILLEGAL3"                    ,        1,      2,      580,    "R/W",  0,      0,      0ull,   3ull},
21661         {"PCI"                         ,        3,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
21662         {"KEY"                         ,        4,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
21663         {"FPA"                         ,        5,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
21664         {"DFA"                         ,        6,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
21665         {"ZIP"                         ,        7,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
21666         {"RNG"                         ,        8,      1,      580,    "R/W",  0,      0,      0ull,   1ull},
21667         {"ILLEGAL2"                    ,        9,      3,      580,    "R/W",  0,      0,      0ull,   7ull},
21668         {"POW"                         ,        12,     1,      580,    "R/W",  0,      0,      0ull,   1ull},
21669         {"ILLEGAL"                     ,        13,     19,     580,    "R/W",  0,      0,      0ull,   524287ull},
21670         {"RESERVED_32_63"              ,        32,     32,     580,    "RAZ",  0,      0,      0ull,   0ull},
21671         {"PP"                          ,        0,      16,     581,    "R/W",  0,      0,      0ull,   0ull},
21672         {"PKI"                         ,        16,     1,      581,    "R/W",  0,      0,      0ull,   0ull},
21673         {"PKO"                         ,        17,     1,      581,    "R/W",  0,      0,      0ull,   0ull},
21674         {"IOBREQ"                      ,        18,     1,      581,    "R/W",  0,      0,      0ull,   0ull},
21675         {"DWB"                         ,        19,     1,      581,    "R/W",  0,      0,      0ull,   0ull},
21676         {"RESERVED_20_63"              ,        20,     44,     581,    "RAZ",  0,      0,      0ull,   0ull},
21677         {"ZIP_CTL"                     ,        0,      4,      582,    "RO",   1,      0,      0,      0ull},
21678         {"ZIP_CORE"                    ,        4,      27,     582,    "RO",   1,      0,      0,      0ull},
21679         {"RESERVED_31_63"              ,        31,     33,     582,    "RAZ",  1,      0,      0,      0ull},
21680         {"PTR"                         ,        0,      33,     583,    "R/W",  0,      0,      0ull,   0ull},
21681         {"SIZE"                        ,        33,     13,     583,    "R/W",  0,      0,      0ull,   0ull},
21682         {"POOL"                        ,        46,     3,      583,    "R/W",  0,      0,      0ull,   0ull},
21683         {"DWB"                         ,        49,     9,      583,    "R/W",  0,      0,      0ull,   0ull},
21684         {"RESERVED_58_63"              ,        58,     6,      583,    "RAZ",  0,      0,      0ull,   0ull},
21685         {"RESET"                       ,        0,      1,      584,    "RAZ",  0,      0,      0ull,   0ull},
21686         {"FORCECLK"                    ,        1,      1,      584,    "R/W",  0,      0,      0ull,   0ull},
21687         {"RESERVED_2_63"               ,        2,      62,     584,    "RAZ",  0,      0,      0ull,   0ull},
21688         {"DISABLED"                    ,        0,      1,      585,    "RO",   0,      0,      0ull,   0ull},
21689         {"RESERVED_1_7"                ,        1,      7,      585,    "RAZ",  0,      0,      0ull,   0ull},
21690         {"CTXSIZE"                     ,        8,      12,     585,    "RO",   0,      0,      1536ull,        1536ull},
21691         {"ONFSIZE"                     ,        20,     12,     585,    "RO",   0,      0,      512ull, 512ull},
21692         {"DEPTH"                       ,        32,     16,     585,    "RO",   0,      0,      31744ull,       31744ull},
21693         {"RESERVED_48_63"              ,        48,     16,     585,    "RAZ",  1,      0,      0,      0ull},
21694         {"ASSERTS"                     ,        0,      14,     586,    "RO",   0,      0,      0ull,   0ull},
21695         {"RESERVED_14_63"              ,        14,     50,     586,    "RAZ",  1,      0,      0,      0ull},
21696         {"DOORBELL"                    ,        0,      1,      587,    "R/W1C",        0,      0,      0ull,   0ull},
21697         {"RESERVED_1_63"               ,        1,      63,     587,    "RAZ",  1,      0,      0,      0ull},
21698         {"DOORBELL"                    ,        0,      1,      588,    "R/W",  0,      0,      0ull,   0ull},
21699         {"RESERVED_1_63"               ,        1,      63,     588,    "RAZ",  1,      0,      0,      0ull},
21700         {NULL,0,0,0,0,0,0,0,0}
21701 };
21702 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xxp1[] = {
21703          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
21704         {"cvmx_asx#_int_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      4,      0},
21705         {"cvmx_asx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      4,      4},
21706         {"cvmx_asx#_prt_loop"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      3,      8},
21707         {"cvmx_asx#_rld_bypass"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      2,      11},
21708         {"cvmx_asx#_rld_bypass_setting",        CVMX_CSR_DB_TYPE_RSL,   64,     8,      2,      13},
21709         {"cvmx_asx#_rld_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     3,      15},
21710         {"cvmx_asx#_rld_data_drv"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     12,     3,      18},
21711         {"cvmx_asx#_rld_nctl_strong"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     2,      21},
21712         {"cvmx_asx#_rld_nctl_weak"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     16,     2,      23},
21713         {"cvmx_asx#_rld_pctl_strong"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     18,     2,      25},
21714         {"cvmx_asx#_rld_pctl_weak"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     20,     2,      27},
21715         {"cvmx_asx#_rld_setting"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     22,     6,      29},
21716         {"cvmx_asx#_rx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     24,     2,      35},
21717         {"cvmx_asx#_rx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     32,     2,      37},
21718         {"cvmx_asx#_tx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     34,     2,      39},
21719         {"cvmx_asx#_tx_comp_byp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     42,     4,      41},
21720         {"cvmx_asx#_tx_hi_water#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     44,     2,      45},
21721         {"cvmx_asx#_tx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     52,     2,      47},
21722         {"cvmx_asx0_dbg_data_drv"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     54,     3,      49},
21723         {"cvmx_asx0_dbg_data_enable"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     55,     2,      52},
21724         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     56,     2,      54},
21725         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     57,     2,      56},
21726         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     58,     2,      58},
21727         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     59,     2,      60},
21728         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     60,     15,     62},
21729         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     93,     2,      77},
21730         {"cvmx_ciu_int#_en4_0"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     126,    15,     79},
21731         {"cvmx_ciu_int#_en4_1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     142,    2,      94},
21732         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     158,    15,     96},
21733         {"cvmx_ciu_int#_sum4"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     191,    15,     111},
21734         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     207,    2,      126},
21735         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     208,    2,      128},
21736         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     224,    2,      130},
21737         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     240,    2,      132},
21738         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     241,    2,      134},
21739         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     242,    2,      136},
21740         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     243,    1,      138},
21741         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     259,    3,      139},
21742         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     260,    2,      142},
21743         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     261,    4,      144},
21744         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     262,    2,      148},
21745         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     263,    3,      150},
21746         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     267,    7,      153},
21747         {"cvmx_dbg_data"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     283,    5,      160},
21748         {"cvmx_dfa_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     284,    4,      165},
21749         {"cvmx_dfa_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     285,    10,     169},
21750         {"cvmx_dfa_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     286,    5,      179},
21751         {"cvmx_dfa_dbell"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     287,    2,      184},
21752         {"cvmx_dfa_difctl"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     288,    4,      186},
21753         {"cvmx_dfa_difrdptr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     289,    3,      190},
21754         {"cvmx_dfa_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     290,    21,     193},
21755         {"cvmx_dfa_memcfg0"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     291,    20,     214},
21756         {"cvmx_dfa_memcfg1"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     292,    11,     234},
21757         {"cvmx_dfa_memcfg2"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     293,    8,      245},
21758         {"cvmx_dfa_memfadr"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     294,    6,      253},
21759         {"cvmx_dfa_memfcr"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     295,    6,      259},
21760         {"cvmx_dfa_memrld"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     296,    2,      265},
21761         {"cvmx_dfa_ncbctl"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     297,    8,      267},
21762         {"cvmx_dfa_rodt_comp_ctl"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     298,    6,      275},
21763         {"cvmx_dfa_sbd_dbg0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     299,    1,      281},
21764         {"cvmx_dfa_sbd_dbg1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     300,    1,      282},
21765         {"cvmx_dfa_sbd_dbg2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     301,    1,      283},
21766         {"cvmx_dfa_sbd_dbg3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     302,    1,      284},
21767         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     303,    6,      285},
21768         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     304,    7,      291},
21769         {"cvmx_fpa_fpf#_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     305,    3,      298},
21770         {"cvmx_fpa_fpf#_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     312,    2,      301},
21771         {"cvmx_fpa_fpf0_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     319,    3,      303},
21772         {"cvmx_fpa_fpf0_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     320,    2,      306},
21773         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     321,    29,     308},
21774         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     322,    29,     337},
21775         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     323,    2,      366},
21776         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     331,    2,      368},
21777         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     339,    3,      370},
21778         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     340,    3,      373},
21779         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     341,    2,      376},
21780         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     342,    2,      378},
21781         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     343,    8,      380},
21782         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     345,    2,      388},
21783         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     347,    3,      390},
21784         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     349,    2,      393},
21785         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     351,    5,      395},
21786         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     359,    1,      400},
21787         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     367,    1,      401},
21788         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     375,    1,      402},
21789         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     383,    1,      403},
21790         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     391,    1,      404},
21791         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     399,    1,      405},
21792         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     407,    2,      406},
21793         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     415,    4,      408},
21794         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     423,    2,      412},
21795         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     431,    11,     414},
21796         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     439,    10,     425},
21797         {"cvmx_gmx#_rx#_frm_max"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     447,    2,      435},
21798         {"cvmx_gmx#_rx#_frm_min"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     455,    2,      437},
21799         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     463,    2,      439},
21800         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     471,    21,     441},
21801         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     479,    21,     462},
21802         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     487,    2,      483},
21803         {"cvmx_gmx#_rx#_pause_drop_time",       CVMX_CSR_DB_TYPE_RSL,   64,     495,    2,      485},
21804         {"cvmx_gmx#_rx#_rx_inbnd"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     503,    4,      487},
21805         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     511,    2,      491},
21806         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     519,    2,      493},
21807         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     527,    2,      495},
21808         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     535,    2,      497},
21809         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     543,    2,      499},
21810         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     551,    2,      501},
21811         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     559,    2,      503},
21812         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     567,    2,      505},
21813         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     575,    2,      507},
21814         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     583,    2,      509},
21815         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     591,    4,      511},
21816         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     599,    2,      515},
21817         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     607,    2,      517},
21818         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     615,    2,      519},
21819         {"cvmx_gmx#_rx_pass_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     623,    2,      521},
21820         {"cvmx_gmx#_rx_pass_map#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     625,    2,      523},
21821         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     657,    3,      525},
21822         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     659,    2,      528},
21823         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     661,    2,      530},
21824         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     669,    3,      532},
21825         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     671,    5,      535},
21826         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     679,    2,      540},
21827         {"cvmx_gmx#_tx#_clk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     687,    2,      542},
21828         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     695,    3,      544},
21829         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     703,    2,      547},
21830         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     711,    2,      549},
21831         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     719,    2,      551},
21832         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     727,    2,      553},
21833         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     735,    2,      555},
21834         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     743,    2,      557},
21835         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     751,    2,      559},
21836         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     759,    2,      561},
21837         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     767,    2,      563},
21838         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     775,    2,      565},
21839         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     783,    2,      567},
21840         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     791,    2,      569},
21841         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     799,    2,      571},
21842         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     807,    2,      573},
21843         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     815,    2,      575},
21844         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     823,    2,      577},
21845         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     831,    2,      579},
21846         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     839,    2,      581},
21847         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     847,    2,      583},
21848         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     855,    2,      585},
21849         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     857,    2,      587},
21850         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     859,    2,      589},
21851         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     861,    3,      591},
21852         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     863,    8,      594},
21853         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     865,    8,      602},
21854         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     867,    2,      610},
21855         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     869,    2,      612},
21856         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     871,    4,      614},
21857         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     873,    2,      618},
21858         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     875,    2,      620},
21859         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     877,    2,      622},
21860         {"cvmx_gmx#_tx_spi_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     879,    3,      624},
21861         {"cvmx_gmx#_tx_spi_drain"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     881,    2,      627},
21862         {"cvmx_gmx#_tx_spi_max"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     883,    4,      629},
21863         {"cvmx_gmx#_tx_spi_round#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     885,    2,      633},
21864         {"cvmx_gmx#_tx_spi_thresh"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     949,    2,      635},
21865         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     951,    7,      637},
21866         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     967,    2,      644},
21867         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     968,    2,      646},
21868         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     969,    2,      648},
21869         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     970,    2,      650},
21870         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     971,    19,     652},
21871         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     972,    6,      671},
21872         {"cvmx_iob_dwb_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     973,    3,      677},
21873         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     974,    3,      680},
21874         {"cvmx_iob_i2c_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     975,    3,      683},
21875         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     976,    5,      686},
21876         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     977,    5,      691},
21877         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     978,    1,      696},
21878         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     979,    1,      697},
21879         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     980,    7,      698},
21880         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     981,    7,      705},
21881         {"cvmx_iob_n2c_l2c_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     982,    3,      712},
21882         {"cvmx_iob_n2c_rsp_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     983,    3,      715},
21883         {"cvmx_iob_outb_com_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     984,    3,      718},
21884         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     985,    5,      721},
21885         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     986,    5,      726},
21886         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     987,    1,      731},
21887         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     988,    1,      732},
21888         {"cvmx_iob_outb_fpa_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     989,    3,      733},
21889         {"cvmx_iob_outb_req_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     990,    3,      736},
21890         {"cvmx_iob_p2c_req_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     991,    3,      739},
21891         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     992,    2,      742},
21892         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     993,    2,      744},
21893         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     994,    2,      746},
21894         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     995,    2,      748},
21895         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     996,    17,     750},
21896         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     997,    2,      767},
21897         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     998,    1,      769},
21898         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     999,    12,     770},
21899         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1000,   11,     782},
21900         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1001,   11,     793},
21901         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     1002,   2,      804},
21902         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1003,   2,      806},
21903         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1004,   2,      808},
21904         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1005,   3,      810},
21905         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     1041,   2,      813},
21906         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     1077,   6,      815},
21907         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     1078,   5,      821},
21908         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1079,   6,      826},
21909         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1080,   7,      832},
21910         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1081,   2,      839},
21911         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     1089,   2,      841},
21912         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1090,   3,      843},
21913         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1091,   5,      846},
21914         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     1099,   3,      851},
21915         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1100,   2,      854},
21916         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1101,   2,      856},
21917         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1102,   2,      858},
21918         {"cvmx_key_bist_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1103,   4,      860},
21919         {"cvmx_key_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1104,   3,      864},
21920         {"cvmx_key_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1105,   5,      867},
21921         {"cvmx_key_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1106,   5,      872},
21922         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1107,   7,      877},
21923         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1108,   5,      884},
21924         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1109,   8,      889},
21925         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1110,   10,     897},
21926         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1111,   8,      907},
21927         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1112,   5,      915},
21928         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1113,   4,      920},
21929         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1114,   2,      924},
21930         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1115,   14,     926},
21931         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1116,   19,     940},
21932         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1117,   3,      959},
21933         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1118,   3,      962},
21934         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1119,   2,      965},
21935         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1123,   17,     967},
21936         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1124,   5,      984},
21937         {"cvmx_l2c_spar1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1125,   5,      989},
21938         {"cvmx_l2c_spar2"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1126,   5,      994},
21939         {"cvmx_l2c_spar3"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1127,   5,      999},
21940         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1128,   2,      1004},
21941         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1129,   3,      1006},
21942         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1130,   2,      1009},
21943         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1131,   2,      1011},
21944         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1132,   2,      1013},
21945         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1133,   7,      1015},
21946         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1134,   5,      1022},
21947         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1135,   3,      1027},
21948         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1136,   3,      1030},
21949         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1137,   2,      1033},
21950         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1138,   2,      1035},
21951         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1139,   2,      1037},
21952         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1140,   6,      1039},
21953         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1141,   14,     1045},
21954         {"cvmx_led_blink"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1142,   2,      1059},
21955         {"cvmx_led_clk_phase"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1143,   2,      1061},
21956         {"cvmx_led_cylon"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1144,   2,      1063},
21957         {"cvmx_led_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1145,   2,      1065},
21958         {"cvmx_led_en"                 ,        CVMX_CSR_DB_TYPE_RSL,   64,     1146,   2,      1067},
21959         {"cvmx_led_polarity"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1147,   2,      1069},
21960         {"cvmx_led_prt"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1148,   2,      1071},
21961         {"cvmx_led_prt_fmt"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1149,   2,      1073},
21962         {"cvmx_led_prt_status#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1150,   2,      1075},
21963         {"cvmx_led_udd_cnt#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1158,   2,      1077},
21964         {"cvmx_led_udd_dat#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1160,   2,      1079},
21965         {"cvmx_led_udd_dat_clr#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1162,   2,      1081},
21966         {"cvmx_led_udd_dat_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1164,   2,      1083},
21967         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1166,   7,      1085},
21968         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1167,   19,     1092},
21969         {"cvmx_lmc#_ctl1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1168,   4,      1111},
21970         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1169,   2,      1115},
21971         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1170,   2,      1117},
21972         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1171,   18,     1119},
21973         {"cvmx_lmc#_delay_cfg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1172,   6,      1137},
21974         {"cvmx_lmc#_dual_memcfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1173,   5,      1143},
21975         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1174,   5,      1148},
21976         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1175,   6,      1153},
21977         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1176,   2,      1159},
21978         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1177,   2,      1161},
21979         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1178,   14,     1163},
21980         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1179,   9,      1177},
21981         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1180,   2,      1186},
21982         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1181,   2,      1188},
21983         {"cvmx_lmc#_pll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1182,   12,     1190},
21984         {"cvmx_lmc#_pll_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1183,   3,      1202},
21985         {"cvmx_lmc#_rodt_comp_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1184,   6,      1205},
21986         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1185,   9,      1211},
21987         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1186,   9,      1220},
21988         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1187,   4,      1229},
21989         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1188,   3,      1233},
21990         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1189,   3,      1236},
21991         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1190,   3,      1239},
21992         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1191,   5,      1242},
21993         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1193,   1,      1247},
21994         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1194,   10,     1248},
21995         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1202,   13,     1258},
21996         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1210,   4,      1271},
21997         {"cvmx_mio_fus_bnk_dat#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1211,   1,      1275},
21998         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1215,   2,      1276},
21999         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1216,   2,      1278},
22000         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1217,   9,      1280},
22001         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1218,   8,      1289},
22002         {"cvmx_mio_fus_ema"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1219,   2,      1297},
22003         {"cvmx_mio_fus_pll"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1220,   3,      1299},
22004         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1221,   2,      1302},
22005         {"cvmx_mio_fus_prog_times"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1222,   6,      1304},
22006         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1223,   8,      1310},
22007         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1224,   4,      1318},
22008         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1225,   2,      1322},
22009         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1226,   2,      1324},
22010         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1227,   13,     1326},
22011         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1228,   12,     1339},
22012         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1229,   3,      1351},
22013         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1230,   3,      1354},
22014         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1231,   2,      1357},
22015         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1233,   2,      1359},
22016         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1235,   2,      1361},
22017         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1237,   7,      1363},
22018         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1239,   2,      1370},
22019         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1241,   7,      1372},
22020         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1243,   4,      1379},
22021         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1245,   8,      1383},
22022         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1247,   9,      1391},
22023         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1249,   7,      1400},
22024         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1251,   9,      1407},
22025         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1253,   2,      1416},
22026         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1255,   2,      1418},
22027         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1257,   4,      1420},
22028         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1259,   2,      1424},
22029         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1261,   2,      1426},
22030         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1263,   2,      1428},
22031         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1265,   4,      1430},
22032         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1267,   2,      1434},
22033         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1269,   2,      1436},
22034         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1271,   2,      1438},
22035         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1273,   2,      1440},
22036         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1275,   2,      1442},
22037         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1277,   2,      1444},
22038         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1279,   6,      1446},
22039         {"cvmx_npi_base_addr_input#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1281,   2,      1452},
22040         {"cvmx_npi_base_addr_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1285,   2,      1454},
22041         {"cvmx_npi_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1289,   21,     1456},
22042         {"cvmx_npi_buff_size_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1290,   3,      1477},
22043         {"cvmx_npi_comp_ctl"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1294,   3,      1480},
22044         {"cvmx_npi_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1295,   21,     1483},
22045         {"cvmx_npi_dbg_select"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1296,   2,      1504},
22046         {"cvmx_npi_dma_control"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1297,   13,     1506},
22047         {"cvmx_npi_dma_highp_counts"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1298,   3,      1519},
22048         {"cvmx_npi_dma_highp_naddr"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1299,   3,      1522},
22049         {"cvmx_npi_dma_lowp_counts"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1300,   3,      1525},
22050         {"cvmx_npi_dma_lowp_naddr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1301,   3,      1528},
22051         {"cvmx_npi_highp_dbell"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1302,   2,      1531},
22052         {"cvmx_npi_highp_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1303,   2,      1533},
22053         {"cvmx_npi_input_control"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1304,   10,     1535},
22054         {"cvmx_npi_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1305,   63,     1545},
22055         {"cvmx_npi_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1306,   63,     1608},
22056         {"cvmx_npi_lowp_dbell"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1307,   2,      1671},
22057         {"cvmx_npi_lowp_ibuff_saddr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1308,   2,      1673},
22058         {"cvmx_npi_mem_access_subid#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1309,   10,     1675},
22059         {"cvmx_npi_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1313,   1,      1685},
22060         {"cvmx_npi_num_desc_output#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1314,   2,      1686},
22061         {"cvmx_npi_output_control"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1318,   39,     1688},
22062         {"cvmx_npi_p#_dbpair_addr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1319,   3,      1727},
22063         {"cvmx_npi_p#_instr_addr"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1323,   2,      1730},
22064         {"cvmx_npi_p#_instr_cnts"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1327,   3,      1732},
22065         {"cvmx_npi_p#_pair_cnts"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1331,   3,      1735},
22066         {"cvmx_npi_pci_burst_size"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1335,   3,      1738},
22067         {"cvmx_npi_pci_int_arb_cfg"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1336,   7,      1741},
22068         {"cvmx_npi_pci_read_cmd"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1337,   2,      1748},
22069         {"cvmx_npi_port32_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1338,   13,     1750},
22070         {"cvmx_npi_port33_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1339,   13,     1763},
22071         {"cvmx_npi_port34_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1340,   13,     1776},
22072         {"cvmx_npi_port35_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1341,   13,     1789},
22073         {"cvmx_npi_port_bp_control"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1342,   3,      1802},
22074         {"cvmx_npi_rsl_int_blocks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1343,   33,     1805},
22075         {"cvmx_npi_size_input#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1344,   2,      1838},
22076         {"cvmx_npi_win_read_to"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1348,   2,      1840},
22077         {"cvmx_pci_bar1_index#"        ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1349,   5,      1842},
22078         {"cvmx_pci_cfg00"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1381,   2,      1847},
22079         {"cvmx_pci_cfg01"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1382,   24,     1849},
22080         {"cvmx_pci_cfg02"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1383,   2,      1873},
22081         {"cvmx_pci_cfg03"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1384,   7,      1875},
22082         {"cvmx_pci_cfg04"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1385,   5,      1882},
22083         {"cvmx_pci_cfg05"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1386,   1,      1887},
22084         {"cvmx_pci_cfg06"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1387,   5,      1888},
22085         {"cvmx_pci_cfg07"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1388,   1,      1893},
22086         {"cvmx_pci_cfg08"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1389,   4,      1894},
22087         {"cvmx_pci_cfg09"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1390,   2,      1898},
22088         {"cvmx_pci_cfg10"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1391,   1,      1900},
22089         {"cvmx_pci_cfg11"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1392,   2,      1901},
22090         {"cvmx_pci_cfg12"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1393,   4,      1903},
22091         {"cvmx_pci_cfg13"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1394,   2,      1907},
22092         {"cvmx_pci_cfg15"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1395,   4,      1909},
22093         {"cvmx_pci_cfg16"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1396,   16,     1913},
22094         {"cvmx_pci_cfg17"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1397,   1,      1929},
22095         {"cvmx_pci_cfg18"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1398,   1,      1930},
22096         {"cvmx_pci_cfg19"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1399,   18,     1931},
22097         {"cvmx_pci_cfg20"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1400,   1,      1949},
22098         {"cvmx_pci_cfg21"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1401,   1,      1950},
22099         {"cvmx_pci_cfg22"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1402,   7,      1951},
22100         {"cvmx_pci_cfg56"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1403,   7,      1958},
22101         {"cvmx_pci_cfg57"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1404,   13,     1965},
22102         {"cvmx_pci_cfg58"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1405,   10,     1978},
22103         {"cvmx_pci_cfg59"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1406,   10,     1988},
22104         {"cvmx_pci_cfg60"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1407,   7,      1998},
22105         {"cvmx_pci_cfg61"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1408,   2,      2005},
22106         {"cvmx_pci_cfg62"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1409,   1,      2007},
22107         {"cvmx_pci_cfg63"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1410,   2,      2008},
22108         {"cvmx_pci_cnt_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1411,   6,      2010},
22109         {"cvmx_pci_ctl_status_2"       ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1412,   22,     2016},
22110         {"cvmx_pci_dbell#"             ,        CVMX_CSR_DB_TYPE_PCI,   32,     1413,   2,      2038},
22111         {"cvmx_pci_dma_cnt#"           ,        CVMX_CSR_DB_TYPE_PCI,   32,     1417,   1,      2040},
22112         {"cvmx_pci_dma_int_lev#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1419,   1,      2041},
22113         {"cvmx_pci_dma_time#"          ,        CVMX_CSR_DB_TYPE_PCI,   32,     1421,   1,      2042},
22114         {"cvmx_pci_instr_count#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1423,   1,      2043},
22115         {"cvmx_pci_int_enb"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     1427,   35,     2044},
22116         {"cvmx_pci_int_enb2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1428,   35,     2079},
22117         {"cvmx_pci_int_sum"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     1429,   35,     2114},
22118         {"cvmx_pci_int_sum2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1430,   35,     2149},
22119         {"cvmx_pci_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI,   32,     1431,   2,      2184},
22120         {"cvmx_pci_pkt_credits#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1432,   2,      2186},
22121         {"cvmx_pci_pkts_sent#"         ,        CVMX_CSR_DB_TYPE_PCI,   32,     1436,   1,      2188},
22122         {"cvmx_pci_pkts_sent_int_lev#" ,        CVMX_CSR_DB_TYPE_PCI,   32,     1440,   1,      2189},
22123         {"cvmx_pci_pkts_sent_time#"    ,        CVMX_CSR_DB_TYPE_PCI,   32,     1444,   1,      2190},
22124         {"cvmx_pci_read_cmd_6"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1448,   3,      2191},
22125         {"cvmx_pci_read_cmd_c"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1449,   3,      2194},
22126         {"cvmx_pci_read_cmd_e"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1450,   3,      2197},
22127         {"cvmx_pci_read_timeout"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1451,   3,      2200},
22128         {"cvmx_pci_scm_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1452,   2,      2203},
22129         {"cvmx_pci_tsr_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1453,   2,      2205},
22130         {"cvmx_pci_win_rd_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1454,   4,      2207},
22131         {"cvmx_pci_win_rd_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1455,   1,      2211},
22132         {"cvmx_pci_win_wr_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1456,   4,      2212},
22133         {"cvmx_pci_win_wr_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1457,   1,      2216},
22134         {"cvmx_pci_win_wr_mask"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1458,   2,      2217},
22135         {"cvmx_pip_bck_prs"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1459,   5,      2219},
22136         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1460,   2,      2224},
22137         {"cvmx_pip_crc_ctl#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1461,   3,      2226},
22138         {"cvmx_pip_crc_iv#"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1463,   2,      2229},
22139         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1465,   4,      2231},
22140         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1469,   8,      2235},
22141         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1470,   16,     2243},
22142         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1471,   10,     2259},
22143         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1472,   10,     2269},
22144         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1473,   2,      2279},
22145         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1474,   19,     2281},
22146         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1510,   25,     2300},
22147         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1546,   2,      2325},
22148         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1610,   2,      2327},
22149         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1618,   9,      2329},
22150         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1622,   2,      2338},
22151         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1623,   2,      2340},
22152         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1624,   2,      2342},
22153         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1660,   2,      2344},
22154         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1696,   2,      2346},
22155         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1732,   2,      2348},
22156         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1768,   2,      2350},
22157         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1804,   2,      2352},
22158         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1840,   2,      2354},
22159         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1876,   2,      2356},
22160         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1912,   2,      2358},
22161         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1948,   2,      2360},
22162         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1984,   2,      2362},
22163         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1985,   2,      2364},
22164         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2021,   2,      2366},
22165         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2057,   2,      2368},
22166         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2093,   2,      2370},
22167         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2157,   2,      2372},
22168         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2158,   3,      2374},
22169         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2159,   3,      2377},
22170         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2160,   2,      2380},
22171         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2161,   2,      2382},
22172         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2162,   4,      2384},
22173         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2163,   5,      2388},
22174         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2164,   4,      2393},
22175         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2165,   8,      2397},
22176         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2166,   4,      2405},
22177         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2167,   5,      2409},
22178         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2168,   5,      2414},
22179         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2169,   1,      2419},
22180         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2170,   18,     2420},
22181         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2171,   4,      2438},
22182         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2172,   2,      2442},
22183         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2173,   6,      2444},
22184         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2174,   7,      2450},
22185         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2175,   4,      2457},
22186         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2176,   9,      2461},
22187         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2177,   5,      2470},
22188         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2178,   15,     2475},
22189         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2179,   4,      2490},
22190         {"cvmx_pko_reg_crc_ctl#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2180,   3,      2494},
22191         {"cvmx_pko_reg_crc_enable"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2182,   2,      2497},
22192         {"cvmx_pko_reg_crc_iv#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2183,   2,      2499},
22193         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2185,   1,      2501},
22194         {"cvmx_pko_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2186,   1,      2502},
22195         {"cvmx_pko_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2187,   1,      2503},
22196         {"cvmx_pko_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2188,   1,      2504},
22197         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2189,   4,      2505},
22198         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2190,   5,      2509},
22199         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2191,   3,      2514},
22200         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2192,   4,      2517},
22201         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2193,   2,      2521},
22202         {"cvmx_pko_reg_queue_ptrs1"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2194,   3,      2523},
22203         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2195,   3,      2526},
22204         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2196,   13,     2529},
22205         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2197,   2,      2542},
22206         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2198,   13,     2544},
22207         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2199,   3,      2557},
22208         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2200,   2,      2560},
22209         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2208,   2,      2562},
22210         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2209,   2,      2564},
22211         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2210,   2,      2566},
22212         {"cvmx_pow_pf_rst_msk"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2211,   2,      2568},
22213         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2212,   10,     2570},
22214         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2228,   5,      2580},
22215         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2236,   8,      2585},
22216         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2244,   2,      2593},
22217         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2245,   2,      2595},
22218         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2246,   2,      2597},
22219         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2254,   3,      2599},
22220         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2255,   4,      2602},
22221         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2271,   5,      2606},
22222         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2272,   7,      2611},
22223         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2288,   2,      2618},
22224         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2304,   3,      2620},
22225         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2305,   7,      2623},
22226         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2306,   8,      2630},
22227         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2307,   6,      2638},
22228         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2308,   2,      2644},
22229         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2309,   4,      2646},
22230         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2310,   4,      2650},
22231         {"cvmx_spx#_bckprs_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2311,   2,      2654},
22232         {"cvmx_spx#_bist_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2313,   4,      2656},
22233         {"cvmx_spx#_clk_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2315,   11,     2660},
22234         {"cvmx_spx#_clk_stat"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2317,   9,      2671},
22235         {"cvmx_spx#_dbg_deskew_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2319,   16,     2680},
22236         {"cvmx_spx#_dbg_deskew_state"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2321,   5,      2696},
22237         {"cvmx_spx#_drv_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2323,   5,      2701},
22238         {"cvmx_spx#_err_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2325,   6,      2706},
22239         {"cvmx_spx#_int_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2327,   6,      2712},
22240         {"cvmx_spx#_int_msk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2329,   12,     2718},
22241         {"cvmx_spx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2331,   14,     2730},
22242         {"cvmx_spx#_int_sync"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2333,   12,     2744},
22243         {"cvmx_spx#_tpa_acc"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2335,   2,      2756},
22244         {"cvmx_spx#_tpa_max"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2337,   2,      2758},
22245         {"cvmx_spx#_tpa_sel"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2339,   2,      2760},
22246         {"cvmx_spx#_trn4_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2341,   8,      2762},
22247         {"cvmx_srx#_com_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2343,   5,      2770},
22248         {"cvmx_srx#_ign_rx_full"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2345,   2,      2775},
22249         {"cvmx_srx#_spi4_cal#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2347,   6,      2777},
22250         {"cvmx_srx#_spi4_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2411,   4,      2783},
22251         {"cvmx_srx#_sw_tick_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2413,   6,      2787},
22252         {"cvmx_srx#_sw_tick_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2415,   1,      2793},
22253         {"cvmx_stx#_arb_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2417,   5,      2794},
22254         {"cvmx_stx#_bckprs_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2419,   2,      2799},
22255         {"cvmx_stx#_com_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2421,   4,      2801},
22256         {"cvmx_stx#_dip_cnt"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2423,   3,      2805},
22257         {"cvmx_stx#_ign_cal"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2425,   2,      2808},
22258         {"cvmx_stx#_int_msk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2427,   9,      2810},
22259         {"cvmx_stx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2429,   10,     2819},
22260         {"cvmx_stx#_int_sync"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2431,   9,      2829},
22261         {"cvmx_stx#_min_bst"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2433,   2,      2838},
22262         {"cvmx_stx#_spi4_cal#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2435,   6,      2840},
22263         {"cvmx_stx#_spi4_dat"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2499,   3,      2846},
22264         {"cvmx_stx#_spi4_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2501,   4,      2849},
22265         {"cvmx_stx#_stat_bytes_hi"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2503,   2,      2853},
22266         {"cvmx_stx#_stat_bytes_lo"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2505,   2,      2855},
22267         {"cvmx_stx#_stat_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2507,   3,      2857},
22268         {"cvmx_stx#_stat_pkt_xmt"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2509,   2,      2860},
22269         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2511,   6,      2862},
22270         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2512,   3,      2868},
22271         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2513,   5,      2871},
22272         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2514,   4,      2876},
22273         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2515,   6,      2880},
22274         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2516,   4,      2886},
22275         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2517,   2,      2890},
22276         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2518,   4,      2892},
22277         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2519,   2,      2896},
22278         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2520,   3,      2898},
22279         {"cvmx_tra_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2521,   4,      2901},
22280         {"cvmx_tra_ctl"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2522,   12,     2905},
22281         {"cvmx_tra_cycles_since"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2523,   3,      2917},
22282         {"cvmx_tra_cycles_since1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2524,   5,      2920},
22283         {"cvmx_tra_filt_adr_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2525,   2,      2925},
22284         {"cvmx_tra_filt_adr_msk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2526,   2,      2927},
22285         {"cvmx_tra_filt_cmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2527,   18,     2929},
22286         {"cvmx_tra_filt_did"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2528,   12,     2947},
22287         {"cvmx_tra_filt_sid"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2529,   6,      2959},
22288         {"cvmx_tra_int_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2530,   5,      2965},
22289         {"cvmx_tra_read_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2531,   1,      2970},
22290         {"cvmx_tra_trig0_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2532,   2,      2971},
22291         {"cvmx_tra_trig0_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2533,   2,      2973},
22292         {"cvmx_tra_trig0_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2534,   18,     2975},
22293         {"cvmx_tra_trig0_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2535,   12,     2993},
22294         {"cvmx_tra_trig0_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2536,   6,      3005},
22295         {"cvmx_tra_trig1_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2537,   2,      3011},
22296         {"cvmx_tra_trig1_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2538,   2,      3013},
22297         {"cvmx_tra_trig1_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2539,   18,     3015},
22298         {"cvmx_tra_trig1_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2540,   12,     3033},
22299         {"cvmx_tra_trig1_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2541,   6,      3045},
22300         {"cvmx_zip_cmd_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2542,   3,      3051},
22301         {"cvmx_zip_cmd_buf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2543,   5,      3054},
22302         {"cvmx_zip_cmd_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2544,   3,      3059},
22303         {"cvmx_zip_constants"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2545,   6,      3062},
22304         {"cvmx_zip_debug0"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     2546,   2,      3068},
22305         {"cvmx_zip_error"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     2547,   2,      3070},
22306         {"cvmx_zip_int_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2548,   2,      3072},
22307         {NULL,0,0,0,0,0}
22308 };
22309 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xxp1[] = {
22310         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
22311         {"ASX0_INT_EN"                 ,           0x11800B0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
22312         {"ASX1_INT_EN"                 ,           0x11800B8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
22313         {"ASX0_INT_REG"                ,           0x11800B0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
22314         {"ASX1_INT_REG"                ,           0x11800B8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
22315         {"ASX0_PRT_LOOP"               ,           0x11800B0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
22316         {"ASX1_PRT_LOOP"               ,           0x11800B8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
22317         {"ASX0_RLD_BYPASS"             ,           0x11800B0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
22318         {"ASX1_RLD_BYPASS"             ,           0x11800B8000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
22319         {"ASX0_RLD_BYPASS_SETTING"     ,           0x11800B0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
22320         {"ASX1_RLD_BYPASS_SETTING"     ,           0x11800B8000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
22321         {"ASX0_RLD_COMP"               ,           0x11800B0000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
22322         {"ASX1_RLD_COMP"               ,           0x11800B8000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
22323         {"ASX0_RLD_DATA_DRV"           ,           0x11800B0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
22324         {"ASX1_RLD_DATA_DRV"           ,           0x11800B8000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
22325         {"ASX0_RLD_NCTL_STRONG"        ,           0x11800B0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
22326         {"ASX1_RLD_NCTL_STRONG"        ,           0x11800B8000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
22327         {"ASX0_RLD_NCTL_WEAK"          ,           0x11800B0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
22328         {"ASX1_RLD_NCTL_WEAK"          ,           0x11800B8000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
22329         {"ASX0_RLD_PCTL_STRONG"        ,           0x11800B0000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
22330         {"ASX1_RLD_PCTL_STRONG"        ,           0x11800B8000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
22331         {"ASX0_RLD_PCTL_WEAK"          ,           0x11800B0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
22332         {"ASX1_RLD_PCTL_WEAK"          ,           0x11800B8000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
22333         {"ASX0_RLD_SETTING"            ,           0x11800B0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
22334         {"ASX1_RLD_SETTING"            ,           0x11800B8000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
22335         {"ASX0_RX_CLK_SET000"          ,           0x11800B0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
22336         {"ASX0_RX_CLK_SET001"          ,           0x11800B0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
22337         {"ASX0_RX_CLK_SET002"          ,           0x11800B0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
22338         {"ASX0_RX_CLK_SET003"          ,           0x11800B0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
22339         {"ASX1_RX_CLK_SET000"          ,           0x11800B8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
22340         {"ASX1_RX_CLK_SET001"          ,           0x11800B8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
22341         {"ASX1_RX_CLK_SET002"          ,           0x11800B8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
22342         {"ASX1_RX_CLK_SET003"          ,           0x11800B8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
22343         {"ASX0_RX_PRT_EN"              ,           0x11800B0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
22344         {"ASX1_RX_PRT_EN"              ,           0x11800B8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
22345         {"ASX0_TX_CLK_SET000"          ,           0x11800B0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
22346         {"ASX0_TX_CLK_SET001"          ,           0x11800B0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
22347         {"ASX0_TX_CLK_SET002"          ,           0x11800B0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
22348         {"ASX0_TX_CLK_SET003"          ,           0x11800B0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
22349         {"ASX1_TX_CLK_SET000"          ,           0x11800B8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
22350         {"ASX1_TX_CLK_SET001"          ,           0x11800B8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
22351         {"ASX1_TX_CLK_SET002"          ,           0x11800B8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
22352         {"ASX1_TX_CLK_SET003"          ,           0x11800B8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
22353         {"ASX0_TX_COMP_BYP"            ,           0x11800B0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
22354         {"ASX1_TX_COMP_BYP"            ,           0x11800B8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
22355         {"ASX0_TX_HI_WATER000"         ,           0x11800B0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
22356         {"ASX0_TX_HI_WATER001"         ,           0x11800B0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
22357         {"ASX0_TX_HI_WATER002"         ,           0x11800B0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
22358         {"ASX0_TX_HI_WATER003"         ,           0x11800B0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
22359         {"ASX1_TX_HI_WATER000"         ,           0x11800B8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
22360         {"ASX1_TX_HI_WATER001"         ,           0x11800B8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
22361         {"ASX1_TX_HI_WATER002"         ,           0x11800B8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
22362         {"ASX1_TX_HI_WATER003"         ,           0x11800B8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
22363         {"ASX0_TX_PRT_EN"              ,           0x11800B0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
22364         {"ASX1_TX_PRT_EN"              ,           0x11800B8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
22365         {"ASX0_DBG_DATA_DRV"           ,           0x11800B0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
22366         {"ASX0_DBG_DATA_ENABLE"        ,           0x11800B0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
22367         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
22368         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     21},
22369         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     22},
22370         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     23},
22371         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22372         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22373         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22374         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22375         {"CIU_INT4_EN0"                ,           0x1070000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22376         {"CIU_INT5_EN0"                ,           0x1070000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22377         {"CIU_INT6_EN0"                ,           0x1070000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22378         {"CIU_INT7_EN0"                ,           0x1070000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22379         {"CIU_INT8_EN0"                ,           0x1070000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22380         {"CIU_INT9_EN0"                ,           0x1070000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22381         {"CIU_INT10_EN0"               ,           0x10700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22382         {"CIU_INT11_EN0"               ,           0x10700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22383         {"CIU_INT12_EN0"               ,           0x10700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22384         {"CIU_INT13_EN0"               ,           0x10700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22385         {"CIU_INT14_EN0"               ,           0x10700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22386         {"CIU_INT15_EN0"               ,           0x10700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22387         {"CIU_INT16_EN0"               ,           0x1070000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22388         {"CIU_INT17_EN0"               ,           0x1070000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22389         {"CIU_INT18_EN0"               ,           0x1070000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22390         {"CIU_INT19_EN0"               ,           0x1070000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22391         {"CIU_INT20_EN0"               ,           0x1070000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22392         {"CIU_INT21_EN0"               ,           0x1070000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22393         {"CIU_INT22_EN0"               ,           0x1070000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22394         {"CIU_INT23_EN0"               ,           0x1070000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22395         {"CIU_INT24_EN0"               ,           0x1070000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22396         {"CIU_INT25_EN0"               ,           0x1070000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22397         {"CIU_INT26_EN0"               ,           0x10700000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22398         {"CIU_INT27_EN0"               ,           0x10700000003B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22399         {"CIU_INT28_EN0"               ,           0x10700000003C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22400         {"CIU_INT29_EN0"               ,           0x10700000003D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22401         {"CIU_INT30_EN0"               ,           0x10700000003E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22402         {"CIU_INT31_EN0"               ,           0x10700000003F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22403         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
22404         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22405         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22406         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22407         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22408         {"CIU_INT4_EN1"                ,           0x1070000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22409         {"CIU_INT5_EN1"                ,           0x1070000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22410         {"CIU_INT6_EN1"                ,           0x1070000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22411         {"CIU_INT7_EN1"                ,           0x1070000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22412         {"CIU_INT8_EN1"                ,           0x1070000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22413         {"CIU_INT9_EN1"                ,           0x1070000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22414         {"CIU_INT10_EN1"               ,           0x10700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22415         {"CIU_INT11_EN1"               ,           0x10700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22416         {"CIU_INT12_EN1"               ,           0x10700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22417         {"CIU_INT13_EN1"               ,           0x10700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22418         {"CIU_INT14_EN1"               ,           0x10700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22419         {"CIU_INT15_EN1"               ,           0x10700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22420         {"CIU_INT16_EN1"               ,           0x1070000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22421         {"CIU_INT17_EN1"               ,           0x1070000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22422         {"CIU_INT18_EN1"               ,           0x1070000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22423         {"CIU_INT19_EN1"               ,           0x1070000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22424         {"CIU_INT20_EN1"               ,           0x1070000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22425         {"CIU_INT21_EN1"               ,           0x1070000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22426         {"CIU_INT22_EN1"               ,           0x1070000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22427         {"CIU_INT23_EN1"               ,           0x1070000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22428         {"CIU_INT24_EN1"               ,           0x1070000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22429         {"CIU_INT25_EN1"               ,           0x1070000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22430         {"CIU_INT26_EN1"               ,           0x10700000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22431         {"CIU_INT27_EN1"               ,           0x10700000003B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22432         {"CIU_INT28_EN1"               ,           0x10700000003C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22433         {"CIU_INT29_EN1"               ,           0x10700000003D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22434         {"CIU_INT30_EN1"               ,           0x10700000003E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22435         {"CIU_INT31_EN1"               ,           0x10700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22436         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
22437         {"CIU_INT0_EN4_0"              ,           0x1070000000C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22438         {"CIU_INT1_EN4_0"              ,           0x1070000000C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22439         {"CIU_INT2_EN4_0"              ,           0x1070000000CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22440         {"CIU_INT3_EN4_0"              ,           0x1070000000CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22441         {"CIU_INT4_EN4_0"              ,           0x1070000000CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22442         {"CIU_INT5_EN4_0"              ,           0x1070000000CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22443         {"CIU_INT6_EN4_0"              ,           0x1070000000CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22444         {"CIU_INT7_EN4_0"              ,           0x1070000000CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22445         {"CIU_INT8_EN4_0"              ,           0x1070000000D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22446         {"CIU_INT9_EN4_0"              ,           0x1070000000D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22447         {"CIU_INT10_EN4_0"             ,           0x1070000000D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22448         {"CIU_INT11_EN4_0"             ,           0x1070000000D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22449         {"CIU_INT12_EN4_0"             ,           0x1070000000D40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22450         {"CIU_INT13_EN4_0"             ,           0x1070000000D50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22451         {"CIU_INT14_EN4_0"             ,           0x1070000000D60ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22452         {"CIU_INT15_EN4_0"             ,           0x1070000000D70ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
22453         {"CIU_INT0_EN4_1"              ,           0x1070000000C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22454         {"CIU_INT1_EN4_1"              ,           0x1070000000C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22455         {"CIU_INT2_EN4_1"              ,           0x1070000000CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22456         {"CIU_INT3_EN4_1"              ,           0x1070000000CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22457         {"CIU_INT4_EN4_1"              ,           0x1070000000CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22458         {"CIU_INT5_EN4_1"              ,           0x1070000000CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22459         {"CIU_INT6_EN4_1"              ,           0x1070000000CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22460         {"CIU_INT7_EN4_1"              ,           0x1070000000CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22461         {"CIU_INT8_EN4_1"              ,           0x1070000000D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22462         {"CIU_INT9_EN4_1"              ,           0x1070000000D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22463         {"CIU_INT10_EN4_1"             ,           0x1070000000D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22464         {"CIU_INT11_EN4_1"             ,           0x1070000000D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22465         {"CIU_INT12_EN4_1"             ,           0x1070000000D48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22466         {"CIU_INT13_EN4_1"             ,           0x1070000000D58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22467         {"CIU_INT14_EN4_1"             ,           0x1070000000D68ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22468         {"CIU_INT15_EN4_1"             ,           0x1070000000D78ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
22469         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22470         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22471         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22472         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22473         {"CIU_INT4_SUM0"               ,           0x1070000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22474         {"CIU_INT5_SUM0"               ,           0x1070000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22475         {"CIU_INT6_SUM0"               ,           0x1070000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22476         {"CIU_INT7_SUM0"               ,           0x1070000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22477         {"CIU_INT8_SUM0"               ,           0x1070000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22478         {"CIU_INT9_SUM0"               ,           0x1070000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22479         {"CIU_INT10_SUM0"              ,           0x1070000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22480         {"CIU_INT11_SUM0"              ,           0x1070000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22481         {"CIU_INT12_SUM0"              ,           0x1070000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22482         {"CIU_INT13_SUM0"              ,           0x1070000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22483         {"CIU_INT14_SUM0"              ,           0x1070000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22484         {"CIU_INT15_SUM0"              ,           0x1070000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22485         {"CIU_INT16_SUM0"              ,           0x1070000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22486         {"CIU_INT17_SUM0"              ,           0x1070000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22487         {"CIU_INT18_SUM0"              ,           0x1070000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22488         {"CIU_INT19_SUM0"              ,           0x1070000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22489         {"CIU_INT20_SUM0"              ,           0x10700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22490         {"CIU_INT21_SUM0"              ,           0x10700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22491         {"CIU_INT22_SUM0"              ,           0x10700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22492         {"CIU_INT23_SUM0"              ,           0x10700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22493         {"CIU_INT24_SUM0"              ,           0x10700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22494         {"CIU_INT25_SUM0"              ,           0x10700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22495         {"CIU_INT26_SUM0"              ,           0x10700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22496         {"CIU_INT27_SUM0"              ,           0x10700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22497         {"CIU_INT28_SUM0"              ,           0x10700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22498         {"CIU_INT29_SUM0"              ,           0x10700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22499         {"CIU_INT30_SUM0"              ,           0x10700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22500         {"CIU_INT31_SUM0"              ,           0x10700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22501         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
22502         {"CIU_INT0_SUM4"               ,           0x1070000000C00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22503         {"CIU_INT1_SUM4"               ,           0x1070000000C08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22504         {"CIU_INT2_SUM4"               ,           0x1070000000C10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22505         {"CIU_INT3_SUM4"               ,           0x1070000000C18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22506         {"CIU_INT4_SUM4"               ,           0x1070000000C20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22507         {"CIU_INT5_SUM4"               ,           0x1070000000C28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22508         {"CIU_INT6_SUM4"               ,           0x1070000000C30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22509         {"CIU_INT7_SUM4"               ,           0x1070000000C38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22510         {"CIU_INT8_SUM4"               ,           0x1070000000C40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22511         {"CIU_INT9_SUM4"               ,           0x1070000000C48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22512         {"CIU_INT10_SUM4"              ,           0x1070000000C50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22513         {"CIU_INT11_SUM4"              ,           0x1070000000C58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22514         {"CIU_INT12_SUM4"              ,           0x1070000000C60ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22515         {"CIU_INT13_SUM4"              ,           0x1070000000C68ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22516         {"CIU_INT14_SUM4"              ,           0x1070000000C70ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22517         {"CIU_INT15_SUM4"              ,           0x1070000000C78ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
22518         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
22519         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22520         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22521         {"CIU_MBOX_CLR2"               ,           0x1070000000690ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22522         {"CIU_MBOX_CLR3"               ,           0x1070000000698ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22523         {"CIU_MBOX_CLR4"               ,           0x10700000006A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22524         {"CIU_MBOX_CLR5"               ,           0x10700000006A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22525         {"CIU_MBOX_CLR6"               ,           0x10700000006B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22526         {"CIU_MBOX_CLR7"               ,           0x10700000006B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22527         {"CIU_MBOX_CLR8"               ,           0x10700000006C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22528         {"CIU_MBOX_CLR9"               ,           0x10700000006C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22529         {"CIU_MBOX_CLR10"              ,           0x10700000006D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22530         {"CIU_MBOX_CLR11"              ,           0x10700000006D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22531         {"CIU_MBOX_CLR12"              ,           0x10700000006E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22532         {"CIU_MBOX_CLR13"              ,           0x10700000006E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22533         {"CIU_MBOX_CLR14"              ,           0x10700000006F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22534         {"CIU_MBOX_CLR15"              ,           0x10700000006F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
22535         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22536         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22537         {"CIU_MBOX_SET2"               ,           0x1070000000610ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22538         {"CIU_MBOX_SET3"               ,           0x1070000000618ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22539         {"CIU_MBOX_SET4"               ,           0x1070000000620ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22540         {"CIU_MBOX_SET5"               ,           0x1070000000628ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22541         {"CIU_MBOX_SET6"               ,           0x1070000000630ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22542         {"CIU_MBOX_SET7"               ,           0x1070000000638ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22543         {"CIU_MBOX_SET8"               ,           0x1070000000640ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22544         {"CIU_MBOX_SET9"               ,           0x1070000000648ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22545         {"CIU_MBOX_SET10"              ,           0x1070000000650ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22546         {"CIU_MBOX_SET11"              ,           0x1070000000658ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22547         {"CIU_MBOX_SET12"              ,           0x1070000000660ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22548         {"CIU_MBOX_SET13"              ,           0x1070000000668ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22549         {"CIU_MBOX_SET14"              ,           0x1070000000670ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22550         {"CIU_MBOX_SET15"              ,           0x1070000000678ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
22551         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
22552         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
22553         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
22554         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22555         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22556         {"CIU_PP_POKE2"                ,           0x1070000000590ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22557         {"CIU_PP_POKE3"                ,           0x1070000000598ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22558         {"CIU_PP_POKE4"                ,           0x10700000005A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22559         {"CIU_PP_POKE5"                ,           0x10700000005A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22560         {"CIU_PP_POKE6"                ,           0x10700000005B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22561         {"CIU_PP_POKE7"                ,           0x10700000005B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22562         {"CIU_PP_POKE8"                ,           0x10700000005C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22563         {"CIU_PP_POKE9"                ,           0x10700000005C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22564         {"CIU_PP_POKE10"               ,           0x10700000005D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22565         {"CIU_PP_POKE11"               ,           0x10700000005D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22566         {"CIU_PP_POKE12"               ,           0x10700000005E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22567         {"CIU_PP_POKE13"               ,           0x10700000005E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22568         {"CIU_PP_POKE14"               ,           0x10700000005F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22569         {"CIU_PP_POKE15"               ,           0x10700000005F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
22570         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
22571         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
22572         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
22573         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
22574         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     41},
22575         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     41},
22576         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     41},
22577         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     41},
22578         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22579         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22580         {"CIU_WDOG2"                   ,           0x1070000000510ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22581         {"CIU_WDOG3"                   ,           0x1070000000518ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22582         {"CIU_WDOG4"                   ,           0x1070000000520ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22583         {"CIU_WDOG5"                   ,           0x1070000000528ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22584         {"CIU_WDOG6"                   ,           0x1070000000530ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22585         {"CIU_WDOG7"                   ,           0x1070000000538ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22586         {"CIU_WDOG8"                   ,           0x1070000000540ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22587         {"CIU_WDOG9"                   ,           0x1070000000548ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22588         {"CIU_WDOG10"                  ,           0x1070000000550ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22589         {"CIU_WDOG11"                  ,           0x1070000000558ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22590         {"CIU_WDOG12"                  ,           0x1070000000560ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22591         {"CIU_WDOG13"                  ,           0x1070000000568ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22592         {"CIU_WDOG14"                  ,           0x1070000000570ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22593         {"CIU_WDOG15"                  ,           0x1070000000578ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
22594         {"DBG_DATA"                    ,           0x11F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
22595         {"DFA_BST0"                    ,           0x11800300007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
22596         {"DFA_BST1"                    ,           0x11800300007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     45},
22597         {"DFA_CFG"                     ,           0x1180030000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
22598         {"DFA_DBELL"                   ,           0x1370000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     47},
22599         {"DFA_DIFCTL"                  ,           0x1370600000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     48},
22600         {"DFA_DIFRDPTR"                ,           0x1370200000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     49},
22601         {"DFA_ERR"                     ,           0x1180030000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
22602         {"DFA_MEMCFG0"                 ,           0x1180030000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
22603         {"DFA_MEMCFG1"                 ,           0x1180030000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
22604         {"DFA_MEMCFG2"                 ,           0x1180030000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
22605         {"DFA_MEMFADR"                 ,           0x1180030000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
22606         {"DFA_MEMFCR"                  ,           0x1180030000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
22607         {"DFA_MEMRLD"                  ,           0x1180030000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
22608         {"DFA_NCBCTL"                  ,           0x1180030000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
22609         {"DFA_RODT_COMP_CTL"           ,           0x1180030000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
22610         {"DFA_SBD_DBG0"                ,           0x1180030000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
22611         {"DFA_SBD_DBG1"                ,           0x1180030000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
22612         {"DFA_SBD_DBG2"                ,           0x1180030000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
22613         {"DFA_SBD_DBG3"                ,           0x1180030000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
22614         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
22615         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
22616         {"FPA_FPF1_MARKS"              ,           0x1180028000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
22617         {"FPA_FPF2_MARKS"              ,           0x1180028000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
22618         {"FPA_FPF3_MARKS"              ,           0x1180028000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
22619         {"FPA_FPF4_MARKS"              ,           0x1180028000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
22620         {"FPA_FPF5_MARKS"              ,           0x1180028000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
22621         {"FPA_FPF6_MARKS"              ,           0x1180028000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
22622         {"FPA_FPF7_MARKS"              ,           0x1180028000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
22623         {"FPA_FPF1_SIZE"               ,           0x1180028000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
22624         {"FPA_FPF2_SIZE"               ,           0x1180028000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
22625         {"FPA_FPF3_SIZE"               ,           0x1180028000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
22626         {"FPA_FPF4_SIZE"               ,           0x1180028000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
22627         {"FPA_FPF5_SIZE"               ,           0x1180028000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
22628         {"FPA_FPF6_SIZE"               ,           0x1180028000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
22629         {"FPA_FPF7_SIZE"               ,           0x1180028000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
22630         {"FPA_FPF0_MARKS"              ,           0x1180028000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
22631         {"FPA_FPF0_SIZE"               ,           0x1180028000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
22632         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
22633         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
22634         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
22635         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
22636         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
22637         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
22638         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
22639         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
22640         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
22641         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
22642         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
22643         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
22644         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
22645         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
22646         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
22647         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
22648         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
22649         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
22650         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
22651         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
22652         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
22653         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
22654         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
22655         {"GMX1_BAD_REG"                ,           0x1180010000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
22656         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
22657         {"GMX1_BIST"                   ,           0x1180010000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
22658         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
22659         {"GMX1_INF_MODE"               ,           0x11800100007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
22660         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
22661         {"GMX1_NXA_ADR"                ,           0x1180010000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
22662         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
22663         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
22664         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
22665         {"GMX0_PRT003_CFG"             ,           0x1180008001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
22666         {"GMX1_PRT000_CFG"             ,           0x1180010000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
22667         {"GMX1_PRT001_CFG"             ,           0x1180010000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
22668         {"GMX1_PRT002_CFG"             ,           0x1180010001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
22669         {"GMX1_PRT003_CFG"             ,           0x1180010001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
22670         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
22671         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
22672         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
22673         {"GMX0_RX003_ADR_CAM0"         ,           0x1180008001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
22674         {"GMX1_RX000_ADR_CAM0"         ,           0x1180010000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
22675         {"GMX1_RX001_ADR_CAM0"         ,           0x1180010000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
22676         {"GMX1_RX002_ADR_CAM0"         ,           0x1180010001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
22677         {"GMX1_RX003_ADR_CAM0"         ,           0x1180010001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
22678         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
22679         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
22680         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
22681         {"GMX0_RX003_ADR_CAM1"         ,           0x1180008001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
22682         {"GMX1_RX000_ADR_CAM1"         ,           0x1180010000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
22683         {"GMX1_RX001_ADR_CAM1"         ,           0x1180010000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
22684         {"GMX1_RX002_ADR_CAM1"         ,           0x1180010001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
22685         {"GMX1_RX003_ADR_CAM1"         ,           0x1180010001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
22686         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
22687         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
22688         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
22689         {"GMX0_RX003_ADR_CAM2"         ,           0x1180008001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
22690         {"GMX1_RX000_ADR_CAM2"         ,           0x1180010000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
22691         {"GMX1_RX001_ADR_CAM2"         ,           0x1180010000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
22692         {"GMX1_RX002_ADR_CAM2"         ,           0x1180010001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
22693         {"GMX1_RX003_ADR_CAM2"         ,           0x1180010001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
22694         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
22695         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
22696         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
22697         {"GMX0_RX003_ADR_CAM3"         ,           0x1180008001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
22698         {"GMX1_RX000_ADR_CAM3"         ,           0x1180010000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
22699         {"GMX1_RX001_ADR_CAM3"         ,           0x1180010000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
22700         {"GMX1_RX002_ADR_CAM3"         ,           0x1180010001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
22701         {"GMX1_RX003_ADR_CAM3"         ,           0x1180010001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
22702         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
22703         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
22704         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
22705         {"GMX0_RX003_ADR_CAM4"         ,           0x11800080019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
22706         {"GMX1_RX000_ADR_CAM4"         ,           0x11800100001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
22707         {"GMX1_RX001_ADR_CAM4"         ,           0x11800100009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
22708         {"GMX1_RX002_ADR_CAM4"         ,           0x11800100011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
22709         {"GMX1_RX003_ADR_CAM4"         ,           0x11800100019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
22710         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
22711         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
22712         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
22713         {"GMX0_RX003_ADR_CAM5"         ,           0x11800080019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
22714         {"GMX1_RX000_ADR_CAM5"         ,           0x11800100001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
22715         {"GMX1_RX001_ADR_CAM5"         ,           0x11800100009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
22716         {"GMX1_RX002_ADR_CAM5"         ,           0x11800100011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
22717         {"GMX1_RX003_ADR_CAM5"         ,           0x11800100019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
22718         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
22719         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
22720         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
22721         {"GMX0_RX003_ADR_CAM_EN"       ,           0x1180008001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
22722         {"GMX1_RX000_ADR_CAM_EN"       ,           0x1180010000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
22723         {"GMX1_RX001_ADR_CAM_EN"       ,           0x1180010000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
22724         {"GMX1_RX002_ADR_CAM_EN"       ,           0x1180010001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
22725         {"GMX1_RX003_ADR_CAM_EN"       ,           0x1180010001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
22726         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
22727         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
22728         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
22729         {"GMX0_RX003_ADR_CTL"          ,           0x1180008001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
22730         {"GMX1_RX000_ADR_CTL"          ,           0x1180010000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
22731         {"GMX1_RX001_ADR_CTL"          ,           0x1180010000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
22732         {"GMX1_RX002_ADR_CTL"          ,           0x1180010001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
22733         {"GMX1_RX003_ADR_CTL"          ,           0x1180010001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
22734         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
22735         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
22736         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
22737         {"GMX0_RX003_DECISION"         ,           0x1180008001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
22738         {"GMX1_RX000_DECISION"         ,           0x1180010000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
22739         {"GMX1_RX001_DECISION"         ,           0x1180010000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
22740         {"GMX1_RX002_DECISION"         ,           0x1180010001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
22741         {"GMX1_RX003_DECISION"         ,           0x1180010001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
22742         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
22743         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
22744         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
22745         {"GMX0_RX003_FRM_CHK"          ,           0x1180008001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
22746         {"GMX1_RX000_FRM_CHK"          ,           0x1180010000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
22747         {"GMX1_RX001_FRM_CHK"          ,           0x1180010000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
22748         {"GMX1_RX002_FRM_CHK"          ,           0x1180010001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
22749         {"GMX1_RX003_FRM_CHK"          ,           0x1180010001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
22750         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
22751         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
22752         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
22753         {"GMX0_RX003_FRM_CTL"          ,           0x1180008001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
22754         {"GMX1_RX000_FRM_CTL"          ,           0x1180010000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
22755         {"GMX1_RX001_FRM_CTL"          ,           0x1180010000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
22756         {"GMX1_RX002_FRM_CTL"          ,           0x1180010001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
22757         {"GMX1_RX003_FRM_CTL"          ,           0x1180010001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
22758         {"GMX0_RX000_FRM_MAX"          ,           0x1180008000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
22759         {"GMX0_RX001_FRM_MAX"          ,           0x1180008000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
22760         {"GMX0_RX002_FRM_MAX"          ,           0x1180008001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
22761         {"GMX0_RX003_FRM_MAX"          ,           0x1180008001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
22762         {"GMX1_RX000_FRM_MAX"          ,           0x1180010000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
22763         {"GMX1_RX001_FRM_MAX"          ,           0x1180010000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
22764         {"GMX1_RX002_FRM_MAX"          ,           0x1180010001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
22765         {"GMX1_RX003_FRM_MAX"          ,           0x1180010001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
22766         {"GMX0_RX000_FRM_MIN"          ,           0x1180008000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
22767         {"GMX0_RX001_FRM_MIN"          ,           0x1180008000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
22768         {"GMX0_RX002_FRM_MIN"          ,           0x1180008001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
22769         {"GMX0_RX003_FRM_MIN"          ,           0x1180008001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
22770         {"GMX1_RX000_FRM_MIN"          ,           0x1180010000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
22771         {"GMX1_RX001_FRM_MIN"          ,           0x1180010000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
22772         {"GMX1_RX002_FRM_MIN"          ,           0x1180010001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
22773         {"GMX1_RX003_FRM_MIN"          ,           0x1180010001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
22774         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
22775         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
22776         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
22777         {"GMX0_RX003_IFG"              ,           0x1180008001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
22778         {"GMX1_RX000_IFG"              ,           0x1180010000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
22779         {"GMX1_RX001_IFG"              ,           0x1180010000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
22780         {"GMX1_RX002_IFG"              ,           0x1180010001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
22781         {"GMX1_RX003_IFG"              ,           0x1180010001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
22782         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
22783         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
22784         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
22785         {"GMX0_RX003_INT_EN"           ,           0x1180008001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
22786         {"GMX1_RX000_INT_EN"           ,           0x1180010000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
22787         {"GMX1_RX001_INT_EN"           ,           0x1180010000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
22788         {"GMX1_RX002_INT_EN"           ,           0x1180010001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
22789         {"GMX1_RX003_INT_EN"           ,           0x1180010001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
22790         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
22791         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
22792         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
22793         {"GMX0_RX003_INT_REG"          ,           0x1180008001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
22794         {"GMX1_RX000_INT_REG"          ,           0x1180010000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
22795         {"GMX1_RX001_INT_REG"          ,           0x1180010000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
22796         {"GMX1_RX002_INT_REG"          ,           0x1180010001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
22797         {"GMX1_RX003_INT_REG"          ,           0x1180010001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
22798         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
22799         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
22800         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
22801         {"GMX0_RX003_JABBER"           ,           0x1180008001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
22802         {"GMX1_RX000_JABBER"           ,           0x1180010000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
22803         {"GMX1_RX001_JABBER"           ,           0x1180010000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
22804         {"GMX1_RX002_JABBER"           ,           0x1180010001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
22805         {"GMX1_RX003_JABBER"           ,           0x1180010001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
22806         {"GMX0_RX000_PAUSE_DROP_TIME"  ,           0x1180008000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
22807         {"GMX0_RX001_PAUSE_DROP_TIME"  ,           0x1180008000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
22808         {"GMX0_RX002_PAUSE_DROP_TIME"  ,           0x1180008001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
22809         {"GMX0_RX003_PAUSE_DROP_TIME"  ,           0x1180008001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
22810         {"GMX1_RX000_PAUSE_DROP_TIME"  ,           0x1180010000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
22811         {"GMX1_RX001_PAUSE_DROP_TIME"  ,           0x1180010000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
22812         {"GMX1_RX002_PAUSE_DROP_TIME"  ,           0x1180010001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
22813         {"GMX1_RX003_PAUSE_DROP_TIME"  ,           0x1180010001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
22814         {"GMX0_RX000_RX_INBND"         ,           0x1180008000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
22815         {"GMX0_RX001_RX_INBND"         ,           0x1180008000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
22816         {"GMX0_RX002_RX_INBND"         ,           0x1180008001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
22817         {"GMX0_RX003_RX_INBND"         ,           0x1180008001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
22818         {"GMX1_RX000_RX_INBND"         ,           0x1180010000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
22819         {"GMX1_RX001_RX_INBND"         ,           0x1180010000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
22820         {"GMX1_RX002_RX_INBND"         ,           0x1180010001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
22821         {"GMX1_RX003_RX_INBND"         ,           0x1180010001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
22822         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
22823         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
22824         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
22825         {"GMX0_RX003_STATS_CTL"        ,           0x1180008001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
22826         {"GMX1_RX000_STATS_CTL"        ,           0x1180010000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
22827         {"GMX1_RX001_STATS_CTL"        ,           0x1180010000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
22828         {"GMX1_RX002_STATS_CTL"        ,           0x1180010001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
22829         {"GMX1_RX003_STATS_CTL"        ,           0x1180010001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
22830         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
22831         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
22832         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
22833         {"GMX0_RX003_STATS_OCTS"       ,           0x1180008001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
22834         {"GMX1_RX000_STATS_OCTS"       ,           0x1180010000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
22835         {"GMX1_RX001_STATS_OCTS"       ,           0x1180010000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
22836         {"GMX1_RX002_STATS_OCTS"       ,           0x1180010001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
22837         {"GMX1_RX003_STATS_OCTS"       ,           0x1180010001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
22838         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
22839         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
22840         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
22841         {"GMX0_RX003_STATS_OCTS_CTL"   ,           0x1180008001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
22842         {"GMX1_RX000_STATS_OCTS_CTL"   ,           0x1180010000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
22843         {"GMX1_RX001_STATS_OCTS_CTL"   ,           0x1180010000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
22844         {"GMX1_RX002_STATS_OCTS_CTL"   ,           0x1180010001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
22845         {"GMX1_RX003_STATS_OCTS_CTL"   ,           0x1180010001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
22846         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
22847         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
22848         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
22849         {"GMX0_RX003_STATS_OCTS_DMAC"  ,           0x11800080018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
22850         {"GMX1_RX000_STATS_OCTS_DMAC"  ,           0x11800100000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
22851         {"GMX1_RX001_STATS_OCTS_DMAC"  ,           0x11800100008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
22852         {"GMX1_RX002_STATS_OCTS_DMAC"  ,           0x11800100010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
22853         {"GMX1_RX003_STATS_OCTS_DMAC"  ,           0x11800100018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
22854         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
22855         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
22856         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
22857         {"GMX0_RX003_STATS_OCTS_DRP"   ,           0x11800080018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
22858         {"GMX1_RX000_STATS_OCTS_DRP"   ,           0x11800100000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
22859         {"GMX1_RX001_STATS_OCTS_DRP"   ,           0x11800100008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
22860         {"GMX1_RX002_STATS_OCTS_DRP"   ,           0x11800100010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
22861         {"GMX1_RX003_STATS_OCTS_DRP"   ,           0x11800100018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
22862         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
22863         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
22864         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
22865         {"GMX0_RX003_STATS_PKTS"       ,           0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
22866         {"GMX1_RX000_STATS_PKTS"       ,           0x1180010000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
22867         {"GMX1_RX001_STATS_PKTS"       ,           0x1180010000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
22868         {"GMX1_RX002_STATS_PKTS"       ,           0x1180010001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
22869         {"GMX1_RX003_STATS_PKTS"       ,           0x1180010001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
22870         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
22871         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
22872         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
22873         {"GMX0_RX003_STATS_PKTS_BAD"   ,           0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
22874         {"GMX1_RX000_STATS_PKTS_BAD"   ,           0x11800100000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
22875         {"GMX1_RX001_STATS_PKTS_BAD"   ,           0x11800100008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
22876         {"GMX1_RX002_STATS_PKTS_BAD"   ,           0x11800100010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
22877         {"GMX1_RX003_STATS_PKTS_BAD"   ,           0x11800100018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
22878         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
22879         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
22880         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
22881         {"GMX0_RX003_STATS_PKTS_CTL"   ,           0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
22882         {"GMX1_RX000_STATS_PKTS_CTL"   ,           0x1180010000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
22883         {"GMX1_RX001_STATS_PKTS_CTL"   ,           0x1180010000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
22884         {"GMX1_RX002_STATS_PKTS_CTL"   ,           0x1180010001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
22885         {"GMX1_RX003_STATS_PKTS_CTL"   ,           0x1180010001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
22886         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
22887         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
22888         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
22889         {"GMX0_RX003_STATS_PKTS_DMAC"  ,           0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
22890         {"GMX1_RX000_STATS_PKTS_DMAC"  ,           0x11800100000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
22891         {"GMX1_RX001_STATS_PKTS_DMAC"  ,           0x11800100008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
22892         {"GMX1_RX002_STATS_PKTS_DMAC"  ,           0x11800100010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
22893         {"GMX1_RX003_STATS_PKTS_DMAC"  ,           0x11800100018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
22894         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
22895         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
22896         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
22897         {"GMX0_RX003_STATS_PKTS_DRP"   ,           0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
22898         {"GMX1_RX000_STATS_PKTS_DRP"   ,           0x11800100000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
22899         {"GMX1_RX001_STATS_PKTS_DRP"   ,           0x11800100008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
22900         {"GMX1_RX002_STATS_PKTS_DRP"   ,           0x11800100010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
22901         {"GMX1_RX003_STATS_PKTS_DRP"   ,           0x11800100018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
22902         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
22903         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
22904         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
22905         {"GMX0_RX003_UDD_SKP"          ,           0x1180008001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
22906         {"GMX1_RX000_UDD_SKP"          ,           0x1180010000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
22907         {"GMX1_RX001_UDD_SKP"          ,           0x1180010000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
22908         {"GMX1_RX002_UDD_SKP"          ,           0x1180010001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
22909         {"GMX1_RX003_UDD_SKP"          ,           0x1180010001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
22910         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
22911         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
22912         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
22913         {"GMX0_RX_BP_DROP003"          ,           0x1180008000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
22914         {"GMX1_RX_BP_DROP000"          ,           0x1180010000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
22915         {"GMX1_RX_BP_DROP001"          ,           0x1180010000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
22916         {"GMX1_RX_BP_DROP002"          ,           0x1180010000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
22917         {"GMX1_RX_BP_DROP003"          ,           0x1180010000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
22918         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
22919         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
22920         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
22921         {"GMX0_RX_BP_OFF003"           ,           0x1180008000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
22922         {"GMX1_RX_BP_OFF000"           ,           0x1180010000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
22923         {"GMX1_RX_BP_OFF001"           ,           0x1180010000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
22924         {"GMX1_RX_BP_OFF002"           ,           0x1180010000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
22925         {"GMX1_RX_BP_OFF003"           ,           0x1180010000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
22926         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
22927         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
22928         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
22929         {"GMX0_RX_BP_ON003"            ,           0x1180008000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
22930         {"GMX1_RX_BP_ON000"            ,           0x1180010000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
22931         {"GMX1_RX_BP_ON001"            ,           0x1180010000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
22932         {"GMX1_RX_BP_ON002"            ,           0x1180010000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
22933         {"GMX1_RX_BP_ON003"            ,           0x1180010000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
22934         {"GMX0_RX_PASS_EN"             ,           0x11800080005F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
22935         {"GMX1_RX_PASS_EN"             ,           0x11800100005F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
22936         {"GMX0_RX_PASS_MAP000"         ,           0x1180008000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22937         {"GMX0_RX_PASS_MAP001"         ,           0x1180008000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22938         {"GMX0_RX_PASS_MAP002"         ,           0x1180008000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22939         {"GMX0_RX_PASS_MAP003"         ,           0x1180008000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22940         {"GMX0_RX_PASS_MAP004"         ,           0x1180008000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22941         {"GMX0_RX_PASS_MAP005"         ,           0x1180008000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22942         {"GMX0_RX_PASS_MAP006"         ,           0x1180008000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22943         {"GMX0_RX_PASS_MAP007"         ,           0x1180008000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22944         {"GMX0_RX_PASS_MAP008"         ,           0x1180008000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22945         {"GMX0_RX_PASS_MAP009"         ,           0x1180008000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22946         {"GMX0_RX_PASS_MAP010"         ,           0x1180008000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22947         {"GMX0_RX_PASS_MAP011"         ,           0x1180008000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22948         {"GMX0_RX_PASS_MAP012"         ,           0x1180008000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22949         {"GMX0_RX_PASS_MAP013"         ,           0x1180008000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22950         {"GMX0_RX_PASS_MAP014"         ,           0x1180008000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22951         {"GMX0_RX_PASS_MAP015"         ,           0x1180008000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22952         {"GMX1_RX_PASS_MAP000"         ,           0x1180010000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22953         {"GMX1_RX_PASS_MAP001"         ,           0x1180010000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22954         {"GMX1_RX_PASS_MAP002"         ,           0x1180010000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22955         {"GMX1_RX_PASS_MAP003"         ,           0x1180010000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22956         {"GMX1_RX_PASS_MAP004"         ,           0x1180010000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22957         {"GMX1_RX_PASS_MAP005"         ,           0x1180010000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22958         {"GMX1_RX_PASS_MAP006"         ,           0x1180010000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22959         {"GMX1_RX_PASS_MAP007"         ,           0x1180010000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22960         {"GMX1_RX_PASS_MAP008"         ,           0x1180010000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22961         {"GMX1_RX_PASS_MAP009"         ,           0x1180010000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22962         {"GMX1_RX_PASS_MAP010"         ,           0x1180010000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22963         {"GMX1_RX_PASS_MAP011"         ,           0x1180010000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22964         {"GMX1_RX_PASS_MAP012"         ,           0x1180010000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22965         {"GMX1_RX_PASS_MAP013"         ,           0x1180010000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22966         {"GMX1_RX_PASS_MAP014"         ,           0x1180010000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22967         {"GMX1_RX_PASS_MAP015"         ,           0x1180010000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
22968         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
22969         {"GMX1_RX_PRT_INFO"            ,           0x11800100004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
22970         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
22971         {"GMX1_RX_PRTS"                ,           0x1180010000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
22972         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
22973         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
22974         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
22975         {"GMX0_SMAC003"                ,           0x1180008001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
22976         {"GMX1_SMAC000"                ,           0x1180010000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
22977         {"GMX1_SMAC001"                ,           0x1180010000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
22978         {"GMX1_SMAC002"                ,           0x1180010001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
22979         {"GMX1_SMAC003"                ,           0x1180010001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
22980         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
22981         {"GMX1_STAT_BP"                ,           0x1180010000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
22982         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
22983         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
22984         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
22985         {"GMX0_TX003_APPEND"           ,           0x1180008001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
22986         {"GMX1_TX000_APPEND"           ,           0x1180010000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
22987         {"GMX1_TX001_APPEND"           ,           0x1180010000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
22988         {"GMX1_TX002_APPEND"           ,           0x1180010001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
22989         {"GMX1_TX003_APPEND"           ,           0x1180010001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
22990         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
22991         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
22992         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
22993         {"GMX0_TX003_BURST"            ,           0x1180008001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
22994         {"GMX1_TX000_BURST"            ,           0x1180010000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
22995         {"GMX1_TX001_BURST"            ,           0x1180010000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
22996         {"GMX1_TX002_BURST"            ,           0x1180010001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
22997         {"GMX1_TX003_BURST"            ,           0x1180010001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
22998         {"GMX0_TX000_CLK"              ,           0x1180008000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
22999         {"GMX0_TX001_CLK"              ,           0x1180008000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
23000         {"GMX0_TX002_CLK"              ,           0x1180008001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
23001         {"GMX0_TX003_CLK"              ,           0x1180008001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
23002         {"GMX1_TX000_CLK"              ,           0x1180010000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
23003         {"GMX1_TX001_CLK"              ,           0x1180010000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
23004         {"GMX1_TX002_CLK"              ,           0x1180010001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
23005         {"GMX1_TX003_CLK"              ,           0x1180010001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
23006         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
23007         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
23008         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
23009         {"GMX0_TX003_CTL"              ,           0x1180008001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
23010         {"GMX1_TX000_CTL"              ,           0x1180010000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
23011         {"GMX1_TX001_CTL"              ,           0x1180010000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
23012         {"GMX1_TX002_CTL"              ,           0x1180010001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
23013         {"GMX1_TX003_CTL"              ,           0x1180010001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
23014         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
23015         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
23016         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
23017         {"GMX0_TX003_MIN_PKT"          ,           0x1180008001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
23018         {"GMX1_TX000_MIN_PKT"          ,           0x1180010000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
23019         {"GMX1_TX001_MIN_PKT"          ,           0x1180010000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
23020         {"GMX1_TX002_MIN_PKT"          ,           0x1180010001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
23021         {"GMX1_TX003_MIN_PKT"          ,           0x1180010001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
23022         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
23023         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
23024         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
23025         {"GMX0_TX003_PAUSE_PKT_INTERVAL",          0x1180008001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
23026         {"GMX1_TX000_PAUSE_PKT_INTERVAL",          0x1180010000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
23027         {"GMX1_TX001_PAUSE_PKT_INTERVAL",          0x1180010000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
23028         {"GMX1_TX002_PAUSE_PKT_INTERVAL",          0x1180010001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
23029         {"GMX1_TX003_PAUSE_PKT_INTERVAL",          0x1180010001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
23030         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
23031         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
23032         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
23033         {"GMX0_TX003_PAUSE_PKT_TIME"   ,           0x1180008001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
23034         {"GMX1_TX000_PAUSE_PKT_TIME"   ,           0x1180010000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
23035         {"GMX1_TX001_PAUSE_PKT_TIME"   ,           0x1180010000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
23036         {"GMX1_TX002_PAUSE_PKT_TIME"   ,           0x1180010001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
23037         {"GMX1_TX003_PAUSE_PKT_TIME"   ,           0x1180010001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
23038         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
23039         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
23040         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
23041         {"GMX0_TX003_PAUSE_TOGO"       ,           0x1180008001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
23042         {"GMX1_TX000_PAUSE_TOGO"       ,           0x1180010000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
23043         {"GMX1_TX001_PAUSE_TOGO"       ,           0x1180010000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
23044         {"GMX1_TX002_PAUSE_TOGO"       ,           0x1180010001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
23045         {"GMX1_TX003_PAUSE_TOGO"       ,           0x1180010001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
23046         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
23047         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
23048         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
23049         {"GMX0_TX003_PAUSE_ZERO"       ,           0x1180008001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
23050         {"GMX1_TX000_PAUSE_ZERO"       ,           0x1180010000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
23051         {"GMX1_TX001_PAUSE_ZERO"       ,           0x1180010000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
23052         {"GMX1_TX002_PAUSE_ZERO"       ,           0x1180010001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
23053         {"GMX1_TX003_PAUSE_ZERO"       ,           0x1180010001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
23054         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
23055         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
23056         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
23057         {"GMX0_TX003_SLOT"             ,           0x1180008001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
23058         {"GMX1_TX000_SLOT"             ,           0x1180010000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
23059         {"GMX1_TX001_SLOT"             ,           0x1180010000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
23060         {"GMX1_TX002_SLOT"             ,           0x1180010001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
23061         {"GMX1_TX003_SLOT"             ,           0x1180010001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
23062         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
23063         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
23064         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
23065         {"GMX0_TX003_SOFT_PAUSE"       ,           0x1180008001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
23066         {"GMX1_TX000_SOFT_PAUSE"       ,           0x1180010000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
23067         {"GMX1_TX001_SOFT_PAUSE"       ,           0x1180010000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
23068         {"GMX1_TX002_SOFT_PAUSE"       ,           0x1180010001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
23069         {"GMX1_TX003_SOFT_PAUSE"       ,           0x1180010001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
23070         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
23071         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
23072         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
23073         {"GMX0_TX003_STAT0"            ,           0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
23074         {"GMX1_TX000_STAT0"            ,           0x1180010000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
23075         {"GMX1_TX001_STAT0"            ,           0x1180010000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
23076         {"GMX1_TX002_STAT0"            ,           0x1180010001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
23077         {"GMX1_TX003_STAT0"            ,           0x1180010001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
23078         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
23079         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
23080         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
23081         {"GMX0_TX003_STAT1"            ,           0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
23082         {"GMX1_TX000_STAT1"            ,           0x1180010000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
23083         {"GMX1_TX001_STAT1"            ,           0x1180010000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
23084         {"GMX1_TX002_STAT1"            ,           0x1180010001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
23085         {"GMX1_TX003_STAT1"            ,           0x1180010001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
23086         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
23087         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
23088         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
23089         {"GMX0_TX003_STAT2"            ,           0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
23090         {"GMX1_TX000_STAT2"            ,           0x1180010000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
23091         {"GMX1_TX001_STAT2"            ,           0x1180010000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
23092         {"GMX1_TX002_STAT2"            ,           0x1180010001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
23093         {"GMX1_TX003_STAT2"            ,           0x1180010001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
23094         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
23095         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
23096         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
23097         {"GMX0_TX003_STAT3"            ,           0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
23098         {"GMX1_TX000_STAT3"            ,           0x1180010000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
23099         {"GMX1_TX001_STAT3"            ,           0x1180010000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
23100         {"GMX1_TX002_STAT3"            ,           0x1180010001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
23101         {"GMX1_TX003_STAT3"            ,           0x1180010001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
23102         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
23103         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
23104         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
23105         {"GMX0_TX003_STAT4"            ,           0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
23106         {"GMX1_TX000_STAT4"            ,           0x11800100002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
23107         {"GMX1_TX001_STAT4"            ,           0x1180010000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
23108         {"GMX1_TX002_STAT4"            ,           0x11800100012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
23109         {"GMX1_TX003_STAT4"            ,           0x1180010001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
23110         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
23111         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
23112         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
23113         {"GMX0_TX003_STAT5"            ,           0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
23114         {"GMX1_TX000_STAT5"            ,           0x11800100002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
23115         {"GMX1_TX001_STAT5"            ,           0x1180010000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
23116         {"GMX1_TX002_STAT5"            ,           0x11800100012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
23117         {"GMX1_TX003_STAT5"            ,           0x1180010001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
23118         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
23119         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
23120         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
23121         {"GMX0_TX003_STAT6"            ,           0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
23122         {"GMX1_TX000_STAT6"            ,           0x11800100002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
23123         {"GMX1_TX001_STAT6"            ,           0x1180010000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
23124         {"GMX1_TX002_STAT6"            ,           0x11800100012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
23125         {"GMX1_TX003_STAT6"            ,           0x1180010001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
23126         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
23127         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
23128         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
23129         {"GMX0_TX003_STAT7"            ,           0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
23130         {"GMX1_TX000_STAT7"            ,           0x11800100002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
23131         {"GMX1_TX001_STAT7"            ,           0x1180010000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
23132         {"GMX1_TX002_STAT7"            ,           0x11800100012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
23133         {"GMX1_TX003_STAT7"            ,           0x1180010001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
23134         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
23135         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
23136         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
23137         {"GMX0_TX003_STAT8"            ,           0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
23138         {"GMX1_TX000_STAT8"            ,           0x11800100002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
23139         {"GMX1_TX001_STAT8"            ,           0x1180010000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
23140         {"GMX1_TX002_STAT8"            ,           0x11800100012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
23141         {"GMX1_TX003_STAT8"            ,           0x1180010001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
23142         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
23143         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
23144         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
23145         {"GMX0_TX003_STAT9"            ,           0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
23146         {"GMX1_TX000_STAT9"            ,           0x11800100002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
23147         {"GMX1_TX001_STAT9"            ,           0x1180010000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
23148         {"GMX1_TX002_STAT9"            ,           0x11800100012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
23149         {"GMX1_TX003_STAT9"            ,           0x1180010001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
23150         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
23151         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
23152         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
23153         {"GMX0_TX003_STATS_CTL"        ,           0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
23154         {"GMX1_TX000_STATS_CTL"        ,           0x1180010000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
23155         {"GMX1_TX001_STATS_CTL"        ,           0x1180010000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
23156         {"GMX1_TX002_STATS_CTL"        ,           0x1180010001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
23157         {"GMX1_TX003_STATS_CTL"        ,           0x1180010001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
23158         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
23159         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
23160         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
23161         {"GMX0_TX003_THRESH"           ,           0x1180008001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
23162         {"GMX1_TX000_THRESH"           ,           0x1180010000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
23163         {"GMX1_TX001_THRESH"           ,           0x1180010000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
23164         {"GMX1_TX002_THRESH"           ,           0x1180010001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
23165         {"GMX1_TX003_THRESH"           ,           0x1180010001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
23166         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
23167         {"GMX1_TX_BP"                  ,           0x11800100004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
23168         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
23169         {"GMX1_TX_COL_ATTEMPT"         ,           0x1180010000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
23170         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
23171         {"GMX1_TX_CORRUPT"             ,           0x11800100004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
23172         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
23173         {"GMX1_TX_IFG"                 ,           0x1180010000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
23174         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
23175         {"GMX1_TX_INT_EN"              ,           0x1180010000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
23176         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
23177         {"GMX1_TX_INT_REG"             ,           0x1180010000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
23178         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
23179         {"GMX1_TX_JAM"                 ,           0x1180010000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
23180         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
23181         {"GMX1_TX_LFSR"                ,           0x11800100004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
23182         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
23183         {"GMX1_TX_OVR_BP"              ,           0x11800100004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
23184         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
23185         {"GMX1_TX_PAUSE_PKT_DMAC"      ,           0x11800100004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
23186         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
23187         {"GMX1_TX_PAUSE_PKT_TYPE"      ,           0x11800100004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
23188         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
23189         {"GMX1_TX_PRTS"                ,           0x1180010000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
23190         {"GMX0_TX_SPI_CTL"             ,           0x11800080004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
23191         {"GMX1_TX_SPI_CTL"             ,           0x11800100004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
23192         {"GMX0_TX_SPI_DRAIN"           ,           0x11800080004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
23193         {"GMX1_TX_SPI_DRAIN"           ,           0x11800100004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
23194         {"GMX0_TX_SPI_MAX"             ,           0x11800080004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
23195         {"GMX1_TX_SPI_MAX"             ,           0x11800100004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
23196         {"GMX0_TX_SPI_ROUND000"        ,           0x1180008000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23197         {"GMX0_TX_SPI_ROUND001"        ,           0x1180008000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23198         {"GMX0_TX_SPI_ROUND002"        ,           0x1180008000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23199         {"GMX0_TX_SPI_ROUND003"        ,           0x1180008000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23200         {"GMX0_TX_SPI_ROUND004"        ,           0x11800080006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23201         {"GMX0_TX_SPI_ROUND005"        ,           0x11800080006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23202         {"GMX0_TX_SPI_ROUND006"        ,           0x11800080006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23203         {"GMX0_TX_SPI_ROUND007"        ,           0x11800080006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23204         {"GMX0_TX_SPI_ROUND008"        ,           0x11800080006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23205         {"GMX0_TX_SPI_ROUND009"        ,           0x11800080006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23206         {"GMX0_TX_SPI_ROUND010"        ,           0x11800080006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23207         {"GMX0_TX_SPI_ROUND011"        ,           0x11800080006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23208         {"GMX0_TX_SPI_ROUND012"        ,           0x11800080006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23209         {"GMX0_TX_SPI_ROUND013"        ,           0x11800080006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23210         {"GMX0_TX_SPI_ROUND014"        ,           0x11800080006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23211         {"GMX0_TX_SPI_ROUND015"        ,           0x11800080006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23212         {"GMX0_TX_SPI_ROUND016"        ,           0x1180008000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23213         {"GMX0_TX_SPI_ROUND017"        ,           0x1180008000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23214         {"GMX0_TX_SPI_ROUND018"        ,           0x1180008000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23215         {"GMX0_TX_SPI_ROUND019"        ,           0x1180008000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23216         {"GMX0_TX_SPI_ROUND020"        ,           0x1180008000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23217         {"GMX0_TX_SPI_ROUND021"        ,           0x1180008000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23218         {"GMX0_TX_SPI_ROUND022"        ,           0x1180008000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23219         {"GMX0_TX_SPI_ROUND023"        ,           0x1180008000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23220         {"GMX0_TX_SPI_ROUND024"        ,           0x1180008000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23221         {"GMX0_TX_SPI_ROUND025"        ,           0x1180008000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23222         {"GMX0_TX_SPI_ROUND026"        ,           0x1180008000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23223         {"GMX0_TX_SPI_ROUND027"        ,           0x1180008000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23224         {"GMX0_TX_SPI_ROUND028"        ,           0x1180008000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23225         {"GMX0_TX_SPI_ROUND029"        ,           0x1180008000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23226         {"GMX0_TX_SPI_ROUND030"        ,           0x1180008000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23227         {"GMX0_TX_SPI_ROUND031"        ,           0x1180008000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23228         {"GMX1_TX_SPI_ROUND000"        ,           0x1180010000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23229         {"GMX1_TX_SPI_ROUND001"        ,           0x1180010000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23230         {"GMX1_TX_SPI_ROUND002"        ,           0x1180010000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23231         {"GMX1_TX_SPI_ROUND003"        ,           0x1180010000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23232         {"GMX1_TX_SPI_ROUND004"        ,           0x11800100006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23233         {"GMX1_TX_SPI_ROUND005"        ,           0x11800100006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23234         {"GMX1_TX_SPI_ROUND006"        ,           0x11800100006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23235         {"GMX1_TX_SPI_ROUND007"        ,           0x11800100006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23236         {"GMX1_TX_SPI_ROUND008"        ,           0x11800100006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23237         {"GMX1_TX_SPI_ROUND009"        ,           0x11800100006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23238         {"GMX1_TX_SPI_ROUND010"        ,           0x11800100006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23239         {"GMX1_TX_SPI_ROUND011"        ,           0x11800100006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23240         {"GMX1_TX_SPI_ROUND012"        ,           0x11800100006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23241         {"GMX1_TX_SPI_ROUND013"        ,           0x11800100006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23242         {"GMX1_TX_SPI_ROUND014"        ,           0x11800100006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23243         {"GMX1_TX_SPI_ROUND015"        ,           0x11800100006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23244         {"GMX1_TX_SPI_ROUND016"        ,           0x1180010000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23245         {"GMX1_TX_SPI_ROUND017"        ,           0x1180010000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23246         {"GMX1_TX_SPI_ROUND018"        ,           0x1180010000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23247         {"GMX1_TX_SPI_ROUND019"        ,           0x1180010000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23248         {"GMX1_TX_SPI_ROUND020"        ,           0x1180010000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23249         {"GMX1_TX_SPI_ROUND021"        ,           0x1180010000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23250         {"GMX1_TX_SPI_ROUND022"        ,           0x1180010000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23251         {"GMX1_TX_SPI_ROUND023"        ,           0x1180010000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23252         {"GMX1_TX_SPI_ROUND024"        ,           0x1180010000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23253         {"GMX1_TX_SPI_ROUND025"        ,           0x1180010000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23254         {"GMX1_TX_SPI_ROUND026"        ,           0x1180010000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23255         {"GMX1_TX_SPI_ROUND027"        ,           0x1180010000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23256         {"GMX1_TX_SPI_ROUND028"        ,           0x1180010000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23257         {"GMX1_TX_SPI_ROUND029"        ,           0x1180010000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23258         {"GMX1_TX_SPI_ROUND030"        ,           0x1180010000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23259         {"GMX1_TX_SPI_ROUND031"        ,           0x1180010000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
23260         {"GMX0_TX_SPI_THRESH"          ,           0x11800080004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
23261         {"GMX1_TX_SPI_THRESH"          ,           0x11800100004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
23262         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23263         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23264         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23265         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23266         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23267         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23268         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23269         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23270         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23271         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23272         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23273         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23274         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23275         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23276         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23277         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
23278         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     162},
23279         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
23280         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
23281         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     165},
23282         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
23283         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
23284         {"IOB_DWB_PRI_CNT"             ,           0x11800F0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
23285         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
23286         {"IOB_I2C_PRI_CNT"             ,           0x11800F0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
23287         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
23288         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
23289         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
23290         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
23291         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
23292         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
23293         {"IOB_N2C_L2C_PRI_CNT"         ,           0x11800F0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
23294         {"IOB_N2C_RSP_PRI_CNT"         ,           0x11800F0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
23295         {"IOB_OUTB_COM_PRI_CNT"        ,           0x11800F0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
23296         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
23297         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
23298         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
23299         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
23300         {"IOB_OUTB_FPA_PRI_CNT"        ,           0x11800F0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
23301         {"IOB_OUTB_REQ_PRI_CNT"        ,           0x11800F0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
23302         {"IOB_P2C_REQ_PRI_CNT"         ,           0x11800F0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
23303         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
23304         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     188},
23305         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     189},
23306         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     190},
23307         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
23308         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
23309         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     193},
23310         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     194},
23311         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     195},
23312         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
23313         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
23314         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     198},
23315         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
23316         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23317         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23318         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23319         {"IPD_PORT3_BP_PAGE_CNT"       ,           0x14F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23320         {"IPD_PORT4_BP_PAGE_CNT"       ,           0x14F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23321         {"IPD_PORT5_BP_PAGE_CNT"       ,           0x14F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23322         {"IPD_PORT6_BP_PAGE_CNT"       ,           0x14F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23323         {"IPD_PORT7_BP_PAGE_CNT"       ,           0x14F0000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23324         {"IPD_PORT8_BP_PAGE_CNT"       ,           0x14F0000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23325         {"IPD_PORT9_BP_PAGE_CNT"       ,           0x14F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23326         {"IPD_PORT10_BP_PAGE_CNT"      ,           0x14F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23327         {"IPD_PORT11_BP_PAGE_CNT"      ,           0x14F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23328         {"IPD_PORT12_BP_PAGE_CNT"      ,           0x14F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23329         {"IPD_PORT13_BP_PAGE_CNT"      ,           0x14F0000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23330         {"IPD_PORT14_BP_PAGE_CNT"      ,           0x14F0000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23331         {"IPD_PORT15_BP_PAGE_CNT"      ,           0x14F00000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23332         {"IPD_PORT16_BP_PAGE_CNT"      ,           0x14F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23333         {"IPD_PORT17_BP_PAGE_CNT"      ,           0x14F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23334         {"IPD_PORT18_BP_PAGE_CNT"      ,           0x14F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23335         {"IPD_PORT19_BP_PAGE_CNT"      ,           0x14F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23336         {"IPD_PORT20_BP_PAGE_CNT"      ,           0x14F00000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23337         {"IPD_PORT21_BP_PAGE_CNT"      ,           0x14F00000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23338         {"IPD_PORT22_BP_PAGE_CNT"      ,           0x14F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23339         {"IPD_PORT23_BP_PAGE_CNT"      ,           0x14F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23340         {"IPD_PORT24_BP_PAGE_CNT"      ,           0x14F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23341         {"IPD_PORT25_BP_PAGE_CNT"      ,           0x14F00000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23342         {"IPD_PORT26_BP_PAGE_CNT"      ,           0x14F00000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23343         {"IPD_PORT27_BP_PAGE_CNT"      ,           0x14F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23344         {"IPD_PORT28_BP_PAGE_CNT"      ,           0x14F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23345         {"IPD_PORT29_BP_PAGE_CNT"      ,           0x14F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23346         {"IPD_PORT30_BP_PAGE_CNT"      ,           0x14F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23347         {"IPD_PORT31_BP_PAGE_CNT"      ,           0x14F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23348         {"IPD_PORT32_BP_PAGE_CNT"      ,           0x14F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23349         {"IPD_PORT33_BP_PAGE_CNT"      ,           0x14F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23350         {"IPD_PORT34_BP_PAGE_CNT"      ,           0x14F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23351         {"IPD_PORT35_BP_PAGE_CNT"      ,           0x14F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
23352         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23353         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23354         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23355         {"IPD_PORT_BP_COUNTERS_PAIR3"  ,           0x14F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23356         {"IPD_PORT_BP_COUNTERS_PAIR4"  ,           0x14F00000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23357         {"IPD_PORT_BP_COUNTERS_PAIR5"  ,           0x14F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23358         {"IPD_PORT_BP_COUNTERS_PAIR6"  ,           0x14F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23359         {"IPD_PORT_BP_COUNTERS_PAIR7"  ,           0x14F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23360         {"IPD_PORT_BP_COUNTERS_PAIR8"  ,           0x14F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23361         {"IPD_PORT_BP_COUNTERS_PAIR9"  ,           0x14F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23362         {"IPD_PORT_BP_COUNTERS_PAIR10" ,           0x14F0000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23363         {"IPD_PORT_BP_COUNTERS_PAIR11" ,           0x14F0000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23364         {"IPD_PORT_BP_COUNTERS_PAIR12" ,           0x14F0000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23365         {"IPD_PORT_BP_COUNTERS_PAIR13" ,           0x14F0000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23366         {"IPD_PORT_BP_COUNTERS_PAIR14" ,           0x14F0000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23367         {"IPD_PORT_BP_COUNTERS_PAIR15" ,           0x14F0000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23368         {"IPD_PORT_BP_COUNTERS_PAIR16" ,           0x14F0000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23369         {"IPD_PORT_BP_COUNTERS_PAIR17" ,           0x14F0000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23370         {"IPD_PORT_BP_COUNTERS_PAIR18" ,           0x14F0000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23371         {"IPD_PORT_BP_COUNTERS_PAIR19" ,           0x14F0000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23372         {"IPD_PORT_BP_COUNTERS_PAIR20" ,           0x14F0000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23373         {"IPD_PORT_BP_COUNTERS_PAIR21" ,           0x14F0000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23374         {"IPD_PORT_BP_COUNTERS_PAIR22" ,           0x14F0000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23375         {"IPD_PORT_BP_COUNTERS_PAIR23" ,           0x14F0000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23376         {"IPD_PORT_BP_COUNTERS_PAIR24" ,           0x14F0000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23377         {"IPD_PORT_BP_COUNTERS_PAIR25" ,           0x14F0000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23378         {"IPD_PORT_BP_COUNTERS_PAIR26" ,           0x14F0000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23379         {"IPD_PORT_BP_COUNTERS_PAIR27" ,           0x14F0000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23380         {"IPD_PORT_BP_COUNTERS_PAIR28" ,           0x14F0000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23381         {"IPD_PORT_BP_COUNTERS_PAIR29" ,           0x14F00000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23382         {"IPD_PORT_BP_COUNTERS_PAIR30" ,           0x14F00000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23383         {"IPD_PORT_BP_COUNTERS_PAIR31" ,           0x14F00000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23384         {"IPD_PORT_BP_COUNTERS_PAIR32" ,           0x14F00000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23385         {"IPD_PORT_BP_COUNTERS_PAIR33" ,           0x14F00000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23386         {"IPD_PORT_BP_COUNTERS_PAIR34" ,           0x14F00000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23387         {"IPD_PORT_BP_COUNTERS_PAIR35" ,           0x14F00000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
23388         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
23389         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     203},
23390         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     204},
23391         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
23392         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
23393         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
23394         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
23395         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
23396         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
23397         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
23398         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
23399         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
23400         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     207},
23401         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
23402         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
23403         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
23404         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
23405         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
23406         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
23407         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
23408         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
23409         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
23410         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     210},
23411         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     211},
23412         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     212},
23413         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     213},
23414         {"KEY_BIST_REG"                ,           0x1180020000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
23415         {"KEY_CTL_STATUS"              ,           0x1180020000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
23416         {"KEY_INT_ENB"                 ,           0x1180020000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
23417         {"KEY_INT_SUM"                 ,           0x1180020000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
23418         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
23419         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     219},
23420         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     220},
23421         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     221},
23422         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
23423         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
23424         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
23425         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     225},
23426         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     226},
23427         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     227},
23428         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
23429         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
23430         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
23431         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
23432         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
23433         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
23434         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
23435         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     232},
23436         {"L2C_SPAR1"                   ,           0x1180080000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
23437         {"L2C_SPAR2"                   ,           0x1180080000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     234},
23438         {"L2C_SPAR3"                   ,           0x1180080000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     235},
23439         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     236},
23440         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     237},
23441         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
23442         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     239},
23443         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     240},
23444         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
23445         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
23446         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     243},
23447         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     244},
23448         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     245},
23449         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     246},
23450         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     247},
23451         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     248},
23452         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     249},
23453         {"LED_BLINK"                   ,           0x1180000001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
23454         {"LED_CLK_PHASE"               ,           0x1180000001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
23455         {"LED_CYLON"                   ,           0x1180000001AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
23456         {"LED_DBG"                     ,           0x1180000001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
23457         {"LED_EN"                      ,           0x1180000001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
23458         {"LED_POLARITY"                ,           0x1180000001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
23459         {"LED_PRT"                     ,           0x1180000001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
23460         {"LED_PRT_FMT"                 ,           0x1180000001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
23461         {"LED_PRT_STATUS0"             ,           0x1180000001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
23462         {"LED_PRT_STATUS1"             ,           0x1180000001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
23463         {"LED_PRT_STATUS2"             ,           0x1180000001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
23464         {"LED_PRT_STATUS3"             ,           0x1180000001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
23465         {"LED_PRT_STATUS4"             ,           0x1180000001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
23466         {"LED_PRT_STATUS5"             ,           0x1180000001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
23467         {"LED_PRT_STATUS6"             ,           0x1180000001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
23468         {"LED_PRT_STATUS7"             ,           0x1180000001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
23469         {"LED_UDD_CNT0"                ,           0x1180000001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
23470         {"LED_UDD_CNT1"                ,           0x1180000001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
23471         {"LED_UDD_DAT0"                ,           0x1180000001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
23472         {"LED_UDD_DAT1"                ,           0x1180000001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
23473         {"LED_UDD_DAT_CLR0"            ,           0x1180000001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
23474         {"LED_UDD_DAT_CLR1"            ,           0x1180000001AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
23475         {"LED_UDD_DAT_SET0"            ,           0x1180000001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
23476         {"LED_UDD_DAT_SET1"            ,           0x1180000001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
23477         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
23478         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
23479         {"LMC0_CTL1"                   ,           0x1180088000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
23480         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
23481         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
23482         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
23483         {"LMC0_DELAY_CFG"              ,           0x1180088000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
23484         {"LMC0_DUAL_MEMCFG"            ,           0x1180088000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
23485         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
23486         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
23487         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
23488         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
23489         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
23490         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
23491         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
23492         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
23493         {"LMC0_PLL_CTL"                ,           0x11800880000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
23494         {"LMC0_PLL_STATUS"             ,           0x11800880000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
23495         {"LMC0_RODT_COMP_CTL"          ,           0x11800880000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
23496         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
23497         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
23498         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
23499         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
23500         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
23501         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     287},
23502         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     288},
23503         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     288},
23504         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     289},
23505         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
23506         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
23507         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
23508         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
23509         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
23510         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
23511         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
23512         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
23513         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
23514         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
23515         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
23516         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
23517         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
23518         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
23519         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
23520         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
23521         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     292},
23522         {"MIO_FUS_BNK_DAT0"            ,           0x1180000001520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
23523         {"MIO_FUS_BNK_DAT1"            ,           0x1180000001528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
23524         {"MIO_FUS_BNK_DAT2"            ,           0x1180000001530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
23525         {"MIO_FUS_BNK_DAT3"            ,           0x1180000001538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
23526         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     294},
23527         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     295},
23528         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     296},
23529         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
23530         {"MIO_FUS_EMA"                 ,           0x1180000001550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     298},
23531         {"MIO_FUS_PLL"                 ,           0x1180000001580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
23532         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
23533         {"MIO_FUS_PROG_TIMES"          ,           0x1180000001518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
23534         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
23535         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
23536         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
23537         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
23538         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
23539         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
23540         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
23541         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
23542         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
23543         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
23544         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
23545         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
23546         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
23547         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
23548         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
23549         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
23550         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
23551         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
23552         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
23553         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
23554         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
23555         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
23556         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
23557         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
23558         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
23559         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
23560         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
23561         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
23562         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
23563         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
23564         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
23565         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
23566         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
23567         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
23568         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
23569         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
23570         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
23571         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
23572         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
23573         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
23574         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
23575         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
23576         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
23577         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
23578         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
23579         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
23580         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
23581         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
23582         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
23583         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
23584         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
23585         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
23586         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
23587         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
23588         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
23589         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
23590         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
23591         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
23592         {"NPI_BASE_ADDR_INPUT0"        ,           0x11F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     335},
23593         {"NPI_BASE_ADDR_INPUT1"        ,           0x11F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     335},
23594         {"NPI_BASE_ADDR_INPUT2"        ,           0x11F0000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     335},
23595         {"NPI_BASE_ADDR_INPUT3"        ,           0x11F00000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     335},
23596         {"NPI_BASE_ADDR_OUTPUT0"       ,           0x11F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     336},
23597         {"NPI_BASE_ADDR_OUTPUT1"       ,           0x11F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     336},
23598         {"NPI_BASE_ADDR_OUTPUT2"       ,           0x11F00000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     336},
23599         {"NPI_BASE_ADDR_OUTPUT3"       ,           0x11F00000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     336},
23600         {"NPI_BIST_STATUS"             ,           0x11F00000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     337},
23601         {"NPI_BUFF_SIZE_OUTPUT0"       ,           0x11F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     338},
23602         {"NPI_BUFF_SIZE_OUTPUT1"       ,           0x11F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     338},
23603         {"NPI_BUFF_SIZE_OUTPUT2"       ,           0x11F00000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     338},
23604         {"NPI_BUFF_SIZE_OUTPUT3"       ,           0x11F00000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     338},
23605         {"NPI_COMP_CTL"                ,           0x11F0000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     339},
23606         {"NPI_CTL_STATUS"              ,           0x11F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     340},
23607         {"NPI_DBG_SELECT"              ,           0x11F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     341},
23608         {"NPI_DMA_CONTROL"             ,           0x11F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     342},
23609         {"NPI_DMA_HIGHP_COUNTS"        ,           0x11F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     343},
23610         {"NPI_DMA_HIGHP_NADDR"         ,           0x11F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     344},
23611         {"NPI_DMA_LOWP_COUNTS"         ,           0x11F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     345},
23612         {"NPI_DMA_LOWP_NADDR"          ,           0x11F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
23613         {"NPI_HIGHP_DBELL"             ,           0x11F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     347},
23614         {"NPI_HIGHP_IBUFF_SADDR"       ,           0x11F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
23615         {"NPI_INPUT_CONTROL"           ,           0x11F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     349},
23616         {"NPI_INT_ENB"                 ,           0x11F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     350},
23617         {"NPI_INT_SUM"                 ,           0x11F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
23618         {"NPI_LOWP_DBELL"              ,           0x11F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     352},
23619         {"NPI_LOWP_IBUFF_SADDR"        ,           0x11F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     353},
23620         {"NPI_MEM_ACCESS_SUBID3"       ,           0x11F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     354},
23621         {"NPI_MEM_ACCESS_SUBID4"       ,           0x11F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     354},
23622         {"NPI_MEM_ACCESS_SUBID5"       ,           0x11F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     354},
23623         {"NPI_MEM_ACCESS_SUBID6"       ,           0x11F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     354},
23624         {"NPI_MSI_RCV"                 ,           0x11F0000001190ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     355},
23625         {"NPI_NUM_DESC_OUTPUT0"        ,           0x11F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     356},
23626         {"NPI_NUM_DESC_OUTPUT1"        ,           0x11F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     356},
23627         {"NPI_NUM_DESC_OUTPUT2"        ,           0x11F0000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     356},
23628         {"NPI_NUM_DESC_OUTPUT3"        ,           0x11F0000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     356},
23629         {"NPI_OUTPUT_CONTROL"          ,           0x11F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     357},
23630         {"NPI_P0_DBPAIR_ADDR"          ,           0x11F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     358},
23631         {"NPI_P1_DBPAIR_ADDR"          ,           0x11F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     358},
23632         {"NPI_P2_DBPAIR_ADDR"          ,           0x11F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     358},
23633         {"NPI_P3_DBPAIR_ADDR"          ,           0x11F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     358},
23634         {"NPI_P0_INSTR_ADDR"           ,           0x11F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     359},
23635         {"NPI_P1_INSTR_ADDR"           ,           0x11F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     359},
23636         {"NPI_P2_INSTR_ADDR"           ,           0x11F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     359},
23637         {"NPI_P3_INSTR_ADDR"           ,           0x11F00000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     359},
23638         {"NPI_P0_INSTR_CNTS"           ,           0x11F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     360},
23639         {"NPI_P1_INSTR_CNTS"           ,           0x11F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     360},
23640         {"NPI_P2_INSTR_CNTS"           ,           0x11F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     360},
23641         {"NPI_P3_INSTR_CNTS"           ,           0x11F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     360},
23642         {"NPI_P0_PAIR_CNTS"            ,           0x11F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     361},
23643         {"NPI_P1_PAIR_CNTS"            ,           0x11F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     361},
23644         {"NPI_P2_PAIR_CNTS"            ,           0x11F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     361},
23645         {"NPI_P3_PAIR_CNTS"            ,           0x11F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     361},
23646         {"NPI_PCI_BURST_SIZE"          ,           0x11F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     362},
23647         {"NPI_PCI_INT_ARB_CFG"         ,           0x11F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     363},
23648         {"NPI_PCI_READ_CMD"            ,           0x11F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     364},
23649         {"NPI_PORT32_INSTR_HDR"        ,           0x11F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     365},
23650         {"NPI_PORT33_INSTR_HDR"        ,           0x11F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     366},
23651         {"NPI_PORT34_INSTR_HDR"        ,           0x11F0000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     367},
23652         {"NPI_PORT35_INSTR_HDR"        ,           0x11F0000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     368},
23653         {"NPI_PORT_BP_CONTROL"         ,           0x11F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     369},
23654         {"NPI_RSL_INT_BLOCKS"          ,           0x11F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     370},
23655         {"NPI_SIZE_INPUT0"             ,           0x11F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
23656         {"NPI_SIZE_INPUT1"             ,           0x11F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
23657         {"NPI_SIZE_INPUT2"             ,           0x11F0000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
23658         {"NPI_SIZE_INPUT3"             ,           0x11F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
23659         {"NPI_WIN_READ_TO"             ,           0x11F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     372},
23660         {"PCI_BAR1_INDEX0"             ,           0x11F0000001100ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23661         {"PCI_BAR1_INDEX1"             ,           0x11F0000001104ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23662         {"PCI_BAR1_INDEX2"             ,           0x11F0000001108ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23663         {"PCI_BAR1_INDEX3"             ,           0x11F000000110Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23664         {"PCI_BAR1_INDEX4"             ,           0x11F0000001110ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23665         {"PCI_BAR1_INDEX5"             ,           0x11F0000001114ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23666         {"PCI_BAR1_INDEX6"             ,           0x11F0000001118ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23667         {"PCI_BAR1_INDEX7"             ,           0x11F000000111Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23668         {"PCI_BAR1_INDEX8"             ,           0x11F0000001120ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23669         {"PCI_BAR1_INDEX9"             ,           0x11F0000001124ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23670         {"PCI_BAR1_INDEX10"            ,           0x11F0000001128ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23671         {"PCI_BAR1_INDEX11"            ,           0x11F000000112Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23672         {"PCI_BAR1_INDEX12"            ,           0x11F0000001130ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23673         {"PCI_BAR1_INDEX13"            ,           0x11F0000001134ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23674         {"PCI_BAR1_INDEX14"            ,           0x11F0000001138ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23675         {"PCI_BAR1_INDEX15"            ,           0x11F000000113Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23676         {"PCI_BAR1_INDEX16"            ,           0x11F0000001140ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23677         {"PCI_BAR1_INDEX17"            ,           0x11F0000001144ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23678         {"PCI_BAR1_INDEX18"            ,           0x11F0000001148ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23679         {"PCI_BAR1_INDEX19"            ,           0x11F000000114Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23680         {"PCI_BAR1_INDEX20"            ,           0x11F0000001150ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23681         {"PCI_BAR1_INDEX21"            ,           0x11F0000001154ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23682         {"PCI_BAR1_INDEX22"            ,           0x11F0000001158ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23683         {"PCI_BAR1_INDEX23"            ,           0x11F000000115Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23684         {"PCI_BAR1_INDEX24"            ,           0x11F0000001160ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23685         {"PCI_BAR1_INDEX25"            ,           0x11F0000001164ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23686         {"PCI_BAR1_INDEX26"            ,           0x11F0000001168ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23687         {"PCI_BAR1_INDEX27"            ,           0x11F000000116Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23688         {"PCI_BAR1_INDEX28"            ,           0x11F0000001170ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23689         {"PCI_BAR1_INDEX29"            ,           0x11F0000001174ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23690         {"PCI_BAR1_INDEX30"            ,           0x11F0000001178ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23691         {"PCI_BAR1_INDEX31"            ,           0x11F000000117Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     373},
23692         {"PCI_CFG00"                   ,           0x11F0000001800ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     374},
23693         {"PCI_CFG01"                   ,           0x11F0000001804ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     375},
23694         {"PCI_CFG02"                   ,           0x11F0000001808ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     376},
23695         {"PCI_CFG03"                   ,           0x11F000000180Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     377},
23696         {"PCI_CFG04"                   ,           0x11F0000001810ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     378},
23697         {"PCI_CFG05"                   ,           0x11F0000001814ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     379},
23698         {"PCI_CFG06"                   ,           0x11F0000001818ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     380},
23699         {"PCI_CFG07"                   ,           0x11F000000181Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     381},
23700         {"PCI_CFG08"                   ,           0x11F0000001820ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     382},
23701         {"PCI_CFG09"                   ,           0x11F0000001824ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     383},
23702         {"PCI_CFG10"                   ,           0x11F0000001828ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     384},
23703         {"PCI_CFG11"                   ,           0x11F000000182Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     385},
23704         {"PCI_CFG12"                   ,           0x11F0000001830ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     386},
23705         {"PCI_CFG13"                   ,           0x11F0000001834ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     387},
23706         {"PCI_CFG15"                   ,           0x11F000000183Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     388},
23707         {"PCI_CFG16"                   ,           0x11F0000001840ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     389},
23708         {"PCI_CFG17"                   ,           0x11F0000001844ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     390},
23709         {"PCI_CFG18"                   ,           0x11F0000001848ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     391},
23710         {"PCI_CFG19"                   ,           0x11F000000184Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     392},
23711         {"PCI_CFG20"                   ,           0x11F0000001850ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     393},
23712         {"PCI_CFG21"                   ,           0x11F0000001854ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     394},
23713         {"PCI_CFG22"                   ,           0x11F0000001858ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     395},
23714         {"PCI_CFG56"                   ,           0x11F00000018E0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     396},
23715         {"PCI_CFG57"                   ,           0x11F00000018E4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     397},
23716         {"PCI_CFG58"                   ,           0x11F00000018E8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     398},
23717         {"PCI_CFG59"                   ,           0x11F00000018ECull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     399},
23718         {"PCI_CFG60"                   ,           0x11F00000018F0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     400},
23719         {"PCI_CFG61"                   ,           0x11F00000018F4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     401},
23720         {"PCI_CFG62"                   ,           0x11F00000018F8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     402},
23721         {"PCI_CFG63"                   ,           0x11F00000018FCull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     403},
23722         {"PCI_CNT_REG"                 ,           0x11F00000011B8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     404},
23723         {"PCI_CTL_STATUS_2"            ,           0x11F000000118Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     405},
23724         {"PCI_DBELL0"                  ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCI,   32,     406},
23725         {"PCI_DBELL1"                  ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCI,   32,     406},
23726         {"PCI_DBELL2"                  ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCI,   32,     406},
23727         {"PCI_DBELL3"                  ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCI,   32,     406},
23728         {"PCI_DMA_CNT0"                ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     407},
23729         {"PCI_DMA_CNT1"                ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCI,   32,     407},
23730         {"PCI_DMA_INT_LEV0"            ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     408},
23731         {"PCI_DMA_INT_LEV1"            ,                      0xACull,  CVMX_CSR_DB_TYPE_PCI,   32,     408},
23732         {"PCI_DMA_TIME0"               ,                      0xB0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     409},
23733         {"PCI_DMA_TIME1"               ,                      0xB4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     409},
23734         {"PCI_INSTR_COUNT0"            ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCI,   32,     410},
23735         {"PCI_INSTR_COUNT1"            ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     410},
23736         {"PCI_INSTR_COUNT2"            ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCI,   32,     410},
23737         {"PCI_INSTR_COUNT3"            ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     410},
23738         {"PCI_INT_ENB"                 ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCI,   64,     411},
23739         {"PCI_INT_ENB2"                ,           0x11F00000011A0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     412},
23740         {"PCI_INT_SUM"                 ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCI,   64,     413},
23741         {"PCI_INT_SUM2"                ,           0x11F0000001198ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     414},
23742         {"PCI_MSI_RCV"                 ,                      0xF0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     415},
23743         {"PCI_PKT_CREDITS0"            ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCI,   32,     416},
23744         {"PCI_PKT_CREDITS1"            ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCI,   32,     416},
23745         {"PCI_PKT_CREDITS2"            ,                      0x64ull,  CVMX_CSR_DB_TYPE_PCI,   32,     416},
23746         {"PCI_PKT_CREDITS3"            ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCI,   32,     416},
23747         {"PCI_PKTS_SENT0"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCI,   32,     417},
23748         {"PCI_PKTS_SENT1"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCI,   32,     417},
23749         {"PCI_PKTS_SENT2"              ,                      0x60ull,  CVMX_CSR_DB_TYPE_PCI,   32,     417},
23750         {"PCI_PKTS_SENT3"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCI,   32,     417},
23751         {"PCI_PKTS_SENT_INT_LEV0"      ,                      0x48ull,  CVMX_CSR_DB_TYPE_PCI,   32,     418},
23752         {"PCI_PKTS_SENT_INT_LEV1"      ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCI,   32,     418},
23753         {"PCI_PKTS_SENT_INT_LEV2"      ,                      0x68ull,  CVMX_CSR_DB_TYPE_PCI,   32,     418},
23754         {"PCI_PKTS_SENT_INT_LEV3"      ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCI,   32,     418},
23755         {"PCI_PKTS_SENT_TIME0"         ,                      0x4Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     419},
23756         {"PCI_PKTS_SENT_TIME1"         ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     419},
23757         {"PCI_PKTS_SENT_TIME2"         ,                      0x6Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     419},
23758         {"PCI_PKTS_SENT_TIME3"         ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     419},
23759         {"PCI_READ_CMD_6"              ,           0x11F0000001180ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     420},
23760         {"PCI_READ_CMD_C"              ,           0x11F0000001184ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     421},
23761         {"PCI_READ_CMD_E"              ,           0x11F0000001188ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     422},
23762         {"PCI_READ_TIMEOUT"            ,           0x11F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     423},
23763         {"PCI_SCM_REG"                 ,           0x11F00000011A8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     424},
23764         {"PCI_TSR_REG"                 ,           0x11F00000011B0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     425},
23765         {"PCI_WIN_RD_ADDR"             ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCI,   64,     426},
23766         {"PCI_WIN_RD_DATA"             ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCI,   64,     427},
23767         {"PCI_WIN_WR_ADDR"             ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCI,   64,     428},
23768         {"PCI_WIN_WR_DATA"             ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCI,   64,     429},
23769         {"PCI_WIN_WR_MASK"             ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCI,   64,     430},
23770         {"PIP_BCK_PRS"                 ,           0x11800A0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
23771         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
23772         {"PIP_CRC_CTL0"                ,           0x11800A0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
23773         {"PIP_CRC_CTL1"                ,           0x11800A0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
23774         {"PIP_CRC_IV0"                 ,           0x11800A0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
23775         {"PIP_CRC_IV1"                 ,           0x11800A0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
23776         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
23777         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
23778         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
23779         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
23780         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
23781         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
23782         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
23783         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
23784         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
23785         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23786         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23787         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23788         {"PIP_PRT_CFG3"                ,           0x11800A0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23789         {"PIP_PRT_CFG4"                ,           0x11800A0000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23790         {"PIP_PRT_CFG5"                ,           0x11800A0000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23791         {"PIP_PRT_CFG6"                ,           0x11800A0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23792         {"PIP_PRT_CFG7"                ,           0x11800A0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23793         {"PIP_PRT_CFG8"                ,           0x11800A0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23794         {"PIP_PRT_CFG9"                ,           0x11800A0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23795         {"PIP_PRT_CFG10"               ,           0x11800A0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23796         {"PIP_PRT_CFG11"               ,           0x11800A0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23797         {"PIP_PRT_CFG12"               ,           0x11800A0000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23798         {"PIP_PRT_CFG13"               ,           0x11800A0000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23799         {"PIP_PRT_CFG14"               ,           0x11800A0000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23800         {"PIP_PRT_CFG15"               ,           0x11800A0000278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23801         {"PIP_PRT_CFG16"               ,           0x11800A0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23802         {"PIP_PRT_CFG17"               ,           0x11800A0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23803         {"PIP_PRT_CFG18"               ,           0x11800A0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23804         {"PIP_PRT_CFG19"               ,           0x11800A0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23805         {"PIP_PRT_CFG20"               ,           0x11800A00002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23806         {"PIP_PRT_CFG21"               ,           0x11800A00002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23807         {"PIP_PRT_CFG22"               ,           0x11800A00002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23808         {"PIP_PRT_CFG23"               ,           0x11800A00002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23809         {"PIP_PRT_CFG24"               ,           0x11800A00002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23810         {"PIP_PRT_CFG25"               ,           0x11800A00002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23811         {"PIP_PRT_CFG26"               ,           0x11800A00002D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23812         {"PIP_PRT_CFG27"               ,           0x11800A00002D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23813         {"PIP_PRT_CFG28"               ,           0x11800A00002E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23814         {"PIP_PRT_CFG29"               ,           0x11800A00002E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23815         {"PIP_PRT_CFG30"               ,           0x11800A00002F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23816         {"PIP_PRT_CFG31"               ,           0x11800A00002F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23817         {"PIP_PRT_CFG32"               ,           0x11800A0000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23818         {"PIP_PRT_CFG33"               ,           0x11800A0000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23819         {"PIP_PRT_CFG34"               ,           0x11800A0000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23820         {"PIP_PRT_CFG35"               ,           0x11800A0000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
23821         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23822         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23823         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23824         {"PIP_PRT_TAG3"                ,           0x11800A0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23825         {"PIP_PRT_TAG4"                ,           0x11800A0000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23826         {"PIP_PRT_TAG5"                ,           0x11800A0000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23827         {"PIP_PRT_TAG6"                ,           0x11800A0000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23828         {"PIP_PRT_TAG7"                ,           0x11800A0000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23829         {"PIP_PRT_TAG8"                ,           0x11800A0000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23830         {"PIP_PRT_TAG9"                ,           0x11800A0000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23831         {"PIP_PRT_TAG10"               ,           0x11800A0000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23832         {"PIP_PRT_TAG11"               ,           0x11800A0000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23833         {"PIP_PRT_TAG12"               ,           0x11800A0000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23834         {"PIP_PRT_TAG13"               ,           0x11800A0000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23835         {"PIP_PRT_TAG14"               ,           0x11800A0000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23836         {"PIP_PRT_TAG15"               ,           0x11800A0000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23837         {"PIP_PRT_TAG16"               ,           0x11800A0000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23838         {"PIP_PRT_TAG17"               ,           0x11800A0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23839         {"PIP_PRT_TAG18"               ,           0x11800A0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23840         {"PIP_PRT_TAG19"               ,           0x11800A0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23841         {"PIP_PRT_TAG20"               ,           0x11800A00004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23842         {"PIP_PRT_TAG21"               ,           0x11800A00004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23843         {"PIP_PRT_TAG22"               ,           0x11800A00004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23844         {"PIP_PRT_TAG23"               ,           0x11800A00004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23845         {"PIP_PRT_TAG24"               ,           0x11800A00004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23846         {"PIP_PRT_TAG25"               ,           0x11800A00004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23847         {"PIP_PRT_TAG26"               ,           0x11800A00004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23848         {"PIP_PRT_TAG27"               ,           0x11800A00004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23849         {"PIP_PRT_TAG28"               ,           0x11800A00004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23850         {"PIP_PRT_TAG29"               ,           0x11800A00004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23851         {"PIP_PRT_TAG30"               ,           0x11800A00004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23852         {"PIP_PRT_TAG31"               ,           0x11800A00004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23853         {"PIP_PRT_TAG32"               ,           0x11800A0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23854         {"PIP_PRT_TAG33"               ,           0x11800A0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23855         {"PIP_PRT_TAG34"               ,           0x11800A0000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23856         {"PIP_PRT_TAG35"               ,           0x11800A0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
23857         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23858         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23859         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23860         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23861         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23862         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23863         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23864         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23865         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23866         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23867         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23868         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23869         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23870         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23871         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23872         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23873         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23874         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23875         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23876         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23877         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23878         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23879         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23880         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23881         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23882         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23883         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23884         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23885         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23886         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23887         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23888         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23889         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23890         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23891         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23892         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23893         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23894         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23895         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23896         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23897         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23898         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23899         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23900         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23901         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23902         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23903         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23904         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23905         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23906         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23907         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23908         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23909         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23910         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23911         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23912         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23913         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23914         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23915         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23916         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23917         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23918         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23919         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23920         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
23921         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
23922         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
23923         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
23924         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
23925         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
23926         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
23927         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
23928         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
23929         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
23930         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
23931         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
23932         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
23933         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
23934         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     447},
23935         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23936         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23937         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23938         {"PIP_STAT0_PRT3"              ,           0x11800A00008F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23939         {"PIP_STAT0_PRT4"              ,           0x11800A0000940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23940         {"PIP_STAT0_PRT5"              ,           0x11800A0000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23941         {"PIP_STAT0_PRT6"              ,           0x11800A00009E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23942         {"PIP_STAT0_PRT7"              ,           0x11800A0000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23943         {"PIP_STAT0_PRT8"              ,           0x11800A0000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23944         {"PIP_STAT0_PRT9"              ,           0x11800A0000AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23945         {"PIP_STAT0_PRT10"             ,           0x11800A0000B20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23946         {"PIP_STAT0_PRT11"             ,           0x11800A0000B70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23947         {"PIP_STAT0_PRT12"             ,           0x11800A0000BC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23948         {"PIP_STAT0_PRT13"             ,           0x11800A0000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23949         {"PIP_STAT0_PRT14"             ,           0x11800A0000C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23950         {"PIP_STAT0_PRT15"             ,           0x11800A0000CB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23951         {"PIP_STAT0_PRT16"             ,           0x11800A0000D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23952         {"PIP_STAT0_PRT17"             ,           0x11800A0000D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23953         {"PIP_STAT0_PRT18"             ,           0x11800A0000DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23954         {"PIP_STAT0_PRT19"             ,           0x11800A0000DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23955         {"PIP_STAT0_PRT20"             ,           0x11800A0000E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23956         {"PIP_STAT0_PRT21"             ,           0x11800A0000E90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23957         {"PIP_STAT0_PRT22"             ,           0x11800A0000EE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23958         {"PIP_STAT0_PRT23"             ,           0x11800A0000F30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23959         {"PIP_STAT0_PRT24"             ,           0x11800A0000F80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23960         {"PIP_STAT0_PRT25"             ,           0x11800A0000FD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23961         {"PIP_STAT0_PRT26"             ,           0x11800A0001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23962         {"PIP_STAT0_PRT27"             ,           0x11800A0001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23963         {"PIP_STAT0_PRT28"             ,           0x11800A00010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23964         {"PIP_STAT0_PRT29"             ,           0x11800A0001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23965         {"PIP_STAT0_PRT30"             ,           0x11800A0001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23966         {"PIP_STAT0_PRT31"             ,           0x11800A00011B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23967         {"PIP_STAT0_PRT32"             ,           0x11800A0001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23968         {"PIP_STAT0_PRT33"             ,           0x11800A0001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23969         {"PIP_STAT0_PRT34"             ,           0x11800A00012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23970         {"PIP_STAT0_PRT35"             ,           0x11800A00012F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
23971         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23972         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23973         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23974         {"PIP_STAT1_PRT3"              ,           0x11800A00008F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23975         {"PIP_STAT1_PRT4"              ,           0x11800A0000948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23976         {"PIP_STAT1_PRT5"              ,           0x11800A0000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23977         {"PIP_STAT1_PRT6"              ,           0x11800A00009E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23978         {"PIP_STAT1_PRT7"              ,           0x11800A0000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23979         {"PIP_STAT1_PRT8"              ,           0x11800A0000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23980         {"PIP_STAT1_PRT9"              ,           0x11800A0000AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23981         {"PIP_STAT1_PRT10"             ,           0x11800A0000B28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23982         {"PIP_STAT1_PRT11"             ,           0x11800A0000B78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23983         {"PIP_STAT1_PRT12"             ,           0x11800A0000BC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23984         {"PIP_STAT1_PRT13"             ,           0x11800A0000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23985         {"PIP_STAT1_PRT14"             ,           0x11800A0000C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23986         {"PIP_STAT1_PRT15"             ,           0x11800A0000CB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23987         {"PIP_STAT1_PRT16"             ,           0x11800A0000D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23988         {"PIP_STAT1_PRT17"             ,           0x11800A0000D58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23989         {"PIP_STAT1_PRT18"             ,           0x11800A0000DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23990         {"PIP_STAT1_PRT19"             ,           0x11800A0000DF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23991         {"PIP_STAT1_PRT20"             ,           0x11800A0000E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23992         {"PIP_STAT1_PRT21"             ,           0x11800A0000E98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23993         {"PIP_STAT1_PRT22"             ,           0x11800A0000EE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23994         {"PIP_STAT1_PRT23"             ,           0x11800A0000F38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23995         {"PIP_STAT1_PRT24"             ,           0x11800A0000F88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23996         {"PIP_STAT1_PRT25"             ,           0x11800A0000FD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23997         {"PIP_STAT1_PRT26"             ,           0x11800A0001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23998         {"PIP_STAT1_PRT27"             ,           0x11800A0001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
23999         {"PIP_STAT1_PRT28"             ,           0x11800A00010C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
24000         {"PIP_STAT1_PRT29"             ,           0x11800A0001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
24001         {"PIP_STAT1_PRT30"             ,           0x11800A0001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
24002         {"PIP_STAT1_PRT31"             ,           0x11800A00011B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
24003         {"PIP_STAT1_PRT32"             ,           0x11800A0001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
24004         {"PIP_STAT1_PRT33"             ,           0x11800A0001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
24005         {"PIP_STAT1_PRT34"             ,           0x11800A00012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
24006         {"PIP_STAT1_PRT35"             ,           0x11800A00012F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
24007         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24008         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24009         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24010         {"PIP_STAT2_PRT3"              ,           0x11800A0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24011         {"PIP_STAT2_PRT4"              ,           0x11800A0000950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24012         {"PIP_STAT2_PRT5"              ,           0x11800A00009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24013         {"PIP_STAT2_PRT6"              ,           0x11800A00009F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24014         {"PIP_STAT2_PRT7"              ,           0x11800A0000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24015         {"PIP_STAT2_PRT8"              ,           0x11800A0000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24016         {"PIP_STAT2_PRT9"              ,           0x11800A0000AE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24017         {"PIP_STAT2_PRT10"             ,           0x11800A0000B30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24018         {"PIP_STAT2_PRT11"             ,           0x11800A0000B80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24019         {"PIP_STAT2_PRT12"             ,           0x11800A0000BD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24020         {"PIP_STAT2_PRT13"             ,           0x11800A0000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24021         {"PIP_STAT2_PRT14"             ,           0x11800A0000C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24022         {"PIP_STAT2_PRT15"             ,           0x11800A0000CC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24023         {"PIP_STAT2_PRT16"             ,           0x11800A0000D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24024         {"PIP_STAT2_PRT17"             ,           0x11800A0000D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24025         {"PIP_STAT2_PRT18"             ,           0x11800A0000DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24026         {"PIP_STAT2_PRT19"             ,           0x11800A0000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24027         {"PIP_STAT2_PRT20"             ,           0x11800A0000E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24028         {"PIP_STAT2_PRT21"             ,           0x11800A0000EA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24029         {"PIP_STAT2_PRT22"             ,           0x11800A0000EF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24030         {"PIP_STAT2_PRT23"             ,           0x11800A0000F40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24031         {"PIP_STAT2_PRT24"             ,           0x11800A0000F90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24032         {"PIP_STAT2_PRT25"             ,           0x11800A0000FE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24033         {"PIP_STAT2_PRT26"             ,           0x11800A0001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24034         {"PIP_STAT2_PRT27"             ,           0x11800A0001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24035         {"PIP_STAT2_PRT28"             ,           0x11800A00010D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24036         {"PIP_STAT2_PRT29"             ,           0x11800A0001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24037         {"PIP_STAT2_PRT30"             ,           0x11800A0001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24038         {"PIP_STAT2_PRT31"             ,           0x11800A00011C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24039         {"PIP_STAT2_PRT32"             ,           0x11800A0001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24040         {"PIP_STAT2_PRT33"             ,           0x11800A0001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24041         {"PIP_STAT2_PRT34"             ,           0x11800A00012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24042         {"PIP_STAT2_PRT35"             ,           0x11800A0001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
24043         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24044         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24045         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24046         {"PIP_STAT3_PRT3"              ,           0x11800A0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24047         {"PIP_STAT3_PRT4"              ,           0x11800A0000958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24048         {"PIP_STAT3_PRT5"              ,           0x11800A00009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24049         {"PIP_STAT3_PRT6"              ,           0x11800A00009F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24050         {"PIP_STAT3_PRT7"              ,           0x11800A0000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24051         {"PIP_STAT3_PRT8"              ,           0x11800A0000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24052         {"PIP_STAT3_PRT9"              ,           0x11800A0000AE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24053         {"PIP_STAT3_PRT10"             ,           0x11800A0000B38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24054         {"PIP_STAT3_PRT11"             ,           0x11800A0000B88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24055         {"PIP_STAT3_PRT12"             ,           0x11800A0000BD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24056         {"PIP_STAT3_PRT13"             ,           0x11800A0000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24057         {"PIP_STAT3_PRT14"             ,           0x11800A0000C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24058         {"PIP_STAT3_PRT15"             ,           0x11800A0000CC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24059         {"PIP_STAT3_PRT16"             ,           0x11800A0000D18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24060         {"PIP_STAT3_PRT17"             ,           0x11800A0000D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24061         {"PIP_STAT3_PRT18"             ,           0x11800A0000DB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24062         {"PIP_STAT3_PRT19"             ,           0x11800A0000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24063         {"PIP_STAT3_PRT20"             ,           0x11800A0000E58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24064         {"PIP_STAT3_PRT21"             ,           0x11800A0000EA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24065         {"PIP_STAT3_PRT22"             ,           0x11800A0000EF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24066         {"PIP_STAT3_PRT23"             ,           0x11800A0000F48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24067         {"PIP_STAT3_PRT24"             ,           0x11800A0000F98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24068         {"PIP_STAT3_PRT25"             ,           0x11800A0000FE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24069         {"PIP_STAT3_PRT26"             ,           0x11800A0001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24070         {"PIP_STAT3_PRT27"             ,           0x11800A0001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24071         {"PIP_STAT3_PRT28"             ,           0x11800A00010D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24072         {"PIP_STAT3_PRT29"             ,           0x11800A0001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24073         {"PIP_STAT3_PRT30"             ,           0x11800A0001178ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24074         {"PIP_STAT3_PRT31"             ,           0x11800A00011C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24075         {"PIP_STAT3_PRT32"             ,           0x11800A0001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24076         {"PIP_STAT3_PRT33"             ,           0x11800A0001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24077         {"PIP_STAT3_PRT34"             ,           0x11800A00012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24078         {"PIP_STAT3_PRT35"             ,           0x11800A0001308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
24079         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24080         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24081         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24082         {"PIP_STAT4_PRT3"              ,           0x11800A0000910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24083         {"PIP_STAT4_PRT4"              ,           0x11800A0000960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24084         {"PIP_STAT4_PRT5"              ,           0x11800A00009B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24085         {"PIP_STAT4_PRT6"              ,           0x11800A0000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24086         {"PIP_STAT4_PRT7"              ,           0x11800A0000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24087         {"PIP_STAT4_PRT8"              ,           0x11800A0000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24088         {"PIP_STAT4_PRT9"              ,           0x11800A0000AF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24089         {"PIP_STAT4_PRT10"             ,           0x11800A0000B40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24090         {"PIP_STAT4_PRT11"             ,           0x11800A0000B90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24091         {"PIP_STAT4_PRT12"             ,           0x11800A0000BE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24092         {"PIP_STAT4_PRT13"             ,           0x11800A0000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24093         {"PIP_STAT4_PRT14"             ,           0x11800A0000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24094         {"PIP_STAT4_PRT15"             ,           0x11800A0000CD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24095         {"PIP_STAT4_PRT16"             ,           0x11800A0000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24096         {"PIP_STAT4_PRT17"             ,           0x11800A0000D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24097         {"PIP_STAT4_PRT18"             ,           0x11800A0000DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24098         {"PIP_STAT4_PRT19"             ,           0x11800A0000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24099         {"PIP_STAT4_PRT20"             ,           0x11800A0000E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24100         {"PIP_STAT4_PRT21"             ,           0x11800A0000EB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24101         {"PIP_STAT4_PRT22"             ,           0x11800A0000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24102         {"PIP_STAT4_PRT23"             ,           0x11800A0000F50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24103         {"PIP_STAT4_PRT24"             ,           0x11800A0000FA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24104         {"PIP_STAT4_PRT25"             ,           0x11800A0000FF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24105         {"PIP_STAT4_PRT26"             ,           0x11800A0001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24106         {"PIP_STAT4_PRT27"             ,           0x11800A0001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24107         {"PIP_STAT4_PRT28"             ,           0x11800A00010E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24108         {"PIP_STAT4_PRT29"             ,           0x11800A0001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24109         {"PIP_STAT4_PRT30"             ,           0x11800A0001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24110         {"PIP_STAT4_PRT31"             ,           0x11800A00011D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24111         {"PIP_STAT4_PRT32"             ,           0x11800A0001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24112         {"PIP_STAT4_PRT33"             ,           0x11800A0001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24113         {"PIP_STAT4_PRT34"             ,           0x11800A00012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24114         {"PIP_STAT4_PRT35"             ,           0x11800A0001310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
24115         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24116         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24117         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24118         {"PIP_STAT5_PRT3"              ,           0x11800A0000918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24119         {"PIP_STAT5_PRT4"              ,           0x11800A0000968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24120         {"PIP_STAT5_PRT5"              ,           0x11800A00009B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24121         {"PIP_STAT5_PRT6"              ,           0x11800A0000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24122         {"PIP_STAT5_PRT7"              ,           0x11800A0000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24123         {"PIP_STAT5_PRT8"              ,           0x11800A0000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24124         {"PIP_STAT5_PRT9"              ,           0x11800A0000AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24125         {"PIP_STAT5_PRT10"             ,           0x11800A0000B48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24126         {"PIP_STAT5_PRT11"             ,           0x11800A0000B98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24127         {"PIP_STAT5_PRT12"             ,           0x11800A0000BE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24128         {"PIP_STAT5_PRT13"             ,           0x11800A0000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24129         {"PIP_STAT5_PRT14"             ,           0x11800A0000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24130         {"PIP_STAT5_PRT15"             ,           0x11800A0000CD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24131         {"PIP_STAT5_PRT16"             ,           0x11800A0000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24132         {"PIP_STAT5_PRT17"             ,           0x11800A0000D78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24133         {"PIP_STAT5_PRT18"             ,           0x11800A0000DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24134         {"PIP_STAT5_PRT19"             ,           0x11800A0000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24135         {"PIP_STAT5_PRT20"             ,           0x11800A0000E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24136         {"PIP_STAT5_PRT21"             ,           0x11800A0000EB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24137         {"PIP_STAT5_PRT22"             ,           0x11800A0000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24138         {"PIP_STAT5_PRT23"             ,           0x11800A0000F58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24139         {"PIP_STAT5_PRT24"             ,           0x11800A0000FA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24140         {"PIP_STAT5_PRT25"             ,           0x11800A0000FF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24141         {"PIP_STAT5_PRT26"             ,           0x11800A0001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24142         {"PIP_STAT5_PRT27"             ,           0x11800A0001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24143         {"PIP_STAT5_PRT28"             ,           0x11800A00010E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24144         {"PIP_STAT5_PRT29"             ,           0x11800A0001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24145         {"PIP_STAT5_PRT30"             ,           0x11800A0001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24146         {"PIP_STAT5_PRT31"             ,           0x11800A00011D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24147         {"PIP_STAT5_PRT32"             ,           0x11800A0001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24148         {"PIP_STAT5_PRT33"             ,           0x11800A0001278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24149         {"PIP_STAT5_PRT34"             ,           0x11800A00012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24150         {"PIP_STAT5_PRT35"             ,           0x11800A0001318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
24151         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24152         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24153         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24154         {"PIP_STAT6_PRT3"              ,           0x11800A0000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24155         {"PIP_STAT6_PRT4"              ,           0x11800A0000970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24156         {"PIP_STAT6_PRT5"              ,           0x11800A00009C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24157         {"PIP_STAT6_PRT6"              ,           0x11800A0000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24158         {"PIP_STAT6_PRT7"              ,           0x11800A0000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24159         {"PIP_STAT6_PRT8"              ,           0x11800A0000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24160         {"PIP_STAT6_PRT9"              ,           0x11800A0000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24161         {"PIP_STAT6_PRT10"             ,           0x11800A0000B50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24162         {"PIP_STAT6_PRT11"             ,           0x11800A0000BA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24163         {"PIP_STAT6_PRT12"             ,           0x11800A0000BF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24164         {"PIP_STAT6_PRT13"             ,           0x11800A0000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24165         {"PIP_STAT6_PRT14"             ,           0x11800A0000C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24166         {"PIP_STAT6_PRT15"             ,           0x11800A0000CE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24167         {"PIP_STAT6_PRT16"             ,           0x11800A0000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24168         {"PIP_STAT6_PRT17"             ,           0x11800A0000D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24169         {"PIP_STAT6_PRT18"             ,           0x11800A0000DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24170         {"PIP_STAT6_PRT19"             ,           0x11800A0000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24171         {"PIP_STAT6_PRT20"             ,           0x11800A0000E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24172         {"PIP_STAT6_PRT21"             ,           0x11800A0000EC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24173         {"PIP_STAT6_PRT22"             ,           0x11800A0000F10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24174         {"PIP_STAT6_PRT23"             ,           0x11800A0000F60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24175         {"PIP_STAT6_PRT24"             ,           0x11800A0000FB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24176         {"PIP_STAT6_PRT25"             ,           0x11800A0001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24177         {"PIP_STAT6_PRT26"             ,           0x11800A0001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24178         {"PIP_STAT6_PRT27"             ,           0x11800A00010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24179         {"PIP_STAT6_PRT28"             ,           0x11800A00010F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24180         {"PIP_STAT6_PRT29"             ,           0x11800A0001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24181         {"PIP_STAT6_PRT30"             ,           0x11800A0001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24182         {"PIP_STAT6_PRT31"             ,           0x11800A00011E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24183         {"PIP_STAT6_PRT32"             ,           0x11800A0001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24184         {"PIP_STAT6_PRT33"             ,           0x11800A0001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24185         {"PIP_STAT6_PRT34"             ,           0x11800A00012D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24186         {"PIP_STAT6_PRT35"             ,           0x11800A0001320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
24187         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24188         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24189         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24190         {"PIP_STAT7_PRT3"              ,           0x11800A0000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24191         {"PIP_STAT7_PRT4"              ,           0x11800A0000978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24192         {"PIP_STAT7_PRT5"              ,           0x11800A00009C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24193         {"PIP_STAT7_PRT6"              ,           0x11800A0000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24194         {"PIP_STAT7_PRT7"              ,           0x11800A0000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24195         {"PIP_STAT7_PRT8"              ,           0x11800A0000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24196         {"PIP_STAT7_PRT9"              ,           0x11800A0000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24197         {"PIP_STAT7_PRT10"             ,           0x11800A0000B58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24198         {"PIP_STAT7_PRT11"             ,           0x11800A0000BA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24199         {"PIP_STAT7_PRT12"             ,           0x11800A0000BF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24200         {"PIP_STAT7_PRT13"             ,           0x11800A0000C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24201         {"PIP_STAT7_PRT14"             ,           0x11800A0000C98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24202         {"PIP_STAT7_PRT15"             ,           0x11800A0000CE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24203         {"PIP_STAT7_PRT16"             ,           0x11800A0000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24204         {"PIP_STAT7_PRT17"             ,           0x11800A0000D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24205         {"PIP_STAT7_PRT18"             ,           0x11800A0000DD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24206         {"PIP_STAT7_PRT19"             ,           0x11800A0000E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24207         {"PIP_STAT7_PRT20"             ,           0x11800A0000E78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24208         {"PIP_STAT7_PRT21"             ,           0x11800A0000EC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24209         {"PIP_STAT7_PRT22"             ,           0x11800A0000F18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24210         {"PIP_STAT7_PRT23"             ,           0x11800A0000F68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24211         {"PIP_STAT7_PRT24"             ,           0x11800A0000FB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24212         {"PIP_STAT7_PRT25"             ,           0x11800A0001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24213         {"PIP_STAT7_PRT26"             ,           0x11800A0001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24214         {"PIP_STAT7_PRT27"             ,           0x11800A00010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24215         {"PIP_STAT7_PRT28"             ,           0x11800A00010F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24216         {"PIP_STAT7_PRT29"             ,           0x11800A0001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24217         {"PIP_STAT7_PRT30"             ,           0x11800A0001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24218         {"PIP_STAT7_PRT31"             ,           0x11800A00011E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24219         {"PIP_STAT7_PRT32"             ,           0x11800A0001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24220         {"PIP_STAT7_PRT33"             ,           0x11800A0001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24221         {"PIP_STAT7_PRT34"             ,           0x11800A00012D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24222         {"PIP_STAT7_PRT35"             ,           0x11800A0001328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
24223         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24224         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24225         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24226         {"PIP_STAT8_PRT3"              ,           0x11800A0000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24227         {"PIP_STAT8_PRT4"              ,           0x11800A0000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24228         {"PIP_STAT8_PRT5"              ,           0x11800A00009D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24229         {"PIP_STAT8_PRT6"              ,           0x11800A0000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24230         {"PIP_STAT8_PRT7"              ,           0x11800A0000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24231         {"PIP_STAT8_PRT8"              ,           0x11800A0000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24232         {"PIP_STAT8_PRT9"              ,           0x11800A0000B10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24233         {"PIP_STAT8_PRT10"             ,           0x11800A0000B60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24234         {"PIP_STAT8_PRT11"             ,           0x11800A0000BB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24235         {"PIP_STAT8_PRT12"             ,           0x11800A0000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24236         {"PIP_STAT8_PRT13"             ,           0x11800A0000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24237         {"PIP_STAT8_PRT14"             ,           0x11800A0000CA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24238         {"PIP_STAT8_PRT15"             ,           0x11800A0000CF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24239         {"PIP_STAT8_PRT16"             ,           0x11800A0000D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24240         {"PIP_STAT8_PRT17"             ,           0x11800A0000D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24241         {"PIP_STAT8_PRT18"             ,           0x11800A0000DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24242         {"PIP_STAT8_PRT19"             ,           0x11800A0000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24243         {"PIP_STAT8_PRT20"             ,           0x11800A0000E80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24244         {"PIP_STAT8_PRT21"             ,           0x11800A0000ED0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24245         {"PIP_STAT8_PRT22"             ,           0x11800A0000F20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24246         {"PIP_STAT8_PRT23"             ,           0x11800A0000F70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24247         {"PIP_STAT8_PRT24"             ,           0x11800A0000FC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24248         {"PIP_STAT8_PRT25"             ,           0x11800A0001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24249         {"PIP_STAT8_PRT26"             ,           0x11800A0001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24250         {"PIP_STAT8_PRT27"             ,           0x11800A00010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24251         {"PIP_STAT8_PRT28"             ,           0x11800A0001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24252         {"PIP_STAT8_PRT29"             ,           0x11800A0001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24253         {"PIP_STAT8_PRT30"             ,           0x11800A00011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24254         {"PIP_STAT8_PRT31"             ,           0x11800A00011F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24255         {"PIP_STAT8_PRT32"             ,           0x11800A0001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24256         {"PIP_STAT8_PRT33"             ,           0x11800A0001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24257         {"PIP_STAT8_PRT34"             ,           0x11800A00012E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24258         {"PIP_STAT8_PRT35"             ,           0x11800A0001330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
24259         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24260         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24261         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24262         {"PIP_STAT9_PRT3"              ,           0x11800A0000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24263         {"PIP_STAT9_PRT4"              ,           0x11800A0000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24264         {"PIP_STAT9_PRT5"              ,           0x11800A00009D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24265         {"PIP_STAT9_PRT6"              ,           0x11800A0000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24266         {"PIP_STAT9_PRT7"              ,           0x11800A0000A78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24267         {"PIP_STAT9_PRT8"              ,           0x11800A0000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24268         {"PIP_STAT9_PRT9"              ,           0x11800A0000B18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24269         {"PIP_STAT9_PRT10"             ,           0x11800A0000B68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24270         {"PIP_STAT9_PRT11"             ,           0x11800A0000BB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24271         {"PIP_STAT9_PRT12"             ,           0x11800A0000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24272         {"PIP_STAT9_PRT13"             ,           0x11800A0000C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24273         {"PIP_STAT9_PRT14"             ,           0x11800A0000CA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24274         {"PIP_STAT9_PRT15"             ,           0x11800A0000CF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24275         {"PIP_STAT9_PRT16"             ,           0x11800A0000D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24276         {"PIP_STAT9_PRT17"             ,           0x11800A0000D98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24277         {"PIP_STAT9_PRT18"             ,           0x11800A0000DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24278         {"PIP_STAT9_PRT19"             ,           0x11800A0000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24279         {"PIP_STAT9_PRT20"             ,           0x11800A0000E88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24280         {"PIP_STAT9_PRT21"             ,           0x11800A0000ED8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24281         {"PIP_STAT9_PRT22"             ,           0x11800A0000F28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24282         {"PIP_STAT9_PRT23"             ,           0x11800A0000F78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24283         {"PIP_STAT9_PRT24"             ,           0x11800A0000FC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24284         {"PIP_STAT9_PRT25"             ,           0x11800A0001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24285         {"PIP_STAT9_PRT26"             ,           0x11800A0001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24286         {"PIP_STAT9_PRT27"             ,           0x11800A00010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24287         {"PIP_STAT9_PRT28"             ,           0x11800A0001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24288         {"PIP_STAT9_PRT29"             ,           0x11800A0001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24289         {"PIP_STAT9_PRT30"             ,           0x11800A00011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24290         {"PIP_STAT9_PRT31"             ,           0x11800A00011F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24291         {"PIP_STAT9_PRT32"             ,           0x11800A0001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24292         {"PIP_STAT9_PRT33"             ,           0x11800A0001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24293         {"PIP_STAT9_PRT34"             ,           0x11800A00012E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24294         {"PIP_STAT9_PRT35"             ,           0x11800A0001338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
24295         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
24296         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24297         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24298         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24299         {"PIP_STAT_INB_ERRS3"          ,           0x11800A0001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24300         {"PIP_STAT_INB_ERRS4"          ,           0x11800A0001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24301         {"PIP_STAT_INB_ERRS5"          ,           0x11800A0001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24302         {"PIP_STAT_INB_ERRS6"          ,           0x11800A0001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24303         {"PIP_STAT_INB_ERRS7"          ,           0x11800A0001AF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24304         {"PIP_STAT_INB_ERRS8"          ,           0x11800A0001B10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24305         {"PIP_STAT_INB_ERRS9"          ,           0x11800A0001B30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24306         {"PIP_STAT_INB_ERRS10"         ,           0x11800A0001B50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24307         {"PIP_STAT_INB_ERRS11"         ,           0x11800A0001B70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24308         {"PIP_STAT_INB_ERRS12"         ,           0x11800A0001B90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24309         {"PIP_STAT_INB_ERRS13"         ,           0x11800A0001BB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24310         {"PIP_STAT_INB_ERRS14"         ,           0x11800A0001BD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24311         {"PIP_STAT_INB_ERRS15"         ,           0x11800A0001BF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24312         {"PIP_STAT_INB_ERRS16"         ,           0x11800A0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24313         {"PIP_STAT_INB_ERRS17"         ,           0x11800A0001C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24314         {"PIP_STAT_INB_ERRS18"         ,           0x11800A0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24315         {"PIP_STAT_INB_ERRS19"         ,           0x11800A0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24316         {"PIP_STAT_INB_ERRS20"         ,           0x11800A0001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24317         {"PIP_STAT_INB_ERRS21"         ,           0x11800A0001CB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24318         {"PIP_STAT_INB_ERRS22"         ,           0x11800A0001CD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24319         {"PIP_STAT_INB_ERRS23"         ,           0x11800A0001CF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24320         {"PIP_STAT_INB_ERRS24"         ,           0x11800A0001D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24321         {"PIP_STAT_INB_ERRS25"         ,           0x11800A0001D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24322         {"PIP_STAT_INB_ERRS26"         ,           0x11800A0001D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24323         {"PIP_STAT_INB_ERRS27"         ,           0x11800A0001D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24324         {"PIP_STAT_INB_ERRS28"         ,           0x11800A0001D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24325         {"PIP_STAT_INB_ERRS29"         ,           0x11800A0001DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24326         {"PIP_STAT_INB_ERRS30"         ,           0x11800A0001DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24327         {"PIP_STAT_INB_ERRS31"         ,           0x11800A0001DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24328         {"PIP_STAT_INB_ERRS32"         ,           0x11800A0001E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24329         {"PIP_STAT_INB_ERRS33"         ,           0x11800A0001E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24330         {"PIP_STAT_INB_ERRS34"         ,           0x11800A0001E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24331         {"PIP_STAT_INB_ERRS35"         ,           0x11800A0001E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
24332         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24333         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24334         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24335         {"PIP_STAT_INB_OCTS3"          ,           0x11800A0001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24336         {"PIP_STAT_INB_OCTS4"          ,           0x11800A0001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24337         {"PIP_STAT_INB_OCTS5"          ,           0x11800A0001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24338         {"PIP_STAT_INB_OCTS6"          ,           0x11800A0001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24339         {"PIP_STAT_INB_OCTS7"          ,           0x11800A0001AE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24340         {"PIP_STAT_INB_OCTS8"          ,           0x11800A0001B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24341         {"PIP_STAT_INB_OCTS9"          ,           0x11800A0001B28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24342         {"PIP_STAT_INB_OCTS10"         ,           0x11800A0001B48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24343         {"PIP_STAT_INB_OCTS11"         ,           0x11800A0001B68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24344         {"PIP_STAT_INB_OCTS12"         ,           0x11800A0001B88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24345         {"PIP_STAT_INB_OCTS13"         ,           0x11800A0001BA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24346         {"PIP_STAT_INB_OCTS14"         ,           0x11800A0001BC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24347         {"PIP_STAT_INB_OCTS15"         ,           0x11800A0001BE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24348         {"PIP_STAT_INB_OCTS16"         ,           0x11800A0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24349         {"PIP_STAT_INB_OCTS17"         ,           0x11800A0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24350         {"PIP_STAT_INB_OCTS18"         ,           0x11800A0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24351         {"PIP_STAT_INB_OCTS19"         ,           0x11800A0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24352         {"PIP_STAT_INB_OCTS20"         ,           0x11800A0001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24353         {"PIP_STAT_INB_OCTS21"         ,           0x11800A0001CA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24354         {"PIP_STAT_INB_OCTS22"         ,           0x11800A0001CC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24355         {"PIP_STAT_INB_OCTS23"         ,           0x11800A0001CE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24356         {"PIP_STAT_INB_OCTS24"         ,           0x11800A0001D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24357         {"PIP_STAT_INB_OCTS25"         ,           0x11800A0001D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24358         {"PIP_STAT_INB_OCTS26"         ,           0x11800A0001D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24359         {"PIP_STAT_INB_OCTS27"         ,           0x11800A0001D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24360         {"PIP_STAT_INB_OCTS28"         ,           0x11800A0001D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24361         {"PIP_STAT_INB_OCTS29"         ,           0x11800A0001DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24362         {"PIP_STAT_INB_OCTS30"         ,           0x11800A0001DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24363         {"PIP_STAT_INB_OCTS31"         ,           0x11800A0001DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24364         {"PIP_STAT_INB_OCTS32"         ,           0x11800A0001E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24365         {"PIP_STAT_INB_OCTS33"         ,           0x11800A0001E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24366         {"PIP_STAT_INB_OCTS34"         ,           0x11800A0001E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24367         {"PIP_STAT_INB_OCTS35"         ,           0x11800A0001E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
24368         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24369         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24370         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24371         {"PIP_STAT_INB_PKTS3"          ,           0x11800A0001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24372         {"PIP_STAT_INB_PKTS4"          ,           0x11800A0001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24373         {"PIP_STAT_INB_PKTS5"          ,           0x11800A0001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24374         {"PIP_STAT_INB_PKTS6"          ,           0x11800A0001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24375         {"PIP_STAT_INB_PKTS7"          ,           0x11800A0001AE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24376         {"PIP_STAT_INB_PKTS8"          ,           0x11800A0001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24377         {"PIP_STAT_INB_PKTS9"          ,           0x11800A0001B20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24378         {"PIP_STAT_INB_PKTS10"         ,           0x11800A0001B40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24379         {"PIP_STAT_INB_PKTS11"         ,           0x11800A0001B60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24380         {"PIP_STAT_INB_PKTS12"         ,           0x11800A0001B80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24381         {"PIP_STAT_INB_PKTS13"         ,           0x11800A0001BA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24382         {"PIP_STAT_INB_PKTS14"         ,           0x11800A0001BC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24383         {"PIP_STAT_INB_PKTS15"         ,           0x11800A0001BE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24384         {"PIP_STAT_INB_PKTS16"         ,           0x11800A0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24385         {"PIP_STAT_INB_PKTS17"         ,           0x11800A0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24386         {"PIP_STAT_INB_PKTS18"         ,           0x11800A0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24387         {"PIP_STAT_INB_PKTS19"         ,           0x11800A0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24388         {"PIP_STAT_INB_PKTS20"         ,           0x11800A0001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24389         {"PIP_STAT_INB_PKTS21"         ,           0x11800A0001CA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24390         {"PIP_STAT_INB_PKTS22"         ,           0x11800A0001CC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24391         {"PIP_STAT_INB_PKTS23"         ,           0x11800A0001CE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24392         {"PIP_STAT_INB_PKTS24"         ,           0x11800A0001D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24393         {"PIP_STAT_INB_PKTS25"         ,           0x11800A0001D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24394         {"PIP_STAT_INB_PKTS26"         ,           0x11800A0001D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24395         {"PIP_STAT_INB_PKTS27"         ,           0x11800A0001D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24396         {"PIP_STAT_INB_PKTS28"         ,           0x11800A0001D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24397         {"PIP_STAT_INB_PKTS29"         ,           0x11800A0001DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24398         {"PIP_STAT_INB_PKTS30"         ,           0x11800A0001DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24399         {"PIP_STAT_INB_PKTS31"         ,           0x11800A0001DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24400         {"PIP_STAT_INB_PKTS32"         ,           0x11800A0001E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24401         {"PIP_STAT_INB_PKTS33"         ,           0x11800A0001E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24402         {"PIP_STAT_INB_PKTS34"         ,           0x11800A0001E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24403         {"PIP_STAT_INB_PKTS35"         ,           0x11800A0001E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
24404         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24405         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24406         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24407         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24408         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24409         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24410         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24411         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24412         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24413         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24414         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24415         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24416         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24417         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24418         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24419         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24420         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24421         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24422         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24423         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24424         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24425         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24426         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24427         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24428         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24429         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24430         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24431         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24432         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24433         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24434         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24435         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24436         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24437         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24438         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24439         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24440         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24441         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24442         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24443         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24444         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24445         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24446         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24447         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24448         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24449         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24450         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24451         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24452         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24453         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24454         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24455         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24456         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24457         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24458         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24459         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24460         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24461         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24462         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24463         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24464         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24465         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24466         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24467         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
24468         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
24469         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
24470         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
24471         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
24472         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
24473         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     468},
24474         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
24475         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
24476         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
24477         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
24478         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     473},
24479         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     474},
24480         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     475},
24481         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     476},
24482         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     477},
24483         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     478},
24484         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     479},
24485         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     480},
24486         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     481},
24487         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     482},
24488         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     483},
24489         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     484},
24490         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     485},
24491         {"PKO_REG_CRC_CTL0"            ,           0x1180050000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     486},
24492         {"PKO_REG_CRC_CTL1"            ,           0x1180050000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     486},
24493         {"PKO_REG_CRC_ENABLE"          ,           0x1180050000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     487},
24494         {"PKO_REG_CRC_IV0"             ,           0x1180050000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     488},
24495         {"PKO_REG_CRC_IV1"             ,           0x1180050000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     488},
24496         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     489},
24497         {"PKO_REG_DEBUG1"              ,           0x11800500000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     490},
24498         {"PKO_REG_DEBUG2"              ,           0x11800500000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     491},
24499         {"PKO_REG_DEBUG3"              ,           0x11800500000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     492},
24500         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     493},
24501         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     494},
24502         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     495},
24503         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     496},
24504         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     497},
24505         {"PKO_REG_QUEUE_PTRS1"         ,           0x1180050000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     498},
24506         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     499},
24507         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     500},
24508         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     501},
24509         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     502},
24510         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     503},
24511         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
24512         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
24513         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
24514         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
24515         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
24516         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
24517         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
24518         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     504},
24519         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     505},
24520         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     506},
24521         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     507},
24522         {"POW_PF_RST_MSK"              ,           0x1670000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     508},
24523         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24524         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24525         {"POW_PP_GRP_MSK2"             ,           0x1670000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24526         {"POW_PP_GRP_MSK3"             ,           0x1670000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24527         {"POW_PP_GRP_MSK4"             ,           0x1670000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24528         {"POW_PP_GRP_MSK5"             ,           0x1670000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24529         {"POW_PP_GRP_MSK6"             ,           0x1670000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24530         {"POW_PP_GRP_MSK7"             ,           0x1670000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24531         {"POW_PP_GRP_MSK8"             ,           0x1670000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24532         {"POW_PP_GRP_MSK9"             ,           0x1670000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24533         {"POW_PP_GRP_MSK10"            ,           0x1670000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24534         {"POW_PP_GRP_MSK11"            ,           0x1670000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24535         {"POW_PP_GRP_MSK12"            ,           0x1670000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24536         {"POW_PP_GRP_MSK13"            ,           0x1670000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24537         {"POW_PP_GRP_MSK14"            ,           0x1670000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24538         {"POW_PP_GRP_MSK15"            ,           0x1670000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     509},
24539         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     510},
24540         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     510},
24541         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     510},
24542         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     510},
24543         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     510},
24544         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     510},
24545         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     510},
24546         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     510},
24547         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     511},
24548         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     511},
24549         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     511},
24550         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     511},
24551         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     511},
24552         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     511},
24553         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     511},
24554         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     511},
24555         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     512},
24556         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     513},
24557         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
24558         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
24559         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
24560         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
24561         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
24562         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
24563         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
24564         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
24565         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     515},
24566         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24567         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24568         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24569         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24570         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24571         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24572         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24573         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24574         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24575         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24576         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24577         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24578         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24579         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24580         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24581         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
24582         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     517},
24583         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24584         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24585         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24586         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24587         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24588         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24589         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24590         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24591         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24592         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24593         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24594         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24595         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24596         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24597         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24598         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
24599         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24600         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24601         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24602         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24603         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24604         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24605         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24606         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24607         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24608         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24609         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24610         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24611         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24612         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24613         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24614         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
24615         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     520},
24616         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     521},
24617         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     522},
24618         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     523},
24619         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     524},
24620         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     525},
24621         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     526},
24622         {"SPX0_BCKPRS_CNT"             ,           0x1180090000340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     527},
24623         {"SPX1_BCKPRS_CNT"             ,           0x1180098000340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     527},
24624         {"SPX0_BIST_STAT"              ,           0x11800900007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     528},
24625         {"SPX1_BIST_STAT"              ,           0x11800980007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     528},
24626         {"SPX0_CLK_CTL"                ,           0x1180090000348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     529},
24627         {"SPX1_CLK_CTL"                ,           0x1180098000348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     529},
24628         {"SPX0_CLK_STAT"               ,           0x1180090000350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     530},
24629         {"SPX1_CLK_STAT"               ,           0x1180098000350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     530},
24630         {"SPX0_DBG_DESKEW_CTL"         ,           0x1180090000368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     531},
24631         {"SPX1_DBG_DESKEW_CTL"         ,           0x1180098000368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     531},
24632         {"SPX0_DBG_DESKEW_STATE"       ,           0x1180090000370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
24633         {"SPX1_DBG_DESKEW_STATE"       ,           0x1180098000370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
24634         {"SPX0_DRV_CTL"                ,           0x1180090000358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     533},
24635         {"SPX1_DRV_CTL"                ,           0x1180098000358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     533},
24636         {"SPX0_ERR_CTL"                ,           0x1180090000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     534},
24637         {"SPX1_ERR_CTL"                ,           0x1180098000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     534},
24638         {"SPX0_INT_DAT"                ,           0x1180090000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     535},
24639         {"SPX1_INT_DAT"                ,           0x1180098000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     535},
24640         {"SPX0_INT_MSK"                ,           0x1180090000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     536},
24641         {"SPX1_INT_MSK"                ,           0x1180098000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     536},
24642         {"SPX0_INT_REG"                ,           0x1180090000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     537},
24643         {"SPX1_INT_REG"                ,           0x1180098000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     537},
24644         {"SPX0_INT_SYNC"               ,           0x1180090000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     538},
24645         {"SPX1_INT_SYNC"               ,           0x1180098000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     538},
24646         {"SPX0_TPA_ACC"                ,           0x1180090000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     539},
24647         {"SPX1_TPA_ACC"                ,           0x1180098000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     539},
24648         {"SPX0_TPA_MAX"                ,           0x1180090000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     540},
24649         {"SPX1_TPA_MAX"                ,           0x1180098000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     540},
24650         {"SPX0_TPA_SEL"                ,           0x1180090000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     541},
24651         {"SPX1_TPA_SEL"                ,           0x1180098000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     541},
24652         {"SPX0_TRN4_CTL"               ,           0x1180090000360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     542},
24653         {"SPX1_TRN4_CTL"               ,           0x1180098000360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     542},
24654         {"SRX0_COM_CTL"                ,           0x1180090000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     543},
24655         {"SRX1_COM_CTL"                ,           0x1180098000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     543},
24656         {"SRX0_IGN_RX_FULL"            ,           0x1180090000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     544},
24657         {"SRX1_IGN_RX_FULL"            ,           0x1180098000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     544},
24658         {"SRX0_SPI4_CAL000"            ,           0x1180090000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24659         {"SRX0_SPI4_CAL001"            ,           0x1180090000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24660         {"SRX0_SPI4_CAL002"            ,           0x1180090000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24661         {"SRX0_SPI4_CAL003"            ,           0x1180090000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24662         {"SRX0_SPI4_CAL004"            ,           0x1180090000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24663         {"SRX0_SPI4_CAL005"            ,           0x1180090000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24664         {"SRX0_SPI4_CAL006"            ,           0x1180090000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24665         {"SRX0_SPI4_CAL007"            ,           0x1180090000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24666         {"SRX0_SPI4_CAL008"            ,           0x1180090000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24667         {"SRX0_SPI4_CAL009"            ,           0x1180090000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24668         {"SRX0_SPI4_CAL010"            ,           0x1180090000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24669         {"SRX0_SPI4_CAL011"            ,           0x1180090000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24670         {"SRX0_SPI4_CAL012"            ,           0x1180090000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24671         {"SRX0_SPI4_CAL013"            ,           0x1180090000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24672         {"SRX0_SPI4_CAL014"            ,           0x1180090000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24673         {"SRX0_SPI4_CAL015"            ,           0x1180090000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24674         {"SRX0_SPI4_CAL016"            ,           0x1180090000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24675         {"SRX0_SPI4_CAL017"            ,           0x1180090000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24676         {"SRX0_SPI4_CAL018"            ,           0x1180090000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24677         {"SRX0_SPI4_CAL019"            ,           0x1180090000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24678         {"SRX0_SPI4_CAL020"            ,           0x11800900000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24679         {"SRX0_SPI4_CAL021"            ,           0x11800900000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24680         {"SRX0_SPI4_CAL022"            ,           0x11800900000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24681         {"SRX0_SPI4_CAL023"            ,           0x11800900000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24682         {"SRX0_SPI4_CAL024"            ,           0x11800900000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24683         {"SRX0_SPI4_CAL025"            ,           0x11800900000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24684         {"SRX0_SPI4_CAL026"            ,           0x11800900000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24685         {"SRX0_SPI4_CAL027"            ,           0x11800900000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24686         {"SRX0_SPI4_CAL028"            ,           0x11800900000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24687         {"SRX0_SPI4_CAL029"            ,           0x11800900000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24688         {"SRX0_SPI4_CAL030"            ,           0x11800900000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24689         {"SRX0_SPI4_CAL031"            ,           0x11800900000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24690         {"SRX1_SPI4_CAL000"            ,           0x1180098000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24691         {"SRX1_SPI4_CAL001"            ,           0x1180098000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24692         {"SRX1_SPI4_CAL002"            ,           0x1180098000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24693         {"SRX1_SPI4_CAL003"            ,           0x1180098000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24694         {"SRX1_SPI4_CAL004"            ,           0x1180098000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24695         {"SRX1_SPI4_CAL005"            ,           0x1180098000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24696         {"SRX1_SPI4_CAL006"            ,           0x1180098000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24697         {"SRX1_SPI4_CAL007"            ,           0x1180098000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24698         {"SRX1_SPI4_CAL008"            ,           0x1180098000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24699         {"SRX1_SPI4_CAL009"            ,           0x1180098000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24700         {"SRX1_SPI4_CAL010"            ,           0x1180098000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24701         {"SRX1_SPI4_CAL011"            ,           0x1180098000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24702         {"SRX1_SPI4_CAL012"            ,           0x1180098000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24703         {"SRX1_SPI4_CAL013"            ,           0x1180098000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24704         {"SRX1_SPI4_CAL014"            ,           0x1180098000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24705         {"SRX1_SPI4_CAL015"            ,           0x1180098000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24706         {"SRX1_SPI4_CAL016"            ,           0x1180098000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24707         {"SRX1_SPI4_CAL017"            ,           0x1180098000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24708         {"SRX1_SPI4_CAL018"            ,           0x1180098000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24709         {"SRX1_SPI4_CAL019"            ,           0x1180098000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24710         {"SRX1_SPI4_CAL020"            ,           0x11800980000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24711         {"SRX1_SPI4_CAL021"            ,           0x11800980000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24712         {"SRX1_SPI4_CAL022"            ,           0x11800980000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24713         {"SRX1_SPI4_CAL023"            ,           0x11800980000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24714         {"SRX1_SPI4_CAL024"            ,           0x11800980000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24715         {"SRX1_SPI4_CAL025"            ,           0x11800980000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24716         {"SRX1_SPI4_CAL026"            ,           0x11800980000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24717         {"SRX1_SPI4_CAL027"            ,           0x11800980000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24718         {"SRX1_SPI4_CAL028"            ,           0x11800980000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24719         {"SRX1_SPI4_CAL029"            ,           0x11800980000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24720         {"SRX1_SPI4_CAL030"            ,           0x11800980000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24721         {"SRX1_SPI4_CAL031"            ,           0x11800980000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
24722         {"SRX0_SPI4_STAT"              ,           0x1180090000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     546},
24723         {"SRX1_SPI4_STAT"              ,           0x1180098000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     546},
24724         {"SRX0_SW_TICK_CTL"            ,           0x1180090000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     547},
24725         {"SRX1_SW_TICK_CTL"            ,           0x1180098000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     547},
24726         {"SRX0_SW_TICK_DAT"            ,           0x1180090000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     548},
24727         {"SRX1_SW_TICK_DAT"            ,           0x1180098000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     548},
24728         {"STX0_ARB_CTL"                ,           0x1180090000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     549},
24729         {"STX1_ARB_CTL"                ,           0x1180098000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     549},
24730         {"STX0_BCKPRS_CNT"             ,           0x1180090000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     550},
24731         {"STX1_BCKPRS_CNT"             ,           0x1180098000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     550},
24732         {"STX0_COM_CTL"                ,           0x1180090000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     551},
24733         {"STX1_COM_CTL"                ,           0x1180098000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     551},
24734         {"STX0_DIP_CNT"                ,           0x1180090000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     552},
24735         {"STX1_DIP_CNT"                ,           0x1180098000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     552},
24736         {"STX0_IGN_CAL"                ,           0x1180090000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     553},
24737         {"STX1_IGN_CAL"                ,           0x1180098000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     553},
24738         {"STX0_INT_MSK"                ,           0x11800900006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     554},
24739         {"STX1_INT_MSK"                ,           0x11800980006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     554},
24740         {"STX0_INT_REG"                ,           0x1180090000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
24741         {"STX1_INT_REG"                ,           0x1180098000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
24742         {"STX0_INT_SYNC"               ,           0x11800900006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     556},
24743         {"STX1_INT_SYNC"               ,           0x11800980006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     556},
24744         {"STX0_MIN_BST"                ,           0x1180090000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     557},
24745         {"STX1_MIN_BST"                ,           0x1180098000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     557},
24746         {"STX0_SPI4_CAL000"            ,           0x1180090000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24747         {"STX0_SPI4_CAL001"            ,           0x1180090000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24748         {"STX0_SPI4_CAL002"            ,           0x1180090000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24749         {"STX0_SPI4_CAL003"            ,           0x1180090000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24750         {"STX0_SPI4_CAL004"            ,           0x1180090000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24751         {"STX0_SPI4_CAL005"            ,           0x1180090000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24752         {"STX0_SPI4_CAL006"            ,           0x1180090000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24753         {"STX0_SPI4_CAL007"            ,           0x1180090000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24754         {"STX0_SPI4_CAL008"            ,           0x1180090000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24755         {"STX0_SPI4_CAL009"            ,           0x1180090000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24756         {"STX0_SPI4_CAL010"            ,           0x1180090000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24757         {"STX0_SPI4_CAL011"            ,           0x1180090000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24758         {"STX0_SPI4_CAL012"            ,           0x1180090000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24759         {"STX0_SPI4_CAL013"            ,           0x1180090000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24760         {"STX0_SPI4_CAL014"            ,           0x1180090000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24761         {"STX0_SPI4_CAL015"            ,           0x1180090000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24762         {"STX0_SPI4_CAL016"            ,           0x1180090000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24763         {"STX0_SPI4_CAL017"            ,           0x1180090000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24764         {"STX0_SPI4_CAL018"            ,           0x1180090000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24765         {"STX0_SPI4_CAL019"            ,           0x1180090000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24766         {"STX0_SPI4_CAL020"            ,           0x11800900004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24767         {"STX0_SPI4_CAL021"            ,           0x11800900004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24768         {"STX0_SPI4_CAL022"            ,           0x11800900004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24769         {"STX0_SPI4_CAL023"            ,           0x11800900004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24770         {"STX0_SPI4_CAL024"            ,           0x11800900004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24771         {"STX0_SPI4_CAL025"            ,           0x11800900004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24772         {"STX0_SPI4_CAL026"            ,           0x11800900004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24773         {"STX0_SPI4_CAL027"            ,           0x11800900004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24774         {"STX0_SPI4_CAL028"            ,           0x11800900004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24775         {"STX0_SPI4_CAL029"            ,           0x11800900004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24776         {"STX0_SPI4_CAL030"            ,           0x11800900004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24777         {"STX0_SPI4_CAL031"            ,           0x11800900004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24778         {"STX1_SPI4_CAL000"            ,           0x1180098000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24779         {"STX1_SPI4_CAL001"            ,           0x1180098000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24780         {"STX1_SPI4_CAL002"            ,           0x1180098000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24781         {"STX1_SPI4_CAL003"            ,           0x1180098000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24782         {"STX1_SPI4_CAL004"            ,           0x1180098000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24783         {"STX1_SPI4_CAL005"            ,           0x1180098000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24784         {"STX1_SPI4_CAL006"            ,           0x1180098000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24785         {"STX1_SPI4_CAL007"            ,           0x1180098000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24786         {"STX1_SPI4_CAL008"            ,           0x1180098000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24787         {"STX1_SPI4_CAL009"            ,           0x1180098000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24788         {"STX1_SPI4_CAL010"            ,           0x1180098000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24789         {"STX1_SPI4_CAL011"            ,           0x1180098000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24790         {"STX1_SPI4_CAL012"            ,           0x1180098000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24791         {"STX1_SPI4_CAL013"            ,           0x1180098000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24792         {"STX1_SPI4_CAL014"            ,           0x1180098000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24793         {"STX1_SPI4_CAL015"            ,           0x1180098000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24794         {"STX1_SPI4_CAL016"            ,           0x1180098000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24795         {"STX1_SPI4_CAL017"            ,           0x1180098000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24796         {"STX1_SPI4_CAL018"            ,           0x1180098000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24797         {"STX1_SPI4_CAL019"            ,           0x1180098000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24798         {"STX1_SPI4_CAL020"            ,           0x11800980004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24799         {"STX1_SPI4_CAL021"            ,           0x11800980004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24800         {"STX1_SPI4_CAL022"            ,           0x11800980004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24801         {"STX1_SPI4_CAL023"            ,           0x11800980004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24802         {"STX1_SPI4_CAL024"            ,           0x11800980004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24803         {"STX1_SPI4_CAL025"            ,           0x11800980004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24804         {"STX1_SPI4_CAL026"            ,           0x11800980004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24805         {"STX1_SPI4_CAL027"            ,           0x11800980004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24806         {"STX1_SPI4_CAL028"            ,           0x11800980004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24807         {"STX1_SPI4_CAL029"            ,           0x11800980004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24808         {"STX1_SPI4_CAL030"            ,           0x11800980004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24809         {"STX1_SPI4_CAL031"            ,           0x11800980004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
24810         {"STX0_SPI4_DAT"               ,           0x1180090000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     559},
24811         {"STX1_SPI4_DAT"               ,           0x1180098000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     559},
24812         {"STX0_SPI4_STAT"              ,           0x1180090000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     560},
24813         {"STX1_SPI4_STAT"              ,           0x1180098000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     560},
24814         {"STX0_STAT_BYTES_HI"          ,           0x1180090000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     561},
24815         {"STX1_STAT_BYTES_HI"          ,           0x1180098000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     561},
24816         {"STX0_STAT_BYTES_LO"          ,           0x1180090000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     562},
24817         {"STX1_STAT_BYTES_LO"          ,           0x1180098000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     562},
24818         {"STX0_STAT_CTL"               ,           0x1180090000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     563},
24819         {"STX1_STAT_CTL"               ,           0x1180098000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     563},
24820         {"STX0_STAT_PKT_XMT"           ,           0x1180090000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     564},
24821         {"STX1_STAT_PKT_XMT"           ,           0x1180098000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     564},
24822         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     565},
24823         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     566},
24824         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     567},
24825         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
24826         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     569},
24827         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     570},
24828         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     571},
24829         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     572},
24830         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     573},
24831         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     574},
24832         {"TRA_BIST_STATUS"             ,           0x11800A8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     575},
24833         {"TRA_CTL"                     ,           0x11800A8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     576},
24834         {"TRA_CYCLES_SINCE"            ,           0x11800A8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     577},
24835         {"TRA_CYCLES_SINCE1"           ,           0x11800A8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     578},
24836         {"TRA_FILT_ADR_ADR"            ,           0x11800A8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     579},
24837         {"TRA_FILT_ADR_MSK"            ,           0x11800A8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     580},
24838         {"TRA_FILT_CMD"                ,           0x11800A8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     581},
24839         {"TRA_FILT_DID"                ,           0x11800A8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     582},
24840         {"TRA_FILT_SID"                ,           0x11800A8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     583},
24841         {"TRA_INT_STATUS"              ,           0x11800A8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     584},
24842         {"TRA_READ_DAT"                ,           0x11800A8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     585},
24843         {"TRA_TRIG0_ADR_ADR"           ,           0x11800A8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     586},
24844         {"TRA_TRIG0_ADR_MSK"           ,           0x11800A80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     587},
24845         {"TRA_TRIG0_CMD"               ,           0x11800A8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     588},
24846         {"TRA_TRIG0_DID"               ,           0x11800A8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     589},
24847         {"TRA_TRIG0_SID"               ,           0x11800A8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     590},
24848         {"TRA_TRIG1_ADR_ADR"           ,           0x11800A80000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     591},
24849         {"TRA_TRIG1_ADR_MSK"           ,           0x11800A80000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     592},
24850         {"TRA_TRIG1_CMD"               ,           0x11800A80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     593},
24851         {"TRA_TRIG1_DID"               ,           0x11800A80000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     594},
24852         {"TRA_TRIG1_SID"               ,           0x11800A80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     595},
24853         {"ZIP_CMD_BIST_RESULT"         ,           0x1180038000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     596},
24854         {"ZIP_CMD_BUF"                 ,           0x1180038000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     597},
24855         {"ZIP_CMD_CTL"                 ,           0x1180038000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     598},
24856         {"ZIP_CONSTANTS"               ,           0x11800380000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     599},
24857         {"ZIP_DEBUG0"                  ,           0x1180038000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     600},
24858         {"ZIP_ERROR"                   ,           0x1180038000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     601},
24859         {"ZIP_INT_MASK"                ,           0x1180038000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     602},
24860         {NULL,0,0,0,0}
24861 };
24862 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xxp1[] = {
24863         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
24864         {"OVRFLW"                      ,        0,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
24865         {"TXPOP"                       ,        4,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
24866         {"TXPSH"                       ,        8,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
24867         {"RESERVED_12_63"              ,        12,     52,     0,      "RAZ",  1,      1,      0,      0},
24868         {"OVRFLW"                      ,        0,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
24869         {"TXPOP"                       ,        4,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
24870         {"TXPSH"                       ,        8,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
24871         {"RESERVED_12_63"              ,        12,     52,     1,      "RAZ",  1,      1,      0,      0},
24872         {"INT_LOOP"                    ,        0,      4,      2,      "R/W",  0,      0,      0ull,   0ull},
24873         {"EXT_LOOP"                    ,        4,      4,      2,      "R/W",  0,      0,      0ull,   0ull},
24874         {"RESERVED_8_63"               ,        8,      56,     2,      "RAZ",  1,      1,      0,      0},
24875         {"BYPASS"                      ,        0,      1,      3,      "R/W",  0,      1,      0ull,   0},
24876         {"RESERVED_1_63"               ,        1,      63,     3,      "RAZ",  1,      1,      0,      0},
24877         {"SETTING"                     ,        0,      5,      4,      "R/W",  0,      1,      0ull,   0},
24878         {"RESERVED_5_63"               ,        5,      59,     4,      "RAZ",  1,      1,      0,      0},
24879         {"NCTL"                        ,        0,      4,      5,      "RO",   0,      1,      0ull,   0},
24880         {"PCTL"                        ,        4,      5,      5,      "RO",   0,      1,      0ull,   0},
24881         {"RESERVED_9_63"               ,        9,      55,     5,      "RAZ",  1,      1,      0,      0},
24882         {"NCTL"                        ,        0,      4,      6,      "R/W",  0,      1,      0ull,   0},
24883         {"PCTL"                        ,        4,      4,      6,      "R/W",  0,      1,      0ull,   0},
24884         {"RESERVED_8_63"               ,        8,      56,     6,      "RAZ",  1,      1,      0,      0},
24885         {"NCTL"                        ,        0,      5,      7,      "R/W",  0,      1,      0ull,   0},
24886         {"RESERVED_5_63"               ,        5,      59,     7,      "RAZ",  1,      1,      0,      0},
24887         {"NCTL"                        ,        0,      5,      8,      "R/W",  0,      1,      0ull,   0},
24888         {"RESERVED_5_63"               ,        5,      59,     8,      "RAZ",  1,      1,      0,      0},
24889         {"PCTL"                        ,        0,      5,      9,      "R/W",  0,      1,      0ull,   0},
24890         {"RESERVED_5_63"               ,        5,      59,     9,      "RAZ",  1,      1,      0,      0},
24891         {"PCTL"                        ,        0,      5,      10,     "R/W",  0,      1,      0ull,   0},
24892         {"RESERVED_5_63"               ,        5,      59,     10,     "RAZ",  1,      1,      0,      0},
24893         {"SETTING"                     ,        0,      5,      11,     "RO",   1,      1,      0,      0},
24894         {"DFALOCK"                     ,        5,      1,      11,     "RO",   1,      1,      0,      0},
24895         {"DFALEAD"                     ,        6,      1,      11,     "RO",   1,      1,      0,      0},
24896         {"DFALAG"                      ,        7,      1,      11,     "RO",   1,      1,      0,      0},
24897         {"DFASET"                      ,        8,      5,      11,     "RO",   1,      1,      0,      0},
24898         {"RESERVED_13_63"              ,        13,     51,     11,     "RAZ",  1,      1,      0,      0},
24899         {"SETTING"                     ,        0,      5,      12,     "R/W",  0,      0,      24ull,  0ull},
24900         {"RESERVED_5_63"               ,        5,      59,     12,     "RAZ",  1,      1,      0,      0},
24901         {"PRT_EN"                      ,        0,      4,      13,     "R/W",  0,      0,      0ull,   1ull},
24902         {"RESERVED_4_63"               ,        4,      60,     13,     "RAZ",  1,      1,      0,      0},
24903         {"SETTING"                     ,        0,      5,      14,     "R/W",  0,      0,      24ull,  0ull},
24904         {"RESERVED_5_63"               ,        5,      59,     14,     "RAZ",  1,      1,      0,      0},
24905         {"NCTL"                        ,        0,      5,      15,     "R/W",  0,      0,      6ull,   6ull},
24906         {"RESERVED_5_7"                ,        5,      3,      15,     "RAZ",  1,      1,      0,      0},
24907         {"PCTL"                        ,        8,      5,      15,     "R/W",  0,      0,      9ull,   9ull},
24908         {"RESERVED_13_63"              ,        13,     51,     15,     "RAZ",  1,      1,      0,      0},
24909         {"MARK"                        ,        0,      4,      16,     "R/W",  0,      0,      0ull,   0ull},
24910         {"RESERVED_4_63"               ,        4,      60,     16,     "RAZ",  1,      1,      0,      0},
24911         {"PRT_EN"                      ,        0,      4,      17,     "R/W",  0,      0,      0ull,   1ull},
24912         {"RESERVED_4_63"               ,        4,      60,     17,     "RAZ",  1,      1,      0,      0},
24913         {"NCTL"                        ,        0,      4,      18,     "R/W",  0,      1,      15ull,  0},
24914         {"PCTL"                        ,        4,      5,      18,     "R/W",  0,      1,      31ull,  0},
24915         {"RESERVED_9_63"               ,        9,      55,     18,     "RAZ",  1,      1,      0,      0},
24916         {"EN"                          ,        0,      1,      19,     "R/W",  0,      1,      1ull,   0},
24917         {"RESERVED_1_63"               ,        1,      63,     19,     "RAZ",  1,      1,      0,      0},
24918         {"BIST"                        ,        0,      4,      20,     "RO",   0,      0,      0ull,   0ull},
24919         {"RESERVED_4_63"               ,        4,      60,     20,     "RAZ",  1,      1,      0,      0},
24920         {"DINT"                        ,        0,      16,     21,     "WO",   0,      0,      0ull,   0ull},
24921         {"RESERVED_16_63"              ,        16,     48,     21,     "RAZ",  1,      1,      0,      0},
24922         {"FUSE"                        ,        0,      16,     22,     "RO",   1,      1,      0,      0},
24923         {"RESERVED_16_63"              ,        16,     48,     22,     "RAZ",  1,      1,      0,      0},
24924         {"GSTOP"                       ,        0,      1,      23,     "R/W",  0,      0,      0ull,   0ull},
24925         {"RESERVED_1_63"               ,        1,      63,     23,     "RAZ",  1,      1,      0,      0},
24926         {"WORKQ"                       ,        0,      16,     24,     "R/W",  0,      0,      0ull,   0ull},
24927         {"GPIO"                        ,        16,     16,     24,     "R/W",  0,      0,      0ull,   0ull},
24928         {"MBOX"                        ,        32,     2,      24,     "R/W",  0,      0,      0ull,   0ull},
24929         {"UART"                        ,        34,     2,      24,     "R/W",  0,      0,      0ull,   0ull},
24930         {"PCI_INT"                     ,        36,     4,      24,     "R/W",  0,      0,      0ull,   0ull},
24931         {"PCI_MSI"                     ,        40,     4,      24,     "R/W",  0,      0,      0ull,   0ull},
24932         {"RESERVED_44_44"              ,        44,     1,      24,     "RAZ",  1,      1,      0,      0},
24933         {"TWSI"                        ,        45,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
24934         {"RML"                         ,        46,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
24935         {"TRACE"                       ,        47,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
24936         {"GMX_DRP"                     ,        48,     2,      24,     "R/W",  0,      0,      0ull,   0ull},
24937         {"IPD_DRP"                     ,        50,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
24938         {"KEY_ZERO"                    ,        51,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
24939         {"TIMER"                       ,        52,     4,      24,     "R/W",  0,      0,      0ull,   0ull},
24940         {"RESERVED_56_63"              ,        56,     8,      24,     "RAZ",  1,      1,      0,      0},
24941         {"WDOG"                        ,        0,      16,     25,     "R/W",  0,      0,      0ull,   0ull},
24942         {"RESERVED_16_63"              ,        16,     48,     25,     "RAZ",  1,      1,      0,      0},
24943         {"WORKQ"                       ,        0,      16,     26,     "R/W",  0,      0,      0ull,   0ull},
24944         {"GPIO"                        ,        16,     16,     26,     "R/W",  0,      0,      0ull,   0ull},
24945         {"MBOX"                        ,        32,     2,      26,     "R/W",  0,      0,      0ull,   0ull},
24946         {"UART"                        ,        34,     2,      26,     "R/W",  0,      0,      0ull,   0ull},
24947         {"PCI_INT"                     ,        36,     4,      26,     "R/W",  0,      0,      0ull,   0ull},
24948         {"PCI_MSI"                     ,        40,     4,      26,     "R/W",  0,      0,      0ull,   0ull},
24949         {"RESERVED_44_44"              ,        44,     1,      26,     "RAZ",  1,      1,      0,      0},
24950         {"TWSI"                        ,        45,     1,      26,     "R/W",  0,      0,      0ull,   0ull},
24951         {"RML"                         ,        46,     1,      26,     "R/W",  0,      0,      0ull,   0ull},
24952         {"TRACE"                       ,        47,     1,      26,     "R/W",  0,      0,      0ull,   0ull},
24953         {"GMX_DRP"                     ,        48,     2,      26,     "R/W",  0,      0,      0ull,   0ull},
24954         {"IPD_DRP"                     ,        50,     1,      26,     "R/W",  0,      0,      0ull,   0ull},
24955         {"KEY_ZERO"                    ,        51,     1,      26,     "R/W",  0,      0,      0ull,   0ull},
24956         {"TIMER"                       ,        52,     4,      26,     "R/W",  0,      0,      0ull,   0ull},
24957         {"RESERVED_56_63"              ,        56,     8,      26,     "RAZ",  1,      1,      0,      0},
24958         {"WDOG"                        ,        0,      16,     27,     "R/W",  0,      0,      0ull,   0ull},
24959         {"RESERVED_16_63"              ,        16,     48,     27,     "RAZ",  1,      1,      0,      0},
24960         {"WORKQ"                       ,        0,      16,     28,     "RO",   0,      0,      0ull,   0ull},
24961         {"GPIO"                        ,        16,     16,     28,     "RO",   0,      0,      0ull,   0ull},
24962         {"MBOX"                        ,        32,     2,      28,     "RO",   0,      0,      0ull,   0ull},
24963         {"UART"                        ,        34,     2,      28,     "RO",   0,      0,      0ull,   0ull},
24964         {"PCI_INT"                     ,        36,     4,      28,     "RO",   0,      0,      0ull,   0ull},
24965         {"PCI_MSI"                     ,        40,     4,      28,     "RO",   0,      0,      0ull,   0ull},
24966         {"WDOG_SUM"                    ,        44,     1,      28,     "RO",   0,      0,      0ull,   0ull},
24967         {"TWSI"                        ,        45,     1,      28,     "RO",   0,      0,      0ull,   0ull},
24968         {"RML"                         ,        46,     1,      28,     "RO",   0,      0,      0ull,   0ull},
24969         {"TRACE"                       ,        47,     1,      28,     "RO",   0,      0,      0ull,   0ull},
24970         {"GMX_DRP"                     ,        48,     2,      28,     "R/W1C",        0,      0,      0ull,   0ull},
24971         {"IPD_DRP"                     ,        50,     1,      28,     "R/W1C",        0,      0,      0ull,   0ull},
24972         {"KEY_ZERO"                    ,        51,     1,      28,     "R/W1C",        0,      0,      0ull,   0ull},
24973         {"TIMER"                       ,        52,     4,      28,     "R/W1C",        0,      0,      0ull,   0ull},
24974         {"RESERVED_56_63"              ,        56,     8,      28,     "RAZ",  1,      1,      0,      0},
24975         {"WORKQ"                       ,        0,      16,     29,     "RO",   0,      0,      0ull,   0ull},
24976         {"GPIO"                        ,        16,     16,     29,     "RO",   0,      0,      0ull,   0ull},
24977         {"MBOX"                        ,        32,     2,      29,     "RO",   0,      0,      0ull,   0ull},
24978         {"UART"                        ,        34,     2,      29,     "RO",   0,      0,      0ull,   0ull},
24979         {"PCI_INT"                     ,        36,     4,      29,     "RO",   0,      0,      0ull,   0ull},
24980         {"PCI_MSI"                     ,        40,     4,      29,     "RO",   0,      0,      0ull,   0ull},
24981         {"WDOG_SUM"                    ,        44,     1,      29,     "RO",   0,      0,      0ull,   0ull},
24982         {"TWSI"                        ,        45,     1,      29,     "RO",   0,      0,      0ull,   0ull},
24983         {"RML"                         ,        46,     1,      29,     "RO",   0,      0,      0ull,   0ull},
24984         {"TRACE"                       ,        47,     1,      29,     "RO",   0,      0,      0ull,   0ull},
24985         {"GMX_DRP"                     ,        48,     2,      29,     "R/W1C",        0,      0,      0ull,   0ull},
24986         {"IPD_DRP"                     ,        50,     1,      29,     "R/W1C",        0,      0,      0ull,   0ull},
24987         {"KEY_ZERO"                    ,        51,     1,      29,     "R/W1C",        0,      0,      0ull,   0ull},
24988         {"TIMER"                       ,        52,     4,      29,     "R/W1C",        0,      0,      0ull,   0ull},
24989         {"RESERVED_56_63"              ,        56,     8,      29,     "RAZ",  1,      1,      0,      0},
24990         {"WDOG"                        ,        0,      16,     30,     "RO",   0,      0,      0ull,   0ull},
24991         {"RESERVED_16_63"              ,        16,     48,     30,     "RAZ",  1,      1,      0,      0},
24992         {"BITS"                        ,        0,      32,     31,     "R/W1C",        0,      0,      0ull,   0ull},
24993         {"RESERVED_32_63"              ,        32,     32,     31,     "RAZ",  1,      1,      0,      0},
24994         {"BITS"                        ,        0,      32,     32,     "R/W1", 0,      0,      0ull,   0ull},
24995         {"RESERVED_32_63"              ,        32,     32,     32,     "RAZ",  1,      1,      0,      0},
24996         {"NMI"                         ,        0,      16,     33,     "WO",   0,      0,      0ull,   0ull},
24997         {"RESERVED_16_63"              ,        16,     48,     33,     "RAZ",  1,      1,      0,      0},
24998         {"INTR"                        ,        0,      2,      34,     "R/W",  0,      0,      0ull,   0ull},
24999         {"RESERVED_2_63"               ,        2,      62,     34,     "RAZ",  1,      1,      0,      0},
25000         {"PPDBG"                       ,        0,      16,     35,     "RO",   0,      0,      0ull,   0ull},
25001         {"RESERVED_16_63"              ,        16,     48,     35,     "RAZ",  1,      1,      0,      0},
25002         {"POKE"                        ,        0,      64,     36,     "RAZ",  1,      1,      0,      0},
25003         {"RST0"                        ,        0,      1,      37,     "R/W",  1,      1,      0,      0},
25004         {"RST"                         ,        1,      15,     37,     "R/W",  0,      0,      32767ull,       0ull},
25005         {"RESERVED_16_63"              ,        16,     48,     37,     "RAZ",  1,      1,      0,      0},
25006         {"SOFT_BIST"                   ,        0,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
25007         {"RESERVED_1_63"               ,        1,      63,     38,     "RAZ",  1,      1,      0,      0},
25008         {"SOFT_PRST"                   ,        0,      1,      39,     "R/W",  0,      0,      1ull,   0ull},
25009         {"NPI"                         ,        1,      1,      39,     "R/W",  0,      0,      0ull,   0ull},
25010         {"HOST64"                      ,        2,      1,      39,     "R/W",  0,      0,      1ull,   1ull},
25011         {"RESERVED_3_63"               ,        3,      61,     39,     "RAZ",  1,      1,      0,      0},
25012         {"SOFT_RST"                    ,        0,      1,      40,     "WO",   0,      0,      0ull,   0ull},
25013         {"RESERVED_1_63"               ,        1,      63,     40,     "RAZ",  1,      1,      0,      0},
25014         {"LEN"                         ,        0,      36,     41,     "R/W",  0,      0,      0ull,   0ull},
25015         {"ONE_SHOT"                    ,        36,     1,      41,     "R/W",  0,      0,      0ull,   0ull},
25016         {"RESERVED_37_63"              ,        37,     27,     41,     "RAZ",  1,      1,      0,      0},
25017         {"MODE"                        ,        0,      2,      42,     "R/W",  0,      0,      0ull,   0ull},
25018         {"STATE"                       ,        2,      2,      42,     "RO",   0,      0,      0ull,   0ull},
25019         {"LEN"                         ,        4,      16,     42,     "R/W",  0,      0,      0ull,   0ull},
25020         {"CNT"                         ,        20,     24,     42,     "RO",   0,      0,      0ull,   0ull},
25021         {"DSTOP"                       ,        44,     1,      42,     "R/W",  0,      0,      0ull,   0ull},
25022         {"GSTOPEN"                     ,        45,     1,      42,     "R/W",  0,      0,      0ull,   0ull},
25023         {"RESERVED_46_63"              ,        46,     18,     42,     "RAZ",  1,      1,      0,      0},
25024         {"DATA"                        ,        0,      17,     43,     "RO",   0,      1,      0ull,   0},
25025         {"DSEL_EXT"                    ,        17,     1,      43,     "R/W",  0,      0,      1ull,   0ull},
25026         {"C_MUL"                       ,        18,     5,      43,     "RO",   1,      1,      0,      0},
25027         {"REM"                         ,        23,     6,      43,     "RO",   1,      1,      0,      0},
25028         {"RESERVED_29_63"              ,        29,     35,     43,     "RAZ",  1,      1,      0,      0},
25029         {"PDF"                         ,        0,      4,      44,     "RO",   0,      0,      0ull,   0ull},
25030         {"RESERVED_4_15"               ,        4,      12,     44,     "RAZ",  0,      0,      0ull,   0ull},
25031         {"RDF"                         ,        16,     4,      44,     "RO",   0,      0,      0ull,   0ull},
25032         {"RESERVED_20_63"              ,        20,     44,     44,     "RAZ",  0,      0,      0ull,   0ull},
25033         {"P1_BRF"                      ,        0,      8,      45,     "RO",   0,      0,      0ull,   0ull},
25034         {"P0_BRF"                      ,        8,      8,      45,     "RO",   0,      0,      0ull,   0ull},
25035         {"P1_BWB"                      ,        16,     1,      45,     "RO",   0,      0,      0ull,   0ull},
25036         {"P0_BWB"                      ,        17,     1,      45,     "RO",   0,      0,      0ull,   0ull},
25037         {"CRF"                         ,        18,     1,      45,     "RO",   0,      0,      0ull,   0ull},
25038         {"RESERVED_19_19"              ,        19,     1,      45,     "RAZ",  0,      0,      0ull,   0ull},
25039         {"GFU"                         ,        20,     1,      45,     "RO",   0,      0,      0ull,   0ull},
25040         {"IFU"                         ,        21,     1,      45,     "RO",   0,      0,      0ull,   0ull},
25041         {"CRQ"                         ,        22,     1,      45,     "RO",   0,      0,      0ull,   0ull},
25042         {"RESERVED_23_63"              ,        23,     41,     45,     "RAZ",  0,      0,      0ull,   0ull},
25043         {"SARB"                        ,        0,      1,      46,     "R/W",  0,      0,      1ull,   1ull},
25044         {"GXOR_ENA"                    ,        1,      1,      46,     "R/W",  0,      0,      0ull,   0ull},
25045         {"NXOR_ENA"                    ,        2,      1,      46,     "R/W",  0,      0,      0ull,   0ull},
25046         {"NRPL_ENA"                    ,        3,      1,      46,     "R/W",  0,      0,      0ull,   0ull},
25047         {"RESERVED_4_63"               ,        4,      60,     46,     "RAZ",  1,      1,      0,      0},
25048         {"DBELL"                       ,        0,      20,     47,     "R/W",  0,      1,      0ull,   0},
25049         {"RESERVED_20_63"              ,        20,     44,     47,     "RAZ",  1,      1,      0,      0},
25050         {"SIZE"                        ,        0,      9,      48,     "R/W",  0,      1,      3ull,   0},
25051         {"POOL"                        ,        9,      3,      48,     "R/W",  0,      1,      0ull,   0},
25052         {"DWBCNT"                      ,        12,     8,      48,     "R/W",  0,      1,      1ull,   0},
25053         {"RESERVED_20_63"              ,        20,     44,     48,     "RAZ",  1,      1,      0,      0},
25054         {"RESERVED_0_4"                ,        0,      5,      49,     "RAZ",  1,      1,      0,      0},
25055         {"RDPTR"                       ,        5,      31,     49,     "R/W",  0,      1,      0ull,   0},
25056         {"RESERVED_36_63"              ,        36,     28,     49,     "RAZ",  1,      1,      0,      0},
25057         {"CP2ECCENA"                   ,        0,      1,      50,     "R/W",  0,      0,      0ull,   0ull},
25058         {"CP2SBE"                      ,        1,      1,      50,     "R/W1C",        0,      0,      0ull,   0ull},
25059         {"CP2DBE"                      ,        2,      1,      50,     "R/W1C",        0,      0,      0ull,   0ull},
25060         {"CP2SBINA"                    ,        3,      1,      50,     "R/W",  0,      0,      0ull,   0ull},
25061         {"CP2DBINA"                    ,        4,      1,      50,     "R/W",  0,      0,      0ull,   0ull},
25062         {"CP2SYN"                      ,        5,      8,      50,     "RO",   0,      0,      0ull,   0ull},
25063         {"DTEECCENA"                   ,        13,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
25064         {"DTESBE"                      ,        14,     1,      50,     "R/W1C",        0,      0,      0ull,   0ull},
25065         {"DTEDBE"                      ,        15,     1,      50,     "R/W1C",        0,      0,      0ull,   0ull},
25066         {"DTESBINA"                    ,        16,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
25067         {"DTEDBINA"                    ,        17,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
25068         {"DTESYN"                      ,        18,     7,      50,     "RO",   0,      0,      0ull,   0ull},
25069         {"DTEPARENA"                   ,        25,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
25070         {"DTEPERR"                     ,        26,     1,      50,     "R/W1C",        0,      0,      0ull,   0ull},
25071         {"DTEPINA"                     ,        27,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
25072         {"CP2PARENA"                   ,        28,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
25073         {"CP2PERR"                     ,        29,     1,      50,     "R/W1C",        0,      0,      0ull,   0ull},
25074         {"CP2PINA"                     ,        30,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
25075         {"DBLOVF"                      ,        31,     1,      50,     "R/W1C",        0,      0,      0ull,   0ull},
25076         {"DBLINA"                      ,        32,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
25077         {"RESERVED_33_63"              ,        33,     31,     50,     "RAZ",  1,      1,      0,      0},
25078         {"ENA_P1"                      ,        0,      1,      51,     "R/W",  0,      0,      1ull,   1ull},
25079         {"ENA_P0"                      ,        1,      1,      51,     "R/W",  0,      0,      1ull,   1ull},
25080         {"RESERVED_2_2"                ,        2,      1,      51,     "RAZ",  1,      1,      0,      0},
25081         {"MTYPE"                       ,        3,      1,      51,     "R/W",  0,      0,      0ull,   0ull},
25082         {"SIL_LAT"                     ,        4,      2,      51,     "R/W",  0,      0,      0ull,   0ull},
25083         {"RW_DLY"                      ,        6,      4,      51,     "R/W",  0,      0,      1ull,   1ull},
25084         {"WR_DLY"                      ,        10,     4,      51,     "R/W",  0,      0,      2ull,   2ull},
25085         {"FPRCH"                       ,        14,     2,      51,     "R/W",  0,      0,      0ull,   0ull},
25086         {"BPRCH"                       ,        16,     2,      51,     "R/W",  0,      0,      0ull,   0ull},
25087         {"BLEN"                        ,        18,     1,      51,     "R/W",  0,      0,      0ull,   0ull},
25088         {"PBUNK"                       ,        19,     3,      51,     "R/W",  0,      0,      2ull,   2ull},
25089         {"R2R_PBUNK"                   ,        22,     1,      51,     "R/W",  0,      0,      1ull,   1ull},
25090         {"INIT_P1"                     ,        23,     1,      51,     "R/W",  0,      0,      0ull,   0ull},
25091         {"INIT_P0"                     ,        24,     1,      51,     "R/W",  0,      0,      0ull,   0ull},
25092         {"BUNK_INIT"                   ,        25,     2,      51,     "R/W",  0,      0,      3ull,   3ull},
25093         {"LPP_ENA"                     ,        27,     1,      51,     "R/W",  0,      0,      0ull,   0ull},
25094         {"CLKDIV"                      ,        28,     2,      51,     "R/W",  0,      0,      0ull,   0ull},
25095         {"RLDCK_RST"                   ,        30,     1,      51,     "R/W",  0,      0,      0ull,   0ull},
25096         {"RLDQCK90_RST"                ,        31,     1,      51,     "R/W",  0,      0,      0ull,   0ull},
25097         {"RESERVED_32_63"              ,        32,     32,     51,     "RAZ",  1,      1,      0,      0},
25098         {"REF_INT"                     ,        0,      4,      52,     "R/W",  0,      0,      3ull,   3ull},
25099         {"TSKW"                        ,        4,      2,      52,     "R/W",  0,      0,      0ull,   0ull},
25100         {"RESERVED_6_7"                ,        6,      2,      52,     "RAZ",  0,      0,      0ull,   0ull},
25101         {"TRL"                         ,        8,      4,      52,     "R/W",  0,      0,      6ull,   6ull},
25102         {"TWL"                         ,        12,     4,      52,     "R/W",  0,      0,      7ull,   7ull},
25103         {"TRC"                         ,        16,     4,      52,     "R/W",  0,      0,      6ull,   6ull},
25104         {"TMRSC"                       ,        20,     3,      52,     "R/W",  0,      0,      6ull,   6ull},
25105         {"MRS_ENA"                     ,        23,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
25106         {"AREF_ENA"                    ,        24,     1,      52,     "R/W",  0,      0,      0ull,   0ull},
25107         {"REF_INTLO"                   ,        25,     9,      52,     "R/W",  0,      0,      0ull,   0ull},
25108         {"RESERVED_34_63"              ,        34,     30,     52,     "RAZ",  1,      1,      0,      0},
25109         {"FCRAM2P"                     ,        0,      1,      53,     "R/W",  0,      0,      0ull,   0ull},
25110         {"MAXBNK"                      ,        1,      1,      53,     "R/W",  0,      0,      1ull,   1ull},
25111         {"UA_START"                    ,        2,      2,      53,     "R/W",  0,      0,      1ull,   1ull},
25112         {"REFSHORT"                    ,        4,      1,      53,     "R/W",  0,      0,      0ull,   0ull},
25113         {"TRFC"                        ,        5,      5,      53,     "R/W",  0,      0,      9ull,   9ull},
25114         {"SILRST"                      ,        10,     1,      53,     "R/W",  0,      0,      0ull,   0ull},
25115         {"DTECLKDIS"                   ,        11,     1,      53,     "R/W",  0,      0,      0ull,   0ull},
25116         {"RESERVED_12_63"              ,        12,     52,     53,     "RAZ",  1,      1,      0,      0},
25117         {"MADDR"                       ,        0,      24,     54,     "RO",   0,      0,      0ull,   0ull},
25118         {"BNUM"                        ,        24,     3,      54,     "RO",   0,      0,      0ull,   0ull},
25119         {"PNUM"                        ,        27,     1,      54,     "RO",   0,      0,      0ull,   0ull},
25120         {"FSRC"                        ,        28,     2,      54,     "RO",   0,      0,      0ull,   0ull},
25121         {"FDST"                        ,        30,     9,      54,     "RO",   0,      0,      0ull,   0ull},
25122         {"RESERVED_39_63"              ,        39,     25,     54,     "RAZ",  1,      1,      0,      0},
25123         {"MRS"                         ,        0,      15,     55,     "R/W",  0,      0,      66ull,  66ull},
25124         {"RESERVED_15_15"              ,        15,     1,      55,     "RAZ",  1,      1,      0,      0},
25125         {"EMRS"                        ,        16,     15,     55,     "R/W",  0,      0,      64ull,  64ull},
25126         {"RESERVED_31_31"              ,        31,     1,      55,     "RAZ",  1,      1,      0,      0},
25127         {"EMRS2"                       ,        32,     15,     55,     "R/W",  0,      0,      0ull,   0ull},
25128         {"RESERVED_47_63"              ,        47,     17,     55,     "RAZ",  1,      1,      0,      0},
25129         {"MRSDAT"                      ,        0,      23,     56,     "R/W",  0,      0,      2ull,   2ull},
25130         {"RESERVED_23_63"              ,        23,     41,     56,     "RAZ",  1,      1,      0,      0},
25131         {"IMODE"                       ,        0,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
25132         {"QMODE"                       ,        1,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
25133         {"PMODE"                       ,        2,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
25134         {"DTMODE"                      ,        3,      1,      57,     "R/W",  0,      0,      1ull,   1ull},
25135         {"DCMODE"                      ,        4,      1,      57,     "R/W",  0,      0,      0ull,   0ull},
25136         {"SBDLCK"                      ,        5,      1,      57,     "R/W",  0,      0,      0ull,   0ull},
25137         {"SBDNUM"                      ,        6,      5,      57,     "R/W",  0,      0,      0ull,   0ull},
25138         {"RESERVED_11_63"              ,        11,     53,     57,     "RAZ",  1,      1,      0,      0},
25139         {"PCTL"                        ,        0,      5,      58,     "R/W",  0,      1,      0ull,   0},
25140         {"RESERVED_5_7"                ,        5,      3,      58,     "RAZ",  0,      1,      0ull,   0},
25141         {"NCTL"                        ,        8,      4,      58,     "R/W",  0,      1,      0ull,   0},
25142         {"RESERVED_12_15"              ,        12,     4,      58,     "RAZ",  0,      1,      0ull,   0},
25143         {"ENABLE"                      ,        16,     1,      58,     "R/W",  0,      1,      0ull,   0},
25144         {"RESERVED_17_63"              ,        17,     47,     58,     "RAZ",  0,      1,      0ull,   0},
25145         {"SBD0"                        ,        0,      64,     59,     "RO",   1,      1,      0,      0},
25146         {"SBD1"                        ,        0,      64,     60,     "RO",   1,      1,      0,      0},
25147         {"SBD2"                        ,        0,      64,     61,     "RO",   1,      1,      0,      0},
25148         {"SBD3"                        ,        0,      64,     62,     "RO",   1,      1,      0,      0},
25149         {"FDR"                         ,        0,      1,      63,     "RO",   0,      0,      0ull,   0ull},
25150         {"FFR"                         ,        1,      1,      63,     "RO",   0,      0,      0ull,   0ull},
25151         {"FPF1"                        ,        2,      1,      63,     "RO",   0,      0,      0ull,   0ull},
25152         {"FPF0"                        ,        3,      1,      63,     "RO",   0,      0,      0ull,   0ull},
25153         {"FRD"                         ,        4,      1,      63,     "RO",   0,      0,      0ull,   0ull},
25154         {"RESERVED_5_63"               ,        5,      59,     63,     "RAZ",  1,      1,      0,      0},
25155         {"MEM0_ERR"                    ,        0,      7,      64,     "R/W",  0,      0,      0ull,   0ull},
25156         {"MEM1_ERR"                    ,        7,      7,      64,     "R/W",  0,      0,      0ull,   0ull},
25157         {"ENB"                         ,        14,     1,      64,     "R/W",  0,      0,      0ull,   0ull},
25158         {"USE_STT"                     ,        15,     1,      64,     "R/W",  0,      0,      0ull,   0ull},
25159         {"USE_LDT"                     ,        16,     1,      64,     "R/W",  0,      0,      0ull,   0ull},
25160         {"RESET"                       ,        17,     1,      64,     "R/W",  0,      0,      0ull,   0ull},
25161         {"RESERVED_18_63"              ,        18,     46,     64,     "RAZ",  1,      1,      0,      0},
25162         {"FPF_RD"                      ,        0,      11,     65,     "R/W",  0,      0,      64ull,  0ull},
25163         {"FPF_WR"                      ,        11,     11,     65,     "R/W",  0,      0,      196ull, 0ull},
25164         {"RESERVED_22_63"              ,        22,     42,     65,     "RAZ",  1,      1,      0,      0},
25165         {"FPF_SIZ"                     ,        0,      11,     66,     "R/W",  0,      0,      256ull, 0ull},
25166         {"RESERVED_11_63"              ,        11,     53,     66,     "RAZ",  1,      1,      0,      0},
25167         {"FPF_RD"                      ,        0,      12,     67,     "R/W",  0,      0,      64ull,  0ull},
25168         {"FPF_WR"                      ,        12,     12,     67,     "R/W",  0,      0,      196ull, 0ull},
25169         {"RESERVED_24_63"              ,        24,     40,     67,     "RAZ",  1,      1,      0,      0},
25170         {"FPF_SIZ"                     ,        0,      12,     68,     "R/W",  0,      0,      256ull, 0ull},
25171         {"RESERVED_12_63"              ,        12,     52,     68,     "RAZ",  1,      1,      0,      0},
25172         {"FED0_SBE"                    ,        0,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25173         {"FED0_DBE"                    ,        1,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25174         {"FED1_SBE"                    ,        2,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25175         {"FED1_DBE"                    ,        3,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25176         {"Q0_UND"                      ,        4,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25177         {"Q0_COFF"                     ,        5,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25178         {"Q0_PERR"                     ,        6,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25179         {"Q1_UND"                      ,        7,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25180         {"Q1_COFF"                     ,        8,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25181         {"Q1_PERR"                     ,        9,      1,      69,     "R/W",  0,      0,      0ull,   0ull},
25182         {"Q2_UND"                      ,        10,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25183         {"Q2_COFF"                     ,        11,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25184         {"Q2_PERR"                     ,        12,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25185         {"Q3_UND"                      ,        13,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25186         {"Q3_COFF"                     ,        14,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25187         {"Q3_PERR"                     ,        15,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25188         {"Q4_UND"                      ,        16,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25189         {"Q4_COFF"                     ,        17,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25190         {"Q4_PERR"                     ,        18,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25191         {"Q5_UND"                      ,        19,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25192         {"Q5_COFF"                     ,        20,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25193         {"Q5_PERR"                     ,        21,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25194         {"Q6_UND"                      ,        22,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25195         {"Q6_COFF"                     ,        23,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25196         {"Q6_PERR"                     ,        24,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25197         {"Q7_UND"                      ,        25,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25198         {"Q7_COFF"                     ,        26,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25199         {"Q7_PERR"                     ,        27,     1,      69,     "R/W",  0,      0,      0ull,   0ull},
25200         {"RESERVED_28_63"              ,        28,     36,     69,     "RAZ",  1,      1,      0,      0},
25201         {"FED0_SBE"                    ,        0,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25202         {"FED0_DBE"                    ,        1,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25203         {"FED1_SBE"                    ,        2,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25204         {"FED1_DBE"                    ,        3,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25205         {"Q0_UND"                      ,        4,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25206         {"Q0_COFF"                     ,        5,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25207         {"Q0_PERR"                     ,        6,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25208         {"Q1_UND"                      ,        7,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25209         {"Q1_COFF"                     ,        8,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25210         {"Q1_PERR"                     ,        9,      1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25211         {"Q2_UND"                      ,        10,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25212         {"Q2_COFF"                     ,        11,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25213         {"Q2_PERR"                     ,        12,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25214         {"Q3_UND"                      ,        13,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25215         {"Q3_COFF"                     ,        14,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25216         {"Q3_PERR"                     ,        15,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25217         {"Q4_UND"                      ,        16,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25218         {"Q4_COFF"                     ,        17,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25219         {"Q4_PERR"                     ,        18,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25220         {"Q5_UND"                      ,        19,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25221         {"Q5_COFF"                     ,        20,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25222         {"Q5_PERR"                     ,        21,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25223         {"Q6_UND"                      ,        22,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25224         {"Q6_COFF"                     ,        23,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25225         {"Q6_PERR"                     ,        24,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25226         {"Q7_UND"                      ,        25,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25227         {"Q7_COFF"                     ,        26,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25228         {"Q7_PERR"                     ,        27,     1,      70,     "R/W1C",        0,      0,      0ull,   0ull},
25229         {"RESERVED_28_63"              ,        28,     36,     70,     "RAZ",  1,      1,      0,      0},
25230         {"QUE_SIZ"                     ,        0,      29,     71,     "RO",   0,      0,      0ull,   0ull},
25231         {"RESERVED_29_63"              ,        29,     35,     71,     "RAZ",  1,      1,      0,      0},
25232         {"PG_NUM"                      ,        0,      25,     72,     "RO",   0,      1,      0ull,   0},
25233         {"RESERVED_25_63"              ,        25,     39,     72,     "RAZ",  1,      1,      0,      0},
25234         {"ACT_INDX"                    ,        0,      26,     73,     "RO",   0,      1,      0ull,   0},
25235         {"ACT_QUE"                     ,        26,     3,      73,     "RO",   0,      1,      0ull,   0},
25236         {"RESERVED_29_63"              ,        29,     35,     73,     "RAZ",  0,      0,      0ull,   7ull},
25237         {"EXP_INDX"                    ,        0,      26,     74,     "RO",   0,      1,      0ull,   0},
25238         {"EXP_QUE"                     ,        26,     3,      74,     "RO",   0,      1,      0ull,   0},
25239         {"RESERVED_29_63"              ,        29,     35,     74,     "RAZ",  0,      0,      0ull,   7ull},
25240         {"CTL"                         ,        0,      16,     75,     "R/W",  1,      0,      0,      0ull},
25241         {"RESERVED_16_63"              ,        16,     48,     75,     "RAZ",  1,      1,      0,      0},
25242         {"STATUS"                      ,        0,      32,     76,     "RO",   0,      0,      0ull,   0ull},
25243         {"RESERVED_32_63"              ,        32,     32,     76,     "RAZ",  1,      1,      0,      0},
25244         {"OUT_COL"                     ,        0,      1,      77,     "R/W1C",        0,      0,      0ull,   0ull},
25245         {"NCB_OVR"                     ,        1,      1,      77,     "R/W1C",        0,      0,      0ull,   0ull},
25246         {"OUT_OVR"                     ,        2,      16,     77,     "R/W1C",        0,      0,      0ull,   0ull},
25247         {"RESERVED_18_21"              ,        18,     4,      77,     "RAZ",  0,      0,      0ull,   0ull},
25248         {"LOSTSTAT"                    ,        22,     4,      77,     "R/W1C",        0,      0,      0ull,   0ull},
25249         {"STATOVR"                     ,        26,     1,      77,     "R/W1C",        0,      0,      0ull,   0ull},
25250         {"INB_NXA"                     ,        27,     4,      77,     "R/W1C",        0,      0,      0ull,   0ull},
25251         {"RESERVED_31_63"              ,        31,     33,     77,     "RAZ",  1,      1,      0,      0},
25252         {"STATUS"                      ,        0,      17,     78,     "RO",   0,      0,      0ull,   0ull},
25253         {"RESERVED_17_63"              ,        17,     47,     78,     "RAZ",  1,      1,      0,      0},
25254         {"TYPE"                        ,        0,      1,      79,     "RO",   1,      1,      0,      0},
25255         {"EN"                          ,        1,      1,      79,     "RO",   1,      1,      0,      0},
25256         {"RESERVED_2_63"               ,        2,      62,     79,     "RAZ",  1,      1,      0,      0},
25257         {"PRT"                         ,        0,      6,      80,     "RO",   0,      1,      0ull,   0},
25258         {"RESERVED_6_63"               ,        6,      58,     80,     "RAZ",  1,      1,      0,      0},
25259         {"EN"                          ,        0,      1,      81,     "R/W",  0,      1,      0ull,   0},
25260         {"SPEED"                       ,        1,      1,      81,     "R/W",  0,      1,      1ull,   0},
25261         {"DUPLEX"                      ,        2,      1,      81,     "R/W",  0,      1,      1ull,   0},
25262         {"SLOTTIME"                    ,        3,      1,      81,     "R/W",  0,      1,      1ull,   0},
25263         {"RESERVED_4_63"               ,        4,      60,     81,     "RAZ",  1,      1,      0,      0},
25264         {"ADR"                         ,        0,      64,     82,     "R/W",  0,      1,      0ull,   0},
25265         {"ADR"                         ,        0,      64,     83,     "R/W",  0,      1,      0ull,   0},
25266         {"ADR"                         ,        0,      64,     84,     "R/W",  0,      1,      0ull,   0},
25267         {"ADR"                         ,        0,      64,     85,     "R/W",  0,      1,      0ull,   0},
25268         {"ADR"                         ,        0,      64,     86,     "R/W",  0,      1,      0ull,   0},
25269         {"ADR"                         ,        0,      64,     87,     "R/W",  0,      1,      0ull,   0},
25270         {"EN"                          ,        0,      8,      88,     "R/W",  0,      1,      0ull,   0},
25271         {"RESERVED_8_63"               ,        8,      56,     88,     "RAZ",  1,      1,      0,      0},
25272         {"BCST"                        ,        0,      1,      89,     "R/W",  0,      1,      1ull,   0},
25273         {"MCST"                        ,        1,      2,      89,     "R/W",  0,      1,      0ull,   0},
25274         {"CAM_MODE"                    ,        3,      1,      89,     "R/W",  0,      1,      0ull,   0},
25275         {"RESERVED_4_63"               ,        4,      60,     89,     "RAZ",  1,      1,      0,      0},
25276         {"CNT"                         ,        0,      5,      90,     "R/W",  0,      0,      24ull,  24ull},
25277         {"RESERVED_5_63"               ,        5,      59,     90,     "RAZ",  1,      1,      0,      0},
25278         {"MINERR"                      ,        0,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25279         {"CAREXT"                      ,        1,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25280         {"MAXERR"                      ,        2,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25281         {"JABBER"                      ,        3,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25282         {"FCSERR"                      ,        4,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25283         {"ALNERR"                      ,        5,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25284         {"LENERR"                      ,        6,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25285         {"RCVERR"                      ,        7,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25286         {"SKPERR"                      ,        8,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25287         {"NIBERR"                      ,        9,      1,      91,     "R/W",  0,      0,      1ull,   1ull},
25288         {"RESERVED_10_63"              ,        10,     54,     91,     "RAZ",  1,      1,      0,      0},
25289         {"PRE_CHK"                     ,        0,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
25290         {"PRE_STRP"                    ,        1,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
25291         {"CTL_DRP"                     ,        2,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
25292         {"CTL_BCK"                     ,        3,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
25293         {"CTL_MCST"                    ,        4,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
25294         {"CTL_SMAC"                    ,        5,      1,      92,     "R/W",  0,      0,      1ull,   1ull},
25295         {"PRE_FREE"                    ,        6,      1,      92,     "R/W",  0,      0,      0ull,   0ull},
25296         {"VLAN_LEN"                    ,        7,      1,      92,     "R/W",  0,      0,      0ull,   0ull},
25297         {"PAD_LEN"                     ,        8,      1,      92,     "R/W",  0,      0,      0ull,   0ull},
25298         {"RESERVED_9_63"               ,        9,      55,     92,     "RAZ",  1,      1,      0,      0},
25299         {"LEN"                         ,        0,      16,     93,     "R/W",  0,      0,      1536ull,        1536ull},
25300         {"RESERVED_16_63"              ,        16,     48,     93,     "RAZ",  1,      1,      0,      0},
25301         {"LEN"                         ,        0,      16,     94,     "R/W",  0,      0,      64ull,  64ull},
25302         {"RESERVED_16_63"              ,        16,     48,     94,     "RAZ",  1,      1,      0,      0},
25303         {"IFG"                         ,        0,      4,      95,     "R/W",  0,      0,      12ull,  12ull},
25304         {"RESERVED_4_63"               ,        4,      60,     95,     "RAZ",  1,      1,      0,      0},
25305         {"MINERR"                      ,        0,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25306         {"CAREXT"                      ,        1,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25307         {"MAXERR"                      ,        2,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25308         {"JABBER"                      ,        3,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25309         {"FCSERR"                      ,        4,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25310         {"ALNERR"                      ,        5,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25311         {"LENERR"                      ,        6,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25312         {"RCVERR"                      ,        7,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25313         {"SKPERR"                      ,        8,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25314         {"NIBERR"                      ,        9,      1,      96,     "R/W",  0,      0,      0ull,   0ull},
25315         {"OVRERR"                      ,        10,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25316         {"PCTERR"                      ,        11,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25317         {"RSVERR"                      ,        12,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25318         {"FALERR"                      ,        13,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25319         {"COLDET"                      ,        14,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25320         {"IFGERR"                      ,        15,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25321         {"PHY_LINK"                    ,        16,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25322         {"PHY_SPD"                     ,        17,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25323         {"PHY_DUPX"                    ,        18,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25324         {"PAUSE_DRP"                   ,        19,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
25325         {"RESERVED_20_63"              ,        20,     44,     96,     "RAZ",  1,      1,      0,      0},
25326         {"MINERR"                      ,        0,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25327         {"CAREXT"                      ,        1,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25328         {"MAXERR"                      ,        2,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25329         {"JABBER"                      ,        3,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25330         {"FCSERR"                      ,        4,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25331         {"ALNERR"                      ,        5,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25332         {"LENERR"                      ,        6,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25333         {"RCVERR"                      ,        7,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25334         {"SKPERR"                      ,        8,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25335         {"NIBERR"                      ,        9,      1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25336         {"OVRERR"                      ,        10,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25337         {"PCTERR"                      ,        11,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25338         {"RSVERR"                      ,        12,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25339         {"FALERR"                      ,        13,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25340         {"COLDET"                      ,        14,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25341         {"IFGERR"                      ,        15,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25342         {"PHY_LINK"                    ,        16,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25343         {"PHY_SPD"                     ,        17,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25344         {"PHY_DUPX"                    ,        18,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25345         {"PAUSE_DRP"                   ,        19,     1,      97,     "R/W1C",        0,      0,      0ull,   0ull},
25346         {"RESERVED_20_63"              ,        20,     44,     97,     "RAZ",  1,      1,      0,      0},
25347         {"CNT"                         ,        0,      16,     98,     "R/W",  0,      0,      10240ull,       10240ull},
25348         {"RESERVED_16_63"              ,        16,     48,     98,     "RAZ",  1,      1,      0,      0},
25349         {"STATUS"                      ,        0,      16,     99,     "R/W1C",        0,      1,      0ull,   0},
25350         {"RESERVED_16_63"              ,        16,     48,     99,     "RAZ",  1,      1,      0,      0},
25351         {"STATUS"                      ,        0,      1,      100,    "RO",   0,      1,      0ull,   0},
25352         {"SPEED"                       ,        1,      2,      100,    "RO",   0,      1,      0ull,   0},
25353         {"DUPLEX"                      ,        3,      1,      100,    "RO",   0,      1,      0ull,   0},
25354         {"RESERVED_4_63"               ,        4,      60,     100,    "RAZ",  1,      1,      0,      0},
25355         {"RD_CLR"                      ,        0,      1,      101,    "R/W",  0,      0,      0ull,   0ull},
25356         {"RESERVED_1_63"               ,        1,      63,     101,    "RAZ",  1,      1,      0,      0},
25357         {"CNT"                         ,        0,      48,     102,    "RC/W", 0,      1,      0ull,   0},
25358         {"RESERVED_48_63"              ,        48,     16,     102,    "RAZ",  1,      1,      0,      0},
25359         {"CNT"                         ,        0,      48,     103,    "RC/W", 0,      1,      0ull,   0},
25360         {"RESERVED_48_63"              ,        48,     16,     103,    "RAZ",  1,      1,      0,      0},
25361         {"CNT"                         ,        0,      48,     104,    "RC/W", 0,      1,      0ull,   0},
25362         {"RESERVED_48_63"              ,        48,     16,     104,    "RAZ",  1,      1,      0,      0},
25363         {"CNT"                         ,        0,      48,     105,    "RC/W", 0,      1,      0ull,   0},
25364         {"RESERVED_48_63"              ,        48,     16,     105,    "RAZ",  1,      1,      0,      0},
25365         {"CNT"                         ,        0,      32,     106,    "RC/W", 0,      1,      0ull,   0},
25366         {"RESERVED_32_63"              ,        32,     32,     106,    "RAZ",  1,      1,      0,      0},
25367         {"CNT"                         ,        0,      32,     107,    "RC/W", 0,      1,      0ull,   0},
25368         {"RESERVED_32_63"              ,        32,     32,     107,    "RAZ",  1,      1,      0,      0},
25369         {"CNT"                         ,        0,      32,     108,    "RC/W", 0,      1,      0ull,   0},
25370         {"RESERVED_32_63"              ,        32,     32,     108,    "RAZ",  1,      1,      0,      0},
25371         {"CNT"                         ,        0,      32,     109,    "RC/W", 0,      1,      0ull,   0},
25372         {"RESERVED_32_63"              ,        32,     32,     109,    "RAZ",  1,      1,      0,      0},
25373         {"CNT"                         ,        0,      32,     110,    "RC/W", 0,      1,      0ull,   0},
25374         {"RESERVED_32_63"              ,        32,     32,     110,    "RAZ",  1,      1,      0,      0},
25375         {"LEN"                         ,        0,      7,      111,    "R/W",  0,      0,      0ull,   0ull},
25376         {"RESERVED_7_7"                ,        7,      1,      111,    "RAZ",  1,      1,      0,      0},
25377         {"FCSSEL"                      ,        8,      1,      111,    "R/W",  0,      0,      0ull,   0ull},
25378         {"RESERVED_9_63"               ,        9,      55,     111,    "RAZ",  1,      1,      0,      0},
25379         {"MARK"                        ,        0,      6,      112,    "R/W",  1,      1,      0,      0},
25380         {"RESERVED_6_63"               ,        6,      58,     112,    "RAZ",  1,      1,      0,      0},
25381         {"MARK"                        ,        0,      6,      113,    "R/W",  0,      0,      16ull,  16ull},
25382         {"RESERVED_6_63"               ,        6,      58,     113,    "RAZ",  1,      1,      0,      0},
25383         {"MARK"                        ,        0,      9,      114,    "R/W",  1,      1,      0,      0},
25384         {"RESERVED_9_63"               ,        9,      55,     114,    "RAZ",  1,      1,      0,      0},
25385         {"EN"                          ,        0,      16,     115,    "R/W",  0,      0,      0ull,   0ull},
25386         {"RESERVED_16_63"              ,        16,     48,     115,    "RAZ",  1,      1,      0,      0},
25387         {"DPRT"                        ,        0,      4,      116,    "R/W",  0,      0,      0ull,   0ull},
25388         {"RESERVED_4_63"               ,        4,      60,     116,    "RAZ",  1,      1,      0,      0},
25389         {"COMMIT"                      ,        0,      16,     117,    "RO",   0,      0,      0ull,   0ull},
25390         {"DROP"                        ,        16,     16,     117,    "RO",   0,      0,      0ull,   0ull},
25391         {"RESERVED_32_63"              ,        32,     32,     117,    "RAZ",  1,      1,      0,      0},
25392         {"PRTS"                        ,        0,      3,      118,    "R/W",  0,      0,      4ull,   4ull},
25393         {"RESERVED_3_63"               ,        3,      61,     118,    "RAZ",  1,      1,      0,      0},
25394         {"SMAC"                        ,        0,      48,     119,    "R/W",  0,      1,      0ull,   0},
25395         {"RESERVED_48_63"              ,        48,     16,     119,    "RAZ",  1,      1,      0,      0},
25396         {"CNT"                         ,        0,      16,     120,    "R/W1C",        0,      0,      0ull,   0ull},
25397         {"BP"                          ,        16,     1,      120,    "RO",   0,      0,      0ull,   0ull},
25398         {"RESERVED_17_63"              ,        17,     47,     120,    "RAZ",  1,      1,      0,      0},
25399         {"PREAMBLE"                    ,        0,      1,      121,    "R/W",  0,      0,      1ull,   1ull},
25400         {"PAD"                         ,        1,      1,      121,    "R/W",  0,      0,      1ull,   1ull},
25401         {"FCS"                         ,        2,      1,      121,    "R/W",  0,      0,      1ull,   1ull},
25402         {"FORCE_FCS"                   ,        3,      1,      121,    "R/W",  0,      0,      1ull,   1ull},
25403         {"RESERVED_4_63"               ,        4,      60,     121,    "RAZ",  1,      1,      0,      0},
25404         {"BURST"                       ,        0,      16,     122,    "R/W",  0,      0,      8192ull,        8192ull},
25405         {"RESERVED_16_63"              ,        16,     48,     122,    "RAZ",  1,      1,      0,      0},
25406         {"CLK_CNT"                     ,        0,      6,      123,    "R/W",  0,      0,      1ull,   1ull},
25407         {"RESERVED_6_63"               ,        6,      58,     123,    "RAZ",  1,      1,      0,      0},
25408         {"XSCOL_EN"                    ,        0,      1,      124,    "R/W",  0,      0,      1ull,   1ull},
25409         {"XSDEF_EN"                    ,        1,      1,      124,    "R/W",  0,      0,      1ull,   1ull},
25410         {"RESERVED_2_63"               ,        2,      62,     124,    "RAZ",  1,      1,      0,      0},
25411         {"MIN_SIZE"                    ,        0,      8,      125,    "R/W",  0,      0,      59ull,  59ull},
25412         {"RESERVED_8_63"               ,        8,      56,     125,    "RAZ",  1,      1,      0,      0},
25413         {"INTERVAL"                    ,        0,      16,     126,    "R/W",  0,      1,      16ull,  0},
25414         {"RESERVED_16_63"              ,        16,     48,     126,    "RAZ",  1,      1,      0,      0},
25415         {"TIME"                        ,        0,      16,     127,    "R/W",  0,      1,      96ull,  0},
25416         {"RESERVED_16_63"              ,        16,     48,     127,    "RAZ",  1,      1,      0,      0},
25417         {"TIME"                        ,        0,      16,     128,    "RO",   1,      1,      0,      0},
25418         {"RESERVED_16_63"              ,        16,     48,     128,    "RAZ",  1,      1,      0,      0},
25419         {"SEND"                        ,        0,      1,      129,    "R/W",  0,      0,      1ull,   1ull},
25420         {"RESERVED_1_63"               ,        1,      63,     129,    "RAZ",  1,      1,      0,      0},
25421         {"SLOT"                        ,        0,      10,     130,    "R/W",  0,      0,      512ull, 512ull},
25422         {"RESERVED_10_63"              ,        10,     54,     130,    "RAZ",  1,      1,      0,      0},
25423         {"TIME"                        ,        0,      16,     131,    "R/W",  0,      1,      0ull,   0},
25424         {"RESERVED_16_63"              ,        16,     48,     131,    "RAZ",  1,      1,      0,      0},
25425         {"XSCOL"                       ,        0,      32,     132,    "RC/W", 0,      1,      0ull,   0},
25426         {"XSDEF"                       ,        32,     32,     132,    "RC/W", 0,      1,      0ull,   0},
25427         {"MCOL"                        ,        0,      32,     133,    "RC/W", 0,      1,      0ull,   0},
25428         {"SCOL"                        ,        32,     32,     133,    "RC/W", 0,      1,      0ull,   0},
25429         {"OCTS"                        ,        0,      48,     134,    "RC/W", 0,      1,      0ull,   0},
25430         {"RESERVED_48_63"              ,        48,     16,     134,    "RAZ",  1,      1,      0,      0},
25431         {"PKTS"                        ,        0,      32,     135,    "RC/W", 0,      1,      0ull,   0},
25432         {"RESERVED_32_63"              ,        32,     32,     135,    "RAZ",  1,      1,      0,      0},
25433         {"HIST0"                       ,        0,      32,     136,    "RC/W", 0,      1,      0ull,   0},
25434         {"HIST1"                       ,        32,     32,     136,    "RC/W", 0,      1,      0ull,   0},
25435         {"HIST2"                       ,        0,      32,     137,    "RC/W", 0,      1,      0ull,   0},
25436         {"HIST3"                       ,        32,     32,     137,    "RC/W", 0,      1,      0ull,   0},
25437         {"HIST4"                       ,        0,      32,     138,    "RC/W", 0,      1,      0ull,   0},
25438         {"HIST5"                       ,        32,     32,     138,    "RC/W", 0,      1,      0ull,   0},
25439         {"HIST6"                       ,        0,      32,     139,    "RC/W", 0,      1,      0ull,   0},
25440         {"HIST7"                       ,        32,     32,     139,    "RC/W", 0,      1,      0ull,   0},
25441         {"BCST"                        ,        0,      32,     140,    "RC/W", 0,      1,      0ull,   0},
25442         {"MCST"                        ,        32,     32,     140,    "RC/W", 0,      1,      0ull,   0},
25443         {"CTL"                         ,        0,      32,     141,    "RC/W", 0,      1,      0ull,   0},
25444         {"UNDFLW"                      ,        32,     32,     141,    "RC/W", 0,      1,      0ull,   0},
25445         {"RD_CLR"                      ,        0,      1,      142,    "R/W",  0,      0,      0ull,   0ull},
25446         {"RESERVED_1_63"               ,        1,      63,     142,    "RAZ",  1,      1,      0,      0},
25447         {"CNT"                         ,        0,      9,      143,    "R/W",  0,      0,      32ull,  32ull},
25448         {"RESERVED_9_63"               ,        9,      55,     143,    "RAZ",  1,      1,      0,      0},
25449         {"BP"                          ,        0,      4,      144,    "RO",   0,      0,      0ull,   0ull},
25450         {"RESERVED_4_63"               ,        4,      60,     144,    "RAZ",  1,      1,      0,      0},
25451         {"LIMIT"                       ,        0,      5,      145,    "R/W",  0,      0,      16ull,  16ull},
25452         {"RESERVED_5_63"               ,        5,      59,     145,    "RAZ",  1,      1,      0,      0},
25453         {"CORRUPT"                     ,        0,      4,      146,    "R/W",  0,      0,      15ull,  15ull},
25454         {"RESERVED_4_63"               ,        4,      60,     146,    "RAZ",  1,      1,      0,      0},
25455         {"IFG1"                        ,        0,      4,      147,    "R/W",  0,      1,      8ull,   0},
25456         {"IFG2"                        ,        4,      4,      147,    "R/W",  0,      1,      4ull,   0},
25457         {"RESERVED_8_63"               ,        8,      56,     147,    "RAZ",  1,      1,      0,      0},
25458         {"PKO_NXA"                     ,        0,      1,      148,    "R/W",  0,      0,      0ull,   0ull},
25459         {"NCB_NXA"                     ,        1,      1,      148,    "R/W",  0,      0,      0ull,   0ull},
25460         {"UNDFLW"                      ,        2,      4,      148,    "R/W",  0,      0,      0ull,   0ull},
25461         {"RESERVED_6_7"                ,        6,      2,      148,    "RAZ",  0,      0,      0ull,   0ull},
25462         {"XSCOL"                       ,        8,      4,      148,    "R/W",  0,      0,      0ull,   0ull},
25463         {"XSDEF"                       ,        12,     4,      148,    "R/W",  0,      0,      0ull,   0ull},
25464         {"LATE_COL"                    ,        16,     4,      148,    "R/W",  0,      0,      0ull,   0ull},
25465         {"RESERVED_20_63"              ,        20,     44,     148,    "RAZ",  1,      1,      0,      0},
25466         {"PKO_NXA"                     ,        0,      1,      149,    "R/W1C",        0,      0,      0ull,   0ull},
25467         {"NCB_NXA"                     ,        1,      1,      149,    "R/W1C",        0,      0,      0ull,   0ull},
25468         {"UNDFLW"                      ,        2,      4,      149,    "R/W1C",        0,      0,      0ull,   0ull},
25469         {"RESERVED_6_7"                ,        6,      2,      149,    "RAZ",  0,      0,      0ull,   0ull},
25470         {"XSCOL"                       ,        8,      4,      149,    "R/W1C",        0,      0,      0ull,   0ull},
25471         {"XSDEF"                       ,        12,     4,      149,    "R/W1C",        0,      0,      0ull,   0ull},
25472         {"LATE_COL"                    ,        16,     4,      149,    "R/W1C",        0,      0,      0ull,   0ull},
25473         {"RESERVED_20_63"              ,        20,     44,     149,    "RAZ",  1,      1,      0,      0},
25474         {"JAM"                         ,        0,      8,      150,    "R/W",  0,      1,      238ull, 0},
25475         {"RESERVED_8_63"               ,        8,      56,     150,    "RAZ",  1,      1,      0,      0},
25476         {"LFSR"                        ,        0,      16,     151,    "R/W",  0,      1,      65535ull,       0},
25477         {"RESERVED_16_63"              ,        16,     48,     151,    "RAZ",  1,      1,      0,      0},
25478         {"IGN_FULL"                    ,        0,      4,      152,    "R/W",  0,      0,      0ull,   0ull},
25479         {"BP"                          ,        4,      4,      152,    "R/W",  0,      0,      0ull,   0ull},
25480         {"EN"                          ,        8,      4,      152,    "R/W",  0,      0,      0ull,   0ull},
25481         {"RESERVED_12_63"              ,        12,     52,     152,    "RAZ",  1,      1,      0,      0},
25482         {"DMAC"                        ,        0,      48,     153,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
25483         {"RESERVED_48_63"              ,        48,     16,     153,    "RAZ",  1,      1,      0,      0},
25484         {"TYPE"                        ,        0,      16,     154,    "R/W",  0,      0,      34824ull,       34824ull},
25485         {"RESERVED_16_63"              ,        16,     48,     154,    "RAZ",  1,      1,      0,      0},
25486         {"PRTS"                        ,        0,      5,      155,    "R/W",  0,      1,      1ull,   0},
25487         {"RESERVED_5_63"               ,        5,      59,     155,    "RAZ",  1,      1,      0,      0},
25488         {"CONT_PKT"                    ,        0,      1,      156,    "R/W",  0,      1,      0ull,   0},
25489         {"TPA_CLR"                     ,        1,      1,      156,    "R/W",  0,      1,      0ull,   0},
25490         {"RESERVED_2_63"               ,        2,      62,     156,    "RAZ",  0,      0,      0ull,   0ull},
25491         {"DRAIN"                       ,        0,      16,     157,    "R/W",  0,      0,      0ull,   0ull},
25492         {"RESERVED_16_63"              ,        16,     48,     157,    "RAZ",  1,      1,      0,      0},
25493         {"MAX1"                        ,        0,      8,      158,    "R/W",  0,      1,      8ull,   0},
25494         {"MAX2"                        ,        8,      8,      158,    "R/W",  0,      1,      4ull,   0},
25495         {"SLICE"                       ,        16,     7,      158,    "R/W",  0,      1,      0ull,   0},
25496         {"RESERVED_23_63"              ,        23,     41,     158,    "RAZ",  1,      1,      0,      0},
25497         {"ROUND"                       ,        0,      16,     159,    "R/W",  0,      1,      0ull,   0},
25498         {"RESERVED_16_63"              ,        16,     48,     159,    "RAZ",  1,      1,      0,      0},
25499         {"THRESH"                      ,        0,      6,      160,    "R/W",  0,      1,      4ull,   0},
25500         {"RESERVED_6_63"               ,        6,      58,     160,    "RAZ",  1,      1,      0,      0},
25501         {"TX_OE"                       ,        0,      1,      161,    "R/W",  0,      0,      0ull,   0ull},
25502         {"RX_XOR"                      ,        1,      1,      161,    "R/W",  0,      0,      0ull,   0ull},
25503         {"INT_EN"                      ,        2,      1,      161,    "R/W",  0,      0,      0ull,   0ull},
25504         {"INT_TYPE"                    ,        3,      1,      161,    "R/W",  0,      0,      0ull,   0ull},
25505         {"FIL_CNT"                     ,        4,      4,      161,    "R/W",  0,      0,      0ull,   0ull},
25506         {"FIL_SEL"                     ,        8,      4,      161,    "R/W",  0,      0,      0ull,   0ull},
25507         {"RESERVED_12_63"              ,        12,     52,     161,    "RAZ",  1,      1,      0,      0},
25508         {"TYPE"                        ,        0,      16,     162,    "WO",   0,      0,      0ull,   0ull},
25509         {"RESERVED_16_63"              ,        16,     48,     162,    "RAZ",  1,      1,      0,      0},
25510         {"DAT"                         ,        0,      16,     163,    "RO",   0,      0,      0ull,   0ull},
25511         {"RESERVED_16_63"              ,        16,     48,     163,    "RAZ",  1,      1,      0,      0},
25512         {"CLR"                         ,        0,      16,     164,    "WO",   0,      0,      0ull,   0ull},
25513         {"RESERVED_16_63"              ,        16,     48,     164,    "RAZ",  1,      1,      0,      0},
25514         {"SET"                         ,        0,      16,     165,    "WO",   0,      0,      0ull,   0ull},
25515         {"RESERVED_16_63"              ,        16,     48,     165,    "RAZ",  1,      1,      0,      0},
25516         {"ICD"                         ,        0,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25517         {"IBD"                         ,        1,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25518         {"ICRP1"                       ,        2,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25519         {"ICRP0"                       ,        3,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25520         {"ICRN1"                       ,        4,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25521         {"ICRN0"                       ,        5,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25522         {"IBRQ1"                       ,        6,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25523         {"IBRQ0"                       ,        7,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25524         {"ICNRT"                       ,        8,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25525         {"IBR1"                        ,        9,      1,      166,    "RO",   0,      0,      0ull,   0ull},
25526         {"IBR0"                        ,        10,     1,      166,    "RO",   0,      0,      0ull,   0ull},
25527         {"IBDR1"                       ,        11,     1,      166,    "RO",   0,      0,      0ull,   0ull},
25528         {"IBDR0"                       ,        12,     1,      166,    "RO",   0,      0,      0ull,   0ull},
25529         {"ICNR0"                       ,        13,     1,      166,    "RO",   0,      0,      0ull,   0ull},
25530         {"ICNR1"                       ,        14,     1,      166,    "RO",   0,      0,      0ull,   0ull},
25531         {"ICR1"                        ,        15,     1,      166,    "RO",   0,      0,      0ull,   0ull},
25532         {"ICR0"                        ,        16,     1,      166,    "RO",   0,      0,      0ull,   0ull},
25533         {"ICNRCB"                      ,        17,     1,      166,    "RO",   0,      0,      0ull,   0ull},
25534         {"RESERVED_18_63"              ,        18,     46,     166,    "RAZ",  1,      1,      0,      0},
25535         {"FAU_END"                     ,        0,      1,      167,    "R/W",  0,      0,      0ull,   0ull},
25536         {"DWB_ENB"                     ,        1,      1,      167,    "R/W",  0,      0,      1ull,   1ull},
25537         {"PKO_ENB"                     ,        2,      1,      167,    "R/W",  0,      0,      0ull,   0ull},
25538         {"INB_MAT"                     ,        3,      1,      167,    "R/W1C",        0,      0,      0ull,   0ull},
25539         {"OUTB_MAT"                    ,        4,      1,      167,    "R/W1C",        0,      0,      0ull,   0ull},
25540         {"RESERVED_5_63"               ,        5,      59,     167,    "RAZ",  1,      1,      0,      0},
25541         {"CNT_VAL"                     ,        0,      15,     168,    "R/W",  0,      0,      0ull,   0ull},
25542         {"CNT_ENB"                     ,        15,     1,      168,    "R/W",  0,      0,      0ull,   0ull},
25543         {"RESERVED_16_63"              ,        16,     48,     168,    "RAZ",  1,      1,      0,      0},
25544         {"TOUT_VAL"                    ,        0,      12,     169,    "R/W",  0,      0,      4ull,   4ull},
25545         {"TOUT_ENB"                    ,        12,     1,      169,    "R/W",  0,      0,      1ull,   0ull},
25546         {"RESERVED_13_63"              ,        13,     51,     169,    "RAZ",  1,      1,      0,      0},
25547         {"CNT_VAL"                     ,        0,      15,     170,    "R/W",  0,      0,      0ull,   0ull},
25548         {"CNT_ENB"                     ,        15,     1,      170,    "R/W",  0,      0,      0ull,   0ull},
25549         {"RESERVED_16_63"              ,        16,     48,     170,    "RAZ",  1,      1,      0,      0},
25550         {"SRC"                         ,        0,      8,      171,    "R/W",  0,      1,      0ull,   0},
25551         {"DST"                         ,        8,      9,      171,    "R/W",  0,      1,      0ull,   0},
25552         {"OPC"                         ,        17,     4,      171,    "R/W",  0,      1,      0ull,   0},
25553         {"MASK"                        ,        21,     8,      171,    "R/W",  0,      1,      0ull,   0},
25554         {"RESERVED_29_63"              ,        29,     35,     171,    "RAZ",  1,      1,      0,      0},
25555         {"SRC"                         ,        0,      8,      172,    "R/W",  0,      1,      0ull,   0},
25556         {"DST"                         ,        8,      9,      172,    "R/W",  0,      1,      0ull,   0},
25557         {"OPC"                         ,        17,     4,      172,    "R/W",  0,      1,      0ull,   0},
25558         {"MASK"                        ,        21,     8,      172,    "R/W",  0,      1,      0ull,   0},
25559         {"RESERVED_29_63"              ,        29,     35,     172,    "RAZ",  1,      1,      0,      0},
25560         {"DATA"                        ,        0,      64,     173,    "R/W",  0,      1,      0ull,   0},
25561         {"DATA"                        ,        0,      64,     174,    "R/W",  0,      1,      0ull,   0},
25562         {"NP_SOP"                      ,        0,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
25563         {"NP_EOP"                      ,        1,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
25564         {"P_SOP"                       ,        2,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
25565         {"P_EOP"                       ,        3,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
25566         {"NP_DAT"                      ,        4,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
25567         {"P_DAT"                       ,        5,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
25568         {"RESERVED_6_63"               ,        6,      58,     175,    "RAZ",  1,      1,      0,      0},
25569         {"NP_SOP"                      ,        0,      1,      176,    "R/W1C",        0,      0,      0ull,   0ull},
25570         {"NP_EOP"                      ,        1,      1,      176,    "R/W1C",        0,      0,      0ull,   0ull},
25571         {"P_SOP"                       ,        2,      1,      176,    "R/W1C",        0,      0,      0ull,   0ull},
25572         {"P_EOP"                       ,        3,      1,      176,    "R/W1C",        0,      0,      0ull,   0ull},
25573         {"NP_DAT"                      ,        4,      1,      176,    "R/W1C",        0,      0,      0ull,   0ull},
25574         {"P_DAT"                       ,        5,      1,      176,    "R/W1C",        0,      0,      0ull,   0ull},
25575         {"RESERVED_6_63"               ,        6,      58,     176,    "RAZ",  1,      1,      0,      0},
25576         {"CNT_VAL"                     ,        0,      15,     177,    "R/W",  0,      0,      0ull,   0ull},
25577         {"CNT_ENB"                     ,        15,     1,      177,    "R/W",  0,      0,      0ull,   0ull},
25578         {"RESERVED_16_63"              ,        16,     48,     177,    "RAZ",  1,      1,      0,      0},
25579         {"CNT_VAL"                     ,        0,      15,     178,    "R/W",  0,      0,      0ull,   0ull},
25580         {"CNT_ENB"                     ,        15,     1,      178,    "R/W",  0,      0,      0ull,   0ull},
25581         {"RESERVED_16_63"              ,        16,     48,     178,    "RAZ",  1,      1,      0,      0},
25582         {"CNT_VAL"                     ,        0,      15,     179,    "R/W",  0,      0,      0ull,   0ull},
25583         {"CNT_ENB"                     ,        15,     1,      179,    "R/W",  0,      0,      0ull,   0ull},
25584         {"RESERVED_16_63"              ,        16,     48,     179,    "RAZ",  1,      1,      0,      0},
25585         {"SRC"                         ,        0,      9,      180,    "R/W",  0,      1,      0ull,   0},
25586         {"DST"                         ,        9,      8,      180,    "R/W",  0,      1,      0ull,   0},
25587         {"EOT"                         ,        17,     1,      180,    "R/W",  0,      1,      0ull,   0},
25588         {"MASK"                        ,        18,     8,      180,    "R/W",  0,      1,      0ull,   0},
25589         {"RESERVED_26_63"              ,        26,     38,     180,    "RAZ",  1,      1,      0,      0},
25590         {"SRC"                         ,        0,      9,      181,    "R/W",  0,      1,      0ull,   0},
25591         {"DST"                         ,        9,      8,      181,    "R/W",  0,      1,      0ull,   0},
25592         {"EOT"                         ,        17,     1,      181,    "R/W",  0,      1,      0ull,   0},
25593         {"MASK"                        ,        18,     8,      181,    "R/W",  0,      1,      0ull,   0},
25594         {"RESERVED_26_63"              ,        26,     38,     181,    "RAZ",  1,      1,      0,      0},
25595         {"DATA"                        ,        0,      64,     182,    "R/W",  0,      1,      0ull,   0},
25596         {"DATA"                        ,        0,      64,     183,    "R/W",  0,      1,      0ull,   0},
25597         {"CNT_VAL"                     ,        0,      15,     184,    "R/W",  0,      0,      0ull,   0ull},
25598         {"CNT_ENB"                     ,        15,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
25599         {"RESERVED_16_63"              ,        16,     48,     184,    "RAZ",  1,      1,      0,      0},
25600         {"CNT_VAL"                     ,        0,      15,     185,    "R/W",  0,      0,      0ull,   0ull},
25601         {"CNT_ENB"                     ,        15,     1,      185,    "R/W",  0,      0,      0ull,   0ull},
25602         {"RESERVED_16_63"              ,        16,     48,     185,    "RAZ",  1,      1,      0,      0},
25603         {"CNT_VAL"                     ,        0,      15,     186,    "R/W",  0,      0,      0ull,   0ull},
25604         {"CNT_ENB"                     ,        15,     1,      186,    "R/W",  0,      0,      0ull,   0ull},
25605         {"RESERVED_16_63"              ,        16,     48,     186,    "RAZ",  1,      1,      0,      0},
25606         {"PORT"                        ,        0,      6,      187,    "RO",   0,      1,      0ull,   0},
25607         {"RESERVED_6_63"               ,        6,      58,     187,    "RAZ",  1,      1,      0,      0},
25608         {"SKIP_SZ"                     ,        0,      6,      188,    "R/W",  0,      0,      0ull,   0ull},
25609         {"RESERVED_6_63"               ,        6,      58,     188,    "RAZ",  1,      1,      0,      0},
25610         {"BACK"                        ,        0,      4,      189,    "R/W",  0,      0,      0ull,   0ull},
25611         {"RESERVED_4_63"               ,        4,      60,     189,    "RAZ",  1,      1,      0,      0},
25612         {"BACK"                        ,        0,      4,      190,    "R/W",  0,      0,      0ull,   0ull},
25613         {"RESERVED_4_63"               ,        4,      60,     190,    "RAZ",  1,      1,      0,      0},
25614         {"PWP"                         ,        0,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25615         {"IPD_NEW"                     ,        1,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25616         {"IPD_OLD"                     ,        2,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25617         {"PRC_OFF"                     ,        3,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25618         {"PWQ0"                        ,        4,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25619         {"PWQ1"                        ,        5,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25620         {"PBM_WORD"                    ,        6,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25621         {"PBM0"                        ,        7,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25622         {"PBM1"                        ,        8,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25623         {"PBM2"                        ,        9,      1,      191,    "RO",   0,      0,      0ull,   0ull},
25624         {"PBM3"                        ,        10,     1,      191,    "RO",   0,      0,      0ull,   0ull},
25625         {"IPQ_PBE0"                    ,        11,     1,      191,    "RO",   0,      0,      0ull,   0ull},
25626         {"IPQ_PBE1"                    ,        12,     1,      191,    "RO",   0,      0,      0ull,   0ull},
25627         {"PWQ_POW"                     ,        13,     1,      191,    "RO",   0,      0,      0ull,   0ull},
25628         {"PWQ_WP1"                     ,        14,     1,      191,    "RO",   0,      0,      0ull,   0ull},
25629         {"PWQ_WQED"                    ,        15,     1,      191,    "RO",   0,      0,      0ull,   0ull},
25630         {"RESERVED_16_63"              ,        16,     48,     191,    "RAZ",  1,      1,      0,      0},
25631         {"PRT_ENB"                     ,        0,      36,     192,    "R/W",  0,      0,      0ull,   0ull},
25632         {"RESERVED_36_63"              ,        36,     28,     192,    "RAZ",  1,      1,      0,      0},
25633         {"CLK_CNT"                     ,        0,      64,     193,    "RO",   0,      0,      0ull,   0ull},
25634         {"IPD_EN"                      ,        0,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
25635         {"OPC_MODE"                    ,        1,      2,      194,    "R/W",  0,      0,      0ull,   0ull},
25636         {"PBP_EN"                      ,        3,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
25637         {"WQE_LEND"                    ,        4,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
25638         {"PKT_LEND"                    ,        5,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
25639         {"NADDBUF"                     ,        6,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
25640         {"ADDPKT"                      ,        7,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
25641         {"RESET"                       ,        8,      1,      194,    "R/W",  0,      0,      0ull,   0ull},
25642         {"LEN_M8"                      ,        9,      1,      194,    "R/W",  0,      0,      0ull,   1ull},
25643         {"PKT_OFF"                     ,        10,     1,      194,    "R/W",  0,      0,      0ull,   0ull},
25644         {"IPD_FULL"                    ,        11,     1,      194,    "R/W",  0,      0,      0ull,   0ull},
25645         {"RESERVED_12_63"              ,        12,     52,     194,    "RAZ",  1,      1,      0,      0},
25646         {"PRC_PAR0"                    ,        0,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25647         {"PRC_PAR1"                    ,        1,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25648         {"PRC_PAR2"                    ,        2,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25649         {"PRC_PAR3"                    ,        3,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25650         {"BP_SUB"                      ,        4,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25651         {"DC_OVR"                      ,        5,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25652         {"CC_OVR"                      ,        6,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25653         {"C_COLL"                      ,        7,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25654         {"D_COLL"                      ,        8,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25655         {"BC_OVR"                      ,        9,      1,      195,    "R/W",  0,      0,      0ull,   0ull},
25656         {"RESERVED_10_63"              ,        10,     54,     195,    "RAZ",  1,      1,      0,      0},
25657         {"PRC_PAR0"                    ,        0,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25658         {"PRC_PAR1"                    ,        1,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25659         {"PRC_PAR2"                    ,        2,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25660         {"PRC_PAR3"                    ,        3,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25661         {"BP_SUB"                      ,        4,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25662         {"DC_OVR"                      ,        5,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25663         {"CC_OVR"                      ,        6,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25664         {"C_COLL"                      ,        7,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25665         {"D_COLL"                      ,        8,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25666         {"BC_OVR"                      ,        9,      1,      196,    "R/W1C",        0,      0,      0ull,   0ull},
25667         {"RESERVED_10_63"              ,        10,     54,     196,    "RAZ",  1,      1,      0,      0},
25668         {"SKIP_SZ"                     ,        0,      6,      197,    "R/W",  0,      0,      0ull,   0ull},
25669         {"RESERVED_6_63"               ,        6,      58,     197,    "RAZ",  1,      1,      0,      0},
25670         {"MB_SIZE"                     ,        0,      12,     198,    "R/W",  0,      0,      32ull,  32ull},
25671         {"RESERVED_12_63"              ,        12,     52,     198,    "RAZ",  1,      1,      0,      0},
25672         {"PTR"                         ,        0,      29,     199,    "RO",   1,      1,      0,      0},
25673         {"RESERVED_29_63"              ,        29,     35,     199,    "RAZ",  1,      1,      0,      0},
25674         {"PAGE_CNT"                    ,        0,      17,     200,    "R/W",  0,      0,      0ull,   0ull},
25675         {"BP_ENB"                      ,        17,     1,      200,    "R/W",  0,      0,      0ull,   0ull},
25676         {"RESERVED_18_63"              ,        18,     46,     200,    "RAZ",  1,      1,      0,      0},
25677         {"CNT_VAL"                     ,        0,      25,     201,    "RO",   0,      1,      0ull,   0},
25678         {"RESERVED_25_63"              ,        25,     39,     201,    "RAZ",  1,      1,      0,      0},
25679         {"RADDR"                       ,        0,      3,      202,    "R/W",  0,      0,      0ull,   0ull},
25680         {"CENA"                        ,        3,      1,      202,    "R/W",  0,      0,      1ull,   1ull},
25681         {"PTR"                         ,        4,      29,     202,    "RO",   1,      1,      0,      0},
25682         {"PRADDR"                      ,        33,     3,      202,    "RO",   1,      1,      0,      0},
25683         {"MAX_PKT"                     ,        36,     3,      202,    "RO",   0,      0,      5ull,   5ull},
25684         {"RESERVED_39_63"              ,        39,     25,     202,    "RAZ",  1,      1,      0,      0},
25685         {"RADDR"                       ,        0,      7,      203,    "R/W",  0,      0,      0ull,   0ull},
25686         {"CENA"                        ,        7,      1,      203,    "R/W",  0,      0,      1ull,   1ull},
25687         {"PTR"                         ,        8,      29,     203,    "RO",   1,      1,      0,      0},
25688         {"MAX_PKT"                     ,        37,     7,      203,    "RO",   0,      0,      36ull,  36ull},
25689         {"RESERVED_44_63"              ,        44,     20,     203,    "RAZ",  1,      1,      0,      0},
25690         {"WQE_PCNT"                    ,        0,      7,      204,    "RO",   0,      0,      0ull,   0ull},
25691         {"PKT_PCNT"                    ,        7,      7,      204,    "RO",   0,      0,      0ull,   0ull},
25692         {"PFIF_CNT"                    ,        14,     3,      204,    "RO",   0,      0,      0ull,   0ull},
25693         {"WQEV_CNT"                    ,        17,     1,      204,    "RO",   0,      0,      0ull,   0ull},
25694         {"PKTV_CNT"                    ,        18,     1,      204,    "RO",   0,      0,      0ull,   0ull},
25695         {"RESERVED_19_63"              ,        19,     45,     204,    "RAZ",  1,      1,      0,      0},
25696         {"RADDR"                       ,        0,      8,      205,    "R/W",  0,      0,      0ull,   0ull},
25697         {"CENA"                        ,        8,      1,      205,    "R/W",  0,      0,      1ull,   1ull},
25698         {"PTR"                         ,        9,      29,     205,    "RO",   1,      1,      0,      0},
25699         {"PRADDR"                      ,        38,     8,      205,    "RO",   1,      1,      0,      0},
25700         {"WRADDR"                      ,        46,     8,      205,    "RO",   1,      1,      0,      0},
25701         {"MAX_CNTS"                    ,        54,     7,      205,    "RO",   0,      0,      64ull,  64ull},
25702         {"RESERVED_61_63"              ,        61,     3,      205,    "RAZ",  1,      1,      0,      0},
25703         {"PASS"                        ,        0,      32,     206,    "R/W",  0,      1,      0ull,   0},
25704         {"DROP"                        ,        32,     32,     206,    "R/W",  0,      1,      0ull,   0},
25705         {"Q0_PCNT"                     ,        0,      32,     207,    "RO",   0,      0,      0ull,   0ull},
25706         {"RESERVED_32_63"              ,        32,     32,     207,    "RAZ",  1,      1,      0,      0},
25707         {"PRT_ENB"                     ,        0,      36,     208,    "R/W",  0,      0,      0ull,   0ull},
25708         {"AVG_DLY"                     ,        36,     14,     208,    "R/W",  0,      1,      0ull,   0},
25709         {"PRB_DLY"                     ,        50,     14,     208,    "R/W",  0,      0,      0ull,   0ull},
25710         {"PRB_CON"                     ,        0,      32,     209,    "R/W",  0,      1,      0ull,   0},
25711         {"AVG_CON"                     ,        32,     8,      209,    "R/W",  0,      1,      0ull,   0},
25712         {"NEW_CON"                     ,        40,     8,      209,    "R/W",  0,      1,      0ull,   0},
25713         {"USE_PCNT"                    ,        48,     1,      209,    "R/W",  0,      0,      0ull,   0ull},
25714         {"RESERVED_49_63"              ,        49,     15,     209,    "RAZ",  1,      1,      0,      0},
25715         {"PAGE_CNT"                    ,        0,      25,     210,    "R/W",  1,      0,      0,      0ull},
25716         {"PORT"                        ,        25,     6,      210,    "R/W",  1,      0,      0,      0ull},
25717         {"RESERVED_31_63"              ,        31,     33,     210,    "RAZ",  1,      1,      0,      0},
25718         {"PORT_BIT"                    ,        0,      32,     211,    "R/W",  0,      0,      4294967295ull,  4294967295ull},
25719         {"RESERVED_32_63"              ,        32,     32,     211,    "RAZ",  1,      1,      0,      0},
25720         {"WQE_POOL"                    ,        0,      3,      212,    "R/W",  0,      0,      1ull,   1ull},
25721         {"RESERVED_3_63"               ,        3,      61,     212,    "RAZ",  1,      1,      0,      0},
25722         {"PTR"                         ,        0,      29,     213,    "RO",   1,      1,      0,      0},
25723         {"RESERVED_29_63"              ,        29,     35,     213,    "RAZ",  1,      1,      0,      0},
25724         {"MEM0"                        ,        0,      1,      214,    "RO",   0,      0,      0ull,   0ull},
25725         {"MEM1"                        ,        1,      1,      214,    "RO",   0,      0,      0ull,   0ull},
25726         {"RRC"                         ,        2,      1,      214,    "RO",   0,      0,      0ull,   0ull},
25727         {"RESERVED_3_63"               ,        3,      61,     214,    "RAZ",  1,      1,      0,      0},
25728         {"MEM0_ERR"                    ,        0,      7,      215,    "R/W",  0,      0,      0ull,   0ull},
25729         {"MEM1_ERR"                    ,        7,      7,      215,    "R/W",  0,      0,      0ull,   0ull},
25730         {"RESERVED_14_63"              ,        14,     50,     215,    "RAZ",  1,      1,      0,      0},
25731         {"KED0_SBE"                    ,        0,      1,      216,    "R/W",  0,      0,      0ull,   0ull},
25732         {"KED0_DBE"                    ,        1,      1,      216,    "R/W",  0,      0,      0ull,   0ull},
25733         {"KED1_SBE"                    ,        2,      1,      216,    "R/W",  0,      0,      0ull,   0ull},
25734         {"KED1_DBE"                    ,        3,      1,      216,    "R/W",  0,      0,      0ull,   0ull},
25735         {"RESERVED_4_63"               ,        4,      60,     216,    "RAZ",  1,      1,      0,      0},
25736         {"KED0_SBE"                    ,        0,      1,      217,    "R/W1C",        0,      0,      0ull,   0ull},
25737         {"KED0_DBE"                    ,        1,      1,      217,    "R/W1C",        0,      0,      0ull,   0ull},
25738         {"KED1_SBE"                    ,        2,      1,      217,    "R/W1C",        0,      0,      0ull,   0ull},
25739         {"KED1_DBE"                    ,        3,      1,      217,    "R/W1C",        0,      0,      0ull,   0ull},
25740         {"RESERVED_4_63"               ,        4,      60,     217,    "RAZ",  1,      1,      0,      0},
25741         {"WLB_DAT"                     ,        0,      4,      218,    "RO",   0,      0,      0ull,   0ull},
25742         {"STIN_MSK"                    ,        4,      1,      218,    "RO",   0,      0,      0ull,   0ull},
25743         {"DT"                          ,        5,      1,      218,    "RO",   0,      0,      0ull,   0ull},
25744         {"DTCNT"                       ,        6,      13,     218,    "RO",   0,      0,      0ull,   0ull},
25745         {"WLB_MSK"                     ,        19,     4,      218,    "RO",   0,      0,      0ull,   0ull},
25746         {"DTBNK"                       ,        23,     1,      218,    "RO",   0,      0,      0ull,   0ull},
25747         {"RESERVED_24_63"              ,        24,     40,     218,    "RAZ",  0,      0,      0ull,   0ull},
25748         {"L2T"                         ,        0,      9,      219,    "RO",   0,      0,      0ull,   0ull},
25749         {"VAB_VWCF"                    ,        9,      1,      219,    "RO",   0,      0,      0ull,   0ull},
25750         {"LRF"                         ,        10,     2,      219,    "RO",   0,      0,      0ull,   0ull},
25751         {"VWDF"                        ,        12,     4,      219,    "RO",   0,      0,      0ull,   0ull},
25752         {"RESERVED_16_63"              ,        16,     48,     219,    "RAZ",  0,      0,      0ull,   0ull},
25753         {"XRDDAT"                      ,        0,      1,      220,    "RO",   0,      0,      0ull,   0ull},
25754         {"XRDMSK"                      ,        1,      1,      220,    "RO",   0,      0,      0ull,   0ull},
25755         {"PICBST"                      ,        2,      1,      220,    "RO",   0,      0,      0ull,   0ull},
25756         {"IPCBST"                      ,        3,      1,      220,    "RO",   0,      0,      0ull,   0ull},
25757         {"RHDB"                        ,        4,      4,      220,    "RO",   0,      0,      0ull,   0ull},
25758         {"RMDB"                        ,        8,      4,      220,    "RO",   0,      0,      0ull,   0ull},
25759         {"MRB"                         ,        12,     4,      220,    "RO",   0,      0,      0ull,   0ull},
25760         {"RESERVED_16_63"              ,        16,     48,     220,    "RAZ",  0,      0,      0ull,   0ull},
25761         {"LRF_ARB_MODE"                ,        0,      1,      221,    "R/W",  0,      0,      1ull,   1ull},
25762         {"RFB_ARB_MODE"                ,        1,      1,      221,    "R/W",  0,      0,      1ull,   1ull},
25763         {"RSP_ARB_MODE"                ,        2,      1,      221,    "R/W",  0,      0,      1ull,   1ull},
25764         {"MWF_CRD"                     ,        3,      4,      221,    "R/W",  0,      0,      2ull,   2ull},
25765         {"IDXALIAS"                    ,        7,      1,      221,    "R/W",  0,      0,      0ull,   1ull},
25766         {"FPEN"                        ,        8,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
25767         {"FPEMPTY"                     ,        9,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
25768         {"FPEXP"                       ,        10,     4,      221,    "R/W",  0,      0,      0ull,   0ull},
25769         {"DFILL_DIS"                   ,        14,     1,      221,    "R/W",  0,      0,      0ull,   0ull},
25770         {"RESERVED_15_63"              ,        15,     49,     221,    "RAZ",  0,      0,      0ull,   0ull},
25771         {"L2T"                         ,        0,      1,      222,    "R/W",  0,      0,      0ull,   0ull},
25772         {"L2D"                         ,        1,      1,      222,    "R/W",  0,      0,      0ull,   0ull},
25773         {"FINV"                        ,        2,      1,      222,    "R/W",  0,      0,      0ull,   0ull},
25774         {"SET"                         ,        3,      3,      222,    "R/W",  0,      0,      0ull,   0ull},
25775         {"PPNUM"                       ,        6,      4,      222,    "R/W",  0,      0,      0ull,   0ull},
25776         {"LFB_DMP"                     ,        10,     1,      222,    "R/W",  0,      0,      0ull,   0ull},
25777         {"LFB_ENUM"                    ,        11,     4,      222,    "R/W",  0,      0,      0ull,   0ull},
25778         {"RESERVED_15_63"              ,        15,     49,     222,    "RAZ",  0,      0,      0ull,   0ull},
25779         {"DT_TAG"                      ,        0,      29,     223,    "RO",   0,      0,      0ull,   0ull},
25780         {"DT_VLD"                      ,        29,     1,      223,    "RO",   0,      0,      0ull,   0ull},
25781         {"RESERVED_30_30"              ,        30,     1,      223,    "RAZ",  0,      0,      0ull,   0ull},
25782         {"DTENA"                       ,        31,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
25783         {"RESERVED_32_63"              ,        32,     32,     223,    "RAZ",  0,      0,      0ull,   0ull},
25784         {"LCK_ENA"                     ,        0,      1,      224,    "R/W",  0,      0,      0ull,   0ull},
25785         {"RESERVED_1_3"                ,        1,      3,      224,    "RAZ",  0,      0,      0ull,   0ull},
25786         {"LCK_BASE"                    ,        4,      27,     224,    "R/W",  0,      0,      0ull,   0ull},
25787         {"RESERVED_31_63"              ,        31,     33,     224,    "RAZ",  0,      0,      0ull,   0ull},
25788         {"LCK_OFFSET"                  ,        0,      10,     225,    "R/W",  0,      0,      0ull,   0ull},
25789         {"RESERVED_10_63"              ,        10,     54,     225,    "RAZ",  0,      0,      0ull,   0ull},
25790         {"VLD"                         ,        0,      1,      226,    "RO",   0,      0,      0ull,   0ull},
25791         {"CMD"                         ,        1,      4,      226,    "RO",   0,      0,      0ull,   0ull},
25792         {"SID"                         ,        5,      9,      226,    "RO",   0,      0,      0ull,   0ull},
25793         {"VABNUM"                      ,        14,     4,      226,    "RO",   0,      0,      0ull,   0ull},
25794         {"SET"                         ,        18,     3,      226,    "RO",   0,      0,      0ull,   0ull},
25795         {"IHD"                         ,        21,     1,      226,    "RO",   0,      0,      0ull,   0ull},
25796         {"ITL"                         ,        22,     1,      226,    "RO",   0,      0,      0ull,   0ull},
25797         {"INXT"                        ,        23,     4,      226,    "RO",   0,      0,      0ull,   0ull},
25798         {"VAM"                         ,        27,     1,      226,    "RO",   0,      0,      0ull,   0ull},
25799         {"STCFL"                       ,        28,     1,      226,    "RO",   0,      0,      0ull,   0ull},
25800         {"STINV"                       ,        29,     1,      226,    "RO",   0,      0,      0ull,   0ull},
25801         {"STPND"                       ,        30,     1,      226,    "RO",   0,      0,      0ull,   0ull},
25802         {"STCPND"                      ,        31,     1,      226,    "RO",   0,      0,      0ull,   0ull},
25803         {"RESERVED_32_63"              ,        32,     32,     226,    "RAZ",  0,      0,      0ull,   0ull},
25804         {"VLD"                         ,        0,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25805         {"WTPRB"                       ,        1,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25806         {"PRBRTY"                      ,        2,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25807         {"WTMFL"                       ,        3,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25808         {"WTVTM"                       ,        4,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25809         {"WTSTRSC"                     ,        5,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25810         {"WTSTRSP"                     ,        6,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25811         {"WTSTDT"                      ,        7,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25812         {"WTRDA"                       ,        8,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25813         {"WTSTM"                       ,        9,      1,      227,    "RO",   0,      0,      0ull,   0ull},
25814         {"WTWRM"                       ,        10,     1,      227,    "RO",   0,      0,      0ull,   0ull},
25815         {"WTWHF"                       ,        11,     1,      227,    "RO",   0,      0,      0ull,   0ull},
25816         {"WTWHP"                       ,        12,     1,      227,    "RO",   0,      0,      0ull,   0ull},
25817         {"WTDQ"                        ,        13,     1,      227,    "RO",   0,      0,      0ull,   0ull},
25818         {"WTDW"                        ,        14,     1,      227,    "RO",   0,      0,      0ull,   0ull},
25819         {"WTRSP"                       ,        15,     1,      227,    "RO",   0,      0,      0ull,   0ull},
25820         {"BID"                         ,        16,     2,      227,    "RO",   0,      0,      0ull,   0ull},
25821         {"DSGOING"                     ,        18,     1,      227,    "RO",   0,      0,      0ull,   0ull},
25822         {"RESERVED_19_63"              ,        19,     45,     227,    "RAZ",  0,      0,      0ull,   0ull},
25823         {"LFB_IDX"                     ,        0,      11,     228,    "RO",   0,      0,      0ull,   0ull},
25824         {"LFB_TAG"                     ,        11,     16,     228,    "RO",   0,      0,      0ull,   0ull},
25825         {"RESERVED_27_63"              ,        27,     37,     228,    "RAZ",  0,      0,      0ull,   0ull},
25826         {"LFB_HWM"                     ,        0,      4,      229,    "R/W",  0,      0,      15ull,  15ull},
25827         {"STPARTDIS"                   ,        4,      1,      229,    "R/W",  0,      0,      0ull,   0ull},
25828         {"RESERVED_5_63"               ,        5,      59,     229,    "RAZ",  0,      0,      0ull,   0ull},
25829         {"PFCNT0"                      ,        0,      36,     230,    "RO",   0,      0,      0ull,   0ull},
25830         {"RESERVED_36_63"              ,        36,     28,     230,    "RAZ",  0,      0,      0ull,   0ull},
25831         {"CNT0SEL"                     ,        0,      6,      231,    "R/W",  0,      0,      0ull,   0ull},
25832         {"CNT0CLR"                     ,        6,      1,      231,    "R/W",  0,      0,      0ull,   0ull},
25833         {"CNT0ENA"                     ,        7,      1,      231,    "R/W",  0,      0,      0ull,   0ull},
25834         {"CNT1SEL"                     ,        8,      6,      231,    "R/W",  0,      0,      0ull,   0ull},
25835         {"CNT1CLR"                     ,        14,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25836         {"CNT1ENA"                     ,        15,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25837         {"CNT2SEL"                     ,        16,     6,      231,    "R/W",  0,      0,      0ull,   0ull},
25838         {"CNT2CLR"                     ,        22,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25839         {"CNT2ENA"                     ,        23,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25840         {"CNT3SEL"                     ,        24,     6,      231,    "R/W",  0,      0,      0ull,   0ull},
25841         {"CNT3CLR"                     ,        30,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25842         {"CNT3ENA"                     ,        31,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25843         {"CNT0RDCLR"                   ,        32,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25844         {"CNT1RDCLR"                   ,        33,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25845         {"CNT2RDCLR"                   ,        34,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25846         {"CNT3RDCLR"                   ,        35,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
25847         {"RESERVED_36_63"              ,        36,     28,     231,    "RAZ",  0,      0,      0ull,   0ull},
25848         {"UMSK0"                       ,        0,      8,      232,    "R/W",  0,      0,      0ull,   0ull},
25849         {"UMSK1"                       ,        8,      8,      232,    "R/W",  0,      0,      0ull,   0ull},
25850         {"UMSK2"                       ,        16,     8,      232,    "R/W",  0,      0,      0ull,   0ull},
25851         {"UMSK3"                       ,        24,     8,      232,    "R/W",  0,      0,      0ull,   0ull},
25852         {"RESERVED_32_63"              ,        32,     32,     232,    "RAZ",  0,      0,      0ull,   0ull},
25853         {"UMSK4"                       ,        0,      8,      233,    "R/W",  0,      0,      0ull,   0ull},
25854         {"UMSK5"                       ,        8,      8,      233,    "R/W",  0,      0,      0ull,   0ull},
25855         {"UMSK6"                       ,        16,     8,      233,    "R/W",  0,      0,      0ull,   0ull},
25856         {"UMSK7"                       ,        24,     8,      233,    "R/W",  0,      0,      0ull,   0ull},
25857         {"RESERVED_32_63"              ,        32,     32,     233,    "RAZ",  0,      0,      0ull,   0ull},
25858         {"UMSK8"                       ,        0,      8,      234,    "R/W",  0,      0,      0ull,   0ull},
25859         {"UMSK9"                       ,        8,      8,      234,    "R/W",  0,      0,      0ull,   0ull},
25860         {"UMSK10"                      ,        16,     8,      234,    "R/W",  0,      0,      0ull,   0ull},
25861         {"UMSK11"                      ,        24,     8,      234,    "R/W",  0,      0,      0ull,   0ull},
25862         {"RESERVED_32_63"              ,        32,     32,     234,    "RAZ",  0,      0,      0ull,   0ull},
25863         {"UMSK12"                      ,        0,      8,      235,    "R/W",  0,      0,      0ull,   0ull},
25864         {"UMSK13"                      ,        8,      8,      235,    "R/W",  0,      0,      0ull,   0ull},
25865         {"UMSK14"                      ,        16,     8,      235,    "R/W",  0,      0,      0ull,   0ull},
25866         {"UMSK15"                      ,        24,     8,      235,    "R/W",  0,      0,      0ull,   0ull},
25867         {"RESERVED_32_63"              ,        32,     32,     235,    "RAZ",  0,      0,      0ull,   0ull},
25868         {"UMSKIOB"                     ,        0,      8,      236,    "R/W",  0,      0,      0ull,   0ull},
25869         {"RESERVED_8_63"               ,        8,      56,     236,    "RAZ",  0,      0,      0ull,   0ull},
25870         {"Q0STAT"                      ,        0,      34,     237,    "RO",   0,      0,      0ull,   0ull},
25871         {"FTL"                         ,        34,     1,      237,    "RO",   0,      0,      0ull,   0ull},
25872         {"RESERVED_35_63"              ,        35,     29,     237,    "RAZ",  0,      0,      0ull,   0ull},
25873         {"Q1STAT"                      ,        0,      34,     238,    "RO",   0,      0,      0ull,   0ull},
25874         {"RESERVED_34_63"              ,        34,     30,     238,    "RAZ",  0,      0,      0ull,   0ull},
25875         {"Q2STAT"                      ,        0,      34,     239,    "RO",   0,      0,      0ull,   0ull},
25876         {"RESERVED_34_63"              ,        34,     30,     239,    "RAZ",  0,      0,      0ull,   0ull},
25877         {"Q3STAT"                      ,        0,      34,     240,    "RO",   0,      0,      0ull,   0ull},
25878         {"RESERVED_34_63"              ,        34,     30,     240,    "RAZ",  0,      0,      0ull,   0ull},
25879         {"ECC_ENA"                     ,        0,      1,      241,    "R/W",  0,      0,      0ull,   1ull},
25880         {"SEC_INTENA"                  ,        1,      1,      241,    "R/W",  0,      0,      0ull,   1ull},
25881         {"DED_INTENA"                  ,        2,      1,      241,    "R/W",  0,      0,      0ull,   1ull},
25882         {"SEC_ERR"                     ,        3,      1,      241,    "R/W1C",        0,      0,      0ull,   0ull},
25883         {"DED_ERR"                     ,        4,      1,      241,    "R/W1C",        0,      0,      0ull,   0ull},
25884         {"BMHCLSEL"                    ,        5,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
25885         {"RESERVED_6_63"               ,        6,      58,     241,    "RAZ",  0,      0,      0ull,   0ull},
25886         {"FADR"                        ,        0,      11,     242,    "RO",   0,      0,      0ull,   0ull},
25887         {"FSET"                        ,        11,     3,      242,    "RO",   0,      0,      0ull,   0ull},
25888         {"FOWMSK"                      ,        14,     4,      242,    "RO",   0,      0,      0ull,   0ull},
25889         {"FADRU"                       ,        18,     1,      242,    "RO",   0,      0,      0ull,   0ull},
25890         {"RESERVED_19_63"              ,        19,     45,     242,    "RAZ",  0,      0,      0ull,   0ull},
25891         {"FSYN_OW0"                    ,        0,      10,     243,    "RO",   0,      0,      0ull,   0ull},
25892         {"FSYN_OW1"                    ,        10,     10,     243,    "RO",   0,      0,      0ull,   0ull},
25893         {"RESERVED_20_63"              ,        20,     44,     243,    "RAZ",  0,      0,      0ull,   0ull},
25894         {"FSYN_OW2"                    ,        0,      10,     244,    "RO",   0,      0,      0ull,   0ull},
25895         {"FSYN_OW3"                    ,        10,     10,     244,    "RO",   0,      0,      0ull,   0ull},
25896         {"RESERVED_20_63"              ,        20,     44,     244,    "RAZ",  0,      0,      0ull,   0ull},
25897         {"Q0FUS"                       ,        0,      34,     245,    "RO",   0,      0,      0ull,   0ull},
25898         {"RESERVED_34_63"              ,        34,     30,     245,    "RAZ",  0,      0,      0ull,   0ull},
25899         {"Q1FUS"                       ,        0,      34,     246,    "RO",   0,      0,      0ull,   0ull},
25900         {"RESERVED_34_63"              ,        34,     30,     246,    "RAZ",  0,      0,      0ull,   0ull},
25901         {"Q2FUS"                       ,        0,      34,     247,    "RO",   0,      0,      0ull,   0ull},
25902         {"RESERVED_34_63"              ,        34,     30,     247,    "RAZ",  0,      0,      0ull,   0ull},
25903         {"Q3FUS"                       ,        0,      34,     248,    "RO",   0,      0,      0ull,   0ull},
25904         {"CRIP_1024K"                  ,        34,     1,      248,    "RO",   0,      0,      0ull,   0ull},
25905         {"CRIP_512K"                   ,        35,     1,      248,    "RO",   0,      0,      0ull,   0ull},
25906         {"RESERVED_36_36"              ,        36,     1,      248,    "RAZ",  0,      0,      0ull,   0ull},
25907         {"EMA_CTL"                     ,        37,     2,      248,    "RO",   0,      0,      0ull,   0ull},
25908         {"RESERVED_39_63"              ,        39,     25,     248,    "RAZ",  0,      0,      0ull,   0ull},
25909         {"ECC_ENA"                     ,        0,      1,      249,    "R/W",  0,      0,      0ull,   1ull},
25910         {"SEC_INTENA"                  ,        1,      1,      249,    "R/W",  0,      0,      0ull,   1ull},
25911         {"DED_INTENA"                  ,        2,      1,      249,    "R/W",  0,      0,      0ull,   1ull},
25912         {"SEC_ERR"                     ,        3,      1,      249,    "R/W1C",        0,      0,      0ull,   0ull},
25913         {"DED_ERR"                     ,        4,      1,      249,    "R/W1C",        0,      0,      0ull,   0ull},
25914         {"FSYN"                        ,        5,      6,      249,    "RO",   0,      0,      0ull,   0ull},
25915         {"FADR"                        ,        11,     10,     249,    "RO",   0,      0,      0ull,   0ull},
25916         {"FSET"                        ,        21,     3,      249,    "RO",   0,      0,      0ull,   0ull},
25917         {"LCKERR"                      ,        24,     1,      249,    "R/W1C",        0,      0,      0ull,   0ull},
25918         {"LCK_INTENA"                  ,        25,     1,      249,    "R/W",  0,      0,      0ull,   1ull},
25919         {"LCKERR2"                     ,        26,     1,      249,    "R/W1C",        0,      0,      0ull,   0ull},
25920         {"LCK_INTENA2"                 ,        27,     1,      249,    "R/W",  0,      0,      0ull,   1ull},
25921         {"FADRU"                       ,        28,     1,      249,    "RO",   0,      0,      0ull,   0ull},
25922         {"RESERVED_29_63"              ,        29,     35,     249,    "RAZ",  0,      0,      0ull,   0ull},
25923         {"RATE"                        ,        0,      8,      250,    "R/W",  0,      0,      4ull,   4ull},
25924         {"RESERVED_8_63"               ,        8,      56,     250,    "RAZ",  1,      1,      0,      0},
25925         {"PHASE"                       ,        0,      7,      251,    "R/W",  0,      0,      4ull,   4ull},
25926         {"RESERVED_7_63"               ,        7,      57,     251,    "RAZ",  1,      1,      0,      0},
25927         {"RATE"                        ,        0,      16,     252,    "R/W",  0,      0,      0ull,   0ull},
25928         {"RESERVED_16_63"              ,        16,     48,     252,    "RAZ",  1,      1,      0,      0},
25929         {"DBG_EN"                      ,        0,      1,      253,    "R/W",  0,      0,      0ull,   0ull},
25930         {"RESERVED_1_63"               ,        1,      63,     253,    "RAZ",  1,      1,      0,      0},
25931         {"EN"                          ,        0,      1,      254,    "R/W",  0,      0,      0ull,   1ull},
25932         {"RESERVED_1_63"               ,        1,      63,     254,    "RAZ",  1,      1,      0,      0},
25933         {"POLARITY"                    ,        0,      1,      255,    "R/W",  0,      0,      0ull,   0ull},
25934         {"RESERVED_1_63"               ,        1,      63,     255,    "RAZ",  1,      1,      0,      0},
25935         {"PRT_EN"                      ,        0,      8,      256,    "R/W",  0,      1,      0ull,   0},
25936         {"RESERVED_8_63"               ,        8,      56,     256,    "RAZ",  1,      1,      0,      0},
25937         {"FORMAT"                      ,        0,      4,      257,    "R/W",  0,      1,      0ull,   0},
25938         {"RESERVED_4_63"               ,        4,      60,     257,    "RAZ",  1,      1,      0,      0},
25939         {"STATUS"                      ,        0,      6,      258,    "R/W",  0,      0,      0ull,   0ull},
25940         {"RESERVED_6_63"               ,        6,      58,     258,    "RAZ",  1,      1,      0,      0},
25941         {"CNT"                         ,        0,      6,      259,    "R/W",  0,      0,      0ull,   0ull},
25942         {"RESERVED_6_63"               ,        6,      58,     259,    "RAZ",  1,      1,      0,      0},
25943         {"DAT"                         ,        0,      32,     260,    "R/W",  0,      1,      0ull,   0},
25944         {"RESERVED_32_63"              ,        32,     32,     260,    "RAZ",  1,      1,      0,      0},
25945         {"CLR"                         ,        0,      32,     261,    "WO",   0,      1,      0ull,   0},
25946         {"RESERVED_32_63"              ,        32,     32,     261,    "RAZ",  1,      1,      0,      0},
25947         {"SET"                         ,        0,      32,     262,    "WO",   0,      1,      0ull,   0},
25948         {"RESERVED_32_63"              ,        32,     32,     262,    "RAZ",  1,      1,      0,      0},
25949         {"PCTL_DAT"                    ,        0,      4,      263,    "R/W",  0,      1,      0ull,   0},
25950         {"RESERVED_4_11"               ,        4,      8,      263,    "RAZ",  0,      1,      0ull,   0},
25951         {"PCTL_CSR"                    ,        12,     4,      263,    "R/W",  0,      1,      15ull,  0},
25952         {"NCTL_DAT"                    ,        16,     4,      263,    "R/W",  0,      1,      0ull,   0},
25953         {"RESERVED_20_27"              ,        20,     8,      263,    "RAZ",  0,      1,      0ull,   0},
25954         {"NCTL_CSR"                    ,        28,     4,      263,    "R/W",  0,      1,      15ull,  0},
25955         {"RESERVED_32_63"              ,        32,     32,     263,    "RAZ",  0,      0,      0ull,   0ull},
25956         {"DIC"                         ,        0,      2,      264,    "R/W",  0,      0,      0ull,   0ull},
25957         {"QS_DIC"                      ,        2,      2,      264,    "R/W",  0,      0,      2ull,   2ull},
25958         {"TSKW"                        ,        4,      2,      264,    "R/W",  0,      0,      0ull,   1ull},
25959         {"SIL_LAT"                     ,        6,      2,      264,    "R/W",  0,      0,      1ull,   1ull},
25960         {"BPRCH"                       ,        8,      1,      264,    "R/W",  0,      1,      0ull,   0},
25961         {"FPRCH2"                      ,        9,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
25962         {"MODE128B"                    ,        10,     1,      264,    "R/W",  0,      0,      1ull,   1ull},
25963         {"DRESET"                      ,        11,     1,      264,    "R/W",  0,      0,      1ull,   0ull},
25964         {"INORDER_MRF"                 ,        12,     1,      264,    "R/W",  0,      0,      0ull,   0ull},
25965         {"INORDER_MWF"                 ,        13,     1,      264,    "RAZ",  0,      0,      0ull,   0ull},
25966         {"R2R_SLOT"                    ,        14,     1,      264,    "R/W",  0,      0,      0ull,   0ull},
25967         {"RDIMM_ENA"                   ,        15,     1,      264,    "R/W",  0,      1,      0ull,   0},
25968         {"RESERVED_16_17"              ,        16,     2,      264,    "RAZ",  0,      0,      0ull,   0ull},
25969         {"MAX_WRITE_BATCH"             ,        18,     4,      264,    "R/W",  0,      0,      8ull,   8ull},
25970         {"XOR_BANK"                    ,        22,     1,      264,    "R/W",  0,      0,      0ull,   1ull},
25971         {"SLOW_SCF"                    ,        23,     1,      264,    "R/W",  0,      0,      0ull,   0ull},
25972         {"DDR__PCTL"                   ,        24,     4,      264,    "RO",   1,      1,      0,      0},
25973         {"DDR__NCTL"                   ,        28,     4,      264,    "RO",   1,      1,      0,      0},
25974         {"RESERVED_32_63"              ,        32,     32,     264,    "RAZ",  1,      1,      0,      0},
25975         {"RESERVED_0_7"                ,        0,      8,      265,    "RAZ",  0,      1,      0ull,   0},
25976         {"DCC_ENABLE"                  ,        8,      1,      265,    "R/W",  0,      0,      0ull,   0ull},
25977         {"SIL_MODE"                    ,        9,      1,      265,    "R/W",  0,      0,      0ull,   1ull},
25978         {"RESERVED_10_63"              ,        10,     54,     265,    "RAZ",  1,      1,      0,      0},
25979         {"DCLKCNT_HI"                  ,        0,      32,     266,    "RO",   0,      0,      0ull,   0ull},
25980         {"RESERVED_32_63"              ,        32,     32,     266,    "RAZ",  1,      1,      0,      0},
25981         {"DCLKCNT_LO"                  ,        0,      32,     267,    "RO",   0,      0,      0ull,   0ull},
25982         {"RESERVED_32_63"              ,        32,     32,     267,    "RAZ",  1,      1,      0,      0},
25983         {"DDR2"                        ,        0,      1,      268,    "R/W",  0,      0,      1ull,   1ull},
25984         {"RDQS"                        ,        1,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
25985         {"DLL90_BYP"                   ,        2,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
25986         {"DLL90_VLU"                   ,        3,      5,      268,    "R/W",  0,      1,      0ull,   0},
25987         {"QDLL_ENA"                    ,        8,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
25988         {"ODT_ENA"                     ,        9,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
25989         {"DDR2T"                       ,        10,     1,      268,    "R/W",  0,      1,      0ull,   0},
25990         {"CRIP_MODE"                   ,        11,     1,      268,    "R/W",  0,      0,      0ull,   0ull},
25991         {"TFAW"                        ,        12,     5,      268,    "R/W",  0,      0,      0ull,   9ull},
25992         {"DDR_EOF"                     ,        17,     4,      268,    "R/W",  0,      0,      0ull,   0ull},
25993         {"SILO_HC"                     ,        21,     1,      268,    "R/W",  0,      1,      1ull,   0},
25994         {"TWR"                         ,        22,     3,      268,    "R/W",  0,      0,      3ull,   1ull},
25995         {"BWCNT"                       ,        25,     1,      268,    "R/W",  0,      0,      0ull,   0ull},
25996         {"POCAS"                       ,        26,     1,      268,    "R/W",  0,      0,      0ull,   0ull},
25997         {"ADDLAT"                      ,        27,     3,      268,    "R/W",  0,      0,      0ull,   0ull},
25998         {"BURST8"                      ,        30,     1,      268,    "R/W",  0,      0,      0ull,   1ull},
25999         {"BANK8"                       ,        31,     1,      268,    "R/W",  0,      1,      0ull,   0},
26000         {"RESERVED_32_63"              ,        32,     32,     268,    "RAZ",  0,      0,      0ull,   0ull},
26001         {"CLK"                         ,        0,      4,      269,    "R/W",  0,      0,      0ull,   0ull},
26002         {"RESERVED_4_4"                ,        4,      1,      269,    "RAZ",  0,      0,      0ull,   0ull},
26003         {"CMD"                         ,        5,      4,      269,    "R/W",  0,      0,      0ull,   0ull},
26004         {"RESERVED_9_9"                ,        9,      1,      269,    "RAZ",  0,      0,      0ull,   0ull},
26005         {"DQ"                          ,        10,     4,      269,    "R/W",  0,      0,      0ull,   0ull},
26006         {"RESERVED_14_63"              ,        14,     50,     269,    "RAZ",  0,      0,      0ull,   0ull},
26007         {"CS_MASK"                     ,        0,      8,      270,    "R/W",  0,      1,      0ull,   0},
26008         {"RESERVED_8_15"               ,        8,      8,      270,    "RAZ",  0,      1,      0ull,   0},
26009         {"ROW_LSB"                     ,        16,     3,      270,    "R/W",  0,      1,      3ull,   0},
26010         {"BANK8"                       ,        19,     1,      270,    "R/W",  0,      1,      0ull,   0},
26011         {"RESERVED_20_63"              ,        20,     44,     270,    "RAZ",  0,      1,      0ull,   0},
26012         {"MRDSYN0"                     ,        0,      8,      271,    "RO",   0,      0,      0ull,   0ull},
26013         {"MRDSYN1"                     ,        8,      8,      271,    "RO",   0,      0,      0ull,   0ull},
26014         {"MRDSYN2"                     ,        16,     8,      271,    "RO",   0,      0,      0ull,   0ull},
26015         {"MRDSYN3"                     ,        24,     8,      271,    "RO",   0,      0,      0ull,   0ull},
26016         {"RESERVED_32_63"              ,        32,     32,     271,    "RAZ",  1,      1,      0,      0},
26017         {"FCOL"                        ,        0,      12,     272,    "RO",   0,      0,      0ull,   0ull},
26018         {"FROW"                        ,        12,     14,     272,    "RO",   0,      0,      0ull,   0ull},
26019         {"FBANK"                       ,        26,     3,      272,    "RO",   0,      0,      0ull,   0ull},
26020         {"FBUNK"                       ,        29,     1,      272,    "RO",   0,      0,      0ull,   0ull},
26021         {"FDIMM"                       ,        30,     2,      272,    "RO",   0,      0,      0ull,   0ull},
26022         {"RESERVED_32_63"              ,        32,     32,     272,    "RAZ",  1,      1,      0,      0},
26023         {"IFBCNT_HI"                   ,        0,      32,     273,    "RO",   0,      0,      0ull,   0ull},
26024         {"RESERVED_32_63"              ,        32,     32,     273,    "RAZ",  1,      1,      0,      0},
26025         {"IFBCNT_LO"                   ,        0,      32,     274,    "RO",   0,      0,      0ull,   0ull},
26026         {"RESERVED_32_63"              ,        32,     32,     274,    "RAZ",  1,      1,      0,      0},
26027         {"INIT_START"                  ,        0,      1,      275,    "R/W",  0,      0,      0ull,   0ull},
26028         {"ECC_ENA"                     ,        1,      1,      275,    "R/W",  0,      0,      0ull,   1ull},
26029         {"ROW_LSB"                     ,        2,      3,      275,    "R/W",  0,      1,      3ull,   0},
26030         {"PBANK_LSB"                   ,        5,      4,      275,    "R/W",  0,      1,      5ull,   0},
26031         {"REF_INT"                     ,        9,      6,      275,    "R/W",  0,      0,      1ull,   2ull},
26032         {"TCL"                         ,        15,     4,      275,    "R/W",  0,      1,      3ull,   0},
26033         {"INTR_SEC_ENA"                ,        19,     1,      275,    "R/W",  0,      0,      0ull,   1ull},
26034         {"INTR_DED_ENA"                ,        20,     1,      275,    "R/W",  0,      0,      0ull,   1ull},
26035         {"SEC_ERR"                     ,        21,     4,      275,    "R/W1C",        0,      0,      0ull,   0ull},
26036         {"DED_ERR"                     ,        25,     4,      275,    "R/W1C",        0,      0,      0ull,   0ull},
26037         {"BUNK_ENA"                    ,        29,     1,      275,    "R/W",  0,      1,      0ull,   0},
26038         {"SILO_QC"                     ,        30,     1,      275,    "R/W",  0,      1,      0ull,   0},
26039         {"RESET"                       ,        31,     1,      275,    "RAZ",  1,      1,      0,      0},
26040         {"RESERVED_32_63"              ,        32,     32,     275,    "RAZ",  1,      1,      0,      0},
26041         {"TRAS"                        ,        0,      5,      276,    "R/W",  0,      0,      12ull,  12ull},
26042         {"TRCD"                        ,        5,      4,      276,    "R/W",  0,      0,      4ull,   4ull},
26043         {"TWTR"                        ,        9,      4,      276,    "R/W",  0,      0,      2ull,   2ull},
26044         {"TRP"                         ,        13,     4,      276,    "R/W",  0,      0,      5ull,   4ull},
26045         {"TRFC"                        ,        17,     5,      276,    "R/W",  0,      0,      6ull,   7ull},
26046         {"TMRD"                        ,        22,     3,      276,    "R/W",  0,      0,      2ull,   2ull},
26047         {"CASLAT"                      ,        25,     3,      276,    "R/W",  0,      0,      4ull,   4ull},
26048         {"TRRD"                        ,        28,     3,      276,    "R/W",  0,      0,      2ull,   2ull},
26049         {"RESERVED_31_63"              ,        31,     33,     276,    "RAZ",  1,      1,      0,      0},
26050         {"OPSCNT_HI"                   ,        0,      32,     277,    "RO",   0,      0,      0ull,   0ull},
26051         {"RESERVED_32_63"              ,        32,     32,     277,    "RAZ",  1,      1,      0,      0},
26052         {"OPSCNT_LO"                   ,        0,      32,     278,    "RO",   0,      0,      0ull,   0ull},
26053         {"RESERVED_32_63"              ,        32,     32,     278,    "RAZ",  1,      1,      0,      0},
26054         {"EN2"                         ,        0,      1,      279,    "R/W",  0,      1,      0ull,   0},
26055         {"EN4"                         ,        1,      1,      279,    "R/W",  0,      1,      0ull,   0},
26056         {"EN6"                         ,        2,      1,      279,    "R/W",  0,      1,      0ull,   0},
26057         {"EN8"                         ,        3,      1,      279,    "R/W",  0,      1,      1ull,   0},
26058         {"EN12"                        ,        4,      1,      279,    "R/W",  0,      1,      0ull,   0},
26059         {"EN16"                        ,        5,      1,      279,    "R/W",  0,      1,      0ull,   0},
26060         {"RESERVED_6_7"                ,        6,      2,      279,    "RAZ",  0,      1,      0ull,   0},
26061         {"CLKR"                        ,        8,      6,      279,    "R/W",  0,      1,      0ull,   0},
26062         {"CLKF"                        ,        14,     12,     279,    "R/W",  0,      1,      31ull,  0},
26063         {"RESET_N"                     ,        26,     1,      279,    "R/W",  0,      0,      0ull,   1ull},
26064         {"DIV_RESET"                   ,        27,     1,      279,    "R/W",  0,      0,      1ull,   0ull},
26065         {"RESERVED_28_63"              ,        28,     36,     279,    "RAZ",  0,      1,      0ull,   0},
26066         {"FBSLIP"                      ,        0,      1,      280,    "R/W1C",        0,      1,      0ull,   0},
26067         {"RFSLIP"                      ,        1,      1,      280,    "R/W1C",        0,      1,      0ull,   0},
26068         {"RESERVED_2_63"               ,        2,      62,     280,    "RAZ",  1,      1,      0,      0},
26069         {"PCTL"                        ,        0,      5,      281,    "R/W",  0,      1,      0ull,   0},
26070         {"RESERVED_5_7"                ,        5,      3,      281,    "RAZ",  0,      1,      0ull,   0},
26071         {"NCTL"                        ,        8,      4,      281,    "R/W",  0,      1,      0ull,   0},
26072         {"RESERVED_12_15"              ,        12,     4,      281,    "RAZ",  0,      1,      0ull,   0},
26073         {"ENABLE"                      ,        16,     1,      281,    "R/W",  0,      1,      0ull,   0},
26074         {"RESERVED_17_63"              ,        17,     47,     281,    "RAZ",  0,      1,      0ull,   0},
26075         {"RODT_LO0"                    ,        0,      4,      282,    "R/W",  0,      0,      15ull,  0ull},
26076         {"RODT_LO1"                    ,        4,      4,      282,    "R/W",  0,      0,      15ull,  0ull},
26077         {"RODT_LO2"                    ,        8,      4,      282,    "R/W",  0,      0,      15ull,  0ull},
26078         {"RODT_LO3"                    ,        12,     4,      282,    "R/W",  0,      0,      15ull,  0ull},
26079         {"RODT_HI0"                    ,        16,     4,      282,    "R/W",  0,      0,      15ull,  0ull},
26080         {"RODT_HI1"                    ,        20,     4,      282,    "R/W",  0,      0,      15ull,  0ull},
26081         {"RODT_HI2"                    ,        24,     4,      282,    "R/W",  0,      0,      15ull,  0ull},
26082         {"RODT_HI3"                    ,        28,     4,      282,    "R/W",  0,      0,      15ull,  0ull},
26083         {"RESERVED_32_63"              ,        32,     32,     282,    "RAZ",  1,      1,      0,      0},
26084         {"WODT_LO0"                    ,        0,      4,      283,    "R/W",  0,      0,      15ull,  15ull},
26085         {"WODT_LO1"                    ,        4,      4,      283,    "R/W",  0,      0,      15ull,  15ull},
26086         {"WODT_LO2"                    ,        8,      4,      283,    "R/W",  0,      0,      15ull,  15ull},
26087         {"WODT_LO3"                    ,        12,     4,      283,    "R/W",  0,      0,      15ull,  15ull},
26088         {"WODT_HI0"                    ,        16,     4,      283,    "R/W",  0,      0,      15ull,  15ull},
26089         {"WODT_HI1"                    ,        20,     4,      283,    "R/W",  0,      0,      15ull,  15ull},
26090         {"WODT_HI2"                    ,        24,     4,      283,    "R/W",  0,      0,      15ull,  15ull},
26091         {"WODT_HI3"                    ,        28,     4,      283,    "R/W",  0,      0,      15ull,  15ull},
26092         {"RESERVED_32_63"              ,        32,     32,     283,    "RAZ",  1,      1,      0,      0},
26093         {"NCBI"                        ,        0,      1,      284,    "RO",   0,      0,      0ull,   0ull},
26094         {"LOC"                         ,        1,      1,      284,    "RO",   0,      0,      0ull,   0ull},
26095         {"NCBO_0"                      ,        2,      1,      284,    "RO",   0,      0,      0ull,   0ull},
26096         {"RESERVED_3_63"               ,        3,      61,     284,    "RAZ",  1,      1,      0,      0},
26097         {"ADR_ERR"                     ,        0,      1,      285,    "R/W1C",        0,      0,      0ull,   0ull},
26098         {"WAIT_ERR"                    ,        1,      1,      285,    "R/W1C",        0,      0,      0ull,   0ull},
26099         {"RESERVED_2_63"               ,        2,      62,     285,    "RAZ",  1,      1,      0,      0},
26100         {"ADR_INT"                     ,        0,      1,      286,    "R/W",  0,      1,      0ull,   0},
26101         {"WAIT_INT"                    ,        1,      1,      286,    "R/W",  0,      1,      0ull,   0},
26102         {"RESERVED_2_63"               ,        2,      62,     286,    "RAZ",  1,      1,      0,      0},
26103         {"RESERVED_0_2"                ,        0,      3,      287,    "RAZ",  1,      1,      0,      0},
26104         {"ADR"                         ,        3,      5,      287,    "R/W",  0,      1,      0ull,   0},
26105         {"RESERVED_8_63"               ,        8,      56,     287,    "RAZ",  1,      1,      0,      0},
26106         {"RESERVED_0_2"                ,        0,      3,      288,    "RAZ",  1,      1,      0,      0},
26107         {"BASE"                        ,        3,      25,     288,    "R/W",  0,      1,      0ull,   0},
26108         {"RESERVED_28_30"              ,        28,     3,      288,    "RAZ",  1,      1,      0,      0},
26109         {"EN"                          ,        31,     1,      288,    "R/W",  0,      1,      0ull,   0},
26110         {"RESERVED_32_63"              ,        32,     32,     288,    "RAZ",  1,      1,      0,      0},
26111         {"DATA"                        ,        0,      64,     289,    "R/W",  1,      1,      0,      0},
26112         {"BASE"                        ,        0,      16,     290,    "R/W",  0,      1,      0ull,   0},
26113         {"SIZE"                        ,        16,     12,     290,    "R/W",  0,      1,      0ull,   0},
26114         {"WIDTH"                       ,        28,     1,      290,    "R/W",  0,      1,      0ull,   0},
26115         {"ALE"                         ,        29,     1,      290,    "R/W",  0,      1,      0ull,   0},
26116         {"ORBIT"                       ,        30,     1,      290,    "R/W",  0,      1,      0ull,   0},
26117         {"EN"                          ,        31,     1,      290,    "R/W",  0,      1,      0ull,   0},
26118         {"OE_EXT"                      ,        32,     2,      290,    "R/W",  0,      1,      0ull,   0},
26119         {"WE_EXT"                      ,        34,     2,      290,    "R/W",  0,      1,      0ull,   0},
26120         {"SAM"                         ,        36,     1,      290,    "R/W",  0,      1,      0ull,   0},
26121         {"RESERVED_37_63"              ,        37,     27,     290,    "RAZ",  1,      1,      0,      0},
26122         {"ADR"                         ,        0,      6,      291,    "R/W",  0,      1,      63ull,  0},
26123         {"CE"                          ,        6,      6,      291,    "R/W",  0,      1,      63ull,  0},
26124         {"OE"                          ,        12,     6,      291,    "R/W",  0,      1,      63ull,  0},
26125         {"WE"                          ,        18,     6,      291,    "R/W",  0,      1,      63ull,  0},
26126         {"RD_HLD"                      ,        24,     6,      291,    "R/W",  0,      1,      63ull,  0},
26127         {"WR_HLD"                      ,        30,     6,      291,    "R/W",  0,      1,      63ull,  0},
26128         {"PAUSE"                       ,        36,     6,      291,    "R/W",  0,      1,      63ull,  0},
26129         {"WAIT"                        ,        42,     6,      291,    "R/W",  0,      1,      63ull,  0},
26130         {"PAGE"                        ,        48,     6,      291,    "R/W",  0,      1,      63ull,  0},
26131         {"ALE"                         ,        54,     6,      291,    "R/W",  0,      1,      63ull,  0},
26132         {"PAGES"                       ,        60,     2,      291,    "R/W",  0,      1,      0ull,   0},
26133         {"WAITM"                       ,        62,     1,      291,    "R/W",  0,      1,      0ull,   0},
26134         {"PAGEM"                       ,        63,     1,      291,    "R/W",  0,      1,      0ull,   0},
26135         {"FIF_THR"                     ,        0,      6,      292,    "R/W",  0,      0,      26ull,  26ull},
26136         {"RESERVED_6_7"                ,        6,      2,      292,    "RAZ",  1,      1,      0,      0},
26137         {"FIF_CNT"                     ,        8,      6,      292,    "RO",   0,      1,      0ull,   0},
26138         {"RESERVED_14_63"              ,        14,     50,     292,    "RAZ",  1,      1,      0,      0},
26139         {"DAT"                         ,        0,      64,     293,    "R/W",  1,      1,      0,      0},
26140         {"MAN_INFO"                    ,        0,      32,     294,    "RO",   1,      1,      0,      0},
26141         {"RESERVED_32_63"              ,        32,     32,     294,    "RAZ",  1,      1,      0,      0},
26142         {"MAN_INFO"                    ,        0,      32,     295,    "RO",   1,      1,      0,      0},
26143         {"RESERVED_32_63"              ,        32,     32,     295,    "RAZ",  1,      1,      0,      0},
26144         {"PP_DIS"                      ,        0,      16,     296,    "RO",   1,      1,      0,      0},
26145         {"CHIP_ID"                     ,        16,     8,      296,    "RO",   1,      1,      0,      0},
26146         {"BIST_DIS"                    ,        24,     1,      296,    "RO",   1,      1,      0,      0},
26147         {"RST_SHT"                     ,        25,     1,      296,    "RO",   1,      1,      0,      0},
26148         {"NOCRYPTO"                    ,        26,     1,      296,    "RO",   1,      1,      0,      0},
26149         {"NOMUL"                       ,        27,     1,      296,    "RO",   1,      1,      0,      0},
26150         {"NODFA_CP2"                   ,        28,     1,      296,    "RO",   1,      1,      0,      0},
26151         {"NOKASU"                      ,        29,     1,      296,    "RO",   1,      1,      0,      0},
26152         {"RESERVED_30_63"              ,        30,     34,     296,    "RAZ",  1,      1,      0,      0},
26153         {"ICACHE"                      ,        0,      24,     297,    "RO",   1,      1,      0,      0},
26154         {"NODFA_DTE"                   ,        24,     1,      297,    "RO",   1,      1,      0,      0},
26155         {"NOZIP"                       ,        25,     1,      297,    "RO",   1,      1,      0,      0},
26156         {"EFUS_IGN"                    ,        26,     1,      297,    "RO",   1,      1,      0,      0},
26157         {"EFUS_LCK"                    ,        27,     1,      297,    "RO",   1,      1,      0,      0},
26158         {"BAR2_EN"                     ,        28,     1,      297,    "RO",   1,      1,      0,      0},
26159         {"ZIP_CRIP"                    ,        29,     2,      297,    "RO",   1,      1,      0,      0},
26160         {"RESERVED_31_63"              ,        31,     33,     297,    "RAZ",  1,      1,      0,      0},
26161         {"EMA"                         ,        0,      2,      298,    "R/W",  1,      0,      0,      0ull},
26162         {"RESERVED_2_63"               ,        2,      62,     298,    "RAZ",  1,      1,      0,      0},
26163         {"FBSLIP"                      ,        0,      1,      299,    "R/W1C",        0,      1,      0ull,   0},
26164         {"RFSLIP"                      ,        1,      1,      299,    "R/W1C",        0,      1,      0ull,   0},
26165         {"RESERVED_2_63"               ,        2,      62,     299,    "RAZ",  1,      1,      0,      0},
26166         {"PROG"                        ,        0,      1,      300,    "R/W",  1,      1,      0,      0},
26167         {"RESERVED_1_63"               ,        1,      63,     300,    "RAZ",  1,      1,      0,      0},
26168         {"SETUP"                       ,        0,      8,      301,    "R/W",  0,      1,      3ull,   0},
26169         {"SCLK_HI"                     ,        8,      12,     301,    "R/W",  0,      1,      100ull, 0},
26170         {"SCLK_LO"                     ,        20,     4,      301,    "R/W",  0,      1,      2ull,   0},
26171         {"OUT"                         ,        24,     8,      301,    "R/W",  0,      1,      3ull,   0},
26172         {"PROG_PIN"                    ,        32,     1,      301,    "RO",   0,      0,      0ull,   0ull},
26173         {"RESERVED_33_63"              ,        33,     31,     301,    "RAZ",  1,      1,      0,      0},
26174         {"ADDR"                        ,        0,      7,      302,    "R/W",  0,      0,      0ull,   0ull},
26175         {"RESERVED_7_7"                ,        7,      1,      302,    "RAZ",  1,      1,      0,      0},
26176         {"EFUSE"                       ,        8,      1,      302,    "R/W",  0,      0,      0ull,   0ull},
26177         {"RESERVED_9_11"               ,        9,      3,      302,    "RAZ",  1,      1,      0,      0},
26178         {"PEND"                        ,        12,     1,      302,    "R/W",  0,      0,      0ull,   0ull},
26179         {"RESERVED_13_15"              ,        13,     3,      302,    "RAZ",  1,      1,      0,      0},
26180         {"DAT"                         ,        16,     8,      302,    "RO",   1,      1,      0,      0},
26181         {"RESERVED_24_63"              ,        24,     40,     302,    "RAZ",  1,      1,      0,      0},
26182         {"REPAIR0"                     ,        0,      14,     303,    "RO",   0,      0,      0ull,   0ull},
26183         {"REPAIR1"                     ,        14,     14,     303,    "RO",   0,      0,      0ull,   0ull},
26184         {"REPAIR2"                     ,        28,     14,     303,    "RO",   0,      0,      0ull,   0ull},
26185         {"RESERVED_42_63"              ,        42,     22,     303,    "RAZ",  1,      1,      0,      0},
26186         {"TOO_MANY"                    ,        0,      1,      304,    "RO",   0,      0,      0ull,   0ull},
26187         {"RESERVED_1_63"               ,        1,      63,     304,    "RAZ",  1,      1,      0,      0},
26188         {"ADDR"                        ,        0,      2,      305,    "R/W",  1,      1,      0,      0},
26189         {"RESERVED_2_63"               ,        2,      62,     305,    "RAZ",  1,      1,      0,      0},
26190         {"ST_INT"                      ,        0,      1,      306,    "R/W1C",        0,      1,      0ull,   0},
26191         {"TS_INT"                      ,        1,      1,      306,    "R/W1C",        0,      1,      0ull,   0},
26192         {"CORE_INT"                    ,        2,      1,      306,    "RO",   0,      1,      0ull,   0},
26193         {"RESERVED_3_3"                ,        3,      1,      306,    "RAZ",  1,      1,      0,      0},
26194         {"ST_EN"                       ,        4,      1,      306,    "R/W",  0,      1,      0ull,   0},
26195         {"TS_EN"                       ,        5,      1,      306,    "R/W",  0,      1,      0ull,   0},
26196         {"CORE_EN"                     ,        6,      1,      306,    "R/W",  0,      1,      0ull,   0},
26197         {"RESERVED_7_7"                ,        7,      1,      306,    "RAZ",  1,      1,      0,      0},
26198         {"SDA_OVR"                     ,        8,      1,      306,    "R/W",  0,      1,      0ull,   0},
26199         {"SCL_OVR"                     ,        9,      1,      306,    "R/W",  0,      1,      0ull,   0},
26200         {"SDA"                         ,        10,     1,      306,    "RO",   1,      1,      0,      0},
26201         {"SCL"                         ,        11,     1,      306,    "RO",   1,      1,      0,      0},
26202         {"RESERVED_12_63"              ,        12,     52,     306,    "RAZ",  1,      1,      0,      0},
26203         {"D"                           ,        0,      32,     307,    "R/W",  0,      1,      0ull,   0},
26204         {"EOP_IA"                      ,        32,     3,      307,    "R/W",  0,      1,      0ull,   0},
26205         {"IA"                          ,        35,     5,      307,    "R/W",  0,      1,      0ull,   0},
26206         {"A"                           ,        40,     10,     307,    "R/W",  0,      1,      0ull,   0},
26207         {"SCR"                         ,        50,     2,      307,    "R/W",  0,      1,      0ull,   0},
26208         {"SIZE"                        ,        52,     3,      307,    "R/W",  0,      1,      0ull,   0},
26209         {"SOVR"                        ,        55,     1,      307,    "R/W",  0,      1,      0ull,   0},
26210         {"R"                           ,        56,     1,      307,    "R/W",  0,      1,      0ull,   0},
26211         {"OP"                          ,        57,     4,      307,    "R/W",  0,      1,      0ull,   0},
26212         {"EIA"                         ,        61,     1,      307,    "R/W",  0,      1,      0ull,   0},
26213         {"SLONLY"                      ,        62,     1,      307,    "R/W",  0,      1,      0ull,   0},
26214         {"V"                           ,        63,     1,      307,    "RC/W", 0,      1,      0ull,   0},
26215         {"D"                           ,        0,      32,     308,    "R/W",  0,      1,      0ull,   0},
26216         {"IA"                          ,        32,     8,      308,    "R/W",  0,      1,      0ull,   0},
26217         {"RESERVED_40_63"              ,        40,     24,     308,    "RAZ",  1,      1,      0,      0},
26218         {"D"                           ,        0,      32,     309,    "R/W",  1,      1,      0,      0},
26219         {"RESERVED_32_61"              ,        32,     30,     309,    "RAZ",  1,      1,      0,      0},
26220         {"V"                           ,        62,     2,      309,    "RC/W", 0,      1,      0ull,   0},
26221         {"DLH"                         ,        0,      8,      310,    "R/W",  0,      1,      0ull,   0},
26222         {"RESERVED_8_63"               ,        8,      56,     310,    "RAZ",  1,      1,      0,      0},
26223         {"DLL"                         ,        0,      8,      311,    "R/W",  0,      1,      0ull,   0},
26224         {"RESERVED_8_63"               ,        8,      56,     311,    "RAZ",  1,      1,      0,      0},
26225         {"FAR"                         ,        0,      1,      312,    "R/W",  0,      1,      0ull,   0},
26226         {"RESERVED_1_63"               ,        1,      63,     312,    "RAZ",  1,      1,      0,      0},
26227         {"EN"                          ,        0,      1,      313,    "WO",   0,      1,      0ull,   0},
26228         {"RXFR"                        ,        1,      1,      313,    "WO",   0,      1,      0ull,   0},
26229         {"TXFR"                        ,        2,      1,      313,    "WO",   0,      1,      0ull,   0},
26230         {"RESERVED_3_3"                ,        3,      1,      313,    "RAZ",  0,      1,      0ull,   0},
26231         {"TXTRIG"                      ,        4,      2,      313,    "WO",   0,      1,      0ull,   0},
26232         {"RXTRIG"                      ,        6,      2,      313,    "WO",   0,      1,      0ull,   0},
26233         {"RESERVED_8_63"               ,        8,      56,     313,    "RAZ",  1,      1,      0,      0},
26234         {"HTX"                         ,        0,      1,      314,    "R/W",  0,      1,      0ull,   0},
26235         {"RESERVED_1_63"               ,        1,      63,     314,    "RAZ",  1,      1,      0,      0},
26236         {"ERBFI"                       ,        0,      1,      315,    "R/W",  0,      1,      0ull,   0},
26237         {"ETBEI"                       ,        1,      1,      315,    "R/W",  0,      1,      0ull,   0},
26238         {"ELSI"                        ,        2,      1,      315,    "R/W",  0,      1,      0ull,   0},
26239         {"EDSSI"                       ,        3,      1,      315,    "R/W",  0,      1,      0ull,   0},
26240         {"RESERVED_4_6"                ,        4,      3,      315,    "RAZ",  0,      1,      0ull,   0},
26241         {"PTIME"                       ,        7,      1,      315,    "R/W",  0,      1,      0ull,   0},
26242         {"RESERVED_8_63"               ,        8,      56,     315,    "RAZ",  1,      1,      0,      0},
26243         {"IID"                         ,        0,      4,      316,    "RO",   0,      1,      1ull,   0},
26244         {"RESERVED_4_5"                ,        4,      2,      316,    "RAZ",  0,      1,      0ull,   0},
26245         {"FEN"                         ,        6,      2,      316,    "RO",   0,      1,      0ull,   0},
26246         {"RESERVED_8_63"               ,        8,      56,     316,    "RAZ",  1,      1,      0,      0},
26247         {"CLS"                         ,        0,      2,      317,    "R/W",  0,      1,      0ull,   0},
26248         {"STOP"                        ,        2,      1,      317,    "R/W",  0,      1,      0ull,   0},
26249         {"PEN"                         ,        3,      1,      317,    "R/W",  0,      1,      0ull,   0},
26250         {"EPS"                         ,        4,      1,      317,    "R/W",  0,      1,      0ull,   0},
26251         {"RESERVED_5_5"                ,        5,      1,      317,    "RAZ",  0,      1,      0ull,   0},
26252         {"BRK"                         ,        6,      1,      317,    "R/W",  0,      1,      0ull,   0},
26253         {"DLAB"                        ,        7,      1,      317,    "R/W",  0,      1,      0ull,   0},
26254         {"RESERVED_8_63"               ,        8,      56,     317,    "RAZ",  1,      1,      0,      0},
26255         {"DR"                          ,        0,      1,      318,    "RO",   0,      1,      0ull,   0},
26256         {"OE"                          ,        1,      1,      318,    "RC",   0,      1,      0ull,   0},
26257         {"PE"                          ,        2,      1,      318,    "RC",   0,      1,      0ull,   0},
26258         {"FE"                          ,        3,      1,      318,    "RC",   0,      1,      0ull,   0},
26259         {"BI"                          ,        4,      1,      318,    "RC",   0,      1,      0ull,   0},
26260         {"THRE"                        ,        5,      1,      318,    "RO",   0,      1,      1ull,   0},
26261         {"TEMT"                        ,        6,      1,      318,    "RO",   0,      1,      1ull,   0},
26262         {"FERR"                        ,        7,      1,      318,    "RC",   0,      1,      0ull,   0},
26263         {"RESERVED_8_63"               ,        8,      56,     318,    "RAZ",  1,      1,      0,      0},
26264         {"DTR"                         ,        0,      1,      319,    "R/W",  0,      1,      0ull,   0},
26265         {"RTS"                         ,        1,      1,      319,    "R/W",  0,      1,      0ull,   0},
26266         {"OUT1"                        ,        2,      1,      319,    "R/W",  0,      1,      0ull,   0},
26267         {"OUT2"                        ,        3,      1,      319,    "R/W",  0,      1,      0ull,   0},
26268         {"LOOP"                        ,        4,      1,      319,    "R/W",  0,      1,      0ull,   0},
26269         {"AFCE"                        ,        5,      1,      319,    "R/W",  0,      1,      0ull,   0},
26270         {"RESERVED_6_63"               ,        6,      58,     319,    "RAZ",  0,      1,      0ull,   0},
26271         {"DCTS"                        ,        0,      1,      320,    "RC",   0,      1,      0ull,   0},
26272         {"DDSR"                        ,        1,      1,      320,    "RC",   0,      1,      0ull,   0},
26273         {"TERI"                        ,        2,      1,      320,    "RC",   0,      1,      0ull,   0},
26274         {"DDCD"                        ,        3,      1,      320,    "RC",   0,      1,      0ull,   0},
26275         {"CTS"                         ,        4,      1,      320,    "RO",   1,      1,      0,      0},
26276         {"DSR"                         ,        5,      1,      320,    "RO",   0,      1,      0ull,   0},
26277         {"RI"                          ,        6,      1,      320,    "RO",   0,      1,      0ull,   0},
26278         {"DCD"                         ,        7,      1,      320,    "RO",   0,      1,      0ull,   0},
26279         {"RESERVED_8_63"               ,        8,      56,     320,    "RAZ",  1,      1,      0,      0},
26280         {"RBR"                         ,        0,      8,      321,    "RO",   0,      1,      0ull,   0},
26281         {"RESERVED_8_63"               ,        8,      56,     321,    "RAZ",  1,      1,      0,      0},
26282         {"RFL"                         ,        0,      7,      322,    "RO",   0,      1,      0ull,   0},
26283         {"RESERVED_7_63"               ,        7,      57,     322,    "RAZ",  1,      1,      0,      0},
26284         {"RFWD"                        ,        0,      8,      323,    "WO",   0,      1,      0ull,   0},
26285         {"RFPE"                        ,        8,      1,      323,    "WO",   0,      1,      0ull,   0},
26286         {"RFFE"                        ,        9,      1,      323,    "WO",   0,      1,      0ull,   0},
26287         {"RESERVED_10_63"              ,        10,     54,     323,    "RAZ",  1,      1,      0,      0},
26288         {"SBCR"                        ,        0,      1,      324,    "R/W",  0,      1,      0ull,   0},
26289         {"RESERVED_1_63"               ,        1,      63,     324,    "RAZ",  1,      1,      0,      0},
26290         {"SCR"                         ,        0,      8,      325,    "R/W",  0,      1,      0ull,   0},
26291         {"RESERVED_8_63"               ,        8,      56,     325,    "RAZ",  1,      1,      0,      0},
26292         {"SFE"                         ,        0,      1,      326,    "R/W",  0,      1,      0ull,   0},
26293         {"RESERVED_1_63"               ,        1,      63,     326,    "RAZ",  1,      1,      0,      0},
26294         {"USR"                         ,        0,      1,      327,    "WO",   0,      1,      0ull,   0},
26295         {"SRFR"                        ,        1,      1,      327,    "WO",   0,      1,      0ull,   0},
26296         {"STFR"                        ,        2,      1,      327,    "WO",   0,      1,      0ull,   0},
26297         {"RESERVED_3_63"               ,        3,      61,     327,    "RAZ",  1,      1,      0,      0},
26298         {"SRT"                         ,        0,      2,      328,    "R/W",  0,      1,      0ull,   0},
26299         {"RESERVED_2_63"               ,        2,      62,     328,    "RAZ",  1,      1,      0,      0},
26300         {"SRTS"                        ,        0,      1,      329,    "R/W",  0,      1,      0ull,   0},
26301         {"RESERVED_1_63"               ,        1,      63,     329,    "RAZ",  1,      1,      0,      0},
26302         {"STT"                         ,        0,      2,      330,    "R/W",  0,      1,      0ull,   0},
26303         {"RESERVED_2_63"               ,        2,      62,     330,    "RAZ",  1,      1,      0,      0},
26304         {"TFL"                         ,        0,      7,      331,    "RO",   0,      1,      0ull,   0},
26305         {"RESERVED_7_63"               ,        7,      57,     331,    "RAZ",  1,      1,      0,      0},
26306         {"TFR"                         ,        0,      8,      332,    "RO",   0,      1,      0ull,   0},
26307         {"RESERVED_8_63"               ,        8,      56,     332,    "RAZ",  1,      1,      0,      0},
26308         {"THR"                         ,        0,      8,      333,    "WO",   0,      1,      0ull,   0},
26309         {"RESERVED_8_63"               ,        8,      56,     333,    "RAZ",  1,      1,      0,      0},
26310         {"BUSY"                        ,        0,      1,      334,    "RO",   0,      1,      0ull,   0},
26311         {"TFNF"                        ,        1,      1,      334,    "RO",   0,      1,      1ull,   0},
26312         {"TFE"                         ,        2,      1,      334,    "RO",   0,      1,      1ull,   0},
26313         {"RFNE"                        ,        3,      1,      334,    "RO",   0,      1,      0ull,   0},
26314         {"RFF"                         ,        4,      1,      334,    "RO",   0,      1,      0ull,   0},
26315         {"RESERVED_5_63"               ,        5,      59,     334,    "RAZ",  1,      1,      0,      0},
26316         {"RESERVED_0_2"                ,        0,      3,      335,    "RAZ",  1,      1,      0,      0},
26317         {"BADDR"                       ,        3,      61,     335,    "R/W",  0,      1,      0ull,   0},
26318         {"RESERVED_0_2"                ,        0,      3,      336,    "RAZ",  1,      1,      0,      0},
26319         {"BADDR"                       ,        3,      61,     336,    "R/W",  0,      1,      0ull,   0},
26320         {"DPI_BS"                      ,        0,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26321         {"PDF_BS"                      ,        1,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26322         {"DOB_BS"                      ,        2,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26323         {"NUS_BS"                      ,        3,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26324         {"POS_BS"                      ,        4,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26325         {"POF3_BS"                     ,        5,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26326         {"POF2_BS"                     ,        6,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26327         {"POF1_BS"                     ,        7,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26328         {"POF0_BS"                     ,        8,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26329         {"PIG_BS"                      ,        9,      1,      337,    "RO",   0,      0,      0ull,   0ull},
26330         {"PGF_BS"                      ,        10,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26331         {"RDNL_BS"                     ,        11,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26332         {"PCAD_BS"                     ,        12,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26333         {"PCAC_BS"                     ,        13,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26334         {"RDN_BS"                      ,        14,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26335         {"PCN_BS"                      ,        15,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26336         {"PCNC_BS"                     ,        16,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26337         {"RDP_BS"                      ,        17,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26338         {"DIF_BS"                      ,        18,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26339         {"CSR_BS"                      ,        19,     1,      337,    "RO",   0,      0,      0ull,   0ull},
26340         {"RESERVED_20_63"              ,        20,     44,     337,    "RAZ",  1,      1,      0,      0},
26341         {"BSIZE"                       ,        0,      16,     338,    "R/W",  0,      1,      1024ull,        0},
26342         {"ISIZE"                       ,        16,     7,      338,    "R/W",  0,      1,      0ull,   0},
26343         {"RESERVED_23_63"              ,        23,     41,     338,    "RAZ",  1,      1,      0,      0},
26344         {"NCTL"                        ,        0,      5,      339,    "R/W",  0,      1,      16ull,  0},
26345         {"PCTL"                        ,        5,      5,      339,    "R/W",  0,      1,      16ull,  0},
26346         {"RESERVED_10_63"              ,        10,     54,     339,    "RAZ",  1,      1,      0,      0},
26347         {"TIMER"                       ,        0,      10,     340,    "R/W",  0,      0,      0ull,   50ull},
26348         {"RESERVED_10_31"              ,        10,     22,     340,    "RAZ",  0,      0,      0ull,   0ull},
26349         {"MAX_WORD"                    ,        32,     5,      340,    "R/W",  0,      0,      2ull,   0ull},
26350         {"RESERVED_37_39"              ,        37,     3,      340,    "RAZ",  0,      0,      0ull,   0ull},
26351         {"WAIT_COM"                    ,        40,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26352         {"PCI_WDIS"                    ,        41,     1,      340,    "R/W",  0,      0,      0ull,   0ull},
26353         {"INS0_64B"                    ,        42,     1,      340,    "R/W",  0,      1,      0ull,   0},
26354         {"INS1_64B"                    ,        43,     1,      340,    "R/W",  0,      1,      0ull,   0},
26355         {"INS2_64B"                    ,        44,     1,      340,    "R/W",  0,      1,      0ull,   0},
26356         {"INS3_64B"                    ,        45,     1,      340,    "R/W",  0,      1,      0ull,   0},
26357         {"INS0_ENB"                    ,        46,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26358         {"INS1_ENB"                    ,        47,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26359         {"INS2_ENB"                    ,        48,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26360         {"INS3_ENB"                    ,        49,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26361         {"OUT0_ENB"                    ,        50,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26362         {"OUT1_ENB"                    ,        51,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26363         {"OUT2_ENB"                    ,        52,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26364         {"OUT3_ENB"                    ,        53,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26365         {"DIS_PNIW"                    ,        54,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
26366         {"CHIP_REV"                    ,        55,     8,      340,    "RO",   1,      1,      0,      0},
26367         {"RESERVED_63_63"              ,        63,     1,      340,    "RAZ",  1,      1,      0,      0},
26368         {"DBG_SEL"                     ,        0,      16,     341,    "R/W",  0,      1,      0ull,   0},
26369         {"RESERVED_16_63"              ,        16,     48,     341,    "RAZ",  1,      1,      0,      0},
26370         {"CSIZE"                       ,        0,      14,     342,    "R/W",  0,      1,      0ull,   0},
26371         {"LP_ENB"                      ,        14,     1,      342,    "R/W",  0,      0,      0ull,   1ull},
26372         {"HP_ENB"                      ,        15,     1,      342,    "R/W",  0,      0,      0ull,   1ull},
26373         {"O_MODE"                      ,        16,     1,      342,    "R/W",  0,      0,      0ull,   1ull},
26374         {"O_ES"                        ,        17,     2,      342,    "R/W",  0,      1,      0ull,   0},
26375         {"O_NS"                        ,        19,     1,      342,    "R/W",  0,      1,      0ull,   0},
26376         {"O_RO"                        ,        20,     1,      342,    "R/W",  0,      1,      0ull,   0},
26377         {"O_ADD1"                      ,        21,     1,      342,    "R/W",  0,      0,      0ull,   1ull},
26378         {"FPA_QUE"                     ,        22,     3,      342,    "R/W",  0,      1,      0ull,   0},
26379         {"DWB_ICHK"                    ,        25,     9,      342,    "R/W",  0,      1,      0ull,   0},
26380         {"DWB_DENB"                    ,        34,     1,      342,    "R/W",  0,      0,      0ull,   1ull},
26381         {"B0_LEND"                     ,        35,     1,      342,    "R/W",  0,      0,      0ull,   0ull},
26382         {"RESERVED_36_63"              ,        36,     28,     342,    "RAZ",  1,      1,      0,      0},
26383         {"DBELL"                       ,        0,      32,     343,    "RO",   0,      0,      0ull,   0ull},
26384         {"FCNT"                        ,        32,     7,      343,    "RO",   0,      0,      0ull,   0ull},
26385         {"RESERVED_39_63"              ,        39,     25,     343,    "RAZ",  1,      1,      0,      0},
26386         {"ADDR"                        ,        0,      36,     344,    "RO",   0,      1,      0ull,   0},
26387         {"STATE"                       ,        36,     4,      344,    "RO",   0,      0,      0ull,   0ull},
26388         {"RESERVED_40_63"              ,        40,     24,     344,    "RAZ",  1,      1,      0,      0},
26389         {"DBELL"                       ,        0,      32,     345,    "RO",   0,      0,      0ull,   0ull},
26390         {"FCNT"                        ,        32,     7,      345,    "RO",   0,      0,      0ull,   0ull},
26391         {"RESERVED_39_63"              ,        39,     25,     345,    "RAZ",  1,      1,      0,      0},
26392         {"ADDR"                        ,        0,      36,     346,    "RO",   0,      1,      0ull,   0},
26393         {"STATE"                       ,        36,     4,      346,    "RO",   0,      0,      0ull,   0ull},
26394         {"RESERVED_40_63"              ,        40,     24,     346,    "RAZ",  1,      1,      0,      0},
26395         {"DBELL"                       ,        0,      16,     347,    "R/W",  0,      1,      0ull,   0},
26396         {"RESERVED_16_63"              ,        16,     48,     347,    "RAZ",  1,      1,      0,      0},
26397         {"SADDR"                       ,        0,      36,     348,    "R/W",  0,      1,      0ull,   0},
26398         {"RESERVED_36_63"              ,        36,     28,     348,    "RAZ",  1,      1,      0,      0},
26399         {"ROR"                         ,        0,      1,      349,    "R/W",  0,      1,      0ull,   0},
26400         {"ESR"                         ,        1,      2,      349,    "R/W",  0,      1,      0ull,   0},
26401         {"NSR"                         ,        3,      1,      349,    "R/W",  0,      1,      0ull,   0},
26402         {"USE_CSR"                     ,        4,      1,      349,    "R/W",  0,      0,      0ull,   1ull},
26403         {"D_ROR"                       ,        5,      1,      349,    "R/W",  0,      1,      0ull,   0},
26404         {"D_ESR"                       ,        6,      2,      349,    "R/W",  0,      1,      0ull,   0},
26405         {"D_NSR"                       ,        8,      1,      349,    "R/W",  0,      1,      0ull,   0},
26406         {"PBP_DHI"                     ,        9,      13,     349,    "R/W",  0,      1,      0ull,   0},
26407         {"PKT_RR"                      ,        22,     1,      349,    "R/W",  0,      0,      0ull,   0ull},
26408         {"RESERVED_23_63"              ,        23,     41,     349,    "RAZ",  1,      1,      0,      0},
26409         {"RML_RTO"                     ,        0,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26410         {"RML_WTO"                     ,        1,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26411         {"PCI_RSL"                     ,        2,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26412         {"PO0_2SML"                    ,        3,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26413         {"PO1_2SML"                    ,        4,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26414         {"PO2_2SML"                    ,        5,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26415         {"PO3_2SML"                    ,        6,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26416         {"I0_RTOUT"                    ,        7,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26417         {"I1_RTOUT"                    ,        8,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26418         {"I2_RTOUT"                    ,        9,      1,      350,    "R/W",  0,      0,      0ull,   1ull},
26419         {"I3_RTOUT"                    ,        10,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26420         {"I0_OVERF"                    ,        11,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26421         {"I1_OVERF"                    ,        12,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26422         {"I2_OVERF"                    ,        13,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26423         {"I3_OVERF"                    ,        14,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26424         {"P0_RTOUT"                    ,        15,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26425         {"P1_RTOUT"                    ,        16,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26426         {"P2_RTOUT"                    ,        17,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26427         {"P3_RTOUT"                    ,        18,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26428         {"P0_PERR"                     ,        19,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26429         {"P1_PERR"                     ,        20,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26430         {"P2_PERR"                     ,        21,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26431         {"P3_PERR"                     ,        22,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26432         {"G0_RTOUT"                    ,        23,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26433         {"G1_RTOUT"                    ,        24,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26434         {"G2_RTOUT"                    ,        25,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26435         {"G3_RTOUT"                    ,        26,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26436         {"P0_PPERR"                    ,        27,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26437         {"P1_PPERR"                    ,        28,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26438         {"P2_PPERR"                    ,        29,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26439         {"P3_PPERR"                    ,        30,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26440         {"P0_PTOUT"                    ,        31,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26441         {"P1_PTOUT"                    ,        32,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26442         {"P2_PTOUT"                    ,        33,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26443         {"P3_PTOUT"                    ,        34,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26444         {"I0_PPERR"                    ,        35,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26445         {"I1_PPERR"                    ,        36,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26446         {"I2_PPERR"                    ,        37,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26447         {"I3_PPERR"                    ,        38,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26448         {"WIN_RTO"                     ,        39,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26449         {"P_DPERR"                     ,        40,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26450         {"IOBDMA"                      ,        41,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26451         {"FCR_S_E"                     ,        42,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26452         {"FCR_A_F"                     ,        43,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26453         {"PCR_S_E"                     ,        44,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26454         {"PCR_A_F"                     ,        45,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26455         {"Q2_S_E"                      ,        46,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26456         {"Q2_A_F"                      ,        47,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26457         {"Q3_S_E"                      ,        48,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26458         {"Q3_A_F"                      ,        49,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26459         {"COM_S_E"                     ,        50,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26460         {"COM_A_F"                     ,        51,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26461         {"PNC_S_E"                     ,        52,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26462         {"PNC_A_F"                     ,        53,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26463         {"RWX_S_E"                     ,        54,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26464         {"RDX_S_E"                     ,        55,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26465         {"PCF_P_E"                     ,        56,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26466         {"PCF_P_F"                     ,        57,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26467         {"PDF_P_E"                     ,        58,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26468         {"PDF_P_F"                     ,        59,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26469         {"Q1_S_E"                      ,        60,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26470         {"Q1_A_F"                      ,        61,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
26471         {"RESERVED_62_63"              ,        62,     2,      350,    "RAZ",  1,      1,      0,      0},
26472         {"RML_RTO"                     ,        0,      1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26473         {"RML_WTO"                     ,        1,      1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26474         {"PCI_RSL"                     ,        2,      1,      351,    "RO",   0,      0,      0ull,   0ull},
26475         {"PO0_2SML"                    ,        3,      1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26476         {"PO1_2SML"                    ,        4,      1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26477         {"PO2_2SML"                    ,        5,      1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26478         {"PO3_2SML"                    ,        6,      1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26479         {"I0_RTOUT"                    ,        7,      1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26480         {"I1_RTOUT"                    ,        8,      1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26481         {"I2_RTOUT"                    ,        9,      1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26482         {"I3_RTOUT"                    ,        10,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26483         {"I0_OVERF"                    ,        11,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26484         {"I1_OVERF"                    ,        12,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26485         {"I2_OVERF"                    ,        13,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26486         {"I3_OVERF"                    ,        14,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26487         {"P0_RTOUT"                    ,        15,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26488         {"P1_RTOUT"                    ,        16,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26489         {"P2_RTOUT"                    ,        17,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26490         {"P3_RTOUT"                    ,        18,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26491         {"P0_PERR"                     ,        19,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26492         {"P1_PERR"                     ,        20,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26493         {"P2_PERR"                     ,        21,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26494         {"P3_PERR"                     ,        22,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26495         {"G0_RTOUT"                    ,        23,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26496         {"G1_RTOUT"                    ,        24,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26497         {"G2_RTOUT"                    ,        25,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26498         {"G3_RTOUT"                    ,        26,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26499         {"P0_PPERR"                    ,        27,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26500         {"P1_PPERR"                    ,        28,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26501         {"P2_PPERR"                    ,        29,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26502         {"P3_PPERR"                    ,        30,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26503         {"P0_PTOUT"                    ,        31,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26504         {"P1_PTOUT"                    ,        32,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26505         {"P2_PTOUT"                    ,        33,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26506         {"P3_PTOUT"                    ,        34,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26507         {"I0_PPERR"                    ,        35,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26508         {"I1_PPERR"                    ,        36,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26509         {"I2_PPERR"                    ,        37,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26510         {"I3_PPERR"                    ,        38,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26511         {"WIN_RTO"                     ,        39,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26512         {"P_DPERR"                     ,        40,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26513         {"IOBDMA"                      ,        41,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26514         {"FCR_S_E"                     ,        42,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26515         {"FCR_A_F"                     ,        43,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26516         {"PCR_S_E"                     ,        44,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26517         {"PCR_A_F"                     ,        45,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26518         {"Q2_S_E"                      ,        46,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26519         {"Q2_A_F"                      ,        47,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26520         {"Q3_S_E"                      ,        48,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26521         {"Q3_A_F"                      ,        49,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26522         {"COM_S_E"                     ,        50,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26523         {"COM_A_F"                     ,        51,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26524         {"PNC_S_E"                     ,        52,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26525         {"PNC_A_F"                     ,        53,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26526         {"RWX_S_E"                     ,        54,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26527         {"RDX_S_E"                     ,        55,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26528         {"PCF_P_E"                     ,        56,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26529         {"PCF_P_F"                     ,        57,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26530         {"PDF_P_E"                     ,        58,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26531         {"PDF_P_F"                     ,        59,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26532         {"Q1_S_E"                      ,        60,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26533         {"Q1_A_F"                      ,        61,     1,      351,    "R/W1C",        0,      0,      0ull,   0ull},
26534         {"RESERVED_62_63"              ,        62,     2,      351,    "RAZ",  1,      1,      0,      0},
26535         {"DBELL"                       ,        0,      16,     352,    "R/W",  0,      1,      0ull,   0},
26536         {"RESERVED_16_63"              ,        16,     48,     352,    "RAZ",  1,      1,      0,      0},
26537         {"SADDR"                       ,        0,      36,     353,    "R/W",  0,      1,      0ull,   0},
26538         {"RESERVED_36_63"              ,        36,     28,     353,    "RAZ",  1,      1,      0,      0},
26539         {"BA"                          ,        0,      28,     354,    "R/W",  0,      1,      0ull,   0},
26540         {"ROW"                         ,        28,     1,      354,    "R/W",  0,      1,      0ull,   0},
26541         {"ROR"                         ,        29,     1,      354,    "R/W",  0,      1,      0ull,   0},
26542         {"NSW"                         ,        30,     1,      354,    "R/W",  0,      1,      0ull,   0},
26543         {"NSR"                         ,        31,     1,      354,    "R/W",  0,      1,      0ull,   0},
26544         {"ESW"                         ,        32,     2,      354,    "R/W",  0,      1,      0ull,   0},
26545         {"ESR"                         ,        34,     2,      354,    "R/W",  0,      1,      0ull,   0},
26546         {"NMERGE"                      ,        36,     1,      354,    "R/W",  0,      1,      0ull,   0},
26547         {"SHORTL"                      ,        37,     1,      354,    "R/W",  0,      1,      0ull,   0},
26548         {"RESERVED_38_63"              ,        38,     26,     354,    "RAZ",  1,      1,      0,      0},
26549         {"INT_VEC"                     ,        0,      64,     355,    "R/W1C",        0,      0,      0ull,   0ull},
26550         {"SIZE"                        ,        0,      32,     356,    "R/W",  0,      1,      0ull,   0},
26551         {"RESERVED_32_63"              ,        32,     32,     356,    "RAZ",  1,      1,      0,      0},
26552         {"ROR_SL0"                     ,        0,      1,      357,    "R/W",  0,      1,      0ull,   0},
26553         {"NSR_SL0"                     ,        1,      1,      357,    "R/W",  0,      1,      0ull,   0},
26554         {"ESR_SL0"                     ,        2,      2,      357,    "R/W",  0,      1,      0ull,   0},
26555         {"ROR_SL1"                     ,        4,      1,      357,    "R/W",  0,      1,      0ull,   0},
26556         {"NSR_SL1"                     ,        5,      1,      357,    "R/W",  0,      1,      0ull,   0},
26557         {"ESR_SL1"                     ,        6,      2,      357,    "R/W",  0,      1,      0ull,   0},
26558         {"ROR_SL2"                     ,        8,      1,      357,    "R/W",  0,      1,      0ull,   0},
26559         {"NSR_SL2"                     ,        9,      1,      357,    "R/W",  0,      1,      0ull,   0},
26560         {"ESR_SL2"                     ,        10,     2,      357,    "R/W",  0,      1,      0ull,   0},
26561         {"ROR_SL3"                     ,        12,     1,      357,    "R/W",  0,      1,      0ull,   0},
26562         {"NSR_SL3"                     ,        13,     1,      357,    "R/W",  0,      1,      0ull,   0},
26563         {"ESR_SL3"                     ,        14,     2,      357,    "R/W",  0,      1,      0ull,   0},
26564         {"IPTR_O0"                     ,        16,     1,      357,    "R/W",  0,      0,      0ull,   1ull},
26565         {"IPTR_O1"                     ,        17,     1,      357,    "R/W",  0,      0,      0ull,   1ull},
26566         {"IPTR_O2"                     ,        18,     1,      357,    "R/W",  0,      0,      0ull,   1ull},
26567         {"IPTR_O3"                     ,        19,     1,      357,    "R/W",  0,      0,      0ull,   1ull},
26568         {"RESERVED_20_23"              ,        20,     4,      357,    "RAZ",  0,      0,      0ull,   0ull},
26569         {"O0_CSRM"                     ,        24,     1,      357,    "R/W",  0,      0,      0ull,   1ull},
26570         {"O1_CSRM"                     ,        25,     1,      357,    "R/W",  0,      0,      0ull,   1ull},
26571         {"O2_CSRM"                     ,        26,     1,      357,    "R/W",  0,      0,      0ull,   1ull},
26572         {"O3_CSRM"                     ,        27,     1,      357,    "R/W",  0,      0,      0ull,   1ull},
26573         {"O0_RO"                       ,        28,     1,      357,    "R/W",  0,      1,      0ull,   0},
26574         {"O0_NS"                       ,        29,     1,      357,    "R/W",  0,      1,      0ull,   0},
26575         {"O0_ES"                       ,        30,     2,      357,    "R/W",  0,      1,      0ull,   0},
26576         {"O1_RO"                       ,        32,     1,      357,    "R/W",  0,      1,      0ull,   0},
26577         {"O1_NS"                       ,        33,     1,      357,    "R/W",  0,      1,      0ull,   0},
26578         {"O1_ES"                       ,        34,     2,      357,    "R/W",  0,      1,      0ull,   0},
26579         {"O2_RO"                       ,        36,     1,      357,    "R/W",  0,      1,      0ull,   0},
26580         {"O2_NS"                       ,        37,     1,      357,    "R/W",  0,      1,      0ull,   0},
26581         {"O2_ES"                       ,        38,     2,      357,    "R/W",  0,      1,      0ull,   0},
26582         {"O3_RO"                       ,        40,     1,      357,    "R/W",  0,      1,      0ull,   0},
26583         {"O3_NS"                       ,        41,     1,      357,    "R/W",  0,      1,      0ull,   0},
26584         {"O3_ES"                       ,        42,     2,      357,    "R/W",  0,      1,      0ull,   0},
26585         {"P0_BMODE"                    ,        44,     1,      357,    "R/W",  0,      0,      0ull,   0ull},
26586         {"P1_BMODE"                    ,        45,     1,      357,    "R/W",  0,      0,      0ull,   0ull},
26587         {"P2_BMODE"                    ,        46,     1,      357,    "R/W",  0,      0,      0ull,   0ull},
26588         {"P3_BMODE"                    ,        47,     1,      357,    "R/W",  0,      0,      0ull,   0ull},
26589         {"PKT_RR"                      ,        48,     1,      357,    "R/W",  0,      0,      0ull,   0ull},
26590         {"RESERVED_49_63"              ,        49,     15,     357,    "RAZ",  1,      1,      0,      0},
26591         {"NADDR"                       ,        0,      61,     358,    "RO",   0,      1,      0ull,   0},
26592         {"STATE"                       ,        61,     2,      358,    "RO",   0,      0,      0ull,   0ull},
26593         {"RESERVED_63_63"              ,        63,     1,      358,    "RAZ",  1,      1,      0,      0},
26594         {"NADDR"                       ,        0,      61,     359,    "RO",   0,      1,      0ull,   0},
26595         {"STATE"                       ,        61,     3,      359,    "RO",   0,      0,      0ull,   0ull},
26596         {"AVAIL"                       ,        0,      32,     360,    "RO",   0,      0,      0ull,   0ull},
26597         {"FCNT"                        ,        32,     6,      360,    "RO",   0,      0,      0ull,   0ull},
26598         {"RESERVED_38_63"              ,        38,     26,     360,    "RAZ",  1,      1,      0,      0},
26599         {"AVAIL"                       ,        0,      32,     361,    "RO",   0,      0,      0ull,   0ull},
26600         {"FCNT"                        ,        32,     5,      361,    "RO",   0,      0,      0ull,   0ull},
26601         {"RESERVED_37_63"              ,        37,     27,     361,    "RAZ",  1,      1,      0,      0},
26602         {"RD_BRST"                     ,        0,      7,      362,    "R/W",  0,      0,      17ull,  64ull},
26603         {"WR_BRST"                     ,        7,      7,      362,    "R/W",  0,      0,      16ull,  64ull},
26604         {"RESERVED_14_63"              ,        14,     50,     362,    "RAZ",  1,      1,      0,      0},
26605         {"PARK_DEV"                    ,        0,      3,      363,    "R/W",  0,      1,      0ull,   0},
26606         {"PARK_MOD"                    ,        3,      1,      363,    "R/W",  0,      1,      0ull,   0},
26607         {"EN"                          ,        4,      1,      363,    "R/W",  0,      1,      0ull,   0},
26608         {"RESERVED_5_7"                ,        5,      3,      363,    "RAZ",  1,      1,      0,      0},
26609         {"PCI_OVR"                     ,        8,      4,      363,    "R/W",  0,      1,      0ull,   0},
26610         {"HOSTMODE"                    ,        12,     1,      363,    "RO",   1,      1,      0,      0},
26611         {"RESERVED_13_63"              ,        13,     51,     363,    "RAZ",  1,      1,      0,      0},
26612         {"CMD_SIZE"                    ,        0,      11,     364,    "R/W",  0,      0,      9ull,   9ull},
26613         {"RESERVED_11_63"              ,        11,     53,     364,    "RAZ",  1,      1,      0,      0},
26614         {"RSV_A"                       ,        0,      6,      365,    "R/W",  0,      1,      0ull,   0},
26615         {"SKP_LEN"                     ,        6,      7,      365,    "R/W",  0,      1,      0ull,   0},
26616         {"RSV_B"                       ,        13,     1,      365,    "R/W",  0,      1,      0ull,   0},
26617         {"PAR_MODE"                    ,        14,     2,      365,    "R/W",  0,      1,      0ull,   0},
26618         {"RSV_C"                       ,        16,     5,      365,    "R/W",  0,      1,      0ull,   0},
26619         {"USE_IHDR"                    ,        21,     1,      365,    "R/W",  0,      1,      0ull,   0},
26620         {"RSV_D"                       ,        22,     6,      365,    "R/W",  0,      1,      0ull,   0},
26621         {"RSKP_LEN"                    ,        28,     7,      365,    "R/W",  0,      1,      8ull,   0},
26622         {"RSV_E"                       ,        35,     1,      365,    "R/W",  0,      1,      0ull,   0},
26623         {"RPARMODE"                    ,        36,     2,      365,    "R/W",  0,      1,      0ull,   0},
26624         {"RSV_F"                       ,        38,     5,      365,    "R/W",  0,      1,      0ull,   0},
26625         {"PBP"                         ,        43,     1,      365,    "R/W",  0,      1,      0ull,   0},
26626         {"RESERVED_44_63"              ,        44,     20,     365,    "RAZ",  1,      1,      0,      0},
26627         {"RSV_A"                       ,        0,      6,      366,    "R/W",  0,      1,      0ull,   0},
26628         {"SKP_LEN"                     ,        6,      7,      366,    "R/W",  0,      1,      0ull,   0},
26629         {"RSV_B"                       ,        13,     1,      366,    "R/W",  0,      1,      0ull,   0},
26630         {"PAR_MODE"                    ,        14,     2,      366,    "R/W",  0,      1,      0ull,   0},
26631         {"RSV_C"                       ,        16,     5,      366,    "R/W",  0,      1,      0ull,   0},
26632         {"USE_IHDR"                    ,        21,     1,      366,    "R/W",  0,      1,      0ull,   0},
26633         {"RSV_D"                       ,        22,     6,      366,    "R/W",  0,      1,      0ull,   0},
26634         {"RSKP_LEN"                    ,        28,     7,      366,    "R/W",  0,      1,      8ull,   0},
26635         {"RSV_E"                       ,        35,     1,      366,    "R/W",  0,      1,      0ull,   0},
26636         {"RPARMODE"                    ,        36,     2,      366,    "R/W",  0,      1,      0ull,   0},
26637         {"RSV_F"                       ,        38,     5,      366,    "R/W",  0,      1,      0ull,   0},
26638         {"PBP"                         ,        43,     1,      366,    "R/W",  0,      1,      0ull,   0},
26639         {"RESERVED_44_63"              ,        44,     20,     366,    "RAZ",  1,      1,      0,      0},
26640         {"RSV_A"                       ,        0,      6,      367,    "R/W",  0,      1,      0ull,   0},
26641         {"SKP_LEN"                     ,        6,      7,      367,    "R/W",  0,      1,      0ull,   0},
26642         {"RSV_B"                       ,        13,     1,      367,    "R/W",  0,      1,      0ull,   0},
26643         {"PAR_MODE"                    ,        14,     2,      367,    "R/W",  0,      1,      0ull,   0},
26644         {"RSV_C"                       ,        16,     5,      367,    "R/W",  0,      1,      0ull,   0},
26645         {"USE_IHDR"                    ,        21,     1,      367,    "R/W",  0,      1,      0ull,   0},
26646         {"RSV_D"                       ,        22,     6,      367,    "R/W",  0,      1,      0ull,   0},
26647         {"RSKP_LEN"                    ,        28,     7,      367,    "R/W",  0,      1,      8ull,   0},
26648         {"RSV_E"                       ,        35,     1,      367,    "R/W",  0,      1,      0ull,   0},
26649         {"RPARMODE"                    ,        36,     2,      367,    "R/W",  0,      1,      0ull,   0},
26650         {"RSV_F"                       ,        38,     5,      367,    "R/W",  0,      1,      0ull,   0},
26651         {"PBP"                         ,        43,     1,      367,    "R/W",  0,      1,      0ull,   0},
26652         {"RESERVED_44_63"              ,        44,     20,     367,    "RAZ",  1,      1,      0,      0},
26653         {"RSV_A"                       ,        0,      6,      368,    "R/W",  0,      1,      0ull,   0},
26654         {"SKP_LEN"                     ,        6,      7,      368,    "R/W",  0,      1,      0ull,   0},
26655         {"RSV_B"                       ,        13,     1,      368,    "R/W",  0,      1,      0ull,   0},
26656         {"PAR_MODE"                    ,        14,     2,      368,    "R/W",  0,      1,      0ull,   0},
26657         {"RSV_C"                       ,        16,     5,      368,    "R/W",  0,      1,      0ull,   0},
26658         {"USE_IHDR"                    ,        21,     1,      368,    "R/W",  0,      1,      0ull,   0},
26659         {"RSV_D"                       ,        22,     6,      368,    "R/W",  0,      1,      0ull,   0},
26660         {"RSKP_LEN"                    ,        28,     7,      368,    "R/W",  0,      1,      8ull,   0},
26661         {"RSV_E"                       ,        35,     1,      368,    "R/W",  0,      1,      0ull,   0},
26662         {"RPARMODE"                    ,        36,     2,      368,    "R/W",  0,      1,      0ull,   0},
26663         {"RSV_F"                       ,        38,     5,      368,    "R/W",  0,      1,      0ull,   0},
26664         {"PBP"                         ,        43,     1,      368,    "R/W",  0,      1,      0ull,   0},
26665         {"RESERVED_44_63"              ,        44,     20,     368,    "RAZ",  1,      1,      0,      0},
26666         {"ENB"                         ,        0,      4,      369,    "R/W",  0,      0,      15ull,  15ull},
26667         {"BP_ON"                       ,        4,      4,      369,    "RO",   0,      0,      0ull,   0ull},
26668         {"RESERVED_8_63"               ,        8,      56,     369,    "RAZ",  1,      1,      0,      0},
26669         {"MIO"                         ,        0,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26670         {"GMX0"                        ,        1,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26671         {"GMX1"                        ,        2,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26672         {"NPI"                         ,        3,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26673         {"KEY"                         ,        4,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26674         {"FPA"                         ,        5,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26675         {"DFA"                         ,        6,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26676         {"ZIP"                         ,        7,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26677         {"RINT_8"                      ,        8,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26678         {"IPD"                         ,        9,      1,      370,    "RO",   0,      0,      0ull,   0ull},
26679         {"PKO"                         ,        10,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26680         {"TIM"                         ,        11,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26681         {"POW"                         ,        12,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26682         {"RINT_13"                     ,        13,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26683         {"RINT_14"                     ,        14,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26684         {"RINT_15"                     ,        15,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26685         {"L2C"                         ,        16,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26686         {"LMC"                         ,        17,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26687         {"SPX0"                        ,        18,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26688         {"SPX1"                        ,        19,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26689         {"PIP"                         ,        20,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26690         {"RINT_21"                     ,        21,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26691         {"ASX0"                        ,        22,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26692         {"ASX1"                        ,        23,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26693         {"RINT_24"                     ,        24,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26694         {"RINT_25"                     ,        25,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26695         {"RINT_26"                     ,        26,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26696         {"RINT_27"                     ,        27,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26697         {"RINT_28"                     ,        28,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26698         {"RINT_29"                     ,        29,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26699         {"IOB"                         ,        30,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26700         {"RINT_31"                     ,        31,     1,      370,    "RO",   0,      0,      0ull,   0ull},
26701         {"RESERVED_32_63"              ,        32,     32,     370,    "RAZ",  1,      1,      0,      0},
26702         {"SIZE"                        ,        0,      32,     371,    "R/W",  0,      1,      0ull,   0},
26703         {"RESERVED_32_63"              ,        32,     32,     371,    "RAZ",  1,      1,      0,      0},
26704         {"TIME"                        ,        0,      32,     372,    "R/W",  0,      0,      0ull,   131072ull},
26705         {"RESERVED_32_63"              ,        32,     32,     372,    "RAZ",  1,      1,      0,      0},
26706         {"ADDR_V"                      ,        0,      1,      373,    "R/W",  0,      1,      0ull,   0},
26707         {"END_SWP"                     ,        1,      2,      373,    "R/W",  0,      1,      0ull,   0},
26708         {"CA"                          ,        3,      1,      373,    "R/W",  0,      0,      0ull,   0ull},
26709         {"ADDR_IDX"                    ,        4,      14,     373,    "R/W",  0,      1,      0ull,   0},
26710         {"RESERVED_18_31"              ,        18,     14,     373,    "RAZ",  1,      1,      0,      0},
26711         {"VENDID"                      ,        0,      16,     374,    "RO",   0,      0,      6013ull,        6013ull},
26712         {"DEVID"                       ,        16,     16,     374,    "RO",   0,      0,      64ull,  64ull},
26713         {"ISAE"                        ,        0,      1,      375,    "RO",   0,      0,      0ull,   0ull},
26714         {"MSAE"                        ,        1,      1,      375,    "R/W",  0,      0,      0ull,   1ull},
26715         {"ME"                          ,        2,      1,      375,    "R/W",  0,      0,      0ull,   1ull},
26716         {"SCSE"                        ,        3,      1,      375,    "RO",   0,      0,      0ull,   0ull},
26717         {"MWICE"                       ,        4,      1,      375,    "R/W",  0,      0,      0ull,   0ull},
26718         {"VPS"                         ,        5,      1,      375,    "RO",   0,      0,      0ull,   0ull},
26719         {"PEE"                         ,        6,      1,      375,    "R/W",  0,      0,      0ull,   1ull},
26720         {"ADS"                         ,        7,      1,      375,    "RO",   0,      0,      0ull,   0ull},
26721         {"SEE"                         ,        8,      1,      375,    "R/W",  0,      0,      0ull,   1ull},
26722         {"FBBE"                        ,        9,      1,      375,    "R/W",  0,      0,      0ull,   1ull},
26723         {"I_DIS"                       ,        10,     1,      375,    "R/W",  0,      0,      0ull,   0ull},
26724         {"RESERVED_11_18"              ,        11,     8,      375,    "RAZ",  1,      1,      0,      0},
26725         {"I_STAT"                      ,        19,     1,      375,    "RO",   0,      0,      0ull,   0ull},
26726         {"CLE"                         ,        20,     1,      375,    "RO",   0,      0,      1ull,   1ull},
26727         {"M66"                         ,        21,     1,      375,    "RO",   0,      0,      1ull,   1ull},
26728         {"RESERVED_22_22"              ,        22,     1,      375,    "RAZ",  1,      1,      0,      0},
26729         {"FBB"                         ,        23,     1,      375,    "RO",   0,      1,      1ull,   0},
26730         {"MDPE"                        ,        24,     1,      375,    "R/W1C",        0,      0,      0ull,   0ull},
26731         {"DEVT"                        ,        25,     2,      375,    "RO",   0,      0,      1ull,   1ull},
26732         {"STA"                         ,        27,     1,      375,    "R/W1C",        0,      0,      0ull,   0ull},
26733         {"RTA"                         ,        28,     1,      375,    "R/W1C",        0,      0,      0ull,   0ull},
26734         {"RMA"                         ,        29,     1,      375,    "R/W1C",        0,      0,      0ull,   0ull},
26735         {"SSE"                         ,        30,     1,      375,    "R/W1C",        0,      0,      0ull,   0ull},
26736         {"DPE"                         ,        31,     1,      375,    "R/W1C",        0,      0,      0ull,   0ull},
26737         {"RID"                         ,        0,      8,      376,    "RO",   0,      0,      0ull,   0ull},
26738         {"CC"                          ,        8,      24,     376,    "RO",   0,      0,      733184ull,      733184ull},
26739         {"CLS"                         ,        0,      8,      377,    "R/W",  0,      1,      0ull,   0},
26740         {"LT"                          ,        8,      8,      377,    "R/W",  0,      0,      0ull,   64ull},
26741         {"HT"                          ,        16,     8,      377,    "RO",   0,      0,      0ull,   0ull},
26742         {"BCOD"                        ,        24,     4,      377,    "RO",   0,      0,      0ull,   0ull},
26743         {"RESERVED_28_29"              ,        28,     2,      377,    "RAZ",  1,      1,      0,      0},
26744         {"BRB"                         ,        30,     1,      377,    "R/W",  0,      0,      0ull,   0ull},
26745         {"BCAP"                        ,        31,     1,      377,    "RO",   0,      0,      0ull,   0ull},
26746         {"MSPC"                        ,        0,      1,      378,    "RO",   0,      0,      0ull,   0ull},
26747         {"TYP"                         ,        1,      2,      378,    "RO",   0,      0,      2ull,   2ull},
26748         {"PF"                          ,        3,      1,      378,    "RO",   0,      0,      1ull,   1ull},
26749         {"LBASEZ"                      ,        4,      8,      378,    "RO",   0,      0,      0ull,   0ull},
26750         {"LBASE"                       ,        12,     20,     378,    "R/W",  0,      1,      0ull,   0},
26751         {"HBASE"                       ,        0,      32,     379,    "R/W",  0,      1,      0ull,   0},
26752         {"MSPC"                        ,        0,      1,      380,    "RO",   0,      0,      0ull,   0ull},
26753         {"TYP"                         ,        1,      2,      380,    "RO",   0,      0,      2ull,   2ull},
26754         {"PF"                          ,        3,      1,      380,    "RO",   0,      0,      1ull,   1ull},
26755         {"LBASEZ"                      ,        4,      23,     380,    "RO",   0,      0,      0ull,   0ull},
26756         {"LBASE"                       ,        27,     5,      380,    "R/W",  0,      1,      0ull,   0},
26757         {"HBASE"                       ,        0,      32,     381,    "R/W",  0,      1,      0ull,   0},
26758         {"MSPC"                        ,        0,      1,      382,    "RO",   0,      0,      0ull,   0ull},
26759         {"TYP"                         ,        1,      2,      382,    "RO",   0,      0,      2ull,   2ull},
26760         {"PF"                          ,        3,      1,      382,    "RO",   0,      0,      1ull,   1ull},
26761         {"LBASEZ"                      ,        4,      28,     382,    "RO",   0,      0,      0ull,   0ull},
26762         {"HBASEZ"                      ,        0,      7,      383,    "RO",   0,      0,      0ull,   0ull},
26763         {"HBASE"                       ,        7,      25,     383,    "R/W",  0,      1,      0ull,   0},
26764         {"CISP"                        ,        0,      32,     384,    "RO",   0,      0,      0ull,   0ull},
26765         {"SSVID"                       ,        0,      16,     385,    "RO",   0,      0,      6013ull,        6013ull},
26766         {"SSID"                        ,        16,     16,     385,    "RO",   0,      0,      1ull,   1ull},
26767         {"ERBAR_EN"                    ,        0,      1,      386,    "R/W",  0,      0,      0ull,   0ull},
26768         {"RESERVED_1_10"               ,        1,      10,     386,    "RAZ",  1,      1,      0,      0},
26769         {"ERBARZ"                      ,        11,     5,      386,    "RO",   0,      0,      0ull,   0ull},
26770         {"ERBAR"                       ,        16,     16,     386,    "R/W",  0,      1,      0ull,   0},
26771         {"CP"                          ,        0,      8,      387,    "RO",   0,      0,      224ull, 224ull},
26772         {"RESERVED_8_31"               ,        8,      24,     387,    "RAZ",  1,      1,      0,      0},
26773         {"IL"                          ,        0,      8,      388,    "R/W",  0,      1,      0ull,   0},
26774         {"INTA"                        ,        8,      8,      388,    "RO",   0,      0,      1ull,   1ull},
26775         {"MG"                          ,        16,     8,      388,    "RO",   0,      0,      64ull,  64ull},
26776         {"ML"                          ,        24,     8,      388,    "RO",   0,      0,      64ull,  64ull},
26777         {"MLTD"                        ,        0,      1,      389,    "R/W",  0,      0,      0ull,   1ull},
26778         {"TSWC"                        ,        1,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
26779         {"RESERVED_2_2"                ,        2,      1,      389,    "RAZ",  1,      1,      0,      0},
26780         {"DPPMR"                       ,        3,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
26781         {"PBE"                         ,        4,      12,     389,    "R/W",  0,      0,      0ull,   0ull},
26782         {"TILT"                        ,        16,     4,      389,    "R/W",  0,      0,      0ull,   0ull},
26783         {"TSLTE"                       ,        20,     3,      389,    "R/W",  0,      0,      0ull,   0ull},
26784         {"TMAE"                        ,        23,     1,      389,    "R/W",  0,      0,      0ull,   0ull},
26785         {"TWTAE"                       ,        24,     1,      389,    "R/W",  0,      0,      0ull,   0ull},
26786         {"TWSEN"                       ,        25,     1,      389,    "R/W",  0,      0,      0ull,   0ull},
26787         {"TWSEI"                       ,        26,     1,      389,    "R/W",  0,      0,      0ull,   0ull},
26788         {"TRTAE"                       ,        27,     1,      389,    "R/W",  0,      0,      0ull,   0ull},
26789         {"TRDRS"                       ,        28,     1,      389,    "R/W",  0,      0,      0ull,   0ull},
26790         {"RDSATI"                      ,        29,     1,      389,    "R/W",  0,      0,      0ull,   0ull},
26791         {"TRDARD"                      ,        30,     1,      389,    "R/W1C",        0,      0,      0ull,   0ull},
26792         {"TRDNPR"                      ,        31,     1,      389,    "R/W1C",        0,      0,      0ull,   0ull},
26793         {"TSCME"                       ,        0,      32,     390,    "R/W1C",        0,      1,      0ull,   0},
26794         {"TDSRPS"                      ,        0,      32,     391,    "R/W1C",        0,      0,      0ull,   0ull},
26795         {"TDOMC"                       ,        0,      5,      392,    "R/W",  0,      0,      1ull,   1ull},
26796         {"TIDOMC"                      ,        5,      1,      392,    "R/W",  0,      0,      0ull,   0ull},
26797         {"RESERVED_6_6"                ,        6,      1,      392,    "RAZ",  1,      1,      0,      0},
26798         {"TIBDE"                       ,        7,      1,      392,    "R/W",  0,      0,      0ull,   0ull},
26799         {"TIBCD"                       ,        8,      1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
26800         {"RESERVED_9_10"               ,        9,      2,      392,    "RAZ",  1,      1,      0,      0},
26801         {"TMAPES"                      ,        11,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
26802         {"TMDPES"                      ,        12,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
26803         {"TMSE"                        ,        13,     1,      392,    "R/W1C",        0,      0,      0ull,   0ull},
26804         {"TMEI"                        ,        14,     1,      392,    "RO",   0,      0,      0ull,   0ull},
26805         {"TECI"                        ,        15,     1,      392,    "RO",   0,      0,      0ull,   0ull},
26806         {"TMES"                        ,        16,     8,      392,    "RO",   0,      0,      0ull,   0ull},
26807         {"MDRRMC"                      ,        24,     3,      392,    "R/W",  0,      0,      2ull,   2ull},
26808         {"MDRIMC"                      ,        27,     1,      392,    "R/W",  0,      0,      0ull,   0ull},
26809         {"MDRE"                        ,        28,     1,      392,    "R/W",  0,      0,      0ull,   0ull},
26810         {"MDWE"                        ,        29,     1,      392,    "R/W",  0,      0,      0ull,   0ull},
26811         {"MRBCI"                       ,        30,     1,      392,    "R/W",  0,      0,      0ull,   0ull},
26812         {"MRBCM"                       ,        31,     1,      392,    "R/W",  0,      0,      1ull,   1ull},
26813         {"MDSP"                        ,        0,      32,     393,    "R/W1C",        0,      1,      0ull,   0},
26814         {"SCMRE"                       ,        0,      32,     394,    "R/W1C",        0,      1,      0ull,   0},
26815         {"MTTV"                        ,        0,      8,      395,    "R/W",  0,      0,      0ull,   0ull},
26816         {"MRV"                         ,        8,      8,      395,    "R/W",  0,      0,      0ull,   255ull},
26817         {"MTTA"                        ,        16,     1,      395,    "R/W1C",        0,      0,      0ull,   0ull},
26818         {"MRA"                         ,        17,     1,      395,    "R/W1C",        0,      0,      0ull,   0ull},
26819         {"FLUSH"                       ,        18,     1,      395,    "R/W",  0,      0,      1ull,   1ull},
26820         {"RESERVED_19_24"              ,        19,     6,      395,    "RAZ",  1,      1,      0,      0},
26821         {"MAC"                         ,        25,     7,      395,    "R/W",  0,      0,      0ull,   0ull},
26822         {"PXCID"                       ,        0,      8,      396,    "RO",   0,      0,      7ull,   7ull},
26823         {"NCP"                         ,        8,      8,      396,    "RO",   0,      0,      232ull, 232ull},
26824         {"DPERE"                       ,        16,     1,      396,    "R/W",  0,      0,      0ull,   0ull},
26825         {"ROE"                         ,        17,     1,      396,    "R/W",  0,      0,      1ull,   1ull},
26826         {"MMBC"                        ,        18,     2,      396,    "R/W",  0,      0,      0ull,   0ull},
26827         {"MOST"                        ,        20,     3,      396,    "R/W",  0,      0,      3ull,   3ull},
26828         {"RESERVED_23_31"              ,        23,     9,      396,    "RAZ",  1,      1,      0,      0},
26829         {"FN"                          ,        0,      3,      397,    "RO",   0,      0,      0ull,   0ull},
26830         {"DN"                          ,        3,      5,      397,    "RO",   0,      0,      31ull,  31ull},
26831         {"BN"                          ,        8,      8,      397,    "RO",   0,      1,      17ull,  0},
26832         {"W64"                         ,        16,     1,      397,    "RO",   0,      0,      1ull,   1ull},
26833         {"M133"                        ,        17,     1,      397,    "RO",   0,      0,      1ull,   1ull},
26834         {"SCD"                         ,        18,     1,      397,    "R/W1C",        0,      1,      0ull,   0},
26835         {"USC"                         ,        19,     1,      397,    "R/W1C",        0,      1,      0ull,   0},
26836         {"DC"                          ,        20,     1,      397,    "RO",   0,      0,      0ull,   0ull},
26837         {"MMRBCD"                      ,        21,     2,      397,    "RO",   0,      0,      2ull,   2ull},
26838         {"MOSTD"                       ,        23,     3,      397,    "RO",   0,      0,      3ull,   3ull},
26839         {"MCRSD"                       ,        26,     3,      397,    "RO",   0,      0,      7ull,   7ull},
26840         {"SCEMR"                       ,        29,     1,      397,    "R/W1C",        0,      1,      0ull,   0},
26841         {"RESERVED_30_31"              ,        30,     2,      397,    "RAZ",  1,      1,      0,      0},
26842         {"PMCID"                       ,        0,      8,      398,    "RO",   0,      0,      1ull,   1ull},
26843         {"NCP"                         ,        8,      8,      398,    "RO",   0,      0,      240ull, 240ull},
26844         {"PCIMIV"                      ,        16,     3,      398,    "RO",   0,      0,      2ull,   2ull},
26845         {"PMEC"                        ,        19,     1,      398,    "RO",   0,      0,      0ull,   0ull},
26846         {"RESERVED_20_20"              ,        20,     1,      398,    "RAZ",  1,      1,      0,      0},
26847         {"DSI"                         ,        21,     1,      398,    "RO",   0,      0,      0ull,   0ull},
26848         {"AUXC"                        ,        22,     3,      398,    "RO",   0,      0,      0ull,   0ull},
26849         {"D1S"                         ,        25,     1,      398,    "RO",   0,      0,      0ull,   0ull},
26850         {"D2S"                         ,        26,     1,      398,    "RO",   0,      0,      0ull,   0ull},
26851         {"PMES"                        ,        27,     5,      398,    "RO",   0,      0,      0ull,   0ull},
26852         {"PS"                          ,        0,      2,      399,    "R/W",  0,      0,      0ull,   0ull},
26853         {"RESERVED_2_7"                ,        2,      6,      399,    "RAZ",  1,      1,      0,      0},
26854         {"PMEENS"                      ,        8,      1,      399,    "R/W",  0,      0,      0ull,   0ull},
26855         {"PMDS"                        ,        9,      4,      399,    "R/W",  0,      0,      0ull,   0ull},
26856         {"PMEDSIA"                     ,        13,     2,      399,    "RO",   0,      0,      0ull,   0ull},
26857         {"PMESS"                       ,        15,     1,      399,    "R/W1C",        0,      0,      0ull,   0ull},
26858         {"RESERVED_16_21"              ,        16,     6,      399,    "RAZ",  1,      1,      0,      0},
26859         {"BD3H"                        ,        22,     1,      399,    "RO",   0,      0,      0ull,   0ull},
26860         {"BPCCEN"                      ,        23,     1,      399,    "RO",   0,      0,      0ull,   0ull},
26861         {"PMDIA"                       ,        24,     8,      399,    "RO",   0,      0,      0ull,   0ull},
26862         {"MSICID"                      ,        0,      8,      400,    "RO",   0,      0,      5ull,   5ull},
26863         {"NCP"                         ,        8,      8,      400,    "RO",   0,      0,      0ull,   0ull},
26864         {"MSIEN"                       ,        16,     1,      400,    "R/W",  0,      0,      0ull,   0ull},
26865         {"MMC"                         ,        17,     3,      400,    "RO",   0,      0,      0ull,   0ull},
26866         {"MME"                         ,        20,     3,      400,    "R/W",  0,      0,      0ull,   0ull},
26867         {"M64"                         ,        23,     1,      400,    "RO",   0,      0,      1ull,   1ull},
26868         {"RESERVED_24_31"              ,        24,     8,      400,    "RAZ",  1,      1,      0,      0},
26869         {"RESERVED_0_1"                ,        0,      2,      401,    "RAZ",  1,      1,      0,      0},
26870         {"MSI31T2"                     ,        2,      30,     401,    "R/W",  0,      1,      0ull,   0},
26871         {"MSI"                         ,        0,      32,     402,    "R/W",  0,      1,      0ull,   0},
26872         {"MSIMD"                       ,        0,      16,     403,    "R/W",  0,      1,      0ull,   0},
26873         {"RESERVED_16_31"              ,        16,     16,     403,    "RAZ",  1,      1,      0,      0},
26874         {"PCICNT"                      ,        0,      32,     404,    "R/W",  0,      1,      0ull,   0},
26875         {"AP_SPEED"                    ,        32,     2,      404,    "RO",   1,      1,      0,      0},
26876         {"AP_PCIX"                     ,        34,     1,      404,    "RO",   1,      1,      0,      0},
26877         {"HM_SPEED"                    ,        35,     2,      404,    "RO",   0,      1,      0ull,   0},
26878         {"HM_PCIX"                     ,        37,     1,      404,    "RO",   0,      1,      0ull,   0},
26879         {"RESERVED_38_63"              ,        38,     26,     404,    "RAZ",  1,      1,      0,      0},
26880         {"BAR2_CAX"                    ,        0,      1,      405,    "R/W",  0,      0,      0ull,   0ull},
26881         {"BAR2_ESX"                    ,        1,      2,      405,    "R/W",  0,      1,      0ull,   0},
26882         {"BAR2_ENB"                    ,        3,      1,      405,    "R/W",  0,      0,      0ull,   1ull},
26883         {"TSR_HWM"                     ,        4,      3,      405,    "R/W",  0,      1,      1ull,   0},
26884         {"PMO_FPC"                     ,        7,      3,      405,    "R/W",  0,      0,      0ull,   0ull},
26885         {"PMO_AMOD"                    ,        10,     1,      405,    "R/W",  0,      0,      0ull,   0ull},
26886         {"B12_BIST"                    ,        11,     1,      405,    "RO",   0,      0,      0ull,   0ull},
26887         {"AP_64AD"                     ,        12,     1,      405,    "RO",   0,      1,      0ull,   0},
26888         {"AP_PCIX"                     ,        13,     1,      405,    "RO",   0,      1,      0ull,   0},
26889         {"RESERVED_14_14"              ,        14,     1,      405,    "RAZ",  0,      0,      0ull,   0ull},
26890         {"EN_WFILT"                    ,        15,     1,      405,    "R/W",  0,      0,      0ull,   1ull},
26891         {"SCM"                         ,        16,     1,      405,    "RO",   0,      1,      0ull,   0},
26892         {"SCMTYP"                      ,        17,     1,      405,    "RO",   0,      1,      0ull,   0},
26893         {"BAR2PRES"                    ,        18,     1,      405,    "R/W",  1,      1,      0,      0},
26894         {"ERST_N"                      ,        19,     1,      405,    "RO",   0,      0,      1ull,   1ull},
26895         {"BB0"                         ,        20,     1,      405,    "R/W",  0,      0,      0ull,   0ull},
26896         {"BB1"                         ,        21,     1,      405,    "R/W",  0,      0,      0ull,   0ull},
26897         {"BB_ES"                       ,        22,     2,      405,    "R/W",  0,      0,      0ull,   0ull},
26898         {"BB_CA"                       ,        24,     1,      405,    "R/W",  0,      0,      0ull,   0ull},
26899         {"BB1_SIZ"                     ,        25,     1,      405,    "R/W",  0,      0,      0ull,   0ull},
26900         {"BB1_HOLE"                    ,        26,     3,      405,    "R/W",  0,      0,      0ull,   0ull},
26901         {"RESERVED_29_31"              ,        29,     3,      405,    "RAZ",  1,      1,      0,      0},
26902         {"INC_VAL"                     ,        0,      16,     406,    "R/W",  0,      1,      0ull,   0},
26903         {"RESERVED_16_31"              ,        16,     16,     406,    "RAZ",  1,      1,      0,      0},
26904         {"DMA_CNT"                     ,        0,      32,     407,    "R/W",  0,      0,      0ull,   0ull},
26905         {"PKT_CNT"                     ,        0,      32,     408,    "R/W",  0,      1,      0ull,   0},
26906         {"DMA_TIME"                    ,        0,      32,     409,    "R/W",  0,      1,      0ull,   0},
26907         {"ICNT"                        ,        0,      32,     410,    "R/W1C",        0,      0,      0ull,   0ull},
26908         {"ITR_WABT"                    ,        0,      1,      411,    "R/W",  0,      1,      0ull,   0},
26909         {"IMR_WABT"                    ,        1,      1,      411,    "R/W",  0,      1,      0ull,   0},
26910         {"IMR_WTTO"                    ,        2,      1,      411,    "R/W",  0,      1,      0ull,   0},
26911         {"ITR_ABT"                     ,        3,      1,      411,    "R/W",  0,      1,      0ull,   0},
26912         {"IMR_ABT"                     ,        4,      1,      411,    "R/W",  0,      1,      0ull,   0},
26913         {"IMR_TTO"                     ,        5,      1,      411,    "R/W",  0,      1,      0ull,   0},
26914         {"IMSI_PER"                    ,        6,      1,      411,    "R/W",  0,      1,      0ull,   0},
26915         {"IMSI_TABT"                   ,        7,      1,      411,    "R/W",  0,      1,      0ull,   0},
26916         {"IMSI_MABT"                   ,        8,      1,      411,    "R/W",  0,      1,      0ull,   0},
26917         {"IMSC_MSG"                    ,        9,      1,      411,    "R/W",  0,      1,      0ull,   0},
26918         {"ITSR_ABT"                    ,        10,     1,      411,    "R/W",  0,      1,      0ull,   0},
26919         {"ISERR"                       ,        11,     1,      411,    "R/W",  0,      1,      0ull,   0},
26920         {"IAPERR"                      ,        12,     1,      411,    "R/W",  0,      1,      0ull,   0},
26921         {"IDPERR"                      ,        13,     1,      411,    "R/W",  0,      1,      0ull,   0},
26922         {"ILL_RWR"                     ,        14,     1,      411,    "R/W",  0,      1,      0ull,   0},
26923         {"ILL_RRD"                     ,        15,     1,      411,    "R/W",  0,      1,      0ull,   0},
26924         {"IRSL_INT"                    ,        16,     1,      411,    "R/W",  0,      1,      0ull,   0},
26925         {"IPCNT0"                      ,        17,     1,      411,    "R/W",  0,      1,      0ull,   0},
26926         {"IPCNT1"                      ,        18,     1,      411,    "R/W",  0,      1,      0ull,   0},
26927         {"IPCNT2"                      ,        19,     1,      411,    "R/W",  0,      1,      0ull,   0},
26928         {"IPCNT3"                      ,        20,     1,      411,    "R/W",  0,      1,      0ull,   0},
26929         {"IPTIME0"                     ,        21,     1,      411,    "R/W",  0,      1,      0ull,   0},
26930         {"IPTIME1"                     ,        22,     1,      411,    "R/W",  0,      1,      0ull,   0},
26931         {"IPTIME2"                     ,        23,     1,      411,    "R/W",  0,      1,      0ull,   0},
26932         {"IPTIME3"                     ,        24,     1,      411,    "R/W",  0,      1,      0ull,   0},
26933         {"IDCNT0"                      ,        25,     1,      411,    "R/W",  0,      1,      0ull,   0},
26934         {"IDCNT1"                      ,        26,     1,      411,    "R/W",  0,      1,      0ull,   0},
26935         {"IDTIME0"                     ,        27,     1,      411,    "R/W",  0,      1,      0ull,   0},
26936         {"IDTIME1"                     ,        28,     1,      411,    "R/W",  0,      1,      0ull,   0},
26937         {"DMA0_FI"                     ,        29,     1,      411,    "R/W",  0,      1,      0ull,   0},
26938         {"DMA1_FI"                     ,        30,     1,      411,    "R/W",  0,      1,      0ull,   0},
26939         {"WIN_WR"                      ,        31,     1,      411,    "R/W",  0,      1,      0ull,   0},
26940         {"ILL_WR"                      ,        32,     1,      411,    "R/W",  0,      1,      0ull,   0},
26941         {"ILL_RD"                      ,        33,     1,      411,    "R/W",  0,      1,      0ull,   0},
26942         {"RESERVED_34_63"              ,        34,     30,     411,    "RAZ",  1,      1,      0,      0},
26943         {"RTR_WABT"                    ,        0,      1,      412,    "R/W",  0,      1,      0ull,   0},
26944         {"RMR_WABT"                    ,        1,      1,      412,    "R/W",  0,      1,      0ull,   0},
26945         {"RMR_WTTO"                    ,        2,      1,      412,    "R/W",  0,      1,      0ull,   0},
26946         {"RTR_ABT"                     ,        3,      1,      412,    "R/W",  0,      1,      0ull,   0},
26947         {"RMR_ABT"                     ,        4,      1,      412,    "R/W",  0,      1,      0ull,   0},
26948         {"RMR_TTO"                     ,        5,      1,      412,    "R/W",  0,      1,      0ull,   0},
26949         {"RMSI_PER"                    ,        6,      1,      412,    "R/W",  0,      1,      0ull,   0},
26950         {"RMSI_TABT"                   ,        7,      1,      412,    "R/W",  0,      1,      0ull,   0},
26951         {"RMSI_MABT"                   ,        8,      1,      412,    "R/W",  0,      1,      0ull,   0},
26952         {"RMSC_MSG"                    ,        9,      1,      412,    "R/W",  0,      1,      0ull,   0},
26953         {"RTSR_ABT"                    ,        10,     1,      412,    "R/W",  0,      1,      0ull,   0},
26954         {"RSERR"                       ,        11,     1,      412,    "R/W",  0,      1,      0ull,   0},
26955         {"RAPERR"                      ,        12,     1,      412,    "R/W",  0,      1,      0ull,   0},
26956         {"RDPERR"                      ,        13,     1,      412,    "R/W",  0,      1,      0ull,   0},
26957         {"ILL_RWR"                     ,        14,     1,      412,    "R/W",  0,      1,      0ull,   0},
26958         {"ILL_RRD"                     ,        15,     1,      412,    "R/W",  0,      1,      0ull,   0},
26959         {"RRSL_INT"                    ,        16,     1,      412,    "R/W",  0,      1,      0ull,   0},
26960         {"RPCNT0"                      ,        17,     1,      412,    "R/W",  0,      1,      0ull,   0},
26961         {"RPCNT1"                      ,        18,     1,      412,    "R/W",  0,      1,      0ull,   0},
26962         {"RPCNT2"                      ,        19,     1,      412,    "R/W",  0,      1,      0ull,   0},
26963         {"RPCNT3"                      ,        20,     1,      412,    "R/W",  0,      1,      0ull,   0},
26964         {"RPTIME0"                     ,        21,     1,      412,    "R/W",  0,      1,      0ull,   0},
26965         {"RPTIME1"                     ,        22,     1,      412,    "R/W",  0,      1,      0ull,   0},
26966         {"RPTIME2"                     ,        23,     1,      412,    "R/W",  0,      1,      0ull,   0},
26967         {"RPTIME3"                     ,        24,     1,      412,    "R/W",  0,      1,      0ull,   0},
26968         {"RDCNT0"                      ,        25,     1,      412,    "R/W",  0,      1,      0ull,   0},
26969         {"RDCNT1"                      ,        26,     1,      412,    "R/W",  0,      1,      0ull,   0},
26970         {"RDTIME0"                     ,        27,     1,      412,    "R/W",  0,      1,      0ull,   0},
26971         {"RDTIME1"                     ,        28,     1,      412,    "R/W",  0,      1,      0ull,   0},
26972         {"DMA0_FI"                     ,        29,     1,      412,    "R/W",  0,      1,      0ull,   0},
26973         {"DMA1_FI"                     ,        30,     1,      412,    "R/W",  0,      1,      0ull,   0},
26974         {"WIN_WR"                      ,        31,     1,      412,    "R/W",  0,      1,      0ull,   0},
26975         {"ILL_WR"                      ,        32,     1,      412,    "R/W",  0,      1,      0ull,   0},
26976         {"ILL_RD"                      ,        33,     1,      412,    "R/W",  0,      1,      0ull,   0},
26977         {"RESERVED_34_63"              ,        34,     30,     412,    "RAZ",  1,      1,      0,      0},
26978         {"TR_WABT"                     ,        0,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26979         {"MR_WABT"                     ,        1,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26980         {"MR_WTTO"                     ,        2,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26981         {"TR_ABT"                      ,        3,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26982         {"MR_ABT"                      ,        4,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26983         {"MR_TTO"                      ,        5,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26984         {"MSI_PER"                     ,        6,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26985         {"MSI_TABT"                    ,        7,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26986         {"MSI_MABT"                    ,        8,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26987         {"MSC_MSG"                     ,        9,      1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26988         {"TSR_ABT"                     ,        10,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26989         {"SERR"                        ,        11,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26990         {"APERR"                       ,        12,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26991         {"DPERR"                       ,        13,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26992         {"ILL_RWR"                     ,        14,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26993         {"ILL_RRD"                     ,        15,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26994         {"RSL_INT"                     ,        16,     1,      413,    "RO",   0,      0,      0ull,   0ull},
26995         {"PCNT0"                       ,        17,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26996         {"PCNT1"                       ,        18,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26997         {"PCNT2"                       ,        19,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26998         {"PCNT3"                       ,        20,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
26999         {"PTIME0"                      ,        21,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27000         {"PTIME1"                      ,        22,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27001         {"PTIME2"                      ,        23,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27002         {"PTIME3"                      ,        24,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27003         {"DCNT0"                       ,        25,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27004         {"DCNT1"                       ,        26,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27005         {"DTIME0"                      ,        27,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27006         {"DTIME1"                      ,        28,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27007         {"DMA0_FI"                     ,        29,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27008         {"DMA1_FI"                     ,        30,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27009         {"WIN_WR"                      ,        31,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27010         {"ILL_WR"                      ,        32,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27011         {"ILL_RD"                      ,        33,     1,      413,    "R/W1C",        0,      0,      0ull,   0ull},
27012         {"RESERVED_34_63"              ,        34,     30,     413,    "RAZ",  1,      1,      0,      0},
27013         {"TR_WABT"                     ,        0,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27014         {"MR_WABT"                     ,        1,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27015         {"MR_WTTO"                     ,        2,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27016         {"TR_ABT"                      ,        3,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27017         {"MR_ABT"                      ,        4,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27018         {"MR_TTO"                      ,        5,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27019         {"MSI_PER"                     ,        6,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27020         {"MSI_TABT"                    ,        7,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27021         {"MSI_MABT"                    ,        8,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27022         {"MSC_MSG"                     ,        9,      1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27023         {"TSR_ABT"                     ,        10,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27024         {"SERR"                        ,        11,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27025         {"APERR"                       ,        12,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27026         {"DPERR"                       ,        13,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27027         {"ILL_RWR"                     ,        14,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27028         {"ILL_RRD"                     ,        15,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27029         {"RSL_INT"                     ,        16,     1,      414,    "RO",   0,      0,      0ull,   0ull},
27030         {"PCNT0"                       ,        17,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27031         {"PCNT1"                       ,        18,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27032         {"PCNT2"                       ,        19,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27033         {"PCNT3"                       ,        20,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27034         {"PTIME0"                      ,        21,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27035         {"PTIME1"                      ,        22,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27036         {"PTIME2"                      ,        23,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27037         {"PTIME3"                      ,        24,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27038         {"DCNT0"                       ,        25,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27039         {"DCNT1"                       ,        26,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27040         {"DTIME0"                      ,        27,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27041         {"DTIME1"                      ,        28,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27042         {"DMA0_FI"                     ,        29,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27043         {"DMA1_FI"                     ,        30,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27044         {"WIN_WR"                      ,        31,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27045         {"ILL_WR"                      ,        32,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27046         {"ILL_RD"                      ,        33,     1,      414,    "R/W1C",        0,      0,      0ull,   0ull},
27047         {"RESERVED_34_63"              ,        34,     30,     414,    "RAZ",  1,      1,      0,      0},
27048         {"INTR"                        ,        0,      6,      415,    "WO",   0,      1,      0ull,   0},
27049         {"RESERVED_6_31"               ,        6,      26,     415,    "R/W",  1,      1,      0,      0},
27050         {"PTR_CNT"                     ,        0,      16,     416,    "R/W",  0,      1,      0ull,   0},
27051         {"PKT_CNT"                     ,        16,     16,     416,    "R/W",  0,      1,      0ull,   0},
27052         {"PKT_CNT"                     ,        0,      32,     417,    "RO",   0,      0,      0ull,   0ull},
27053         {"PKT_CNT"                     ,        0,      32,     418,    "R/W",  0,      1,      0ull,   0},
27054         {"PKT_TIME"                    ,        0,      32,     419,    "R/W",  0,      1,      0ull,   0},
27055         {"PREFETCH"                    ,        0,      3,      420,    "R/W",  0,      0,      0ull,   2ull},
27056         {"MIN_DATA"                    ,        3,      6,      420,    "R/W",  0,      0,      0ull,   4ull},
27057         {"RESERVED_9_31"               ,        9,      23,     420,    "RAZ",  1,      1,      0,      0},
27058         {"PREFETCH"                    ,        0,      3,      421,    "R/W",  0,      0,      0ull,   3ull},
27059         {"MIN_DATA"                    ,        3,      6,      421,    "R/W",  0,      0,      0ull,   6ull},
27060         {"RESERVED_9_31"               ,        9,      23,     421,    "RAZ",  1,      1,      0,      0},
27061         {"PREFETCH"                    ,        0,      3,      422,    "R/W",  0,      0,      0ull,   3ull},
27062         {"MIN_DATA"                    ,        3,      6,      422,    "R/W",  0,      0,      0ull,   6ull},
27063         {"RESERVED_9_31"               ,        9,      23,     422,    "RAZ",  1,      1,      0,      0},
27064         {"CNT"                         ,        0,      31,     423,    "R/W",  0,      0,      10000ull,       10000ull},
27065         {"ENB"                         ,        31,     1,      423,    "R/W",  0,      0,      0ull,   1ull},
27066         {"RESERVED_32_63"              ,        32,     32,     423,    "RAZ",  1,      1,      0,      0},
27067         {"SCM"                         ,        0,      32,     424,    "RO",   0,      1,      0ull,   0},
27068         {"RESERVED_32_63"              ,        32,     32,     424,    "RAZ",  1,      1,      0,      0},
27069         {"TSR"                         ,        0,      36,     425,    "RO",   0,      1,      0ull,   0},
27070         {"RESERVED_36_63"              ,        36,     28,     425,    "RAZ",  1,      1,      0,      0},
27071         {"RESERVED_0_2"                ,        0,      3,      426,    "RAZ",  1,      1,      0,      0},
27072         {"RD_ADDR"                     ,        3,      45,     426,    "R/W",  0,      1,      0ull,   0},
27073         {"IOBIT"                       ,        48,     1,      426,    "RAZ",  0,      0,      0ull,   0ull},
27074         {"RESERVED_49_63"              ,        49,     15,     426,    "RAZ",  1,      1,      0,      0},
27075         {"RD_DATA"                     ,        0,      64,     427,    "RO",   0,      1,      0ull,   0},
27076         {"RESERVED_0_2"                ,        0,      3,      428,    "RAZ",  1,      1,      0,      0},
27077         {"WR_ADDR"                     ,        3,      45,     428,    "R/W",  0,      1,      0ull,   0},
27078         {"IOBIT"                       ,        48,     1,      428,    "RAZ",  0,      0,      0ull,   0ull},
27079         {"RESERVED_49_63"              ,        49,     15,     428,    "RAZ",  1,      1,      0,      0},
27080         {"WR_DATA"                     ,        0,      64,     429,    "R/W",  0,      1,      0ull,   0},
27081         {"WR_MASK"                     ,        0,      8,      430,    "R/W",  0,      0,      0ull,   0ull},
27082         {"RESERVED_8_63"               ,        8,      56,     430,    "RAZ",  1,      1,      0,      0},
27083         {"LOWATER"                     ,        0,      5,      431,    "R/W",  0,      0,      4ull,   4ull},
27084         {"RESERVED_5_7"                ,        5,      3,      431,    "RAZ",  0,      1,      0ull,   0},
27085         {"HIWATER"                     ,        8,      5,      431,    "R/W",  0,      0,      24ull,  24ull},
27086         {"RESERVED_13_62"              ,        13,     50,     431,    "RAZ",  0,      1,      0ull,   0},
27087         {"BCKPRS"                      ,        63,     1,      431,    "RO",   0,      0,      0ull,   0ull},
27088         {"BIST"                        ,        0,      18,     432,    "RO",   0,      0,      0ull,   0ull},
27089         {"RESERVED_18_63"              ,        18,     46,     432,    "RAZ",  1,      1,      0,      0},
27090         {"REFLECT"                     ,        0,      1,      433,    "R/W",  0,      0,      1ull,   1ull},
27091         {"INVRES"                      ,        1,      1,      433,    "R/W",  0,      0,      1ull,   1ull},
27092         {"RESERVED_2_63"               ,        2,      62,     433,    "RAZ",  1,      1,      0,      0},
27093         {"IV"                          ,        0,      32,     434,    "R/W",  0,      0,      1185899593ull,  1185899593ull},
27094         {"RESERVED_32_63"              ,        32,     32,     434,    "RAZ",  1,      1,      0,      0},
27095         {"DPRT"                        ,        0,      16,     435,    "R/W",  0,      0,      0ull,   0ull},
27096         {"UDP"                         ,        16,     1,      435,    "R/W",  0,      0,      0ull,   0ull},
27097         {"TCP"                         ,        17,     1,      435,    "R/W",  0,      0,      0ull,   0ull},
27098         {"RESERVED_18_63"              ,        18,     46,     435,    "RAZ",  1,      1,      0,      0},
27099         {"NIP_SHF"                     ,        0,      3,      436,    "R/W",  0,      0,      0ull,   0ull},
27100         {"RESERVED_3_7"                ,        3,      5,      436,    "RAZ",  1,      1,      0,      0},
27101         {"RAW_SHF"                     ,        8,      3,      436,    "R/W",  0,      0,      0ull,   0ull},
27102         {"RESERVED_11_15"              ,        11,     5,      436,    "RAZ",  1,      1,      0,      0},
27103         {"MAX_L2"                      ,        16,     1,      436,    "R/W",  0,      0,      0ull,   0ull},
27104         {"IP6_UDP"                     ,        17,     1,      436,    "R/W",  0,      0,      1ull,   1ull},
27105         {"TAG_SYN"                     ,        18,     1,      436,    "R/W",  0,      0,      0ull,   0ull},
27106         {"RESERVED_19_63"              ,        19,     45,     436,    "RAZ",  1,      1,      0,      0},
27107         {"IP_CHK"                      ,        0,      1,      437,    "R/W",  0,      0,      1ull,   1ull},
27108         {"IP_MAL"                      ,        1,      1,      437,    "R/W",  0,      0,      1ull,   1ull},
27109         {"IP_HOP"                      ,        2,      1,      437,    "R/W",  0,      0,      1ull,   1ull},
27110         {"IP4_OPTS"                    ,        3,      1,      437,    "R/W",  0,      0,      1ull,   1ull},
27111         {"IP6_EEXT"                    ,        4,      2,      437,    "R/W",  0,      0,      1ull,   3ull},
27112         {"RESERVED_6_7"                ,        6,      2,      437,    "RAZ",  0,      1,      0ull,   0},
27113         {"L4_MAL"                      ,        8,      1,      437,    "R/W",  0,      0,      1ull,   1ull},
27114         {"L4_PRT"                      ,        9,      1,      437,    "R/W",  0,      0,      1ull,   1ull},
27115         {"L4_CHK"                      ,        10,     1,      437,    "R/W",  0,      0,      1ull,   1ull},
27116         {"L4_LEN"                      ,        11,     1,      437,    "R/W",  0,      0,      1ull,   1ull},
27117         {"TCP_FLAG"                    ,        12,     1,      437,    "R/W",  0,      0,      1ull,   1ull},
27118         {"L2_MAL"                      ,        13,     1,      437,    "R/W",  0,      0,      1ull,   1ull},
27119         {"VS_QOS"                      ,        14,     1,      437,    "R/W",  0,      0,      0ull,   0ull},
27120         {"VS_WQE"                      ,        15,     1,      437,    "R/W",  0,      0,      0ull,   0ull},
27121         {"IGNRS"                       ,        16,     1,      437,    "R/W",  0,      0,      0ull,   0ull},
27122         {"RESERVED_17_63"              ,        17,     47,     437,    "RAZ",  0,      0,      0ull,   0ull},
27123         {"PKTDRP"                      ,        0,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
27124         {"CRCERR"                      ,        1,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
27125         {"BCKPRS"                      ,        2,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
27126         {"PRTNXA"                      ,        3,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
27127         {"BADTAG"                      ,        4,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
27128         {"SKPRUNT"                     ,        5,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
27129         {"TODOOVR"                     ,        6,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
27130         {"FEPERR"                      ,        7,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
27131         {"BEPERR"                      ,        8,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
27132         {"RESERVED_9_63"               ,        9,      55,     438,    "RAZ",  1,      1,      0,      0},
27133         {"PKTDRP"                      ,        0,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
27134         {"CRCERR"                      ,        1,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
27135         {"BCKPRS"                      ,        2,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
27136         {"PRTNXA"                      ,        3,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
27137         {"BADTAG"                      ,        4,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
27138         {"SKPRUNT"                     ,        5,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
27139         {"TODOOVR"                     ,        6,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
27140         {"FEPERR"                      ,        7,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
27141         {"BEPERR"                      ,        8,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
27142         {"RESERVED_9_63"               ,        9,      55,     439,    "RAZ",  1,      1,      0,      0},
27143         {"OFFSET"                      ,        0,      3,      440,    "R/W",  0,      0,      0ull,   0ull},
27144         {"RESERVED_3_63"               ,        3,      61,     440,    "RAZ",  1,      1,      0,      0},
27145         {"SKIP"                        ,        0,      7,      441,    "R/W",  0,      0,      0ull,   0ull},
27146         {"RESERVED_7_7"                ,        7,      1,      441,    "RAZ",  1,      1,      0,      0},
27147         {"MODE"                        ,        8,      2,      441,    "R/W",  0,      0,      0ull,   0ull},
27148         {"RESERVED_10_11"              ,        10,     2,      441,    "RAZ",  1,      1,      0,      0},
27149         {"CRC_EN"                      ,        12,     1,      441,    "R/W",  0,      0,      1ull,   1ull},
27150         {"RESERVED_13_15"              ,        13,     3,      441,    "RAZ",  1,      1,      0,      0},
27151         {"QOS_VLAN"                    ,        16,     1,      441,    "R/W",  0,      0,      0ull,   0ull},
27152         {"QOS_DIFF"                    ,        17,     1,      441,    "R/W",  0,      0,      0ull,   0ull},
27153         {"QOS_VOD"                     ,        18,     1,      441,    "R/W",  0,      0,      0ull,   0ull},
27154         {"RESERVED_19_19"              ,        19,     1,      441,    "RAZ",  1,      1,      0,      0},
27155         {"QOS_WAT"                     ,        20,     4,      441,    "R/W",  0,      0,      0ull,   0ull},
27156         {"QOS"                         ,        24,     3,      441,    "R/W",  0,      0,      0ull,   0ull},
27157         {"RESERVED_27_27"              ,        27,     1,      441,    "RAZ",  1,      1,      0,      0},
27158         {"GRP_WAT"                     ,        28,     4,      441,    "R/W",  0,      0,      0ull,   0ull},
27159         {"INST_HDR"                    ,        32,     1,      441,    "R/W",  0,      0,      0ull,   0ull},
27160         {"DYN_RS"                      ,        33,     1,      441,    "R/W",  0,      0,      0ull,   0ull},
27161         {"TAG_INC"                     ,        34,     2,      441,    "R/W",  0,      0,      0ull,   0ull},
27162         {"RAWDRP"                      ,        36,     1,      441,    "R/W",  0,      0,      0ull,   0ull},
27163         {"RESERVED_37_63"              ,        37,     27,     441,    "RAZ",  1,      1,      0,      0},
27164         {"GRP"                         ,        0,      4,      442,    "R/W",  0,      0,      0ull,   0ull},
27165         {"NON_TAG_TYPE"                ,        4,      2,      442,    "R/W",  0,      0,      0ull,   0ull},
27166         {"IP4_TAG_TYPE"                ,        6,      2,      442,    "R/W",  0,      0,      0ull,   0ull},
27167         {"IP6_TAG_TYPE"                ,        8,      2,      442,    "R/W",  0,      0,      0ull,   0ull},
27168         {"TCP4_TAG_TYPE"               ,        10,     2,      442,    "R/W",  0,      0,      0ull,   0ull},
27169         {"TCP6_TAG_TYPE"               ,        12,     2,      442,    "R/W",  0,      0,      0ull,   0ull},
27170         {"IP4_SRC_FLAG"                ,        14,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27171         {"IP6_SRC_FLAG"                ,        15,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27172         {"IP4_DST_FLAG"                ,        16,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27173         {"IP6_DST_FLAG"                ,        17,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27174         {"IP4_PCTL_FLAG"               ,        18,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27175         {"IP6_NXTH_FLAG"               ,        19,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27176         {"IP4_SPRT_FLAG"               ,        20,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27177         {"IP6_SPRT_FLAG"               ,        21,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27178         {"IP4_DPRT_FLAG"               ,        22,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27179         {"IP6_DPRT_FLAG"               ,        23,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27180         {"INC_PRT_FLAG"                ,        24,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27181         {"INC_VLAN"                    ,        25,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27182         {"INC_VS"                      ,        26,     2,      442,    "R/W",  0,      0,      0ull,   0ull},
27183         {"TAG_MODE"                    ,        28,     2,      442,    "R/W",  0,      0,      0ull,   0ull},
27184         {"RESERVED_30_30"              ,        30,     1,      442,    "RAZ",  0,      0,      0ull,   0ull},
27185         {"GRPTAG"                      ,        31,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
27186         {"GRPTAGMASK"                  ,        32,     4,      442,    "R/W",  0,      0,      0ull,   0ull},
27187         {"GRPTAGBASE"                  ,        36,     4,      442,    "R/W",  0,      0,      0ull,   0ull},
27188         {"RESERVED_40_63"              ,        40,     24,     442,    "RAZ",  1,      1,      0,      0},
27189         {"QOS"                         ,        0,      3,      443,    "R/W",  0,      0,      0ull,   0ull},
27190         {"RESERVED_3_63"               ,        3,      61,     443,    "RAZ",  1,      1,      0,      0},
27191         {"QOS"                         ,        0,      3,      444,    "R/W",  0,      0,      0ull,   0ull},
27192         {"RESERVED_3_63"               ,        3,      61,     444,    "RAZ",  1,      1,      0,      0},
27193         {"MATCH_VALUE"                 ,        0,      16,     445,    "R/W",  0,      0,      0ull,   0ull},
27194         {"MATCH_TYPE"                  ,        16,     2,      445,    "R/W",  0,      0,      0ull,   0ull},
27195         {"RESERVED_18_19"              ,        18,     2,      445,    "RAZ",  1,      1,      0,      0},
27196         {"QOS"                         ,        20,     3,      445,    "R/W",  0,      0,      0ull,   0ull},
27197         {"RESERVED_23_23"              ,        23,     1,      445,    "RAZ",  1,      1,      0,      0},
27198         {"GRP"                         ,        24,     4,      445,    "R/W",  0,      0,      0ull,   0ull},
27199         {"RESERVED_28_31"              ,        28,     4,      445,    "RAZ",  1,      1,      0,      0},
27200         {"MASK"                        ,        32,     16,     445,    "R/W",  0,      0,      0ull,   0ull},
27201         {"RESERVED_48_63"              ,        48,     16,     445,    "RAZ",  1,      1,      0,      0},
27202         {"WORD"                        ,        0,      56,     446,    "R/W",  0,      0,      0ull,   0ull},
27203         {"RESERVED_56_63"              ,        56,     8,      446,    "RAZ",  1,      1,      0,      0},
27204         {"RST"                         ,        0,      1,      447,    "R/W",  0,      0,      0ull,   0ull},
27205         {"RESERVED_1_63"               ,        1,      63,     447,    "RAZ",  1,      1,      0,      0},
27206         {"DRP_OCTS"                    ,        0,      32,     448,    "R/W",  0,      1,      0ull,   0},
27207         {"DRP_PKTS"                    ,        32,     32,     448,    "R/W",  0,      1,      0ull,   0},
27208         {"OCTS"                        ,        0,      48,     449,    "R/W",  0,      1,      0ull,   0},
27209         {"RESERVED_48_63"              ,        48,     16,     449,    "RAZ",  1,      1,      0,      0},
27210         {"RAW"                         ,        0,      32,     450,    "R/W",  0,      1,      0ull,   0},
27211         {"PKTS"                        ,        32,     32,     450,    "R/W",  0,      1,      0ull,   0},
27212         {"MCST"                        ,        0,      32,     451,    "R/W",  0,      1,      0ull,   0},
27213         {"BCST"                        ,        32,     32,     451,    "R/W",  0,      1,      0ull,   0},
27214         {"H64"                         ,        0,      32,     452,    "R/W",  0,      1,      0ull,   0},
27215         {"H65TO127"                    ,        32,     32,     452,    "R/W",  0,      1,      0ull,   0},
27216         {"H128TO255"                   ,        0,      32,     453,    "R/W",  0,      1,      0ull,   0},
27217         {"H256TO511"                   ,        32,     32,     453,    "R/W",  0,      1,      0ull,   0},
27218         {"H512TO1023"                  ,        0,      32,     454,    "R/W",  0,      1,      0ull,   0},
27219         {"H1024TO1518"                 ,        32,     32,     454,    "R/W",  0,      1,      0ull,   0},
27220         {"H1519"                       ,        0,      32,     455,    "R/W",  0,      1,      0ull,   0},
27221         {"FCS"                         ,        32,     32,     455,    "R/W",  0,      1,      0ull,   0},
27222         {"UNDERSZ"                     ,        0,      32,     456,    "R/W",  0,      1,      0ull,   0},
27223         {"FRAG"                        ,        32,     32,     456,    "R/W",  0,      1,      0ull,   0},
27224         {"OVERSZ"                      ,        0,      32,     457,    "R/W",  0,      1,      0ull,   0},
27225         {"JABBER"                      ,        32,     32,     457,    "R/W",  0,      1,      0ull,   0},
27226         {"RDCLR"                       ,        0,      1,      458,    "R/W",  0,      0,      1ull,   1ull},
27227         {"RESERVED_1_63"               ,        1,      63,     458,    "RAZ",  1,      1,      0,      0},
27228         {"ERRS"                        ,        0,      16,     459,    "R/W",  0,      1,      0ull,   0},
27229         {"RESERVED_16_63"              ,        16,     48,     459,    "RAZ",  1,      1,      0,      0},
27230         {"OCTS"                        ,        0,      48,     460,    "R/W",  0,      1,      0ull,   0},
27231         {"RESERVED_48_63"              ,        48,     16,     460,    "RAZ",  1,      1,      0,      0},
27232         {"PKTS"                        ,        0,      32,     461,    "R/W",  0,      1,      0ull,   0},
27233         {"RESERVED_32_63"              ,        32,     32,     461,    "RAZ",  1,      1,      0,      0},
27234         {"EN"                          ,        0,      8,      462,    "R/W",  0,      0,      0ull,   0ull},
27235         {"RESERVED_8_63"               ,        8,      56,     462,    "RAZ",  1,      1,      0,      0},
27236         {"MASK"                        ,        0,      16,     463,    "R/W",  0,      0,      0ull,   0ull},
27237         {"RESERVED_16_63"              ,        16,     48,     463,    "RAZ",  1,      1,      0,      0},
27238         {"SRC"                         ,        0,      16,     464,    "R/W",  0,      0,      0ull,   0ull},
27239         {"DST"                         ,        16,     16,     464,    "R/W",  0,      0,      0ull,   0ull},
27240         {"RESERVED_32_63"              ,        32,     32,     464,    "RAZ",  1,      1,      0,      0},
27241         {"ENTRY"                       ,        0,      62,     465,    "RO",   1,      1,      0,      0},
27242         {"RESERVED_62_62"              ,        62,     1,      465,    "RAZ",  1,      1,      0,      0},
27243         {"VAL"                         ,        63,     1,      465,    "RO",   1,      1,      0,      0},
27244         {"COUNT"                       ,        0,      32,     466,    "R/W1C",        1,      0,      0,      0ull},
27245         {"RESERVED_32_63"              ,        32,     32,     466,    "RAZ",  1,      1,      0,      0},
27246         {"COUNT"                       ,        0,      48,     467,    "R/W1C",        1,      0,      0,      0ull},
27247         {"RESERVED_48_63"              ,        48,     16,     467,    "RAZ",  1,      1,      0,      0},
27248         {"SIZE"                        ,        0,      16,     468,    "RO",   1,      0,      0,      0ull},
27249         {"SEGS"                        ,        16,     6,      468,    "RO",   1,      0,      0,      0ull},
27250         {"CMD"                         ,        22,     14,     468,    "RO",   1,      0,      0,      0ull},
27251         {"FAU"                         ,        36,     28,     468,    "RO",   1,      0,      0,      0ull},
27252         {"PTR"                         ,        0,      40,     469,    "RO",   1,      0,      0,      0ull},
27253         {"SIZE"                        ,        40,     16,     469,    "RO",   1,      0,      0,      0ull},
27254         {"POOL"                        ,        56,     3,      469,    "RO",   1,      0,      0,      0ull},
27255         {"BACK"                        ,        59,     4,      469,    "RO",   1,      0,      0,      0ull},
27256         {"I"                           ,        63,     1,      469,    "RO",   1,      0,      0,      0ull},
27257         {"PTRS2"                       ,        0,      17,     470,    "RO",   1,      0,      0,      0ull},
27258         {"RESERVED_17_31"              ,        17,     15,     470,    "RAZ",  1,      0,      0,      0ull},
27259         {"PTRS1"                       ,        32,     17,     470,    "RO",   1,      0,      0,      0ull},
27260         {"RESERVED_49_63"              ,        49,     15,     470,    "RAZ",  1,      0,      0,      0ull},
27261         {"MOD"                         ,        0,      3,      471,    "RO",   1,      0,      0,      0ull},
27262         {"CNT"                         ,        3,      13,     471,    "RO",   1,      0,      0,      0ull},
27263         {"CHK"                         ,        16,     1,      471,    "RO",   1,      0,      0,      0ull},
27264         {"LEN"                         ,        17,     1,      471,    "RO",   1,      0,      0,      0ull},
27265         {"SOP"                         ,        18,     1,      471,    "RO",   1,      0,      0,      0ull},
27266         {"UID"                         ,        19,     3,      471,    "RO",   1,      0,      0,      0ull},
27267         {"MAJ"                         ,        22,     1,      471,    "RO",   1,      0,      0,      0ull},
27268         {"RESERVED_23_63"              ,        23,     41,     471,    "RAZ",  1,      0,      0,      0ull},
27269         {"SIZE"                        ,        0,      16,     472,    "RO",   1,      0,      0,      0ull},
27270         {"SEGS"                        ,        16,     6,      472,    "RO",   1,      0,      0,      0ull},
27271         {"CMD"                         ,        22,     14,     472,    "RO",   1,      0,      0,      0ull},
27272         {"FAU"                         ,        36,     28,     472,    "RO",   1,      0,      0,      0ull},
27273         {"PTR"                         ,        0,      40,     473,    "RO",   1,      0,      0,      0ull},
27274         {"SIZE"                        ,        40,     16,     473,    "RO",   1,      0,      0,      0ull},
27275         {"POOL"                        ,        56,     3,      473,    "RO",   1,      0,      0,      0ull},
27276         {"BACK"                        ,        59,     4,      473,    "RO",   1,      0,      0,      0ull},
27277         {"I"                           ,        63,     1,      473,    "RO",   1,      0,      0,      0ull},
27278         {"PTR"                         ,        0,      40,     474,    "RO",   1,      0,      0,      0ull},
27279         {"SIZE"                        ,        40,     16,     474,    "RO",   1,      0,      0,      0ull},
27280         {"POOL"                        ,        56,     3,      474,    "RO",   1,      0,      0,      0ull},
27281         {"BACK"                        ,        59,     4,      474,    "RO",   1,      0,      0,      0ull},
27282         {"I"                           ,        63,     1,      474,    "RO",   1,      0,      0,      0ull},
27283         {"DATA"                        ,        0,      64,     475,    "RO",   1,      0,      0,      0ull},
27284         {"MAJOR"                       ,        0,      3,      476,    "RO",   1,      0,      0,      0ull},
27285         {"MINOR"                       ,        3,      2,      476,    "RO",   1,      0,      0,      0ull},
27286         {"WAIT"                        ,        5,      1,      476,    "RO",   1,      0,      0,      0ull},
27287         {"QID_BASE"                    ,        6,      8,      476,    "RO",   1,      0,      0,      0ull},
27288         {"QID_OFF"                     ,        14,     4,      476,    "RO",   1,      0,      0,      0ull},
27289         {"QID_OFF_MAX"                 ,        18,     4,      476,    "RO",   1,      0,      0,      0ull},
27290         {"QCB_RIDX"                    ,        22,     5,      476,    "RO",   1,      0,      0,      0ull},
27291         {"QOS"                         ,        27,     3,      476,    "RO",   1,      0,      0,      0ull},
27292         {"STATIC_P"                    ,        30,     1,      476,    "RO",   1,      0,      0,      0ull},
27293         {"ACTIVE"                      ,        31,     1,      476,    "RO",   1,      0,      0,      0ull},
27294         {"CHK_MODE"                    ,        32,     1,      476,    "RO",   1,      0,      0,      0ull},
27295         {"CHK_ONCE"                    ,        33,     1,      476,    "RO",   1,      0,      0,      0ull},
27296         {"INIT_DWRITE"                 ,        34,     1,      476,    "RO",   1,      0,      0,      0ull},
27297         {"DREAD_SOP"                   ,        35,     1,      476,    "RO",   1,      0,      0,      0ull},
27298         {"UID"                         ,        36,     3,      476,    "RO",   1,      0,      0,      0ull},
27299         {"CMND_OFF"                    ,        39,     6,      476,    "RO",   1,      0,      0,      0ull},
27300         {"CMND_SIZ"                    ,        45,     16,     476,    "RO",   1,      0,      0,      0ull},
27301         {"CMND_SEGS"                   ,        61,     3,      476,    "RO",   1,      0,      0,      0ull},
27302         {"CMND_SEGS"                   ,        0,      3,      477,    "RO",   1,      0,      0,      0ull},
27303         {"CURR_OFF"                    ,        3,      16,     477,    "RO",   1,      0,      0,      0ull},
27304         {"CURR_SIZ"                    ,        19,     16,     477,    "RO",   1,      0,      0,      0ull},
27305         {"CURR_PTR"                    ,        35,     29,     477,    "RO",   1,      0,      0,      0ull},
27306         {"CURR_PTR"                    ,        0,      11,     478,    "RO",   1,      0,      0,      0ull},
27307         {"RESERVED_11_63"              ,        11,     53,     478,    "RAZ",  1,      0,      0,      0ull},
27308         {"QCB_RIDX"                    ,        0,      6,      479,    "RO",   1,      0,      0,      0ull},
27309         {"QCB_WIDX"                    ,        6,      6,      479,    "RO",   1,      0,      0,      0ull},
27310         {"BUF_PTR"                     ,        12,     33,     479,    "RO",   1,      0,      0,      0ull},
27311         {"BUF_SIZ"                     ,        45,     13,     479,    "RO",   1,      0,      0,      0ull},
27312         {"TAIL"                        ,        58,     1,      479,    "RO",   1,      0,      0,      0ull},
27313         {"QOS"                         ,        59,     5,      479,    "RO",   1,      0,      0,      0ull},
27314         {"QOS"                         ,        0,      3,      480,    "RO",   1,      0,      0,      0ull},
27315         {"STATIC_Q"                    ,        3,      1,      480,    "RO",   1,      0,      0,      0ull},
27316         {"S_TAIL"                      ,        4,      1,      480,    "RO",   1,      0,      0,      0ull},
27317         {"STATIC_P"                    ,        5,      1,      480,    "RO",   1,      0,      0,      0ull},
27318         {"RESERVED_6_7"                ,        6,      2,      480,    "RAZ",  1,      0,      0,      0ull},
27319         {"DOORBELL"                    ,        8,      20,     480,    "RO",   1,      0,      0,      0ull},
27320         {"RESERVED_28_63"              ,        28,     36,     480,    "RAZ",  1,      0,      0,      0ull},
27321         {"PTRS3"                       ,        0,      17,     481,    "RO",   1,      0,      0,      0ull},
27322         {"RESERVED_17_31"              ,        17,     15,     481,    "RAZ",  1,      0,      0,      0ull},
27323         {"PTRS0"                       ,        32,     17,     481,    "RO",   1,      0,      0,      0ull},
27324         {"RESERVED_49_63"              ,        49,     15,     481,    "RAZ",  1,      0,      0,      0ull},
27325         {"QUEUE"                       ,        0,      7,      482,    "R/W",  1,      0,      0,      0ull},
27326         {"PORT"                        ,        7,      6,      482,    "WR0",  1,      0,      0,      0ull},
27327         {"INDEX"                       ,        13,     3,      482,    "WR0",  1,      0,      0,      0ull},
27328         {"TAIL"                        ,        16,     1,      482,    "R/W",  1,      0,      0,      0ull},
27329         {"BUF_PTR"                     ,        17,     36,     482,    "R/W",  1,      0,      0,      0ull},
27330         {"QOS_MASK"                    ,        53,     8,      482,    "R/W",  1,      0,      0,      0ull},
27331         {"STATIC_Q"                    ,        61,     1,      482,    "R/W",  1,      0,      0,      0ull},
27332         {"STATIC_P"                    ,        62,     1,      482,    "R/W",  1,      0,      0,      0ull},
27333         {"S_TAIL"                      ,        63,     1,      482,    "R/W",  1,      0,      0,      0ull},
27334         {"QID"                         ,        0,      7,      483,    "R/W",  1,      0,      0,      0ull},
27335         {"PID"                         ,        7,      6,      483,    "WR0",  1,      0,      0,      0ull},
27336         {"RESERVED_13_52"              ,        13,     40,     483,    "RAZ",  1,      0,      0,      0ull},
27337         {"QOS_MASK"                    ,        53,     8,      483,    "R/W",  1,      0,      0,      0ull},
27338         {"RESERVED_61_63"              ,        61,     3,      483,    "RAZ",  1,      0,      0,      0ull},
27339         {"DAT_PTR"                     ,        0,      4,      484,    "RO",   1,      0,      0,      0ull},
27340         {"DAT_DAT"                     ,        4,      4,      484,    "RO",   1,      0,      0,      0ull},
27341         {"PRT_QSB"                     ,        8,      3,      484,    "RO",   1,      0,      0,      0ull},
27342         {"PRT_QCB"                     ,        11,     2,      484,    "RO",   1,      0,      0,      0ull},
27343         {"NCB_INB"                     ,        13,     2,      484,    "RO",   1,      0,      0,      0ull},
27344         {"PRT_PSB"                     ,        15,     6,      484,    "RO",   1,      0,      0,      0ull},
27345         {"PRT_NXT"                     ,        21,     1,      484,    "RO",   1,      0,      0,      0ull},
27346         {"PRT_CHK"                     ,        22,     3,      484,    "RO",   1,      0,      0,      0ull},
27347         {"OUT_WIF"                     ,        25,     1,      484,    "RO",   1,      0,      0,      0ull},
27348         {"OUT_STA"                     ,        26,     1,      484,    "RO",   1,      0,      0,      0ull},
27349         {"OUT_CTL"                     ,        27,     3,      484,    "RO",   1,      0,      0,      0ull},
27350         {"OUT_CRC"                     ,        30,     1,      484,    "RO",   1,      0,      0,      0ull},
27351         {"IOB"                         ,        31,     1,      484,    "RO",   1,      0,      0,      0ull},
27352         {"CSR"                         ,        32,     1,      484,    "RO",   1,      0,      0,      0ull},
27353         {"RESERVED_33_63"              ,        33,     31,     484,    "RAZ",  1,      0,      0,      0ull},
27354         {"SIZE"                        ,        0,      13,     485,    "R/W",  0,      0,      0ull,   0ull},
27355         {"RESERVED_13_19"              ,        13,     7,      485,    "RAZ",  0,      0,      0ull,   0ull},
27356         {"POOL"                        ,        20,     3,      485,    "R/W",  0,      0,      0ull,   0ull},
27357         {"RESERVED_23_63"              ,        23,     41,     485,    "RAZ",  1,      0,      0,      0ull},
27358         {"REFIN"                       ,        0,      1,      486,    "R/W",  0,      0,      1ull,   1ull},
27359         {"INVRES"                      ,        1,      1,      486,    "R/W",  0,      0,      1ull,   1ull},
27360         {"RESERVED_2_63"               ,        2,      62,     486,    "RAZ",  1,      1,      0,      0},
27361         {"ENABLE"                      ,        0,      32,     487,    "R/W",  0,      0,      0ull,   0ull},
27362         {"RESERVED_32_63"              ,        32,     32,     487,    "RAZ",  1,      0,      0,      0ull},
27363         {"IV"                          ,        0,      32,     488,    "R/W",  0,      0,      1185899593ull,  1185899593ull},
27364         {"RESERVED_32_63"              ,        32,     32,     488,    "RAZ",  1,      1,      0,      0},
27365         {"ASSERTS"                     ,        0,      64,     489,    "RO",   0,      0,      0ull,   0ull},
27366         {"ASSERTS"                     ,        0,      64,     490,    "RO",   0,      0,      0ull,   0ull},
27367         {"ASSERTS"                     ,        0,      64,     491,    "RO",   0,      0,      0ull,   0ull},
27368         {"ASSERTS"                     ,        0,      64,     492,    "RO",   0,      0,      0ull,   0ull},
27369         {"PARITY"                      ,        0,      1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
27370         {"DOORBELL"                    ,        1,      1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
27371         {"CURRZERO"                    ,        2,      1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
27372         {"RESERVED_3_63"               ,        3,      61,     493,    "RAZ",  1,      0,      0,      0ull},
27373         {"ENA_PKO"                     ,        0,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
27374         {"ENA_DWB"                     ,        1,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
27375         {"STORE_BE"                    ,        2,      1,      494,    "R/W",  0,      0,      0ull,   0ull},
27376         {"RESET"                       ,        3,      1,      494,    "RAZ",  0,      0,      0ull,   0ull},
27377         {"RESERVED_4_63"               ,        4,      60,     494,    "RAZ",  1,      0,      0,      0ull},
27378         {"MODE0"                       ,        0,      3,      495,    "R/W",  0,      0,      0ull,   0ull},
27379         {"MODE1"                       ,        3,      3,      495,    "R/W",  0,      0,      0ull,   0ull},
27380         {"RESERVED_6_63"               ,        6,      58,     495,    "RAZ",  1,      0,      0,      0ull},
27381         {"PARITY"                      ,        0,      1,      496,    "R/W",  0,      0,      0ull,   0ull},
27382         {"DOORBELL"                    ,        1,      1,      496,    "R/W",  0,      0,      0ull,   0ull},
27383         {"CURRZERO"                    ,        2,      1,      496,    "R/W",  0,      0,      0ull,   0ull},
27384         {"RESERVED_3_63"               ,        3,      61,     496,    "RAZ",  1,      0,      0,      0ull},
27385         {"MODE"                        ,        0,      2,      497,    "R/W",  0,      0,      0ull,   0ull},
27386         {"RESERVED_2_63"               ,        2,      62,     497,    "RAZ",  1,      0,      0,      0ull},
27387         {"QID7"                        ,        0,      1,      498,    "R/W",  0,      0,      0ull,   0ull},
27388         {"IDX3"                        ,        1,      1,      498,    "R/W",  0,      0,      0ull,   0ull},
27389         {"RESERVED_2_63"               ,        2,      62,     498,    "RAZ",  1,      0,      0,      0ull},
27390         {"INDEX"                       ,        0,      8,      499,    "R/W",  0,      0,      0ull,   0ull},
27391         {"INC"                         ,        8,      8,      499,    "R/W",  0,      0,      0ull,   0ull},
27392         {"RESERVED_16_63"              ,        16,     48,     499,    "RAZ",  1,      0,      0,      0ull},
27393         {"ADR0"                        ,        0,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27394         {"ADR1"                        ,        1,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27395         {"PEND0"                       ,        2,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27396         {"PEND1"                       ,        3,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27397         {"NBR0"                        ,        4,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27398         {"NBR1"                        ,        5,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27399         {"FIDX"                        ,        6,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27400         {"INDEX"                       ,        7,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27401         {"NBT"                         ,        8,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27402         {"CAM"                         ,        9,      1,      500,    "RO",   0,      0,      0ull,   0ull},
27403         {"RESERVED_10_15"              ,        10,     6,      500,    "RAZ",  1,      1,      0,      0},
27404         {"PP"                          ,        16,     16,     500,    "RO",   0,      0,      0ull,   0ull},
27405         {"RESERVED_32_63"              ,        32,     32,     500,    "RAZ",  1,      1,      0,      0},
27406         {"DS_PC"                       ,        0,      32,     501,    "R/W1C",        0,      1,      0ull,   0},
27407         {"RESERVED_32_63"              ,        32,     32,     501,    "RAZ",  1,      1,      0,      0},
27408         {"SBE"                         ,        0,      1,      502,    "R/W1C",        0,      0,      0ull,   0ull},
27409         {"DBE"                         ,        1,      1,      502,    "R/W1C",        0,      0,      0ull,   0ull},
27410         {"SBE_IE"                      ,        2,      1,      502,    "R/W",  0,      1,      0ull,   0},
27411         {"DBE_IE"                      ,        3,      1,      502,    "R/W",  0,      1,      0ull,   0},
27412         {"SYN"                         ,        4,      5,      502,    "RO",   1,      1,      0,      0},
27413         {"RESERVED_9_11"               ,        9,      3,      502,    "RAZ",  1,      1,      0,      0},
27414         {"RPE"                         ,        12,     1,      502,    "R/W1C",        0,      0,      0ull,   0ull},
27415         {"RPE_IE"                      ,        13,     1,      502,    "R/W",  0,      1,      0ull,   0},
27416         {"RESERVED_14_15"              ,        14,     2,      502,    "RAZ",  1,      1,      0,      0},
27417         {"IOP"                         ,        16,     13,     502,    "R/W1C",        0,      0,      0ull,   0ull},
27418         {"RESERVED_29_31"              ,        29,     3,      502,    "RAZ",  1,      1,      0,      0},
27419         {"IOP_IE"                      ,        32,     13,     502,    "R/W",  0,      1,      0ull,   0},
27420         {"RESERVED_45_63"              ,        45,     19,     502,    "RAZ",  1,      1,      0,      0},
27421         {"NBR_THR"                     ,        0,      5,      503,    "R/W",  0,      0,      2ull,   2ull},
27422         {"PFR_DIS"                     ,        5,      1,      503,    "R/W",  0,      0,      0ull,   0ull},
27423         {"RESERVED_6_63"               ,        6,      58,     503,    "RAZ",  1,      1,      0,      0},
27424         {"IQ_CNT"                      ,        0,      32,     504,    "RO",   0,      1,      0ull,   0},
27425         {"RESERVED_32_63"              ,        32,     32,     504,    "RAZ",  1,      1,      0,      0},
27426         {"IQ_CNT"                      ,        0,      32,     505,    "RO",   0,      1,      0ull,   0},
27427         {"RESERVED_32_63"              ,        32,     32,     505,    "RAZ",  1,      1,      0,      0},
27428         {"NOS_CNT"                     ,        0,      12,     506,    "RO",   0,      1,      0ull,   0},
27429         {"RESERVED_12_63"              ,        12,     52,     506,    "RAZ",  1,      1,      0,      0},
27430         {"NW_TIM"                      ,        0,      10,     507,    "R/W",  0,      0,      0ull,   1023ull},
27431         {"RESERVED_10_63"              ,        10,     54,     507,    "RAZ",  1,      1,      0,      0},
27432         {"RST_MSK"                     ,        0,      8,      508,    "R/W",  0,      1,      0ull,   0},
27433         {"RESERVED_8_63"               ,        8,      56,     508,    "RAZ",  1,      1,      0,      0},
27434         {"GRP_MSK"                     ,        0,      16,     509,    "R/W",  0,      0,      65535ull,       65535ull},
27435         {"QOS0_PRI"                    ,        16,     4,      509,    "R/W",  0,      1,      0ull,   0},
27436         {"QOS1_PRI"                    ,        20,     4,      509,    "R/W",  0,      1,      0ull,   0},
27437         {"QOS2_PRI"                    ,        24,     4,      509,    "R/W",  0,      1,      0ull,   0},
27438         {"QOS3_PRI"                    ,        28,     4,      509,    "R/W",  0,      1,      0ull,   0},
27439         {"QOS4_PRI"                    ,        32,     4,      509,    "R/W",  0,      1,      0ull,   0},
27440         {"QOS5_PRI"                    ,        36,     4,      509,    "R/W",  0,      1,      0ull,   0},
27441         {"QOS6_PRI"                    ,        40,     4,      509,    "R/W",  0,      1,      0ull,   0},
27442         {"QOS7_PRI"                    ,        44,     4,      509,    "R/W",  0,      1,      0ull,   0},
27443         {"RESERVED_48_63"              ,        48,     16,     509,    "RAZ",  1,      1,      0,      0},
27444         {"RND"                         ,        0,      8,      510,    "R/W",  0,      1,      255ull, 0},
27445         {"RND_P1"                      ,        8,      8,      510,    "R/W",  0,      1,      255ull, 0},
27446         {"RND_P2"                      ,        16,     8,      510,    "R/W",  0,      1,      255ull, 0},
27447         {"RND_P3"                      ,        24,     8,      510,    "R/W",  0,      1,      255ull, 0},
27448         {"RESERVED_32_63"              ,        32,     32,     510,    "RAZ",  1,      1,      0,      0},
27449         {"MIN_THR"                     ,        0,      11,     511,    "R/W",  0,      1,      0ull,   0},
27450         {"RESERVED_11_11"              ,        11,     1,      511,    "RAZ",  1,      1,      0,      0},
27451         {"MAX_THR"                     ,        12,     11,     511,    "R/W",  0,      1,      2047ull,        0},
27452         {"RESERVED_23_23"              ,        23,     1,      511,    "RAZ",  1,      1,      0,      0},
27453         {"FREE_CNT"                    ,        24,     12,     511,    "RO",   0,      1,      2027ull,        0},
27454         {"BUF_CNT"                     ,        36,     12,     511,    "RO",   0,      1,      0ull,   0},
27455         {"DES_CNT"                     ,        48,     12,     511,    "RO",   0,      1,      0ull,   0},
27456         {"RESERVED_60_63"              ,        60,     4,      511,    "RAZ",  1,      1,      0,      0},
27457         {"TS_PC"                       ,        0,      32,     512,    "R/W1C",        0,      1,      0ull,   0},
27458         {"RESERVED_32_63"              ,        32,     32,     512,    "RAZ",  1,      1,      0,      0},
27459         {"WA_PC"                       ,        0,      32,     513,    "R/W1C",        0,      1,      0ull,   0},
27460         {"RESERVED_32_63"              ,        32,     32,     513,    "RAZ",  1,      1,      0,      0},
27461         {"WA_PC"                       ,        0,      32,     514,    "R/W1C",        0,      1,      0ull,   0},
27462         {"RESERVED_32_63"              ,        32,     32,     514,    "RAZ",  1,      1,      0,      0},
27463         {"WQ_INT"                      ,        0,      16,     515,    "R/W1C",        0,      1,      0ull,   0},
27464         {"IQ_DIS"                      ,        16,     16,     515,    "R/W1", 0,      1,      0ull,   0},
27465         {"RESERVED_32_63"              ,        32,     32,     515,    "RAZ",  1,      1,      0,      0},
27466         {"IQ_CNT"                      ,        0,      12,     516,    "RO",   0,      1,      0ull,   0},
27467         {"DS_CNT"                      ,        12,     12,     516,    "RO",   0,      1,      0ull,   0},
27468         {"TC_CNT"                      ,        24,     4,      516,    "RO",   0,      1,      0ull,   0},
27469         {"RESERVED_28_63"              ,        28,     36,     516,    "RAZ",  1,      1,      0,      0},
27470         {"RESERVED_0_7"                ,        0,      8,      517,    "RAZ",  1,      1,      0,      0},
27471         {"PC_THR"                      ,        8,      20,     517,    "R/W",  0,      1,      0ull,   0},
27472         {"RESERVED_28_31"              ,        28,     4,      517,    "RAZ",  1,      1,      0,      0},
27473         {"PC"                          ,        32,     28,     517,    "RO",   0,      1,      0ull,   0},
27474         {"RESERVED_60_63"              ,        60,     4,      517,    "RAZ",  1,      1,      0,      0},
27475         {"IQ_THR"                      ,        0,      11,     518,    "R/W",  0,      1,      0ull,   0},
27476         {"RESERVED_11_11"              ,        11,     1,      518,    "RAZ",  1,      1,      0,      0},
27477         {"DS_THR"                      ,        12,     11,     518,    "R/W",  0,      1,      0ull,   0},
27478         {"RESERVED_23_23"              ,        23,     1,      518,    "RAZ",  1,      1,      0,      0},
27479         {"TC_THR"                      ,        24,     4,      518,    "R/W",  0,      1,      0ull,   0},
27480         {"TC_EN"                       ,        28,     1,      518,    "R/W",  0,      1,      0ull,   0},
27481         {"RESERVED_29_63"              ,        29,     35,     518,    "RAZ",  1,      1,      0,      0},
27482         {"WS_PC"                       ,        0,      32,     519,    "R/W1C",        0,      1,      0ull,   0},
27483         {"RESERVED_32_63"              ,        32,     32,     519,    "RAZ",  1,      1,      0,      0},
27484         {"MEM"                         ,        0,      1,      520,    "RO",   0,      0,      0ull,   0ull},
27485         {"RRC"                         ,        1,      1,      520,    "RO",   0,      0,      0ull,   0ull},
27486         {"RESERVED_2_63"               ,        2,      62,     520,    "RAZ",  1,      1,      0,      0},
27487         {"ENT_EN"                      ,        0,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
27488         {"RNG_EN"                      ,        1,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
27489         {"RNM_RST"                     ,        2,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
27490         {"RNG_RST"                     ,        3,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
27491         {"EXP_ENT"                     ,        4,      1,      521,    "R/W",  0,      0,      0ull,   0ull},
27492         {"ENT_SEL"                     ,        5,      4,      521,    "R/W",  0,      0,      0ull,   0ull},
27493         {"RESERVED_9_63"               ,        9,      55,     521,    "RAZ",  1,      1,      0,      0},
27494         {"PHASE"                       ,        0,      8,      522,    "R/W",  0,      0,      100ull, 100ull},
27495         {"SAMPLE"                      ,        8,      4,      522,    "R/W",  0,      0,      2ull,   2ull},
27496         {"PREAMBLE"                    ,        12,     1,      522,    "R/W",  0,      0,      1ull,   1ull},
27497         {"CLK_IDLE"                    ,        13,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
27498         {"RESERVED_14_14"              ,        14,     1,      522,    "RAZ",  1,      1,      0,      0},
27499         {"SAMPLE_MODE"                 ,        15,     1,      522,    "RAZ",  0,      0,      0ull,   0ull},
27500         {"SAMPLE_HI"                   ,        16,     5,      522,    "R/W",  0,      0,      0ull,   0ull},
27501         {"RESERVED_21_63"              ,        21,     43,     522,    "RAZ",  1,      1,      0,      0},
27502         {"REG_ADR"                     ,        0,      5,      523,    "R/W",  0,      1,      0ull,   0},
27503         {"RESERVED_5_7"                ,        5,      3,      523,    "RAZ",  1,      1,      0,      0},
27504         {"PHY_ADR"                     ,        8,      5,      523,    "R/W",  0,      1,      0ull,   0},
27505         {"RESERVED_13_15"              ,        13,     3,      523,    "RAZ",  1,      1,      0,      0},
27506         {"PHY_OP"                      ,        16,     1,      523,    "R/W",  0,      1,      0ull,   0},
27507         {"RESERVED_17_63"              ,        17,     47,     523,    "RAZ",  1,      1,      0,      0},
27508         {"EN"                          ,        0,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
27509         {"RESERVED_1_63"               ,        1,      63,     524,    "RAZ",  1,      1,      0,      0},
27510         {"DAT"                         ,        0,      16,     525,    "RO",   0,      1,      0ull,   0},
27511         {"VAL"                         ,        16,     1,      525,    "RO",   0,      1,      0ull,   0},
27512         {"PENDING"                     ,        17,     1,      525,    "RO",   0,      1,      0ull,   0},
27513         {"RESERVED_18_63"              ,        18,     46,     525,    "RAZ",  1,      1,      0,      0},
27514         {"DAT"                         ,        0,      16,     526,    "R/W",  0,      1,      0ull,   0},
27515         {"VAL"                         ,        16,     1,      526,    "RO",   0,      1,      0ull,   0},
27516         {"PENDING"                     ,        17,     1,      526,    "RO",   0,      1,      0ull,   0},
27517         {"RESERVED_18_63"              ,        18,     46,     526,    "RAZ",  1,      1,      0,      0},
27518         {"CNT"                         ,        0,      32,     527,    "R/W1C",        0,      0,      0ull,   0ull},
27519         {"RESERVED_32_63"              ,        32,     32,     527,    "RAZ",  0,      0,      0ull,   0ull},
27520         {"STAT0"                       ,        0,      1,      528,    "RO",   0,      0,      0ull,   0ull},
27521         {"STAT1"                       ,        1,      1,      528,    "RO",   0,      0,      0ull,   0ull},
27522         {"STAT2"                       ,        2,      1,      528,    "RO",   0,      0,      0ull,   0ull},
27523         {"RESERVED_3_63"               ,        3,      61,     528,    "RAZ",  0,      0,      0ull,   0ull},
27524         {"SRXDLCK"                     ,        0,      1,      529,    "R/W",  0,      0,      0ull,   1ull},
27525         {"RCVTRN"                      ,        1,      1,      529,    "R/W",  0,      0,      0ull,   1ull},
27526         {"DRPTRN"                      ,        2,      1,      529,    "R/W",  0,      0,      0ull,   1ull},
27527         {"SNDTRN"                      ,        3,      1,      529,    "R/W",  0,      0,      0ull,   1ull},
27528         {"STATRCV"                     ,        4,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
27529         {"STATDRV"                     ,        5,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
27530         {"RUNBIST"                     ,        6,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
27531         {"CLKDLY"                      ,        7,      5,      529,    "R/W",  0,      0,      16ull,  16ull},
27532         {"RESERVED_12_15"              ,        12,     4,      529,    "RAZ",  0,      0,      0ull,   0ull},
27533         {"SEETRN"                      ,        16,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
27534         {"RESERVED_17_63"              ,        17,     47,     529,    "RAZ",  0,      0,      0ull,   0ull},
27535         {"RESERVED_0_3"                ,        0,      4,      530,    "RAZ",  0,      1,      0ull,   0},
27536         {"D4CLK0"                      ,        4,      1,      530,    "R/W1C",        0,      1,      0ull,   0},
27537         {"D4CLK1"                      ,        5,      1,      530,    "R/W1C",        0,      1,      0ull,   0},
27538         {"S4CLK0"                      ,        6,      1,      530,    "R/W1C",        0,      1,      0ull,   0},
27539         {"S4CLK1"                      ,        7,      1,      530,    "R/W1C",        0,      1,      0ull,   0},
27540         {"SRXTRN"                      ,        8,      1,      530,    "R/W1C",        0,      1,      0ull,   0},
27541         {"RESERVED_9_9"                ,        9,      1,      530,    "RAZ",  0,      1,      0ull,   0},
27542         {"STXCAL"                      ,        10,     1,      530,    "R/W1C",        0,      1,      0ull,   0},
27543         {"RESERVED_11_63"              ,        11,     53,     530,    "RAZ",  0,      0,      0ull,   0ull},
27544         {"DLLDIS"                      ,        0,      1,      531,    "R/W",  1,      0,      0,      0ull},
27545         {"DLLFRC"                      ,        1,      1,      531,    "WR0",  1,      0,      0,      0ull},
27546         {"OFFDLY"                      ,        2,      6,      531,    "R/W",  1,      0,      0,      0ull},
27547         {"BITSEL"                      ,        8,      5,      531,    "R/W",  1,      1,      0,      0},
27548         {"OFFSET"                      ,        13,     5,      531,    "R/W",  1,      1,      0,      0},
27549         {"MUX"                         ,        18,     1,      531,    "WR0",  1,      1,      0,      0},
27550         {"INC"                         ,        19,     1,      531,    "WR0",  1,      1,      0,      0},
27551         {"DEC"                         ,        20,     1,      531,    "WR0",  1,      1,      0,      0},
27552         {"CLRDLY"                      ,        21,     1,      531,    "WR0",  1,      1,      0,      0},
27553         {"RESERVED_22_23"              ,        22,     2,      531,    "RAZ",  0,      0,      0ull,   0ull},
27554         {"SSTEP"                       ,        24,     1,      531,    "R/W",  1,      0,      0,      0ull},
27555         {"SSTEP_GO"                    ,        25,     1,      531,    "WR0",  1,      1,      0,      0},
27556         {"RESERVED_26_27"              ,        26,     2,      531,    "RAZ",  0,      0,      0ull,   0ull},
27557         {"FALL8"                       ,        28,     1,      531,    "R/W",  0,      0,      0ull,   0ull},
27558         {"FALLNOP"                     ,        29,     1,      531,    "R/W",  0,      0,      0ull,   0ull},
27559         {"RESERVED_30_63"              ,        30,     34,     531,    "RAZ",  0,      0,      0ull,   0ull},
27560         {"OFFSET"                      ,        0,      5,      532,    "RO",   0,      1,      0ull,   0},
27561         {"MUXSEL"                      ,        5,      2,      532,    "RO",   0,      1,      0ull,   0},
27562         {"UNXTERM"                     ,        7,      1,      532,    "R/W1C",        0,      0,      0ull,   0ull},
27563         {"TESTRES"                     ,        8,      1,      532,    "R/W1C",        0,      0,      0ull,   0ull},
27564         {"RESERVED_9_63"               ,        9,      55,     532,    "RAZ",  0,      0,      0ull,   0ull},
27565         {"SRX4CMP"                     ,        0,      10,     533,    "R/W",  0,      0,      239ull, 239ull},
27566         {"RESERVED_10_15"              ,        10,     6,      533,    "RAZ",  0,      0,      0ull,   0ull},
27567         {"STX4PCMP"                    ,        16,     4,      533,    "R/W",  0,      0,      3ull,   3ull},
27568         {"STX4NCMP"                    ,        20,     4,      533,    "R/W",  0,      0,      12ull,  12ull},
27569         {"RESERVED_24_63"              ,        24,     40,     533,    "RAZ",  0,      0,      0ull,   0ull},
27570         {"ERRCNT"                      ,        0,      4,      534,    "R/W",  0,      0,      0ull,   3ull},
27571         {"RESERVED_4_5"                ,        4,      2,      534,    "RAZ",  0,      0,      0ull,   0ull},
27572         {"DIPPAY"                      ,        6,      1,      534,    "R/W",  0,      0,      0ull,   0ull},
27573         {"DIPCLS"                      ,        7,      1,      534,    "R/W",  0,      0,      0ull,   0ull},
27574         {"PRTNXA"                      ,        8,      1,      534,    "R/W",  0,      0,      0ull,   0ull},
27575         {"RESERVED_9_63"               ,        9,      55,     534,    "RAZ",  0,      0,      0ull,   0ull},
27576         {"PRT"                         ,        0,      8,      535,    "RO",   0,      0,      0ull,   0ull},
27577         {"RSVOP"                       ,        8,      4,      535,    "RO",   0,      0,      0ull,   0ull},
27578         {"CALBNK"                      ,        12,     2,      535,    "RO",   0,      0,      0ull,   0ull},
27579         {"RESERVED_14_30"              ,        14,     17,     535,    "RAZ",  0,      0,      0ull,   0ull},
27580         {"MUL"                         ,        31,     1,      535,    "RO",   0,      0,      0ull,   0ull},
27581         {"RESERVED_32_63"              ,        32,     32,     535,    "RAZ",  0,      0,      0ull,   0ull},
27582         {"PRTNXA"                      ,        0,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
27583         {"ABNORM"                      ,        1,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
27584         {"RESERVED_2_3"                ,        2,      2,      536,    "RAZ",  0,      0,      0ull,   0ull},
27585         {"SPIOVR"                      ,        4,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
27586         {"CLSERR"                      ,        5,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
27587         {"DRWNNG"                      ,        6,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
27588         {"RSVERR"                      ,        7,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
27589         {"TPAOVR"                      ,        8,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
27590         {"DIPERR"                      ,        9,      1,      536,    "R/W",  0,      0,      0ull,   0ull},
27591         {"SYNCERR"                     ,        10,     1,      536,    "R/W",  0,      0,      0ull,   0ull},
27592         {"CALERR"                      ,        11,     1,      536,    "R/W",  0,      0,      0ull,   0ull},
27593         {"RESERVED_12_63"              ,        12,     52,     536,    "RAZ",  0,      0,      0ull,   0ull},
27594         {"PRTNXA"                      ,        0,      1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27595         {"ABNORM"                      ,        1,      1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27596         {"RESERVED_2_3"                ,        2,      2,      537,    "RAZ",  0,      0,      0ull,   0ull},
27597         {"SPIOVR"                      ,        4,      1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27598         {"CLSERR"                      ,        5,      1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27599         {"DRWNNG"                      ,        6,      1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27600         {"RSVERR"                      ,        7,      1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27601         {"TPAOVR"                      ,        8,      1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27602         {"DIPERR"                      ,        9,      1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27603         {"SYNCERR"                     ,        10,     1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27604         {"CALERR"                      ,        11,     1,      537,    "R/W1C",        0,      0,      0ull,   0ull},
27605         {"RESERVED_12_30"              ,        12,     19,     537,    "RAZ",  0,      0,      0ull,   0ull},
27606         {"SPF"                         ,        31,     1,      537,    "RO",   0,      0,      0ull,   0ull},
27607         {"RESERVED_32_63"              ,        32,     32,     537,    "RAZ",  0,      0,      0ull,   0ull},
27608         {"PRTNXA"                      ,        0,      1,      538,    "R/W",  0,      0,      0ull,   0ull},
27609         {"ABNORM"                      ,        1,      1,      538,    "R/W",  0,      0,      0ull,   0ull},
27610         {"RESERVED_2_3"                ,        2,      2,      538,    "RAZ",  0,      0,      0ull,   0ull},
27611         {"SPIOVR"                      ,        4,      1,      538,    "R/W",  0,      0,      0ull,   0ull},
27612         {"CLSERR"                      ,        5,      1,      538,    "R/W",  0,      0,      0ull,   0ull},
27613         {"DRWNNG"                      ,        6,      1,      538,    "R/W",  0,      0,      0ull,   0ull},
27614         {"RSVERR"                      ,        7,      1,      538,    "R/W",  0,      0,      0ull,   0ull},
27615         {"TPAOVR"                      ,        8,      1,      538,    "R/W",  0,      0,      0ull,   0ull},
27616         {"DIPERR"                      ,        9,      1,      538,    "R/W",  0,      0,      0ull,   0ull},
27617         {"SYNCERR"                     ,        10,     1,      538,    "R/W",  0,      0,      0ull,   0ull},
27618         {"CALERR"                      ,        11,     1,      538,    "R/W",  0,      0,      0ull,   0ull},
27619         {"RESERVED_12_63"              ,        12,     52,     538,    "RAZ",  0,      0,      0ull,   0ull},
27620         {"CNT"                         ,        0,      32,     539,    "RO",   0,      1,      0ull,   0},
27621         {"RESERVED_32_63"              ,        32,     32,     539,    "RAZ",  0,      0,      0ull,   0ull},
27622         {"MAX"                         ,        0,      32,     540,    "R/W",  0,      0,      0ull,   0ull},
27623         {"RESERVED_32_63"              ,        32,     32,     540,    "RAZ",  0,      0,      0ull,   0ull},
27624         {"PRTSEL"                      ,        0,      4,      541,    "R/W",  0,      0,      0ull,   0ull},
27625         {"RESERVED_4_63"               ,        4,      60,     541,    "RAZ",  0,      0,      0ull,   0ull},
27626         {"MUX_EN"                      ,        0,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
27627         {"MACRO_EN"                    ,        1,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
27628         {"MAXDIST"                     ,        2,      5,      542,    "R/W",  0,      0,      0ull,   8ull},
27629         {"SET_BOOT"                    ,        7,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
27630         {"CLR_BOOT"                    ,        8,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
27631         {"JITTER"                      ,        9,      3,      542,    "R/W",  0,      0,      0ull,   1ull},
27632         {"TRNTEST"                     ,        12,     1,      542,    "R/W",  0,      0,      0ull,   0ull},
27633         {"RESERVED_13_63"              ,        13,     51,     542,    "RAZ",  0,      0,      0ull,   0ull},
27634         {"INF_EN"                      ,        0,      1,      543,    "R/W",  0,      0,      0ull,   1ull},
27635         {"RESERVED_1_2"                ,        1,      2,      543,    "RAZ",  0,      0,      0ull,   0ull},
27636         {"ST_EN"                       ,        3,      1,      543,    "R/W",  0,      0,      0ull,   1ull},
27637         {"PRTS"                        ,        4,      4,      543,    "R/W",  0,      1,      0ull,   0},
27638         {"RESERVED_8_63"               ,        8,      56,     543,    "RAZ",  0,      0,      0ull,   0ull},
27639         {"IGNORE"                      ,        0,      16,     544,    "R/W",  0,      0,      0ull,   0ull},
27640         {"RESERVED_16_63"              ,        16,     48,     544,    "RAZ",  0,      0,      0ull,   0ull},
27641         {"PRT0"                        ,        0,      4,      545,    "R/W",  1,      1,      0,      0},
27642         {"PRT1"                        ,        4,      4,      545,    "R/W",  1,      1,      0,      0},
27643         {"PRT2"                        ,        8,      4,      545,    "R/W",  1,      1,      0,      0},
27644         {"PRT3"                        ,        12,     4,      545,    "R/W",  1,      1,      0,      0},
27645         {"ODDPAR"                      ,        16,     1,      545,    "R/W",  1,      1,      0,      0},
27646         {"RESERVED_17_63"              ,        17,     47,     545,    "RAZ",  0,      0,      0ull,   0ull},
27647         {"LEN"                         ,        0,      7,      546,    "R/W",  0,      1,      0ull,   0},
27648         {"RESERVED_7_7"                ,        7,      1,      546,    "RAZ",  0,      0,      0ull,   0ull},
27649         {"M"                           ,        8,      8,      546,    "R/W",  0,      1,      0ull,   0},
27650         {"RESERVED_16_63"              ,        16,     48,     546,    "RAZ",  0,      0,      0ull,   0ull},
27651         {"ADR"                         ,        0,      4,      547,    "R/W",  0,      0,      0ull,   0ull},
27652         {"OPC"                         ,        4,      4,      547,    "R/W",  0,      0,      0ull,   0ull},
27653         {"MOD"                         ,        8,      4,      547,    "R/W",  0,      0,      0ull,   0ull},
27654         {"SOP"                         ,        12,     1,      547,    "R/W",  0,      0,      0ull,   0ull},
27655         {"EOP"                         ,        13,     1,      547,    "R/W",  0,      0,      0ull,   0ull},
27656         {"RESERVED_14_63"              ,        14,     50,     547,    "RAZ",  0,      0,      0ull,   0ull},
27657         {"DAT"                         ,        0,      64,     548,    "R/W",  0,      0,      0ull,   0ull},
27658         {"RESERVED_0_2"                ,        0,      3,      549,    "R/W",  0,      0,      0ull,   0ull},
27659         {"IGNTPA"                      ,        3,      1,      549,    "R/W",  0,      0,      0ull,   0ull},
27660         {"RESERVED_4_4"                ,        4,      1,      549,    "R/W",  0,      0,      0ull,   0ull},
27661         {"MINTRN"                      ,        5,      1,      549,    "R/W",  0,      0,      0ull,   0ull},
27662         {"RESERVED_6_63"               ,        6,      58,     549,    "RAZ",  0,      0,      0ull,   0ull},
27663         {"CNT"                         ,        0,      32,     550,    "R/W1C",        0,      0,      0ull,   0ull},
27664         {"RESERVED_32_63"              ,        32,     32,     550,    "RAZ",  0,      0,      0ull,   0ull},
27665         {"INF_EN"                      ,        0,      1,      551,    "R/W",  0,      0,      0ull,   1ull},
27666         {"RESERVED_1_2"                ,        1,      2,      551,    "RAZ",  0,      0,      0ull,   0ull},
27667         {"ST_EN"                       ,        3,      1,      551,    "R/W",  0,      0,      0ull,   1ull},
27668         {"RESERVED_4_63"               ,        4,      60,     551,    "RAZ",  0,      0,      0ull,   0ull},
27669         {"DIPMAX"                      ,        0,      4,      552,    "R/W",  0,      0,      0ull,   0ull},
27670         {"FRMMAX"                      ,        4,      4,      552,    "R/W",  0,      0,      0ull,   0ull},
27671         {"RESERVED_8_63"               ,        8,      56,     552,    "RAZ",  0,      0,      0ull,   0ull},
27672         {"IGNTPA"                      ,        0,      16,     553,    "R/W",  0,      0,      0ull,   0ull},
27673         {"RESERVED_16_63"              ,        16,     48,     553,    "RAZ",  0,      0,      0ull,   0ull},
27674         {"CALPAR0"                     ,        0,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
27675         {"CALPAR1"                     ,        1,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
27676         {"OVRBST"                      ,        2,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
27677         {"DATOVR"                      ,        3,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
27678         {"DIPERR"                      ,        4,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
27679         {"NOSYNC"                      ,        5,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
27680         {"UNXFRM"                      ,        6,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
27681         {"FRMERR"                      ,        7,      1,      554,    "R/W",  0,      0,      0ull,   0ull},
27682         {"RESERVED_8_63"               ,        8,      56,     554,    "RAZ",  0,      0,      0ull,   0ull},
27683         {"CALPAR0"                     ,        0,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
27684         {"CALPAR1"                     ,        1,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
27685         {"OVRBST"                      ,        2,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
27686         {"DATOVR"                      ,        3,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
27687         {"DIPERR"                      ,        4,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
27688         {"NOSYNC"                      ,        5,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
27689         {"UNXFRM"                      ,        6,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
27690         {"FRMERR"                      ,        7,      1,      555,    "R/W1C",        0,      0,      0ull,   0ull},
27691         {"SYNCERR"                     ,        8,      1,      555,    "RO",   0,      0,      0ull,   0ull},
27692         {"RESERVED_9_63"               ,        9,      55,     555,    "RAZ",  0,      0,      0ull,   0ull},
27693         {"CALPAR0"                     ,        0,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
27694         {"CALPAR1"                     ,        1,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
27695         {"OVRBST"                      ,        2,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
27696         {"DATOVR"                      ,        3,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
27697         {"DIPERR"                      ,        4,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
27698         {"NOSYNC"                      ,        5,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
27699         {"UNXFRM"                      ,        6,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
27700         {"FRMERR"                      ,        7,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
27701         {"RESERVED_8_63"               ,        8,      56,     556,    "RAZ",  0,      0,      0ull,   0ull},
27702         {"MINB"                        ,        0,      9,      557,    "R/W",  0,      0,      0ull,   0ull},
27703         {"RESERVED_9_63"               ,        9,      55,     557,    "RAZ",  0,      0,      0ull,   0ull},
27704         {"PRT0"                        ,        0,      4,      558,    "R/W",  1,      1,      0,      0},
27705         {"PRT1"                        ,        4,      4,      558,    "R/W",  1,      1,      0,      0},
27706         {"PRT2"                        ,        8,      4,      558,    "R/W",  1,      1,      0,      0},
27707         {"PRT3"                        ,        12,     4,      558,    "R/W",  1,      1,      0,      0},
27708         {"ODDPAR"                      ,        16,     1,      558,    "R/W",  1,      1,      0,      0},
27709         {"RESERVED_17_63"              ,        17,     47,     558,    "RAZ",  0,      0,      0ull,   0ull},
27710         {"MAX_T"                       ,        0,      16,     559,    "R/W",  0,      1,      0ull,   0},
27711         {"ALPHA"                       ,        16,     16,     559,    "R/W",  0,      1,      0ull,   0},
27712         {"RESERVED_32_63"              ,        32,     32,     559,    "RAZ",  0,      0,      0ull,   0ull},
27713         {"LEN"                         ,        0,      7,      560,    "R/W",  0,      1,      0ull,   0},
27714         {"RESERVED_7_7"                ,        7,      1,      560,    "RAZ",  0,      0,      0ull,   0ull},
27715         {"M"                           ,        8,      8,      560,    "R/W",  0,      1,      0ull,   0},
27716         {"RESERVED_16_63"              ,        16,     48,     560,    "RAZ",  0,      0,      0ull,   0ull},
27717         {"CNT"                         ,        0,      32,     561,    "RO",   0,      0,      0ull,   0ull},
27718         {"RESERVED_32_63"              ,        32,     32,     561,    "RAZ",  0,      0,      0ull,   0ull},
27719         {"CNT"                         ,        0,      32,     562,    "RO",   0,      0,      0ull,   0ull},
27720         {"RESERVED_32_63"              ,        32,     32,     562,    "RAZ",  0,      0,      0ull,   0ull},
27721         {"BCKPRS"                      ,        0,      4,      563,    "R/W",  0,      0,      0ull,   0ull},
27722         {"CLR"                         ,        4,      1,      563,    "WR0",  0,      0,      0ull,   0ull},
27723         {"RESERVED_5_63"               ,        5,      59,     563,    "RAZ",  0,      0,      0ull,   0ull},
27724         {"CNT"                         ,        0,      32,     564,    "RO",   0,      0,      0ull,   0ull},
27725         {"RESERVED_32_63"              ,        32,     32,     564,    "RAZ",  0,      0,      0ull,   0ull},
27726         {"INTERVAL"                    ,        0,      22,     565,    "RO",   1,      0,      0,      0ull},
27727         {"RESERVED_22_23"              ,        22,     2,      565,    "RAZ",  1,      0,      0,      0ull},
27728         {"COUNT"                       ,        24,     22,     565,    "RO",   1,      0,      0,      0ull},
27729         {"RESERVED_46_46"              ,        46,     1,      565,    "RAZ",  1,      0,      0,      0ull},
27730         {"ENA"                         ,        47,     1,      565,    "RO",   1,      0,      0,      0ull},
27731         {"RESERVED_48_63"              ,        48,     16,     565,    "RAZ",  1,      0,      0,      0ull},
27732         {"BSIZE"                       ,        0,      20,     566,    "RO",   1,      0,      0,      0ull},
27733         {"BASE"                        ,        20,     31,     566,    "RO",   1,      0,      0,      0ull},
27734         {"BUCKET"                      ,        51,     13,     566,    "RO",   1,      0,      0,      0ull},
27735         {"BUCKET"                      ,        0,      7,      567,    "RO",   1,      0,      0,      0ull},
27736         {"RESERVED_7_7"                ,        7,      1,      567,    "RAZ",  1,      0,      0,      0ull},
27737         {"CSIZE"                       ,        8,      13,     567,    "RO",   1,      0,      0,      0ull},
27738         {"CPOOL"                       ,        21,     3,      567,    "RO",   1,      0,      0,      0ull},
27739         {"RESERVED_24_63"              ,        24,     40,     567,    "RAZ",  1,      0,      0,      0ull},
27740         {"RING"                        ,        0,      4,      568,    "R/W",  0,      0,      0ull,   0ull},
27741         {"NUM_BUCKETS"                 ,        4,      20,     568,    "R/W",  0,      0,      0ull,   0ull},
27742         {"FIRST_BUCKET"                ,        24,     31,     568,    "R/W",  0,      0,      0ull,   0ull},
27743         {"RESERVED_55_63"              ,        55,     9,      568,    "RAZ",  1,      0,      0,      0ull},
27744         {"RING"                        ,        0,      4,      569,    "R/W",  0,      0,      0ull,   0ull},
27745         {"INTERVAL"                    ,        4,      22,     569,    "R/W",  0,      0,      0ull,   0ull},
27746         {"WORDS_PER_CHUNK"             ,        26,     13,     569,    "R/W",  0,      0,      0ull,   0ull},
27747         {"POOL"                        ,        39,     3,      569,    "R/W",  0,      0,      0ull,   0ull},
27748         {"ENABLE"                      ,        42,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
27749         {"RESERVED_43_63"              ,        43,     21,     569,    "RAZ",  1,      0,      0,      0ull},
27750         {"CTL"                         ,        0,      1,      570,    "RO",   1,      0,      0,      0ull},
27751         {"NCB"                         ,        1,      1,      570,    "RO",   1,      0,      0,      0ull},
27752         {"STA"                         ,        2,      2,      570,    "RO",   1,      0,      0,      0ull},
27753         {"RESERVED_4_63"               ,        4,      60,     570,    "RAZ",  1,      0,      0,      0ull},
27754         {"MASK"                        ,        0,      16,     571,    "R/W1C",        0,      0,      0ull,   0ull},
27755         {"RESERVED_16_63"              ,        16,     48,     571,    "RAZ",  1,      0,      0,      0ull},
27756         {"ENABLE_TIMERS"               ,        0,      1,      572,    "R/W",  0,      0,      0ull,   0ull},
27757         {"ENABLE_DWB"                  ,        1,      1,      572,    "R/W",  0,      0,      0ull,   0ull},
27758         {"RESET"                       ,        2,      1,      572,    "RAZ",  0,      0,      0ull,   0ull},
27759         {"RESERVED_3_63"               ,        3,      61,     572,    "RAZ",  1,      0,      0,      0ull},
27760         {"MASK"                        ,        0,      16,     573,    "R/W",  0,      0,      0ull,   0ull},
27761         {"RESERVED_16_63"              ,        16,     48,     573,    "RAZ",  1,      0,      0,      0ull},
27762         {"INDEX"                       ,        0,      8,      574,    "R/W",  0,      0,      0ull,   0ull},
27763         {"INC"                         ,        8,      8,      574,    "R/W",  0,      0,      0ull,   0ull},
27764         {"RESERVED_16_63"              ,        16,     48,     574,    "RAZ",  1,      0,      0,      0ull},
27765         {"TDF0"                        ,        0,      1,      575,    "RO",   0,      0,      0ull,   0ull},
27766         {"TDF1"                        ,        1,      1,      575,    "RO",   0,      0,      0ull,   0ull},
27767         {"TCF"                         ,        2,      1,      575,    "RO",   0,      0,      0ull,   0ull},
27768         {"RESERVED_3_63"               ,        3,      61,     575,    "RAZ",  0,      0,      0ull,   0ull},
27769         {"ENA"                         ,        0,      1,      576,    "R/W",  0,      0,      0ull,   0ull},
27770         {"WRAP"                        ,        1,      1,      576,    "R/W",  0,      0,      0ull,   0ull},
27771         {"TRIG_CTL"                    ,        2,      2,      576,    "R/W",  0,      0,      0ull,   0ull},
27772         {"TIME_GRN"                    ,        4,      3,      576,    "R/W",  0,      0,      0ull,   0ull},
27773         {"FULL_THR"                    ,        7,      2,      576,    "R/W",  0,      0,      0ull,   0ull},
27774         {"CIU_TRG"                     ,        9,      1,      576,    "R/W",  0,      0,      0ull,   0ull},
27775         {"CIU_THR"                     ,        10,     1,      576,    "R/W",  0,      0,      0ull,   0ull},
27776         {"MCD0_TRG"                    ,        11,     1,      576,    "R/W",  0,      0,      0ull,   0ull},
27777         {"MCD0_THR"                    ,        12,     1,      576,    "R/W",  0,      0,      0ull,   0ull},
27778         {"MCD0_ENA"                    ,        13,     1,      576,    "R/W",  0,      0,      0ull,   0ull},
27779         {"IGNORE_O"                    ,        14,     1,      576,    "R/W",  0,      0,      0ull,   0ull},
27780         {"RESERVED_15_63"              ,        15,     49,     576,    "RAZ",  0,      0,      0ull,   0ull},
27781         {"WPTR"                        ,        0,      8,      577,    "RO",   0,      0,      0ull,   0ull},
27782         {"RPTR"                        ,        8,      8,      577,    "RO",   0,      0,      0ull,   0ull},
27783         {"CYCLES"                      ,        16,     48,     577,    "RO",   0,      0,      0ull,   0ull},
27784         {"WPTR"                        ,        0,      10,     578,    "RO",   0,      0,      0ull,   0ull},
27785         {"RESERVED_10_11"              ,        10,     2,      578,    "RAZ",  0,      0,      0ull,   0ull},
27786         {"RPTR"                        ,        12,     10,     578,    "RO",   0,      0,      0ull,   0ull},
27787         {"RESERVED_22_23"              ,        22,     2,      578,    "RAZ",  0,      0,      0ull,   0ull},
27788         {"CYCLES"                      ,        24,     40,     578,    "RO",   0,      0,      0ull,   0ull},
27789         {"ADR"                         ,        0,      36,     579,    "R/W",  0,      1,      0ull,   0},
27790         {"RESERVED_36_63"              ,        36,     28,     579,    "RAZ",  0,      0,      0ull,   0ull},
27791         {"ADR"                         ,        0,      36,     580,    "R/W",  0,      0,      0ull,   0ull},
27792         {"RESERVED_36_63"              ,        36,     28,     580,    "RAZ",  0,      0,      0ull,   0ull},
27793         {"DWB"                         ,        0,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27794         {"PL2"                         ,        1,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27795         {"PSL1"                        ,        2,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27796         {"LDD"                         ,        3,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27797         {"LDI"                         ,        4,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27798         {"LDT"                         ,        5,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27799         {"STF"                         ,        6,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27800         {"STC"                         ,        7,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27801         {"STP"                         ,        8,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27802         {"STT"                         ,        9,      1,      581,    "R/W",  0,      0,      0ull,   1ull},
27803         {"IOBLD8"                      ,        10,     1,      581,    "R/W",  0,      0,      0ull,   1ull},
27804         {"IOBLD16"                     ,        11,     1,      581,    "R/W",  0,      0,      0ull,   1ull},
27805         {"IOBLD32"                     ,        12,     1,      581,    "R/W",  0,      0,      0ull,   1ull},
27806         {"IOBLD64"                     ,        13,     1,      581,    "R/W",  0,      0,      0ull,   1ull},
27807         {"IOBST"                       ,        14,     1,      581,    "R/W",  0,      0,      0ull,   1ull},
27808         {"IOBDMA"                      ,        15,     1,      581,    "R/W",  0,      0,      0ull,   1ull},
27809         {"SAA"                         ,        16,     1,      581,    "R/W",  0,      0,      0ull,   1ull},
27810         {"RESERVED_17_63"              ,        17,     47,     581,    "RAZ",  0,      0,      0ull,   0ull},
27811         {"MIO"                         ,        0,      1,      582,    "R/W",  0,      0,      0ull,   1ull},
27812         {"ILLEGAL3"                    ,        1,      2,      582,    "R/W",  0,      0,      0ull,   3ull},
27813         {"PCI"                         ,        3,      1,      582,    "R/W",  0,      0,      0ull,   1ull},
27814         {"KEY"                         ,        4,      1,      582,    "R/W",  0,      0,      0ull,   1ull},
27815         {"FPA"                         ,        5,      1,      582,    "R/W",  0,      0,      0ull,   1ull},
27816         {"DFA"                         ,        6,      1,      582,    "R/W",  0,      0,      0ull,   1ull},
27817         {"ZIP"                         ,        7,      1,      582,    "R/W",  0,      0,      0ull,   1ull},
27818         {"RNG"                         ,        8,      1,      582,    "R/W",  0,      0,      0ull,   1ull},
27819         {"ILLEGAL2"                    ,        9,      3,      582,    "R/W",  0,      0,      0ull,   7ull},
27820         {"POW"                         ,        12,     1,      582,    "R/W",  0,      0,      0ull,   1ull},
27821         {"ILLEGAL"                     ,        13,     19,     582,    "R/W",  0,      0,      0ull,   524287ull},
27822         {"RESERVED_32_63"              ,        32,     32,     582,    "RAZ",  0,      0,      0ull,   0ull},
27823         {"PP"                          ,        0,      16,     583,    "R/W",  0,      0,      0ull,   0ull},
27824         {"PKI"                         ,        16,     1,      583,    "R/W",  0,      0,      0ull,   0ull},
27825         {"PKO"                         ,        17,     1,      583,    "R/W",  0,      0,      0ull,   0ull},
27826         {"IOBREQ"                      ,        18,     1,      583,    "R/W",  0,      0,      0ull,   0ull},
27827         {"DWB"                         ,        19,     1,      583,    "R/W",  0,      0,      0ull,   0ull},
27828         {"RESERVED_20_63"              ,        20,     44,     583,    "RAZ",  0,      0,      0ull,   0ull},
27829         {"CIU_TRG"                     ,        0,      1,      584,    "R/W1C",        0,      0,      0ull,   0ull},
27830         {"CIU_THR"                     ,        1,      1,      584,    "R/W1C",        0,      0,      0ull,   0ull},
27831         {"MCD0_TRG"                    ,        2,      1,      584,    "R/W1C",        0,      0,      0ull,   0ull},
27832         {"MCD0_THR"                    ,        3,      1,      584,    "R/W1C",        0,      0,      0ull,   0ull},
27833         {"RESERVED_4_63"               ,        4,      60,     584,    "RAZ",  0,      0,      0ull,   0ull},
27834         {"DATA"                        ,        0,      64,     585,    "RO",   0,      0,      0ull,   0ull},
27835         {"ADR"                         ,        0,      36,     586,    "R/W",  0,      1,      0ull,   0},
27836         {"RESERVED_36_63"              ,        36,     28,     586,    "RAZ",  0,      0,      0ull,   0ull},
27837         {"ADR"                         ,        0,      36,     587,    "R/W",  0,      0,      0ull,   0ull},
27838         {"RESERVED_36_63"              ,        36,     28,     587,    "RAZ",  0,      0,      0ull,   0ull},
27839         {"DWB"                         ,        0,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27840         {"PL2"                         ,        1,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27841         {"PSL1"                        ,        2,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27842         {"LDD"                         ,        3,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27843         {"LDI"                         ,        4,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27844         {"LDT"                         ,        5,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27845         {"STF"                         ,        6,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27846         {"STC"                         ,        7,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27847         {"STP"                         ,        8,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27848         {"STT"                         ,        9,      1,      588,    "R/W",  0,      0,      0ull,   1ull},
27849         {"IOBLD8"                      ,        10,     1,      588,    "R/W",  0,      0,      0ull,   1ull},
27850         {"IOBLD16"                     ,        11,     1,      588,    "R/W",  0,      0,      0ull,   1ull},
27851         {"IOBLD32"                     ,        12,     1,      588,    "R/W",  0,      0,      0ull,   1ull},
27852         {"IOBLD64"                     ,        13,     1,      588,    "R/W",  0,      0,      0ull,   1ull},
27853         {"IOBST"                       ,        14,     1,      588,    "R/W",  0,      0,      0ull,   1ull},
27854         {"IOBDMA"                      ,        15,     1,      588,    "R/W",  0,      0,      0ull,   1ull},
27855         {"SAA"                         ,        16,     1,      588,    "R/W",  0,      0,      0ull,   1ull},
27856         {"RESERVED_17_63"              ,        17,     47,     588,    "RAZ",  0,      0,      0ull,   0ull},
27857         {"MIO"                         ,        0,      1,      589,    "R/W",  0,      0,      0ull,   1ull},
27858         {"ILLEGAL3"                    ,        1,      2,      589,    "R/W",  0,      0,      0ull,   3ull},
27859         {"PCI"                         ,        3,      1,      589,    "R/W",  0,      0,      0ull,   1ull},
27860         {"KEY"                         ,        4,      1,      589,    "R/W",  0,      0,      0ull,   1ull},
27861         {"FPA"                         ,        5,      1,      589,    "R/W",  0,      0,      0ull,   1ull},
27862         {"DFA"                         ,        6,      1,      589,    "R/W",  0,      0,      0ull,   1ull},
27863         {"ZIP"                         ,        7,      1,      589,    "R/W",  0,      0,      0ull,   1ull},
27864         {"RNG"                         ,        8,      1,      589,    "R/W",  0,      0,      0ull,   1ull},
27865         {"ILLEGAL2"                    ,        9,      3,      589,    "R/W",  0,      0,      0ull,   7ull},
27866         {"POW"                         ,        12,     1,      589,    "R/W",  0,      0,      0ull,   1ull},
27867         {"ILLEGAL"                     ,        13,     19,     589,    "R/W",  0,      0,      0ull,   524287ull},
27868         {"RESERVED_32_63"              ,        32,     32,     589,    "RAZ",  0,      0,      0ull,   0ull},
27869         {"PP"                          ,        0,      16,     590,    "R/W",  0,      0,      0ull,   0ull},
27870         {"PKI"                         ,        16,     1,      590,    "R/W",  0,      0,      0ull,   0ull},
27871         {"PKO"                         ,        17,     1,      590,    "R/W",  0,      0,      0ull,   0ull},
27872         {"IOBREQ"                      ,        18,     1,      590,    "R/W",  0,      0,      0ull,   0ull},
27873         {"DWB"                         ,        19,     1,      590,    "R/W",  0,      0,      0ull,   0ull},
27874         {"RESERVED_20_63"              ,        20,     44,     590,    "RAZ",  0,      0,      0ull,   0ull},
27875         {"ADR"                         ,        0,      36,     591,    "R/W",  0,      1,      0ull,   0},
27876         {"RESERVED_36_63"              ,        36,     28,     591,    "RAZ",  0,      0,      0ull,   0ull},
27877         {"ADR"                         ,        0,      36,     592,    "R/W",  0,      0,      0ull,   0ull},
27878         {"RESERVED_36_63"              ,        36,     28,     592,    "RAZ",  0,      0,      0ull,   0ull},
27879         {"DWB"                         ,        0,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27880         {"PL2"                         ,        1,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27881         {"PSL1"                        ,        2,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27882         {"LDD"                         ,        3,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27883         {"LDI"                         ,        4,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27884         {"LDT"                         ,        5,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27885         {"STF"                         ,        6,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27886         {"STC"                         ,        7,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27887         {"STP"                         ,        8,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27888         {"STT"                         ,        9,      1,      593,    "R/W",  0,      0,      0ull,   1ull},
27889         {"IOBLD8"                      ,        10,     1,      593,    "R/W",  0,      0,      0ull,   1ull},
27890         {"IOBLD16"                     ,        11,     1,      593,    "R/W",  0,      0,      0ull,   1ull},
27891         {"IOBLD32"                     ,        12,     1,      593,    "R/W",  0,      0,      0ull,   1ull},
27892         {"IOBLD64"                     ,        13,     1,      593,    "R/W",  0,      0,      0ull,   1ull},
27893         {"IOBST"                       ,        14,     1,      593,    "R/W",  0,      0,      0ull,   1ull},
27894         {"IOBDMA"                      ,        15,     1,      593,    "R/W",  0,      0,      0ull,   1ull},
27895         {"SAA"                         ,        16,     1,      593,    "R/W",  0,      0,      0ull,   1ull},
27896         {"RESERVED_17_63"              ,        17,     47,     593,    "RAZ",  0,      0,      0ull,   0ull},
27897         {"MIO"                         ,        0,      1,      594,    "R/W",  0,      0,      0ull,   1ull},
27898         {"ILLEGAL3"                    ,        1,      2,      594,    "R/W",  0,      0,      0ull,   3ull},
27899         {"PCI"                         ,        3,      1,      594,    "R/W",  0,      0,      0ull,   1ull},
27900         {"KEY"                         ,        4,      1,      594,    "R/W",  0,      0,      0ull,   1ull},
27901         {"FPA"                         ,        5,      1,      594,    "R/W",  0,      0,      0ull,   1ull},
27902         {"DFA"                         ,        6,      1,      594,    "R/W",  0,      0,      0ull,   1ull},
27903         {"ZIP"                         ,        7,      1,      594,    "R/W",  0,      0,      0ull,   1ull},
27904         {"RNG"                         ,        8,      1,      594,    "R/W",  0,      0,      0ull,   1ull},
27905         {"ILLEGAL2"                    ,        9,      3,      594,    "R/W",  0,      0,      0ull,   7ull},
27906         {"POW"                         ,        12,     1,      594,    "R/W",  0,      0,      0ull,   1ull},
27907         {"ILLEGAL"                     ,        13,     19,     594,    "R/W",  0,      0,      0ull,   524287ull},
27908         {"RESERVED_32_63"              ,        32,     32,     594,    "RAZ",  0,      0,      0ull,   0ull},
27909         {"PP"                          ,        0,      16,     595,    "R/W",  0,      0,      0ull,   0ull},
27910         {"PKI"                         ,        16,     1,      595,    "R/W",  0,      0,      0ull,   0ull},
27911         {"PKO"                         ,        17,     1,      595,    "R/W",  0,      0,      0ull,   0ull},
27912         {"IOBREQ"                      ,        18,     1,      595,    "R/W",  0,      0,      0ull,   0ull},
27913         {"DWB"                         ,        19,     1,      595,    "R/W",  0,      0,      0ull,   0ull},
27914         {"RESERVED_20_63"              ,        20,     44,     595,    "RAZ",  0,      0,      0ull,   0ull},
27915         {"ZIP_CTL"                     ,        0,      4,      596,    "RO",   1,      0,      0,      0ull},
27916         {"ZIP_CORE"                    ,        4,      27,     596,    "RO",   1,      0,      0,      0ull},
27917         {"RESERVED_31_63"              ,        31,     33,     596,    "RAZ",  1,      0,      0,      0ull},
27918         {"PTR"                         ,        0,      33,     597,    "R/W",  0,      0,      0ull,   0ull},
27919         {"SIZE"                        ,        33,     13,     597,    "R/W",  0,      0,      0ull,   0ull},
27920         {"POOL"                        ,        46,     3,      597,    "R/W",  0,      0,      0ull,   0ull},
27921         {"DWB"                         ,        49,     9,      597,    "R/W",  0,      0,      0ull,   0ull},
27922         {"RESERVED_58_63"              ,        58,     6,      597,    "RAZ",  0,      0,      0ull,   0ull},
27923         {"RESET"                       ,        0,      1,      598,    "RAZ",  0,      0,      0ull,   0ull},
27924         {"FORCECLK"                    ,        1,      1,      598,    "R/W",  0,      0,      0ull,   0ull},
27925         {"RESERVED_2_63"               ,        2,      62,     598,    "RAZ",  0,      0,      0ull,   0ull},
27926         {"DISABLED"                    ,        0,      1,      599,    "RO",   0,      0,      0ull,   0ull},
27927         {"RESERVED_1_7"                ,        1,      7,      599,    "RAZ",  0,      0,      0ull,   0ull},
27928         {"CTXSIZE"                     ,        8,      12,     599,    "RO",   0,      0,      1536ull,        1536ull},
27929         {"ONFSIZE"                     ,        20,     12,     599,    "RO",   0,      0,      512ull, 512ull},
27930         {"DEPTH"                       ,        32,     16,     599,    "RO",   0,      0,      31744ull,       31744ull},
27931         {"RESERVED_48_63"              ,        48,     16,     599,    "RAZ",  1,      0,      0,      0ull},
27932         {"ASSERTS"                     ,        0,      14,     600,    "RO",   0,      0,      0ull,   0ull},
27933         {"RESERVED_14_63"              ,        14,     50,     600,    "RAZ",  1,      0,      0,      0ull},
27934         {"DOORBELL"                    ,        0,      1,      601,    "R/W1C",        0,      0,      0ull,   0ull},
27935         {"RESERVED_1_63"               ,        1,      63,     601,    "RAZ",  1,      0,      0,      0ull},
27936         {"DOORBELL"                    ,        0,      1,      602,    "R/W",  0,      0,      0ull,   0ull},
27937         {"RESERVED_1_63"               ,        1,      63,     602,    "RAZ",  1,      0,      0,      0ull},
27938         {NULL,0,0,0,0,0,0,0,0}
27939 };
27940 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn58xx[] = {
27941          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
27942         {"cvmx_asx#_int_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      4,      0},
27943         {"cvmx_asx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      4,      4},
27944         {"cvmx_asx#_prt_loop"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      3,      8},
27945         {"cvmx_asx#_rld_bypass"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      2,      11},
27946         {"cvmx_asx#_rld_bypass_setting",        CVMX_CSR_DB_TYPE_RSL,   64,     8,      2,      13},
27947         {"cvmx_asx#_rld_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     3,      15},
27948         {"cvmx_asx#_rld_data_drv"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     12,     3,      18},
27949         {"cvmx_asx#_rld_nctl_strong"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     2,      21},
27950         {"cvmx_asx#_rld_nctl_weak"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     16,     2,      23},
27951         {"cvmx_asx#_rld_pctl_strong"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     18,     2,      25},
27952         {"cvmx_asx#_rld_pctl_weak"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     20,     2,      27},
27953         {"cvmx_asx#_rld_setting"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     22,     6,      29},
27954         {"cvmx_asx#_rx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     24,     2,      35},
27955         {"cvmx_asx#_rx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     32,     2,      37},
27956         {"cvmx_asx#_tx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     34,     2,      39},
27957         {"cvmx_asx#_tx_comp_byp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     42,     4,      41},
27958         {"cvmx_asx#_tx_hi_water#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     44,     2,      45},
27959         {"cvmx_asx#_tx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     52,     2,      47},
27960         {"cvmx_asx0_dbg_data_drv"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     54,     3,      49},
27961         {"cvmx_asx0_dbg_data_enable"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     55,     2,      52},
27962         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     56,     2,      54},
27963         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     57,     2,      56},
27964         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     58,     2,      58},
27965         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     59,     2,      60},
27966         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     60,     15,     62},
27967         {"cvmx_ciu_int#_en0_w1c"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     93,     15,     77},
27968         {"cvmx_ciu_int#_en0_w1s"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     126,    15,     92},
27969         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     159,    2,      107},
27970         {"cvmx_ciu_int#_en1_w1c"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     192,    2,      109},
27971         {"cvmx_ciu_int#_en1_w1s"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     225,    2,      111},
27972         {"cvmx_ciu_int#_en4_0"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     258,    15,     113},
27973         {"cvmx_ciu_int#_en4_0_w1c"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     274,    15,     128},
27974         {"cvmx_ciu_int#_en4_0_w1s"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     290,    15,     143},
27975         {"cvmx_ciu_int#_en4_1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     306,    2,      158},
27976         {"cvmx_ciu_int#_en4_1_w1c"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     322,    2,      160},
27977         {"cvmx_ciu_int#_en4_1_w1s"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     338,    2,      162},
27978         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     354,    15,     164},
27979         {"cvmx_ciu_int#_sum4"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     387,    15,     179},
27980         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     403,    2,      194},
27981         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     404,    2,      196},
27982         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     420,    2,      198},
27983         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     436,    2,      200},
27984         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     437,    2,      202},
27985         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     438,    2,      204},
27986         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     439,    1,      206},
27987         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     455,    3,      207},
27988         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     456,    2,      210},
27989         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     457,    4,      212},
27990         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     458,    2,      216},
27991         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     459,    3,      218},
27992         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     463,    7,      221},
27993         {"cvmx_dbg_data"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     479,    5,      228},
27994         {"cvmx_dfa_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     480,    4,      233},
27995         {"cvmx_dfa_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     481,    10,     237},
27996         {"cvmx_dfa_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     482,    5,      247},
27997         {"cvmx_dfa_dbell"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     483,    2,      252},
27998         {"cvmx_dfa_difctl"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     484,    4,      254},
27999         {"cvmx_dfa_difrdptr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     485,    3,      258},
28000         {"cvmx_dfa_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     486,    21,     261},
28001         {"cvmx_dfa_memcfg0"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     487,    20,     282},
28002         {"cvmx_dfa_memcfg1"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     488,    11,     302},
28003         {"cvmx_dfa_memcfg2"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     489,    8,      313},
28004         {"cvmx_dfa_memfadr"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     490,    6,      321},
28005         {"cvmx_dfa_memfcr"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     491,    6,      327},
28006         {"cvmx_dfa_memrld"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     492,    2,      333},
28007         {"cvmx_dfa_ncbctl"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     493,    8,      335},
28008         {"cvmx_dfa_rodt_comp_ctl"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     494,    6,      343},
28009         {"cvmx_dfa_sbd_dbg0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     495,    1,      349},
28010         {"cvmx_dfa_sbd_dbg1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     496,    1,      350},
28011         {"cvmx_dfa_sbd_dbg2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     497,    1,      351},
28012         {"cvmx_dfa_sbd_dbg3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     498,    1,      352},
28013         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     499,    6,      353},
28014         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     500,    7,      359},
28015         {"cvmx_fpa_fpf#_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     501,    3,      366},
28016         {"cvmx_fpa_fpf#_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     508,    2,      369},
28017         {"cvmx_fpa_fpf0_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     515,    3,      371},
28018         {"cvmx_fpa_fpf0_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     516,    2,      374},
28019         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     517,    29,     376},
28020         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     518,    29,     405},
28021         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     519,    2,      434},
28022         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     527,    2,      436},
28023         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     535,    3,      438},
28024         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     536,    3,      441},
28025         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     537,    2,      444},
28026         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     538,    2,      446},
28027         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     539,    8,      448},
28028         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     541,    2,      456},
28029         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     543,    3,      458},
28030         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     545,    2,      461},
28031         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     547,    5,      463},
28032         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     555,    1,      468},
28033         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     563,    1,      469},
28034         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     571,    1,      470},
28035         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     579,    1,      471},
28036         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     587,    1,      472},
28037         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     595,    1,      473},
28038         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     603,    2,      474},
28039         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     611,    4,      476},
28040         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     619,    2,      480},
28041         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     627,    11,     482},
28042         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     635,    12,     493},
28043         {"cvmx_gmx#_rx#_frm_max"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     643,    2,      505},
28044         {"cvmx_gmx#_rx#_frm_min"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     651,    2,      507},
28045         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     659,    2,      509},
28046         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     667,    21,     511},
28047         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     675,    21,     532},
28048         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     683,    2,      553},
28049         {"cvmx_gmx#_rx#_pause_drop_time",       CVMX_CSR_DB_TYPE_RSL,   64,     691,    2,      555},
28050         {"cvmx_gmx#_rx#_rx_inbnd"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     699,    4,      557},
28051         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     707,    2,      561},
28052         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     715,    2,      563},
28053         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     723,    2,      565},
28054         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     731,    2,      567},
28055         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     739,    2,      569},
28056         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     747,    2,      571},
28057         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     755,    2,      573},
28058         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     763,    2,      575},
28059         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     771,    2,      577},
28060         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     779,    2,      579},
28061         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     787,    4,      581},
28062         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     795,    2,      585},
28063         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     803,    2,      587},
28064         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     811,    2,      589},
28065         {"cvmx_gmx#_rx_pass_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     819,    2,      591},
28066         {"cvmx_gmx#_rx_pass_map#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     821,    2,      593},
28067         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     853,    3,      595},
28068         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     855,    2,      598},
28069         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     857,    2,      600},
28070         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     865,    3,      602},
28071         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     867,    5,      605},
28072         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     875,    2,      610},
28073         {"cvmx_gmx#_tx#_clk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     883,    2,      612},
28074         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     891,    3,      614},
28075         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     899,    2,      617},
28076         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     907,    2,      619},
28077         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     915,    2,      621},
28078         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     923,    2,      623},
28079         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     931,    2,      625},
28080         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     939,    2,      627},
28081         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     947,    2,      629},
28082         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     955,    2,      631},
28083         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     963,    2,      633},
28084         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     971,    2,      635},
28085         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     979,    2,      637},
28086         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     987,    2,      639},
28087         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     995,    2,      641},
28088         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1003,   2,      643},
28089         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1011,   2,      645},
28090         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1019,   2,      647},
28091         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1027,   2,      649},
28092         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1035,   2,      651},
28093         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1043,   2,      653},
28094         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1051,   2,      655},
28095         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1053,   2,      657},
28096         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1055,   2,      659},
28097         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1057,   3,      661},
28098         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1059,   8,      664},
28099         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1061,   8,      672},
28100         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1063,   2,      680},
28101         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1065,   2,      682},
28102         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1067,   4,      684},
28103         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1069,   2,      688},
28104         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1071,   2,      690},
28105         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1073,   2,      692},
28106         {"cvmx_gmx#_tx_spi_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1075,   3,      694},
28107         {"cvmx_gmx#_tx_spi_drain"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1077,   2,      697},
28108         {"cvmx_gmx#_tx_spi_max"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1079,   4,      699},
28109         {"cvmx_gmx#_tx_spi_round#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1081,   2,      703},
28110         {"cvmx_gmx#_tx_spi_thresh"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1145,   2,      705},
28111         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1147,   7,      707},
28112         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1163,   2,      714},
28113         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1164,   2,      716},
28114         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1165,   2,      718},
28115         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1166,   2,      720},
28116         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1167,   19,     722},
28117         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1168,   6,      741},
28118         {"cvmx_iob_dwb_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1169,   3,      747},
28119         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1170,   3,      750},
28120         {"cvmx_iob_i2c_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1171,   3,      753},
28121         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1172,   5,      756},
28122         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     1173,   5,      761},
28123         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1174,   1,      766},
28124         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1175,   1,      767},
28125         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1176,   7,      768},
28126         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1177,   7,      775},
28127         {"cvmx_iob_n2c_l2c_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1178,   3,      782},
28128         {"cvmx_iob_n2c_rsp_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1179,   3,      785},
28129         {"cvmx_iob_outb_com_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1180,   3,      788},
28130         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1181,   5,      791},
28131         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     1182,   5,      796},
28132         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1183,   1,      801},
28133         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     1184,   1,      802},
28134         {"cvmx_iob_outb_fpa_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1185,   3,      803},
28135         {"cvmx_iob_outb_req_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1186,   3,      806},
28136         {"cvmx_iob_p2c_req_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1187,   3,      809},
28137         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1188,   2,      812},
28138         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1189,   2,      814},
28139         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1190,   2,      816},
28140         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1191,   2,      818},
28141         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1192,   17,     820},
28142         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1193,   2,      837},
28143         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1194,   1,      839},
28144         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1195,   12,     840},
28145         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1196,   11,     852},
28146         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1197,   11,     863},
28147         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     1198,   2,      874},
28148         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1199,   2,      876},
28149         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1200,   2,      878},
28150         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1201,   3,      880},
28151         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     1237,   2,      883},
28152         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     1273,   6,      885},
28153         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     1274,   5,      891},
28154         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1275,   6,      896},
28155         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1276,   7,      902},
28156         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1277,   2,      909},
28157         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     1285,   2,      911},
28158         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1286,   3,      913},
28159         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1287,   5,      916},
28160         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     1295,   3,      921},
28161         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1296,   2,      924},
28162         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1297,   2,      926},
28163         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1298,   2,      928},
28164         {"cvmx_key_bist_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1299,   4,      930},
28165         {"cvmx_key_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1300,   3,      934},
28166         {"cvmx_key_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1301,   5,      937},
28167         {"cvmx_key_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1302,   5,      942},
28168         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1303,   7,      947},
28169         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1304,   5,      954},
28170         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1305,   8,      959},
28171         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1306,   13,     967},
28172         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1307,   8,      980},
28173         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1308,   5,      988},
28174         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1309,   4,      993},
28175         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1310,   2,      997},
28176         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1311,   14,     999},
28177         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1312,   19,     1013},
28178         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1313,   3,      1032},
28179         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1314,   3,      1035},
28180         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1315,   2,      1038},
28181         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1319,   17,     1040},
28182         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1320,   5,      1057},
28183         {"cvmx_l2c_spar1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1321,   5,      1062},
28184         {"cvmx_l2c_spar2"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1322,   5,      1067},
28185         {"cvmx_l2c_spar3"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1323,   5,      1072},
28186         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1324,   2,      1077},
28187         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1325,   3,      1079},
28188         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1326,   2,      1082},
28189         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1327,   2,      1084},
28190         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1328,   2,      1086},
28191         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1329,   7,      1088},
28192         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1330,   5,      1095},
28193         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1331,   3,      1100},
28194         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1332,   3,      1103},
28195         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1333,   2,      1106},
28196         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1334,   2,      1108},
28197         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1335,   2,      1110},
28198         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1336,   6,      1112},
28199         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1337,   14,     1118},
28200         {"cvmx_led_blink"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1338,   2,      1132},
28201         {"cvmx_led_clk_phase"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1339,   2,      1134},
28202         {"cvmx_led_cylon"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1340,   2,      1136},
28203         {"cvmx_led_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1341,   2,      1138},
28204         {"cvmx_led_en"                 ,        CVMX_CSR_DB_TYPE_RSL,   64,     1342,   2,      1140},
28205         {"cvmx_led_polarity"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1343,   2,      1142},
28206         {"cvmx_led_prt"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1344,   2,      1144},
28207         {"cvmx_led_prt_fmt"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1345,   2,      1146},
28208         {"cvmx_led_prt_status#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1346,   2,      1148},
28209         {"cvmx_led_udd_cnt#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1354,   2,      1150},
28210         {"cvmx_led_udd_dat#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1356,   2,      1152},
28211         {"cvmx_led_udd_dat_clr#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1358,   2,      1154},
28212         {"cvmx_led_udd_dat_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1360,   2,      1156},
28213         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1362,   7,      1158},
28214         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1363,   19,     1165},
28215         {"cvmx_lmc#_ctl1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1364,   4,      1184},
28216         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1365,   2,      1188},
28217         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1366,   2,      1190},
28218         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1367,   18,     1192},
28219         {"cvmx_lmc#_delay_cfg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1368,   6,      1210},
28220         {"cvmx_lmc#_dual_memcfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1369,   5,      1216},
28221         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1370,   5,      1221},
28222         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1371,   6,      1226},
28223         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1372,   2,      1232},
28224         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1373,   2,      1234},
28225         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1374,   14,     1236},
28226         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1375,   9,      1250},
28227         {"cvmx_lmc#_nxm"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1376,   2,      1259},
28228         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1377,   2,      1261},
28229         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1378,   2,      1263},
28230         {"cvmx_lmc#_pll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1379,   12,     1265},
28231         {"cvmx_lmc#_pll_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1380,   6,      1277},
28232         {"cvmx_lmc#_rodt_comp_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1381,   6,      1283},
28233         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1382,   9,      1289},
28234         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1383,   9,      1298},
28235         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1384,   4,      1307},
28236         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1385,   3,      1311},
28237         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1386,   3,      1314},
28238         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1387,   3,      1317},
28239         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1388,   5,      1320},
28240         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1390,   1,      1325},
28241         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1391,   10,     1326},
28242         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1399,   13,     1336},
28243         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1407,   4,      1349},
28244         {"cvmx_mio_fus_bnk_dat#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1408,   1,      1353},
28245         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1412,   2,      1354},
28246         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1413,   2,      1356},
28247         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1414,   9,      1358},
28248         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1415,   8,      1367},
28249         {"cvmx_mio_fus_ema"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1416,   2,      1375},
28250         {"cvmx_mio_fus_pdf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1417,   1,      1377},
28251         {"cvmx_mio_fus_pll"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1418,   3,      1378},
28252         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1419,   2,      1381},
28253         {"cvmx_mio_fus_prog_times"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1420,   6,      1383},
28254         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1421,   8,      1389},
28255         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1422,   4,      1397},
28256         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1423,   2,      1401},
28257         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1424,   2,      1403},
28258         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1425,   13,     1405},
28259         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1426,   12,     1418},
28260         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1427,   3,      1430},
28261         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1428,   3,      1433},
28262         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1429,   2,      1436},
28263         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1431,   2,      1438},
28264         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1433,   2,      1440},
28265         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1435,   7,      1442},
28266         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1437,   2,      1449},
28267         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1439,   7,      1451},
28268         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1441,   4,      1458},
28269         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1443,   8,      1462},
28270         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1445,   9,      1470},
28271         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1447,   7,      1479},
28272         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1449,   9,      1486},
28273         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1451,   2,      1495},
28274         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1453,   2,      1497},
28275         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1455,   4,      1499},
28276         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1457,   2,      1503},
28277         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1459,   2,      1505},
28278         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1461,   2,      1507},
28279         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1463,   4,      1509},
28280         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1465,   2,      1513},
28281         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1467,   2,      1515},
28282         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1469,   2,      1517},
28283         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1471,   2,      1519},
28284         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1473,   2,      1521},
28285         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1475,   2,      1523},
28286         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1477,   6,      1525},
28287         {"cvmx_npi_base_addr_input#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1479,   2,      1531},
28288         {"cvmx_npi_base_addr_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1483,   2,      1533},
28289         {"cvmx_npi_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1487,   21,     1535},
28290         {"cvmx_npi_buff_size_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1488,   3,      1556},
28291         {"cvmx_npi_comp_ctl"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1492,   3,      1559},
28292         {"cvmx_npi_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1493,   21,     1562},
28293         {"cvmx_npi_dbg_select"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1494,   2,      1583},
28294         {"cvmx_npi_dma_control"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1495,   13,     1585},
28295         {"cvmx_npi_dma_highp_counts"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1496,   3,      1598},
28296         {"cvmx_npi_dma_highp_naddr"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1497,   3,      1601},
28297         {"cvmx_npi_dma_lowp_counts"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1498,   3,      1604},
28298         {"cvmx_npi_dma_lowp_naddr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1499,   3,      1607},
28299         {"cvmx_npi_highp_dbell"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1500,   2,      1610},
28300         {"cvmx_npi_highp_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1501,   2,      1612},
28301         {"cvmx_npi_input_control"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1502,   10,     1614},
28302         {"cvmx_npi_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1503,   63,     1624},
28303         {"cvmx_npi_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1504,   63,     1687},
28304         {"cvmx_npi_lowp_dbell"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1505,   2,      1750},
28305         {"cvmx_npi_lowp_ibuff_saddr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1506,   2,      1752},
28306         {"cvmx_npi_mem_access_subid#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1507,   10,     1754},
28307         {"cvmx_npi_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1511,   1,      1764},
28308         {"cvmx_npi_num_desc_output#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1512,   2,      1765},
28309         {"cvmx_npi_output_control"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1516,   39,     1767},
28310         {"cvmx_npi_p#_dbpair_addr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1517,   3,      1806},
28311         {"cvmx_npi_p#_instr_addr"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1521,   2,      1809},
28312         {"cvmx_npi_p#_instr_cnts"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1525,   3,      1811},
28313         {"cvmx_npi_p#_pair_cnts"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1529,   3,      1814},
28314         {"cvmx_npi_pci_burst_size"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1533,   3,      1817},
28315         {"cvmx_npi_pci_int_arb_cfg"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1534,   7,      1820},
28316         {"cvmx_npi_pci_read_cmd"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1535,   2,      1827},
28317         {"cvmx_npi_port32_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1536,   13,     1829},
28318         {"cvmx_npi_port33_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1537,   13,     1842},
28319         {"cvmx_npi_port34_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1538,   13,     1855},
28320         {"cvmx_npi_port35_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1539,   13,     1868},
28321         {"cvmx_npi_port_bp_control"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1540,   3,      1881},
28322         {"cvmx_npi_rsl_int_blocks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1541,   33,     1884},
28323         {"cvmx_npi_size_input#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1542,   2,      1917},
28324         {"cvmx_npi_win_read_to"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1546,   2,      1919},
28325         {"cvmx_pci_bar1_index#"        ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1547,   5,      1921},
28326         {"cvmx_pci_cfg00"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1579,   2,      1926},
28327         {"cvmx_pci_cfg01"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1580,   24,     1928},
28328         {"cvmx_pci_cfg02"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1581,   2,      1952},
28329         {"cvmx_pci_cfg03"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1582,   7,      1954},
28330         {"cvmx_pci_cfg04"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1583,   5,      1961},
28331         {"cvmx_pci_cfg05"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1584,   1,      1966},
28332         {"cvmx_pci_cfg06"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1585,   5,      1967},
28333         {"cvmx_pci_cfg07"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1586,   1,      1972},
28334         {"cvmx_pci_cfg08"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1587,   4,      1973},
28335         {"cvmx_pci_cfg09"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1588,   2,      1977},
28336         {"cvmx_pci_cfg10"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1589,   1,      1979},
28337         {"cvmx_pci_cfg11"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1590,   2,      1980},
28338         {"cvmx_pci_cfg12"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1591,   4,      1982},
28339         {"cvmx_pci_cfg13"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1592,   2,      1986},
28340         {"cvmx_pci_cfg15"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1593,   4,      1988},
28341         {"cvmx_pci_cfg16"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1594,   16,     1992},
28342         {"cvmx_pci_cfg17"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1595,   1,      2008},
28343         {"cvmx_pci_cfg18"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1596,   1,      2009},
28344         {"cvmx_pci_cfg19"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1597,   18,     2010},
28345         {"cvmx_pci_cfg20"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1598,   1,      2028},
28346         {"cvmx_pci_cfg21"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1599,   1,      2029},
28347         {"cvmx_pci_cfg22"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1600,   7,      2030},
28348         {"cvmx_pci_cfg56"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1601,   7,      2037},
28349         {"cvmx_pci_cfg57"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1602,   13,     2044},
28350         {"cvmx_pci_cfg58"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1603,   10,     2057},
28351         {"cvmx_pci_cfg59"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1604,   10,     2067},
28352         {"cvmx_pci_cfg60"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1605,   7,      2077},
28353         {"cvmx_pci_cfg61"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1606,   2,      2084},
28354         {"cvmx_pci_cfg62"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1607,   1,      2086},
28355         {"cvmx_pci_cfg63"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     1608,   2,      2087},
28356         {"cvmx_pci_cnt_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1609,   6,      2089},
28357         {"cvmx_pci_ctl_status_2"       ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1610,   22,     2095},
28358         {"cvmx_pci_dbell#"             ,        CVMX_CSR_DB_TYPE_PCI,   32,     1611,   2,      2117},
28359         {"cvmx_pci_dma_cnt#"           ,        CVMX_CSR_DB_TYPE_PCI,   32,     1615,   1,      2119},
28360         {"cvmx_pci_dma_int_lev#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1617,   1,      2120},
28361         {"cvmx_pci_dma_time#"          ,        CVMX_CSR_DB_TYPE_PCI,   32,     1619,   1,      2121},
28362         {"cvmx_pci_instr_count#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1621,   1,      2122},
28363         {"cvmx_pci_int_enb"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     1625,   35,     2123},
28364         {"cvmx_pci_int_enb2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1626,   35,     2158},
28365         {"cvmx_pci_int_sum"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     1627,   35,     2193},
28366         {"cvmx_pci_int_sum2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1628,   35,     2228},
28367         {"cvmx_pci_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI,   32,     1629,   2,      2263},
28368         {"cvmx_pci_pkt_credits#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     1630,   2,      2265},
28369         {"cvmx_pci_pkts_sent#"         ,        CVMX_CSR_DB_TYPE_PCI,   32,     1634,   1,      2267},
28370         {"cvmx_pci_pkts_sent_int_lev#" ,        CVMX_CSR_DB_TYPE_PCI,   32,     1638,   1,      2268},
28371         {"cvmx_pci_pkts_sent_time#"    ,        CVMX_CSR_DB_TYPE_PCI,   32,     1642,   1,      2269},
28372         {"cvmx_pci_read_cmd_6"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1646,   3,      2270},
28373         {"cvmx_pci_read_cmd_c"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1647,   3,      2273},
28374         {"cvmx_pci_read_cmd_e"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     1648,   3,      2276},
28375         {"cvmx_pci_read_timeout"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1649,   3,      2279},
28376         {"cvmx_pci_scm_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1650,   2,      2282},
28377         {"cvmx_pci_tsr_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     1651,   2,      2284},
28378         {"cvmx_pci_win_rd_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1652,   4,      2286},
28379         {"cvmx_pci_win_rd_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1653,   1,      2290},
28380         {"cvmx_pci_win_wr_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1654,   4,      2291},
28381         {"cvmx_pci_win_wr_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1655,   1,      2295},
28382         {"cvmx_pci_win_wr_mask"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     1656,   2,      2296},
28383         {"cvmx_pip_bck_prs"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1657,   5,      2298},
28384         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1658,   2,      2303},
28385         {"cvmx_pip_crc_ctl#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1659,   3,      2305},
28386         {"cvmx_pip_crc_iv#"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1661,   2,      2308},
28387         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1663,   4,      2310},
28388         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1667,   8,      2314},
28389         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1668,   16,     2322},
28390         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1669,   12,     2338},
28391         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1670,   12,     2350},
28392         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1671,   2,      2362},
28393         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1672,   19,     2364},
28394         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1708,   25,     2383},
28395         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1744,   2,      2408},
28396         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1808,   2,      2410},
28397         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1816,   9,      2412},
28398         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1820,   2,      2421},
28399         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1821,   2,      2423},
28400         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1822,   2,      2425},
28401         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1858,   2,      2427},
28402         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1894,   2,      2429},
28403         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1930,   2,      2431},
28404         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1966,   2,      2433},
28405         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2002,   2,      2435},
28406         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2038,   2,      2437},
28407         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2074,   2,      2439},
28408         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2110,   2,      2441},
28409         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2146,   2,      2443},
28410         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2182,   2,      2445},
28411         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2183,   2,      2447},
28412         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2219,   2,      2449},
28413         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2255,   2,      2451},
28414         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2291,   2,      2453},
28415         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2355,   2,      2455},
28416         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2356,   3,      2457},
28417         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2357,   3,      2460},
28418         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2358,   2,      2463},
28419         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2359,   2,      2465},
28420         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2360,   4,      2467},
28421         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2361,   5,      2471},
28422         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2362,   4,      2476},
28423         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2363,   8,      2480},
28424         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2364,   4,      2488},
28425         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2365,   5,      2492},
28426         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2366,   5,      2497},
28427         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2367,   1,      2502},
28428         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2368,   18,     2503},
28429         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2369,   4,      2521},
28430         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2370,   2,      2525},
28431         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2371,   6,      2527},
28432         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2372,   7,      2533},
28433         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2373,   4,      2540},
28434         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2374,   9,      2544},
28435         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2375,   5,      2553},
28436         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2376,   15,     2558},
28437         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2377,   4,      2573},
28438         {"cvmx_pko_reg_crc_ctl#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2378,   3,      2577},
28439         {"cvmx_pko_reg_crc_enable"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2380,   2,      2580},
28440         {"cvmx_pko_reg_crc_iv#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2381,   2,      2582},
28441         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2383,   1,      2584},
28442         {"cvmx_pko_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2384,   1,      2585},
28443         {"cvmx_pko_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2385,   1,      2586},
28444         {"cvmx_pko_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2386,   1,      2587},
28445         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2387,   4,      2588},
28446         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2388,   5,      2592},
28447         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2389,   3,      2597},
28448         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2390,   4,      2600},
28449         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2391,   2,      2604},
28450         {"cvmx_pko_reg_queue_ptrs1"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2392,   3,      2606},
28451         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2393,   3,      2609},
28452         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2394,   13,     2612},
28453         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2395,   2,      2625},
28454         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2396,   13,     2627},
28455         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2397,   3,      2640},
28456         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2398,   2,      2643},
28457         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2406,   2,      2645},
28458         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2407,   2,      2647},
28459         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2408,   2,      2649},
28460         {"cvmx_pow_pf_rst_msk"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2409,   2,      2651},
28461         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2410,   10,     2653},
28462         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2426,   5,      2663},
28463         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2434,   8,      2668},
28464         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2442,   2,      2676},
28465         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2443,   2,      2678},
28466         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2444,   2,      2680},
28467         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2452,   3,      2682},
28468         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2453,   4,      2685},
28469         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2469,   5,      2689},
28470         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2470,   7,      2694},
28471         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2486,   2,      2701},
28472         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2502,   3,      2703},
28473         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2503,   7,      2706},
28474         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2504,   8,      2713},
28475         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2505,   6,      2721},
28476         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2506,   2,      2727},
28477         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2507,   4,      2729},
28478         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2508,   4,      2733},
28479         {"cvmx_spx#_bckprs_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2509,   2,      2737},
28480         {"cvmx_spx#_bist_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2511,   4,      2739},
28481         {"cvmx_spx#_clk_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2513,   11,     2743},
28482         {"cvmx_spx#_clk_stat"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2515,   9,      2754},
28483         {"cvmx_spx#_dbg_deskew_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2517,   16,     2763},
28484         {"cvmx_spx#_dbg_deskew_state"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2519,   5,      2779},
28485         {"cvmx_spx#_drv_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2521,   5,      2784},
28486         {"cvmx_spx#_err_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2523,   6,      2789},
28487         {"cvmx_spx#_int_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2525,   6,      2795},
28488         {"cvmx_spx#_int_msk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2527,   12,     2801},
28489         {"cvmx_spx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2529,   14,     2813},
28490         {"cvmx_spx#_int_sync"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2531,   12,     2827},
28491         {"cvmx_spx#_tpa_acc"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2533,   2,      2839},
28492         {"cvmx_spx#_tpa_max"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2535,   2,      2841},
28493         {"cvmx_spx#_tpa_sel"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2537,   2,      2843},
28494         {"cvmx_spx#_trn4_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2539,   8,      2845},
28495         {"cvmx_srx#_com_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2541,   5,      2853},
28496         {"cvmx_srx#_ign_rx_full"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2543,   2,      2858},
28497         {"cvmx_srx#_spi4_cal#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2545,   6,      2860},
28498         {"cvmx_srx#_spi4_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2609,   4,      2866},
28499         {"cvmx_srx#_sw_tick_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2611,   6,      2870},
28500         {"cvmx_srx#_sw_tick_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2613,   1,      2876},
28501         {"cvmx_stx#_arb_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2615,   5,      2877},
28502         {"cvmx_stx#_bckprs_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2617,   2,      2882},
28503         {"cvmx_stx#_com_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2619,   4,      2884},
28504         {"cvmx_stx#_dip_cnt"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2621,   3,      2888},
28505         {"cvmx_stx#_ign_cal"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2623,   2,      2891},
28506         {"cvmx_stx#_int_msk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2625,   9,      2893},
28507         {"cvmx_stx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2627,   10,     2902},
28508         {"cvmx_stx#_int_sync"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2629,   9,      2912},
28509         {"cvmx_stx#_min_bst"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2631,   2,      2921},
28510         {"cvmx_stx#_spi4_cal#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2633,   6,      2923},
28511         {"cvmx_stx#_spi4_dat"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2697,   3,      2929},
28512         {"cvmx_stx#_spi4_stat"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2699,   4,      2932},
28513         {"cvmx_stx#_stat_bytes_hi"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2701,   2,      2936},
28514         {"cvmx_stx#_stat_bytes_lo"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2703,   2,      2938},
28515         {"cvmx_stx#_stat_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2705,   3,      2940},
28516         {"cvmx_stx#_stat_pkt_xmt"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2707,   2,      2943},
28517         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2709,   6,      2945},
28518         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2710,   3,      2951},
28519         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2711,   5,      2954},
28520         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2712,   4,      2959},
28521         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2713,   6,      2963},
28522         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2714,   4,      2969},
28523         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2715,   2,      2973},
28524         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2716,   4,      2975},
28525         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2717,   2,      2979},
28526         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2718,   3,      2981},
28527         {"cvmx_tra_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2719,   4,      2984},
28528         {"cvmx_tra_ctl"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2720,   12,     2988},
28529         {"cvmx_tra_cycles_since"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2721,   3,      3000},
28530         {"cvmx_tra_cycles_since1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2722,   5,      3003},
28531         {"cvmx_tra_filt_adr_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2723,   2,      3008},
28532         {"cvmx_tra_filt_adr_msk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2724,   2,      3010},
28533         {"cvmx_tra_filt_cmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2725,   18,     3012},
28534         {"cvmx_tra_filt_did"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2726,   12,     3030},
28535         {"cvmx_tra_filt_sid"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2727,   6,      3042},
28536         {"cvmx_tra_int_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2728,   5,      3048},
28537         {"cvmx_tra_read_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2729,   1,      3053},
28538         {"cvmx_tra_trig0_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2730,   2,      3054},
28539         {"cvmx_tra_trig0_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2731,   2,      3056},
28540         {"cvmx_tra_trig0_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2732,   18,     3058},
28541         {"cvmx_tra_trig0_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2733,   12,     3076},
28542         {"cvmx_tra_trig0_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2734,   6,      3088},
28543         {"cvmx_tra_trig1_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2735,   2,      3094},
28544         {"cvmx_tra_trig1_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2736,   2,      3096},
28545         {"cvmx_tra_trig1_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2737,   18,     3098},
28546         {"cvmx_tra_trig1_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2738,   12,     3116},
28547         {"cvmx_tra_trig1_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2739,   6,      3128},
28548         {"cvmx_zip_cmd_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2740,   3,      3134},
28549         {"cvmx_zip_cmd_buf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2741,   5,      3137},
28550         {"cvmx_zip_cmd_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2742,   3,      3142},
28551         {"cvmx_zip_constants"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2743,   6,      3145},
28552         {"cvmx_zip_debug0"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     2744,   2,      3151},
28553         {"cvmx_zip_error"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     2745,   2,      3153},
28554         {"cvmx_zip_int_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2746,   2,      3155},
28555         {NULL,0,0,0,0,0}
28556 };
28557 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn58xx[] = {
28558         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
28559         {"ASX0_INT_EN"                 ,           0x11800B0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
28560         {"ASX1_INT_EN"                 ,           0x11800B8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
28561         {"ASX0_INT_REG"                ,           0x11800B0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
28562         {"ASX1_INT_REG"                ,           0x11800B8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
28563         {"ASX0_PRT_LOOP"               ,           0x11800B0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
28564         {"ASX1_PRT_LOOP"               ,           0x11800B8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
28565         {"ASX0_RLD_BYPASS"             ,           0x11800B0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
28566         {"ASX1_RLD_BYPASS"             ,           0x11800B8000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
28567         {"ASX0_RLD_BYPASS_SETTING"     ,           0x11800B0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
28568         {"ASX1_RLD_BYPASS_SETTING"     ,           0x11800B8000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
28569         {"ASX0_RLD_COMP"               ,           0x11800B0000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
28570         {"ASX1_RLD_COMP"               ,           0x11800B8000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
28571         {"ASX0_RLD_DATA_DRV"           ,           0x11800B0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
28572         {"ASX1_RLD_DATA_DRV"           ,           0x11800B8000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
28573         {"ASX0_RLD_NCTL_STRONG"        ,           0x11800B0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
28574         {"ASX1_RLD_NCTL_STRONG"        ,           0x11800B8000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
28575         {"ASX0_RLD_NCTL_WEAK"          ,           0x11800B0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
28576         {"ASX1_RLD_NCTL_WEAK"          ,           0x11800B8000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
28577         {"ASX0_RLD_PCTL_STRONG"        ,           0x11800B0000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
28578         {"ASX1_RLD_PCTL_STRONG"        ,           0x11800B8000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
28579         {"ASX0_RLD_PCTL_WEAK"          ,           0x11800B0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
28580         {"ASX1_RLD_PCTL_WEAK"          ,           0x11800B8000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
28581         {"ASX0_RLD_SETTING"            ,           0x11800B0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
28582         {"ASX1_RLD_SETTING"            ,           0x11800B8000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
28583         {"ASX0_RX_CLK_SET000"          ,           0x11800B0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
28584         {"ASX0_RX_CLK_SET001"          ,           0x11800B0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
28585         {"ASX0_RX_CLK_SET002"          ,           0x11800B0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
28586         {"ASX0_RX_CLK_SET003"          ,           0x11800B0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
28587         {"ASX1_RX_CLK_SET000"          ,           0x11800B8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
28588         {"ASX1_RX_CLK_SET001"          ,           0x11800B8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
28589         {"ASX1_RX_CLK_SET002"          ,           0x11800B8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
28590         {"ASX1_RX_CLK_SET003"          ,           0x11800B8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
28591         {"ASX0_RX_PRT_EN"              ,           0x11800B0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
28592         {"ASX1_RX_PRT_EN"              ,           0x11800B8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
28593         {"ASX0_TX_CLK_SET000"          ,           0x11800B0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
28594         {"ASX0_TX_CLK_SET001"          ,           0x11800B0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
28595         {"ASX0_TX_CLK_SET002"          ,           0x11800B0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
28596         {"ASX0_TX_CLK_SET003"          ,           0x11800B0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
28597         {"ASX1_TX_CLK_SET000"          ,           0x11800B8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
28598         {"ASX1_TX_CLK_SET001"          ,           0x11800B8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
28599         {"ASX1_TX_CLK_SET002"          ,           0x11800B8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
28600         {"ASX1_TX_CLK_SET003"          ,           0x11800B8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
28601         {"ASX0_TX_COMP_BYP"            ,           0x11800B0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
28602         {"ASX1_TX_COMP_BYP"            ,           0x11800B8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
28603         {"ASX0_TX_HI_WATER000"         ,           0x11800B0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
28604         {"ASX0_TX_HI_WATER001"         ,           0x11800B0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
28605         {"ASX0_TX_HI_WATER002"         ,           0x11800B0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
28606         {"ASX0_TX_HI_WATER003"         ,           0x11800B0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
28607         {"ASX1_TX_HI_WATER000"         ,           0x11800B8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
28608         {"ASX1_TX_HI_WATER001"         ,           0x11800B8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
28609         {"ASX1_TX_HI_WATER002"         ,           0x11800B8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
28610         {"ASX1_TX_HI_WATER003"         ,           0x11800B8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
28611         {"ASX0_TX_PRT_EN"              ,           0x11800B0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
28612         {"ASX1_TX_PRT_EN"              ,           0x11800B8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
28613         {"ASX0_DBG_DATA_DRV"           ,           0x11800B0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
28614         {"ASX0_DBG_DATA_ENABLE"        ,           0x11800B0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
28615         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
28616         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     21},
28617         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     22},
28618         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     23},
28619         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28620         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28621         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28622         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28623         {"CIU_INT4_EN0"                ,           0x1070000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28624         {"CIU_INT5_EN0"                ,           0x1070000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28625         {"CIU_INT6_EN0"                ,           0x1070000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28626         {"CIU_INT7_EN0"                ,           0x1070000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28627         {"CIU_INT8_EN0"                ,           0x1070000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28628         {"CIU_INT9_EN0"                ,           0x1070000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28629         {"CIU_INT10_EN0"               ,           0x10700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28630         {"CIU_INT11_EN0"               ,           0x10700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28631         {"CIU_INT12_EN0"               ,           0x10700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28632         {"CIU_INT13_EN0"               ,           0x10700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28633         {"CIU_INT14_EN0"               ,           0x10700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28634         {"CIU_INT15_EN0"               ,           0x10700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28635         {"CIU_INT16_EN0"               ,           0x1070000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28636         {"CIU_INT17_EN0"               ,           0x1070000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28637         {"CIU_INT18_EN0"               ,           0x1070000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28638         {"CIU_INT19_EN0"               ,           0x1070000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28639         {"CIU_INT20_EN0"               ,           0x1070000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28640         {"CIU_INT21_EN0"               ,           0x1070000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28641         {"CIU_INT22_EN0"               ,           0x1070000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28642         {"CIU_INT23_EN0"               ,           0x1070000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28643         {"CIU_INT24_EN0"               ,           0x1070000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28644         {"CIU_INT25_EN0"               ,           0x1070000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28645         {"CIU_INT26_EN0"               ,           0x10700000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28646         {"CIU_INT27_EN0"               ,           0x10700000003B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28647         {"CIU_INT28_EN0"               ,           0x10700000003C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28648         {"CIU_INT29_EN0"               ,           0x10700000003D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28649         {"CIU_INT30_EN0"               ,           0x10700000003E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28650         {"CIU_INT31_EN0"               ,           0x10700000003F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28651         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
28652         {"CIU_INT0_EN0_W1C"            ,           0x1070000002200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28653         {"CIU_INT1_EN0_W1C"            ,           0x1070000002210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28654         {"CIU_INT2_EN0_W1C"            ,           0x1070000002220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28655         {"CIU_INT3_EN0_W1C"            ,           0x1070000002230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28656         {"CIU_INT4_EN0_W1C"            ,           0x1070000002240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28657         {"CIU_INT5_EN0_W1C"            ,           0x1070000002250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28658         {"CIU_INT6_EN0_W1C"            ,           0x1070000002260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28659         {"CIU_INT7_EN0_W1C"            ,           0x1070000002270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28660         {"CIU_INT8_EN0_W1C"            ,           0x1070000002280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28661         {"CIU_INT9_EN0_W1C"            ,           0x1070000002290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28662         {"CIU_INT10_EN0_W1C"           ,           0x10700000022A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28663         {"CIU_INT11_EN0_W1C"           ,           0x10700000022B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28664         {"CIU_INT12_EN0_W1C"           ,           0x10700000022C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28665         {"CIU_INT13_EN0_W1C"           ,           0x10700000022D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28666         {"CIU_INT14_EN0_W1C"           ,           0x10700000022E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28667         {"CIU_INT15_EN0_W1C"           ,           0x10700000022F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28668         {"CIU_INT16_EN0_W1C"           ,           0x1070000002300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28669         {"CIU_INT17_EN0_W1C"           ,           0x1070000002310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28670         {"CIU_INT18_EN0_W1C"           ,           0x1070000002320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28671         {"CIU_INT19_EN0_W1C"           ,           0x1070000002330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28672         {"CIU_INT20_EN0_W1C"           ,           0x1070000002340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28673         {"CIU_INT21_EN0_W1C"           ,           0x1070000002350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28674         {"CIU_INT22_EN0_W1C"           ,           0x1070000002360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28675         {"CIU_INT23_EN0_W1C"           ,           0x1070000002370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28676         {"CIU_INT24_EN0_W1C"           ,           0x1070000002380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28677         {"CIU_INT25_EN0_W1C"           ,           0x1070000002390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28678         {"CIU_INT26_EN0_W1C"           ,           0x10700000023A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28679         {"CIU_INT27_EN0_W1C"           ,           0x10700000023B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28680         {"CIU_INT28_EN0_W1C"           ,           0x10700000023C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28681         {"CIU_INT29_EN0_W1C"           ,           0x10700000023D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28682         {"CIU_INT30_EN0_W1C"           ,           0x10700000023E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28683         {"CIU_INT31_EN0_W1C"           ,           0x10700000023F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28684         {"CIU_INT32_EN0_W1C"           ,           0x1070000002400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
28685         {"CIU_INT0_EN0_W1S"            ,           0x1070000006200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28686         {"CIU_INT1_EN0_W1S"            ,           0x1070000006210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28687         {"CIU_INT2_EN0_W1S"            ,           0x1070000006220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28688         {"CIU_INT3_EN0_W1S"            ,           0x1070000006230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28689         {"CIU_INT4_EN0_W1S"            ,           0x1070000006240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28690         {"CIU_INT5_EN0_W1S"            ,           0x1070000006250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28691         {"CIU_INT6_EN0_W1S"            ,           0x1070000006260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28692         {"CIU_INT7_EN0_W1S"            ,           0x1070000006270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28693         {"CIU_INT8_EN0_W1S"            ,           0x1070000006280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28694         {"CIU_INT9_EN0_W1S"            ,           0x1070000006290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28695         {"CIU_INT10_EN0_W1S"           ,           0x10700000062A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28696         {"CIU_INT11_EN0_W1S"           ,           0x10700000062B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28697         {"CIU_INT12_EN0_W1S"           ,           0x10700000062C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28698         {"CIU_INT13_EN0_W1S"           ,           0x10700000062D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28699         {"CIU_INT14_EN0_W1S"           ,           0x10700000062E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28700         {"CIU_INT15_EN0_W1S"           ,           0x10700000062F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28701         {"CIU_INT16_EN0_W1S"           ,           0x1070000006300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28702         {"CIU_INT17_EN0_W1S"           ,           0x1070000006310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28703         {"CIU_INT18_EN0_W1S"           ,           0x1070000006320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28704         {"CIU_INT19_EN0_W1S"           ,           0x1070000006330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28705         {"CIU_INT20_EN0_W1S"           ,           0x1070000006340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28706         {"CIU_INT21_EN0_W1S"           ,           0x1070000006350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28707         {"CIU_INT22_EN0_W1S"           ,           0x1070000006360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28708         {"CIU_INT23_EN0_W1S"           ,           0x1070000006370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28709         {"CIU_INT24_EN0_W1S"           ,           0x1070000006380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28710         {"CIU_INT25_EN0_W1S"           ,           0x1070000006390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28711         {"CIU_INT26_EN0_W1S"           ,           0x10700000063A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28712         {"CIU_INT27_EN0_W1S"           ,           0x10700000063B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28713         {"CIU_INT28_EN0_W1S"           ,           0x10700000063C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28714         {"CIU_INT29_EN0_W1S"           ,           0x10700000063D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28715         {"CIU_INT30_EN0_W1S"           ,           0x10700000063E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28716         {"CIU_INT31_EN0_W1S"           ,           0x10700000063F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28717         {"CIU_INT32_EN0_W1S"           ,           0x1070000006400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
28718         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28719         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28720         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28721         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28722         {"CIU_INT4_EN1"                ,           0x1070000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28723         {"CIU_INT5_EN1"                ,           0x1070000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28724         {"CIU_INT6_EN1"                ,           0x1070000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28725         {"CIU_INT7_EN1"                ,           0x1070000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28726         {"CIU_INT8_EN1"                ,           0x1070000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28727         {"CIU_INT9_EN1"                ,           0x1070000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28728         {"CIU_INT10_EN1"               ,           0x10700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28729         {"CIU_INT11_EN1"               ,           0x10700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28730         {"CIU_INT12_EN1"               ,           0x10700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28731         {"CIU_INT13_EN1"               ,           0x10700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28732         {"CIU_INT14_EN1"               ,           0x10700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28733         {"CIU_INT15_EN1"               ,           0x10700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28734         {"CIU_INT16_EN1"               ,           0x1070000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28735         {"CIU_INT17_EN1"               ,           0x1070000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28736         {"CIU_INT18_EN1"               ,           0x1070000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28737         {"CIU_INT19_EN1"               ,           0x1070000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28738         {"CIU_INT20_EN1"               ,           0x1070000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28739         {"CIU_INT21_EN1"               ,           0x1070000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28740         {"CIU_INT22_EN1"               ,           0x1070000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28741         {"CIU_INT23_EN1"               ,           0x1070000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28742         {"CIU_INT24_EN1"               ,           0x1070000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28743         {"CIU_INT25_EN1"               ,           0x1070000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28744         {"CIU_INT26_EN1"               ,           0x10700000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28745         {"CIU_INT27_EN1"               ,           0x10700000003B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28746         {"CIU_INT28_EN1"               ,           0x10700000003C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28747         {"CIU_INT29_EN1"               ,           0x10700000003D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28748         {"CIU_INT30_EN1"               ,           0x10700000003E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28749         {"CIU_INT31_EN1"               ,           0x10700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28750         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
28751         {"CIU_INT0_EN1_W1C"            ,           0x1070000002208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28752         {"CIU_INT1_EN1_W1C"            ,           0x1070000002218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28753         {"CIU_INT2_EN1_W1C"            ,           0x1070000002228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28754         {"CIU_INT3_EN1_W1C"            ,           0x1070000002238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28755         {"CIU_INT4_EN1_W1C"            ,           0x1070000002248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28756         {"CIU_INT5_EN1_W1C"            ,           0x1070000002258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28757         {"CIU_INT6_EN1_W1C"            ,           0x1070000002268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28758         {"CIU_INT7_EN1_W1C"            ,           0x1070000002278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28759         {"CIU_INT8_EN1_W1C"            ,           0x1070000002288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28760         {"CIU_INT9_EN1_W1C"            ,           0x1070000002298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28761         {"CIU_INT10_EN1_W1C"           ,           0x10700000022A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28762         {"CIU_INT11_EN1_W1C"           ,           0x10700000022B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28763         {"CIU_INT12_EN1_W1C"           ,           0x10700000022C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28764         {"CIU_INT13_EN1_W1C"           ,           0x10700000022D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28765         {"CIU_INT14_EN1_W1C"           ,           0x10700000022E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28766         {"CIU_INT15_EN1_W1C"           ,           0x10700000022F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28767         {"CIU_INT16_EN1_W1C"           ,           0x1070000002308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28768         {"CIU_INT17_EN1_W1C"           ,           0x1070000002318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28769         {"CIU_INT18_EN1_W1C"           ,           0x1070000002328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28770         {"CIU_INT19_EN1_W1C"           ,           0x1070000002338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28771         {"CIU_INT20_EN1_W1C"           ,           0x1070000002348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28772         {"CIU_INT21_EN1_W1C"           ,           0x1070000002358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28773         {"CIU_INT22_EN1_W1C"           ,           0x1070000002368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28774         {"CIU_INT23_EN1_W1C"           ,           0x1070000002378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28775         {"CIU_INT24_EN1_W1C"           ,           0x1070000002388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28776         {"CIU_INT25_EN1_W1C"           ,           0x1070000002398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28777         {"CIU_INT26_EN1_W1C"           ,           0x10700000023A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28778         {"CIU_INT27_EN1_W1C"           ,           0x10700000023B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28779         {"CIU_INT28_EN1_W1C"           ,           0x10700000023C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28780         {"CIU_INT29_EN1_W1C"           ,           0x10700000023D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28781         {"CIU_INT30_EN1_W1C"           ,           0x10700000023E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28782         {"CIU_INT31_EN1_W1C"           ,           0x10700000023F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28783         {"CIU_INT32_EN1_W1C"           ,           0x1070000002408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
28784         {"CIU_INT0_EN1_W1S"            ,           0x1070000006208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28785         {"CIU_INT1_EN1_W1S"            ,           0x1070000006218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28786         {"CIU_INT2_EN1_W1S"            ,           0x1070000006228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28787         {"CIU_INT3_EN1_W1S"            ,           0x1070000006238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28788         {"CIU_INT4_EN1_W1S"            ,           0x1070000006248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28789         {"CIU_INT5_EN1_W1S"            ,           0x1070000006258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28790         {"CIU_INT6_EN1_W1S"            ,           0x1070000006268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28791         {"CIU_INT7_EN1_W1S"            ,           0x1070000006278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28792         {"CIU_INT8_EN1_W1S"            ,           0x1070000006288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28793         {"CIU_INT9_EN1_W1S"            ,           0x1070000006298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28794         {"CIU_INT10_EN1_W1S"           ,           0x10700000062A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28795         {"CIU_INT11_EN1_W1S"           ,           0x10700000062B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28796         {"CIU_INT12_EN1_W1S"           ,           0x10700000062C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28797         {"CIU_INT13_EN1_W1S"           ,           0x10700000062D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28798         {"CIU_INT14_EN1_W1S"           ,           0x10700000062E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28799         {"CIU_INT15_EN1_W1S"           ,           0x10700000062F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28800         {"CIU_INT16_EN1_W1S"           ,           0x1070000006308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28801         {"CIU_INT17_EN1_W1S"           ,           0x1070000006318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28802         {"CIU_INT18_EN1_W1S"           ,           0x1070000006328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28803         {"CIU_INT19_EN1_W1S"           ,           0x1070000006338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28804         {"CIU_INT20_EN1_W1S"           ,           0x1070000006348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28805         {"CIU_INT21_EN1_W1S"           ,           0x1070000006358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28806         {"CIU_INT22_EN1_W1S"           ,           0x1070000006368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28807         {"CIU_INT23_EN1_W1S"           ,           0x1070000006378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28808         {"CIU_INT24_EN1_W1S"           ,           0x1070000006388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28809         {"CIU_INT25_EN1_W1S"           ,           0x1070000006398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28810         {"CIU_INT26_EN1_W1S"           ,           0x10700000063A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28811         {"CIU_INT27_EN1_W1S"           ,           0x10700000063B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28812         {"CIU_INT28_EN1_W1S"           ,           0x10700000063C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28813         {"CIU_INT29_EN1_W1S"           ,           0x10700000063D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28814         {"CIU_INT30_EN1_W1S"           ,           0x10700000063E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28815         {"CIU_INT31_EN1_W1S"           ,           0x10700000063F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28816         {"CIU_INT32_EN1_W1S"           ,           0x1070000006408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
28817         {"CIU_INT0_EN4_0"              ,           0x1070000000C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28818         {"CIU_INT1_EN4_0"              ,           0x1070000000C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28819         {"CIU_INT2_EN4_0"              ,           0x1070000000CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28820         {"CIU_INT3_EN4_0"              ,           0x1070000000CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28821         {"CIU_INT4_EN4_0"              ,           0x1070000000CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28822         {"CIU_INT5_EN4_0"              ,           0x1070000000CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28823         {"CIU_INT6_EN4_0"              ,           0x1070000000CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28824         {"CIU_INT7_EN4_0"              ,           0x1070000000CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28825         {"CIU_INT8_EN4_0"              ,           0x1070000000D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28826         {"CIU_INT9_EN4_0"              ,           0x1070000000D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28827         {"CIU_INT10_EN4_0"             ,           0x1070000000D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28828         {"CIU_INT11_EN4_0"             ,           0x1070000000D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28829         {"CIU_INT12_EN4_0"             ,           0x1070000000D40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28830         {"CIU_INT13_EN4_0"             ,           0x1070000000D50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28831         {"CIU_INT14_EN4_0"             ,           0x1070000000D60ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28832         {"CIU_INT15_EN4_0"             ,           0x1070000000D70ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
28833         {"CIU_INT0_EN4_0_W1C"          ,           0x1070000002C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28834         {"CIU_INT1_EN4_0_W1C"          ,           0x1070000002C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28835         {"CIU_INT2_EN4_0_W1C"          ,           0x1070000002CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28836         {"CIU_INT3_EN4_0_W1C"          ,           0x1070000002CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28837         {"CIU_INT4_EN4_0_W1C"          ,           0x1070000002CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28838         {"CIU_INT5_EN4_0_W1C"          ,           0x1070000002CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28839         {"CIU_INT6_EN4_0_W1C"          ,           0x1070000002CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28840         {"CIU_INT7_EN4_0_W1C"          ,           0x1070000002CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28841         {"CIU_INT8_EN4_0_W1C"          ,           0x1070000002D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28842         {"CIU_INT9_EN4_0_W1C"          ,           0x1070000002D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28843         {"CIU_INT10_EN4_0_W1C"         ,           0x1070000002D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28844         {"CIU_INT11_EN4_0_W1C"         ,           0x1070000002D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28845         {"CIU_INT12_EN4_0_W1C"         ,           0x1070000002D40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28846         {"CIU_INT13_EN4_0_W1C"         ,           0x1070000002D50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28847         {"CIU_INT14_EN4_0_W1C"         ,           0x1070000002D60ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28848         {"CIU_INT15_EN4_0_W1C"         ,           0x1070000002D70ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
28849         {"CIU_INT0_EN4_0_W1S"          ,           0x1070000006C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28850         {"CIU_INT1_EN4_0_W1S"          ,           0x1070000006C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28851         {"CIU_INT2_EN4_0_W1S"          ,           0x1070000006CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28852         {"CIU_INT3_EN4_0_W1S"          ,           0x1070000006CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28853         {"CIU_INT4_EN4_0_W1S"          ,           0x1070000006CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28854         {"CIU_INT5_EN4_0_W1S"          ,           0x1070000006CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28855         {"CIU_INT6_EN4_0_W1S"          ,           0x1070000006CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28856         {"CIU_INT7_EN4_0_W1S"          ,           0x1070000006CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28857         {"CIU_INT8_EN4_0_W1S"          ,           0x1070000006D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28858         {"CIU_INT9_EN4_0_W1S"          ,           0x1070000006D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28859         {"CIU_INT10_EN4_0_W1S"         ,           0x1070000006D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28860         {"CIU_INT11_EN4_0_W1S"         ,           0x1070000006D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28861         {"CIU_INT12_EN4_0_W1S"         ,           0x1070000006D40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28862         {"CIU_INT13_EN4_0_W1S"         ,           0x1070000006D50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28863         {"CIU_INT14_EN4_0_W1S"         ,           0x1070000006D60ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28864         {"CIU_INT15_EN4_0_W1S"         ,           0x1070000006D70ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
28865         {"CIU_INT0_EN4_1"              ,           0x1070000000C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28866         {"CIU_INT1_EN4_1"              ,           0x1070000000C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28867         {"CIU_INT2_EN4_1"              ,           0x1070000000CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28868         {"CIU_INT3_EN4_1"              ,           0x1070000000CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28869         {"CIU_INT4_EN4_1"              ,           0x1070000000CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28870         {"CIU_INT5_EN4_1"              ,           0x1070000000CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28871         {"CIU_INT6_EN4_1"              ,           0x1070000000CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28872         {"CIU_INT7_EN4_1"              ,           0x1070000000CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28873         {"CIU_INT8_EN4_1"              ,           0x1070000000D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28874         {"CIU_INT9_EN4_1"              ,           0x1070000000D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28875         {"CIU_INT10_EN4_1"             ,           0x1070000000D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28876         {"CIU_INT11_EN4_1"             ,           0x1070000000D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28877         {"CIU_INT12_EN4_1"             ,           0x1070000000D48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28878         {"CIU_INT13_EN4_1"             ,           0x1070000000D58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28879         {"CIU_INT14_EN4_1"             ,           0x1070000000D68ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28880         {"CIU_INT15_EN4_1"             ,           0x1070000000D78ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
28881         {"CIU_INT0_EN4_1_W1C"          ,           0x1070000002C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28882         {"CIU_INT1_EN4_1_W1C"          ,           0x1070000002C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28883         {"CIU_INT2_EN4_1_W1C"          ,           0x1070000002CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28884         {"CIU_INT3_EN4_1_W1C"          ,           0x1070000002CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28885         {"CIU_INT4_EN4_1_W1C"          ,           0x1070000002CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28886         {"CIU_INT5_EN4_1_W1C"          ,           0x1070000002CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28887         {"CIU_INT6_EN4_1_W1C"          ,           0x1070000002CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28888         {"CIU_INT7_EN4_1_W1C"          ,           0x1070000002CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28889         {"CIU_INT8_EN4_1_W1C"          ,           0x1070000002D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28890         {"CIU_INT9_EN4_1_W1C"          ,           0x1070000002D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28891         {"CIU_INT10_EN4_1_W1C"         ,           0x1070000002D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28892         {"CIU_INT11_EN4_1_W1C"         ,           0x1070000002D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28893         {"CIU_INT12_EN4_1_W1C"         ,           0x1070000002D48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28894         {"CIU_INT13_EN4_1_W1C"         ,           0x1070000002D58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28895         {"CIU_INT14_EN4_1_W1C"         ,           0x1070000002D68ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28896         {"CIU_INT15_EN4_1_W1C"         ,           0x1070000002D78ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
28897         {"CIU_INT0_EN4_1_W1S"          ,           0x1070000006C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28898         {"CIU_INT1_EN4_1_W1S"          ,           0x1070000006C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28899         {"CIU_INT2_EN4_1_W1S"          ,           0x1070000006CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28900         {"CIU_INT3_EN4_1_W1S"          ,           0x1070000006CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28901         {"CIU_INT4_EN4_1_W1S"          ,           0x1070000006CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28902         {"CIU_INT5_EN4_1_W1S"          ,           0x1070000006CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28903         {"CIU_INT6_EN4_1_W1S"          ,           0x1070000006CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28904         {"CIU_INT7_EN4_1_W1S"          ,           0x1070000006CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28905         {"CIU_INT8_EN4_1_W1S"          ,           0x1070000006D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28906         {"CIU_INT9_EN4_1_W1S"          ,           0x1070000006D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28907         {"CIU_INT10_EN4_1_W1S"         ,           0x1070000006D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28908         {"CIU_INT11_EN4_1_W1S"         ,           0x1070000006D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28909         {"CIU_INT12_EN4_1_W1S"         ,           0x1070000006D48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28910         {"CIU_INT13_EN4_1_W1S"         ,           0x1070000006D58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28911         {"CIU_INT14_EN4_1_W1S"         ,           0x1070000006D68ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28912         {"CIU_INT15_EN4_1_W1S"         ,           0x1070000006D78ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
28913         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28914         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28915         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28916         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28917         {"CIU_INT4_SUM0"               ,           0x1070000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28918         {"CIU_INT5_SUM0"               ,           0x1070000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28919         {"CIU_INT6_SUM0"               ,           0x1070000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28920         {"CIU_INT7_SUM0"               ,           0x1070000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28921         {"CIU_INT8_SUM0"               ,           0x1070000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28922         {"CIU_INT9_SUM0"               ,           0x1070000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28923         {"CIU_INT10_SUM0"              ,           0x1070000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28924         {"CIU_INT11_SUM0"              ,           0x1070000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28925         {"CIU_INT12_SUM0"              ,           0x1070000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28926         {"CIU_INT13_SUM0"              ,           0x1070000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28927         {"CIU_INT14_SUM0"              ,           0x1070000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28928         {"CIU_INT15_SUM0"              ,           0x1070000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28929         {"CIU_INT16_SUM0"              ,           0x1070000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28930         {"CIU_INT17_SUM0"              ,           0x1070000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28931         {"CIU_INT18_SUM0"              ,           0x1070000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28932         {"CIU_INT19_SUM0"              ,           0x1070000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28933         {"CIU_INT20_SUM0"              ,           0x10700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28934         {"CIU_INT21_SUM0"              ,           0x10700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28935         {"CIU_INT22_SUM0"              ,           0x10700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28936         {"CIU_INT23_SUM0"              ,           0x10700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28937         {"CIU_INT24_SUM0"              ,           0x10700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28938         {"CIU_INT25_SUM0"              ,           0x10700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28939         {"CIU_INT26_SUM0"              ,           0x10700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28940         {"CIU_INT27_SUM0"              ,           0x10700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28941         {"CIU_INT28_SUM0"              ,           0x10700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28942         {"CIU_INT29_SUM0"              ,           0x10700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28943         {"CIU_INT30_SUM0"              ,           0x10700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28944         {"CIU_INT31_SUM0"              ,           0x10700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28945         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     36},
28946         {"CIU_INT0_SUM4"               ,           0x1070000000C00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28947         {"CIU_INT1_SUM4"               ,           0x1070000000C08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28948         {"CIU_INT2_SUM4"               ,           0x1070000000C10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28949         {"CIU_INT3_SUM4"               ,           0x1070000000C18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28950         {"CIU_INT4_SUM4"               ,           0x1070000000C20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28951         {"CIU_INT5_SUM4"               ,           0x1070000000C28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28952         {"CIU_INT6_SUM4"               ,           0x1070000000C30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28953         {"CIU_INT7_SUM4"               ,           0x1070000000C38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28954         {"CIU_INT8_SUM4"               ,           0x1070000000C40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28955         {"CIU_INT9_SUM4"               ,           0x1070000000C48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28956         {"CIU_INT10_SUM4"              ,           0x1070000000C50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28957         {"CIU_INT11_SUM4"              ,           0x1070000000C58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28958         {"CIU_INT12_SUM4"              ,           0x1070000000C60ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28959         {"CIU_INT13_SUM4"              ,           0x1070000000C68ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28960         {"CIU_INT14_SUM4"              ,           0x1070000000C70ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28961         {"CIU_INT15_SUM4"              ,           0x1070000000C78ull,  CVMX_CSR_DB_TYPE_NCB,   64,     37},
28962         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     38},
28963         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28964         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28965         {"CIU_MBOX_CLR2"               ,           0x1070000000690ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28966         {"CIU_MBOX_CLR3"               ,           0x1070000000698ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28967         {"CIU_MBOX_CLR4"               ,           0x10700000006A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28968         {"CIU_MBOX_CLR5"               ,           0x10700000006A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28969         {"CIU_MBOX_CLR6"               ,           0x10700000006B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28970         {"CIU_MBOX_CLR7"               ,           0x10700000006B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28971         {"CIU_MBOX_CLR8"               ,           0x10700000006C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28972         {"CIU_MBOX_CLR9"               ,           0x10700000006C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28973         {"CIU_MBOX_CLR10"              ,           0x10700000006D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28974         {"CIU_MBOX_CLR11"              ,           0x10700000006D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28975         {"CIU_MBOX_CLR12"              ,           0x10700000006E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28976         {"CIU_MBOX_CLR13"              ,           0x10700000006E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28977         {"CIU_MBOX_CLR14"              ,           0x10700000006F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28978         {"CIU_MBOX_CLR15"              ,           0x10700000006F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     39},
28979         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28980         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28981         {"CIU_MBOX_SET2"               ,           0x1070000000610ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28982         {"CIU_MBOX_SET3"               ,           0x1070000000618ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28983         {"CIU_MBOX_SET4"               ,           0x1070000000620ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28984         {"CIU_MBOX_SET5"               ,           0x1070000000628ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28985         {"CIU_MBOX_SET6"               ,           0x1070000000630ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28986         {"CIU_MBOX_SET7"               ,           0x1070000000638ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28987         {"CIU_MBOX_SET8"               ,           0x1070000000640ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28988         {"CIU_MBOX_SET9"               ,           0x1070000000648ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28989         {"CIU_MBOX_SET10"              ,           0x1070000000650ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28990         {"CIU_MBOX_SET11"              ,           0x1070000000658ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28991         {"CIU_MBOX_SET12"              ,           0x1070000000660ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28992         {"CIU_MBOX_SET13"              ,           0x1070000000668ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28993         {"CIU_MBOX_SET14"              ,           0x1070000000670ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28994         {"CIU_MBOX_SET15"              ,           0x1070000000678ull,  CVMX_CSR_DB_TYPE_NCB,   64,     40},
28995         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     41},
28996         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     42},
28997         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     43},
28998         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
28999         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29000         {"CIU_PP_POKE2"                ,           0x1070000000590ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29001         {"CIU_PP_POKE3"                ,           0x1070000000598ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29002         {"CIU_PP_POKE4"                ,           0x10700000005A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29003         {"CIU_PP_POKE5"                ,           0x10700000005A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29004         {"CIU_PP_POKE6"                ,           0x10700000005B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29005         {"CIU_PP_POKE7"                ,           0x10700000005B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29006         {"CIU_PP_POKE8"                ,           0x10700000005C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29007         {"CIU_PP_POKE9"                ,           0x10700000005C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29008         {"CIU_PP_POKE10"               ,           0x10700000005D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29009         {"CIU_PP_POKE11"               ,           0x10700000005D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29010         {"CIU_PP_POKE12"               ,           0x10700000005E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29011         {"CIU_PP_POKE13"               ,           0x10700000005E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29012         {"CIU_PP_POKE14"               ,           0x10700000005F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29013         {"CIU_PP_POKE15"               ,           0x10700000005F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     44},
29014         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     45},
29015         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     46},
29016         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     47},
29017         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     48},
29018         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     49},
29019         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     49},
29020         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     49},
29021         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     49},
29022         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29023         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29024         {"CIU_WDOG2"                   ,           0x1070000000510ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29025         {"CIU_WDOG3"                   ,           0x1070000000518ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29026         {"CIU_WDOG4"                   ,           0x1070000000520ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29027         {"CIU_WDOG5"                   ,           0x1070000000528ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29028         {"CIU_WDOG6"                   ,           0x1070000000530ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29029         {"CIU_WDOG7"                   ,           0x1070000000538ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29030         {"CIU_WDOG8"                   ,           0x1070000000540ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29031         {"CIU_WDOG9"                   ,           0x1070000000548ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29032         {"CIU_WDOG10"                  ,           0x1070000000550ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29033         {"CIU_WDOG11"                  ,           0x1070000000558ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29034         {"CIU_WDOG12"                  ,           0x1070000000560ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29035         {"CIU_WDOG13"                  ,           0x1070000000568ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29036         {"CIU_WDOG14"                  ,           0x1070000000570ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29037         {"CIU_WDOG15"                  ,           0x1070000000578ull,  CVMX_CSR_DB_TYPE_NCB,   64,     50},
29038         {"DBG_DATA"                    ,           0x11F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     51},
29039         {"DFA_BST0"                    ,           0x11800300007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
29040         {"DFA_BST1"                    ,           0x11800300007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
29041         {"DFA_CFG"                     ,           0x1180030000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
29042         {"DFA_DBELL"                   ,           0x1370000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     55},
29043         {"DFA_DIFCTL"                  ,           0x1370600000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     56},
29044         {"DFA_DIFRDPTR"                ,           0x1370200000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     57},
29045         {"DFA_ERR"                     ,           0x1180030000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
29046         {"DFA_MEMCFG0"                 ,           0x1180030000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
29047         {"DFA_MEMCFG1"                 ,           0x1180030000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
29048         {"DFA_MEMCFG2"                 ,           0x1180030000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
29049         {"DFA_MEMFADR"                 ,           0x1180030000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
29050         {"DFA_MEMFCR"                  ,           0x1180030000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
29051         {"DFA_MEMRLD"                  ,           0x1180030000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
29052         {"DFA_NCBCTL"                  ,           0x1180030000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
29053         {"DFA_RODT_COMP_CTL"           ,           0x1180030000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
29054         {"DFA_SBD_DBG0"                ,           0x1180030000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
29055         {"DFA_SBD_DBG1"                ,           0x1180030000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
29056         {"DFA_SBD_DBG2"                ,           0x1180030000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
29057         {"DFA_SBD_DBG3"                ,           0x1180030000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
29058         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
29059         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
29060         {"FPA_FPF1_MARKS"              ,           0x1180028000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
29061         {"FPA_FPF2_MARKS"              ,           0x1180028000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
29062         {"FPA_FPF3_MARKS"              ,           0x1180028000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
29063         {"FPA_FPF4_MARKS"              ,           0x1180028000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
29064         {"FPA_FPF5_MARKS"              ,           0x1180028000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
29065         {"FPA_FPF6_MARKS"              ,           0x1180028000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
29066         {"FPA_FPF7_MARKS"              ,           0x1180028000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
29067         {"FPA_FPF1_SIZE"               ,           0x1180028000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
29068         {"FPA_FPF2_SIZE"               ,           0x1180028000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
29069         {"FPA_FPF3_SIZE"               ,           0x1180028000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
29070         {"FPA_FPF4_SIZE"               ,           0x1180028000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
29071         {"FPA_FPF5_SIZE"               ,           0x1180028000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
29072         {"FPA_FPF6_SIZE"               ,           0x1180028000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
29073         {"FPA_FPF7_SIZE"               ,           0x1180028000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
29074         {"FPA_FPF0_MARKS"              ,           0x1180028000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
29075         {"FPA_FPF0_SIZE"               ,           0x1180028000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
29076         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
29077         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
29078         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
29079         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
29080         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
29081         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
29082         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
29083         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
29084         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
29085         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
29086         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
29087         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
29088         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
29089         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
29090         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
29091         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
29092         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
29093         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
29094         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
29095         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
29096         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
29097         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
29098         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
29099         {"GMX1_BAD_REG"                ,           0x1180010000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
29100         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
29101         {"GMX1_BIST"                   ,           0x1180010000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
29102         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
29103         {"GMX1_INF_MODE"               ,           0x11800100007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
29104         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
29105         {"GMX1_NXA_ADR"                ,           0x1180010000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
29106         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
29107         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
29108         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
29109         {"GMX0_PRT003_CFG"             ,           0x1180008001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
29110         {"GMX1_PRT000_CFG"             ,           0x1180010000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
29111         {"GMX1_PRT001_CFG"             ,           0x1180010000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
29112         {"GMX1_PRT002_CFG"             ,           0x1180010001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
29113         {"GMX1_PRT003_CFG"             ,           0x1180010001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
29114         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
29115         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
29116         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
29117         {"GMX0_RX003_ADR_CAM0"         ,           0x1180008001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
29118         {"GMX1_RX000_ADR_CAM0"         ,           0x1180010000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
29119         {"GMX1_RX001_ADR_CAM0"         ,           0x1180010000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
29120         {"GMX1_RX002_ADR_CAM0"         ,           0x1180010001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
29121         {"GMX1_RX003_ADR_CAM0"         ,           0x1180010001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
29122         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
29123         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
29124         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
29125         {"GMX0_RX003_ADR_CAM1"         ,           0x1180008001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
29126         {"GMX1_RX000_ADR_CAM1"         ,           0x1180010000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
29127         {"GMX1_RX001_ADR_CAM1"         ,           0x1180010000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
29128         {"GMX1_RX002_ADR_CAM1"         ,           0x1180010001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
29129         {"GMX1_RX003_ADR_CAM1"         ,           0x1180010001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
29130         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
29131         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
29132         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
29133         {"GMX0_RX003_ADR_CAM2"         ,           0x1180008001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
29134         {"GMX1_RX000_ADR_CAM2"         ,           0x1180010000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
29135         {"GMX1_RX001_ADR_CAM2"         ,           0x1180010000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
29136         {"GMX1_RX002_ADR_CAM2"         ,           0x1180010001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
29137         {"GMX1_RX003_ADR_CAM2"         ,           0x1180010001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
29138         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
29139         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
29140         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
29141         {"GMX0_RX003_ADR_CAM3"         ,           0x1180008001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
29142         {"GMX1_RX000_ADR_CAM3"         ,           0x1180010000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
29143         {"GMX1_RX001_ADR_CAM3"         ,           0x1180010000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
29144         {"GMX1_RX002_ADR_CAM3"         ,           0x1180010001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
29145         {"GMX1_RX003_ADR_CAM3"         ,           0x1180010001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
29146         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
29147         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
29148         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
29149         {"GMX0_RX003_ADR_CAM4"         ,           0x11800080019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
29150         {"GMX1_RX000_ADR_CAM4"         ,           0x11800100001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
29151         {"GMX1_RX001_ADR_CAM4"         ,           0x11800100009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
29152         {"GMX1_RX002_ADR_CAM4"         ,           0x11800100011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
29153         {"GMX1_RX003_ADR_CAM4"         ,           0x11800100019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
29154         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
29155         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
29156         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
29157         {"GMX0_RX003_ADR_CAM5"         ,           0x11800080019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
29158         {"GMX1_RX000_ADR_CAM5"         ,           0x11800100001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
29159         {"GMX1_RX001_ADR_CAM5"         ,           0x11800100009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
29160         {"GMX1_RX002_ADR_CAM5"         ,           0x11800100011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
29161         {"GMX1_RX003_ADR_CAM5"         ,           0x11800100019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
29162         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
29163         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
29164         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
29165         {"GMX0_RX003_ADR_CAM_EN"       ,           0x1180008001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
29166         {"GMX1_RX000_ADR_CAM_EN"       ,           0x1180010000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
29167         {"GMX1_RX001_ADR_CAM_EN"       ,           0x1180010000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
29168         {"GMX1_RX002_ADR_CAM_EN"       ,           0x1180010001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
29169         {"GMX1_RX003_ADR_CAM_EN"       ,           0x1180010001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
29170         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
29171         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
29172         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
29173         {"GMX0_RX003_ADR_CTL"          ,           0x1180008001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
29174         {"GMX1_RX000_ADR_CTL"          ,           0x1180010000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
29175         {"GMX1_RX001_ADR_CTL"          ,           0x1180010000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
29176         {"GMX1_RX002_ADR_CTL"          ,           0x1180010001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
29177         {"GMX1_RX003_ADR_CTL"          ,           0x1180010001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
29178         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
29179         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
29180         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
29181         {"GMX0_RX003_DECISION"         ,           0x1180008001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
29182         {"GMX1_RX000_DECISION"         ,           0x1180010000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
29183         {"GMX1_RX001_DECISION"         ,           0x1180010000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
29184         {"GMX1_RX002_DECISION"         ,           0x1180010001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
29185         {"GMX1_RX003_DECISION"         ,           0x1180010001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
29186         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
29187         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
29188         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
29189         {"GMX0_RX003_FRM_CHK"          ,           0x1180008001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
29190         {"GMX1_RX000_FRM_CHK"          ,           0x1180010000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
29191         {"GMX1_RX001_FRM_CHK"          ,           0x1180010000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
29192         {"GMX1_RX002_FRM_CHK"          ,           0x1180010001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
29193         {"GMX1_RX003_FRM_CHK"          ,           0x1180010001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
29194         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
29195         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
29196         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
29197         {"GMX0_RX003_FRM_CTL"          ,           0x1180008001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
29198         {"GMX1_RX000_FRM_CTL"          ,           0x1180010000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
29199         {"GMX1_RX001_FRM_CTL"          ,           0x1180010000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
29200         {"GMX1_RX002_FRM_CTL"          ,           0x1180010001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
29201         {"GMX1_RX003_FRM_CTL"          ,           0x1180010001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
29202         {"GMX0_RX000_FRM_MAX"          ,           0x1180008000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
29203         {"GMX0_RX001_FRM_MAX"          ,           0x1180008000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
29204         {"GMX0_RX002_FRM_MAX"          ,           0x1180008001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
29205         {"GMX0_RX003_FRM_MAX"          ,           0x1180008001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
29206         {"GMX1_RX000_FRM_MAX"          ,           0x1180010000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
29207         {"GMX1_RX001_FRM_MAX"          ,           0x1180010000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
29208         {"GMX1_RX002_FRM_MAX"          ,           0x1180010001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
29209         {"GMX1_RX003_FRM_MAX"          ,           0x1180010001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
29210         {"GMX0_RX000_FRM_MIN"          ,           0x1180008000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
29211         {"GMX0_RX001_FRM_MIN"          ,           0x1180008000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
29212         {"GMX0_RX002_FRM_MIN"          ,           0x1180008001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
29213         {"GMX0_RX003_FRM_MIN"          ,           0x1180008001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
29214         {"GMX1_RX000_FRM_MIN"          ,           0x1180010000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
29215         {"GMX1_RX001_FRM_MIN"          ,           0x1180010000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
29216         {"GMX1_RX002_FRM_MIN"          ,           0x1180010001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
29217         {"GMX1_RX003_FRM_MIN"          ,           0x1180010001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
29218         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
29219         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
29220         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
29221         {"GMX0_RX003_IFG"              ,           0x1180008001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
29222         {"GMX1_RX000_IFG"              ,           0x1180010000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
29223         {"GMX1_RX001_IFG"              ,           0x1180010000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
29224         {"GMX1_RX002_IFG"              ,           0x1180010001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
29225         {"GMX1_RX003_IFG"              ,           0x1180010001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
29226         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
29227         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
29228         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
29229         {"GMX0_RX003_INT_EN"           ,           0x1180008001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
29230         {"GMX1_RX000_INT_EN"           ,           0x1180010000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
29231         {"GMX1_RX001_INT_EN"           ,           0x1180010000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
29232         {"GMX1_RX002_INT_EN"           ,           0x1180010001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
29233         {"GMX1_RX003_INT_EN"           ,           0x1180010001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
29234         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
29235         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
29236         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
29237         {"GMX0_RX003_INT_REG"          ,           0x1180008001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
29238         {"GMX1_RX000_INT_REG"          ,           0x1180010000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
29239         {"GMX1_RX001_INT_REG"          ,           0x1180010000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
29240         {"GMX1_RX002_INT_REG"          ,           0x1180010001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
29241         {"GMX1_RX003_INT_REG"          ,           0x1180010001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
29242         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
29243         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
29244         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
29245         {"GMX0_RX003_JABBER"           ,           0x1180008001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
29246         {"GMX1_RX000_JABBER"           ,           0x1180010000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
29247         {"GMX1_RX001_JABBER"           ,           0x1180010000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
29248         {"GMX1_RX002_JABBER"           ,           0x1180010001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
29249         {"GMX1_RX003_JABBER"           ,           0x1180010001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
29250         {"GMX0_RX000_PAUSE_DROP_TIME"  ,           0x1180008000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
29251         {"GMX0_RX001_PAUSE_DROP_TIME"  ,           0x1180008000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
29252         {"GMX0_RX002_PAUSE_DROP_TIME"  ,           0x1180008001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
29253         {"GMX0_RX003_PAUSE_DROP_TIME"  ,           0x1180008001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
29254         {"GMX1_RX000_PAUSE_DROP_TIME"  ,           0x1180010000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
29255         {"GMX1_RX001_PAUSE_DROP_TIME"  ,           0x1180010000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
29256         {"GMX1_RX002_PAUSE_DROP_TIME"  ,           0x1180010001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
29257         {"GMX1_RX003_PAUSE_DROP_TIME"  ,           0x1180010001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
29258         {"GMX0_RX000_RX_INBND"         ,           0x1180008000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
29259         {"GMX0_RX001_RX_INBND"         ,           0x1180008000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
29260         {"GMX0_RX002_RX_INBND"         ,           0x1180008001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
29261         {"GMX0_RX003_RX_INBND"         ,           0x1180008001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
29262         {"GMX1_RX000_RX_INBND"         ,           0x1180010000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
29263         {"GMX1_RX001_RX_INBND"         ,           0x1180010000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
29264         {"GMX1_RX002_RX_INBND"         ,           0x1180010001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
29265         {"GMX1_RX003_RX_INBND"         ,           0x1180010001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
29266         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
29267         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
29268         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
29269         {"GMX0_RX003_STATS_CTL"        ,           0x1180008001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
29270         {"GMX1_RX000_STATS_CTL"        ,           0x1180010000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
29271         {"GMX1_RX001_STATS_CTL"        ,           0x1180010000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
29272         {"GMX1_RX002_STATS_CTL"        ,           0x1180010001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
29273         {"GMX1_RX003_STATS_CTL"        ,           0x1180010001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
29274         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
29275         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
29276         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
29277         {"GMX0_RX003_STATS_OCTS"       ,           0x1180008001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
29278         {"GMX1_RX000_STATS_OCTS"       ,           0x1180010000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
29279         {"GMX1_RX001_STATS_OCTS"       ,           0x1180010000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
29280         {"GMX1_RX002_STATS_OCTS"       ,           0x1180010001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
29281         {"GMX1_RX003_STATS_OCTS"       ,           0x1180010001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
29282         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
29283         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
29284         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
29285         {"GMX0_RX003_STATS_OCTS_CTL"   ,           0x1180008001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
29286         {"GMX1_RX000_STATS_OCTS_CTL"   ,           0x1180010000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
29287         {"GMX1_RX001_STATS_OCTS_CTL"   ,           0x1180010000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
29288         {"GMX1_RX002_STATS_OCTS_CTL"   ,           0x1180010001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
29289         {"GMX1_RX003_STATS_OCTS_CTL"   ,           0x1180010001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
29290         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
29291         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
29292         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
29293         {"GMX0_RX003_STATS_OCTS_DMAC"  ,           0x11800080018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
29294         {"GMX1_RX000_STATS_OCTS_DMAC"  ,           0x11800100000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
29295         {"GMX1_RX001_STATS_OCTS_DMAC"  ,           0x11800100008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
29296         {"GMX1_RX002_STATS_OCTS_DMAC"  ,           0x11800100010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
29297         {"GMX1_RX003_STATS_OCTS_DMAC"  ,           0x11800100018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
29298         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
29299         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
29300         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
29301         {"GMX0_RX003_STATS_OCTS_DRP"   ,           0x11800080018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
29302         {"GMX1_RX000_STATS_OCTS_DRP"   ,           0x11800100000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
29303         {"GMX1_RX001_STATS_OCTS_DRP"   ,           0x11800100008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
29304         {"GMX1_RX002_STATS_OCTS_DRP"   ,           0x11800100010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
29305         {"GMX1_RX003_STATS_OCTS_DRP"   ,           0x11800100018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
29306         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
29307         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
29308         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
29309         {"GMX0_RX003_STATS_PKTS"       ,           0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
29310         {"GMX1_RX000_STATS_PKTS"       ,           0x1180010000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
29311         {"GMX1_RX001_STATS_PKTS"       ,           0x1180010000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
29312         {"GMX1_RX002_STATS_PKTS"       ,           0x1180010001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
29313         {"GMX1_RX003_STATS_PKTS"       ,           0x1180010001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
29314         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
29315         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
29316         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
29317         {"GMX0_RX003_STATS_PKTS_BAD"   ,           0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
29318         {"GMX1_RX000_STATS_PKTS_BAD"   ,           0x11800100000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
29319         {"GMX1_RX001_STATS_PKTS_BAD"   ,           0x11800100008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
29320         {"GMX1_RX002_STATS_PKTS_BAD"   ,           0x11800100010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
29321         {"GMX1_RX003_STATS_PKTS_BAD"   ,           0x11800100018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
29322         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
29323         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
29324         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
29325         {"GMX0_RX003_STATS_PKTS_CTL"   ,           0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
29326         {"GMX1_RX000_STATS_PKTS_CTL"   ,           0x1180010000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
29327         {"GMX1_RX001_STATS_PKTS_CTL"   ,           0x1180010000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
29328         {"GMX1_RX002_STATS_PKTS_CTL"   ,           0x1180010001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
29329         {"GMX1_RX003_STATS_PKTS_CTL"   ,           0x1180010001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
29330         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
29331         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
29332         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
29333         {"GMX0_RX003_STATS_PKTS_DMAC"  ,           0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
29334         {"GMX1_RX000_STATS_PKTS_DMAC"  ,           0x11800100000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
29335         {"GMX1_RX001_STATS_PKTS_DMAC"  ,           0x11800100008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
29336         {"GMX1_RX002_STATS_PKTS_DMAC"  ,           0x11800100010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
29337         {"GMX1_RX003_STATS_PKTS_DMAC"  ,           0x11800100018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
29338         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
29339         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
29340         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
29341         {"GMX0_RX003_STATS_PKTS_DRP"   ,           0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
29342         {"GMX1_RX000_STATS_PKTS_DRP"   ,           0x11800100000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
29343         {"GMX1_RX001_STATS_PKTS_DRP"   ,           0x11800100008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
29344         {"GMX1_RX002_STATS_PKTS_DRP"   ,           0x11800100010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
29345         {"GMX1_RX003_STATS_PKTS_DRP"   ,           0x11800100018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
29346         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
29347         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
29348         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
29349         {"GMX0_RX003_UDD_SKP"          ,           0x1180008001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
29350         {"GMX1_RX000_UDD_SKP"          ,           0x1180010000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
29351         {"GMX1_RX001_UDD_SKP"          ,           0x1180010000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
29352         {"GMX1_RX002_UDD_SKP"          ,           0x1180010001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
29353         {"GMX1_RX003_UDD_SKP"          ,           0x1180010001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
29354         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
29355         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
29356         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
29357         {"GMX0_RX_BP_DROP003"          ,           0x1180008000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
29358         {"GMX1_RX_BP_DROP000"          ,           0x1180010000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
29359         {"GMX1_RX_BP_DROP001"          ,           0x1180010000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
29360         {"GMX1_RX_BP_DROP002"          ,           0x1180010000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
29361         {"GMX1_RX_BP_DROP003"          ,           0x1180010000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
29362         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
29363         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
29364         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
29365         {"GMX0_RX_BP_OFF003"           ,           0x1180008000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
29366         {"GMX1_RX_BP_OFF000"           ,           0x1180010000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
29367         {"GMX1_RX_BP_OFF001"           ,           0x1180010000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
29368         {"GMX1_RX_BP_OFF002"           ,           0x1180010000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
29369         {"GMX1_RX_BP_OFF003"           ,           0x1180010000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
29370         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
29371         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
29372         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
29373         {"GMX0_RX_BP_ON003"            ,           0x1180008000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
29374         {"GMX1_RX_BP_ON000"            ,           0x1180010000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
29375         {"GMX1_RX_BP_ON001"            ,           0x1180010000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
29376         {"GMX1_RX_BP_ON002"            ,           0x1180010000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
29377         {"GMX1_RX_BP_ON003"            ,           0x1180010000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
29378         {"GMX0_RX_PASS_EN"             ,           0x11800080005F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
29379         {"GMX1_RX_PASS_EN"             ,           0x11800100005F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
29380         {"GMX0_RX_PASS_MAP000"         ,           0x1180008000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29381         {"GMX0_RX_PASS_MAP001"         ,           0x1180008000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29382         {"GMX0_RX_PASS_MAP002"         ,           0x1180008000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29383         {"GMX0_RX_PASS_MAP003"         ,           0x1180008000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29384         {"GMX0_RX_PASS_MAP004"         ,           0x1180008000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29385         {"GMX0_RX_PASS_MAP005"         ,           0x1180008000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29386         {"GMX0_RX_PASS_MAP006"         ,           0x1180008000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29387         {"GMX0_RX_PASS_MAP007"         ,           0x1180008000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29388         {"GMX0_RX_PASS_MAP008"         ,           0x1180008000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29389         {"GMX0_RX_PASS_MAP009"         ,           0x1180008000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29390         {"GMX0_RX_PASS_MAP010"         ,           0x1180008000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29391         {"GMX0_RX_PASS_MAP011"         ,           0x1180008000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29392         {"GMX0_RX_PASS_MAP012"         ,           0x1180008000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29393         {"GMX0_RX_PASS_MAP013"         ,           0x1180008000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29394         {"GMX0_RX_PASS_MAP014"         ,           0x1180008000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29395         {"GMX0_RX_PASS_MAP015"         ,           0x1180008000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29396         {"GMX1_RX_PASS_MAP000"         ,           0x1180010000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29397         {"GMX1_RX_PASS_MAP001"         ,           0x1180010000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29398         {"GMX1_RX_PASS_MAP002"         ,           0x1180010000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29399         {"GMX1_RX_PASS_MAP003"         ,           0x1180010000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29400         {"GMX1_RX_PASS_MAP004"         ,           0x1180010000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29401         {"GMX1_RX_PASS_MAP005"         ,           0x1180010000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29402         {"GMX1_RX_PASS_MAP006"         ,           0x1180010000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29403         {"GMX1_RX_PASS_MAP007"         ,           0x1180010000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29404         {"GMX1_RX_PASS_MAP008"         ,           0x1180010000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29405         {"GMX1_RX_PASS_MAP009"         ,           0x1180010000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29406         {"GMX1_RX_PASS_MAP010"         ,           0x1180010000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29407         {"GMX1_RX_PASS_MAP011"         ,           0x1180010000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29408         {"GMX1_RX_PASS_MAP012"         ,           0x1180010000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29409         {"GMX1_RX_PASS_MAP013"         ,           0x1180010000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29410         {"GMX1_RX_PASS_MAP014"         ,           0x1180010000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29411         {"GMX1_RX_PASS_MAP015"         ,           0x1180010000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
29412         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
29413         {"GMX1_RX_PRT_INFO"            ,           0x11800100004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
29414         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
29415         {"GMX1_RX_PRTS"                ,           0x1180010000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
29416         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
29417         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
29418         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
29419         {"GMX0_SMAC003"                ,           0x1180008001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
29420         {"GMX1_SMAC000"                ,           0x1180010000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
29421         {"GMX1_SMAC001"                ,           0x1180010000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
29422         {"GMX1_SMAC002"                ,           0x1180010001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
29423         {"GMX1_SMAC003"                ,           0x1180010001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
29424         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
29425         {"GMX1_STAT_BP"                ,           0x1180010000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
29426         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
29427         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
29428         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
29429         {"GMX0_TX003_APPEND"           ,           0x1180008001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
29430         {"GMX1_TX000_APPEND"           ,           0x1180010000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
29431         {"GMX1_TX001_APPEND"           ,           0x1180010000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
29432         {"GMX1_TX002_APPEND"           ,           0x1180010001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
29433         {"GMX1_TX003_APPEND"           ,           0x1180010001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
29434         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
29435         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
29436         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
29437         {"GMX0_TX003_BURST"            ,           0x1180008001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
29438         {"GMX1_TX000_BURST"            ,           0x1180010000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
29439         {"GMX1_TX001_BURST"            ,           0x1180010000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
29440         {"GMX1_TX002_BURST"            ,           0x1180010001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
29441         {"GMX1_TX003_BURST"            ,           0x1180010001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
29442         {"GMX0_TX000_CLK"              ,           0x1180008000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
29443         {"GMX0_TX001_CLK"              ,           0x1180008000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
29444         {"GMX0_TX002_CLK"              ,           0x1180008001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
29445         {"GMX0_TX003_CLK"              ,           0x1180008001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
29446         {"GMX1_TX000_CLK"              ,           0x1180010000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
29447         {"GMX1_TX001_CLK"              ,           0x1180010000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
29448         {"GMX1_TX002_CLK"              ,           0x1180010001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
29449         {"GMX1_TX003_CLK"              ,           0x1180010001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
29450         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
29451         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
29452         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
29453         {"GMX0_TX003_CTL"              ,           0x1180008001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
29454         {"GMX1_TX000_CTL"              ,           0x1180010000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
29455         {"GMX1_TX001_CTL"              ,           0x1180010000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
29456         {"GMX1_TX002_CTL"              ,           0x1180010001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
29457         {"GMX1_TX003_CTL"              ,           0x1180010001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
29458         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
29459         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
29460         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
29461         {"GMX0_TX003_MIN_PKT"          ,           0x1180008001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
29462         {"GMX1_TX000_MIN_PKT"          ,           0x1180010000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
29463         {"GMX1_TX001_MIN_PKT"          ,           0x1180010000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
29464         {"GMX1_TX002_MIN_PKT"          ,           0x1180010001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
29465         {"GMX1_TX003_MIN_PKT"          ,           0x1180010001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
29466         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
29467         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
29468         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
29469         {"GMX0_TX003_PAUSE_PKT_INTERVAL",          0x1180008001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
29470         {"GMX1_TX000_PAUSE_PKT_INTERVAL",          0x1180010000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
29471         {"GMX1_TX001_PAUSE_PKT_INTERVAL",          0x1180010000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
29472         {"GMX1_TX002_PAUSE_PKT_INTERVAL",          0x1180010001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
29473         {"GMX1_TX003_PAUSE_PKT_INTERVAL",          0x1180010001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
29474         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
29475         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
29476         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
29477         {"GMX0_TX003_PAUSE_PKT_TIME"   ,           0x1180008001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
29478         {"GMX1_TX000_PAUSE_PKT_TIME"   ,           0x1180010000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
29479         {"GMX1_TX001_PAUSE_PKT_TIME"   ,           0x1180010000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
29480         {"GMX1_TX002_PAUSE_PKT_TIME"   ,           0x1180010001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
29481         {"GMX1_TX003_PAUSE_PKT_TIME"   ,           0x1180010001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
29482         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
29483         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
29484         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
29485         {"GMX0_TX003_PAUSE_TOGO"       ,           0x1180008001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
29486         {"GMX1_TX000_PAUSE_TOGO"       ,           0x1180010000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
29487         {"GMX1_TX001_PAUSE_TOGO"       ,           0x1180010000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
29488         {"GMX1_TX002_PAUSE_TOGO"       ,           0x1180010001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
29489         {"GMX1_TX003_PAUSE_TOGO"       ,           0x1180010001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
29490         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
29491         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
29492         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
29493         {"GMX0_TX003_PAUSE_ZERO"       ,           0x1180008001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
29494         {"GMX1_TX000_PAUSE_ZERO"       ,           0x1180010000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
29495         {"GMX1_TX001_PAUSE_ZERO"       ,           0x1180010000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
29496         {"GMX1_TX002_PAUSE_ZERO"       ,           0x1180010001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
29497         {"GMX1_TX003_PAUSE_ZERO"       ,           0x1180010001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
29498         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
29499         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
29500         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
29501         {"GMX0_TX003_SLOT"             ,           0x1180008001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
29502         {"GMX1_TX000_SLOT"             ,           0x1180010000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
29503         {"GMX1_TX001_SLOT"             ,           0x1180010000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
29504         {"GMX1_TX002_SLOT"             ,           0x1180010001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
29505         {"GMX1_TX003_SLOT"             ,           0x1180010001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
29506         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
29507         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
29508         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
29509         {"GMX0_TX003_SOFT_PAUSE"       ,           0x1180008001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
29510         {"GMX1_TX000_SOFT_PAUSE"       ,           0x1180010000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
29511         {"GMX1_TX001_SOFT_PAUSE"       ,           0x1180010000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
29512         {"GMX1_TX002_SOFT_PAUSE"       ,           0x1180010001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
29513         {"GMX1_TX003_SOFT_PAUSE"       ,           0x1180010001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
29514         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
29515         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
29516         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
29517         {"GMX0_TX003_STAT0"            ,           0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
29518         {"GMX1_TX000_STAT0"            ,           0x1180010000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
29519         {"GMX1_TX001_STAT0"            ,           0x1180010000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
29520         {"GMX1_TX002_STAT0"            ,           0x1180010001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
29521         {"GMX1_TX003_STAT0"            ,           0x1180010001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
29522         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
29523         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
29524         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
29525         {"GMX0_TX003_STAT1"            ,           0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
29526         {"GMX1_TX000_STAT1"            ,           0x1180010000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
29527         {"GMX1_TX001_STAT1"            ,           0x1180010000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
29528         {"GMX1_TX002_STAT1"            ,           0x1180010001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
29529         {"GMX1_TX003_STAT1"            ,           0x1180010001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
29530         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
29531         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
29532         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
29533         {"GMX0_TX003_STAT2"            ,           0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
29534         {"GMX1_TX000_STAT2"            ,           0x1180010000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
29535         {"GMX1_TX001_STAT2"            ,           0x1180010000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
29536         {"GMX1_TX002_STAT2"            ,           0x1180010001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
29537         {"GMX1_TX003_STAT2"            ,           0x1180010001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
29538         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
29539         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
29540         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
29541         {"GMX0_TX003_STAT3"            ,           0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
29542         {"GMX1_TX000_STAT3"            ,           0x1180010000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
29543         {"GMX1_TX001_STAT3"            ,           0x1180010000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
29544         {"GMX1_TX002_STAT3"            ,           0x1180010001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
29545         {"GMX1_TX003_STAT3"            ,           0x1180010001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
29546         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
29547         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
29548         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
29549         {"GMX0_TX003_STAT4"            ,           0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
29550         {"GMX1_TX000_STAT4"            ,           0x11800100002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
29551         {"GMX1_TX001_STAT4"            ,           0x1180010000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
29552         {"GMX1_TX002_STAT4"            ,           0x11800100012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
29553         {"GMX1_TX003_STAT4"            ,           0x1180010001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
29554         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
29555         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
29556         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
29557         {"GMX0_TX003_STAT5"            ,           0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
29558         {"GMX1_TX000_STAT5"            ,           0x11800100002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
29559         {"GMX1_TX001_STAT5"            ,           0x1180010000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
29560         {"GMX1_TX002_STAT5"            ,           0x11800100012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
29561         {"GMX1_TX003_STAT5"            ,           0x1180010001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
29562         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
29563         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
29564         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
29565         {"GMX0_TX003_STAT6"            ,           0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
29566         {"GMX1_TX000_STAT6"            ,           0x11800100002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
29567         {"GMX1_TX001_STAT6"            ,           0x1180010000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
29568         {"GMX1_TX002_STAT6"            ,           0x11800100012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
29569         {"GMX1_TX003_STAT6"            ,           0x1180010001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
29570         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
29571         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
29572         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
29573         {"GMX0_TX003_STAT7"            ,           0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
29574         {"GMX1_TX000_STAT7"            ,           0x11800100002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
29575         {"GMX1_TX001_STAT7"            ,           0x1180010000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
29576         {"GMX1_TX002_STAT7"            ,           0x11800100012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
29577         {"GMX1_TX003_STAT7"            ,           0x1180010001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
29578         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
29579         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
29580         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
29581         {"GMX0_TX003_STAT8"            ,           0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
29582         {"GMX1_TX000_STAT8"            ,           0x11800100002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
29583         {"GMX1_TX001_STAT8"            ,           0x1180010000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
29584         {"GMX1_TX002_STAT8"            ,           0x11800100012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
29585         {"GMX1_TX003_STAT8"            ,           0x1180010001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
29586         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
29587         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
29588         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
29589         {"GMX0_TX003_STAT9"            ,           0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
29590         {"GMX1_TX000_STAT9"            ,           0x11800100002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
29591         {"GMX1_TX001_STAT9"            ,           0x1180010000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
29592         {"GMX1_TX002_STAT9"            ,           0x11800100012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
29593         {"GMX1_TX003_STAT9"            ,           0x1180010001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
29594         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
29595         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
29596         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
29597         {"GMX0_TX003_STATS_CTL"        ,           0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
29598         {"GMX1_TX000_STATS_CTL"        ,           0x1180010000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
29599         {"GMX1_TX001_STATS_CTL"        ,           0x1180010000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
29600         {"GMX1_TX002_STATS_CTL"        ,           0x1180010001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
29601         {"GMX1_TX003_STATS_CTL"        ,           0x1180010001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
29602         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
29603         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
29604         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
29605         {"GMX0_TX003_THRESH"           ,           0x1180008001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
29606         {"GMX1_TX000_THRESH"           ,           0x1180010000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
29607         {"GMX1_TX001_THRESH"           ,           0x1180010000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
29608         {"GMX1_TX002_THRESH"           ,           0x1180010001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
29609         {"GMX1_TX003_THRESH"           ,           0x1180010001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
29610         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
29611         {"GMX1_TX_BP"                  ,           0x11800100004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
29612         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
29613         {"GMX1_TX_COL_ATTEMPT"         ,           0x1180010000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
29614         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
29615         {"GMX1_TX_CORRUPT"             ,           0x11800100004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
29616         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
29617         {"GMX1_TX_IFG"                 ,           0x1180010000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
29618         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
29619         {"GMX1_TX_INT_EN"              ,           0x1180010000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
29620         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
29621         {"GMX1_TX_INT_REG"             ,           0x1180010000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
29622         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
29623         {"GMX1_TX_JAM"                 ,           0x1180010000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
29624         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
29625         {"GMX1_TX_LFSR"                ,           0x11800100004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
29626         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
29627         {"GMX1_TX_OVR_BP"              ,           0x11800100004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
29628         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
29629         {"GMX1_TX_PAUSE_PKT_DMAC"      ,           0x11800100004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
29630         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
29631         {"GMX1_TX_PAUSE_PKT_TYPE"      ,           0x11800100004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
29632         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
29633         {"GMX1_TX_PRTS"                ,           0x1180010000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
29634         {"GMX0_TX_SPI_CTL"             ,           0x11800080004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
29635         {"GMX1_TX_SPI_CTL"             ,           0x11800100004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
29636         {"GMX0_TX_SPI_DRAIN"           ,           0x11800080004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
29637         {"GMX1_TX_SPI_DRAIN"           ,           0x11800100004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
29638         {"GMX0_TX_SPI_MAX"             ,           0x11800080004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
29639         {"GMX1_TX_SPI_MAX"             ,           0x11800100004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
29640         {"GMX0_TX_SPI_ROUND000"        ,           0x1180008000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29641         {"GMX0_TX_SPI_ROUND001"        ,           0x1180008000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29642         {"GMX0_TX_SPI_ROUND002"        ,           0x1180008000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29643         {"GMX0_TX_SPI_ROUND003"        ,           0x1180008000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29644         {"GMX0_TX_SPI_ROUND004"        ,           0x11800080006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29645         {"GMX0_TX_SPI_ROUND005"        ,           0x11800080006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29646         {"GMX0_TX_SPI_ROUND006"        ,           0x11800080006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29647         {"GMX0_TX_SPI_ROUND007"        ,           0x11800080006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29648         {"GMX0_TX_SPI_ROUND008"        ,           0x11800080006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29649         {"GMX0_TX_SPI_ROUND009"        ,           0x11800080006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29650         {"GMX0_TX_SPI_ROUND010"        ,           0x11800080006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29651         {"GMX0_TX_SPI_ROUND011"        ,           0x11800080006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29652         {"GMX0_TX_SPI_ROUND012"        ,           0x11800080006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29653         {"GMX0_TX_SPI_ROUND013"        ,           0x11800080006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29654         {"GMX0_TX_SPI_ROUND014"        ,           0x11800080006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29655         {"GMX0_TX_SPI_ROUND015"        ,           0x11800080006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29656         {"GMX0_TX_SPI_ROUND016"        ,           0x1180008000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29657         {"GMX0_TX_SPI_ROUND017"        ,           0x1180008000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29658         {"GMX0_TX_SPI_ROUND018"        ,           0x1180008000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29659         {"GMX0_TX_SPI_ROUND019"        ,           0x1180008000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29660         {"GMX0_TX_SPI_ROUND020"        ,           0x1180008000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29661         {"GMX0_TX_SPI_ROUND021"        ,           0x1180008000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29662         {"GMX0_TX_SPI_ROUND022"        ,           0x1180008000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29663         {"GMX0_TX_SPI_ROUND023"        ,           0x1180008000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29664         {"GMX0_TX_SPI_ROUND024"        ,           0x1180008000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29665         {"GMX0_TX_SPI_ROUND025"        ,           0x1180008000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29666         {"GMX0_TX_SPI_ROUND026"        ,           0x1180008000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29667         {"GMX0_TX_SPI_ROUND027"        ,           0x1180008000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29668         {"GMX0_TX_SPI_ROUND028"        ,           0x1180008000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29669         {"GMX0_TX_SPI_ROUND029"        ,           0x1180008000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29670         {"GMX0_TX_SPI_ROUND030"        ,           0x1180008000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29671         {"GMX0_TX_SPI_ROUND031"        ,           0x1180008000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29672         {"GMX1_TX_SPI_ROUND000"        ,           0x1180010000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29673         {"GMX1_TX_SPI_ROUND001"        ,           0x1180010000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29674         {"GMX1_TX_SPI_ROUND002"        ,           0x1180010000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29675         {"GMX1_TX_SPI_ROUND003"        ,           0x1180010000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29676         {"GMX1_TX_SPI_ROUND004"        ,           0x11800100006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29677         {"GMX1_TX_SPI_ROUND005"        ,           0x11800100006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29678         {"GMX1_TX_SPI_ROUND006"        ,           0x11800100006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29679         {"GMX1_TX_SPI_ROUND007"        ,           0x11800100006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29680         {"GMX1_TX_SPI_ROUND008"        ,           0x11800100006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29681         {"GMX1_TX_SPI_ROUND009"        ,           0x11800100006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29682         {"GMX1_TX_SPI_ROUND010"        ,           0x11800100006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29683         {"GMX1_TX_SPI_ROUND011"        ,           0x11800100006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29684         {"GMX1_TX_SPI_ROUND012"        ,           0x11800100006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29685         {"GMX1_TX_SPI_ROUND013"        ,           0x11800100006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29686         {"GMX1_TX_SPI_ROUND014"        ,           0x11800100006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29687         {"GMX1_TX_SPI_ROUND015"        ,           0x11800100006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29688         {"GMX1_TX_SPI_ROUND016"        ,           0x1180010000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29689         {"GMX1_TX_SPI_ROUND017"        ,           0x1180010000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29690         {"GMX1_TX_SPI_ROUND018"        ,           0x1180010000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29691         {"GMX1_TX_SPI_ROUND019"        ,           0x1180010000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29692         {"GMX1_TX_SPI_ROUND020"        ,           0x1180010000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29693         {"GMX1_TX_SPI_ROUND021"        ,           0x1180010000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29694         {"GMX1_TX_SPI_ROUND022"        ,           0x1180010000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29695         {"GMX1_TX_SPI_ROUND023"        ,           0x1180010000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29696         {"GMX1_TX_SPI_ROUND024"        ,           0x1180010000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29697         {"GMX1_TX_SPI_ROUND025"        ,           0x1180010000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29698         {"GMX1_TX_SPI_ROUND026"        ,           0x1180010000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29699         {"GMX1_TX_SPI_ROUND027"        ,           0x1180010000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29700         {"GMX1_TX_SPI_ROUND028"        ,           0x1180010000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29701         {"GMX1_TX_SPI_ROUND029"        ,           0x1180010000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29702         {"GMX1_TX_SPI_ROUND030"        ,           0x1180010000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29703         {"GMX1_TX_SPI_ROUND031"        ,           0x1180010000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
29704         {"GMX0_TX_SPI_THRESH"          ,           0x11800080004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
29705         {"GMX1_TX_SPI_THRESH"          ,           0x11800100004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
29706         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29707         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29708         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29709         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29710         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29711         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29712         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29713         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29714         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29715         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29716         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29717         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29718         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29719         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29720         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29721         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
29722         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     170},
29723         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     171},
29724         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     172},
29725         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     173},
29726         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
29727         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
29728         {"IOB_DWB_PRI_CNT"             ,           0x11800F0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
29729         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
29730         {"IOB_I2C_PRI_CNT"             ,           0x11800F0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
29731         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
29732         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
29733         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
29734         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
29735         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
29736         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
29737         {"IOB_N2C_L2C_PRI_CNT"         ,           0x11800F0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
29738         {"IOB_N2C_RSP_PRI_CNT"         ,           0x11800F0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
29739         {"IOB_OUTB_COM_PRI_CNT"        ,           0x11800F0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
29740         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
29741         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
29742         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
29743         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     191},
29744         {"IOB_OUTB_FPA_PRI_CNT"        ,           0x11800F0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     192},
29745         {"IOB_OUTB_REQ_PRI_CNT"        ,           0x11800F0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     193},
29746         {"IOB_P2C_REQ_PRI_CNT"         ,           0x11800F0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     194},
29747         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     195},
29748         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
29749         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     197},
29750         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     198},
29751         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     199},
29752         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     200},
29753         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     201},
29754         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
29755         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     203},
29756         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     204},
29757         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
29758         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
29759         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     207},
29760         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29761         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29762         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29763         {"IPD_PORT3_BP_PAGE_CNT"       ,           0x14F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29764         {"IPD_PORT4_BP_PAGE_CNT"       ,           0x14F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29765         {"IPD_PORT5_BP_PAGE_CNT"       ,           0x14F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29766         {"IPD_PORT6_BP_PAGE_CNT"       ,           0x14F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29767         {"IPD_PORT7_BP_PAGE_CNT"       ,           0x14F0000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29768         {"IPD_PORT8_BP_PAGE_CNT"       ,           0x14F0000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29769         {"IPD_PORT9_BP_PAGE_CNT"       ,           0x14F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29770         {"IPD_PORT10_BP_PAGE_CNT"      ,           0x14F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29771         {"IPD_PORT11_BP_PAGE_CNT"      ,           0x14F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29772         {"IPD_PORT12_BP_PAGE_CNT"      ,           0x14F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29773         {"IPD_PORT13_BP_PAGE_CNT"      ,           0x14F0000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29774         {"IPD_PORT14_BP_PAGE_CNT"      ,           0x14F0000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29775         {"IPD_PORT15_BP_PAGE_CNT"      ,           0x14F00000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29776         {"IPD_PORT16_BP_PAGE_CNT"      ,           0x14F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29777         {"IPD_PORT17_BP_PAGE_CNT"      ,           0x14F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29778         {"IPD_PORT18_BP_PAGE_CNT"      ,           0x14F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29779         {"IPD_PORT19_BP_PAGE_CNT"      ,           0x14F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29780         {"IPD_PORT20_BP_PAGE_CNT"      ,           0x14F00000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29781         {"IPD_PORT21_BP_PAGE_CNT"      ,           0x14F00000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29782         {"IPD_PORT22_BP_PAGE_CNT"      ,           0x14F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29783         {"IPD_PORT23_BP_PAGE_CNT"      ,           0x14F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29784         {"IPD_PORT24_BP_PAGE_CNT"      ,           0x14F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29785         {"IPD_PORT25_BP_PAGE_CNT"      ,           0x14F00000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29786         {"IPD_PORT26_BP_PAGE_CNT"      ,           0x14F00000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29787         {"IPD_PORT27_BP_PAGE_CNT"      ,           0x14F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29788         {"IPD_PORT28_BP_PAGE_CNT"      ,           0x14F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29789         {"IPD_PORT29_BP_PAGE_CNT"      ,           0x14F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29790         {"IPD_PORT30_BP_PAGE_CNT"      ,           0x14F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29791         {"IPD_PORT31_BP_PAGE_CNT"      ,           0x14F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29792         {"IPD_PORT32_BP_PAGE_CNT"      ,           0x14F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29793         {"IPD_PORT33_BP_PAGE_CNT"      ,           0x14F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29794         {"IPD_PORT34_BP_PAGE_CNT"      ,           0x14F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29795         {"IPD_PORT35_BP_PAGE_CNT"      ,           0x14F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
29796         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29797         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29798         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29799         {"IPD_PORT_BP_COUNTERS_PAIR3"  ,           0x14F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29800         {"IPD_PORT_BP_COUNTERS_PAIR4"  ,           0x14F00000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29801         {"IPD_PORT_BP_COUNTERS_PAIR5"  ,           0x14F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29802         {"IPD_PORT_BP_COUNTERS_PAIR6"  ,           0x14F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29803         {"IPD_PORT_BP_COUNTERS_PAIR7"  ,           0x14F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29804         {"IPD_PORT_BP_COUNTERS_PAIR8"  ,           0x14F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29805         {"IPD_PORT_BP_COUNTERS_PAIR9"  ,           0x14F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29806         {"IPD_PORT_BP_COUNTERS_PAIR10" ,           0x14F0000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29807         {"IPD_PORT_BP_COUNTERS_PAIR11" ,           0x14F0000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29808         {"IPD_PORT_BP_COUNTERS_PAIR12" ,           0x14F0000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29809         {"IPD_PORT_BP_COUNTERS_PAIR13" ,           0x14F0000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29810         {"IPD_PORT_BP_COUNTERS_PAIR14" ,           0x14F0000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29811         {"IPD_PORT_BP_COUNTERS_PAIR15" ,           0x14F0000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29812         {"IPD_PORT_BP_COUNTERS_PAIR16" ,           0x14F0000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29813         {"IPD_PORT_BP_COUNTERS_PAIR17" ,           0x14F0000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29814         {"IPD_PORT_BP_COUNTERS_PAIR18" ,           0x14F0000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29815         {"IPD_PORT_BP_COUNTERS_PAIR19" ,           0x14F0000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29816         {"IPD_PORT_BP_COUNTERS_PAIR20" ,           0x14F0000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29817         {"IPD_PORT_BP_COUNTERS_PAIR21" ,           0x14F0000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29818         {"IPD_PORT_BP_COUNTERS_PAIR22" ,           0x14F0000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29819         {"IPD_PORT_BP_COUNTERS_PAIR23" ,           0x14F0000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29820         {"IPD_PORT_BP_COUNTERS_PAIR24" ,           0x14F0000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29821         {"IPD_PORT_BP_COUNTERS_PAIR25" ,           0x14F0000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29822         {"IPD_PORT_BP_COUNTERS_PAIR26" ,           0x14F0000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29823         {"IPD_PORT_BP_COUNTERS_PAIR27" ,           0x14F0000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29824         {"IPD_PORT_BP_COUNTERS_PAIR28" ,           0x14F0000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29825         {"IPD_PORT_BP_COUNTERS_PAIR29" ,           0x14F00000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29826         {"IPD_PORT_BP_COUNTERS_PAIR30" ,           0x14F00000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29827         {"IPD_PORT_BP_COUNTERS_PAIR31" ,           0x14F00000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29828         {"IPD_PORT_BP_COUNTERS_PAIR32" ,           0x14F00000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29829         {"IPD_PORT_BP_COUNTERS_PAIR33" ,           0x14F00000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29830         {"IPD_PORT_BP_COUNTERS_PAIR34" ,           0x14F00000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29831         {"IPD_PORT_BP_COUNTERS_PAIR35" ,           0x14F00000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
29832         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     210},
29833         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     211},
29834         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     212},
29835         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     213},
29836         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     214},
29837         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     214},
29838         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     214},
29839         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     214},
29840         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     214},
29841         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     214},
29842         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     214},
29843         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     214},
29844         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     215},
29845         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     216},
29846         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     217},
29847         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     217},
29848         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     217},
29849         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     217},
29850         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     217},
29851         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     217},
29852         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     217},
29853         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     217},
29854         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     218},
29855         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     219},
29856         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     220},
29857         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     221},
29858         {"KEY_BIST_REG"                ,           0x1180020000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
29859         {"KEY_CTL_STATUS"              ,           0x1180020000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
29860         {"KEY_INT_ENB"                 ,           0x1180020000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
29861         {"KEY_INT_SUM"                 ,           0x1180020000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     225},
29862         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     226},
29863         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     227},
29864         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
29865         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
29866         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
29867         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
29868         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     232},
29869         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
29870         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     234},
29871         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     235},
29872         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     236},
29873         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     237},
29874         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
29875         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
29876         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
29877         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
29878         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     239},
29879         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     240},
29880         {"L2C_SPAR1"                   ,           0x1180080000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
29881         {"L2C_SPAR2"                   ,           0x1180080000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
29882         {"L2C_SPAR3"                   ,           0x1180080000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     243},
29883         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     244},
29884         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     245},
29885         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     246},
29886         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     247},
29887         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     248},
29888         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     249},
29889         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
29890         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
29891         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
29892         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
29893         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
29894         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
29895         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
29896         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
29897         {"LED_BLINK"                   ,           0x1180000001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
29898         {"LED_CLK_PHASE"               ,           0x1180000001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
29899         {"LED_CYLON"                   ,           0x1180000001AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
29900         {"LED_DBG"                     ,           0x1180000001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
29901         {"LED_EN"                      ,           0x1180000001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
29902         {"LED_POLARITY"                ,           0x1180000001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
29903         {"LED_PRT"                     ,           0x1180000001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
29904         {"LED_PRT_FMT"                 ,           0x1180000001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
29905         {"LED_PRT_STATUS0"             ,           0x1180000001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
29906         {"LED_PRT_STATUS1"             ,           0x1180000001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
29907         {"LED_PRT_STATUS2"             ,           0x1180000001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
29908         {"LED_PRT_STATUS3"             ,           0x1180000001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
29909         {"LED_PRT_STATUS4"             ,           0x1180000001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
29910         {"LED_PRT_STATUS5"             ,           0x1180000001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
29911         {"LED_PRT_STATUS6"             ,           0x1180000001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
29912         {"LED_PRT_STATUS7"             ,           0x1180000001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
29913         {"LED_UDD_CNT0"                ,           0x1180000001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
29914         {"LED_UDD_CNT1"                ,           0x1180000001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
29915         {"LED_UDD_DAT0"                ,           0x1180000001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
29916         {"LED_UDD_DAT1"                ,           0x1180000001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
29917         {"LED_UDD_DAT_CLR0"            ,           0x1180000001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
29918         {"LED_UDD_DAT_CLR1"            ,           0x1180000001AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
29919         {"LED_UDD_DAT_SET0"            ,           0x1180000001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
29920         {"LED_UDD_DAT_SET1"            ,           0x1180000001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
29921         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
29922         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
29923         {"LMC0_CTL1"                   ,           0x1180088000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
29924         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
29925         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
29926         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
29927         {"LMC0_DELAY_CFG"              ,           0x1180088000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
29928         {"LMC0_DUAL_MEMCFG"            ,           0x1180088000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
29929         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
29930         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
29931         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
29932         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
29933         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
29934         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
29935         {"LMC0_NXM"                    ,           0x11800880000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
29936         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
29937         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     287},
29938         {"LMC0_PLL_CTL"                ,           0x11800880000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     288},
29939         {"LMC0_PLL_STATUS"             ,           0x11800880000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     289},
29940         {"LMC0_RODT_COMP_CTL"          ,           0x11800880000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
29941         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
29942         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     292},
29943         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
29944         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     294},
29945         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     295},
29946         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     296},
29947         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
29948         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
29949         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     298},
29950         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
29951         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
29952         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
29953         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
29954         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
29955         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
29956         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
29957         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
29958         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
29959         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
29960         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
29961         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
29962         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
29963         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
29964         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
29965         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
29966         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
29967         {"MIO_FUS_BNK_DAT0"            ,           0x1180000001520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
29968         {"MIO_FUS_BNK_DAT1"            ,           0x1180000001528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
29969         {"MIO_FUS_BNK_DAT2"            ,           0x1180000001530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
29970         {"MIO_FUS_BNK_DAT3"            ,           0x1180000001538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
29971         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
29972         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
29973         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
29974         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
29975         {"MIO_FUS_EMA"                 ,           0x1180000001550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
29976         {"MIO_FUS_PDF"                 ,           0x1180000001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
29977         {"MIO_FUS_PLL"                 ,           0x1180000001580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
29978         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
29979         {"MIO_FUS_PROG_TIMES"          ,           0x1180000001518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
29980         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
29981         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
29982         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
29983         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
29984         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
29985         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
29986         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
29987         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
29988         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
29989         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
29990         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
29991         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
29992         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
29993         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
29994         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
29995         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
29996         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
29997         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
29998         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
29999         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
30000         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
30001         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
30002         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
30003         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
30004         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
30005         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
30006         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
30007         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
30008         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
30009         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
30010         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
30011         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
30012         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
30013         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
30014         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
30015         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
30016         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
30017         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
30018         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     335},
30019         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     335},
30020         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     336},
30021         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     336},
30022         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     337},
30023         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     337},
30024         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     338},
30025         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     338},
30026         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     339},
30027         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     339},
30028         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
30029         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
30030         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     341},
30031         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     341},
30032         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     342},
30033         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     342},
30034         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
30035         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
30036         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
30037         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
30038         {"NPI_BASE_ADDR_INPUT0"        ,           0x11F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     345},
30039         {"NPI_BASE_ADDR_INPUT1"        ,           0x11F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     345},
30040         {"NPI_BASE_ADDR_INPUT2"        ,           0x11F0000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     345},
30041         {"NPI_BASE_ADDR_INPUT3"        ,           0x11F00000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     345},
30042         {"NPI_BASE_ADDR_OUTPUT0"       ,           0x11F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
30043         {"NPI_BASE_ADDR_OUTPUT1"       ,           0x11F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
30044         {"NPI_BASE_ADDR_OUTPUT2"       ,           0x11F00000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
30045         {"NPI_BASE_ADDR_OUTPUT3"       ,           0x11F00000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     346},
30046         {"NPI_BIST_STATUS"             ,           0x11F00000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     347},
30047         {"NPI_BUFF_SIZE_OUTPUT0"       ,           0x11F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
30048         {"NPI_BUFF_SIZE_OUTPUT1"       ,           0x11F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
30049         {"NPI_BUFF_SIZE_OUTPUT2"       ,           0x11F00000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
30050         {"NPI_BUFF_SIZE_OUTPUT3"       ,           0x11F00000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     348},
30051         {"NPI_COMP_CTL"                ,           0x11F0000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     349},
30052         {"NPI_CTL_STATUS"              ,           0x11F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     350},
30053         {"NPI_DBG_SELECT"              ,           0x11F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     351},
30054         {"NPI_DMA_CONTROL"             ,           0x11F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     352},
30055         {"NPI_DMA_HIGHP_COUNTS"        ,           0x11F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     353},
30056         {"NPI_DMA_HIGHP_NADDR"         ,           0x11F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     354},
30057         {"NPI_DMA_LOWP_COUNTS"         ,           0x11F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     355},
30058         {"NPI_DMA_LOWP_NADDR"          ,           0x11F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     356},
30059         {"NPI_HIGHP_DBELL"             ,           0x11F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     357},
30060         {"NPI_HIGHP_IBUFF_SADDR"       ,           0x11F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     358},
30061         {"NPI_INPUT_CONTROL"           ,           0x11F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     359},
30062         {"NPI_INT_ENB"                 ,           0x11F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     360},
30063         {"NPI_INT_SUM"                 ,           0x11F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     361},
30064         {"NPI_LOWP_DBELL"              ,           0x11F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     362},
30065         {"NPI_LOWP_IBUFF_SADDR"        ,           0x11F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     363},
30066         {"NPI_MEM_ACCESS_SUBID3"       ,           0x11F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     364},
30067         {"NPI_MEM_ACCESS_SUBID4"       ,           0x11F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     364},
30068         {"NPI_MEM_ACCESS_SUBID5"       ,           0x11F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     364},
30069         {"NPI_MEM_ACCESS_SUBID6"       ,           0x11F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     364},
30070         {"NPI_MSI_RCV"                 ,           0x11F0000001190ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     365},
30071         {"NPI_NUM_DESC_OUTPUT0"        ,           0x11F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     366},
30072         {"NPI_NUM_DESC_OUTPUT1"        ,           0x11F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     366},
30073         {"NPI_NUM_DESC_OUTPUT2"        ,           0x11F0000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     366},
30074         {"NPI_NUM_DESC_OUTPUT3"        ,           0x11F0000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     366},
30075         {"NPI_OUTPUT_CONTROL"          ,           0x11F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     367},
30076         {"NPI_P0_DBPAIR_ADDR"          ,           0x11F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     368},
30077         {"NPI_P1_DBPAIR_ADDR"          ,           0x11F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     368},
30078         {"NPI_P2_DBPAIR_ADDR"          ,           0x11F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     368},
30079         {"NPI_P3_DBPAIR_ADDR"          ,           0x11F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     368},
30080         {"NPI_P0_INSTR_ADDR"           ,           0x11F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     369},
30081         {"NPI_P1_INSTR_ADDR"           ,           0x11F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     369},
30082         {"NPI_P2_INSTR_ADDR"           ,           0x11F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     369},
30083         {"NPI_P3_INSTR_ADDR"           ,           0x11F00000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     369},
30084         {"NPI_P0_INSTR_CNTS"           ,           0x11F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     370},
30085         {"NPI_P1_INSTR_CNTS"           ,           0x11F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     370},
30086         {"NPI_P2_INSTR_CNTS"           ,           0x11F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     370},
30087         {"NPI_P3_INSTR_CNTS"           ,           0x11F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     370},
30088         {"NPI_P0_PAIR_CNTS"            ,           0x11F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
30089         {"NPI_P1_PAIR_CNTS"            ,           0x11F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
30090         {"NPI_P2_PAIR_CNTS"            ,           0x11F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
30091         {"NPI_P3_PAIR_CNTS"            ,           0x11F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     371},
30092         {"NPI_PCI_BURST_SIZE"          ,           0x11F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     372},
30093         {"NPI_PCI_INT_ARB_CFG"         ,           0x11F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     373},
30094         {"NPI_PCI_READ_CMD"            ,           0x11F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     374},
30095         {"NPI_PORT32_INSTR_HDR"        ,           0x11F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     375},
30096         {"NPI_PORT33_INSTR_HDR"        ,           0x11F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     376},
30097         {"NPI_PORT34_INSTR_HDR"        ,           0x11F0000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     377},
30098         {"NPI_PORT35_INSTR_HDR"        ,           0x11F0000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     378},
30099         {"NPI_PORT_BP_CONTROL"         ,           0x11F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     379},
30100         {"NPI_RSL_INT_BLOCKS"          ,           0x11F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     380},
30101         {"NPI_SIZE_INPUT0"             ,           0x11F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
30102         {"NPI_SIZE_INPUT1"             ,           0x11F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
30103         {"NPI_SIZE_INPUT2"             ,           0x11F0000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
30104         {"NPI_SIZE_INPUT3"             ,           0x11F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
30105         {"NPI_WIN_READ_TO"             ,           0x11F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
30106         {"PCI_BAR1_INDEX0"             ,           0x11F0000001100ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30107         {"PCI_BAR1_INDEX1"             ,           0x11F0000001104ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30108         {"PCI_BAR1_INDEX2"             ,           0x11F0000001108ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30109         {"PCI_BAR1_INDEX3"             ,           0x11F000000110Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30110         {"PCI_BAR1_INDEX4"             ,           0x11F0000001110ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30111         {"PCI_BAR1_INDEX5"             ,           0x11F0000001114ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30112         {"PCI_BAR1_INDEX6"             ,           0x11F0000001118ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30113         {"PCI_BAR1_INDEX7"             ,           0x11F000000111Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30114         {"PCI_BAR1_INDEX8"             ,           0x11F0000001120ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30115         {"PCI_BAR1_INDEX9"             ,           0x11F0000001124ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30116         {"PCI_BAR1_INDEX10"            ,           0x11F0000001128ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30117         {"PCI_BAR1_INDEX11"            ,           0x11F000000112Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30118         {"PCI_BAR1_INDEX12"            ,           0x11F0000001130ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30119         {"PCI_BAR1_INDEX13"            ,           0x11F0000001134ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30120         {"PCI_BAR1_INDEX14"            ,           0x11F0000001138ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30121         {"PCI_BAR1_INDEX15"            ,           0x11F000000113Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30122         {"PCI_BAR1_INDEX16"            ,           0x11F0000001140ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30123         {"PCI_BAR1_INDEX17"            ,           0x11F0000001144ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30124         {"PCI_BAR1_INDEX18"            ,           0x11F0000001148ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30125         {"PCI_BAR1_INDEX19"            ,           0x11F000000114Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30126         {"PCI_BAR1_INDEX20"            ,           0x11F0000001150ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30127         {"PCI_BAR1_INDEX21"            ,           0x11F0000001154ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30128         {"PCI_BAR1_INDEX22"            ,           0x11F0000001158ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30129         {"PCI_BAR1_INDEX23"            ,           0x11F000000115Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30130         {"PCI_BAR1_INDEX24"            ,           0x11F0000001160ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30131         {"PCI_BAR1_INDEX25"            ,           0x11F0000001164ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30132         {"PCI_BAR1_INDEX26"            ,           0x11F0000001168ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30133         {"PCI_BAR1_INDEX27"            ,           0x11F000000116Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30134         {"PCI_BAR1_INDEX28"            ,           0x11F0000001170ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30135         {"PCI_BAR1_INDEX29"            ,           0x11F0000001174ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30136         {"PCI_BAR1_INDEX30"            ,           0x11F0000001178ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30137         {"PCI_BAR1_INDEX31"            ,           0x11F000000117Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     383},
30138         {"PCI_CFG00"                   ,           0x11F0000001800ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     384},
30139         {"PCI_CFG01"                   ,           0x11F0000001804ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     385},
30140         {"PCI_CFG02"                   ,           0x11F0000001808ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     386},
30141         {"PCI_CFG03"                   ,           0x11F000000180Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     387},
30142         {"PCI_CFG04"                   ,           0x11F0000001810ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     388},
30143         {"PCI_CFG05"                   ,           0x11F0000001814ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     389},
30144         {"PCI_CFG06"                   ,           0x11F0000001818ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     390},
30145         {"PCI_CFG07"                   ,           0x11F000000181Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     391},
30146         {"PCI_CFG08"                   ,           0x11F0000001820ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     392},
30147         {"PCI_CFG09"                   ,           0x11F0000001824ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     393},
30148         {"PCI_CFG10"                   ,           0x11F0000001828ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     394},
30149         {"PCI_CFG11"                   ,           0x11F000000182Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     395},
30150         {"PCI_CFG12"                   ,           0x11F0000001830ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     396},
30151         {"PCI_CFG13"                   ,           0x11F0000001834ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     397},
30152         {"PCI_CFG15"                   ,           0x11F000000183Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     398},
30153         {"PCI_CFG16"                   ,           0x11F0000001840ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     399},
30154         {"PCI_CFG17"                   ,           0x11F0000001844ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     400},
30155         {"PCI_CFG18"                   ,           0x11F0000001848ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     401},
30156         {"PCI_CFG19"                   ,           0x11F000000184Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     402},
30157         {"PCI_CFG20"                   ,           0x11F0000001850ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     403},
30158         {"PCI_CFG21"                   ,           0x11F0000001854ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     404},
30159         {"PCI_CFG22"                   ,           0x11F0000001858ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     405},
30160         {"PCI_CFG56"                   ,           0x11F00000018E0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     406},
30161         {"PCI_CFG57"                   ,           0x11F00000018E4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     407},
30162         {"PCI_CFG58"                   ,           0x11F00000018E8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     408},
30163         {"PCI_CFG59"                   ,           0x11F00000018ECull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     409},
30164         {"PCI_CFG60"                   ,           0x11F00000018F0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     410},
30165         {"PCI_CFG61"                   ,           0x11F00000018F4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     411},
30166         {"PCI_CFG62"                   ,           0x11F00000018F8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     412},
30167         {"PCI_CFG63"                   ,           0x11F00000018FCull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     413},
30168         {"PCI_CNT_REG"                 ,           0x11F00000011B8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     414},
30169         {"PCI_CTL_STATUS_2"            ,           0x11F000000118Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     415},
30170         {"PCI_DBELL0"                  ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCI,   32,     416},
30171         {"PCI_DBELL1"                  ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCI,   32,     416},
30172         {"PCI_DBELL2"                  ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCI,   32,     416},
30173         {"PCI_DBELL3"                  ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCI,   32,     416},
30174         {"PCI_DMA_CNT0"                ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     417},
30175         {"PCI_DMA_CNT1"                ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCI,   32,     417},
30176         {"PCI_DMA_INT_LEV0"            ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     418},
30177         {"PCI_DMA_INT_LEV1"            ,                      0xACull,  CVMX_CSR_DB_TYPE_PCI,   32,     418},
30178         {"PCI_DMA_TIME0"               ,                      0xB0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     419},
30179         {"PCI_DMA_TIME1"               ,                      0xB4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     419},
30180         {"PCI_INSTR_COUNT0"            ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCI,   32,     420},
30181         {"PCI_INSTR_COUNT1"            ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     420},
30182         {"PCI_INSTR_COUNT2"            ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCI,   32,     420},
30183         {"PCI_INSTR_COUNT3"            ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     420},
30184         {"PCI_INT_ENB"                 ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCI,   64,     421},
30185         {"PCI_INT_ENB2"                ,           0x11F00000011A0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     422},
30186         {"PCI_INT_SUM"                 ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCI,   64,     423},
30187         {"PCI_INT_SUM2"                ,           0x11F0000001198ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     424},
30188         {"PCI_MSI_RCV"                 ,                      0xF0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     425},
30189         {"PCI_PKT_CREDITS0"            ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCI,   32,     426},
30190         {"PCI_PKT_CREDITS1"            ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCI,   32,     426},
30191         {"PCI_PKT_CREDITS2"            ,                      0x64ull,  CVMX_CSR_DB_TYPE_PCI,   32,     426},
30192         {"PCI_PKT_CREDITS3"            ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCI,   32,     426},
30193         {"PCI_PKTS_SENT0"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCI,   32,     427},
30194         {"PCI_PKTS_SENT1"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCI,   32,     427},
30195         {"PCI_PKTS_SENT2"              ,                      0x60ull,  CVMX_CSR_DB_TYPE_PCI,   32,     427},
30196         {"PCI_PKTS_SENT3"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCI,   32,     427},
30197         {"PCI_PKTS_SENT_INT_LEV0"      ,                      0x48ull,  CVMX_CSR_DB_TYPE_PCI,   32,     428},
30198         {"PCI_PKTS_SENT_INT_LEV1"      ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCI,   32,     428},
30199         {"PCI_PKTS_SENT_INT_LEV2"      ,                      0x68ull,  CVMX_CSR_DB_TYPE_PCI,   32,     428},
30200         {"PCI_PKTS_SENT_INT_LEV3"      ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCI,   32,     428},
30201         {"PCI_PKTS_SENT_TIME0"         ,                      0x4Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     429},
30202         {"PCI_PKTS_SENT_TIME1"         ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     429},
30203         {"PCI_PKTS_SENT_TIME2"         ,                      0x6Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     429},
30204         {"PCI_PKTS_SENT_TIME3"         ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     429},
30205         {"PCI_READ_CMD_6"              ,           0x11F0000001180ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     430},
30206         {"PCI_READ_CMD_C"              ,           0x11F0000001184ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     431},
30207         {"PCI_READ_CMD_E"              ,           0x11F0000001188ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     432},
30208         {"PCI_READ_TIMEOUT"            ,           0x11F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     433},
30209         {"PCI_SCM_REG"                 ,           0x11F00000011A8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     434},
30210         {"PCI_TSR_REG"                 ,           0x11F00000011B0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     435},
30211         {"PCI_WIN_RD_ADDR"             ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCI,   64,     436},
30212         {"PCI_WIN_RD_DATA"             ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCI,   64,     437},
30213         {"PCI_WIN_WR_ADDR"             ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCI,   64,     438},
30214         {"PCI_WIN_WR_DATA"             ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCI,   64,     439},
30215         {"PCI_WIN_WR_MASK"             ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCI,   64,     440},
30216         {"PIP_BCK_PRS"                 ,           0x11800A0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
30217         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
30218         {"PIP_CRC_CTL0"                ,           0x11800A0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
30219         {"PIP_CRC_CTL1"                ,           0x11800A0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
30220         {"PIP_CRC_IV0"                 ,           0x11800A0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
30221         {"PIP_CRC_IV1"                 ,           0x11800A0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
30222         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
30223         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
30224         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
30225         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
30226         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
30227         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     447},
30228         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
30229         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
30230         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
30231         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30232         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30233         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30234         {"PIP_PRT_CFG3"                ,           0x11800A0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30235         {"PIP_PRT_CFG4"                ,           0x11800A0000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30236         {"PIP_PRT_CFG5"                ,           0x11800A0000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30237         {"PIP_PRT_CFG6"                ,           0x11800A0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30238         {"PIP_PRT_CFG7"                ,           0x11800A0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30239         {"PIP_PRT_CFG8"                ,           0x11800A0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30240         {"PIP_PRT_CFG9"                ,           0x11800A0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30241         {"PIP_PRT_CFG10"               ,           0x11800A0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30242         {"PIP_PRT_CFG11"               ,           0x11800A0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30243         {"PIP_PRT_CFG12"               ,           0x11800A0000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30244         {"PIP_PRT_CFG13"               ,           0x11800A0000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30245         {"PIP_PRT_CFG14"               ,           0x11800A0000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30246         {"PIP_PRT_CFG15"               ,           0x11800A0000278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30247         {"PIP_PRT_CFG16"               ,           0x11800A0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30248         {"PIP_PRT_CFG17"               ,           0x11800A0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30249         {"PIP_PRT_CFG18"               ,           0x11800A0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30250         {"PIP_PRT_CFG19"               ,           0x11800A0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30251         {"PIP_PRT_CFG20"               ,           0x11800A00002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30252         {"PIP_PRT_CFG21"               ,           0x11800A00002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30253         {"PIP_PRT_CFG22"               ,           0x11800A00002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30254         {"PIP_PRT_CFG23"               ,           0x11800A00002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30255         {"PIP_PRT_CFG24"               ,           0x11800A00002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30256         {"PIP_PRT_CFG25"               ,           0x11800A00002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30257         {"PIP_PRT_CFG26"               ,           0x11800A00002D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30258         {"PIP_PRT_CFG27"               ,           0x11800A00002D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30259         {"PIP_PRT_CFG28"               ,           0x11800A00002E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30260         {"PIP_PRT_CFG29"               ,           0x11800A00002E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30261         {"PIP_PRT_CFG30"               ,           0x11800A00002F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30262         {"PIP_PRT_CFG31"               ,           0x11800A00002F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30263         {"PIP_PRT_CFG32"               ,           0x11800A0000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30264         {"PIP_PRT_CFG33"               ,           0x11800A0000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30265         {"PIP_PRT_CFG34"               ,           0x11800A0000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30266         {"PIP_PRT_CFG35"               ,           0x11800A0000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
30267         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30268         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30269         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30270         {"PIP_PRT_TAG3"                ,           0x11800A0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30271         {"PIP_PRT_TAG4"                ,           0x11800A0000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30272         {"PIP_PRT_TAG5"                ,           0x11800A0000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30273         {"PIP_PRT_TAG6"                ,           0x11800A0000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30274         {"PIP_PRT_TAG7"                ,           0x11800A0000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30275         {"PIP_PRT_TAG8"                ,           0x11800A0000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30276         {"PIP_PRT_TAG9"                ,           0x11800A0000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30277         {"PIP_PRT_TAG10"               ,           0x11800A0000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30278         {"PIP_PRT_TAG11"               ,           0x11800A0000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30279         {"PIP_PRT_TAG12"               ,           0x11800A0000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30280         {"PIP_PRT_TAG13"               ,           0x11800A0000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30281         {"PIP_PRT_TAG14"               ,           0x11800A0000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30282         {"PIP_PRT_TAG15"               ,           0x11800A0000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30283         {"PIP_PRT_TAG16"               ,           0x11800A0000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30284         {"PIP_PRT_TAG17"               ,           0x11800A0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30285         {"PIP_PRT_TAG18"               ,           0x11800A0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30286         {"PIP_PRT_TAG19"               ,           0x11800A0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30287         {"PIP_PRT_TAG20"               ,           0x11800A00004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30288         {"PIP_PRT_TAG21"               ,           0x11800A00004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30289         {"PIP_PRT_TAG22"               ,           0x11800A00004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30290         {"PIP_PRT_TAG23"               ,           0x11800A00004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30291         {"PIP_PRT_TAG24"               ,           0x11800A00004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30292         {"PIP_PRT_TAG25"               ,           0x11800A00004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30293         {"PIP_PRT_TAG26"               ,           0x11800A00004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30294         {"PIP_PRT_TAG27"               ,           0x11800A00004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30295         {"PIP_PRT_TAG28"               ,           0x11800A00004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30296         {"PIP_PRT_TAG29"               ,           0x11800A00004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30297         {"PIP_PRT_TAG30"               ,           0x11800A00004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30298         {"PIP_PRT_TAG31"               ,           0x11800A00004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30299         {"PIP_PRT_TAG32"               ,           0x11800A0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30300         {"PIP_PRT_TAG33"               ,           0x11800A0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30301         {"PIP_PRT_TAG34"               ,           0x11800A0000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30302         {"PIP_PRT_TAG35"               ,           0x11800A0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
30303         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30304         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30305         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30306         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30307         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30308         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30309         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30310         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30311         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30312         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30313         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30314         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30315         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30316         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30317         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30318         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30319         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30320         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30321         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30322         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30323         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30324         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30325         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30326         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30327         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30328         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30329         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30330         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30331         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30332         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30333         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30334         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30335         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30336         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30337         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30338         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30339         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30340         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30341         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30342         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30343         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30344         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30345         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30346         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30347         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30348         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30349         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30350         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30351         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30352         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30353         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30354         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30355         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30356         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30357         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30358         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30359         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30360         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30361         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30362         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30363         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30364         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30365         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30366         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
30367         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
30368         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
30369         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
30370         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
30371         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
30372         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
30373         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
30374         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
30375         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
30376         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
30377         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
30378         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
30379         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
30380         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
30381         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30382         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30383         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30384         {"PIP_STAT0_PRT3"              ,           0x11800A00008F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30385         {"PIP_STAT0_PRT4"              ,           0x11800A0000940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30386         {"PIP_STAT0_PRT5"              ,           0x11800A0000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30387         {"PIP_STAT0_PRT6"              ,           0x11800A00009E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30388         {"PIP_STAT0_PRT7"              ,           0x11800A0000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30389         {"PIP_STAT0_PRT8"              ,           0x11800A0000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30390         {"PIP_STAT0_PRT9"              ,           0x11800A0000AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30391         {"PIP_STAT0_PRT10"             ,           0x11800A0000B20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30392         {"PIP_STAT0_PRT11"             ,           0x11800A0000B70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30393         {"PIP_STAT0_PRT12"             ,           0x11800A0000BC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30394         {"PIP_STAT0_PRT13"             ,           0x11800A0000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30395         {"PIP_STAT0_PRT14"             ,           0x11800A0000C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30396         {"PIP_STAT0_PRT15"             ,           0x11800A0000CB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30397         {"PIP_STAT0_PRT16"             ,           0x11800A0000D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30398         {"PIP_STAT0_PRT17"             ,           0x11800A0000D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30399         {"PIP_STAT0_PRT18"             ,           0x11800A0000DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30400         {"PIP_STAT0_PRT19"             ,           0x11800A0000DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30401         {"PIP_STAT0_PRT20"             ,           0x11800A0000E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30402         {"PIP_STAT0_PRT21"             ,           0x11800A0000E90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30403         {"PIP_STAT0_PRT22"             ,           0x11800A0000EE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30404         {"PIP_STAT0_PRT23"             ,           0x11800A0000F30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30405         {"PIP_STAT0_PRT24"             ,           0x11800A0000F80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30406         {"PIP_STAT0_PRT25"             ,           0x11800A0000FD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30407         {"PIP_STAT0_PRT26"             ,           0x11800A0001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30408         {"PIP_STAT0_PRT27"             ,           0x11800A0001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30409         {"PIP_STAT0_PRT28"             ,           0x11800A00010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30410         {"PIP_STAT0_PRT29"             ,           0x11800A0001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30411         {"PIP_STAT0_PRT30"             ,           0x11800A0001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30412         {"PIP_STAT0_PRT31"             ,           0x11800A00011B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30413         {"PIP_STAT0_PRT32"             ,           0x11800A0001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30414         {"PIP_STAT0_PRT33"             ,           0x11800A0001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30415         {"PIP_STAT0_PRT34"             ,           0x11800A00012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30416         {"PIP_STAT0_PRT35"             ,           0x11800A00012F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
30417         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30418         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30419         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30420         {"PIP_STAT1_PRT3"              ,           0x11800A00008F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30421         {"PIP_STAT1_PRT4"              ,           0x11800A0000948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30422         {"PIP_STAT1_PRT5"              ,           0x11800A0000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30423         {"PIP_STAT1_PRT6"              ,           0x11800A00009E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30424         {"PIP_STAT1_PRT7"              ,           0x11800A0000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30425         {"PIP_STAT1_PRT8"              ,           0x11800A0000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30426         {"PIP_STAT1_PRT9"              ,           0x11800A0000AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30427         {"PIP_STAT1_PRT10"             ,           0x11800A0000B28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30428         {"PIP_STAT1_PRT11"             ,           0x11800A0000B78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30429         {"PIP_STAT1_PRT12"             ,           0x11800A0000BC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30430         {"PIP_STAT1_PRT13"             ,           0x11800A0000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30431         {"PIP_STAT1_PRT14"             ,           0x11800A0000C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30432         {"PIP_STAT1_PRT15"             ,           0x11800A0000CB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30433         {"PIP_STAT1_PRT16"             ,           0x11800A0000D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30434         {"PIP_STAT1_PRT17"             ,           0x11800A0000D58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30435         {"PIP_STAT1_PRT18"             ,           0x11800A0000DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30436         {"PIP_STAT1_PRT19"             ,           0x11800A0000DF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30437         {"PIP_STAT1_PRT20"             ,           0x11800A0000E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30438         {"PIP_STAT1_PRT21"             ,           0x11800A0000E98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30439         {"PIP_STAT1_PRT22"             ,           0x11800A0000EE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30440         {"PIP_STAT1_PRT23"             ,           0x11800A0000F38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30441         {"PIP_STAT1_PRT24"             ,           0x11800A0000F88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30442         {"PIP_STAT1_PRT25"             ,           0x11800A0000FD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30443         {"PIP_STAT1_PRT26"             ,           0x11800A0001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30444         {"PIP_STAT1_PRT27"             ,           0x11800A0001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30445         {"PIP_STAT1_PRT28"             ,           0x11800A00010C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30446         {"PIP_STAT1_PRT29"             ,           0x11800A0001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30447         {"PIP_STAT1_PRT30"             ,           0x11800A0001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30448         {"PIP_STAT1_PRT31"             ,           0x11800A00011B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30449         {"PIP_STAT1_PRT32"             ,           0x11800A0001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30450         {"PIP_STAT1_PRT33"             ,           0x11800A0001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30451         {"PIP_STAT1_PRT34"             ,           0x11800A00012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30452         {"PIP_STAT1_PRT35"             ,           0x11800A00012F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
30453         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30454         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30455         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30456         {"PIP_STAT2_PRT3"              ,           0x11800A0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30457         {"PIP_STAT2_PRT4"              ,           0x11800A0000950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30458         {"PIP_STAT2_PRT5"              ,           0x11800A00009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30459         {"PIP_STAT2_PRT6"              ,           0x11800A00009F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30460         {"PIP_STAT2_PRT7"              ,           0x11800A0000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30461         {"PIP_STAT2_PRT8"              ,           0x11800A0000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30462         {"PIP_STAT2_PRT9"              ,           0x11800A0000AE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30463         {"PIP_STAT2_PRT10"             ,           0x11800A0000B30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30464         {"PIP_STAT2_PRT11"             ,           0x11800A0000B80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30465         {"PIP_STAT2_PRT12"             ,           0x11800A0000BD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30466         {"PIP_STAT2_PRT13"             ,           0x11800A0000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30467         {"PIP_STAT2_PRT14"             ,           0x11800A0000C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30468         {"PIP_STAT2_PRT15"             ,           0x11800A0000CC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30469         {"PIP_STAT2_PRT16"             ,           0x11800A0000D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30470         {"PIP_STAT2_PRT17"             ,           0x11800A0000D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30471         {"PIP_STAT2_PRT18"             ,           0x11800A0000DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30472         {"PIP_STAT2_PRT19"             ,           0x11800A0000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30473         {"PIP_STAT2_PRT20"             ,           0x11800A0000E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30474         {"PIP_STAT2_PRT21"             ,           0x11800A0000EA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30475         {"PIP_STAT2_PRT22"             ,           0x11800A0000EF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30476         {"PIP_STAT2_PRT23"             ,           0x11800A0000F40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30477         {"PIP_STAT2_PRT24"             ,           0x11800A0000F90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30478         {"PIP_STAT2_PRT25"             ,           0x11800A0000FE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30479         {"PIP_STAT2_PRT26"             ,           0x11800A0001030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30480         {"PIP_STAT2_PRT27"             ,           0x11800A0001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30481         {"PIP_STAT2_PRT28"             ,           0x11800A00010D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30482         {"PIP_STAT2_PRT29"             ,           0x11800A0001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30483         {"PIP_STAT2_PRT30"             ,           0x11800A0001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30484         {"PIP_STAT2_PRT31"             ,           0x11800A00011C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30485         {"PIP_STAT2_PRT32"             ,           0x11800A0001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30486         {"PIP_STAT2_PRT33"             ,           0x11800A0001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30487         {"PIP_STAT2_PRT34"             ,           0x11800A00012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30488         {"PIP_STAT2_PRT35"             ,           0x11800A0001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
30489         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30490         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30491         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30492         {"PIP_STAT3_PRT3"              ,           0x11800A0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30493         {"PIP_STAT3_PRT4"              ,           0x11800A0000958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30494         {"PIP_STAT3_PRT5"              ,           0x11800A00009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30495         {"PIP_STAT3_PRT6"              ,           0x11800A00009F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30496         {"PIP_STAT3_PRT7"              ,           0x11800A0000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30497         {"PIP_STAT3_PRT8"              ,           0x11800A0000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30498         {"PIP_STAT3_PRT9"              ,           0x11800A0000AE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30499         {"PIP_STAT3_PRT10"             ,           0x11800A0000B38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30500         {"PIP_STAT3_PRT11"             ,           0x11800A0000B88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30501         {"PIP_STAT3_PRT12"             ,           0x11800A0000BD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30502         {"PIP_STAT3_PRT13"             ,           0x11800A0000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30503         {"PIP_STAT3_PRT14"             ,           0x11800A0000C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30504         {"PIP_STAT3_PRT15"             ,           0x11800A0000CC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30505         {"PIP_STAT3_PRT16"             ,           0x11800A0000D18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30506         {"PIP_STAT3_PRT17"             ,           0x11800A0000D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30507         {"PIP_STAT3_PRT18"             ,           0x11800A0000DB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30508         {"PIP_STAT3_PRT19"             ,           0x11800A0000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30509         {"PIP_STAT3_PRT20"             ,           0x11800A0000E58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30510         {"PIP_STAT3_PRT21"             ,           0x11800A0000EA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30511         {"PIP_STAT3_PRT22"             ,           0x11800A0000EF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30512         {"PIP_STAT3_PRT23"             ,           0x11800A0000F48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30513         {"PIP_STAT3_PRT24"             ,           0x11800A0000F98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30514         {"PIP_STAT3_PRT25"             ,           0x11800A0000FE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30515         {"PIP_STAT3_PRT26"             ,           0x11800A0001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30516         {"PIP_STAT3_PRT27"             ,           0x11800A0001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30517         {"PIP_STAT3_PRT28"             ,           0x11800A00010D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30518         {"PIP_STAT3_PRT29"             ,           0x11800A0001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30519         {"PIP_STAT3_PRT30"             ,           0x11800A0001178ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30520         {"PIP_STAT3_PRT31"             ,           0x11800A00011C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30521         {"PIP_STAT3_PRT32"             ,           0x11800A0001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30522         {"PIP_STAT3_PRT33"             ,           0x11800A0001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30523         {"PIP_STAT3_PRT34"             ,           0x11800A00012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30524         {"PIP_STAT3_PRT35"             ,           0x11800A0001308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
30525         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30526         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30527         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30528         {"PIP_STAT4_PRT3"              ,           0x11800A0000910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30529         {"PIP_STAT4_PRT4"              ,           0x11800A0000960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30530         {"PIP_STAT4_PRT5"              ,           0x11800A00009B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30531         {"PIP_STAT4_PRT6"              ,           0x11800A0000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30532         {"PIP_STAT4_PRT7"              ,           0x11800A0000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30533         {"PIP_STAT4_PRT8"              ,           0x11800A0000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30534         {"PIP_STAT4_PRT9"              ,           0x11800A0000AF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30535         {"PIP_STAT4_PRT10"             ,           0x11800A0000B40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30536         {"PIP_STAT4_PRT11"             ,           0x11800A0000B90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30537         {"PIP_STAT4_PRT12"             ,           0x11800A0000BE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30538         {"PIP_STAT4_PRT13"             ,           0x11800A0000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30539         {"PIP_STAT4_PRT14"             ,           0x11800A0000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30540         {"PIP_STAT4_PRT15"             ,           0x11800A0000CD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30541         {"PIP_STAT4_PRT16"             ,           0x11800A0000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30542         {"PIP_STAT4_PRT17"             ,           0x11800A0000D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30543         {"PIP_STAT4_PRT18"             ,           0x11800A0000DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30544         {"PIP_STAT4_PRT19"             ,           0x11800A0000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30545         {"PIP_STAT4_PRT20"             ,           0x11800A0000E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30546         {"PIP_STAT4_PRT21"             ,           0x11800A0000EB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30547         {"PIP_STAT4_PRT22"             ,           0x11800A0000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30548         {"PIP_STAT4_PRT23"             ,           0x11800A0000F50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30549         {"PIP_STAT4_PRT24"             ,           0x11800A0000FA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30550         {"PIP_STAT4_PRT25"             ,           0x11800A0000FF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30551         {"PIP_STAT4_PRT26"             ,           0x11800A0001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30552         {"PIP_STAT4_PRT27"             ,           0x11800A0001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30553         {"PIP_STAT4_PRT28"             ,           0x11800A00010E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30554         {"PIP_STAT4_PRT29"             ,           0x11800A0001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30555         {"PIP_STAT4_PRT30"             ,           0x11800A0001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30556         {"PIP_STAT4_PRT31"             ,           0x11800A00011D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30557         {"PIP_STAT4_PRT32"             ,           0x11800A0001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30558         {"PIP_STAT4_PRT33"             ,           0x11800A0001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30559         {"PIP_STAT4_PRT34"             ,           0x11800A00012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30560         {"PIP_STAT4_PRT35"             ,           0x11800A0001310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
30561         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30562         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30563         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30564         {"PIP_STAT5_PRT3"              ,           0x11800A0000918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30565         {"PIP_STAT5_PRT4"              ,           0x11800A0000968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30566         {"PIP_STAT5_PRT5"              ,           0x11800A00009B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30567         {"PIP_STAT5_PRT6"              ,           0x11800A0000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30568         {"PIP_STAT5_PRT7"              ,           0x11800A0000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30569         {"PIP_STAT5_PRT8"              ,           0x11800A0000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30570         {"PIP_STAT5_PRT9"              ,           0x11800A0000AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30571         {"PIP_STAT5_PRT10"             ,           0x11800A0000B48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30572         {"PIP_STAT5_PRT11"             ,           0x11800A0000B98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30573         {"PIP_STAT5_PRT12"             ,           0x11800A0000BE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30574         {"PIP_STAT5_PRT13"             ,           0x11800A0000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30575         {"PIP_STAT5_PRT14"             ,           0x11800A0000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30576         {"PIP_STAT5_PRT15"             ,           0x11800A0000CD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30577         {"PIP_STAT5_PRT16"             ,           0x11800A0000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30578         {"PIP_STAT5_PRT17"             ,           0x11800A0000D78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30579         {"PIP_STAT5_PRT18"             ,           0x11800A0000DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30580         {"PIP_STAT5_PRT19"             ,           0x11800A0000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30581         {"PIP_STAT5_PRT20"             ,           0x11800A0000E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30582         {"PIP_STAT5_PRT21"             ,           0x11800A0000EB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30583         {"PIP_STAT5_PRT22"             ,           0x11800A0000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30584         {"PIP_STAT5_PRT23"             ,           0x11800A0000F58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30585         {"PIP_STAT5_PRT24"             ,           0x11800A0000FA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30586         {"PIP_STAT5_PRT25"             ,           0x11800A0000FF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30587         {"PIP_STAT5_PRT26"             ,           0x11800A0001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30588         {"PIP_STAT5_PRT27"             ,           0x11800A0001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30589         {"PIP_STAT5_PRT28"             ,           0x11800A00010E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30590         {"PIP_STAT5_PRT29"             ,           0x11800A0001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30591         {"PIP_STAT5_PRT30"             ,           0x11800A0001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30592         {"PIP_STAT5_PRT31"             ,           0x11800A00011D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30593         {"PIP_STAT5_PRT32"             ,           0x11800A0001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30594         {"PIP_STAT5_PRT33"             ,           0x11800A0001278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30595         {"PIP_STAT5_PRT34"             ,           0x11800A00012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30596         {"PIP_STAT5_PRT35"             ,           0x11800A0001318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
30597         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30598         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30599         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30600         {"PIP_STAT6_PRT3"              ,           0x11800A0000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30601         {"PIP_STAT6_PRT4"              ,           0x11800A0000970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30602         {"PIP_STAT6_PRT5"              ,           0x11800A00009C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30603         {"PIP_STAT6_PRT6"              ,           0x11800A0000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30604         {"PIP_STAT6_PRT7"              ,           0x11800A0000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30605         {"PIP_STAT6_PRT8"              ,           0x11800A0000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30606         {"PIP_STAT6_PRT9"              ,           0x11800A0000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30607         {"PIP_STAT6_PRT10"             ,           0x11800A0000B50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30608         {"PIP_STAT6_PRT11"             ,           0x11800A0000BA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30609         {"PIP_STAT6_PRT12"             ,           0x11800A0000BF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30610         {"PIP_STAT6_PRT13"             ,           0x11800A0000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30611         {"PIP_STAT6_PRT14"             ,           0x11800A0000C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30612         {"PIP_STAT6_PRT15"             ,           0x11800A0000CE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30613         {"PIP_STAT6_PRT16"             ,           0x11800A0000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30614         {"PIP_STAT6_PRT17"             ,           0x11800A0000D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30615         {"PIP_STAT6_PRT18"             ,           0x11800A0000DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30616         {"PIP_STAT6_PRT19"             ,           0x11800A0000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30617         {"PIP_STAT6_PRT20"             ,           0x11800A0000E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30618         {"PIP_STAT6_PRT21"             ,           0x11800A0000EC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30619         {"PIP_STAT6_PRT22"             ,           0x11800A0000F10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30620         {"PIP_STAT6_PRT23"             ,           0x11800A0000F60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30621         {"PIP_STAT6_PRT24"             ,           0x11800A0000FB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30622         {"PIP_STAT6_PRT25"             ,           0x11800A0001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30623         {"PIP_STAT6_PRT26"             ,           0x11800A0001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30624         {"PIP_STAT6_PRT27"             ,           0x11800A00010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30625         {"PIP_STAT6_PRT28"             ,           0x11800A00010F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30626         {"PIP_STAT6_PRT29"             ,           0x11800A0001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30627         {"PIP_STAT6_PRT30"             ,           0x11800A0001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30628         {"PIP_STAT6_PRT31"             ,           0x11800A00011E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30629         {"PIP_STAT6_PRT32"             ,           0x11800A0001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30630         {"PIP_STAT6_PRT33"             ,           0x11800A0001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30631         {"PIP_STAT6_PRT34"             ,           0x11800A00012D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30632         {"PIP_STAT6_PRT35"             ,           0x11800A0001320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
30633         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30634         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30635         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30636         {"PIP_STAT7_PRT3"              ,           0x11800A0000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30637         {"PIP_STAT7_PRT4"              ,           0x11800A0000978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30638         {"PIP_STAT7_PRT5"              ,           0x11800A00009C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30639         {"PIP_STAT7_PRT6"              ,           0x11800A0000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30640         {"PIP_STAT7_PRT7"              ,           0x11800A0000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30641         {"PIP_STAT7_PRT8"              ,           0x11800A0000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30642         {"PIP_STAT7_PRT9"              ,           0x11800A0000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30643         {"PIP_STAT7_PRT10"             ,           0x11800A0000B58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30644         {"PIP_STAT7_PRT11"             ,           0x11800A0000BA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30645         {"PIP_STAT7_PRT12"             ,           0x11800A0000BF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30646         {"PIP_STAT7_PRT13"             ,           0x11800A0000C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30647         {"PIP_STAT7_PRT14"             ,           0x11800A0000C98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30648         {"PIP_STAT7_PRT15"             ,           0x11800A0000CE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30649         {"PIP_STAT7_PRT16"             ,           0x11800A0000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30650         {"PIP_STAT7_PRT17"             ,           0x11800A0000D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30651         {"PIP_STAT7_PRT18"             ,           0x11800A0000DD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30652         {"PIP_STAT7_PRT19"             ,           0x11800A0000E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30653         {"PIP_STAT7_PRT20"             ,           0x11800A0000E78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30654         {"PIP_STAT7_PRT21"             ,           0x11800A0000EC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30655         {"PIP_STAT7_PRT22"             ,           0x11800A0000F18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30656         {"PIP_STAT7_PRT23"             ,           0x11800A0000F68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30657         {"PIP_STAT7_PRT24"             ,           0x11800A0000FB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30658         {"PIP_STAT7_PRT25"             ,           0x11800A0001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30659         {"PIP_STAT7_PRT26"             ,           0x11800A0001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30660         {"PIP_STAT7_PRT27"             ,           0x11800A00010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30661         {"PIP_STAT7_PRT28"             ,           0x11800A00010F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30662         {"PIP_STAT7_PRT29"             ,           0x11800A0001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30663         {"PIP_STAT7_PRT30"             ,           0x11800A0001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30664         {"PIP_STAT7_PRT31"             ,           0x11800A00011E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30665         {"PIP_STAT7_PRT32"             ,           0x11800A0001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30666         {"PIP_STAT7_PRT33"             ,           0x11800A0001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30667         {"PIP_STAT7_PRT34"             ,           0x11800A00012D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30668         {"PIP_STAT7_PRT35"             ,           0x11800A0001328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
30669         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30670         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30671         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30672         {"PIP_STAT8_PRT3"              ,           0x11800A0000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30673         {"PIP_STAT8_PRT4"              ,           0x11800A0000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30674         {"PIP_STAT8_PRT5"              ,           0x11800A00009D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30675         {"PIP_STAT8_PRT6"              ,           0x11800A0000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30676         {"PIP_STAT8_PRT7"              ,           0x11800A0000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30677         {"PIP_STAT8_PRT8"              ,           0x11800A0000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30678         {"PIP_STAT8_PRT9"              ,           0x11800A0000B10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30679         {"PIP_STAT8_PRT10"             ,           0x11800A0000B60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30680         {"PIP_STAT8_PRT11"             ,           0x11800A0000BB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30681         {"PIP_STAT8_PRT12"             ,           0x11800A0000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30682         {"PIP_STAT8_PRT13"             ,           0x11800A0000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30683         {"PIP_STAT8_PRT14"             ,           0x11800A0000CA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30684         {"PIP_STAT8_PRT15"             ,           0x11800A0000CF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30685         {"PIP_STAT8_PRT16"             ,           0x11800A0000D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30686         {"PIP_STAT8_PRT17"             ,           0x11800A0000D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30687         {"PIP_STAT8_PRT18"             ,           0x11800A0000DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30688         {"PIP_STAT8_PRT19"             ,           0x11800A0000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30689         {"PIP_STAT8_PRT20"             ,           0x11800A0000E80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30690         {"PIP_STAT8_PRT21"             ,           0x11800A0000ED0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30691         {"PIP_STAT8_PRT22"             ,           0x11800A0000F20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30692         {"PIP_STAT8_PRT23"             ,           0x11800A0000F70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30693         {"PIP_STAT8_PRT24"             ,           0x11800A0000FC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30694         {"PIP_STAT8_PRT25"             ,           0x11800A0001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30695         {"PIP_STAT8_PRT26"             ,           0x11800A0001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30696         {"PIP_STAT8_PRT27"             ,           0x11800A00010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30697         {"PIP_STAT8_PRT28"             ,           0x11800A0001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30698         {"PIP_STAT8_PRT29"             ,           0x11800A0001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30699         {"PIP_STAT8_PRT30"             ,           0x11800A00011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30700         {"PIP_STAT8_PRT31"             ,           0x11800A00011F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30701         {"PIP_STAT8_PRT32"             ,           0x11800A0001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30702         {"PIP_STAT8_PRT33"             ,           0x11800A0001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30703         {"PIP_STAT8_PRT34"             ,           0x11800A00012E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30704         {"PIP_STAT8_PRT35"             ,           0x11800A0001330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
30705         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30706         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30707         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30708         {"PIP_STAT9_PRT3"              ,           0x11800A0000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30709         {"PIP_STAT9_PRT4"              ,           0x11800A0000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30710         {"PIP_STAT9_PRT5"              ,           0x11800A00009D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30711         {"PIP_STAT9_PRT6"              ,           0x11800A0000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30712         {"PIP_STAT9_PRT7"              ,           0x11800A0000A78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30713         {"PIP_STAT9_PRT8"              ,           0x11800A0000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30714         {"PIP_STAT9_PRT9"              ,           0x11800A0000B18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30715         {"PIP_STAT9_PRT10"             ,           0x11800A0000B68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30716         {"PIP_STAT9_PRT11"             ,           0x11800A0000BB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30717         {"PIP_STAT9_PRT12"             ,           0x11800A0000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30718         {"PIP_STAT9_PRT13"             ,           0x11800A0000C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30719         {"PIP_STAT9_PRT14"             ,           0x11800A0000CA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30720         {"PIP_STAT9_PRT15"             ,           0x11800A0000CF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30721         {"PIP_STAT9_PRT16"             ,           0x11800A0000D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30722         {"PIP_STAT9_PRT17"             ,           0x11800A0000D98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30723         {"PIP_STAT9_PRT18"             ,           0x11800A0000DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30724         {"PIP_STAT9_PRT19"             ,           0x11800A0000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30725         {"PIP_STAT9_PRT20"             ,           0x11800A0000E88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30726         {"PIP_STAT9_PRT21"             ,           0x11800A0000ED8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30727         {"PIP_STAT9_PRT22"             ,           0x11800A0000F28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30728         {"PIP_STAT9_PRT23"             ,           0x11800A0000F78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30729         {"PIP_STAT9_PRT24"             ,           0x11800A0000FC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30730         {"PIP_STAT9_PRT25"             ,           0x11800A0001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30731         {"PIP_STAT9_PRT26"             ,           0x11800A0001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30732         {"PIP_STAT9_PRT27"             ,           0x11800A00010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30733         {"PIP_STAT9_PRT28"             ,           0x11800A0001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30734         {"PIP_STAT9_PRT29"             ,           0x11800A0001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30735         {"PIP_STAT9_PRT30"             ,           0x11800A00011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30736         {"PIP_STAT9_PRT31"             ,           0x11800A00011F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30737         {"PIP_STAT9_PRT32"             ,           0x11800A0001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30738         {"PIP_STAT9_PRT33"             ,           0x11800A0001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30739         {"PIP_STAT9_PRT34"             ,           0x11800A00012E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30740         {"PIP_STAT9_PRT35"             ,           0x11800A0001338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
30741         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     468},
30742         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30743         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30744         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30745         {"PIP_STAT_INB_ERRS3"          ,           0x11800A0001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30746         {"PIP_STAT_INB_ERRS4"          ,           0x11800A0001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30747         {"PIP_STAT_INB_ERRS5"          ,           0x11800A0001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30748         {"PIP_STAT_INB_ERRS6"          ,           0x11800A0001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30749         {"PIP_STAT_INB_ERRS7"          ,           0x11800A0001AF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30750         {"PIP_STAT_INB_ERRS8"          ,           0x11800A0001B10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30751         {"PIP_STAT_INB_ERRS9"          ,           0x11800A0001B30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30752         {"PIP_STAT_INB_ERRS10"         ,           0x11800A0001B50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30753         {"PIP_STAT_INB_ERRS11"         ,           0x11800A0001B70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30754         {"PIP_STAT_INB_ERRS12"         ,           0x11800A0001B90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30755         {"PIP_STAT_INB_ERRS13"         ,           0x11800A0001BB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30756         {"PIP_STAT_INB_ERRS14"         ,           0x11800A0001BD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30757         {"PIP_STAT_INB_ERRS15"         ,           0x11800A0001BF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30758         {"PIP_STAT_INB_ERRS16"         ,           0x11800A0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30759         {"PIP_STAT_INB_ERRS17"         ,           0x11800A0001C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30760         {"PIP_STAT_INB_ERRS18"         ,           0x11800A0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30761         {"PIP_STAT_INB_ERRS19"         ,           0x11800A0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30762         {"PIP_STAT_INB_ERRS20"         ,           0x11800A0001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30763         {"PIP_STAT_INB_ERRS21"         ,           0x11800A0001CB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30764         {"PIP_STAT_INB_ERRS22"         ,           0x11800A0001CD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30765         {"PIP_STAT_INB_ERRS23"         ,           0x11800A0001CF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30766         {"PIP_STAT_INB_ERRS24"         ,           0x11800A0001D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30767         {"PIP_STAT_INB_ERRS25"         ,           0x11800A0001D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30768         {"PIP_STAT_INB_ERRS26"         ,           0x11800A0001D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30769         {"PIP_STAT_INB_ERRS27"         ,           0x11800A0001D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30770         {"PIP_STAT_INB_ERRS28"         ,           0x11800A0001D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30771         {"PIP_STAT_INB_ERRS29"         ,           0x11800A0001DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30772         {"PIP_STAT_INB_ERRS30"         ,           0x11800A0001DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30773         {"PIP_STAT_INB_ERRS31"         ,           0x11800A0001DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30774         {"PIP_STAT_INB_ERRS32"         ,           0x11800A0001E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30775         {"PIP_STAT_INB_ERRS33"         ,           0x11800A0001E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30776         {"PIP_STAT_INB_ERRS34"         ,           0x11800A0001E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30777         {"PIP_STAT_INB_ERRS35"         ,           0x11800A0001E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     469},
30778         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30779         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30780         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30781         {"PIP_STAT_INB_OCTS3"          ,           0x11800A0001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30782         {"PIP_STAT_INB_OCTS4"          ,           0x11800A0001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30783         {"PIP_STAT_INB_OCTS5"          ,           0x11800A0001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30784         {"PIP_STAT_INB_OCTS6"          ,           0x11800A0001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30785         {"PIP_STAT_INB_OCTS7"          ,           0x11800A0001AE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30786         {"PIP_STAT_INB_OCTS8"          ,           0x11800A0001B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30787         {"PIP_STAT_INB_OCTS9"          ,           0x11800A0001B28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30788         {"PIP_STAT_INB_OCTS10"         ,           0x11800A0001B48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30789         {"PIP_STAT_INB_OCTS11"         ,           0x11800A0001B68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30790         {"PIP_STAT_INB_OCTS12"         ,           0x11800A0001B88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30791         {"PIP_STAT_INB_OCTS13"         ,           0x11800A0001BA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30792         {"PIP_STAT_INB_OCTS14"         ,           0x11800A0001BC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30793         {"PIP_STAT_INB_OCTS15"         ,           0x11800A0001BE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30794         {"PIP_STAT_INB_OCTS16"         ,           0x11800A0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30795         {"PIP_STAT_INB_OCTS17"         ,           0x11800A0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30796         {"PIP_STAT_INB_OCTS18"         ,           0x11800A0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30797         {"PIP_STAT_INB_OCTS19"         ,           0x11800A0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30798         {"PIP_STAT_INB_OCTS20"         ,           0x11800A0001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30799         {"PIP_STAT_INB_OCTS21"         ,           0x11800A0001CA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30800         {"PIP_STAT_INB_OCTS22"         ,           0x11800A0001CC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30801         {"PIP_STAT_INB_OCTS23"         ,           0x11800A0001CE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30802         {"PIP_STAT_INB_OCTS24"         ,           0x11800A0001D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30803         {"PIP_STAT_INB_OCTS25"         ,           0x11800A0001D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30804         {"PIP_STAT_INB_OCTS26"         ,           0x11800A0001D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30805         {"PIP_STAT_INB_OCTS27"         ,           0x11800A0001D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30806         {"PIP_STAT_INB_OCTS28"         ,           0x11800A0001D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30807         {"PIP_STAT_INB_OCTS29"         ,           0x11800A0001DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30808         {"PIP_STAT_INB_OCTS30"         ,           0x11800A0001DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30809         {"PIP_STAT_INB_OCTS31"         ,           0x11800A0001DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30810         {"PIP_STAT_INB_OCTS32"         ,           0x11800A0001E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30811         {"PIP_STAT_INB_OCTS33"         ,           0x11800A0001E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30812         {"PIP_STAT_INB_OCTS34"         ,           0x11800A0001E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30813         {"PIP_STAT_INB_OCTS35"         ,           0x11800A0001E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     470},
30814         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30815         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30816         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30817         {"PIP_STAT_INB_PKTS3"          ,           0x11800A0001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30818         {"PIP_STAT_INB_PKTS4"          ,           0x11800A0001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30819         {"PIP_STAT_INB_PKTS5"          ,           0x11800A0001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30820         {"PIP_STAT_INB_PKTS6"          ,           0x11800A0001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30821         {"PIP_STAT_INB_PKTS7"          ,           0x11800A0001AE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30822         {"PIP_STAT_INB_PKTS8"          ,           0x11800A0001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30823         {"PIP_STAT_INB_PKTS9"          ,           0x11800A0001B20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30824         {"PIP_STAT_INB_PKTS10"         ,           0x11800A0001B40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30825         {"PIP_STAT_INB_PKTS11"         ,           0x11800A0001B60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30826         {"PIP_STAT_INB_PKTS12"         ,           0x11800A0001B80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30827         {"PIP_STAT_INB_PKTS13"         ,           0x11800A0001BA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30828         {"PIP_STAT_INB_PKTS14"         ,           0x11800A0001BC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30829         {"PIP_STAT_INB_PKTS15"         ,           0x11800A0001BE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30830         {"PIP_STAT_INB_PKTS16"         ,           0x11800A0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30831         {"PIP_STAT_INB_PKTS17"         ,           0x11800A0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30832         {"PIP_STAT_INB_PKTS18"         ,           0x11800A0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30833         {"PIP_STAT_INB_PKTS19"         ,           0x11800A0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30834         {"PIP_STAT_INB_PKTS20"         ,           0x11800A0001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30835         {"PIP_STAT_INB_PKTS21"         ,           0x11800A0001CA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30836         {"PIP_STAT_INB_PKTS22"         ,           0x11800A0001CC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30837         {"PIP_STAT_INB_PKTS23"         ,           0x11800A0001CE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30838         {"PIP_STAT_INB_PKTS24"         ,           0x11800A0001D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30839         {"PIP_STAT_INB_PKTS25"         ,           0x11800A0001D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30840         {"PIP_STAT_INB_PKTS26"         ,           0x11800A0001D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30841         {"PIP_STAT_INB_PKTS27"         ,           0x11800A0001D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30842         {"PIP_STAT_INB_PKTS28"         ,           0x11800A0001D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30843         {"PIP_STAT_INB_PKTS29"         ,           0x11800A0001DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30844         {"PIP_STAT_INB_PKTS30"         ,           0x11800A0001DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30845         {"PIP_STAT_INB_PKTS31"         ,           0x11800A0001DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30846         {"PIP_STAT_INB_PKTS32"         ,           0x11800A0001E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30847         {"PIP_STAT_INB_PKTS33"         ,           0x11800A0001E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30848         {"PIP_STAT_INB_PKTS34"         ,           0x11800A0001E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30849         {"PIP_STAT_INB_PKTS35"         ,           0x11800A0001E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     471},
30850         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30851         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30852         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30853         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30854         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30855         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30856         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30857         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30858         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30859         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30860         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30861         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30862         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30863         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30864         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30865         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30866         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30867         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30868         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30869         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30870         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30871         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30872         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30873         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30874         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30875         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30876         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30877         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30878         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30879         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30880         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30881         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30882         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30883         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30884         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30885         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30886         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30887         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30888         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30889         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30890         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30891         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30892         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30893         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30894         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30895         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30896         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30897         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30898         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30899         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30900         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30901         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30902         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30903         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30904         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30905         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30906         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30907         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30908         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30909         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30910         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30911         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30912         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30913         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     472},
30914         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     473},
30915         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     474},
30916         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     475},
30917         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     476},
30918         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     477},
30919         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     478},
30920         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     479},
30921         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     480},
30922         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     481},
30923         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     482},
30924         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     483},
30925         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     484},
30926         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     485},
30927         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     486},
30928         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     487},
30929         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     488},
30930         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     489},
30931         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     490},
30932         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     491},
30933         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     492},
30934         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     493},
30935         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     494},
30936         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     495},
30937         {"PKO_REG_CRC_CTL0"            ,           0x1180050000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     496},
30938         {"PKO_REG_CRC_CTL1"            ,           0x1180050000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     496},
30939         {"PKO_REG_CRC_ENABLE"          ,           0x1180050000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     497},
30940         {"PKO_REG_CRC_IV0"             ,           0x1180050000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     498},
30941         {"PKO_REG_CRC_IV1"             ,           0x1180050000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     498},
30942         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     499},
30943         {"PKO_REG_DEBUG1"              ,           0x11800500000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     500},
30944         {"PKO_REG_DEBUG2"              ,           0x11800500000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     501},
30945         {"PKO_REG_DEBUG3"              ,           0x11800500000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     502},
30946         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     503},
30947         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     504},
30948         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     505},
30949         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     506},
30950         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     507},
30951         {"PKO_REG_QUEUE_PTRS1"         ,           0x1180050000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     508},
30952         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     509},
30953         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     510},
30954         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     511},
30955         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     512},
30956         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     513},
30957         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
30958         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
30959         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
30960         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
30961         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
30962         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
30963         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
30964         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     514},
30965         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     515},
30966         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     516},
30967         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     517},
30968         {"POW_PF_RST_MSK"              ,           0x1670000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     518},
30969         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30970         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30971         {"POW_PP_GRP_MSK2"             ,           0x1670000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30972         {"POW_PP_GRP_MSK3"             ,           0x1670000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30973         {"POW_PP_GRP_MSK4"             ,           0x1670000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30974         {"POW_PP_GRP_MSK5"             ,           0x1670000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30975         {"POW_PP_GRP_MSK6"             ,           0x1670000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30976         {"POW_PP_GRP_MSK7"             ,           0x1670000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30977         {"POW_PP_GRP_MSK8"             ,           0x1670000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30978         {"POW_PP_GRP_MSK9"             ,           0x1670000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30979         {"POW_PP_GRP_MSK10"            ,           0x1670000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30980         {"POW_PP_GRP_MSK11"            ,           0x1670000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30981         {"POW_PP_GRP_MSK12"            ,           0x1670000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30982         {"POW_PP_GRP_MSK13"            ,           0x1670000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30983         {"POW_PP_GRP_MSK14"            ,           0x1670000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30984         {"POW_PP_GRP_MSK15"            ,           0x1670000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     519},
30985         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     520},
30986         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     520},
30987         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     520},
30988         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     520},
30989         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     520},
30990         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     520},
30991         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     520},
30992         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     520},
30993         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     521},
30994         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     521},
30995         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     521},
30996         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     521},
30997         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     521},
30998         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     521},
30999         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     521},
31000         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     521},
31001         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     522},
31002         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     523},
31003         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     524},
31004         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     524},
31005         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     524},
31006         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     524},
31007         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     524},
31008         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     524},
31009         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     524},
31010         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     524},
31011         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     525},
31012         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31013         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31014         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31015         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31016         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31017         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31018         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31019         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31020         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31021         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31022         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31023         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31024         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31025         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31026         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31027         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     526},
31028         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     527},
31029         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31030         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31031         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31032         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31033         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31034         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31035         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31036         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31037         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31038         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31039         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31040         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31041         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31042         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31043         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31044         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     528},
31045         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31046         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31047         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31048         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31049         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31050         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31051         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31052         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31053         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31054         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31055         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31056         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31057         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31058         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31059         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31060         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     529},
31061         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     530},
31062         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     531},
31063         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     532},
31064         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     533},
31065         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     534},
31066         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     535},
31067         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     536},
31068         {"SPX0_BCKPRS_CNT"             ,           0x1180090000340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     537},
31069         {"SPX1_BCKPRS_CNT"             ,           0x1180098000340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     537},
31070         {"SPX0_BIST_STAT"              ,           0x11800900007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     538},
31071         {"SPX1_BIST_STAT"              ,           0x11800980007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     538},
31072         {"SPX0_CLK_CTL"                ,           0x1180090000348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     539},
31073         {"SPX1_CLK_CTL"                ,           0x1180098000348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     539},
31074         {"SPX0_CLK_STAT"               ,           0x1180090000350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     540},
31075         {"SPX1_CLK_STAT"               ,           0x1180098000350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     540},
31076         {"SPX0_DBG_DESKEW_CTL"         ,           0x1180090000368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     541},
31077         {"SPX1_DBG_DESKEW_CTL"         ,           0x1180098000368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     541},
31078         {"SPX0_DBG_DESKEW_STATE"       ,           0x1180090000370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     542},
31079         {"SPX1_DBG_DESKEW_STATE"       ,           0x1180098000370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     542},
31080         {"SPX0_DRV_CTL"                ,           0x1180090000358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     543},
31081         {"SPX1_DRV_CTL"                ,           0x1180098000358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     543},
31082         {"SPX0_ERR_CTL"                ,           0x1180090000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     544},
31083         {"SPX1_ERR_CTL"                ,           0x1180098000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     544},
31084         {"SPX0_INT_DAT"                ,           0x1180090000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
31085         {"SPX1_INT_DAT"                ,           0x1180098000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     545},
31086         {"SPX0_INT_MSK"                ,           0x1180090000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     546},
31087         {"SPX1_INT_MSK"                ,           0x1180098000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     546},
31088         {"SPX0_INT_REG"                ,           0x1180090000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     547},
31089         {"SPX1_INT_REG"                ,           0x1180098000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     547},
31090         {"SPX0_INT_SYNC"               ,           0x1180090000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     548},
31091         {"SPX1_INT_SYNC"               ,           0x1180098000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     548},
31092         {"SPX0_TPA_ACC"                ,           0x1180090000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     549},
31093         {"SPX1_TPA_ACC"                ,           0x1180098000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     549},
31094         {"SPX0_TPA_MAX"                ,           0x1180090000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     550},
31095         {"SPX1_TPA_MAX"                ,           0x1180098000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     550},
31096         {"SPX0_TPA_SEL"                ,           0x1180090000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     551},
31097         {"SPX1_TPA_SEL"                ,           0x1180098000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     551},
31098         {"SPX0_TRN4_CTL"               ,           0x1180090000360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     552},
31099         {"SPX1_TRN4_CTL"               ,           0x1180098000360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     552},
31100         {"SRX0_COM_CTL"                ,           0x1180090000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     553},
31101         {"SRX1_COM_CTL"                ,           0x1180098000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     553},
31102         {"SRX0_IGN_RX_FULL"            ,           0x1180090000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     554},
31103         {"SRX1_IGN_RX_FULL"            ,           0x1180098000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     554},
31104         {"SRX0_SPI4_CAL000"            ,           0x1180090000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31105         {"SRX0_SPI4_CAL001"            ,           0x1180090000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31106         {"SRX0_SPI4_CAL002"            ,           0x1180090000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31107         {"SRX0_SPI4_CAL003"            ,           0x1180090000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31108         {"SRX0_SPI4_CAL004"            ,           0x1180090000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31109         {"SRX0_SPI4_CAL005"            ,           0x1180090000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31110         {"SRX0_SPI4_CAL006"            ,           0x1180090000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31111         {"SRX0_SPI4_CAL007"            ,           0x1180090000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31112         {"SRX0_SPI4_CAL008"            ,           0x1180090000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31113         {"SRX0_SPI4_CAL009"            ,           0x1180090000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31114         {"SRX0_SPI4_CAL010"            ,           0x1180090000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31115         {"SRX0_SPI4_CAL011"            ,           0x1180090000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31116         {"SRX0_SPI4_CAL012"            ,           0x1180090000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31117         {"SRX0_SPI4_CAL013"            ,           0x1180090000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31118         {"SRX0_SPI4_CAL014"            ,           0x1180090000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31119         {"SRX0_SPI4_CAL015"            ,           0x1180090000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31120         {"SRX0_SPI4_CAL016"            ,           0x1180090000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31121         {"SRX0_SPI4_CAL017"            ,           0x1180090000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31122         {"SRX0_SPI4_CAL018"            ,           0x1180090000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31123         {"SRX0_SPI4_CAL019"            ,           0x1180090000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31124         {"SRX0_SPI4_CAL020"            ,           0x11800900000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31125         {"SRX0_SPI4_CAL021"            ,           0x11800900000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31126         {"SRX0_SPI4_CAL022"            ,           0x11800900000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31127         {"SRX0_SPI4_CAL023"            ,           0x11800900000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31128         {"SRX0_SPI4_CAL024"            ,           0x11800900000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31129         {"SRX0_SPI4_CAL025"            ,           0x11800900000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31130         {"SRX0_SPI4_CAL026"            ,           0x11800900000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31131         {"SRX0_SPI4_CAL027"            ,           0x11800900000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31132         {"SRX0_SPI4_CAL028"            ,           0x11800900000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31133         {"SRX0_SPI4_CAL029"            ,           0x11800900000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31134         {"SRX0_SPI4_CAL030"            ,           0x11800900000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31135         {"SRX0_SPI4_CAL031"            ,           0x11800900000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31136         {"SRX1_SPI4_CAL000"            ,           0x1180098000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31137         {"SRX1_SPI4_CAL001"            ,           0x1180098000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31138         {"SRX1_SPI4_CAL002"            ,           0x1180098000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31139         {"SRX1_SPI4_CAL003"            ,           0x1180098000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31140         {"SRX1_SPI4_CAL004"            ,           0x1180098000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31141         {"SRX1_SPI4_CAL005"            ,           0x1180098000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31142         {"SRX1_SPI4_CAL006"            ,           0x1180098000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31143         {"SRX1_SPI4_CAL007"            ,           0x1180098000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31144         {"SRX1_SPI4_CAL008"            ,           0x1180098000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31145         {"SRX1_SPI4_CAL009"            ,           0x1180098000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31146         {"SRX1_SPI4_CAL010"            ,           0x1180098000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31147         {"SRX1_SPI4_CAL011"            ,           0x1180098000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31148         {"SRX1_SPI4_CAL012"            ,           0x1180098000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31149         {"SRX1_SPI4_CAL013"            ,           0x1180098000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31150         {"SRX1_SPI4_CAL014"            ,           0x1180098000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31151         {"SRX1_SPI4_CAL015"            ,           0x1180098000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31152         {"SRX1_SPI4_CAL016"            ,           0x1180098000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31153         {"SRX1_SPI4_CAL017"            ,           0x1180098000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31154         {"SRX1_SPI4_CAL018"            ,           0x1180098000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31155         {"SRX1_SPI4_CAL019"            ,           0x1180098000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31156         {"SRX1_SPI4_CAL020"            ,           0x11800980000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31157         {"SRX1_SPI4_CAL021"            ,           0x11800980000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31158         {"SRX1_SPI4_CAL022"            ,           0x11800980000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31159         {"SRX1_SPI4_CAL023"            ,           0x11800980000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31160         {"SRX1_SPI4_CAL024"            ,           0x11800980000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31161         {"SRX1_SPI4_CAL025"            ,           0x11800980000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31162         {"SRX1_SPI4_CAL026"            ,           0x11800980000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31163         {"SRX1_SPI4_CAL027"            ,           0x11800980000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31164         {"SRX1_SPI4_CAL028"            ,           0x11800980000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31165         {"SRX1_SPI4_CAL029"            ,           0x11800980000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31166         {"SRX1_SPI4_CAL030"            ,           0x11800980000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31167         {"SRX1_SPI4_CAL031"            ,           0x11800980000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     555},
31168         {"SRX0_SPI4_STAT"              ,           0x1180090000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     556},
31169         {"SRX1_SPI4_STAT"              ,           0x1180098000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     556},
31170         {"SRX0_SW_TICK_CTL"            ,           0x1180090000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     557},
31171         {"SRX1_SW_TICK_CTL"            ,           0x1180098000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     557},
31172         {"SRX0_SW_TICK_DAT"            ,           0x1180090000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
31173         {"SRX1_SW_TICK_DAT"            ,           0x1180098000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
31174         {"STX0_ARB_CTL"                ,           0x1180090000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     559},
31175         {"STX1_ARB_CTL"                ,           0x1180098000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     559},
31176         {"STX0_BCKPRS_CNT"             ,           0x1180090000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     560},
31177         {"STX1_BCKPRS_CNT"             ,           0x1180098000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     560},
31178         {"STX0_COM_CTL"                ,           0x1180090000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     561},
31179         {"STX1_COM_CTL"                ,           0x1180098000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     561},
31180         {"STX0_DIP_CNT"                ,           0x1180090000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     562},
31181         {"STX1_DIP_CNT"                ,           0x1180098000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     562},
31182         {"STX0_IGN_CAL"                ,           0x1180090000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     563},
31183         {"STX1_IGN_CAL"                ,           0x1180098000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     563},
31184         {"STX0_INT_MSK"                ,           0x11800900006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     564},
31185         {"STX1_INT_MSK"                ,           0x11800980006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     564},
31186         {"STX0_INT_REG"                ,           0x1180090000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     565},
31187         {"STX1_INT_REG"                ,           0x1180098000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     565},
31188         {"STX0_INT_SYNC"               ,           0x11800900006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     566},
31189         {"STX1_INT_SYNC"               ,           0x11800980006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     566},
31190         {"STX0_MIN_BST"                ,           0x1180090000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     567},
31191         {"STX1_MIN_BST"                ,           0x1180098000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     567},
31192         {"STX0_SPI4_CAL000"            ,           0x1180090000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31193         {"STX0_SPI4_CAL001"            ,           0x1180090000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31194         {"STX0_SPI4_CAL002"            ,           0x1180090000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31195         {"STX0_SPI4_CAL003"            ,           0x1180090000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31196         {"STX0_SPI4_CAL004"            ,           0x1180090000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31197         {"STX0_SPI4_CAL005"            ,           0x1180090000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31198         {"STX0_SPI4_CAL006"            ,           0x1180090000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31199         {"STX0_SPI4_CAL007"            ,           0x1180090000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31200         {"STX0_SPI4_CAL008"            ,           0x1180090000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31201         {"STX0_SPI4_CAL009"            ,           0x1180090000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31202         {"STX0_SPI4_CAL010"            ,           0x1180090000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31203         {"STX0_SPI4_CAL011"            ,           0x1180090000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31204         {"STX0_SPI4_CAL012"            ,           0x1180090000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31205         {"STX0_SPI4_CAL013"            ,           0x1180090000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31206         {"STX0_SPI4_CAL014"            ,           0x1180090000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31207         {"STX0_SPI4_CAL015"            ,           0x1180090000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31208         {"STX0_SPI4_CAL016"            ,           0x1180090000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31209         {"STX0_SPI4_CAL017"            ,           0x1180090000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31210         {"STX0_SPI4_CAL018"            ,           0x1180090000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31211         {"STX0_SPI4_CAL019"            ,           0x1180090000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31212         {"STX0_SPI4_CAL020"            ,           0x11800900004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31213         {"STX0_SPI4_CAL021"            ,           0x11800900004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31214         {"STX0_SPI4_CAL022"            ,           0x11800900004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31215         {"STX0_SPI4_CAL023"            ,           0x11800900004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31216         {"STX0_SPI4_CAL024"            ,           0x11800900004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31217         {"STX0_SPI4_CAL025"            ,           0x11800900004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31218         {"STX0_SPI4_CAL026"            ,           0x11800900004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31219         {"STX0_SPI4_CAL027"            ,           0x11800900004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31220         {"STX0_SPI4_CAL028"            ,           0x11800900004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31221         {"STX0_SPI4_CAL029"            ,           0x11800900004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31222         {"STX0_SPI4_CAL030"            ,           0x11800900004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31223         {"STX0_SPI4_CAL031"            ,           0x11800900004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31224         {"STX1_SPI4_CAL000"            ,           0x1180098000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31225         {"STX1_SPI4_CAL001"            ,           0x1180098000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31226         {"STX1_SPI4_CAL002"            ,           0x1180098000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31227         {"STX1_SPI4_CAL003"            ,           0x1180098000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31228         {"STX1_SPI4_CAL004"            ,           0x1180098000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31229         {"STX1_SPI4_CAL005"            ,           0x1180098000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31230         {"STX1_SPI4_CAL006"            ,           0x1180098000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31231         {"STX1_SPI4_CAL007"            ,           0x1180098000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31232         {"STX1_SPI4_CAL008"            ,           0x1180098000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31233         {"STX1_SPI4_CAL009"            ,           0x1180098000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31234         {"STX1_SPI4_CAL010"            ,           0x1180098000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31235         {"STX1_SPI4_CAL011"            ,           0x1180098000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31236         {"STX1_SPI4_CAL012"            ,           0x1180098000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31237         {"STX1_SPI4_CAL013"            ,           0x1180098000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31238         {"STX1_SPI4_CAL014"            ,           0x1180098000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31239         {"STX1_SPI4_CAL015"            ,           0x1180098000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31240         {"STX1_SPI4_CAL016"            ,           0x1180098000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31241         {"STX1_SPI4_CAL017"            ,           0x1180098000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31242         {"STX1_SPI4_CAL018"            ,           0x1180098000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31243         {"STX1_SPI4_CAL019"            ,           0x1180098000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31244         {"STX1_SPI4_CAL020"            ,           0x11800980004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31245         {"STX1_SPI4_CAL021"            ,           0x11800980004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31246         {"STX1_SPI4_CAL022"            ,           0x11800980004B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31247         {"STX1_SPI4_CAL023"            ,           0x11800980004B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31248         {"STX1_SPI4_CAL024"            ,           0x11800980004C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31249         {"STX1_SPI4_CAL025"            ,           0x11800980004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31250         {"STX1_SPI4_CAL026"            ,           0x11800980004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31251         {"STX1_SPI4_CAL027"            ,           0x11800980004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31252         {"STX1_SPI4_CAL028"            ,           0x11800980004E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31253         {"STX1_SPI4_CAL029"            ,           0x11800980004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31254         {"STX1_SPI4_CAL030"            ,           0x11800980004F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31255         {"STX1_SPI4_CAL031"            ,           0x11800980004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     568},
31256         {"STX0_SPI4_DAT"               ,           0x1180090000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     569},
31257         {"STX1_SPI4_DAT"               ,           0x1180098000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     569},
31258         {"STX0_SPI4_STAT"              ,           0x1180090000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     570},
31259         {"STX1_SPI4_STAT"              ,           0x1180098000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     570},
31260         {"STX0_STAT_BYTES_HI"          ,           0x1180090000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     571},
31261         {"STX1_STAT_BYTES_HI"          ,           0x1180098000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     571},
31262         {"STX0_STAT_BYTES_LO"          ,           0x1180090000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     572},
31263         {"STX1_STAT_BYTES_LO"          ,           0x1180098000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     572},
31264         {"STX0_STAT_CTL"               ,           0x1180090000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     573},
31265         {"STX1_STAT_CTL"               ,           0x1180098000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     573},
31266         {"STX0_STAT_PKT_XMT"           ,           0x1180090000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     574},
31267         {"STX1_STAT_PKT_XMT"           ,           0x1180098000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     574},
31268         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     575},
31269         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     576},
31270         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     577},
31271         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     578},
31272         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     579},
31273         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     580},
31274         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     581},
31275         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     582},
31276         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     583},
31277         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     584},
31278         {"TRA_BIST_STATUS"             ,           0x11800A8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     585},
31279         {"TRA_CTL"                     ,           0x11800A8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     586},
31280         {"TRA_CYCLES_SINCE"            ,           0x11800A8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     587},
31281         {"TRA_CYCLES_SINCE1"           ,           0x11800A8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     588},
31282         {"TRA_FILT_ADR_ADR"            ,           0x11800A8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     589},
31283         {"TRA_FILT_ADR_MSK"            ,           0x11800A8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     590},
31284         {"TRA_FILT_CMD"                ,           0x11800A8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     591},
31285         {"TRA_FILT_DID"                ,           0x11800A8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     592},
31286         {"TRA_FILT_SID"                ,           0x11800A8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     593},
31287         {"TRA_INT_STATUS"              ,           0x11800A8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     594},
31288         {"TRA_READ_DAT"                ,           0x11800A8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     595},
31289         {"TRA_TRIG0_ADR_ADR"           ,           0x11800A8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     596},
31290         {"TRA_TRIG0_ADR_MSK"           ,           0x11800A80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     597},
31291         {"TRA_TRIG0_CMD"               ,           0x11800A8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     598},
31292         {"TRA_TRIG0_DID"               ,           0x11800A8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     599},
31293         {"TRA_TRIG0_SID"               ,           0x11800A8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     600},
31294         {"TRA_TRIG1_ADR_ADR"           ,           0x11800A80000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     601},
31295         {"TRA_TRIG1_ADR_MSK"           ,           0x11800A80000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     602},
31296         {"TRA_TRIG1_CMD"               ,           0x11800A80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     603},
31297         {"TRA_TRIG1_DID"               ,           0x11800A80000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     604},
31298         {"TRA_TRIG1_SID"               ,           0x11800A80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     605},
31299         {"ZIP_CMD_BIST_RESULT"         ,           0x1180038000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     606},
31300         {"ZIP_CMD_BUF"                 ,           0x1180038000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     607},
31301         {"ZIP_CMD_CTL"                 ,           0x1180038000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     608},
31302         {"ZIP_CONSTANTS"               ,           0x11800380000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     609},
31303         {"ZIP_DEBUG0"                  ,           0x1180038000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     610},
31304         {"ZIP_ERROR"                   ,           0x1180038000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     611},
31305         {"ZIP_INT_MASK"                ,           0x1180038000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     612},
31306         {NULL,0,0,0,0}
31307 };
31308 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn58xx[] = {
31309         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
31310         {"OVRFLW"                      ,        0,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
31311         {"TXPOP"                       ,        4,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
31312         {"TXPSH"                       ,        8,      4,      0,      "R/W",  0,      0,      0ull,   1ull},
31313         {"RESERVED_12_63"              ,        12,     52,     0,      "RAZ",  1,      1,      0,      0},
31314         {"OVRFLW"                      ,        0,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
31315         {"TXPOP"                       ,        4,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
31316         {"TXPSH"                       ,        8,      4,      1,      "R/W1C",        0,      0,      0ull,   0ull},
31317         {"RESERVED_12_63"              ,        12,     52,     1,      "RAZ",  1,      1,      0,      0},
31318         {"INT_LOOP"                    ,        0,      4,      2,      "R/W",  0,      0,      0ull,   0ull},
31319         {"EXT_LOOP"                    ,        4,      4,      2,      "R/W",  0,      0,      0ull,   0ull},
31320         {"RESERVED_8_63"               ,        8,      56,     2,      "RAZ",  1,      1,      0,      0},
31321         {"BYPASS"                      ,        0,      1,      3,      "R/W",  0,      1,      0ull,   0},
31322         {"RESERVED_1_63"               ,        1,      63,     3,      "RAZ",  1,      1,      0,      0},
31323         {"SETTING"                     ,        0,      5,      4,      "R/W",  0,      1,      0ull,   0},
31324         {"RESERVED_5_63"               ,        5,      59,     4,      "RAZ",  1,      1,      0,      0},
31325         {"NCTL"                        ,        0,      4,      5,      "RO",   0,      1,      0ull,   0},
31326         {"PCTL"                        ,        4,      5,      5,      "RO",   0,      1,      0ull,   0},
31327         {"RESERVED_9_63"               ,        9,      55,     5,      "RAZ",  1,      1,      0,      0},
31328         {"NCTL"                        ,        0,      4,      6,      "R/W",  0,      1,      0ull,   0},
31329         {"PCTL"                        ,        4,      4,      6,      "R/W",  0,      1,      0ull,   0},
31330         {"RESERVED_8_63"               ,        8,      56,     6,      "RAZ",  1,      1,      0,      0},
31331         {"NCTL"                        ,        0,      5,      7,      "R/W",  0,      1,      0ull,   0},
31332         {"RESERVED_5_63"               ,        5,      59,     7,      "RAZ",  1,      1,      0,      0},
31333         {"NCTL"                        ,        0,      5,      8,      "R/W",  0,      1,      0ull,   0},
31334         {"RESERVED_5_63"               ,        5,      59,     8,      "RAZ",  1,      1,      0,      0},
31335         {"PCTL"                        ,        0,      5,      9,      "R/W",  0,      1,      0ull,   0},
31336         {"RESERVED_5_63"               ,        5,      59,     9,      "RAZ",  1,      1,      0,      0},
31337         {"PCTL"                        ,        0,      5,      10,     "R/W",  0,      1,      0ull,   0},
31338         {"RESERVED_5_63"               ,        5,      59,     10,     "RAZ",  1,      1,      0,      0},
31339         {"SETTING"                     ,        0,      5,      11,     "RO",   1,      1,      0,      0},
31340         {"DFALOCK"                     ,        5,      1,      11,     "RO",   1,      1,      0,      0},
31341         {"DFALEAD"                     ,        6,      1,      11,     "RO",   1,      1,      0,      0},
31342         {"DFALAG"                      ,        7,      1,      11,     "RO",   1,      1,      0,      0},
31343         {"DFASET"                      ,        8,      5,      11,     "RO",   1,      1,      0,      0},
31344         {"RESERVED_13_63"              ,        13,     51,     11,     "RAZ",  1,      1,      0,      0},
31345         {"SETTING"                     ,        0,      5,      12,     "R/W",  0,      0,      24ull,  0ull},
31346         {"RESERVED_5_63"               ,        5,      59,     12,     "RAZ",  1,      1,      0,      0},
31347         {"PRT_EN"                      ,        0,      4,      13,     "R/W",  0,      0,      0ull,   1ull},
31348         {"RESERVED_4_63"               ,        4,      60,     13,     "RAZ",  1,      1,      0,      0},
31349         {"SETTING"                     ,        0,      5,      14,     "R/W",  0,      0,      24ull,  0ull},
31350         {"RESERVED_5_63"               ,        5,      59,     14,     "RAZ",  1,      1,      0,      0},
31351         {"NCTL"                        ,        0,      5,      15,     "R/W",  0,      0,      6ull,   6ull},
31352         {"RESERVED_5_7"                ,        5,      3,      15,     "RAZ",  1,      1,      0,      0},
31353         {"PCTL"                        ,        8,      5,      15,     "R/W",  0,      0,      9ull,   9ull},
31354         {"RESERVED_13_63"              ,        13,     51,     15,     "RAZ",  1,      1,      0,      0},
31355         {"MARK"                        ,        0,      4,      16,     "R/W",  0,      0,      0ull,   0ull},
31356         {"RESERVED_4_63"               ,        4,      60,     16,     "RAZ",  1,      1,      0,      0},
31357         {"PRT_EN"                      ,        0,      4,      17,     "R/W",  0,      0,      0ull,   1ull},
31358         {"RESERVED_4_63"               ,        4,      60,     17,     "RAZ",  1,      1,      0,      0},
31359         {"NCTL"                        ,        0,      4,      18,     "R/W",  0,      1,      15ull,  0},
31360         {"PCTL"                        ,        4,      5,      18,     "R/W",  0,      1,      31ull,  0},
31361         {"RESERVED_9_63"               ,        9,      55,     18,     "RAZ",  1,      1,      0,      0},
31362         {"EN"                          ,        0,      1,      19,     "R/W",  0,      1,      1ull,   0},
31363         {"RESERVED_1_63"               ,        1,      63,     19,     "RAZ",  1,      1,      0,      0},
31364         {"BIST"                        ,        0,      4,      20,     "RO",   0,      0,      0ull,   0ull},
31365         {"RESERVED_4_63"               ,        4,      60,     20,     "RAZ",  1,      1,      0,      0},
31366         {"DINT"                        ,        0,      16,     21,     "WO",   0,      0,      0ull,   0ull},
31367         {"RESERVED_16_63"              ,        16,     48,     21,     "RAZ",  1,      1,      0,      0},
31368         {"FUSE"                        ,        0,      16,     22,     "RO",   1,      1,      0,      0},
31369         {"RESERVED_16_63"              ,        16,     48,     22,     "RAZ",  1,      1,      0,      0},
31370         {"GSTOP"                       ,        0,      1,      23,     "R/W",  0,      0,      0ull,   0ull},
31371         {"RESERVED_1_63"               ,        1,      63,     23,     "RAZ",  1,      1,      0,      0},
31372         {"WORKQ"                       ,        0,      16,     24,     "R/W",  0,      0,      0ull,   0ull},
31373         {"GPIO"                        ,        16,     16,     24,     "R/W",  0,      0,      0ull,   0ull},
31374         {"MBOX"                        ,        32,     2,      24,     "R/W",  0,      0,      0ull,   0ull},
31375         {"UART"                        ,        34,     2,      24,     "R/W",  0,      0,      0ull,   0ull},
31376         {"PCI_INT"                     ,        36,     4,      24,     "R/W",  0,      0,      0ull,   0ull},
31377         {"PCI_MSI"                     ,        40,     4,      24,     "R/W",  0,      0,      0ull,   0ull},
31378         {"RESERVED_44_44"              ,        44,     1,      24,     "RAZ",  1,      1,      0,      0},
31379         {"TWSI"                        ,        45,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
31380         {"RML"                         ,        46,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
31381         {"TRACE"                       ,        47,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
31382         {"GMX_DRP"                     ,        48,     2,      24,     "R/W",  0,      0,      0ull,   0ull},
31383         {"IPD_DRP"                     ,        50,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
31384         {"KEY_ZERO"                    ,        51,     1,      24,     "R/W",  0,      0,      0ull,   0ull},
31385         {"TIMER"                       ,        52,     4,      24,     "R/W",  0,      0,      0ull,   0ull},
31386         {"RESERVED_56_63"              ,        56,     8,      24,     "RAZ",  1,      1,      0,      0},
31387         {"WORKQ"                       ,        0,      16,     25,     "R/W1C",        0,      0,      0ull,   0ull},
31388         {"GPIO"                        ,        16,     16,     25,     "R/W1C",        0,      0,      0ull,   0ull},
31389         {"MBOX"                        ,        32,     2,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31390         {"UART"                        ,        34,     2,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31391         {"PCI_INT"                     ,        36,     4,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31392         {"PCI_MSI"                     ,        40,     4,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31393         {"RESERVED_44_44"              ,        44,     1,      25,     "RAZ",  1,      1,      0,      0},
31394         {"TWSI"                        ,        45,     1,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31395         {"RML"                         ,        46,     1,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31396         {"TRACE"                       ,        47,     1,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31397         {"GMX_DRP"                     ,        48,     2,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31398         {"IPD_DRP"                     ,        50,     1,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31399         {"KEY_ZERO"                    ,        51,     1,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31400         {"TIMER"                       ,        52,     4,      25,     "R/W1C",        0,      0,      0ull,   0ull},
31401         {"RESERVED_56_63"              ,        56,     8,      25,     "RAZ",  1,      1,      0,      0},
31402         {"WORKQ"                       ,        0,      16,     26,     "R/W1", 0,      0,      0ull,   0ull},
31403         {"GPIO"                        ,        16,     16,     26,     "R/W1", 0,      0,      0ull,   0ull},
31404         {"MBOX"                        ,        32,     2,      26,     "R/W1", 0,      0,      0ull,   0ull},
31405         {"UART"                        ,        34,     2,      26,     "R/W1", 0,      0,      0ull,   0ull},
31406         {"PCI_INT"                     ,        36,     4,      26,     "R/W1", 0,      0,      0ull,   0ull},
31407         {"PCI_MSI"                     ,        40,     4,      26,     "R/W1", 0,      0,      0ull,   0ull},
31408         {"RESERVED_44_44"              ,        44,     1,      26,     "RAZ",  1,      1,      0,      0},
31409         {"TWSI"                        ,        45,     1,      26,     "R/W1", 0,      0,      0ull,   0ull},
31410         {"RML"                         ,        46,     1,      26,     "R/W1", 0,      0,      0ull,   0ull},
31411         {"TRACE"                       ,        47,     1,      26,     "R/W1", 0,      0,      0ull,   0ull},
31412         {"GMX_DRP"                     ,        48,     2,      26,     "R/W1", 0,      0,      0ull,   0ull},
31413         {"IPD_DRP"                     ,        50,     1,      26,     "R/W1", 0,      0,      0ull,   0ull},
31414         {"KEY_ZERO"                    ,        51,     1,      26,     "R/W1", 0,      0,      0ull,   0ull},
31415         {"TIMER"                       ,        52,     4,      26,     "R/W1", 0,      0,      0ull,   0ull},
31416         {"RESERVED_56_63"              ,        56,     8,      26,     "RAZ",  1,      1,      0,      0},
31417         {"WDOG"                        ,        0,      16,     27,     "R/W",  0,      0,      0ull,   0ull},
31418         {"RESERVED_16_63"              ,        16,     48,     27,     "RAZ",  1,      1,      0,      0},
31419         {"WDOG"                        ,        0,      16,     28,     "R/W1C",        0,      0,      0ull,   0ull},
31420         {"RESERVED_16_63"              ,        16,     48,     28,     "RAZ",  1,      1,      0,      0},
31421         {"WDOG"                        ,        0,      16,     29,     "R/W1", 0,      0,      0ull,   0ull},
31422         {"RESERVED_16_63"              ,        16,     48,     29,     "RAZ",  1,      1,      0,      0},
31423         {"WORKQ"                       ,        0,      16,     30,     "R/W",  0,      0,      0ull,   0ull},
31424         {"GPIO"                        ,        16,     16,     30,     "R/W",  0,      0,      0ull,   0ull},
31425         {"MBOX"                        ,        32,     2,      30,     "R/W",  0,      0,      0ull,   0ull},
31426         {"UART"                        ,        34,     2,      30,     "R/W",  0,      0,      0ull,   0ull},
31427         {"PCI_INT"                     ,        36,     4,      30,     "R/W",  0,      0,      0ull,   0ull},
31428         {"PCI_MSI"                     ,        40,     4,      30,     "R/W",  0,      0,      0ull,   0ull},
31429         {"RESERVED_44_44"              ,        44,     1,      30,     "RAZ",  1,      1,      0,      0},
31430         {"TWSI"                        ,        45,     1,      30,     "R/W",  0,      0,      0ull,   0ull},
31431         {"RML"                         ,        46,     1,      30,     "R/W",  0,      0,      0ull,   0ull},
31432         {"TRACE"                       ,        47,     1,      30,     "R/W",  0,      0,      0ull,   0ull},
31433         {"GMX_DRP"                     ,        48,     2,      30,     "R/W",  0,      0,      0ull,   0ull},
31434         {"IPD_DRP"                     ,        50,     1,      30,     "R/W",  0,      0,      0ull,   0ull},
31435         {"KEY_ZERO"                    ,        51,     1,      30,     "R/W",  0,      0,      0ull,   0ull},
31436         {"TIMER"                       ,        52,     4,      30,     "R/W",  0,      0,      0ull,   0ull},
31437         {"RESERVED_56_63"              ,        56,     8,      30,     "RAZ",  1,      1,      0,      0},
31438         {"WORKQ"                       ,        0,      16,     31,     "R/W1C",        0,      0,      0ull,   0ull},
31439         {"GPIO"                        ,        16,     16,     31,     "R/W1C",        0,      0,      0ull,   0ull},
31440         {"MBOX"                        ,        32,     2,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31441         {"UART"                        ,        34,     2,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31442         {"PCI_INT"                     ,        36,     4,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31443         {"PCI_MSI"                     ,        40,     4,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31444         {"RESERVED_44_44"              ,        44,     1,      31,     "RAZ",  1,      1,      0,      0},
31445         {"TWSI"                        ,        45,     1,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31446         {"RML"                         ,        46,     1,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31447         {"TRACE"                       ,        47,     1,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31448         {"GMX_DRP"                     ,        48,     2,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31449         {"IPD_DRP"                     ,        50,     1,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31450         {"KEY_ZERO"                    ,        51,     1,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31451         {"TIMER"                       ,        52,     4,      31,     "R/W1C",        0,      0,      0ull,   0ull},
31452         {"RESERVED_56_63"              ,        56,     8,      31,     "RAZ",  1,      1,      0,      0},
31453         {"WORKQ"                       ,        0,      16,     32,     "R/W1", 0,      0,      0ull,   0ull},
31454         {"GPIO"                        ,        16,     16,     32,     "R/W1", 0,      0,      0ull,   0ull},
31455         {"MBOX"                        ,        32,     2,      32,     "R/W1", 0,      0,      0ull,   0ull},
31456         {"UART"                        ,        34,     2,      32,     "R/W1", 0,      0,      0ull,   0ull},
31457         {"PCI_INT"                     ,        36,     4,      32,     "R/W1", 0,      0,      0ull,   0ull},
31458         {"PCI_MSI"                     ,        40,     4,      32,     "R/W1", 0,      0,      0ull,   0ull},
31459         {"RESERVED_44_44"              ,        44,     1,      32,     "RAZ",  1,      1,      0,      0},
31460         {"TWSI"                        ,        45,     1,      32,     "R/W1", 0,      0,      0ull,   0ull},
31461         {"RML"                         ,        46,     1,      32,     "R/W1", 0,      0,      0ull,   0ull},
31462         {"TRACE"                       ,        47,     1,      32,     "R/W1", 0,      0,      0ull,   0ull},
31463         {"GMX_DRP"                     ,        48,     2,      32,     "R/W1", 0,      0,      0ull,   0ull},
31464         {"IPD_DRP"                     ,        50,     1,      32,     "R/W1", 0,      0,      0ull,   0ull},
31465         {"KEY_ZERO"                    ,        51,     1,      32,     "R/W1", 0,      0,      0ull,   0ull},
31466         {"TIMER"                       ,        52,     4,      32,     "R/W1", 0,      0,      0ull,   0ull},
31467         {"RESERVED_56_63"              ,        56,     8,      32,     "RAZ",  1,      1,      0,      0},
31468         {"WDOG"                        ,        0,      16,     33,     "R/W",  0,      0,      0ull,   0ull},
31469         {"RESERVED_16_63"              ,        16,     48,     33,     "RAZ",  1,      1,      0,      0},
31470         {"WDOG"                        ,        0,      16,     34,     "R/W1C",        0,      0,      0ull,   0ull},
31471         {"RESERVED_16_63"              ,        16,     48,     34,     "RAZ",  1,      1,      0,      0},
31472         {"WDOG"                        ,        0,      16,     35,     "R/W1", 0,      0,      0ull,   0ull},
31473         {"RESERVED_16_63"              ,        16,     48,     35,     "RAZ",  1,      1,      0,      0},
31474         {"WORKQ"                       ,        0,      16,     36,     "RO",   0,      0,      0ull,   0ull},
31475         {"GPIO"                        ,        16,     16,     36,     "RO",   0,      0,      0ull,   0ull},
31476         {"MBOX"                        ,        32,     2,      36,     "RO",   0,      0,      0ull,   0ull},
31477         {"UART"                        ,        34,     2,      36,     "RO",   0,      0,      0ull,   0ull},
31478         {"PCI_INT"                     ,        36,     4,      36,     "RO",   0,      0,      0ull,   0ull},
31479         {"PCI_MSI"                     ,        40,     4,      36,     "RO",   0,      0,      0ull,   0ull},
31480         {"WDOG_SUM"                    ,        44,     1,      36,     "RO",   0,      0,      0ull,   0ull},
31481         {"TWSI"                        ,        45,     1,      36,     "RO",   0,      0,      0ull,   0ull},
31482         {"RML"                         ,        46,     1,      36,     "RO",   0,      0,      0ull,   0ull},
31483         {"TRACE"                       ,        47,     1,      36,     "RO",   0,      0,      0ull,   0ull},
31484         {"GMX_DRP"                     ,        48,     2,      36,     "R/W1C",        0,      0,      0ull,   0ull},
31485         {"IPD_DRP"                     ,        50,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
31486         {"KEY_ZERO"                    ,        51,     1,      36,     "R/W1C",        0,      0,      0ull,   0ull},
31487         {"TIMER"                       ,        52,     4,      36,     "R/W1C",        0,      0,      0ull,   0ull},
31488         {"RESERVED_56_63"              ,        56,     8,      36,     "RAZ",  1,      1,      0,      0},
31489         {"WORKQ"                       ,        0,      16,     37,     "RO",   0,      0,      0ull,   0ull},
31490         {"GPIO"                        ,        16,     16,     37,     "RO",   0,      0,      0ull,   0ull},
31491         {"MBOX"                        ,        32,     2,      37,     "RO",   0,      0,      0ull,   0ull},
31492         {"UART"                        ,        34,     2,      37,     "RO",   0,      0,      0ull,   0ull},
31493         {"PCI_INT"                     ,        36,     4,      37,     "RO",   0,      0,      0ull,   0ull},
31494         {"PCI_MSI"                     ,        40,     4,      37,     "RO",   0,      0,      0ull,   0ull},
31495         {"WDOG_SUM"                    ,        44,     1,      37,     "RO",   0,      0,      0ull,   0ull},
31496         {"TWSI"                        ,        45,     1,      37,     "RO",   0,      0,      0ull,   0ull},
31497         {"RML"                         ,        46,     1,      37,     "RO",   0,      0,      0ull,   0ull},
31498         {"TRACE"                       ,        47,     1,      37,     "RO",   0,      0,      0ull,   0ull},
31499         {"GMX_DRP"                     ,        48,     2,      37,     "R/W1C",        0,      0,      0ull,   0ull},
31500         {"IPD_DRP"                     ,        50,     1,      37,     "R/W1C",        0,      0,      0ull,   0ull},
31501         {"KEY_ZERO"                    ,        51,     1,      37,     "R/W1C",        0,      0,      0ull,   0ull},
31502         {"TIMER"                       ,        52,     4,      37,     "R/W1C",        0,      0,      0ull,   0ull},
31503         {"RESERVED_56_63"              ,        56,     8,      37,     "RAZ",  1,      1,      0,      0},
31504         {"WDOG"                        ,        0,      16,     38,     "RO",   0,      0,      0ull,   0ull},
31505         {"RESERVED_16_63"              ,        16,     48,     38,     "RAZ",  1,      1,      0,      0},
31506         {"BITS"                        ,        0,      32,     39,     "R/W1C",        0,      0,      0ull,   0ull},
31507         {"RESERVED_32_63"              ,        32,     32,     39,     "RAZ",  1,      1,      0,      0},
31508         {"BITS"                        ,        0,      32,     40,     "R/W1", 0,      0,      0ull,   0ull},
31509         {"RESERVED_32_63"              ,        32,     32,     40,     "RAZ",  1,      1,      0,      0},
31510         {"NMI"                         ,        0,      16,     41,     "WO",   0,      0,      0ull,   0ull},
31511         {"RESERVED_16_63"              ,        16,     48,     41,     "RAZ",  1,      1,      0,      0},
31512         {"INTR"                        ,        0,      2,      42,     "R/W",  0,      0,      0ull,   0ull},
31513         {"RESERVED_2_63"               ,        2,      62,     42,     "RAZ",  1,      1,      0,      0},
31514         {"PPDBG"                       ,        0,      16,     43,     "RO",   0,      0,      0ull,   0ull},
31515         {"RESERVED_16_63"              ,        16,     48,     43,     "RAZ",  1,      1,      0,      0},
31516         {"POKE"                        ,        0,      64,     44,     "RAZ",  1,      1,      0,      0},
31517         {"RST0"                        ,        0,      1,      45,     "R/W",  1,      1,      0,      0},
31518         {"RST"                         ,        1,      15,     45,     "R/W",  0,      0,      32767ull,       0ull},
31519         {"RESERVED_16_63"              ,        16,     48,     45,     "RAZ",  1,      1,      0,      0},
31520         {"SOFT_BIST"                   ,        0,      1,      46,     "R/W",  0,      0,      0ull,   0ull},
31521         {"RESERVED_1_63"               ,        1,      63,     46,     "RAZ",  1,      1,      0,      0},
31522         {"SOFT_PRST"                   ,        0,      1,      47,     "R/W",  0,      0,      1ull,   0ull},
31523         {"NPI"                         ,        1,      1,      47,     "R/W",  0,      0,      0ull,   0ull},
31524         {"HOST64"                      ,        2,      1,      47,     "R/W",  0,      0,      1ull,   1ull},
31525         {"RESERVED_3_63"               ,        3,      61,     47,     "RAZ",  1,      1,      0,      0},
31526         {"SOFT_RST"                    ,        0,      1,      48,     "WO",   0,      0,      0ull,   0ull},
31527         {"RESERVED_1_63"               ,        1,      63,     48,     "RAZ",  1,      1,      0,      0},
31528         {"LEN"                         ,        0,      36,     49,     "R/W",  0,      0,      0ull,   0ull},
31529         {"ONE_SHOT"                    ,        36,     1,      49,     "R/W",  0,      0,      0ull,   0ull},
31530         {"RESERVED_37_63"              ,        37,     27,     49,     "RAZ",  1,      1,      0,      0},
31531         {"MODE"                        ,        0,      2,      50,     "R/W",  0,      0,      0ull,   0ull},
31532         {"STATE"                       ,        2,      2,      50,     "RO",   0,      0,      0ull,   0ull},
31533         {"LEN"                         ,        4,      16,     50,     "R/W",  0,      0,      0ull,   0ull},
31534         {"CNT"                         ,        20,     24,     50,     "RO",   0,      0,      0ull,   0ull},
31535         {"DSTOP"                       ,        44,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
31536         {"GSTOPEN"                     ,        45,     1,      50,     "R/W",  0,      0,      0ull,   0ull},
31537         {"RESERVED_46_63"              ,        46,     18,     50,     "RAZ",  1,      1,      0,      0},
31538         {"DATA"                        ,        0,      17,     51,     "RO",   0,      1,      0ull,   0},
31539         {"DSEL_EXT"                    ,        17,     1,      51,     "R/W",  0,      0,      1ull,   0ull},
31540         {"C_MUL"                       ,        18,     5,      51,     "RO",   1,      1,      0,      0},
31541         {"REM"                         ,        23,     6,      51,     "RO",   1,      1,      0,      0},
31542         {"RESERVED_29_63"              ,        29,     35,     51,     "RAZ",  1,      1,      0,      0},
31543         {"PDF"                         ,        0,      4,      52,     "RO",   0,      0,      0ull,   0ull},
31544         {"RESERVED_4_15"               ,        4,      12,     52,     "RAZ",  0,      0,      0ull,   0ull},
31545         {"RDF"                         ,        16,     4,      52,     "RO",   0,      0,      0ull,   0ull},
31546         {"RESERVED_20_63"              ,        20,     44,     52,     "RAZ",  0,      0,      0ull,   0ull},
31547         {"P1_BRF"                      ,        0,      8,      53,     "RO",   0,      0,      0ull,   0ull},
31548         {"P0_BRF"                      ,        8,      8,      53,     "RO",   0,      0,      0ull,   0ull},
31549         {"P1_BWB"                      ,        16,     1,      53,     "RO",   0,      0,      0ull,   0ull},
31550         {"P0_BWB"                      ,        17,     1,      53,     "RO",   0,      0,      0ull,   0ull},
31551         {"CRF"                         ,        18,     1,      53,     "RO",   0,      0,      0ull,   0ull},
31552         {"RESERVED_19_19"              ,        19,     1,      53,     "RAZ",  0,      0,      0ull,   0ull},
31553         {"GFU"                         ,        20,     1,      53,     "RO",   0,      0,      0ull,   0ull},
31554         {"IFU"                         ,        21,     1,      53,     "RO",   0,      0,      0ull,   0ull},
31555         {"CRQ"                         ,        22,     1,      53,     "RO",   0,      0,      0ull,   0ull},
31556         {"RESERVED_23_63"              ,        23,     41,     53,     "RAZ",  0,      0,      0ull,   0ull},
31557         {"SARB"                        ,        0,      1,      54,     "R/W",  0,      0,      1ull,   1ull},
31558         {"GXOR_ENA"                    ,        1,      1,      54,     "R/W",  0,      0,      0ull,   0ull},
31559         {"NXOR_ENA"                    ,        2,      1,      54,     "R/W",  0,      0,      0ull,   0ull},
31560         {"NRPL_ENA"                    ,        3,      1,      54,     "R/W",  0,      0,      0ull,   0ull},
31561         {"RESERVED_4_63"               ,        4,      60,     54,     "RAZ",  1,      1,      0,      0},
31562         {"DBELL"                       ,        0,      20,     55,     "R/W",  0,      1,      0ull,   0},
31563         {"RESERVED_20_63"              ,        20,     44,     55,     "RAZ",  1,      1,      0,      0},
31564         {"SIZE"                        ,        0,      9,      56,     "R/W",  0,      1,      3ull,   0},
31565         {"POOL"                        ,        9,      3,      56,     "R/W",  0,      1,      0ull,   0},
31566         {"DWBCNT"                      ,        12,     8,      56,     "R/W",  0,      1,      1ull,   0},
31567         {"RESERVED_20_63"              ,        20,     44,     56,     "RAZ",  1,      1,      0,      0},
31568         {"RESERVED_0_4"                ,        0,      5,      57,     "RAZ",  1,      1,      0,      0},
31569         {"RDPTR"                       ,        5,      31,     57,     "R/W",  0,      1,      0ull,   0},
31570         {"RESERVED_36_63"              ,        36,     28,     57,     "RAZ",  1,      1,      0,      0},
31571         {"CP2ECCENA"                   ,        0,      1,      58,     "R/W",  0,      0,      0ull,   0ull},
31572         {"CP2SBE"                      ,        1,      1,      58,     "R/W1C",        0,      0,      0ull,   0ull},
31573         {"CP2DBE"                      ,        2,      1,      58,     "R/W1C",        0,      0,      0ull,   0ull},
31574         {"CP2SBINA"                    ,        3,      1,      58,     "R/W",  0,      0,      0ull,   0ull},
31575         {"CP2DBINA"                    ,        4,      1,      58,     "R/W",  0,      0,      0ull,   0ull},
31576         {"CP2SYN"                      ,        5,      8,      58,     "RO",   0,      0,      0ull,   0ull},
31577         {"DTEECCENA"                   ,        13,     1,      58,     "R/W",  0,      0,      0ull,   0ull},
31578         {"DTESBE"                      ,        14,     1,      58,     "R/W1C",        0,      0,      0ull,   0ull},
31579         {"DTEDBE"                      ,        15,     1,      58,     "R/W1C",        0,      0,      0ull,   0ull},
31580         {"DTESBINA"                    ,        16,     1,      58,     "R/W",  0,      0,      0ull,   0ull},
31581         {"DTEDBINA"                    ,        17,     1,      58,     "R/W",  0,      0,      0ull,   0ull},
31582         {"DTESYN"                      ,        18,     7,      58,     "RO",   0,      0,      0ull,   0ull},
31583         {"DTEPARENA"                   ,        25,     1,      58,     "R/W",  0,      0,      0ull,   0ull},
31584         {"DTEPERR"                     ,        26,     1,      58,     "R/W1C",        0,      0,      0ull,   0ull},
31585         {"DTEPINA"                     ,        27,     1,      58,     "R/W",  0,      0,      0ull,   0ull},
31586         {"CP2PARENA"                   ,        28,     1,      58,     "R/W",  0,      0,      0ull,   0ull},
31587         {"CP2PERR"                     ,        29,     1,      58,     "R/W1C",        0,      0,      0ull,   0ull},
31588         {"CP2PINA"                     ,        30,     1,      58,     "R/W",  0,      0,      0ull,   0ull},
31589         {"DBLOVF"                      ,        31,     1,      58,     "R/W1C",        0,      0,      0ull,   0ull},
31590         {"DBLINA"                      ,        32,     1,      58,     "R/W",  0,      0,      0ull,   0ull},
31591         {"RESERVED_33_63"              ,        33,     31,     58,     "RAZ",  1,      1,      0,      0},
31592         {"ENA_P1"                      ,        0,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
31593         {"ENA_P0"                      ,        1,      1,      59,     "R/W",  0,      0,      1ull,   1ull},
31594         {"RESERVED_2_2"                ,        2,      1,      59,     "RAZ",  1,      1,      0,      0},
31595         {"MTYPE"                       ,        3,      1,      59,     "R/W",  0,      0,      0ull,   0ull},
31596         {"SIL_LAT"                     ,        4,      2,      59,     "R/W",  0,      0,      0ull,   0ull},
31597         {"RW_DLY"                      ,        6,      4,      59,     "R/W",  0,      0,      1ull,   1ull},
31598         {"WR_DLY"                      ,        10,     4,      59,     "R/W",  0,      0,      2ull,   2ull},
31599         {"FPRCH"                       ,        14,     2,      59,     "R/W",  0,      0,      0ull,   0ull},
31600         {"BPRCH"                       ,        16,     2,      59,     "R/W",  0,      0,      0ull,   0ull},
31601         {"BLEN"                        ,        18,     1,      59,     "R/W",  0,      0,      0ull,   0ull},
31602         {"PBUNK"                       ,        19,     3,      59,     "R/W",  0,      0,      2ull,   2ull},
31603         {"R2R_PBUNK"                   ,        22,     1,      59,     "R/W",  0,      0,      1ull,   1ull},
31604         {"INIT_P1"                     ,        23,     1,      59,     "R/W",  0,      0,      0ull,   0ull},
31605         {"INIT_P0"                     ,        24,     1,      59,     "R/W",  0,      0,      0ull,   0ull},
31606         {"BUNK_INIT"                   ,        25,     2,      59,     "R/W",  0,      0,      3ull,   3ull},
31607         {"LPP_ENA"                     ,        27,     1,      59,     "R/W",  0,      0,      0ull,   0ull},
31608         {"CLKDIV"                      ,        28,     2,      59,     "R/W",  0,      0,      0ull,   0ull},
31609         {"RLDCK_RST"                   ,        30,     1,      59,     "R/W",  0,      0,      0ull,   0ull},
31610         {"RLDQCK90_RST"                ,        31,     1,      59,     "R/W",  0,      0,      0ull,   0ull},
31611         {"RESERVED_32_63"              ,        32,     32,     59,     "RAZ",  1,      1,      0,      0},
31612         {"REF_INT"                     ,        0,      4,      60,     "R/W",  0,      0,      3ull,   3ull},
31613         {"TSKW"                        ,        4,      2,      60,     "R/W",  0,      0,      0ull,   0ull},
31614         {"RESERVED_6_7"                ,        6,      2,      60,     "RAZ",  0,      0,      0ull,   0ull},
31615         {"TRL"                         ,        8,      4,      60,     "R/W",  0,      0,      6ull,   6ull},
31616         {"TWL"                         ,        12,     4,      60,     "R/W",  0,      0,      7ull,   7ull},
31617         {"TRC"                         ,        16,     4,      60,     "R/W",  0,      0,      6ull,   6ull},
31618         {"TMRSC"                       ,        20,     3,      60,     "R/W",  0,      0,      6ull,   6ull},
31619         {"MRS_ENA"                     ,        23,     1,      60,     "R/W",  0,      0,      0ull,   0ull},
31620         {"AREF_ENA"                    ,        24,     1,      60,     "R/W",  0,      0,      0ull,   0ull},
31621         {"REF_INTLO"                   ,        25,     9,      60,     "R/W",  0,      0,      0ull,   0ull},
31622         {"RESERVED_34_63"              ,        34,     30,     60,     "RAZ",  1,      1,      0,      0},
31623         {"FCRAM2P"                     ,        0,      1,      61,     "R/W",  0,      0,      0ull,   0ull},
31624         {"MAXBNK"                      ,        1,      1,      61,     "R/W",  0,      0,      1ull,   1ull},
31625         {"UA_START"                    ,        2,      2,      61,     "R/W",  0,      0,      1ull,   1ull},
31626         {"REFSHORT"                    ,        4,      1,      61,     "R/W",  0,      0,      0ull,   0ull},
31627         {"TRFC"                        ,        5,      5,      61,     "R/W",  0,      0,      9ull,   9ull},
31628         {"SILRST"                      ,        10,     1,      61,     "R/W",  0,      0,      0ull,   0ull},
31629         {"DTECLKDIS"                   ,        11,     1,      61,     "R/W",  0,      0,      0ull,   0ull},
31630         {"RESERVED_12_63"              ,        12,     52,     61,     "RAZ",  1,      1,      0,      0},
31631         {"MADDR"                       ,        0,      24,     62,     "RO",   0,      0,      0ull,   0ull},
31632         {"BNUM"                        ,        24,     3,      62,     "RO",   0,      0,      0ull,   0ull},
31633         {"PNUM"                        ,        27,     1,      62,     "RO",   0,      0,      0ull,   0ull},
31634         {"FSRC"                        ,        28,     2,      62,     "RO",   0,      0,      0ull,   0ull},
31635         {"FDST"                        ,        30,     9,      62,     "RO",   0,      0,      0ull,   0ull},
31636         {"RESERVED_39_63"              ,        39,     25,     62,     "RAZ",  1,      1,      0,      0},
31637         {"MRS"                         ,        0,      15,     63,     "R/W",  0,      0,      66ull,  66ull},
31638         {"RESERVED_15_15"              ,        15,     1,      63,     "RAZ",  1,      1,      0,      0},
31639         {"EMRS"                        ,        16,     15,     63,     "R/W",  0,      0,      64ull,  64ull},
31640         {"RESERVED_31_31"              ,        31,     1,      63,     "RAZ",  1,      1,      0,      0},
31641         {"EMRS2"                       ,        32,     15,     63,     "R/W",  0,      0,      0ull,   0ull},
31642         {"RESERVED_47_63"              ,        47,     17,     63,     "RAZ",  1,      1,      0,      0},
31643         {"MRSDAT"                      ,        0,      23,     64,     "R/W",  0,      0,      2ull,   2ull},
31644         {"RESERVED_23_63"              ,        23,     41,     64,     "RAZ",  1,      1,      0,      0},
31645         {"IMODE"                       ,        0,      1,      65,     "R/W",  0,      0,      1ull,   1ull},
31646         {"QMODE"                       ,        1,      1,      65,     "R/W",  0,      0,      1ull,   1ull},
31647         {"PMODE"                       ,        2,      1,      65,     "R/W",  0,      0,      1ull,   1ull},
31648         {"DTMODE"                      ,        3,      1,      65,     "R/W",  0,      0,      1ull,   1ull},
31649         {"DCMODE"                      ,        4,      1,      65,     "R/W",  0,      0,      0ull,   0ull},
31650         {"SBDLCK"                      ,        5,      1,      65,     "R/W",  0,      0,      0ull,   0ull},
31651         {"SBDNUM"                      ,        6,      5,      65,     "R/W",  0,      0,      0ull,   0ull},
31652         {"RESERVED_11_63"              ,        11,     53,     65,     "RAZ",  1,      1,      0,      0},
31653         {"PCTL"                        ,        0,      5,      66,     "R/W",  0,      1,      0ull,   0},
31654         {"RESERVED_5_7"                ,        5,      3,      66,     "RAZ",  0,      1,      0ull,   0},
31655         {"NCTL"                        ,        8,      4,      66,     "R/W",  0,      1,      0ull,   0},
31656         {"RESERVED_12_15"              ,        12,     4,      66,     "RAZ",  0,      1,      0ull,   0},
31657         {"ENABLE"                      ,        16,     1,      66,     "R/W",  0,      1,      0ull,   0},
31658         {"RESERVED_17_63"              ,        17,     47,     66,     "RAZ",  0,      1,      0ull,   0},
31659         {"SBD0"                        ,        0,      64,     67,     "RO",   1,      1,      0,      0},
31660         {"SBD1"                        ,        0,      64,     68,     "RO",   1,      1,      0,      0},
31661         {"SBD2"                        ,        0,      64,     69,     "RO",   1,      1,      0,      0},
31662         {"SBD3"                        ,        0,      64,     70,     "RO",   1,      1,      0,      0},
31663         {"FDR"                         ,        0,      1,      71,     "RO",   0,      0,      0ull,   0ull},
31664         {"FFR"                         ,        1,      1,      71,     "RO",   0,      0,      0ull,   0ull},
31665         {"FPF1"                        ,        2,      1,      71,     "RO",   0,      0,      0ull,   0ull},
31666         {"FPF0"                        ,        3,      1,      71,     "RO",   0,      0,      0ull,   0ull},
31667         {"FRD"                         ,        4,      1,      71,     "RO",   0,      0,      0ull,   0ull},
31668         {"RESERVED_5_63"               ,        5,      59,     71,     "RAZ",  1,      1,      0,      0},
31669         {"MEM0_ERR"                    ,        0,      7,      72,     "R/W",  0,      0,      0ull,   0ull},
31670         {"MEM1_ERR"                    ,        7,      7,      72,     "R/W",  0,      0,      0ull,   0ull},
31671         {"ENB"                         ,        14,     1,      72,     "R/W",  0,      0,      0ull,   0ull},
31672         {"USE_STT"                     ,        15,     1,      72,     "R/W",  0,      0,      0ull,   0ull},
31673         {"USE_LDT"                     ,        16,     1,      72,     "R/W",  0,      0,      0ull,   0ull},
31674         {"RESET"                       ,        17,     1,      72,     "R/W",  0,      0,      0ull,   0ull},
31675         {"RESERVED_18_63"              ,        18,     46,     72,     "RAZ",  1,      1,      0,      0},
31676         {"FPF_RD"                      ,        0,      11,     73,     "R/W",  0,      0,      64ull,  0ull},
31677         {"FPF_WR"                      ,        11,     11,     73,     "R/W",  0,      0,      196ull, 0ull},
31678         {"RESERVED_22_63"              ,        22,     42,     73,     "RAZ",  1,      1,      0,      0},
31679         {"FPF_SIZ"                     ,        0,      11,     74,     "R/W",  0,      0,      256ull, 0ull},
31680         {"RESERVED_11_63"              ,        11,     53,     74,     "RAZ",  1,      1,      0,      0},
31681         {"FPF_RD"                      ,        0,      12,     75,     "R/W",  0,      0,      64ull,  0ull},
31682         {"FPF_WR"                      ,        12,     12,     75,     "R/W",  0,      0,      196ull, 0ull},
31683         {"RESERVED_24_63"              ,        24,     40,     75,     "RAZ",  1,      1,      0,      0},
31684         {"FPF_SIZ"                     ,        0,      12,     76,     "R/W",  0,      0,      256ull, 0ull},
31685         {"RESERVED_12_63"              ,        12,     52,     76,     "RAZ",  1,      1,      0,      0},
31686         {"FED0_SBE"                    ,        0,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31687         {"FED0_DBE"                    ,        1,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31688         {"FED1_SBE"                    ,        2,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31689         {"FED1_DBE"                    ,        3,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31690         {"Q0_UND"                      ,        4,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31691         {"Q0_COFF"                     ,        5,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31692         {"Q0_PERR"                     ,        6,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31693         {"Q1_UND"                      ,        7,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31694         {"Q1_COFF"                     ,        8,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31695         {"Q1_PERR"                     ,        9,      1,      77,     "R/W",  0,      0,      0ull,   0ull},
31696         {"Q2_UND"                      ,        10,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31697         {"Q2_COFF"                     ,        11,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31698         {"Q2_PERR"                     ,        12,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31699         {"Q3_UND"                      ,        13,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31700         {"Q3_COFF"                     ,        14,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31701         {"Q3_PERR"                     ,        15,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31702         {"Q4_UND"                      ,        16,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31703         {"Q4_COFF"                     ,        17,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31704         {"Q4_PERR"                     ,        18,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31705         {"Q5_UND"                      ,        19,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31706         {"Q5_COFF"                     ,        20,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31707         {"Q5_PERR"                     ,        21,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31708         {"Q6_UND"                      ,        22,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31709         {"Q6_COFF"                     ,        23,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31710         {"Q6_PERR"                     ,        24,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31711         {"Q7_UND"                      ,        25,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31712         {"Q7_COFF"                     ,        26,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31713         {"Q7_PERR"                     ,        27,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
31714         {"RESERVED_28_63"              ,        28,     36,     77,     "RAZ",  1,      1,      0,      0},
31715         {"FED0_SBE"                    ,        0,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31716         {"FED0_DBE"                    ,        1,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31717         {"FED1_SBE"                    ,        2,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31718         {"FED1_DBE"                    ,        3,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31719         {"Q0_UND"                      ,        4,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31720         {"Q0_COFF"                     ,        5,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31721         {"Q0_PERR"                     ,        6,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31722         {"Q1_UND"                      ,        7,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31723         {"Q1_COFF"                     ,        8,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31724         {"Q1_PERR"                     ,        9,      1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31725         {"Q2_UND"                      ,        10,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31726         {"Q2_COFF"                     ,        11,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31727         {"Q2_PERR"                     ,        12,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31728         {"Q3_UND"                      ,        13,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31729         {"Q3_COFF"                     ,        14,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31730         {"Q3_PERR"                     ,        15,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31731         {"Q4_UND"                      ,        16,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31732         {"Q4_COFF"                     ,        17,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31733         {"Q4_PERR"                     ,        18,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31734         {"Q5_UND"                      ,        19,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31735         {"Q5_COFF"                     ,        20,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31736         {"Q5_PERR"                     ,        21,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31737         {"Q6_UND"                      ,        22,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31738         {"Q6_COFF"                     ,        23,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31739         {"Q6_PERR"                     ,        24,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31740         {"Q7_UND"                      ,        25,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31741         {"Q7_COFF"                     ,        26,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31742         {"Q7_PERR"                     ,        27,     1,      78,     "R/W1C",        0,      0,      0ull,   0ull},
31743         {"RESERVED_28_63"              ,        28,     36,     78,     "RAZ",  1,      1,      0,      0},
31744         {"QUE_SIZ"                     ,        0,      29,     79,     "RO",   0,      0,      0ull,   0ull},
31745         {"RESERVED_29_63"              ,        29,     35,     79,     "RAZ",  1,      1,      0,      0},
31746         {"PG_NUM"                      ,        0,      25,     80,     "RO",   0,      1,      0ull,   0},
31747         {"RESERVED_25_63"              ,        25,     39,     80,     "RAZ",  1,      1,      0,      0},
31748         {"ACT_INDX"                    ,        0,      26,     81,     "RO",   0,      1,      0ull,   0},
31749         {"ACT_QUE"                     ,        26,     3,      81,     "RO",   0,      1,      0ull,   0},
31750         {"RESERVED_29_63"              ,        29,     35,     81,     "RAZ",  0,      0,      0ull,   7ull},
31751         {"EXP_INDX"                    ,        0,      26,     82,     "RO",   0,      1,      0ull,   0},
31752         {"EXP_QUE"                     ,        26,     3,      82,     "RO",   0,      1,      0ull,   0},
31753         {"RESERVED_29_63"              ,        29,     35,     82,     "RAZ",  0,      0,      0ull,   7ull},
31754         {"CTL"                         ,        0,      16,     83,     "R/W",  1,      0,      0,      0ull},
31755         {"RESERVED_16_63"              ,        16,     48,     83,     "RAZ",  1,      1,      0,      0},
31756         {"STATUS"                      ,        0,      32,     84,     "RO",   0,      0,      0ull,   0ull},
31757         {"RESERVED_32_63"              ,        32,     32,     84,     "RAZ",  1,      1,      0,      0},
31758         {"OUT_COL"                     ,        0,      1,      85,     "R/W1C",        0,      0,      0ull,   0ull},
31759         {"NCB_OVR"                     ,        1,      1,      85,     "R/W1C",        0,      0,      0ull,   0ull},
31760         {"OUT_OVR"                     ,        2,      16,     85,     "R/W1C",        0,      0,      0ull,   0ull},
31761         {"RESERVED_18_21"              ,        18,     4,      85,     "RAZ",  0,      0,      0ull,   0ull},
31762         {"LOSTSTAT"                    ,        22,     4,      85,     "R/W1C",        0,      0,      0ull,   0ull},
31763         {"STATOVR"                     ,        26,     1,      85,     "R/W1C",        0,      0,      0ull,   0ull},
31764         {"INB_NXA"                     ,        27,     4,      85,     "R/W1C",        0,      0,      0ull,   0ull},
31765         {"RESERVED_31_63"              ,        31,     33,     85,     "RAZ",  1,      1,      0,      0},
31766         {"STATUS"                      ,        0,      17,     86,     "RO",   0,      0,      0ull,   0ull},
31767         {"RESERVED_17_63"              ,        17,     47,     86,     "RAZ",  1,      1,      0,      0},
31768         {"TYPE"                        ,        0,      1,      87,     "RO",   1,      1,      0,      0},
31769         {"EN"                          ,        1,      1,      87,     "RO",   1,      1,      0,      0},
31770         {"RESERVED_2_63"               ,        2,      62,     87,     "RAZ",  1,      1,      0,      0},
31771         {"PRT"                         ,        0,      6,      88,     "RO",   0,      1,      0ull,   0},
31772         {"RESERVED_6_63"               ,        6,      58,     88,     "RAZ",  1,      1,      0,      0},
31773         {"EN"                          ,        0,      1,      89,     "R/W",  0,      1,      0ull,   0},
31774         {"SPEED"                       ,        1,      1,      89,     "R/W",  0,      1,      1ull,   0},
31775         {"DUPLEX"                      ,        2,      1,      89,     "R/W",  0,      1,      1ull,   0},
31776         {"SLOTTIME"                    ,        3,      1,      89,     "R/W",  0,      1,      1ull,   0},
31777         {"RESERVED_4_63"               ,        4,      60,     89,     "RAZ",  1,      1,      0,      0},
31778         {"ADR"                         ,        0,      64,     90,     "R/W",  0,      1,      0ull,   0},
31779         {"ADR"                         ,        0,      64,     91,     "R/W",  0,      1,      0ull,   0},
31780         {"ADR"                         ,        0,      64,     92,     "R/W",  0,      1,      0ull,   0},
31781         {"ADR"                         ,        0,      64,     93,     "R/W",  0,      1,      0ull,   0},
31782         {"ADR"                         ,        0,      64,     94,     "R/W",  0,      1,      0ull,   0},
31783         {"ADR"                         ,        0,      64,     95,     "R/W",  0,      1,      0ull,   0},
31784         {"EN"                          ,        0,      8,      96,     "R/W",  0,      1,      0ull,   0},
31785         {"RESERVED_8_63"               ,        8,      56,     96,     "RAZ",  1,      1,      0,      0},
31786         {"BCST"                        ,        0,      1,      97,     "R/W",  0,      1,      1ull,   0},
31787         {"MCST"                        ,        1,      2,      97,     "R/W",  0,      1,      0ull,   0},
31788         {"CAM_MODE"                    ,        3,      1,      97,     "R/W",  0,      1,      0ull,   0},
31789         {"RESERVED_4_63"               ,        4,      60,     97,     "RAZ",  1,      1,      0,      0},
31790         {"CNT"                         ,        0,      5,      98,     "R/W",  0,      0,      24ull,  24ull},
31791         {"RESERVED_5_63"               ,        5,      59,     98,     "RAZ",  1,      1,      0,      0},
31792         {"MINERR"                      ,        0,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31793         {"CAREXT"                      ,        1,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31794         {"MAXERR"                      ,        2,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31795         {"JABBER"                      ,        3,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31796         {"FCSERR"                      ,        4,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31797         {"ALNERR"                      ,        5,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31798         {"LENERR"                      ,        6,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31799         {"RCVERR"                      ,        7,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31800         {"SKPERR"                      ,        8,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31801         {"NIBERR"                      ,        9,      1,      99,     "R/W",  0,      0,      1ull,   1ull},
31802         {"RESERVED_10_63"              ,        10,     54,     99,     "RAZ",  1,      1,      0,      0},
31803         {"PRE_CHK"                     ,        0,      1,      100,    "R/W",  0,      0,      1ull,   1ull},
31804         {"PRE_STRP"                    ,        1,      1,      100,    "R/W",  0,      0,      1ull,   1ull},
31805         {"CTL_DRP"                     ,        2,      1,      100,    "R/W",  0,      0,      1ull,   1ull},
31806         {"CTL_BCK"                     ,        3,      1,      100,    "R/W",  0,      0,      1ull,   1ull},
31807         {"CTL_MCST"                    ,        4,      1,      100,    "R/W",  0,      0,      1ull,   1ull},
31808         {"CTL_SMAC"                    ,        5,      1,      100,    "R/W",  0,      0,      1ull,   1ull},
31809         {"PRE_FREE"                    ,        6,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
31810         {"VLAN_LEN"                    ,        7,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
31811         {"PAD_LEN"                     ,        8,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
31812         {"PRE_ALIGN"                   ,        9,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
31813         {"NULL_DIS"                    ,        10,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
31814         {"RESERVED_11_63"              ,        11,     53,     100,    "RAZ",  1,      1,      0,      0},
31815         {"LEN"                         ,        0,      16,     101,    "R/W",  0,      0,      1536ull,        1536ull},
31816         {"RESERVED_16_63"              ,        16,     48,     101,    "RAZ",  1,      1,      0,      0},
31817         {"LEN"                         ,        0,      16,     102,    "R/W",  0,      0,      64ull,  64ull},
31818         {"RESERVED_16_63"              ,        16,     48,     102,    "RAZ",  1,      1,      0,      0},
31819         {"IFG"                         ,        0,      4,      103,    "R/W",  0,      0,      12ull,  12ull},
31820         {"RESERVED_4_63"               ,        4,      60,     103,    "RAZ",  1,      1,      0,      0},
31821         {"MINERR"                      ,        0,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31822         {"CAREXT"                      ,        1,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31823         {"MAXERR"                      ,        2,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31824         {"JABBER"                      ,        3,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31825         {"FCSERR"                      ,        4,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31826         {"ALNERR"                      ,        5,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31827         {"LENERR"                      ,        6,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31828         {"RCVERR"                      ,        7,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31829         {"SKPERR"                      ,        8,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31830         {"NIBERR"                      ,        9,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
31831         {"OVRERR"                      ,        10,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31832         {"PCTERR"                      ,        11,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31833         {"RSVERR"                      ,        12,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31834         {"FALERR"                      ,        13,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31835         {"COLDET"                      ,        14,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31836         {"IFGERR"                      ,        15,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31837         {"PHY_LINK"                    ,        16,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31838         {"PHY_SPD"                     ,        17,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31839         {"PHY_DUPX"                    ,        18,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31840         {"PAUSE_DRP"                   ,        19,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
31841         {"RESERVED_20_63"              ,        20,     44,     104,    "RAZ",  1,      1,      0,      0},
31842         {"MINERR"                      ,        0,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31843         {"CAREXT"                      ,        1,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31844         {"MAXERR"                      ,        2,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31845         {"JABBER"                      ,        3,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31846         {"FCSERR"                      ,        4,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31847         {"ALNERR"                      ,        5,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31848         {"LENERR"                      ,        6,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31849         {"RCVERR"                      ,        7,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31850         {"SKPERR"                      ,        8,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31851         {"NIBERR"                      ,        9,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31852         {"OVRERR"                      ,        10,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31853         {"PCTERR"                      ,        11,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31854         {"RSVERR"                      ,        12,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31855         {"FALERR"                      ,        13,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31856         {"COLDET"                      ,        14,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31857         {"IFGERR"                      ,        15,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31858         {"PHY_LINK"                    ,        16,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31859         {"PHY_SPD"                     ,        17,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31860         {"PHY_DUPX"                    ,        18,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31861         {"PAUSE_DRP"                   ,        19,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
31862         {"RESERVED_20_63"              ,        20,     44,     105,    "RAZ",  1,      1,      0,      0},
31863         {"CNT"                         ,        0,      16,     106,    "R/W",  0,      0,      10240ull,       10240ull},
31864         {"RESERVED_16_63"              ,        16,     48,     106,    "RAZ",  1,      1,      0,      0},
31865         {"STATUS"                      ,        0,      16,     107,    "R/W1C",        0,      1,      0ull,   0},
31866         {"RESERVED_16_63"              ,        16,     48,     107,    "RAZ",  1,      1,      0,      0},
31867         {"STATUS"                      ,        0,      1,      108,    "RO",   0,      1,      0ull,   0},
31868         {"SPEED"                       ,        1,      2,      108,    "RO",   0,      1,      0ull,   0},
31869         {"DUPLEX"                      ,        3,      1,      108,    "RO",   0,      1,      0ull,   0},
31870         {"RESERVED_4_63"               ,        4,      60,     108,    "RAZ",  1,      1,      0,      0},
31871         {"RD_CLR"                      ,        0,      1,      109,    "R/W",  0,      0,      0ull,   0ull},
31872         {"RESERVED_1_63"               ,        1,      63,     109,    "RAZ",  1,      1,      0,      0},
31873         {"CNT"                         ,        0,      48,     110,    "RC/W", 0,      1,      0ull,   0},
31874         {"RESERVED_48_63"              ,        48,     16,     110,    "RAZ",  1,      1,      0,      0},
31875         {"CNT"                         ,        0,      48,     111,    "RC/W", 0,      1,      0ull,   0},
31876         {"RESERVED_48_63"              ,        48,     16,     111,    "RAZ",  1,      1,      0,      0},
31877         {"CNT"                         ,        0,      48,     112,    "RC/W", 0,      1,      0ull,   0},
31878         {"RESERVED_48_63"              ,        48,     16,     112,    "RAZ",  1,      1,      0,      0},
31879         {"CNT"                         ,        0,      48,     113,    "RC/W", 0,      1,      0ull,   0},
31880         {"RESERVED_48_63"              ,        48,     16,     113,    "RAZ",  1,      1,      0,      0},
31881         {"CNT"                         ,        0,      32,     114,    "RC/W", 0,      1,      0ull,   0},
31882         {"RESERVED_32_63"              ,        32,     32,     114,    "RAZ",  1,      1,      0,      0},
31883         {"CNT"                         ,        0,      32,     115,    "RC/W", 0,      1,      0ull,   0},
31884         {"RESERVED_32_63"              ,        32,     32,     115,    "RAZ",  1,      1,      0,      0},
31885         {"CNT"                         ,        0,      32,     116,    "RC/W", 0,      1,      0ull,   0},
31886         {"RESERVED_32_63"              ,        32,     32,     116,    "RAZ",  1,      1,      0,      0},
31887         {"CNT"                         ,        0,      32,     117,    "RC/W", 0,      1,      0ull,   0},
31888         {"RESERVED_32_63"              ,        32,     32,     117,    "RAZ",  1,      1,      0,      0},
31889         {"CNT"                         ,        0,      32,     118,    "RC/W", 0,      1,      0ull,   0},
31890         {"RESERVED_32_63"              ,        32,     32,     118,    "RAZ",  1,      1,      0,      0},
31891         {"LEN"                         ,        0,      7,      119,    "R/W",  0,      0,      0ull,   0ull},
31892         {"RESERVED_7_7"                ,        7,      1,      119,    "RAZ",  1,      1,      0,      0},
31893         {"FCSSEL"                      ,        8,      1,      119,    "R/W",  0,      0,      0ull,   0ull},
31894         {"RESERVED_9_63"               ,        9,      55,     119,    "RAZ",  1,      1,      0,      0},
31895         {"MARK"                        ,        0,      6,      120,    "R/W",  1,      1,      0,      0},
31896         {"RESERVED_6_63"               ,        6,      58,     120,    "RAZ",  1,      1,      0,      0},
31897         {"MARK"                        ,        0,      6,      121,    "R/W",  0,      0,      16ull,  16ull},
31898         {"RESERVED_6_63"               ,        6,      58,     121,    "RAZ",  1,      1,      0,      0},
31899         {"MARK"                        ,        0,      9,      122,    "R/W",  1,      1,      0,      0},
31900         {"RESERVED_9_63"               ,        9,      55,     122,    "RAZ",  1,      1,      0,      0},
31901         {"EN"                          ,        0,      16,     123,    "R/W",  0,      0,      0ull,   0ull},
31902         {"RESERVED_16_63"              ,        16,     48,     123,    "RAZ",  1,      1,      0,      0},
31903         {"DPRT"                        ,        0,      4,      124,    "R/W",  0,      0,      0ull,   0ull},
31904         {"RESERVED_4_63"               ,        4,      60,     124,    "RAZ",  1,      1,      0,      0},
31905         {"COMMIT"                      ,        0,      16,     125,    "RO",   0,      0,      0ull,   0ull},
31906         {"DROP"                        ,        16,     16,     125,    "RO",   0,      0,      0ull,   0ull},
31907         {"RESERVED_32_63"              ,        32,     32,     125,    "RAZ",  1,      1,      0,      0},
31908         {"PRTS"                        ,        0,      3,      126,    "R/W",  0,      0,      4ull,   4ull},
31909         {"RESERVED_3_63"               ,        3,      61,     126,    "RAZ",  1,      1,      0,      0},
31910         {"SMAC"                        ,        0,      48,     127,    "R/W",  0,      1,      0ull,   0},
31911         {"RESERVED_48_63"              ,        48,     16,     127,    "RAZ",  1,      1,      0,      0},
31912         {"CNT"                         ,        0,      16,     128,    "R/W1C",        0,      0,      0ull,   0ull},
31913         {"BP"                          ,        16,     1,      128,    "RO",   0,      0,      0ull,   0ull},
31914         {"RESERVED_17_63"              ,        17,     47,     128,    "RAZ",  1,      1,      0,      0},
31915         {"PREAMBLE"                    ,        0,      1,      129,    "R/W",  0,      0,      1ull,   1ull},
31916         {"PAD"                         ,        1,      1,      129,    "R/W",  0,      0,      1ull,   1ull},
31917         {"FCS"                         ,        2,      1,      129,    "R/W",  0,      0,      1ull,   1ull},
31918         {"FORCE_FCS"                   ,        3,      1,      129,    "R/W",  0,      0,      1ull,   1ull},
31919         {"RESERVED_4_63"               ,        4,      60,     129,    "RAZ",  1,      1,      0,      0},
31920         {"BURST"                       ,        0,      16,     130,    "R/W",  0,      0,      8192ull,        8192ull},
31921         {"RESERVED_16_63"              ,        16,     48,     130,    "RAZ",  1,      1,      0,      0},
31922         {"CLK_CNT"                     ,        0,      6,      131,    "R/W",  0,      0,      1ull,   1ull},
31923         {"RESERVED_6_63"               ,        6,      58,     131,    "RAZ",  1,      1,      0,      0},
31924         {"XSCOL_EN"                    ,        0,      1,      132,    "R/W",  0,      0,      1ull,   1ull},
31925         {"XSDEF_EN"                    ,        1,      1,      132,    "R/W",  0,      0,      1ull,   1ull},
31926         {"RESERVED_2_63"               ,        2,      62,     132,    "RAZ",  1,      1,      0,      0},
31927         {"MIN_SIZE"                    ,        0,      8,      133,    "R/W",  0,      0,      59ull,  59ull},
31928         {"RESERVED_8_63"               ,        8,      56,     133,    "RAZ",  1,      1,      0,      0},
31929         {"INTERVAL"                    ,        0,      16,     134,    "R/W",  0,      1,      16ull,  0},
31930         {"RESERVED_16_63"              ,        16,     48,     134,    "RAZ",  1,      1,      0,      0},
31931         {"TIME"                        ,        0,      16,     135,    "R/W",  0,      1,      96ull,  0},
31932         {"RESERVED_16_63"              ,        16,     48,     135,    "RAZ",  1,      1,      0,      0},
31933         {"TIME"                        ,        0,      16,     136,    "RO",   1,      1,      0,      0},
31934         {"RESERVED_16_63"              ,        16,     48,     136,    "RAZ",  1,      1,      0,      0},
31935         {"SEND"                        ,        0,      1,      137,    "R/W",  0,      0,      1ull,   1ull},
31936         {"RESERVED_1_63"               ,        1,      63,     137,    "RAZ",  1,      1,      0,      0},
31937         {"SLOT"                        ,        0,      10,     138,    "R/W",  0,      0,      512ull, 512ull},
31938         {"RESERVED_10_63"              ,        10,     54,     138,    "RAZ",  1,      1,      0,      0},
31939         {"TIME"                        ,        0,      16,     139,    "R/W",  0,      1,      0ull,   0},
31940         {"RESERVED_16_63"              ,        16,     48,     139,    "RAZ",  1,      1,      0,      0},
31941         {"XSCOL"                       ,        0,      32,     140,    "RC/W", 0,      1,      0ull,   0},
31942         {"XSDEF"                       ,        32,     32,     140,    "RC/W", 0,      1,      0ull,   0},
31943         {"MCOL"                        ,        0,      32,     141,    "RC/W", 0,      1,      0ull,   0},
31944         {"SCOL"                        ,        32,     32,     141,    "RC/W", 0,      1,      0ull,   0},
31945         {"OCTS"                        ,        0,      48,     142,    "RC/W", 0,      1,      0ull,   0},
31946         {"RESERVED_48_63"              ,        48,     16,     142,    "RAZ",  1,      1,      0,      0},
31947         {"PKTS"                        ,        0,      32,     143,    "RC/W", 0,      1,      0ull,   0},
31948         {"RESERVED_32_63"              ,        32,     32,     143,    "RAZ",  1,      1,      0,      0},
31949         {"HIST0"                       ,        0,      32,     144,    "RC/W", 0,      1,      0ull,   0},
31950         {"HIST1"                       ,        32,     32,     144,    "RC/W", 0,      1,      0ull,   0},
31951         {"HIST2"                       ,        0,      32,     145,    "RC/W", 0,      1,      0ull,   0},
31952         {"HIST3"                       ,        32,     32,     145,    "RC/W", 0,      1,      0ull,   0},
31953         {"HIST4"                       ,        0,      32,     146,    "RC/W", 0,      1,      0ull,   0},
31954         {"HIST5"                       ,        32,     32,     146,    "RC/W", 0,      1,      0ull,   0},
31955         {"HIST6"                       ,        0,      32,     147,    "RC/W", 0,      1,      0ull,   0},
31956         {"HIST7"                       ,        32,     32,     147,    "RC/W", 0,      1,      0ull,   0},
31957         {"BCST"                        ,        0,      32,     148,    "RC/W", 0,      1,      0ull,   0},
31958         {"MCST"                        ,        32,     32,     148,    "RC/W", 0,      1,      0ull,   0},
31959         {"CTL"                         ,        0,      32,     149,    "RC/W", 0,      1,      0ull,   0},
31960         {"UNDFLW"                      ,        32,     32,     149,    "RC/W", 0,      1,      0ull,   0},
31961         {"RD_CLR"                      ,        0,      1,      150,    "R/W",  0,      0,      0ull,   0ull},
31962         {"RESERVED_1_63"               ,        1,      63,     150,    "RAZ",  1,      1,      0,      0},
31963         {"CNT"                         ,        0,      9,      151,    "R/W",  0,      0,      32ull,  32ull},
31964         {"RESERVED_9_63"               ,        9,      55,     151,    "RAZ",  1,      1,      0,      0},
31965         {"BP"                          ,        0,      4,      152,    "RO",   0,      0,      0ull,   0ull},
31966         {"RESERVED_4_63"               ,        4,      60,     152,    "RAZ",  1,      1,      0,      0},
31967         {"LIMIT"                       ,        0,      5,      153,    "R/W",  0,      0,      16ull,  16ull},
31968         {"RESERVED_5_63"               ,        5,      59,     153,    "RAZ",  1,      1,      0,      0},
31969         {"CORRUPT"                     ,        0,      4,      154,    "R/W",  0,      0,      15ull,  15ull},
31970         {"RESERVED_4_63"               ,        4,      60,     154,    "RAZ",  1,      1,      0,      0},
31971         {"IFG1"                        ,        0,      4,      155,    "R/W",  0,      1,      8ull,   0},
31972         {"IFG2"                        ,        4,      4,      155,    "R/W",  0,      1,      4ull,   0},
31973         {"RESERVED_8_63"               ,        8,      56,     155,    "RAZ",  1,      1,      0,      0},
31974         {"PKO_NXA"                     ,        0,      1,      156,    "R/W",  0,      0,      0ull,   0ull},
31975         {"NCB_NXA"                     ,        1,      1,      156,    "R/W",  0,      0,      0ull,   0ull},
31976         {"UNDFLW"                      ,        2,      4,      156,    "R/W",  0,      0,      0ull,   0ull},
31977         {"RESERVED_6_7"                ,        6,      2,      156,    "RAZ",  0,      0,      0ull,   0ull},
31978         {"XSCOL"                       ,        8,      4,      156,    "R/W",  0,      0,      0ull,   0ull},
31979         {"XSDEF"                       ,        12,     4,      156,    "R/W",  0,      0,      0ull,   0ull},
31980         {"LATE_COL"                    ,        16,     4,      156,    "R/W",  0,      0,      0ull,   0ull},
31981         {"RESERVED_20_63"              ,        20,     44,     156,    "RAZ",  1,      1,      0,      0},
31982         {"PKO_NXA"                     ,        0,      1,      157,    "R/W1C",        0,      0,      0ull,   0ull},
31983         {"NCB_NXA"                     ,        1,      1,      157,    "R/W1C",        0,      0,      0ull,   0ull},
31984         {"UNDFLW"                      ,        2,      4,      157,    "R/W1C",        0,      0,      0ull,   0ull},
31985         {"RESERVED_6_7"                ,        6,      2,      157,    "RAZ",  0,      0,      0ull,   0ull},
31986         {"XSCOL"                       ,        8,      4,      157,    "R/W1C",        0,      0,      0ull,   0ull},
31987         {"XSDEF"                       ,        12,     4,      157,    "R/W1C",        0,      0,      0ull,   0ull},
31988         {"LATE_COL"                    ,        16,     4,      157,    "R/W1C",        0,      0,      0ull,   0ull},
31989         {"RESERVED_20_63"              ,        20,     44,     157,    "RAZ",  1,      1,      0,      0},
31990         {"JAM"                         ,        0,      8,      158,    "R/W",  0,      1,      238ull, 0},
31991         {"RESERVED_8_63"               ,        8,      56,     158,    "RAZ",  1,      1,      0,      0},
31992         {"LFSR"                        ,        0,      16,     159,    "R/W",  0,      1,      65535ull,       0},
31993         {"RESERVED_16_63"              ,        16,     48,     159,    "RAZ",  1,      1,      0,      0},
31994         {"IGN_FULL"                    ,        0,      4,      160,    "R/W",  0,      0,      0ull,   0ull},
31995         {"BP"                          ,        4,      4,      160,    "R/W",  0,      0,      0ull,   0ull},
31996         {"EN"                          ,        8,      4,      160,    "R/W",  0,      0,      0ull,   0ull},
31997         {"RESERVED_12_63"              ,        12,     52,     160,    "RAZ",  1,      1,      0,      0},
31998         {"DMAC"                        ,        0,      48,     161,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
31999         {"RESERVED_48_63"              ,        48,     16,     161,    "RAZ",  1,      1,      0,      0},
32000         {"TYPE"                        ,        0,      16,     162,    "R/W",  0,      0,      34824ull,       34824ull},
32001         {"RESERVED_16_63"              ,        16,     48,     162,    "RAZ",  1,      1,      0,      0},
32002         {"PRTS"                        ,        0,      5,      163,    "R/W",  0,      1,      1ull,   0},
32003         {"RESERVED_5_63"               ,        5,      59,     163,    "RAZ",  1,      1,      0,      0},
32004         {"CONT_PKT"                    ,        0,      1,      164,    "R/W",  0,      1,      0ull,   0},
32005         {"TPA_CLR"                     ,        1,      1,      164,    "R/W",  0,      1,      0ull,   0},
32006         {"RESERVED_2_63"               ,        2,      62,     164,    "RAZ",  0,      0,      0ull,   0ull},
32007         {"DRAIN"                       ,        0,      16,     165,    "R/W",  0,      0,      0ull,   0ull},
32008         {"RESERVED_16_63"              ,        16,     48,     165,    "RAZ",  1,      1,      0,      0},
32009         {"MAX1"                        ,        0,      8,      166,    "R/W",  0,      1,      8ull,   0},
32010         {"MAX2"                        ,        8,      8,      166,    "R/W",  0,      1,      4ull,   0},
32011         {"SLICE"                       ,        16,     7,      166,    "R/W",  0,      1,      0ull,   0},
32012         {"RESERVED_23_63"              ,        23,     41,     166,    "RAZ",  1,      1,      0,      0},
32013         {"ROUND"                       ,        0,      16,     167,    "R/W",  0,      1,      0ull,   0},
32014         {"RESERVED_16_63"              ,        16,     48,     167,    "RAZ",  1,      1,      0,      0},
32015         {"THRESH"                      ,        0,      6,      168,    "R/W",  0,      1,      4ull,   0},
32016         {"RESERVED_6_63"               ,        6,      58,     168,    "RAZ",  1,      1,      0,      0},
32017         {"TX_OE"                       ,        0,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
32018         {"RX_XOR"                      ,        1,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
32019         {"INT_EN"                      ,        2,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
32020         {"INT_TYPE"                    ,        3,      1,      169,    "R/W",  0,      0,      0ull,   0ull},
32021         {"FIL_CNT"                     ,        4,      4,      169,    "R/W",  0,      0,      0ull,   0ull},
32022         {"FIL_SEL"                     ,        8,      4,      169,    "R/W",  0,      0,      0ull,   0ull},
32023         {"RESERVED_12_63"              ,        12,     52,     169,    "RAZ",  1,      1,      0,      0},
32024         {"TYPE"                        ,        0,      16,     170,    "WO",   0,      0,      0ull,   0ull},
32025         {"RESERVED_16_63"              ,        16,     48,     170,    "RAZ",  1,      1,      0,      0},
32026         {"DAT"                         ,        0,      16,     171,    "RO",   0,      0,      0ull,   0ull},
32027         {"RESERVED_16_63"              ,        16,     48,     171,    "RAZ",  1,      1,      0,      0},
32028         {"CLR"                         ,        0,      16,     172,    "WO",   0,      0,      0ull,   0ull},
32029         {"RESERVED_16_63"              ,        16,     48,     172,    "RAZ",  1,      1,      0,      0},
32030         {"SET"                         ,        0,      16,     173,    "WO",   0,      0,      0ull,   0ull},
32031         {"RESERVED_16_63"              ,        16,     48,     173,    "RAZ",  1,      1,      0,      0},
32032         {"ICD"                         ,        0,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32033         {"IBD"                         ,        1,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32034         {"ICRP1"                       ,        2,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32035         {"ICRP0"                       ,        3,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32036         {"ICRN1"                       ,        4,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32037         {"ICRN0"                       ,        5,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32038         {"IBRQ1"                       ,        6,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32039         {"IBRQ0"                       ,        7,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32040         {"ICNRT"                       ,        8,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32041         {"IBR1"                        ,        9,      1,      174,    "RO",   0,      0,      0ull,   0ull},
32042         {"IBR0"                        ,        10,     1,      174,    "RO",   0,      0,      0ull,   0ull},
32043         {"IBDR1"                       ,        11,     1,      174,    "RO",   0,      0,      0ull,   0ull},
32044         {"IBDR0"                       ,        12,     1,      174,    "RO",   0,      0,      0ull,   0ull},
32045         {"ICNR0"                       ,        13,     1,      174,    "RO",   0,      0,      0ull,   0ull},
32046         {"ICNR1"                       ,        14,     1,      174,    "RO",   0,      0,      0ull,   0ull},
32047         {"ICR1"                        ,        15,     1,      174,    "RO",   0,      0,      0ull,   0ull},
32048         {"ICR0"                        ,        16,     1,      174,    "RO",   0,      0,      0ull,   0ull},
32049         {"ICNRCB"                      ,        17,     1,      174,    "RO",   0,      0,      0ull,   0ull},
32050         {"RESERVED_18_63"              ,        18,     46,     174,    "RAZ",  1,      1,      0,      0},
32051         {"FAU_END"                     ,        0,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
32052         {"DWB_ENB"                     ,        1,      1,      175,    "R/W",  0,      0,      1ull,   1ull},
32053         {"PKO_ENB"                     ,        2,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
32054         {"INB_MAT"                     ,        3,      1,      175,    "R/W1C",        0,      0,      0ull,   0ull},
32055         {"OUTB_MAT"                    ,        4,      1,      175,    "R/W1C",        0,      0,      0ull,   0ull},
32056         {"RESERVED_5_63"               ,        5,      59,     175,    "RAZ",  1,      1,      0,      0},
32057         {"CNT_VAL"                     ,        0,      15,     176,    "R/W",  0,      0,      0ull,   0ull},
32058         {"CNT_ENB"                     ,        15,     1,      176,    "R/W",  0,      0,      0ull,   0ull},
32059         {"RESERVED_16_63"              ,        16,     48,     176,    "RAZ",  1,      1,      0,      0},
32060         {"TOUT_VAL"                    ,        0,      12,     177,    "R/W",  0,      0,      4ull,   4ull},
32061         {"TOUT_ENB"                    ,        12,     1,      177,    "R/W",  0,      0,      1ull,   0ull},
32062         {"RESERVED_13_63"              ,        13,     51,     177,    "RAZ",  1,      1,      0,      0},
32063         {"CNT_VAL"                     ,        0,      15,     178,    "R/W",  0,      0,      0ull,   0ull},
32064         {"CNT_ENB"                     ,        15,     1,      178,    "R/W",  0,      0,      0ull,   0ull},
32065         {"RESERVED_16_63"              ,        16,     48,     178,    "RAZ",  1,      1,      0,      0},
32066         {"SRC"                         ,        0,      8,      179,    "R/W",  0,      1,      0ull,   0},
32067         {"DST"                         ,        8,      9,      179,    "R/W",  0,      1,      0ull,   0},
32068         {"OPC"                         ,        17,     4,      179,    "R/W",  0,      1,      0ull,   0},
32069         {"MASK"                        ,        21,     8,      179,    "R/W",  0,      1,      0ull,   0},
32070         {"RESERVED_29_63"              ,        29,     35,     179,    "RAZ",  1,      1,      0,      0},
32071         {"SRC"                         ,        0,      8,      180,    "R/W",  0,      1,      0ull,   0},
32072         {"DST"                         ,        8,      9,      180,    "R/W",  0,      1,      0ull,   0},
32073         {"OPC"                         ,        17,     4,      180,    "R/W",  0,      1,      0ull,   0},
32074         {"MASK"                        ,        21,     8,      180,    "R/W",  0,      1,      0ull,   0},
32075         {"RESERVED_29_63"              ,        29,     35,     180,    "RAZ",  1,      1,      0,      0},
32076         {"DATA"                        ,        0,      64,     181,    "R/W",  0,      1,      0ull,   0},
32077         {"DATA"                        ,        0,      64,     182,    "R/W",  0,      1,      0ull,   0},
32078         {"NP_SOP"                      ,        0,      1,      183,    "R/W",  0,      0,      0ull,   0ull},
32079         {"NP_EOP"                      ,        1,      1,      183,    "R/W",  0,      0,      0ull,   0ull},
32080         {"P_SOP"                       ,        2,      1,      183,    "R/W",  0,      0,      0ull,   0ull},
32081         {"P_EOP"                       ,        3,      1,      183,    "R/W",  0,      0,      0ull,   0ull},
32082         {"NP_DAT"                      ,        4,      1,      183,    "R/W",  0,      0,      0ull,   0ull},
32083         {"P_DAT"                       ,        5,      1,      183,    "R/W",  0,      0,      0ull,   0ull},
32084         {"RESERVED_6_63"               ,        6,      58,     183,    "RAZ",  1,      1,      0,      0},
32085         {"NP_SOP"                      ,        0,      1,      184,    "R/W1C",        0,      0,      0ull,   0ull},
32086         {"NP_EOP"                      ,        1,      1,      184,    "R/W1C",        0,      0,      0ull,   0ull},
32087         {"P_SOP"                       ,        2,      1,      184,    "R/W1C",        0,      0,      0ull,   0ull},
32088         {"P_EOP"                       ,        3,      1,      184,    "R/W1C",        0,      0,      0ull,   0ull},
32089         {"NP_DAT"                      ,        4,      1,      184,    "R/W1C",        0,      0,      0ull,   0ull},
32090         {"P_DAT"                       ,        5,      1,      184,    "R/W1C",        0,      0,      0ull,   0ull},
32091         {"RESERVED_6_63"               ,        6,      58,     184,    "RAZ",  1,      1,      0,      0},
32092         {"CNT_VAL"                     ,        0,      15,     185,    "R/W",  0,      0,      0ull,   0ull},
32093         {"CNT_ENB"                     ,        15,     1,      185,    "R/W",  0,      0,      0ull,   0ull},
32094         {"RESERVED_16_63"              ,        16,     48,     185,    "RAZ",  1,      1,      0,      0},
32095         {"CNT_VAL"                     ,        0,      15,     186,    "R/W",  0,      0,      0ull,   0ull},
32096         {"CNT_ENB"                     ,        15,     1,      186,    "R/W",  0,      0,      0ull,   0ull},
32097         {"RESERVED_16_63"              ,        16,     48,     186,    "RAZ",  1,      1,      0,      0},
32098         {"CNT_VAL"                     ,        0,      15,     187,    "R/W",  0,      0,      0ull,   0ull},
32099         {"CNT_ENB"                     ,        15,     1,      187,    "R/W",  0,      0,      0ull,   0ull},
32100         {"RESERVED_16_63"              ,        16,     48,     187,    "RAZ",  1,      1,      0,      0},
32101         {"SRC"                         ,        0,      9,      188,    "R/W",  0,      1,      0ull,   0},
32102         {"DST"                         ,        9,      8,      188,    "R/W",  0,      1,      0ull,   0},
32103         {"EOT"                         ,        17,     1,      188,    "R/W",  0,      1,      0ull,   0},
32104         {"MASK"                        ,        18,     8,      188,    "R/W",  0,      1,      0ull,   0},
32105         {"RESERVED_26_63"              ,        26,     38,     188,    "RAZ",  1,      1,      0,      0},
32106         {"SRC"                         ,        0,      9,      189,    "R/W",  0,      1,      0ull,   0},
32107         {"DST"                         ,        9,      8,      189,    "R/W",  0,      1,      0ull,   0},
32108         {"EOT"                         ,        17,     1,      189,    "R/W",  0,      1,      0ull,   0},
32109         {"MASK"                        ,        18,     8,      189,    "R/W",  0,      1,      0ull,   0},
32110         {"RESERVED_26_63"              ,        26,     38,     189,    "RAZ",  1,      1,      0,      0},
32111         {"DATA"                        ,        0,      64,     190,    "R/W",  0,      1,      0ull,   0},
32112         {"DATA"                        ,        0,      64,     191,    "R/W",  0,      1,      0ull,   0},
32113         {"CNT_VAL"                     ,        0,      15,     192,    "R/W",  0,      0,      0ull,   0ull},
32114         {"CNT_ENB"                     ,        15,     1,      192,    "R/W",  0,      0,      0ull,   0ull},
32115         {"RESERVED_16_63"              ,        16,     48,     192,    "RAZ",  1,      1,      0,      0},
32116         {"CNT_VAL"                     ,        0,      15,     193,    "R/W",  0,      0,      0ull,   0ull},
32117         {"CNT_ENB"                     ,        15,     1,      193,    "R/W",  0,      0,      0ull,   0ull},
32118         {"RESERVED_16_63"              ,        16,     48,     193,    "RAZ",  1,      1,      0,      0},
32119         {"CNT_VAL"                     ,        0,      15,     194,    "R/W",  0,      0,      0ull,   0ull},
32120         {"CNT_ENB"                     ,        15,     1,      194,    "R/W",  0,      0,      0ull,   0ull},
32121         {"RESERVED_16_63"              ,        16,     48,     194,    "RAZ",  1,      1,      0,      0},
32122         {"PORT"                        ,        0,      6,      195,    "RO",   0,      1,      0ull,   0},
32123         {"RESERVED_6_63"               ,        6,      58,     195,    "RAZ",  1,      1,      0,      0},
32124         {"SKIP_SZ"                     ,        0,      6,      196,    "R/W",  0,      0,      0ull,   0ull},
32125         {"RESERVED_6_63"               ,        6,      58,     196,    "RAZ",  1,      1,      0,      0},
32126         {"BACK"                        ,        0,      4,      197,    "R/W",  0,      0,      0ull,   0ull},
32127         {"RESERVED_4_63"               ,        4,      60,     197,    "RAZ",  1,      1,      0,      0},
32128         {"BACK"                        ,        0,      4,      198,    "R/W",  0,      0,      0ull,   0ull},
32129         {"RESERVED_4_63"               ,        4,      60,     198,    "RAZ",  1,      1,      0,      0},
32130         {"PWP"                         ,        0,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32131         {"IPD_NEW"                     ,        1,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32132         {"IPD_OLD"                     ,        2,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32133         {"PRC_OFF"                     ,        3,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32134         {"PWQ0"                        ,        4,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32135         {"PWQ1"                        ,        5,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32136         {"PBM_WORD"                    ,        6,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32137         {"PBM0"                        ,        7,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32138         {"PBM1"                        ,        8,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32139         {"PBM2"                        ,        9,      1,      199,    "RO",   0,      0,      0ull,   0ull},
32140         {"PBM3"                        ,        10,     1,      199,    "RO",   0,      0,      0ull,   0ull},
32141         {"IPQ_PBE0"                    ,        11,     1,      199,    "RO",   0,      0,      0ull,   0ull},
32142         {"IPQ_PBE1"                    ,        12,     1,      199,    "RO",   0,      0,      0ull,   0ull},
32143         {"PWQ_POW"                     ,        13,     1,      199,    "RO",   0,      0,      0ull,   0ull},
32144         {"PWQ_WP1"                     ,        14,     1,      199,    "RO",   0,      0,      0ull,   0ull},
32145         {"PWQ_WQED"                    ,        15,     1,      199,    "RO",   0,      0,      0ull,   0ull},
32146         {"RESERVED_16_63"              ,        16,     48,     199,    "RAZ",  1,      1,      0,      0},
32147         {"PRT_ENB"                     ,        0,      36,     200,    "R/W",  0,      0,      0ull,   0ull},
32148         {"RESERVED_36_63"              ,        36,     28,     200,    "RAZ",  1,      1,      0,      0},
32149         {"CLK_CNT"                     ,        0,      64,     201,    "RO",   0,      0,      0ull,   0ull},
32150         {"IPD_EN"                      ,        0,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
32151         {"OPC_MODE"                    ,        1,      2,      202,    "R/W",  0,      0,      0ull,   0ull},
32152         {"PBP_EN"                      ,        3,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
32153         {"WQE_LEND"                    ,        4,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
32154         {"PKT_LEND"                    ,        5,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
32155         {"NADDBUF"                     ,        6,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
32156         {"ADDPKT"                      ,        7,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
32157         {"RESET"                       ,        8,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
32158         {"LEN_M8"                      ,        9,      1,      202,    "R/W",  0,      0,      0ull,   1ull},
32159         {"PKT_OFF"                     ,        10,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
32160         {"IPD_FULL"                    ,        11,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
32161         {"RESERVED_12_63"              ,        12,     52,     202,    "RAZ",  1,      1,      0,      0},
32162         {"PRC_PAR0"                    ,        0,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32163         {"PRC_PAR1"                    ,        1,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32164         {"PRC_PAR2"                    ,        2,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32165         {"PRC_PAR3"                    ,        3,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32166         {"BP_SUB"                      ,        4,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32167         {"DC_OVR"                      ,        5,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32168         {"CC_OVR"                      ,        6,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32169         {"C_COLL"                      ,        7,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32170         {"D_COLL"                      ,        8,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32171         {"BC_OVR"                      ,        9,      1,      203,    "R/W",  0,      0,      0ull,   0ull},
32172         {"RESERVED_10_63"              ,        10,     54,     203,    "RAZ",  1,      1,      0,      0},
32173         {"PRC_PAR0"                    ,        0,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32174         {"PRC_PAR1"                    ,        1,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32175         {"PRC_PAR2"                    ,        2,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32176         {"PRC_PAR3"                    ,        3,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32177         {"BP_SUB"                      ,        4,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32178         {"DC_OVR"                      ,        5,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32179         {"CC_OVR"                      ,        6,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32180         {"C_COLL"                      ,        7,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32181         {"D_COLL"                      ,        8,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32182         {"BC_OVR"                      ,        9,      1,      204,    "R/W1C",        0,      0,      0ull,   0ull},
32183         {"RESERVED_10_63"              ,        10,     54,     204,    "RAZ",  1,      1,      0,      0},
32184         {"SKIP_SZ"                     ,        0,      6,      205,    "R/W",  0,      0,      0ull,   0ull},
32185         {"RESERVED_6_63"               ,        6,      58,     205,    "RAZ",  1,      1,      0,      0},
32186         {"MB_SIZE"                     ,        0,      12,     206,    "R/W",  0,      0,      32ull,  32ull},
32187         {"RESERVED_12_63"              ,        12,     52,     206,    "RAZ",  1,      1,      0,      0},
32188         {"PTR"                         ,        0,      29,     207,    "RO",   1,      1,      0,      0},
32189         {"RESERVED_29_63"              ,        29,     35,     207,    "RAZ",  1,      1,      0,      0},
32190         {"PAGE_CNT"                    ,        0,      17,     208,    "R/W",  0,      0,      0ull,   0ull},
32191         {"BP_ENB"                      ,        17,     1,      208,    "R/W",  0,      0,      0ull,   0ull},
32192         {"RESERVED_18_63"              ,        18,     46,     208,    "RAZ",  1,      1,      0,      0},
32193         {"CNT_VAL"                     ,        0,      25,     209,    "RO",   0,      1,      0ull,   0},
32194         {"RESERVED_25_63"              ,        25,     39,     209,    "RAZ",  1,      1,      0,      0},
32195         {"RADDR"                       ,        0,      3,      210,    "R/W",  0,      0,      0ull,   0ull},
32196         {"CENA"                        ,        3,      1,      210,    "R/W",  0,      0,      1ull,   1ull},
32197         {"PTR"                         ,        4,      29,     210,    "RO",   1,      1,      0,      0},
32198         {"PRADDR"                      ,        33,     3,      210,    "RO",   1,      1,      0,      0},
32199         {"MAX_PKT"                     ,        36,     3,      210,    "RO",   0,      0,      5ull,   5ull},
32200         {"RESERVED_39_63"              ,        39,     25,     210,    "RAZ",  1,      1,      0,      0},
32201         {"RADDR"                       ,        0,      7,      211,    "R/W",  0,      0,      0ull,   0ull},
32202         {"CENA"                        ,        7,      1,      211,    "R/W",  0,      0,      1ull,   1ull},
32203         {"PTR"                         ,        8,      29,     211,    "RO",   1,      1,      0,      0},
32204         {"MAX_PKT"                     ,        37,     7,      211,    "RO",   0,      0,      36ull,  36ull},
32205         {"RESERVED_44_63"              ,        44,     20,     211,    "RAZ",  1,      1,      0,      0},
32206         {"WQE_PCNT"                    ,        0,      7,      212,    "RO",   0,      0,      0ull,   0ull},
32207         {"PKT_PCNT"                    ,        7,      7,      212,    "RO",   0,      0,      0ull,   0ull},
32208         {"PFIF_CNT"                    ,        14,     3,      212,    "RO",   0,      0,      0ull,   0ull},
32209         {"WQEV_CNT"                    ,        17,     1,      212,    "RO",   0,      0,      0ull,   0ull},
32210         {"PKTV_CNT"                    ,        18,     1,      212,    "RO",   0,      0,      0ull,   0ull},
32211         {"RESERVED_19_63"              ,        19,     45,     212,    "RAZ",  1,      1,      0,      0},
32212         {"RADDR"                       ,        0,      8,      213,    "R/W",  0,      0,      0ull,   0ull},
32213         {"CENA"                        ,        8,      1,      213,    "R/W",  0,      0,      1ull,   1ull},
32214         {"PTR"                         ,        9,      29,     213,    "RO",   1,      1,      0,      0},
32215         {"PRADDR"                      ,        38,     8,      213,    "RO",   1,      1,      0,      0},
32216         {"WRADDR"                      ,        46,     8,      213,    "RO",   1,      1,      0,      0},
32217         {"MAX_CNTS"                    ,        54,     7,      213,    "RO",   0,      0,      64ull,  64ull},
32218         {"RESERVED_61_63"              ,        61,     3,      213,    "RAZ",  1,      1,      0,      0},
32219         {"PASS"                        ,        0,      32,     214,    "R/W",  0,      1,      0ull,   0},
32220         {"DROP"                        ,        32,     32,     214,    "R/W",  0,      1,      0ull,   0},
32221         {"Q0_PCNT"                     ,        0,      32,     215,    "RO",   0,      0,      0ull,   0ull},
32222         {"RESERVED_32_63"              ,        32,     32,     215,    "RAZ",  1,      1,      0,      0},
32223         {"PRT_ENB"                     ,        0,      36,     216,    "R/W",  0,      0,      0ull,   0ull},
32224         {"AVG_DLY"                     ,        36,     14,     216,    "R/W",  0,      1,      0ull,   0},
32225         {"PRB_DLY"                     ,        50,     14,     216,    "R/W",  0,      0,      0ull,   0ull},
32226         {"PRB_CON"                     ,        0,      32,     217,    "R/W",  0,      1,      0ull,   0},
32227         {"AVG_CON"                     ,        32,     8,      217,    "R/W",  0,      1,      0ull,   0},
32228         {"NEW_CON"                     ,        40,     8,      217,    "R/W",  0,      1,      0ull,   0},
32229         {"USE_PCNT"                    ,        48,     1,      217,    "R/W",  0,      0,      0ull,   0ull},
32230         {"RESERVED_49_63"              ,        49,     15,     217,    "RAZ",  1,      1,      0,      0},
32231         {"PAGE_CNT"                    ,        0,      25,     218,    "R/W",  1,      0,      0,      0ull},
32232         {"PORT"                        ,        25,     6,      218,    "R/W",  1,      0,      0,      0ull},
32233         {"RESERVED_31_63"              ,        31,     33,     218,    "RAZ",  1,      1,      0,      0},
32234         {"PORT_BIT"                    ,        0,      32,     219,    "R/W",  0,      0,      4294967295ull,  4294967295ull},
32235         {"RESERVED_32_63"              ,        32,     32,     219,    "RAZ",  1,      1,      0,      0},
32236         {"WQE_POOL"                    ,        0,      3,      220,    "R/W",  0,      0,      1ull,   1ull},
32237         {"RESERVED_3_63"               ,        3,      61,     220,    "RAZ",  1,      1,      0,      0},
32238         {"PTR"                         ,        0,      29,     221,    "RO",   1,      1,      0,      0},
32239         {"RESERVED_29_63"              ,        29,     35,     221,    "RAZ",  1,      1,      0,      0},
32240         {"MEM0"                        ,        0,      1,      222,    "RO",   0,      0,      0ull,   0ull},
32241         {"MEM1"                        ,        1,      1,      222,    "RO",   0,      0,      0ull,   0ull},
32242         {"RRC"                         ,        2,      1,      222,    "RO",   0,      0,      0ull,   0ull},
32243         {"RESERVED_3_63"               ,        3,      61,     222,    "RAZ",  1,      1,      0,      0},
32244         {"MEM0_ERR"                    ,        0,      7,      223,    "R/W",  0,      0,      0ull,   0ull},
32245         {"MEM1_ERR"                    ,        7,      7,      223,    "R/W",  0,      0,      0ull,   0ull},
32246         {"RESERVED_14_63"              ,        14,     50,     223,    "RAZ",  1,      1,      0,      0},
32247         {"KED0_SBE"                    ,        0,      1,      224,    "R/W",  0,      0,      0ull,   0ull},
32248         {"KED0_DBE"                    ,        1,      1,      224,    "R/W",  0,      0,      0ull,   0ull},
32249         {"KED1_SBE"                    ,        2,      1,      224,    "R/W",  0,      0,      0ull,   0ull},
32250         {"KED1_DBE"                    ,        3,      1,      224,    "R/W",  0,      0,      0ull,   0ull},
32251         {"RESERVED_4_63"               ,        4,      60,     224,    "RAZ",  1,      1,      0,      0},
32252         {"KED0_SBE"                    ,        0,      1,      225,    "R/W1C",        0,      0,      0ull,   0ull},
32253         {"KED0_DBE"                    ,        1,      1,      225,    "R/W1C",        0,      0,      0ull,   0ull},
32254         {"KED1_SBE"                    ,        2,      1,      225,    "R/W1C",        0,      0,      0ull,   0ull},
32255         {"KED1_DBE"                    ,        3,      1,      225,    "R/W1C",        0,      0,      0ull,   0ull},
32256         {"RESERVED_4_63"               ,        4,      60,     225,    "RAZ",  1,      1,      0,      0},
32257         {"WLB_DAT"                     ,        0,      4,      226,    "RO",   0,      0,      0ull,   0ull},
32258         {"STIN_MSK"                    ,        4,      1,      226,    "RO",   0,      0,      0ull,   0ull},
32259         {"DT"                          ,        5,      1,      226,    "RO",   0,      0,      0ull,   0ull},
32260         {"DTCNT"                       ,        6,      13,     226,    "RO",   0,      0,      0ull,   0ull},
32261         {"WLB_MSK"                     ,        19,     4,      226,    "RO",   0,      0,      0ull,   0ull},
32262         {"DTBNK"                       ,        23,     1,      226,    "RO",   0,      0,      0ull,   0ull},
32263         {"RESERVED_24_63"              ,        24,     40,     226,    "RAZ",  0,      0,      0ull,   0ull},
32264         {"L2T"                         ,        0,      9,      227,    "RO",   0,      0,      0ull,   0ull},
32265         {"VAB_VWCF"                    ,        9,      1,      227,    "RO",   0,      0,      0ull,   0ull},
32266         {"LRF"                         ,        10,     2,      227,    "RO",   0,      0,      0ull,   0ull},
32267         {"VWDF"                        ,        12,     4,      227,    "RO",   0,      0,      0ull,   0ull},
32268         {"RESERVED_16_63"              ,        16,     48,     227,    "RAZ",  0,      0,      0ull,   0ull},
32269         {"XRDDAT"                      ,        0,      1,      228,    "RO",   0,      0,      0ull,   0ull},
32270         {"XRDMSK"                      ,        1,      1,      228,    "RO",   0,      0,      0ull,   0ull},
32271         {"PICBST"                      ,        2,      1,      228,    "RO",   0,      0,      0ull,   0ull},
32272         {"IPCBST"                      ,        3,      1,      228,    "RO",   0,      0,      0ull,   0ull},
32273         {"RHDB"                        ,        4,      4,      228,    "RO",   0,      0,      0ull,   0ull},
32274         {"RMDB"                        ,        8,      4,      228,    "RO",   0,      0,      0ull,   0ull},
32275         {"MRB"                         ,        12,     4,      228,    "RO",   0,      0,      0ull,   0ull},
32276         {"RESERVED_16_63"              ,        16,     48,     228,    "RAZ",  0,      0,      0ull,   0ull},
32277         {"LRF_ARB_MODE"                ,        0,      1,      229,    "R/W",  0,      0,      1ull,   1ull},
32278         {"RFB_ARB_MODE"                ,        1,      1,      229,    "R/W",  0,      0,      1ull,   1ull},
32279         {"RSP_ARB_MODE"                ,        2,      1,      229,    "R/W",  0,      0,      1ull,   1ull},
32280         {"MWF_CRD"                     ,        3,      4,      229,    "R/W",  0,      0,      2ull,   2ull},
32281         {"IDXALIAS"                    ,        7,      1,      229,    "R/W",  0,      0,      0ull,   1ull},
32282         {"FPEN"                        ,        8,      1,      229,    "R/W",  0,      0,      0ull,   0ull},
32283         {"FPEMPTY"                     ,        9,      1,      229,    "R/W",  0,      0,      0ull,   0ull},
32284         {"FPEXP"                       ,        10,     4,      229,    "R/W",  0,      0,      0ull,   0ull},
32285         {"DFILL_DIS"                   ,        14,     1,      229,    "R/W",  0,      0,      0ull,   0ull},
32286         {"RESERVED_15_17"              ,        15,     3,      229,    "RAZ",  0,      0,      0ull,   0ull},
32287         {"LBIST"                       ,        18,     1,      229,    "R/W",  0,      0,      0ull,   0ull},
32288         {"BSTRUN"                      ,        19,     1,      229,    "RO",   0,      0,      0ull,   0ull},
32289         {"RESERVED_20_63"              ,        20,     44,     229,    "RAZ",  1,      1,      0,      0},
32290         {"L2T"                         ,        0,      1,      230,    "R/W",  0,      0,      0ull,   0ull},
32291         {"L2D"                         ,        1,      1,      230,    "R/W",  0,      0,      0ull,   0ull},
32292         {"FINV"                        ,        2,      1,      230,    "R/W",  0,      0,      0ull,   0ull},
32293         {"SET"                         ,        3,      3,      230,    "R/W",  0,      0,      0ull,   0ull},
32294         {"PPNUM"                       ,        6,      4,      230,    "R/W",  0,      0,      0ull,   0ull},
32295         {"LFB_DMP"                     ,        10,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
32296         {"LFB_ENUM"                    ,        11,     4,      230,    "R/W",  0,      0,      0ull,   0ull},
32297         {"RESERVED_15_63"              ,        15,     49,     230,    "RAZ",  0,      0,      0ull,   0ull},
32298         {"DT_TAG"                      ,        0,      29,     231,    "RO",   0,      0,      0ull,   0ull},
32299         {"DT_VLD"                      ,        29,     1,      231,    "RO",   0,      0,      0ull,   0ull},
32300         {"RESERVED_30_30"              ,        30,     1,      231,    "RAZ",  0,      0,      0ull,   0ull},
32301         {"DTENA"                       ,        31,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
32302         {"RESERVED_32_63"              ,        32,     32,     231,    "RAZ",  0,      0,      0ull,   0ull},
32303         {"LCK_ENA"                     ,        0,      1,      232,    "R/W",  0,      0,      0ull,   0ull},
32304         {"RESERVED_1_3"                ,        1,      3,      232,    "RAZ",  0,      0,      0ull,   0ull},
32305         {"LCK_BASE"                    ,        4,      27,     232,    "R/W",  0,      0,      0ull,   0ull},
32306         {"RESERVED_31_63"              ,        31,     33,     232,    "RAZ",  0,      0,      0ull,   0ull},
32307         {"LCK_OFFSET"                  ,        0,      10,     233,    "R/W",  0,      0,      0ull,   0ull},
32308         {"RESERVED_10_63"              ,        10,     54,     233,    "RAZ",  0,      0,      0ull,   0ull},
32309         {"VLD"                         ,        0,      1,      234,    "RO",   0,      0,      0ull,   0ull},
32310         {"CMD"                         ,        1,      4,      234,    "RO",   0,      0,      0ull,   0ull},
32311         {"SID"                         ,        5,      9,      234,    "RO",   0,      0,      0ull,   0ull},
32312         {"VABNUM"                      ,        14,     4,      234,    "RO",   0,      0,      0ull,   0ull},
32313         {"SET"                         ,        18,     3,      234,    "RO",   0,      0,      0ull,   0ull},
32314         {"IHD"                         ,        21,     1,      234,    "RO",   0,      0,      0ull,   0ull},
32315         {"ITL"                         ,        22,     1,      234,    "RO",   0,      0,      0ull,   0ull},
32316         {"INXT"                        ,        23,     4,      234,    "RO",   0,      0,      0ull,   0ull},
32317         {"VAM"                         ,        27,     1,      234,    "RO",   0,      0,      0ull,   0ull},
32318         {"STCFL"                       ,        28,     1,      234,    "RO",   0,      0,      0ull,   0ull},
32319         {"STINV"                       ,        29,     1,      234,    "RO",   0,      0,      0ull,   0ull},
32320         {"STPND"                       ,        30,     1,      234,    "RO",   0,      0,      0ull,   0ull},
32321         {"STCPND"                      ,        31,     1,      234,    "RO",   0,      0,      0ull,   0ull},
32322         {"RESERVED_32_63"              ,        32,     32,     234,    "RAZ",  0,      0,      0ull,   0ull},
32323         {"VLD"                         ,        0,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32324         {"WTPRB"                       ,        1,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32325         {"PRBRTY"                      ,        2,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32326         {"WTMFL"                       ,        3,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32327         {"WTVTM"                       ,        4,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32328         {"WTSTRSC"                     ,        5,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32329         {"WTSTRSP"                     ,        6,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32330         {"WTSTDT"                      ,        7,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32331         {"WTRDA"                       ,        8,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32332         {"WTSTM"                       ,        9,      1,      235,    "RO",   0,      0,      0ull,   0ull},
32333         {"WTWRM"                       ,        10,     1,      235,    "RO",   0,      0,      0ull,   0ull},
32334         {"WTWHF"                       ,        11,     1,      235,    "RO",   0,      0,      0ull,   0ull},
32335         {"WTWHP"                       ,        12,     1,      235,    "RO",   0,      0,      0ull,   0ull},
32336         {"WTDQ"                        ,        13,     1,      235,    "RO",   0,      0,      0ull,   0ull},
32337         {"WTDW"                        ,        14,     1,      235,    "RO",   0,      0,      0ull,   0ull},
32338         {"WTRSP"                       ,        15,     1,      235,    "RO",   0,      0,      0ull,   0ull},
32339         {"BID"                         ,        16,     2,      235,    "RO",   0,      0,      0ull,   0ull},
32340         {"DSGOING"                     ,        18,     1,      235,    "RO",   0,      0,      0ull,   0ull},
32341         {"RESERVED_19_63"              ,        19,     45,     235,    "RAZ",  0,      0,      0ull,   0ull},
32342         {"LFB_IDX"                     ,        0,      11,     236,    "RO",   0,      0,      0ull,   0ull},
32343         {"LFB_TAG"                     ,        11,     16,     236,    "RO",   0,      0,      0ull,   0ull},
32344         {"RESERVED_27_63"              ,        27,     37,     236,    "RAZ",  0,      0,      0ull,   0ull},
32345         {"LFB_HWM"                     ,        0,      4,      237,    "R/W",  0,      0,      15ull,  15ull},
32346         {"STPARTDIS"                   ,        4,      1,      237,    "R/W",  0,      0,      0ull,   0ull},
32347         {"RESERVED_5_63"               ,        5,      59,     237,    "RAZ",  0,      0,      0ull,   0ull},
32348         {"PFCNT0"                      ,        0,      36,     238,    "RO",   0,      0,      0ull,   0ull},
32349         {"RESERVED_36_63"              ,        36,     28,     238,    "RAZ",  0,      0,      0ull,   0ull},
32350         {"CNT0SEL"                     ,        0,      6,      239,    "R/W",  0,      0,      0ull,   0ull},
32351         {"CNT0CLR"                     ,        6,      1,      239,    "R/W",  0,      0,      0ull,   0ull},
32352         {"CNT0ENA"                     ,        7,      1,      239,    "R/W",  0,      0,      0ull,   0ull},
32353         {"CNT1SEL"                     ,        8,      6,      239,    "R/W",  0,      0,      0ull,   0ull},
32354         {"CNT1CLR"                     ,        14,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32355         {"CNT1ENA"                     ,        15,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32356         {"CNT2SEL"                     ,        16,     6,      239,    "R/W",  0,      0,      0ull,   0ull},
32357         {"CNT2CLR"                     ,        22,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32358         {"CNT2ENA"                     ,        23,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32359         {"CNT3SEL"                     ,        24,     6,      239,    "R/W",  0,      0,      0ull,   0ull},
32360         {"CNT3CLR"                     ,        30,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32361         {"CNT3ENA"                     ,        31,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32362         {"CNT0RDCLR"                   ,        32,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32363         {"CNT1RDCLR"                   ,        33,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32364         {"CNT2RDCLR"                   ,        34,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32365         {"CNT3RDCLR"                   ,        35,     1,      239,    "R/W",  0,      0,      0ull,   0ull},
32366         {"RESERVED_36_63"              ,        36,     28,     239,    "RAZ",  0,      0,      0ull,   0ull},
32367         {"UMSK0"                       ,        0,      8,      240,    "R/W",  0,      0,      0ull,   0ull},
32368         {"UMSK1"                       ,        8,      8,      240,    "R/W",  0,      0,      0ull,   0ull},
32369         {"UMSK2"                       ,        16,     8,      240,    "R/W",  0,      0,      0ull,   0ull},
32370         {"UMSK3"                       ,        24,     8,      240,    "R/W",  0,      0,      0ull,   0ull},
32371         {"RESERVED_32_63"              ,        32,     32,     240,    "RAZ",  0,      0,      0ull,   0ull},
32372         {"UMSK4"                       ,        0,      8,      241,    "R/W",  0,      0,      0ull,   0ull},
32373         {"UMSK5"                       ,        8,      8,      241,    "R/W",  0,      0,      0ull,   0ull},
32374         {"UMSK6"                       ,        16,     8,      241,    "R/W",  0,      0,      0ull,   0ull},
32375         {"UMSK7"                       ,        24,     8,      241,    "R/W",  0,      0,      0ull,   0ull},
32376         {"RESERVED_32_63"              ,        32,     32,     241,    "RAZ",  0,      0,      0ull,   0ull},
32377         {"UMSK8"                       ,        0,      8,      242,    "R/W",  0,      0,      0ull,   0ull},
32378         {"UMSK9"                       ,        8,      8,      242,    "R/W",  0,      0,      0ull,   0ull},
32379         {"UMSK10"                      ,        16,     8,      242,    "R/W",  0,      0,      0ull,   0ull},
32380         {"UMSK11"                      ,        24,     8,      242,    "R/W",  0,      0,      0ull,   0ull},
32381         {"RESERVED_32_63"              ,        32,     32,     242,    "RAZ",  0,      0,      0ull,   0ull},
32382         {"UMSK12"                      ,        0,      8,      243,    "R/W",  0,      0,      0ull,   0ull},
32383         {"UMSK13"                      ,        8,      8,      243,    "R/W",  0,      0,      0ull,   0ull},
32384         {"UMSK14"                      ,        16,     8,      243,    "R/W",  0,      0,      0ull,   0ull},
32385         {"UMSK15"                      ,        24,     8,      243,    "R/W",  0,      0,      0ull,   0ull},
32386         {"RESERVED_32_63"              ,        32,     32,     243,    "RAZ",  0,      0,      0ull,   0ull},
32387         {"UMSKIOB"                     ,        0,      8,      244,    "R/W",  0,      0,      0ull,   0ull},
32388         {"RESERVED_8_63"               ,        8,      56,     244,    "RAZ",  0,      0,      0ull,   0ull},
32389         {"Q0STAT"                      ,        0,      34,     245,    "RO",   0,      0,      0ull,   0ull},
32390         {"FTL"                         ,        34,     1,      245,    "RO",   0,      0,      0ull,   0ull},
32391         {"RESERVED_35_63"              ,        35,     29,     245,    "RAZ",  0,      0,      0ull,   0ull},
32392         {"Q1STAT"                      ,        0,      34,     246,    "RO",   0,      0,      0ull,   0ull},
32393         {"RESERVED_34_63"              ,        34,     30,     246,    "RAZ",  0,      0,      0ull,   0ull},
32394         {"Q2STAT"                      ,        0,      34,     247,    "RO",   0,      0,      0ull,   0ull},
32395         {"RESERVED_34_63"              ,        34,     30,     247,    "RAZ",  0,      0,      0ull,   0ull},
32396         {"Q3STAT"                      ,        0,      34,     248,    "RO",   0,      0,      0ull,   0ull},
32397         {"RESERVED_34_63"              ,        34,     30,     248,    "RAZ",  0,      0,      0ull,   0ull},
32398         {"ECC_ENA"                     ,        0,      1,      249,    "R/W",  0,      0,      0ull,   1ull},
32399         {"SEC_INTENA"                  ,        1,      1,      249,    "R/W",  0,      0,      0ull,   1ull},
32400         {"DED_INTENA"                  ,        2,      1,      249,    "R/W",  0,      0,      0ull,   1ull},
32401         {"SEC_ERR"                     ,        3,      1,      249,    "R/W1C",        0,      0,      0ull,   0ull},
32402         {"DED_ERR"                     ,        4,      1,      249,    "R/W1C",        0,      0,      0ull,   0ull},
32403         {"BMHCLSEL"                    ,        5,      1,      249,    "R/W",  0,      0,      0ull,   0ull},
32404         {"RESERVED_6_63"               ,        6,      58,     249,    "RAZ",  0,      0,      0ull,   0ull},
32405         {"FADR"                        ,        0,      11,     250,    "RO",   0,      0,      0ull,   0ull},
32406         {"FSET"                        ,        11,     3,      250,    "RO",   0,      0,      0ull,   0ull},
32407         {"FOWMSK"                      ,        14,     4,      250,    "RO",   0,      0,      0ull,   0ull},
32408         {"FADRU"                       ,        18,     1,      250,    "RO",   0,      0,      0ull,   0ull},
32409         {"RESERVED_19_63"              ,        19,     45,     250,    "RAZ",  0,      0,      0ull,   0ull},
32410         {"FSYN_OW0"                    ,        0,      10,     251,    "RO",   0,      0,      0ull,   0ull},
32411         {"FSYN_OW1"                    ,        10,     10,     251,    "RO",   0,      0,      0ull,   0ull},
32412         {"RESERVED_20_63"              ,        20,     44,     251,    "RAZ",  0,      0,      0ull,   0ull},
32413         {"FSYN_OW2"                    ,        0,      10,     252,    "RO",   0,      0,      0ull,   0ull},
32414         {"FSYN_OW3"                    ,        10,     10,     252,    "RO",   0,      0,      0ull,   0ull},
32415         {"RESERVED_20_63"              ,        20,     44,     252,    "RAZ",  0,      0,      0ull,   0ull},
32416         {"Q0FUS"                       ,        0,      34,     253,    "RO",   0,      0,      0ull,   0ull},
32417         {"RESERVED_34_63"              ,        34,     30,     253,    "RAZ",  0,      0,      0ull,   0ull},
32418         {"Q1FUS"                       ,        0,      34,     254,    "RO",   0,      0,      0ull,   0ull},
32419         {"RESERVED_34_63"              ,        34,     30,     254,    "RAZ",  0,      0,      0ull,   0ull},
32420         {"Q2FUS"                       ,        0,      34,     255,    "RO",   0,      0,      0ull,   0ull},
32421         {"RESERVED_34_63"              ,        34,     30,     255,    "RAZ",  0,      0,      0ull,   0ull},
32422         {"Q3FUS"                       ,        0,      34,     256,    "RO",   0,      0,      0ull,   0ull},
32423         {"CRIP_1024K"                  ,        34,     1,      256,    "RO",   0,      0,      0ull,   0ull},
32424         {"CRIP_512K"                   ,        35,     1,      256,    "RO",   0,      0,      0ull,   0ull},
32425         {"RESERVED_36_36"              ,        36,     1,      256,    "RAZ",  0,      0,      0ull,   0ull},
32426         {"EMA_CTL"                     ,        37,     2,      256,    "RO",   0,      0,      0ull,   0ull},
32427         {"RESERVED_39_63"              ,        39,     25,     256,    "RAZ",  0,      0,      0ull,   0ull},
32428         {"ECC_ENA"                     ,        0,      1,      257,    "R/W",  0,      0,      0ull,   1ull},
32429         {"SEC_INTENA"                  ,        1,      1,      257,    "R/W",  0,      0,      0ull,   1ull},
32430         {"DED_INTENA"                  ,        2,      1,      257,    "R/W",  0,      0,      0ull,   1ull},
32431         {"SEC_ERR"                     ,        3,      1,      257,    "R/W1C",        0,      0,      0ull,   0ull},
32432         {"DED_ERR"                     ,        4,      1,      257,    "R/W1C",        0,      0,      0ull,   0ull},
32433         {"FSYN"                        ,        5,      6,      257,    "RO",   0,      0,      0ull,   0ull},
32434         {"FADR"                        ,        11,     10,     257,    "RO",   0,      0,      0ull,   0ull},
32435         {"FSET"                        ,        21,     3,      257,    "RO",   0,      0,      0ull,   0ull},
32436         {"LCKERR"                      ,        24,     1,      257,    "R/W1C",        0,      0,      0ull,   0ull},
32437         {"LCK_INTENA"                  ,        25,     1,      257,    "R/W",  0,      0,      0ull,   1ull},
32438         {"LCKERR2"                     ,        26,     1,      257,    "R/W1C",        0,      0,      0ull,   0ull},
32439         {"LCK_INTENA2"                 ,        27,     1,      257,    "R/W",  0,      0,      0ull,   1ull},
32440         {"FADRU"                       ,        28,     1,      257,    "RO",   0,      0,      0ull,   0ull},
32441         {"RESERVED_29_63"              ,        29,     35,     257,    "RAZ",  0,      0,      0ull,   0ull},
32442         {"RATE"                        ,        0,      8,      258,    "R/W",  0,      0,      4ull,   4ull},
32443         {"RESERVED_8_63"               ,        8,      56,     258,    "RAZ",  1,      1,      0,      0},
32444         {"PHASE"                       ,        0,      7,      259,    "R/W",  0,      0,      4ull,   4ull},
32445         {"RESERVED_7_63"               ,        7,      57,     259,    "RAZ",  1,      1,      0,      0},
32446         {"RATE"                        ,        0,      16,     260,    "R/W",  0,      0,      0ull,   0ull},
32447         {"RESERVED_16_63"              ,        16,     48,     260,    "RAZ",  1,      1,      0,      0},
32448         {"DBG_EN"                      ,        0,      1,      261,    "R/W",  0,      0,      0ull,   0ull},
32449         {"RESERVED_1_63"               ,        1,      63,     261,    "RAZ",  1,      1,      0,      0},
32450         {"EN"                          ,        0,      1,      262,    "R/W",  0,      0,      0ull,   1ull},
32451         {"RESERVED_1_63"               ,        1,      63,     262,    "RAZ",  1,      1,      0,      0},
32452         {"POLARITY"                    ,        0,      1,      263,    "R/W",  0,      0,      0ull,   0ull},
32453         {"RESERVED_1_63"               ,        1,      63,     263,    "RAZ",  1,      1,      0,      0},
32454         {"PRT_EN"                      ,        0,      8,      264,    "R/W",  0,      1,      0ull,   0},
32455         {"RESERVED_8_63"               ,        8,      56,     264,    "RAZ",  1,      1,      0,      0},
32456         {"FORMAT"                      ,        0,      4,      265,    "R/W",  0,      1,      0ull,   0},
32457         {"RESERVED_4_63"               ,        4,      60,     265,    "RAZ",  1,      1,      0,      0},
32458         {"STATUS"                      ,        0,      6,      266,    "R/W",  0,      0,      0ull,   0ull},
32459         {"RESERVED_6_63"               ,        6,      58,     266,    "RAZ",  1,      1,      0,      0},
32460         {"CNT"                         ,        0,      6,      267,    "R/W",  0,      0,      0ull,   0ull},
32461         {"RESERVED_6_63"               ,        6,      58,     267,    "RAZ",  1,      1,      0,      0},
32462         {"DAT"                         ,        0,      32,     268,    "R/W",  0,      1,      0ull,   0},
32463         {"RESERVED_32_63"              ,        32,     32,     268,    "RAZ",  1,      1,      0,      0},
32464         {"CLR"                         ,        0,      32,     269,    "WO",   0,      1,      0ull,   0},
32465         {"RESERVED_32_63"              ,        32,     32,     269,    "RAZ",  1,      1,      0,      0},
32466         {"SET"                         ,        0,      32,     270,    "WO",   0,      1,      0ull,   0},
32467         {"RESERVED_32_63"              ,        32,     32,     270,    "RAZ",  1,      1,      0,      0},
32468         {"PCTL_DAT"                    ,        0,      5,      271,    "R/W",  0,      1,      0ull,   0},
32469         {"RESERVED_5_11"               ,        5,      7,      271,    "RAZ",  0,      1,      0ull,   0},
32470         {"PCTL_CSR"                    ,        12,     4,      271,    "R/W",  0,      1,      15ull,  0},
32471         {"NCTL_DAT"                    ,        16,     4,      271,    "R/W",  0,      1,      0ull,   0},
32472         {"RESERVED_20_27"              ,        20,     8,      271,    "RAZ",  0,      1,      0ull,   0},
32473         {"NCTL_CSR"                    ,        28,     4,      271,    "R/W",  0,      1,      15ull,  0},
32474         {"RESERVED_32_63"              ,        32,     32,     271,    "RAZ",  0,      0,      0ull,   0ull},
32475         {"DIC"                         ,        0,      2,      272,    "R/W",  0,      0,      0ull,   0ull},
32476         {"QS_DIC"                      ,        2,      2,      272,    "R/W",  0,      0,      2ull,   2ull},
32477         {"TSKW"                        ,        4,      2,      272,    "R/W",  0,      0,      0ull,   1ull},
32478         {"SIL_LAT"                     ,        6,      2,      272,    "R/W",  0,      0,      1ull,   1ull},
32479         {"BPRCH"                       ,        8,      1,      272,    "R/W",  0,      1,      0ull,   0},
32480         {"FPRCH2"                      ,        9,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
32481         {"MODE128B"                    ,        10,     1,      272,    "R/W",  0,      0,      1ull,   1ull},
32482         {"DRESET"                      ,        11,     1,      272,    "R/W",  0,      0,      1ull,   0ull},
32483         {"INORDER_MRF"                 ,        12,     1,      272,    "R/W",  0,      0,      0ull,   0ull},
32484         {"INORDER_MWF"                 ,        13,     1,      272,    "RAZ",  0,      0,      0ull,   0ull},
32485         {"R2R_SLOT"                    ,        14,     1,      272,    "R/W",  0,      0,      0ull,   0ull},
32486         {"RDIMM_ENA"                   ,        15,     1,      272,    "R/W",  0,      1,      0ull,   0},
32487         {"RESERVED_16_17"              ,        16,     2,      272,    "RAZ",  0,      0,      0ull,   0ull},
32488         {"MAX_WRITE_BATCH"             ,        18,     4,      272,    "R/W",  0,      0,      8ull,   8ull},
32489         {"XOR_BANK"                    ,        22,     1,      272,    "R/W",  0,      0,      0ull,   1ull},
32490         {"SLOW_SCF"                    ,        23,     1,      272,    "R/W",  0,      0,      0ull,   0ull},
32491         {"DDR__PCTL"                   ,        24,     4,      272,    "RO",   1,      1,      0,      0},
32492         {"DDR__NCTL"                   ,        28,     4,      272,    "RO",   1,      1,      0,      0},
32493         {"RESERVED_32_63"              ,        32,     32,     272,    "RAZ",  1,      1,      0,      0},
32494         {"RESERVED_0_7"                ,        0,      8,      273,    "RAZ",  0,      1,      0ull,   0},
32495         {"DCC_ENABLE"                  ,        8,      1,      273,    "R/W",  0,      0,      0ull,   0ull},
32496         {"SIL_MODE"                    ,        9,      1,      273,    "R/W",  0,      0,      0ull,   1ull},
32497         {"RESERVED_10_63"              ,        10,     54,     273,    "RAZ",  1,      1,      0,      0},
32498         {"DCLKCNT_HI"                  ,        0,      32,     274,    "RO",   0,      0,      0ull,   0ull},
32499         {"RESERVED_32_63"              ,        32,     32,     274,    "RAZ",  1,      1,      0,      0},
32500         {"DCLKCNT_LO"                  ,        0,      32,     275,    "RO",   0,      0,      0ull,   0ull},
32501         {"RESERVED_32_63"              ,        32,     32,     275,    "RAZ",  1,      1,      0,      0},
32502         {"DDR2"                        ,        0,      1,      276,    "R/W",  0,      0,      1ull,   1ull},
32503         {"RDQS"                        ,        1,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
32504         {"DLL90_BYP"                   ,        2,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
32505         {"DLL90_VLU"                   ,        3,      5,      276,    "R/W",  0,      1,      0ull,   0},
32506         {"QDLL_ENA"                    ,        8,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
32507         {"ODT_ENA"                     ,        9,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
32508         {"DDR2T"                       ,        10,     1,      276,    "R/W",  0,      1,      0ull,   0},
32509         {"CRIP_MODE"                   ,        11,     1,      276,    "R/W",  0,      0,      0ull,   0ull},
32510         {"TFAW"                        ,        12,     5,      276,    "R/W",  0,      0,      0ull,   9ull},
32511         {"DDR_EOF"                     ,        17,     4,      276,    "R/W",  0,      0,      0ull,   0ull},
32512         {"SILO_HC"                     ,        21,     1,      276,    "R/W",  0,      1,      1ull,   0},
32513         {"TWR"                         ,        22,     3,      276,    "R/W",  0,      0,      3ull,   1ull},
32514         {"BWCNT"                       ,        25,     1,      276,    "R/W",  0,      0,      0ull,   0ull},
32515         {"POCAS"                       ,        26,     1,      276,    "R/W",  0,      0,      0ull,   0ull},
32516         {"ADDLAT"                      ,        27,     3,      276,    "R/W",  0,      0,      0ull,   0ull},
32517         {"BURST8"                      ,        30,     1,      276,    "R/W",  0,      0,      0ull,   1ull},
32518         {"BANK8"                       ,        31,     1,      276,    "R/W",  0,      1,      0ull,   0},
32519         {"RESERVED_32_63"              ,        32,     32,     276,    "RAZ",  0,      0,      0ull,   0ull},
32520         {"CLK"                         ,        0,      4,      277,    "R/W",  0,      0,      0ull,   0ull},
32521         {"RESERVED_4_4"                ,        4,      1,      277,    "RAZ",  0,      0,      0ull,   0ull},
32522         {"CMD"                         ,        5,      4,      277,    "R/W",  0,      0,      0ull,   0ull},
32523         {"RESERVED_9_9"                ,        9,      1,      277,    "RAZ",  0,      0,      0ull,   0ull},
32524         {"DQ"                          ,        10,     4,      277,    "R/W",  0,      0,      0ull,   0ull},
32525         {"RESERVED_14_63"              ,        14,     50,     277,    "RAZ",  0,      0,      0ull,   0ull},
32526         {"CS_MASK"                     ,        0,      8,      278,    "R/W",  0,      1,      0ull,   0},
32527         {"RESERVED_8_15"               ,        8,      8,      278,    "RAZ",  0,      1,      0ull,   0},
32528         {"ROW_LSB"                     ,        16,     3,      278,    "R/W",  0,      1,      3ull,   0},
32529         {"BANK8"                       ,        19,     1,      278,    "R/W",  0,      1,      0ull,   0},
32530         {"RESERVED_20_63"              ,        20,     44,     278,    "RAZ",  0,      1,      0ull,   0},
32531         {"MRDSYN0"                     ,        0,      8,      279,    "RO",   0,      0,      0ull,   0ull},
32532         {"MRDSYN1"                     ,        8,      8,      279,    "RO",   0,      0,      0ull,   0ull},
32533         {"MRDSYN2"                     ,        16,     8,      279,    "RO",   0,      0,      0ull,   0ull},
32534         {"MRDSYN3"                     ,        24,     8,      279,    "RO",   0,      0,      0ull,   0ull},
32535         {"RESERVED_32_63"              ,        32,     32,     279,    "RAZ",  1,      1,      0,      0},
32536         {"FCOL"                        ,        0,      12,     280,    "RO",   0,      0,      0ull,   0ull},
32537         {"FROW"                        ,        12,     14,     280,    "RO",   0,      0,      0ull,   0ull},
32538         {"FBANK"                       ,        26,     3,      280,    "RO",   0,      0,      0ull,   0ull},
32539         {"FBUNK"                       ,        29,     1,      280,    "RO",   0,      0,      0ull,   0ull},
32540         {"FDIMM"                       ,        30,     2,      280,    "RO",   0,      0,      0ull,   0ull},
32541         {"RESERVED_32_63"              ,        32,     32,     280,    "RAZ",  1,      1,      0,      0},
32542         {"IFBCNT_HI"                   ,        0,      32,     281,    "RO",   0,      0,      0ull,   0ull},
32543         {"RESERVED_32_63"              ,        32,     32,     281,    "RAZ",  1,      1,      0,      0},
32544         {"IFBCNT_LO"                   ,        0,      32,     282,    "RO",   0,      0,      0ull,   0ull},
32545         {"RESERVED_32_63"              ,        32,     32,     282,    "RAZ",  1,      1,      0,      0},
32546         {"INIT_START"                  ,        0,      1,      283,    "R/W",  0,      0,      0ull,   0ull},
32547         {"ECC_ENA"                     ,        1,      1,      283,    "R/W",  0,      0,      0ull,   1ull},
32548         {"ROW_LSB"                     ,        2,      3,      283,    "R/W",  0,      1,      3ull,   0},
32549         {"PBANK_LSB"                   ,        5,      4,      283,    "R/W",  0,      1,      5ull,   0},
32550         {"REF_INT"                     ,        9,      6,      283,    "R/W",  0,      0,      1ull,   2ull},
32551         {"TCL"                         ,        15,     4,      283,    "R/W",  0,      1,      3ull,   0},
32552         {"INTR_SEC_ENA"                ,        19,     1,      283,    "R/W",  0,      0,      0ull,   1ull},
32553         {"INTR_DED_ENA"                ,        20,     1,      283,    "R/W",  0,      0,      0ull,   1ull},
32554         {"SEC_ERR"                     ,        21,     4,      283,    "R/W1C",        0,      0,      0ull,   0ull},
32555         {"DED_ERR"                     ,        25,     4,      283,    "R/W1C",        0,      0,      0ull,   0ull},
32556         {"BUNK_ENA"                    ,        29,     1,      283,    "R/W",  0,      1,      0ull,   0},
32557         {"SILO_QC"                     ,        30,     1,      283,    "R/W",  0,      1,      0ull,   0},
32558         {"RESET"                       ,        31,     1,      283,    "RAZ",  1,      1,      0,      0},
32559         {"RESERVED_32_63"              ,        32,     32,     283,    "RAZ",  1,      1,      0,      0},
32560         {"TRAS"                        ,        0,      5,      284,    "R/W",  0,      0,      12ull,  12ull},
32561         {"TRCD"                        ,        5,      4,      284,    "R/W",  0,      0,      4ull,   4ull},
32562         {"TWTR"                        ,        9,      4,      284,    "R/W",  0,      0,      2ull,   2ull},
32563         {"TRP"                         ,        13,     4,      284,    "R/W",  0,      0,      5ull,   4ull},
32564         {"TRFC"                        ,        17,     5,      284,    "R/W",  0,      0,      6ull,   7ull},
32565         {"TMRD"                        ,        22,     3,      284,    "R/W",  0,      0,      2ull,   2ull},
32566         {"CASLAT"                      ,        25,     3,      284,    "R/W",  0,      0,      4ull,   4ull},
32567         {"TRRD"                        ,        28,     3,      284,    "R/W",  0,      0,      2ull,   2ull},
32568         {"RESERVED_31_63"              ,        31,     33,     284,    "RAZ",  1,      1,      0,      0},
32569         {"CS_MASK"                     ,        0,      8,      285,    "R/W",  0,      1,      0ull,   0},
32570         {"RESERVED_8_63"               ,        8,      56,     285,    "RAZ",  1,      1,      0,      0},
32571         {"OPSCNT_HI"                   ,        0,      32,     286,    "RO",   0,      0,      0ull,   0ull},
32572         {"RESERVED_32_63"              ,        32,     32,     286,    "RAZ",  1,      1,      0,      0},
32573         {"OPSCNT_LO"                   ,        0,      32,     287,    "RO",   0,      0,      0ull,   0ull},
32574         {"RESERVED_32_63"              ,        32,     32,     287,    "RAZ",  1,      1,      0,      0},
32575         {"EN2"                         ,        0,      1,      288,    "R/W",  0,      1,      0ull,   0},
32576         {"EN4"                         ,        1,      1,      288,    "R/W",  0,      1,      0ull,   0},
32577         {"EN6"                         ,        2,      1,      288,    "R/W",  0,      1,      0ull,   0},
32578         {"EN8"                         ,        3,      1,      288,    "R/W",  0,      1,      1ull,   0},
32579         {"EN12"                        ,        4,      1,      288,    "R/W",  0,      1,      0ull,   0},
32580         {"EN16"                        ,        5,      1,      288,    "R/W",  0,      1,      0ull,   0},
32581         {"RESERVED_6_7"                ,        6,      2,      288,    "RAZ",  0,      1,      0ull,   0},
32582         {"CLKR"                        ,        8,      6,      288,    "R/W",  0,      1,      0ull,   0},
32583         {"CLKF"                        ,        14,     12,     288,    "R/W",  0,      1,      31ull,  0},
32584         {"RESET_N"                     ,        26,     1,      288,    "R/W",  0,      0,      0ull,   1ull},
32585         {"DIV_RESET"                   ,        27,     1,      288,    "R/W",  0,      0,      1ull,   0ull},
32586         {"RESERVED_28_63"              ,        28,     36,     288,    "RAZ",  0,      1,      0ull,   0},
32587         {"FBSLIP"                      ,        0,      1,      289,    "R/W1C",        0,      1,      0ull,   0},
32588         {"RFSLIP"                      ,        1,      1,      289,    "R/W1C",        0,      1,      0ull,   0},
32589         {"RESERVED_2_21"               ,        2,      20,     289,    "RAZ",  1,      1,      0,      0},
32590         {"DDR__PCTL"                   ,        22,     5,      289,    "RO",   1,      1,      0,      0},
32591         {"DDR__NCTL"                   ,        27,     5,      289,    "RO",   1,      1,      0,      0},
32592         {"RESERVED_32_63"              ,        32,     32,     289,    "RAZ",  1,      1,      0,      0},
32593         {"PCTL"                        ,        0,      5,      290,    "R/W",  0,      1,      0ull,   0},
32594         {"RESERVED_5_7"                ,        5,      3,      290,    "RAZ",  0,      1,      0ull,   0},
32595         {"NCTL"                        ,        8,      4,      290,    "R/W",  0,      1,      0ull,   0},
32596         {"RESERVED_12_15"              ,        12,     4,      290,    "RAZ",  0,      1,      0ull,   0},
32597         {"ENABLE"                      ,        16,     1,      290,    "R/W",  0,      1,      0ull,   0},
32598         {"RESERVED_17_63"              ,        17,     47,     290,    "RAZ",  0,      1,      0ull,   0},
32599         {"RODT_LO0"                    ,        0,      4,      291,    "R/W",  0,      0,      15ull,  15ull},
32600         {"RODT_LO1"                    ,        4,      4,      291,    "R/W",  0,      0,      15ull,  15ull},
32601         {"RODT_LO2"                    ,        8,      4,      291,    "R/W",  0,      0,      15ull,  15ull},
32602         {"RODT_LO3"                    ,        12,     4,      291,    "R/W",  0,      0,      15ull,  15ull},
32603         {"RODT_HI0"                    ,        16,     4,      291,    "R/W",  0,      0,      15ull,  15ull},
32604         {"RODT_HI1"                    ,        20,     4,      291,    "R/W",  0,      0,      15ull,  15ull},
32605         {"RODT_HI2"                    ,        24,     4,      291,    "R/W",  0,      0,      15ull,  15ull},
32606         {"RODT_HI3"                    ,        28,     4,      291,    "R/W",  0,      0,      15ull,  15ull},
32607         {"RESERVED_32_63"              ,        32,     32,     291,    "RAZ",  1,      1,      0,      0},
32608         {"WODT_LO0"                    ,        0,      4,      292,    "R/W",  0,      0,      15ull,  15ull},
32609         {"WODT_LO1"                    ,        4,      4,      292,    "R/W",  0,      0,      15ull,  15ull},
32610         {"WODT_LO2"                    ,        8,      4,      292,    "R/W",  0,      0,      15ull,  15ull},
32611         {"WODT_LO3"                    ,        12,     4,      292,    "R/W",  0,      0,      15ull,  15ull},
32612         {"WODT_HI0"                    ,        16,     4,      292,    "R/W",  0,      0,      15ull,  15ull},
32613         {"WODT_HI1"                    ,        20,     4,      292,    "R/W",  0,      0,      15ull,  15ull},
32614         {"WODT_HI2"                    ,        24,     4,      292,    "R/W",  0,      0,      15ull,  15ull},
32615         {"WODT_HI3"                    ,        28,     4,      292,    "R/W",  0,      0,      15ull,  15ull},
32616         {"RESERVED_32_63"              ,        32,     32,     292,    "RAZ",  1,      1,      0,      0},
32617         {"NCBI"                        ,        0,      1,      293,    "RO",   0,      0,      0ull,   0ull},
32618         {"LOC"                         ,        1,      1,      293,    "RO",   0,      0,      0ull,   0ull},
32619         {"NCBO_0"                      ,        2,      1,      293,    "RO",   0,      0,      0ull,   0ull},
32620         {"RESERVED_3_63"               ,        3,      61,     293,    "RAZ",  1,      1,      0,      0},
32621         {"ADR_ERR"                     ,        0,      1,      294,    "R/W1C",        0,      0,      0ull,   0ull},
32622         {"WAIT_ERR"                    ,        1,      1,      294,    "R/W1C",        0,      0,      0ull,   0ull},
32623         {"RESERVED_2_63"               ,        2,      62,     294,    "RAZ",  1,      1,      0,      0},
32624         {"ADR_INT"                     ,        0,      1,      295,    "R/W",  0,      1,      0ull,   0},
32625         {"WAIT_INT"                    ,        1,      1,      295,    "R/W",  0,      1,      0ull,   0},
32626         {"RESERVED_2_63"               ,        2,      62,     295,    "RAZ",  1,      1,      0,      0},
32627         {"RESERVED_0_2"                ,        0,      3,      296,    "RAZ",  1,      1,      0,      0},
32628         {"ADR"                         ,        3,      5,      296,    "R/W",  0,      1,      0ull,   0},
32629         {"RESERVED_8_63"               ,        8,      56,     296,    "RAZ",  1,      1,      0,      0},
32630         {"RESERVED_0_2"                ,        0,      3,      297,    "RAZ",  1,      1,      0,      0},
32631         {"BASE"                        ,        3,      25,     297,    "R/W",  0,      1,      0ull,   0},
32632         {"RESERVED_28_30"              ,        28,     3,      297,    "RAZ",  1,      1,      0,      0},
32633         {"EN"                          ,        31,     1,      297,    "R/W",  0,      1,      0ull,   0},
32634         {"RESERVED_32_63"              ,        32,     32,     297,    "RAZ",  1,      1,      0,      0},
32635         {"DATA"                        ,        0,      64,     298,    "R/W",  1,      1,      0,      0},
32636         {"BASE"                        ,        0,      16,     299,    "R/W",  0,      1,      0ull,   0},
32637         {"SIZE"                        ,        16,     12,     299,    "R/W",  0,      1,      0ull,   0},
32638         {"WIDTH"                       ,        28,     1,      299,    "R/W",  0,      1,      0ull,   0},
32639         {"ALE"                         ,        29,     1,      299,    "R/W",  0,      1,      0ull,   0},
32640         {"ORBIT"                       ,        30,     1,      299,    "R/W",  0,      1,      0ull,   0},
32641         {"EN"                          ,        31,     1,      299,    "R/W",  0,      1,      0ull,   0},
32642         {"OE_EXT"                      ,        32,     2,      299,    "R/W",  0,      1,      0ull,   0},
32643         {"WE_EXT"                      ,        34,     2,      299,    "R/W",  0,      1,      0ull,   0},
32644         {"SAM"                         ,        36,     1,      299,    "R/W",  0,      1,      0ull,   0},
32645         {"RESERVED_37_63"              ,        37,     27,     299,    "RAZ",  1,      1,      0,      0},
32646         {"ADR"                         ,        0,      6,      300,    "R/W",  0,      1,      63ull,  0},
32647         {"CE"                          ,        6,      6,      300,    "R/W",  0,      1,      63ull,  0},
32648         {"OE"                          ,        12,     6,      300,    "R/W",  0,      1,      63ull,  0},
32649         {"WE"                          ,        18,     6,      300,    "R/W",  0,      1,      63ull,  0},
32650         {"RD_HLD"                      ,        24,     6,      300,    "R/W",  0,      1,      63ull,  0},
32651         {"WR_HLD"                      ,        30,     6,      300,    "R/W",  0,      1,      63ull,  0},
32652         {"PAUSE"                       ,        36,     6,      300,    "R/W",  0,      1,      63ull,  0},
32653         {"WAIT"                        ,        42,     6,      300,    "R/W",  0,      1,      63ull,  0},
32654         {"PAGE"                        ,        48,     6,      300,    "R/W",  0,      1,      63ull,  0},
32655         {"ALE"                         ,        54,     6,      300,    "R/W",  0,      1,      63ull,  0},
32656         {"PAGES"                       ,        60,     2,      300,    "R/W",  0,      1,      0ull,   0},
32657         {"WAITM"                       ,        62,     1,      300,    "R/W",  0,      1,      0ull,   0},
32658         {"PAGEM"                       ,        63,     1,      300,    "R/W",  0,      1,      0ull,   0},
32659         {"FIF_THR"                     ,        0,      6,      301,    "R/W",  0,      0,      26ull,  26ull},
32660         {"RESERVED_6_7"                ,        6,      2,      301,    "RAZ",  1,      1,      0,      0},
32661         {"FIF_CNT"                     ,        8,      6,      301,    "RO",   0,      1,      0ull,   0},
32662         {"RESERVED_14_63"              ,        14,     50,     301,    "RAZ",  1,      1,      0,      0},
32663         {"DAT"                         ,        0,      64,     302,    "R/W",  1,      1,      0,      0},
32664         {"MAN_INFO"                    ,        0,      32,     303,    "RO",   1,      1,      0,      0},
32665         {"RESERVED_32_63"              ,        32,     32,     303,    "RAZ",  1,      1,      0,      0},
32666         {"MAN_INFO"                    ,        0,      32,     304,    "RO",   1,      1,      0,      0},
32667         {"RESERVED_32_63"              ,        32,     32,     304,    "RAZ",  1,      1,      0,      0},
32668         {"PP_DIS"                      ,        0,      16,     305,    "RO",   1,      1,      0,      0},
32669         {"CHIP_ID"                     ,        16,     8,      305,    "RO",   1,      1,      0,      0},
32670         {"BIST_DIS"                    ,        24,     1,      305,    "RO",   1,      1,      0,      0},
32671         {"RST_SHT"                     ,        25,     1,      305,    "RO",   1,      1,      0,      0},
32672         {"NOCRYPTO"                    ,        26,     1,      305,    "RO",   1,      1,      0,      0},
32673         {"NOMUL"                       ,        27,     1,      305,    "RO",   1,      1,      0,      0},
32674         {"NODFA_CP2"                   ,        28,     1,      305,    "RO",   1,      1,      0,      0},
32675         {"NOKASU"                      ,        29,     1,      305,    "RO",   1,      1,      0,      0},
32676         {"RESERVED_30_63"              ,        30,     34,     305,    "RAZ",  1,      1,      0,      0},
32677         {"ICACHE"                      ,        0,      24,     306,    "RO",   1,      1,      0,      0},
32678         {"NODFA_DTE"                   ,        24,     1,      306,    "RO",   1,      1,      0,      0},
32679         {"NOZIP"                       ,        25,     1,      306,    "RO",   1,      1,      0,      0},
32680         {"EFUS_IGN"                    ,        26,     1,      306,    "RO",   1,      1,      0,      0},
32681         {"EFUS_LCK"                    ,        27,     1,      306,    "RO",   1,      1,      0,      0},
32682         {"BAR2_EN"                     ,        28,     1,      306,    "RO",   1,      1,      0,      0},
32683         {"ZIP_CRIP"                    ,        29,     2,      306,    "RO",   1,      1,      0,      0},
32684         {"RESERVED_31_63"              ,        31,     33,     306,    "RAZ",  1,      1,      0,      0},
32685         {"EMA"                         ,        0,      2,      307,    "R/W",  1,      0,      0,      0ull},
32686         {"RESERVED_2_63"               ,        2,      62,     307,    "RAZ",  1,      1,      0,      0},
32687         {"PDF"                         ,        0,      64,     308,    "RO",   1,      1,      0,      0},
32688         {"FBSLIP"                      ,        0,      1,      309,    "R/W1C",        0,      1,      0ull,   0},
32689         {"RFSLIP"                      ,        1,      1,      309,    "R/W1C",        0,      1,      0ull,   0},
32690         {"RESERVED_2_63"               ,        2,      62,     309,    "RAZ",  1,      1,      0,      0},
32691         {"PROG"                        ,        0,      1,      310,    "R/W",  1,      1,      0,      0},
32692         {"RESERVED_1_63"               ,        1,      63,     310,    "RAZ",  1,      1,      0,      0},
32693         {"SETUP"                       ,        0,      8,      311,    "R/W",  0,      1,      3ull,   0},
32694         {"SCLK_HI"                     ,        8,      12,     311,    "R/W",  0,      1,      100ull, 0},
32695         {"SCLK_LO"                     ,        20,     4,      311,    "R/W",  0,      1,      2ull,   0},
32696         {"OUT"                         ,        24,     8,      311,    "R/W",  0,      1,      3ull,   0},
32697         {"PROG_PIN"                    ,        32,     1,      311,    "RO",   0,      0,      0ull,   0ull},
32698         {"RESERVED_33_63"              ,        33,     31,     311,    "RAZ",  1,      1,      0,      0},
32699         {"ADDR"                        ,        0,      7,      312,    "R/W",  0,      0,      0ull,   0ull},
32700         {"RESERVED_7_7"                ,        7,      1,      312,    "RAZ",  1,      1,      0,      0},
32701         {"EFUSE"                       ,        8,      1,      312,    "R/W",  0,      0,      0ull,   0ull},
32702         {"RESERVED_9_11"               ,        9,      3,      312,    "RAZ",  1,      1,      0,      0},
32703         {"PEND"                        ,        12,     1,      312,    "R/W",  0,      0,      0ull,   0ull},
32704         {"RESERVED_13_15"              ,        13,     3,      312,    "RAZ",  1,      1,      0,      0},
32705         {"DAT"                         ,        16,     8,      312,    "RO",   1,      1,      0,      0},
32706         {"RESERVED_24_63"              ,        24,     40,     312,    "RAZ",  1,      1,      0,      0},
32707         {"REPAIR0"                     ,        0,      14,     313,    "RO",   0,      0,      0ull,   0ull},
32708         {"REPAIR1"                     ,        14,     14,     313,    "RO",   0,      0,      0ull,   0ull},
32709         {"REPAIR2"                     ,        28,     14,     313,    "RO",   0,      0,      0ull,   0ull},
32710         {"RESERVED_42_63"              ,        42,     22,     313,    "RAZ",  1,      1,      0,      0},
32711         {"TOO_MANY"                    ,        0,      1,      314,    "RO",   0,      0,      0ull,   0ull},
32712         {"RESERVED_1_63"               ,        1,      63,     314,    "RAZ",  1,      1,      0,      0},
32713         {"ADDR"                        ,        0,      2,      315,    "R/W",  1,      1,      0,      0},
32714         {"RESERVED_2_63"               ,        2,      62,     315,    "RAZ",  1,      1,      0,      0},
32715         {"ST_INT"                      ,        0,      1,      316,    "R/W1C",        0,      1,      0ull,   0},
32716         {"TS_INT"                      ,        1,      1,      316,    "R/W1C",        0,      1,      0ull,   0},
32717         {"CORE_INT"                    ,        2,      1,      316,    "RO",   0,      1,      0ull,   0},
32718         {"RESERVED_3_3"                ,        3,      1,      316,    "RAZ",  1,      1,      0,      0},
32719         {"ST_EN"                       ,        4,      1,      316,    "R/W",  0,      1,      0ull,   0},
32720         {"TS_EN"                       ,        5,      1,      316,    "R/W",  0,      1,      0ull,   0},
32721         {"CORE_EN"                     ,        6,      1,      316,    "R/W",  0,      1,      0ull,   0},
32722         {"RESERVED_7_7"                ,        7,      1,      316,    "RAZ",  1,      1,      0,      0},
32723         {"SDA_OVR"                     ,        8,      1,      316,    "R/W",  0,      1,      0ull,   0},
32724         {"SCL_OVR"                     ,        9,      1,      316,    "R/W",  0,      1,      0ull,   0},
32725         {"SDA"                         ,        10,     1,      316,    "RO",   1,      1,      0,      0},
32726         {"SCL"                         ,        11,     1,      316,    "RO",   1,      1,      0,      0},
32727         {"RESERVED_12_63"              ,        12,     52,     316,    "RAZ",  1,      1,      0,      0},
32728         {"D"                           ,        0,      32,     317,    "R/W",  0,      1,      0ull,   0},
32729         {"EOP_IA"                      ,        32,     3,      317,    "R/W",  0,      1,      0ull,   0},
32730         {"IA"                          ,        35,     5,      317,    "R/W",  0,      1,      0ull,   0},
32731         {"A"                           ,        40,     10,     317,    "R/W",  0,      1,      0ull,   0},
32732         {"SCR"                         ,        50,     2,      317,    "R/W",  0,      1,      0ull,   0},
32733         {"SIZE"                        ,        52,     3,      317,    "R/W",  0,      1,      0ull,   0},
32734         {"SOVR"                        ,        55,     1,      317,    "R/W",  0,      1,      0ull,   0},
32735         {"R"                           ,        56,     1,      317,    "R/W",  0,      1,      0ull,   0},
32736         {"OP"                          ,        57,     4,      317,    "R/W",  0,      1,      0ull,   0},
32737         {"EIA"                         ,        61,     1,      317,    "R/W",  0,      1,      0ull,   0},
32738         {"SLONLY"                      ,        62,     1,      317,    "R/W",  0,      1,      0ull,   0},
32739         {"V"                           ,        63,     1,      317,    "RC/W", 0,      1,      0ull,   0},
32740         {"D"                           ,        0,      32,     318,    "R/W",  0,      1,      0ull,   0},
32741         {"IA"                          ,        32,     8,      318,    "R/W",  0,      1,      0ull,   0},
32742         {"RESERVED_40_63"              ,        40,     24,     318,    "RAZ",  1,      1,      0,      0},
32743         {"D"                           ,        0,      32,     319,    "R/W",  1,      1,      0,      0},
32744         {"RESERVED_32_61"              ,        32,     30,     319,    "RAZ",  1,      1,      0,      0},
32745         {"V"                           ,        62,     2,      319,    "RC/W", 0,      1,      0ull,   0},
32746         {"DLH"                         ,        0,      8,      320,    "R/W",  0,      1,      0ull,   0},
32747         {"RESERVED_8_63"               ,        8,      56,     320,    "RAZ",  1,      1,      0,      0},
32748         {"DLL"                         ,        0,      8,      321,    "R/W",  0,      1,      0ull,   0},
32749         {"RESERVED_8_63"               ,        8,      56,     321,    "RAZ",  1,      1,      0,      0},
32750         {"FAR"                         ,        0,      1,      322,    "R/W",  0,      1,      0ull,   0},
32751         {"RESERVED_1_63"               ,        1,      63,     322,    "RAZ",  1,      1,      0,      0},
32752         {"EN"                          ,        0,      1,      323,    "WO",   0,      1,      0ull,   0},
32753         {"RXFR"                        ,        1,      1,      323,    "WO",   0,      1,      0ull,   0},
32754         {"TXFR"                        ,        2,      1,      323,    "WO",   0,      1,      0ull,   0},
32755         {"RESERVED_3_3"                ,        3,      1,      323,    "RAZ",  0,      1,      0ull,   0},
32756         {"TXTRIG"                      ,        4,      2,      323,    "WO",   0,      1,      0ull,   0},
32757         {"RXTRIG"                      ,        6,      2,      323,    "WO",   0,      1,      0ull,   0},
32758         {"RESERVED_8_63"               ,        8,      56,     323,    "RAZ",  1,      1,      0,      0},
32759         {"HTX"                         ,        0,      1,      324,    "R/W",  0,      1,      0ull,   0},
32760         {"RESERVED_1_63"               ,        1,      63,     324,    "RAZ",  1,      1,      0,      0},
32761         {"ERBFI"                       ,        0,      1,      325,    "R/W",  0,      1,      0ull,   0},
32762         {"ETBEI"                       ,        1,      1,      325,    "R/W",  0,      1,      0ull,   0},
32763         {"ELSI"                        ,        2,      1,      325,    "R/W",  0,      1,      0ull,   0},
32764         {"EDSSI"                       ,        3,      1,      325,    "R/W",  0,      1,      0ull,   0},
32765         {"RESERVED_4_6"                ,        4,      3,      325,    "RAZ",  0,      1,      0ull,   0},
32766         {"PTIME"                       ,        7,      1,      325,    "R/W",  0,      1,      0ull,   0},
32767         {"RESERVED_8_63"               ,        8,      56,     325,    "RAZ",  1,      1,      0,      0},
32768         {"IID"                         ,        0,      4,      326,    "RO",   0,      1,      1ull,   0},
32769         {"RESERVED_4_5"                ,        4,      2,      326,    "RAZ",  0,      1,      0ull,   0},
32770         {"FEN"                         ,        6,      2,      326,    "RO",   0,      1,      0ull,   0},
32771         {"RESERVED_8_63"               ,        8,      56,     326,    "RAZ",  1,      1,      0,      0},
32772         {"CLS"                         ,        0,      2,      327,    "R/W",  0,      1,      0ull,   0},
32773         {"STOP"                        ,        2,      1,      327,    "R/W",  0,      1,      0ull,   0},
32774         {"PEN"                         ,        3,      1,      327,    "R/W",  0,      1,      0ull,   0},
32775         {"EPS"                         ,        4,      1,      327,    "R/W",  0,      1,      0ull,   0},
32776         {"RESERVED_5_5"                ,        5,      1,      327,    "RAZ",  0,      1,      0ull,   0},
32777         {"BRK"                         ,        6,      1,      327,    "R/W",  0,      1,      0ull,   0},
32778         {"DLAB"                        ,        7,      1,      327,    "R/W",  0,      1,      0ull,   0},
32779         {"RESERVED_8_63"               ,        8,      56,     327,    "RAZ",  1,      1,      0,      0},
32780         {"DR"                          ,        0,      1,      328,    "RO",   0,      1,      0ull,   0},
32781         {"OE"                          ,        1,      1,      328,    "RC",   0,      1,      0ull,   0},
32782         {"PE"                          ,        2,      1,      328,    "RC",   0,      1,      0ull,   0},
32783         {"FE"                          ,        3,      1,      328,    "RC",   0,      1,      0ull,   0},
32784         {"BI"                          ,        4,      1,      328,    "RC",   0,      1,      0ull,   0},
32785         {"THRE"                        ,        5,      1,      328,    "RO",   0,      1,      1ull,   0},
32786         {"TEMT"                        ,        6,      1,      328,    "RO",   0,      1,      1ull,   0},
32787         {"FERR"                        ,        7,      1,      328,    "RC",   0,      1,      0ull,   0},
32788         {"RESERVED_8_63"               ,        8,      56,     328,    "RAZ",  1,      1,      0,      0},
32789         {"DTR"                         ,        0,      1,      329,    "R/W",  0,      1,      0ull,   0},
32790         {"RTS"                         ,        1,      1,      329,    "R/W",  0,      1,      0ull,   0},
32791         {"OUT1"                        ,        2,      1,      329,    "R/W",  0,      1,      0ull,   0},
32792         {"OUT2"                        ,        3,      1,      329,    "R/W",  0,      1,      0ull,   0},
32793         {"LOOP"                        ,        4,      1,      329,    "R/W",  0,      1,      0ull,   0},
32794         {"AFCE"                        ,        5,      1,      329,    "R/W",  0,      1,      0ull,   0},
32795         {"RESERVED_6_63"               ,        6,      58,     329,    "RAZ",  0,      1,      0ull,   0},
32796         {"DCTS"                        ,        0,      1,      330,    "RC",   0,      1,      0ull,   0},
32797         {"DDSR"                        ,        1,      1,      330,    "RC",   0,      1,      0ull,   0},
32798         {"TERI"                        ,        2,      1,      330,    "RC",   0,      1,      0ull,   0},
32799         {"DDCD"                        ,        3,      1,      330,    "RC",   0,      1,      0ull,   0},
32800         {"CTS"                         ,        4,      1,      330,    "RO",   1,      1,      0,      0},
32801         {"DSR"                         ,        5,      1,      330,    "RO",   0,      1,      0ull,   0},
32802         {"RI"                          ,        6,      1,      330,    "RO",   0,      1,      0ull,   0},
32803         {"DCD"                         ,        7,      1,      330,    "RO",   0,      1,      0ull,   0},
32804         {"RESERVED_8_63"               ,        8,      56,     330,    "RAZ",  1,      1,      0,      0},
32805         {"RBR"                         ,        0,      8,      331,    "RO",   0,      1,      0ull,   0},
32806         {"RESERVED_8_63"               ,        8,      56,     331,    "RAZ",  1,      1,      0,      0},
32807         {"RFL"                         ,        0,      7,      332,    "RO",   0,      1,      0ull,   0},
32808         {"RESERVED_7_63"               ,        7,      57,     332,    "RAZ",  1,      1,      0,      0},
32809         {"RFWD"                        ,        0,      8,      333,    "WO",   0,      1,      0ull,   0},
32810         {"RFPE"                        ,        8,      1,      333,    "WO",   0,      1,      0ull,   0},
32811         {"RFFE"                        ,        9,      1,      333,    "WO",   0,      1,      0ull,   0},
32812         {"RESERVED_10_63"              ,        10,     54,     333,    "RAZ",  1,      1,      0,      0},
32813         {"SBCR"                        ,        0,      1,      334,    "R/W",  0,      1,      0ull,   0},
32814         {"RESERVED_1_63"               ,        1,      63,     334,    "RAZ",  1,      1,      0,      0},
32815         {"SCR"                         ,        0,      8,      335,    "R/W",  0,      1,      0ull,   0},
32816         {"RESERVED_8_63"               ,        8,      56,     335,    "RAZ",  1,      1,      0,      0},
32817         {"SFE"                         ,        0,      1,      336,    "R/W",  0,      1,      0ull,   0},
32818         {"RESERVED_1_63"               ,        1,      63,     336,    "RAZ",  1,      1,      0,      0},
32819         {"USR"                         ,        0,      1,      337,    "WO",   0,      1,      0ull,   0},
32820         {"SRFR"                        ,        1,      1,      337,    "WO",   0,      1,      0ull,   0},
32821         {"STFR"                        ,        2,      1,      337,    "WO",   0,      1,      0ull,   0},
32822         {"RESERVED_3_63"               ,        3,      61,     337,    "RAZ",  1,      1,      0,      0},
32823         {"SRT"                         ,        0,      2,      338,    "R/W",  0,      1,      0ull,   0},
32824         {"RESERVED_2_63"               ,        2,      62,     338,    "RAZ",  1,      1,      0,      0},
32825         {"SRTS"                        ,        0,      1,      339,    "R/W",  0,      1,      0ull,   0},
32826         {"RESERVED_1_63"               ,        1,      63,     339,    "RAZ",  1,      1,      0,      0},
32827         {"STT"                         ,        0,      2,      340,    "R/W",  0,      1,      0ull,   0},
32828         {"RESERVED_2_63"               ,        2,      62,     340,    "RAZ",  1,      1,      0,      0},
32829         {"TFL"                         ,        0,      7,      341,    "RO",   0,      1,      0ull,   0},
32830         {"RESERVED_7_63"               ,        7,      57,     341,    "RAZ",  1,      1,      0,      0},
32831         {"TFR"                         ,        0,      8,      342,    "RO",   0,      1,      0ull,   0},
32832         {"RESERVED_8_63"               ,        8,      56,     342,    "RAZ",  1,      1,      0,      0},
32833         {"THR"                         ,        0,      8,      343,    "WO",   0,      1,      0ull,   0},
32834         {"RESERVED_8_63"               ,        8,      56,     343,    "RAZ",  1,      1,      0,      0},
32835         {"BUSY"                        ,        0,      1,      344,    "RO",   0,      1,      0ull,   0},
32836         {"TFNF"                        ,        1,      1,      344,    "RO",   0,      1,      1ull,   0},
32837         {"TFE"                         ,        2,      1,      344,    "RO",   0,      1,      1ull,   0},
32838         {"RFNE"                        ,        3,      1,      344,    "RO",   0,      1,      0ull,   0},
32839         {"RFF"                         ,        4,      1,      344,    "RO",   0,      1,      0ull,   0},
32840         {"RESERVED_5_63"               ,        5,      59,     344,    "RAZ",  1,      1,      0,      0},
32841         {"RESERVED_0_2"                ,        0,      3,      345,    "RAZ",  1,      1,      0,      0},
32842         {"BADDR"                       ,        3,      61,     345,    "R/W",  0,      1,      0ull,   0},
32843         {"RESERVED_0_2"                ,        0,      3,      346,    "RAZ",  1,      1,      0,      0},
32844         {"BADDR"                       ,        3,      61,     346,    "R/W",  0,      1,      0ull,   0},
32845         {"DPI_BS"                      ,        0,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32846         {"PDF_BS"                      ,        1,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32847         {"DOB_BS"                      ,        2,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32848         {"NUS_BS"                      ,        3,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32849         {"POS_BS"                      ,        4,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32850         {"POF3_BS"                     ,        5,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32851         {"POF2_BS"                     ,        6,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32852         {"POF1_BS"                     ,        7,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32853         {"POF0_BS"                     ,        8,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32854         {"PIG_BS"                      ,        9,      1,      347,    "RO",   0,      0,      0ull,   0ull},
32855         {"PGF_BS"                      ,        10,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32856         {"RDNL_BS"                     ,        11,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32857         {"PCAD_BS"                     ,        12,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32858         {"PCAC_BS"                     ,        13,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32859         {"RDN_BS"                      ,        14,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32860         {"PCN_BS"                      ,        15,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32861         {"PCNC_BS"                     ,        16,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32862         {"RDP_BS"                      ,        17,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32863         {"DIF_BS"                      ,        18,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32864         {"CSR_BS"                      ,        19,     1,      347,    "RO",   0,      0,      0ull,   0ull},
32865         {"RESERVED_20_63"              ,        20,     44,     347,    "RAZ",  1,      1,      0,      0},
32866         {"BSIZE"                       ,        0,      16,     348,    "R/W",  0,      1,      1024ull,        0},
32867         {"ISIZE"                       ,        16,     7,      348,    "R/W",  0,      1,      0ull,   0},
32868         {"RESERVED_23_63"              ,        23,     41,     348,    "RAZ",  1,      1,      0,      0},
32869         {"NCTL"                        ,        0,      5,      349,    "R/W",  0,      1,      16ull,  0},
32870         {"PCTL"                        ,        5,      5,      349,    "R/W",  0,      1,      16ull,  0},
32871         {"RESERVED_10_63"              ,        10,     54,     349,    "RAZ",  1,      1,      0,      0},
32872         {"TIMER"                       ,        0,      10,     350,    "R/W",  0,      0,      0ull,   50ull},
32873         {"RESERVED_10_31"              ,        10,     22,     350,    "RAZ",  0,      0,      0ull,   0ull},
32874         {"MAX_WORD"                    ,        32,     5,      350,    "R/W",  0,      0,      2ull,   0ull},
32875         {"RESERVED_37_39"              ,        37,     3,      350,    "RAZ",  0,      0,      0ull,   0ull},
32876         {"WAIT_COM"                    ,        40,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32877         {"PCI_WDIS"                    ,        41,     1,      350,    "R/W",  0,      0,      0ull,   0ull},
32878         {"INS0_64B"                    ,        42,     1,      350,    "R/W",  0,      1,      0ull,   0},
32879         {"INS1_64B"                    ,        43,     1,      350,    "R/W",  0,      1,      0ull,   0},
32880         {"INS2_64B"                    ,        44,     1,      350,    "R/W",  0,      1,      0ull,   0},
32881         {"INS3_64B"                    ,        45,     1,      350,    "R/W",  0,      1,      0ull,   0},
32882         {"INS0_ENB"                    ,        46,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32883         {"INS1_ENB"                    ,        47,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32884         {"INS2_ENB"                    ,        48,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32885         {"INS3_ENB"                    ,        49,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32886         {"OUT0_ENB"                    ,        50,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32887         {"OUT1_ENB"                    ,        51,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32888         {"OUT2_ENB"                    ,        52,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32889         {"OUT3_ENB"                    ,        53,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32890         {"DIS_PNIW"                    ,        54,     1,      350,    "R/W",  0,      0,      0ull,   1ull},
32891         {"CHIP_REV"                    ,        55,     8,      350,    "RO",   1,      1,      0,      0},
32892         {"RESERVED_63_63"              ,        63,     1,      350,    "RAZ",  1,      1,      0,      0},
32893         {"DBG_SEL"                     ,        0,      16,     351,    "R/W",  0,      1,      0ull,   0},
32894         {"RESERVED_16_63"              ,        16,     48,     351,    "RAZ",  1,      1,      0,      0},
32895         {"CSIZE"                       ,        0,      14,     352,    "R/W",  0,      1,      0ull,   0},
32896         {"LP_ENB"                      ,        14,     1,      352,    "R/W",  0,      0,      0ull,   1ull},
32897         {"HP_ENB"                      ,        15,     1,      352,    "R/W",  0,      0,      0ull,   1ull},
32898         {"O_MODE"                      ,        16,     1,      352,    "R/W",  0,      0,      0ull,   1ull},
32899         {"O_ES"                        ,        17,     2,      352,    "R/W",  0,      1,      0ull,   0},
32900         {"O_NS"                        ,        19,     1,      352,    "R/W",  0,      1,      0ull,   0},
32901         {"O_RO"                        ,        20,     1,      352,    "R/W",  0,      1,      0ull,   0},
32902         {"O_ADD1"                      ,        21,     1,      352,    "R/W",  0,      0,      0ull,   1ull},
32903         {"FPA_QUE"                     ,        22,     3,      352,    "R/W",  0,      1,      0ull,   0},
32904         {"DWB_ICHK"                    ,        25,     9,      352,    "R/W",  0,      1,      0ull,   0},
32905         {"DWB_DENB"                    ,        34,     1,      352,    "R/W",  0,      0,      0ull,   1ull},
32906         {"B0_LEND"                     ,        35,     1,      352,    "R/W",  0,      0,      0ull,   0ull},
32907         {"RESERVED_36_63"              ,        36,     28,     352,    "RAZ",  1,      1,      0,      0},
32908         {"DBELL"                       ,        0,      32,     353,    "RO",   0,      0,      0ull,   0ull},
32909         {"FCNT"                        ,        32,     7,      353,    "RO",   0,      0,      0ull,   0ull},
32910         {"RESERVED_39_63"              ,        39,     25,     353,    "RAZ",  1,      1,      0,      0},
32911         {"ADDR"                        ,        0,      36,     354,    "RO",   0,      1,      0ull,   0},
32912         {"STATE"                       ,        36,     4,      354,    "RO",   0,      0,      0ull,   0ull},
32913         {"RESERVED_40_63"              ,        40,     24,     354,    "RAZ",  1,      1,      0,      0},
32914         {"DBELL"                       ,        0,      32,     355,    "RO",   0,      0,      0ull,   0ull},
32915         {"FCNT"                        ,        32,     7,      355,    "RO",   0,      0,      0ull,   0ull},
32916         {"RESERVED_39_63"              ,        39,     25,     355,    "RAZ",  1,      1,      0,      0},
32917         {"ADDR"                        ,        0,      36,     356,    "RO",   0,      1,      0ull,   0},
32918         {"STATE"                       ,        36,     4,      356,    "RO",   0,      0,      0ull,   0ull},
32919         {"RESERVED_40_63"              ,        40,     24,     356,    "RAZ",  1,      1,      0,      0},
32920         {"DBELL"                       ,        0,      16,     357,    "R/W",  0,      1,      0ull,   0},
32921         {"RESERVED_16_63"              ,        16,     48,     357,    "RAZ",  1,      1,      0,      0},
32922         {"SADDR"                       ,        0,      36,     358,    "R/W",  0,      1,      0ull,   0},
32923         {"RESERVED_36_63"              ,        36,     28,     358,    "RAZ",  1,      1,      0,      0},
32924         {"ROR"                         ,        0,      1,      359,    "R/W",  0,      1,      0ull,   0},
32925         {"ESR"                         ,        1,      2,      359,    "R/W",  0,      1,      0ull,   0},
32926         {"NSR"                         ,        3,      1,      359,    "R/W",  0,      1,      0ull,   0},
32927         {"USE_CSR"                     ,        4,      1,      359,    "R/W",  0,      0,      0ull,   1ull},
32928         {"D_ROR"                       ,        5,      1,      359,    "R/W",  0,      1,      0ull,   0},
32929         {"D_ESR"                       ,        6,      2,      359,    "R/W",  0,      1,      0ull,   0},
32930         {"D_NSR"                       ,        8,      1,      359,    "R/W",  0,      1,      0ull,   0},
32931         {"PBP_DHI"                     ,        9,      13,     359,    "R/W",  0,      1,      0ull,   0},
32932         {"PKT_RR"                      ,        22,     1,      359,    "R/W",  0,      0,      0ull,   0ull},
32933         {"RESERVED_23_63"              ,        23,     41,     359,    "RAZ",  1,      1,      0,      0},
32934         {"RML_RTO"                     ,        0,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32935         {"RML_WTO"                     ,        1,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32936         {"PCI_RSL"                     ,        2,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32937         {"PO0_2SML"                    ,        3,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32938         {"PO1_2SML"                    ,        4,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32939         {"PO2_2SML"                    ,        5,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32940         {"PO3_2SML"                    ,        6,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32941         {"I0_RTOUT"                    ,        7,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32942         {"I1_RTOUT"                    ,        8,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32943         {"I2_RTOUT"                    ,        9,      1,      360,    "R/W",  0,      0,      0ull,   1ull},
32944         {"I3_RTOUT"                    ,        10,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32945         {"I0_OVERF"                    ,        11,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32946         {"I1_OVERF"                    ,        12,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32947         {"I2_OVERF"                    ,        13,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32948         {"I3_OVERF"                    ,        14,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32949         {"P0_RTOUT"                    ,        15,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32950         {"P1_RTOUT"                    ,        16,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32951         {"P2_RTOUT"                    ,        17,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32952         {"P3_RTOUT"                    ,        18,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32953         {"P0_PERR"                     ,        19,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32954         {"P1_PERR"                     ,        20,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32955         {"P2_PERR"                     ,        21,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32956         {"P3_PERR"                     ,        22,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32957         {"G0_RTOUT"                    ,        23,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32958         {"G1_RTOUT"                    ,        24,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32959         {"G2_RTOUT"                    ,        25,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32960         {"G3_RTOUT"                    ,        26,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32961         {"P0_PPERR"                    ,        27,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32962         {"P1_PPERR"                    ,        28,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32963         {"P2_PPERR"                    ,        29,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32964         {"P3_PPERR"                    ,        30,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32965         {"P0_PTOUT"                    ,        31,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32966         {"P1_PTOUT"                    ,        32,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32967         {"P2_PTOUT"                    ,        33,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32968         {"P3_PTOUT"                    ,        34,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32969         {"I0_PPERR"                    ,        35,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32970         {"I1_PPERR"                    ,        36,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32971         {"I2_PPERR"                    ,        37,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32972         {"I3_PPERR"                    ,        38,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32973         {"WIN_RTO"                     ,        39,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32974         {"P_DPERR"                     ,        40,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32975         {"IOBDMA"                      ,        41,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32976         {"FCR_S_E"                     ,        42,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32977         {"FCR_A_F"                     ,        43,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32978         {"PCR_S_E"                     ,        44,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32979         {"PCR_A_F"                     ,        45,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32980         {"Q2_S_E"                      ,        46,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32981         {"Q2_A_F"                      ,        47,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32982         {"Q3_S_E"                      ,        48,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32983         {"Q3_A_F"                      ,        49,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32984         {"COM_S_E"                     ,        50,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32985         {"COM_A_F"                     ,        51,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32986         {"PNC_S_E"                     ,        52,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32987         {"PNC_A_F"                     ,        53,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32988         {"RWX_S_E"                     ,        54,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32989         {"RDX_S_E"                     ,        55,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32990         {"PCF_P_E"                     ,        56,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32991         {"PCF_P_F"                     ,        57,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32992         {"PDF_P_E"                     ,        58,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32993         {"PDF_P_F"                     ,        59,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32994         {"Q1_S_E"                      ,        60,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32995         {"Q1_A_F"                      ,        61,     1,      360,    "R/W",  0,      0,      0ull,   1ull},
32996         {"RESERVED_62_63"              ,        62,     2,      360,    "RAZ",  1,      1,      0,      0},
32997         {"RML_RTO"                     ,        0,      1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
32998         {"RML_WTO"                     ,        1,      1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
32999         {"PCI_RSL"                     ,        2,      1,      361,    "RO",   0,      0,      0ull,   0ull},
33000         {"PO0_2SML"                    ,        3,      1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33001         {"PO1_2SML"                    ,        4,      1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33002         {"PO2_2SML"                    ,        5,      1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33003         {"PO3_2SML"                    ,        6,      1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33004         {"I0_RTOUT"                    ,        7,      1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33005         {"I1_RTOUT"                    ,        8,      1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33006         {"I2_RTOUT"                    ,        9,      1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33007         {"I3_RTOUT"                    ,        10,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33008         {"I0_OVERF"                    ,        11,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33009         {"I1_OVERF"                    ,        12,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33010         {"I2_OVERF"                    ,        13,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33011         {"I3_OVERF"                    ,        14,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33012         {"P0_RTOUT"                    ,        15,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33013         {"P1_RTOUT"                    ,        16,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33014         {"P2_RTOUT"                    ,        17,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33015         {"P3_RTOUT"                    ,        18,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33016         {"P0_PERR"                     ,        19,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33017         {"P1_PERR"                     ,        20,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33018         {"P2_PERR"                     ,        21,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33019         {"P3_PERR"                     ,        22,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33020         {"G0_RTOUT"                    ,        23,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33021         {"G1_RTOUT"                    ,        24,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33022         {"G2_RTOUT"                    ,        25,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33023         {"G3_RTOUT"                    ,        26,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33024         {"P0_PPERR"                    ,        27,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33025         {"P1_PPERR"                    ,        28,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33026         {"P2_PPERR"                    ,        29,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33027         {"P3_PPERR"                    ,        30,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33028         {"P0_PTOUT"                    ,        31,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33029         {"P1_PTOUT"                    ,        32,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33030         {"P2_PTOUT"                    ,        33,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33031         {"P3_PTOUT"                    ,        34,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33032         {"I0_PPERR"                    ,        35,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33033         {"I1_PPERR"                    ,        36,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33034         {"I2_PPERR"                    ,        37,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33035         {"I3_PPERR"                    ,        38,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33036         {"WIN_RTO"                     ,        39,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33037         {"P_DPERR"                     ,        40,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33038         {"IOBDMA"                      ,        41,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33039         {"FCR_S_E"                     ,        42,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33040         {"FCR_A_F"                     ,        43,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33041         {"PCR_S_E"                     ,        44,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33042         {"PCR_A_F"                     ,        45,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33043         {"Q2_S_E"                      ,        46,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33044         {"Q2_A_F"                      ,        47,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33045         {"Q3_S_E"                      ,        48,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33046         {"Q3_A_F"                      ,        49,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33047         {"COM_S_E"                     ,        50,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33048         {"COM_A_F"                     ,        51,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33049         {"PNC_S_E"                     ,        52,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33050         {"PNC_A_F"                     ,        53,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33051         {"RWX_S_E"                     ,        54,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33052         {"RDX_S_E"                     ,        55,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33053         {"PCF_P_E"                     ,        56,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33054         {"PCF_P_F"                     ,        57,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33055         {"PDF_P_E"                     ,        58,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33056         {"PDF_P_F"                     ,        59,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33057         {"Q1_S_E"                      ,        60,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33058         {"Q1_A_F"                      ,        61,     1,      361,    "R/W1C",        0,      0,      0ull,   0ull},
33059         {"RESERVED_62_63"              ,        62,     2,      361,    "RAZ",  1,      1,      0,      0},
33060         {"DBELL"                       ,        0,      16,     362,    "R/W",  0,      1,      0ull,   0},
33061         {"RESERVED_16_63"              ,        16,     48,     362,    "RAZ",  1,      1,      0,      0},
33062         {"SADDR"                       ,        0,      36,     363,    "R/W",  0,      1,      0ull,   0},
33063         {"RESERVED_36_63"              ,        36,     28,     363,    "RAZ",  1,      1,      0,      0},
33064         {"BA"                          ,        0,      28,     364,    "R/W",  0,      1,      0ull,   0},
33065         {"ROW"                         ,        28,     1,      364,    "R/W",  0,      1,      0ull,   0},
33066         {"ROR"                         ,        29,     1,      364,    "R/W",  0,      1,      0ull,   0},
33067         {"NSW"                         ,        30,     1,      364,    "R/W",  0,      1,      0ull,   0},
33068         {"NSR"                         ,        31,     1,      364,    "R/W",  0,      1,      0ull,   0},
33069         {"ESW"                         ,        32,     2,      364,    "R/W",  0,      1,      0ull,   0},
33070         {"ESR"                         ,        34,     2,      364,    "R/W",  0,      1,      0ull,   0},
33071         {"NMERGE"                      ,        36,     1,      364,    "R/W",  0,      1,      0ull,   0},
33072         {"SHORTL"                      ,        37,     1,      364,    "R/W",  0,      1,      0ull,   0},
33073         {"RESERVED_38_63"              ,        38,     26,     364,    "RAZ",  1,      1,      0,      0},
33074         {"INT_VEC"                     ,        0,      64,     365,    "R/W1C",        0,      0,      0ull,   0ull},
33075         {"SIZE"                        ,        0,      32,     366,    "R/W",  0,      1,      0ull,   0},
33076         {"RESERVED_32_63"              ,        32,     32,     366,    "RAZ",  1,      1,      0,      0},
33077         {"ROR_SL0"                     ,        0,      1,      367,    "R/W",  0,      1,      0ull,   0},
33078         {"NSR_SL0"                     ,        1,      1,      367,    "R/W",  0,      1,      0ull,   0},
33079         {"ESR_SL0"                     ,        2,      2,      367,    "R/W",  0,      1,      0ull,   0},
33080         {"ROR_SL1"                     ,        4,      1,      367,    "R/W",  0,      1,      0ull,   0},
33081         {"NSR_SL1"                     ,        5,      1,      367,    "R/W",  0,      1,      0ull,   0},
33082         {"ESR_SL1"                     ,        6,      2,      367,    "R/W",  0,      1,      0ull,   0},
33083         {"ROR_SL2"                     ,        8,      1,      367,    "R/W",  0,      1,      0ull,   0},
33084         {"NSR_SL2"                     ,        9,      1,      367,    "R/W",  0,      1,      0ull,   0},
33085         {"ESR_SL2"                     ,        10,     2,      367,    "R/W",  0,      1,      0ull,   0},
33086         {"ROR_SL3"                     ,        12,     1,      367,    "R/W",  0,      1,      0ull,   0},
33087         {"NSR_SL3"                     ,        13,     1,      367,    "R/W",  0,      1,      0ull,   0},
33088         {"ESR_SL3"                     ,        14,     2,      367,    "R/W",  0,      1,      0ull,   0},
33089         {"IPTR_O0"                     ,        16,     1,      367,    "R/W",  0,      0,      0ull,   1ull},
33090         {"IPTR_O1"                     ,        17,     1,      367,    "R/W",  0,      0,      0ull,   1ull},
33091         {"IPTR_O2"                     ,        18,     1,      367,    "R/W",  0,      0,      0ull,   1ull},
33092         {"IPTR_O3"                     ,        19,     1,      367,    "R/W",  0,      0,      0ull,   1ull},
33093         {"RESERVED_20_23"              ,        20,     4,      367,    "RAZ",  0,      0,      0ull,   0ull},
33094         {"O0_CSRM"                     ,        24,     1,      367,    "R/W",  0,      0,      0ull,   1ull},
33095         {"O1_CSRM"                     ,        25,     1,      367,    "R/W",  0,      0,      0ull,   1ull},
33096         {"O2_CSRM"                     ,        26,     1,      367,    "R/W",  0,      0,      0ull,   1ull},
33097         {"O3_CSRM"                     ,        27,     1,      367,    "R/W",  0,      0,      0ull,   1ull},
33098         {"O0_RO"                       ,        28,     1,      367,    "R/W",  0,      1,      0ull,   0},
33099         {"O0_NS"                       ,        29,     1,      367,    "R/W",  0,      1,      0ull,   0},
33100         {"O0_ES"                       ,        30,     2,      367,    "R/W",  0,      1,      0ull,   0},
33101         {"O1_RO"                       ,        32,     1,      367,    "R/W",  0,      1,      0ull,   0},
33102         {"O1_NS"                       ,        33,     1,      367,    "R/W",  0,      1,      0ull,   0},
33103         {"O1_ES"                       ,        34,     2,      367,    "R/W",  0,      1,      0ull,   0},
33104         {"O2_RO"                       ,        36,     1,      367,    "R/W",  0,      1,      0ull,   0},
33105         {"O2_NS"                       ,        37,     1,      367,    "R/W",  0,      1,      0ull,   0},
33106         {"O2_ES"                       ,        38,     2,      367,    "R/W",  0,      1,      0ull,   0},
33107         {"O3_RO"                       ,        40,     1,      367,    "R/W",  0,      1,      0ull,   0},
33108         {"O3_NS"                       ,        41,     1,      367,    "R/W",  0,      1,      0ull,   0},
33109         {"O3_ES"                       ,        42,     2,      367,    "R/W",  0,      1,      0ull,   0},
33110         {"P0_BMODE"                    ,        44,     1,      367,    "R/W",  0,      0,      0ull,   0ull},
33111         {"P1_BMODE"                    ,        45,     1,      367,    "R/W",  0,      0,      0ull,   0ull},
33112         {"P2_BMODE"                    ,        46,     1,      367,    "R/W",  0,      0,      0ull,   0ull},
33113         {"P3_BMODE"                    ,        47,     1,      367,    "R/W",  0,      0,      0ull,   0ull},
33114         {"PKT_RR"                      ,        48,     1,      367,    "R/W",  0,      0,      0ull,   0ull},
33115         {"RESERVED_49_63"              ,        49,     15,     367,    "RAZ",  1,      1,      0,      0},
33116         {"NADDR"                       ,        0,      61,     368,    "RO",   0,      1,      0ull,   0},
33117         {"STATE"                       ,        61,     2,      368,    "RO",   0,      0,      0ull,   0ull},
33118         {"RESERVED_63_63"              ,        63,     1,      368,    "RAZ",  1,      1,      0,      0},
33119         {"NADDR"                       ,        0,      61,     369,    "RO",   0,      1,      0ull,   0},
33120         {"STATE"                       ,        61,     3,      369,    "RO",   0,      0,      0ull,   0ull},
33121         {"AVAIL"                       ,        0,      32,     370,    "RO",   0,      0,      0ull,   0ull},
33122         {"FCNT"                        ,        32,     6,      370,    "RO",   0,      0,      0ull,   0ull},
33123         {"RESERVED_38_63"              ,        38,     26,     370,    "RAZ",  1,      1,      0,      0},
33124         {"AVAIL"                       ,        0,      32,     371,    "RO",   0,      0,      0ull,   0ull},
33125         {"FCNT"                        ,        32,     5,      371,    "RO",   0,      0,      0ull,   0ull},
33126         {"RESERVED_37_63"              ,        37,     27,     371,    "RAZ",  1,      1,      0,      0},
33127         {"RD_BRST"                     ,        0,      7,      372,    "R/W",  0,      0,      17ull,  64ull},
33128         {"WR_BRST"                     ,        7,      7,      372,    "R/W",  0,      0,      16ull,  64ull},
33129         {"RESERVED_14_63"              ,        14,     50,     372,    "RAZ",  1,      1,      0,      0},
33130         {"PARK_DEV"                    ,        0,      3,      373,    "R/W",  0,      1,      0ull,   0},
33131         {"PARK_MOD"                    ,        3,      1,      373,    "R/W",  0,      1,      0ull,   0},
33132         {"EN"                          ,        4,      1,      373,    "R/W",  0,      1,      0ull,   0},
33133         {"RESERVED_5_7"                ,        5,      3,      373,    "RAZ",  1,      1,      0,      0},
33134         {"PCI_OVR"                     ,        8,      4,      373,    "R/W",  0,      1,      0ull,   0},
33135         {"HOSTMODE"                    ,        12,     1,      373,    "RO",   1,      1,      0,      0},
33136         {"RESERVED_13_63"              ,        13,     51,     373,    "RAZ",  1,      1,      0,      0},
33137         {"CMD_SIZE"                    ,        0,      11,     374,    "R/W",  0,      0,      9ull,   9ull},
33138         {"RESERVED_11_63"              ,        11,     53,     374,    "RAZ",  1,      1,      0,      0},
33139         {"RSV_A"                       ,        0,      6,      375,    "R/W",  0,      1,      0ull,   0},
33140         {"SKP_LEN"                     ,        6,      7,      375,    "R/W",  0,      1,      0ull,   0},
33141         {"RSV_B"                       ,        13,     1,      375,    "R/W",  0,      1,      0ull,   0},
33142         {"PAR_MODE"                    ,        14,     2,      375,    "R/W",  0,      1,      0ull,   0},
33143         {"RSV_C"                       ,        16,     5,      375,    "R/W",  0,      1,      0ull,   0},
33144         {"USE_IHDR"                    ,        21,     1,      375,    "R/W",  0,      1,      0ull,   0},
33145         {"RSV_D"                       ,        22,     6,      375,    "R/W",  0,      1,      0ull,   0},
33146         {"RSKP_LEN"                    ,        28,     7,      375,    "R/W",  0,      1,      8ull,   0},
33147         {"RSV_E"                       ,        35,     1,      375,    "R/W",  0,      1,      0ull,   0},
33148         {"RPARMODE"                    ,        36,     2,      375,    "R/W",  0,      1,      0ull,   0},
33149         {"RSV_F"                       ,        38,     5,      375,    "R/W",  0,      1,      0ull,   0},
33150         {"PBP"                         ,        43,     1,      375,    "R/W",  0,      1,      0ull,   0},
33151         {"RESERVED_44_63"              ,        44,     20,     375,    "RAZ",  1,      1,      0,      0},
33152         {"RSV_A"                       ,        0,      6,      376,    "R/W",  0,      1,      0ull,   0},
33153         {"SKP_LEN"                     ,        6,      7,      376,    "R/W",  0,      1,      0ull,   0},
33154         {"RSV_B"                       ,        13,     1,      376,    "R/W",  0,      1,      0ull,   0},
33155         {"PAR_MODE"                    ,        14,     2,      376,    "R/W",  0,      1,      0ull,   0},
33156         {"RSV_C"                       ,        16,     5,      376,    "R/W",  0,      1,      0ull,   0},
33157         {"USE_IHDR"                    ,        21,     1,      376,    "R/W",  0,      1,      0ull,   0},
33158         {"RSV_D"                       ,        22,     6,      376,    "R/W",  0,      1,      0ull,   0},
33159         {"RSKP_LEN"                    ,        28,     7,      376,    "R/W",  0,      1,      8ull,   0},
33160         {"RSV_E"                       ,        35,     1,      376,    "R/W",  0,      1,      0ull,   0},
33161         {"RPARMODE"                    ,        36,     2,      376,    "R/W",  0,      1,      0ull,   0},
33162         {"RSV_F"                       ,        38,     5,      376,    "R/W",  0,      1,      0ull,   0},
33163         {"PBP"                         ,        43,     1,      376,    "R/W",  0,      1,      0ull,   0},
33164         {"RESERVED_44_63"              ,        44,     20,     376,    "RAZ",  1,      1,      0,      0},
33165         {"RSV_A"                       ,        0,      6,      377,    "R/W",  0,      1,      0ull,   0},
33166         {"SKP_LEN"                     ,        6,      7,      377,    "R/W",  0,      1,      0ull,   0},
33167         {"RSV_B"                       ,        13,     1,      377,    "R/W",  0,      1,      0ull,   0},
33168         {"PAR_MODE"                    ,        14,     2,      377,    "R/W",  0,      1,      0ull,   0},
33169         {"RSV_C"                       ,        16,     5,      377,    "R/W",  0,      1,      0ull,   0},
33170         {"USE_IHDR"                    ,        21,     1,      377,    "R/W",  0,      1,      0ull,   0},
33171         {"RSV_D"                       ,        22,     6,      377,    "R/W",  0,      1,      0ull,   0},
33172         {"RSKP_LEN"                    ,        28,     7,      377,    "R/W",  0,      1,      8ull,   0},
33173         {"RSV_E"                       ,        35,     1,      377,    "R/W",  0,      1,      0ull,   0},
33174         {"RPARMODE"                    ,        36,     2,      377,    "R/W",  0,      1,      0ull,   0},
33175         {"RSV_F"                       ,        38,     5,      377,    "R/W",  0,      1,      0ull,   0},
33176         {"PBP"                         ,        43,     1,      377,    "R/W",  0,      1,      0ull,   0},
33177         {"RESERVED_44_63"              ,        44,     20,     377,    "RAZ",  1,      1,      0,      0},
33178         {"RSV_A"                       ,        0,      6,      378,    "R/W",  0,      1,      0ull,   0},
33179         {"SKP_LEN"                     ,        6,      7,      378,    "R/W",  0,      1,      0ull,   0},
33180         {"RSV_B"                       ,        13,     1,      378,    "R/W",  0,      1,      0ull,   0},
33181         {"PAR_MODE"                    ,        14,     2,      378,    "R/W",  0,      1,      0ull,   0},
33182         {"RSV_C"                       ,        16,     5,      378,    "R/W",  0,      1,      0ull,   0},
33183         {"USE_IHDR"                    ,        21,     1,      378,    "R/W",  0,      1,      0ull,   0},
33184         {"RSV_D"                       ,        22,     6,      378,    "R/W",  0,      1,      0ull,   0},
33185         {"RSKP_LEN"                    ,        28,     7,      378,    "R/W",  0,      1,      8ull,   0},
33186         {"RSV_E"                       ,        35,     1,      378,    "R/W",  0,      1,      0ull,   0},
33187         {"RPARMODE"                    ,        36,     2,      378,    "R/W",  0,      1,      0ull,   0},
33188         {"RSV_F"                       ,        38,     5,      378,    "R/W",  0,      1,      0ull,   0},
33189         {"PBP"                         ,        43,     1,      378,    "R/W",  0,      1,      0ull,   0},
33190         {"RESERVED_44_63"              ,        44,     20,     378,    "RAZ",  1,      1,      0,      0},
33191         {"ENB"                         ,        0,      4,      379,    "R/W",  0,      0,      15ull,  15ull},
33192         {"BP_ON"                       ,        4,      4,      379,    "RO",   0,      0,      0ull,   0ull},
33193         {"RESERVED_8_63"               ,        8,      56,     379,    "RAZ",  1,      1,      0,      0},
33194         {"MIO"                         ,        0,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33195         {"GMX0"                        ,        1,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33196         {"GMX1"                        ,        2,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33197         {"NPI"                         ,        3,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33198         {"KEY"                         ,        4,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33199         {"FPA"                         ,        5,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33200         {"DFA"                         ,        6,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33201         {"ZIP"                         ,        7,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33202         {"RINT_8"                      ,        8,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33203         {"IPD"                         ,        9,      1,      380,    "RO",   0,      0,      0ull,   0ull},
33204         {"PKO"                         ,        10,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33205         {"TIM"                         ,        11,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33206         {"POW"                         ,        12,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33207         {"RINT_13"                     ,        13,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33208         {"RINT_14"                     ,        14,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33209         {"RINT_15"                     ,        15,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33210         {"L2C"                         ,        16,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33211         {"LMC"                         ,        17,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33212         {"SPX0"                        ,        18,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33213         {"SPX1"                        ,        19,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33214         {"PIP"                         ,        20,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33215         {"RINT_21"                     ,        21,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33216         {"ASX0"                        ,        22,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33217         {"ASX1"                        ,        23,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33218         {"RINT_24"                     ,        24,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33219         {"RINT_25"                     ,        25,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33220         {"RINT_26"                     ,        26,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33221         {"RINT_27"                     ,        27,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33222         {"RINT_28"                     ,        28,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33223         {"RINT_29"                     ,        29,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33224         {"IOB"                         ,        30,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33225         {"RINT_31"                     ,        31,     1,      380,    "RO",   0,      0,      0ull,   0ull},
33226         {"RESERVED_32_63"              ,        32,     32,     380,    "RAZ",  1,      1,      0,      0},
33227         {"SIZE"                        ,        0,      32,     381,    "R/W",  0,      1,      0ull,   0},
33228         {"RESERVED_32_63"              ,        32,     32,     381,    "RAZ",  1,      1,      0,      0},
33229         {"TIME"                        ,        0,      32,     382,    "R/W",  0,      0,      0ull,   131072ull},
33230         {"RESERVED_32_63"              ,        32,     32,     382,    "RAZ",  1,      1,      0,      0},
33231         {"ADDR_V"                      ,        0,      1,      383,    "R/W",  0,      1,      0ull,   0},
33232         {"END_SWP"                     ,        1,      2,      383,    "R/W",  0,      1,      0ull,   0},
33233         {"CA"                          ,        3,      1,      383,    "R/W",  0,      0,      0ull,   0ull},
33234         {"ADDR_IDX"                    ,        4,      14,     383,    "R/W",  0,      1,      0ull,   0},
33235         {"RESERVED_18_31"              ,        18,     14,     383,    "RAZ",  1,      1,      0,      0},
33236         {"VENDID"                      ,        0,      16,     384,    "RO",   0,      0,      6013ull,        6013ull},
33237         {"DEVID"                       ,        16,     16,     384,    "RO",   0,      0,      64ull,  64ull},
33238         {"ISAE"                        ,        0,      1,      385,    "RO",   0,      0,      0ull,   0ull},
33239         {"MSAE"                        ,        1,      1,      385,    "R/W",  0,      0,      0ull,   1ull},
33240         {"ME"                          ,        2,      1,      385,    "R/W",  0,      0,      0ull,   1ull},
33241         {"SCSE"                        ,        3,      1,      385,    "RO",   0,      0,      0ull,   0ull},
33242         {"MWICE"                       ,        4,      1,      385,    "R/W",  0,      0,      0ull,   0ull},
33243         {"VPS"                         ,        5,      1,      385,    "RO",   0,      0,      0ull,   0ull},
33244         {"PEE"                         ,        6,      1,      385,    "R/W",  0,      0,      0ull,   1ull},
33245         {"ADS"                         ,        7,      1,      385,    "RO",   0,      0,      0ull,   0ull},
33246         {"SEE"                         ,        8,      1,      385,    "R/W",  0,      0,      0ull,   1ull},
33247         {"FBBE"                        ,        9,      1,      385,    "R/W",  0,      0,      0ull,   1ull},
33248         {"I_DIS"                       ,        10,     1,      385,    "R/W",  0,      0,      0ull,   0ull},
33249         {"RESERVED_11_18"              ,        11,     8,      385,    "RAZ",  1,      1,      0,      0},
33250         {"I_STAT"                      ,        19,     1,      385,    "RO",   0,      0,      0ull,   0ull},
33251         {"CLE"                         ,        20,     1,      385,    "RO",   0,      0,      1ull,   1ull},
33252         {"M66"                         ,        21,     1,      385,    "RO",   0,      0,      1ull,   1ull},
33253         {"RESERVED_22_22"              ,        22,     1,      385,    "RAZ",  1,      1,      0,      0},
33254         {"FBB"                         ,        23,     1,      385,    "RO",   0,      1,      1ull,   0},
33255         {"MDPE"                        ,        24,     1,      385,    "R/W1C",        0,      0,      0ull,   0ull},
33256         {"DEVT"                        ,        25,     2,      385,    "RO",   0,      0,      1ull,   1ull},
33257         {"STA"                         ,        27,     1,      385,    "R/W1C",        0,      0,      0ull,   0ull},
33258         {"RTA"                         ,        28,     1,      385,    "R/W1C",        0,      0,      0ull,   0ull},
33259         {"RMA"                         ,        29,     1,      385,    "R/W1C",        0,      0,      0ull,   0ull},
33260         {"SSE"                         ,        30,     1,      385,    "R/W1C",        0,      0,      0ull,   0ull},
33261         {"DPE"                         ,        31,     1,      385,    "R/W1C",        0,      0,      0ull,   0ull},
33262         {"RID"                         ,        0,      8,      386,    "RO",   0,      0,      0ull,   0ull},
33263         {"CC"                          ,        8,      24,     386,    "RO",   0,      0,      733184ull,      733184ull},
33264         {"CLS"                         ,        0,      8,      387,    "R/W",  0,      1,      0ull,   0},
33265         {"LT"                          ,        8,      8,      387,    "R/W",  0,      0,      0ull,   64ull},
33266         {"HT"                          ,        16,     8,      387,    "RO",   0,      0,      0ull,   0ull},
33267         {"BCOD"                        ,        24,     4,      387,    "RO",   0,      0,      0ull,   0ull},
33268         {"RESERVED_28_29"              ,        28,     2,      387,    "RAZ",  1,      1,      0,      0},
33269         {"BRB"                         ,        30,     1,      387,    "R/W",  0,      0,      0ull,   0ull},
33270         {"BCAP"                        ,        31,     1,      387,    "RO",   0,      0,      0ull,   0ull},
33271         {"MSPC"                        ,        0,      1,      388,    "RO",   0,      0,      0ull,   0ull},
33272         {"TYP"                         ,        1,      2,      388,    "RO",   0,      0,      2ull,   2ull},
33273         {"PF"                          ,        3,      1,      388,    "RO",   0,      0,      1ull,   1ull},
33274         {"LBASEZ"                      ,        4,      8,      388,    "RO",   0,      0,      0ull,   0ull},
33275         {"LBASE"                       ,        12,     20,     388,    "R/W",  0,      1,      0ull,   0},
33276         {"HBASE"                       ,        0,      32,     389,    "R/W",  0,      1,      0ull,   0},
33277         {"MSPC"                        ,        0,      1,      390,    "RO",   0,      0,      0ull,   0ull},
33278         {"TYP"                         ,        1,      2,      390,    "RO",   0,      0,      2ull,   2ull},
33279         {"PF"                          ,        3,      1,      390,    "RO",   0,      0,      1ull,   1ull},
33280         {"LBASEZ"                      ,        4,      23,     390,    "RO",   0,      0,      0ull,   0ull},
33281         {"LBASE"                       ,        27,     5,      390,    "R/W",  0,      1,      0ull,   0},
33282         {"HBASE"                       ,        0,      32,     391,    "R/W",  0,      1,      0ull,   0},
33283         {"MSPC"                        ,        0,      1,      392,    "RO",   0,      0,      0ull,   0ull},
33284         {"TYP"                         ,        1,      2,      392,    "RO",   0,      0,      2ull,   2ull},
33285         {"PF"                          ,        3,      1,      392,    "RO",   0,      0,      1ull,   1ull},
33286         {"LBASEZ"                      ,        4,      28,     392,    "RO",   0,      0,      0ull,   0ull},
33287         {"HBASEZ"                      ,        0,      7,      393,    "RO",   0,      0,      0ull,   0ull},
33288         {"HBASE"                       ,        7,      25,     393,    "R/W",  0,      1,      0ull,   0},
33289         {"CISP"                        ,        0,      32,     394,    "RO",   0,      0,      0ull,   0ull},
33290         {"SSVID"                       ,        0,      16,     395,    "RO",   0,      0,      6013ull,        6013ull},
33291         {"SSID"                        ,        16,     16,     395,    "RO",   0,      0,      1ull,   1ull},
33292         {"ERBAR_EN"                    ,        0,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
33293         {"RESERVED_1_10"               ,        1,      10,     396,    "RAZ",  1,      1,      0,      0},
33294         {"ERBARZ"                      ,        11,     5,      396,    "RO",   0,      0,      0ull,   0ull},
33295         {"ERBAR"                       ,        16,     16,     396,    "R/W",  0,      1,      0ull,   0},
33296         {"CP"                          ,        0,      8,      397,    "RO",   0,      0,      224ull, 224ull},
33297         {"RESERVED_8_31"               ,        8,      24,     397,    "RAZ",  1,      1,      0,      0},
33298         {"IL"                          ,        0,      8,      398,    "R/W",  0,      1,      0ull,   0},
33299         {"INTA"                        ,        8,      8,      398,    "RO",   0,      0,      1ull,   1ull},
33300         {"MG"                          ,        16,     8,      398,    "RO",   0,      0,      64ull,  64ull},
33301         {"ML"                          ,        24,     8,      398,    "RO",   0,      0,      64ull,  64ull},
33302         {"MLTD"                        ,        0,      1,      399,    "R/W",  0,      0,      0ull,   1ull},
33303         {"TSWC"                        ,        1,      1,      399,    "R/W",  0,      0,      0ull,   0ull},
33304         {"RESERVED_2_2"                ,        2,      1,      399,    "RAZ",  1,      1,      0,      0},
33305         {"DPPMR"                       ,        3,      1,      399,    "R/W",  0,      0,      0ull,   0ull},
33306         {"PBE"                         ,        4,      12,     399,    "R/W",  0,      0,      0ull,   0ull},
33307         {"TILT"                        ,        16,     4,      399,    "R/W",  0,      0,      0ull,   0ull},
33308         {"TSLTE"                       ,        20,     3,      399,    "R/W",  0,      0,      0ull,   0ull},
33309         {"TMAE"                        ,        23,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
33310         {"TWTAE"                       ,        24,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
33311         {"TWSEN"                       ,        25,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
33312         {"TWSEI"                       ,        26,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
33313         {"TRTAE"                       ,        27,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
33314         {"TRDRS"                       ,        28,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
33315         {"RDSATI"                      ,        29,     1,      399,    "R/W",  0,      0,      0ull,   0ull},
33316         {"TRDARD"                      ,        30,     1,      399,    "R/W1C",        0,      0,      0ull,   0ull},
33317         {"TRDNPR"                      ,        31,     1,      399,    "R/W1C",        0,      0,      0ull,   0ull},
33318         {"TSCME"                       ,        0,      32,     400,    "R/W1C",        0,      1,      0ull,   0},
33319         {"TDSRPS"                      ,        0,      32,     401,    "R/W1C",        0,      0,      0ull,   0ull},
33320         {"TDOMC"                       ,        0,      5,      402,    "R/W",  0,      0,      1ull,   1ull},
33321         {"TIDOMC"                      ,        5,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
33322         {"RESERVED_6_6"                ,        6,      1,      402,    "RAZ",  1,      1,      0,      0},
33323         {"TIBDE"                       ,        7,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
33324         {"TIBCD"                       ,        8,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
33325         {"RESERVED_9_10"               ,        9,      2,      402,    "RAZ",  1,      1,      0,      0},
33326         {"TMAPES"                      ,        11,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
33327         {"TMDPES"                      ,        12,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
33328         {"TMSE"                        ,        13,     1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
33329         {"TMEI"                        ,        14,     1,      402,    "RO",   0,      0,      0ull,   0ull},
33330         {"TECI"                        ,        15,     1,      402,    "RO",   0,      0,      0ull,   0ull},
33331         {"TMES"                        ,        16,     8,      402,    "RO",   0,      0,      0ull,   0ull},
33332         {"MDRRMC"                      ,        24,     3,      402,    "R/W",  0,      0,      2ull,   2ull},
33333         {"MDRIMC"                      ,        27,     1,      402,    "R/W",  0,      0,      0ull,   0ull},
33334         {"MDRE"                        ,        28,     1,      402,    "R/W",  0,      0,      0ull,   0ull},
33335         {"MDWE"                        ,        29,     1,      402,    "R/W",  0,      0,      0ull,   0ull},
33336         {"MRBCI"                       ,        30,     1,      402,    "R/W",  0,      0,      0ull,   0ull},
33337         {"MRBCM"                       ,        31,     1,      402,    "R/W",  0,      0,      1ull,   1ull},
33338         {"MDSP"                        ,        0,      32,     403,    "R/W1C",        0,      1,      0ull,   0},
33339         {"SCMRE"                       ,        0,      32,     404,    "R/W1C",        0,      1,      0ull,   0},
33340         {"MTTV"                        ,        0,      8,      405,    "R/W",  0,      0,      0ull,   0ull},
33341         {"MRV"                         ,        8,      8,      405,    "R/W",  0,      0,      0ull,   255ull},
33342         {"MTTA"                        ,        16,     1,      405,    "R/W1C",        0,      0,      0ull,   0ull},
33343         {"MRA"                         ,        17,     1,      405,    "R/W1C",        0,      0,      0ull,   0ull},
33344         {"FLUSH"                       ,        18,     1,      405,    "R/W",  0,      0,      1ull,   1ull},
33345         {"RESERVED_19_24"              ,        19,     6,      405,    "RAZ",  1,      1,      0,      0},
33346         {"MAC"                         ,        25,     7,      405,    "R/W",  0,      0,      0ull,   0ull},
33347         {"PXCID"                       ,        0,      8,      406,    "RO",   0,      0,      7ull,   7ull},
33348         {"NCP"                         ,        8,      8,      406,    "RO",   0,      0,      232ull, 232ull},
33349         {"DPERE"                       ,        16,     1,      406,    "R/W",  0,      0,      0ull,   0ull},
33350         {"ROE"                         ,        17,     1,      406,    "R/W",  0,      0,      1ull,   1ull},
33351         {"MMBC"                        ,        18,     2,      406,    "R/W",  0,      0,      0ull,   0ull},
33352         {"MOST"                        ,        20,     3,      406,    "R/W",  0,      0,      3ull,   3ull},
33353         {"RESERVED_23_31"              ,        23,     9,      406,    "RAZ",  1,      1,      0,      0},
33354         {"FN"                          ,        0,      3,      407,    "RO",   0,      0,      0ull,   0ull},
33355         {"DN"                          ,        3,      5,      407,    "RO",   0,      0,      31ull,  31ull},
33356         {"BN"                          ,        8,      8,      407,    "RO",   0,      1,      17ull,  0},
33357         {"W64"                         ,        16,     1,      407,    "RO",   0,      0,      1ull,   1ull},
33358         {"M133"                        ,        17,     1,      407,    "RO",   0,      0,      1ull,   1ull},
33359         {"SCD"                         ,        18,     1,      407,    "R/W1C",        0,      1,      0ull,   0},
33360         {"USC"                         ,        19,     1,      407,    "R/W1C",        0,      1,      0ull,   0},
33361         {"DC"                          ,        20,     1,      407,    "RO",   0,      0,      0ull,   0ull},
33362         {"MMRBCD"                      ,        21,     2,      407,    "RO",   0,      0,      2ull,   2ull},
33363         {"MOSTD"                       ,        23,     3,      407,    "RO",   0,      0,      3ull,   3ull},
33364         {"MCRSD"                       ,        26,     3,      407,    "RO",   0,      0,      7ull,   7ull},
33365         {"SCEMR"                       ,        29,     1,      407,    "R/W1C",        0,      1,      0ull,   0},
33366         {"RESERVED_30_31"              ,        30,     2,      407,    "RAZ",  1,      1,      0,      0},
33367         {"PMCID"                       ,        0,      8,      408,    "RO",   0,      0,      1ull,   1ull},
33368         {"NCP"                         ,        8,      8,      408,    "RO",   0,      0,      240ull, 240ull},
33369         {"PCIMIV"                      ,        16,     3,      408,    "RO",   0,      0,      2ull,   2ull},
33370         {"PMEC"                        ,        19,     1,      408,    "RO",   0,      0,      0ull,   0ull},
33371         {"RESERVED_20_20"              ,        20,     1,      408,    "RAZ",  1,      1,      0,      0},
33372         {"DSI"                         ,        21,     1,      408,    "RO",   0,      0,      0ull,   0ull},
33373         {"AUXC"                        ,        22,     3,      408,    "RO",   0,      0,      0ull,   0ull},
33374         {"D1S"                         ,        25,     1,      408,    "RO",   0,      0,      0ull,   0ull},
33375         {"D2S"                         ,        26,     1,      408,    "RO",   0,      0,      0ull,   0ull},
33376         {"PMES"                        ,        27,     5,      408,    "RO",   0,      0,      0ull,   0ull},
33377         {"PS"                          ,        0,      2,      409,    "R/W",  0,      0,      0ull,   0ull},
33378         {"RESERVED_2_7"                ,        2,      6,      409,    "RAZ",  1,      1,      0,      0},
33379         {"PMEENS"                      ,        8,      1,      409,    "R/W",  0,      0,      0ull,   0ull},
33380         {"PMDS"                        ,        9,      4,      409,    "R/W",  0,      0,      0ull,   0ull},
33381         {"PMEDSIA"                     ,        13,     2,      409,    "RO",   0,      0,      0ull,   0ull},
33382         {"PMESS"                       ,        15,     1,      409,    "R/W1C",        0,      0,      0ull,   0ull},
33383         {"RESERVED_16_21"              ,        16,     6,      409,    "RAZ",  1,      1,      0,      0},
33384         {"BD3H"                        ,        22,     1,      409,    "RO",   0,      0,      0ull,   0ull},
33385         {"BPCCEN"                      ,        23,     1,      409,    "RO",   0,      0,      0ull,   0ull},
33386         {"PMDIA"                       ,        24,     8,      409,    "RO",   0,      0,      0ull,   0ull},
33387         {"MSICID"                      ,        0,      8,      410,    "RO",   0,      0,      5ull,   5ull},
33388         {"NCP"                         ,        8,      8,      410,    "RO",   0,      0,      0ull,   0ull},
33389         {"MSIEN"                       ,        16,     1,      410,    "R/W",  0,      0,      0ull,   0ull},
33390         {"MMC"                         ,        17,     3,      410,    "RO",   0,      0,      0ull,   0ull},
33391         {"MME"                         ,        20,     3,      410,    "R/W",  0,      0,      0ull,   0ull},
33392         {"M64"                         ,        23,     1,      410,    "RO",   0,      0,      1ull,   1ull},
33393         {"RESERVED_24_31"              ,        24,     8,      410,    "RAZ",  1,      1,      0,      0},
33394         {"RESERVED_0_1"                ,        0,      2,      411,    "RAZ",  1,      1,      0,      0},
33395         {"MSI31T2"                     ,        2,      30,     411,    "R/W",  0,      1,      0ull,   0},
33396         {"MSI"                         ,        0,      32,     412,    "R/W",  0,      1,      0ull,   0},
33397         {"MSIMD"                       ,        0,      16,     413,    "R/W",  0,      1,      0ull,   0},
33398         {"RESERVED_16_31"              ,        16,     16,     413,    "RAZ",  1,      1,      0,      0},
33399         {"PCICNT"                      ,        0,      32,     414,    "R/W",  0,      1,      0ull,   0},
33400         {"AP_SPEED"                    ,        32,     2,      414,    "RO",   1,      1,      0,      0},
33401         {"AP_PCIX"                     ,        34,     1,      414,    "RO",   1,      1,      0,      0},
33402         {"HM_SPEED"                    ,        35,     2,      414,    "RO",   0,      1,      0ull,   0},
33403         {"HM_PCIX"                     ,        37,     1,      414,    "RO",   0,      1,      0ull,   0},
33404         {"RESERVED_38_63"              ,        38,     26,     414,    "RAZ",  1,      1,      0,      0},
33405         {"BAR2_CAX"                    ,        0,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
33406         {"BAR2_ESX"                    ,        1,      2,      415,    "R/W",  0,      1,      0ull,   0},
33407         {"BAR2_ENB"                    ,        3,      1,      415,    "R/W",  0,      0,      0ull,   1ull},
33408         {"TSR_HWM"                     ,        4,      3,      415,    "R/W",  0,      1,      1ull,   0},
33409         {"PMO_FPC"                     ,        7,      3,      415,    "R/W",  0,      0,      0ull,   0ull},
33410         {"PMO_AMOD"                    ,        10,     1,      415,    "R/W",  0,      0,      0ull,   0ull},
33411         {"B12_BIST"                    ,        11,     1,      415,    "RO",   0,      0,      0ull,   0ull},
33412         {"AP_64AD"                     ,        12,     1,      415,    "RO",   0,      1,      0ull,   0},
33413         {"AP_PCIX"                     ,        13,     1,      415,    "RO",   0,      1,      0ull,   0},
33414         {"RESERVED_14_14"              ,        14,     1,      415,    "RAZ",  0,      0,      0ull,   0ull},
33415         {"EN_WFILT"                    ,        15,     1,      415,    "R/W",  0,      0,      0ull,   1ull},
33416         {"SCM"                         ,        16,     1,      415,    "RO",   0,      1,      0ull,   0},
33417         {"SCMTYP"                      ,        17,     1,      415,    "RO",   0,      1,      0ull,   0},
33418         {"BAR2PRES"                    ,        18,     1,      415,    "R/W",  1,      1,      0,      0},
33419         {"ERST_N"                      ,        19,     1,      415,    "RO",   0,      0,      1ull,   1ull},
33420         {"BB0"                         ,        20,     1,      415,    "R/W",  0,      0,      0ull,   0ull},
33421         {"BB1"                         ,        21,     1,      415,    "R/W",  0,      0,      0ull,   0ull},
33422         {"BB_ES"                       ,        22,     2,      415,    "R/W",  0,      0,      0ull,   0ull},
33423         {"BB_CA"                       ,        24,     1,      415,    "R/W",  0,      0,      0ull,   0ull},
33424         {"BB1_SIZ"                     ,        25,     1,      415,    "R/W",  0,      0,      0ull,   0ull},
33425         {"BB1_HOLE"                    ,        26,     3,      415,    "R/W",  0,      0,      0ull,   0ull},
33426         {"RESERVED_29_31"              ,        29,     3,      415,    "RAZ",  1,      1,      0,      0},
33427         {"INC_VAL"                     ,        0,      16,     416,    "R/W",  0,      1,      0ull,   0},
33428         {"RESERVED_16_31"              ,        16,     16,     416,    "RAZ",  1,      1,      0,      0},
33429         {"DMA_CNT"                     ,        0,      32,     417,    "R/W",  0,      0,      0ull,   0ull},
33430         {"PKT_CNT"                     ,        0,      32,     418,    "R/W",  0,      1,      0ull,   0},
33431         {"DMA_TIME"                    ,        0,      32,     419,    "R/W",  0,      1,      0ull,   0},
33432         {"ICNT"                        ,        0,      32,     420,    "R/W1C",        0,      0,      0ull,   0ull},
33433         {"ITR_WABT"                    ,        0,      1,      421,    "R/W",  0,      1,      0ull,   0},
33434         {"IMR_WABT"                    ,        1,      1,      421,    "R/W",  0,      1,      0ull,   0},
33435         {"IMR_WTTO"                    ,        2,      1,      421,    "R/W",  0,      1,      0ull,   0},
33436         {"ITR_ABT"                     ,        3,      1,      421,    "R/W",  0,      1,      0ull,   0},
33437         {"IMR_ABT"                     ,        4,      1,      421,    "R/W",  0,      1,      0ull,   0},
33438         {"IMR_TTO"                     ,        5,      1,      421,    "R/W",  0,      1,      0ull,   0},
33439         {"IMSI_PER"                    ,        6,      1,      421,    "R/W",  0,      1,      0ull,   0},
33440         {"IMSI_TABT"                   ,        7,      1,      421,    "R/W",  0,      1,      0ull,   0},
33441         {"IMSI_MABT"                   ,        8,      1,      421,    "R/W",  0,      1,      0ull,   0},
33442         {"IMSC_MSG"                    ,        9,      1,      421,    "R/W",  0,      1,      0ull,   0},
33443         {"ITSR_ABT"                    ,        10,     1,      421,    "R/W",  0,      1,      0ull,   0},
33444         {"ISERR"                       ,        11,     1,      421,    "R/W",  0,      1,      0ull,   0},
33445         {"IAPERR"                      ,        12,     1,      421,    "R/W",  0,      1,      0ull,   0},
33446         {"IDPERR"                      ,        13,     1,      421,    "R/W",  0,      1,      0ull,   0},
33447         {"ILL_RWR"                     ,        14,     1,      421,    "R/W",  0,      1,      0ull,   0},
33448         {"ILL_RRD"                     ,        15,     1,      421,    "R/W",  0,      1,      0ull,   0},
33449         {"IRSL_INT"                    ,        16,     1,      421,    "R/W",  0,      1,      0ull,   0},
33450         {"IPCNT0"                      ,        17,     1,      421,    "R/W",  0,      1,      0ull,   0},
33451         {"IPCNT1"                      ,        18,     1,      421,    "R/W",  0,      1,      0ull,   0},
33452         {"IPCNT2"                      ,        19,     1,      421,    "R/W",  0,      1,      0ull,   0},
33453         {"IPCNT3"                      ,        20,     1,      421,    "R/W",  0,      1,      0ull,   0},
33454         {"IPTIME0"                     ,        21,     1,      421,    "R/W",  0,      1,      0ull,   0},
33455         {"IPTIME1"                     ,        22,     1,      421,    "R/W",  0,      1,      0ull,   0},
33456         {"IPTIME2"                     ,        23,     1,      421,    "R/W",  0,      1,      0ull,   0},
33457         {"IPTIME3"                     ,        24,     1,      421,    "R/W",  0,      1,      0ull,   0},
33458         {"IDCNT0"                      ,        25,     1,      421,    "R/W",  0,      1,      0ull,   0},
33459         {"IDCNT1"                      ,        26,     1,      421,    "R/W",  0,      1,      0ull,   0},
33460         {"IDTIME0"                     ,        27,     1,      421,    "R/W",  0,      1,      0ull,   0},
33461         {"IDTIME1"                     ,        28,     1,      421,    "R/W",  0,      1,      0ull,   0},
33462         {"DMA0_FI"                     ,        29,     1,      421,    "R/W",  0,      1,      0ull,   0},
33463         {"DMA1_FI"                     ,        30,     1,      421,    "R/W",  0,      1,      0ull,   0},
33464         {"WIN_WR"                      ,        31,     1,      421,    "R/W",  0,      1,      0ull,   0},
33465         {"ILL_WR"                      ,        32,     1,      421,    "R/W",  0,      1,      0ull,   0},
33466         {"ILL_RD"                      ,        33,     1,      421,    "R/W",  0,      1,      0ull,   0},
33467         {"RESERVED_34_63"              ,        34,     30,     421,    "RAZ",  1,      1,      0,      0},
33468         {"RTR_WABT"                    ,        0,      1,      422,    "R/W",  0,      1,      0ull,   0},
33469         {"RMR_WABT"                    ,        1,      1,      422,    "R/W",  0,      1,      0ull,   0},
33470         {"RMR_WTTO"                    ,        2,      1,      422,    "R/W",  0,      1,      0ull,   0},
33471         {"RTR_ABT"                     ,        3,      1,      422,    "R/W",  0,      1,      0ull,   0},
33472         {"RMR_ABT"                     ,        4,      1,      422,    "R/W",  0,      1,      0ull,   0},
33473         {"RMR_TTO"                     ,        5,      1,      422,    "R/W",  0,      1,      0ull,   0},
33474         {"RMSI_PER"                    ,        6,      1,      422,    "R/W",  0,      1,      0ull,   0},
33475         {"RMSI_TABT"                   ,        7,      1,      422,    "R/W",  0,      1,      0ull,   0},
33476         {"RMSI_MABT"                   ,        8,      1,      422,    "R/W",  0,      1,      0ull,   0},
33477         {"RMSC_MSG"                    ,        9,      1,      422,    "R/W",  0,      1,      0ull,   0},
33478         {"RTSR_ABT"                    ,        10,     1,      422,    "R/W",  0,      1,      0ull,   0},
33479         {"RSERR"                       ,        11,     1,      422,    "R/W",  0,      1,      0ull,   0},
33480         {"RAPERR"                      ,        12,     1,      422,    "R/W",  0,      1,      0ull,   0},
33481         {"RDPERR"                      ,        13,     1,      422,    "R/W",  0,      1,      0ull,   0},
33482         {"ILL_RWR"                     ,        14,     1,      422,    "R/W",  0,      1,      0ull,   0},
33483         {"ILL_RRD"                     ,        15,     1,      422,    "R/W",  0,      1,      0ull,   0},
33484         {"RRSL_INT"                    ,        16,     1,      422,    "R/W",  0,      1,      0ull,   0},
33485         {"RPCNT0"                      ,        17,     1,      422,    "R/W",  0,      1,      0ull,   0},
33486         {"RPCNT1"                      ,        18,     1,      422,    "R/W",  0,      1,      0ull,   0},
33487         {"RPCNT2"                      ,        19,     1,      422,    "R/W",  0,      1,      0ull,   0},
33488         {"RPCNT3"                      ,        20,     1,      422,    "R/W",  0,      1,      0ull,   0},
33489         {"RPTIME0"                     ,        21,     1,      422,    "R/W",  0,      1,      0ull,   0},
33490         {"RPTIME1"                     ,        22,     1,      422,    "R/W",  0,      1,      0ull,   0},
33491         {"RPTIME2"                     ,        23,     1,      422,    "R/W",  0,      1,      0ull,   0},
33492         {"RPTIME3"                     ,        24,     1,      422,    "R/W",  0,      1,      0ull,   0},
33493         {"RDCNT0"                      ,        25,     1,      422,    "R/W",  0,      1,      0ull,   0},
33494         {"RDCNT1"                      ,        26,     1,      422,    "R/W",  0,      1,      0ull,   0},
33495         {"RDTIME0"                     ,        27,     1,      422,    "R/W",  0,      1,      0ull,   0},
33496         {"RDTIME1"                     ,        28,     1,      422,    "R/W",  0,      1,      0ull,   0},
33497         {"DMA0_FI"                     ,        29,     1,      422,    "R/W",  0,      1,      0ull,   0},
33498         {"DMA1_FI"                     ,        30,     1,      422,    "R/W",  0,      1,      0ull,   0},
33499         {"WIN_WR"                      ,        31,     1,      422,    "R/W",  0,      1,      0ull,   0},
33500         {"ILL_WR"                      ,        32,     1,      422,    "R/W",  0,      1,      0ull,   0},
33501         {"ILL_RD"                      ,        33,     1,      422,    "R/W",  0,      1,      0ull,   0},
33502         {"RESERVED_34_63"              ,        34,     30,     422,    "RAZ",  1,      1,      0,      0},
33503         {"TR_WABT"                     ,        0,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33504         {"MR_WABT"                     ,        1,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33505         {"MR_WTTO"                     ,        2,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33506         {"TR_ABT"                      ,        3,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33507         {"MR_ABT"                      ,        4,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33508         {"MR_TTO"                      ,        5,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33509         {"MSI_PER"                     ,        6,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33510         {"MSI_TABT"                    ,        7,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33511         {"MSI_MABT"                    ,        8,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33512         {"MSC_MSG"                     ,        9,      1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33513         {"TSR_ABT"                     ,        10,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33514         {"SERR"                        ,        11,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33515         {"APERR"                       ,        12,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33516         {"DPERR"                       ,        13,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33517         {"ILL_RWR"                     ,        14,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33518         {"ILL_RRD"                     ,        15,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33519         {"RSL_INT"                     ,        16,     1,      423,    "RO",   0,      0,      0ull,   0ull},
33520         {"PCNT0"                       ,        17,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33521         {"PCNT1"                       ,        18,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33522         {"PCNT2"                       ,        19,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33523         {"PCNT3"                       ,        20,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33524         {"PTIME0"                      ,        21,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33525         {"PTIME1"                      ,        22,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33526         {"PTIME2"                      ,        23,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33527         {"PTIME3"                      ,        24,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33528         {"DCNT0"                       ,        25,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33529         {"DCNT1"                       ,        26,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33530         {"DTIME0"                      ,        27,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33531         {"DTIME1"                      ,        28,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33532         {"DMA0_FI"                     ,        29,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33533         {"DMA1_FI"                     ,        30,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33534         {"WIN_WR"                      ,        31,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33535         {"ILL_WR"                      ,        32,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33536         {"ILL_RD"                      ,        33,     1,      423,    "R/W1C",        0,      0,      0ull,   0ull},
33537         {"RESERVED_34_63"              ,        34,     30,     423,    "RAZ",  1,      1,      0,      0},
33538         {"TR_WABT"                     ,        0,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33539         {"MR_WABT"                     ,        1,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33540         {"MR_WTTO"                     ,        2,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33541         {"TR_ABT"                      ,        3,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33542         {"MR_ABT"                      ,        4,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33543         {"MR_TTO"                      ,        5,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33544         {"MSI_PER"                     ,        6,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33545         {"MSI_TABT"                    ,        7,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33546         {"MSI_MABT"                    ,        8,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33547         {"MSC_MSG"                     ,        9,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33548         {"TSR_ABT"                     ,        10,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33549         {"SERR"                        ,        11,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33550         {"APERR"                       ,        12,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33551         {"DPERR"                       ,        13,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33552         {"ILL_RWR"                     ,        14,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33553         {"ILL_RRD"                     ,        15,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33554         {"RSL_INT"                     ,        16,     1,      424,    "RO",   0,      0,      0ull,   0ull},
33555         {"PCNT0"                       ,        17,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33556         {"PCNT1"                       ,        18,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33557         {"PCNT2"                       ,        19,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33558         {"PCNT3"                       ,        20,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33559         {"PTIME0"                      ,        21,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33560         {"PTIME1"                      ,        22,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33561         {"PTIME2"                      ,        23,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33562         {"PTIME3"                      ,        24,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33563         {"DCNT0"                       ,        25,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33564         {"DCNT1"                       ,        26,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33565         {"DTIME0"                      ,        27,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33566         {"DTIME1"                      ,        28,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33567         {"DMA0_FI"                     ,        29,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33568         {"DMA1_FI"                     ,        30,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33569         {"WIN_WR"                      ,        31,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33570         {"ILL_WR"                      ,        32,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33571         {"ILL_RD"                      ,        33,     1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
33572         {"RESERVED_34_63"              ,        34,     30,     424,    "RAZ",  1,      1,      0,      0},
33573         {"INTR"                        ,        0,      6,      425,    "WO",   0,      1,      0ull,   0},
33574         {"RESERVED_6_31"               ,        6,      26,     425,    "R/W",  1,      1,      0,      0},
33575         {"PTR_CNT"                     ,        0,      16,     426,    "R/W",  0,      1,      0ull,   0},
33576         {"PKT_CNT"                     ,        16,     16,     426,    "R/W",  0,      1,      0ull,   0},
33577         {"PKT_CNT"                     ,        0,      32,     427,    "RO",   0,      0,      0ull,   0ull},
33578         {"PKT_CNT"                     ,        0,      32,     428,    "R/W",  0,      1,      0ull,   0},
33579         {"PKT_TIME"                    ,        0,      32,     429,    "R/W",  0,      1,      0ull,   0},
33580         {"PREFETCH"                    ,        0,      3,      430,    "R/W",  0,      0,      0ull,   2ull},
33581         {"MIN_DATA"                    ,        3,      6,      430,    "R/W",  0,      0,      0ull,   4ull},
33582         {"RESERVED_9_31"               ,        9,      23,     430,    "RAZ",  1,      1,      0,      0},
33583         {"PREFETCH"                    ,        0,      3,      431,    "R/W",  0,      0,      0ull,   3ull},
33584         {"MIN_DATA"                    ,        3,      6,      431,    "R/W",  0,      0,      0ull,   6ull},
33585         {"RESERVED_9_31"               ,        9,      23,     431,    "RAZ",  1,      1,      0,      0},
33586         {"PREFETCH"                    ,        0,      3,      432,    "R/W",  0,      0,      0ull,   3ull},
33587         {"MIN_DATA"                    ,        3,      6,      432,    "R/W",  0,      0,      0ull,   6ull},
33588         {"RESERVED_9_31"               ,        9,      23,     432,    "RAZ",  1,      1,      0,      0},
33589         {"CNT"                         ,        0,      31,     433,    "R/W",  0,      0,      10000ull,       10000ull},
33590         {"ENB"                         ,        31,     1,      433,    "R/W",  0,      0,      0ull,   1ull},
33591         {"RESERVED_32_63"              ,        32,     32,     433,    "RAZ",  1,      1,      0,      0},
33592         {"SCM"                         ,        0,      32,     434,    "RO",   0,      1,      0ull,   0},
33593         {"RESERVED_32_63"              ,        32,     32,     434,    "RAZ",  1,      1,      0,      0},
33594         {"TSR"                         ,        0,      36,     435,    "RO",   0,      1,      0ull,   0},
33595         {"RESERVED_36_63"              ,        36,     28,     435,    "RAZ",  1,      1,      0,      0},
33596         {"RESERVED_0_2"                ,        0,      3,      436,    "RAZ",  1,      1,      0,      0},
33597         {"RD_ADDR"                     ,        3,      45,     436,    "R/W",  0,      1,      0ull,   0},
33598         {"IOBIT"                       ,        48,     1,      436,    "RAZ",  0,      0,      0ull,   0ull},
33599         {"RESERVED_49_63"              ,        49,     15,     436,    "RAZ",  1,      1,      0,      0},
33600         {"RD_DATA"                     ,        0,      64,     437,    "RO",   0,      1,      0ull,   0},
33601         {"RESERVED_0_2"                ,        0,      3,      438,    "RAZ",  1,      1,      0,      0},
33602         {"WR_ADDR"                     ,        3,      45,     438,    "R/W",  0,      1,      0ull,   0},
33603         {"IOBIT"                       ,        48,     1,      438,    "RAZ",  0,      0,      0ull,   0ull},
33604         {"RESERVED_49_63"              ,        49,     15,     438,    "RAZ",  1,      1,      0,      0},
33605         {"WR_DATA"                     ,        0,      64,     439,    "R/W",  0,      1,      0ull,   0},
33606         {"WR_MASK"                     ,        0,      8,      440,    "R/W",  0,      0,      0ull,   0ull},
33607         {"RESERVED_8_63"               ,        8,      56,     440,    "RAZ",  1,      1,      0,      0},
33608         {"LOWATER"                     ,        0,      5,      441,    "R/W",  0,      0,      4ull,   4ull},
33609         {"RESERVED_5_7"                ,        5,      3,      441,    "RAZ",  0,      1,      0ull,   0},
33610         {"HIWATER"                     ,        8,      5,      441,    "R/W",  0,      0,      24ull,  24ull},
33611         {"RESERVED_13_62"              ,        13,     50,     441,    "RAZ",  0,      1,      0ull,   0},
33612         {"BCKPRS"                      ,        63,     1,      441,    "RO",   0,      0,      0ull,   0ull},
33613         {"BIST"                        ,        0,      18,     442,    "RO",   0,      0,      0ull,   0ull},
33614         {"RESERVED_18_63"              ,        18,     46,     442,    "RAZ",  1,      1,      0,      0},
33615         {"REFLECT"                     ,        0,      1,      443,    "R/W",  0,      0,      1ull,   1ull},
33616         {"INVRES"                      ,        1,      1,      443,    "R/W",  0,      0,      1ull,   1ull},
33617         {"RESERVED_2_63"               ,        2,      62,     443,    "RAZ",  1,      1,      0,      0},
33618         {"IV"                          ,        0,      32,     444,    "R/W",  0,      0,      1185899593ull,  1185899593ull},
33619         {"RESERVED_32_63"              ,        32,     32,     444,    "RAZ",  1,      1,      0,      0},
33620         {"DPRT"                        ,        0,      16,     445,    "R/W",  0,      0,      0ull,   0ull},
33621         {"UDP"                         ,        16,     1,      445,    "R/W",  0,      0,      0ull,   0ull},
33622         {"TCP"                         ,        17,     1,      445,    "R/W",  0,      0,      0ull,   0ull},
33623         {"RESERVED_18_63"              ,        18,     46,     445,    "RAZ",  1,      1,      0,      0},
33624         {"NIP_SHF"                     ,        0,      3,      446,    "R/W",  0,      0,      0ull,   0ull},
33625         {"RESERVED_3_7"                ,        3,      5,      446,    "RAZ",  1,      1,      0,      0},
33626         {"RAW_SHF"                     ,        8,      3,      446,    "R/W",  0,      0,      0ull,   0ull},
33627         {"RESERVED_11_15"              ,        11,     5,      446,    "RAZ",  1,      1,      0,      0},
33628         {"MAX_L2"                      ,        16,     1,      446,    "R/W",  0,      0,      0ull,   0ull},
33629         {"IP6_UDP"                     ,        17,     1,      446,    "R/W",  0,      0,      1ull,   1ull},
33630         {"TAG_SYN"                     ,        18,     1,      446,    "R/W",  0,      0,      0ull,   0ull},
33631         {"RESERVED_19_63"              ,        19,     45,     446,    "RAZ",  1,      1,      0,      0},
33632         {"IP_CHK"                      ,        0,      1,      447,    "R/W",  0,      0,      1ull,   1ull},
33633         {"IP_MAL"                      ,        1,      1,      447,    "R/W",  0,      0,      1ull,   1ull},
33634         {"IP_HOP"                      ,        2,      1,      447,    "R/W",  0,      0,      1ull,   1ull},
33635         {"IP4_OPTS"                    ,        3,      1,      447,    "R/W",  0,      0,      1ull,   1ull},
33636         {"IP6_EEXT"                    ,        4,      2,      447,    "R/W",  0,      0,      1ull,   3ull},
33637         {"RESERVED_6_7"                ,        6,      2,      447,    "RAZ",  0,      1,      0ull,   0},
33638         {"L4_MAL"                      ,        8,      1,      447,    "R/W",  0,      0,      1ull,   1ull},
33639         {"L4_PRT"                      ,        9,      1,      447,    "R/W",  0,      0,      1ull,   1ull},
33640         {"L4_CHK"                      ,        10,     1,      447,    "R/W",  0,      0,      1ull,   1ull},
33641         {"L4_LEN"                      ,        11,     1,      447,    "R/W",  0,      0,      1ull,   1ull},
33642         {"TCP_FLAG"                    ,        12,     1,      447,    "R/W",  0,      0,      1ull,   1ull},
33643         {"L2_MAL"                      ,        13,     1,      447,    "R/W",  0,      0,      1ull,   1ull},
33644         {"VS_QOS"                      ,        14,     1,      447,    "R/W",  0,      0,      0ull,   0ull},
33645         {"VS_WQE"                      ,        15,     1,      447,    "R/W",  0,      0,      0ull,   0ull},
33646         {"IGNRS"                       ,        16,     1,      447,    "R/W",  0,      0,      0ull,   0ull},
33647         {"RESERVED_17_63"              ,        17,     47,     447,    "RAZ",  0,      0,      0ull,   0ull},
33648         {"PKTDRP"                      ,        0,      1,      448,    "R/W",  0,      0,      0ull,   0ull},
33649         {"CRCERR"                      ,        1,      1,      448,    "R/W",  0,      0,      0ull,   0ull},
33650         {"BCKPRS"                      ,        2,      1,      448,    "R/W",  0,      0,      0ull,   0ull},
33651         {"PRTNXA"                      ,        3,      1,      448,    "R/W",  0,      0,      0ull,   0ull},
33652         {"BADTAG"                      ,        4,      1,      448,    "R/W",  0,      0,      0ull,   0ull},
33653         {"SKPRUNT"                     ,        5,      1,      448,    "R/W",  0,      0,      0ull,   0ull},
33654         {"TODOOVR"                     ,        6,      1,      448,    "R/W",  0,      0,      0ull,   0ull},
33655         {"FEPERR"                      ,        7,      1,      448,    "R/W",  0,      0,      0ull,   0ull},
33656         {"BEPERR"                      ,        8,      1,      448,    "R/W",  0,      0,      0ull,   0ull},
33657         {"RESERVED_9_11"               ,        9,      3,      448,    "RAZ",  1,      1,      0,      0},
33658         {"PUNYERR"                     ,        12,     1,      448,    "R/W",  0,      0,      0ull,   0ull},
33659         {"RESERVED_13_63"              ,        13,     51,     448,    "RAZ",  1,      1,      0,      0},
33660         {"PKTDRP"                      ,        0,      1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33661         {"CRCERR"                      ,        1,      1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33662         {"BCKPRS"                      ,        2,      1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33663         {"PRTNXA"                      ,        3,      1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33664         {"BADTAG"                      ,        4,      1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33665         {"SKPRUNT"                     ,        5,      1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33666         {"TODOOVR"                     ,        6,      1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33667         {"FEPERR"                      ,        7,      1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33668         {"BEPERR"                      ,        8,      1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33669         {"RESERVED_9_11"               ,        9,      3,      449,    "RAZ",  1,      1,      0,      0},
33670         {"PUNYERR"                     ,        12,     1,      449,    "R/W1C",        0,      0,      0ull,   0ull},
33671         {"RESERVED_13_63"              ,        13,     51,     449,    "RAZ",  1,      1,      0,      0},
33672         {"OFFSET"                      ,        0,      3,      450,    "R/W",  0,      0,      0ull,   0ull},
33673         {"RESERVED_3_63"               ,        3,      61,     450,    "RAZ",  1,      1,      0,      0},
33674         {"SKIP"                        ,        0,      7,      451,    "R/W",  0,      0,      0ull,   0ull},
33675         {"RESERVED_7_7"                ,        7,      1,      451,    "RAZ",  1,      1,      0,      0},
33676         {"MODE"                        ,        8,      2,      451,    "R/W",  0,      0,      0ull,   0ull},
33677         {"RESERVED_10_11"              ,        10,     2,      451,    "RAZ",  1,      1,      0,      0},
33678         {"CRC_EN"                      ,        12,     1,      451,    "R/W",  0,      0,      1ull,   1ull},
33679         {"RESERVED_13_15"              ,        13,     3,      451,    "RAZ",  1,      1,      0,      0},
33680         {"QOS_VLAN"                    ,        16,     1,      451,    "R/W",  0,      0,      0ull,   0ull},
33681         {"QOS_DIFF"                    ,        17,     1,      451,    "R/W",  0,      0,      0ull,   0ull},
33682         {"QOS_VOD"                     ,        18,     1,      451,    "R/W",  0,      0,      0ull,   0ull},
33683         {"RESERVED_19_19"              ,        19,     1,      451,    "RAZ",  1,      1,      0,      0},
33684         {"QOS_WAT"                     ,        20,     4,      451,    "R/W",  0,      0,      0ull,   0ull},
33685         {"QOS"                         ,        24,     3,      451,    "R/W",  0,      0,      0ull,   0ull},
33686         {"RESERVED_27_27"              ,        27,     1,      451,    "RAZ",  1,      1,      0,      0},
33687         {"GRP_WAT"                     ,        28,     4,      451,    "R/W",  0,      0,      0ull,   0ull},
33688         {"INST_HDR"                    ,        32,     1,      451,    "R/W",  0,      0,      0ull,   0ull},
33689         {"DYN_RS"                      ,        33,     1,      451,    "R/W",  0,      0,      0ull,   0ull},
33690         {"TAG_INC"                     ,        34,     2,      451,    "R/W",  0,      0,      0ull,   0ull},
33691         {"RAWDRP"                      ,        36,     1,      451,    "R/W",  0,      0,      0ull,   0ull},
33692         {"RESERVED_37_63"              ,        37,     27,     451,    "RAZ",  1,      1,      0,      0},
33693         {"GRP"                         ,        0,      4,      452,    "R/W",  0,      0,      0ull,   0ull},
33694         {"NON_TAG_TYPE"                ,        4,      2,      452,    "R/W",  0,      0,      0ull,   0ull},
33695         {"IP4_TAG_TYPE"                ,        6,      2,      452,    "R/W",  0,      0,      0ull,   0ull},
33696         {"IP6_TAG_TYPE"                ,        8,      2,      452,    "R/W",  0,      0,      0ull,   0ull},
33697         {"TCP4_TAG_TYPE"               ,        10,     2,      452,    "R/W",  0,      0,      0ull,   0ull},
33698         {"TCP6_TAG_TYPE"               ,        12,     2,      452,    "R/W",  0,      0,      0ull,   0ull},
33699         {"IP4_SRC_FLAG"                ,        14,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33700         {"IP6_SRC_FLAG"                ,        15,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33701         {"IP4_DST_FLAG"                ,        16,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33702         {"IP6_DST_FLAG"                ,        17,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33703         {"IP4_PCTL_FLAG"               ,        18,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33704         {"IP6_NXTH_FLAG"               ,        19,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33705         {"IP4_SPRT_FLAG"               ,        20,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33706         {"IP6_SPRT_FLAG"               ,        21,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33707         {"IP4_DPRT_FLAG"               ,        22,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33708         {"IP6_DPRT_FLAG"               ,        23,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33709         {"INC_PRT_FLAG"                ,        24,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33710         {"INC_VLAN"                    ,        25,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33711         {"INC_VS"                      ,        26,     2,      452,    "R/W",  0,      0,      0ull,   0ull},
33712         {"TAG_MODE"                    ,        28,     2,      452,    "R/W",  0,      0,      0ull,   0ull},
33713         {"RESERVED_30_30"              ,        30,     1,      452,    "RAZ",  0,      0,      0ull,   0ull},
33714         {"GRPTAG"                      ,        31,     1,      452,    "R/W",  0,      0,      0ull,   0ull},
33715         {"GRPTAGMASK"                  ,        32,     4,      452,    "R/W",  0,      0,      0ull,   0ull},
33716         {"GRPTAGBASE"                  ,        36,     4,      452,    "R/W",  0,      0,      0ull,   0ull},
33717         {"RESERVED_40_63"              ,        40,     24,     452,    "RAZ",  1,      1,      0,      0},
33718         {"QOS"                         ,        0,      3,      453,    "R/W",  0,      0,      0ull,   0ull},
33719         {"RESERVED_3_63"               ,        3,      61,     453,    "RAZ",  1,      1,      0,      0},
33720         {"QOS"                         ,        0,      3,      454,    "R/W",  0,      0,      0ull,   0ull},
33721         {"RESERVED_3_63"               ,        3,      61,     454,    "RAZ",  1,      1,      0,      0},
33722         {"MATCH_VALUE"                 ,        0,      16,     455,    "R/W",  0,      0,      0ull,   0ull},
33723         {"MATCH_TYPE"                  ,        16,     2,      455,    "R/W",  0,      0,      0ull,   0ull},
33724         {"RESERVED_18_19"              ,        18,     2,      455,    "RAZ",  1,      1,      0,      0},
33725         {"QOS"                         ,        20,     3,      455,    "R/W",  0,      0,      0ull,   0ull},
33726         {"RESERVED_23_23"              ,        23,     1,      455,    "RAZ",  1,      1,      0,      0},
33727         {"GRP"                         ,        24,     4,      455,    "R/W",  0,      0,      0ull,   0ull},
33728         {"RESERVED_28_31"              ,        28,     4,      455,    "RAZ",  1,      1,      0,      0},
33729         {"MASK"                        ,        32,     16,     455,    "R/W",  0,      0,      0ull,   0ull},
33730         {"RESERVED_48_63"              ,        48,     16,     455,    "RAZ",  1,      1,      0,      0},
33731         {"WORD"                        ,        0,      56,     456,    "R/W",  0,      0,      0ull,   0ull},
33732         {"RESERVED_56_63"              ,        56,     8,      456,    "RAZ",  1,      1,      0,      0},
33733         {"RST"                         ,        0,      1,      457,    "R/W",  0,      0,      0ull,   0ull},
33734         {"RESERVED_1_63"               ,        1,      63,     457,    "RAZ",  1,      1,      0,      0},
33735         {"DRP_OCTS"                    ,        0,      32,     458,    "R/W",  0,      1,      0ull,   0},
33736         {"DRP_PKTS"                    ,        32,     32,     458,    "R/W",  0,      1,      0ull,   0},
33737         {"OCTS"                        ,        0,      48,     459,    "R/W",  0,      1,      0ull,   0},
33738         {"RESERVED_48_63"              ,        48,     16,     459,    "RAZ",  1,      1,      0,      0},
33739         {"RAW"                         ,        0,      32,     460,    "R/W",  0,      1,      0ull,   0},
33740         {"PKTS"                        ,        32,     32,     460,    "R/W",  0,      1,      0ull,   0},
33741         {"MCST"                        ,        0,      32,     461,    "R/W",  0,      1,      0ull,   0},
33742         {"BCST"                        ,        32,     32,     461,    "R/W",  0,      1,      0ull,   0},
33743         {"H64"                         ,        0,      32,     462,    "R/W",  0,      1,      0ull,   0},
33744         {"H65TO127"                    ,        32,     32,     462,    "R/W",  0,      1,      0ull,   0},
33745         {"H128TO255"                   ,        0,      32,     463,    "R/W",  0,      1,      0ull,   0},
33746         {"H256TO511"                   ,        32,     32,     463,    "R/W",  0,      1,      0ull,   0},
33747         {"H512TO1023"                  ,        0,      32,     464,    "R/W",  0,      1,      0ull,   0},
33748         {"H1024TO1518"                 ,        32,     32,     464,    "R/W",  0,      1,      0ull,   0},
33749         {"H1519"                       ,        0,      32,     465,    "R/W",  0,      1,      0ull,   0},
33750         {"FCS"                         ,        32,     32,     465,    "R/W",  0,      1,      0ull,   0},
33751         {"UNDERSZ"                     ,        0,      32,     466,    "R/W",  0,      1,      0ull,   0},
33752         {"FRAG"                        ,        32,     32,     466,    "R/W",  0,      1,      0ull,   0},
33753         {"OVERSZ"                      ,        0,      32,     467,    "R/W",  0,      1,      0ull,   0},
33754         {"JABBER"                      ,        32,     32,     467,    "R/W",  0,      1,      0ull,   0},
33755         {"RDCLR"                       ,        0,      1,      468,    "R/W",  0,      0,      1ull,   1ull},
33756         {"RESERVED_1_63"               ,        1,      63,     468,    "RAZ",  1,      1,      0,      0},
33757         {"ERRS"                        ,        0,      16,     469,    "R/W",  0,      1,      0ull,   0},
33758         {"RESERVED_16_63"              ,        16,     48,     469,    "RAZ",  1,      1,      0,      0},
33759         {"OCTS"                        ,        0,      48,     470,    "R/W",  0,      1,      0ull,   0},
33760         {"RESERVED_48_63"              ,        48,     16,     470,    "RAZ",  1,      1,      0,      0},
33761         {"PKTS"                        ,        0,      32,     471,    "R/W",  0,      1,      0ull,   0},
33762         {"RESERVED_32_63"              ,        32,     32,     471,    "RAZ",  1,      1,      0,      0},
33763         {"EN"                          ,        0,      8,      472,    "R/W",  0,      0,      0ull,   0ull},
33764         {"RESERVED_8_63"               ,        8,      56,     472,    "RAZ",  1,      1,      0,      0},
33765         {"MASK"                        ,        0,      16,     473,    "R/W",  0,      0,      0ull,   0ull},
33766         {"RESERVED_16_63"              ,        16,     48,     473,    "RAZ",  1,      1,      0,      0},
33767         {"SRC"                         ,        0,      16,     474,    "R/W",  0,      0,      0ull,   0ull},
33768         {"DST"                         ,        16,     16,     474,    "R/W",  0,      0,      0ull,   0ull},
33769         {"RESERVED_32_63"              ,        32,     32,     474,    "RAZ",  1,      1,      0,      0},
33770         {"ENTRY"                       ,        0,      62,     475,    "RO",   1,      1,      0,      0},
33771         {"RESERVED_62_62"              ,        62,     1,      475,    "RAZ",  1,      1,      0,      0},
33772         {"VAL"                         ,        63,     1,      475,    "RO",   1,      1,      0,      0},
33773         {"COUNT"                       ,        0,      32,     476,    "R/W1C",        1,      0,      0,      0ull},
33774         {"RESERVED_32_63"              ,        32,     32,     476,    "RAZ",  1,      1,      0,      0},
33775         {"COUNT"                       ,        0,      48,     477,    "R/W1C",        1,      0,      0,      0ull},
33776         {"RESERVED_48_63"              ,        48,     16,     477,    "RAZ",  1,      1,      0,      0},
33777         {"SIZE"                        ,        0,      16,     478,    "RO",   1,      0,      0,      0ull},
33778         {"SEGS"                        ,        16,     6,      478,    "RO",   1,      0,      0,      0ull},
33779         {"CMD"                         ,        22,     14,     478,    "RO",   1,      0,      0,      0ull},
33780         {"FAU"                         ,        36,     28,     478,    "RO",   1,      0,      0,      0ull},
33781         {"PTR"                         ,        0,      40,     479,    "RO",   1,      0,      0,      0ull},
33782         {"SIZE"                        ,        40,     16,     479,    "RO",   1,      0,      0,      0ull},
33783         {"POOL"                        ,        56,     3,      479,    "RO",   1,      0,      0,      0ull},
33784         {"BACK"                        ,        59,     4,      479,    "RO",   1,      0,      0,      0ull},
33785         {"I"                           ,        63,     1,      479,    "RO",   1,      0,      0,      0ull},
33786         {"PTRS2"                       ,        0,      17,     480,    "RO",   1,      0,      0,      0ull},
33787         {"RESERVED_17_31"              ,        17,     15,     480,    "RAZ",  1,      0,      0,      0ull},
33788         {"PTRS1"                       ,        32,     17,     480,    "RO",   1,      0,      0,      0ull},
33789         {"RESERVED_49_63"              ,        49,     15,     480,    "RAZ",  1,      0,      0,      0ull},
33790         {"MOD"                         ,        0,      3,      481,    "RO",   1,      0,      0,      0ull},
33791         {"CNT"                         ,        3,      13,     481,    "RO",   1,      0,      0,      0ull},
33792         {"CHK"                         ,        16,     1,      481,    "RO",   1,      0,      0,      0ull},
33793         {"LEN"                         ,        17,     1,      481,    "RO",   1,      0,      0,      0ull},
33794         {"SOP"                         ,        18,     1,      481,    "RO",   1,      0,      0,      0ull},
33795         {"UID"                         ,        19,     3,      481,    "RO",   1,      0,      0,      0ull},
33796         {"MAJ"                         ,        22,     1,      481,    "RO",   1,      0,      0,      0ull},
33797         {"RESERVED_23_63"              ,        23,     41,     481,    "RAZ",  1,      0,      0,      0ull},
33798         {"SIZE"                        ,        0,      16,     482,    "RO",   1,      0,      0,      0ull},
33799         {"SEGS"                        ,        16,     6,      482,    "RO",   1,      0,      0,      0ull},
33800         {"CMD"                         ,        22,     14,     482,    "RO",   1,      0,      0,      0ull},
33801         {"FAU"                         ,        36,     28,     482,    "RO",   1,      0,      0,      0ull},
33802         {"PTR"                         ,        0,      40,     483,    "RO",   1,      0,      0,      0ull},
33803         {"SIZE"                        ,        40,     16,     483,    "RO",   1,      0,      0,      0ull},
33804         {"POOL"                        ,        56,     3,      483,    "RO",   1,      0,      0,      0ull},
33805         {"BACK"                        ,        59,     4,      483,    "RO",   1,      0,      0,      0ull},
33806         {"I"                           ,        63,     1,      483,    "RO",   1,      0,      0,      0ull},
33807         {"PTR"                         ,        0,      40,     484,    "RO",   1,      0,      0,      0ull},
33808         {"SIZE"                        ,        40,     16,     484,    "RO",   1,      0,      0,      0ull},
33809         {"POOL"                        ,        56,     3,      484,    "RO",   1,      0,      0,      0ull},
33810         {"BACK"                        ,        59,     4,      484,    "RO",   1,      0,      0,      0ull},
33811         {"I"                           ,        63,     1,      484,    "RO",   1,      0,      0,      0ull},
33812         {"DATA"                        ,        0,      64,     485,    "RO",   1,      0,      0,      0ull},
33813         {"MAJOR"                       ,        0,      3,      486,    "RO",   1,      0,      0,      0ull},
33814         {"MINOR"                       ,        3,      2,      486,    "RO",   1,      0,      0,      0ull},
33815         {"WAIT"                        ,        5,      1,      486,    "RO",   1,      0,      0,      0ull},
33816         {"QID_BASE"                    ,        6,      8,      486,    "RO",   1,      0,      0,      0ull},
33817         {"QID_OFF"                     ,        14,     4,      486,    "RO",   1,      0,      0,      0ull},
33818         {"QID_OFF_MAX"                 ,        18,     4,      486,    "RO",   1,      0,      0,      0ull},
33819         {"QCB_RIDX"                    ,        22,     5,      486,    "RO",   1,      0,      0,      0ull},
33820         {"QOS"                         ,        27,     3,      486,    "RO",   1,      0,      0,      0ull},
33821         {"STATIC_P"                    ,        30,     1,      486,    "RO",   1,      0,      0,      0ull},
33822         {"ACTIVE"                      ,        31,     1,      486,    "RO",   1,      0,      0,      0ull},
33823         {"CHK_MODE"                    ,        32,     1,      486,    "RO",   1,      0,      0,      0ull},
33824         {"CHK_ONCE"                    ,        33,     1,      486,    "RO",   1,      0,      0,      0ull},
33825         {"INIT_DWRITE"                 ,        34,     1,      486,    "RO",   1,      0,      0,      0ull},
33826         {"DREAD_SOP"                   ,        35,     1,      486,    "RO",   1,      0,      0,      0ull},
33827         {"UID"                         ,        36,     3,      486,    "RO",   1,      0,      0,      0ull},
33828         {"CMND_OFF"                    ,        39,     6,      486,    "RO",   1,      0,      0,      0ull},
33829         {"CMND_SIZ"                    ,        45,     16,     486,    "RO",   1,      0,      0,      0ull},
33830         {"CMND_SEGS"                   ,        61,     3,      486,    "RO",   1,      0,      0,      0ull},
33831         {"CMND_SEGS"                   ,        0,      3,      487,    "RO",   1,      0,      0,      0ull},
33832         {"CURR_OFF"                    ,        3,      16,     487,    "RO",   1,      0,      0,      0ull},
33833         {"CURR_SIZ"                    ,        19,     16,     487,    "RO",   1,      0,      0,      0ull},
33834         {"CURR_PTR"                    ,        35,     29,     487,    "RO",   1,      0,      0,      0ull},
33835         {"CURR_PTR"                    ,        0,      11,     488,    "RO",   1,      0,      0,      0ull},
33836         {"RESERVED_11_63"              ,        11,     53,     488,    "RAZ",  1,      0,      0,      0ull},
33837         {"QCB_RIDX"                    ,        0,      6,      489,    "RO",   1,      0,      0,      0ull},
33838         {"QCB_WIDX"                    ,        6,      6,      489,    "RO",   1,      0,      0,      0ull},
33839         {"BUF_PTR"                     ,        12,     33,     489,    "RO",   1,      0,      0,      0ull},
33840         {"BUF_SIZ"                     ,        45,     13,     489,    "RO",   1,      0,      0,      0ull},
33841         {"TAIL"                        ,        58,     1,      489,    "RO",   1,      0,      0,      0ull},
33842         {"QOS"                         ,        59,     5,      489,    "RO",   1,      0,      0,      0ull},
33843         {"QOS"                         ,        0,      3,      490,    "RO",   1,      0,      0,      0ull},
33844         {"STATIC_Q"                    ,        3,      1,      490,    "RO",   1,      0,      0,      0ull},
33845         {"S_TAIL"                      ,        4,      1,      490,    "RO",   1,      0,      0,      0ull},
33846         {"STATIC_P"                    ,        5,      1,      490,    "RO",   1,      0,      0,      0ull},
33847         {"RESERVED_6_7"                ,        6,      2,      490,    "RAZ",  1,      0,      0,      0ull},
33848         {"DOORBELL"                    ,        8,      20,     490,    "RO",   1,      0,      0,      0ull},
33849         {"RESERVED_28_63"              ,        28,     36,     490,    "RAZ",  1,      0,      0,      0ull},
33850         {"PTRS3"                       ,        0,      17,     491,    "RO",   1,      0,      0,      0ull},
33851         {"RESERVED_17_31"              ,        17,     15,     491,    "RAZ",  1,      0,      0,      0ull},
33852         {"PTRS0"                       ,        32,     17,     491,    "RO",   1,      0,      0,      0ull},
33853         {"RESERVED_49_63"              ,        49,     15,     491,    "RAZ",  1,      0,      0,      0ull},
33854         {"QUEUE"                       ,        0,      7,      492,    "R/W",  1,      0,      0,      0ull},
33855         {"PORT"                        ,        7,      6,      492,    "WR0",  1,      0,      0,      0ull},
33856         {"INDEX"                       ,        13,     3,      492,    "WR0",  1,      0,      0,      0ull},
33857         {"TAIL"                        ,        16,     1,      492,    "R/W",  1,      0,      0,      0ull},
33858         {"BUF_PTR"                     ,        17,     36,     492,    "R/W",  1,      0,      0,      0ull},
33859         {"QOS_MASK"                    ,        53,     8,      492,    "R/W",  1,      0,      0,      0ull},
33860         {"STATIC_Q"                    ,        61,     1,      492,    "R/W",  1,      0,      0,      0ull},
33861         {"STATIC_P"                    ,        62,     1,      492,    "R/W",  1,      0,      0,      0ull},
33862         {"S_TAIL"                      ,        63,     1,      492,    "R/W",  1,      0,      0,      0ull},
33863         {"QID"                         ,        0,      7,      493,    "R/W",  1,      0,      0,      0ull},
33864         {"PID"                         ,        7,      6,      493,    "WR0",  1,      0,      0,      0ull},
33865         {"RESERVED_13_52"              ,        13,     40,     493,    "RAZ",  1,      0,      0,      0ull},
33866         {"QOS_MASK"                    ,        53,     8,      493,    "R/W",  1,      0,      0,      0ull},
33867         {"RESERVED_61_63"              ,        61,     3,      493,    "RAZ",  1,      0,      0,      0ull},
33868         {"DAT_PTR"                     ,        0,      4,      494,    "RO",   1,      0,      0,      0ull},
33869         {"DAT_DAT"                     ,        4,      4,      494,    "RO",   1,      0,      0,      0ull},
33870         {"PRT_QSB"                     ,        8,      3,      494,    "RO",   1,      0,      0,      0ull},
33871         {"PRT_QCB"                     ,        11,     2,      494,    "RO",   1,      0,      0,      0ull},
33872         {"NCB_INB"                     ,        13,     2,      494,    "RO",   1,      0,      0,      0ull},
33873         {"PRT_PSB"                     ,        15,     6,      494,    "RO",   1,      0,      0,      0ull},
33874         {"PRT_NXT"                     ,        21,     1,      494,    "RO",   1,      0,      0,      0ull},
33875         {"PRT_CHK"                     ,        22,     3,      494,    "RO",   1,      0,      0,      0ull},
33876         {"OUT_WIF"                     ,        25,     1,      494,    "RO",   1,      0,      0,      0ull},
33877         {"OUT_STA"                     ,        26,     1,      494,    "RO",   1,      0,      0,      0ull},
33878         {"OUT_CTL"                     ,        27,     3,      494,    "RO",   1,      0,      0,      0ull},
33879         {"OUT_CRC"                     ,        30,     1,      494,    "RO",   1,      0,      0,      0ull},
33880         {"IOB"                         ,        31,     1,      494,    "RO",   1,      0,      0,      0ull},
33881         {"CSR"                         ,        32,     1,      494,    "RO",   1,      0,      0,      0ull},
33882         {"RESERVED_33_63"              ,        33,     31,     494,    "RAZ",  1,      0,      0,      0ull},
33883         {"SIZE"                        ,        0,      13,     495,    "R/W",  0,      0,      0ull,   0ull},
33884         {"RESERVED_13_19"              ,        13,     7,      495,    "RAZ",  0,      0,      0ull,   0ull},
33885         {"POOL"                        ,        20,     3,      495,    "R/W",  0,      0,      0ull,   0ull},
33886         {"RESERVED_23_63"              ,        23,     41,     495,    "RAZ",  1,      0,      0,      0ull},
33887         {"REFIN"                       ,        0,      1,      496,    "R/W",  0,      0,      1ull,   1ull},
33888         {"INVRES"                      ,        1,      1,      496,    "R/W",  0,      0,      1ull,   1ull},
33889         {"RESERVED_2_63"               ,        2,      62,     496,    "RAZ",  1,      1,      0,      0},
33890         {"ENABLE"                      ,        0,      32,     497,    "R/W",  0,      0,      0ull,   0ull},
33891         {"RESERVED_32_63"              ,        32,     32,     497,    "RAZ",  1,      0,      0,      0ull},
33892         {"IV"                          ,        0,      32,     498,    "R/W",  0,      0,      1185899593ull,  1185899593ull},
33893         {"RESERVED_32_63"              ,        32,     32,     498,    "RAZ",  1,      1,      0,      0},
33894         {"ASSERTS"                     ,        0,      64,     499,    "RO",   0,      0,      0ull,   0ull},
33895         {"ASSERTS"                     ,        0,      64,     500,    "RO",   0,      0,      0ull,   0ull},
33896         {"ASSERTS"                     ,        0,      64,     501,    "RO",   0,      0,      0ull,   0ull},
33897         {"ASSERTS"                     ,        0,      64,     502,    "RO",   0,      0,      0ull,   0ull},
33898         {"PARITY"                      ,        0,      1,      503,    "R/W1C",        0,      0,      0ull,   0ull},
33899         {"DOORBELL"                    ,        1,      1,      503,    "R/W1C",        0,      0,      0ull,   0ull},
33900         {"CURRZERO"                    ,        2,      1,      503,    "R/W1C",        0,      0,      0ull,   0ull},
33901         {"RESERVED_3_63"               ,        3,      61,     503,    "RAZ",  1,      0,      0,      0ull},
33902         {"ENA_PKO"                     ,        0,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
33903         {"ENA_DWB"                     ,        1,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
33904         {"STORE_BE"                    ,        2,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
33905         {"RESET"                       ,        3,      1,      504,    "RAZ",  0,      0,      0ull,   0ull},
33906         {"RESERVED_4_63"               ,        4,      60,     504,    "RAZ",  1,      0,      0,      0ull},
33907         {"MODE0"                       ,        0,      3,      505,    "R/W",  0,      0,      0ull,   0ull},
33908         {"MODE1"                       ,        3,      3,      505,    "R/W",  0,      0,      0ull,   0ull},
33909         {"RESERVED_6_63"               ,        6,      58,     505,    "RAZ",  1,      0,      0,      0ull},
33910         {"PARITY"                      ,        0,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
33911         {"DOORBELL"                    ,        1,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
33912         {"CURRZERO"                    ,        2,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
33913         {"RESERVED_3_63"               ,        3,      61,     506,    "RAZ",  1,      0,      0,      0ull},
33914         {"MODE"                        ,        0,      2,      507,    "R/W",  0,      0,      0ull,   0ull},
33915         {"RESERVED_2_63"               ,        2,      62,     507,    "RAZ",  1,      0,      0,      0ull},
33916         {"QID7"                        ,        0,      1,      508,    "R/W",  0,      0,      0ull,   0ull},
33917         {"IDX3"                        ,        1,      1,      508,    "R/W",  0,      0,      0ull,   0ull},
33918         {"RESERVED_2_63"               ,        2,      62,     508,    "RAZ",  1,      0,      0,      0ull},
33919         {"INDEX"                       ,        0,      8,      509,    "R/W",  0,      0,      0ull,   0ull},
33920         {"INC"                         ,        8,      8,      509,    "R/W",  0,      0,      0ull,   0ull},
33921         {"RESERVED_16_63"              ,        16,     48,     509,    "RAZ",  1,      0,      0,      0ull},
33922         {"ADR0"                        ,        0,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33923         {"ADR1"                        ,        1,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33924         {"PEND0"                       ,        2,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33925         {"PEND1"                       ,        3,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33926         {"NBR0"                        ,        4,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33927         {"NBR1"                        ,        5,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33928         {"FIDX"                        ,        6,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33929         {"INDEX"                       ,        7,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33930         {"NBT"                         ,        8,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33931         {"CAM"                         ,        9,      1,      510,    "RO",   0,      0,      0ull,   0ull},
33932         {"RESERVED_10_15"              ,        10,     6,      510,    "RAZ",  1,      1,      0,      0},
33933         {"PP"                          ,        16,     16,     510,    "RO",   0,      0,      0ull,   0ull},
33934         {"RESERVED_32_63"              ,        32,     32,     510,    "RAZ",  1,      1,      0,      0},
33935         {"DS_PC"                       ,        0,      32,     511,    "R/W1C",        0,      1,      0ull,   0},
33936         {"RESERVED_32_63"              ,        32,     32,     511,    "RAZ",  1,      1,      0,      0},
33937         {"SBE"                         ,        0,      1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
33938         {"DBE"                         ,        1,      1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
33939         {"SBE_IE"                      ,        2,      1,      512,    "R/W",  0,      1,      0ull,   0},
33940         {"DBE_IE"                      ,        3,      1,      512,    "R/W",  0,      1,      0ull,   0},
33941         {"SYN"                         ,        4,      5,      512,    "RO",   1,      1,      0,      0},
33942         {"RESERVED_9_11"               ,        9,      3,      512,    "RAZ",  1,      1,      0,      0},
33943         {"RPE"                         ,        12,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
33944         {"RPE_IE"                      ,        13,     1,      512,    "R/W",  0,      1,      0ull,   0},
33945         {"RESERVED_14_15"              ,        14,     2,      512,    "RAZ",  1,      1,      0,      0},
33946         {"IOP"                         ,        16,     13,     512,    "R/W1C",        0,      0,      0ull,   0ull},
33947         {"RESERVED_29_31"              ,        29,     3,      512,    "RAZ",  1,      1,      0,      0},
33948         {"IOP_IE"                      ,        32,     13,     512,    "R/W",  0,      1,      0ull,   0},
33949         {"RESERVED_45_63"              ,        45,     19,     512,    "RAZ",  1,      1,      0,      0},
33950         {"NBR_THR"                     ,        0,      5,      513,    "R/W",  0,      0,      2ull,   2ull},
33951         {"PFR_DIS"                     ,        5,      1,      513,    "R/W",  0,      0,      0ull,   0ull},
33952         {"RESERVED_6_63"               ,        6,      58,     513,    "RAZ",  1,      1,      0,      0},
33953         {"IQ_CNT"                      ,        0,      32,     514,    "RO",   0,      1,      0ull,   0},
33954         {"RESERVED_32_63"              ,        32,     32,     514,    "RAZ",  1,      1,      0,      0},
33955         {"IQ_CNT"                      ,        0,      32,     515,    "RO",   0,      1,      0ull,   0},
33956         {"RESERVED_32_63"              ,        32,     32,     515,    "RAZ",  1,      1,      0,      0},
33957         {"NOS_CNT"                     ,        0,      12,     516,    "RO",   0,      1,      0ull,   0},
33958         {"RESERVED_12_63"              ,        12,     52,     516,    "RAZ",  1,      1,      0,      0},
33959         {"NW_TIM"                      ,        0,      10,     517,    "R/W",  0,      0,      0ull,   1023ull},
33960         {"RESERVED_10_63"              ,        10,     54,     517,    "RAZ",  1,      1,      0,      0},
33961         {"RST_MSK"                     ,        0,      8,      518,    "R/W",  0,      1,      0ull,   0},
33962         {"RESERVED_8_63"               ,        8,      56,     518,    "RAZ",  1,      1,      0,      0},
33963         {"GRP_MSK"                     ,        0,      16,     519,    "R/W",  0,      0,      65535ull,       65535ull},
33964         {"QOS0_PRI"                    ,        16,     4,      519,    "R/W",  0,      1,      0ull,   0},
33965         {"QOS1_PRI"                    ,        20,     4,      519,    "R/W",  0,      1,      0ull,   0},
33966         {"QOS2_PRI"                    ,        24,     4,      519,    "R/W",  0,      1,      0ull,   0},
33967         {"QOS3_PRI"                    ,        28,     4,      519,    "R/W",  0,      1,      0ull,   0},
33968         {"QOS4_PRI"                    ,        32,     4,      519,    "R/W",  0,      1,      0ull,   0},
33969         {"QOS5_PRI"                    ,        36,     4,      519,    "R/W",  0,      1,      0ull,   0},
33970         {"QOS6_PRI"                    ,        40,     4,      519,    "R/W",  0,      1,      0ull,   0},
33971         {"QOS7_PRI"                    ,        44,     4,      519,    "R/W",  0,      1,      0ull,   0},
33972         {"RESERVED_48_63"              ,        48,     16,     519,    "RAZ",  1,      1,      0,      0},
33973         {"RND"                         ,        0,      8,      520,    "R/W",  0,      1,      255ull, 0},
33974         {"RND_P1"                      ,        8,      8,      520,    "R/W",  0,      1,      255ull, 0},
33975         {"RND_P2"                      ,        16,     8,      520,    "R/W",  0,      1,      255ull, 0},
33976         {"RND_P3"                      ,        24,     8,      520,    "R/W",  0,      1,      255ull, 0},
33977         {"RESERVED_32_63"              ,        32,     32,     520,    "RAZ",  1,      1,      0,      0},
33978         {"MIN_THR"                     ,        0,      11,     521,    "R/W",  0,      1,      0ull,   0},
33979         {"RESERVED_11_11"              ,        11,     1,      521,    "RAZ",  1,      1,      0,      0},
33980         {"MAX_THR"                     ,        12,     11,     521,    "R/W",  0,      1,      2047ull,        0},
33981         {"RESERVED_23_23"              ,        23,     1,      521,    "RAZ",  1,      1,      0,      0},
33982         {"FREE_CNT"                    ,        24,     12,     521,    "RO",   0,      1,      2027ull,        0},
33983         {"BUF_CNT"                     ,        36,     12,     521,    "RO",   0,      1,      0ull,   0},
33984         {"DES_CNT"                     ,        48,     12,     521,    "RO",   0,      1,      0ull,   0},
33985         {"RESERVED_60_63"              ,        60,     4,      521,    "RAZ",  1,      1,      0,      0},
33986         {"TS_PC"                       ,        0,      32,     522,    "R/W1C",        0,      1,      0ull,   0},
33987         {"RESERVED_32_63"              ,        32,     32,     522,    "RAZ",  1,      1,      0,      0},
33988         {"WA_PC"                       ,        0,      32,     523,    "R/W1C",        0,      1,      0ull,   0},
33989         {"RESERVED_32_63"              ,        32,     32,     523,    "RAZ",  1,      1,      0,      0},
33990         {"WA_PC"                       ,        0,      32,     524,    "R/W1C",        0,      1,      0ull,   0},
33991         {"RESERVED_32_63"              ,        32,     32,     524,    "RAZ",  1,      1,      0,      0},
33992         {"WQ_INT"                      ,        0,      16,     525,    "R/W1C",        0,      1,      0ull,   0},
33993         {"IQ_DIS"                      ,        16,     16,     525,    "R/W1", 0,      1,      0ull,   0},
33994         {"RESERVED_32_63"              ,        32,     32,     525,    "RAZ",  1,      1,      0,      0},
33995         {"IQ_CNT"                      ,        0,      12,     526,    "RO",   0,      1,      0ull,   0},
33996         {"DS_CNT"                      ,        12,     12,     526,    "RO",   0,      1,      0ull,   0},
33997         {"TC_CNT"                      ,        24,     4,      526,    "RO",   0,      1,      0ull,   0},
33998         {"RESERVED_28_63"              ,        28,     36,     526,    "RAZ",  1,      1,      0,      0},
33999         {"RESERVED_0_7"                ,        0,      8,      527,    "RAZ",  1,      1,      0,      0},
34000         {"PC_THR"                      ,        8,      20,     527,    "R/W",  0,      1,      0ull,   0},
34001         {"RESERVED_28_31"              ,        28,     4,      527,    "RAZ",  1,      1,      0,      0},
34002         {"PC"                          ,        32,     28,     527,    "RO",   0,      1,      0ull,   0},
34003         {"RESERVED_60_63"              ,        60,     4,      527,    "RAZ",  1,      1,      0,      0},
34004         {"IQ_THR"                      ,        0,      11,     528,    "R/W",  0,      1,      0ull,   0},
34005         {"RESERVED_11_11"              ,        11,     1,      528,    "RAZ",  1,      1,      0,      0},
34006         {"DS_THR"                      ,        12,     11,     528,    "R/W",  0,      1,      0ull,   0},
34007         {"RESERVED_23_23"              ,        23,     1,      528,    "RAZ",  1,      1,      0,      0},
34008         {"TC_THR"                      ,        24,     4,      528,    "R/W",  0,      1,      0ull,   0},
34009         {"TC_EN"                       ,        28,     1,      528,    "R/W",  0,      1,      0ull,   0},
34010         {"RESERVED_29_63"              ,        29,     35,     528,    "RAZ",  1,      1,      0,      0},
34011         {"WS_PC"                       ,        0,      32,     529,    "R/W1C",        0,      1,      0ull,   0},
34012         {"RESERVED_32_63"              ,        32,     32,     529,    "RAZ",  1,      1,      0,      0},
34013         {"MEM"                         ,        0,      1,      530,    "RO",   0,      0,      0ull,   0ull},
34014         {"RRC"                         ,        1,      1,      530,    "RO",   0,      0,      0ull,   0ull},
34015         {"RESERVED_2_63"               ,        2,      62,     530,    "RAZ",  1,      1,      0,      0},
34016         {"ENT_EN"                      ,        0,      1,      531,    "R/W",  0,      0,      0ull,   0ull},
34017         {"RNG_EN"                      ,        1,      1,      531,    "R/W",  0,      0,      0ull,   0ull},
34018         {"RNM_RST"                     ,        2,      1,      531,    "R/W",  0,      0,      0ull,   0ull},
34019         {"RNG_RST"                     ,        3,      1,      531,    "R/W",  0,      0,      0ull,   0ull},
34020         {"EXP_ENT"                     ,        4,      1,      531,    "R/W",  0,      0,      0ull,   0ull},
34021         {"ENT_SEL"                     ,        5,      4,      531,    "R/W",  0,      0,      0ull,   0ull},
34022         {"RESERVED_9_63"               ,        9,      55,     531,    "RAZ",  1,      1,      0,      0},
34023         {"PHASE"                       ,        0,      8,      532,    "R/W",  0,      0,      100ull, 100ull},
34024         {"SAMPLE"                      ,        8,      4,      532,    "R/W",  0,      0,      2ull,   2ull},
34025         {"PREAMBLE"                    ,        12,     1,      532,    "R/W",  0,      0,      1ull,   1ull},
34026         {"CLK_IDLE"                    ,        13,     1,      532,    "R/W",  0,      0,      0ull,   0ull},
34027         {"RESERVED_14_14"              ,        14,     1,      532,    "RAZ",  1,      1,      0,      0},
34028         {"SAMPLE_MODE"                 ,        15,     1,      532,    "RAZ",  0,      0,      0ull,   0ull},
34029         {"SAMPLE_HI"                   ,        16,     5,      532,    "R/W",  0,      0,      0ull,   0ull},
34030         {"RESERVED_21_63"              ,        21,     43,     532,    "RAZ",  1,      1,      0,      0},
34031         {"REG_ADR"                     ,        0,      5,      533,    "R/W",  0,      1,      0ull,   0},
34032         {"RESERVED_5_7"                ,        5,      3,      533,    "RAZ",  1,      1,      0,      0},
34033         {"PHY_ADR"                     ,        8,      5,      533,    "R/W",  0,      1,      0ull,   0},
34034         {"RESERVED_13_15"              ,        13,     3,      533,    "RAZ",  1,      1,      0,      0},
34035         {"PHY_OP"                      ,        16,     1,      533,    "R/W",  0,      1,      0ull,   0},
34036         {"RESERVED_17_63"              ,        17,     47,     533,    "RAZ",  1,      1,      0,      0},
34037         {"EN"                          ,        0,      1,      534,    "R/W",  0,      0,      0ull,   1ull},
34038         {"RESERVED_1_63"               ,        1,      63,     534,    "RAZ",  1,      1,      0,      0},
34039         {"DAT"                         ,        0,      16,     535,    "RO",   0,      1,      0ull,   0},
34040         {"VAL"                         ,        16,     1,      535,    "RO",   0,      1,      0ull,   0},
34041         {"PENDING"                     ,        17,     1,      535,    "RO",   0,      1,      0ull,   0},
34042         {"RESERVED_18_63"              ,        18,     46,     535,    "RAZ",  1,      1,      0,      0},
34043         {"DAT"                         ,        0,      16,     536,    "R/W",  0,      1,      0ull,   0},
34044         {"VAL"                         ,        16,     1,      536,    "RO",   0,      1,      0ull,   0},
34045         {"PENDING"                     ,        17,     1,      536,    "RO",   0,      1,      0ull,   0},
34046         {"RESERVED_18_63"              ,        18,     46,     536,    "RAZ",  1,      1,      0,      0},
34047         {"CNT"                         ,        0,      32,     537,    "R/W1C",        0,      0,      0ull,   0ull},
34048         {"RESERVED_32_63"              ,        32,     32,     537,    "RAZ",  0,      0,      0ull,   0ull},
34049         {"STAT0"                       ,        0,      1,      538,    "RO",   0,      0,      0ull,   0ull},
34050         {"STAT1"                       ,        1,      1,      538,    "RO",   0,      0,      0ull,   0ull},
34051         {"STAT2"                       ,        2,      1,      538,    "RO",   0,      0,      0ull,   0ull},
34052         {"RESERVED_3_63"               ,        3,      61,     538,    "RAZ",  0,      0,      0ull,   0ull},
34053         {"SRXDLCK"                     ,        0,      1,      539,    "R/W",  0,      0,      0ull,   1ull},
34054         {"RCVTRN"                      ,        1,      1,      539,    "R/W",  0,      0,      0ull,   1ull},
34055         {"DRPTRN"                      ,        2,      1,      539,    "R/W",  0,      0,      0ull,   1ull},
34056         {"SNDTRN"                      ,        3,      1,      539,    "R/W",  0,      0,      0ull,   1ull},
34057         {"STATRCV"                     ,        4,      1,      539,    "R/W",  0,      0,      0ull,   0ull},
34058         {"STATDRV"                     ,        5,      1,      539,    "R/W",  0,      0,      0ull,   0ull},
34059         {"RUNBIST"                     ,        6,      1,      539,    "R/W",  0,      0,      0ull,   0ull},
34060         {"CLKDLY"                      ,        7,      5,      539,    "R/W",  0,      0,      16ull,  16ull},
34061         {"RESERVED_12_15"              ,        12,     4,      539,    "RAZ",  0,      0,      0ull,   0ull},
34062         {"SEETRN"                      ,        16,     1,      539,    "R/W",  0,      0,      0ull,   0ull},
34063         {"RESERVED_17_63"              ,        17,     47,     539,    "RAZ",  0,      0,      0ull,   0ull},
34064         {"RESERVED_0_3"                ,        0,      4,      540,    "RAZ",  0,      1,      0ull,   0},
34065         {"D4CLK0"                      ,        4,      1,      540,    "R/W1C",        0,      1,      0ull,   0},
34066         {"D4CLK1"                      ,        5,      1,      540,    "R/W1C",        0,      1,      0ull,   0},
34067         {"S4CLK0"                      ,        6,      1,      540,    "R/W1C",        0,      1,      0ull,   0},
34068         {"S4CLK1"                      ,        7,      1,      540,    "R/W1C",        0,      1,      0ull,   0},
34069         {"SRXTRN"                      ,        8,      1,      540,    "R/W1C",        0,      1,      0ull,   0},
34070         {"RESERVED_9_9"                ,        9,      1,      540,    "RAZ",  0,      1,      0ull,   0},
34071         {"STXCAL"                      ,        10,     1,      540,    "R/W1C",        0,      1,      0ull,   0},
34072         {"RESERVED_11_63"              ,        11,     53,     540,    "RAZ",  0,      0,      0ull,   0ull},
34073         {"DLLDIS"                      ,        0,      1,      541,    "R/W",  1,      0,      0,      0ull},
34074         {"DLLFRC"                      ,        1,      1,      541,    "WR0",  1,      0,      0,      0ull},
34075         {"OFFDLY"                      ,        2,      6,      541,    "R/W",  1,      0,      0,      0ull},
34076         {"BITSEL"                      ,        8,      5,      541,    "R/W",  1,      1,      0,      0},
34077         {"OFFSET"                      ,        13,     5,      541,    "R/W",  1,      1,      0,      0},
34078         {"MUX"                         ,        18,     1,      541,    "WR0",  1,      1,      0,      0},
34079         {"INC"                         ,        19,     1,      541,    "WR0",  1,      1,      0,      0},
34080         {"DEC"                         ,        20,     1,      541,    "WR0",  1,      1,      0,      0},
34081         {"CLRDLY"                      ,        21,     1,      541,    "WR0",  1,      1,      0,      0},
34082         {"RESERVED_22_23"              ,        22,     2,      541,    "RAZ",  0,      0,      0ull,   0ull},
34083         {"SSTEP"                       ,        24,     1,      541,    "R/W",  1,      0,      0,      0ull},
34084         {"SSTEP_GO"                    ,        25,     1,      541,    "WR0",  1,      1,      0,      0},
34085         {"RESERVED_26_27"              ,        26,     2,      541,    "RAZ",  0,      0,      0ull,   0ull},
34086         {"FALL8"                       ,        28,     1,      541,    "R/W",  0,      0,      0ull,   0ull},
34087         {"FALLNOP"                     ,        29,     1,      541,    "R/W",  0,      0,      0ull,   0ull},
34088         {"RESERVED_30_63"              ,        30,     34,     541,    "RAZ",  0,      0,      0ull,   0ull},
34089         {"OFFSET"                      ,        0,      5,      542,    "RO",   0,      1,      0ull,   0},
34090         {"MUXSEL"                      ,        5,      2,      542,    "RO",   0,      1,      0ull,   0},
34091         {"UNXTERM"                     ,        7,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
34092         {"TESTRES"                     ,        8,      1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
34093         {"RESERVED_9_63"               ,        9,      55,     542,    "RAZ",  0,      0,      0ull,   0ull},
34094         {"SRX4CMP"                     ,        0,      10,     543,    "R/W",  0,      0,      239ull, 239ull},
34095         {"RESERVED_10_15"              ,        10,     6,      543,    "RAZ",  0,      0,      0ull,   0ull},
34096         {"STX4PCMP"                    ,        16,     4,      543,    "R/W",  0,      0,      3ull,   3ull},
34097         {"STX4NCMP"                    ,        20,     4,      543,    "R/W",  0,      0,      12ull,  12ull},
34098         {"RESERVED_24_63"              ,        24,     40,     543,    "RAZ",  0,      0,      0ull,   0ull},
34099         {"ERRCNT"                      ,        0,      4,      544,    "R/W",  0,      0,      0ull,   3ull},
34100         {"RESERVED_4_5"                ,        4,      2,      544,    "RAZ",  0,      0,      0ull,   0ull},
34101         {"DIPPAY"                      ,        6,      1,      544,    "R/W",  0,      0,      0ull,   0ull},
34102         {"DIPCLS"                      ,        7,      1,      544,    "R/W",  0,      0,      0ull,   0ull},
34103         {"PRTNXA"                      ,        8,      1,      544,    "R/W",  0,      0,      0ull,   0ull},
34104         {"RESERVED_9_63"               ,        9,      55,     544,    "RAZ",  0,      0,      0ull,   0ull},
34105         {"PRT"                         ,        0,      8,      545,    "RO",   0,      0,      0ull,   0ull},
34106         {"RSVOP"                       ,        8,      4,      545,    "RO",   0,      0,      0ull,   0ull},
34107         {"CALBNK"                      ,        12,     2,      545,    "RO",   0,      0,      0ull,   0ull},
34108         {"RESERVED_14_30"              ,        14,     17,     545,    "RAZ",  0,      0,      0ull,   0ull},
34109         {"MUL"                         ,        31,     1,      545,    "RO",   0,      0,      0ull,   0ull},
34110         {"RESERVED_32_63"              ,        32,     32,     545,    "RAZ",  0,      0,      0ull,   0ull},
34111         {"PRTNXA"                      ,        0,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
34112         {"ABNORM"                      ,        1,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
34113         {"RESERVED_2_3"                ,        2,      2,      546,    "RAZ",  0,      0,      0ull,   0ull},
34114         {"SPIOVR"                      ,        4,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
34115         {"CLSERR"                      ,        5,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
34116         {"DRWNNG"                      ,        6,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
34117         {"RSVERR"                      ,        7,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
34118         {"TPAOVR"                      ,        8,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
34119         {"DIPERR"                      ,        9,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
34120         {"SYNCERR"                     ,        10,     1,      546,    "R/W",  0,      0,      0ull,   0ull},
34121         {"CALERR"                      ,        11,     1,      546,    "R/W",  0,      0,      0ull,   0ull},
34122         {"RESERVED_12_63"              ,        12,     52,     546,    "RAZ",  0,      0,      0ull,   0ull},
34123         {"PRTNXA"                      ,        0,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34124         {"ABNORM"                      ,        1,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34125         {"RESERVED_2_3"                ,        2,      2,      547,    "RAZ",  0,      0,      0ull,   0ull},
34126         {"SPIOVR"                      ,        4,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34127         {"CLSERR"                      ,        5,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34128         {"DRWNNG"                      ,        6,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34129         {"RSVERR"                      ,        7,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34130         {"TPAOVR"                      ,        8,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34131         {"DIPERR"                      ,        9,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34132         {"SYNCERR"                     ,        10,     1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34133         {"CALERR"                      ,        11,     1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
34134         {"RESERVED_12_30"              ,        12,     19,     547,    "RAZ",  0,      0,      0ull,   0ull},
34135         {"SPF"                         ,        31,     1,      547,    "RO",   0,      0,      0ull,   0ull},
34136         {"RESERVED_32_63"              ,        32,     32,     547,    "RAZ",  0,      0,      0ull,   0ull},
34137         {"PRTNXA"                      ,        0,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
34138         {"ABNORM"                      ,        1,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
34139         {"RESERVED_2_3"                ,        2,      2,      548,    "RAZ",  0,      0,      0ull,   0ull},
34140         {"SPIOVR"                      ,        4,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
34141         {"CLSERR"                      ,        5,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
34142         {"DRWNNG"                      ,        6,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
34143         {"RSVERR"                      ,        7,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
34144         {"TPAOVR"                      ,        8,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
34145         {"DIPERR"                      ,        9,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
34146         {"SYNCERR"                     ,        10,     1,      548,    "R/W",  0,      0,      0ull,   0ull},
34147         {"CALERR"                      ,        11,     1,      548,    "R/W",  0,      0,      0ull,   0ull},
34148         {"RESERVED_12_63"              ,        12,     52,     548,    "RAZ",  0,      0,      0ull,   0ull},
34149         {"CNT"                         ,        0,      32,     549,    "RO",   0,      1,      0ull,   0},
34150         {"RESERVED_32_63"              ,        32,     32,     549,    "RAZ",  0,      0,      0ull,   0ull},
34151         {"MAX"                         ,        0,      32,     550,    "R/W",  0,      0,      0ull,   0ull},
34152         {"RESERVED_32_63"              ,        32,     32,     550,    "RAZ",  0,      0,      0ull,   0ull},
34153         {"PRTSEL"                      ,        0,      4,      551,    "R/W",  0,      0,      0ull,   0ull},
34154         {"RESERVED_4_63"               ,        4,      60,     551,    "RAZ",  0,      0,      0ull,   0ull},
34155         {"MUX_EN"                      ,        0,      1,      552,    "R/W",  0,      0,      0ull,   0ull},
34156         {"MACRO_EN"                    ,        1,      1,      552,    "R/W",  0,      0,      0ull,   0ull},
34157         {"MAXDIST"                     ,        2,      5,      552,    "R/W",  0,      0,      0ull,   8ull},
34158         {"SET_BOOT"                    ,        7,      1,      552,    "R/W",  0,      0,      0ull,   0ull},
34159         {"CLR_BOOT"                    ,        8,      1,      552,    "R/W",  0,      0,      0ull,   0ull},
34160         {"JITTER"                      ,        9,      3,      552,    "R/W",  0,      0,      0ull,   1ull},
34161         {"TRNTEST"                     ,        12,     1,      552,    "R/W",  0,      0,      0ull,   0ull},
34162         {"RESERVED_13_63"              ,        13,     51,     552,    "RAZ",  0,      0,      0ull,   0ull},
34163         {"INF_EN"                      ,        0,      1,      553,    "R/W",  0,      0,      0ull,   1ull},
34164         {"RESERVED_1_2"                ,        1,      2,      553,    "RAZ",  0,      0,      0ull,   0ull},
34165         {"ST_EN"                       ,        3,      1,      553,    "R/W",  0,      0,      0ull,   1ull},
34166         {"PRTS"                        ,        4,      4,      553,    "R/W",  0,      1,      0ull,   0},
34167         {"RESERVED_8_63"               ,        8,      56,     553,    "RAZ",  0,      0,      0ull,   0ull},
34168         {"IGNORE"                      ,        0,      16,     554,    "R/W",  0,      0,      0ull,   0ull},
34169         {"RESERVED_16_63"              ,        16,     48,     554,    "RAZ",  0,      0,      0ull,   0ull},
34170         {"PRT0"                        ,        0,      4,      555,    "R/W",  1,      1,      0,      0},
34171         {"PRT1"                        ,        4,      4,      555,    "R/W",  1,      1,      0,      0},
34172         {"PRT2"                        ,        8,      4,      555,    "R/W",  1,      1,      0,      0},
34173         {"PRT3"                        ,        12,     4,      555,    "R/W",  1,      1,      0,      0},
34174         {"ODDPAR"                      ,        16,     1,      555,    "R/W",  1,      1,      0,      0},
34175         {"RESERVED_17_63"              ,        17,     47,     555,    "RAZ",  0,      0,      0ull,   0ull},
34176         {"LEN"                         ,        0,      7,      556,    "R/W",  0,      1,      0ull,   0},
34177         {"RESERVED_7_7"                ,        7,      1,      556,    "RAZ",  0,      0,      0ull,   0ull},
34178         {"M"                           ,        8,      8,      556,    "R/W",  0,      1,      0ull,   0},
34179         {"RESERVED_16_63"              ,        16,     48,     556,    "RAZ",  0,      0,      0ull,   0ull},
34180         {"ADR"                         ,        0,      4,      557,    "R/W",  0,      0,      0ull,   0ull},
34181         {"OPC"                         ,        4,      4,      557,    "R/W",  0,      0,      0ull,   0ull},
34182         {"MOD"                         ,        8,      4,      557,    "R/W",  0,      0,      0ull,   0ull},
34183         {"SOP"                         ,        12,     1,      557,    "R/W",  0,      0,      0ull,   0ull},
34184         {"EOP"                         ,        13,     1,      557,    "R/W",  0,      0,      0ull,   0ull},
34185         {"RESERVED_14_63"              ,        14,     50,     557,    "RAZ",  0,      0,      0ull,   0ull},
34186         {"DAT"                         ,        0,      64,     558,    "R/W",  0,      0,      0ull,   0ull},
34187         {"RESERVED_0_2"                ,        0,      3,      559,    "R/W",  0,      0,      0ull,   0ull},
34188         {"IGNTPA"                      ,        3,      1,      559,    "R/W",  0,      0,      0ull,   0ull},
34189         {"RESERVED_4_4"                ,        4,      1,      559,    "R/W",  0,      0,      0ull,   0ull},
34190         {"MINTRN"                      ,        5,      1,      559,    "R/W",  0,      0,      0ull,   0ull},
34191         {"RESERVED_6_63"               ,        6,      58,     559,    "RAZ",  0,      0,      0ull,   0ull},
34192         {"CNT"                         ,        0,      32,     560,    "R/W1C",        0,      0,      0ull,   0ull},
34193         {"RESERVED_32_63"              ,        32,     32,     560,    "RAZ",  0,      0,      0ull,   0ull},
34194         {"INF_EN"                      ,        0,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
34195         {"RESERVED_1_2"                ,        1,      2,      561,    "RAZ",  0,      0,      0ull,   0ull},
34196         {"ST_EN"                       ,        3,      1,      561,    "R/W",  0,      0,      0ull,   1ull},
34197         {"RESERVED_4_63"               ,        4,      60,     561,    "RAZ",  0,      0,      0ull,   0ull},
34198         {"DIPMAX"                      ,        0,      4,      562,    "R/W",  0,      0,      0ull,   0ull},
34199         {"FRMMAX"                      ,        4,      4,      562,    "R/W",  0,      0,      0ull,   0ull},
34200         {"RESERVED_8_63"               ,        8,      56,     562,    "RAZ",  0,      0,      0ull,   0ull},
34201         {"IGNTPA"                      ,        0,      16,     563,    "R/W",  0,      0,      0ull,   0ull},
34202         {"RESERVED_16_63"              ,        16,     48,     563,    "RAZ",  0,      0,      0ull,   0ull},
34203         {"CALPAR0"                     ,        0,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
34204         {"CALPAR1"                     ,        1,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
34205         {"OVRBST"                      ,        2,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
34206         {"DATOVR"                      ,        3,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
34207         {"DIPERR"                      ,        4,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
34208         {"NOSYNC"                      ,        5,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
34209         {"UNXFRM"                      ,        6,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
34210         {"FRMERR"                      ,        7,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
34211         {"RESERVED_8_63"               ,        8,      56,     564,    "RAZ",  0,      0,      0ull,   0ull},
34212         {"CALPAR0"                     ,        0,      1,      565,    "R/W1C",        0,      0,      0ull,   0ull},
34213         {"CALPAR1"                     ,        1,      1,      565,    "R/W1C",        0,      0,      0ull,   0ull},
34214         {"OVRBST"                      ,        2,      1,      565,    "R/W1C",        0,      0,      0ull,   0ull},
34215         {"DATOVR"                      ,        3,      1,      565,    "R/W1C",        0,      0,      0ull,   0ull},
34216         {"DIPERR"                      ,        4,      1,      565,    "R/W1C",        0,      0,      0ull,   0ull},
34217         {"NOSYNC"                      ,        5,      1,      565,    "R/W1C",        0,      0,      0ull,   0ull},
34218         {"UNXFRM"                      ,        6,      1,      565,    "R/W1C",        0,      0,      0ull,   0ull},
34219         {"FRMERR"                      ,        7,      1,      565,    "R/W1C",        0,      0,      0ull,   0ull},
34220         {"SYNCERR"                     ,        8,      1,      565,    "RO",   0,      0,      0ull,   0ull},
34221         {"RESERVED_9_63"               ,        9,      55,     565,    "RAZ",  0,      0,      0ull,   0ull},
34222         {"CALPAR0"                     ,        0,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
34223         {"CALPAR1"                     ,        1,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
34224         {"OVRBST"                      ,        2,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
34225         {"DATOVR"                      ,        3,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
34226         {"DIPERR"                      ,        4,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
34227         {"NOSYNC"                      ,        5,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
34228         {"UNXFRM"                      ,        6,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
34229         {"FRMERR"                      ,        7,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
34230         {"RESERVED_8_63"               ,        8,      56,     566,    "RAZ",  0,      0,      0ull,   0ull},
34231         {"MINB"                        ,        0,      9,      567,    "R/W",  0,      0,      0ull,   0ull},
34232         {"RESERVED_9_63"               ,        9,      55,     567,    "RAZ",  0,      0,      0ull,   0ull},
34233         {"PRT0"                        ,        0,      4,      568,    "R/W",  1,      1,      0,      0},
34234         {"PRT1"                        ,        4,      4,      568,    "R/W",  1,      1,      0,      0},
34235         {"PRT2"                        ,        8,      4,      568,    "R/W",  1,      1,      0,      0},
34236         {"PRT3"                        ,        12,     4,      568,    "R/W",  1,      1,      0,      0},
34237         {"ODDPAR"                      ,        16,     1,      568,    "R/W",  1,      1,      0,      0},
34238         {"RESERVED_17_63"              ,        17,     47,     568,    "RAZ",  0,      0,      0ull,   0ull},
34239         {"MAX_T"                       ,        0,      16,     569,    "R/W",  0,      1,      0ull,   0},
34240         {"ALPHA"                       ,        16,     16,     569,    "R/W",  0,      1,      0ull,   0},
34241         {"RESERVED_32_63"              ,        32,     32,     569,    "RAZ",  0,      0,      0ull,   0ull},
34242         {"LEN"                         ,        0,      7,      570,    "R/W",  0,      1,      0ull,   0},
34243         {"RESERVED_7_7"                ,        7,      1,      570,    "RAZ",  0,      0,      0ull,   0ull},
34244         {"M"                           ,        8,      8,      570,    "R/W",  0,      1,      0ull,   0},
34245         {"RESERVED_16_63"              ,        16,     48,     570,    "RAZ",  0,      0,      0ull,   0ull},
34246         {"CNT"                         ,        0,      32,     571,    "RO",   0,      0,      0ull,   0ull},
34247         {"RESERVED_32_63"              ,        32,     32,     571,    "RAZ",  0,      0,      0ull,   0ull},
34248         {"CNT"                         ,        0,      32,     572,    "RO",   0,      0,      0ull,   0ull},
34249         {"RESERVED_32_63"              ,        32,     32,     572,    "RAZ",  0,      0,      0ull,   0ull},
34250         {"BCKPRS"                      ,        0,      4,      573,    "R/W",  0,      0,      0ull,   0ull},
34251         {"CLR"                         ,        4,      1,      573,    "WR0",  0,      0,      0ull,   0ull},
34252         {"RESERVED_5_63"               ,        5,      59,     573,    "RAZ",  0,      0,      0ull,   0ull},
34253         {"CNT"                         ,        0,      32,     574,    "RO",   0,      0,      0ull,   0ull},
34254         {"RESERVED_32_63"              ,        32,     32,     574,    "RAZ",  0,      0,      0ull,   0ull},
34255         {"INTERVAL"                    ,        0,      22,     575,    "RO",   1,      0,      0,      0ull},
34256         {"RESERVED_22_23"              ,        22,     2,      575,    "RAZ",  1,      0,      0,      0ull},
34257         {"COUNT"                       ,        24,     22,     575,    "RO",   1,      0,      0,      0ull},
34258         {"RESERVED_46_46"              ,        46,     1,      575,    "RAZ",  1,      0,      0,      0ull},
34259         {"ENA"                         ,        47,     1,      575,    "RO",   1,      0,      0,      0ull},
34260         {"RESERVED_48_63"              ,        48,     16,     575,    "RAZ",  1,      0,      0,      0ull},
34261         {"BSIZE"                       ,        0,      20,     576,    "RO",   1,      0,      0,      0ull},
34262         {"BASE"                        ,        20,     31,     576,    "RO",   1,      0,      0,      0ull},
34263         {"BUCKET"                      ,        51,     13,     576,    "RO",   1,      0,      0,      0ull},
34264         {"BUCKET"                      ,        0,      7,      577,    "RO",   1,      0,      0,      0ull},
34265         {"RESERVED_7_7"                ,        7,      1,      577,    "RAZ",  1,      0,      0,      0ull},
34266         {"CSIZE"                       ,        8,      13,     577,    "RO",   1,      0,      0,      0ull},
34267         {"CPOOL"                       ,        21,     3,      577,    "RO",   1,      0,      0,      0ull},
34268         {"RESERVED_24_63"              ,        24,     40,     577,    "RAZ",  1,      0,      0,      0ull},
34269         {"RING"                        ,        0,      4,      578,    "R/W",  0,      0,      0ull,   0ull},
34270         {"NUM_BUCKETS"                 ,        4,      20,     578,    "R/W",  0,      0,      0ull,   0ull},
34271         {"FIRST_BUCKET"                ,        24,     31,     578,    "R/W",  0,      0,      0ull,   0ull},
34272         {"RESERVED_55_63"              ,        55,     9,      578,    "RAZ",  1,      0,      0,      0ull},
34273         {"RING"                        ,        0,      4,      579,    "R/W",  0,      0,      0ull,   0ull},
34274         {"INTERVAL"                    ,        4,      22,     579,    "R/W",  0,      0,      0ull,   0ull},
34275         {"WORDS_PER_CHUNK"             ,        26,     13,     579,    "R/W",  0,      0,      0ull,   0ull},
34276         {"POOL"                        ,        39,     3,      579,    "R/W",  0,      0,      0ull,   0ull},
34277         {"ENABLE"                      ,        42,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
34278         {"RESERVED_43_63"              ,        43,     21,     579,    "RAZ",  1,      0,      0,      0ull},
34279         {"CTL"                         ,        0,      1,      580,    "RO",   1,      0,      0,      0ull},
34280         {"NCB"                         ,        1,      1,      580,    "RO",   1,      0,      0,      0ull},
34281         {"STA"                         ,        2,      2,      580,    "RO",   1,      0,      0,      0ull},
34282         {"RESERVED_4_63"               ,        4,      60,     580,    "RAZ",  1,      0,      0,      0ull},
34283         {"MASK"                        ,        0,      16,     581,    "R/W1C",        0,      0,      0ull,   0ull},
34284         {"RESERVED_16_63"              ,        16,     48,     581,    "RAZ",  1,      0,      0,      0ull},
34285         {"ENABLE_TIMERS"               ,        0,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
34286         {"ENABLE_DWB"                  ,        1,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
34287         {"RESET"                       ,        2,      1,      582,    "RAZ",  0,      0,      0ull,   0ull},
34288         {"RESERVED_3_63"               ,        3,      61,     582,    "RAZ",  1,      0,      0,      0ull},
34289         {"MASK"                        ,        0,      16,     583,    "R/W",  0,      0,      0ull,   0ull},
34290         {"RESERVED_16_63"              ,        16,     48,     583,    "RAZ",  1,      0,      0,      0ull},
34291         {"INDEX"                       ,        0,      8,      584,    "R/W",  0,      0,      0ull,   0ull},
34292         {"INC"                         ,        8,      8,      584,    "R/W",  0,      0,      0ull,   0ull},
34293         {"RESERVED_16_63"              ,        16,     48,     584,    "RAZ",  1,      0,      0,      0ull},
34294         {"TDF0"                        ,        0,      1,      585,    "RO",   0,      0,      0ull,   0ull},
34295         {"TDF1"                        ,        1,      1,      585,    "RO",   0,      0,      0ull,   0ull},
34296         {"TCF"                         ,        2,      1,      585,    "RO",   0,      0,      0ull,   0ull},
34297         {"RESERVED_3_63"               ,        3,      61,     585,    "RAZ",  0,      0,      0ull,   0ull},
34298         {"ENA"                         ,        0,      1,      586,    "R/W",  0,      0,      0ull,   0ull},
34299         {"WRAP"                        ,        1,      1,      586,    "R/W",  0,      0,      0ull,   0ull},
34300         {"TRIG_CTL"                    ,        2,      2,      586,    "R/W",  0,      0,      0ull,   0ull},
34301         {"TIME_GRN"                    ,        4,      3,      586,    "R/W",  0,      0,      0ull,   0ull},
34302         {"FULL_THR"                    ,        7,      2,      586,    "R/W",  0,      0,      0ull,   0ull},
34303         {"CIU_TRG"                     ,        9,      1,      586,    "R/W",  0,      0,      0ull,   0ull},
34304         {"CIU_THR"                     ,        10,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
34305         {"MCD0_TRG"                    ,        11,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
34306         {"MCD0_THR"                    ,        12,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
34307         {"MCD0_ENA"                    ,        13,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
34308         {"IGNORE_O"                    ,        14,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
34309         {"RESERVED_15_63"              ,        15,     49,     586,    "RAZ",  0,      0,      0ull,   0ull},
34310         {"WPTR"                        ,        0,      8,      587,    "RO",   0,      0,      0ull,   0ull},
34311         {"RPTR"                        ,        8,      8,      587,    "RO",   0,      0,      0ull,   0ull},
34312         {"CYCLES"                      ,        16,     48,     587,    "RO",   0,      0,      0ull,   0ull},
34313         {"WPTR"                        ,        0,      10,     588,    "RO",   0,      0,      0ull,   0ull},
34314         {"RESERVED_10_11"              ,        10,     2,      588,    "RAZ",  0,      0,      0ull,   0ull},
34315         {"RPTR"                        ,        12,     10,     588,    "RO",   0,      0,      0ull,   0ull},
34316         {"RESERVED_22_23"              ,        22,     2,      588,    "RAZ",  0,      0,      0ull,   0ull},
34317         {"CYCLES"                      ,        24,     40,     588,    "RO",   0,      0,      0ull,   0ull},
34318         {"ADR"                         ,        0,      36,     589,    "R/W",  0,      1,      0ull,   0},
34319         {"RESERVED_36_63"              ,        36,     28,     589,    "RAZ",  0,      0,      0ull,   0ull},
34320         {"ADR"                         ,        0,      36,     590,    "R/W",  0,      0,      0ull,   0ull},
34321         {"RESERVED_36_63"              ,        36,     28,     590,    "RAZ",  0,      0,      0ull,   0ull},
34322         {"DWB"                         ,        0,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34323         {"PL2"                         ,        1,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34324         {"PSL1"                        ,        2,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34325         {"LDD"                         ,        3,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34326         {"LDI"                         ,        4,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34327         {"LDT"                         ,        5,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34328         {"STF"                         ,        6,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34329         {"STC"                         ,        7,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34330         {"STP"                         ,        8,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34331         {"STT"                         ,        9,      1,      591,    "R/W",  0,      0,      0ull,   1ull},
34332         {"IOBLD8"                      ,        10,     1,      591,    "R/W",  0,      0,      0ull,   1ull},
34333         {"IOBLD16"                     ,        11,     1,      591,    "R/W",  0,      0,      0ull,   1ull},
34334         {"IOBLD32"                     ,        12,     1,      591,    "R/W",  0,      0,      0ull,   1ull},
34335         {"IOBLD64"                     ,        13,     1,      591,    "R/W",  0,      0,      0ull,   1ull},
34336         {"IOBST"                       ,        14,     1,      591,    "R/W",  0,      0,      0ull,   1ull},
34337         {"IOBDMA"                      ,        15,     1,      591,    "R/W",  0,      0,      0ull,   1ull},
34338         {"SAA"                         ,        16,     1,      591,    "R/W",  0,      0,      0ull,   1ull},
34339         {"RESERVED_17_63"              ,        17,     47,     591,    "RAZ",  0,      0,      0ull,   0ull},
34340         {"MIO"                         ,        0,      1,      592,    "R/W",  0,      0,      0ull,   1ull},
34341         {"ILLEGAL3"                    ,        1,      2,      592,    "R/W",  0,      0,      0ull,   3ull},
34342         {"PCI"                         ,        3,      1,      592,    "R/W",  0,      0,      0ull,   1ull},
34343         {"KEY"                         ,        4,      1,      592,    "R/W",  0,      0,      0ull,   1ull},
34344         {"FPA"                         ,        5,      1,      592,    "R/W",  0,      0,      0ull,   1ull},
34345         {"DFA"                         ,        6,      1,      592,    "R/W",  0,      0,      0ull,   1ull},
34346         {"ZIP"                         ,        7,      1,      592,    "R/W",  0,      0,      0ull,   1ull},
34347         {"RNG"                         ,        8,      1,      592,    "R/W",  0,      0,      0ull,   1ull},
34348         {"ILLEGAL2"                    ,        9,      3,      592,    "R/W",  0,      0,      0ull,   7ull},
34349         {"POW"                         ,        12,     1,      592,    "R/W",  0,      0,      0ull,   1ull},
34350         {"ILLEGAL"                     ,        13,     19,     592,    "R/W",  0,      0,      0ull,   524287ull},
34351         {"RESERVED_32_63"              ,        32,     32,     592,    "RAZ",  0,      0,      0ull,   0ull},
34352         {"PP"                          ,        0,      16,     593,    "R/W",  0,      0,      0ull,   0ull},
34353         {"PKI"                         ,        16,     1,      593,    "R/W",  0,      0,      0ull,   0ull},
34354         {"PKO"                         ,        17,     1,      593,    "R/W",  0,      0,      0ull,   0ull},
34355         {"IOBREQ"                      ,        18,     1,      593,    "R/W",  0,      0,      0ull,   0ull},
34356         {"DWB"                         ,        19,     1,      593,    "R/W",  0,      0,      0ull,   0ull},
34357         {"RESERVED_20_63"              ,        20,     44,     593,    "RAZ",  0,      0,      0ull,   0ull},
34358         {"CIU_TRG"                     ,        0,      1,      594,    "R/W1C",        0,      0,      0ull,   0ull},
34359         {"CIU_THR"                     ,        1,      1,      594,    "R/W1C",        0,      0,      0ull,   0ull},
34360         {"MCD0_TRG"                    ,        2,      1,      594,    "R/W1C",        0,      0,      0ull,   0ull},
34361         {"MCD0_THR"                    ,        3,      1,      594,    "R/W1C",        0,      0,      0ull,   0ull},
34362         {"RESERVED_4_63"               ,        4,      60,     594,    "RAZ",  0,      0,      0ull,   0ull},
34363         {"DATA"                        ,        0,      64,     595,    "RO",   0,      0,      0ull,   0ull},
34364         {"ADR"                         ,        0,      36,     596,    "R/W",  0,      1,      0ull,   0},
34365         {"RESERVED_36_63"              ,        36,     28,     596,    "RAZ",  0,      0,      0ull,   0ull},
34366         {"ADR"                         ,        0,      36,     597,    "R/W",  0,      0,      0ull,   0ull},
34367         {"RESERVED_36_63"              ,        36,     28,     597,    "RAZ",  0,      0,      0ull,   0ull},
34368         {"DWB"                         ,        0,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34369         {"PL2"                         ,        1,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34370         {"PSL1"                        ,        2,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34371         {"LDD"                         ,        3,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34372         {"LDI"                         ,        4,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34373         {"LDT"                         ,        5,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34374         {"STF"                         ,        6,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34375         {"STC"                         ,        7,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34376         {"STP"                         ,        8,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34377         {"STT"                         ,        9,      1,      598,    "R/W",  0,      0,      0ull,   1ull},
34378         {"IOBLD8"                      ,        10,     1,      598,    "R/W",  0,      0,      0ull,   1ull},
34379         {"IOBLD16"                     ,        11,     1,      598,    "R/W",  0,      0,      0ull,   1ull},
34380         {"IOBLD32"                     ,        12,     1,      598,    "R/W",  0,      0,      0ull,   1ull},
34381         {"IOBLD64"                     ,        13,     1,      598,    "R/W",  0,      0,      0ull,   1ull},
34382         {"IOBST"                       ,        14,     1,      598,    "R/W",  0,      0,      0ull,   1ull},
34383         {"IOBDMA"                      ,        15,     1,      598,    "R/W",  0,      0,      0ull,   1ull},
34384         {"SAA"                         ,        16,     1,      598,    "R/W",  0,      0,      0ull,   1ull},
34385         {"RESERVED_17_63"              ,        17,     47,     598,    "RAZ",  0,      0,      0ull,   0ull},
34386         {"MIO"                         ,        0,      1,      599,    "R/W",  0,      0,      0ull,   1ull},
34387         {"ILLEGAL3"                    ,        1,      2,      599,    "R/W",  0,      0,      0ull,   3ull},
34388         {"PCI"                         ,        3,      1,      599,    "R/W",  0,      0,      0ull,   1ull},
34389         {"KEY"                         ,        4,      1,      599,    "R/W",  0,      0,      0ull,   1ull},
34390         {"FPA"                         ,        5,      1,      599,    "R/W",  0,      0,      0ull,   1ull},
34391         {"DFA"                         ,        6,      1,      599,    "R/W",  0,      0,      0ull,   1ull},
34392         {"ZIP"                         ,        7,      1,      599,    "R/W",  0,      0,      0ull,   1ull},
34393         {"RNG"                         ,        8,      1,      599,    "R/W",  0,      0,      0ull,   1ull},
34394         {"ILLEGAL2"                    ,        9,      3,      599,    "R/W",  0,      0,      0ull,   7ull},
34395         {"POW"                         ,        12,     1,      599,    "R/W",  0,      0,      0ull,   1ull},
34396         {"ILLEGAL"                     ,        13,     19,     599,    "R/W",  0,      0,      0ull,   524287ull},
34397         {"RESERVED_32_63"              ,        32,     32,     599,    "RAZ",  0,      0,      0ull,   0ull},
34398         {"PP"                          ,        0,      16,     600,    "R/W",  0,      0,      0ull,   0ull},
34399         {"PKI"                         ,        16,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
34400         {"PKO"                         ,        17,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
34401         {"IOBREQ"                      ,        18,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
34402         {"DWB"                         ,        19,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
34403         {"RESERVED_20_63"              ,        20,     44,     600,    "RAZ",  0,      0,      0ull,   0ull},
34404         {"ADR"                         ,        0,      36,     601,    "R/W",  0,      1,      0ull,   0},
34405         {"RESERVED_36_63"              ,        36,     28,     601,    "RAZ",  0,      0,      0ull,   0ull},
34406         {"ADR"                         ,        0,      36,     602,    "R/W",  0,      0,      0ull,   0ull},
34407         {"RESERVED_36_63"              ,        36,     28,     602,    "RAZ",  0,      0,      0ull,   0ull},
34408         {"DWB"                         ,        0,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34409         {"PL2"                         ,        1,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34410         {"PSL1"                        ,        2,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34411         {"LDD"                         ,        3,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34412         {"LDI"                         ,        4,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34413         {"LDT"                         ,        5,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34414         {"STF"                         ,        6,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34415         {"STC"                         ,        7,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34416         {"STP"                         ,        8,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34417         {"STT"                         ,        9,      1,      603,    "R/W",  0,      0,      0ull,   1ull},
34418         {"IOBLD8"                      ,        10,     1,      603,    "R/W",  0,      0,      0ull,   1ull},
34419         {"IOBLD16"                     ,        11,     1,      603,    "R/W",  0,      0,      0ull,   1ull},
34420         {"IOBLD32"                     ,        12,     1,      603,    "R/W",  0,      0,      0ull,   1ull},
34421         {"IOBLD64"                     ,        13,     1,      603,    "R/W",  0,      0,      0ull,   1ull},
34422         {"IOBST"                       ,        14,     1,      603,    "R/W",  0,      0,      0ull,   1ull},
34423         {"IOBDMA"                      ,        15,     1,      603,    "R/W",  0,      0,      0ull,   1ull},
34424         {"SAA"                         ,        16,     1,      603,    "R/W",  0,      0,      0ull,   1ull},
34425         {"RESERVED_17_63"              ,        17,     47,     603,    "RAZ",  0,      0,      0ull,   0ull},
34426         {"MIO"                         ,        0,      1,      604,    "R/W",  0,      0,      0ull,   1ull},
34427         {"ILLEGAL3"                    ,        1,      2,      604,    "R/W",  0,      0,      0ull,   3ull},
34428         {"PCI"                         ,        3,      1,      604,    "R/W",  0,      0,      0ull,   1ull},
34429         {"KEY"                         ,        4,      1,      604,    "R/W",  0,      0,      0ull,   1ull},
34430         {"FPA"                         ,        5,      1,      604,    "R/W",  0,      0,      0ull,   1ull},
34431         {"DFA"                         ,        6,      1,      604,    "R/W",  0,      0,      0ull,   1ull},
34432         {"ZIP"                         ,        7,      1,      604,    "R/W",  0,      0,      0ull,   1ull},
34433         {"RNG"                         ,        8,      1,      604,    "R/W",  0,      0,      0ull,   1ull},
34434         {"ILLEGAL2"                    ,        9,      3,      604,    "R/W",  0,      0,      0ull,   7ull},
34435         {"POW"                         ,        12,     1,      604,    "R/W",  0,      0,      0ull,   1ull},
34436         {"ILLEGAL"                     ,        13,     19,     604,    "R/W",  0,      0,      0ull,   524287ull},
34437         {"RESERVED_32_63"              ,        32,     32,     604,    "RAZ",  0,      0,      0ull,   0ull},
34438         {"PP"                          ,        0,      16,     605,    "R/W",  0,      0,      0ull,   0ull},
34439         {"PKI"                         ,        16,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
34440         {"PKO"                         ,        17,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
34441         {"IOBREQ"                      ,        18,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
34442         {"DWB"                         ,        19,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
34443         {"RESERVED_20_63"              ,        20,     44,     605,    "RAZ",  0,      0,      0ull,   0ull},
34444         {"ZIP_CTL"                     ,        0,      4,      606,    "RO",   1,      0,      0,      0ull},
34445         {"ZIP_CORE"                    ,        4,      27,     606,    "RO",   1,      0,      0,      0ull},
34446         {"RESERVED_31_63"              ,        31,     33,     606,    "RAZ",  1,      0,      0,      0ull},
34447         {"PTR"                         ,        0,      33,     607,    "R/W",  0,      0,      0ull,   0ull},
34448         {"SIZE"                        ,        33,     13,     607,    "R/W",  0,      0,      0ull,   0ull},
34449         {"POOL"                        ,        46,     3,      607,    "R/W",  0,      0,      0ull,   0ull},
34450         {"DWB"                         ,        49,     9,      607,    "R/W",  0,      0,      0ull,   0ull},
34451         {"RESERVED_58_63"              ,        58,     6,      607,    "RAZ",  0,      0,      0ull,   0ull},
34452         {"RESET"                       ,        0,      1,      608,    "RAZ",  0,      0,      0ull,   0ull},
34453         {"FORCECLK"                    ,        1,      1,      608,    "R/W",  0,      0,      0ull,   0ull},
34454         {"RESERVED_2_63"               ,        2,      62,     608,    "RAZ",  0,      0,      0ull,   0ull},
34455         {"DISABLED"                    ,        0,      1,      609,    "RO",   0,      0,      0ull,   0ull},
34456         {"RESERVED_1_7"                ,        1,      7,      609,    "RAZ",  0,      0,      0ull,   0ull},
34457         {"CTXSIZE"                     ,        8,      12,     609,    "RO",   0,      0,      1536ull,        1536ull},
34458         {"ONFSIZE"                     ,        20,     12,     609,    "RO",   0,      0,      512ull, 512ull},
34459         {"DEPTH"                       ,        32,     16,     609,    "RO",   0,      0,      31744ull,       31744ull},
34460         {"RESERVED_48_63"              ,        48,     16,     609,    "RAZ",  1,      0,      0,      0ull},
34461         {"ASSERTS"                     ,        0,      14,     610,    "RO",   0,      0,      0ull,   0ull},
34462         {"RESERVED_14_63"              ,        14,     50,     610,    "RAZ",  1,      0,      0,      0ull},
34463         {"DOORBELL"                    ,        0,      1,      611,    "R/W1C",        0,      0,      0ull,   0ull},
34464         {"RESERVED_1_63"               ,        1,      63,     611,    "RAZ",  1,      0,      0,      0ull},
34465         {"DOORBELL"                    ,        0,      1,      612,    "R/W",  0,      0,      0ull,   0ull},
34466         {"RESERVED_1_63"               ,        1,      63,     612,    "RAZ",  1,      0,      0,      0ull},
34467         {NULL,0,0,0,0,0,0,0,0}
34468 };
34469 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xxp1[] = {
34470          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
34471         {"cvmx_agl_gmx_bad_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      11,     0},
34472         {"cvmx_agl_gmx_bist"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1,      2,      11},
34473         {"cvmx_agl_gmx_drv_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      6,      13},
34474         {"cvmx_agl_gmx_inf_mode"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     3,      3,      19},
34475         {"cvmx_agl_gmx_prt#_cfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      7,      22},
34476         {"cvmx_agl_gmx_rx#_adr_cam0"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     5,      1,      29},
34477         {"cvmx_agl_gmx_rx#_adr_cam1"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      1,      30},
34478         {"cvmx_agl_gmx_rx#_adr_cam2"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     7,      1,      31},
34479         {"cvmx_agl_gmx_rx#_adr_cam3"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     8,      1,      32},
34480         {"cvmx_agl_gmx_rx#_adr_cam4"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     9,      1,      33},
34481         {"cvmx_agl_gmx_rx#_adr_cam5"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     1,      34},
34482         {"cvmx_agl_gmx_rx#_adr_cam_en" ,        CVMX_CSR_DB_TYPE_RSL,   64,     11,     2,      35},
34483         {"cvmx_agl_gmx_rx#_adr_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     12,     4,      37},
34484         {"cvmx_agl_gmx_rx#_decision"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     13,     2,      41},
34485         {"cvmx_agl_gmx_rx#_frm_chk"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     10,     43},
34486         {"cvmx_agl_gmx_rx#_frm_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     15,     11,     53},
34487         {"cvmx_agl_gmx_rx#_frm_max"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     16,     2,      64},
34488         {"cvmx_agl_gmx_rx#_frm_min"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     17,     2,      66},
34489         {"cvmx_agl_gmx_rx#_ifg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     18,     2,      68},
34490         {"cvmx_agl_gmx_rx#_int_en"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     19,     19,     70},
34491         {"cvmx_agl_gmx_rx#_int_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     20,     19,     89},
34492         {"cvmx_agl_gmx_rx#_jabber"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     21,     2,      108},
34493         {"cvmx_agl_gmx_rx#_pause_drop_time",    CVMX_CSR_DB_TYPE_RSL,   64,     22,     2,      110},
34494         {"cvmx_agl_gmx_rx#_stats_ctl"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     23,     2,      112},
34495         {"cvmx_agl_gmx_rx#_stats_octs" ,        CVMX_CSR_DB_TYPE_RSL,   64,     24,     2,      114},
34496         {"cvmx_agl_gmx_rx#_stats_octs_ctl",     CVMX_CSR_DB_TYPE_RSL,   64,     25,     2,      116},
34497         {"cvmx_agl_gmx_rx#_stats_octs_dmac",    CVMX_CSR_DB_TYPE_RSL,   64,     26,     2,      118},
34498         {"cvmx_agl_gmx_rx#_stats_octs_drp",     CVMX_CSR_DB_TYPE_RSL,   64,     27,     2,      120},
34499         {"cvmx_agl_gmx_rx#_stats_pkts" ,        CVMX_CSR_DB_TYPE_RSL,   64,     28,     2,      122},
34500         {"cvmx_agl_gmx_rx#_stats_pkts_bad",     CVMX_CSR_DB_TYPE_RSL,   64,     29,     2,      124},
34501         {"cvmx_agl_gmx_rx#_stats_pkts_ctl",     CVMX_CSR_DB_TYPE_RSL,   64,     30,     2,      126},
34502         {"cvmx_agl_gmx_rx#_stats_pkts_dmac",    CVMX_CSR_DB_TYPE_RSL,   64,     31,     2,      128},
34503         {"cvmx_agl_gmx_rx#_stats_pkts_drp",     CVMX_CSR_DB_TYPE_RSL,   64,     32,     2,      130},
34504         {"cvmx_agl_gmx_rx#_udd_skp"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     33,     4,      132},
34505         {"cvmx_agl_gmx_rx_bp_drop#"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     34,     2,      136},
34506         {"cvmx_agl_gmx_rx_bp_off#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     35,     2,      138},
34507         {"cvmx_agl_gmx_rx_bp_on#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     36,     2,      140},
34508         {"cvmx_agl_gmx_rx_prt_info"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     37,     4,      142},
34509         {"cvmx_agl_gmx_rx_tx_status"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     38,     4,      146},
34510         {"cvmx_agl_gmx_smac#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     39,     2,      150},
34511         {"cvmx_agl_gmx_stat_bp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     40,     3,      152},
34512         {"cvmx_agl_gmx_tx#_append"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     41,     5,      155},
34513         {"cvmx_agl_gmx_tx#_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     42,     3,      160},
34514         {"cvmx_agl_gmx_tx#_min_pkt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     43,     2,      163},
34515         {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL,   64,     44,     2,      165},
34516         {"cvmx_agl_gmx_tx#_pause_pkt_time",     CVMX_CSR_DB_TYPE_RSL,   64,     45,     2,      167},
34517         {"cvmx_agl_gmx_tx#_pause_togo" ,        CVMX_CSR_DB_TYPE_RSL,   64,     46,     2,      169},
34518         {"cvmx_agl_gmx_tx#_pause_zero" ,        CVMX_CSR_DB_TYPE_RSL,   64,     47,     2,      171},
34519         {"cvmx_agl_gmx_tx#_soft_pause" ,        CVMX_CSR_DB_TYPE_RSL,   64,     48,     2,      173},
34520         {"cvmx_agl_gmx_tx#_stat0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     49,     2,      175},
34521         {"cvmx_agl_gmx_tx#_stat1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     50,     2,      177},
34522         {"cvmx_agl_gmx_tx#_stat2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     51,     2,      179},
34523         {"cvmx_agl_gmx_tx#_stat3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     52,     2,      181},
34524         {"cvmx_agl_gmx_tx#_stat4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     53,     2,      183},
34525         {"cvmx_agl_gmx_tx#_stat5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     54,     2,      185},
34526         {"cvmx_agl_gmx_tx#_stat6"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     55,     2,      187},
34527         {"cvmx_agl_gmx_tx#_stat7"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     56,     2,      189},
34528         {"cvmx_agl_gmx_tx#_stat8"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     57,     2,      191},
34529         {"cvmx_agl_gmx_tx#_stat9"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     58,     2,      193},
34530         {"cvmx_agl_gmx_tx#_stats_ctl"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     59,     2,      195},
34531         {"cvmx_agl_gmx_tx#_thresh"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     60,     2,      197},
34532         {"cvmx_agl_gmx_tx_bp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     61,     2,      199},
34533         {"cvmx_agl_gmx_tx_col_attempt" ,        CVMX_CSR_DB_TYPE_RSL,   64,     62,     2,      201},
34534         {"cvmx_agl_gmx_tx_ifg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     63,     3,      203},
34535         {"cvmx_agl_gmx_tx_int_en"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     64,     10,     206},
34536         {"cvmx_agl_gmx_tx_int_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     65,     10,     216},
34537         {"cvmx_agl_gmx_tx_jam"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     66,     2,      226},
34538         {"cvmx_agl_gmx_tx_lfsr"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     67,     2,      228},
34539         {"cvmx_agl_gmx_tx_ovr_bp"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     68,     6,      230},
34540         {"cvmx_agl_gmx_tx_pause_pkt_dmac",      CVMX_CSR_DB_TYPE_RSL,   64,     69,     2,      236},
34541         {"cvmx_agl_gmx_tx_pause_pkt_type",      CVMX_CSR_DB_TYPE_RSL,   64,     70,     2,      238},
34542         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     71,     2,      240},
34543         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     72,     2,      242},
34544         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     73,     2,      244},
34545         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     74,     2,      246},
34546         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     75,     21,     248},
34547         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     100,    2,      269},
34548         {"cvmx_ciu_int#_en4_0"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     125,    21,     271},
34549         {"cvmx_ciu_int#_en4_1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     137,    2,      292},
34550         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     149,    21,     294},
34551         {"cvmx_ciu_int#_sum4"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     174,    21,     315},
34552         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     186,    2,      336},
34553         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     187,    2,      338},
34554         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     199,    2,      340},
34555         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     211,    2,      342},
34556         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     212,    2,      344},
34557         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     213,    2,      346},
34558         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     214,    1,      348},
34559         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     226,    3,      349},
34560         {"cvmx_ciu_qlm_dcok"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     227,    2,      352},
34561         {"cvmx_ciu_qlm_jtgc"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     228,    5,      354},
34562         {"cvmx_ciu_qlm_jtgd"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     229,    6,      359},
34563         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     230,    2,      365},
34564         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     231,    2,      367},
34565         {"cvmx_ciu_soft_prst1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     232,    2,      369},
34566         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     233,    2,      371},
34567         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     234,    3,      373},
34568         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     238,    7,      376},
34569         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     250,    6,      383},
34570         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     251,    7,      389},
34571         {"cvmx_fpa_fpf#_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     252,    3,      396},
34572         {"cvmx_fpa_fpf#_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     259,    2,      399},
34573         {"cvmx_fpa_fpf0_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     266,    3,      401},
34574         {"cvmx_fpa_fpf0_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     267,    2,      404},
34575         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     268,    29,     406},
34576         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     269,    29,     435},
34577         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     270,    2,      464},
34578         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     278,    2,      466},
34579         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     286,    3,      468},
34580         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     287,    3,      471},
34581         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     288,    2,      474},
34582         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     289,    2,      476},
34583         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     290,    7,      478},
34584         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     292,    2,      485},
34585         {"cvmx_gmx#_clk_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     294,    2,      487},
34586         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     296,    7,      489},
34587         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     298,    2,      496},
34588         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     300,    10,     498},
34589         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     308,    1,      508},
34590         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     316,    1,      509},
34591         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     324,    1,      510},
34592         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     332,    1,      511},
34593         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     340,    1,      512},
34594         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     348,    1,      513},
34595         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     356,    2,      514},
34596         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     364,    4,      516},
34597         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     372,    2,      520},
34598         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     380,    9,      522},
34599         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     388,    10,     531},
34600         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     396,    2,      541},
34601         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     404,    25,     543},
34602         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     412,    25,     568},
34603         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     420,    2,      593},
34604         {"cvmx_gmx#_rx#_pause_drop_time",       CVMX_CSR_DB_TYPE_RSL,   64,     428,    2,      595},
34605         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     436,    2,      597},
34606         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     444,    2,      599},
34607         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     452,    2,      601},
34608         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     460,    2,      603},
34609         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     468,    2,      605},
34610         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     476,    2,      607},
34611         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     484,    2,      609},
34612         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     492,    2,      611},
34613         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     500,    2,      613},
34614         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     508,    2,      615},
34615         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     516,    4,      617},
34616         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     524,    2,      621},
34617         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     532,    2,      623},
34618         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     540,    2,      625},
34619         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     548,    4,      627},
34620         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     550,    2,      631},
34621         {"cvmx_gmx#_rx_xaui_bad_col"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     552,    5,      633},
34622         {"cvmx_gmx#_rx_xaui_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     554,    2,      638},
34623         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     556,    2,      640},
34624         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     564,    3,      642},
34625         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     566,    5,      645},
34626         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     574,    2,      650},
34627         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     582,    3,      652},
34628         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     590,    2,      655},
34629         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     598,    2,      657},
34630         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     606,    2,      659},
34631         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     614,    2,      661},
34632         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     622,    2,      663},
34633         {"cvmx_gmx#_tx#_sgmii_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     630,    2,      665},
34634         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     638,    2,      667},
34635         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     646,    2,      669},
34636         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     654,    2,      671},
34637         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     662,    2,      673},
34638         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     670,    2,      675},
34639         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     678,    2,      677},
34640         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     686,    2,      679},
34641         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     694,    2,      681},
34642         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     702,    2,      683},
34643         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     710,    2,      685},
34644         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     718,    2,      687},
34645         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     726,    2,      689},
34646         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     734,    2,      691},
34647         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     742,    2,      693},
34648         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     750,    2,      695},
34649         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     752,    2,      697},
34650         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     754,    2,      699},
34651         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     756,    3,      701},
34652         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     758,    8,      704},
34653         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     760,    8,      712},
34654         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     762,    2,      720},
34655         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     764,    2,      722},
34656         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     766,    6,      724},
34657         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     768,    2,      730},
34658         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     770,    2,      732},
34659         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     772,    2,      734},
34660         {"cvmx_gmx#_tx_xaui_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     774,    9,      736},
34661         {"cvmx_gmx#_xaui_ext_loopback" ,        CVMX_CSR_DB_TYPE_RSL,   64,     776,    3,      745},
34662         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     778,    9,      748},
34663         {"cvmx_gpio_clk_gen#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     794,    2,      757},
34664         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     798,    2,      759},
34665         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     799,    2,      761},
34666         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     800,    2,      763},
34667         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     801,    2,      765},
34668         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     802,    19,     767},
34669         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     803,    6,      786},
34670         {"cvmx_iob_dwb_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     804,    3,      792},
34671         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     805,    3,      795},
34672         {"cvmx_iob_i2c_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     806,    3,      798},
34673         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     807,    5,      801},
34674         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     808,    5,      806},
34675         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     809,    1,      811},
34676         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     810,    1,      812},
34677         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     811,    7,      813},
34678         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     812,    7,      820},
34679         {"cvmx_iob_n2c_l2c_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     813,    3,      827},
34680         {"cvmx_iob_n2c_rsp_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     814,    3,      830},
34681         {"cvmx_iob_outb_com_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     815,    3,      833},
34682         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     816,    5,      836},
34683         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     817,    5,      841},
34684         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     818,    1,      846},
34685         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     819,    1,      847},
34686         {"cvmx_iob_outb_fpa_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     820,    3,      848},
34687         {"cvmx_iob_outb_req_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     821,    3,      851},
34688         {"cvmx_iob_p2c_req_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     822,    3,      854},
34689         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     823,    2,      857},
34690         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     824,    2,      859},
34691         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     825,    2,      861},
34692         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     826,    2,      863},
34693         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     827,    19,     865},
34694         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     828,    2,      884},
34695         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     829,    1,      886},
34696         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     830,    15,     887},
34697         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     831,    13,     902},
34698         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     832,    13,     915},
34699         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     833,    2,      928},
34700         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     834,    2,      930},
34701         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     835,    2,      932},
34702         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     836,    3,      934},
34703         {"cvmx_ipd_port#_bp_page_cnt2" ,        CVMX_CSR_DB_TYPE_NCB,   64,     844,    3,      937},
34704         {"cvmx_ipd_port_bp_counters2_pair#",    CVMX_CSR_DB_TYPE_NCB,   64,     848,    2,      940},
34705         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     852,    2,      942},
34706         {"cvmx_ipd_port_qos_#_cnt"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     860,    2,      944},
34707         {"cvmx_ipd_port_qos_int#"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     956,    1,      946},
34708         {"cvmx_ipd_port_qos_int_enb#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     959,    1,      947},
34709         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     962,    6,      948},
34710         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     963,    5,      954},
34711         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     964,    6,      959},
34712         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     965,    7,      965},
34713         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     966,    2,      972},
34714         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     974,    2,      974},
34715         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     975,    3,      976},
34716         {"cvmx_ipd_red_port_enable2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     976,    2,      979},
34717         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     977,    5,      981},
34718         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     985,    3,      986},
34719         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     986,    4,      989},
34720         {"cvmx_ipd_sub_port_qos_cnt"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     987,    3,      993},
34721         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     988,    2,      996},
34722         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     989,    2,      998},
34723         {"cvmx_key_bist_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     990,    4,      1000},
34724         {"cvmx_key_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     991,    3,      1004},
34725         {"cvmx_key_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     992,    5,      1007},
34726         {"cvmx_key_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     993,    5,      1012},
34727         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     994,    7,      1017},
34728         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     995,    11,     1024},
34729         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     996,    8,      1035},
34730         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     997,    15,     1043},
34731         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     998,    8,      1058},
34732         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     999,    5,      1066},
34733         {"cvmx_l2c_grpwrr0"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1000,   2,      1071},
34734         {"cvmx_l2c_grpwrr1"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1001,   2,      1073},
34735         {"cvmx_l2c_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1002,   10,     1075},
34736         {"cvmx_l2c_int_stat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1003,   10,     1085},
34737         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1004,   4,      1095},
34738         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1005,   2,      1099},
34739         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1006,   14,     1101},
34740         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1007,   19,     1115},
34741         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1008,   3,      1134},
34742         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1009,   3,      1137},
34743         {"cvmx_l2c_oob"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1010,   3,      1140},
34744         {"cvmx_l2c_oob1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1011,   6,      1143},
34745         {"cvmx_l2c_oob2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1012,   6,      1149},
34746         {"cvmx_l2c_oob3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1013,   6,      1155},
34747         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1014,   2,      1161},
34748         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1018,   17,     1163},
34749         {"cvmx_l2c_ppgrp"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1019,   13,     1180},
34750         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1020,   5,      1193},
34751         {"cvmx_l2c_spar1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1021,   5,      1198},
34752         {"cvmx_l2c_spar2"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1022,   5,      1203},
34753         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1023,   2,      1208},
34754         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1024,   3,      1210},
34755         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1025,   2,      1213},
34756         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1026,   2,      1215},
34757         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1027,   2,      1217},
34758         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1028,   7,      1219},
34759         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1029,   5,      1226},
34760         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1030,   3,      1231},
34761         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1031,   3,      1234},
34762         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1032,   2,      1237},
34763         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1033,   2,      1239},
34764         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1034,   2,      1241},
34765         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1035,   6,      1243},
34766         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1036,   14,     1249},
34767         {"cvmx_led_blink"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1037,   2,      1263},
34768         {"cvmx_led_clk_phase"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1038,   2,      1265},
34769         {"cvmx_led_cylon"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1039,   2,      1267},
34770         {"cvmx_led_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1040,   2,      1269},
34771         {"cvmx_led_en"                 ,        CVMX_CSR_DB_TYPE_RSL,   64,     1041,   2,      1271},
34772         {"cvmx_led_polarity"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1042,   2,      1273},
34773         {"cvmx_led_prt"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1043,   2,      1275},
34774         {"cvmx_led_prt_fmt"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1044,   2,      1277},
34775         {"cvmx_led_prt_status#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1045,   2,      1279},
34776         {"cvmx_led_udd_cnt#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1053,   2,      1281},
34777         {"cvmx_led_udd_dat#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1055,   2,      1283},
34778         {"cvmx_led_udd_dat_clr#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1057,   2,      1285},
34779         {"cvmx_led_udd_dat_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1059,   2,      1287},
34780         {"cvmx_lmc#_bist_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1061,   2,      1289},
34781         {"cvmx_lmc#_bist_result"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1063,   8,      1291},
34782         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1065,   7,      1299},
34783         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1067,   19,     1306},
34784         {"cvmx_lmc#_ctl1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1069,   8,      1325},
34785         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1071,   2,      1333},
34786         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1073,   2,      1335},
34787         {"cvmx_lmc#_dclk_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1075,   5,      1337},
34788         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1077,   18,     1342},
34789         {"cvmx_lmc#_delay_cfg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1079,   6,      1360},
34790         {"cvmx_lmc#_dll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1081,   5,      1366},
34791         {"cvmx_lmc#_dual_memcfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1083,   5,      1371},
34792         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1085,   5,      1376},
34793         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1087,   6,      1381},
34794         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1089,   2,      1387},
34795         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1091,   2,      1389},
34796         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1093,   14,     1391},
34797         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1095,   9,      1405},
34798         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1097,   2,      1414},
34799         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1099,   2,      1416},
34800         {"cvmx_lmc#_pll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1101,   12,     1418},
34801         {"cvmx_lmc#_pll_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1103,   6,      1430},
34802         {"cvmx_lmc#_read_level_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1105,   7,      1436},
34803         {"cvmx_lmc#_read_level_dbg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1107,   4,      1443},
34804         {"cvmx_lmc#_read_level_rank#"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1109,   11,     1447},
34805         {"cvmx_lmc#_rodt_comp_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1117,   6,      1458},
34806         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1119,   9,      1464},
34807         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1121,   5,      1473},
34808         {"cvmx_lmc#_wodt_ctl1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1123,   5,      1478},
34809         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1125,   5,      1483},
34810         {"cvmx_mio_boot_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1126,   3,      1488},
34811         {"cvmx_mio_boot_dma_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1127,   10,     1491},
34812         {"cvmx_mio_boot_dma_int#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1130,   3,      1501},
34813         {"cvmx_mio_boot_dma_int_en#"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1133,   3,      1504},
34814         {"cvmx_mio_boot_dma_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1136,   15,     1507},
34815         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1139,   3,      1522},
34816         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1140,   3,      1525},
34817         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1141,   3,      1528},
34818         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1142,   5,      1531},
34819         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1144,   1,      1536},
34820         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1145,   13,     1537},
34821         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1153,   13,     1550},
34822         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1161,   6,      1563},
34823         {"cvmx_mio_fus_bnk_dat#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1162,   1,      1569},
34824         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1166,   2,      1570},
34825         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1167,   2,      1572},
34826         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1168,   13,     1574},
34827         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1169,   8,      1587},
34828         {"cvmx_mio_fus_ema"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1170,   4,      1595},
34829         {"cvmx_mio_fus_pdf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1171,   1,      1599},
34830         {"cvmx_mio_fus_pll"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1172,   3,      1600},
34831         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1173,   2,      1603},
34832         {"cvmx_mio_fus_prog_times"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1174,   6,      1605},
34833         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1175,   7,      1611},
34834         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1176,   4,      1618},
34835         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1177,   2,      1622},
34836         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1178,   2,      1624},
34837         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1179,   13,     1626},
34838         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1181,   12,     1639},
34839         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1183,   3,      1651},
34840         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1185,   3,      1654},
34841         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1187,   2,      1657},
34842         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1189,   2,      1659},
34843         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1191,   2,      1661},
34844         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1193,   7,      1663},
34845         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1195,   2,      1670},
34846         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1197,   7,      1672},
34847         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1199,   4,      1679},
34848         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1201,   8,      1683},
34849         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1203,   9,      1691},
34850         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1205,   7,      1700},
34851         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1207,   9,      1707},
34852         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1209,   2,      1716},
34853         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1211,   2,      1718},
34854         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1213,   4,      1720},
34855         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1215,   2,      1724},
34856         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1217,   2,      1726},
34857         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1219,   2,      1728},
34858         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1221,   4,      1730},
34859         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1223,   2,      1734},
34860         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1225,   2,      1736},
34861         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1227,   2,      1738},
34862         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1229,   2,      1740},
34863         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1231,   2,      1742},
34864         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1233,   2,      1744},
34865         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1235,   6,      1746},
34866         {"cvmx_mix#_bist"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1237,   5,      1752},
34867         {"cvmx_mix#_ctl"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     1238,   8,      1757},
34868         {"cvmx_mix#_intena"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1239,   8,      1765},
34869         {"cvmx_mix#_ircnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1240,   2,      1773},
34870         {"cvmx_mix#_irhwm"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1241,   3,      1775},
34871         {"cvmx_mix#_iring1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1242,   5,      1778},
34872         {"cvmx_mix#_iring2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1243,   4,      1783},
34873         {"cvmx_mix#_isr"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     1244,   8,      1787},
34874         {"cvmx_mix#_orcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1245,   2,      1795},
34875         {"cvmx_mix#_orhwm"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1246,   2,      1797},
34876         {"cvmx_mix#_oring1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1247,   5,      1799},
34877         {"cvmx_mix#_oring2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1248,   4,      1804},
34878         {"cvmx_mix#_remcnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1249,   4,      1808},
34879         {"cvmx_npei_bar1_index#"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     1250,   5,      1812},
34880         {"cvmx_npei_bist_status"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1282,   59,     1817},
34881         {"cvmx_npei_ctl_port0"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1283,   17,     1876},
34882         {"cvmx_npei_ctl_port1"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1284,   17,     1893},
34883         {"cvmx_npei_ctl_status"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1285,   6,      1910},
34884         {"cvmx_npei_ctl_status2"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1286,   11,     1916},
34885         {"cvmx_npei_data_out_cnt"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1287,   5,      1927},
34886         {"cvmx_npei_dbg_data"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1288,   8,      1932},
34887         {"cvmx_npei_dbg_select"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1289,   2,      1940},
34888         {"cvmx_npei_dma#_counts"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1290,   3,      1942},
34889         {"cvmx_npei_dma#_dbell"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     1295,   2,      1945},
34890         {"cvmx_npei_dma#_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1300,   3,      1947},
34891         {"cvmx_npei_dma#_naddr"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1305,   2,      1950},
34892         {"cvmx_npei_dma0_int_level"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1310,   2,      1952},
34893         {"cvmx_npei_dma1_int_level"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1311,   2,      1954},
34894         {"cvmx_npei_dma_cnts"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1312,   2,      1956},
34895         {"cvmx_npei_dma_control"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1313,   16,     1958},
34896         {"cvmx_npei_dma_state1_p1"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1314,   11,     1974},
34897         {"cvmx_npei_dma_state2_p1"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1315,   6,      1985},
34898         {"cvmx_npei_dma_state3_p1"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1316,   5,      1991},
34899         {"cvmx_npei_dma_state4_p1"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1317,   5,      1996},
34900         {"cvmx_npei_dma_state5_p1"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1318,   3,      2001},
34901         {"cvmx_npei_int_enb"           ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1319,   63,     2004},
34902         {"cvmx_npei_int_enb2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1320,   62,     2067},
34903         {"cvmx_npei_int_info"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1321,   3,      2129},
34904         {"cvmx_npei_int_sum"           ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1322,   60,     2132},
34905         {"cvmx_npei_last_win_rdata0"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1323,   1,      2192},
34906         {"cvmx_npei_last_win_rdata1"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1324,   1,      2193},
34907         {"cvmx_npei_mem_access_ctl"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1325,   3,      2194},
34908         {"cvmx_npei_mem_access_subid#" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1326,   11,     2197},
34909         {"cvmx_npei_msi_enb0"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1342,   1,      2208},
34910         {"cvmx_npei_msi_enb1"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1343,   1,      2209},
34911         {"cvmx_npei_msi_enb2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1344,   1,      2210},
34912         {"cvmx_npei_msi_enb3"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1345,   1,      2211},
34913         {"cvmx_npei_msi_rcv0"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1346,   1,      2212},
34914         {"cvmx_npei_msi_rcv1"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1347,   1,      2213},
34915         {"cvmx_npei_msi_rcv2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1348,   1,      2214},
34916         {"cvmx_npei_msi_rcv3"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1349,   1,      2215},
34917         {"cvmx_npei_msi_rd_map"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1350,   3,      2216},
34918         {"cvmx_npei_msi_wr_map"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1351,   3,      2219},
34919         {"cvmx_npei_pcie_msi_rcv"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1352,   2,      2222},
34920         {"cvmx_npei_pcie_msi_rcv_b1"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1353,   3,      2224},
34921         {"cvmx_npei_pcie_msi_rcv_b2"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1354,   3,      2227},
34922         {"cvmx_npei_pcie_msi_rcv_b3"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1355,   3,      2230},
34923         {"cvmx_npei_rsl_int_blocks"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1356,   29,     2233},
34924         {"cvmx_npei_scratch_1"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1357,   1,      2262},
34925         {"cvmx_npei_state1"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1358,   4,      2263},
34926         {"cvmx_npei_state2"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1359,   7,      2267},
34927         {"cvmx_npei_state3"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1360,   5,      2274},
34928         {"cvmx_npei_win_rd_addr"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1361,   4,      2279},
34929         {"cvmx_npei_win_rd_data"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1362,   1,      2283},
34930         {"cvmx_npei_win_wr_addr"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1363,   4,      2284},
34931         {"cvmx_npei_win_wr_data"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1364,   1,      2288},
34932         {"cvmx_npei_win_wr_mask"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1365,   2,      2289},
34933         {"cvmx_npei_window_ctl"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1366,   2,      2291},
34934         {"cvmx_pcieep_cfg000"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1367,   2,      2293},
34935         {"cvmx_pcieep_cfg001"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1368,   24,     2295},
34936         {"cvmx_pcieep_cfg002"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1369,   4,      2319},
34937         {"cvmx_pcieep_cfg003"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1370,   5,      2323},
34938         {"cvmx_pcieep_cfg004"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1371,   5,      2328},
34939         {"cvmx_pcieep_cfg004_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1372,   2,      2333},
34940         {"cvmx_pcieep_cfg005"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1373,   1,      2335},
34941         {"cvmx_pcieep_cfg005_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1374,   1,      2336},
34942         {"cvmx_pcieep_cfg006"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1375,   5,      2337},
34943         {"cvmx_pcieep_cfg006_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1376,   2,      2342},
34944         {"cvmx_pcieep_cfg007"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1377,   1,      2344},
34945         {"cvmx_pcieep_cfg007_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1378,   1,      2345},
34946         {"cvmx_pcieep_cfg008"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1379,   4,      2346},
34947         {"cvmx_pcieep_cfg008_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1380,   2,      2350},
34948         {"cvmx_pcieep_cfg009"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1381,   2,      2352},
34949         {"cvmx_pcieep_cfg009_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1382,   1,      2354},
34950         {"cvmx_pcieep_cfg010"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1383,   1,      2355},
34951         {"cvmx_pcieep_cfg011"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1384,   2,      2356},
34952         {"cvmx_pcieep_cfg012"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1385,   3,      2358},
34953         {"cvmx_pcieep_cfg012_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1386,   2,      2361},
34954         {"cvmx_pcieep_cfg013"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1387,   2,      2363},
34955         {"cvmx_pcieep_cfg015"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1388,   4,      2365},
34956         {"cvmx_pcieep_cfg016"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1389,   10,     2369},
34957         {"cvmx_pcieep_cfg017"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1390,   12,     2379},
34958         {"cvmx_pcieep_cfg020"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1391,   7,      2391},
34959         {"cvmx_pcieep_cfg021"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1392,   2,      2398},
34960         {"cvmx_pcieep_cfg022"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1393,   1,      2400},
34961         {"cvmx_pcieep_cfg023"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1394,   2,      2401},
34962         {"cvmx_pcieep_cfg028"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1395,   7,      2403},
34963         {"cvmx_pcieep_cfg029"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1396,   11,     2410},
34964         {"cvmx_pcieep_cfg030"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1397,   19,     2421},
34965         {"cvmx_pcieep_cfg031"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1398,   11,     2440},
34966         {"cvmx_pcieep_cfg032"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1399,   17,     2451},
34967         {"cvmx_pcieep_cfg033"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1400,   12,     2468},
34968         {"cvmx_pcieep_cfg034"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1401,   22,     2480},
34969         {"cvmx_pcieep_cfg037"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1402,   3,      2502},
34970         {"cvmx_pcieep_cfg038"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1403,   3,      2505},
34971         {"cvmx_pcieep_cfg039"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1404,   1,      2508},
34972         {"cvmx_pcieep_cfg040"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1405,   1,      2509},
34973         {"cvmx_pcieep_cfg041"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1406,   1,      2510},
34974         {"cvmx_pcieep_cfg042"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1407,   1,      2511},
34975         {"cvmx_pcieep_cfg064"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1408,   3,      2512},
34976         {"cvmx_pcieep_cfg065"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1409,   14,     2515},
34977         {"cvmx_pcieep_cfg066"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1410,   14,     2529},
34978         {"cvmx_pcieep_cfg067"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1411,   14,     2543},
34979         {"cvmx_pcieep_cfg068"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1412,   9,      2557},
34980         {"cvmx_pcieep_cfg069"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1413,   9,      2566},
34981         {"cvmx_pcieep_cfg070"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1414,   6,      2575},
34982         {"cvmx_pcieep_cfg071"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1415,   1,      2581},
34983         {"cvmx_pcieep_cfg072"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1416,   1,      2582},
34984         {"cvmx_pcieep_cfg073"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1417,   1,      2583},
34985         {"cvmx_pcieep_cfg074"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1418,   1,      2584},
34986         {"cvmx_pcieep_cfg448"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1419,   2,      2585},
34987         {"cvmx_pcieep_cfg449"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1420,   1,      2587},
34988         {"cvmx_pcieep_cfg450"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1421,   6,      2588},
34989         {"cvmx_pcieep_cfg451"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1422,   6,      2594},
34990         {"cvmx_pcieep_cfg452"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1423,   13,     2600},
34991         {"cvmx_pcieep_cfg453"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1424,   5,      2613},
34992         {"cvmx_pcieep_cfg454"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1425,   8,      2618},
34993         {"cvmx_pcieep_cfg455"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1426,   19,     2626},
34994         {"cvmx_pcieep_cfg456"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1427,   3,      2645},
34995         {"cvmx_pcieep_cfg458"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1428,   1,      2648},
34996         {"cvmx_pcieep_cfg459"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1429,   1,      2649},
34997         {"cvmx_pcieep_cfg460"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1430,   3,      2650},
34998         {"cvmx_pcieep_cfg461"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1431,   3,      2653},
34999         {"cvmx_pcieep_cfg462"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1432,   3,      2656},
35000         {"cvmx_pcieep_cfg463"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1433,   4,      2659},
35001         {"cvmx_pcieep_cfg464"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1434,   4,      2663},
35002         {"cvmx_pcieep_cfg465"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1435,   4,      2667},
35003         {"cvmx_pcieep_cfg466"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1436,   7,      2671},
35004         {"cvmx_pcieep_cfg467"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1437,   5,      2678},
35005         {"cvmx_pcieep_cfg468"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1438,   5,      2683},
35006         {"cvmx_pcieep_cfg490"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1439,   4,      2688},
35007         {"cvmx_pcieep_cfg491"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1440,   4,      2692},
35008         {"cvmx_pcieep_cfg492"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1441,   4,      2696},
35009         {"cvmx_pcieep_cfg516"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1442,   1,      2700},
35010         {"cvmx_pcieep_cfg517"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1443,   1,      2701},
35011         {"cvmx_pcierc#_cfg000"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1444,   2,      2702},
35012         {"cvmx_pcierc#_cfg001"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1446,   24,     2704},
35013         {"cvmx_pcierc#_cfg002"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1448,   4,      2728},
35014         {"cvmx_pcierc#_cfg003"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1450,   5,      2732},
35015         {"cvmx_pcierc#_cfg004"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1452,   1,      2737},
35016         {"cvmx_pcierc#_cfg005"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1454,   1,      2738},
35017         {"cvmx_pcierc#_cfg006"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1456,   4,      2739},
35018         {"cvmx_pcierc#_cfg007"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1458,   17,     2743},
35019         {"cvmx_pcierc#_cfg008"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1460,   4,      2760},
35020         {"cvmx_pcierc#_cfg009"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1462,   6,      2764},
35021         {"cvmx_pcierc#_cfg010"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1464,   1,      2770},
35022         {"cvmx_pcierc#_cfg011"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1466,   1,      2771},
35023         {"cvmx_pcierc#_cfg012"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1468,   2,      2772},
35024         {"cvmx_pcierc#_cfg013"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1470,   2,      2774},
35025         {"cvmx_pcierc#_cfg014"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1472,   1,      2776},
35026         {"cvmx_pcierc#_cfg015"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1474,   15,     2777},
35027         {"cvmx_pcierc#_cfg016"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1476,   10,     2792},
35028         {"cvmx_pcierc#_cfg017"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1478,   12,     2802},
35029         {"cvmx_pcierc#_cfg020"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1480,   7,      2814},
35030         {"cvmx_pcierc#_cfg021"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1482,   2,      2821},
35031         {"cvmx_pcierc#_cfg022"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1484,   1,      2823},
35032         {"cvmx_pcierc#_cfg023"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1486,   2,      2824},
35033         {"cvmx_pcierc#_cfg028"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1488,   7,      2826},
35034         {"cvmx_pcierc#_cfg029"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1490,   11,     2833},
35035         {"cvmx_pcierc#_cfg030"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1492,   19,     2844},
35036         {"cvmx_pcierc#_cfg031"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1494,   11,     2863},
35037         {"cvmx_pcierc#_cfg032"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1496,   20,     2874},
35038         {"cvmx_pcierc#_cfg033"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1498,   12,     2894},
35039         {"cvmx_pcierc#_cfg034"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1500,   22,     2906},
35040         {"cvmx_pcierc#_cfg035"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1502,   8,      2928},
35041         {"cvmx_pcierc#_cfg036"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1504,   4,      2936},
35042         {"cvmx_pcierc#_cfg037"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1506,   3,      2940},
35043         {"cvmx_pcierc#_cfg038"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1508,   3,      2943},
35044         {"cvmx_pcierc#_cfg039"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1510,   1,      2946},
35045         {"cvmx_pcierc#_cfg040"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1512,   1,      2947},
35046         {"cvmx_pcierc#_cfg041"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1514,   1,      2948},
35047         {"cvmx_pcierc#_cfg042"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1516,   1,      2949},
35048         {"cvmx_pcierc#_cfg064"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1518,   3,      2950},
35049         {"cvmx_pcierc#_cfg065"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1520,   14,     2953},
35050         {"cvmx_pcierc#_cfg066"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1522,   14,     2967},
35051         {"cvmx_pcierc#_cfg067"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1524,   14,     2981},
35052         {"cvmx_pcierc#_cfg068"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1526,   9,      2995},
35053         {"cvmx_pcierc#_cfg069"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1528,   9,      3004},
35054         {"cvmx_pcierc#_cfg070"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1530,   6,      3013},
35055         {"cvmx_pcierc#_cfg071"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1532,   1,      3019},
35056         {"cvmx_pcierc#_cfg072"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1534,   1,      3020},
35057         {"cvmx_pcierc#_cfg073"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1536,   1,      3021},
35058         {"cvmx_pcierc#_cfg074"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1538,   1,      3022},
35059         {"cvmx_pcierc#_cfg075"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1540,   4,      3023},
35060         {"cvmx_pcierc#_cfg076"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1542,   9,      3027},
35061         {"cvmx_pcierc#_cfg077"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1544,   2,      3036},
35062         {"cvmx_pcierc#_cfg448"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1546,   2,      3038},
35063         {"cvmx_pcierc#_cfg449"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1548,   1,      3040},
35064         {"cvmx_pcierc#_cfg450"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1550,   6,      3041},
35065         {"cvmx_pcierc#_cfg451"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1552,   6,      3047},
35066         {"cvmx_pcierc#_cfg452"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1554,   13,     3053},
35067         {"cvmx_pcierc#_cfg453"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1556,   5,      3066},
35068         {"cvmx_pcierc#_cfg454"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1558,   8,      3071},
35069         {"cvmx_pcierc#_cfg455"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1560,   19,     3079},
35070         {"cvmx_pcierc#_cfg456"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1562,   3,      3098},
35071         {"cvmx_pcierc#_cfg458"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1564,   1,      3101},
35072         {"cvmx_pcierc#_cfg459"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1566,   1,      3102},
35073         {"cvmx_pcierc#_cfg460"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1568,   3,      3103},
35074         {"cvmx_pcierc#_cfg461"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1570,   3,      3106},
35075         {"cvmx_pcierc#_cfg462"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1572,   3,      3109},
35076         {"cvmx_pcierc#_cfg463"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1574,   4,      3112},
35077         {"cvmx_pcierc#_cfg464"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1576,   4,      3116},
35078         {"cvmx_pcierc#_cfg465"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1578,   4,      3120},
35079         {"cvmx_pcierc#_cfg466"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1580,   7,      3124},
35080         {"cvmx_pcierc#_cfg467"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1582,   5,      3131},
35081         {"cvmx_pcierc#_cfg468"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1584,   5,      3136},
35082         {"cvmx_pcierc#_cfg490"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1586,   4,      3141},
35083         {"cvmx_pcierc#_cfg491"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1588,   4,      3145},
35084         {"cvmx_pcierc#_cfg492"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1590,   4,      3149},
35085         {"cvmx_pcierc#_cfg516"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1592,   1,      3153},
35086         {"cvmx_pcierc#_cfg517"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1594,   1,      3154},
35087         {"cvmx_pcs#_an#_adv_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1596,   9,      3155},
35088         {"cvmx_pcs#_an#_ext_st_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1604,   6,      3164},
35089         {"cvmx_pcs#_an#_lp_abil_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1612,   9,      3170},
35090         {"cvmx_pcs#_an#_results_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1620,   6,      3179},
35091         {"cvmx_pcs#_int#_en_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1628,   13,     3185},
35092         {"cvmx_pcs#_int#_reg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1636,   13,     3198},
35093         {"cvmx_pcs#_link#_timer_count_reg",     CVMX_CSR_DB_TYPE_RSL,   64,     1644,   2,      3211},
35094         {"cvmx_pcs#_log_anl#_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1652,   4,      3213},
35095         {"cvmx_pcs#_misc#_ctl_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1660,   8,      3217},
35096         {"cvmx_pcs#_mr#_control_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1668,   13,     3225},
35097         {"cvmx_pcs#_mr#_status_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1676,   17,     3238},
35098         {"cvmx_pcs#_rx#_states_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1684,   7,      3255},
35099         {"cvmx_pcs#_rx#_sync_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1692,   3,      3262},
35100         {"cvmx_pcs#_sgm#_an_adv_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1700,   8,      3265},
35101         {"cvmx_pcs#_sgm#_lp_adv_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1708,   7,      3273},
35102         {"cvmx_pcs#_tx#_states_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1716,   4,      3280},
35103         {"cvmx_pcs#_tx_rx#_polarity_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     1724,   5,      3284},
35104         {"cvmx_pcsx#_10gbx_status_reg" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1732,   8,      3289},
35105         {"cvmx_pcsx#_bist_status_reg"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1734,   2,      3297},
35106         {"cvmx_pcsx#_bit_lock_status_reg",      CVMX_CSR_DB_TYPE_RSL,   64,     1736,   5,      3299},
35107         {"cvmx_pcsx#_control1_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1738,   10,     3304},
35108         {"cvmx_pcsx#_control2_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1740,   2,      3314},
35109         {"cvmx_pcsx#_int_en_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1742,   7,      3316},
35110         {"cvmx_pcsx#_int_reg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1744,   7,      3323},
35111         {"cvmx_pcsx#_log_anl_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1746,   6,      3330},
35112         {"cvmx_pcsx#_misc_ctl_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1748,   5,      3336},
35113         {"cvmx_pcsx#_rx_sync_states_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     1750,   5,      3341},
35114         {"cvmx_pcsx#_spd_abil_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1752,   3,      3346},
35115         {"cvmx_pcsx#_status1_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1754,   6,      3349},
35116         {"cvmx_pcsx#_status2_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1756,   9,      3355},
35117         {"cvmx_pcsx#_tx_rx_polarity_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     1758,   3,      3364},
35118         {"cvmx_pcsx#_tx_rx_states_reg" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1760,   9,      3367},
35119         {"cvmx_pesc#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1762,   13,     3376},
35120         {"cvmx_pesc#_bist_status2"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1764,   15,     3389},
35121         {"cvmx_pesc#_cfg_rd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1766,   2,      3404},
35122         {"cvmx_pesc#_cfg_wr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1768,   2,      3406},
35123         {"cvmx_pesc#_cpl_lut_valid"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1770,   2,      3408},
35124         {"cvmx_pesc#_ctl_status"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1772,   16,     3410},
35125         {"cvmx_pesc#_ctl_status2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1774,   2,      3426},
35126         {"cvmx_pesc#_dbg_info"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1776,   32,     3428},
35127         {"cvmx_pesc#_dbg_info_en"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1778,   32,     3460},
35128         {"cvmx_pesc#_diag_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1780,   5,      3492},
35129         {"cvmx_pesc#_p2n_bar0_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1782,   2,      3497},
35130         {"cvmx_pesc#_p2n_bar1_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1784,   2,      3499},
35131         {"cvmx_pesc#_p2n_bar2_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1786,   2,      3501},
35132         {"cvmx_pesc#_p2p_bar#_end"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1788,   2,      3503},
35133         {"cvmx_pesc#_p2p_bar#_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1796,   2,      3505},
35134         {"cvmx_pesc#_tlp_credits"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1804,   8,      3507},
35135         {"cvmx_pip_bck_prs"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1806,   5,      3515},
35136         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1807,   2,      3520},
35137         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1808,   4,      3522},
35138         {"cvmx_pip_frm_len_chk#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1812,   3,      3526},
35139         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1814,   8,      3529},
35140         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1815,   18,     3537},
35141         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1816,   13,     3555},
35142         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1817,   13,     3568},
35143         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1818,   2,      3581},
35144         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1819,   27,     3583},
35145         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1831,   25,     3610},
35146         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1843,   2,      3635},
35147         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1907,   2,      3637},
35148         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1915,   9,      3639},
35149         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1923,   2,      3648},
35150         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1924,   2,      3650},
35151         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1925,   2,      3652},
35152         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1937,   2,      3654},
35153         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1949,   2,      3656},
35154         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1961,   2,      3658},
35155         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1973,   2,      3660},
35156         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1985,   2,      3662},
35157         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1997,   2,      3664},
35158         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2009,   2,      3666},
35159         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2021,   2,      3668},
35160         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2033,   2,      3670},
35161         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2045,   2,      3672},
35162         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2046,   2,      3674},
35163         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2058,   2,      3676},
35164         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2070,   2,      3678},
35165         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2082,   2,      3680},
35166         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2146,   2,      3682},
35167         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2147,   3,      3684},
35168         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2148,   3,      3687},
35169         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2149,   2,      3690},
35170         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2150,   2,      3692},
35171         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2151,   4,      3694},
35172         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2152,   5,      3698},
35173         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2153,   4,      3703},
35174         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2154,   8,      3707},
35175         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2155,   4,      3715},
35176         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2156,   5,      3719},
35177         {"cvmx_pko_mem_debug14"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2157,   1,      3724},
35178         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2158,   5,      3725},
35179         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2159,   1,      3730},
35180         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2160,   13,     3731},
35181         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2161,   4,      3744},
35182         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2162,   13,     3748},
35183         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2163,   6,      3761},
35184         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2164,   9,      3767},
35185         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2165,   4,      3776},
35186         {"cvmx_pko_mem_port_ptrs"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2166,   7,      3780},
35187         {"cvmx_pko_mem_port_qos"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2167,   5,      3787},
35188         {"cvmx_pko_mem_port_rate0"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2168,   5,      3792},
35189         {"cvmx_pko_mem_port_rate1"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2169,   4,      3797},
35190         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2170,   9,      3801},
35191         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2171,   5,      3810},
35192         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2172,   16,     3815},
35193         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2173,   4,      3831},
35194         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2174,   1,      3835},
35195         {"cvmx_pko_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2175,   1,      3836},
35196         {"cvmx_pko_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2176,   1,      3837},
35197         {"cvmx_pko_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2177,   1,      3838},
35198         {"cvmx_pko_reg_engine_inflight",        CVMX_CSR_DB_TYPE_RSL,   64,     2178,   11,     3839},
35199         {"cvmx_pko_reg_engine_thresh"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2179,   2,      3850},
35200         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2180,   4,      3852},
35201         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2181,   5,      3856},
35202         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2182,   3,      3861},
35203         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2183,   4,      3864},
35204         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2184,   2,      3868},
35205         {"cvmx_pko_reg_queue_ptrs1"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2185,   3,      3870},
35206         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2186,   3,      3873},
35207         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2187,   13,     3876},
35208         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2188,   2,      3889},
35209         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2189,   13,     3891},
35210         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2190,   3,      3904},
35211         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2191,   2,      3907},
35212         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2199,   2,      3909},
35213         {"cvmx_pow_iq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2200,   2,      3911},
35214         {"cvmx_pow_iq_int_en"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2201,   2,      3913},
35215         {"cvmx_pow_iq_thr#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2202,   2,      3915},
35216         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2210,   2,      3917},
35217         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2211,   2,      3919},
35218         {"cvmx_pow_pf_rst_msk"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2212,   2,      3921},
35219         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2213,   10,     3923},
35220         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2225,   5,      3933},
35221         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2233,   8,      3938},
35222         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2241,   2,      3946},
35223         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2242,   2,      3948},
35224         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2243,   2,      3950},
35225         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2251,   3,      3952},
35226         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2252,   4,      3955},
35227         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2268,   5,      3959},
35228         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2269,   7,      3964},
35229         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2285,   2,      3971},
35230         {"cvmx_rad_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2301,   1,      3973},
35231         {"cvmx_rad_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2302,   1,      3974},
35232         {"cvmx_rad_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2303,   1,      3975},
35233         {"cvmx_rad_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2304,   5,      3976},
35234         {"cvmx_rad_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2305,   5,      3981},
35235         {"cvmx_rad_reg_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2306,   4,      3986},
35236         {"cvmx_rad_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2307,   10,     3990},
35237         {"cvmx_rad_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2308,   1,      4000},
35238         {"cvmx_rad_reg_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2309,   3,      4001},
35239         {"cvmx_rad_reg_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2310,   7,      4004},
35240         {"cvmx_rad_reg_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2311,   2,      4011},
35241         {"cvmx_rad_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2312,   1,      4013},
35242         {"cvmx_rad_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2313,   1,      4014},
35243         {"cvmx_rad_reg_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2314,   1,      4015},
35244         {"cvmx_rad_reg_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2315,   18,     4016},
35245         {"cvmx_rad_reg_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2316,   3,      4034},
35246         {"cvmx_rad_reg_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2317,   2,      4037},
35247         {"cvmx_rad_reg_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2318,   3,      4039},
35248         {"cvmx_rad_reg_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2319,   7,      4042},
35249         {"cvmx_rad_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2320,   2,      4049},
35250         {"cvmx_rad_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2321,   2,      4051},
35251         {"cvmx_rad_reg_polynomial"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2322,   2,      4053},
35252         {"cvmx_rad_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2323,   3,      4055},
35253         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2324,   3,      4058},
35254         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2325,   7,      4061},
35255         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2326,   10,     4068},
35256         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2328,   6,      4078},
35257         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2330,   2,      4084},
35258         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2332,   4,      4086},
35259         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2334,   4,      4090},
35260         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2336,   6,      4094},
35261         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2337,   3,      4100},
35262         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2338,   5,      4103},
35263         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2339,   4,      4108},
35264         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2340,   6,      4112},
35265         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2341,   4,      4118},
35266         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2342,   2,      4122},
35267         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2343,   4,      4124},
35268         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2344,   2,      4128},
35269         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2345,   3,      4130},
35270         {"cvmx_tra_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2346,   4,      4133},
35271         {"cvmx_tra_ctl"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2347,   12,     4137},
35272         {"cvmx_tra_cycles_since"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2348,   3,      4149},
35273         {"cvmx_tra_cycles_since1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2349,   5,      4152},
35274         {"cvmx_tra_filt_adr_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2350,   2,      4157},
35275         {"cvmx_tra_filt_adr_msk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2351,   2,      4159},
35276         {"cvmx_tra_filt_cmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2352,   18,     4161},
35277         {"cvmx_tra_filt_did"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2353,   12,     4179},
35278         {"cvmx_tra_filt_sid"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2354,   6,      4191},
35279         {"cvmx_tra_int_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2355,   5,      4197},
35280         {"cvmx_tra_read_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2356,   1,      4202},
35281         {"cvmx_tra_trig0_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2357,   2,      4203},
35282         {"cvmx_tra_trig0_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2358,   2,      4205},
35283         {"cvmx_tra_trig0_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2359,   18,     4207},
35284         {"cvmx_tra_trig0_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2360,   12,     4225},
35285         {"cvmx_tra_trig0_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2361,   6,      4237},
35286         {"cvmx_tra_trig1_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2362,   2,      4243},
35287         {"cvmx_tra_trig1_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2363,   2,      4245},
35288         {"cvmx_tra_trig1_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2364,   18,     4247},
35289         {"cvmx_tra_trig1_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2365,   12,     4265},
35290         {"cvmx_tra_trig1_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2366,   6,      4277},
35291         {"cvmx_usbc#_daint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     2367,   2,      4283},
35292         {"cvmx_usbc#_daintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2368,   2,      4285},
35293         {"cvmx_usbc#_dcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2369,   8,      4287},
35294         {"cvmx_usbc#_dctl"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2370,   11,     4295},
35295         {"cvmx_usbc#_diepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2371,   15,     4306},
35296         {"cvmx_usbc#_diepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2376,   8,      4321},
35297         {"cvmx_usbc#_diepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2381,   8,      4329},
35298         {"cvmx_usbc#_dieptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2382,   4,      4337},
35299         {"cvmx_usbc#_doepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2387,   15,     4341},
35300         {"cvmx_usbc#_doepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2392,   6,      4356},
35301         {"cvmx_usbc#_doepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2397,   6,      4362},
35302         {"cvmx_usbc#_doeptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2398,   4,      4368},
35303         {"cvmx_usbc#_dptxfsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2403,   2,      4372},
35304         {"cvmx_usbc#_dsts"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2407,   6,      4374},
35305         {"cvmx_usbc#_dtknqr1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2408,   4,      4380},
35306         {"cvmx_usbc#_dtknqr2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2409,   1,      4384},
35307         {"cvmx_usbc#_dtknqr3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2410,   1,      4385},
35308         {"cvmx_usbc#_dtknqr4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2411,   1,      4386},
35309         {"cvmx_usbc#_gahbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2412,   7,      4387},
35310         {"cvmx_usbc#_ghwcfg1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2413,   1,      4394},
35311         {"cvmx_usbc#_ghwcfg2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2414,   14,     4395},
35312         {"cvmx_usbc#_ghwcfg3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2415,   10,     4409},
35313         {"cvmx_usbc#_ghwcfg4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2416,   14,     4419},
35314         {"cvmx_usbc#_gintmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2417,   32,     4433},
35315         {"cvmx_usbc#_gintsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2418,   32,     4465},
35316         {"cvmx_usbc#_gnptxfsiz"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2419,   2,      4497},
35317         {"cvmx_usbc#_gnptxsts"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2420,   4,      4499},
35318         {"cvmx_usbc#_gotgctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2421,   13,     4503},
35319         {"cvmx_usbc#_gotgint"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2422,   10,     4516},
35320         {"cvmx_usbc#_grstctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2423,   10,     4526},
35321         {"cvmx_usbc#_grxfsiz"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2424,   2,      4536},
35322         {"cvmx_usbc#_grxstspd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2425,   6,      4538},
35323         {"cvmx_usbc#_grxstsph"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2426,   5,      4544},
35324         {"cvmx_usbc#_grxstsrd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2427,   6,      4549},
35325         {"cvmx_usbc#_grxstsrh"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2428,   5,      4555},
35326         {"cvmx_usbc#_gsnpsid"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2429,   1,      4560},
35327         {"cvmx_usbc#_gusbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2430,   13,     4561},
35328         {"cvmx_usbc#_haint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     2431,   2,      4574},
35329         {"cvmx_usbc#_haintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2432,   2,      4576},
35330         {"cvmx_usbc#_hcchar#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2433,   11,     4578},
35331         {"cvmx_usbc#_hcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2441,   3,      4589},
35332         {"cvmx_usbc#_hcint#"           ,        CVMX_CSR_DB_TYPE_NCB,   32,     2442,   12,     4592},
35333         {"cvmx_usbc#_hcintmsk#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2450,   12,     4604},
35334         {"cvmx_usbc#_hcsplt#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2458,   6,      4616},
35335         {"cvmx_usbc#_hctsiz#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2466,   4,      4622},
35336         {"cvmx_usbc#_hfir"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2474,   2,      4626},
35337         {"cvmx_usbc#_hfnum"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     2475,   2,      4628},
35338         {"cvmx_usbc#_hprt"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2476,   15,     4630},
35339         {"cvmx_usbc#_hptxfsiz"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2477,   2,      4645},
35340         {"cvmx_usbc#_hptxsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2478,   3,      4647},
35341         {"cvmx_usbc#_nptxdfifo#"       ,        CVMX_CSR_DB_TYPE_NCB,   32,     2479,   1,      4650},
35342         {"cvmx_usbc#_pcgcctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2487,   6,      4651},
35343         {"cvmx_usbn#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2488,   8,      4657},
35344         {"cvmx_usbn#_clk_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2489,   15,     4665},
35345         {"cvmx_usbn#_ctl_status"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     2490,   6,      4680},
35346         {"cvmx_usbn#_dma0_inb_chn0"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2491,   2,      4686},
35347         {"cvmx_usbn#_dma0_inb_chn1"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2492,   2,      4688},
35348         {"cvmx_usbn#_dma0_inb_chn2"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2493,   2,      4690},
35349         {"cvmx_usbn#_dma0_inb_chn3"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2494,   2,      4692},
35350         {"cvmx_usbn#_dma0_inb_chn4"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2495,   2,      4694},
35351         {"cvmx_usbn#_dma0_inb_chn5"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2496,   2,      4696},
35352         {"cvmx_usbn#_dma0_inb_chn6"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2497,   2,      4698},
35353         {"cvmx_usbn#_dma0_inb_chn7"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2498,   2,      4700},
35354         {"cvmx_usbn#_dma0_outb_chn0"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2499,   2,      4702},
35355         {"cvmx_usbn#_dma0_outb_chn1"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2500,   2,      4704},
35356         {"cvmx_usbn#_dma0_outb_chn2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2501,   2,      4706},
35357         {"cvmx_usbn#_dma0_outb_chn3"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2502,   2,      4708},
35358         {"cvmx_usbn#_dma0_outb_chn4"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2503,   2,      4710},
35359         {"cvmx_usbn#_dma0_outb_chn5"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2504,   2,      4712},
35360         {"cvmx_usbn#_dma0_outb_chn6"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2505,   2,      4714},
35361         {"cvmx_usbn#_dma0_outb_chn7"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2506,   2,      4716},
35362         {"cvmx_usbn#_dma_test"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2507,   7,      4718},
35363         {"cvmx_usbn#_int_enb"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2508,   34,     4725},
35364         {"cvmx_usbn#_int_sum"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2509,   34,     4759},
35365         {"cvmx_usbn#_usbp_ctl_status"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2510,   35,     4793},
35366         {"cvmx_zip_cmd_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2511,   3,      4828},
35367         {"cvmx_zip_cmd_buf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2512,   5,      4831},
35368         {"cvmx_zip_cmd_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2513,   3,      4836},
35369         {"cvmx_zip_constants"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2514,   6,      4839},
35370         {"cvmx_zip_debug0"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     2515,   2,      4845},
35371         {"cvmx_zip_error"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     2516,   2,      4847},
35372         {"cvmx_zip_int_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2517,   2,      4849},
35373         {NULL,0,0,0,0,0}
35374 };
35375 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xxp1[] = {
35376         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
35377         {"AGL_GMX_BAD_REG"             ,           0x11800E0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
35378         {"AGL_GMX_BIST"                ,           0x11800E0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
35379         {"AGL_GMX_DRV_CTL"             ,           0x11800E00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
35380         {"AGL_GMX_INF_MODE"            ,           0x11800E00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
35381         {"AGL_GMX_PRT0_CFG"            ,           0x11800E0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
35382         {"AGL_GMX_RX0_ADR_CAM0"        ,           0x11800E0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
35383         {"AGL_GMX_RX0_ADR_CAM1"        ,           0x11800E0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
35384         {"AGL_GMX_RX0_ADR_CAM2"        ,           0x11800E0000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
35385         {"AGL_GMX_RX0_ADR_CAM3"        ,           0x11800E0000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
35386         {"AGL_GMX_RX0_ADR_CAM4"        ,           0x11800E00001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
35387         {"AGL_GMX_RX0_ADR_CAM5"        ,           0x11800E00001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
35388         {"AGL_GMX_RX0_ADR_CAM_EN"      ,           0x11800E0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
35389         {"AGL_GMX_RX0_ADR_CTL"         ,           0x11800E0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
35390         {"AGL_GMX_RX0_DECISION"        ,           0x11800E0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
35391         {"AGL_GMX_RX0_FRM_CHK"         ,           0x11800E0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
35392         {"AGL_GMX_RX0_FRM_CTL"         ,           0x11800E0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
35393         {"AGL_GMX_RX0_FRM_MAX"         ,           0x11800E0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
35394         {"AGL_GMX_RX0_FRM_MIN"         ,           0x11800E0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
35395         {"AGL_GMX_RX0_IFG"             ,           0x11800E0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
35396         {"AGL_GMX_RX0_INT_EN"          ,           0x11800E0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
35397         {"AGL_GMX_RX0_INT_REG"         ,           0x11800E0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
35398         {"AGL_GMX_RX0_JABBER"          ,           0x11800E0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
35399         {"AGL_GMX_RX0_PAUSE_DROP_TIME" ,           0x11800E0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
35400         {"AGL_GMX_RX0_STATS_CTL"       ,           0x11800E0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     23},
35401         {"AGL_GMX_RX0_STATS_OCTS"      ,           0x11800E0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     24},
35402         {"AGL_GMX_RX0_STATS_OCTS_CTL"  ,           0x11800E0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     25},
35403         {"AGL_GMX_RX0_STATS_OCTS_DMAC" ,           0x11800E00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     26},
35404         {"AGL_GMX_RX0_STATS_OCTS_DRP"  ,           0x11800E00000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     27},
35405         {"AGL_GMX_RX0_STATS_PKTS"      ,           0x11800E0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     28},
35406         {"AGL_GMX_RX0_STATS_PKTS_BAD"  ,           0x11800E00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     29},
35407         {"AGL_GMX_RX0_STATS_PKTS_CTL"  ,           0x11800E0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     30},
35408         {"AGL_GMX_RX0_STATS_PKTS_DMAC" ,           0x11800E00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     31},
35409         {"AGL_GMX_RX0_STATS_PKTS_DRP"  ,           0x11800E00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     32},
35410         {"AGL_GMX_RX0_UDD_SKP"         ,           0x11800E0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     33},
35411         {"AGL_GMX_RX_BP_DROP0"         ,           0x11800E0000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     34},
35412         {"AGL_GMX_RX_BP_OFF0"          ,           0x11800E0000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     35},
35413         {"AGL_GMX_RX_BP_ON0"           ,           0x11800E0000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     36},
35414         {"AGL_GMX_RX_PRT_INFO"         ,           0x11800E00004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
35415         {"AGL_GMX_RX_TX_STATUS"        ,           0x11800E00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
35416         {"AGL_GMX_SMAC0"               ,           0x11800E0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     39},
35417         {"AGL_GMX_STAT_BP"             ,           0x11800E0000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
35418         {"AGL_GMX_TX0_APPEND"          ,           0x11800E0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
35419         {"AGL_GMX_TX0_CTL"             ,           0x11800E0000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     42},
35420         {"AGL_GMX_TX0_MIN_PKT"         ,           0x11800E0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     43},
35421         {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",         0x11800E0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
35422         {"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,           0x11800E0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     45},
35423         {"AGL_GMX_TX0_PAUSE_TOGO"      ,           0x11800E0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
35424         {"AGL_GMX_TX0_PAUSE_ZERO"      ,           0x11800E0000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
35425         {"AGL_GMX_TX0_SOFT_PAUSE"      ,           0x11800E0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
35426         {"AGL_GMX_TX0_STAT0"           ,           0x11800E0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
35427         {"AGL_GMX_TX0_STAT1"           ,           0x11800E0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
35428         {"AGL_GMX_TX0_STAT2"           ,           0x11800E0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
35429         {"AGL_GMX_TX0_STAT3"           ,           0x11800E0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
35430         {"AGL_GMX_TX0_STAT4"           ,           0x11800E00002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
35431         {"AGL_GMX_TX0_STAT5"           ,           0x11800E00002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
35432         {"AGL_GMX_TX0_STAT6"           ,           0x11800E00002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
35433         {"AGL_GMX_TX0_STAT7"           ,           0x11800E00002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
35434         {"AGL_GMX_TX0_STAT8"           ,           0x11800E00002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
35435         {"AGL_GMX_TX0_STAT9"           ,           0x11800E00002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
35436         {"AGL_GMX_TX0_STATS_CTL"       ,           0x11800E0000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
35437         {"AGL_GMX_TX0_THRESH"          ,           0x11800E0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
35438         {"AGL_GMX_TX_BP"               ,           0x11800E00004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
35439         {"AGL_GMX_TX_COL_ATTEMPT"      ,           0x11800E0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
35440         {"AGL_GMX_TX_IFG"              ,           0x11800E0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
35441         {"AGL_GMX_TX_INT_EN"           ,           0x11800E0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
35442         {"AGL_GMX_TX_INT_REG"          ,           0x11800E0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
35443         {"AGL_GMX_TX_JAM"              ,           0x11800E0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
35444         {"AGL_GMX_TX_LFSR"             ,           0x11800E00004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
35445         {"AGL_GMX_TX_OVR_BP"           ,           0x11800E00004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
35446         {"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,           0x11800E00004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
35447         {"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,           0x11800E00004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
35448         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     71},
35449         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     72},
35450         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     73},
35451         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     74},
35452         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35453         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35454         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35455         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35456         {"CIU_INT4_EN0"                ,           0x1070000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35457         {"CIU_INT5_EN0"                ,           0x1070000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35458         {"CIU_INT6_EN0"                ,           0x1070000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35459         {"CIU_INT7_EN0"                ,           0x1070000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35460         {"CIU_INT8_EN0"                ,           0x1070000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35461         {"CIU_INT9_EN0"                ,           0x1070000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35462         {"CIU_INT10_EN0"               ,           0x10700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35463         {"CIU_INT11_EN0"               ,           0x10700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35464         {"CIU_INT12_EN0"               ,           0x10700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35465         {"CIU_INT13_EN0"               ,           0x10700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35466         {"CIU_INT14_EN0"               ,           0x10700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35467         {"CIU_INT15_EN0"               ,           0x10700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35468         {"CIU_INT16_EN0"               ,           0x1070000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35469         {"CIU_INT17_EN0"               ,           0x1070000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35470         {"CIU_INT18_EN0"               ,           0x1070000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35471         {"CIU_INT19_EN0"               ,           0x1070000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35472         {"CIU_INT20_EN0"               ,           0x1070000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35473         {"CIU_INT21_EN0"               ,           0x1070000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35474         {"CIU_INT22_EN0"               ,           0x1070000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35475         {"CIU_INT23_EN0"               ,           0x1070000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35476         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
35477         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35478         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35479         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35480         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35481         {"CIU_INT4_EN1"                ,           0x1070000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35482         {"CIU_INT5_EN1"                ,           0x1070000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35483         {"CIU_INT6_EN1"                ,           0x1070000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35484         {"CIU_INT7_EN1"                ,           0x1070000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35485         {"CIU_INT8_EN1"                ,           0x1070000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35486         {"CIU_INT9_EN1"                ,           0x1070000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35487         {"CIU_INT10_EN1"               ,           0x10700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35488         {"CIU_INT11_EN1"               ,           0x10700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35489         {"CIU_INT12_EN1"               ,           0x10700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35490         {"CIU_INT13_EN1"               ,           0x10700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35491         {"CIU_INT14_EN1"               ,           0x10700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35492         {"CIU_INT15_EN1"               ,           0x10700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35493         {"CIU_INT16_EN1"               ,           0x1070000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35494         {"CIU_INT17_EN1"               ,           0x1070000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35495         {"CIU_INT18_EN1"               ,           0x1070000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35496         {"CIU_INT19_EN1"               ,           0x1070000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35497         {"CIU_INT20_EN1"               ,           0x1070000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35498         {"CIU_INT21_EN1"               ,           0x1070000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35499         {"CIU_INT22_EN1"               ,           0x1070000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35500         {"CIU_INT23_EN1"               ,           0x1070000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35501         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
35502         {"CIU_INT0_EN4_0"              ,           0x1070000000C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35503         {"CIU_INT1_EN4_0"              ,           0x1070000000C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35504         {"CIU_INT2_EN4_0"              ,           0x1070000000CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35505         {"CIU_INT3_EN4_0"              ,           0x1070000000CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35506         {"CIU_INT4_EN4_0"              ,           0x1070000000CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35507         {"CIU_INT5_EN4_0"              ,           0x1070000000CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35508         {"CIU_INT6_EN4_0"              ,           0x1070000000CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35509         {"CIU_INT7_EN4_0"              ,           0x1070000000CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35510         {"CIU_INT8_EN4_0"              ,           0x1070000000D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35511         {"CIU_INT9_EN4_0"              ,           0x1070000000D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35512         {"CIU_INT10_EN4_0"             ,           0x1070000000D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35513         {"CIU_INT11_EN4_0"             ,           0x1070000000D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
35514         {"CIU_INT0_EN4_1"              ,           0x1070000000C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35515         {"CIU_INT1_EN4_1"              ,           0x1070000000C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35516         {"CIU_INT2_EN4_1"              ,           0x1070000000CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35517         {"CIU_INT3_EN4_1"              ,           0x1070000000CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35518         {"CIU_INT4_EN4_1"              ,           0x1070000000CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35519         {"CIU_INT5_EN4_1"              ,           0x1070000000CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35520         {"CIU_INT6_EN4_1"              ,           0x1070000000CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35521         {"CIU_INT7_EN4_1"              ,           0x1070000000CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35522         {"CIU_INT8_EN4_1"              ,           0x1070000000D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35523         {"CIU_INT9_EN4_1"              ,           0x1070000000D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35524         {"CIU_INT10_EN4_1"             ,           0x1070000000D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35525         {"CIU_INT11_EN4_1"             ,           0x1070000000D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
35526         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35527         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35528         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35529         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35530         {"CIU_INT4_SUM0"               ,           0x1070000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35531         {"CIU_INT5_SUM0"               ,           0x1070000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35532         {"CIU_INT6_SUM0"               ,           0x1070000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35533         {"CIU_INT7_SUM0"               ,           0x1070000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35534         {"CIU_INT8_SUM0"               ,           0x1070000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35535         {"CIU_INT9_SUM0"               ,           0x1070000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35536         {"CIU_INT10_SUM0"              ,           0x1070000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35537         {"CIU_INT11_SUM0"              ,           0x1070000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35538         {"CIU_INT12_SUM0"              ,           0x1070000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35539         {"CIU_INT13_SUM0"              ,           0x1070000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35540         {"CIU_INT14_SUM0"              ,           0x1070000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35541         {"CIU_INT15_SUM0"              ,           0x1070000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35542         {"CIU_INT16_SUM0"              ,           0x1070000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35543         {"CIU_INT17_SUM0"              ,           0x1070000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35544         {"CIU_INT18_SUM0"              ,           0x1070000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35545         {"CIU_INT19_SUM0"              ,           0x1070000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35546         {"CIU_INT20_SUM0"              ,           0x10700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35547         {"CIU_INT21_SUM0"              ,           0x10700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35548         {"CIU_INT22_SUM0"              ,           0x10700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35549         {"CIU_INT23_SUM0"              ,           0x10700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35550         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
35551         {"CIU_INT0_SUM4"               ,           0x1070000000C00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35552         {"CIU_INT1_SUM4"               ,           0x1070000000C08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35553         {"CIU_INT2_SUM4"               ,           0x1070000000C10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35554         {"CIU_INT3_SUM4"               ,           0x1070000000C18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35555         {"CIU_INT4_SUM4"               ,           0x1070000000C20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35556         {"CIU_INT5_SUM4"               ,           0x1070000000C28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35557         {"CIU_INT6_SUM4"               ,           0x1070000000C30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35558         {"CIU_INT7_SUM4"               ,           0x1070000000C38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35559         {"CIU_INT8_SUM4"               ,           0x1070000000C40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35560         {"CIU_INT9_SUM4"               ,           0x1070000000C48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35561         {"CIU_INT10_SUM4"              ,           0x1070000000C50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35562         {"CIU_INT11_SUM4"              ,           0x1070000000C58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
35563         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
35564         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35565         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35566         {"CIU_MBOX_CLR2"               ,           0x1070000000690ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35567         {"CIU_MBOX_CLR3"               ,           0x1070000000698ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35568         {"CIU_MBOX_CLR4"               ,           0x10700000006A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35569         {"CIU_MBOX_CLR5"               ,           0x10700000006A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35570         {"CIU_MBOX_CLR6"               ,           0x10700000006B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35571         {"CIU_MBOX_CLR7"               ,           0x10700000006B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35572         {"CIU_MBOX_CLR8"               ,           0x10700000006C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35573         {"CIU_MBOX_CLR9"               ,           0x10700000006C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35574         {"CIU_MBOX_CLR10"              ,           0x10700000006D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35575         {"CIU_MBOX_CLR11"              ,           0x10700000006D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
35576         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35577         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35578         {"CIU_MBOX_SET2"               ,           0x1070000000610ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35579         {"CIU_MBOX_SET3"               ,           0x1070000000618ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35580         {"CIU_MBOX_SET4"               ,           0x1070000000620ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35581         {"CIU_MBOX_SET5"               ,           0x1070000000628ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35582         {"CIU_MBOX_SET6"               ,           0x1070000000630ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35583         {"CIU_MBOX_SET7"               ,           0x1070000000638ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35584         {"CIU_MBOX_SET8"               ,           0x1070000000640ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35585         {"CIU_MBOX_SET9"               ,           0x1070000000648ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35586         {"CIU_MBOX_SET10"              ,           0x1070000000650ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35587         {"CIU_MBOX_SET11"              ,           0x1070000000658ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
35588         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
35589         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
35590         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
35591         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35592         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35593         {"CIU_PP_POKE2"                ,           0x1070000000590ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35594         {"CIU_PP_POKE3"                ,           0x1070000000598ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35595         {"CIU_PP_POKE4"                ,           0x10700000005A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35596         {"CIU_PP_POKE5"                ,           0x10700000005A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35597         {"CIU_PP_POKE6"                ,           0x10700000005B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35598         {"CIU_PP_POKE7"                ,           0x10700000005B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35599         {"CIU_PP_POKE8"                ,           0x10700000005C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35600         {"CIU_PP_POKE9"                ,           0x10700000005C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35601         {"CIU_PP_POKE10"               ,           0x10700000005D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35602         {"CIU_PP_POKE11"               ,           0x10700000005D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
35603         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
35604         {"CIU_QLM_DCOK"                ,           0x1070000000760ull,  CVMX_CSR_DB_TYPE_NCB,   64,     89},
35605         {"CIU_QLM_JTGC"                ,           0x1070000000768ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
35606         {"CIU_QLM_JTGD"                ,           0x1070000000770ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
35607         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     92},
35608         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     93},
35609         {"CIU_SOFT_PRST1"              ,           0x1070000000758ull,  CVMX_CSR_DB_TYPE_NCB,   64,     94},
35610         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
35611         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
35612         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
35613         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
35614         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
35615         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35616         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35617         {"CIU_WDOG2"                   ,           0x1070000000510ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35618         {"CIU_WDOG3"                   ,           0x1070000000518ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35619         {"CIU_WDOG4"                   ,           0x1070000000520ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35620         {"CIU_WDOG5"                   ,           0x1070000000528ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35621         {"CIU_WDOG6"                   ,           0x1070000000530ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35622         {"CIU_WDOG7"                   ,           0x1070000000538ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35623         {"CIU_WDOG8"                   ,           0x1070000000540ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35624         {"CIU_WDOG9"                   ,           0x1070000000548ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35625         {"CIU_WDOG10"                  ,           0x1070000000550ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35626         {"CIU_WDOG11"                  ,           0x1070000000558ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
35627         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
35628         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
35629         {"FPA_FPF1_MARKS"              ,           0x1180028000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
35630         {"FPA_FPF2_MARKS"              ,           0x1180028000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
35631         {"FPA_FPF3_MARKS"              ,           0x1180028000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
35632         {"FPA_FPF4_MARKS"              ,           0x1180028000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
35633         {"FPA_FPF5_MARKS"              ,           0x1180028000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
35634         {"FPA_FPF6_MARKS"              ,           0x1180028000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
35635         {"FPA_FPF7_MARKS"              ,           0x1180028000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
35636         {"FPA_FPF1_SIZE"               ,           0x1180028000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
35637         {"FPA_FPF2_SIZE"               ,           0x1180028000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
35638         {"FPA_FPF3_SIZE"               ,           0x1180028000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
35639         {"FPA_FPF4_SIZE"               ,           0x1180028000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
35640         {"FPA_FPF5_SIZE"               ,           0x1180028000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
35641         {"FPA_FPF6_SIZE"               ,           0x1180028000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
35642         {"FPA_FPF7_SIZE"               ,           0x1180028000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
35643         {"FPA_FPF0_MARKS"              ,           0x1180028000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
35644         {"FPA_FPF0_SIZE"               ,           0x1180028000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
35645         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
35646         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
35647         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
35648         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
35649         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
35650         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
35651         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
35652         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
35653         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
35654         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
35655         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
35656         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
35657         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
35658         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
35659         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
35660         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
35661         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
35662         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
35663         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
35664         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
35665         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
35666         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
35667         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
35668         {"GMX1_BAD_REG"                ,           0x1180010000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
35669         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
35670         {"GMX1_BIST"                   ,           0x1180010000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
35671         {"GMX0_CLK_EN"                 ,           0x11800080007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
35672         {"GMX1_CLK_EN"                 ,           0x11800100007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
35673         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
35674         {"GMX1_INF_MODE"               ,           0x11800100007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
35675         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
35676         {"GMX1_NXA_ADR"                ,           0x1180010000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
35677         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
35678         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
35679         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
35680         {"GMX0_PRT003_CFG"             ,           0x1180008001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
35681         {"GMX1_PRT000_CFG"             ,           0x1180010000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
35682         {"GMX1_PRT001_CFG"             ,           0x1180010000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
35683         {"GMX1_PRT002_CFG"             ,           0x1180010001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
35684         {"GMX1_PRT003_CFG"             ,           0x1180010001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
35685         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
35686         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
35687         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
35688         {"GMX0_RX003_ADR_CAM0"         ,           0x1180008001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
35689         {"GMX1_RX000_ADR_CAM0"         ,           0x1180010000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
35690         {"GMX1_RX001_ADR_CAM0"         ,           0x1180010000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
35691         {"GMX1_RX002_ADR_CAM0"         ,           0x1180010001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
35692         {"GMX1_RX003_ADR_CAM0"         ,           0x1180010001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
35693         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
35694         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
35695         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
35696         {"GMX0_RX003_ADR_CAM1"         ,           0x1180008001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
35697         {"GMX1_RX000_ADR_CAM1"         ,           0x1180010000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
35698         {"GMX1_RX001_ADR_CAM1"         ,           0x1180010000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
35699         {"GMX1_RX002_ADR_CAM1"         ,           0x1180010001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
35700         {"GMX1_RX003_ADR_CAM1"         ,           0x1180010001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
35701         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
35702         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
35703         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
35704         {"GMX0_RX003_ADR_CAM2"         ,           0x1180008001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
35705         {"GMX1_RX000_ADR_CAM2"         ,           0x1180010000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
35706         {"GMX1_RX001_ADR_CAM2"         ,           0x1180010000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
35707         {"GMX1_RX002_ADR_CAM2"         ,           0x1180010001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
35708         {"GMX1_RX003_ADR_CAM2"         ,           0x1180010001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
35709         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
35710         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
35711         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
35712         {"GMX0_RX003_ADR_CAM3"         ,           0x1180008001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
35713         {"GMX1_RX000_ADR_CAM3"         ,           0x1180010000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
35714         {"GMX1_RX001_ADR_CAM3"         ,           0x1180010000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
35715         {"GMX1_RX002_ADR_CAM3"         ,           0x1180010001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
35716         {"GMX1_RX003_ADR_CAM3"         ,           0x1180010001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
35717         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
35718         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
35719         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
35720         {"GMX0_RX003_ADR_CAM4"         ,           0x11800080019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
35721         {"GMX1_RX000_ADR_CAM4"         ,           0x11800100001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
35722         {"GMX1_RX001_ADR_CAM4"         ,           0x11800100009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
35723         {"GMX1_RX002_ADR_CAM4"         ,           0x11800100011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
35724         {"GMX1_RX003_ADR_CAM4"         ,           0x11800100019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
35725         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
35726         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
35727         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
35728         {"GMX0_RX003_ADR_CAM5"         ,           0x11800080019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
35729         {"GMX1_RX000_ADR_CAM5"         ,           0x11800100001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
35730         {"GMX1_RX001_ADR_CAM5"         ,           0x11800100009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
35731         {"GMX1_RX002_ADR_CAM5"         ,           0x11800100011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
35732         {"GMX1_RX003_ADR_CAM5"         ,           0x11800100019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
35733         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
35734         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
35735         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
35736         {"GMX0_RX003_ADR_CAM_EN"       ,           0x1180008001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
35737         {"GMX1_RX000_ADR_CAM_EN"       ,           0x1180010000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
35738         {"GMX1_RX001_ADR_CAM_EN"       ,           0x1180010000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
35739         {"GMX1_RX002_ADR_CAM_EN"       ,           0x1180010001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
35740         {"GMX1_RX003_ADR_CAM_EN"       ,           0x1180010001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
35741         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
35742         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
35743         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
35744         {"GMX0_RX003_ADR_CTL"          ,           0x1180008001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
35745         {"GMX1_RX000_ADR_CTL"          ,           0x1180010000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
35746         {"GMX1_RX001_ADR_CTL"          ,           0x1180010000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
35747         {"GMX1_RX002_ADR_CTL"          ,           0x1180010001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
35748         {"GMX1_RX003_ADR_CTL"          ,           0x1180010001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
35749         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
35750         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
35751         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
35752         {"GMX0_RX003_DECISION"         ,           0x1180008001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
35753         {"GMX1_RX000_DECISION"         ,           0x1180010000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
35754         {"GMX1_RX001_DECISION"         ,           0x1180010000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
35755         {"GMX1_RX002_DECISION"         ,           0x1180010001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
35756         {"GMX1_RX003_DECISION"         ,           0x1180010001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
35757         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
35758         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
35759         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
35760         {"GMX0_RX003_FRM_CHK"          ,           0x1180008001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
35761         {"GMX1_RX000_FRM_CHK"          ,           0x1180010000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
35762         {"GMX1_RX001_FRM_CHK"          ,           0x1180010000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
35763         {"GMX1_RX002_FRM_CHK"          ,           0x1180010001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
35764         {"GMX1_RX003_FRM_CHK"          ,           0x1180010001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
35765         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
35766         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
35767         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
35768         {"GMX0_RX003_FRM_CTL"          ,           0x1180008001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
35769         {"GMX1_RX000_FRM_CTL"          ,           0x1180010000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
35770         {"GMX1_RX001_FRM_CTL"          ,           0x1180010000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
35771         {"GMX1_RX002_FRM_CTL"          ,           0x1180010001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
35772         {"GMX1_RX003_FRM_CTL"          ,           0x1180010001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
35773         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
35774         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
35775         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
35776         {"GMX0_RX003_IFG"              ,           0x1180008001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
35777         {"GMX1_RX000_IFG"              ,           0x1180010000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
35778         {"GMX1_RX001_IFG"              ,           0x1180010000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
35779         {"GMX1_RX002_IFG"              ,           0x1180010001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
35780         {"GMX1_RX003_IFG"              ,           0x1180010001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
35781         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
35782         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
35783         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
35784         {"GMX0_RX003_INT_EN"           ,           0x1180008001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
35785         {"GMX1_RX000_INT_EN"           ,           0x1180010000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
35786         {"GMX1_RX001_INT_EN"           ,           0x1180010000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
35787         {"GMX1_RX002_INT_EN"           ,           0x1180010001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
35788         {"GMX1_RX003_INT_EN"           ,           0x1180010001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
35789         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
35790         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
35791         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
35792         {"GMX0_RX003_INT_REG"          ,           0x1180008001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
35793         {"GMX1_RX000_INT_REG"          ,           0x1180010000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
35794         {"GMX1_RX001_INT_REG"          ,           0x1180010000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
35795         {"GMX1_RX002_INT_REG"          ,           0x1180010001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
35796         {"GMX1_RX003_INT_REG"          ,           0x1180010001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
35797         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
35798         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
35799         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
35800         {"GMX0_RX003_JABBER"           ,           0x1180008001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
35801         {"GMX1_RX000_JABBER"           ,           0x1180010000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
35802         {"GMX1_RX001_JABBER"           ,           0x1180010000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
35803         {"GMX1_RX002_JABBER"           ,           0x1180010001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
35804         {"GMX1_RX003_JABBER"           ,           0x1180010001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
35805         {"GMX0_RX000_PAUSE_DROP_TIME"  ,           0x1180008000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
35806         {"GMX0_RX001_PAUSE_DROP_TIME"  ,           0x1180008000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
35807         {"GMX0_RX002_PAUSE_DROP_TIME"  ,           0x1180008001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
35808         {"GMX0_RX003_PAUSE_DROP_TIME"  ,           0x1180008001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
35809         {"GMX1_RX000_PAUSE_DROP_TIME"  ,           0x1180010000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
35810         {"GMX1_RX001_PAUSE_DROP_TIME"  ,           0x1180010000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
35811         {"GMX1_RX002_PAUSE_DROP_TIME"  ,           0x1180010001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
35812         {"GMX1_RX003_PAUSE_DROP_TIME"  ,           0x1180010001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
35813         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
35814         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
35815         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
35816         {"GMX0_RX003_STATS_CTL"        ,           0x1180008001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
35817         {"GMX1_RX000_STATS_CTL"        ,           0x1180010000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
35818         {"GMX1_RX001_STATS_CTL"        ,           0x1180010000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
35819         {"GMX1_RX002_STATS_CTL"        ,           0x1180010001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
35820         {"GMX1_RX003_STATS_CTL"        ,           0x1180010001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
35821         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
35822         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
35823         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
35824         {"GMX0_RX003_STATS_OCTS"       ,           0x1180008001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
35825         {"GMX1_RX000_STATS_OCTS"       ,           0x1180010000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
35826         {"GMX1_RX001_STATS_OCTS"       ,           0x1180010000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
35827         {"GMX1_RX002_STATS_OCTS"       ,           0x1180010001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
35828         {"GMX1_RX003_STATS_OCTS"       ,           0x1180010001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
35829         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
35830         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
35831         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
35832         {"GMX0_RX003_STATS_OCTS_CTL"   ,           0x1180008001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
35833         {"GMX1_RX000_STATS_OCTS_CTL"   ,           0x1180010000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
35834         {"GMX1_RX001_STATS_OCTS_CTL"   ,           0x1180010000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
35835         {"GMX1_RX002_STATS_OCTS_CTL"   ,           0x1180010001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
35836         {"GMX1_RX003_STATS_OCTS_CTL"   ,           0x1180010001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
35837         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
35838         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
35839         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
35840         {"GMX0_RX003_STATS_OCTS_DMAC"  ,           0x11800080018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
35841         {"GMX1_RX000_STATS_OCTS_DMAC"  ,           0x11800100000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
35842         {"GMX1_RX001_STATS_OCTS_DMAC"  ,           0x11800100008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
35843         {"GMX1_RX002_STATS_OCTS_DMAC"  ,           0x11800100010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
35844         {"GMX1_RX003_STATS_OCTS_DMAC"  ,           0x11800100018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
35845         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
35846         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
35847         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
35848         {"GMX0_RX003_STATS_OCTS_DRP"   ,           0x11800080018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
35849         {"GMX1_RX000_STATS_OCTS_DRP"   ,           0x11800100000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
35850         {"GMX1_RX001_STATS_OCTS_DRP"   ,           0x11800100008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
35851         {"GMX1_RX002_STATS_OCTS_DRP"   ,           0x11800100010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
35852         {"GMX1_RX003_STATS_OCTS_DRP"   ,           0x11800100018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
35853         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
35854         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
35855         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
35856         {"GMX0_RX003_STATS_PKTS"       ,           0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
35857         {"GMX1_RX000_STATS_PKTS"       ,           0x1180010000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
35858         {"GMX1_RX001_STATS_PKTS"       ,           0x1180010000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
35859         {"GMX1_RX002_STATS_PKTS"       ,           0x1180010001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
35860         {"GMX1_RX003_STATS_PKTS"       ,           0x1180010001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
35861         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
35862         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
35863         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
35864         {"GMX0_RX003_STATS_PKTS_BAD"   ,           0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
35865         {"GMX1_RX000_STATS_PKTS_BAD"   ,           0x11800100000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
35866         {"GMX1_RX001_STATS_PKTS_BAD"   ,           0x11800100008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
35867         {"GMX1_RX002_STATS_PKTS_BAD"   ,           0x11800100010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
35868         {"GMX1_RX003_STATS_PKTS_BAD"   ,           0x11800100018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
35869         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
35870         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
35871         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
35872         {"GMX0_RX003_STATS_PKTS_CTL"   ,           0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
35873         {"GMX1_RX000_STATS_PKTS_CTL"   ,           0x1180010000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
35874         {"GMX1_RX001_STATS_PKTS_CTL"   ,           0x1180010000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
35875         {"GMX1_RX002_STATS_PKTS_CTL"   ,           0x1180010001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
35876         {"GMX1_RX003_STATS_PKTS_CTL"   ,           0x1180010001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
35877         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
35878         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
35879         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
35880         {"GMX0_RX003_STATS_PKTS_DMAC"  ,           0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
35881         {"GMX1_RX000_STATS_PKTS_DMAC"  ,           0x11800100000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
35882         {"GMX1_RX001_STATS_PKTS_DMAC"  ,           0x11800100008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
35883         {"GMX1_RX002_STATS_PKTS_DMAC"  ,           0x11800100010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
35884         {"GMX1_RX003_STATS_PKTS_DMAC"  ,           0x11800100018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
35885         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
35886         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
35887         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
35888         {"GMX0_RX003_STATS_PKTS_DRP"   ,           0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
35889         {"GMX1_RX000_STATS_PKTS_DRP"   ,           0x11800100000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
35890         {"GMX1_RX001_STATS_PKTS_DRP"   ,           0x11800100008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
35891         {"GMX1_RX002_STATS_PKTS_DRP"   ,           0x11800100010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
35892         {"GMX1_RX003_STATS_PKTS_DRP"   ,           0x11800100018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
35893         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
35894         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
35895         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
35896         {"GMX0_RX003_UDD_SKP"          ,           0x1180008001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
35897         {"GMX1_RX000_UDD_SKP"          ,           0x1180010000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
35898         {"GMX1_RX001_UDD_SKP"          ,           0x1180010000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
35899         {"GMX1_RX002_UDD_SKP"          ,           0x1180010001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
35900         {"GMX1_RX003_UDD_SKP"          ,           0x1180010001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
35901         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
35902         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
35903         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
35904         {"GMX0_RX_BP_DROP003"          ,           0x1180008000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
35905         {"GMX1_RX_BP_DROP000"          ,           0x1180010000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
35906         {"GMX1_RX_BP_DROP001"          ,           0x1180010000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
35907         {"GMX1_RX_BP_DROP002"          ,           0x1180010000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
35908         {"GMX1_RX_BP_DROP003"          ,           0x1180010000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
35909         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
35910         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
35911         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
35912         {"GMX0_RX_BP_OFF003"           ,           0x1180008000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
35913         {"GMX1_RX_BP_OFF000"           ,           0x1180010000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
35914         {"GMX1_RX_BP_OFF001"           ,           0x1180010000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
35915         {"GMX1_RX_BP_OFF002"           ,           0x1180010000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
35916         {"GMX1_RX_BP_OFF003"           ,           0x1180010000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
35917         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
35918         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
35919         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
35920         {"GMX0_RX_BP_ON003"            ,           0x1180008000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
35921         {"GMX1_RX_BP_ON000"            ,           0x1180010000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
35922         {"GMX1_RX_BP_ON001"            ,           0x1180010000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
35923         {"GMX1_RX_BP_ON002"            ,           0x1180010000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
35924         {"GMX1_RX_BP_ON003"            ,           0x1180010000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
35925         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
35926         {"GMX1_RX_PRT_INFO"            ,           0x11800100004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
35927         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
35928         {"GMX1_RX_PRTS"                ,           0x1180010000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
35929         {"GMX0_RX_XAUI_BAD_COL"        ,           0x1180008000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
35930         {"GMX1_RX_XAUI_BAD_COL"        ,           0x1180010000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
35931         {"GMX0_RX_XAUI_CTL"            ,           0x1180008000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
35932         {"GMX1_RX_XAUI_CTL"            ,           0x1180010000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
35933         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
35934         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
35935         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
35936         {"GMX0_SMAC003"                ,           0x1180008001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
35937         {"GMX1_SMAC000"                ,           0x1180010000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
35938         {"GMX1_SMAC001"                ,           0x1180010000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
35939         {"GMX1_SMAC002"                ,           0x1180010001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
35940         {"GMX1_SMAC003"                ,           0x1180010001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
35941         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
35942         {"GMX1_STAT_BP"                ,           0x1180010000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
35943         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
35944         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
35945         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
35946         {"GMX0_TX003_APPEND"           ,           0x1180008001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
35947         {"GMX1_TX000_APPEND"           ,           0x1180010000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
35948         {"GMX1_TX001_APPEND"           ,           0x1180010000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
35949         {"GMX1_TX002_APPEND"           ,           0x1180010001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
35950         {"GMX1_TX003_APPEND"           ,           0x1180010001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
35951         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
35952         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
35953         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
35954         {"GMX0_TX003_BURST"            ,           0x1180008001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
35955         {"GMX1_TX000_BURST"            ,           0x1180010000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
35956         {"GMX1_TX001_BURST"            ,           0x1180010000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
35957         {"GMX1_TX002_BURST"            ,           0x1180010001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
35958         {"GMX1_TX003_BURST"            ,           0x1180010001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
35959         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
35960         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
35961         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
35962         {"GMX0_TX003_CTL"              ,           0x1180008001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
35963         {"GMX1_TX000_CTL"              ,           0x1180010000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
35964         {"GMX1_TX001_CTL"              ,           0x1180010000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
35965         {"GMX1_TX002_CTL"              ,           0x1180010001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
35966         {"GMX1_TX003_CTL"              ,           0x1180010001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
35967         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
35968         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
35969         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
35970         {"GMX0_TX003_MIN_PKT"          ,           0x1180008001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
35971         {"GMX1_TX000_MIN_PKT"          ,           0x1180010000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
35972         {"GMX1_TX001_MIN_PKT"          ,           0x1180010000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
35973         {"GMX1_TX002_MIN_PKT"          ,           0x1180010001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
35974         {"GMX1_TX003_MIN_PKT"          ,           0x1180010001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
35975         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
35976         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
35977         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
35978         {"GMX0_TX003_PAUSE_PKT_INTERVAL",          0x1180008001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
35979         {"GMX1_TX000_PAUSE_PKT_INTERVAL",          0x1180010000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
35980         {"GMX1_TX001_PAUSE_PKT_INTERVAL",          0x1180010000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
35981         {"GMX1_TX002_PAUSE_PKT_INTERVAL",          0x1180010001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
35982         {"GMX1_TX003_PAUSE_PKT_INTERVAL",          0x1180010001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
35983         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
35984         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
35985         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
35986         {"GMX0_TX003_PAUSE_PKT_TIME"   ,           0x1180008001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
35987         {"GMX1_TX000_PAUSE_PKT_TIME"   ,           0x1180010000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
35988         {"GMX1_TX001_PAUSE_PKT_TIME"   ,           0x1180010000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
35989         {"GMX1_TX002_PAUSE_PKT_TIME"   ,           0x1180010001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
35990         {"GMX1_TX003_PAUSE_PKT_TIME"   ,           0x1180010001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
35991         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
35992         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
35993         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
35994         {"GMX0_TX003_PAUSE_TOGO"       ,           0x1180008001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
35995         {"GMX1_TX000_PAUSE_TOGO"       ,           0x1180010000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
35996         {"GMX1_TX001_PAUSE_TOGO"       ,           0x1180010000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
35997         {"GMX1_TX002_PAUSE_TOGO"       ,           0x1180010001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
35998         {"GMX1_TX003_PAUSE_TOGO"       ,           0x1180010001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
35999         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
36000         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
36001         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
36002         {"GMX0_TX003_PAUSE_ZERO"       ,           0x1180008001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
36003         {"GMX1_TX000_PAUSE_ZERO"       ,           0x1180010000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
36004         {"GMX1_TX001_PAUSE_ZERO"       ,           0x1180010000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
36005         {"GMX1_TX002_PAUSE_ZERO"       ,           0x1180010001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
36006         {"GMX1_TX003_PAUSE_ZERO"       ,           0x1180010001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
36007         {"GMX0_TX000_SGMII_CTL"        ,           0x1180008000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
36008         {"GMX0_TX001_SGMII_CTL"        ,           0x1180008000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
36009         {"GMX0_TX002_SGMII_CTL"        ,           0x1180008001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
36010         {"GMX0_TX003_SGMII_CTL"        ,           0x1180008001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
36011         {"GMX1_TX000_SGMII_CTL"        ,           0x1180010000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
36012         {"GMX1_TX001_SGMII_CTL"        ,           0x1180010000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
36013         {"GMX1_TX002_SGMII_CTL"        ,           0x1180010001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
36014         {"GMX1_TX003_SGMII_CTL"        ,           0x1180010001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
36015         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
36016         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
36017         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
36018         {"GMX0_TX003_SLOT"             ,           0x1180008001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
36019         {"GMX1_TX000_SLOT"             ,           0x1180010000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
36020         {"GMX1_TX001_SLOT"             ,           0x1180010000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
36021         {"GMX1_TX002_SLOT"             ,           0x1180010001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
36022         {"GMX1_TX003_SLOT"             ,           0x1180010001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
36023         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
36024         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
36025         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
36026         {"GMX0_TX003_SOFT_PAUSE"       ,           0x1180008001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
36027         {"GMX1_TX000_SOFT_PAUSE"       ,           0x1180010000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
36028         {"GMX1_TX001_SOFT_PAUSE"       ,           0x1180010000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
36029         {"GMX1_TX002_SOFT_PAUSE"       ,           0x1180010001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
36030         {"GMX1_TX003_SOFT_PAUSE"       ,           0x1180010001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
36031         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
36032         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
36033         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
36034         {"GMX0_TX003_STAT0"            ,           0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
36035         {"GMX1_TX000_STAT0"            ,           0x1180010000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
36036         {"GMX1_TX001_STAT0"            ,           0x1180010000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
36037         {"GMX1_TX002_STAT0"            ,           0x1180010001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
36038         {"GMX1_TX003_STAT0"            ,           0x1180010001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
36039         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
36040         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
36041         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
36042         {"GMX0_TX003_STAT1"            ,           0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
36043         {"GMX1_TX000_STAT1"            ,           0x1180010000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
36044         {"GMX1_TX001_STAT1"            ,           0x1180010000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
36045         {"GMX1_TX002_STAT1"            ,           0x1180010001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
36046         {"GMX1_TX003_STAT1"            ,           0x1180010001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
36047         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
36048         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
36049         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
36050         {"GMX0_TX003_STAT2"            ,           0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
36051         {"GMX1_TX000_STAT2"            ,           0x1180010000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
36052         {"GMX1_TX001_STAT2"            ,           0x1180010000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
36053         {"GMX1_TX002_STAT2"            ,           0x1180010001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
36054         {"GMX1_TX003_STAT2"            ,           0x1180010001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
36055         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
36056         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
36057         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
36058         {"GMX0_TX003_STAT3"            ,           0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
36059         {"GMX1_TX000_STAT3"            ,           0x1180010000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
36060         {"GMX1_TX001_STAT3"            ,           0x1180010000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
36061         {"GMX1_TX002_STAT3"            ,           0x1180010001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
36062         {"GMX1_TX003_STAT3"            ,           0x1180010001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
36063         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
36064         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
36065         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
36066         {"GMX0_TX003_STAT4"            ,           0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
36067         {"GMX1_TX000_STAT4"            ,           0x11800100002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
36068         {"GMX1_TX001_STAT4"            ,           0x1180010000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
36069         {"GMX1_TX002_STAT4"            ,           0x11800100012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
36070         {"GMX1_TX003_STAT4"            ,           0x1180010001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
36071         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
36072         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
36073         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
36074         {"GMX0_TX003_STAT5"            ,           0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
36075         {"GMX1_TX000_STAT5"            ,           0x11800100002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
36076         {"GMX1_TX001_STAT5"            ,           0x1180010000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
36077         {"GMX1_TX002_STAT5"            ,           0x11800100012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
36078         {"GMX1_TX003_STAT5"            ,           0x1180010001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
36079         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
36080         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
36081         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
36082         {"GMX0_TX003_STAT6"            ,           0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
36083         {"GMX1_TX000_STAT6"            ,           0x11800100002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
36084         {"GMX1_TX001_STAT6"            ,           0x1180010000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
36085         {"GMX1_TX002_STAT6"            ,           0x11800100012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
36086         {"GMX1_TX003_STAT6"            ,           0x1180010001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
36087         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
36088         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
36089         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
36090         {"GMX0_TX003_STAT7"            ,           0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
36091         {"GMX1_TX000_STAT7"            ,           0x11800100002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
36092         {"GMX1_TX001_STAT7"            ,           0x1180010000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
36093         {"GMX1_TX002_STAT7"            ,           0x11800100012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
36094         {"GMX1_TX003_STAT7"            ,           0x1180010001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
36095         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
36096         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
36097         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
36098         {"GMX0_TX003_STAT8"            ,           0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
36099         {"GMX1_TX000_STAT8"            ,           0x11800100002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
36100         {"GMX1_TX001_STAT8"            ,           0x1180010000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
36101         {"GMX1_TX002_STAT8"            ,           0x11800100012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
36102         {"GMX1_TX003_STAT8"            ,           0x1180010001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
36103         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
36104         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
36105         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
36106         {"GMX0_TX003_STAT9"            ,           0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
36107         {"GMX1_TX000_STAT9"            ,           0x11800100002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
36108         {"GMX1_TX001_STAT9"            ,           0x1180010000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
36109         {"GMX1_TX002_STAT9"            ,           0x11800100012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
36110         {"GMX1_TX003_STAT9"            ,           0x1180010001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
36111         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
36112         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
36113         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
36114         {"GMX0_TX003_STATS_CTL"        ,           0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
36115         {"GMX1_TX000_STATS_CTL"        ,           0x1180010000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
36116         {"GMX1_TX001_STATS_CTL"        ,           0x1180010000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
36117         {"GMX1_TX002_STATS_CTL"        ,           0x1180010001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
36118         {"GMX1_TX003_STATS_CTL"        ,           0x1180010001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
36119         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
36120         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
36121         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
36122         {"GMX0_TX003_THRESH"           ,           0x1180008001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
36123         {"GMX1_TX000_THRESH"           ,           0x1180010000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
36124         {"GMX1_TX001_THRESH"           ,           0x1180010000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
36125         {"GMX1_TX002_THRESH"           ,           0x1180010001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
36126         {"GMX1_TX003_THRESH"           ,           0x1180010001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
36127         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
36128         {"GMX1_TX_BP"                  ,           0x11800100004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
36129         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
36130         {"GMX1_TX_COL_ATTEMPT"         ,           0x1180010000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
36131         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
36132         {"GMX1_TX_CORRUPT"             ,           0x11800100004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
36133         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
36134         {"GMX1_TX_IFG"                 ,           0x1180010000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
36135         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
36136         {"GMX1_TX_INT_EN"              ,           0x1180010000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
36137         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
36138         {"GMX1_TX_INT_REG"             ,           0x1180010000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
36139         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
36140         {"GMX1_TX_JAM"                 ,           0x1180010000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
36141         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
36142         {"GMX1_TX_LFSR"                ,           0x11800100004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
36143         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
36144         {"GMX1_TX_OVR_BP"              ,           0x11800100004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
36145         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
36146         {"GMX1_TX_PAUSE_PKT_DMAC"      ,           0x11800100004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
36147         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
36148         {"GMX1_TX_PAUSE_PKT_TYPE"      ,           0x11800100004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
36149         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
36150         {"GMX1_TX_PRTS"                ,           0x1180010000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
36151         {"GMX0_TX_XAUI_CTL"            ,           0x1180008000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
36152         {"GMX1_TX_XAUI_CTL"            ,           0x1180010000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
36153         {"GMX0_XAUI_EXT_LOOPBACK"      ,           0x1180008000540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
36154         {"GMX1_XAUI_EXT_LOOPBACK"      ,           0x1180010000540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
36155         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36156         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36157         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36158         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36159         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36160         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36161         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36162         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36163         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36164         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36165         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36166         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36167         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36168         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36169         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36170         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
36171         {"GPIO_CLK_GEN0"               ,           0x10700000008C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
36172         {"GPIO_CLK_GEN1"               ,           0x10700000008C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
36173         {"GPIO_CLK_GEN2"               ,           0x10700000008D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
36174         {"GPIO_CLK_GEN3"               ,           0x10700000008D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
36175         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     193},
36176         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     194},
36177         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     195},
36178         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
36179         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     197},
36180         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     198},
36181         {"IOB_DWB_PRI_CNT"             ,           0x11800F0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     199},
36182         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     200},
36183         {"IOB_I2C_PRI_CNT"             ,           0x11800F0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
36184         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     202},
36185         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     203},
36186         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     204},
36187         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     205},
36188         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     206},
36189         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     207},
36190         {"IOB_N2C_L2C_PRI_CNT"         ,           0x11800F0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     208},
36191         {"IOB_N2C_RSP_PRI_CNT"         ,           0x11800F0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     209},
36192         {"IOB_OUTB_COM_PRI_CNT"        ,           0x11800F0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     210},
36193         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     211},
36194         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     212},
36195         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     213},
36196         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
36197         {"IOB_OUTB_FPA_PRI_CNT"        ,           0x11800F0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
36198         {"IOB_OUTB_REQ_PRI_CNT"        ,           0x11800F0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
36199         {"IOB_P2C_REQ_PRI_CNT"         ,           0x11800F0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
36200         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
36201         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     219},
36202         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     220},
36203         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     221},
36204         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     222},
36205         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     223},
36206         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     224},
36207         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     225},
36208         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     226},
36209         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     227},
36210         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     228},
36211         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     229},
36212         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     230},
36213         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
36214         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
36215         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
36216         {"IPD_PORT3_BP_PAGE_CNT"       ,           0x14F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
36217         {"IPD_PORT16_BP_PAGE_CNT"      ,           0x14F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
36218         {"IPD_PORT17_BP_PAGE_CNT"      ,           0x14F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
36219         {"IPD_PORT18_BP_PAGE_CNT"      ,           0x14F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
36220         {"IPD_PORT19_BP_PAGE_CNT"      ,           0x14F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
36221         {"IPD_PORT36_BP_PAGE_CNT2"     ,           0x14F0000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     232},
36222         {"IPD_PORT37_BP_PAGE_CNT2"     ,           0x14F0000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     232},
36223         {"IPD_PORT38_BP_PAGE_CNT2"     ,           0x14F0000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     232},
36224         {"IPD_PORT39_BP_PAGE_CNT2"     ,           0x14F0000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     232},
36225         {"IPD_PORT_BP_COUNTERS2_PAIR36",           0x14F0000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     233},
36226         {"IPD_PORT_BP_COUNTERS2_PAIR37",           0x14F0000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     233},
36227         {"IPD_PORT_BP_COUNTERS2_PAIR38",           0x14F0000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     233},
36228         {"IPD_PORT_BP_COUNTERS2_PAIR39",           0x14F00000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     233},
36229         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
36230         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
36231         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
36232         {"IPD_PORT_BP_COUNTERS_PAIR3"  ,           0x14F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
36233         {"IPD_PORT_BP_COUNTERS_PAIR16" ,           0x14F0000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
36234         {"IPD_PORT_BP_COUNTERS_PAIR17" ,           0x14F0000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
36235         {"IPD_PORT_BP_COUNTERS_PAIR18" ,           0x14F0000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
36236         {"IPD_PORT_BP_COUNTERS_PAIR19" ,           0x14F0000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
36237         {"IPD_PORT_QOS_0_CNT"          ,           0x14F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36238         {"IPD_PORT_QOS_1_CNT"          ,           0x14F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36239         {"IPD_PORT_QOS_2_CNT"          ,           0x14F0000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36240         {"IPD_PORT_QOS_3_CNT"          ,           0x14F00000008A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36241         {"IPD_PORT_QOS_4_CNT"          ,           0x14F00000008A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36242         {"IPD_PORT_QOS_5_CNT"          ,           0x14F00000008B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36243         {"IPD_PORT_QOS_6_CNT"          ,           0x14F00000008B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36244         {"IPD_PORT_QOS_7_CNT"          ,           0x14F00000008C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36245         {"IPD_PORT_QOS_8_CNT"          ,           0x14F00000008C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36246         {"IPD_PORT_QOS_9_CNT"          ,           0x14F00000008D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36247         {"IPD_PORT_QOS_10_CNT"         ,           0x14F00000008D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36248         {"IPD_PORT_QOS_11_CNT"         ,           0x14F00000008E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36249         {"IPD_PORT_QOS_12_CNT"         ,           0x14F00000008E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36250         {"IPD_PORT_QOS_13_CNT"         ,           0x14F00000008F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36251         {"IPD_PORT_QOS_14_CNT"         ,           0x14F00000008F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36252         {"IPD_PORT_QOS_15_CNT"         ,           0x14F0000000900ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36253         {"IPD_PORT_QOS_16_CNT"         ,           0x14F0000000908ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36254         {"IPD_PORT_QOS_17_CNT"         ,           0x14F0000000910ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36255         {"IPD_PORT_QOS_18_CNT"         ,           0x14F0000000918ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36256         {"IPD_PORT_QOS_19_CNT"         ,           0x14F0000000920ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36257         {"IPD_PORT_QOS_20_CNT"         ,           0x14F0000000928ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36258         {"IPD_PORT_QOS_21_CNT"         ,           0x14F0000000930ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36259         {"IPD_PORT_QOS_22_CNT"         ,           0x14F0000000938ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36260         {"IPD_PORT_QOS_23_CNT"         ,           0x14F0000000940ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36261         {"IPD_PORT_QOS_24_CNT"         ,           0x14F0000000948ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36262         {"IPD_PORT_QOS_25_CNT"         ,           0x14F0000000950ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36263         {"IPD_PORT_QOS_26_CNT"         ,           0x14F0000000958ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36264         {"IPD_PORT_QOS_27_CNT"         ,           0x14F0000000960ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36265         {"IPD_PORT_QOS_28_CNT"         ,           0x14F0000000968ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36266         {"IPD_PORT_QOS_29_CNT"         ,           0x14F0000000970ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36267         {"IPD_PORT_QOS_30_CNT"         ,           0x14F0000000978ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36268         {"IPD_PORT_QOS_31_CNT"         ,           0x14F0000000980ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36269         {"IPD_PORT_QOS_128_CNT"        ,           0x14F0000000C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36270         {"IPD_PORT_QOS_129_CNT"        ,           0x14F0000000C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36271         {"IPD_PORT_QOS_130_CNT"        ,           0x14F0000000C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36272         {"IPD_PORT_QOS_131_CNT"        ,           0x14F0000000CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36273         {"IPD_PORT_QOS_132_CNT"        ,           0x14F0000000CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36274         {"IPD_PORT_QOS_133_CNT"        ,           0x14F0000000CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36275         {"IPD_PORT_QOS_134_CNT"        ,           0x14F0000000CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36276         {"IPD_PORT_QOS_135_CNT"        ,           0x14F0000000CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36277         {"IPD_PORT_QOS_136_CNT"        ,           0x14F0000000CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36278         {"IPD_PORT_QOS_137_CNT"        ,           0x14F0000000CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36279         {"IPD_PORT_QOS_138_CNT"        ,           0x14F0000000CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36280         {"IPD_PORT_QOS_139_CNT"        ,           0x14F0000000CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36281         {"IPD_PORT_QOS_140_CNT"        ,           0x14F0000000CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36282         {"IPD_PORT_QOS_141_CNT"        ,           0x14F0000000CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36283         {"IPD_PORT_QOS_142_CNT"        ,           0x14F0000000CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36284         {"IPD_PORT_QOS_143_CNT"        ,           0x14F0000000D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36285         {"IPD_PORT_QOS_144_CNT"        ,           0x14F0000000D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36286         {"IPD_PORT_QOS_145_CNT"        ,           0x14F0000000D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36287         {"IPD_PORT_QOS_146_CNT"        ,           0x14F0000000D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36288         {"IPD_PORT_QOS_147_CNT"        ,           0x14F0000000D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36289         {"IPD_PORT_QOS_148_CNT"        ,           0x14F0000000D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36290         {"IPD_PORT_QOS_149_CNT"        ,           0x14F0000000D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36291         {"IPD_PORT_QOS_150_CNT"        ,           0x14F0000000D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36292         {"IPD_PORT_QOS_151_CNT"        ,           0x14F0000000D40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36293         {"IPD_PORT_QOS_152_CNT"        ,           0x14F0000000D48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36294         {"IPD_PORT_QOS_153_CNT"        ,           0x14F0000000D50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36295         {"IPD_PORT_QOS_154_CNT"        ,           0x14F0000000D58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36296         {"IPD_PORT_QOS_155_CNT"        ,           0x14F0000000D60ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36297         {"IPD_PORT_QOS_156_CNT"        ,           0x14F0000000D68ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36298         {"IPD_PORT_QOS_157_CNT"        ,           0x14F0000000D70ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36299         {"IPD_PORT_QOS_158_CNT"        ,           0x14F0000000D78ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36300         {"IPD_PORT_QOS_159_CNT"        ,           0x14F0000000D80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36301         {"IPD_PORT_QOS_288_CNT"        ,           0x14F0000001188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36302         {"IPD_PORT_QOS_289_CNT"        ,           0x14F0000001190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36303         {"IPD_PORT_QOS_290_CNT"        ,           0x14F0000001198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36304         {"IPD_PORT_QOS_291_CNT"        ,           0x14F00000011A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36305         {"IPD_PORT_QOS_292_CNT"        ,           0x14F00000011A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36306         {"IPD_PORT_QOS_293_CNT"        ,           0x14F00000011B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36307         {"IPD_PORT_QOS_294_CNT"        ,           0x14F00000011B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36308         {"IPD_PORT_QOS_295_CNT"        ,           0x14F00000011C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36309         {"IPD_PORT_QOS_296_CNT"        ,           0x14F00000011C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36310         {"IPD_PORT_QOS_297_CNT"        ,           0x14F00000011D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36311         {"IPD_PORT_QOS_298_CNT"        ,           0x14F00000011D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36312         {"IPD_PORT_QOS_299_CNT"        ,           0x14F00000011E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36313         {"IPD_PORT_QOS_300_CNT"        ,           0x14F00000011E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36314         {"IPD_PORT_QOS_301_CNT"        ,           0x14F00000011F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36315         {"IPD_PORT_QOS_302_CNT"        ,           0x14F00000011F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36316         {"IPD_PORT_QOS_303_CNT"        ,           0x14F0000001200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36317         {"IPD_PORT_QOS_304_CNT"        ,           0x14F0000001208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36318         {"IPD_PORT_QOS_305_CNT"        ,           0x14F0000001210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36319         {"IPD_PORT_QOS_306_CNT"        ,           0x14F0000001218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36320         {"IPD_PORT_QOS_307_CNT"        ,           0x14F0000001220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36321         {"IPD_PORT_QOS_308_CNT"        ,           0x14F0000001228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36322         {"IPD_PORT_QOS_309_CNT"        ,           0x14F0000001230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36323         {"IPD_PORT_QOS_310_CNT"        ,           0x14F0000001238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36324         {"IPD_PORT_QOS_311_CNT"        ,           0x14F0000001240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36325         {"IPD_PORT_QOS_312_CNT"        ,           0x14F0000001248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36326         {"IPD_PORT_QOS_313_CNT"        ,           0x14F0000001250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36327         {"IPD_PORT_QOS_314_CNT"        ,           0x14F0000001258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36328         {"IPD_PORT_QOS_315_CNT"        ,           0x14F0000001260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36329         {"IPD_PORT_QOS_316_CNT"        ,           0x14F0000001268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36330         {"IPD_PORT_QOS_317_CNT"        ,           0x14F0000001270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36331         {"IPD_PORT_QOS_318_CNT"        ,           0x14F0000001278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36332         {"IPD_PORT_QOS_319_CNT"        ,           0x14F0000001280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
36333         {"IPD_PORT_QOS_INT0"           ,           0x14F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     236},
36334         {"IPD_PORT_QOS_INT2"           ,           0x14F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     236},
36335         {"IPD_PORT_QOS_INT4"           ,           0x14F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     236},
36336         {"IPD_PORT_QOS_INT_ENB0"       ,           0x14F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     237},
36337         {"IPD_PORT_QOS_INT_ENB2"       ,           0x14F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     237},
36338         {"IPD_PORT_QOS_INT_ENB4"       ,           0x14F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     237},
36339         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     238},
36340         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     239},
36341         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     240},
36342         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     241},
36343         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
36344         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
36345         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
36346         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
36347         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
36348         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
36349         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
36350         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
36351         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
36352         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     244},
36353         {"IPD_RED_PORT_ENABLE2"        ,           0x14F00000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     245},
36354         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
36355         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
36356         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
36357         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
36358         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
36359         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
36360         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
36361         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
36362         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
36363         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     248},
36364         {"IPD_SUB_PORT_QOS_CNT"        ,           0x14F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
36365         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
36366         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     251},
36367         {"KEY_BIST_REG"                ,           0x1180020000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
36368         {"KEY_CTL_STATUS"              ,           0x1180020000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
36369         {"KEY_INT_ENB"                 ,           0x1180020000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
36370         {"KEY_INT_SUM"                 ,           0x1180020000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
36371         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
36372         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
36373         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
36374         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
36375         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
36376         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
36377         {"L2C_GRPWRR0"                 ,           0x11800800000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
36378         {"L2C_GRPWRR1"                 ,           0x11800800000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
36379         {"L2C_INT_EN"                  ,           0x1180080000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
36380         {"L2C_INT_STAT"                ,           0x11800800000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
36381         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
36382         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
36383         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
36384         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
36385         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
36386         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
36387         {"L2C_OOB"                     ,           0x11800800000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
36388         {"L2C_OOB1"                    ,           0x11800800000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
36389         {"L2C_OOB2"                    ,           0x11800800000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
36390         {"L2C_OOB3"                    ,           0x11800800000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
36391         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
36392         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
36393         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
36394         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
36395         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
36396         {"L2C_PPGRP"                   ,           0x11800800000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
36397         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
36398         {"L2C_SPAR1"                   ,           0x1180080000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
36399         {"L2C_SPAR2"                   ,           0x1180080000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
36400         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
36401         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
36402         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
36403         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
36404         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
36405         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     287},
36406         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     288},
36407         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     289},
36408         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
36409         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
36410         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     292},
36411         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
36412         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     294},
36413         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     295},
36414         {"LED_BLINK"                   ,           0x1180000001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     296},
36415         {"LED_CLK_PHASE"               ,           0x1180000001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
36416         {"LED_CYLON"                   ,           0x1180000001AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     298},
36417         {"LED_DBG"                     ,           0x1180000001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
36418         {"LED_EN"                      ,           0x1180000001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
36419         {"LED_POLARITY"                ,           0x1180000001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
36420         {"LED_PRT"                     ,           0x1180000001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
36421         {"LED_PRT_FMT"                 ,           0x1180000001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
36422         {"LED_PRT_STATUS0"             ,           0x1180000001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
36423         {"LED_PRT_STATUS1"             ,           0x1180000001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
36424         {"LED_PRT_STATUS2"             ,           0x1180000001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
36425         {"LED_PRT_STATUS3"             ,           0x1180000001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
36426         {"LED_PRT_STATUS4"             ,           0x1180000001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
36427         {"LED_PRT_STATUS5"             ,           0x1180000001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
36428         {"LED_PRT_STATUS6"             ,           0x1180000001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
36429         {"LED_PRT_STATUS7"             ,           0x1180000001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
36430         {"LED_UDD_CNT0"                ,           0x1180000001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
36431         {"LED_UDD_CNT1"                ,           0x1180000001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
36432         {"LED_UDD_DAT0"                ,           0x1180000001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
36433         {"LED_UDD_DAT1"                ,           0x1180000001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
36434         {"LED_UDD_DAT_CLR0"            ,           0x1180000001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
36435         {"LED_UDD_DAT_CLR1"            ,           0x1180000001AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
36436         {"LED_UDD_DAT_SET0"            ,           0x1180000001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
36437         {"LED_UDD_DAT_SET1"            ,           0x1180000001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
36438         {"LMC0_BIST_CTL"               ,           0x11800880000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
36439         {"LMC1_BIST_CTL"               ,           0x11800E80000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
36440         {"LMC0_BIST_RESULT"            ,           0x11800880000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
36441         {"LMC1_BIST_RESULT"            ,           0x11800E80000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
36442         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
36443         {"LMC1_COMP_CTL"               ,           0x11800E8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
36444         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
36445         {"LMC1_CTL"                    ,           0x11800E8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
36446         {"LMC0_CTL1"                   ,           0x1180088000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
36447         {"LMC1_CTL1"                   ,           0x11800E8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
36448         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
36449         {"LMC1_DCLK_CNT_HI"            ,           0x11800E8000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
36450         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
36451         {"LMC1_DCLK_CNT_LO"            ,           0x11800E8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
36452         {"LMC0_DCLK_CTL"               ,           0x11800880000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
36453         {"LMC1_DCLK_CTL"               ,           0x11800E80000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
36454         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
36455         {"LMC1_DDR2_CTL"               ,           0x11800E8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
36456         {"LMC0_DELAY_CFG"              ,           0x1180088000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
36457         {"LMC1_DELAY_CFG"              ,           0x11800E8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
36458         {"LMC0_DLL_CTL"                ,           0x11800880000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
36459         {"LMC1_DLL_CTL"                ,           0x11800E80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
36460         {"LMC0_DUAL_MEMCFG"            ,           0x1180088000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
36461         {"LMC1_DUAL_MEMCFG"            ,           0x11800E8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
36462         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
36463         {"LMC1_ECC_SYND"               ,           0x11800E8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
36464         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
36465         {"LMC1_FADR"                   ,           0x11800E8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
36466         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
36467         {"LMC1_IFB_CNT_HI"             ,           0x11800E8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
36468         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
36469         {"LMC1_IFB_CNT_LO"             ,           0x11800E8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
36470         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
36471         {"LMC1_MEM_CFG0"               ,           0x11800E8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
36472         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
36473         {"LMC1_MEM_CFG1"               ,           0x11800E8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
36474         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
36475         {"LMC1_OPS_CNT_HI"             ,           0x11800E8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
36476         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
36477         {"LMC1_OPS_CNT_LO"             ,           0x11800E8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
36478         {"LMC0_PLL_CTL"                ,           0x11800880000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
36479         {"LMC1_PLL_CTL"                ,           0x11800E80000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
36480         {"LMC0_PLL_STATUS"             ,           0x11800880000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
36481         {"LMC1_PLL_STATUS"             ,           0x11800E80000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
36482         {"LMC0_READ_LEVEL_CTL"         ,           0x1180088000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
36483         {"LMC1_READ_LEVEL_CTL"         ,           0x11800E8000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
36484         {"LMC0_READ_LEVEL_DBG"         ,           0x1180088000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
36485         {"LMC1_READ_LEVEL_DBG"         ,           0x11800E8000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
36486         {"LMC0_READ_LEVEL_RANK000"     ,           0x1180088000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
36487         {"LMC0_READ_LEVEL_RANK001"     ,           0x1180088000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
36488         {"LMC0_READ_LEVEL_RANK002"     ,           0x1180088000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
36489         {"LMC0_READ_LEVEL_RANK003"     ,           0x1180088000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
36490         {"LMC1_READ_LEVEL_RANK000"     ,           0x11800E8000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
36491         {"LMC1_READ_LEVEL_RANK001"     ,           0x11800E8000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
36492         {"LMC1_READ_LEVEL_RANK002"     ,           0x11800E8000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
36493         {"LMC1_READ_LEVEL_RANK003"     ,           0x11800E8000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
36494         {"LMC0_RODT_COMP_CTL"          ,           0x11800880000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
36495         {"LMC1_RODT_COMP_CTL"          ,           0x11800E80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
36496         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     335},
36497         {"LMC1_RODT_CTL"               ,           0x11800E8000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     335},
36498         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     336},
36499         {"LMC1_WODT_CTL0"              ,           0x11800E8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     336},
36500         {"LMC0_WODT_CTL1"              ,           0x1180088000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     337},
36501         {"LMC1_WODT_CTL1"              ,           0x11800E8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     337},
36502         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     338},
36503         {"MIO_BOOT_COMP"               ,           0x11800000000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     339},
36504         {"MIO_BOOT_DMA_CFG0"           ,           0x1180000000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
36505         {"MIO_BOOT_DMA_CFG1"           ,           0x1180000000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
36506         {"MIO_BOOT_DMA_CFG2"           ,           0x1180000000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
36507         {"MIO_BOOT_DMA_INT0"           ,           0x1180000000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     341},
36508         {"MIO_BOOT_DMA_INT1"           ,           0x1180000000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     341},
36509         {"MIO_BOOT_DMA_INT2"           ,           0x1180000000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     341},
36510         {"MIO_BOOT_DMA_INT_EN0"        ,           0x1180000000150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     342},
36511         {"MIO_BOOT_DMA_INT_EN1"        ,           0x1180000000158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     342},
36512         {"MIO_BOOT_DMA_INT_EN2"        ,           0x1180000000160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     342},
36513         {"MIO_BOOT_DMA_TIM0"           ,           0x1180000000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
36514         {"MIO_BOOT_DMA_TIM1"           ,           0x1180000000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
36515         {"MIO_BOOT_DMA_TIM2"           ,           0x1180000000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
36516         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
36517         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     345},
36518         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     346},
36519         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     347},
36520         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     347},
36521         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     348},
36522         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
36523         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
36524         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
36525         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
36526         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
36527         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
36528         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
36529         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
36530         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
36531         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
36532         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
36533         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
36534         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
36535         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
36536         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
36537         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
36538         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     351},
36539         {"MIO_FUS_BNK_DAT0"            ,           0x1180000001520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     352},
36540         {"MIO_FUS_BNK_DAT1"            ,           0x1180000001528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     352},
36541         {"MIO_FUS_BNK_DAT2"            ,           0x1180000001530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     352},
36542         {"MIO_FUS_BNK_DAT3"            ,           0x1180000001538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     352},
36543         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     353},
36544         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     354},
36545         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     355},
36546         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     356},
36547         {"MIO_FUS_EMA"                 ,           0x1180000001550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     357},
36548         {"MIO_FUS_PDF"                 ,           0x1180000001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     358},
36549         {"MIO_FUS_PLL"                 ,           0x1180000001580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     359},
36550         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     360},
36551         {"MIO_FUS_PROG_TIMES"          ,           0x1180000001518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     361},
36552         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     362},
36553         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     363},
36554         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     364},
36555         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     365},
36556         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
36557         {"MIO_TWS1_INT"                ,           0x1180000001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
36558         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
36559         {"MIO_TWS1_SW_TWSI"            ,           0x1180000001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
36560         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     368},
36561         {"MIO_TWS1_SW_TWSI_EXT"        ,           0x1180000001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     368},
36562         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
36563         {"MIO_TWS1_TWSI_SW"            ,           0x1180000001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
36564         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     370},
36565         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     370},
36566         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     371},
36567         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     371},
36568         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     372},
36569         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     372},
36570         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     373},
36571         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     373},
36572         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     374},
36573         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     374},
36574         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     375},
36575         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     375},
36576         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     376},
36577         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     376},
36578         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     377},
36579         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     377},
36580         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     378},
36581         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     378},
36582         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     379},
36583         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     379},
36584         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     380},
36585         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     380},
36586         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     381},
36587         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     381},
36588         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     382},
36589         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     382},
36590         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     383},
36591         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     383},
36592         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     384},
36593         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     384},
36594         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     385},
36595         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     385},
36596         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     386},
36597         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     386},
36598         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     387},
36599         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     387},
36600         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     388},
36601         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     388},
36602         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     389},
36603         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     389},
36604         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     390},
36605         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     390},
36606         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     391},
36607         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     391},
36608         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     392},
36609         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     392},
36610         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
36611         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
36612         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     394},
36613         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     394},
36614         {"MIX0_BIST"                   ,           0x1070000100078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     395},
36615         {"MIX0_CTL"                    ,           0x1070000100020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     396},
36616         {"MIX0_INTENA"                 ,           0x1070000100050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     397},
36617         {"MIX0_IRCNT"                  ,           0x1070000100030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     398},
36618         {"MIX0_IRHWM"                  ,           0x1070000100028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     399},
36619         {"MIX0_IRING1"                 ,           0x1070000100010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
36620         {"MIX0_IRING2"                 ,           0x1070000100018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
36621         {"MIX0_ISR"                    ,           0x1070000100048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
36622         {"MIX0_ORCNT"                  ,           0x1070000100040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     403},
36623         {"MIX0_ORHWM"                  ,           0x1070000100038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     404},
36624         {"MIX0_ORING1"                 ,           0x1070000100000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     405},
36625         {"MIX0_ORING2"                 ,           0x1070000100008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     406},
36626         {"MIX0_REMCNT"                 ,           0x1070000100058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     407},
36627         {"NPEI_BAR1_INDEX0"            ,           0x11F0000008000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36628         {"NPEI_BAR1_INDEX1"            ,           0x11F0000008010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36629         {"NPEI_BAR1_INDEX2"            ,           0x11F0000008020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36630         {"NPEI_BAR1_INDEX3"            ,           0x11F0000008030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36631         {"NPEI_BAR1_INDEX4"            ,           0x11F0000008040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36632         {"NPEI_BAR1_INDEX5"            ,           0x11F0000008050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36633         {"NPEI_BAR1_INDEX6"            ,           0x11F0000008060ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36634         {"NPEI_BAR1_INDEX7"            ,           0x11F0000008070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36635         {"NPEI_BAR1_INDEX8"            ,           0x11F0000008080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36636         {"NPEI_BAR1_INDEX9"            ,           0x11F0000008090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36637         {"NPEI_BAR1_INDEX10"           ,           0x11F00000080A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36638         {"NPEI_BAR1_INDEX11"           ,           0x11F00000080B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36639         {"NPEI_BAR1_INDEX12"           ,           0x11F00000080C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36640         {"NPEI_BAR1_INDEX13"           ,           0x11F00000080D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36641         {"NPEI_BAR1_INDEX14"           ,           0x11F00000080E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36642         {"NPEI_BAR1_INDEX15"           ,           0x11F00000080F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36643         {"NPEI_BAR1_INDEX16"           ,           0x11F0000008100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36644         {"NPEI_BAR1_INDEX17"           ,           0x11F0000008110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36645         {"NPEI_BAR1_INDEX18"           ,           0x11F0000008120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36646         {"NPEI_BAR1_INDEX19"           ,           0x11F0000008130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36647         {"NPEI_BAR1_INDEX20"           ,           0x11F0000008140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36648         {"NPEI_BAR1_INDEX21"           ,           0x11F0000008150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36649         {"NPEI_BAR1_INDEX22"           ,           0x11F0000008160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36650         {"NPEI_BAR1_INDEX23"           ,           0x11F0000008170ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36651         {"NPEI_BAR1_INDEX24"           ,           0x11F0000008180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36652         {"NPEI_BAR1_INDEX25"           ,           0x11F0000008190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36653         {"NPEI_BAR1_INDEX26"           ,           0x11F00000081A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36654         {"NPEI_BAR1_INDEX27"           ,           0x11F00000081B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36655         {"NPEI_BAR1_INDEX28"           ,           0x11F00000081C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36656         {"NPEI_BAR1_INDEX29"           ,           0x11F00000081D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36657         {"NPEI_BAR1_INDEX30"           ,           0x11F00000081E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36658         {"NPEI_BAR1_INDEX31"           ,           0x11F00000081F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     408},
36659         {"NPEI_BIST_STATUS"            ,           0x11F0000008580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     409},
36660         {"NPEI_CTL_PORT0"              ,           0x11F0000008250ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     410},
36661         {"NPEI_CTL_PORT1"              ,           0x11F0000008260ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     411},
36662         {"NPEI_CTL_STATUS"             ,           0x11F0000008570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     412},
36663         {"NPEI_CTL_STATUS2"            ,           0x11F000000BC00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     413},
36664         {"NPEI_DATA_OUT_CNT"           ,           0x11F00000085F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     414},
36665         {"NPEI_DBG_DATA"               ,           0x11F0000008510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     415},
36666         {"NPEI_DBG_SELECT"             ,           0x11F0000008500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     416},
36667         {"NPEI_DMA0_COUNTS"            ,           0x11F0000008450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     417},
36668         {"NPEI_DMA1_COUNTS"            ,           0x11F0000008460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     417},
36669         {"NPEI_DMA2_COUNTS"            ,           0x11F0000008470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     417},
36670         {"NPEI_DMA3_COUNTS"            ,           0x11F0000008480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     417},
36671         {"NPEI_DMA4_COUNTS"            ,           0x11F0000008490ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     417},
36672         {"NPEI_DMA0_DBELL"             ,           0x11F00000083B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     418},
36673         {"NPEI_DMA1_DBELL"             ,           0x11F00000083C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     418},
36674         {"NPEI_DMA2_DBELL"             ,           0x11F00000083D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     418},
36675         {"NPEI_DMA3_DBELL"             ,           0x11F00000083E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     418},
36676         {"NPEI_DMA4_DBELL"             ,           0x11F00000083F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     418},
36677         {"NPEI_DMA0_IBUFF_SADDR"       ,           0x11F0000008400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     419},
36678         {"NPEI_DMA1_IBUFF_SADDR"       ,           0x11F0000008410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     419},
36679         {"NPEI_DMA2_IBUFF_SADDR"       ,           0x11F0000008420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     419},
36680         {"NPEI_DMA3_IBUFF_SADDR"       ,           0x11F0000008430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     419},
36681         {"NPEI_DMA4_IBUFF_SADDR"       ,           0x11F0000008440ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     419},
36682         {"NPEI_DMA0_NADDR"             ,           0x11F00000084A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     420},
36683         {"NPEI_DMA1_NADDR"             ,           0x11F00000084B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     420},
36684         {"NPEI_DMA2_NADDR"             ,           0x11F00000084C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     420},
36685         {"NPEI_DMA3_NADDR"             ,           0x11F00000084D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     420},
36686         {"NPEI_DMA4_NADDR"             ,           0x11F00000084E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     420},
36687         {"NPEI_DMA0_INT_LEVEL"         ,           0x11F00000085C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     421},
36688         {"NPEI_DMA1_INT_LEVEL"         ,           0x11F00000085D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     422},
36689         {"NPEI_DMA_CNTS"               ,           0x11F00000085E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     423},
36690         {"NPEI_DMA_CONTROL"            ,           0x11F00000083A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     424},
36691         {"NPEI_DMA_STATE1_P1"          ,           0x11F0000008680ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     425},
36692         {"NPEI_DMA_STATE2_P1"          ,           0x11F0000008690ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     426},
36693         {"NPEI_DMA_STATE3_P1"          ,           0x11F00000086A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     427},
36694         {"NPEI_DMA_STATE4_P1"          ,           0x11F00000086B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     428},
36695         {"NPEI_DMA_STATE5_P1"          ,           0x11F00000086C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     429},
36696         {"NPEI_INT_ENB"                ,           0x11F0000008540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     430},
36697         {"NPEI_INT_ENB2"               ,           0x11F000000BCD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     431},
36698         {"NPEI_INT_INFO"               ,           0x11F0000008590ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     432},
36699         {"NPEI_INT_SUM"                ,           0x11F0000008530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     433},
36700         {"NPEI_LAST_WIN_RDATA0"        ,           0x11F0000008600ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     434},
36701         {"NPEI_LAST_WIN_RDATA1"        ,           0x11F0000008610ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     435},
36702         {"NPEI_MEM_ACCESS_CTL"         ,           0x11F00000084F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     436},
36703         {"NPEI_MEM_ACCESS_SUBID12"     ,           0x11F0000008280ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36704         {"NPEI_MEM_ACCESS_SUBID13"     ,           0x11F0000008290ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36705         {"NPEI_MEM_ACCESS_SUBID14"     ,           0x11F00000082A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36706         {"NPEI_MEM_ACCESS_SUBID15"     ,           0x11F00000082B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36707         {"NPEI_MEM_ACCESS_SUBID16"     ,           0x11F00000082C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36708         {"NPEI_MEM_ACCESS_SUBID17"     ,           0x11F00000082D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36709         {"NPEI_MEM_ACCESS_SUBID18"     ,           0x11F00000082E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36710         {"NPEI_MEM_ACCESS_SUBID19"     ,           0x11F00000082F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36711         {"NPEI_MEM_ACCESS_SUBID20"     ,           0x11F0000008300ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36712         {"NPEI_MEM_ACCESS_SUBID21"     ,           0x11F0000008310ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36713         {"NPEI_MEM_ACCESS_SUBID22"     ,           0x11F0000008320ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36714         {"NPEI_MEM_ACCESS_SUBID23"     ,           0x11F0000008330ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36715         {"NPEI_MEM_ACCESS_SUBID24"     ,           0x11F0000008340ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36716         {"NPEI_MEM_ACCESS_SUBID25"     ,           0x11F0000008350ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36717         {"NPEI_MEM_ACCESS_SUBID26"     ,           0x11F0000008360ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36718         {"NPEI_MEM_ACCESS_SUBID27"     ,           0x11F0000008370ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
36719         {"NPEI_MSI_ENB0"               ,           0x11F000000BC50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     438},
36720         {"NPEI_MSI_ENB1"               ,           0x11F000000BC60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     439},
36721         {"NPEI_MSI_ENB2"               ,           0x11F000000BC70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     440},
36722         {"NPEI_MSI_ENB3"               ,           0x11F000000BC80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     441},
36723         {"NPEI_MSI_RCV0"               ,           0x11F000000BC10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     442},
36724         {"NPEI_MSI_RCV1"               ,           0x11F000000BC20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     443},
36725         {"NPEI_MSI_RCV2"               ,           0x11F000000BC30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
36726         {"NPEI_MSI_RCV3"               ,           0x11F000000BC40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     445},
36727         {"NPEI_MSI_RD_MAP"             ,           0x11F000000BCA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     446},
36728         {"NPEI_MSI_WR_MAP"             ,           0x11F000000BC90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     447},
36729         {"NPEI_PCIE_MSI_RCV"           ,           0x11F000000BCB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     448},
36730         {"NPEI_PCIE_MSI_RCV_B1"        ,           0x11F0000008650ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     449},
36731         {"NPEI_PCIE_MSI_RCV_B2"        ,           0x11F0000008660ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     450},
36732         {"NPEI_PCIE_MSI_RCV_B3"        ,           0x11F0000008670ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     451},
36733         {"NPEI_RSL_INT_BLOCKS"         ,           0x11F0000008520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     452},
36734         {"NPEI_SCRATCH_1"              ,           0x11F0000008270ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     453},
36735         {"NPEI_STATE1"                 ,           0x11F0000008620ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     454},
36736         {"NPEI_STATE2"                 ,           0x11F0000008630ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
36737         {"NPEI_STATE3"                 ,           0x11F0000008640ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     456},
36738         {"NPEI_WIN_RD_ADDR"            ,                     0x210ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     457},
36739         {"NPEI_WIN_RD_DATA"            ,                     0x240ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     458},
36740         {"NPEI_WIN_WR_ADDR"            ,                     0x200ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     459},
36741         {"NPEI_WIN_WR_DATA"            ,                     0x220ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     460},
36742         {"NPEI_WIN_WR_MASK"            ,                     0x230ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     461},
36743         {"NPEI_WINDOW_CTL"             ,           0x11F0000008380ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     462},
36744         {"PCIEEP_CFG000"               ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     463},
36745         {"PCIEEP_CFG001"               ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     464},
36746         {"PCIEEP_CFG002"               ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     465},
36747         {"PCIEEP_CFG003"               ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     466},
36748         {"PCIEEP_CFG004"               ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     467},
36749         {"PCIEEP_CFG004_MASK"          ,                0x80000010ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     468},
36750         {"PCIEEP_CFG005"               ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     469},
36751         {"PCIEEP_CFG005_MASK"          ,                0x80000014ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     470},
36752         {"PCIEEP_CFG006"               ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     471},
36753         {"PCIEEP_CFG006_MASK"          ,                0x80000018ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     472},
36754         {"PCIEEP_CFG007"               ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     473},
36755         {"PCIEEP_CFG007_MASK"          ,                0x8000001Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     474},
36756         {"PCIEEP_CFG008"               ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     475},
36757         {"PCIEEP_CFG008_MASK"          ,                0x80000020ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     476},
36758         {"PCIEEP_CFG009"               ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     477},
36759         {"PCIEEP_CFG009_MASK"          ,                0x80000024ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     478},
36760         {"PCIEEP_CFG010"               ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     479},
36761         {"PCIEEP_CFG011"               ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     480},
36762         {"PCIEEP_CFG012"               ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     481},
36763         {"PCIEEP_CFG012_MASK"          ,                0x80000030ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     482},
36764         {"PCIEEP_CFG013"               ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     483},
36765         {"PCIEEP_CFG015"               ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     484},
36766         {"PCIEEP_CFG016"               ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     485},
36767         {"PCIEEP_CFG017"               ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     486},
36768         {"PCIEEP_CFG020"               ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     487},
36769         {"PCIEEP_CFG021"               ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     488},
36770         {"PCIEEP_CFG022"               ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     489},
36771         {"PCIEEP_CFG023"               ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     490},
36772         {"PCIEEP_CFG028"               ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     491},
36773         {"PCIEEP_CFG029"               ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     492},
36774         {"PCIEEP_CFG030"               ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     493},
36775         {"PCIEEP_CFG031"               ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     494},
36776         {"PCIEEP_CFG032"               ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     495},
36777         {"PCIEEP_CFG033"               ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     496},
36778         {"PCIEEP_CFG034"               ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     497},
36779         {"PCIEEP_CFG037"               ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     498},
36780         {"PCIEEP_CFG038"               ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     499},
36781         {"PCIEEP_CFG039"               ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     500},
36782         {"PCIEEP_CFG040"               ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     501},
36783         {"PCIEEP_CFG041"               ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     502},
36784         {"PCIEEP_CFG042"               ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     503},
36785         {"PCIEEP_CFG064"               ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     504},
36786         {"PCIEEP_CFG065"               ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     505},
36787         {"PCIEEP_CFG066"               ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     506},
36788         {"PCIEEP_CFG067"               ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     507},
36789         {"PCIEEP_CFG068"               ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     508},
36790         {"PCIEEP_CFG069"               ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     509},
36791         {"PCIEEP_CFG070"               ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     510},
36792         {"PCIEEP_CFG071"               ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     511},
36793         {"PCIEEP_CFG072"               ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     512},
36794         {"PCIEEP_CFG073"               ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     513},
36795         {"PCIEEP_CFG074"               ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     514},
36796         {"PCIEEP_CFG448"               ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     515},
36797         {"PCIEEP_CFG449"               ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     516},
36798         {"PCIEEP_CFG450"               ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     517},
36799         {"PCIEEP_CFG451"               ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     518},
36800         {"PCIEEP_CFG452"               ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     519},
36801         {"PCIEEP_CFG453"               ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     520},
36802         {"PCIEEP_CFG454"               ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     521},
36803         {"PCIEEP_CFG455"               ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     522},
36804         {"PCIEEP_CFG456"               ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     523},
36805         {"PCIEEP_CFG458"               ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     524},
36806         {"PCIEEP_CFG459"               ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     525},
36807         {"PCIEEP_CFG460"               ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     526},
36808         {"PCIEEP_CFG461"               ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     527},
36809         {"PCIEEP_CFG462"               ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     528},
36810         {"PCIEEP_CFG463"               ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     529},
36811         {"PCIEEP_CFG464"               ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     530},
36812         {"PCIEEP_CFG465"               ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     531},
36813         {"PCIEEP_CFG466"               ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     532},
36814         {"PCIEEP_CFG467"               ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     533},
36815         {"PCIEEP_CFG468"               ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     534},
36816         {"PCIEEP_CFG490"               ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     535},
36817         {"PCIEEP_CFG491"               ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     536},
36818         {"PCIEEP_CFG492"               ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     537},
36819         {"PCIEEP_CFG516"               ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     538},
36820         {"PCIEEP_CFG517"               ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     539},
36821         {"PCIERC0_CFG000"              ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     540},
36822         {"PCIERC1_CFG000"              ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     540},
36823         {"PCIERC0_CFG001"              ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     541},
36824         {"PCIERC1_CFG001"              ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     541},
36825         {"PCIERC0_CFG002"              ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     542},
36826         {"PCIERC1_CFG002"              ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     542},
36827         {"PCIERC0_CFG003"              ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     543},
36828         {"PCIERC1_CFG003"              ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     543},
36829         {"PCIERC0_CFG004"              ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     544},
36830         {"PCIERC1_CFG004"              ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     544},
36831         {"PCIERC0_CFG005"              ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     545},
36832         {"PCIERC1_CFG005"              ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     545},
36833         {"PCIERC0_CFG006"              ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     546},
36834         {"PCIERC1_CFG006"              ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     546},
36835         {"PCIERC0_CFG007"              ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     547},
36836         {"PCIERC1_CFG007"              ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     547},
36837         {"PCIERC0_CFG008"              ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     548},
36838         {"PCIERC1_CFG008"              ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     548},
36839         {"PCIERC0_CFG009"              ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     549},
36840         {"PCIERC1_CFG009"              ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     549},
36841         {"PCIERC0_CFG010"              ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     550},
36842         {"PCIERC1_CFG010"              ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     550},
36843         {"PCIERC0_CFG011"              ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     551},
36844         {"PCIERC1_CFG011"              ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     551},
36845         {"PCIERC0_CFG012"              ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     552},
36846         {"PCIERC1_CFG012"              ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     552},
36847         {"PCIERC0_CFG013"              ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     553},
36848         {"PCIERC1_CFG013"              ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     553},
36849         {"PCIERC0_CFG014"              ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     554},
36850         {"PCIERC1_CFG014"              ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     554},
36851         {"PCIERC0_CFG015"              ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     555},
36852         {"PCIERC1_CFG015"              ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     555},
36853         {"PCIERC0_CFG016"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     556},
36854         {"PCIERC1_CFG016"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     556},
36855         {"PCIERC0_CFG017"              ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     557},
36856         {"PCIERC1_CFG017"              ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     557},
36857         {"PCIERC0_CFG020"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     558},
36858         {"PCIERC1_CFG020"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     558},
36859         {"PCIERC0_CFG021"              ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     559},
36860         {"PCIERC1_CFG021"              ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     559},
36861         {"PCIERC0_CFG022"              ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     560},
36862         {"PCIERC1_CFG022"              ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     560},
36863         {"PCIERC0_CFG023"              ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     561},
36864         {"PCIERC1_CFG023"              ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     561},
36865         {"PCIERC0_CFG028"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     562},
36866         {"PCIERC1_CFG028"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     562},
36867         {"PCIERC0_CFG029"              ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     563},
36868         {"PCIERC1_CFG029"              ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     563},
36869         {"PCIERC0_CFG030"              ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     564},
36870         {"PCIERC1_CFG030"              ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     564},
36871         {"PCIERC0_CFG031"              ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     565},
36872         {"PCIERC1_CFG031"              ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     565},
36873         {"PCIERC0_CFG032"              ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     566},
36874         {"PCIERC1_CFG032"              ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     566},
36875         {"PCIERC0_CFG033"              ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     567},
36876         {"PCIERC1_CFG033"              ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     567},
36877         {"PCIERC0_CFG034"              ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     568},
36878         {"PCIERC1_CFG034"              ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     568},
36879         {"PCIERC0_CFG035"              ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     569},
36880         {"PCIERC1_CFG035"              ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     569},
36881         {"PCIERC0_CFG036"              ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     570},
36882         {"PCIERC1_CFG036"              ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     570},
36883         {"PCIERC0_CFG037"              ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     571},
36884         {"PCIERC1_CFG037"              ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     571},
36885         {"PCIERC0_CFG038"              ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     572},
36886         {"PCIERC1_CFG038"              ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     572},
36887         {"PCIERC0_CFG039"              ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     573},
36888         {"PCIERC1_CFG039"              ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     573},
36889         {"PCIERC0_CFG040"              ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     574},
36890         {"PCIERC1_CFG040"              ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     574},
36891         {"PCIERC0_CFG041"              ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     575},
36892         {"PCIERC1_CFG041"              ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     575},
36893         {"PCIERC0_CFG042"              ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     576},
36894         {"PCIERC1_CFG042"              ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     576},
36895         {"PCIERC0_CFG064"              ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     577},
36896         {"PCIERC1_CFG064"              ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     577},
36897         {"PCIERC0_CFG065"              ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     578},
36898         {"PCIERC1_CFG065"              ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     578},
36899         {"PCIERC0_CFG066"              ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     579},
36900         {"PCIERC1_CFG066"              ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     579},
36901         {"PCIERC0_CFG067"              ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     580},
36902         {"PCIERC1_CFG067"              ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     580},
36903         {"PCIERC0_CFG068"              ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     581},
36904         {"PCIERC1_CFG068"              ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     581},
36905         {"PCIERC0_CFG069"              ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     582},
36906         {"PCIERC1_CFG069"              ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     582},
36907         {"PCIERC0_CFG070"              ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     583},
36908         {"PCIERC1_CFG070"              ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     583},
36909         {"PCIERC0_CFG071"              ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     584},
36910         {"PCIERC1_CFG071"              ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     584},
36911         {"PCIERC0_CFG072"              ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     585},
36912         {"PCIERC1_CFG072"              ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     585},
36913         {"PCIERC0_CFG073"              ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     586},
36914         {"PCIERC1_CFG073"              ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     586},
36915         {"PCIERC0_CFG074"              ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     587},
36916         {"PCIERC1_CFG074"              ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     587},
36917         {"PCIERC0_CFG075"              ,                     0x12Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     588},
36918         {"PCIERC1_CFG075"              ,                     0x12Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     588},
36919         {"PCIERC0_CFG076"              ,                     0x130ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     589},
36920         {"PCIERC1_CFG076"              ,                     0x130ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     589},
36921         {"PCIERC0_CFG077"              ,                     0x134ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     590},
36922         {"PCIERC1_CFG077"              ,                     0x134ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     590},
36923         {"PCIERC0_CFG448"              ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     591},
36924         {"PCIERC1_CFG448"              ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     591},
36925         {"PCIERC0_CFG449"              ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     592},
36926         {"PCIERC1_CFG449"              ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     592},
36927         {"PCIERC0_CFG450"              ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     593},
36928         {"PCIERC1_CFG450"              ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     593},
36929         {"PCIERC0_CFG451"              ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     594},
36930         {"PCIERC1_CFG451"              ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     594},
36931         {"PCIERC0_CFG452"              ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     595},
36932         {"PCIERC1_CFG452"              ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     595},
36933         {"PCIERC0_CFG453"              ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     596},
36934         {"PCIERC1_CFG453"              ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     596},
36935         {"PCIERC0_CFG454"              ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     597},
36936         {"PCIERC1_CFG454"              ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     597},
36937         {"PCIERC0_CFG455"              ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     598},
36938         {"PCIERC1_CFG455"              ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     598},
36939         {"PCIERC0_CFG456"              ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     599},
36940         {"PCIERC1_CFG456"              ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     599},
36941         {"PCIERC0_CFG458"              ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     600},
36942         {"PCIERC1_CFG458"              ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     600},
36943         {"PCIERC0_CFG459"              ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     601},
36944         {"PCIERC1_CFG459"              ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     601},
36945         {"PCIERC0_CFG460"              ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     602},
36946         {"PCIERC1_CFG460"              ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     602},
36947         {"PCIERC0_CFG461"              ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     603},
36948         {"PCIERC1_CFG461"              ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     603},
36949         {"PCIERC0_CFG462"              ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     604},
36950         {"PCIERC1_CFG462"              ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     604},
36951         {"PCIERC0_CFG463"              ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     605},
36952         {"PCIERC1_CFG463"              ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     605},
36953         {"PCIERC0_CFG464"              ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     606},
36954         {"PCIERC1_CFG464"              ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     606},
36955         {"PCIERC0_CFG465"              ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     607},
36956         {"PCIERC1_CFG465"              ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     607},
36957         {"PCIERC0_CFG466"              ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     608},
36958         {"PCIERC1_CFG466"              ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     608},
36959         {"PCIERC0_CFG467"              ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     609},
36960         {"PCIERC1_CFG467"              ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     609},
36961         {"PCIERC0_CFG468"              ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     610},
36962         {"PCIERC1_CFG468"              ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     610},
36963         {"PCIERC0_CFG490"              ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     611},
36964         {"PCIERC1_CFG490"              ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     611},
36965         {"PCIERC0_CFG491"              ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     612},
36966         {"PCIERC1_CFG491"              ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     612},
36967         {"PCIERC0_CFG492"              ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     613},
36968         {"PCIERC1_CFG492"              ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     613},
36969         {"PCIERC0_CFG516"              ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     614},
36970         {"PCIERC1_CFG516"              ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     614},
36971         {"PCIERC0_CFG517"              ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     615},
36972         {"PCIERC1_CFG517"              ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     615},
36973         {"PCS0_AN000_ADV_REG"          ,           0x11800B0001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     616},
36974         {"PCS0_AN001_ADV_REG"          ,           0x11800B0001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     616},
36975         {"PCS0_AN002_ADV_REG"          ,           0x11800B0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     616},
36976         {"PCS0_AN003_ADV_REG"          ,           0x11800B0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     616},
36977         {"PCS1_AN000_ADV_REG"          ,           0x11800B8001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     616},
36978         {"PCS1_AN001_ADV_REG"          ,           0x11800B8001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     616},
36979         {"PCS1_AN002_ADV_REG"          ,           0x11800B8001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     616},
36980         {"PCS1_AN003_ADV_REG"          ,           0x11800B8001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     616},
36981         {"PCS0_AN000_EXT_ST_REG"       ,           0x11800B0001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     617},
36982         {"PCS0_AN001_EXT_ST_REG"       ,           0x11800B0001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     617},
36983         {"PCS0_AN002_EXT_ST_REG"       ,           0x11800B0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     617},
36984         {"PCS0_AN003_EXT_ST_REG"       ,           0x11800B0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     617},
36985         {"PCS1_AN000_EXT_ST_REG"       ,           0x11800B8001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     617},
36986         {"PCS1_AN001_EXT_ST_REG"       ,           0x11800B8001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     617},
36987         {"PCS1_AN002_EXT_ST_REG"       ,           0x11800B8001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     617},
36988         {"PCS1_AN003_EXT_ST_REG"       ,           0x11800B8001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     617},
36989         {"PCS0_AN000_LP_ABIL_REG"      ,           0x11800B0001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     618},
36990         {"PCS0_AN001_LP_ABIL_REG"      ,           0x11800B0001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     618},
36991         {"PCS0_AN002_LP_ABIL_REG"      ,           0x11800B0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     618},
36992         {"PCS0_AN003_LP_ABIL_REG"      ,           0x11800B0001C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     618},
36993         {"PCS1_AN000_LP_ABIL_REG"      ,           0x11800B8001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     618},
36994         {"PCS1_AN001_LP_ABIL_REG"      ,           0x11800B8001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     618},
36995         {"PCS1_AN002_LP_ABIL_REG"      ,           0x11800B8001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     618},
36996         {"PCS1_AN003_LP_ABIL_REG"      ,           0x11800B8001C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     618},
36997         {"PCS0_AN000_RESULTS_REG"      ,           0x11800B0001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     619},
36998         {"PCS0_AN001_RESULTS_REG"      ,           0x11800B0001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     619},
36999         {"PCS0_AN002_RESULTS_REG"      ,           0x11800B0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     619},
37000         {"PCS0_AN003_RESULTS_REG"      ,           0x11800B0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     619},
37001         {"PCS1_AN000_RESULTS_REG"      ,           0x11800B8001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     619},
37002         {"PCS1_AN001_RESULTS_REG"      ,           0x11800B8001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     619},
37003         {"PCS1_AN002_RESULTS_REG"      ,           0x11800B8001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     619},
37004         {"PCS1_AN003_RESULTS_REG"      ,           0x11800B8001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     619},
37005         {"PCS0_INT000_EN_REG"          ,           0x11800B0001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     620},
37006         {"PCS0_INT001_EN_REG"          ,           0x11800B0001488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     620},
37007         {"PCS0_INT002_EN_REG"          ,           0x11800B0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     620},
37008         {"PCS0_INT003_EN_REG"          ,           0x11800B0001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     620},
37009         {"PCS1_INT000_EN_REG"          ,           0x11800B8001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     620},
37010         {"PCS1_INT001_EN_REG"          ,           0x11800B8001488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     620},
37011         {"PCS1_INT002_EN_REG"          ,           0x11800B8001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     620},
37012         {"PCS1_INT003_EN_REG"          ,           0x11800B8001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     620},
37013         {"PCS0_INT000_REG"             ,           0x11800B0001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     621},
37014         {"PCS0_INT001_REG"             ,           0x11800B0001480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     621},
37015         {"PCS0_INT002_REG"             ,           0x11800B0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     621},
37016         {"PCS0_INT003_REG"             ,           0x11800B0001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     621},
37017         {"PCS1_INT000_REG"             ,           0x11800B8001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     621},
37018         {"PCS1_INT001_REG"             ,           0x11800B8001480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     621},
37019         {"PCS1_INT002_REG"             ,           0x11800B8001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     621},
37020         {"PCS1_INT003_REG"             ,           0x11800B8001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     621},
37021         {"PCS0_LINK000_TIMER_COUNT_REG",           0x11800B0001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     622},
37022         {"PCS0_LINK001_TIMER_COUNT_REG",           0x11800B0001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     622},
37023         {"PCS0_LINK002_TIMER_COUNT_REG",           0x11800B0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     622},
37024         {"PCS0_LINK003_TIMER_COUNT_REG",           0x11800B0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     622},
37025         {"PCS1_LINK000_TIMER_COUNT_REG",           0x11800B8001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     622},
37026         {"PCS1_LINK001_TIMER_COUNT_REG",           0x11800B8001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     622},
37027         {"PCS1_LINK002_TIMER_COUNT_REG",           0x11800B8001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     622},
37028         {"PCS1_LINK003_TIMER_COUNT_REG",           0x11800B8001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     622},
37029         {"PCS0_LOG_ANL000_REG"         ,           0x11800B0001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
37030         {"PCS0_LOG_ANL001_REG"         ,           0x11800B0001490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
37031         {"PCS0_LOG_ANL002_REG"         ,           0x11800B0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
37032         {"PCS0_LOG_ANL003_REG"         ,           0x11800B0001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
37033         {"PCS1_LOG_ANL000_REG"         ,           0x11800B8001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
37034         {"PCS1_LOG_ANL001_REG"         ,           0x11800B8001490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
37035         {"PCS1_LOG_ANL002_REG"         ,           0x11800B8001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
37036         {"PCS1_LOG_ANL003_REG"         ,           0x11800B8001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
37037         {"PCS0_MISC000_CTL_REG"        ,           0x11800B0001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
37038         {"PCS0_MISC001_CTL_REG"        ,           0x11800B0001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
37039         {"PCS0_MISC002_CTL_REG"        ,           0x11800B0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
37040         {"PCS0_MISC003_CTL_REG"        ,           0x11800B0001C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
37041         {"PCS1_MISC000_CTL_REG"        ,           0x11800B8001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
37042         {"PCS1_MISC001_CTL_REG"        ,           0x11800B8001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
37043         {"PCS1_MISC002_CTL_REG"        ,           0x11800B8001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
37044         {"PCS1_MISC003_CTL_REG"        ,           0x11800B8001C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
37045         {"PCS0_MR000_CONTROL_REG"      ,           0x11800B0001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
37046         {"PCS0_MR001_CONTROL_REG"      ,           0x11800B0001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
37047         {"PCS0_MR002_CONTROL_REG"      ,           0x11800B0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
37048         {"PCS0_MR003_CONTROL_REG"      ,           0x11800B0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
37049         {"PCS1_MR000_CONTROL_REG"      ,           0x11800B8001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
37050         {"PCS1_MR001_CONTROL_REG"      ,           0x11800B8001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
37051         {"PCS1_MR002_CONTROL_REG"      ,           0x11800B8001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
37052         {"PCS1_MR003_CONTROL_REG"      ,           0x11800B8001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
37053         {"PCS0_MR000_STATUS_REG"       ,           0x11800B0001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
37054         {"PCS0_MR001_STATUS_REG"       ,           0x11800B0001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
37055         {"PCS0_MR002_STATUS_REG"       ,           0x11800B0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
37056         {"PCS0_MR003_STATUS_REG"       ,           0x11800B0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
37057         {"PCS1_MR000_STATUS_REG"       ,           0x11800B8001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
37058         {"PCS1_MR001_STATUS_REG"       ,           0x11800B8001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
37059         {"PCS1_MR002_STATUS_REG"       ,           0x11800B8001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
37060         {"PCS1_MR003_STATUS_REG"       ,           0x11800B8001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
37061         {"PCS0_RX000_STATES_REG"       ,           0x11800B0001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
37062         {"PCS0_RX001_STATES_REG"       ,           0x11800B0001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
37063         {"PCS0_RX002_STATES_REG"       ,           0x11800B0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
37064         {"PCS0_RX003_STATES_REG"       ,           0x11800B0001C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
37065         {"PCS1_RX000_STATES_REG"       ,           0x11800B8001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
37066         {"PCS1_RX001_STATES_REG"       ,           0x11800B8001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
37067         {"PCS1_RX002_STATES_REG"       ,           0x11800B8001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
37068         {"PCS1_RX003_STATES_REG"       ,           0x11800B8001C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
37069         {"PCS0_RX000_SYNC_REG"         ,           0x11800B0001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
37070         {"PCS0_RX001_SYNC_REG"         ,           0x11800B0001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
37071         {"PCS0_RX002_SYNC_REG"         ,           0x11800B0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
37072         {"PCS0_RX003_SYNC_REG"         ,           0x11800B0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
37073         {"PCS1_RX000_SYNC_REG"         ,           0x11800B8001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
37074         {"PCS1_RX001_SYNC_REG"         ,           0x11800B8001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
37075         {"PCS1_RX002_SYNC_REG"         ,           0x11800B8001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
37076         {"PCS1_RX003_SYNC_REG"         ,           0x11800B8001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
37077         {"PCS0_SGM000_AN_ADV_REG"      ,           0x11800B0001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
37078         {"PCS0_SGM001_AN_ADV_REG"      ,           0x11800B0001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
37079         {"PCS0_SGM002_AN_ADV_REG"      ,           0x11800B0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
37080         {"PCS0_SGM003_AN_ADV_REG"      ,           0x11800B0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
37081         {"PCS1_SGM000_AN_ADV_REG"      ,           0x11800B8001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
37082         {"PCS1_SGM001_AN_ADV_REG"      ,           0x11800B8001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
37083         {"PCS1_SGM002_AN_ADV_REG"      ,           0x11800B8001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
37084         {"PCS1_SGM003_AN_ADV_REG"      ,           0x11800B8001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
37085         {"PCS0_SGM000_LP_ADV_REG"      ,           0x11800B0001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
37086         {"PCS0_SGM001_LP_ADV_REG"      ,           0x11800B0001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
37087         {"PCS0_SGM002_LP_ADV_REG"      ,           0x11800B0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
37088         {"PCS0_SGM003_LP_ADV_REG"      ,           0x11800B0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
37089         {"PCS1_SGM000_LP_ADV_REG"      ,           0x11800B8001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
37090         {"PCS1_SGM001_LP_ADV_REG"      ,           0x11800B8001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
37091         {"PCS1_SGM002_LP_ADV_REG"      ,           0x11800B8001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
37092         {"PCS1_SGM003_LP_ADV_REG"      ,           0x11800B8001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
37093         {"PCS0_TX000_STATES_REG"       ,           0x11800B0001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
37094         {"PCS0_TX001_STATES_REG"       ,           0x11800B0001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
37095         {"PCS0_TX002_STATES_REG"       ,           0x11800B0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
37096         {"PCS0_TX003_STATES_REG"       ,           0x11800B0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
37097         {"PCS1_TX000_STATES_REG"       ,           0x11800B8001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
37098         {"PCS1_TX001_STATES_REG"       ,           0x11800B8001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
37099         {"PCS1_TX002_STATES_REG"       ,           0x11800B8001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
37100         {"PCS1_TX003_STATES_REG"       ,           0x11800B8001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
37101         {"PCS0_TX_RX000_POLARITY_REG"  ,           0x11800B0001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
37102         {"PCS0_TX_RX001_POLARITY_REG"  ,           0x11800B0001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
37103         {"PCS0_TX_RX002_POLARITY_REG"  ,           0x11800B0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
37104         {"PCS0_TX_RX003_POLARITY_REG"  ,           0x11800B0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
37105         {"PCS1_TX_RX000_POLARITY_REG"  ,           0x11800B8001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
37106         {"PCS1_TX_RX001_POLARITY_REG"  ,           0x11800B8001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
37107         {"PCS1_TX_RX002_POLARITY_REG"  ,           0x11800B8001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
37108         {"PCS1_TX_RX003_POLARITY_REG"  ,           0x11800B8001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
37109         {"PCSX0_10GBX_STATUS_REG"      ,           0x11800B0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     633},
37110         {"PCSX1_10GBX_STATUS_REG"      ,           0x11800B8000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     633},
37111         {"PCSX0_BIST_STATUS_REG"       ,           0x11800B0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     634},
37112         {"PCSX1_BIST_STATUS_REG"       ,           0x11800B8000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     634},
37113         {"PCSX0_BIT_LOCK_STATUS_REG"   ,           0x11800B0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     635},
37114         {"PCSX1_BIT_LOCK_STATUS_REG"   ,           0x11800B8000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     635},
37115         {"PCSX0_CONTROL1_REG"          ,           0x11800B0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     636},
37116         {"PCSX1_CONTROL1_REG"          ,           0x11800B8000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     636},
37117         {"PCSX0_CONTROL2_REG"          ,           0x11800B0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     637},
37118         {"PCSX1_CONTROL2_REG"          ,           0x11800B8000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     637},
37119         {"PCSX0_INT_EN_REG"            ,           0x11800B0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     638},
37120         {"PCSX1_INT_EN_REG"            ,           0x11800B8000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     638},
37121         {"PCSX0_INT_REG"               ,           0x11800B0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     639},
37122         {"PCSX1_INT_REG"               ,           0x11800B8000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     639},
37123         {"PCSX0_LOG_ANL_REG"           ,           0x11800B0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     640},
37124         {"PCSX1_LOG_ANL_REG"           ,           0x11800B8000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     640},
37125         {"PCSX0_MISC_CTL_REG"          ,           0x11800B0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     641},
37126         {"PCSX1_MISC_CTL_REG"          ,           0x11800B8000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     641},
37127         {"PCSX0_RX_SYNC_STATES_REG"    ,           0x11800B0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     642},
37128         {"PCSX1_RX_SYNC_STATES_REG"    ,           0x11800B8000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     642},
37129         {"PCSX0_SPD_ABIL_REG"          ,           0x11800B0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     643},
37130         {"PCSX1_SPD_ABIL_REG"          ,           0x11800B8000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     643},
37131         {"PCSX0_STATUS1_REG"           ,           0x11800B0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     644},
37132         {"PCSX1_STATUS1_REG"           ,           0x11800B8000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     644},
37133         {"PCSX0_STATUS2_REG"           ,           0x11800B0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     645},
37134         {"PCSX1_STATUS2_REG"           ,           0x11800B8000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     645},
37135         {"PCSX0_TX_RX_POLARITY_REG"    ,           0x11800B0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     646},
37136         {"PCSX1_TX_RX_POLARITY_REG"    ,           0x11800B8000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     646},
37137         {"PCSX0_TX_RX_STATES_REG"      ,           0x11800B0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     647},
37138         {"PCSX1_TX_RX_STATES_REG"      ,           0x11800B8000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     647},
37139         {"PESC0_BIST_STATUS"           ,           0x11800C8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     648},
37140         {"PESC1_BIST_STATUS"           ,           0x11800D0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     648},
37141         {"PESC0_BIST_STATUS2"          ,           0x11800C8000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     649},
37142         {"PESC1_BIST_STATUS2"          ,           0x11800D0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     649},
37143         {"PESC0_CFG_RD"                ,           0x11800C8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     650},
37144         {"PESC1_CFG_RD"                ,           0x11800D0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     650},
37145         {"PESC0_CFG_WR"                ,           0x11800C8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     651},
37146         {"PESC1_CFG_WR"                ,           0x11800D0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     651},
37147         {"PESC0_CPL_LUT_VALID"         ,           0x11800C8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     652},
37148         {"PESC1_CPL_LUT_VALID"         ,           0x11800D0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     652},
37149         {"PESC0_CTL_STATUS"            ,           0x11800C8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     653},
37150         {"PESC1_CTL_STATUS"            ,           0x11800D0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     653},
37151         {"PESC0_CTL_STATUS2"           ,           0x11800C8000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     654},
37152         {"PESC1_CTL_STATUS2"           ,           0x11800D0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     654},
37153         {"PESC0_DBG_INFO"              ,           0x11800C8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     655},
37154         {"PESC1_DBG_INFO"              ,           0x11800D0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     655},
37155         {"PESC0_DBG_INFO_EN"           ,           0x11800C80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     656},
37156         {"PESC1_DBG_INFO_EN"           ,           0x11800D00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     656},
37157         {"PESC0_DIAG_STATUS"           ,           0x11800C8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     657},
37158         {"PESC1_DIAG_STATUS"           ,           0x11800D0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     657},
37159         {"PESC0_P2N_BAR0_START"        ,           0x11800C8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     658},
37160         {"PESC1_P2N_BAR0_START"        ,           0x11800D0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     658},
37161         {"PESC0_P2N_BAR1_START"        ,           0x11800C8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     659},
37162         {"PESC1_P2N_BAR1_START"        ,           0x11800D0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     659},
37163         {"PESC0_P2N_BAR2_START"        ,           0x11800C8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     660},
37164         {"PESC1_P2N_BAR2_START"        ,           0x11800D0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     660},
37165         {"PESC0_P2P_BAR000_END"        ,           0x11800C8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
37166         {"PESC0_P2P_BAR001_END"        ,           0x11800C8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
37167         {"PESC0_P2P_BAR002_END"        ,           0x11800C8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
37168         {"PESC0_P2P_BAR003_END"        ,           0x11800C8000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
37169         {"PESC1_P2P_BAR000_END"        ,           0x11800D0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
37170         {"PESC1_P2P_BAR001_END"        ,           0x11800D0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
37171         {"PESC1_P2P_BAR002_END"        ,           0x11800D0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
37172         {"PESC1_P2P_BAR003_END"        ,           0x11800D0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
37173         {"PESC0_P2P_BAR000_START"      ,           0x11800C8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
37174         {"PESC0_P2P_BAR001_START"      ,           0x11800C8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
37175         {"PESC0_P2P_BAR002_START"      ,           0x11800C8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
37176         {"PESC0_P2P_BAR003_START"      ,           0x11800C8000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
37177         {"PESC1_P2P_BAR000_START"      ,           0x11800D0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
37178         {"PESC1_P2P_BAR001_START"      ,           0x11800D0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
37179         {"PESC1_P2P_BAR002_START"      ,           0x11800D0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
37180         {"PESC1_P2P_BAR003_START"      ,           0x11800D0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
37181         {"PESC0_TLP_CREDITS"           ,           0x11800C8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     663},
37182         {"PESC1_TLP_CREDITS"           ,           0x11800D0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     663},
37183         {"PIP_BCK_PRS"                 ,           0x11800A0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     664},
37184         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     665},
37185         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     666},
37186         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     666},
37187         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     666},
37188         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     666},
37189         {"PIP_FRM_LEN_CHK0"            ,           0x11800A0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     667},
37190         {"PIP_FRM_LEN_CHK1"            ,           0x11800A0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     667},
37191         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     668},
37192         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     669},
37193         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     670},
37194         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     671},
37195         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     672},
37196         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37197         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37198         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37199         {"PIP_PRT_CFG3"                ,           0x11800A0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37200         {"PIP_PRT_CFG16"               ,           0x11800A0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37201         {"PIP_PRT_CFG17"               ,           0x11800A0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37202         {"PIP_PRT_CFG18"               ,           0x11800A0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37203         {"PIP_PRT_CFG19"               ,           0x11800A0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37204         {"PIP_PRT_CFG36"               ,           0x11800A0000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37205         {"PIP_PRT_CFG37"               ,           0x11800A0000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37206         {"PIP_PRT_CFG38"               ,           0x11800A0000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37207         {"PIP_PRT_CFG39"               ,           0x11800A0000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
37208         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37209         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37210         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37211         {"PIP_PRT_TAG3"                ,           0x11800A0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37212         {"PIP_PRT_TAG16"               ,           0x11800A0000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37213         {"PIP_PRT_TAG17"               ,           0x11800A0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37214         {"PIP_PRT_TAG18"               ,           0x11800A0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37215         {"PIP_PRT_TAG19"               ,           0x11800A0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37216         {"PIP_PRT_TAG36"               ,           0x11800A0000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37217         {"PIP_PRT_TAG37"               ,           0x11800A0000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37218         {"PIP_PRT_TAG38"               ,           0x11800A0000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37219         {"PIP_PRT_TAG39"               ,           0x11800A0000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
37220         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37221         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37222         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37223         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37224         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37225         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37226         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37227         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37228         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37229         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37230         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37231         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37232         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37233         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37234         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37235         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37236         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37237         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37238         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37239         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37240         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37241         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37242         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37243         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37244         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37245         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37246         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37247         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37248         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37249         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37250         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37251         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37252         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37253         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37254         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37255         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37256         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37257         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37258         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37259         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37260         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37261         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37262         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37263         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37264         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37265         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37266         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37267         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37268         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37269         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37270         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37271         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37272         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37273         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37274         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37275         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37276         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37277         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37278         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37279         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37280         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37281         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37282         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37283         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
37284         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     676},
37285         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     676},
37286         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     676},
37287         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     676},
37288         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     676},
37289         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     676},
37290         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     676},
37291         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     676},
37292         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     677},
37293         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     677},
37294         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     677},
37295         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     677},
37296         {"PIP_QOS_WATCH4"              ,           0x11800A0000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     677},
37297         {"PIP_QOS_WATCH5"              ,           0x11800A0000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     677},
37298         {"PIP_QOS_WATCH6"              ,           0x11800A0000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     677},
37299         {"PIP_QOS_WATCH7"              ,           0x11800A0000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     677},
37300         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     678},
37301         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
37302         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37303         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37304         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37305         {"PIP_STAT0_PRT3"              ,           0x11800A00008F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37306         {"PIP_STAT0_PRT16"             ,           0x11800A0000D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37307         {"PIP_STAT0_PRT17"             ,           0x11800A0000D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37308         {"PIP_STAT0_PRT18"             ,           0x11800A0000DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37309         {"PIP_STAT0_PRT19"             ,           0x11800A0000DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37310         {"PIP_STAT0_PRT36"             ,           0x11800A0001340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37311         {"PIP_STAT0_PRT37"             ,           0x11800A0001390ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37312         {"PIP_STAT0_PRT38"             ,           0x11800A00013E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37313         {"PIP_STAT0_PRT39"             ,           0x11800A0001430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
37314         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37315         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37316         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37317         {"PIP_STAT1_PRT3"              ,           0x11800A00008F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37318         {"PIP_STAT1_PRT16"             ,           0x11800A0000D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37319         {"PIP_STAT1_PRT17"             ,           0x11800A0000D58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37320         {"PIP_STAT1_PRT18"             ,           0x11800A0000DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37321         {"PIP_STAT1_PRT19"             ,           0x11800A0000DF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37322         {"PIP_STAT1_PRT36"             ,           0x11800A0001348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37323         {"PIP_STAT1_PRT37"             ,           0x11800A0001398ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37324         {"PIP_STAT1_PRT38"             ,           0x11800A00013E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37325         {"PIP_STAT1_PRT39"             ,           0x11800A0001438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
37326         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37327         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37328         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37329         {"PIP_STAT2_PRT3"              ,           0x11800A0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37330         {"PIP_STAT2_PRT16"             ,           0x11800A0000D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37331         {"PIP_STAT2_PRT17"             ,           0x11800A0000D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37332         {"PIP_STAT2_PRT18"             ,           0x11800A0000DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37333         {"PIP_STAT2_PRT19"             ,           0x11800A0000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37334         {"PIP_STAT2_PRT36"             ,           0x11800A0001350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37335         {"PIP_STAT2_PRT37"             ,           0x11800A00013A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37336         {"PIP_STAT2_PRT38"             ,           0x11800A00013F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37337         {"PIP_STAT2_PRT39"             ,           0x11800A0001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
37338         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37339         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37340         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37341         {"PIP_STAT3_PRT3"              ,           0x11800A0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37342         {"PIP_STAT3_PRT16"             ,           0x11800A0000D18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37343         {"PIP_STAT3_PRT17"             ,           0x11800A0000D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37344         {"PIP_STAT3_PRT18"             ,           0x11800A0000DB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37345         {"PIP_STAT3_PRT19"             ,           0x11800A0000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37346         {"PIP_STAT3_PRT36"             ,           0x11800A0001358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37347         {"PIP_STAT3_PRT37"             ,           0x11800A00013A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37348         {"PIP_STAT3_PRT38"             ,           0x11800A00013F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37349         {"PIP_STAT3_PRT39"             ,           0x11800A0001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
37350         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37351         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37352         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37353         {"PIP_STAT4_PRT3"              ,           0x11800A0000910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37354         {"PIP_STAT4_PRT16"             ,           0x11800A0000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37355         {"PIP_STAT4_PRT17"             ,           0x11800A0000D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37356         {"PIP_STAT4_PRT18"             ,           0x11800A0000DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37357         {"PIP_STAT4_PRT19"             ,           0x11800A0000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37358         {"PIP_STAT4_PRT36"             ,           0x11800A0001360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37359         {"PIP_STAT4_PRT37"             ,           0x11800A00013B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37360         {"PIP_STAT4_PRT38"             ,           0x11800A0001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37361         {"PIP_STAT4_PRT39"             ,           0x11800A0001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
37362         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37363         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37364         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37365         {"PIP_STAT5_PRT3"              ,           0x11800A0000918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37366         {"PIP_STAT5_PRT16"             ,           0x11800A0000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37367         {"PIP_STAT5_PRT17"             ,           0x11800A0000D78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37368         {"PIP_STAT5_PRT18"             ,           0x11800A0000DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37369         {"PIP_STAT5_PRT19"             ,           0x11800A0000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37370         {"PIP_STAT5_PRT36"             ,           0x11800A0001368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37371         {"PIP_STAT5_PRT37"             ,           0x11800A00013B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37372         {"PIP_STAT5_PRT38"             ,           0x11800A0001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37373         {"PIP_STAT5_PRT39"             ,           0x11800A0001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
37374         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37375         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37376         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37377         {"PIP_STAT6_PRT3"              ,           0x11800A0000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37378         {"PIP_STAT6_PRT16"             ,           0x11800A0000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37379         {"PIP_STAT6_PRT17"             ,           0x11800A0000D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37380         {"PIP_STAT6_PRT18"             ,           0x11800A0000DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37381         {"PIP_STAT6_PRT19"             ,           0x11800A0000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37382         {"PIP_STAT6_PRT36"             ,           0x11800A0001370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37383         {"PIP_STAT6_PRT37"             ,           0x11800A00013C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37384         {"PIP_STAT6_PRT38"             ,           0x11800A0001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37385         {"PIP_STAT6_PRT39"             ,           0x11800A0001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
37386         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37387         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37388         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37389         {"PIP_STAT7_PRT3"              ,           0x11800A0000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37390         {"PIP_STAT7_PRT16"             ,           0x11800A0000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37391         {"PIP_STAT7_PRT17"             ,           0x11800A0000D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37392         {"PIP_STAT7_PRT18"             ,           0x11800A0000DD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37393         {"PIP_STAT7_PRT19"             ,           0x11800A0000E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37394         {"PIP_STAT7_PRT36"             ,           0x11800A0001378ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37395         {"PIP_STAT7_PRT37"             ,           0x11800A00013C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37396         {"PIP_STAT7_PRT38"             ,           0x11800A0001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37397         {"PIP_STAT7_PRT39"             ,           0x11800A0001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
37398         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37399         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37400         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37401         {"PIP_STAT8_PRT3"              ,           0x11800A0000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37402         {"PIP_STAT8_PRT16"             ,           0x11800A0000D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37403         {"PIP_STAT8_PRT17"             ,           0x11800A0000D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37404         {"PIP_STAT8_PRT18"             ,           0x11800A0000DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37405         {"PIP_STAT8_PRT19"             ,           0x11800A0000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37406         {"PIP_STAT8_PRT36"             ,           0x11800A0001380ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37407         {"PIP_STAT8_PRT37"             ,           0x11800A00013D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37408         {"PIP_STAT8_PRT38"             ,           0x11800A0001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37409         {"PIP_STAT8_PRT39"             ,           0x11800A0001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
37410         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37411         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37412         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37413         {"PIP_STAT9_PRT3"              ,           0x11800A0000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37414         {"PIP_STAT9_PRT16"             ,           0x11800A0000D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37415         {"PIP_STAT9_PRT17"             ,           0x11800A0000D98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37416         {"PIP_STAT9_PRT18"             ,           0x11800A0000DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37417         {"PIP_STAT9_PRT19"             ,           0x11800A0000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37418         {"PIP_STAT9_PRT36"             ,           0x11800A0001388ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37419         {"PIP_STAT9_PRT37"             ,           0x11800A00013D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37420         {"PIP_STAT9_PRT38"             ,           0x11800A0001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37421         {"PIP_STAT9_PRT39"             ,           0x11800A0001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
37422         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
37423         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37424         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37425         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37426         {"PIP_STAT_INB_ERRS3"          ,           0x11800A0001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37427         {"PIP_STAT_INB_ERRS16"         ,           0x11800A0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37428         {"PIP_STAT_INB_ERRS17"         ,           0x11800A0001C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37429         {"PIP_STAT_INB_ERRS18"         ,           0x11800A0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37430         {"PIP_STAT_INB_ERRS19"         ,           0x11800A0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37431         {"PIP_STAT_INB_ERRS36"         ,           0x11800A0001E90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37432         {"PIP_STAT_INB_ERRS37"         ,           0x11800A0001EB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37433         {"PIP_STAT_INB_ERRS38"         ,           0x11800A0001ED0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37434         {"PIP_STAT_INB_ERRS39"         ,           0x11800A0001EF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
37435         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37436         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37437         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37438         {"PIP_STAT_INB_OCTS3"          ,           0x11800A0001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37439         {"PIP_STAT_INB_OCTS16"         ,           0x11800A0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37440         {"PIP_STAT_INB_OCTS17"         ,           0x11800A0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37441         {"PIP_STAT_INB_OCTS18"         ,           0x11800A0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37442         {"PIP_STAT_INB_OCTS19"         ,           0x11800A0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37443         {"PIP_STAT_INB_OCTS36"         ,           0x11800A0001E88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37444         {"PIP_STAT_INB_OCTS37"         ,           0x11800A0001EA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37445         {"PIP_STAT_INB_OCTS38"         ,           0x11800A0001EC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37446         {"PIP_STAT_INB_OCTS39"         ,           0x11800A0001EE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
37447         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37448         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37449         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37450         {"PIP_STAT_INB_PKTS3"          ,           0x11800A0001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37451         {"PIP_STAT_INB_PKTS16"         ,           0x11800A0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37452         {"PIP_STAT_INB_PKTS17"         ,           0x11800A0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37453         {"PIP_STAT_INB_PKTS18"         ,           0x11800A0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37454         {"PIP_STAT_INB_PKTS19"         ,           0x11800A0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37455         {"PIP_STAT_INB_PKTS36"         ,           0x11800A0001E80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37456         {"PIP_STAT_INB_PKTS37"         ,           0x11800A0001EA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37457         {"PIP_STAT_INB_PKTS38"         ,           0x11800A0001EC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37458         {"PIP_STAT_INB_PKTS39"         ,           0x11800A0001EE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
37459         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37460         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37461         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37462         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37463         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37464         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37465         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37466         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37467         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37468         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37469         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37470         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37471         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37472         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37473         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37474         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37475         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37476         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37477         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37478         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37479         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37480         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37481         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37482         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37483         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37484         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37485         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37486         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37487         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37488         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37489         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37490         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37491         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37492         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37493         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37494         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37495         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37496         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37497         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37498         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37499         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37500         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37501         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37502         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37503         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37504         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37505         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37506         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37507         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37508         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37509         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37510         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37511         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37512         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37513         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37514         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37515         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37516         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37517         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37518         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37519         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37520         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37521         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37522         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
37523         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
37524         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
37525         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
37526         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
37527         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     699},
37528         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
37529         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
37530         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
37531         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
37532         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     704},
37533         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     705},
37534         {"PKO_MEM_DEBUG14"             ,           0x1180050001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     706},
37535         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     707},
37536         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     708},
37537         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     709},
37538         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     710},
37539         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     711},
37540         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     712},
37541         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     713},
37542         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     714},
37543         {"PKO_MEM_PORT_PTRS"           ,           0x1180050001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     715},
37544         {"PKO_MEM_PORT_QOS"            ,           0x1180050001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     716},
37545         {"PKO_MEM_PORT_RATE0"          ,           0x1180050001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     717},
37546         {"PKO_MEM_PORT_RATE1"          ,           0x1180050001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     718},
37547         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     719},
37548         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     720},
37549         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     721},
37550         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     722},
37551         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     723},
37552         {"PKO_REG_DEBUG1"              ,           0x11800500000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
37553         {"PKO_REG_DEBUG2"              ,           0x11800500000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
37554         {"PKO_REG_DEBUG3"              ,           0x11800500000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     726},
37555         {"PKO_REG_ENGINE_INFLIGHT"     ,           0x1180050000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     727},
37556         {"PKO_REG_ENGINE_THRESH"       ,           0x1180050000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     728},
37557         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     729},
37558         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     730},
37559         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     731},
37560         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     732},
37561         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     733},
37562         {"PKO_REG_QUEUE_PTRS1"         ,           0x1180050000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     734},
37563         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     735},
37564         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     736},
37565         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     737},
37566         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     738},
37567         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     739},
37568         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     740},
37569         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     740},
37570         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     740},
37571         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     740},
37572         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     740},
37573         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     740},
37574         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     740},
37575         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     740},
37576         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     741},
37577         {"POW_IQ_INT"                  ,           0x1670000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     742},
37578         {"POW_IQ_INT_EN"               ,           0x1670000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     743},
37579         {"POW_IQ_THR0"                 ,           0x16700000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     744},
37580         {"POW_IQ_THR1"                 ,           0x16700000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     744},
37581         {"POW_IQ_THR2"                 ,           0x16700000003B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     744},
37582         {"POW_IQ_THR3"                 ,           0x16700000003B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     744},
37583         {"POW_IQ_THR4"                 ,           0x16700000003C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     744},
37584         {"POW_IQ_THR5"                 ,           0x16700000003C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     744},
37585         {"POW_IQ_THR6"                 ,           0x16700000003D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     744},
37586         {"POW_IQ_THR7"                 ,           0x16700000003D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     744},
37587         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     745},
37588         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     746},
37589         {"POW_PF_RST_MSK"              ,           0x1670000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     747},
37590         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37591         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37592         {"POW_PP_GRP_MSK2"             ,           0x1670000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37593         {"POW_PP_GRP_MSK3"             ,           0x1670000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37594         {"POW_PP_GRP_MSK4"             ,           0x1670000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37595         {"POW_PP_GRP_MSK5"             ,           0x1670000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37596         {"POW_PP_GRP_MSK6"             ,           0x1670000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37597         {"POW_PP_GRP_MSK7"             ,           0x1670000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37598         {"POW_PP_GRP_MSK8"             ,           0x1670000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37599         {"POW_PP_GRP_MSK9"             ,           0x1670000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37600         {"POW_PP_GRP_MSK10"            ,           0x1670000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37601         {"POW_PP_GRP_MSK11"            ,           0x1670000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
37602         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
37603         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
37604         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
37605         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
37606         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
37607         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
37608         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
37609         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
37610         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     750},
37611         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     750},
37612         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     750},
37613         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     750},
37614         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     750},
37615         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     750},
37616         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     750},
37617         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     750},
37618         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     751},
37619         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     752},
37620         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
37621         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
37622         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
37623         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
37624         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
37625         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
37626         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
37627         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
37628         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     754},
37629         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37630         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37631         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37632         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37633         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37634         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37635         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37636         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37637         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37638         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37639         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37640         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37641         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37642         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37643         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37644         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
37645         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     756},
37646         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37647         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37648         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37649         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37650         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37651         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37652         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37653         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37654         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37655         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37656         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37657         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37658         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37659         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37660         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37661         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
37662         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37663         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37664         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37665         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37666         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37667         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37668         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37669         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37670         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37671         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37672         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37673         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37674         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37675         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37676         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37677         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
37678         {"RAD_MEM_DEBUG0"              ,           0x1180070001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
37679         {"RAD_MEM_DEBUG1"              ,           0x1180070001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
37680         {"RAD_MEM_DEBUG2"              ,           0x1180070001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
37681         {"RAD_REG_BIST_RESULT"         ,           0x1180070000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
37682         {"RAD_REG_CMD_BUF"             ,           0x1180070000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
37683         {"RAD_REG_CTL"                 ,           0x1180070000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
37684         {"RAD_REG_DEBUG0"              ,           0x1180070000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
37685         {"RAD_REG_DEBUG1"              ,           0x1180070000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
37686         {"RAD_REG_DEBUG10"             ,           0x1180070000150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
37687         {"RAD_REG_DEBUG11"             ,           0x1180070000158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
37688         {"RAD_REG_DEBUG12"             ,           0x1180070000160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
37689         {"RAD_REG_DEBUG2"              ,           0x1180070000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     770},
37690         {"RAD_REG_DEBUG3"              ,           0x1180070000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
37691         {"RAD_REG_DEBUG4"              ,           0x1180070000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
37692         {"RAD_REG_DEBUG5"              ,           0x1180070000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
37693         {"RAD_REG_DEBUG6"              ,           0x1180070000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
37694         {"RAD_REG_DEBUG7"              ,           0x1180070000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     775},
37695         {"RAD_REG_DEBUG8"              ,           0x1180070000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     776},
37696         {"RAD_REG_DEBUG9"              ,           0x1180070000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     777},
37697         {"RAD_REG_ERROR"               ,           0x1180070000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     778},
37698         {"RAD_REG_INT_MASK"            ,           0x1180070000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     779},
37699         {"RAD_REG_POLYNOMIAL"          ,           0x1180070000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     780},
37700         {"RAD_REG_READ_IDX"            ,           0x1180070000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     781},
37701         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     782},
37702         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     783},
37703         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     784},
37704         {"SMI1_CLK"                    ,           0x1180000001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     784},
37705         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     785},
37706         {"SMI1_CMD"                    ,           0x1180000001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     785},
37707         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     786},
37708         {"SMI1_EN"                     ,           0x1180000001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     786},
37709         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     787},
37710         {"SMI1_RD_DAT"                 ,           0x1180000001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     787},
37711         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     788},
37712         {"SMI1_WR_DAT"                 ,           0x1180000001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     788},
37713         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     789},
37714         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     790},
37715         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     791},
37716         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     792},
37717         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     793},
37718         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     794},
37719         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     795},
37720         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     796},
37721         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     797},
37722         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     798},
37723         {"TRA_BIST_STATUS"             ,           0x11800A8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     799},
37724         {"TRA_CTL"                     ,           0x11800A8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     800},
37725         {"TRA_CYCLES_SINCE"            ,           0x11800A8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     801},
37726         {"TRA_CYCLES_SINCE1"           ,           0x11800A8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     802},
37727         {"TRA_FILT_ADR_ADR"            ,           0x11800A8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     803},
37728         {"TRA_FILT_ADR_MSK"            ,           0x11800A8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     804},
37729         {"TRA_FILT_CMD"                ,           0x11800A8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     805},
37730         {"TRA_FILT_DID"                ,           0x11800A8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     806},
37731         {"TRA_FILT_SID"                ,           0x11800A8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     807},
37732         {"TRA_INT_STATUS"              ,           0x11800A8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     808},
37733         {"TRA_READ_DAT"                ,           0x11800A8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     809},
37734         {"TRA_TRIG0_ADR_ADR"           ,           0x11800A8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     810},
37735         {"TRA_TRIG0_ADR_MSK"           ,           0x11800A80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     811},
37736         {"TRA_TRIG0_CMD"               ,           0x11800A8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     812},
37737         {"TRA_TRIG0_DID"               ,           0x11800A8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     813},
37738         {"TRA_TRIG0_SID"               ,           0x11800A8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     814},
37739         {"TRA_TRIG1_ADR_ADR"           ,           0x11800A80000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     815},
37740         {"TRA_TRIG1_ADR_MSK"           ,           0x11800A80000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     816},
37741         {"TRA_TRIG1_CMD"               ,           0x11800A80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     817},
37742         {"TRA_TRIG1_DID"               ,           0x11800A80000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     818},
37743         {"TRA_TRIG1_SID"               ,           0x11800A80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     819},
37744         {"USBC0_DAINT"                 ,           0x16F0010000818ull,  CVMX_CSR_DB_TYPE_NCB,   32,     820},
37745         {"USBC0_DAINTMSK"              ,           0x16F001000081Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     821},
37746         {"USBC0_DCFG"                  ,           0x16F0010000800ull,  CVMX_CSR_DB_TYPE_NCB,   32,     822},
37747         {"USBC0_DCTL"                  ,           0x16F0010000804ull,  CVMX_CSR_DB_TYPE_NCB,   32,     823},
37748         {"USBC0_DIEPCTL000"            ,           0x16F0010000900ull,  CVMX_CSR_DB_TYPE_NCB,   32,     824},
37749         {"USBC0_DIEPCTL001"            ,           0x16F0010000920ull,  CVMX_CSR_DB_TYPE_NCB,   32,     824},
37750         {"USBC0_DIEPCTL002"            ,           0x16F0010000940ull,  CVMX_CSR_DB_TYPE_NCB,   32,     824},
37751         {"USBC0_DIEPCTL003"            ,           0x16F0010000960ull,  CVMX_CSR_DB_TYPE_NCB,   32,     824},
37752         {"USBC0_DIEPCTL004"            ,           0x16F0010000980ull,  CVMX_CSR_DB_TYPE_NCB,   32,     824},
37753         {"USBC0_DIEPINT000"            ,           0x16F0010000908ull,  CVMX_CSR_DB_TYPE_NCB,   32,     825},
37754         {"USBC0_DIEPINT001"            ,           0x16F0010000928ull,  CVMX_CSR_DB_TYPE_NCB,   32,     825},
37755         {"USBC0_DIEPINT002"            ,           0x16F0010000948ull,  CVMX_CSR_DB_TYPE_NCB,   32,     825},
37756         {"USBC0_DIEPINT003"            ,           0x16F0010000968ull,  CVMX_CSR_DB_TYPE_NCB,   32,     825},
37757         {"USBC0_DIEPINT004"            ,           0x16F0010000988ull,  CVMX_CSR_DB_TYPE_NCB,   32,     825},
37758         {"USBC0_DIEPMSK"               ,           0x16F0010000810ull,  CVMX_CSR_DB_TYPE_NCB,   32,     826},
37759         {"USBC0_DIEPTSIZ000"           ,           0x16F0010000910ull,  CVMX_CSR_DB_TYPE_NCB,   32,     827},
37760         {"USBC0_DIEPTSIZ001"           ,           0x16F0010000930ull,  CVMX_CSR_DB_TYPE_NCB,   32,     827},
37761         {"USBC0_DIEPTSIZ002"           ,           0x16F0010000950ull,  CVMX_CSR_DB_TYPE_NCB,   32,     827},
37762         {"USBC0_DIEPTSIZ003"           ,           0x16F0010000970ull,  CVMX_CSR_DB_TYPE_NCB,   32,     827},
37763         {"USBC0_DIEPTSIZ004"           ,           0x16F0010000990ull,  CVMX_CSR_DB_TYPE_NCB,   32,     827},
37764         {"USBC0_DOEPCTL000"            ,           0x16F0010000B00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     828},
37765         {"USBC0_DOEPCTL001"            ,           0x16F0010000B20ull,  CVMX_CSR_DB_TYPE_NCB,   32,     828},
37766         {"USBC0_DOEPCTL002"            ,           0x16F0010000B40ull,  CVMX_CSR_DB_TYPE_NCB,   32,     828},
37767         {"USBC0_DOEPCTL003"            ,           0x16F0010000B60ull,  CVMX_CSR_DB_TYPE_NCB,   32,     828},
37768         {"USBC0_DOEPCTL004"            ,           0x16F0010000B80ull,  CVMX_CSR_DB_TYPE_NCB,   32,     828},
37769         {"USBC0_DOEPINT000"            ,           0x16F0010000B08ull,  CVMX_CSR_DB_TYPE_NCB,   32,     829},
37770         {"USBC0_DOEPINT001"            ,           0x16F0010000B28ull,  CVMX_CSR_DB_TYPE_NCB,   32,     829},
37771         {"USBC0_DOEPINT002"            ,           0x16F0010000B48ull,  CVMX_CSR_DB_TYPE_NCB,   32,     829},
37772         {"USBC0_DOEPINT003"            ,           0x16F0010000B68ull,  CVMX_CSR_DB_TYPE_NCB,   32,     829},
37773         {"USBC0_DOEPINT004"            ,           0x16F0010000B88ull,  CVMX_CSR_DB_TYPE_NCB,   32,     829},
37774         {"USBC0_DOEPMSK"               ,           0x16F0010000814ull,  CVMX_CSR_DB_TYPE_NCB,   32,     830},
37775         {"USBC0_DOEPTSIZ000"           ,           0x16F0010000B10ull,  CVMX_CSR_DB_TYPE_NCB,   32,     831},
37776         {"USBC0_DOEPTSIZ001"           ,           0x16F0010000B30ull,  CVMX_CSR_DB_TYPE_NCB,   32,     831},
37777         {"USBC0_DOEPTSIZ002"           ,           0x16F0010000B50ull,  CVMX_CSR_DB_TYPE_NCB,   32,     831},
37778         {"USBC0_DOEPTSIZ003"           ,           0x16F0010000B70ull,  CVMX_CSR_DB_TYPE_NCB,   32,     831},
37779         {"USBC0_DOEPTSIZ004"           ,           0x16F0010000B90ull,  CVMX_CSR_DB_TYPE_NCB,   32,     831},
37780         {"USBC0_DPTXFSIZ001"           ,           0x16F0010000104ull,  CVMX_CSR_DB_TYPE_NCB,   32,     832},
37781         {"USBC0_DPTXFSIZ002"           ,           0x16F0010000108ull,  CVMX_CSR_DB_TYPE_NCB,   32,     832},
37782         {"USBC0_DPTXFSIZ003"           ,           0x16F001000010Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     832},
37783         {"USBC0_DPTXFSIZ004"           ,           0x16F0010000110ull,  CVMX_CSR_DB_TYPE_NCB,   32,     832},
37784         {"USBC0_DSTS"                  ,           0x16F0010000808ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
37785         {"USBC0_DTKNQR1"               ,           0x16F0010000820ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
37786         {"USBC0_DTKNQR2"               ,           0x16F0010000824ull,  CVMX_CSR_DB_TYPE_NCB,   32,     835},
37787         {"USBC0_DTKNQR3"               ,           0x16F0010000830ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
37788         {"USBC0_DTKNQR4"               ,           0x16F0010000834ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
37789         {"USBC0_GAHBCFG"               ,           0x16F0010000008ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
37790         {"USBC0_GHWCFG1"               ,           0x16F0010000044ull,  CVMX_CSR_DB_TYPE_NCB,   32,     839},
37791         {"USBC0_GHWCFG2"               ,           0x16F0010000048ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
37792         {"USBC0_GHWCFG3"               ,           0x16F001000004Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     841},
37793         {"USBC0_GHWCFG4"               ,           0x16F0010000050ull,  CVMX_CSR_DB_TYPE_NCB,   32,     842},
37794         {"USBC0_GINTMSK"               ,           0x16F0010000018ull,  CVMX_CSR_DB_TYPE_NCB,   32,     843},
37795         {"USBC0_GINTSTS"               ,           0x16F0010000014ull,  CVMX_CSR_DB_TYPE_NCB,   32,     844},
37796         {"USBC0_GNPTXFSIZ"             ,           0x16F0010000028ull,  CVMX_CSR_DB_TYPE_NCB,   32,     845},
37797         {"USBC0_GNPTXSTS"              ,           0x16F001000002Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     846},
37798         {"USBC0_GOTGCTL"               ,           0x16F0010000000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     847},
37799         {"USBC0_GOTGINT"               ,           0x16F0010000004ull,  CVMX_CSR_DB_TYPE_NCB,   32,     848},
37800         {"USBC0_GRSTCTL"               ,           0x16F0010000010ull,  CVMX_CSR_DB_TYPE_NCB,   32,     849},
37801         {"USBC0_GRXFSIZ"               ,           0x16F0010000024ull,  CVMX_CSR_DB_TYPE_NCB,   32,     850},
37802         {"USBC0_GRXSTSPD"              ,           0x16F0010040020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     851},
37803         {"USBC0_GRXSTSPH"              ,           0x16F0010000020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     852},
37804         {"USBC0_GRXSTSRD"              ,           0x16F001004001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     853},
37805         {"USBC0_GRXSTSRH"              ,           0x16F001000001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     854},
37806         {"USBC0_GSNPSID"               ,           0x16F0010000040ull,  CVMX_CSR_DB_TYPE_NCB,   32,     855},
37807         {"USBC0_GUSBCFG"               ,           0x16F001000000Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     856},
37808         {"USBC0_HAINT"                 ,           0x16F0010000414ull,  CVMX_CSR_DB_TYPE_NCB,   32,     857},
37809         {"USBC0_HAINTMSK"              ,           0x16F0010000418ull,  CVMX_CSR_DB_TYPE_NCB,   32,     858},
37810         {"USBC0_HCCHAR000"             ,           0x16F0010000500ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
37811         {"USBC0_HCCHAR001"             ,           0x16F0010000520ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
37812         {"USBC0_HCCHAR002"             ,           0x16F0010000540ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
37813         {"USBC0_HCCHAR003"             ,           0x16F0010000560ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
37814         {"USBC0_HCCHAR004"             ,           0x16F0010000580ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
37815         {"USBC0_HCCHAR005"             ,           0x16F00100005A0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
37816         {"USBC0_HCCHAR006"             ,           0x16F00100005C0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
37817         {"USBC0_HCCHAR007"             ,           0x16F00100005E0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
37818         {"USBC0_HCFG"                  ,           0x16F0010000400ull,  CVMX_CSR_DB_TYPE_NCB,   32,     860},
37819         {"USBC0_HCINT000"              ,           0x16F0010000508ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
37820         {"USBC0_HCINT001"              ,           0x16F0010000528ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
37821         {"USBC0_HCINT002"              ,           0x16F0010000548ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
37822         {"USBC0_HCINT003"              ,           0x16F0010000568ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
37823         {"USBC0_HCINT004"              ,           0x16F0010000588ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
37824         {"USBC0_HCINT005"              ,           0x16F00100005A8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
37825         {"USBC0_HCINT006"              ,           0x16F00100005C8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
37826         {"USBC0_HCINT007"              ,           0x16F00100005E8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
37827         {"USBC0_HCINTMSK000"           ,           0x16F001000050Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
37828         {"USBC0_HCINTMSK001"           ,           0x16F001000052Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
37829         {"USBC0_HCINTMSK002"           ,           0x16F001000054Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
37830         {"USBC0_HCINTMSK003"           ,           0x16F001000056Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
37831         {"USBC0_HCINTMSK004"           ,           0x16F001000058Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
37832         {"USBC0_HCINTMSK005"           ,           0x16F00100005ACull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
37833         {"USBC0_HCINTMSK006"           ,           0x16F00100005CCull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
37834         {"USBC0_HCINTMSK007"           ,           0x16F00100005ECull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
37835         {"USBC0_HCSPLT000"             ,           0x16F0010000504ull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
37836         {"USBC0_HCSPLT001"             ,           0x16F0010000524ull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
37837         {"USBC0_HCSPLT002"             ,           0x16F0010000544ull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
37838         {"USBC0_HCSPLT003"             ,           0x16F0010000564ull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
37839         {"USBC0_HCSPLT004"             ,           0x16F0010000584ull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
37840         {"USBC0_HCSPLT005"             ,           0x16F00100005A4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
37841         {"USBC0_HCSPLT006"             ,           0x16F00100005C4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
37842         {"USBC0_HCSPLT007"             ,           0x16F00100005E4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
37843         {"USBC0_HCTSIZ000"             ,           0x16F0010000510ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
37844         {"USBC0_HCTSIZ001"             ,           0x16F0010000530ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
37845         {"USBC0_HCTSIZ002"             ,           0x16F0010000550ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
37846         {"USBC0_HCTSIZ003"             ,           0x16F0010000570ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
37847         {"USBC0_HCTSIZ004"             ,           0x16F0010000590ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
37848         {"USBC0_HCTSIZ005"             ,           0x16F00100005B0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
37849         {"USBC0_HCTSIZ006"             ,           0x16F00100005D0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
37850         {"USBC0_HCTSIZ007"             ,           0x16F00100005F0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
37851         {"USBC0_HFIR"                  ,           0x16F0010000404ull,  CVMX_CSR_DB_TYPE_NCB,   32,     865},
37852         {"USBC0_HFNUM"                 ,           0x16F0010000408ull,  CVMX_CSR_DB_TYPE_NCB,   32,     866},
37853         {"USBC0_HPRT"                  ,           0x16F0010000440ull,  CVMX_CSR_DB_TYPE_NCB,   32,     867},
37854         {"USBC0_HPTXFSIZ"              ,           0x16F0010000100ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
37855         {"USBC0_HPTXSTS"               ,           0x16F0010000410ull,  CVMX_CSR_DB_TYPE_NCB,   32,     869},
37856         {"USBC0_NPTXDFIFO000"          ,           0x16F0010001000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
37857         {"USBC0_NPTXDFIFO001"          ,           0x16F0010002000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
37858         {"USBC0_NPTXDFIFO002"          ,           0x16F0010003000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
37859         {"USBC0_NPTXDFIFO003"          ,           0x16F0010004000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
37860         {"USBC0_NPTXDFIFO004"          ,           0x16F0010005000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
37861         {"USBC0_NPTXDFIFO005"          ,           0x16F0010006000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
37862         {"USBC0_NPTXDFIFO006"          ,           0x16F0010007000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
37863         {"USBC0_NPTXDFIFO007"          ,           0x16F0010008000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
37864         {"USBC0_PCGCCTL"               ,           0x16F0010000E00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
37865         {"USBN0_BIST_STATUS"           ,           0x11800680007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     872},
37866         {"USBN0_CLK_CTL"               ,           0x1180068000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     873},
37867         {"USBN0_CTL_STATUS"            ,           0x16F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     874},
37868         {"USBN0_DMA0_INB_CHN0"         ,           0x16F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     875},
37869         {"USBN0_DMA0_INB_CHN1"         ,           0x16F0000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     876},
37870         {"USBN0_DMA0_INB_CHN2"         ,           0x16F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     877},
37871         {"USBN0_DMA0_INB_CHN3"         ,           0x16F0000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     878},
37872         {"USBN0_DMA0_INB_CHN4"         ,           0x16F0000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     879},
37873         {"USBN0_DMA0_INB_CHN5"         ,           0x16F0000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     880},
37874         {"USBN0_DMA0_INB_CHN6"         ,           0x16F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     881},
37875         {"USBN0_DMA0_INB_CHN7"         ,           0x16F0000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     882},
37876         {"USBN0_DMA0_OUTB_CHN0"        ,           0x16F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     883},
37877         {"USBN0_DMA0_OUTB_CHN1"        ,           0x16F0000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     884},
37878         {"USBN0_DMA0_OUTB_CHN2"        ,           0x16F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     885},
37879         {"USBN0_DMA0_OUTB_CHN3"        ,           0x16F0000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     886},
37880         {"USBN0_DMA0_OUTB_CHN4"        ,           0x16F0000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     887},
37881         {"USBN0_DMA0_OUTB_CHN5"        ,           0x16F0000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     888},
37882         {"USBN0_DMA0_OUTB_CHN6"        ,           0x16F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     889},
37883         {"USBN0_DMA0_OUTB_CHN7"        ,           0x16F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     890},
37884         {"USBN0_DMA_TEST"              ,           0x16F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     891},
37885         {"USBN0_INT_ENB"               ,           0x1180068000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     892},
37886         {"USBN0_INT_SUM"               ,           0x1180068000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     893},
37887         {"USBN0_USBP_CTL_STATUS"       ,           0x1180068000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     894},
37888         {"ZIP_CMD_BIST_RESULT"         ,           0x1180038000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     895},
37889         {"ZIP_CMD_BUF"                 ,           0x1180038000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     896},
37890         {"ZIP_CMD_CTL"                 ,           0x1180038000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     897},
37891         {"ZIP_CONSTANTS"               ,           0x11800380000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     898},
37892         {"ZIP_DEBUG0"                  ,           0x1180038000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     899},
37893         {"ZIP_ERROR"                   ,           0x1180038000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     900},
37894         {"ZIP_INT_MASK"                ,           0x1180038000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     901},
37895         {NULL,0,0,0,0}
37896 };
37897 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xxp1[] = {
37898         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
37899         {"RESERVED_0_1"                ,        0,      2,      0,      "RAZ",  0,      0,      0ull,   0ull},
37900         {"OUT_OVR"                     ,        2,      1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
37901         {"RESERVED_3_21"               ,        3,      19,     0,      "RAZ",  0,      0,      0ull,   0ull},
37902         {"LOSTSTAT"                    ,        22,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
37903         {"RESERVED_23_25"              ,        23,     3,      0,      "RAZ",  0,      0,      0ull,   0ull},
37904         {"STATOVR"                     ,        26,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
37905         {"RESERVED_27_31"              ,        27,     5,      0,      "RAZ",  0,      0,      0ull,   0ull},
37906         {"OVRFLW"                      ,        32,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
37907         {"TXPOP"                       ,        33,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
37908         {"TXPSH"                       ,        34,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
37909         {"RESERVED_35_63"              ,        35,     29,     0,      "RAZ",  1,      1,      0,      0},
37910         {"STATUS"                      ,        0,      10,     1,      "RO",   0,      0,      0ull,   0ull},
37911         {"RESERVED_10_63"              ,        10,     54,     1,      "RAZ",  1,      1,      0,      0},
37912         {"NCTL"                        ,        0,      5,      2,      "R/W",  0,      1,      16ull,  0},
37913         {"RESERVED_5_7"                ,        5,      3,      2,      "RAZ",  1,      1,      0,      0},
37914         {"PCTL"                        ,        8,      5,      2,      "R/W",  0,      1,      16ull,  0},
37915         {"RESERVED_13_15"              ,        13,     3,      2,      "RAZ",  1,      1,      0,      0},
37916         {"BYP_EN"                      ,        16,     1,      2,      "R/W",  0,      0,      0ull,   0ull},
37917         {"RESERVED_17_63"              ,        17,     47,     2,      "RAZ",  1,      1,      0,      0},
37918         {"RESERVED_0_0"                ,        0,      1,      3,      "RAZ",  1,      1,      0,      0},
37919         {"EN"                          ,        1,      1,      3,      "R/W",  0,      0,      0ull,   1ull},
37920         {"RESERVED_2_63"               ,        2,      62,     3,      "RAZ",  1,      1,      0,      0},
37921         {"EN"                          ,        0,      1,      4,      "R/W",  0,      1,      0ull,   0},
37922         {"SPEED"                       ,        1,      1,      4,      "RO",   0,      0,      0ull,   0ull},
37923         {"DUPLEX"                      ,        2,      1,      4,      "R/W",  0,      1,      1ull,   0},
37924         {"SLOTTIME"                    ,        3,      1,      4,      "RO",   0,      0,      0ull,   0ull},
37925         {"RX_EN"                       ,        4,      1,      4,      "R/W",  0,      1,      0ull,   0},
37926         {"TX_EN"                       ,        5,      1,      4,      "R/W",  0,      1,      0ull,   0},
37927         {"RESERVED_6_63"               ,        6,      58,     4,      "RAZ",  1,      1,      0,      0},
37928         {"ADR"                         ,        0,      64,     5,      "R/W",  0,      1,      0ull,   0},
37929         {"ADR"                         ,        0,      64,     6,      "R/W",  0,      1,      0ull,   0},
37930         {"ADR"                         ,        0,      64,     7,      "R/W",  0,      1,      0ull,   0},
37931         {"ADR"                         ,        0,      64,     8,      "R/W",  0,      1,      0ull,   0},
37932         {"ADR"                         ,        0,      64,     9,      "R/W",  0,      1,      0ull,   0},
37933         {"ADR"                         ,        0,      64,     10,     "R/W",  0,      1,      0ull,   0},
37934         {"EN"                          ,        0,      8,      11,     "R/W",  0,      1,      0ull,   0},
37935         {"RESERVED_8_63"               ,        8,      56,     11,     "RAZ",  1,      1,      0,      0},
37936         {"BCST"                        ,        0,      1,      12,     "R/W",  0,      1,      1ull,   0},
37937         {"MCST"                        ,        1,      2,      12,     "R/W",  0,      1,      0ull,   0},
37938         {"CAM_MODE"                    ,        3,      1,      12,     "R/W",  0,      1,      0ull,   0},
37939         {"RESERVED_4_63"               ,        4,      60,     12,     "RAZ",  1,      1,      0,      0},
37940         {"CNT"                         ,        0,      5,      13,     "R/W",  0,      0,      24ull,  24ull},
37941         {"RESERVED_5_63"               ,        5,      59,     13,     "RAZ",  1,      1,      0,      0},
37942         {"MINERR"                      ,        0,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
37943         {"RESERVED_1_1"                ,        1,      1,      14,     "RAZ",  0,      0,      0ull,   0ull},
37944         {"MAXERR"                      ,        2,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
37945         {"JABBER"                      ,        3,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
37946         {"FCSERR"                      ,        4,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
37947         {"ALNERR"                      ,        5,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
37948         {"LENERR"                      ,        6,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
37949         {"RCVERR"                      ,        7,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
37950         {"SKPERR"                      ,        8,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
37951         {"RESERVED_9_63"               ,        9,      55,     14,     "RAZ",  1,      1,      0,      0},
37952         {"PRE_CHK"                     ,        0,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
37953         {"PRE_STRP"                    ,        1,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
37954         {"CTL_DRP"                     ,        2,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
37955         {"CTL_BCK"                     ,        3,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
37956         {"CTL_MCST"                    ,        4,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
37957         {"CTL_SMAC"                    ,        5,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
37958         {"PRE_FREE"                    ,        6,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
37959         {"VLAN_LEN"                    ,        7,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
37960         {"PAD_LEN"                     ,        8,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
37961         {"PRE_ALIGN"                   ,        9,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
37962         {"RESERVED_10_63"              ,        10,     54,     15,     "RAZ",  1,      1,      0,      0},
37963         {"LEN"                         ,        0,      16,     16,     "R/W",  0,      0,      1536ull,        1536ull},
37964         {"RESERVED_16_63"              ,        16,     48,     16,     "RAZ",  1,      1,      0,      0},
37965         {"LEN"                         ,        0,      16,     17,     "R/W",  0,      0,      64ull,  64ull},
37966         {"RESERVED_16_63"              ,        16,     48,     17,     "RAZ",  1,      1,      0,      0},
37967         {"IFG"                         ,        0,      4,      18,     "R/W",  0,      0,      12ull,  12ull},
37968         {"RESERVED_4_63"               ,        4,      60,     18,     "RAZ",  1,      1,      0,      0},
37969         {"MINERR"                      ,        0,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
37970         {"RESERVED_1_1"                ,        1,      1,      19,     "RAZ",  1,      1,      0,      0},
37971         {"MAXERR"                      ,        2,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
37972         {"JABBER"                      ,        3,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
37973         {"FCSERR"                      ,        4,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
37974         {"ALNERR"                      ,        5,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
37975         {"LENERR"                      ,        6,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
37976         {"RCVERR"                      ,        7,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
37977         {"SKPERR"                      ,        8,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
37978         {"RESERVED_9_9"                ,        9,      1,      19,     "RAZ",  1,      1,      0,      0},
37979         {"OVRERR"                      ,        10,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
37980         {"PCTERR"                      ,        11,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
37981         {"RSVERR"                      ,        12,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
37982         {"FALERR"                      ,        13,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
37983         {"COLDET"                      ,        14,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
37984         {"IFGERR"                      ,        15,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
37985         {"RESERVED_16_18"              ,        16,     3,      19,     "RAZ",  1,      1,      0,      0},
37986         {"PAUSE_DRP"                   ,        19,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
37987         {"RESERVED_20_63"              ,        20,     44,     19,     "RAZ",  1,      1,      0,      0},
37988         {"MINERR"                      ,        0,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
37989         {"RESERVED_1_1"                ,        1,      1,      20,     "RAZ",  0,      0,      0ull,   0ull},
37990         {"MAXERR"                      ,        2,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
37991         {"JABBER"                      ,        3,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
37992         {"FCSERR"                      ,        4,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
37993         {"ALNERR"                      ,        5,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
37994         {"LENERR"                      ,        6,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
37995         {"RCVERR"                      ,        7,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
37996         {"SKPERR"                      ,        8,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
37997         {"RESERVED_9_9"                ,        9,      1,      20,     "RAZ",  0,      0,      0ull,   0ull},
37998         {"OVRERR"                      ,        10,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
37999         {"PCTERR"                      ,        11,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
38000         {"RSVERR"                      ,        12,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
38001         {"FALERR"                      ,        13,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
38002         {"COLDET"                      ,        14,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
38003         {"IFGERR"                      ,        15,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
38004         {"RESERVED_16_18"              ,        16,     3,      20,     "RAZ",  0,      0,      0ull,   0ull},
38005         {"PAUSE_DRP"                   ,        19,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
38006         {"RESERVED_20_63"              ,        20,     44,     20,     "RAZ",  1,      1,      0,      0},
38007         {"CNT"                         ,        0,      16,     21,     "R/W",  0,      0,      10240ull,       10240ull},
38008         {"RESERVED_16_63"              ,        16,     48,     21,     "RAZ",  1,      1,      0,      0},
38009         {"STATUS"                      ,        0,      16,     22,     "R/W1C",        0,      1,      0ull,   0},
38010         {"RESERVED_16_63"              ,        16,     48,     22,     "RAZ",  1,      1,      0,      0},
38011         {"RD_CLR"                      ,        0,      1,      23,     "R/W",  0,      0,      0ull,   0ull},
38012         {"RESERVED_1_63"               ,        1,      63,     23,     "RAZ",  1,      1,      0,      0},
38013         {"CNT"                         ,        0,      48,     24,     "RC/W", 0,      1,      0ull,   0},
38014         {"RESERVED_48_63"              ,        48,     16,     24,     "RAZ",  1,      1,      0,      0},
38015         {"CNT"                         ,        0,      48,     25,     "RC/W", 0,      1,      0ull,   0},
38016         {"RESERVED_48_63"              ,        48,     16,     25,     "RAZ",  1,      1,      0,      0},
38017         {"CNT"                         ,        0,      48,     26,     "RC/W", 0,      1,      0ull,   0},
38018         {"RESERVED_48_63"              ,        48,     16,     26,     "RAZ",  1,      1,      0,      0},
38019         {"CNT"                         ,        0,      48,     27,     "RC/W", 0,      1,      0ull,   0},
38020         {"RESERVED_48_63"              ,        48,     16,     27,     "RAZ",  1,      1,      0,      0},
38021         {"CNT"                         ,        0,      32,     28,     "RC/W", 0,      1,      0ull,   0},
38022         {"RESERVED_32_63"              ,        32,     32,     28,     "RAZ",  1,      1,      0,      0},
38023         {"CNT"                         ,        0,      32,     29,     "RC/W", 0,      1,      0ull,   0},
38024         {"RESERVED_32_63"              ,        32,     32,     29,     "RAZ",  1,      1,      0,      0},
38025         {"CNT"                         ,        0,      32,     30,     "RC/W", 0,      1,      0ull,   0},
38026         {"RESERVED_32_63"              ,        32,     32,     30,     "RAZ",  1,      1,      0,      0},
38027         {"CNT"                         ,        0,      32,     31,     "RC/W", 0,      1,      0ull,   0},
38028         {"RESERVED_32_63"              ,        32,     32,     31,     "RAZ",  1,      1,      0,      0},
38029         {"CNT"                         ,        0,      32,     32,     "RC/W", 0,      1,      0ull,   0},
38030         {"RESERVED_32_63"              ,        32,     32,     32,     "RAZ",  1,      1,      0,      0},
38031         {"LEN"                         ,        0,      7,      33,     "R/W",  0,      0,      0ull,   0ull},
38032         {"RESERVED_7_7"                ,        7,      1,      33,     "RAZ",  1,      1,      0,      0},
38033         {"FCSSEL"                      ,        8,      1,      33,     "R/W",  0,      0,      0ull,   0ull},
38034         {"RESERVED_9_63"               ,        9,      55,     33,     "RAZ",  1,      1,      0,      0},
38035         {"MARK"                        ,        0,      6,      34,     "R/W",  0,      0,      2ull,   2ull},
38036         {"RESERVED_6_63"               ,        6,      58,     34,     "RAZ",  1,      1,      0,      0},
38037         {"MARK"                        ,        0,      6,      35,     "R/W",  0,      0,      16ull,  16ull},
38038         {"RESERVED_6_63"               ,        6,      58,     35,     "RAZ",  1,      1,      0,      0},
38039         {"MARK"                        ,        0,      9,      36,     "R/W",  0,      0,      32ull,  32ull},
38040         {"RESERVED_9_63"               ,        9,      55,     36,     "RAZ",  1,      1,      0,      0},
38041         {"COMMIT"                      ,        0,      1,      37,     "RO",   0,      0,      0ull,   0ull},
38042         {"RESERVED_1_15"               ,        1,      15,     37,     "RAZ",  1,      1,      0,      0},
38043         {"DROP"                        ,        16,     1,      37,     "RO",   0,      0,      0ull,   0ull},
38044         {"RESERVED_17_63"              ,        17,     47,     37,     "RAZ",  1,      1,      0,      0},
38045         {"RX"                          ,        0,      1,      38,     "RC",   0,      0,      0ull,   0ull},
38046         {"RESERVED_1_3"                ,        1,      3,      38,     "RAZ",  1,      1,      0,      0},
38047         {"TX"                          ,        4,      1,      38,     "RC",   0,      0,      0ull,   0ull},
38048         {"RESERVED_5_63"               ,        5,      59,     38,     "RAZ",  1,      1,      0,      0},
38049         {"SMAC"                        ,        0,      48,     39,     "R/W",  0,      1,      0ull,   0},
38050         {"RESERVED_48_63"              ,        48,     16,     39,     "RAZ",  1,      1,      0,      0},
38051         {"CNT"                         ,        0,      16,     40,     "R/W1C",        0,      0,      0ull,   0ull},
38052         {"BP"                          ,        16,     1,      40,     "RO",   0,      0,      0ull,   0ull},
38053         {"RESERVED_17_63"              ,        17,     47,     40,     "RAZ",  1,      1,      0,      0},
38054         {"PREAMBLE"                    ,        0,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
38055         {"PAD"                         ,        1,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
38056         {"FCS"                         ,        2,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
38057         {"FORCE_FCS"                   ,        3,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
38058         {"RESERVED_4_63"               ,        4,      60,     41,     "RAZ",  1,      1,      0,      0},
38059         {"XSCOL_EN"                    ,        0,      1,      42,     "R/W",  0,      0,      1ull,   1ull},
38060         {"XSDEF_EN"                    ,        1,      1,      42,     "R/W",  0,      0,      1ull,   1ull},
38061         {"RESERVED_2_63"               ,        2,      62,     42,     "RAZ",  1,      1,      0,      0},
38062         {"MIN_SIZE"                    ,        0,      8,      43,     "R/W",  0,      0,      59ull,  59ull},
38063         {"RESERVED_8_63"               ,        8,      56,     43,     "RAZ",  1,      1,      0,      0},
38064         {"INTERVAL"                    ,        0,      16,     44,     "R/W",  0,      1,      16ull,  0},
38065         {"RESERVED_16_63"              ,        16,     48,     44,     "RAZ",  1,      1,      0,      0},
38066         {"TIME"                        ,        0,      16,     45,     "R/W",  0,      1,      96ull,  0},
38067         {"RESERVED_16_63"              ,        16,     48,     45,     "RAZ",  1,      1,      0,      0},
38068         {"TIME"                        ,        0,      16,     46,     "RO",   1,      1,      0,      0},
38069         {"RESERVED_16_63"              ,        16,     48,     46,     "RAZ",  1,      1,      0,      0},
38070         {"SEND"                        ,        0,      1,      47,     "R/W",  0,      0,      1ull,   1ull},
38071         {"RESERVED_1_63"               ,        1,      63,     47,     "RAZ",  1,      1,      0,      0},
38072         {"TIME"                        ,        0,      16,     48,     "R/W",  0,      1,      0ull,   0},
38073         {"RESERVED_16_63"              ,        16,     48,     48,     "RAZ",  1,      1,      0,      0},
38074         {"XSCOL"                       ,        0,      32,     49,     "RC/W", 0,      1,      0ull,   0},
38075         {"XSDEF"                       ,        32,     32,     49,     "RC/W", 0,      1,      0ull,   0},
38076         {"MCOL"                        ,        0,      32,     50,     "RC/W", 0,      1,      0ull,   0},
38077         {"SCOL"                        ,        32,     32,     50,     "RC/W", 0,      1,      0ull,   0},
38078         {"OCTS"                        ,        0,      48,     51,     "RC/W", 0,      1,      0ull,   0},
38079         {"RESERVED_48_63"              ,        48,     16,     51,     "RAZ",  1,      1,      0,      0},
38080         {"PKTS"                        ,        0,      32,     52,     "RC/W", 0,      1,      0ull,   0},
38081         {"RESERVED_32_63"              ,        32,     32,     52,     "RAZ",  1,      1,      0,      0},
38082         {"HIST0"                       ,        0,      32,     53,     "RC/W", 0,      1,      0ull,   0},
38083         {"HIST1"                       ,        32,     32,     53,     "RC/W", 0,      1,      0ull,   0},
38084         {"HIST2"                       ,        0,      32,     54,     "RC/W", 0,      1,      0ull,   0},
38085         {"HIST3"                       ,        32,     32,     54,     "RC/W", 0,      1,      0ull,   0},
38086         {"HIST4"                       ,        0,      32,     55,     "RC/W", 0,      1,      0ull,   0},
38087         {"HIST5"                       ,        32,     32,     55,     "RC/W", 0,      1,      0ull,   0},
38088         {"HIST6"                       ,        0,      32,     56,     "RC/W", 0,      1,      0ull,   0},
38089         {"HIST7"                       ,        32,     32,     56,     "RC/W", 0,      1,      0ull,   0},
38090         {"BCST"                        ,        0,      32,     57,     "RC/W", 0,      1,      0ull,   0},
38091         {"MCST"                        ,        32,     32,     57,     "RC/W", 0,      1,      0ull,   0},
38092         {"CTL"                         ,        0,      32,     58,     "RC/W", 0,      1,      0ull,   0},
38093         {"UNDFLW"                      ,        32,     32,     58,     "RC/W", 0,      1,      0ull,   0},
38094         {"RD_CLR"                      ,        0,      1,      59,     "R/W",  0,      0,      0ull,   0ull},
38095         {"RESERVED_1_63"               ,        1,      63,     59,     "RAZ",  1,      1,      0,      0},
38096         {"CNT"                         ,        0,      6,      60,     "R/W",  0,      0,      16ull,  16ull},
38097         {"RESERVED_6_63"               ,        6,      58,     60,     "RAZ",  1,      1,      0,      0},
38098         {"BP"                          ,        0,      1,      61,     "RO",   0,      0,      0ull,   0ull},
38099         {"RESERVED_1_63"               ,        1,      63,     61,     "RAZ",  1,      1,      0,      0},
38100         {"LIMIT"                       ,        0,      5,      62,     "R/W",  0,      0,      16ull,  16ull},
38101         {"RESERVED_5_63"               ,        5,      59,     62,     "RAZ",  1,      1,      0,      0},
38102         {"IFG1"                        ,        0,      4,      63,     "R/W",  0,      1,      8ull,   0},
38103         {"IFG2"                        ,        4,      4,      63,     "R/W",  0,      1,      4ull,   0},
38104         {"RESERVED_8_63"               ,        8,      56,     63,     "RAZ",  1,      1,      0,      0},
38105         {"PKO_NXA"                     ,        0,      1,      64,     "R/W",  0,      0,      0ull,   0ull},
38106         {"RESERVED_1_1"                ,        1,      1,      64,     "RAZ",  0,      0,      0ull,   0ull},
38107         {"UNDFLW"                      ,        2,      1,      64,     "R/W",  0,      0,      0ull,   0ull},
38108         {"RESERVED_3_7"                ,        3,      5,      64,     "RAZ",  0,      0,      0ull,   0ull},
38109         {"XSCOL"                       ,        8,      1,      64,     "R/W",  0,      0,      0ull,   0ull},
38110         {"RESERVED_9_11"               ,        9,      3,      64,     "RAZ",  0,      0,      0ull,   0ull},
38111         {"XSDEF"                       ,        12,     1,      64,     "R/W",  0,      0,      0ull,   0ull},
38112         {"RESERVED_13_15"              ,        13,     3,      64,     "RAZ",  0,      0,      0ull,   0ull},
38113         {"LATE_COL"                    ,        16,     1,      64,     "R/W",  0,      0,      0ull,   0ull},
38114         {"RESERVED_17_63"              ,        17,     47,     64,     "RAZ",  0,      0,      0ull,   0ull},
38115         {"PKO_NXA"                     ,        0,      1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
38116         {"RESERVED_1_1"                ,        1,      1,      65,     "RAZ",  0,      0,      0ull,   0ull},
38117         {"UNDFLW"                      ,        2,      1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
38118         {"RESERVED_3_7"                ,        3,      5,      65,     "RAZ",  0,      0,      0ull,   0ull},
38119         {"XSCOL"                       ,        8,      1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
38120         {"RESERVED_9_11"               ,        9,      3,      65,     "RAZ",  0,      0,      0ull,   0ull},
38121         {"XSDEF"                       ,        12,     1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
38122         {"RESERVED_13_15"              ,        13,     3,      65,     "RAZ",  0,      0,      0ull,   0ull},
38123         {"LATE_COL"                    ,        16,     1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
38124         {"RESERVED_17_63"              ,        17,     47,     65,     "RAZ",  0,      0,      0ull,   0ull},
38125         {"JAM"                         ,        0,      8,      66,     "R/W",  0,      1,      238ull, 0},
38126         {"RESERVED_8_63"               ,        8,      56,     66,     "RAZ",  1,      1,      0,      0},
38127         {"LFSR"                        ,        0,      16,     67,     "R/W",  0,      1,      65535ull,       0},
38128         {"RESERVED_16_63"              ,        16,     48,     67,     "RAZ",  1,      1,      0,      0},
38129         {"IGN_FULL"                    ,        0,      1,      68,     "R/W",  0,      0,      0ull,   0ull},
38130         {"RESERVED_1_3"                ,        1,      3,      68,     "RAZ",  0,      0,      0ull,   0ull},
38131         {"BP"                          ,        4,      1,      68,     "R/W",  0,      0,      0ull,   0ull},
38132         {"RESERVED_5_7"                ,        5,      3,      68,     "RAZ",  0,      0,      0ull,   0ull},
38133         {"EN"                          ,        8,      1,      68,     "R/W",  0,      0,      0ull,   0ull},
38134         {"RESERVED_9_63"               ,        9,      55,     68,     "RAZ",  0,      0,      0ull,   0ull},
38135         {"DMAC"                        ,        0,      48,     69,     "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
38136         {"RESERVED_48_63"              ,        48,     16,     69,     "RAZ",  1,      1,      0,      0},
38137         {"TYPE"                        ,        0,      16,     70,     "R/W",  0,      0,      34824ull,       34824ull},
38138         {"RESERVED_16_63"              ,        16,     48,     70,     "RAZ",  1,      1,      0,      0},
38139         {"BIST"                        ,        0,      4,      71,     "RO",   0,      0,      0ull,   0ull},
38140         {"RESERVED_4_63"               ,        4,      60,     71,     "RAZ",  1,      1,      0,      0},
38141         {"DINT"                        ,        0,      12,     72,     "WO",   0,      0,      0ull,   0ull},
38142         {"RESERVED_12_63"              ,        12,     52,     72,     "RAZ",  1,      1,      0,      0},
38143         {"FUSE"                        ,        0,      12,     73,     "RO",   1,      1,      0,      0},
38144         {"RESERVED_12_63"              ,        12,     52,     73,     "RAZ",  1,      1,      0,      0},
38145         {"GSTOP"                       ,        0,      1,      74,     "R/W",  0,      0,      0ull,   0ull},
38146         {"RESERVED_1_63"               ,        1,      63,     74,     "RAZ",  1,      1,      0,      0},
38147         {"WORKQ"                       ,        0,      16,     75,     "R/W",  0,      0,      0ull,   0ull},
38148         {"GPIO"                        ,        16,     16,     75,     "R/W",  0,      0,      0ull,   0ull},
38149         {"MBOX"                        ,        32,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
38150         {"UART"                        ,        34,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
38151         {"PCI_INT"                     ,        36,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
38152         {"PCI_MSI"                     ,        40,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
38153         {"RESERVED_44_44"              ,        44,     1,      75,     "RAZ",  1,      1,      0,      0},
38154         {"TWSI"                        ,        45,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38155         {"RML"                         ,        46,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38156         {"TRACE"                       ,        47,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38157         {"GMX_DRP"                     ,        48,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
38158         {"IPD_DRP"                     ,        50,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38159         {"KEY_ZERO"                    ,        51,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38160         {"TIMER"                       ,        52,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
38161         {"USB"                         ,        56,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38162         {"RESERVED_57_58"              ,        57,     2,      75,     "RAZ",  0,      0,      0ull,   0ull},
38163         {"TWSI2"                       ,        59,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38164         {"POWIQ"                       ,        60,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38165         {"IPDPPTHR"                    ,        61,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38166         {"MII"                         ,        62,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38167         {"BOOTDMA"                     ,        63,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
38168         {"WDOG"                        ,        0,      12,     76,     "R/W",  0,      0,      0ull,   0ull},
38169         {"RESERVED_12_63"              ,        12,     52,     76,     "RAZ",  1,      1,      0,      0},
38170         {"WORKQ"                       ,        0,      16,     77,     "R/W",  0,      0,      0ull,   0ull},
38171         {"GPIO"                        ,        16,     16,     77,     "R/W",  0,      0,      0ull,   0ull},
38172         {"MBOX"                        ,        32,     2,      77,     "R/W",  0,      0,      0ull,   0ull},
38173         {"UART"                        ,        34,     2,      77,     "R/W",  0,      0,      0ull,   0ull},
38174         {"PCI_INT"                     ,        36,     4,      77,     "R/W",  0,      0,      0ull,   0ull},
38175         {"PCI_MSI"                     ,        40,     4,      77,     "R/W",  0,      0,      0ull,   0ull},
38176         {"RESERVED_44_44"              ,        44,     1,      77,     "RAZ",  1,      1,      0,      0},
38177         {"TWSI"                        ,        45,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38178         {"RML"                         ,        46,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38179         {"TRACE"                       ,        47,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38180         {"GMX_DRP"                     ,        48,     2,      77,     "R/W",  0,      0,      0ull,   0ull},
38181         {"IPD_DRP"                     ,        50,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38182         {"KEY_ZERO"                    ,        51,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38183         {"TIMER"                       ,        52,     4,      77,     "R/W",  0,      0,      0ull,   0ull},
38184         {"USB"                         ,        56,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38185         {"RESERVED_57_58"              ,        57,     2,      77,     "RAZ",  0,      0,      0ull,   0ull},
38186         {"TWSI2"                       ,        59,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38187         {"POWIQ"                       ,        60,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38188         {"IPDPPTHR"                    ,        61,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38189         {"MII"                         ,        62,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38190         {"BOOTDMA"                     ,        63,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
38191         {"WDOG"                        ,        0,      12,     78,     "R/W",  0,      0,      0ull,   0ull},
38192         {"RESERVED_12_63"              ,        12,     52,     78,     "RAZ",  1,      1,      0,      0},
38193         {"WORKQ"                       ,        0,      16,     79,     "RO",   0,      0,      0ull,   0ull},
38194         {"GPIO"                        ,        16,     16,     79,     "RO",   0,      0,      0ull,   0ull},
38195         {"MBOX"                        ,        32,     2,      79,     "RO",   0,      0,      0ull,   0ull},
38196         {"UART"                        ,        34,     2,      79,     "RO",   0,      0,      0ull,   0ull},
38197         {"PCI_INT"                     ,        36,     4,      79,     "RO",   0,      0,      0ull,   0ull},
38198         {"PCI_MSI"                     ,        40,     4,      79,     "RO",   0,      0,      0ull,   0ull},
38199         {"WDOG_SUM"                    ,        44,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38200         {"TWSI"                        ,        45,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38201         {"RML"                         ,        46,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38202         {"TRACE"                       ,        47,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38203         {"GMX_DRP"                     ,        48,     2,      79,     "R/W1C",        0,      0,      0ull,   0ull},
38204         {"IPD_DRP"                     ,        50,     1,      79,     "R/W1C",        0,      0,      0ull,   0ull},
38205         {"KEY_ZERO"                    ,        51,     1,      79,     "R/W1C",        0,      0,      0ull,   0ull},
38206         {"TIMER"                       ,        52,     4,      79,     "R/W1C",        0,      0,      0ull,   0ull},
38207         {"USB"                         ,        56,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38208         {"RESERVED_57_58"              ,        57,     2,      79,     "RAZ",  0,      0,      0ull,   0ull},
38209         {"TWSI2"                       ,        59,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38210         {"POWIQ"                       ,        60,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38211         {"IPDPPTHR"                    ,        61,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38212         {"MII"                         ,        62,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38213         {"BOOTDMA"                     ,        63,     1,      79,     "RO",   0,      0,      0ull,   0ull},
38214         {"WORKQ"                       ,        0,      16,     80,     "RO",   0,      0,      0ull,   0ull},
38215         {"GPIO"                        ,        16,     16,     80,     "RO",   0,      0,      0ull,   0ull},
38216         {"MBOX"                        ,        32,     2,      80,     "RO",   0,      0,      0ull,   0ull},
38217         {"UART"                        ,        34,     2,      80,     "RO",   0,      0,      0ull,   0ull},
38218         {"PCI_INT"                     ,        36,     4,      80,     "RO",   0,      0,      0ull,   0ull},
38219         {"PCI_MSI"                     ,        40,     4,      80,     "RO",   0,      0,      0ull,   0ull},
38220         {"WDOG_SUM"                    ,        44,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38221         {"TWSI"                        ,        45,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38222         {"RML"                         ,        46,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38223         {"TRACE"                       ,        47,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38224         {"GMX_DRP"                     ,        48,     2,      80,     "R/W1C",        0,      0,      0ull,   0ull},
38225         {"IPD_DRP"                     ,        50,     1,      80,     "R/W1C",        0,      0,      0ull,   0ull},
38226         {"KEY_ZERO"                    ,        51,     1,      80,     "R/W1C",        0,      0,      0ull,   0ull},
38227         {"TIMER"                       ,        52,     4,      80,     "R/W1C",        0,      0,      0ull,   0ull},
38228         {"USB"                         ,        56,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38229         {"RESERVED_57_58"              ,        57,     2,      80,     "RAZ",  0,      0,      0ull,   0ull},
38230         {"TWSI2"                       ,        59,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38231         {"POWIQ"                       ,        60,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38232         {"IPDPPTHR"                    ,        61,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38233         {"MII"                         ,        62,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38234         {"BOOTDMA"                     ,        63,     1,      80,     "RO",   0,      0,      0ull,   0ull},
38235         {"WDOG"                        ,        0,      12,     81,     "RO",   0,      0,      0ull,   0ull},
38236         {"RESERVED_12_63"              ,        12,     52,     81,     "RAZ",  1,      1,      0,      0},
38237         {"BITS"                        ,        0,      32,     82,     "R/W1C",        0,      0,      0ull,   0ull},
38238         {"RESERVED_32_63"              ,        32,     32,     82,     "RAZ",  1,      1,      0,      0},
38239         {"BITS"                        ,        0,      32,     83,     "R/W1", 0,      0,      0ull,   0ull},
38240         {"RESERVED_32_63"              ,        32,     32,     83,     "RAZ",  1,      1,      0,      0},
38241         {"NMI"                         ,        0,      12,     84,     "WO",   0,      0,      0ull,   0ull},
38242         {"RESERVED_12_63"              ,        12,     52,     84,     "RAZ",  1,      1,      0,      0},
38243         {"INTR"                        ,        0,      2,      85,     "R/W",  0,      0,      0ull,   0ull},
38244         {"RESERVED_2_63"               ,        2,      62,     85,     "RAZ",  1,      1,      0,      0},
38245         {"PPDBG"                       ,        0,      12,     86,     "RO",   0,      0,      0ull,   0ull},
38246         {"RESERVED_12_63"              ,        12,     52,     86,     "RAZ",  1,      1,      0,      0},
38247         {"POKE"                        ,        0,      64,     87,     "RAZ",  1,      1,      0,      0},
38248         {"RST0"                        ,        0,      1,      88,     "R/W",  1,      1,      0,      0},
38249         {"RST"                         ,        1,      11,     88,     "R/W",  0,      0,      32767ull,       0ull},
38250         {"RESERVED_12_63"              ,        12,     52,     88,     "RAZ",  1,      1,      0,      0},
38251         {"QLM_DCOK"                    ,        0,      4,      89,     "R/W",  0,      0,      1ull,   1ull},
38252         {"RESERVED_4_63"               ,        4,      60,     89,     "RAZ",  1,      1,      0,      0},
38253         {"BYPASS"                      ,        0,      4,      90,     "R/W",  0,      1,      0ull,   0},
38254         {"MUX_SEL"                     ,        4,      2,      90,     "R/W",  0,      1,      0ull,   0},
38255         {"RESERVED_6_7"                ,        6,      2,      90,     "RAZ",  1,      1,      0,      0},
38256         {"CLK_DIV"                     ,        8,      3,      90,     "R/W",  0,      1,      0ull,   0},
38257         {"RESERVED_11_63"              ,        11,     53,     90,     "RAZ",  1,      1,      0,      0},
38258         {"SHFT_REG"                    ,        0,      32,     91,     "R/W",  0,      1,      0ull,   0},
38259         {"SHFT_CNT"                    ,        32,     5,      91,     "R/W",  0,      1,      0ull,   0},
38260         {"RESERVED_37_60"              ,        37,     24,     91,     "RAZ",  1,      1,      0,      0},
38261         {"UPDATE"                      ,        61,     1,      91,     "R/W",  0,      1,      0ull,   0},
38262         {"SHIFT"                       ,        62,     1,      91,     "R/W",  0,      1,      0ull,   0},
38263         {"CAPTURE"                     ,        63,     1,      91,     "R/W",  0,      1,      0ull,   0},
38264         {"SOFT_BIST"                   ,        0,      1,      92,     "R/W",  0,      0,      0ull,   0ull},
38265         {"RESERVED_1_63"               ,        1,      63,     92,     "RAZ",  1,      1,      0,      0},
38266         {"SOFT_PRST"                   ,        0,      1,      93,     "R/W",  0,      0,      1ull,   0ull},
38267         {"RESERVED_1_63"               ,        1,      63,     93,     "RAZ",  1,      1,      0,      0},
38268         {"SOFT_PRST"                   ,        0,      1,      94,     "R/W",  0,      0,      1ull,   0ull},
38269         {"RESERVED_1_63"               ,        1,      63,     94,     "RAZ",  1,      1,      0,      0},
38270         {"SOFT_RST"                    ,        0,      1,      95,     "WO",   0,      0,      0ull,   0ull},
38271         {"RESERVED_1_63"               ,        1,      63,     95,     "RAZ",  1,      1,      0,      0},
38272         {"LEN"                         ,        0,      36,     96,     "R/W",  0,      0,      0ull,   0ull},
38273         {"ONE_SHOT"                    ,        36,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
38274         {"RESERVED_37_63"              ,        37,     27,     96,     "RAZ",  1,      1,      0,      0},
38275         {"MODE"                        ,        0,      2,      97,     "R/W",  0,      0,      0ull,   0ull},
38276         {"STATE"                       ,        2,      2,      97,     "RO",   0,      0,      0ull,   0ull},
38277         {"LEN"                         ,        4,      16,     97,     "R/W",  0,      0,      0ull,   0ull},
38278         {"CNT"                         ,        20,     24,     97,     "RO",   0,      0,      0ull,   0ull},
38279         {"DSTOP"                       ,        44,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
38280         {"GSTOPEN"                     ,        45,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
38281         {"RESERVED_46_63"              ,        46,     18,     97,     "RAZ",  1,      1,      0,      0},
38282         {"FDR"                         ,        0,      1,      98,     "RO",   0,      0,      0ull,   0ull},
38283         {"FFR"                         ,        1,      1,      98,     "RO",   0,      0,      0ull,   0ull},
38284         {"FPF1"                        ,        2,      1,      98,     "RO",   0,      0,      0ull,   0ull},
38285         {"FPF0"                        ,        3,      1,      98,     "RO",   0,      0,      0ull,   0ull},
38286         {"FRD"                         ,        4,      1,      98,     "RO",   0,      0,      0ull,   0ull},
38287         {"RESERVED_5_63"               ,        5,      59,     98,     "RAZ",  1,      1,      0,      0},
38288         {"MEM0_ERR"                    ,        0,      7,      99,     "R/W",  0,      0,      0ull,   0ull},
38289         {"MEM1_ERR"                    ,        7,      7,      99,     "R/W",  0,      0,      0ull,   0ull},
38290         {"ENB"                         ,        14,     1,      99,     "R/W",  0,      0,      0ull,   0ull},
38291         {"USE_STT"                     ,        15,     1,      99,     "R/W",  0,      0,      0ull,   0ull},
38292         {"USE_LDT"                     ,        16,     1,      99,     "R/W",  0,      0,      0ull,   0ull},
38293         {"RESET"                       ,        17,     1,      99,     "R/W",  0,      0,      0ull,   0ull},
38294         {"RESERVED_18_63"              ,        18,     46,     99,     "RAZ",  1,      1,      0,      0},
38295         {"FPF_RD"                      ,        0,      11,     100,    "R/W",  0,      0,      64ull,  0ull},
38296         {"FPF_WR"                      ,        11,     11,     100,    "R/W",  0,      0,      196ull, 0ull},
38297         {"RESERVED_22_63"              ,        22,     42,     100,    "RAZ",  1,      1,      0,      0},
38298         {"FPF_SIZ"                     ,        0,      11,     101,    "R/W",  0,      0,      256ull, 0ull},
38299         {"RESERVED_11_63"              ,        11,     53,     101,    "RAZ",  1,      1,      0,      0},
38300         {"FPF_RD"                      ,        0,      12,     102,    "R/W",  0,      0,      64ull,  0ull},
38301         {"FPF_WR"                      ,        12,     12,     102,    "R/W",  0,      0,      196ull, 0ull},
38302         {"RESERVED_24_63"              ,        24,     40,     102,    "RAZ",  1,      1,      0,      0},
38303         {"FPF_SIZ"                     ,        0,      12,     103,    "R/W",  0,      0,      256ull, 0ull},
38304         {"RESERVED_12_63"              ,        12,     52,     103,    "RAZ",  1,      1,      0,      0},
38305         {"FED0_SBE"                    ,        0,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38306         {"FED0_DBE"                    ,        1,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38307         {"FED1_SBE"                    ,        2,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38308         {"FED1_DBE"                    ,        3,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38309         {"Q0_UND"                      ,        4,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38310         {"Q0_COFF"                     ,        5,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38311         {"Q0_PERR"                     ,        6,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38312         {"Q1_UND"                      ,        7,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38313         {"Q1_COFF"                     ,        8,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38314         {"Q1_PERR"                     ,        9,      1,      104,    "R/W",  0,      0,      0ull,   0ull},
38315         {"Q2_UND"                      ,        10,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38316         {"Q2_COFF"                     ,        11,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38317         {"Q2_PERR"                     ,        12,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38318         {"Q3_UND"                      ,        13,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38319         {"Q3_COFF"                     ,        14,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38320         {"Q3_PERR"                     ,        15,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38321         {"Q4_UND"                      ,        16,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38322         {"Q4_COFF"                     ,        17,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38323         {"Q4_PERR"                     ,        18,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38324         {"Q5_UND"                      ,        19,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38325         {"Q5_COFF"                     ,        20,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38326         {"Q5_PERR"                     ,        21,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38327         {"Q6_UND"                      ,        22,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38328         {"Q6_COFF"                     ,        23,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38329         {"Q6_PERR"                     ,        24,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38330         {"Q7_UND"                      ,        25,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38331         {"Q7_COFF"                     ,        26,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38332         {"Q7_PERR"                     ,        27,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
38333         {"RESERVED_28_63"              ,        28,     36,     104,    "RAZ",  1,      1,      0,      0},
38334         {"FED0_SBE"                    ,        0,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38335         {"FED0_DBE"                    ,        1,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38336         {"FED1_SBE"                    ,        2,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38337         {"FED1_DBE"                    ,        3,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38338         {"Q0_UND"                      ,        4,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38339         {"Q0_COFF"                     ,        5,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38340         {"Q0_PERR"                     ,        6,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38341         {"Q1_UND"                      ,        7,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38342         {"Q1_COFF"                     ,        8,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38343         {"Q1_PERR"                     ,        9,      1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38344         {"Q2_UND"                      ,        10,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38345         {"Q2_COFF"                     ,        11,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38346         {"Q2_PERR"                     ,        12,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38347         {"Q3_UND"                      ,        13,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38348         {"Q3_COFF"                     ,        14,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38349         {"Q3_PERR"                     ,        15,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38350         {"Q4_UND"                      ,        16,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38351         {"Q4_COFF"                     ,        17,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38352         {"Q4_PERR"                     ,        18,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38353         {"Q5_UND"                      ,        19,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38354         {"Q5_COFF"                     ,        20,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38355         {"Q5_PERR"                     ,        21,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38356         {"Q6_UND"                      ,        22,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38357         {"Q6_COFF"                     ,        23,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38358         {"Q6_PERR"                     ,        24,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38359         {"Q7_UND"                      ,        25,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38360         {"Q7_COFF"                     ,        26,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38361         {"Q7_PERR"                     ,        27,     1,      105,    "R/W1C",        0,      0,      0ull,   0ull},
38362         {"RESERVED_28_63"              ,        28,     36,     105,    "RAZ",  1,      1,      0,      0},
38363         {"QUE_SIZ"                     ,        0,      29,     106,    "RO",   0,      0,      0ull,   0ull},
38364         {"RESERVED_29_63"              ,        29,     35,     106,    "RAZ",  1,      1,      0,      0},
38365         {"PG_NUM"                      ,        0,      25,     107,    "RO",   0,      1,      0ull,   0},
38366         {"RESERVED_25_63"              ,        25,     39,     107,    "RAZ",  1,      1,      0,      0},
38367         {"ACT_INDX"                    ,        0,      26,     108,    "RO",   0,      1,      0ull,   0},
38368         {"ACT_QUE"                     ,        26,     3,      108,    "RO",   0,      1,      0ull,   0},
38369         {"RESERVED_29_63"              ,        29,     35,     108,    "RAZ",  0,      0,      0ull,   7ull},
38370         {"EXP_INDX"                    ,        0,      26,     109,    "RO",   0,      1,      0ull,   0},
38371         {"EXP_QUE"                     ,        26,     3,      109,    "RO",   0,      1,      0ull,   0},
38372         {"RESERVED_29_63"              ,        29,     35,     109,    "RAZ",  0,      0,      0ull,   7ull},
38373         {"CTL"                         ,        0,      16,     110,    "R/W",  1,      0,      0,      0ull},
38374         {"RESERVED_16_63"              ,        16,     48,     110,    "RAZ",  1,      1,      0,      0},
38375         {"STATUS"                      ,        0,      32,     111,    "RO",   0,      0,      0ull,   0ull},
38376         {"RESERVED_32_63"              ,        32,     32,     111,    "RAZ",  1,      1,      0,      0},
38377         {"RESERVED_0_1"                ,        0,      2,      112,    "RAZ",  1,      1,      0,      0},
38378         {"OUT_OVR"                     ,        2,      4,      112,    "R/W1C",        0,      0,      0ull,   0ull},
38379         {"RESERVED_6_21"               ,        6,      16,     112,    "RAZ",  1,      1,      0,      0},
38380         {"LOSTSTAT"                    ,        22,     4,      112,    "R/W1C",        0,      0,      0ull,   0ull},
38381         {"STATOVR"                     ,        26,     1,      112,    "R/W1C",        0,      0,      0ull,   0ull},
38382         {"INB_NXA"                     ,        27,     4,      112,    "R/W1C",        0,      0,      0ull,   0ull},
38383         {"RESERVED_31_63"              ,        31,     33,     112,    "RAZ",  1,      1,      0,      0},
38384         {"STATUS"                      ,        0,      16,     113,    "RO",   0,      0,      0ull,   0ull},
38385         {"RESERVED_16_63"              ,        16,     48,     113,    "RAZ",  1,      1,      0,      0},
38386         {"CLK_EN"                      ,        0,      1,      114,    "R/W",  0,      0,      0ull,   0ull},
38387         {"RESERVED_1_63"               ,        1,      63,     114,    "RAZ",  1,      1,      0,      0},
38388         {"TYPE"                        ,        0,      1,      115,    "RO",   0,      1,      0ull,   0},
38389         {"EN"                          ,        1,      1,      115,    "R/W",  0,      1,      0ull,   0},
38390         {"RESERVED_2_3"                ,        2,      2,      115,    "RAZ",  1,      1,      0,      0},
38391         {"MODE"                        ,        4,      2,      115,    "RO",   0,      1,      0ull,   0},
38392         {"RESERVED_6_7"                ,        6,      2,      115,    "RAZ",  1,      1,      0,      0},
38393         {"SPEED"                       ,        8,      2,      115,    "RO",   1,      1,      0,      0},
38394         {"RESERVED_10_63"              ,        10,     54,     115,    "RAZ",  1,      1,      0,      0},
38395         {"PRT"                         ,        0,      6,      116,    "RO",   0,      1,      0ull,   0},
38396         {"RESERVED_6_63"               ,        6,      58,     116,    "RAZ",  1,      1,      0,      0},
38397         {"EN"                          ,        0,      1,      117,    "R/W",  0,      1,      0ull,   0},
38398         {"SPEED"                       ,        1,      1,      117,    "R/W",  0,      1,      1ull,   0},
38399         {"DUPLEX"                      ,        2,      1,      117,    "R/W",  0,      1,      1ull,   0},
38400         {"SLOTTIME"                    ,        3,      1,      117,    "R/W",  0,      1,      1ull,   0},
38401         {"RESERVED_4_7"                ,        4,      4,      117,    "RAZ",  1,      1,      0,      0},
38402         {"SPEED_MSB"                   ,        8,      1,      117,    "R/W",  0,      1,      0ull,   0},
38403         {"RESERVED_9_11"               ,        9,      3,      117,    "RAZ",  1,      1,      0,      0},
38404         {"RX_IDLE"                     ,        12,     1,      117,    "RO",   0,      1,      1ull,   0},
38405         {"TX_IDLE"                     ,        13,     1,      117,    "RO",   0,      1,      1ull,   0},
38406         {"RESERVED_14_63"              ,        14,     50,     117,    "RAZ",  1,      1,      0,      0},
38407         {"ADR"                         ,        0,      64,     118,    "R/W",  0,      1,      0ull,   0},
38408         {"ADR"                         ,        0,      64,     119,    "R/W",  0,      1,      0ull,   0},
38409         {"ADR"                         ,        0,      64,     120,    "R/W",  0,      1,      0ull,   0},
38410         {"ADR"                         ,        0,      64,     121,    "R/W",  0,      1,      0ull,   0},
38411         {"ADR"                         ,        0,      64,     122,    "R/W",  0,      1,      0ull,   0},
38412         {"ADR"                         ,        0,      64,     123,    "R/W",  0,      1,      0ull,   0},
38413         {"EN"                          ,        0,      8,      124,    "R/W",  0,      1,      0ull,   0},
38414         {"RESERVED_8_63"               ,        8,      56,     124,    "RAZ",  1,      1,      0,      0},
38415         {"BCST"                        ,        0,      1,      125,    "R/W",  0,      1,      1ull,   0},
38416         {"MCST"                        ,        1,      2,      125,    "R/W",  0,      1,      0ull,   0},
38417         {"CAM_MODE"                    ,        3,      1,      125,    "R/W",  0,      1,      0ull,   0},
38418         {"RESERVED_4_63"               ,        4,      60,     125,    "RAZ",  1,      1,      0,      0},
38419         {"CNT"                         ,        0,      5,      126,    "R/W",  0,      0,      24ull,  24ull},
38420         {"RESERVED_5_63"               ,        5,      59,     126,    "RAZ",  1,      1,      0,      0},
38421         {"RESERVED_0_0"                ,        0,      1,      127,    "RAZ",  1,      1,      0,      0},
38422         {"CAREXT"                      ,        1,      1,      127,    "R/W",  0,      0,      1ull,   1ull},
38423         {"RESERVED_2_2"                ,        2,      1,      127,    "RAZ",  1,      1,      0,      0},
38424         {"JABBER"                      ,        3,      1,      127,    "R/W",  0,      0,      1ull,   1ull},
38425         {"FCSERR"                      ,        4,      1,      127,    "R/W",  0,      0,      1ull,   1ull},
38426         {"RESERVED_5_6"                ,        5,      2,      127,    "RAZ",  1,      1,      0,      0},
38427         {"RCVERR"                      ,        7,      1,      127,    "R/W",  0,      0,      1ull,   1ull},
38428         {"SKPERR"                      ,        8,      1,      127,    "R/W",  0,      0,      1ull,   1ull},
38429         {"RESERVED_9_63"               ,        9,      55,     127,    "RAZ",  1,      1,      0,      0},
38430         {"PRE_CHK"                     ,        0,      1,      128,    "R/W",  0,      0,      1ull,   1ull},
38431         {"PRE_STRP"                    ,        1,      1,      128,    "R/W",  0,      0,      1ull,   1ull},
38432         {"CTL_DRP"                     ,        2,      1,      128,    "R/W",  0,      0,      1ull,   1ull},
38433         {"CTL_BCK"                     ,        3,      1,      128,    "R/W",  0,      0,      1ull,   1ull},
38434         {"CTL_MCST"                    ,        4,      1,      128,    "R/W",  0,      0,      1ull,   1ull},
38435         {"CTL_SMAC"                    ,        5,      1,      128,    "R/W",  0,      0,      0ull,   0ull},
38436         {"PRE_FREE"                    ,        6,      1,      128,    "RO",   0,      0,      1ull,   1ull},
38437         {"RESERVED_7_8"                ,        7,      2,      128,    "RAZ",  1,      1,      0,      0},
38438         {"PRE_ALIGN"                   ,        9,      1,      128,    "R/W",  0,      0,      0ull,   0ull},
38439         {"RESERVED_10_63"              ,        10,     54,     128,    "RAZ",  1,      1,      0,      0},
38440         {"IFG"                         ,        0,      4,      129,    "R/W",  0,      0,      8ull,   8ull},
38441         {"RESERVED_4_63"               ,        4,      60,     129,    "RAZ",  1,      1,      0,      0},
38442         {"RESERVED_0_0"                ,        0,      1,      130,    "RAZ",  1,      1,      0,      0},
38443         {"CAREXT"                      ,        1,      1,      130,    "R/W",  0,      0,      0ull,   0ull},
38444         {"RESERVED_2_2"                ,        2,      1,      130,    "RAZ",  1,      1,      0,      0},
38445         {"JABBER"                      ,        3,      1,      130,    "R/W",  0,      0,      0ull,   0ull},
38446         {"FCSERR"                      ,        4,      1,      130,    "R/W",  0,      0,      0ull,   0ull},
38447         {"RESERVED_5_6"                ,        5,      2,      130,    "RAZ",  1,      1,      0,      0},
38448         {"RCVERR"                      ,        7,      1,      130,    "R/W",  0,      0,      0ull,   0ull},
38449         {"SKPERR"                      ,        8,      1,      130,    "R/W",  0,      0,      0ull,   0ull},
38450         {"RESERVED_9_9"                ,        9,      1,      130,    "RAZ",  1,      1,      0,      0},
38451         {"OVRERR"                      ,        10,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38452         {"PCTERR"                      ,        11,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38453         {"RSVERR"                      ,        12,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38454         {"FALERR"                      ,        13,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38455         {"COLDET"                      ,        14,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38456         {"IFGERR"                      ,        15,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38457         {"RESERVED_16_18"              ,        16,     3,      130,    "RAZ",  1,      1,      0,      0},
38458         {"PAUSE_DRP"                   ,        19,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38459         {"LOC_FAULT"                   ,        20,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38460         {"REM_FAULT"                   ,        21,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38461         {"BAD_SEQ"                     ,        22,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38462         {"BAD_TERM"                    ,        23,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38463         {"UNSOP"                       ,        24,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38464         {"UNEOP"                       ,        25,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38465         {"UNDAT"                       ,        26,     1,      130,    "R/W",  0,      0,      0ull,   0ull},
38466         {"RESERVED_27_63"              ,        27,     37,     130,    "RAZ",  1,      1,      0,      0},
38467         {"RESERVED_0_0"                ,        0,      1,      131,    "RAZ",  1,      1,      0,      0},
38468         {"CAREXT"                      ,        1,      1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38469         {"RESERVED_2_2"                ,        2,      1,      131,    "RAZ",  1,      1,      0,      0},
38470         {"JABBER"                      ,        3,      1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38471         {"FCSERR"                      ,        4,      1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38472         {"RESERVED_5_6"                ,        5,      2,      131,    "RAZ",  1,      1,      0,      0},
38473         {"RCVERR"                      ,        7,      1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38474         {"SKPERR"                      ,        8,      1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38475         {"RESERVED_9_9"                ,        9,      1,      131,    "RAZ",  1,      1,      0,      0},
38476         {"OVRERR"                      ,        10,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38477         {"PCTERR"                      ,        11,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38478         {"RSVERR"                      ,        12,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38479         {"FALERR"                      ,        13,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38480         {"COLDET"                      ,        14,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38481         {"IFGERR"                      ,        15,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38482         {"RESERVED_16_18"              ,        16,     3,      131,    "RAZ",  1,      1,      0,      0},
38483         {"PAUSE_DRP"                   ,        19,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38484         {"LOC_FAULT"                   ,        20,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38485         {"REM_FAULT"                   ,        21,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38486         {"BAD_SEQ"                     ,        22,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38487         {"BAD_TERM"                    ,        23,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38488         {"UNSOP"                       ,        24,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38489         {"UNEOP"                       ,        25,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38490         {"UNDAT"                       ,        26,     1,      131,    "R/W1C",        0,      0,      0ull,   0ull},
38491         {"RESERVED_27_63"              ,        27,     37,     131,    "RAZ",  1,      1,      0,      0},
38492         {"CNT"                         ,        0,      16,     132,    "R/W",  0,      0,      10240ull,       10240ull},
38493         {"RESERVED_16_63"              ,        16,     48,     132,    "RAZ",  1,      1,      0,      0},
38494         {"STATUS"                      ,        0,      16,     133,    "R/W1C",        0,      1,      0ull,   0},
38495         {"RESERVED_16_63"              ,        16,     48,     133,    "RAZ",  1,      1,      0,      0},
38496         {"RD_CLR"                      ,        0,      1,      134,    "R/W",  0,      0,      0ull,   0ull},
38497         {"RESERVED_1_63"               ,        1,      63,     134,    "RAZ",  1,      1,      0,      0},
38498         {"CNT"                         ,        0,      48,     135,    "RC/W", 0,      1,      0ull,   0},
38499         {"RESERVED_48_63"              ,        48,     16,     135,    "RAZ",  1,      1,      0,      0},
38500         {"CNT"                         ,        0,      48,     136,    "RC/W", 0,      1,      0ull,   0},
38501         {"RESERVED_48_63"              ,        48,     16,     136,    "RAZ",  1,      1,      0,      0},
38502         {"CNT"                         ,        0,      48,     137,    "RC/W", 0,      1,      0ull,   0},
38503         {"RESERVED_48_63"              ,        48,     16,     137,    "RAZ",  1,      1,      0,      0},
38504         {"CNT"                         ,        0,      48,     138,    "RC/W", 0,      1,      0ull,   0},
38505         {"RESERVED_48_63"              ,        48,     16,     138,    "RAZ",  1,      1,      0,      0},
38506         {"CNT"                         ,        0,      32,     139,    "RC/W", 0,      1,      0ull,   0},
38507         {"RESERVED_32_63"              ,        32,     32,     139,    "RAZ",  1,      1,      0,      0},
38508         {"CNT"                         ,        0,      32,     140,    "RC/W", 0,      1,      0ull,   0},
38509         {"RESERVED_32_63"              ,        32,     32,     140,    "RAZ",  1,      1,      0,      0},
38510         {"CNT"                         ,        0,      32,     141,    "RC/W", 0,      1,      0ull,   0},
38511         {"RESERVED_32_63"              ,        32,     32,     141,    "RAZ",  1,      1,      0,      0},
38512         {"CNT"                         ,        0,      32,     142,    "RC/W", 0,      1,      0ull,   0},
38513         {"RESERVED_32_63"              ,        32,     32,     142,    "RAZ",  1,      1,      0,      0},
38514         {"CNT"                         ,        0,      32,     143,    "RC/W", 0,      1,      0ull,   0},
38515         {"RESERVED_32_63"              ,        32,     32,     143,    "RAZ",  1,      1,      0,      0},
38516         {"LEN"                         ,        0,      7,      144,    "R/W",  0,      0,      0ull,   0ull},
38517         {"RESERVED_7_7"                ,        7,      1,      144,    "RAZ",  1,      1,      0,      0},
38518         {"FCSSEL"                      ,        8,      1,      144,    "R/W",  0,      0,      0ull,   0ull},
38519         {"RESERVED_9_63"               ,        9,      55,     144,    "RAZ",  1,      1,      0,      0},
38520         {"MARK"                        ,        0,      6,      145,    "R/W",  0,      0,      2ull,   2ull},
38521         {"RESERVED_6_63"               ,        6,      58,     145,    "RAZ",  1,      1,      0,      0},
38522         {"MARK"                        ,        0,      6,      146,    "R/W",  0,      0,      16ull,  16ull},
38523         {"RESERVED_6_63"               ,        6,      58,     146,    "RAZ",  1,      1,      0,      0},
38524         {"MARK"                        ,        0,      9,      147,    "R/W",  0,      0,      64ull,  64ull},
38525         {"RESERVED_9_63"               ,        9,      55,     147,    "RAZ",  1,      1,      0,      0},
38526         {"COMMIT"                      ,        0,      4,      148,    "RO",   0,      0,      0ull,   0ull},
38527         {"RESERVED_4_15"               ,        4,      12,     148,    "RAZ",  1,      1,      0,      0},
38528         {"DROP"                        ,        16,     4,      148,    "RO",   0,      0,      0ull,   0ull},
38529         {"RESERVED_20_63"              ,        20,     44,     148,    "RAZ",  1,      1,      0,      0},
38530         {"PRTS"                        ,        0,      3,      149,    "R/W",  0,      0,      4ull,   4ull},
38531         {"RESERVED_3_63"               ,        3,      61,     149,    "RAZ",  1,      1,      0,      0},
38532         {"LANE_RXD"                    ,        0,      32,     150,    "RO",   0,      1,      0ull,   0},
38533         {"LANE_RXC"                    ,        32,     4,      150,    "RO",   0,      1,      0ull,   0},
38534         {"STATE"                       ,        36,     3,      150,    "RO",   0,      1,      0ull,   0},
38535         {"VAL"                         ,        39,     1,      150,    "R/W1C",        0,      1,      0ull,   0},
38536         {"RESERVED_40_63"              ,        40,     24,     150,    "RAZ",  1,      1,      0,      0},
38537         {"STATUS"                      ,        0,      2,      151,    "RO",   0,      0,      0ull,   0ull},
38538         {"RESERVED_2_63"               ,        2,      62,     151,    "RAZ",  1,      1,      0,      0},
38539         {"SMAC"                        ,        0,      48,     152,    "R/W",  0,      1,      0ull,   0},
38540         {"RESERVED_48_63"              ,        48,     16,     152,    "RAZ",  1,      1,      0,      0},
38541         {"CNT"                         ,        0,      16,     153,    "R/W1C",        0,      0,      0ull,   0ull},
38542         {"BP"                          ,        16,     1,      153,    "RO",   0,      0,      0ull,   0ull},
38543         {"RESERVED_17_63"              ,        17,     47,     153,    "RAZ",  1,      1,      0,      0},
38544         {"PREAMBLE"                    ,        0,      1,      154,    "R/W",  0,      0,      1ull,   1ull},
38545         {"PAD"                         ,        1,      1,      154,    "R/W",  0,      0,      1ull,   1ull},
38546         {"FCS"                         ,        2,      1,      154,    "R/W",  0,      0,      1ull,   1ull},
38547         {"FORCE_FCS"                   ,        3,      1,      154,    "R/W",  0,      0,      1ull,   1ull},
38548         {"RESERVED_4_63"               ,        4,      60,     154,    "RAZ",  1,      1,      0,      0},
38549         {"BURST"                       ,        0,      16,     155,    "R/W",  0,      0,      8192ull,        8192ull},
38550         {"RESERVED_16_63"              ,        16,     48,     155,    "RAZ",  1,      1,      0,      0},
38551         {"XSCOL_EN"                    ,        0,      1,      156,    "R/W",  0,      0,      1ull,   1ull},
38552         {"XSDEF_EN"                    ,        1,      1,      156,    "R/W",  0,      0,      1ull,   1ull},
38553         {"RESERVED_2_63"               ,        2,      62,     156,    "RAZ",  1,      1,      0,      0},
38554         {"MIN_SIZE"                    ,        0,      8,      157,    "R/W",  0,      0,      59ull,  59ull},
38555         {"RESERVED_8_63"               ,        8,      56,     157,    "RAZ",  1,      1,      0,      0},
38556         {"INTERVAL"                    ,        0,      16,     158,    "R/W",  0,      1,      16ull,  0},
38557         {"RESERVED_16_63"              ,        16,     48,     158,    "RAZ",  1,      1,      0,      0},
38558         {"TIME"                        ,        0,      16,     159,    "R/W",  0,      1,      96ull,  0},
38559         {"RESERVED_16_63"              ,        16,     48,     159,    "RAZ",  1,      1,      0,      0},
38560         {"TIME"                        ,        0,      16,     160,    "RO",   1,      1,      0,      0},
38561         {"RESERVED_16_63"              ,        16,     48,     160,    "RAZ",  1,      1,      0,      0},
38562         {"SEND"                        ,        0,      1,      161,    "R/W",  0,      0,      1ull,   1ull},
38563         {"RESERVED_1_63"               ,        1,      63,     161,    "RAZ",  1,      1,      0,      0},
38564         {"ALIGN"                       ,        0,      1,      162,    "R/W",  0,      0,      1ull,   1ull},
38565         {"RESERVED_1_63"               ,        1,      63,     162,    "RAZ",  1,      1,      0,      0},
38566         {"SLOT"                        ,        0,      10,     163,    "R/W",  0,      0,      512ull, 512ull},
38567         {"RESERVED_10_63"              ,        10,     54,     163,    "RAZ",  1,      1,      0,      0},
38568         {"TIME"                        ,        0,      16,     164,    "R/W",  0,      1,      0ull,   0},
38569         {"RESERVED_16_63"              ,        16,     48,     164,    "RAZ",  1,      1,      0,      0},
38570         {"XSCOL"                       ,        0,      32,     165,    "RC/W", 0,      1,      0ull,   0},
38571         {"XSDEF"                       ,        32,     32,     165,    "RC/W", 0,      1,      0ull,   0},
38572         {"MCOL"                        ,        0,      32,     166,    "RC/W", 0,      1,      0ull,   0},
38573         {"SCOL"                        ,        32,     32,     166,    "RC/W", 0,      1,      0ull,   0},
38574         {"OCTS"                        ,        0,      48,     167,    "RC/W", 0,      1,      0ull,   0},
38575         {"RESERVED_48_63"              ,        48,     16,     167,    "RAZ",  1,      1,      0,      0},
38576         {"PKTS"                        ,        0,      32,     168,    "RC/W", 0,      1,      0ull,   0},
38577         {"RESERVED_32_63"              ,        32,     32,     168,    "RAZ",  1,      1,      0,      0},
38578         {"HIST0"                       ,        0,      32,     169,    "RC/W", 0,      1,      0ull,   0},
38579         {"HIST1"                       ,        32,     32,     169,    "RC/W", 0,      1,      0ull,   0},
38580         {"HIST2"                       ,        0,      32,     170,    "RC/W", 0,      1,      0ull,   0},
38581         {"HIST3"                       ,        32,     32,     170,    "RC/W", 0,      1,      0ull,   0},
38582         {"HIST4"                       ,        0,      32,     171,    "RC/W", 0,      1,      0ull,   0},
38583         {"HIST5"                       ,        32,     32,     171,    "RC/W", 0,      1,      0ull,   0},
38584         {"HIST6"                       ,        0,      32,     172,    "RC/W", 0,      1,      0ull,   0},
38585         {"HIST7"                       ,        32,     32,     172,    "RC/W", 0,      1,      0ull,   0},
38586         {"BCST"                        ,        0,      32,     173,    "RC/W", 0,      1,      0ull,   0},
38587         {"MCST"                        ,        32,     32,     173,    "RC/W", 0,      1,      0ull,   0},
38588         {"CTL"                         ,        0,      32,     174,    "RC/W", 0,      1,      0ull,   0},
38589         {"UNDFLW"                      ,        32,     32,     174,    "RC/W", 0,      1,      0ull,   0},
38590         {"RD_CLR"                      ,        0,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
38591         {"RESERVED_1_63"               ,        1,      63,     175,    "RAZ",  1,      1,      0,      0},
38592         {"CNT"                         ,        0,      9,      176,    "R/W",  0,      0,      32ull,  32ull},
38593         {"RESERVED_9_63"               ,        9,      55,     176,    "RAZ",  1,      1,      0,      0},
38594         {"BP"                          ,        0,      4,      177,    "RO",   0,      0,      0ull,   0ull},
38595         {"RESERVED_4_63"               ,        4,      60,     177,    "RAZ",  1,      1,      0,      0},
38596         {"LIMIT"                       ,        0,      5,      178,    "R/W",  0,      0,      16ull,  16ull},
38597         {"RESERVED_5_63"               ,        5,      59,     178,    "RAZ",  1,      1,      0,      0},
38598         {"CORRUPT"                     ,        0,      4,      179,    "R/W",  0,      0,      15ull,  15ull},
38599         {"RESERVED_4_63"               ,        4,      60,     179,    "RAZ",  1,      1,      0,      0},
38600         {"IFG1"                        ,        0,      4,      180,    "R/W",  0,      1,      8ull,   0},
38601         {"IFG2"                        ,        4,      4,      180,    "R/W",  0,      1,      4ull,   0},
38602         {"RESERVED_8_63"               ,        8,      56,     180,    "RAZ",  1,      1,      0,      0},
38603         {"PKO_NXA"                     ,        0,      1,      181,    "R/W",  0,      0,      0ull,   0ull},
38604         {"RESERVED_1_1"                ,        1,      1,      181,    "RAZ",  0,      0,      0ull,   0ull},
38605         {"UNDFLW"                      ,        2,      4,      181,    "R/W",  0,      0,      0ull,   0ull},
38606         {"RESERVED_6_7"                ,        6,      2,      181,    "RAZ",  0,      0,      0ull,   0ull},
38607         {"XSCOL"                       ,        8,      4,      181,    "R/W",  0,      0,      0ull,   0ull},
38608         {"XSDEF"                       ,        12,     4,      181,    "R/W",  0,      0,      0ull,   0ull},
38609         {"LATE_COL"                    ,        16,     4,      181,    "R/W",  0,      0,      0ull,   0ull},
38610         {"RESERVED_20_63"              ,        20,     44,     181,    "RAZ",  1,      1,      0,      0},
38611         {"PKO_NXA"                     ,        0,      1,      182,    "R/W1C",        0,      0,      0ull,   0ull},
38612         {"RESERVED_1_1"                ,        1,      1,      182,    "RAZ",  0,      0,      0ull,   0ull},
38613         {"UNDFLW"                      ,        2,      4,      182,    "R/W1C",        0,      0,      0ull,   0ull},
38614         {"RESERVED_6_7"                ,        6,      2,      182,    "RAZ",  0,      0,      0ull,   0ull},
38615         {"XSCOL"                       ,        8,      4,      182,    "R/W1C",        0,      0,      0ull,   0ull},
38616         {"XSDEF"                       ,        12,     4,      182,    "R/W1C",        0,      0,      0ull,   0ull},
38617         {"LATE_COL"                    ,        16,     4,      182,    "R/W1C",        0,      0,      0ull,   0ull},
38618         {"RESERVED_20_63"              ,        20,     44,     182,    "RAZ",  1,      1,      0,      0},
38619         {"JAM"                         ,        0,      8,      183,    "R/W",  0,      1,      238ull, 0},
38620         {"RESERVED_8_63"               ,        8,      56,     183,    "RAZ",  1,      1,      0,      0},
38621         {"LFSR"                        ,        0,      16,     184,    "R/W",  0,      1,      65535ull,       0},
38622         {"RESERVED_16_63"              ,        16,     48,     184,    "RAZ",  1,      1,      0,      0},
38623         {"IGN_FULL"                    ,        0,      4,      185,    "R/W",  0,      0,      0ull,   0ull},
38624         {"BP"                          ,        4,      4,      185,    "R/W",  0,      0,      0ull,   0ull},
38625         {"EN"                          ,        8,      4,      185,    "R/W",  0,      0,      0ull,   0ull},
38626         {"RESERVED_12_31"              ,        12,     20,     185,    "RAZ",  1,      1,      0,      0},
38627         {"TX_PRT_BP"                   ,        32,     16,     185,    "R/W",  0,      0,      0ull,   0ull},
38628         {"RESERVED_48_63"              ,        48,     16,     185,    "RAZ",  1,      1,      0,      0},
38629         {"DMAC"                        ,        0,      48,     186,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
38630         {"RESERVED_48_63"              ,        48,     16,     186,    "RAZ",  1,      1,      0,      0},
38631         {"TYPE"                        ,        0,      16,     187,    "R/W",  0,      0,      34824ull,       34824ull},
38632         {"RESERVED_16_63"              ,        16,     48,     187,    "RAZ",  1,      1,      0,      0},
38633         {"PRTS"                        ,        0,      5,      188,    "R/W",  0,      1,      4ull,   0},
38634         {"RESERVED_5_63"               ,        5,      59,     188,    "RAZ",  1,      1,      0,      0},
38635         {"DIC_EN"                      ,        0,      1,      189,    "R/W",  0,      0,      0ull,   1ull},
38636         {"UNI_EN"                      ,        1,      1,      189,    "R/W",  0,      0,      0ull,   0ull},
38637         {"RESERVED_2_3"                ,        2,      2,      189,    "RAZ",  1,      1,      0,      0},
38638         {"LS"                          ,        4,      2,      189,    "R/W",  0,      0,      0ull,   0ull},
38639         {"LS_BYP"                      ,        6,      1,      189,    "R/W",  0,      0,      0ull,   0ull},
38640         {"RESERVED_7_7"                ,        7,      1,      189,    "RAZ",  1,      1,      0,      0},
38641         {"HG_EN"                       ,        8,      1,      189,    "R/W",  0,      0,      0ull,   0ull},
38642         {"HG_PAUSE_HGI"                ,        9,      2,      189,    "R/W",  0,      0,      2ull,   2ull},
38643         {"RESERVED_11_63"              ,        11,     53,     189,    "RAZ",  1,      1,      0,      0},
38644         {"THRESH"                      ,        0,      4,      190,    "R/W",  0,      0,      8ull,   8ull},
38645         {"EN"                          ,        4,      1,      190,    "R/W",  0,      0,      0ull,   0ull},
38646         {"RESERVED_5_63"               ,        5,      59,     190,    "RAZ",  1,      1,      0,      0},
38647         {"TX_OE"                       ,        0,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
38648         {"RX_XOR"                      ,        1,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
38649         {"INT_EN"                      ,        2,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
38650         {"INT_TYPE"                    ,        3,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
38651         {"FIL_CNT"                     ,        4,      4,      191,    "R/W",  0,      0,      0ull,   0ull},
38652         {"FIL_SEL"                     ,        8,      4,      191,    "R/W",  0,      0,      0ull,   0ull},
38653         {"CLK_SEL"                     ,        12,     2,      191,    "R/W",  0,      0,      0ull,   0ull},
38654         {"CLK_GEN"                     ,        14,     1,      191,    "R/W",  0,      0,      0ull,   0ull},
38655         {"RESERVED_15_63"              ,        15,     49,     191,    "RAZ",  1,      1,      0,      0},
38656         {"N"                           ,        0,      32,     192,    "WO",   0,      1,      0ull,   0},
38657         {"RESERVED_32_63"              ,        32,     32,     192,    "RAZ",  1,      1,      0,      0},
38658         {"TYPE"                        ,        0,      16,     193,    "WO",   0,      0,      0ull,   0ull},
38659         {"RESERVED_16_63"              ,        16,     48,     193,    "RAZ",  1,      1,      0,      0},
38660         {"DAT"                         ,        0,      16,     194,    "RO",   0,      0,      0ull,   0ull},
38661         {"RESERVED_16_63"              ,        16,     48,     194,    "RAZ",  1,      1,      0,      0},
38662         {"CLR"                         ,        0,      16,     195,    "WO",   0,      0,      0ull,   0ull},
38663         {"RESERVED_16_63"              ,        16,     48,     195,    "RAZ",  1,      1,      0,      0},
38664         {"SET"                         ,        0,      16,     196,    "WO",   0,      0,      0ull,   0ull},
38665         {"RESERVED_16_63"              ,        16,     48,     196,    "RAZ",  1,      1,      0,      0},
38666         {"ICD"                         ,        0,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38667         {"IBD"                         ,        1,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38668         {"ICRP1"                       ,        2,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38669         {"ICRP0"                       ,        3,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38670         {"ICRN1"                       ,        4,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38671         {"ICRN0"                       ,        5,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38672         {"IBRQ1"                       ,        6,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38673         {"IBRQ0"                       ,        7,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38674         {"ICNRT"                       ,        8,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38675         {"IBR1"                        ,        9,      1,      197,    "RO",   0,      0,      0ull,   0ull},
38676         {"IBR0"                        ,        10,     1,      197,    "RO",   0,      0,      0ull,   0ull},
38677         {"IBDR1"                       ,        11,     1,      197,    "RO",   0,      0,      0ull,   0ull},
38678         {"IBDR0"                       ,        12,     1,      197,    "RO",   0,      0,      0ull,   0ull},
38679         {"ICNR0"                       ,        13,     1,      197,    "RO",   0,      0,      0ull,   0ull},
38680         {"ICNR1"                       ,        14,     1,      197,    "RO",   0,      0,      0ull,   0ull},
38681         {"ICR1"                        ,        15,     1,      197,    "RO",   0,      0,      0ull,   0ull},
38682         {"ICR0"                        ,        16,     1,      197,    "RO",   0,      0,      0ull,   0ull},
38683         {"ICNRCB"                      ,        17,     1,      197,    "RO",   0,      0,      0ull,   0ull},
38684         {"RESERVED_18_63"              ,        18,     46,     197,    "RAZ",  1,      1,      0,      0},
38685         {"FAU_END"                     ,        0,      1,      198,    "R/W",  0,      0,      0ull,   0ull},
38686         {"DWB_ENB"                     ,        1,      1,      198,    "R/W",  0,      0,      1ull,   1ull},
38687         {"PKO_ENB"                     ,        2,      1,      198,    "R/W",  0,      0,      0ull,   0ull},
38688         {"INB_MAT"                     ,        3,      1,      198,    "R/W1C",        0,      0,      0ull,   0ull},
38689         {"OUTB_MAT"                    ,        4,      1,      198,    "R/W1C",        0,      0,      0ull,   0ull},
38690         {"RESERVED_5_63"               ,        5,      59,     198,    "RAZ",  1,      1,      0,      0},
38691         {"CNT_VAL"                     ,        0,      15,     199,    "R/W",  0,      0,      0ull,   0ull},
38692         {"CNT_ENB"                     ,        15,     1,      199,    "R/W",  0,      0,      0ull,   0ull},
38693         {"RESERVED_16_63"              ,        16,     48,     199,    "RAZ",  1,      1,      0,      0},
38694         {"TOUT_VAL"                    ,        0,      12,     200,    "R/W",  0,      0,      4ull,   4ull},
38695         {"TOUT_ENB"                    ,        12,     1,      200,    "R/W",  0,      0,      1ull,   0ull},
38696         {"RESERVED_13_63"              ,        13,     51,     200,    "RAZ",  1,      1,      0,      0},
38697         {"CNT_VAL"                     ,        0,      15,     201,    "R/W",  0,      0,      0ull,   0ull},
38698         {"CNT_ENB"                     ,        15,     1,      201,    "R/W",  0,      0,      0ull,   0ull},
38699         {"RESERVED_16_63"              ,        16,     48,     201,    "RAZ",  1,      1,      0,      0},
38700         {"SRC"                         ,        0,      8,      202,    "R/W",  0,      1,      0ull,   0},
38701         {"DST"                         ,        8,      9,      202,    "R/W",  0,      1,      0ull,   0},
38702         {"OPC"                         ,        17,     4,      202,    "R/W",  0,      1,      0ull,   0},
38703         {"MASK"                        ,        21,     8,      202,    "R/W",  0,      1,      0ull,   0},
38704         {"RESERVED_29_63"              ,        29,     35,     202,    "RAZ",  1,      1,      0,      0},
38705         {"SRC"                         ,        0,      8,      203,    "R/W",  0,      1,      0ull,   0},
38706         {"DST"                         ,        8,      9,      203,    "R/W",  0,      1,      0ull,   0},
38707         {"OPC"                         ,        17,     4,      203,    "R/W",  0,      1,      0ull,   0},
38708         {"MASK"                        ,        21,     8,      203,    "R/W",  0,      1,      0ull,   0},
38709         {"RESERVED_29_63"              ,        29,     35,     203,    "RAZ",  1,      1,      0,      0},
38710         {"DATA"                        ,        0,      64,     204,    "R/W",  0,      1,      0ull,   0},
38711         {"DATA"                        ,        0,      64,     205,    "R/W",  0,      1,      0ull,   0},
38712         {"NP_SOP"                      ,        0,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
38713         {"NP_EOP"                      ,        1,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
38714         {"P_SOP"                       ,        2,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
38715         {"P_EOP"                       ,        3,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
38716         {"NP_DAT"                      ,        4,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
38717         {"P_DAT"                       ,        5,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
38718         {"RESERVED_6_63"               ,        6,      58,     206,    "RAZ",  1,      1,      0,      0},
38719         {"NP_SOP"                      ,        0,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
38720         {"NP_EOP"                      ,        1,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
38721         {"P_SOP"                       ,        2,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
38722         {"P_EOP"                       ,        3,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
38723         {"NP_DAT"                      ,        4,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
38724         {"P_DAT"                       ,        5,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
38725         {"RESERVED_6_63"               ,        6,      58,     207,    "RAZ",  1,      1,      0,      0},
38726         {"CNT_VAL"                     ,        0,      15,     208,    "R/W",  0,      0,      0ull,   0ull},
38727         {"CNT_ENB"                     ,        15,     1,      208,    "R/W",  0,      0,      0ull,   0ull},
38728         {"RESERVED_16_63"              ,        16,     48,     208,    "RAZ",  1,      1,      0,      0},
38729         {"CNT_VAL"                     ,        0,      15,     209,    "R/W",  0,      0,      0ull,   0ull},
38730         {"CNT_ENB"                     ,        15,     1,      209,    "R/W",  0,      0,      0ull,   0ull},
38731         {"RESERVED_16_63"              ,        16,     48,     209,    "RAZ",  1,      1,      0,      0},
38732         {"CNT_VAL"                     ,        0,      15,     210,    "R/W",  0,      0,      0ull,   0ull},
38733         {"CNT_ENB"                     ,        15,     1,      210,    "R/W",  0,      0,      0ull,   0ull},
38734         {"RESERVED_16_63"              ,        16,     48,     210,    "RAZ",  1,      1,      0,      0},
38735         {"SRC"                         ,        0,      9,      211,    "R/W",  0,      1,      0ull,   0},
38736         {"DST"                         ,        9,      8,      211,    "R/W",  0,      1,      0ull,   0},
38737         {"EOT"                         ,        17,     1,      211,    "R/W",  0,      1,      0ull,   0},
38738         {"MASK"                        ,        18,     8,      211,    "R/W",  0,      1,      0ull,   0},
38739         {"RESERVED_26_63"              ,        26,     38,     211,    "RAZ",  1,      1,      0,      0},
38740         {"SRC"                         ,        0,      9,      212,    "R/W",  0,      1,      0ull,   0},
38741         {"DST"                         ,        9,      8,      212,    "R/W",  0,      1,      0ull,   0},
38742         {"EOT"                         ,        17,     1,      212,    "R/W",  0,      1,      0ull,   0},
38743         {"MASK"                        ,        18,     8,      212,    "R/W",  0,      1,      0ull,   0},
38744         {"RESERVED_26_63"              ,        26,     38,     212,    "RAZ",  1,      1,      0,      0},
38745         {"DATA"                        ,        0,      64,     213,    "R/W",  0,      1,      0ull,   0},
38746         {"DATA"                        ,        0,      64,     214,    "R/W",  0,      1,      0ull,   0},
38747         {"CNT_VAL"                     ,        0,      15,     215,    "R/W",  0,      0,      0ull,   0ull},
38748         {"CNT_ENB"                     ,        15,     1,      215,    "R/W",  0,      0,      0ull,   0ull},
38749         {"RESERVED_16_63"              ,        16,     48,     215,    "RAZ",  1,      1,      0,      0},
38750         {"CNT_VAL"                     ,        0,      15,     216,    "R/W",  0,      0,      0ull,   0ull},
38751         {"CNT_ENB"                     ,        15,     1,      216,    "R/W",  0,      0,      0ull,   0ull},
38752         {"RESERVED_16_63"              ,        16,     48,     216,    "RAZ",  1,      1,      0,      0},
38753         {"CNT_VAL"                     ,        0,      15,     217,    "R/W",  0,      0,      0ull,   0ull},
38754         {"CNT_ENB"                     ,        15,     1,      217,    "R/W",  0,      0,      0ull,   0ull},
38755         {"RESERVED_16_63"              ,        16,     48,     217,    "RAZ",  1,      1,      0,      0},
38756         {"PORT"                        ,        0,      6,      218,    "RO",   0,      1,      0ull,   0},
38757         {"RESERVED_6_63"               ,        6,      58,     218,    "RAZ",  1,      1,      0,      0},
38758         {"SKIP_SZ"                     ,        0,      6,      219,    "R/W",  0,      0,      0ull,   0ull},
38759         {"RESERVED_6_63"               ,        6,      58,     219,    "RAZ",  1,      1,      0,      0},
38760         {"BACK"                        ,        0,      4,      220,    "R/W",  0,      0,      0ull,   0ull},
38761         {"RESERVED_4_63"               ,        4,      60,     220,    "RAZ",  1,      1,      0,      0},
38762         {"BACK"                        ,        0,      4,      221,    "R/W",  0,      0,      0ull,   0ull},
38763         {"RESERVED_4_63"               ,        4,      60,     221,    "RAZ",  1,      1,      0,      0},
38764         {"PWP"                         ,        0,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38765         {"IPD_NEW"                     ,        1,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38766         {"IPD_OLD"                     ,        2,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38767         {"PRC_OFF"                     ,        3,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38768         {"PWQ0"                        ,        4,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38769         {"PWQ1"                        ,        5,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38770         {"PBM_WORD"                    ,        6,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38771         {"PBM0"                        ,        7,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38772         {"PBM1"                        ,        8,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38773         {"PBM2"                        ,        9,      1,      222,    "RO",   0,      0,      0ull,   0ull},
38774         {"PBM3"                        ,        10,     1,      222,    "RO",   0,      0,      0ull,   0ull},
38775         {"IPQ_PBE0"                    ,        11,     1,      222,    "RO",   0,      0,      0ull,   0ull},
38776         {"IPQ_PBE1"                    ,        12,     1,      222,    "RO",   0,      0,      0ull,   0ull},
38777         {"PWQ_POW"                     ,        13,     1,      222,    "RO",   0,      0,      0ull,   0ull},
38778         {"PWQ_WP1"                     ,        14,     1,      222,    "RO",   0,      0,      0ull,   0ull},
38779         {"PWQ_WQED"                    ,        15,     1,      222,    "RO",   0,      0,      0ull,   0ull},
38780         {"CSR_NCMD"                    ,        16,     1,      222,    "RO",   0,      0,      0ull,   0ull},
38781         {"CSR_MEM"                     ,        17,     1,      222,    "RO",   0,      0,      0ull,   0ull},
38782         {"RESERVED_18_63"              ,        18,     46,     222,    "RAZ",  1,      1,      0,      0},
38783         {"PRT_ENB"                     ,        0,      40,     223,    "R/W",  0,      0,      0ull,   0ull},
38784         {"RESERVED_40_63"              ,        40,     24,     223,    "RAZ",  1,      1,      0,      0},
38785         {"CLK_CNT"                     ,        0,      64,     224,    "RO",   0,      0,      0ull,   0ull},
38786         {"IPD_EN"                      ,        0,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
38787         {"OPC_MODE"                    ,        1,      2,      225,    "R/W",  0,      0,      0ull,   0ull},
38788         {"PBP_EN"                      ,        3,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
38789         {"WQE_LEND"                    ,        4,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
38790         {"PKT_LEND"                    ,        5,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
38791         {"NADDBUF"                     ,        6,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
38792         {"ADDPKT"                      ,        7,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
38793         {"RESET"                       ,        8,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
38794         {"LEN_M8"                      ,        9,      1,      225,    "R/W",  0,      0,      0ull,   1ull},
38795         {"PKT_OFF"                     ,        10,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
38796         {"IPD_FULL"                    ,        11,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
38797         {"PQ_NABUF"                    ,        12,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
38798         {"PQ_APKT"                     ,        13,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
38799         {"NO_WPTR"                     ,        14,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
38800         {"RESERVED_15_63"              ,        15,     49,     225,    "RAZ",  1,      1,      0,      0},
38801         {"PRC_PAR0"                    ,        0,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38802         {"PRC_PAR1"                    ,        1,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38803         {"PRC_PAR2"                    ,        2,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38804         {"PRC_PAR3"                    ,        3,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38805         {"BP_SUB"                      ,        4,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38806         {"DC_OVR"                      ,        5,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38807         {"CC_OVR"                      ,        6,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38808         {"C_COLL"                      ,        7,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38809         {"D_COLL"                      ,        8,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38810         {"BC_OVR"                      ,        9,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
38811         {"PQ_ADD"                      ,        10,     1,      226,    "R/W",  0,      0,      0ull,   0ull},
38812         {"PQ_SUB"                      ,        11,     1,      226,    "R/W",  0,      0,      0ull,   0ull},
38813         {"RESERVED_12_63"              ,        12,     52,     226,    "RAZ",  1,      1,      0,      0},
38814         {"PRC_PAR0"                    ,        0,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38815         {"PRC_PAR1"                    ,        1,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38816         {"PRC_PAR2"                    ,        2,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38817         {"PRC_PAR3"                    ,        3,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38818         {"BP_SUB"                      ,        4,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38819         {"DC_OVR"                      ,        5,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38820         {"CC_OVR"                      ,        6,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38821         {"C_COLL"                      ,        7,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38822         {"D_COLL"                      ,        8,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38823         {"BC_OVR"                      ,        9,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38824         {"PQ_ADD"                      ,        10,     1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38825         {"PQ_SUB"                      ,        11,     1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
38826         {"RESERVED_12_63"              ,        12,     52,     227,    "RAZ",  1,      1,      0,      0},
38827         {"SKIP_SZ"                     ,        0,      6,      228,    "R/W",  0,      0,      0ull,   0ull},
38828         {"RESERVED_6_63"               ,        6,      58,     228,    "RAZ",  1,      1,      0,      0},
38829         {"MB_SIZE"                     ,        0,      12,     229,    "R/W",  0,      0,      32ull,  32ull},
38830         {"RESERVED_12_63"              ,        12,     52,     229,    "RAZ",  1,      1,      0,      0},
38831         {"PTR"                         ,        0,      29,     230,    "RO",   1,      1,      0,      0},
38832         {"RESERVED_29_63"              ,        29,     35,     230,    "RAZ",  1,      1,      0,      0},
38833         {"PAGE_CNT"                    ,        0,      17,     231,    "R/W",  0,      0,      0ull,   0ull},
38834         {"BP_ENB"                      ,        17,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
38835         {"RESERVED_18_63"              ,        18,     46,     231,    "RAZ",  1,      1,      0,      0},
38836         {"PAGE_CNT"                    ,        0,      17,     232,    "R/W",  0,      0,      0ull,   0ull},
38837         {"BP_ENB"                      ,        17,     1,      232,    "R/W",  0,      0,      0ull,   0ull},
38838         {"RESERVED_18_63"              ,        18,     46,     232,    "RAZ",  1,      1,      0,      0},
38839         {"CNT_VAL"                     ,        0,      25,     233,    "RO",   0,      1,      0ull,   0},
38840         {"RESERVED_25_63"              ,        25,     39,     233,    "RAZ",  1,      1,      0,      0},
38841         {"CNT_VAL"                     ,        0,      25,     234,    "RO",   0,      1,      0ull,   0},
38842         {"RESERVED_25_63"              ,        25,     39,     234,    "RAZ",  1,      1,      0,      0},
38843         {"CNT"                         ,        0,      32,     235,    "RO",   0,      1,      0ull,   0},
38844         {"WMARK"                       ,        32,     32,     235,    "R/W",  0,      1,      4294967295ull,  0},
38845         {"INTR"                        ,        0,      64,     236,    "R/W1C",        0,      0,      0ull,   0ull},
38846         {"ENB"                         ,        0,      64,     237,    "R/W",  0,      0,      0ull,   1ull},
38847         {"RADDR"                       ,        0,      3,      238,    "R/W",  0,      0,      0ull,   0ull},
38848         {"CENA"                        ,        3,      1,      238,    "R/W",  0,      0,      1ull,   1ull},
38849         {"PTR"                         ,        4,      29,     238,    "RO",   1,      1,      0,      0},
38850         {"PRADDR"                      ,        33,     3,      238,    "RO",   1,      1,      0,      0},
38851         {"MAX_PKT"                     ,        36,     3,      238,    "RO",   0,      0,      5ull,   5ull},
38852         {"RESERVED_39_63"              ,        39,     25,     238,    "RAZ",  1,      1,      0,      0},
38853         {"RADDR"                       ,        0,      7,      239,    "R/W",  0,      0,      0ull,   0ull},
38854         {"CENA"                        ,        7,      1,      239,    "R/W",  0,      0,      1ull,   1ull},
38855         {"PTR"                         ,        8,      29,     239,    "RO",   1,      1,      0,      0},
38856         {"MAX_PKT"                     ,        37,     7,      239,    "RO",   0,      0,      16ull,  16ull},
38857         {"RESERVED_44_63"              ,        44,     20,     239,    "RAZ",  1,      1,      0,      0},
38858         {"WQE_PCNT"                    ,        0,      7,      240,    "RO",   0,      0,      0ull,   0ull},
38859         {"PKT_PCNT"                    ,        7,      7,      240,    "RO",   0,      0,      0ull,   0ull},
38860         {"PFIF_CNT"                    ,        14,     3,      240,    "RO",   0,      0,      0ull,   0ull},
38861         {"WQEV_CNT"                    ,        17,     1,      240,    "RO",   0,      0,      0ull,   0ull},
38862         {"PKTV_CNT"                    ,        18,     1,      240,    "RO",   0,      0,      0ull,   0ull},
38863         {"RESERVED_19_63"              ,        19,     45,     240,    "RAZ",  1,      1,      0,      0},
38864         {"RADDR"                       ,        0,      8,      241,    "R/W",  0,      0,      0ull,   0ull},
38865         {"CENA"                        ,        8,      1,      241,    "R/W",  0,      0,      1ull,   1ull},
38866         {"PTR"                         ,        9,      29,     241,    "RO",   1,      1,      0,      0},
38867         {"PRADDR"                      ,        38,     8,      241,    "RO",   1,      1,      0,      0},
38868         {"WRADDR"                      ,        46,     8,      241,    "RO",   1,      1,      0,      0},
38869         {"MAX_CNTS"                    ,        54,     7,      241,    "RO",   0,      0,      64ull,  64ull},
38870         {"RESERVED_61_63"              ,        61,     3,      241,    "RAZ",  1,      1,      0,      0},
38871         {"PASS"                        ,        0,      32,     242,    "R/W",  0,      1,      0ull,   0},
38872         {"DROP"                        ,        32,     32,     242,    "R/W",  0,      1,      0ull,   0},
38873         {"Q0_PCNT"                     ,        0,      32,     243,    "RO",   0,      0,      0ull,   0ull},
38874         {"RESERVED_32_63"              ,        32,     32,     243,    "RAZ",  1,      1,      0,      0},
38875         {"PRT_ENB"                     ,        0,      36,     244,    "R/W",  0,      0,      0ull,   0ull},
38876         {"AVG_DLY"                     ,        36,     14,     244,    "R/W",  0,      1,      0ull,   0},
38877         {"PRB_DLY"                     ,        50,     14,     244,    "R/W",  0,      0,      0ull,   0ull},
38878         {"PRT_ENB"                     ,        0,      4,      245,    "R/W",  0,      0,      0ull,   0ull},
38879         {"RESERVED_4_63"               ,        4,      60,     245,    "RAZ",  1,      1,      0,      0},
38880         {"PRB_CON"                     ,        0,      32,     246,    "R/W",  0,      1,      0ull,   0},
38881         {"AVG_CON"                     ,        32,     8,      246,    "R/W",  0,      1,      0ull,   0},
38882         {"NEW_CON"                     ,        40,     8,      246,    "R/W",  0,      1,      0ull,   0},
38883         {"USE_PCNT"                    ,        48,     1,      246,    "R/W",  0,      0,      0ull,   0ull},
38884         {"RESERVED_49_63"              ,        49,     15,     246,    "RAZ",  1,      1,      0,      0},
38885         {"PAGE_CNT"                    ,        0,      25,     247,    "R/W",  1,      0,      0,      0ull},
38886         {"PORT"                        ,        25,     6,      247,    "R/W",  1,      0,      0,      0ull},
38887         {"RESERVED_31_63"              ,        31,     33,     247,    "RAZ",  1,      1,      0,      0},
38888         {"PORT_BIT"                    ,        0,      32,     248,    "R/W",  0,      0,      4294967295ull,  4294967295ull},
38889         {"RESERVED_32_35"              ,        32,     4,      248,    "RAZ",  1,      1,      0,      0},
38890         {"PORT_BIT2"                   ,        36,     4,      248,    "R/W",  0,      0,      15ull,  15ull},
38891         {"RESERVED_40_63"              ,        40,     24,     248,    "RAZ",  1,      1,      0,      0},
38892         {"CNT"                         ,        0,      32,     249,    "R/W",  1,      0,      0,      0ull},
38893         {"PORT_QOS"                    ,        32,     9,      249,    "R/W",  1,      0,      0,      0ull},
38894         {"RESERVED_41_63"              ,        41,     23,     249,    "RAZ",  1,      1,      0,      0},
38895         {"WQE_POOL"                    ,        0,      3,      250,    "R/W",  0,      0,      1ull,   1ull},
38896         {"RESERVED_3_63"               ,        3,      61,     250,    "RAZ",  1,      1,      0,      0},
38897         {"PTR"                         ,        0,      29,     251,    "RO",   1,      1,      0,      0},
38898         {"RESERVED_29_63"              ,        29,     35,     251,    "RAZ",  1,      1,      0,      0},
38899         {"MEM0"                        ,        0,      1,      252,    "RO",   0,      0,      0ull,   0ull},
38900         {"MEM1"                        ,        1,      1,      252,    "RO",   0,      0,      0ull,   0ull},
38901         {"RRC"                         ,        2,      1,      252,    "RO",   0,      0,      0ull,   0ull},
38902         {"RESERVED_3_63"               ,        3,      61,     252,    "RAZ",  1,      1,      0,      0},
38903         {"MEM0_ERR"                    ,        0,      7,      253,    "R/W",  0,      0,      0ull,   0ull},
38904         {"MEM1_ERR"                    ,        7,      7,      253,    "R/W",  0,      0,      0ull,   0ull},
38905         {"RESERVED_14_63"              ,        14,     50,     253,    "RAZ",  1,      1,      0,      0},
38906         {"KED0_SBE"                    ,        0,      1,      254,    "R/W",  0,      0,      0ull,   0ull},
38907         {"KED0_DBE"                    ,        1,      1,      254,    "R/W",  0,      0,      0ull,   0ull},
38908         {"KED1_SBE"                    ,        2,      1,      254,    "R/W",  0,      0,      0ull,   0ull},
38909         {"KED1_DBE"                    ,        3,      1,      254,    "R/W",  0,      0,      0ull,   0ull},
38910         {"RESERVED_4_63"               ,        4,      60,     254,    "RAZ",  1,      1,      0,      0},
38911         {"KED0_SBE"                    ,        0,      1,      255,    "R/W1C",        0,      0,      0ull,   0ull},
38912         {"KED0_DBE"                    ,        1,      1,      255,    "R/W1C",        0,      0,      0ull,   0ull},
38913         {"KED1_SBE"                    ,        2,      1,      255,    "R/W1C",        0,      0,      0ull,   0ull},
38914         {"KED1_DBE"                    ,        3,      1,      255,    "R/W1C",        0,      0,      0ull,   0ull},
38915         {"RESERVED_4_63"               ,        4,      60,     255,    "RAZ",  1,      1,      0,      0},
38916         {"WLB_DAT"                     ,        0,      4,      256,    "RO",   0,      0,      0ull,   0ull},
38917         {"STIN_MSK"                    ,        4,      1,      256,    "RO",   0,      0,      0ull,   0ull},
38918         {"DT"                          ,        5,      1,      256,    "RO",   0,      0,      0ull,   0ull},
38919         {"DTCNT"                       ,        6,      13,     256,    "RO",   0,      0,      0ull,   0ull},
38920         {"WLB_MSK"                     ,        19,     4,      256,    "RO",   0,      0,      0ull,   0ull},
38921         {"DTBNK"                       ,        23,     1,      256,    "RO",   0,      0,      0ull,   0ull},
38922         {"RESERVED_24_63"              ,        24,     40,     256,    "RAZ",  0,      0,      0ull,   0ull},
38923         {"L2T"                         ,        0,      9,      257,    "RO",   0,      0,      0ull,   0ull},
38924         {"VAB_VWCF0"                   ,        9,      1,      257,    "RO",   0,      0,      0ull,   0ull},
38925         {"RESERVED_10_10"              ,        10,     1,      257,    "RAZ",  0,      0,      0ull,   0ull},
38926         {"VAB_VWCF1"                   ,        11,     1,      257,    "RO",   0,      0,      0ull,   0ull},
38927         {"VWDF0"                       ,        12,     4,      257,    "RO",   0,      0,      0ull,   0ull},
38928         {"VWDF1"                       ,        16,     4,      257,    "RO",   0,      0,      0ull,   0ull},
38929         {"ILC"                         ,        20,     1,      257,    "RO",   0,      0,      0ull,   0ull},
38930         {"PLC0"                        ,        21,     1,      257,    "RO",   0,      0,      0ull,   0ull},
38931         {"PLC1"                        ,        22,     1,      257,    "RO",   0,      0,      0ull,   0ull},
38932         {"PLC2"                        ,        23,     1,      257,    "RO",   0,      0,      0ull,   0ull},
38933         {"RESERVED_24_63"              ,        24,     40,     257,    "RAZ",  0,      0,      0ull,   0ull},
38934         {"XRDDAT"                      ,        0,      1,      258,    "RO",   0,      0,      0ull,   0ull},
38935         {"XRDMSK"                      ,        1,      1,      258,    "RO",   0,      0,      0ull,   0ull},
38936         {"PICBST"                      ,        2,      1,      258,    "RO",   0,      0,      0ull,   0ull},
38937         {"IPCBST"                      ,        3,      1,      258,    "RO",   0,      0,      0ull,   0ull},
38938         {"RHDB"                        ,        4,      4,      258,    "RO",   0,      0,      0ull,   0ull},
38939         {"RMDB"                        ,        8,      4,      258,    "RO",   0,      0,      0ull,   0ull},
38940         {"MRB"                         ,        12,     4,      258,    "RO",   0,      0,      0ull,   0ull},
38941         {"RESERVED_16_63"              ,        16,     48,     258,    "RAZ",  0,      0,      0ull,   0ull},
38942         {"LRF_ARB_MODE"                ,        0,      1,      259,    "R/W",  0,      0,      1ull,   1ull},
38943         {"RFB_ARB_MODE"                ,        1,      1,      259,    "R/W",  0,      0,      1ull,   1ull},
38944         {"RSP_ARB_MODE"                ,        2,      1,      259,    "R/W",  0,      0,      1ull,   1ull},
38945         {"MWF_CRD"                     ,        3,      4,      259,    "R/W",  0,      0,      2ull,   2ull},
38946         {"IDXALIAS"                    ,        7,      1,      259,    "R/W",  0,      0,      0ull,   1ull},
38947         {"FPEN"                        ,        8,      1,      259,    "R/W",  0,      0,      0ull,   0ull},
38948         {"FPEMPTY"                     ,        9,      1,      259,    "R/W",  0,      0,      0ull,   0ull},
38949         {"FPEXP"                       ,        10,     4,      259,    "R/W",  0,      0,      0ull,   0ull},
38950         {"DFILL_DIS"                   ,        14,     1,      259,    "R/W",  0,      0,      0ull,   0ull},
38951         {"DPRES0"                      ,        15,     1,      259,    "R/W",  0,      0,      0ull,   0ull},
38952         {"DPRES1"                      ,        16,     1,      259,    "R/W",  0,      0,      0ull,   0ull},
38953         {"XOR_BANK"                    ,        17,     1,      259,    "R/W",  0,      0,      0ull,   0ull},
38954         {"LBIST"                       ,        18,     1,      259,    "R/W",  0,      0,      0ull,   0ull},
38955         {"BSTRUN"                      ,        19,     1,      259,    "RO",   0,      0,      0ull,   0ull},
38956         {"RESERVED_20_63"              ,        20,     44,     259,    "RAZ",  1,      1,      0,      0},
38957         {"L2T"                         ,        0,      1,      260,    "R/W",  0,      0,      0ull,   0ull},
38958         {"L2D"                         ,        1,      1,      260,    "R/W",  0,      0,      0ull,   0ull},
38959         {"FINV"                        ,        2,      1,      260,    "R/W",  0,      0,      0ull,   0ull},
38960         {"SET"                         ,        3,      3,      260,    "R/W",  0,      0,      0ull,   0ull},
38961         {"PPNUM"                       ,        6,      4,      260,    "R/W",  0,      0,      0ull,   0ull},
38962         {"LFB_DMP"                     ,        10,     1,      260,    "R/W",  0,      0,      0ull,   0ull},
38963         {"LFB_ENUM"                    ,        11,     4,      260,    "R/W",  0,      0,      0ull,   0ull},
38964         {"RESERVED_15_63"              ,        15,     49,     260,    "RAZ",  0,      0,      0ull,   0ull},
38965         {"DT_TAG"                      ,        0,      29,     261,    "RO",   0,      0,      0ull,   0ull},
38966         {"DT_VLD"                      ,        29,     1,      261,    "RO",   0,      0,      0ull,   0ull},
38967         {"RESERVED_30_30"              ,        30,     1,      261,    "RAZ",  0,      0,      0ull,   0ull},
38968         {"DTENA"                       ,        31,     1,      261,    "R/W",  0,      0,      0ull,   0ull},
38969         {"RESERVED_32_63"              ,        32,     32,     261,    "RAZ",  0,      0,      0ull,   0ull},
38970         {"PLC0RMSK"                    ,        0,      32,     262,    "R/W",  0,      0,      0ull,   0ull},
38971         {"PLC1RMSK"                    ,        32,     32,     262,    "R/W",  0,      0,      0ull,   0ull},
38972         {"PLC2RMSK"                    ,        0,      32,     263,    "R/W",  0,      0,      0ull,   0ull},
38973         {"ILCRMSK"                     ,        32,     32,     263,    "R/W",  0,      0,      0ull,   0ull},
38974         {"OOB1EN"                      ,        0,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
38975         {"OOB2EN"                      ,        1,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
38976         {"OOB3EN"                      ,        2,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
38977         {"L2TSECEN"                    ,        3,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
38978         {"L2TDEDEN"                    ,        4,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
38979         {"L2DSECEN"                    ,        5,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
38980         {"L2DDEDEN"                    ,        6,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
38981         {"LCKENA"                      ,        7,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
38982         {"LCK2ENA"                     ,        8,      1,      264,    "R/W",  0,      0,      0ull,   1ull},
38983         {"RESERVED_9_63"               ,        9,      55,     264,    "RAZ",  0,      0,      0ull,   0ull},
38984         {"OOB1"                        ,        0,      1,      265,    "R/W1C",        0,      0,      0ull,   0ull},
38985         {"OOB2"                        ,        1,      1,      265,    "R/W1C",        0,      0,      0ull,   0ull},
38986         {"OOB3"                        ,        2,      1,      265,    "R/W1C",        0,      0,      0ull,   0ull},
38987         {"L2TSEC"                      ,        3,      1,      265,    "R/W1C",        0,      0,      0ull,   0ull},
38988         {"L2TDED"                      ,        4,      1,      265,    "R/W1C",        0,      0,      0ull,   0ull},
38989         {"L2DSEC"                      ,        5,      1,      265,    "R/W1C",        0,      0,      0ull,   0ull},
38990         {"L2DDED"                      ,        6,      1,      265,    "R/W1C",        0,      0,      0ull,   0ull},
38991         {"LCK"                         ,        7,      1,      265,    "R/W1C",        0,      0,      0ull,   0ull},
38992         {"LCK2"                        ,        8,      1,      265,    "R/W1C",        0,      0,      0ull,   0ull},
38993         {"RESERVED_9_63"               ,        9,      55,     265,    "RAZ",  0,      0,      0ull,   0ull},
38994         {"LCK_ENA"                     ,        0,      1,      266,    "R/W",  0,      0,      0ull,   0ull},
38995         {"RESERVED_1_3"                ,        1,      3,      266,    "RAZ",  0,      0,      0ull,   0ull},
38996         {"LCK_BASE"                    ,        4,      27,     266,    "R/W",  0,      0,      0ull,   0ull},
38997         {"RESERVED_31_63"              ,        31,     33,     266,    "RAZ",  0,      0,      0ull,   0ull},
38998         {"LCK_OFFSET"                  ,        0,      10,     267,    "R/W",  0,      0,      0ull,   0ull},
38999         {"RESERVED_10_63"              ,        10,     54,     267,    "RAZ",  0,      0,      0ull,   0ull},
39000         {"VLD"                         ,        0,      1,      268,    "RO",   0,      0,      0ull,   0ull},
39001         {"CMD"                         ,        1,      4,      268,    "RO",   0,      0,      0ull,   0ull},
39002         {"SID"                         ,        5,      9,      268,    "RO",   0,      0,      0ull,   0ull},
39003         {"VABNUM"                      ,        14,     4,      268,    "RO",   0,      0,      0ull,   0ull},
39004         {"SET"                         ,        18,     3,      268,    "RO",   0,      0,      0ull,   0ull},
39005         {"IHD"                         ,        21,     1,      268,    "RO",   0,      0,      0ull,   0ull},
39006         {"ITL"                         ,        22,     1,      268,    "RO",   0,      0,      0ull,   0ull},
39007         {"INXT"                        ,        23,     4,      268,    "RO",   0,      0,      0ull,   0ull},
39008         {"VAM"                         ,        27,     1,      268,    "RO",   0,      0,      0ull,   0ull},
39009         {"STCFL"                       ,        28,     1,      268,    "RO",   0,      0,      0ull,   0ull},
39010         {"STINV"                       ,        29,     1,      268,    "RO",   0,      0,      0ull,   0ull},
39011         {"STPND"                       ,        30,     1,      268,    "RO",   0,      0,      0ull,   0ull},
39012         {"STCPND"                      ,        31,     1,      268,    "RO",   0,      0,      0ull,   0ull},
39013         {"RESERVED_32_63"              ,        32,     32,     268,    "RAZ",  0,      0,      0ull,   0ull},
39014         {"VLD"                         ,        0,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39015         {"WTPRB"                       ,        1,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39016         {"PRBRTY"                      ,        2,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39017         {"WTMFL"                       ,        3,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39018         {"WTVTM"                       ,        4,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39019         {"WTSTRSC"                     ,        5,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39020         {"WTSTRSP"                     ,        6,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39021         {"WTSTDT"                      ,        7,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39022         {"WTRDA"                       ,        8,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39023         {"WTSTM"                       ,        9,      1,      269,    "RO",   0,      0,      0ull,   0ull},
39024         {"WTWRM"                       ,        10,     1,      269,    "RO",   0,      0,      0ull,   0ull},
39025         {"WTWHF"                       ,        11,     1,      269,    "RO",   0,      0,      0ull,   0ull},
39026         {"WTWHP"                       ,        12,     1,      269,    "RO",   0,      0,      0ull,   0ull},
39027         {"WTDQ"                        ,        13,     1,      269,    "RO",   0,      0,      0ull,   0ull},
39028         {"WTDW"                        ,        14,     1,      269,    "RO",   0,      0,      0ull,   0ull},
39029         {"WTRSP"                       ,        15,     1,      269,    "RO",   0,      0,      0ull,   0ull},
39030         {"BID"                         ,        16,     2,      269,    "RO",   0,      0,      0ull,   0ull},
39031         {"DSGOING"                     ,        18,     1,      269,    "RO",   0,      0,      0ull,   0ull},
39032         {"RESERVED_19_63"              ,        19,     45,     269,    "RAZ",  0,      0,      0ull,   0ull},
39033         {"LFB_IDX"                     ,        0,      11,     270,    "RO",   0,      0,      0ull,   0ull},
39034         {"LFB_TAG"                     ,        11,     16,     270,    "RO",   0,      0,      0ull,   0ull},
39035         {"RESERVED_27_63"              ,        27,     37,     270,    "RAZ",  0,      0,      0ull,   0ull},
39036         {"LFB_HWM"                     ,        0,      4,      271,    "R/W",  0,      0,      15ull,  15ull},
39037         {"STPARTDIS"                   ,        4,      1,      271,    "R/W",  0,      0,      0ull,   0ull},
39038         {"RESERVED_5_63"               ,        5,      59,     271,    "RAZ",  0,      0,      0ull,   0ull},
39039         {"STENA"                       ,        0,      1,      272,    "R/W",  0,      0,      0ull,   0ull},
39040         {"DWBENA"                      ,        1,      1,      272,    "R/W",  0,      0,      0ull,   0ull},
39041         {"RESERVED_2_63"               ,        2,      62,     272,    "RAZ",  0,      0,      0ull,   0ull},
39042         {"SIZE"                        ,        0,      14,     273,    "R/W",  0,      0,      0ull,   0ull},
39043         {"RESERVED_14_19"              ,        14,     6,      273,    "RAZ",  0,      0,      0ull,   0ull},
39044         {"SADR"                        ,        20,     14,     273,    "R/W",  0,      0,      0ull,   0ull},
39045         {"RESERVED_34_35"              ,        34,     2,      273,    "RAZ",  0,      0,      0ull,   0ull},
39046         {"FSRC"                        ,        36,     1,      273,    "RO",   0,      0,      0ull,   0ull},
39047         {"FADR"                        ,        37,     27,     273,    "RO",   0,      0,      0ull,   0ull},
39048         {"SIZE"                        ,        0,      14,     274,    "R/W",  0,      0,      0ull,   0ull},
39049         {"RESERVED_14_19"              ,        14,     6,      274,    "RAZ",  0,      0,      0ull,   0ull},
39050         {"SADR"                        ,        20,     14,     274,    "R/W",  0,      0,      0ull,   0ull},
39051         {"RESERVED_34_35"              ,        34,     2,      274,    "RAZ",  0,      0,      0ull,   0ull},
39052         {"FSRC"                        ,        36,     1,      274,    "RO",   0,      0,      0ull,   0ull},
39053         {"FADR"                        ,        37,     27,     274,    "RO",   0,      0,      0ull,   0ull},
39054         {"SIZE"                        ,        0,      14,     275,    "R/W",  0,      0,      0ull,   0ull},
39055         {"RESERVED_14_19"              ,        14,     6,      275,    "RAZ",  0,      0,      0ull,   0ull},
39056         {"SADR"                        ,        20,     14,     275,    "R/W",  0,      0,      0ull,   0ull},
39057         {"RESERVED_34_35"              ,        34,     2,      275,    "RAZ",  0,      0,      0ull,   0ull},
39058         {"FSRC"                        ,        36,     1,      275,    "RO",   0,      0,      0ull,   0ull},
39059         {"FADR"                        ,        37,     27,     275,    "RO",   0,      0,      0ull,   0ull},
39060         {"PFCNT0"                      ,        0,      36,     276,    "RO",   0,      0,      0ull,   0ull},
39061         {"RESERVED_36_63"              ,        36,     28,     276,    "RAZ",  0,      0,      0ull,   0ull},
39062         {"CNT0SEL"                     ,        0,      6,      277,    "R/W",  0,      0,      0ull,   0ull},
39063         {"CNT0CLR"                     ,        6,      1,      277,    "R/W",  0,      0,      0ull,   0ull},
39064         {"CNT0ENA"                     ,        7,      1,      277,    "R/W",  0,      0,      0ull,   0ull},
39065         {"CNT1SEL"                     ,        8,      6,      277,    "R/W",  0,      0,      0ull,   0ull},
39066         {"CNT1CLR"                     ,        14,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39067         {"CNT1ENA"                     ,        15,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39068         {"CNT2SEL"                     ,        16,     6,      277,    "R/W",  0,      0,      0ull,   0ull},
39069         {"CNT2CLR"                     ,        22,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39070         {"CNT2ENA"                     ,        23,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39071         {"CNT3SEL"                     ,        24,     6,      277,    "R/W",  0,      0,      0ull,   0ull},
39072         {"CNT3CLR"                     ,        30,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39073         {"CNT3ENA"                     ,        31,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39074         {"CNT0RDCLR"                   ,        32,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39075         {"CNT1RDCLR"                   ,        33,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39076         {"CNT2RDCLR"                   ,        34,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39077         {"CNT3RDCLR"                   ,        35,     1,      277,    "R/W",  0,      0,      0ull,   0ull},
39078         {"RESERVED_36_63"              ,        36,     28,     277,    "RAZ",  0,      0,      0ull,   0ull},
39079         {"PP0GRP"                      ,        0,      2,      278,    "R/W",  0,      0,      0ull,   0ull},
39080         {"PP1GRP"                      ,        2,      2,      278,    "R/W",  0,      0,      0ull,   0ull},
39081         {"PP2GRP"                      ,        4,      2,      278,    "R/W",  0,      0,      0ull,   0ull},
39082         {"PP3GRP"                      ,        6,      2,      278,    "R/W",  0,      0,      0ull,   0ull},
39083         {"PP4GRP"                      ,        8,      2,      278,    "R/W",  0,      0,      0ull,   0ull},
39084         {"PP5GRP"                      ,        10,     2,      278,    "R/W",  0,      0,      0ull,   0ull},
39085         {"PP6GRP"                      ,        12,     2,      278,    "R/W",  0,      0,      0ull,   0ull},
39086         {"PP7GRP"                      ,        14,     2,      278,    "R/W",  0,      0,      0ull,   0ull},
39087         {"PP8GRP"                      ,        16,     2,      278,    "R/W",  0,      0,      0ull,   0ull},
39088         {"PP9GRP"                      ,        18,     2,      278,    "R/W",  0,      0,      0ull,   0ull},
39089         {"PP10GRP"                     ,        20,     2,      278,    "R/W",  0,      0,      0ull,   0ull},
39090         {"PP11GRP"                     ,        22,     2,      278,    "R/W",  0,      0,      0ull,   0ull},
39091         {"RESERVED_24_63"              ,        24,     40,     278,    "RAZ",  0,      0,      0ull,   0ull},
39092         {"UMSK0"                       ,        0,      8,      279,    "R/W",  0,      0,      0ull,   0ull},
39093         {"UMSK1"                       ,        8,      8,      279,    "R/W",  0,      0,      0ull,   0ull},
39094         {"UMSK2"                       ,        16,     8,      279,    "R/W",  0,      0,      0ull,   0ull},
39095         {"UMSK3"                       ,        24,     8,      279,    "R/W",  0,      0,      0ull,   0ull},
39096         {"RESERVED_32_63"              ,        32,     32,     279,    "RAZ",  0,      0,      0ull,   0ull},
39097         {"UMSK4"                       ,        0,      8,      280,    "R/W",  0,      0,      0ull,   0ull},
39098         {"UMSK5"                       ,        8,      8,      280,    "R/W",  0,      0,      0ull,   0ull},
39099         {"UMSK6"                       ,        16,     8,      280,    "R/W",  0,      0,      0ull,   0ull},
39100         {"UMSK7"                       ,        24,     8,      280,    "R/W",  0,      0,      0ull,   0ull},
39101         {"RESERVED_32_63"              ,        32,     32,     280,    "RAZ",  0,      0,      0ull,   0ull},
39102         {"UMSK8"                       ,        0,      8,      281,    "R/W",  0,      0,      0ull,   0ull},
39103         {"UMSK9"                       ,        8,      8,      281,    "R/W",  0,      0,      0ull,   0ull},
39104         {"UMSK10"                      ,        16,     8,      281,    "R/W",  0,      0,      0ull,   0ull},
39105         {"UMSK11"                      ,        24,     8,      281,    "R/W",  0,      0,      0ull,   0ull},
39106         {"RESERVED_32_63"              ,        32,     32,     281,    "RAZ",  0,      0,      0ull,   0ull},
39107         {"UMSKIOB"                     ,        0,      8,      282,    "R/W",  0,      0,      0ull,   0ull},
39108         {"RESERVED_8_63"               ,        8,      56,     282,    "RAZ",  0,      0,      0ull,   0ull},
39109         {"Q0STAT"                      ,        0,      34,     283,    "RO",   0,      0,      0ull,   0ull},
39110         {"FTL"                         ,        34,     1,      283,    "RO",   0,      0,      0ull,   0ull},
39111         {"RESERVED_35_63"              ,        35,     29,     283,    "RAZ",  0,      0,      0ull,   0ull},
39112         {"Q1STAT"                      ,        0,      34,     284,    "RO",   0,      0,      0ull,   0ull},
39113         {"RESERVED_34_63"              ,        34,     30,     284,    "RAZ",  0,      0,      0ull,   0ull},
39114         {"Q2STAT"                      ,        0,      34,     285,    "RO",   0,      0,      0ull,   0ull},
39115         {"RESERVED_34_63"              ,        34,     30,     285,    "RAZ",  0,      0,      0ull,   0ull},
39116         {"Q3STAT"                      ,        0,      34,     286,    "RO",   0,      0,      0ull,   0ull},
39117         {"RESERVED_34_63"              ,        34,     30,     286,    "RAZ",  0,      0,      0ull,   0ull},
39118         {"ECC_ENA"                     ,        0,      1,      287,    "R/W",  0,      0,      0ull,   1ull},
39119         {"SEC_INTENA"                  ,        1,      1,      287,    "R/W",  0,      0,      0ull,   1ull},
39120         {"DED_INTENA"                  ,        2,      1,      287,    "R/W",  0,      0,      0ull,   1ull},
39121         {"SEC_ERR"                     ,        3,      1,      287,    "R/W1C",        0,      0,      0ull,   0ull},
39122         {"DED_ERR"                     ,        4,      1,      287,    "R/W1C",        0,      0,      0ull,   0ull},
39123         {"BMHCLSEL"                    ,        5,      1,      287,    "R/W",  0,      0,      0ull,   0ull},
39124         {"RESERVED_6_63"               ,        6,      58,     287,    "RAZ",  0,      0,      0ull,   0ull},
39125         {"FADR"                        ,        0,      11,     288,    "RO",   0,      0,      0ull,   0ull},
39126         {"FSET"                        ,        11,     3,      288,    "RO",   0,      0,      0ull,   0ull},
39127         {"FOWMSK"                      ,        14,     4,      288,    "RO",   0,      0,      0ull,   0ull},
39128         {"FADRU"                       ,        18,     1,      288,    "RO",   0,      0,      0ull,   0ull},
39129         {"RESERVED_19_63"              ,        19,     45,     288,    "RAZ",  0,      0,      0ull,   0ull},
39130         {"FSYN_OW0"                    ,        0,      10,     289,    "RO",   0,      0,      0ull,   0ull},
39131         {"FSYN_OW1"                    ,        10,     10,     289,    "RO",   0,      0,      0ull,   0ull},
39132         {"RESERVED_20_63"              ,        20,     44,     289,    "RAZ",  0,      0,      0ull,   0ull},
39133         {"FSYN_OW2"                    ,        0,      10,     290,    "RO",   0,      0,      0ull,   0ull},
39134         {"FSYN_OW3"                    ,        10,     10,     290,    "RO",   0,      0,      0ull,   0ull},
39135         {"RESERVED_20_63"              ,        20,     44,     290,    "RAZ",  0,      0,      0ull,   0ull},
39136         {"Q0FUS"                       ,        0,      34,     291,    "RO",   0,      0,      0ull,   0ull},
39137         {"RESERVED_34_63"              ,        34,     30,     291,    "RAZ",  0,      0,      0ull,   0ull},
39138         {"Q1FUS"                       ,        0,      34,     292,    "RO",   0,      0,      0ull,   0ull},
39139         {"RESERVED_34_63"              ,        34,     30,     292,    "RAZ",  0,      0,      0ull,   0ull},
39140         {"Q2FUS"                       ,        0,      34,     293,    "RO",   0,      0,      0ull,   0ull},
39141         {"RESERVED_34_63"              ,        34,     30,     293,    "RAZ",  0,      0,      0ull,   0ull},
39142         {"Q3FUS"                       ,        0,      34,     294,    "RO",   0,      0,      0ull,   0ull},
39143         {"CRIP_1024K"                  ,        34,     1,      294,    "RO",   0,      0,      0ull,   0ull},
39144         {"CRIP_512K"                   ,        35,     1,      294,    "RO",   0,      0,      0ull,   0ull},
39145         {"RESERVED_36_36"              ,        36,     1,      294,    "RAZ",  0,      0,      0ull,   0ull},
39146         {"EMA_CTL"                     ,        37,     3,      294,    "RO",   0,      0,      0ull,   0ull},
39147         {"RESERVED_40_63"              ,        40,     24,     294,    "RAZ",  0,      0,      0ull,   0ull},
39148         {"ECC_ENA"                     ,        0,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
39149         {"SEC_INTENA"                  ,        1,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
39150         {"DED_INTENA"                  ,        2,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
39151         {"SEC_ERR"                     ,        3,      1,      295,    "R/W1C",        0,      0,      0ull,   0ull},
39152         {"DED_ERR"                     ,        4,      1,      295,    "R/W1C",        0,      0,      0ull,   0ull},
39153         {"FSYN"                        ,        5,      6,      295,    "RO",   0,      0,      0ull,   0ull},
39154         {"FADR"                        ,        11,     10,     295,    "RO",   0,      0,      0ull,   0ull},
39155         {"FSET"                        ,        21,     3,      295,    "RO",   0,      0,      0ull,   0ull},
39156         {"LCKERR"                      ,        24,     1,      295,    "R/W1C",        0,      0,      0ull,   0ull},
39157         {"LCK_INTENA"                  ,        25,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
39158         {"LCKERR2"                     ,        26,     1,      295,    "R/W1C",        0,      0,      0ull,   0ull},
39159         {"LCK_INTENA2"                 ,        27,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
39160         {"FADRU"                       ,        28,     1,      295,    "RO",   0,      0,      0ull,   0ull},
39161         {"RESERVED_29_63"              ,        29,     35,     295,    "RAZ",  0,      0,      0ull,   0ull},
39162         {"RATE"                        ,        0,      8,      296,    "R/W",  0,      0,      4ull,   4ull},
39163         {"RESERVED_8_63"               ,        8,      56,     296,    "RAZ",  1,      1,      0,      0},
39164         {"PHASE"                       ,        0,      7,      297,    "R/W",  0,      0,      4ull,   4ull},
39165         {"RESERVED_7_63"               ,        7,      57,     297,    "RAZ",  1,      1,      0,      0},
39166         {"RATE"                        ,        0,      16,     298,    "R/W",  0,      0,      0ull,   0ull},
39167         {"RESERVED_16_63"              ,        16,     48,     298,    "RAZ",  1,      1,      0,      0},
39168         {"DBG_EN"                      ,        0,      1,      299,    "R/W",  0,      0,      0ull,   0ull},
39169         {"RESERVED_1_63"               ,        1,      63,     299,    "RAZ",  1,      1,      0,      0},
39170         {"EN"                          ,        0,      1,      300,    "R/W",  0,      0,      0ull,   1ull},
39171         {"RESERVED_1_63"               ,        1,      63,     300,    "RAZ",  1,      1,      0,      0},
39172         {"POLARITY"                    ,        0,      1,      301,    "R/W",  0,      0,      0ull,   0ull},
39173         {"RESERVED_1_63"               ,        1,      63,     301,    "RAZ",  1,      1,      0,      0},
39174         {"PRT_EN"                      ,        0,      8,      302,    "R/W",  0,      1,      0ull,   0},
39175         {"RESERVED_8_63"               ,        8,      56,     302,    "RAZ",  1,      1,      0,      0},
39176         {"FORMAT"                      ,        0,      4,      303,    "R/W",  0,      1,      0ull,   0},
39177         {"RESERVED_4_63"               ,        4,      60,     303,    "RAZ",  1,      1,      0,      0},
39178         {"STATUS"                      ,        0,      6,      304,    "R/W",  0,      0,      0ull,   0ull},
39179         {"RESERVED_6_63"               ,        6,      58,     304,    "RAZ",  1,      1,      0,      0},
39180         {"CNT"                         ,        0,      6,      305,    "R/W",  0,      0,      0ull,   0ull},
39181         {"RESERVED_6_63"               ,        6,      58,     305,    "RAZ",  1,      1,      0,      0},
39182         {"DAT"                         ,        0,      32,     306,    "R/W",  0,      1,      0ull,   0},
39183         {"RESERVED_32_63"              ,        32,     32,     306,    "RAZ",  1,      1,      0,      0},
39184         {"CLR"                         ,        0,      32,     307,    "WO",   0,      1,      0ull,   0},
39185         {"RESERVED_32_63"              ,        32,     32,     307,    "RAZ",  1,      1,      0,      0},
39186         {"SET"                         ,        0,      32,     308,    "WO",   0,      1,      0ull,   0},
39187         {"RESERVED_32_63"              ,        32,     32,     308,    "RAZ",  1,      1,      0,      0},
39188         {"START"                       ,        0,      1,      309,    "R/W",  0,      0,      0ull,   0ull},
39189         {"RESERVED_1_63"               ,        1,      63,     309,    "RAZ",  1,      0,      0,      0ull},
39190         {"MRD"                         ,        0,      3,      310,    "RO",   1,      0,      0,      0ull},
39191         {"MRF"                         ,        3,      1,      310,    "RO",   1,      0,      0,      0ull},
39192         {"MWC"                         ,        4,      1,      310,    "RO",   1,      0,      0,      0ull},
39193         {"MWD"                         ,        5,      3,      310,    "RO",   1,      0,      0,      0ull},
39194         {"MWF"                         ,        8,      1,      310,    "RO",   1,      0,      0,      0ull},
39195         {"CSRE2D"                      ,        9,      1,      310,    "RO",   1,      0,      0,      0ull},
39196         {"CSRD2E"                      ,        10,     1,      310,    "RO",   1,      0,      0,      0ull},
39197         {"RESERVED_11_63"              ,        11,     53,     310,    "RAZ",  1,      0,      0,      0ull},
39198         {"PCTL_DAT"                    ,        0,      5,      311,    "R/W",  0,      1,      0ull,   0},
39199         {"RESERVED_5_11"               ,        5,      7,      311,    "RAZ",  0,      1,      0ull,   0},
39200         {"PCTL_CSR"                    ,        12,     4,      311,    "R/W",  0,      1,      15ull,  0},
39201         {"NCTL_DAT"                    ,        16,     4,      311,    "R/W",  0,      1,      0ull,   0},
39202         {"RESERVED_20_27"              ,        20,     8,      311,    "RAZ",  0,      1,      0ull,   0},
39203         {"NCTL_CSR"                    ,        28,     4,      311,    "R/W",  0,      1,      15ull,  0},
39204         {"RESERVED_32_63"              ,        32,     32,     311,    "RAZ",  0,      0,      0ull,   0ull},
39205         {"DIC"                         ,        0,      2,      312,    "R/W",  0,      0,      0ull,   0ull},
39206         {"QS_DIC"                      ,        2,      2,      312,    "R/W",  0,      0,      2ull,   2ull},
39207         {"TSKW"                        ,        4,      2,      312,    "R/W",  0,      0,      0ull,   1ull},
39208         {"SIL_LAT"                     ,        6,      2,      312,    "R/W",  0,      0,      1ull,   1ull},
39209         {"BPRCH"                       ,        8,      1,      312,    "R/W",  0,      1,      0ull,   0},
39210         {"FPRCH2"                      ,        9,      1,      312,    "R/W",  0,      0,      0ull,   1ull},
39211         {"MODE32B"                     ,        10,     1,      312,    "R/W",  0,      0,      0ull,   0ull},
39212         {"DRESET"                      ,        11,     1,      312,    "R/W",  0,      0,      0ull,   0ull},
39213         {"INORDER_MRF"                 ,        12,     1,      312,    "R/W",  0,      0,      0ull,   0ull},
39214         {"INORDER_MWF"                 ,        13,     1,      312,    "RAZ",  0,      0,      0ull,   0ull},
39215         {"R2R_SLOT"                    ,        14,     1,      312,    "R/W",  0,      0,      0ull,   0ull},
39216         {"RDIMM_ENA"                   ,        15,     1,      312,    "R/W",  0,      1,      0ull,   0},
39217         {"RESERVED_16_17"              ,        16,     2,      312,    "RAZ",  0,      0,      0ull,   0ull},
39218         {"MAX_WRITE_BATCH"             ,        18,     4,      312,    "R/W",  0,      0,      8ull,   8ull},
39219         {"XOR_BANK"                    ,        22,     1,      312,    "R/W",  0,      0,      0ull,   1ull},
39220         {"SLOW_SCF"                    ,        23,     1,      312,    "R/W",  0,      0,      0ull,   0ull},
39221         {"DDR__PCTL"                   ,        24,     4,      312,    "RO",   1,      1,      0,      0},
39222         {"DDR__NCTL"                   ,        28,     4,      312,    "RO",   1,      1,      0,      0},
39223         {"RESERVED_32_63"              ,        32,     32,     312,    "RAZ",  1,      1,      0,      0},
39224         {"RESERVED_0_7"                ,        0,      8,      313,    "RAZ",  0,      1,      0ull,   0},
39225         {"DCC_ENABLE"                  ,        8,      1,      313,    "R/W",  0,      0,      0ull,   0ull},
39226         {"SIL_MODE"                    ,        9,      1,      313,    "R/W",  0,      0,      0ull,   1ull},
39227         {"SEQUENCE"                    ,        10,     3,      313,    "R/W",  0,      0,      0ull,   0ull},
39228         {"IDLEPOWER"                   ,        13,     3,      313,    "R/W",  0,      0,      0ull,   6ull},
39229         {"FORCEWRITE"                  ,        16,     4,      313,    "R/W",  0,      0,      0ull,   0ull},
39230         {"ECC_ADR"                     ,        20,     1,      313,    "R/W",  0,      0,      0ull,   1ull},
39231         {"RESERVED_21_63"              ,        21,     43,     313,    "RAZ",  1,      1,      0,      0},
39232         {"DCLKCNT_HI"                  ,        0,      32,     314,    "RO",   0,      0,      0ull,   0ull},
39233         {"RESERVED_32_63"              ,        32,     32,     314,    "RAZ",  1,      1,      0,      0},
39234         {"DCLKCNT_LO"                  ,        0,      32,     315,    "RO",   0,      0,      0ull,   0ull},
39235         {"RESERVED_32_63"              ,        32,     32,     315,    "RAZ",  1,      1,      0,      0},
39236         {"DCLK90_VLU"                  ,        0,      5,      316,    "R/W",  0,      1,      0ull,   0},
39237         {"DCLK90_LD"                   ,        5,      1,      316,    "R/W",  0,      1,      0ull,   0},
39238         {"DCLK90_BYP"                  ,        6,      1,      316,    "R/W",  0,      1,      0ull,   0},
39239         {"OFF90_ENA"                   ,        7,      1,      316,    "R/W",  0,      1,      0ull,   0},
39240         {"RESERVED_8_63"               ,        8,      56,     316,    "RAZ",  1,      1,      0,      0},
39241         {"DDR2"                        ,        0,      1,      317,    "R/W",  0,      0,      1ull,   1ull},
39242         {"RDQS"                        ,        1,      1,      317,    "R/W",  0,      0,      0ull,   0ull},
39243         {"DLL90_BYP"                   ,        2,      1,      317,    "R/W",  0,      0,      0ull,   0ull},
39244         {"DLL90_VLU"                   ,        3,      5,      317,    "R/W",  0,      1,      0ull,   0},
39245         {"QDLL_ENA"                    ,        8,      1,      317,    "R/W",  0,      0,      0ull,   0ull},
39246         {"ODT_ENA"                     ,        9,      1,      317,    "R/W",  0,      0,      0ull,   0ull},
39247         {"DDR2T"                       ,        10,     1,      317,    "R/W",  0,      1,      0ull,   0},
39248         {"CRIP_MODE"                   ,        11,     1,      317,    "R/W",  0,      0,      0ull,   0ull},
39249         {"TFAW"                        ,        12,     5,      317,    "R/W",  0,      0,      0ull,   9ull},
39250         {"DDR_EOF"                     ,        17,     4,      317,    "R/W",  0,      0,      0ull,   0ull},
39251         {"SILO_HC"                     ,        21,     1,      317,    "R/W",  0,      1,      1ull,   0},
39252         {"TWR"                         ,        22,     3,      317,    "R/W",  0,      0,      3ull,   1ull},
39253         {"BWCNT"                       ,        25,     1,      317,    "R/W",  0,      0,      0ull,   0ull},
39254         {"POCAS"                       ,        26,     1,      317,    "R/W",  0,      0,      0ull,   0ull},
39255         {"ADDLAT"                      ,        27,     3,      317,    "R/W",  0,      0,      0ull,   0ull},
39256         {"BURST8"                      ,        30,     1,      317,    "R/W",  0,      0,      0ull,   1ull},
39257         {"BANK8"                       ,        31,     1,      317,    "R/W",  0,      1,      0ull,   0},
39258         {"RESERVED_32_63"              ,        32,     32,     317,    "RAZ",  0,      0,      0ull,   0ull},
39259         {"CLK"                         ,        0,      4,      318,    "R/W",  0,      0,      0ull,   0ull},
39260         {"RESERVED_4_4"                ,        4,      1,      318,    "RAZ",  0,      0,      0ull,   0ull},
39261         {"CMD"                         ,        5,      4,      318,    "R/W",  0,      0,      0ull,   0ull},
39262         {"RESERVED_9_9"                ,        9,      1,      318,    "RAZ",  0,      0,      0ull,   0ull},
39263         {"DQ"                          ,        10,     4,      318,    "R/W",  0,      0,      0ull,   0ull},
39264         {"RESERVED_14_63"              ,        14,     50,     318,    "RAZ",  0,      0,      0ull,   0ull},
39265         {"DLL90_VLU"                   ,        0,      5,      319,    "R/W",  0,      1,      0ull,   0},
39266         {"DLL90_ENA"                   ,        5,      1,      319,    "R/W",  0,      0,      0ull,   0ull},
39267         {"DLL90_BYP"                   ,        6,      1,      319,    "R/W",  0,      0,      0ull,   0ull},
39268         {"DRESET"                      ,        7,      1,      319,    "R/W",  0,      0,      1ull,   0ull},
39269         {"RESERVED_8_63"               ,        8,      56,     319,    "RAZ",  1,      1,      0,      0},
39270         {"CS_MASK"                     ,        0,      8,      320,    "R/W",  0,      1,      0ull,   0},
39271         {"RESERVED_8_15"               ,        8,      8,      320,    "RAZ",  0,      1,      0ull,   0},
39272         {"ROW_LSB"                     ,        16,     3,      320,    "R/W",  0,      1,      3ull,   0},
39273         {"BANK8"                       ,        19,     1,      320,    "R/W",  0,      1,      0ull,   0},
39274         {"RESERVED_20_63"              ,        20,     44,     320,    "RAZ",  0,      1,      0ull,   0},
39275         {"MRDSYN0"                     ,        0,      8,      321,    "RO",   0,      0,      0ull,   0ull},
39276         {"MRDSYN1"                     ,        8,      8,      321,    "RO",   0,      0,      0ull,   0ull},
39277         {"MRDSYN2"                     ,        16,     8,      321,    "RO",   0,      0,      0ull,   0ull},
39278         {"MRDSYN3"                     ,        24,     8,      321,    "RO",   0,      0,      0ull,   0ull},
39279         {"RESERVED_32_63"              ,        32,     32,     321,    "RAZ",  1,      1,      0,      0},
39280         {"FCOL"                        ,        0,      12,     322,    "RO",   0,      0,      0ull,   0ull},
39281         {"FROW"                        ,        12,     14,     322,    "RO",   0,      0,      0ull,   0ull},
39282         {"FBANK"                       ,        26,     3,      322,    "RO",   0,      0,      0ull,   0ull},
39283         {"FBUNK"                       ,        29,     1,      322,    "RO",   0,      0,      0ull,   0ull},
39284         {"FDIMM"                       ,        30,     2,      322,    "RO",   0,      0,      0ull,   0ull},
39285         {"RESERVED_32_63"              ,        32,     32,     322,    "RAZ",  1,      1,      0,      0},
39286         {"IFBCNT_HI"                   ,        0,      32,     323,    "RO",   0,      0,      0ull,   0ull},
39287         {"RESERVED_32_63"              ,        32,     32,     323,    "RAZ",  1,      1,      0,      0},
39288         {"IFBCNT_LO"                   ,        0,      32,     324,    "RO",   0,      0,      0ull,   0ull},
39289         {"RESERVED_32_63"              ,        32,     32,     324,    "RAZ",  1,      1,      0,      0},
39290         {"INIT_START"                  ,        0,      1,      325,    "WR0",  0,      0,      0ull,   0ull},
39291         {"ECC_ENA"                     ,        1,      1,      325,    "R/W",  0,      0,      0ull,   1ull},
39292         {"ROW_LSB"                     ,        2,      3,      325,    "R/W",  0,      1,      3ull,   0},
39293         {"PBANK_LSB"                   ,        5,      4,      325,    "R/W",  0,      1,      5ull,   0},
39294         {"REF_INT"                     ,        9,      6,      325,    "R/W",  0,      0,      1ull,   2ull},
39295         {"TCL"                         ,        15,     4,      325,    "R/W",  0,      1,      3ull,   0},
39296         {"INTR_SEC_ENA"                ,        19,     1,      325,    "R/W",  0,      0,      0ull,   1ull},
39297         {"INTR_DED_ENA"                ,        20,     1,      325,    "R/W",  0,      0,      0ull,   1ull},
39298         {"SEC_ERR"                     ,        21,     4,      325,    "R/W1C",        0,      0,      0ull,   0ull},
39299         {"DED_ERR"                     ,        25,     4,      325,    "R/W1C",        0,      0,      0ull,   0ull},
39300         {"BUNK_ENA"                    ,        29,     1,      325,    "R/W",  0,      1,      0ull,   0},
39301         {"SILO_QC"                     ,        30,     1,      325,    "R/W",  0,      1,      0ull,   0},
39302         {"RESET"                       ,        31,     1,      325,    "RAZ",  1,      1,      0,      0},
39303         {"RESERVED_32_63"              ,        32,     32,     325,    "RAZ",  1,      1,      0,      0},
39304         {"TRAS"                        ,        0,      5,      326,    "R/W",  0,      0,      12ull,  12ull},
39305         {"TRCD"                        ,        5,      4,      326,    "R/W",  0,      0,      4ull,   4ull},
39306         {"TWTR"                        ,        9,      4,      326,    "R/W",  0,      0,      2ull,   2ull},
39307         {"TRP"                         ,        13,     4,      326,    "R/W",  0,      0,      5ull,   4ull},
39308         {"TRFC"                        ,        17,     5,      326,    "R/W",  0,      0,      6ull,   7ull},
39309         {"TMRD"                        ,        22,     3,      326,    "R/W",  0,      0,      2ull,   2ull},
39310         {"CASLAT"                      ,        25,     3,      326,    "R/W",  0,      0,      4ull,   4ull},
39311         {"TRRD"                        ,        28,     3,      326,    "R/W",  0,      0,      2ull,   2ull},
39312         {"RESERVED_31_63"              ,        31,     33,     326,    "RAZ",  1,      1,      0,      0},
39313         {"OPSCNT_HI"                   ,        0,      32,     327,    "RO",   0,      0,      0ull,   0ull},
39314         {"RESERVED_32_63"              ,        32,     32,     327,    "RAZ",  1,      1,      0,      0},
39315         {"OPSCNT_LO"                   ,        0,      32,     328,    "RO",   0,      0,      0ull,   0ull},
39316         {"RESERVED_32_63"              ,        32,     32,     328,    "RAZ",  1,      1,      0,      0},
39317         {"EN2"                         ,        0,      1,      329,    "R/W",  0,      1,      0ull,   0},
39318         {"EN4"                         ,        1,      1,      329,    "R/W",  0,      1,      0ull,   0},
39319         {"EN6"                         ,        2,      1,      329,    "R/W",  0,      1,      0ull,   0},
39320         {"EN8"                         ,        3,      1,      329,    "R/W",  0,      1,      1ull,   0},
39321         {"EN12"                        ,        4,      1,      329,    "R/W",  0,      1,      0ull,   0},
39322         {"EN16"                        ,        5,      1,      329,    "R/W",  0,      1,      0ull,   0},
39323         {"RESERVED_6_7"                ,        6,      2,      329,    "RAZ",  0,      1,      0ull,   0},
39324         {"CLKR"                        ,        8,      6,      329,    "R/W",  0,      1,      0ull,   0},
39325         {"CLKF"                        ,        14,     12,     329,    "R/W",  0,      1,      31ull,  0},
39326         {"RESET_N"                     ,        26,     1,      329,    "R/W",  0,      0,      0ull,   1ull},
39327         {"DIV_RESET"                   ,        27,     1,      329,    "R/W",  0,      0,      1ull,   0ull},
39328         {"RESERVED_28_63"              ,        28,     36,     329,    "RAZ",  0,      1,      0ull,   0},
39329         {"FBSLIP"                      ,        0,      1,      330,    "R/W1C",        0,      1,      0ull,   0},
39330         {"RFSLIP"                      ,        1,      1,      330,    "R/W1C",        0,      1,      0ull,   0},
39331         {"RESERVED_2_21"               ,        2,      20,     330,    "RAZ",  1,      1,      0,      0},
39332         {"DDR__PCTL"                   ,        22,     5,      330,    "RO",   1,      1,      0,      0},
39333         {"DDR__NCTL"                   ,        27,     5,      330,    "RO",   1,      1,      0,      0},
39334         {"RESERVED_32_63"              ,        32,     32,     330,    "RAZ",  1,      1,      0,      0},
39335         {"BNK"                         ,        0,      3,      331,    "R/W",  0,      0,      0ull,   0ull},
39336         {"RESERVED_3_3"                ,        3,      1,      331,    "RAZ",  0,      0,      0ull,   0ull},
39337         {"COL"                         ,        4,      12,     331,    "R/W",  0,      0,      0ull,   0ull},
39338         {"ROW"                         ,        16,     16,     331,    "R/W",  0,      0,      0ull,   0ull},
39339         {"PATTERN"                     ,        32,     8,      331,    "R/W",  0,      0,      170ull, 170ull},
39340         {"RANKMASK"                    ,        40,     4,      331,    "R/W",  0,      0,      0ull,   0ull},
39341         {"RESERVED_44_63"              ,        44,     20,     331,    "RAZ",  0,      0,      0ull,   0ull},
39342         {"BYTE"                        ,        0,      4,      332,    "R/W",  0,      0,      0ull,   0ull},
39343         {"RESERVED_4_15"               ,        4,      12,     332,    "RAZ",  0,      0,      0ull,   0ull},
39344         {"BITMASK"                     ,        16,     16,     332,    "RO",   0,      0,      0ull,   0ull},
39345         {"RESERVED_32_63"              ,        32,     32,     332,    "RAZ",  0,      0,      0ull,   0ull},
39346         {"BYTE0"                       ,        0,      4,      333,    "R/W",  0,      1,      0ull,   0},
39347         {"BYTE1"                       ,        4,      4,      333,    "R/W",  0,      1,      0ull,   0},
39348         {"BYTE2"                       ,        8,      4,      333,    "R/W",  0,      1,      0ull,   0},
39349         {"BYTE3"                       ,        12,     4,      333,    "R/W",  0,      1,      0ull,   0},
39350         {"BYTE4"                       ,        16,     4,      333,    "R/W",  0,      1,      0ull,   0},
39351         {"BYTE5"                       ,        20,     4,      333,    "R/W",  0,      1,      0ull,   0},
39352         {"BYTE6"                       ,        24,     4,      333,    "R/W",  0,      1,      0ull,   0},
39353         {"BYTE7"                       ,        28,     4,      333,    "R/W",  0,      1,      0ull,   0},
39354         {"BYTE8"                       ,        32,     4,      333,    "R/W",  0,      1,      0ull,   0},
39355         {"STATUS"                      ,        36,     2,      333,    "RO",   0,      1,      0ull,   0},
39356         {"RESERVED_38_63"              ,        38,     26,     333,    "RAZ",  1,      0,      0,      0ull},
39357         {"PCTL"                        ,        0,      5,      334,    "R/W",  0,      1,      0ull,   0},
39358         {"RESERVED_5_7"                ,        5,      3,      334,    "RAZ",  0,      1,      0ull,   0},
39359         {"NCTL"                        ,        8,      4,      334,    "R/W",  0,      1,      0ull,   0},
39360         {"RESERVED_12_15"              ,        12,     4,      334,    "RAZ",  0,      1,      0ull,   0},
39361         {"ENABLE"                      ,        16,     1,      334,    "R/W",  0,      1,      0ull,   0},
39362         {"RESERVED_17_63"              ,        17,     47,     334,    "RAZ",  0,      1,      0ull,   0},
39363         {"RODT_LO0"                    ,        0,      4,      335,    "R/W",  0,      0,      15ull,  0ull},
39364         {"RODT_LO1"                    ,        4,      4,      335,    "R/W",  0,      0,      15ull,  0ull},
39365         {"RODT_LO2"                    ,        8,      4,      335,    "R/W",  0,      0,      15ull,  0ull},
39366         {"RODT_LO3"                    ,        12,     4,      335,    "R/W",  0,      0,      15ull,  0ull},
39367         {"RODT_HI0"                    ,        16,     4,      335,    "R/W",  0,      0,      15ull,  0ull},
39368         {"RODT_HI1"                    ,        20,     4,      335,    "R/W",  0,      0,      15ull,  0ull},
39369         {"RODT_HI2"                    ,        24,     4,      335,    "R/W",  0,      0,      15ull,  0ull},
39370         {"RODT_HI3"                    ,        28,     4,      335,    "R/W",  0,      0,      15ull,  0ull},
39371         {"RESERVED_32_63"              ,        32,     32,     335,    "RAZ",  1,      1,      0,      0},
39372         {"WODT_D0_R0"                  ,        0,      8,      336,    "R/W",  0,      0,      255ull, 255ull},
39373         {"WODT_D0_R1"                  ,        8,      8,      336,    "R/W",  0,      0,      255ull, 255ull},
39374         {"WODT_D1_R0"                  ,        16,     8,      336,    "R/W",  0,      0,      255ull, 255ull},
39375         {"WODT_D1_R1"                  ,        24,     8,      336,    "R/W",  0,      0,      255ull, 255ull},
39376         {"RESERVED_32_63"              ,        32,     32,     336,    "RAZ",  0,      0,      0ull,   0ull},
39377         {"WODT_D2_R0"                  ,        0,      8,      337,    "R/W",  0,      0,      255ull, 255ull},
39378         {"WODT_D2_R1"                  ,        8,      8,      337,    "R/W",  0,      0,      255ull, 255ull},
39379         {"WODT_D3_R0"                  ,        16,     8,      337,    "R/W",  0,      0,      255ull, 255ull},
39380         {"WODT_D3_R1"                  ,        24,     8,      337,    "R/W",  0,      0,      255ull, 255ull},
39381         {"RESERVED_32_63"              ,        32,     32,     337,    "RAZ",  0,      0,      0ull,   0ull},
39382         {"NCBI"                        ,        0,      1,      338,    "RO",   0,      0,      0ull,   0ull},
39383         {"LOC"                         ,        1,      1,      338,    "RO",   0,      0,      0ull,   0ull},
39384         {"DMA"                         ,        2,      1,      338,    "RO",   0,      0,      0ull,   0ull},
39385         {"NCBO_0"                      ,        3,      1,      338,    "RO",   0,      0,      0ull,   0ull},
39386         {"RESERVED_4_63"               ,        4,      60,     338,    "RAZ",  1,      1,      0,      0},
39387         {"NCTL"                        ,        0,      5,      339,    "R/W",  0,      1,      31ull,  0},
39388         {"PCTL"                        ,        5,      5,      339,    "R/W",  0,      1,      31ull,  0},
39389         {"RESERVED_10_63"              ,        10,     54,     339,    "RAZ",  1,      1,      0,      0},
39390         {"ADR"                         ,        0,      36,     340,    "R/W",  0,      1,      0ull,   0},
39391         {"SIZE"                        ,        36,     20,     340,    "R/W",  0,      1,      0ull,   0},
39392         {"ENDIAN"                      ,        56,     1,      340,    "R/W",  0,      1,      0ull,   0},
39393         {"SWAP8"                       ,        57,     1,      340,    "R/W",  0,      1,      0ull,   0},
39394         {"SWAP16"                      ,        58,     1,      340,    "R/W",  0,      1,      0ull,   0},
39395         {"SWAP32"                      ,        59,     1,      340,    "R/W",  0,      1,      0ull,   0},
39396         {"RESERVED_60_60"              ,        60,     1,      340,    "RAZ",  1,      1,      0,      0},
39397         {"CLR"                         ,        61,     1,      340,    "R/W",  0,      1,      0ull,   0},
39398         {"RW"                          ,        62,     1,      340,    "R/W",  0,      1,      0ull,   0},
39399         {"EN"                          ,        63,     1,      340,    "R/W",  0,      1,      0ull,   0},
39400         {"DONE"                        ,        0,      1,      341,    "R/W1C",        0,      1,      0ull,   0},
39401         {"DMARQ"                       ,        1,      1,      341,    "RO",   1,      1,      0,      0},
39402         {"RESERVED_2_63"               ,        2,      62,     341,    "RAZ",  1,      1,      0,      0},
39403         {"DONE"                        ,        0,      1,      342,    "R/W",  0,      1,      0ull,   0},
39404         {"DMARQ"                       ,        1,      1,      342,    "R/W",  0,      1,      0ull,   0},
39405         {"RESERVED_2_63"               ,        2,      62,     342,    "RAZ",  1,      1,      0,      0},
39406         {"DMARQ"                       ,        0,      6,      343,    "R/W",  0,      1,      63ull,  0},
39407         {"DMACK_S"                     ,        6,      6,      343,    "R/W",  0,      1,      63ull,  0},
39408         {"OE_A"                        ,        12,     6,      343,    "R/W",  0,      1,      63ull,  0},
39409         {"OE_N"                        ,        18,     6,      343,    "R/W",  0,      1,      63ull,  0},
39410         {"WE_A"                        ,        24,     6,      343,    "R/W",  0,      1,      63ull,  0},
39411         {"WE_N"                        ,        30,     6,      343,    "R/W",  0,      1,      63ull,  0},
39412         {"DMACK_H"                     ,        36,     6,      343,    "R/W",  0,      1,      63ull,  0},
39413         {"PAUSE"                       ,        42,     6,      343,    "R/W",  0,      1,      63ull,  0},
39414         {"RESERVED_48_54"              ,        48,     7,      343,    "RAZ",  1,      1,      0,      0},
39415         {"WIDTH"                       ,        55,     1,      343,    "R/W",  0,      1,      0ull,   0},
39416         {"DDR"                         ,        56,     1,      343,    "R/W",  0,      1,      0ull,   0},
39417         {"RD_DLY"                      ,        57,     3,      343,    "R/W",  0,      1,      0ull,   0},
39418         {"TIM_MULT"                    ,        60,     2,      343,    "R/W",  0,      1,      0ull,   0},
39419         {"DMARQ_PI"                    ,        62,     1,      343,    "R/W",  0,      1,      0ull,   0},
39420         {"DMACK_PI"                    ,        63,     1,      343,    "R/W",  0,      1,      0ull,   0},
39421         {"ADR_ERR"                     ,        0,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
39422         {"WAIT_ERR"                    ,        1,      1,      344,    "R/W1C",        0,      0,      0ull,   0ull},
39423         {"RESERVED_2_63"               ,        2,      62,     344,    "RAZ",  1,      1,      0,      0},
39424         {"ADR_INT"                     ,        0,      1,      345,    "R/W",  0,      1,      0ull,   0},
39425         {"WAIT_INT"                    ,        1,      1,      345,    "R/W",  0,      1,      0ull,   0},
39426         {"RESERVED_2_63"               ,        2,      62,     345,    "RAZ",  1,      1,      0,      0},
39427         {"RESERVED_0_2"                ,        0,      3,      346,    "RAZ",  1,      1,      0,      0},
39428         {"ADR"                         ,        3,      5,      346,    "R/W",  0,      1,      0ull,   0},
39429         {"RESERVED_8_63"               ,        8,      56,     346,    "RAZ",  1,      1,      0,      0},
39430         {"RESERVED_0_2"                ,        0,      3,      347,    "RAZ",  1,      1,      0,      0},
39431         {"BASE"                        ,        3,      25,     347,    "R/W",  0,      1,      0ull,   0},
39432         {"RESERVED_28_30"              ,        28,     3,      347,    "RAZ",  1,      1,      0,      0},
39433         {"EN"                          ,        31,     1,      347,    "R/W",  0,      1,      0ull,   0},
39434         {"RESERVED_32_63"              ,        32,     32,     347,    "RAZ",  1,      1,      0,      0},
39435         {"DATA"                        ,        0,      64,     348,    "R/W",  1,      1,      0,      0},
39436         {"BASE"                        ,        0,      16,     349,    "R/W",  0,      1,      0ull,   0},
39437         {"SIZE"                        ,        16,     12,     349,    "R/W",  0,      1,      0ull,   0},
39438         {"WIDTH"                       ,        28,     1,      349,    "R/W",  0,      1,      0ull,   0},
39439         {"ALE"                         ,        29,     1,      349,    "R/W",  0,      1,      0ull,   0},
39440         {"ORBIT"                       ,        30,     1,      349,    "R/W",  0,      1,      0ull,   0},
39441         {"EN"                          ,        31,     1,      349,    "R/W",  0,      1,      0ull,   0},
39442         {"OE_EXT"                      ,        32,     2,      349,    "R/W",  0,      1,      0ull,   0},
39443         {"WE_EXT"                      ,        34,     2,      349,    "R/W",  0,      1,      0ull,   0},
39444         {"SAM"                         ,        36,     1,      349,    "R/W",  0,      1,      0ull,   0},
39445         {"RD_DLY"                      ,        37,     3,      349,    "R/W",  0,      1,      0ull,   0},
39446         {"TIM_MULT"                    ,        40,     2,      349,    "R/W",  0,      1,      0ull,   0},
39447         {"DMACK"                       ,        42,     2,      349,    "R/W",  0,      1,      0ull,   0},
39448         {"RESERVED_44_63"              ,        44,     20,     349,    "RAZ",  1,      1,      0,      0},
39449         {"ADR"                         ,        0,      6,      350,    "R/W",  0,      1,      63ull,  0},
39450         {"CE"                          ,        6,      6,      350,    "R/W",  0,      1,      63ull,  0},
39451         {"OE"                          ,        12,     6,      350,    "R/W",  0,      1,      63ull,  0},
39452         {"WE"                          ,        18,     6,      350,    "R/W",  0,      1,      63ull,  0},
39453         {"RD_HLD"                      ,        24,     6,      350,    "R/W",  0,      1,      63ull,  0},
39454         {"WR_HLD"                      ,        30,     6,      350,    "R/W",  0,      1,      63ull,  0},
39455         {"PAUSE"                       ,        36,     6,      350,    "R/W",  0,      1,      63ull,  0},
39456         {"WAIT"                        ,        42,     6,      350,    "R/W",  0,      1,      63ull,  0},
39457         {"PAGE"                        ,        48,     6,      350,    "R/W",  0,      1,      63ull,  0},
39458         {"ALE"                         ,        54,     6,      350,    "R/W",  0,      1,      63ull,  0},
39459         {"PAGES"                       ,        60,     2,      350,    "R/W",  0,      1,      0ull,   0},
39460         {"WAITM"                       ,        62,     1,      350,    "R/W",  0,      1,      0ull,   0},
39461         {"PAGEM"                       ,        63,     1,      350,    "R/W",  0,      1,      0ull,   0},
39462         {"FIF_THR"                     ,        0,      6,      351,    "R/W",  0,      0,      26ull,  26ull},
39463         {"RESERVED_6_7"                ,        6,      2,      351,    "RAZ",  1,      1,      0,      0},
39464         {"FIF_CNT"                     ,        8,      6,      351,    "RO",   0,      1,      0ull,   0},
39465         {"RESERVED_14_15"              ,        14,     2,      351,    "RAZ",  1,      1,      0,      0},
39466         {"DMA_THR"                     ,        16,     6,      351,    "R/W",  0,      1,      0ull,   0},
39467         {"RESERVED_22_63"              ,        22,     42,     351,    "RAZ",  1,      1,      0,      0},
39468         {"DAT"                         ,        0,      64,     352,    "R/W",  1,      1,      0,      0},
39469         {"MAN_INFO"                    ,        0,      32,     353,    "RO",   1,      1,      0,      0},
39470         {"RESERVED_32_63"              ,        32,     32,     353,    "RAZ",  1,      1,      0,      0},
39471         {"MAN_INFO"                    ,        0,      32,     354,    "RO",   1,      1,      0,      0},
39472         {"RESERVED_32_63"              ,        32,     32,     354,    "RAZ",  1,      1,      0,      0},
39473         {"PP_DIS"                      ,        0,      12,     355,    "RO",   1,      1,      0,      0},
39474         {"RESERVED_12_15"              ,        12,     4,      355,    "RO",   1,      1,      0,      0},
39475         {"CHIP_ID"                     ,        16,     8,      355,    "RO",   1,      1,      0,      0},
39476         {"BIST_DIS"                    ,        24,     1,      355,    "RO",   1,      1,      0,      0},
39477         {"RST_SHT"                     ,        25,     1,      355,    "RO",   1,      1,      0,      0},
39478         {"NOCRYPTO"                    ,        26,     1,      355,    "RO",   1,      1,      0,      0},
39479         {"NOMUL"                       ,        27,     1,      355,    "RO",   1,      1,      0,      0},
39480         {"NODFA_CP2"                   ,        28,     1,      355,    "RO",   1,      1,      0,      0},
39481         {"NOKASU"                      ,        29,     1,      355,    "RO",   1,      1,      0,      0},
39482         {"RESERVED_30_31"              ,        30,     2,      355,    "RAZ",  1,      1,      0,      0},
39483         {"RAID_EN"                     ,        32,     1,      355,    "RO",   1,      1,      0,      0},
39484         {"FUS318"                      ,        33,     1,      355,    "RO",   1,      1,      0,      0},
39485         {"RESERVED_34_63"              ,        34,     30,     355,    "RAZ",  1,      1,      0,      0},
39486         {"ICACHE"                      ,        0,      24,     356,    "RO",   1,      1,      0,      0},
39487         {"NODFA_DTE"                   ,        24,     1,      356,    "RO",   1,      1,      0,      0},
39488         {"NOZIP"                       ,        25,     1,      356,    "RO",   1,      1,      0,      0},
39489         {"EFUS_IGN"                    ,        26,     1,      356,    "RO",   1,      1,      0,      0},
39490         {"EFUS_LCK"                    ,        27,     1,      356,    "RO",   1,      1,      0,      0},
39491         {"BAR2_EN"                     ,        28,     1,      356,    "RO",   1,      1,      0,      0},
39492         {"ZIP_CRIP"                    ,        29,     2,      356,    "RO",   1,      1,      0,      0},
39493         {"RESERVED_31_63"              ,        31,     33,     356,    "RAZ",  1,      1,      0,      0},
39494         {"EMA"                         ,        0,      3,      357,    "R/W",  1,      0,      0,      0ull},
39495         {"RESERVED_3_3"                ,        3,      1,      357,    "RAZ",  1,      1,      0,      0},
39496         {"EFF_EMA"                     ,        4,      3,      357,    "RO",   1,      0,      0,      0ull},
39497         {"RESERVED_7_63"               ,        7,      57,     357,    "RAZ",  1,      1,      0,      0},
39498         {"PDF"                         ,        0,      64,     358,    "RO",   1,      1,      0,      0},
39499         {"FBSLIP"                      ,        0,      1,      359,    "R/W1C",        0,      1,      0ull,   0},
39500         {"RFSLIP"                      ,        1,      1,      359,    "R/W1C",        0,      1,      0ull,   0},
39501         {"RESERVED_2_63"               ,        2,      62,     359,    "RAZ",  1,      1,      0,      0},
39502         {"PROG"                        ,        0,      1,      360,    "R/W",  1,      1,      0,      0},
39503         {"RESERVED_1_63"               ,        1,      63,     360,    "RAZ",  1,      1,      0,      0},
39504         {"SETUP"                       ,        0,      8,      361,    "R/W",  0,      1,      3ull,   0},
39505         {"SCLK_HI"                     ,        8,      12,     361,    "R/W",  0,      1,      100ull, 0},
39506         {"SCLK_LO"                     ,        20,     4,      361,    "R/W",  0,      1,      2ull,   0},
39507         {"OUT"                         ,        24,     8,      361,    "R/W",  0,      1,      3ull,   0},
39508         {"PROG_PIN"                    ,        32,     1,      361,    "RO",   0,      0,      0ull,   0ull},
39509         {"RESERVED_33_63"              ,        33,     31,     361,    "RAZ",  1,      1,      0,      0},
39510         {"ADDR"                        ,        0,      8,      362,    "R/W",  0,      0,      0ull,   0ull},
39511         {"EFUSE"                       ,        8,      1,      362,    "R/W",  0,      0,      0ull,   0ull},
39512         {"RESERVED_9_11"               ,        9,      3,      362,    "RAZ",  1,      1,      0,      0},
39513         {"PEND"                        ,        12,     1,      362,    "R/W",  0,      0,      0ull,   0ull},
39514         {"RESERVED_13_15"              ,        13,     3,      362,    "RAZ",  1,      1,      0,      0},
39515         {"DAT"                         ,        16,     8,      362,    "RO",   1,      1,      0,      0},
39516         {"RESERVED_24_63"              ,        24,     40,     362,    "RAZ",  1,      1,      0,      0},
39517         {"REPAIR0"                     ,        0,      14,     363,    "RO",   0,      0,      0ull,   0ull},
39518         {"REPAIR1"                     ,        14,     14,     363,    "RO",   0,      0,      0ull,   0ull},
39519         {"REPAIR2"                     ,        28,     14,     363,    "RO",   0,      0,      0ull,   0ull},
39520         {"RESERVED_42_63"              ,        42,     22,     363,    "RAZ",  1,      1,      0,      0},
39521         {"TOO_MANY"                    ,        0,      1,      364,    "RO",   0,      0,      0ull,   0ull},
39522         {"RESERVED_1_63"               ,        1,      63,     364,    "RAZ",  1,      1,      0,      0},
39523         {"ADDR"                        ,        0,      3,      365,    "R/W",  1,      1,      0,      0},
39524         {"RESERVED_3_63"               ,        3,      61,     365,    "RAZ",  1,      1,      0,      0},
39525         {"ST_INT"                      ,        0,      1,      366,    "R/W1C",        0,      1,      0ull,   0},
39526         {"TS_INT"                      ,        1,      1,      366,    "R/W1C",        0,      1,      0ull,   0},
39527         {"CORE_INT"                    ,        2,      1,      366,    "RO",   0,      1,      0ull,   0},
39528         {"RESERVED_3_3"                ,        3,      1,      366,    "RAZ",  1,      1,      0,      0},
39529         {"ST_EN"                       ,        4,      1,      366,    "R/W",  0,      1,      0ull,   0},
39530         {"TS_EN"                       ,        5,      1,      366,    "R/W",  0,      1,      0ull,   0},
39531         {"CORE_EN"                     ,        6,      1,      366,    "R/W",  0,      1,      0ull,   0},
39532         {"RESERVED_7_7"                ,        7,      1,      366,    "RAZ",  1,      1,      0,      0},
39533         {"SDA_OVR"                     ,        8,      1,      366,    "R/W",  0,      1,      0ull,   0},
39534         {"SCL_OVR"                     ,        9,      1,      366,    "R/W",  0,      1,      0ull,   0},
39535         {"SDA"                         ,        10,     1,      366,    "RO",   1,      1,      0,      0},
39536         {"SCL"                         ,        11,     1,      366,    "RO",   1,      1,      0,      0},
39537         {"RESERVED_12_63"              ,        12,     52,     366,    "RAZ",  1,      1,      0,      0},
39538         {"D"                           ,        0,      32,     367,    "R/W",  0,      1,      0ull,   0},
39539         {"EOP_IA"                      ,        32,     3,      367,    "R/W",  0,      1,      0ull,   0},
39540         {"IA"                          ,        35,     5,      367,    "R/W",  0,      1,      0ull,   0},
39541         {"A"                           ,        40,     10,     367,    "R/W",  0,      1,      0ull,   0},
39542         {"SCR"                         ,        50,     2,      367,    "R/W",  0,      1,      0ull,   0},
39543         {"SIZE"                        ,        52,     3,      367,    "R/W",  0,      1,      0ull,   0},
39544         {"SOVR"                        ,        55,     1,      367,    "R/W",  0,      1,      0ull,   0},
39545         {"R"                           ,        56,     1,      367,    "R/W",  0,      1,      0ull,   0},
39546         {"OP"                          ,        57,     4,      367,    "R/W",  0,      1,      0ull,   0},
39547         {"EIA"                         ,        61,     1,      367,    "R/W",  0,      1,      0ull,   0},
39548         {"SLONLY"                      ,        62,     1,      367,    "R/W",  0,      1,      0ull,   0},
39549         {"V"                           ,        63,     1,      367,    "RC/W", 0,      1,      0ull,   0},
39550         {"D"                           ,        0,      32,     368,    "R/W",  0,      1,      0ull,   0},
39551         {"IA"                          ,        32,     8,      368,    "R/W",  0,      1,      0ull,   0},
39552         {"RESERVED_40_63"              ,        40,     24,     368,    "RAZ",  1,      1,      0,      0},
39553         {"D"                           ,        0,      32,     369,    "R/W",  1,      1,      0,      0},
39554         {"RESERVED_32_61"              ,        32,     30,     369,    "RAZ",  1,      1,      0,      0},
39555         {"V"                           ,        62,     2,      369,    "RC/W", 0,      1,      0ull,   0},
39556         {"DLH"                         ,        0,      8,      370,    "R/W",  0,      1,      0ull,   0},
39557         {"RESERVED_8_63"               ,        8,      56,     370,    "RAZ",  1,      1,      0,      0},
39558         {"DLL"                         ,        0,      8,      371,    "R/W",  0,      1,      0ull,   0},
39559         {"RESERVED_8_63"               ,        8,      56,     371,    "RAZ",  1,      1,      0,      0},
39560         {"FAR"                         ,        0,      1,      372,    "R/W",  0,      1,      0ull,   0},
39561         {"RESERVED_1_63"               ,        1,      63,     372,    "RAZ",  1,      1,      0,      0},
39562         {"EN"                          ,        0,      1,      373,    "WO",   0,      1,      0ull,   0},
39563         {"RXFR"                        ,        1,      1,      373,    "WO",   0,      1,      0ull,   0},
39564         {"TXFR"                        ,        2,      1,      373,    "WO",   0,      1,      0ull,   0},
39565         {"RESERVED_3_3"                ,        3,      1,      373,    "RAZ",  0,      1,      0ull,   0},
39566         {"TXTRIG"                      ,        4,      2,      373,    "WO",   0,      1,      0ull,   0},
39567         {"RXTRIG"                      ,        6,      2,      373,    "WO",   0,      1,      0ull,   0},
39568         {"RESERVED_8_63"               ,        8,      56,     373,    "RAZ",  1,      1,      0,      0},
39569         {"HTX"                         ,        0,      1,      374,    "R/W",  0,      1,      0ull,   0},
39570         {"RESERVED_1_63"               ,        1,      63,     374,    "RAZ",  1,      1,      0,      0},
39571         {"ERBFI"                       ,        0,      1,      375,    "R/W",  0,      1,      0ull,   0},
39572         {"ETBEI"                       ,        1,      1,      375,    "R/W",  0,      1,      0ull,   0},
39573         {"ELSI"                        ,        2,      1,      375,    "R/W",  0,      1,      0ull,   0},
39574         {"EDSSI"                       ,        3,      1,      375,    "R/W",  0,      1,      0ull,   0},
39575         {"RESERVED_4_6"                ,        4,      3,      375,    "RAZ",  0,      1,      0ull,   0},
39576         {"PTIME"                       ,        7,      1,      375,    "R/W",  0,      1,      0ull,   0},
39577         {"RESERVED_8_63"               ,        8,      56,     375,    "RAZ",  1,      1,      0,      0},
39578         {"IID"                         ,        0,      4,      376,    "RO",   0,      1,      1ull,   0},
39579         {"RESERVED_4_5"                ,        4,      2,      376,    "RAZ",  0,      1,      0ull,   0},
39580         {"FEN"                         ,        6,      2,      376,    "RO",   0,      1,      0ull,   0},
39581         {"RESERVED_8_63"               ,        8,      56,     376,    "RAZ",  1,      1,      0,      0},
39582         {"CLS"                         ,        0,      2,      377,    "R/W",  0,      1,      0ull,   0},
39583         {"STOP"                        ,        2,      1,      377,    "R/W",  0,      1,      0ull,   0},
39584         {"PEN"                         ,        3,      1,      377,    "R/W",  0,      1,      0ull,   0},
39585         {"EPS"                         ,        4,      1,      377,    "R/W",  0,      1,      0ull,   0},
39586         {"RESERVED_5_5"                ,        5,      1,      377,    "RAZ",  0,      1,      0ull,   0},
39587         {"BRK"                         ,        6,      1,      377,    "R/W",  0,      1,      0ull,   0},
39588         {"DLAB"                        ,        7,      1,      377,    "R/W",  0,      1,      0ull,   0},
39589         {"RESERVED_8_63"               ,        8,      56,     377,    "RAZ",  1,      1,      0,      0},
39590         {"DR"                          ,        0,      1,      378,    "RO",   0,      1,      0ull,   0},
39591         {"OE"                          ,        1,      1,      378,    "RC",   0,      1,      0ull,   0},
39592         {"PE"                          ,        2,      1,      378,    "RC",   0,      1,      0ull,   0},
39593         {"FE"                          ,        3,      1,      378,    "RC",   0,      1,      0ull,   0},
39594         {"BI"                          ,        4,      1,      378,    "RC",   0,      1,      0ull,   0},
39595         {"THRE"                        ,        5,      1,      378,    "RO",   0,      1,      1ull,   0},
39596         {"TEMT"                        ,        6,      1,      378,    "RO",   0,      1,      1ull,   0},
39597         {"FERR"                        ,        7,      1,      378,    "RC",   0,      1,      0ull,   0},
39598         {"RESERVED_8_63"               ,        8,      56,     378,    "RAZ",  1,      1,      0,      0},
39599         {"DTR"                         ,        0,      1,      379,    "R/W",  0,      1,      0ull,   0},
39600         {"RTS"                         ,        1,      1,      379,    "R/W",  0,      1,      0ull,   0},
39601         {"OUT1"                        ,        2,      1,      379,    "R/W",  0,      1,      0ull,   0},
39602         {"OUT2"                        ,        3,      1,      379,    "R/W",  0,      1,      0ull,   0},
39603         {"LOOP"                        ,        4,      1,      379,    "R/W",  0,      1,      0ull,   0},
39604         {"AFCE"                        ,        5,      1,      379,    "R/W",  0,      1,      0ull,   0},
39605         {"RESERVED_6_63"               ,        6,      58,     379,    "RAZ",  0,      1,      0ull,   0},
39606         {"DCTS"                        ,        0,      1,      380,    "RC",   0,      1,      0ull,   0},
39607         {"DDSR"                        ,        1,      1,      380,    "RC",   0,      1,      0ull,   0},
39608         {"TERI"                        ,        2,      1,      380,    "RC",   0,      1,      0ull,   0},
39609         {"DDCD"                        ,        3,      1,      380,    "RC",   0,      1,      0ull,   0},
39610         {"CTS"                         ,        4,      1,      380,    "RO",   1,      1,      0,      0},
39611         {"DSR"                         ,        5,      1,      380,    "RO",   0,      1,      0ull,   0},
39612         {"RI"                          ,        6,      1,      380,    "RO",   0,      1,      0ull,   0},
39613         {"DCD"                         ,        7,      1,      380,    "RO",   0,      1,      0ull,   0},
39614         {"RESERVED_8_63"               ,        8,      56,     380,    "RAZ",  1,      1,      0,      0},
39615         {"RBR"                         ,        0,      8,      381,    "RO",   0,      1,      0ull,   0},
39616         {"RESERVED_8_63"               ,        8,      56,     381,    "RAZ",  1,      1,      0,      0},
39617         {"RFL"                         ,        0,      7,      382,    "RO",   0,      1,      0ull,   0},
39618         {"RESERVED_7_63"               ,        7,      57,     382,    "RAZ",  1,      1,      0,      0},
39619         {"RFWD"                        ,        0,      8,      383,    "WO",   0,      1,      0ull,   0},
39620         {"RFPE"                        ,        8,      1,      383,    "WO",   0,      1,      0ull,   0},
39621         {"RFFE"                        ,        9,      1,      383,    "WO",   0,      1,      0ull,   0},
39622         {"RESERVED_10_63"              ,        10,     54,     383,    "RAZ",  1,      1,      0,      0},
39623         {"SBCR"                        ,        0,      1,      384,    "R/W",  0,      1,      0ull,   0},
39624         {"RESERVED_1_63"               ,        1,      63,     384,    "RAZ",  1,      1,      0,      0},
39625         {"SCR"                         ,        0,      8,      385,    "R/W",  0,      1,      0ull,   0},
39626         {"RESERVED_8_63"               ,        8,      56,     385,    "RAZ",  1,      1,      0,      0},
39627         {"SFE"                         ,        0,      1,      386,    "R/W",  0,      1,      0ull,   0},
39628         {"RESERVED_1_63"               ,        1,      63,     386,    "RAZ",  1,      1,      0,      0},
39629         {"USR"                         ,        0,      1,      387,    "WO",   0,      1,      0ull,   0},
39630         {"SRFR"                        ,        1,      1,      387,    "WO",   0,      1,      0ull,   0},
39631         {"STFR"                        ,        2,      1,      387,    "WO",   0,      1,      0ull,   0},
39632         {"RESERVED_3_63"               ,        3,      61,     387,    "RAZ",  1,      1,      0,      0},
39633         {"SRT"                         ,        0,      2,      388,    "R/W",  0,      1,      0ull,   0},
39634         {"RESERVED_2_63"               ,        2,      62,     388,    "RAZ",  1,      1,      0,      0},
39635         {"SRTS"                        ,        0,      1,      389,    "R/W",  0,      1,      0ull,   0},
39636         {"RESERVED_1_63"               ,        1,      63,     389,    "RAZ",  1,      1,      0,      0},
39637         {"STT"                         ,        0,      2,      390,    "R/W",  0,      1,      0ull,   0},
39638         {"RESERVED_2_63"               ,        2,      62,     390,    "RAZ",  1,      1,      0,      0},
39639         {"TFL"                         ,        0,      7,      391,    "RO",   0,      1,      0ull,   0},
39640         {"RESERVED_7_63"               ,        7,      57,     391,    "RAZ",  1,      1,      0,      0},
39641         {"TFR"                         ,        0,      8,      392,    "RO",   0,      1,      0ull,   0},
39642         {"RESERVED_8_63"               ,        8,      56,     392,    "RAZ",  1,      1,      0,      0},
39643         {"THR"                         ,        0,      8,      393,    "WO",   0,      1,      0ull,   0},
39644         {"RESERVED_8_63"               ,        8,      56,     393,    "RAZ",  1,      1,      0,      0},
39645         {"BUSY"                        ,        0,      1,      394,    "RO",   0,      1,      0ull,   0},
39646         {"TFNF"                        ,        1,      1,      394,    "RO",   0,      1,      1ull,   0},
39647         {"TFE"                         ,        2,      1,      394,    "RO",   0,      1,      1ull,   0},
39648         {"RFNE"                        ,        3,      1,      394,    "RO",   0,      1,      0ull,   0},
39649         {"RFF"                         ,        4,      1,      394,    "RO",   0,      1,      0ull,   0},
39650         {"RESERVED_5_63"               ,        5,      59,     394,    "RAZ",  1,      1,      0,      0},
39651         {"ORFDAT"                      ,        0,      1,      395,    "RO",   0,      0,      0ull,   0ull},
39652         {"IRFDAT"                      ,        1,      1,      395,    "RO",   0,      0,      0ull,   0ull},
39653         {"IPFDAT"                      ,        2,      1,      395,    "RO",   0,      0,      0ull,   0ull},
39654         {"MRQDAT"                      ,        3,      1,      395,    "RO",   0,      0,      0ull,   0ull},
39655         {"RESERVED_4_63"               ,        4,      60,     395,    "RAZ",  0,      0,      0ull,   0ull},
39656         {"MRQ_HWM"                     ,        0,      2,      396,    "R/W",  0,      0,      1ull,   1ull},
39657         {"NBTARB"                      ,        2,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
39658         {"LENDIAN"                     ,        3,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
39659         {"RESET"                       ,        4,      1,      396,    "RAZ",  0,      0,      0ull,   0ull},
39660         {"EN"                          ,        5,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
39661         {"BUSY"                        ,        6,      1,      396,    "RO",   0,      0,      0ull,   0ull},
39662         {"CRC_STRIP"                   ,        7,      1,      396,    "R/W",  0,      0,      0ull,   0ull},
39663         {"RESERVED_8_63"               ,        8,      56,     396,    "RAZ",  1,      1,      0,      0},
39664         {"OVFENA"                      ,        0,      1,      397,    "R/W",  0,      0,      0ull,   0ull},
39665         {"IVFENA"                      ,        1,      1,      397,    "R/W",  0,      0,      0ull,   0ull},
39666         {"OTHENA"                      ,        2,      1,      397,    "R/W",  0,      0,      0ull,   0ull},
39667         {"ITHENA"                      ,        3,      1,      397,    "R/W",  0,      0,      0ull,   0ull},
39668         {"DATA_DRPENA"                 ,        4,      1,      397,    "R/W",  0,      0,      0ull,   0ull},
39669         {"IRUNENA"                     ,        5,      1,      397,    "R/W",  0,      0,      0ull,   0ull},
39670         {"ORUNENA"                     ,        6,      1,      397,    "R/W",  0,      0,      0ull,   0ull},
39671         {"RESERVED_7_63"               ,        7,      57,     397,    "RAZ",  1,      1,      0,      0},
39672         {"IRCNT"                       ,        0,      20,     398,    "R/W",  0,      0,      0ull,   0ull},
39673         {"RESERVED_20_63"              ,        20,     44,     398,    "RAZ",  1,      1,      0,      0},
39674         {"IRHWM"                       ,        0,      20,     399,    "R/W",  0,      0,      0ull,   0ull},
39675         {"IBPLWM"                      ,        20,     20,     399,    "R/W",  0,      0,      0ull,   0ull},
39676         {"RESERVED_40_63"              ,        40,     24,     399,    "RAZ",  1,      1,      0,      0},
39677         {"RESERVED_0_2"                ,        0,      3,      400,    "RAZ",  1,      1,      0,      0},
39678         {"IBASE"                       ,        3,      33,     400,    "R/W",  0,      1,      0ull,   0},
39679         {"RESERVED_36_39"              ,        36,     4,      400,    "RAZ",  1,      1,      0,      0},
39680         {"ISIZE"                       ,        40,     20,     400,    "R/W",  0,      1,      0ull,   0},
39681         {"RESERVED_60_63"              ,        60,     4,      400,    "RAZ",  1,      1,      0,      0},
39682         {"IDBELL"                      ,        0,      20,     401,    "R/W",  0,      1,      0ull,   0},
39683         {"RESERVED_20_31"              ,        20,     12,     401,    "RAZ",  1,      1,      0,      0},
39684         {"ITLPTR"                      ,        32,     20,     401,    "RO",   0,      1,      0ull,   0},
39685         {"RESERVED_52_63"              ,        52,     12,     401,    "RAZ",  1,      1,      0,      0},
39686         {"ODBLOVF"                     ,        0,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
39687         {"IDBLOVF"                     ,        1,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
39688         {"ORTHRESH"                    ,        2,      1,      402,    "RO",   0,      0,      0ull,   0ull},
39689         {"IRTHRESH"                    ,        3,      1,      402,    "RO",   0,      0,      0ull,   0ull},
39690         {"DATA_DRP"                    ,        4,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
39691         {"IRUN"                        ,        5,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
39692         {"ORUN"                        ,        6,      1,      402,    "R/W1C",        0,      0,      0ull,   0ull},
39693         {"RESERVED_7_63"               ,        7,      57,     402,    "RAZ",  1,      1,      0,      0},
39694         {"ORCNT"                       ,        0,      20,     403,    "R/W",  0,      0,      0ull,   0ull},
39695         {"RESERVED_20_63"              ,        20,     44,     403,    "RAZ",  1,      1,      0,      0},
39696         {"ORHWM"                       ,        0,      20,     404,    "R/W",  0,      0,      0ull,   0ull},
39697         {"RESERVED_20_63"              ,        20,     44,     404,    "RAZ",  1,      1,      0,      0},
39698         {"RESERVED_0_2"                ,        0,      3,      405,    "RAZ",  1,      1,      0,      0},
39699         {"OBASE"                       ,        3,      33,     405,    "R/W",  0,      1,      0ull,   0},
39700         {"RESERVED_36_39"              ,        36,     4,      405,    "RAZ",  1,      1,      0,      0},
39701         {"OSIZE"                       ,        40,     20,     405,    "R/W",  0,      1,      0ull,   0},
39702         {"RESERVED_60_63"              ,        60,     4,      405,    "RAZ",  1,      1,      0,      0},
39703         {"ODBELL"                      ,        0,      20,     406,    "R/W",  0,      1,      0ull,   0},
39704         {"RESERVED_20_31"              ,        20,     12,     406,    "RAZ",  1,      1,      0,      0},
39705         {"OTLPTR"                      ,        32,     20,     406,    "RO",   0,      1,      0ull,   0},
39706         {"RESERVED_52_63"              ,        52,     12,     406,    "RAZ",  1,      1,      0,      0},
39707         {"OREMCNT"                     ,        0,      20,     407,    "RO",   0,      0,      0ull,   0ull},
39708         {"RESERVED_20_31"              ,        20,     12,     407,    "RAZ",  1,      1,      0,      0},
39709         {"IREMCNT"                     ,        32,     20,     407,    "RO",   0,      0,      0ull,   0ull},
39710         {"RESERVED_52_63"              ,        52,     12,     407,    "RAZ",  1,      1,      0,      0},
39711         {"ADDR_V"                      ,        0,      1,      408,    "R/W",  0,      1,      0ull,   0},
39712         {"END_SWP"                     ,        1,      2,      408,    "R/W",  0,      1,      0ull,   0},
39713         {"CA"                          ,        3,      1,      408,    "R/W",  0,      0,      0ull,   0ull},
39714         {"ADDR_IDX"                    ,        4,      14,     408,    "R/W",  0,      1,      0ull,   0},
39715         {"RESERVED_18_31"              ,        18,     14,     408,    "RAZ",  1,      1,      0,      0},
39716         {"NCB_CMD"                     ,        0,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39717         {"MSI"                         ,        1,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39718         {"DIF4"                        ,        2,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39719         {"DIF3"                        ,        3,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39720         {"DIF2"                        ,        4,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39721         {"DIF1"                        ,        5,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39722         {"DIF0"                        ,        6,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39723         {"CSM1"                        ,        7,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39724         {"CSM0"                        ,        8,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39725         {"P2N1_P1"                     ,        9,      1,      409,    "RO",   0,      0,      0ull,   0ull},
39726         {"P2N1_P0"                     ,        10,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39727         {"P2N1_N"                      ,        11,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39728         {"P2N1_C1"                     ,        12,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39729         {"P2N1_C0"                     ,        13,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39730         {"P2N0_P1"                     ,        14,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39731         {"P2N0_P0"                     ,        15,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39732         {"P2N0_N"                      ,        16,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39733         {"P2N0_C1"                     ,        17,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39734         {"P2N0_C0"                     ,        18,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39735         {"P2N0_CO"                     ,        19,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39736         {"P2N0_NO"                     ,        20,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39737         {"P2N0_PO"                     ,        21,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39738         {"P2N1_CO"                     ,        22,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39739         {"P2N1_NO"                     ,        23,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39740         {"P2N1_PO"                     ,        24,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39741         {"CPL_P1"                      ,        25,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39742         {"CPL_P0"                      ,        26,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39743         {"N2P1_O"                      ,        27,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39744         {"N2P1_C"                      ,        28,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39745         {"N2P0_O"                      ,        29,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39746         {"N2P0_C"                      ,        30,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39747         {"D4_PST"                      ,        31,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39748         {"D3_PST"                      ,        32,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39749         {"D2_PST"                      ,        33,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39750         {"D1_PST"                      ,        34,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39751         {"D0_PST"                      ,        35,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39752         {"D4_MEM"                      ,        36,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39753         {"D3_MEM"                      ,        37,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39754         {"D2_MEM"                      ,        38,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39755         {"D1_MEM"                      ,        39,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39756         {"D0_MEM"                      ,        40,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39757         {"PKT_S1"                      ,        41,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39758         {"PKT_S0"                      ,        42,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39759         {"PKT_I1"                      ,        43,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39760         {"PKT_I0"                      ,        44,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39761         {"PKT_OUT"                     ,        45,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39762         {"PKT_OIF"                     ,        46,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39763         {"PKT_ODF"                     ,        47,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39764         {"PKT_SLM"                     ,        48,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39765         {"PKT_IND"                     ,        49,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39766         {"PKT_CNTM"                    ,        50,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39767         {"PKT_IMEM"                    ,        51,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39768         {"PKT_POUT"                    ,        52,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39769         {"PCSR_SL"                     ,        53,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39770         {"PCSR_ID"                     ,        54,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39771         {"PCSR_CNT"                    ,        55,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39772         {"PCSR_IM"                     ,        56,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39773         {"PCSR_INT"                    ,        57,     1,      409,    "RO",   0,      0,      0ull,   0ull},
39774         {"RESERVED_58_63"              ,        58,     6,      409,    "RAZ",  1,      1,      0,      0},
39775         {"WAIT_COM"                    ,        0,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
39776         {"BAR2_CAX"                    ,        1,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
39777         {"BAR2_ESX"                    ,        2,      2,      410,    "R/W",  0,      1,      0ull,   0},
39778         {"BAR2_ENB"                    ,        4,      1,      410,    "R/W",  0,      0,      0ull,   1ull},
39779         {"PTLP_RO"                     ,        5,      1,      410,    "R/W",  0,      0,      0ull,   1ull},
39780         {"RESERVED_6_6"                ,        6,      1,      410,    "RAZ",  0,      0,      0ull,   0ull},
39781         {"CTLP_RO"                     ,        7,      1,      410,    "R/W",  0,      0,      0ull,   1ull},
39782         {"INTA_MAP"                    ,        8,      2,      410,    "R/W",  0,      0,      0ull,   0ull},
39783         {"INTB_MAP"                    ,        10,     2,      410,    "R/W",  0,      0,      1ull,   1ull},
39784         {"INTC_MAP"                    ,        12,     2,      410,    "R/W",  0,      0,      2ull,   2ull},
39785         {"INTD_MAP"                    ,        14,     2,      410,    "R/W",  0,      0,      3ull,   3ull},
39786         {"INTA"                        ,        16,     1,      410,    "RO",   0,      0,      1ull,   1ull},
39787         {"INTB"                        ,        17,     1,      410,    "RO",   0,      0,      1ull,   1ull},
39788         {"INTC"                        ,        18,     1,      410,    "RO",   0,      0,      1ull,   1ull},
39789         {"INTD"                        ,        19,     1,      410,    "RO",   0,      0,      1ull,   1ull},
39790         {"WAITL_COM"                   ,        20,     1,      410,    "R/W",  0,      1,      0ull,   0},
39791         {"RESERVED_21_63"              ,        21,     43,     410,    "RAZ",  1,      1,      0,      0},
39792         {"WAIT_COM"                    ,        0,      1,      411,    "R/W",  0,      0,      0ull,   0ull},
39793         {"BAR2_CAX"                    ,        1,      1,      411,    "R/W",  0,      0,      0ull,   0ull},
39794         {"BAR2_ESX"                    ,        2,      2,      411,    "R/W",  0,      1,      0ull,   0},
39795         {"BAR2_ENB"                    ,        4,      1,      411,    "R/W",  0,      0,      0ull,   1ull},
39796         {"PTLP_RO"                     ,        5,      1,      411,    "R/W",  0,      0,      0ull,   1ull},
39797         {"RESERVED_6_6"                ,        6,      1,      411,    "RAZ",  0,      0,      0ull,   0ull},
39798         {"CTLP_RO"                     ,        7,      1,      411,    "R/W",  0,      0,      0ull,   1ull},
39799         {"INTA_MAP"                    ,        8,      2,      411,    "R/W",  0,      0,      0ull,   0ull},
39800         {"INTB_MAP"                    ,        10,     2,      411,    "R/W",  0,      0,      1ull,   1ull},
39801         {"INTC_MAP"                    ,        12,     2,      411,    "R/W",  0,      0,      2ull,   2ull},
39802         {"INTD_MAP"                    ,        14,     2,      411,    "R/W",  0,      0,      3ull,   3ull},
39803         {"INTA"                        ,        16,     1,      411,    "RO",   0,      0,      1ull,   1ull},
39804         {"INTB"                        ,        17,     1,      411,    "RO",   0,      0,      1ull,   1ull},
39805         {"INTC"                        ,        18,     1,      411,    "RO",   0,      0,      1ull,   1ull},
39806         {"INTD"                        ,        19,     1,      411,    "RO",   0,      0,      1ull,   1ull},
39807         {"WAITL_COM"                   ,        20,     1,      411,    "R/W",  0,      1,      0ull,   0},
39808         {"RESERVED_21_63"              ,        21,     43,     411,    "RAZ",  1,      1,      0,      0},
39809         {"CHIP_REV"                    ,        0,      8,      412,    "RO",   1,      1,      0,      0},
39810         {"HOST_MODE"                   ,        8,      1,      412,    "RO",   1,      1,      0,      0},
39811         {"PKT_BP"                      ,        9,      4,      412,    "R/W",  0,      0,      15ull,  15ull},
39812         {"ARB"                         ,        13,     1,      412,    "R/W",  0,      0,      0ull,   1ull},
39813         {"LNK_RST"                     ,        14,     1,      412,    "R/W1C",        0,      0,      0ull,   0ull},
39814         {"RESERVED_15_63"              ,        15,     49,     412,    "RAZ",  1,      1,      0,      0},
39815         {"C0_B0_D"                     ,        0,      1,      413,    "R/W",  0,      0,      0ull,   0ull},
39816         {"C0_WI_D"                     ,        1,      1,      413,    "R/W",  0,      0,      0ull,   0ull},
39817         {"C1_B0_D"                     ,        2,      1,      413,    "R/W",  0,      0,      0ull,   0ull},
39818         {"C1_WI_D"                     ,        3,      1,      413,    "R/W",  0,      0,      0ull,   0ull},
39819         {"C0_B1_S"                     ,        4,      3,      413,    "R/W",  0,      0,      1ull,   1ull},
39820         {"C1_B1_S"                     ,        7,      3,      413,    "R/W",  0,      0,      1ull,   1ull},
39821         {"C0_W_FLT"                    ,        10,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
39822         {"C1_W_FLT"                    ,        11,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
39823         {"MRRS"                        ,        12,     3,      413,    "R/W",  0,      0,      2ull,   2ull},
39824         {"MPS"                         ,        15,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
39825         {"RESERVED_16_63"              ,        16,     48,     413,    "RAZ",  1,      1,      0,      0},
39826         {"P0_FCNT"                     ,        0,      6,      414,    "RO",   0,      1,      0ull,   0},
39827         {"P0_UCNT"                     ,        6,      16,     414,    "RO",   0,      1,      0ull,   0},
39828         {"P1_FCNT"                     ,        22,     6,      414,    "RO",   0,      1,      0ull,   0},
39829         {"P1_UCNT"                     ,        28,     16,     414,    "RO",   0,      1,      0ull,   0},
39830         {"RESERVED_44_63"              ,        44,     20,     414,    "RAZ",  1,      1,      0,      0},
39831         {"DATA"                        ,        0,      17,     415,    "RO",   0,      1,      0ull,   0},
39832         {"DSEL_EXT"                    ,        17,     1,      415,    "R/W",  0,      0,      1ull,   0ull},
39833         {"C_MUL"                       ,        18,     5,      415,    "RO",   1,      1,      0,      0},
39834         {"QLM1_SPD"                    ,        23,     2,      415,    "RO",   1,      1,      0,      0},
39835         {"QLM3_SPD"                    ,        25,     2,      415,    "RO",   1,      1,      0,      0},
39836         {"QLM0_REV_LANES"              ,        27,     1,      415,    "RO",   1,      1,      0,      0},
39837         {"QLM2_REV_LANES"              ,        28,     1,      415,    "RO",   1,      1,      0,      0},
39838         {"RESERVED_29_63"              ,        29,     35,     415,    "RAZ",  1,      1,      0,      0},
39839         {"DBG_SEL"                     ,        0,      16,     416,    "R/W",  0,      1,      0ull,   0},
39840         {"RESERVED_16_63"              ,        16,     48,     416,    "RAZ",  1,      1,      0,      0},
39841         {"DBELL"                       ,        0,      32,     417,    "RO",   0,      0,      0ull,   0ull},
39842         {"FCNT"                        ,        32,     7,      417,    "RO",   0,      0,      0ull,   0ull},
39843         {"RESERVED_39_63"              ,        39,     25,     417,    "RAZ",  1,      1,      0,      0},
39844         {"DBELL"                       ,        0,      16,     418,    "R/W",  0,      1,      0ull,   0},
39845         {"RESERVED_16_31"              ,        16,     16,     418,    "RAZ",  1,      1,      0,      0},
39846         {"RESERVED_0_6"                ,        0,      7,      419,    "RAZ",  1,      1,      0,      0},
39847         {"SADDR"                       ,        7,      29,     419,    "R/W",  0,      1,      0ull,   0},
39848         {"RESERVED_36_63"              ,        36,     28,     419,    "RAZ",  1,      1,      0,      0},
39849         {"ADDR"                        ,        0,      36,     420,    "RO",   0,      1,      0ull,   0},
39850         {"RESERVED_36_63"              ,        36,     28,     420,    "RAZ",  1,      1,      0,      0},
39851         {"CNT"                         ,        0,      32,     421,    "R/W",  0,      1,      0ull,   0},
39852         {"TIME"                        ,        32,     32,     421,    "R/W",  0,      1,      0ull,   0},
39853         {"CNT"                         ,        0,      32,     422,    "R/W",  0,      1,      0ull,   0},
39854         {"TIME"                        ,        32,     32,     422,    "R/W",  0,      1,      0ull,   0},
39855         {"DMA0"                        ,        0,      32,     423,    "R/W",  0,      1,      0ull,   0},
39856         {"DMA1"                        ,        32,     32,     423,    "R/W",  0,      1,      0ull,   0},
39857         {"CSIZE"                       ,        0,      14,     424,    "R/W",  0,      1,      0ull,   0},
39858         {"O_MODE"                      ,        14,     1,      424,    "R/W",  0,      0,      0ull,   1ull},
39859         {"O_ES"                        ,        15,     2,      424,    "R/W",  0,      1,      0ull,   0},
39860         {"O_NS"                        ,        17,     1,      424,    "R/W",  0,      1,      0ull,   0},
39861         {"O_RO"                        ,        18,     1,      424,    "R/W",  0,      1,      0ull,   0},
39862         {"O_ADD1"                      ,        19,     1,      424,    "R/W",  0,      0,      0ull,   1ull},
39863         {"FPA_QUE"                     ,        20,     3,      424,    "R/W",  0,      1,      0ull,   0},
39864         {"DWB_ICHK"                    ,        23,     9,      424,    "R/W",  0,      1,      0ull,   0},
39865         {"DWB_DENB"                    ,        32,     1,      424,    "R/W",  0,      0,      0ull,   1ull},
39866         {"B0_LEND"                     ,        33,     1,      424,    "R/W",  0,      0,      0ull,   0ull},
39867         {"DMA0_ENB"                    ,        34,     1,      424,    "R/W",  0,      0,      0ull,   1ull},
39868         {"DMA1_ENB"                    ,        35,     1,      424,    "R/W",  0,      0,      0ull,   1ull},
39869         {"DMA2_ENB"                    ,        36,     1,      424,    "R/W",  0,      0,      0ull,   1ull},
39870         {"DMA3_ENB"                    ,        37,     1,      424,    "R/W",  0,      0,      0ull,   1ull},
39871         {"DMA4_ENB"                    ,        38,     1,      424,    "R/W",  0,      0,      0ull,   1ull},
39872         {"RESERVED_39_63"              ,        39,     25,     424,    "RAZ",  1,      1,      0,      0},
39873         {"D4_REQST"                    ,        0,      5,      425,    "RO",   0,      1,      0ull,   0},
39874         {"D3_REQST"                    ,        5,      5,      425,    "RO",   0,      1,      0ull,   0},
39875         {"D2_REQST"                    ,        10,     5,      425,    "RO",   0,      1,      0ull,   0},
39876         {"D1_REQST"                    ,        15,     5,      425,    "RO",   0,      1,      0ull,   0},
39877         {"D0_REQST"                    ,        20,     5,      425,    "RO",   0,      1,      0ull,   0},
39878         {"D4_DIFST"                    ,        25,     7,      425,    "RO",   0,      1,      0ull,   0},
39879         {"D3_DIFST"                    ,        32,     7,      425,    "RO",   0,      1,      0ull,   0},
39880         {"D2_DIFST"                    ,        39,     7,      425,    "RO",   0,      1,      0ull,   0},
39881         {"D1_DIFST"                    ,        46,     7,      425,    "RO",   0,      1,      0ull,   0},
39882         {"D0_DIFST"                    ,        53,     7,      425,    "RO",   0,      1,      0ull,   0},
39883         {"RESERVED_60_63"              ,        60,     4,      425,    "RAZ",  0,      0,      0ull,   0ull},
39884         {"D4_DFFST"                    ,        0,      9,      426,    "RO",   0,      1,      0ull,   0},
39885         {"D3_DFFST"                    ,        9,      9,      426,    "RO",   0,      1,      0ull,   0},
39886         {"D2_DFFST"                    ,        18,     9,      426,    "RO",   0,      1,      0ull,   0},
39887         {"D1_DFFST"                    ,        27,     9,      426,    "RO",   0,      1,      0ull,   0},
39888         {"D0_DFFST"                    ,        36,     9,      426,    "RO",   0,      1,      0ull,   0},
39889         {"RESERVED_45_63"              ,        45,     19,     426,    "RAZ",  0,      0,      0ull,   0ull},
39890         {"D3_DREST"                    ,        0,      15,     427,    "RO",   0,      1,      0ull,   0},
39891         {"D2_DREST"                    ,        15,     15,     427,    "RO",   0,      1,      0ull,   0},
39892         {"D1_DREST"                    ,        30,     15,     427,    "RO",   0,      1,      0ull,   0},
39893         {"D0_DREST"                    ,        45,     15,     427,    "RO",   0,      1,      0ull,   0},
39894         {"RESERVED_60_63"              ,        60,     4,      427,    "RAZ",  0,      0,      0ull,   0ull},
39895         {"D3_DWEST"                    ,        0,      13,     428,    "RO",   0,      1,      0ull,   0},
39896         {"D2_DWEST"                    ,        13,     13,     428,    "RO",   0,      1,      0ull,   0},
39897         {"D1_DWEST"                    ,        26,     13,     428,    "RO",   0,      1,      0ull,   0},
39898         {"D0_DWEST"                    ,        39,     13,     428,    "RO",   0,      1,      0ull,   0},
39899         {"RESERVED_52_63"              ,        52,     12,     428,    "RAZ",  0,      0,      0ull,   0ull},
39900         {"D4_DWEST"                    ,        0,      13,     429,    "RO",   0,      1,      0ull,   0},
39901         {"D4_DREST"                    ,        13,     15,     429,    "RO",   0,      1,      0ull,   0},
39902         {"RESERVED_28_63"              ,        28,     36,     429,    "RAZ",  0,      0,      0ull,   0ull},
39903         {"RML_RTO"                     ,        0,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39904         {"RML_WTO"                     ,        1,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39905         {"BAR0_TO"                     ,        2,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39906         {"IOB2BIG"                     ,        3,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39907         {"DMA0DBO"                     ,        4,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39908         {"DMA1DBO"                     ,        5,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39909         {"DMA2DBO"                     ,        6,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39910         {"DMA3DBO"                     ,        7,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39911         {"DMA4DBO"                     ,        8,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39912         {"DMA0FI"                      ,        9,      1,      430,    "R/W",  0,      0,      0ull,   1ull},
39913         {"DMA1FI"                      ,        10,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39914         {"DCNT0"                       ,        11,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39915         {"DCNT1"                       ,        12,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39916         {"DTIME0"                      ,        13,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39917         {"DTIME1"                      ,        14,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39918         {"PSLDBOF"                     ,        15,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39919         {"PIDBOF"                      ,        16,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39920         {"PCNT"                        ,        17,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39921         {"PTIME"                       ,        18,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39922         {"C0_AERI"                     ,        19,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39923         {"RESERVED_20_20"              ,        20,     1,      430,    "RAZ",  0,      0,      0ull,   1ull},
39924         {"C0_SE"                       ,        21,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39925         {"RESERVED_22_22"              ,        22,     1,      430,    "RAZ",  0,      0,      0ull,   1ull},
39926         {"C0_WAKE"                     ,        23,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39927         {"C0_PMEI"                     ,        24,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39928         {"C0_HPINT"                    ,        25,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39929         {"C1_AERI"                     ,        26,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39930         {"RESERVED_27_27"              ,        27,     1,      430,    "RAZ",  0,      0,      0ull,   1ull},
39931         {"C1_SE"                       ,        28,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39932         {"RESERVED_29_29"              ,        29,     1,      430,    "RAZ",  0,      0,      0ull,   1ull},
39933         {"C1_WAKE"                     ,        30,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39934         {"C1_PMEI"                     ,        31,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39935         {"C1_HPINT"                    ,        32,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39936         {"C0_UP_B0"                    ,        33,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39937         {"C0_UP_B1"                    ,        34,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39938         {"C0_UP_B2"                    ,        35,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39939         {"C0_UP_WI"                    ,        36,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39940         {"C0_UP_BX"                    ,        37,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39941         {"C0_UN_B0"                    ,        38,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39942         {"C0_UN_B1"                    ,        39,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39943         {"C0_UN_B2"                    ,        40,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39944         {"C0_UN_WI"                    ,        41,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39945         {"C0_UN_BX"                    ,        42,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39946         {"C1_UP_B0"                    ,        43,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39947         {"C1_UP_B1"                    ,        44,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39948         {"C1_UP_B2"                    ,        45,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39949         {"C1_UP_WI"                    ,        46,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39950         {"C1_UP_BX"                    ,        47,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39951         {"C1_UN_B0"                    ,        48,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39952         {"C1_UN_B1"                    ,        49,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39953         {"C1_UN_B2"                    ,        50,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39954         {"C1_UN_WI"                    ,        51,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39955         {"C1_UN_BX"                    ,        52,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39956         {"C0_UN_WF"                    ,        53,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39957         {"C1_UN_WF"                    ,        54,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39958         {"C0_UP_WF"                    ,        55,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39959         {"C1_UP_WF"                    ,        56,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39960         {"C0_EXC"                      ,        57,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39961         {"C1_EXC"                      ,        58,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39962         {"C0_LDWN"                     ,        59,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39963         {"C1_LDWN"                     ,        60,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39964         {"RESERVED_61_62"              ,        61,     2,      430,    "RAZ",  0,      1,      0ull,   0},
39965         {"MIO_INTA"                    ,        63,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
39966         {"RML_RTO"                     ,        0,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39967         {"RML_WTO"                     ,        1,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39968         {"BAR0_TO"                     ,        2,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39969         {"IOB2BIG"                     ,        3,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39970         {"DMA0DBO"                     ,        4,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39971         {"DMA1DBO"                     ,        5,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39972         {"DMA2DBO"                     ,        6,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39973         {"DMA3DBO"                     ,        7,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39974         {"DMA4DBO"                     ,        8,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39975         {"DMA0FI"                      ,        9,      1,      431,    "R/W",  0,      0,      0ull,   1ull},
39976         {"DMA1FI"                      ,        10,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39977         {"DCNT0"                       ,        11,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39978         {"DCNT1"                       ,        12,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39979         {"DTIME0"                      ,        13,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39980         {"DTIME1"                      ,        14,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39981         {"PSLDBOF"                     ,        15,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39982         {"PIDBOF"                      ,        16,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39983         {"PCNT"                        ,        17,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39984         {"PTIME"                       ,        18,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39985         {"C0_AERI"                     ,        19,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39986         {"RESERVED_20_20"              ,        20,     1,      431,    "RAZ",  0,      0,      0ull,   1ull},
39987         {"C0_SE"                       ,        21,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39988         {"RESERVED_22_22"              ,        22,     1,      431,    "RAZ",  0,      0,      0ull,   1ull},
39989         {"C0_WAKE"                     ,        23,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39990         {"C0_PMEI"                     ,        24,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39991         {"C0_HPINT"                    ,        25,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39992         {"C1_AERI"                     ,        26,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39993         {"RESERVED_27_27"              ,        27,     1,      431,    "RAZ",  0,      0,      0ull,   1ull},
39994         {"C1_SE"                       ,        28,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39995         {"RESERVED_29_29"              ,        29,     1,      431,    "RAZ",  0,      0,      0ull,   1ull},
39996         {"C1_WAKE"                     ,        30,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39997         {"C1_PMEI"                     ,        31,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39998         {"C1_HPINT"                    ,        32,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
39999         {"C0_UP_B0"                    ,        33,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40000         {"C0_UP_B1"                    ,        34,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40001         {"C0_UP_B2"                    ,        35,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40002         {"C0_UP_WI"                    ,        36,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40003         {"C0_UP_BX"                    ,        37,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40004         {"C0_UN_B0"                    ,        38,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40005         {"C0_UN_B1"                    ,        39,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40006         {"C0_UN_B2"                    ,        40,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40007         {"C0_UN_WI"                    ,        41,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40008         {"C0_UN_BX"                    ,        42,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40009         {"C1_UP_B0"                    ,        43,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40010         {"C1_UP_B1"                    ,        44,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40011         {"C1_UP_B2"                    ,        45,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40012         {"C1_UP_WI"                    ,        46,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40013         {"C1_UP_BX"                    ,        47,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40014         {"C1_UN_B0"                    ,        48,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40015         {"C1_UN_B1"                    ,        49,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40016         {"C1_UN_B2"                    ,        50,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40017         {"C1_UN_WI"                    ,        51,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40018         {"C1_UN_BX"                    ,        52,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40019         {"C0_UN_WF"                    ,        53,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40020         {"C1_UN_WF"                    ,        54,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40021         {"C0_UP_WF"                    ,        55,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40022         {"C1_UP_WF"                    ,        56,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40023         {"C0_EXC"                      ,        57,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40024         {"C1_EXC"                      ,        58,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40025         {"C0_LDWN"                     ,        59,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40026         {"C1_LDWN"                     ,        60,     1,      431,    "R/W",  0,      0,      0ull,   1ull},
40027         {"RESERVED_61_63"              ,        61,     3,      431,    "RAZ",  0,      1,      0ull,   0},
40028         {"PSLDBOF"                     ,        0,      6,      432,    "RO",   0,      1,      0ull,   0},
40029         {"PIDBOF"                      ,        6,      6,      432,    "RO",   0,      1,      0ull,   0},
40030         {"RESERVED_12_63"              ,        12,     52,     432,    "RAZ",  1,      1,      0,      0},
40031         {"RML_RTO"                     ,        0,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40032         {"RML_WTO"                     ,        1,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40033         {"BAR0_TO"                     ,        2,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40034         {"IOB2BIG"                     ,        3,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40035         {"DMA0DBO"                     ,        4,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40036         {"DMA1DBO"                     ,        5,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40037         {"DMA2DBO"                     ,        6,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40038         {"DMA3DBO"                     ,        7,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40039         {"DMA4DBO"                     ,        8,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40040         {"DMA0FI"                      ,        9,      1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40041         {"DMA1FI"                      ,        10,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40042         {"DCNT0"                       ,        11,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40043         {"DCNT1"                       ,        12,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40044         {"DTIME0"                      ,        13,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40045         {"DTIME1"                      ,        14,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40046         {"RESERVED_15_18"              ,        15,     4,      433,    "RAZ",  0,      0,      0ull,   0ull},
40047         {"C0_AERI"                     ,        19,     1,      433,    "RO",   0,      0,      0ull,   0ull},
40048         {"RESERVED_20_20"              ,        20,     1,      433,    "RAZ",  0,      0,      0ull,   0ull},
40049         {"C0_SE"                       ,        21,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40050         {"RESERVED_22_22"              ,        22,     1,      433,    "RAZ",  0,      0,      0ull,   0ull},
40051         {"C0_WAKE"                     ,        23,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40052         {"C0_PMEI"                     ,        24,     1,      433,    "RO",   0,      0,      0ull,   0ull},
40053         {"C0_HPINT"                    ,        25,     1,      433,    "RO",   0,      0,      0ull,   0ull},
40054         {"C1_AERI"                     ,        26,     1,      433,    "RO",   0,      0,      0ull,   0ull},
40055         {"RESERVED_27_27"              ,        27,     1,      433,    "RAZ",  0,      0,      0ull,   0ull},
40056         {"C1_SE"                       ,        28,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40057         {"RESERVED_29_29"              ,        29,     1,      433,    "RAZ",  0,      0,      0ull,   0ull},
40058         {"C1_WAKE"                     ,        30,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40059         {"C1_PMEI"                     ,        31,     1,      433,    "RO",   0,      0,      0ull,   0ull},
40060         {"C1_HPINT"                    ,        32,     1,      433,    "RO",   0,      0,      0ull,   0ull},
40061         {"C0_UP_B0"                    ,        33,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40062         {"C0_UP_B1"                    ,        34,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40063         {"C0_UP_B2"                    ,        35,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40064         {"C0_UP_WI"                    ,        36,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40065         {"C0_UP_BX"                    ,        37,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40066         {"C0_UN_B0"                    ,        38,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40067         {"C0_UN_B1"                    ,        39,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40068         {"C0_UN_B2"                    ,        40,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40069         {"C0_UN_WI"                    ,        41,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40070         {"C0_UN_BX"                    ,        42,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40071         {"C1_UP_B0"                    ,        43,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40072         {"C1_UP_B1"                    ,        44,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40073         {"C1_UP_B2"                    ,        45,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40074         {"C1_UP_WI"                    ,        46,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40075         {"C1_UP_BX"                    ,        47,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40076         {"C1_UN_B0"                    ,        48,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40077         {"C1_UN_B1"                    ,        49,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40078         {"C1_UN_B2"                    ,        50,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40079         {"C1_UN_WI"                    ,        51,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40080         {"C1_UN_BX"                    ,        52,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40081         {"C0_UN_WF"                    ,        53,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40082         {"C1_UN_WF"                    ,        54,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40083         {"C0_UP_WF"                    ,        55,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40084         {"C1_UP_WF"                    ,        56,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40085         {"C0_EXC"                      ,        57,     1,      433,    "RO",   0,      0,      0ull,   0ull},
40086         {"C1_EXC"                      ,        58,     1,      433,    "RO",   0,      0,      0ull,   0ull},
40087         {"C0_LDWN"                     ,        59,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40088         {"C1_LDWN"                     ,        60,     1,      433,    "R/W1C",        0,      0,      0ull,   0ull},
40089         {"RESERVED_61_62"              ,        61,     2,      433,    "RAZ",  0,      0,      0ull,   0ull},
40090         {"MIO_INTA"                    ,        63,     1,      433,    "RO",   0,      0,      0ull,   0ull},
40091         {"DATA"                        ,        0,      64,     434,    "RO",   0,      1,      0ull,   0},
40092         {"DATA"                        ,        0,      64,     435,    "RO",   0,      1,      0ull,   0},
40093         {"TIMER"                       ,        0,      10,     436,    "R/W",  0,      0,      0ull,   50ull},
40094         {"MAX_WORD"                    ,        10,     4,      436,    "R/W",  0,      0,      0ull,   0ull},
40095         {"RESERVED_14_63"              ,        14,     50,     436,    "RAZ",  1,      1,      0,      0},
40096         {"BA"                          ,        0,      30,     437,    "R/W",  0,      1,      0ull,   0},
40097         {"ROW"                         ,        30,     1,      437,    "R/W",  0,      1,      0ull,   0},
40098         {"ROR"                         ,        31,     1,      437,    "R/W",  0,      1,      0ull,   0},
40099         {"NSW"                         ,        32,     1,      437,    "R/W",  0,      1,      0ull,   0},
40100         {"NSR"                         ,        33,     1,      437,    "R/W",  0,      1,      0ull,   0},
40101         {"ESW"                         ,        34,     2,      437,    "R/W",  0,      1,      0ull,   0},
40102         {"ESR"                         ,        36,     2,      437,    "R/W",  0,      1,      0ull,   0},
40103         {"NMERGE"                      ,        38,     1,      437,    "R/W",  0,      0,      0ull,   0ull},
40104         {"PORT"                        ,        39,     2,      437,    "R/W",  0,      1,      0ull,   0},
40105         {"ZERO"                        ,        41,     1,      437,    "R/W",  0,      0,      0ull,   0ull},
40106         {"RESERVED_42_63"              ,        42,     22,     437,    "RAZ",  1,      1,      0,      0},
40107         {"ENB"                         ,        0,      64,     438,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
40108         {"ENB"                         ,        0,      64,     439,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
40109         {"ENB"                         ,        0,      64,     440,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
40110         {"ENB"                         ,        0,      64,     441,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
40111         {"INTR"                        ,        0,      64,     442,    "R/W1C",        0,      0,      0ull,   0ull},
40112         {"INTR"                        ,        0,      64,     443,    "R/W1C",        0,      0,      0ull,   0ull},
40113         {"INTR"                        ,        0,      64,     444,    "R/W1C",        0,      0,      0ull,   0ull},
40114         {"INTR"                        ,        0,      64,     445,    "R/W1C",        0,      0,      0ull,   0ull},
40115         {"MSI_INT"                     ,        0,      8,      446,    "R/W",  0,      1,      0ull,   0},
40116         {"RD_INT"                      ,        8,      8,      446,    "RO",   0,      1,      0ull,   0},
40117         {"RESERVED_16_63"              ,        16,     48,     446,    "RAZ",  1,      1,      0,      0},
40118         {"MSI_INT"                     ,        0,      8,      447,    "R/W",  0,      1,      0ull,   0},
40119         {"CIU_INT"                     ,        8,      8,      447,    "R/W",  0,      1,      0ull,   0},
40120         {"RESERVED_16_63"              ,        16,     48,     447,    "RAZ",  1,      1,      0,      0},
40121         {"INTR"                        ,        0,      8,      448,    "R/W",  0,      1,      0ull,   0},
40122         {"RESERVED_8_63"               ,        8,      56,     448,    "RAZ",  1,      1,      0,      0},
40123         {"RESERVED_0_7"                ,        0,      8,      449,    "RAZ",  1,      1,      0,      0},
40124         {"INTR"                        ,        8,      8,      449,    "R/W",  0,      1,      0ull,   0},
40125         {"RESERVED_16_63"              ,        16,     48,     449,    "RAZ",  1,      1,      0,      0},
40126         {"RESERVED_0_15"               ,        0,      16,     450,    "RAZ",  1,      1,      0,      0},
40127         {"INTR"                        ,        16,     8,      450,    "R/W",  0,      1,      0ull,   0},
40128         {"RESERVED_24_63"              ,        24,     40,     450,    "RAZ",  1,      1,      0,      0},
40129         {"RESERVED_0_23"               ,        0,      24,     451,    "RAZ",  1,      1,      0,      0},
40130         {"INTR"                        ,        24,     8,      451,    "R/W",  0,      1,      0ull,   0},
40131         {"RESERVED_32_63"              ,        32,     32,     451,    "RAZ",  1,      1,      0,      0},
40132         {"MIO"                         ,        0,      1,      452,    "RO",   0,      0,      0ull,   0ull},
40133         {"GMX0"                        ,        1,      1,      452,    "RO",   0,      0,      0ull,   0ull},
40134         {"GMX1"                        ,        2,      1,      452,    "RO",   0,      0,      0ull,   0ull},
40135         {"NPEI"                        ,        3,      1,      452,    "RO",   0,      0,      0ull,   0ull},
40136         {"KEY"                         ,        4,      1,      452,    "RO",   0,      0,      0ull,   0ull},
40137         {"FPA"                         ,        5,      1,      452,    "RO",   0,      0,      0ull,   0ull},
40138         {"DFA"                         ,        6,      1,      452,    "RAZ",  0,      0,      0ull,   0ull},
40139         {"ZIP"                         ,        7,      1,      452,    "RO",   0,      0,      0ull,   0ull},
40140         {"RESERVED_8_8"                ,        8,      1,      452,    "RAZ",  0,      0,      0ull,   0ull},
40141         {"IPD"                         ,        9,      1,      452,    "RO",   0,      0,      0ull,   0ull},
40142         {"PKO"                         ,        10,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40143         {"TIM"                         ,        11,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40144         {"POW"                         ,        12,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40145         {"USB"                         ,        13,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40146         {"RAD"                         ,        14,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40147         {"USB1"                        ,        15,     1,      452,    "RAZ",  0,      0,      0ull,   0ull},
40148         {"L2C"                         ,        16,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40149         {"LMC0"                        ,        17,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40150         {"SPX0"                        ,        18,     1,      452,    "RAZ",  0,      0,      0ull,   0ull},
40151         {"SPX1"                        ,        19,     1,      452,    "RAZ",  0,      0,      0ull,   0ull},
40152         {"PIP"                         ,        20,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40153         {"RESERVED_21_21"              ,        21,     1,      452,    "RAZ",  0,      0,      0ull,   0ull},
40154         {"ASXPCS0"                     ,        22,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40155         {"ASXPCS1"                     ,        23,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40156         {"RESERVED_24_27"              ,        24,     4,      452,    "RAZ",  0,      0,      0ull,   0ull},
40157         {"AGL"                         ,        28,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40158         {"LMC1"                        ,        29,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40159         {"IOB"                         ,        30,     1,      452,    "RO",   0,      0,      0ull,   0ull},
40160         {"RESERVED_31_63"              ,        31,     33,     452,    "RAZ",  0,      0,      0ull,   0ull},
40161         {"DATA"                        ,        0,      64,     453,    "R/W",  0,      1,      0ull,   0},
40162         {"CSR"                         ,        0,      39,     454,    "RO",   0,      1,      1ull,   0},
40163         {"ARB"                         ,        39,     1,      454,    "RO",   0,      1,      0ull,   0},
40164         {"CPL0"                        ,        40,     12,     454,    "RO",   0,      1,      1ull,   0},
40165         {"CPL1"                        ,        52,     12,     454,    "RO",   0,      1,      1ull,   0},
40166         {"NND"                         ,        0,      8,      455,    "RO",   0,      1,      1ull,   0},
40167         {"NNP0"                        ,        8,      8,      455,    "RO",   0,      1,      1ull,   0},
40168         {"CSM0"                        ,        16,     15,     455,    "RO",   0,      1,      1ull,   0},
40169         {"CSM1"                        ,        31,     15,     455,    "RO",   0,      1,      1ull,   0},
40170         {"RAC"                         ,        46,     1,      455,    "RO",   0,      1,      1ull,   0},
40171         {"NPEI"                        ,        47,     1,      455,    "RO",   0,      1,      1ull,   0},
40172         {"RESERVED_48_63"              ,        48,     16,     455,    "RAZ",  1,      1,      0,      0},
40173         {"NSM0"                        ,        0,      13,     456,    "RO",   0,      1,      1ull,   0},
40174         {"NSM1"                        ,        13,     13,     456,    "RO",   0,      1,      1ull,   0},
40175         {"PSM0"                        ,        26,     15,     456,    "RO",   0,      1,      1ull,   0},
40176         {"PSM1"                        ,        41,     15,     456,    "RO",   0,      1,      1ull,   0},
40177         {"RESERVED_56_63"              ,        56,     8,      456,    "RAZ",  1,      1,      0,      0},
40178         {"RD_ADDR"                     ,        0,      48,     457,    "R/W",  0,      1,      0ull,   0},
40179         {"IOBIT"                       ,        48,     1,      457,    "RAZ",  0,      0,      0ull,   0ull},
40180         {"LD_CMD"                      ,        49,     2,      457,    "R/W",  0,      1,      0ull,   0},
40181         {"RESERVED_51_63"              ,        51,     13,     457,    "RAZ",  1,      1,      0,      0},
40182         {"RD_DATA"                     ,        0,      64,     458,    "RO",   0,      1,      0ull,   0},
40183         {"RESERVED_0_1"                ,        0,      2,      459,    "RAZ",  1,      1,      0,      0},
40184         {"WR_ADDR"                     ,        2,      46,     459,    "R/W",  0,      1,      0ull,   0},
40185         {"IOBIT"                       ,        48,     1,      459,    "RAZ",  0,      0,      0ull,   0ull},
40186         {"RESERVED_49_63"              ,        49,     15,     459,    "RAZ",  1,      1,      0,      0},
40187         {"WR_DATA"                     ,        0,      64,     460,    "R/W",  0,      1,      0ull,   0},
40188         {"WR_MASK"                     ,        0,      8,      461,    "R/W",  0,      0,      0ull,   0ull},
40189         {"RESERVED_8_63"               ,        8,      56,     461,    "RAZ",  1,      1,      0,      0},
40190         {"TIME"                        ,        0,      32,     462,    "R/W",  0,      0,      0ull,   2097152ull},
40191         {"RESERVED_32_63"              ,        32,     32,     462,    "RAZ",  1,      1,      0,      0},
40192         {"VENDID"                      ,        0,      16,     463,    "RO/WRSL",      0,      0,      6013ull,        6013ull},
40193         {"DEVID"                       ,        16,     16,     463,    "RO/WRSL",      0,      0,      80ull,  80ull},
40194         {"ISAE"                        ,        0,      1,      464,    "R/W",  0,      0,      0ull,   0ull},
40195         {"MSAE"                        ,        1,      1,      464,    "R/W",  0,      0,      0ull,   0ull},
40196         {"ME"                          ,        2,      1,      464,    "R/W",  0,      0,      0ull,   0ull},
40197         {"SCSE"                        ,        3,      1,      464,    "RO",   0,      0,      0ull,   0ull},
40198         {"MWICE"                       ,        4,      1,      464,    "RO",   0,      0,      0ull,   0ull},
40199         {"VPS"                         ,        5,      1,      464,    "RO",   0,      0,      0ull,   0ull},
40200         {"PER"                         ,        6,      1,      464,    "R/W",  0,      0,      0ull,   0ull},
40201         {"IDS_WCC"                     ,        7,      1,      464,    "RO",   0,      0,      0ull,   0ull},
40202         {"SEE"                         ,        8,      1,      464,    "R/W",  0,      0,      0ull,   0ull},
40203         {"FBBE"                        ,        9,      1,      464,    "RO",   0,      0,      0ull,   0ull},
40204         {"I_DIS"                       ,        10,     1,      464,    "R/W",  0,      0,      0ull,   0ull},
40205         {"RESERVED_11_18"              ,        11,     8,      464,    "RAZ",  1,      1,      0,      0},
40206         {"I_STAT"                      ,        19,     1,      464,    "RO",   0,      0,      0ull,   0ull},
40207         {"CL"                          ,        20,     1,      464,    "RO",   0,      0,      1ull,   1ull},
40208         {"M66"                         ,        21,     1,      464,    "RO",   0,      0,      0ull,   0ull},
40209         {"RESERVED_22_22"              ,        22,     1,      464,    "RAZ",  1,      1,      0,      0},
40210         {"FBB"                         ,        23,     1,      464,    "RO",   0,      0,      0ull,   0ull},
40211         {"MDPE"                        ,        24,     1,      464,    "R/W1C",        0,      0,      0ull,   0ull},
40212         {"DEVT"                        ,        25,     2,      464,    "RO",   0,      0,      0ull,   0ull},
40213         {"STA"                         ,        27,     1,      464,    "R/W1C",        0,      0,      0ull,   0ull},
40214         {"RTA"                         ,        28,     1,      464,    "R/W1C",        0,      0,      0ull,   0ull},
40215         {"RMA"                         ,        29,     1,      464,    "R/W1C",        0,      0,      0ull,   0ull},
40216         {"SSE"                         ,        30,     1,      464,    "R/W1C",        0,      0,      0ull,   0ull},
40217         {"DPE"                         ,        31,     1,      464,    "R/W1C",        0,      0,      0ull,   0ull},
40218         {"RID"                         ,        0,      8,      465,    "RO/WRSL",      0,      0,      0ull,   0ull},
40219         {"PI"                          ,        8,      8,      465,    "RO/WRSL",      0,      0,      0ull,   0ull},
40220         {"SC"                          ,        16,     8,      465,    "RO/WRSL",      0,      0,      48ull,  48ull},
40221         {"BCC"                         ,        24,     8,      465,    "RO/WRSL",      0,      0,      11ull,  11ull},
40222         {"CLS"                         ,        0,      8,      466,    "R/W",  0,      0,      0ull,   0ull},
40223         {"LT"                          ,        8,      8,      466,    "RO",   0,      0,      0ull,   0ull},
40224         {"CHF"                         ,        16,     7,      466,    "RO",   0,      0,      0ull,   0ull},
40225         {"MFD"                         ,        23,     1,      466,    "RO/WRSL",      0,      0,      0ull,   0ull},
40226         {"BIST"                        ,        24,     8,      466,    "RO",   0,      0,      0ull,   0ull},
40227         {"MSPC"                        ,        0,      1,      467,    "RO/WRSL",      0,      0,      0ull,   0ull},
40228         {"TYP"                         ,        1,      2,      467,    "RO/WRSL",      0,      0,      2ull,   2ull},
40229         {"PF"                          ,        3,      1,      467,    "RO/WRSL",      0,      0,      1ull,   1ull},
40230         {"RESERVED_4_13"               ,        4,      10,     467,    "RAZ",  1,      1,      0,      0},
40231         {"LBAB"                        ,        14,     18,     467,    "R/W",  0,      0,      0ull,   0ull},
40232         {"ENB"                         ,        0,      1,      468,    "WORSL",        0,      0,      1ull,   1ull},
40233         {"LMASK"                       ,        1,      31,     468,    "WORSL",        0,      0,      8191ull,        8191ull},
40234         {"UBAB"                        ,        0,      32,     469,    "R/W",  0,      0,      0ull,   0ull},
40235         {"UMASK"                       ,        0,      32,     470,    "WORSL",        0,      0,      0ull,   0ull},
40236         {"MSPC"                        ,        0,      1,      471,    "RO/WRSL",      0,      0,      0ull,   0ull},
40237         {"TYP"                         ,        1,      2,      471,    "RO/WRSL",      0,      0,      2ull,   2ull},
40238         {"PF"                          ,        3,      1,      471,    "RO/WRSL",      0,      0,      1ull,   1ull},
40239         {"RESERVED_4_25"               ,        4,      22,     471,    "RAZ",  1,      1,      0,      0},
40240         {"LBAB"                        ,        26,     6,      471,    "R/W",  0,      0,      0ull,   0ull},
40241         {"ENB"                         ,        0,      1,      472,    "WORSL",        0,      0,      1ull,   1ull},
40242         {"LMASK"                       ,        1,      31,     472,    "WORSL",        0,      0,      33554431ull,    33554431ull},
40243         {"UBAB"                        ,        0,      32,     473,    "R/W",  0,      0,      0ull,   0ull},
40244         {"UMASK"                       ,        0,      32,     474,    "WORSL",        0,      0,      0ull,   0ull},
40245         {"MSPC"                        ,        0,      1,      475,    "RO/WRSL",      0,      0,      0ull,   0ull},
40246         {"TYP"                         ,        1,      2,      475,    "RO/WRSL",      0,      0,      2ull,   2ull},
40247         {"PF"                          ,        3,      1,      475,    "RO/WRSL",      0,      0,      1ull,   1ull},
40248         {"RESERVED_4_31"               ,        4,      28,     475,    "RAZ",  1,      1,      0,      0},
40249         {"ENB"                         ,        0,      1,      476,    "WORSL",        0,      0,      1ull,   1ull},
40250         {"LMASK"                       ,        1,      31,     476,    "WORSL",        0,      0,      2147483647ull,  2147483647ull},
40251         {"RESERVED_0_6"                ,        0,      7,      477,    "RAZ",  1,      1,      0,      0},
40252         {"UBAB"                        ,        7,      25,     477,    "R/W",  0,      0,      0ull,   0ull},
40253         {"UMASK"                       ,        0,      32,     478,    "WORSL",        0,      0,      127ull, 127ull},
40254         {"CISP"                        ,        0,      32,     479,    "RO/WRSL",      0,      0,      0ull,   0ull},
40255         {"SSVID"                       ,        0,      16,     480,    "RO/WRSL",      0,      0,      6013ull,        6013ull},
40256         {"SSID"                        ,        16,     16,     480,    "RO/WRSL",      0,      0,      1ull,   1ull},
40257         {"ER_EN"                       ,        0,      1,      481,    "R/W",  0,      0,      0ull,   0ull},
40258         {"RESERVED_1_15"               ,        1,      15,     481,    "RAZ",  1,      1,      0,      0},
40259         {"ERADDR"                      ,        16,     16,     481,    "R/W",  0,      0,      0ull,   0ull},
40260         {"ENB"                         ,        0,      1,      482,    "WORSL",        0,      0,      1ull,   1ull},
40261         {"MASK"                        ,        1,      31,     482,    "WORSL",        0,      0,      2147483647ull,  2147483647ull},
40262         {"CP"                          ,        0,      8,      483,    "RO/WRSL",      0,      0,      64ull,  64ull},
40263         {"RESERVED_8_31"               ,        8,      24,     483,    "RAZ",  1,      1,      0,      0},
40264         {"IL"                          ,        0,      8,      484,    "R/W",  0,      0,      255ull, 255ull},
40265         {"INTA"                        ,        8,      8,      484,    "RO/WRSL",      0,      0,      1ull,   1ull},
40266         {"MG"                          ,        16,     8,      484,    "RO",   0,      0,      0ull,   0ull},
40267         {"ML"                          ,        24,     8,      484,    "RO",   0,      0,      0ull,   0ull},
40268         {"PMCID"                       ,        0,      8,      485,    "RO",   0,      0,      1ull,   0ull},
40269         {"NCP"                         ,        8,      8,      485,    "RO/WRSL",      0,      0,      80ull,  0ull},
40270         {"PMSV"                        ,        16,     3,      485,    "RO/WRSL",      0,      0,      3ull,   0ull},
40271         {"PME_CLOCK"                   ,        19,     1,      485,    "RO",   0,      0,      0ull,   0ull},
40272         {"RESERVED_20_20"              ,        20,     1,      485,    "RAZ",  1,      1,      0,      0},
40273         {"DSI"                         ,        21,     1,      485,    "RO/WRSL",      0,      0,      0ull,   0ull},
40274         {"AUXC"                        ,        22,     3,      485,    "RO/WRSL",      0,      0,      0ull,   0ull},
40275         {"D1S"                         ,        25,     1,      485,    "RO/WRSL",      0,      0,      0ull,   0ull},
40276         {"D2S"                         ,        26,     1,      485,    "RO/WRSL",      0,      0,      0ull,   0ull},
40277         {"PMES"                        ,        27,     5,      485,    "RO/WRSL",      0,      0,      0ull,   0ull},
40278         {"PS"                          ,        0,      2,      486,    "R/W",  0,      0,      0ull,   0ull},
40279         {"RESERVED_2_2"                ,        2,      1,      486,    "RAZ",  1,      1,      0,      0},
40280         {"NSR"                         ,        3,      1,      486,    "RO/WRSL",      0,      0,      0ull,   0ull},
40281         {"RESERVED_4_7"                ,        4,      4,      486,    "RAZ",  1,      1,      0,      0},
40282         {"PMEENS"                      ,        8,      1,      486,    "R/W",  0,      0,      0ull,   0ull},
40283         {"PMDS"                        ,        9,      4,      486,    "RO",   0,      0,      0ull,   0ull},
40284         {"PMEDSIA"                     ,        13,     2,      486,    "RO",   0,      0,      0ull,   0ull},
40285         {"PMESS"                       ,        15,     1,      486,    "R/W1C",        0,      0,      0ull,   0ull},
40286         {"RESERVED_16_21"              ,        16,     6,      486,    "RAZ",  1,      1,      0,      0},
40287         {"BD3H"                        ,        22,     1,      486,    "RO",   0,      0,      0ull,   0ull},
40288         {"BPCCEE"                      ,        23,     1,      486,    "RO",   0,      0,      0ull,   0ull},
40289         {"PMDIA"                       ,        24,     8,      486,    "RO",   0,      0,      0ull,   0ull},
40290         {"MSICID"                      ,        0,      8,      487,    "RO",   0,      0,      5ull,   5ull},
40291         {"NCP"                         ,        8,      8,      487,    "RO/WRSL",      0,      0,      112ull, 112ull},
40292         {"MSIEN"                       ,        16,     1,      487,    "R/W",  0,      0,      0ull,   0ull},
40293         {"MMC"                         ,        17,     3,      487,    "RO/WRSL",      0,      0,      0ull,   0ull},
40294         {"MME"                         ,        20,     3,      487,    "R/W",  0,      0,      0ull,   0ull},
40295         {"M64"                         ,        23,     1,      487,    "RO/WRSL",      0,      0,      1ull,   1ull},
40296         {"RESERVED_24_31"              ,        24,     8,      487,    "RAZ",  1,      1,      0,      0},
40297         {"RESERVED_0_1"                ,        0,      2,      488,    "RAZ",  1,      1,      0,      0},
40298         {"LMSI"                        ,        2,      30,     488,    "R/W",  0,      0,      0ull,   0ull},
40299         {"UMSI"                        ,        0,      32,     489,    "R/W",  0,      0,      0ull,   0ull},
40300         {"MSIMD"                       ,        0,      16,     490,    "R/W",  0,      0,      0ull,   0ull},
40301         {"RESERVED_16_31"              ,        16,     16,     490,    "RAZ",  1,      1,      0,      0},
40302         {"PCIEID"                      ,        0,      8,      491,    "RO",   0,      0,      16ull,  16ull},
40303         {"NCP"                         ,        8,      8,      491,    "RO/WRSL",      0,      0,      0ull,   0ull},
40304         {"PCIECV"                      ,        16,     4,      491,    "RO",   0,      0,      2ull,   2ull},
40305         {"DPT"                         ,        20,     4,      491,    "RO",   0,      0,      0ull,   0ull},
40306         {"SI"                          ,        24,     1,      491,    "RO/WRSL",      0,      0,      0ull,   0ull},
40307         {"IMN"                         ,        25,     5,      491,    "RO/WRSL",      0,      0,      0ull,   0ull},
40308         {"RESERVED_30_31"              ,        30,     2,      491,    "RAZ",  1,      1,      0,      0},
40309         {"MPSS"                        ,        0,      3,      492,    "RO/WRSL",      0,      0,      1ull,   1ull},
40310         {"PFS"                         ,        3,      2,      492,    "RO/WRSL",      0,      0,      0ull,   0ull},
40311         {"ETFS"                        ,        5,      1,      492,    "RO/WRSL",      0,      0,      0ull,   0ull},
40312         {"EL0AL"                       ,        6,      3,      492,    "RO/WRSL",      0,      0,      4ull,   4ull},
40313         {"EL1AL"                       ,        9,      3,      492,    "RO/WRSL",      0,      0,      3ull,   3ull},
40314         {"RESERVED_12_14"              ,        12,     3,      492,    "RAZ",  1,      1,      0,      0},
40315         {"RBER"                        ,        15,     1,      492,    "RO/WRSL",      0,      0,      1ull,   1ull},
40316         {"RESERVED_16_17"              ,        16,     2,      492,    "RAZ",  1,      1,      0,      0},
40317         {"CSPLV"                       ,        18,     8,      492,    "RO",   0,      0,      0ull,   0ull},
40318         {"CSPLS"                       ,        26,     2,      492,    "RO",   0,      0,      0ull,   0ull},
40319         {"RESERVED_28_31"              ,        28,     4,      492,    "RAZ",  1,      1,      0,      0},
40320         {"CE_EN"                       ,        0,      1,      493,    "R/W",  0,      0,      0ull,   0ull},
40321         {"NFE_EN"                      ,        1,      1,      493,    "R/W",  0,      0,      0ull,   0ull},
40322         {"FE_EN"                       ,        2,      1,      493,    "R/W",  0,      0,      0ull,   0ull},
40323         {"UR_EN"                       ,        3,      1,      493,    "R/W",  0,      0,      0ull,   0ull},
40324         {"RO_EN"                       ,        4,      1,      493,    "R/W",  0,      0,      1ull,   1ull},
40325         {"MPS"                         ,        5,      3,      493,    "R/W",  0,      0,      0ull,   0ull},
40326         {"ETF_EN"                      ,        8,      1,      493,    "R/W",  0,      0,      0ull,   0ull},
40327         {"PF_EN"                       ,        9,      1,      493,    "R/W",  0,      0,      0ull,   0ull},
40328         {"AP_EN"                       ,        10,     1,      493,    "R/W",  0,      0,      0ull,   0ull},
40329         {"NS_EN"                       ,        11,     1,      493,    "R/W",  0,      0,      1ull,   1ull},
40330         {"MRRS"                        ,        12,     3,      493,    "R/W",  0,      0,      2ull,   2ull},
40331         {"RESERVED_15_15"              ,        15,     1,      493,    "RAZ",  1,      1,      0,      0},
40332         {"CE_D"                        ,        16,     1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
40333         {"NFE_D"                       ,        17,     1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
40334         {"FE_D"                        ,        18,     1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
40335         {"UR_D"                        ,        19,     1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
40336         {"AP_D"                        ,        20,     1,      493,    "RO",   0,      0,      0ull,   0ull},
40337         {"TP"                          ,        21,     1,      493,    "RO",   0,      0,      0ull,   0ull},
40338         {"RESERVED_22_31"              ,        22,     10,     493,    "RAZ",  1,      1,      0,      0},
40339         {"MLS"                         ,        0,      4,      494,    "RO/WRSL",      0,      0,      1ull,   1ull},
40340         {"MLW"                         ,        4,      6,      494,    "RO/WRSL",      0,      0,      8ull,   8ull},
40341         {"ASLPMS"                      ,        10,     2,      494,    "RO/WRSL",      0,      0,      3ull,   3ull},
40342         {"L0EL"                        ,        12,     3,      494,    "RO/WRSL",      0,      0,      6ull,   6ull},
40343         {"L1EL"                        ,        15,     3,      494,    "RO/WRSL",      0,      0,      6ull,   6ull},
40344         {"CPM"                         ,        18,     1,      494,    "RO/WRSL",      0,      0,      0ull,   0ull},
40345         {"SDERC"                       ,        19,     1,      494,    "RO",   0,      0,      0ull,   0ull},
40346         {"DLLARC"                      ,        20,     1,      494,    "RO",   0,      0,      0ull,   0ull},
40347         {"LBNC"                        ,        21,     1,      494,    "RO",   0,      0,      0ull,   0ull},
40348         {"RESERVED_22_23"              ,        22,     2,      494,    "RAZ",  1,      1,      0,      0},
40349         {"PNUM"                        ,        24,     8,      494,    "RO/WRSL",      0,      0,      0ull,   0ull},
40350         {"ASLPC"                       ,        0,      2,      495,    "R/W",  0,      0,      0ull,   0ull},
40351         {"RESERVED_2_2"                ,        2,      1,      495,    "RAZ",  1,      1,      0,      0},
40352         {"RCB"                         ,        3,      1,      495,    "RO",   0,      0,      0ull,   0ull},
40353         {"LD"                          ,        4,      1,      495,    "RO",   0,      0,      0ull,   0ull},
40354         {"RL"                          ,        5,      1,      495,    "RO",   0,      0,      0ull,   0ull},
40355         {"CCC"                         ,        6,      1,      495,    "R/W",  0,      0,      0ull,   0ull},
40356         {"ES"                          ,        7,      1,      495,    "R/W",  0,      0,      0ull,   0ull},
40357         {"ECPM"                        ,        8,      1,      495,    "R/W",  0,      0,      0ull,   0ull},
40358         {"HAWD"                        ,        9,      1,      495,    "R/W",  0,      0,      0ull,   0ull},
40359         {"RESERVED_10_15"              ,        10,     6,      495,    "RAZ",  1,      1,      0,      0},
40360         {"LS"                          ,        16,     4,      495,    "RO",   0,      0,      1ull,   1ull},
40361         {"NLW"                         ,        20,     6,      495,    "RO",   0,      0,      0ull,   8ull},
40362         {"RESERVED_26_26"              ,        26,     1,      495,    "RAZ",  1,      1,      0,      0},
40363         {"LT"                          ,        27,     1,      495,    "RO",   0,      0,      0ull,   0ull},
40364         {"SCC"                         ,        28,     1,      495,    "RO/WRSL",      0,      0,      1ull,   1ull},
40365         {"DLLA"                        ,        29,     1,      495,    "RO",   0,      0,      0ull,   0ull},
40366         {"RESERVED_30_31"              ,        30,     2,      495,    "RAZ",  1,      1,      0,      0},
40367         {"ABP"                         ,        0,      1,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40368         {"PCP"                         ,        1,      1,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40369         {"MRLSP"                       ,        2,      1,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40370         {"AIP"                         ,        3,      1,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40371         {"PIP"                         ,        4,      1,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40372         {"HP_S"                        ,        5,      1,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40373         {"HP_C"                        ,        6,      1,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40374         {"SP_LV"                       ,        7,      8,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40375         {"SP_LS"                       ,        15,     2,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40376         {"EMIP"                        ,        17,     1,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40377         {"NCCS"                        ,        18,     1,      496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40378         {"PS_NUM"                      ,        19,     13,     496,    "RO/WRSL",      0,      0,      0ull,   0ull},
40379         {"ABP_EN"                      ,        0,      1,      497,    "R/W",  0,      0,      0ull,   0ull},
40380         {"PF_EN"                       ,        1,      1,      497,    "R/W",  0,      0,      0ull,   0ull},
40381         {"MRLS_EN"                     ,        2,      1,      497,    "R/W",  0,      0,      0ull,   0ull},
40382         {"PD_EN"                       ,        3,      1,      497,    "R/W",  0,      0,      0ull,   0ull},
40383         {"CCINT_EN"                    ,        4,      1,      497,    "R/W",  0,      0,      0ull,   0ull},
40384         {"HPINT_EN"                    ,        5,      1,      497,    "R/W",  0,      0,      0ull,   0ull},
40385         {"AIC"                         ,        6,      2,      497,    "R/W",  0,      0,      0ull,   0ull},
40386         {"PIC"                         ,        8,      2,      497,    "R/W",  0,      0,      0ull,   0ull},
40387         {"PCC"                         ,        10,     1,      497,    "R/W",  0,      0,      0ull,   0ull},
40388         {"EMIC"                        ,        11,     1,      497,    "R/W",  0,      0,      0ull,   0ull},
40389         {"DLLS_EN"                     ,        12,     1,      497,    "RO",   0,      0,      0ull,   0ull},
40390         {"RESERVED_13_15"              ,        13,     3,      497,    "RAZ",  1,      1,      0,      0},
40391         {"ABP_D"                       ,        16,     1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
40392         {"PF_D"                        ,        17,     1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
40393         {"MRLS_C"                      ,        18,     1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
40394         {"PD_C"                        ,        19,     1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
40395         {"CCINT_D"                     ,        20,     1,      497,    "R/W1C",        0,      0,      0ull,   0ull},
40396         {"MRLSS"                       ,        21,     1,      497,    "RO",   0,      0,      0ull,   0ull},
40397         {"PDS"                         ,        22,     1,      497,    "RO",   0,      0,      0ull,   0ull},
40398         {"EMIS"                        ,        23,     1,      497,    "RO",   0,      0,      0ull,   0ull},
40399         {"DLLS_C"                      ,        24,     1,      497,    "RO",   0,      0,      0ull,   0ull},
40400         {"RESERVED_25_31"              ,        25,     7,      497,    "RAZ",  1,      1,      0,      0},
40401         {"CTRS"                        ,        0,      4,      498,    "RO",   0,      0,      0ull,   0ull},
40402         {"CTDS"                        ,        4,      1,      498,    "RO",   0,      0,      1ull,   1ull},
40403         {"RESERVED_5_31"               ,        5,      27,     498,    "RAZ",  1,      1,      0,      0},
40404         {"CTV"                         ,        0,      4,      499,    "RO",   0,      0,      0ull,   0ull},
40405         {"CTD"                         ,        4,      1,      499,    "R/W",  0,      0,      0ull,   0ull},
40406         {"RESERVED_5_31"               ,        5,      27,     499,    "RAZ",  1,      1,      0,      0},
40407         {"RESERVED_0_31"               ,        0,      32,     500,    "RAZ",  1,      1,      0,      0},
40408         {"RESERVED_0_31"               ,        0,      32,     501,    "RAZ",  1,      1,      0,      0},
40409         {"RESERVED_0_31"               ,        0,      32,     502,    "RAZ",  1,      1,      0,      0},
40410         {"RESERVED_0_31"               ,        0,      32,     503,    "RAZ",  1,      1,      0,      0},
40411         {"PCIEEC"                      ,        0,      16,     504,    "RO",   0,      0,      1ull,   0ull},
40412         {"CV"                          ,        16,     4,      504,    "RO",   0,      0,      1ull,   0ull},
40413         {"NCO"                         ,        20,     12,     504,    "RO",   0,      0,      0ull,   0ull},
40414         {"RESERVED_0_3"                ,        0,      4,      505,    "RAZ",  1,      1,      0,      0},
40415         {"DLPES"                       ,        4,      1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40416         {"SDES"                        ,        5,      1,      505,    "RO",   0,      0,      0ull,   0ull},
40417         {"RESERVED_6_11"               ,        6,      6,      505,    "RAZ",  1,      1,      0,      0},
40418         {"PTLPS"                       ,        12,     1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40419         {"FCPES"                       ,        13,     1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40420         {"CTS"                         ,        14,     1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40421         {"CAS"                         ,        15,     1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40422         {"UCS"                         ,        16,     1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40423         {"ROS"                         ,        17,     1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40424         {"MTLPS"                       ,        18,     1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40425         {"ECRCES"                      ,        19,     1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40426         {"URES"                        ,        20,     1,      505,    "R/W1C",        0,      0,      0ull,   0ull},
40427         {"RESERVED_21_31"              ,        21,     11,     505,    "RAZ",  1,      1,      0,      0},
40428         {"RESERVED_0_3"                ,        0,      4,      506,    "RAZ",  1,      1,      0,      0},
40429         {"DLPEM"                       ,        4,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
40430         {"SDEM"                        ,        5,      1,      506,    "RO",   0,      0,      0ull,   0ull},
40431         {"RESERVED_6_11"               ,        6,      6,      506,    "RAZ",  1,      1,      0,      0},
40432         {"PTLPM"                       ,        12,     1,      506,    "R/W",  0,      0,      0ull,   0ull},
40433         {"FCPEM"                       ,        13,     1,      506,    "R/W",  0,      0,      0ull,   0ull},
40434         {"CTM"                         ,        14,     1,      506,    "R/W",  0,      0,      0ull,   0ull},
40435         {"CAM"                         ,        15,     1,      506,    "R/W",  0,      0,      0ull,   0ull},
40436         {"UCM"                         ,        16,     1,      506,    "R/W",  0,      0,      0ull,   0ull},
40437         {"ROM"                         ,        17,     1,      506,    "R/W",  0,      0,      0ull,   0ull},
40438         {"MTLPM"                       ,        18,     1,      506,    "R/W",  0,      0,      0ull,   0ull},
40439         {"ECRCEM"                      ,        19,     1,      506,    "R/W",  0,      0,      0ull,   0ull},
40440         {"UREM"                        ,        20,     1,      506,    "R/W",  0,      0,      0ull,   0ull},
40441         {"RESERVED_21_31"              ,        21,     11,     506,    "RAZ",  1,      1,      0,      0},
40442         {"RESERVED_0_3"                ,        0,      4,      507,    "RAZ",  1,      1,      0,      0},
40443         {"DLPES"                       ,        4,      1,      507,    "R/W",  0,      0,      1ull,   1ull},
40444         {"SDES"                        ,        5,      1,      507,    "RO",   0,      0,      1ull,   1ull},
40445         {"RESERVED_6_11"               ,        6,      6,      507,    "RAZ",  1,      1,      0,      0},
40446         {"PTLPS"                       ,        12,     1,      507,    "R/W",  0,      0,      0ull,   0ull},
40447         {"FCPES"                       ,        13,     1,      507,    "R/W",  0,      0,      1ull,   1ull},
40448         {"CTS"                         ,        14,     1,      507,    "R/W",  0,      0,      0ull,   0ull},
40449         {"CAS"                         ,        15,     1,      507,    "R/W",  0,      0,      0ull,   0ull},
40450         {"UCS"                         ,        16,     1,      507,    "R/W",  0,      0,      0ull,   0ull},
40451         {"ROS"                         ,        17,     1,      507,    "R/W",  0,      0,      1ull,   1ull},
40452         {"MTLPS"                       ,        18,     1,      507,    "R/W",  0,      0,      1ull,   1ull},
40453         {"ECRCES"                      ,        19,     1,      507,    "R/W",  0,      0,      0ull,   0ull},
40454         {"URES"                        ,        20,     1,      507,    "R/W",  0,      0,      0ull,   0ull},
40455         {"RESERVED_21_31"              ,        21,     11,     507,    "RAZ",  1,      1,      0,      0},
40456         {"RES"                         ,        0,      1,      508,    "R/W1C",        0,      0,      0ull,   0ull},
40457         {"RESERVED_1_5"                ,        1,      5,      508,    "RAZ",  1,      1,      0,      0},
40458         {"BTLPS"                       ,        6,      1,      508,    "R/W1C",        0,      0,      0ull,   0ull},
40459         {"BDLLPS"                      ,        7,      1,      508,    "R/W1C",        0,      0,      0ull,   0ull},
40460         {"RNRS"                        ,        8,      1,      508,    "R/W1C",        0,      0,      0ull,   0ull},
40461         {"RESERVED_9_11"               ,        9,      3,      508,    "RAZ",  1,      1,      0,      0},
40462         {"RTTS"                        ,        12,     1,      508,    "R/W1C",        0,      0,      0ull,   0ull},
40463         {"ANFES"                       ,        13,     1,      508,    "R/W1C",        0,      0,      0ull,   0ull},
40464         {"RESERVED_14_31"              ,        14,     18,     508,    "RAZ",  1,      1,      0,      0},
40465         {"REM"                         ,        0,      1,      509,    "R/W",  0,      0,      0ull,   0ull},
40466         {"RESERVED_1_5"                ,        1,      5,      509,    "RAZ",  1,      1,      0,      0},
40467         {"BTLPM"                       ,        6,      1,      509,    "R/W",  0,      0,      0ull,   0ull},
40468         {"BDLLPM"                      ,        7,      1,      509,    "R/W",  0,      0,      0ull,   0ull},
40469         {"RNRM"                        ,        8,      1,      509,    "R/W",  0,      0,      0ull,   0ull},
40470         {"RESERVED_9_11"               ,        9,      3,      509,    "RAZ",  1,      1,      0,      0},
40471         {"RTTM"                        ,        12,     1,      509,    "R/W",  0,      0,      0ull,   0ull},
40472         {"ANFEM"                       ,        13,     1,      509,    "R/W",  0,      0,      1ull,   1ull},
40473         {"RESERVED_14_31"              ,        14,     18,     509,    "RAZ",  1,      1,      0,      0},
40474         {"FEP"                         ,        0,      5,      510,    "RO",   0,      0,      0ull,   0ull},
40475         {"GC"                          ,        5,      1,      510,    "RO",   0,      0,      1ull,   1ull},
40476         {"GE"                          ,        6,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
40477         {"CC"                          ,        7,      1,      510,    "RO",   0,      0,      1ull,   1ull},
40478         {"CE"                          ,        8,      1,      510,    "R/W",  0,      0,      0ull,   0ull},
40479         {"RESERVED_9_31"               ,        9,      23,     510,    "RAZ",  1,      1,      0,      0},
40480         {"DWORD1"                      ,        0,      32,     511,    "RO",   0,      0,      0ull,   0ull},
40481         {"DWORD2"                      ,        0,      32,     512,    "RO",   0,      0,      0ull,   0ull},
40482         {"DWORD3"                      ,        0,      32,     513,    "RO",   0,      0,      0ull,   0ull},
40483         {"DWORD4"                      ,        0,      32,     514,    "RO",   0,      0,      0ull,   0ull},
40484         {"RTLTL"                       ,        0,      16,     515,    "R/W",  0,      0,      4143ull,        4143ull},
40485         {"RTL"                         ,        16,     16,     515,    "R/W",  0,      0,      12429ull,       12429ull},
40486         {"OMR"                         ,        0,      32,     516,    "R/W",  0,      1,      4294967295ull,  0},
40487         {"LINK_NUM"                    ,        0,      8,      517,    "RO",   0,      0,      0ull,   0ull},
40488         {"RESERVED_8_14"               ,        8,      7,      517,    "RAZ",  1,      1,      0,      0},
40489         {"FORCE_LINK"                  ,        15,     1,      517,    "R/W",  0,      0,      0ull,   0ull},
40490         {"LINK_STATE"                  ,        16,     6,      517,    "R/W",  0,      0,      0ull,   0ull},
40491         {"RESERVED_22_23"              ,        22,     2,      517,    "RAZ",  1,      1,      0,      0},
40492         {"LPEC"                        ,        24,     8,      517,    "R/W",  0,      0,      7ull,   7ull},
40493         {"ACK_FREQ"                    ,        0,      8,      518,    "R/W",  0,      0,      0ull,   0ull},
40494         {"N_FTS"                       ,        8,      8,      518,    "R/W",  0,      0,      128ull, 128ull},
40495         {"N_FTS_CC"                    ,        16,     8,      518,    "R/W",  0,      0,      128ull, 128ull},
40496         {"L0EL"                        ,        24,     3,      518,    "R/W",  0,      0,      3ull,   3ull},
40497         {"L1EL"                        ,        27,     3,      518,    "R/W",  0,      0,      3ull,   3ull},
40498         {"RESERVED_30_31"              ,        30,     2,      518,    "RAZ",  1,      1,      0,      0},
40499         {"OMR"                         ,        0,      1,      519,    "R/W",  0,      0,      0ull,   0ull},
40500         {"SD"                          ,        1,      1,      519,    "R/W",  0,      0,      0ull,   0ull},
40501         {"LE"                          ,        2,      1,      519,    "R/W",  0,      0,      0ull,   0ull},
40502         {"RA"                          ,        3,      1,      519,    "R/W",  0,      0,      0ull,   0ull},
40503         {"RESERVED_4_4"                ,        4,      1,      519,    "RAZ",  1,      1,      0,      0},
40504         {"DLLLE"                       ,        5,      1,      519,    "R/W",  0,      0,      1ull,   1ull},
40505         {"RESERVED_6_6"                ,        6,      1,      519,    "RAZ",  1,      1,      0,      0},
40506         {"FLM"                         ,        7,      1,      519,    "R/W",  0,      0,      0ull,   0ull},
40507         {"RESERVED_8_15"               ,        8,      8,      519,    "RO",   0,      0,      1ull,   1ull},
40508         {"LME"                         ,        16,     6,      519,    "R/W",  0,      0,      15ull,  15ull},
40509         {"RESERVED_22_24"              ,        22,     3,      519,    "RAZ",  1,      1,      0,      0},
40510         {"ECCRC"                       ,        25,     1,      519,    "R/W",  0,      0,      0ull,   0ull},
40511         {"RESERVED_26_31"              ,        26,     6,      519,    "RAZ",  1,      1,      0,      0},
40512         {"ILST"                        ,        0,      24,     520,    "R/W",  0,      0,      0ull,   0ull},
40513         {"FCD"                         ,        24,     1,      520,    "R/W",  0,      0,      0ull,   0ull},
40514         {"ACK_NAK"                     ,        25,     1,      520,    "R/W",  0,      0,      0ull,   0ull},
40515         {"RESERVED_26_30"              ,        26,     5,      520,    "RAZ",  1,      1,      0,      0},
40516         {"DLLD"                        ,        31,     1,      520,    "R/W",  0,      0,      0ull,   0ull},
40517         {"NTSS"                        ,        0,      4,      521,    "R/W",  0,      0,      10ull,  10ull},
40518         {"RESERVED_4_7"                ,        4,      4,      521,    "RO",   1,      1,      0,      0},
40519         {"NSKPS"                       ,        8,      3,      521,    "R/W",  0,      0,      3ull,   3ull},
40520         {"RESERVED_11_13"              ,        11,     3,      521,    "RAZ",  1,      1,      0,      0},
40521         {"TMRT"                        ,        14,     5,      521,    "R/W",  0,      0,      8ull,   8ull},
40522         {"TMANLT"                      ,        19,     5,      521,    "R/W",  0,      0,      0ull,   0ull},
40523         {"TMFCWT"                      ,        24,     5,      521,    "R/W",  0,      0,      0ull,   0ull},
40524         {"RESERVED_29_31"              ,        29,     3,      521,    "RO",   1,      1,      0,      0},
40525         {"SKPIV"                       ,        0,      11,     522,    "R/W",  0,      0,      1280ull,        1280ull},
40526         {"RESERVED_11_14"              ,        11,     4,      522,    "RAZ",  1,      1,      0,      0},
40527         {"DFCWT"                       ,        15,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40528         {"M_FUN"                       ,        16,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40529         {"M_POIS_FILT"                 ,        17,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40530         {"M_BAR_MATCH"                 ,        18,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40531         {"M_CFG1_FILT"                 ,        19,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40532         {"M_LK_FILT"                   ,        20,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40533         {"M_CPL_TAG_ERR"               ,        21,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40534         {"M_CPL_RID_ERR"               ,        22,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40535         {"M_CPL_FUN_ERR"               ,        23,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40536         {"M_CPL_TC_ERR"                ,        24,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40537         {"M_CPL_ATTR_ERR"              ,        25,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40538         {"M_CPL_LEN_ERR"               ,        26,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40539         {"M_ECRC_FILT"                 ,        27,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40540         {"M_CPL_ECRC_FILT"             ,        28,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40541         {"MSG_CTRL"                    ,        29,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40542         {"M_IO_FILT"                   ,        30,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40543         {"M_CFG0_FILT"                 ,        31,     1,      522,    "R/W",  0,      0,      0ull,   0ull},
40544         {"M_VEND0_DRP"                 ,        0,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
40545         {"M_VEND1_DRP"                 ,        1,      1,      523,    "R/W",  0,      0,      0ull,   0ull},
40546         {"RESERVED_2_31"               ,        2,      30,     523,    "RAZ",  1,      1,      0,      0},
40547         {"DBG_INFO_L32"                ,        0,      32,     524,    "RO",   0,      0,      0ull,   0ull},
40548         {"DBG_INFO_U32"                ,        0,      32,     525,    "RO",   0,      0,      0ull,   0ull},
40549         {"TPDFCC"                      ,        0,      12,     526,    "RO",   0,      0,      0ull,   0ull},
40550         {"TPHFCC"                      ,        12,     8,      526,    "RO",   0,      0,      0ull,   0ull},
40551         {"RESERVED_20_31"              ,        20,     12,     526,    "RAZ",  1,      1,      0,      0},
40552         {"TCDFCC"                      ,        0,      12,     527,    "RO",   0,      0,      0ull,   0ull},
40553         {"TCHFCC"                      ,        12,     8,      527,    "RO",   0,      0,      0ull,   0ull},
40554         {"RESERVED_20_31"              ,        20,     12,     527,    "RAZ",  1,      1,      0,      0},
40555         {"TCDFCC"                      ,        0,      12,     528,    "RO",   0,      0,      0ull,   0ull},
40556         {"TCHFCC"                      ,        12,     8,      528,    "RO",   0,      0,      0ull,   0ull},
40557         {"RESERVED_20_31"              ,        20,     12,     528,    "RAZ",  1,      1,      0,      0},
40558         {"RTLPFCCNR"                   ,        0,      1,      529,    "RO",   0,      0,      0ull,   0ull},
40559         {"TRBNE"                       ,        1,      1,      529,    "RO",   0,      0,      0ull,   0ull},
40560         {"RQNE"                        ,        2,      1,      529,    "RO",   0,      0,      0ull,   0ull},
40561         {"RESERVED_3_31"               ,        3,      29,     529,    "RAZ",  1,      1,      0,      0},
40562         {"WRR_VC0"                     ,        0,      8,      530,    "RO",   0,      0,      15ull,  15ull},
40563         {"WRR_VC1"                     ,        8,      8,      530,    "RO",   0,      0,      0ull,   0ull},
40564         {"WRR_VC2"                     ,        16,     8,      530,    "RO",   0,      0,      0ull,   0ull},
40565         {"WRR_VC3"                     ,        24,     8,      530,    "RO",   0,      0,      0ull,   0ull},
40566         {"WRR_VC4"                     ,        0,      8,      531,    "RO",   0,      0,      0ull,   0ull},
40567         {"WRR_VC5"                     ,        8,      8,      531,    "RO",   0,      0,      0ull,   0ull},
40568         {"WRR_VC6"                     ,        16,     8,      531,    "RO",   0,      0,      0ull,   0ull},
40569         {"WRR_VC7"                     ,        24,     8,      531,    "RO",   0,      0,      0ull,   0ull},
40570         {"DATA_CREDITS"                ,        0,      12,     532,    "RO/WRSL",      0,      0,      72ull,  72ull},
40571         {"HEADER_CREDITS"              ,        12,     8,      532,    "RO/WRSL",      0,      0,      32ull,  32ull},
40572         {"RESERVED_20_20"              ,        20,     1,      532,    "RAZ",  1,      1,      0,      0},
40573         {"QUEUE_MODE"                  ,        21,     3,      532,    "RO/WRSL",      0,      0,      2ull,   2ull},
40574         {"RESERVED_24_29"              ,        24,     6,      532,    "RAZ",  1,      1,      0,      0},
40575         {"TYPE_ORDERING"               ,        30,     1,      532,    "RO/WRSL",      0,      0,      1ull,   1ull},
40576         {"RX_QUEUE_ORDER"              ,        31,     1,      532,    "RO/WRSL",      0,      0,      0ull,   0ull},
40577         {"DATA_CREDITS"                ,        0,      12,     533,    "RO/WRSL",      0,      0,      4ull,   4ull},
40578         {"HEADER_CREDITS"              ,        12,     8,      533,    "RO/WRSL",      0,      0,      8ull,   8ull},
40579         {"RESERVED_20_20"              ,        20,     1,      533,    "RAZ",  1,      1,      0,      0},
40580         {"QUEUE_MODE"                  ,        21,     3,      533,    "RO/WRSL",      0,      0,      2ull,   2ull},
40581         {"RESERVED_24_31"              ,        24,     8,      533,    "RAZ",  1,      1,      0,      0},
40582         {"DATA_CREDITS"                ,        0,      12,     534,    "RO/WRSL",      0,      0,      0ull,   0ull},
40583         {"HEADER_CREDITS"              ,        12,     8,      534,    "RO/WRSL",      0,      0,      0ull,   0ull},
40584         {"RESERVED_20_20"              ,        20,     1,      534,    "RAZ",  1,      1,      0,      0},
40585         {"QUEUE_MODE"                  ,        21,     3,      534,    "RO/WRSL",      0,      0,      2ull,   2ull},
40586         {"RESERVED_24_31"              ,        24,     8,      534,    "RAZ",  1,      1,      0,      0},
40587         {"DATA_DEPTH"                  ,        0,      14,     535,    "RO/WRSL",      0,      0,      216ull, 216ull},
40588         {"RESERVED_14_15"              ,        14,     2,      535,    "RAZ",  1,      1,      0,      0},
40589         {"HEADER_DEPTH"                ,        16,     10,     535,    "RO/WRSL",      0,      0,      38ull,  38ull},
40590         {"RESERVED_26_31"              ,        26,     6,      535,    "RAZ",  1,      1,      0,      0},
40591         {"DATA_DEPTH"                  ,        0,      14,     536,    "RO/WRSL",      0,      0,      56ull,  56ull},
40592         {"RESERVED_14_15"              ,        14,     2,      536,    "RAZ",  1,      1,      0,      0},
40593         {"HEADER_DEPTH"                ,        16,     10,     536,    "RO/WRSL",      0,      0,      14ull,  14ull},
40594         {"RESERVED_26_31"              ,        26,     6,      536,    "RAZ",  1,      1,      0,      0},
40595         {"DATA_DEPTH"                  ,        0,      14,     537,    "RO/WRSL",      0,      0,      360ull, 360ull},
40596         {"RESERVED_14_15"              ,        14,     2,      537,    "RAZ",  1,      1,      0,      0},
40597         {"HEADER_DEPTH"                ,        16,     10,     537,    "RO/WRSL",      0,      0,      70ull,  70ull},
40598         {"RESERVED_26_31"              ,        26,     6,      537,    "RAZ",  1,      1,      0,      0},
40599         {"PHY_STAT"                    ,        0,      32,     538,    "RO",   0,      0,      0ull,   0ull},
40600         {"PHY_CTRL"                    ,        0,      32,     539,    "R/W",  0,      0,      0ull,   0ull},
40601         {"VENDID"                      ,        0,      16,     540,    "R/W",  0,      0,      6013ull,        6013ull},
40602         {"DEVID"                       ,        16,     16,     540,    "R/W",  0,      0,      80ull,  80ull},
40603         {"ISAE"                        ,        0,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
40604         {"MSAE"                        ,        1,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
40605         {"ME"                          ,        2,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
40606         {"SCSE"                        ,        3,      1,      541,    "RO",   0,      0,      0ull,   0ull},
40607         {"MWICE"                       ,        4,      1,      541,    "RO",   0,      0,      0ull,   0ull},
40608         {"VPS"                         ,        5,      1,      541,    "RO",   0,      0,      0ull,   0ull},
40609         {"PER"                         ,        6,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
40610         {"IDS_WCC"                     ,        7,      1,      541,    "RO",   0,      0,      0ull,   0ull},
40611         {"SEE"                         ,        8,      1,      541,    "R/W",  0,      0,      0ull,   0ull},
40612         {"FBBE"                        ,        9,      1,      541,    "RO",   0,      0,      0ull,   0ull},
40613         {"I_DIS"                       ,        10,     1,      541,    "R/W",  0,      0,      0ull,   0ull},
40614         {"RESERVED_11_18"              ,        11,     8,      541,    "RAZ",  1,      1,      0,      0},
40615         {"I_STAT"                      ,        19,     1,      541,    "RO",   0,      0,      0ull,   0ull},
40616         {"CL"                          ,        20,     1,      541,    "RO",   0,      0,      1ull,   1ull},
40617         {"M66"                         ,        21,     1,      541,    "RO",   0,      0,      0ull,   0ull},
40618         {"RESERVED_22_22"              ,        22,     1,      541,    "RO",   1,      1,      0,      0},
40619         {"FBB"                         ,        23,     1,      541,    "RO",   0,      0,      0ull,   0ull},
40620         {"MDPE"                        ,        24,     1,      541,    "R/W1C",        0,      0,      0ull,   0ull},
40621         {"DEVT"                        ,        25,     2,      541,    "RO",   0,      0,      0ull,   0ull},
40622         {"STA"                         ,        27,     1,      541,    "R/W1C",        0,      0,      0ull,   0ull},
40623         {"RTA"                         ,        28,     1,      541,    "R/W1C",        0,      0,      0ull,   0ull},
40624         {"RMA"                         ,        29,     1,      541,    "R/W1C",        0,      0,      0ull,   0ull},
40625         {"SSE"                         ,        30,     1,      541,    "R/W1C",        0,      0,      0ull,   0ull},
40626         {"DPE"                         ,        31,     1,      541,    "R/W1C",        0,      0,      0ull,   0ull},
40627         {"RID"                         ,        0,      8,      542,    "R/W",  0,      0,      0ull,   0ull},
40628         {"PI"                          ,        8,      8,      542,    "R/W",  0,      0,      0ull,   0ull},
40629         {"SC"                          ,        16,     8,      542,    "R/W",  0,      0,      48ull,  48ull},
40630         {"BCC"                         ,        24,     8,      542,    "R/W",  0,      0,      11ull,  11ull},
40631         {"CLS"                         ,        0,      8,      543,    "R/W",  0,      0,      0ull,   0ull},
40632         {"LT"                          ,        8,      8,      543,    "RO",   0,      0,      0ull,   0ull},
40633         {"CHF"                         ,        16,     7,      543,    "RO",   0,      0,      1ull,   1ull},
40634         {"MFD"                         ,        23,     1,      543,    "R/W",  0,      0,      0ull,   0ull},
40635         {"BIST"                        ,        24,     8,      543,    "RO",   0,      0,      0ull,   0ull},
40636         {"RESERVED_0_31"               ,        0,      32,     544,    "RO",   1,      1,      0,      0},
40637         {"RESERVED_0_31"               ,        0,      32,     545,    "RO",   1,      1,      0,      0},
40638         {"PBNUM"                       ,        0,      8,      546,    "R/W",  0,      0,      0ull,   0ull},
40639         {"SBNUM"                       ,        8,      8,      546,    "R/W",  0,      0,      0ull,   0ull},
40640         {"SUBBNUM"                     ,        16,     8,      546,    "R/W",  0,      0,      0ull,   0ull},
40641         {"SLT"                         ,        24,     8,      546,    "RO",   0,      0,      0ull,   0ull},
40642         {"IO32A"                       ,        0,      1,      547,    "R/W",  0,      0,      1ull,   1ull},
40643         {"RESERVED_1_3"                ,        1,      3,      547,    "RAZ",  0,      0,      0ull,   0ull},
40644         {"LIO_BASE"                    ,        4,      4,      547,    "R/W",  0,      0,      0ull,   0ull},
40645         {"IO32B"                       ,        8,      1,      547,    "RO",   0,      0,      1ull,   1ull},
40646         {"RESERVED_9_11"               ,        9,      3,      547,    "RAZ",  0,      0,      0ull,   0ull},
40647         {"LIO_LIMI"                    ,        12,     4,      547,    "R/W",  0,      0,      0ull,   0ull},
40648         {"RESERVED_16_20"              ,        16,     5,      547,    "RAZ",  1,      1,      0,      0},
40649         {"M66"                         ,        21,     1,      547,    "RO",   0,      0,      0ull,   0ull},
40650         {"RESERVED_22_22"              ,        22,     1,      547,    "RO",   1,      1,      0,      0},
40651         {"FBB"                         ,        23,     1,      547,    "RO",   0,      0,      0ull,   0ull},
40652         {"MDPE"                        ,        24,     1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
40653         {"DEVT"                        ,        25,     2,      547,    "RO",   0,      0,      0ull,   0ull},
40654         {"STA"                         ,        27,     1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
40655         {"RTA"                         ,        28,     1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
40656         {"RMA"                         ,        29,     1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
40657         {"SSE"                         ,        30,     1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
40658         {"DPE"                         ,        31,     1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
40659         {"RESERVED_0_3"                ,        0,      4,      548,    "RO",   1,      1,      0,      0},
40660         {"MB_ADDR"                     ,        4,      12,     548,    "R/W",  0,      0,      0ull,   0ull},
40661         {"RESERVED_16_19"              ,        16,     4,      548,    "RO",   1,      1,      0,      0},
40662         {"ML_ADDR"                     ,        20,     12,     548,    "R/W",  0,      0,      0ull,   0ull},
40663         {"MEM64A"                      ,        0,      1,      549,    "R/W",  0,      0,      1ull,   1ull},
40664         {"RESERVED_1_3"                ,        1,      3,      549,    "RO",   1,      1,      0,      0},
40665         {"LMEM_BASE"                   ,        4,      12,     549,    "R/W",  0,      0,      0ull,   0ull},
40666         {"MEM64B"                      ,        16,     1,      549,    "RO",   0,      0,      1ull,   1ull},
40667         {"RESERVED_17_19"              ,        17,     3,      549,    "RO",   1,      1,      0,      0},
40668         {"LMEM_LIMIT"                  ,        20,     12,     549,    "R/W",  0,      0,      0ull,   0ull},
40669         {"UMEM_BASE"                   ,        0,      32,     550,    "R/W",  0,      0,      0ull,   0ull},
40670         {"UMEM_LIMIT"                  ,        0,      32,     551,    "R/W",  0,      0,      0ull,   0ull},
40671         {"UIO_BASE"                    ,        0,      16,     552,    "R/W",  0,      0,      0ull,   0ull},
40672         {"UIO_LIMIT"                   ,        16,     16,     552,    "R/W",  0,      0,      0ull,   0ull},
40673         {"CP"                          ,        0,      8,      553,    "R/W",  0,      0,      64ull,  64ull},
40674         {"RESERVED_8_31"               ,        8,      24,     553,    "RAZ",  1,      1,      0,      0},
40675         {"RESERVED_0_31"               ,        0,      32,     554,    "RAZ",  1,      1,      0,      0},
40676         {"IL"                          ,        0,      8,      555,    "R/W",  0,      0,      255ull, 255ull},
40677         {"INTA"                        ,        8,      8,      555,    "R/W",  0,      0,      1ull,   1ull},
40678         {"PERE"                        ,        16,     1,      555,    "R/W",  0,      0,      0ull,   0ull},
40679         {"SEE"                         ,        17,     1,      555,    "R/W",  0,      0,      0ull,   0ull},
40680         {"ISAE"                        ,        18,     1,      555,    "R/W",  0,      0,      0ull,   0ull},
40681         {"VGAE"                        ,        19,     1,      555,    "R/W",  0,      0,      0ull,   0ull},
40682         {"VGA16D"                      ,        20,     1,      555,    "R/W",  0,      0,      0ull,   0ull},
40683         {"MAM"                         ,        21,     1,      555,    "RO",   0,      0,      0ull,   0ull},
40684         {"SBRST"                       ,        22,     1,      555,    "R/W",  0,      0,      0ull,   0ull},
40685         {"FBBE"                        ,        23,     1,      555,    "RO",   0,      0,      0ull,   0ull},
40686         {"PDT"                         ,        24,     1,      555,    "RO",   0,      0,      0ull,   0ull},
40687         {"SDT"                         ,        25,     1,      555,    "RO",   0,      0,      0ull,   0ull},
40688         {"DTS"                         ,        26,     1,      555,    "RO",   0,      0,      0ull,   0ull},
40689         {"DTSEES"                      ,        27,     1,      555,    "RO",   0,      0,      0ull,   0ull},
40690         {"RESERVED_28_31"              ,        28,     4,      555,    "RO",   1,      1,      0,      0},
40691         {"PMCID"                       ,        0,      8,      556,    "RO",   0,      0,      1ull,   1ull},
40692         {"NCP"                         ,        8,      8,      556,    "R/W",  0,      0,      80ull,  80ull},
40693         {"PMSV"                        ,        16,     3,      556,    "R/W",  0,      0,      3ull,   3ull},
40694         {"PME_CLOCK"                   ,        19,     1,      556,    "RO",   0,      0,      0ull,   0ull},
40695         {"RESERVED_20_20"              ,        20,     1,      556,    "RAZ",  1,      1,      0,      0},
40696         {"DSI"                         ,        21,     1,      556,    "R/W",  0,      0,      0ull,   0ull},
40697         {"AUXC"                        ,        22,     3,      556,    "R/W",  0,      0,      0ull,   0ull},
40698         {"D1S"                         ,        25,     1,      556,    "R/W",  0,      0,      0ull,   0ull},
40699         {"D2S"                         ,        26,     1,      556,    "R/W",  0,      0,      0ull,   0ull},
40700         {"PMES"                        ,        27,     5,      556,    "R/W",  0,      0,      0ull,   0ull},
40701         {"PS"                          ,        0,      2,      557,    "R/W",  0,      0,      0ull,   0ull},
40702         {"RESERVED_2_2"                ,        2,      1,      557,    "RAZ",  1,      1,      0,      0},
40703         {"NSR"                         ,        3,      1,      557,    "R/W",  0,      0,      0ull,   0ull},
40704         {"RESERVED_4_7"                ,        4,      4,      557,    "RAZ",  1,      1,      0,      0},
40705         {"PMEENS"                      ,        8,      1,      557,    "R/W",  0,      0,      0ull,   0ull},
40706         {"PMDS"                        ,        9,      4,      557,    "RO",   0,      0,      0ull,   0ull},
40707         {"PMEDSIA"                     ,        13,     2,      557,    "RO",   0,      0,      0ull,   0ull},
40708         {"PMESS"                       ,        15,     1,      557,    "R/W1C",        0,      0,      0ull,   0ull},
40709         {"RESERVED_16_21"              ,        16,     6,      557,    "RAZ",  1,      1,      0,      0},
40710         {"BD3H"                        ,        22,     1,      557,    "RO",   0,      0,      0ull,   0ull},
40711         {"BPCCEE"                      ,        23,     1,      557,    "RO",   0,      0,      0ull,   0ull},
40712         {"PMDIA"                       ,        24,     8,      557,    "RO",   0,      0,      0ull,   0ull},
40713         {"MSICID"                      ,        0,      8,      558,    "RO",   0,      0,      5ull,   5ull},
40714         {"NCP"                         ,        8,      8,      558,    "R/W",  0,      0,      112ull, 112ull},
40715         {"MSIEN"                       ,        16,     1,      558,    "R/W",  0,      0,      0ull,   0ull},
40716         {"MMC"                         ,        17,     3,      558,    "R/W",  0,      0,      0ull,   0ull},
40717         {"MME"                         ,        20,     3,      558,    "R/W",  0,      0,      0ull,   0ull},
40718         {"M64"                         ,        23,     1,      558,    "R/W",  0,      0,      1ull,   1ull},
40719         {"RESERVED_24_31"              ,        24,     8,      558,    "RAZ",  1,      1,      0,      0},
40720         {"RESERVED_0_1"                ,        0,      2,      559,    "RAZ",  1,      1,      0,      0},
40721         {"LMSI"                        ,        2,      30,     559,    "R/W",  0,      0,      0ull,   0ull},
40722         {"UMSI"                        ,        0,      32,     560,    "R/W",  0,      0,      0ull,   0ull},
40723         {"MSIMD"                       ,        0,      16,     561,    "R/W",  0,      0,      0ull,   0ull},
40724         {"RESERVED_16_31"              ,        16,     16,     561,    "RAZ",  1,      1,      0,      0},
40725         {"PCIEID"                      ,        0,      8,      562,    "RO",   0,      0,      16ull,  16ull},
40726         {"NCP"                         ,        8,      8,      562,    "R/W",  0,      0,      0ull,   0ull},
40727         {"PCIECV"                      ,        16,     4,      562,    "RO",   0,      0,      2ull,   2ull},
40728         {"DPT"                         ,        20,     4,      562,    "RO",   0,      0,      4ull,   4ull},
40729         {"SI"                          ,        24,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
40730         {"IMN"                         ,        25,     5,      562,    "R/W",  0,      0,      0ull,   0ull},
40731         {"RESERVED_30_31"              ,        30,     2,      562,    "RAZ",  1,      1,      0,      0},
40732         {"MPSS"                        ,        0,      3,      563,    "R/W",  0,      0,      1ull,   1ull},
40733         {"PFS"                         ,        3,      2,      563,    "R/W",  0,      0,      0ull,   0ull},
40734         {"ETFS"                        ,        5,      1,      563,    "R/W",  0,      0,      0ull,   0ull},
40735         {"EL0AL"                       ,        6,      3,      563,    "R/W",  0,      0,      0ull,   0ull},
40736         {"EL1AL"                       ,        9,      3,      563,    "R/W",  0,      0,      0ull,   0ull},
40737         {"RESERVED_12_14"              ,        12,     3,      563,    "RAZ",  1,      1,      0,      0},
40738         {"RBER"                        ,        15,     1,      563,    "R/W",  0,      0,      1ull,   1ull},
40739         {"RESERVED_16_17"              ,        16,     2,      563,    "RAZ",  1,      1,      0,      0},
40740         {"CSPLV"                       ,        18,     8,      563,    "RO",   0,      0,      0ull,   0ull},
40741         {"CSPLS"                       ,        26,     2,      563,    "RO",   0,      0,      0ull,   0ull},
40742         {"RESERVED_28_31"              ,        28,     4,      563,    "RAZ",  1,      1,      0,      0},
40743         {"CE_EN"                       ,        0,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
40744         {"NFE_EN"                      ,        1,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
40745         {"FE_EN"                       ,        2,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
40746         {"UR_EN"                       ,        3,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
40747         {"RO_EN"                       ,        4,      1,      564,    "R/W",  0,      0,      1ull,   1ull},
40748         {"MPS"                         ,        5,      3,      564,    "R/W",  0,      0,      0ull,   0ull},
40749         {"ETF_EN"                      ,        8,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
40750         {"PF_EN"                       ,        9,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
40751         {"AP_EN"                       ,        10,     1,      564,    "R/W",  0,      0,      0ull,   0ull},
40752         {"NS_EN"                       ,        11,     1,      564,    "R/W",  0,      0,      1ull,   1ull},
40753         {"MRRS"                        ,        12,     3,      564,    "R/W",  0,      0,      2ull,   2ull},
40754         {"RESERVED_15_15"              ,        15,     1,      564,    "RAZ",  1,      1,      0,      0},
40755         {"CE_D"                        ,        16,     1,      564,    "R/W1C",        0,      0,      0ull,   0ull},
40756         {"NFE_D"                       ,        17,     1,      564,    "R/W1C",        0,      0,      0ull,   0ull},
40757         {"FE_D"                        ,        18,     1,      564,    "R/W1C",        0,      0,      0ull,   0ull},
40758         {"UR_D"                        ,        19,     1,      564,    "R/W1C",        0,      0,      0ull,   0ull},
40759         {"AP_D"                        ,        20,     1,      564,    "RO",   0,      0,      0ull,   0ull},
40760         {"TP"                          ,        21,     1,      564,    "RO",   0,      0,      0ull,   0ull},
40761         {"RESERVED_22_31"              ,        22,     10,     564,    "RAZ",  1,      1,      0,      0},
40762         {"MLS"                         ,        0,      4,      565,    "R/W",  0,      0,      1ull,   1ull},
40763         {"MLW"                         ,        4,      6,      565,    "R/W",  0,      0,      8ull,   8ull},
40764         {"ASLPMS"                      ,        10,     2,      565,    "R/W",  0,      0,      3ull,   3ull},
40765         {"L0EL"                        ,        12,     3,      565,    "R/W",  0,      0,      6ull,   6ull},
40766         {"L1EL"                        ,        15,     3,      565,    "R/W",  0,      0,      6ull,   6ull},
40767         {"CPM"                         ,        18,     1,      565,    "R/W",  0,      0,      0ull,   0ull},
40768         {"SDERC"                       ,        19,     1,      565,    "RO",   0,      0,      0ull,   0ull},
40769         {"DLLARC"                      ,        20,     1,      565,    "RO",   0,      0,      1ull,   1ull},
40770         {"LBNC"                        ,        21,     1,      565,    "RO",   0,      0,      1ull,   1ull},
40771         {"RESERVED_22_23"              ,        22,     2,      565,    "RAZ",  1,      1,      0,      0},
40772         {"PNUM"                        ,        24,     8,      565,    "R/W",  0,      0,      0ull,   0ull},
40773         {"ASLPC"                       ,        0,      2,      566,    "R/W",  0,      0,      0ull,   0ull},
40774         {"RESERVED_2_2"                ,        2,      1,      566,    "RAZ",  1,      1,      0,      0},
40775         {"RCB"                         ,        3,      1,      566,    "R/W",  0,      0,      1ull,   1ull},
40776         {"LD"                          ,        4,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
40777         {"RL"                          ,        5,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
40778         {"CCC"                         ,        6,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
40779         {"ES"                          ,        7,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
40780         {"ECPM"                        ,        8,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
40781         {"HAWD"                        ,        9,      1,      566,    "R/W",  0,      0,      0ull,   0ull},
40782         {"LBM_INT_ENB"                 ,        10,     1,      566,    "R/W",  0,      0,      0ull,   0ull},
40783         {"LAB_INT_ENB"                 ,        11,     1,      566,    "R/W",  0,      0,      0ull,   0ull},
40784         {"RESERVED_12_15"              ,        12,     4,      566,    "RAZ",  1,      1,      0,      0},
40785         {"LS"                          ,        16,     4,      566,    "RO",   0,      0,      1ull,   1ull},
40786         {"NLW"                         ,        20,     6,      566,    "RO",   0,      0,      0ull,   0ull},
40787         {"RESERVED_26_26"              ,        26,     1,      566,    "RAZ",  1,      1,      0,      0},
40788         {"LT"                          ,        27,     1,      566,    "RO",   0,      0,      0ull,   0ull},
40789         {"SCC"                         ,        28,     1,      566,    "R/W",  0,      0,      1ull,   0ull},
40790         {"DLLA"                        ,        29,     1,      566,    "RO",   0,      0,      0ull,   1ull},
40791         {"LBM"                         ,        30,     1,      566,    "R/W1C",        0,      0,      0ull,   0ull},
40792         {"LAB"                         ,        31,     1,      566,    "R/W1C",        0,      0,      0ull,   0ull},
40793         {"ABP"                         ,        0,      1,      567,    "R/W",  0,      0,      0ull,   0ull},
40794         {"PCP"                         ,        1,      1,      567,    "R/W",  0,      0,      0ull,   0ull},
40795         {"MRLSP"                       ,        2,      1,      567,    "R/W",  0,      0,      0ull,   0ull},
40796         {"AIP"                         ,        3,      1,      567,    "R/W",  0,      0,      0ull,   0ull},
40797         {"PIP"                         ,        4,      1,      567,    "R/W",  0,      0,      0ull,   0ull},
40798         {"HP_S"                        ,        5,      1,      567,    "R/W",  0,      0,      0ull,   0ull},
40799         {"HP_C"                        ,        6,      1,      567,    "R/W",  0,      0,      0ull,   0ull},
40800         {"SP_LV"                       ,        7,      8,      567,    "R/W",  0,      0,      0ull,   0ull},
40801         {"SP_LS"                       ,        15,     2,      567,    "R/W",  0,      0,      0ull,   0ull},
40802         {"EMIP"                        ,        17,     1,      567,    "R/W",  0,      0,      0ull,   0ull},
40803         {"NCCS"                        ,        18,     1,      567,    "R/W",  0,      0,      0ull,   0ull},
40804         {"PS_NUM"                      ,        19,     13,     567,    "R/W",  0,      0,      0ull,   0ull},
40805         {"ABP_EN"                      ,        0,      1,      568,    "R/W",  0,      0,      0ull,   0ull},
40806         {"PF_EN"                       ,        1,      1,      568,    "R/W",  0,      0,      0ull,   0ull},
40807         {"MRLS_EN"                     ,        2,      1,      568,    "R/W",  0,      0,      0ull,   0ull},
40808         {"PD_EN"                       ,        3,      1,      568,    "R/W",  0,      0,      0ull,   0ull},
40809         {"CCINT_EN"                    ,        4,      1,      568,    "R/W",  0,      0,      0ull,   0ull},
40810         {"HPINT_EN"                    ,        5,      1,      568,    "R/W",  0,      0,      0ull,   0ull},
40811         {"AIC"                         ,        6,      2,      568,    "R/W",  0,      0,      3ull,   3ull},
40812         {"PIC"                         ,        8,      2,      568,    "R/W",  0,      0,      3ull,   3ull},
40813         {"PCC"                         ,        10,     1,      568,    "R/W",  0,      0,      0ull,   0ull},
40814         {"EMIC"                        ,        11,     1,      568,    "R/W",  0,      0,      0ull,   0ull},
40815         {"DLLS_EN"                     ,        12,     1,      568,    "R/W",  0,      0,      0ull,   0ull},
40816         {"RESERVED_13_15"              ,        13,     3,      568,    "RAZ",  1,      1,      0,      0},
40817         {"ABP_D"                       ,        16,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
40818         {"PF_D"                        ,        17,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
40819         {"MRLS_C"                      ,        18,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
40820         {"PD_C"                        ,        19,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
40821         {"CCINT_D"                     ,        20,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
40822         {"MRLSS"                       ,        21,     1,      568,    "RO",   0,      0,      0ull,   0ull},
40823         {"PDS"                         ,        22,     1,      568,    "RO",   0,      0,      1ull,   1ull},
40824         {"EMIS"                        ,        23,     1,      568,    "RO",   0,      0,      0ull,   0ull},
40825         {"DLLS_C"                      ,        24,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
40826         {"RESERVED_25_31"              ,        25,     7,      568,    "RAZ",  1,      1,      0,      0},
40827         {"SECEE"                       ,        0,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
40828         {"SENFEE"                      ,        1,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
40829         {"SEFEE"                       ,        2,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
40830         {"PMEIE"                       ,        3,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
40831         {"CRSSVE"                      ,        4,      1,      569,    "RO",   0,      0,      0ull,   0ull},
40832         {"RESERVED_5_15"               ,        5,      11,     569,    "RAZ",  1,      1,      0,      0},
40833         {"CRSSV"                       ,        16,     1,      569,    "RO",   0,      0,      0ull,   0ull},
40834         {"RESERVED_17_31"              ,        17,     15,     569,    "RAZ",  1,      1,      0,      0},
40835         {"PME_RID"                     ,        0,      16,     570,    "RO",   0,      0,      0ull,   0ull},
40836         {"PME_STAT"                    ,        16,     1,      570,    "R/W1C",        0,      0,      0ull,   0ull},
40837         {"PME_PEND"                    ,        17,     1,      570,    "RO",   0,      0,      0ull,   0ull},
40838         {"RESERVED_18_31"              ,        18,     14,     570,    "RAZ",  0,      0,      0ull,   0ull},
40839         {"CTRS"                        ,        0,      4,      571,    "RO",   0,      0,      0ull,   0ull},
40840         {"CTDS"                        ,        4,      1,      571,    "RO",   0,      0,      1ull,   1ull},
40841         {"RESERVED_5_31"               ,        5,      27,     571,    "RAZ",  1,      1,      0,      0},
40842         {"CTV"                         ,        0,      4,      572,    "RO",   0,      0,      0ull,   0ull},
40843         {"CTD"                         ,        4,      1,      572,    "R/W",  0,      0,      0ull,   0ull},
40844         {"RESERVED_5_31"               ,        5,      27,     572,    "RAZ",  1,      1,      0,      0},
40845         {"RESERVED_0_31"               ,        0,      32,     573,    "RAZ",  1,      1,      0,      0},
40846         {"RESERVED_0_31"               ,        0,      32,     574,    "RAZ",  1,      1,      0,      0},
40847         {"RESERVED_0_31"               ,        0,      32,     575,    "RAZ",  1,      1,      0,      0},
40848         {"RESERVED_0_31"               ,        0,      32,     576,    "RAZ",  1,      1,      0,      0},
40849         {"PCIEEC"                      ,        0,      16,     577,    "RO",   0,      0,      1ull,   1ull},
40850         {"CV"                          ,        16,     4,      577,    "RO",   0,      0,      1ull,   1ull},
40851         {"NCO"                         ,        20,     12,     577,    "RO",   0,      0,      0ull,   0ull},
40852         {"RESERVED_0_3"                ,        0,      4,      578,    "RAZ",  1,      1,      0,      0},
40853         {"DLPES"                       ,        4,      1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40854         {"SDES"                        ,        5,      1,      578,    "RO",   0,      0,      0ull,   0ull},
40855         {"RESERVED_6_11"               ,        6,      6,      578,    "RAZ",  1,      1,      0,      0},
40856         {"PTLPS"                       ,        12,     1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40857         {"FCPES"                       ,        13,     1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40858         {"CTS"                         ,        14,     1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40859         {"CAS"                         ,        15,     1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40860         {"UCS"                         ,        16,     1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40861         {"ROS"                         ,        17,     1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40862         {"MTLPS"                       ,        18,     1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40863         {"ECRCES"                      ,        19,     1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40864         {"URES"                        ,        20,     1,      578,    "R/W1C",        0,      0,      0ull,   0ull},
40865         {"RESERVED_21_31"              ,        21,     11,     578,    "RAZ",  1,      1,      0,      0},
40866         {"RESERVED_0_3"                ,        0,      4,      579,    "RAZ",  1,      1,      0,      0},
40867         {"DLPEM"                       ,        4,      1,      579,    "R/W",  0,      0,      0ull,   0ull},
40868         {"SDEM"                        ,        5,      1,      579,    "RO",   0,      0,      0ull,   0ull},
40869         {"RESERVED_6_11"               ,        6,      6,      579,    "RAZ",  1,      1,      0,      0},
40870         {"PTLPM"                       ,        12,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
40871         {"FCPEM"                       ,        13,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
40872         {"CTM"                         ,        14,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
40873         {"CAM"                         ,        15,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
40874         {"UCM"                         ,        16,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
40875         {"ROM"                         ,        17,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
40876         {"MTLPM"                       ,        18,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
40877         {"ECRCEM"                      ,        19,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
40878         {"UREM"                        ,        20,     1,      579,    "R/W",  0,      0,      0ull,   0ull},
40879         {"RESERVED_21_31"              ,        21,     11,     579,    "RAZ",  1,      1,      0,      0},
40880         {"RESERVED_0_3"                ,        0,      4,      580,    "RAZ",  1,      1,      0,      0},
40881         {"DLPES"                       ,        4,      1,      580,    "R/W",  0,      0,      1ull,   1ull},
40882         {"SDES"                        ,        5,      1,      580,    "RO",   0,      0,      1ull,   1ull},
40883         {"RESERVED_6_11"               ,        6,      6,      580,    "RAZ",  1,      1,      0,      0},
40884         {"PTLPS"                       ,        12,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
40885         {"FCPES"                       ,        13,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
40886         {"CTS"                         ,        14,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
40887         {"CAS"                         ,        15,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
40888         {"UCS"                         ,        16,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
40889         {"ROS"                         ,        17,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
40890         {"MTLPS"                       ,        18,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
40891         {"ECRCES"                      ,        19,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
40892         {"URES"                        ,        20,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
40893         {"RESERVED_21_31"              ,        21,     11,     580,    "RAZ",  1,      1,      0,      0},
40894         {"RES"                         ,        0,      1,      581,    "R/W1C",        0,      0,      0ull,   0ull},
40895         {"RESERVED_1_5"                ,        1,      5,      581,    "RAZ",  1,      1,      0,      0},
40896         {"BTLPS"                       ,        6,      1,      581,    "R/W1C",        0,      0,      0ull,   0ull},
40897         {"BDLLPS"                      ,        7,      1,      581,    "R/W1C",        0,      0,      0ull,   0ull},
40898         {"RNRS"                        ,        8,      1,      581,    "R/W1C",        0,      0,      0ull,   0ull},
40899         {"RESERVED_9_11"               ,        9,      3,      581,    "RAZ",  1,      1,      0,      0},
40900         {"RTTS"                        ,        12,     1,      581,    "R/W1C",        0,      0,      0ull,   0ull},
40901         {"ANFES"                       ,        13,     1,      581,    "R/W1C",        0,      0,      0ull,   0ull},
40902         {"RESERVED_14_31"              ,        14,     18,     581,    "RAZ",  1,      1,      0,      0},
40903         {"REM"                         ,        0,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
40904         {"RESERVED_1_5"                ,        1,      5,      582,    "RAZ",  1,      1,      0,      0},
40905         {"BTLPM"                       ,        6,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
40906         {"BDLLPM"                      ,        7,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
40907         {"RNRM"                        ,        8,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
40908         {"RESERVED_9_11"               ,        9,      3,      582,    "RAZ",  1,      1,      0,      0},
40909         {"RTTM"                        ,        12,     1,      582,    "R/W",  0,      0,      0ull,   0ull},
40910         {"ANFEM"                       ,        13,     1,      582,    "R/W",  0,      0,      1ull,   1ull},
40911         {"RESERVED_14_31"              ,        14,     18,     582,    "RAZ",  1,      1,      0,      0},
40912         {"FEP"                         ,        0,      5,      583,    "RO",   0,      0,      0ull,   0ull},
40913         {"GC"                          ,        5,      1,      583,    "RO",   0,      0,      1ull,   1ull},
40914         {"GE"                          ,        6,      1,      583,    "R/W",  0,      0,      0ull,   0ull},
40915         {"CC"                          ,        7,      1,      583,    "RO",   0,      0,      1ull,   1ull},
40916         {"CE"                          ,        8,      1,      583,    "R/W",  0,      0,      0ull,   0ull},
40917         {"RESERVED_9_31"               ,        9,      23,     583,    "RAZ",  1,      1,      0,      0},
40918         {"DWORD1"                      ,        0,      32,     584,    "RO",   0,      0,      0ull,   0ull},
40919         {"DWORD2"                      ,        0,      32,     585,    "RO",   0,      0,      0ull,   0ull},
40920         {"DWORD3"                      ,        0,      32,     586,    "RO",   0,      0,      0ull,   0ull},
40921         {"DWORD4"                      ,        0,      32,     587,    "RO",   0,      0,      0ull,   0ull},
40922         {"CERE"                        ,        0,      1,      588,    "R/W",  0,      0,      0ull,   0ull},
40923         {"NFERE"                       ,        1,      1,      588,    "R/W",  0,      0,      0ull,   0ull},
40924         {"FERE"                        ,        2,      1,      588,    "R/W",  0,      0,      0ull,   0ull},
40925         {"RESERVED_3_31"               ,        3,      29,     588,    "RAZ",  1,      1,      0,      0},
40926         {"ECR"                         ,        0,      1,      589,    "R/W1C",        0,      0,      0ull,   0ull},
40927         {"MULTI_ECR"                   ,        1,      1,      589,    "R/W1C",        0,      0,      0ull,   0ull},
40928         {"EFNFR"                       ,        2,      1,      589,    "R/W1C",        0,      0,      0ull,   0ull},
40929         {"MULTI_EFNFR"                 ,        3,      1,      589,    "R/W1C",        0,      0,      0ull,   0ull},
40930         {"FUF"                         ,        4,      1,      589,    "R/W1C",        0,      0,      0ull,   0ull},
40931         {"NFEMR"                       ,        5,      1,      589,    "R/W1C",        0,      0,      0ull,   0ull},
40932         {"FEMR"                        ,        6,      1,      589,    "R/W1C",        0,      0,      0ull,   0ull},
40933         {"RESERVED_7_26"               ,        7,      20,     589,    "RAZ",  1,      1,      0,      0},
40934         {"AEIMN"                       ,        27,     5,      589,    "R/W",  0,      0,      0ull,   0ull},
40935         {"ECSI"                        ,        0,      16,     590,    "RO",   0,      0,      0ull,   0ull},
40936         {"EFNFSI"                      ,        16,     16,     590,    "RO",   0,      0,      0ull,   0ull},
40937         {"RTLTL"                       ,        0,      16,     591,    "R/W",  0,      0,      4143ull,        4143ull},
40938         {"RTL"                         ,        16,     16,     591,    "R/W",  0,      0,      12429ull,       12429ull},
40939         {"OMR"                         ,        0,      32,     592,    "R/W",  0,      1,      4294967295ull,  0},
40940         {"LINK_NUM"                    ,        0,      8,      593,    "R/W",  0,      0,      4ull,   4ull},
40941         {"RESERVED_8_14"               ,        8,      7,      593,    "RAZ",  1,      1,      0,      0},
40942         {"FORCE_LINK"                  ,        15,     1,      593,    "R/W",  0,      0,      0ull,   0ull},
40943         {"LINK_STATE"                  ,        16,     6,      593,    "R/W",  0,      0,      0ull,   0ull},
40944         {"RESERVED_22_23"              ,        22,     2,      593,    "RAZ",  1,      1,      0,      0},
40945         {"LPEC"                        ,        24,     8,      593,    "RO",   0,      0,      7ull,   7ull},
40946         {"ACK_FREQ"                    ,        0,      8,      594,    "R/W",  0,      0,      0ull,   0ull},
40947         {"N_FTS"                       ,        8,      8,      594,    "R/W",  0,      0,      128ull, 128ull},
40948         {"N_FTS_CC"                    ,        16,     8,      594,    "R/W",  0,      0,      128ull, 128ull},
40949         {"L0EL"                        ,        24,     3,      594,    "R/W",  0,      0,      3ull,   3ull},
40950         {"L1EL"                        ,        27,     3,      594,    "R/W",  0,      0,      3ull,   3ull},
40951         {"RESERVED_30_31"              ,        30,     2,      594,    "RAZ",  1,      1,      0,      0},
40952         {"OMR"                         ,        0,      1,      595,    "R/W",  0,      0,      0ull,   0ull},
40953         {"SD"                          ,        1,      1,      595,    "R/W",  0,      0,      0ull,   0ull},
40954         {"LE"                          ,        2,      1,      595,    "R/W",  0,      0,      0ull,   0ull},
40955         {"RA"                          ,        3,      1,      595,    "R/W",  0,      0,      0ull,   0ull},
40956         {"RESERVED_4_4"                ,        4,      1,      595,    "RAZ",  1,      1,      0,      0},
40957         {"DLLLE"                       ,        5,      1,      595,    "R/W",  0,      0,      1ull,   1ull},
40958         {"RESERVED_6_6"                ,        6,      1,      595,    "RAZ",  1,      1,      0,      0},
40959         {"FLM"                         ,        7,      1,      595,    "R/W",  0,      0,      0ull,   0ull},
40960         {"RESERVED_8_15"               ,        8,      8,      595,    "RO",   0,      0,      1ull,   1ull},
40961         {"LME"                         ,        16,     6,      595,    "R/W",  0,      0,      15ull,  15ull},
40962         {"RESERVED_22_24"              ,        22,     3,      595,    "RAZ",  1,      1,      0,      0},
40963         {"ECCRC"                       ,        25,     1,      595,    "R/W",  0,      0,      0ull,   0ull},
40964         {"RESERVED_26_31"              ,        26,     6,      595,    "RAZ",  1,      1,      0,      0},
40965         {"ILST"                        ,        0,      24,     596,    "R/W",  0,      0,      0ull,   0ull},
40966         {"FCD"                         ,        24,     1,      596,    "R/W",  0,      0,      0ull,   0ull},
40967         {"ACK_NAK"                     ,        25,     1,      596,    "R/W",  0,      0,      0ull,   0ull},
40968         {"RESERVED_26_30"              ,        26,     5,      596,    "RAZ",  1,      1,      0,      0},
40969         {"DLLD"                        ,        31,     1,      596,    "R/W",  0,      0,      0ull,   0ull},
40970         {"NTSS"                        ,        0,      4,      597,    "R/W",  0,      0,      10ull,  10ull},
40971         {"RESERVED_4_7"                ,        4,      4,      597,    "RO",   1,      1,      0,      0},
40972         {"NSKPS"                       ,        8,      3,      597,    "R/W",  0,      0,      3ull,   3ull},
40973         {"RESERVED_11_13"              ,        11,     3,      597,    "RAZ",  1,      1,      0,      0},
40974         {"TMRT"                        ,        14,     5,      597,    "R/W",  0,      0,      8ull,   8ull},
40975         {"TMANLT"                      ,        19,     5,      597,    "R/W",  0,      0,      0ull,   0ull},
40976         {"TMFCWT"                      ,        24,     5,      597,    "R/W",  0,      0,      0ull,   0ull},
40977         {"RESERVED_29_31"              ,        29,     3,      597,    "RO",   1,      1,      0,      0},
40978         {"SKPIV"                       ,        0,      11,     598,    "R/W",  0,      0,      1280ull,        1280ull},
40979         {"RESERVED_11_14"              ,        11,     4,      598,    "RAZ",  1,      1,      0,      0},
40980         {"DFCWT"                       ,        15,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40981         {"M_FUN"                       ,        16,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40982         {"M_POIS_FILT"                 ,        17,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40983         {"M_BAR_MATCH"                 ,        18,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40984         {"M_CFG1_FILT"                 ,        19,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40985         {"M_LK_FILT"                   ,        20,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40986         {"M_CPL_TAG_ERR"               ,        21,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40987         {"M_CPL_RID_ERR"               ,        22,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40988         {"M_CPL_FUN_ERR"               ,        23,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40989         {"M_CPL_TC_ERR"                ,        24,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40990         {"M_CPL_ATTR_ERR"              ,        25,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40991         {"M_CPL_LEN_ERR"               ,        26,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40992         {"M_ECRC_FILT"                 ,        27,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40993         {"M_CPL_ECRC_FILT"             ,        28,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40994         {"MSG_CTRL"                    ,        29,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40995         {"M_IO_FILT"                   ,        30,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40996         {"M_CFG0_FILT"                 ,        31,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
40997         {"M_VEND0_DRP"                 ,        0,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
40998         {"M_VEND1_DRP"                 ,        1,      1,      599,    "R/W",  0,      0,      0ull,   0ull},
40999         {"RESERVED_2_31"               ,        2,      30,     599,    "RAZ",  1,      1,      0,      0},
41000         {"DBG_INFO_L32"                ,        0,      32,     600,    "RO",   0,      0,      0ull,   0ull},
41001         {"DBG_INFO_U32"                ,        0,      32,     601,    "RO",   0,      0,      0ull,   0ull},
41002         {"TPDFCC"                      ,        0,      12,     602,    "RO",   0,      0,      0ull,   0ull},
41003         {"TPHFCC"                      ,        12,     8,      602,    "RO",   0,      0,      0ull,   0ull},
41004         {"RESERVED_20_31"              ,        20,     12,     602,    "RAZ",  1,      1,      0,      0},
41005         {"TCDFCC"                      ,        0,      12,     603,    "RO",   0,      0,      0ull,   0ull},
41006         {"TCHFCC"                      ,        12,     8,      603,    "RO",   0,      0,      0ull,   0ull},
41007         {"RESERVED_20_31"              ,        20,     12,     603,    "RAZ",  1,      1,      0,      0},
41008         {"TCDFCC"                      ,        0,      12,     604,    "RO",   0,      0,      0ull,   0ull},
41009         {"TCHFCC"                      ,        12,     8,      604,    "RO",   0,      0,      0ull,   0ull},
41010         {"RESERVED_20_31"              ,        20,     12,     604,    "RAZ",  1,      1,      0,      0},
41011         {"RTLPFCCNR"                   ,        0,      1,      605,    "RO",   0,      0,      0ull,   0ull},
41012         {"TRBNE"                       ,        1,      1,      605,    "RO",   0,      0,      0ull,   0ull},
41013         {"RQNE"                        ,        2,      1,      605,    "RO",   0,      0,      0ull,   0ull},
41014         {"RESERVED_3_31"               ,        3,      29,     605,    "RAZ",  1,      1,      0,      0},
41015         {"WRR_VC0"                     ,        0,      8,      606,    "RO",   0,      0,      15ull,  15ull},
41016         {"WRR_VC1"                     ,        8,      8,      606,    "RO",   0,      0,      0ull,   0ull},
41017         {"WRR_VC2"                     ,        16,     8,      606,    "RO",   0,      0,      0ull,   0ull},
41018         {"WRR_VC3"                     ,        24,     8,      606,    "RO",   0,      0,      0ull,   0ull},
41019         {"WRR_VC4"                     ,        0,      8,      607,    "RO",   0,      0,      0ull,   0ull},
41020         {"WRR_VC5"                     ,        8,      8,      607,    "RO",   0,      0,      0ull,   0ull},
41021         {"WRR_VC6"                     ,        16,     8,      607,    "RO",   0,      0,      0ull,   0ull},
41022         {"WRR_VC7"                     ,        24,     8,      607,    "RO",   0,      0,      0ull,   0ull},
41023         {"DATA_CREDITS"                ,        0,      12,     608,    "R/W",  0,      0,      72ull,  72ull},
41024         {"HEADER_CREDITS"              ,        12,     8,      608,    "R/W",  0,      0,      32ull,  32ull},
41025         {"RESERVED_20_20"              ,        20,     1,      608,    "RAZ",  1,      1,      0,      0},
41026         {"QUEUE_MODE"                  ,        21,     3,      608,    "R/W",  0,      0,      2ull,   2ull},
41027         {"RESERVED_24_29"              ,        24,     6,      608,    "RAZ",  1,      1,      0,      0},
41028         {"TYPE_ORDERING"               ,        30,     1,      608,    "R/W",  0,      0,      1ull,   1ull},
41029         {"RX_QUEUE_ORDER"              ,        31,     1,      608,    "R/W",  0,      0,      0ull,   0ull},
41030         {"DATA_CREDITS"                ,        0,      12,     609,    "R/W",  0,      0,      4ull,   4ull},
41031         {"HEADER_CREDITS"              ,        12,     8,      609,    "R/W",  0,      0,      8ull,   8ull},
41032         {"RESERVED_20_20"              ,        20,     1,      609,    "RAZ",  1,      1,      0,      0},
41033         {"QUEUE_MODE"                  ,        21,     3,      609,    "R/W",  0,      0,      2ull,   2ull},
41034         {"RESERVED_24_31"              ,        24,     8,      609,    "RAZ",  1,      1,      0,      0},
41035         {"DATA_CREDITS"                ,        0,      12,     610,    "R/W",  0,      0,      128ull, 128ull},
41036         {"HEADER_CREDITS"              ,        12,     8,      610,    "R/W",  0,      0,      64ull,  64ull},
41037         {"RESERVED_20_20"              ,        20,     1,      610,    "RAZ",  1,      1,      0,      0},
41038         {"QUEUE_MODE"                  ,        21,     3,      610,    "R/W",  0,      0,      2ull,   2ull},
41039         {"RESERVED_24_31"              ,        24,     8,      610,    "RAZ",  1,      1,      0,      0},
41040         {"DATA_DEPTH"                  ,        0,      14,     611,    "R/W",  0,      0,      216ull, 216ull},
41041         {"RESERVED_14_15"              ,        14,     2,      611,    "RAZ",  1,      1,      0,      0},
41042         {"HEADER_DEPTH"                ,        16,     10,     611,    "R/W",  0,      0,      38ull,  38ull},
41043         {"RESERVED_26_31"              ,        26,     6,      611,    "RAZ",  1,      1,      0,      0},
41044         {"DATA_DEPTH"                  ,        0,      14,     612,    "R/W",  0,      0,      56ull,  56ull},
41045         {"RESERVED_14_15"              ,        14,     2,      612,    "RAZ",  1,      1,      0,      0},
41046         {"HEADER_DEPTH"                ,        16,     10,     612,    "R/W",  0,      0,      14ull,  14ull},
41047         {"RESERVED_26_31"              ,        26,     6,      612,    "RAZ",  1,      1,      0,      0},
41048         {"DATA_DEPTH"                  ,        0,      14,     613,    "R/W",  0,      0,      360ull, 360ull},
41049         {"RESERVED_14_15"              ,        14,     2,      613,    "RAZ",  1,      1,      0,      0},
41050         {"HEADER_DEPTH"                ,        16,     10,     613,    "R/W",  0,      0,      70ull,  70ull},
41051         {"RESERVED_26_31"              ,        26,     6,      613,    "RAZ",  1,      1,      0,      0},
41052         {"PHY_STAT"                    ,        0,      32,     614,    "RO",   0,      0,      0ull,   0ull},
41053         {"PHY_CTRL"                    ,        0,      32,     615,    "R/W",  0,      0,      0ull,   0ull},
41054         {"RESERVED_0_4"                ,        0,      5,      616,    "RAZ",  0,      0,      0ull,   0ull},
41055         {"FD"                          ,        5,      1,      616,    "R/W",  0,      0,      1ull,   1ull},
41056         {"HFD"                         ,        6,      1,      616,    "R/W",  0,      0,      1ull,   1ull},
41057         {"PAUSE"                       ,        7,      2,      616,    "R/W",  0,      0,      0ull,   0ull},
41058         {"RESERVED_9_11"               ,        9,      3,      616,    "RAZ",  0,      0,      0ull,   0ull},
41059         {"REM_FLT"                     ,        12,     2,      616,    "R/W",  0,      0,      0ull,   0ull},
41060         {"RESERVED_14_14"              ,        14,     1,      616,    "RAZ",  0,      0,      0ull,   0ull},
41061         {"NP"                          ,        15,     1,      616,    "RO",   0,      0,      0ull,   0ull},
41062         {"RESERVED_16_63"              ,        16,     48,     616,    "RAZ",  1,      1,      0,      0},
41063         {"RESERVED_0_11"               ,        0,      12,     617,    "RAZ",  0,      0,      0ull,   0ull},
41064         {"THOU_THD"                    ,        12,     1,      617,    "RO",   0,      0,      0ull,   0ull},
41065         {"THOU_TFD"                    ,        13,     1,      617,    "RO",   0,      0,      0ull,   0ull},
41066         {"THOU_XHD"                    ,        14,     1,      617,    "RO",   0,      0,      1ull,   1ull},
41067         {"THOU_XFD"                    ,        15,     1,      617,    "RO",   0,      0,      1ull,   1ull},
41068         {"RESERVED_16_63"              ,        16,     48,     617,    "RAZ",  1,      1,      0,      0},
41069         {"RESERVED_0_4"                ,        0,      5,      618,    "RAZ",  0,      0,      0ull,   0ull},
41070         {"FD"                          ,        5,      1,      618,    "RO",   0,      0,      0ull,   0ull},
41071         {"HFD"                         ,        6,      1,      618,    "RO",   0,      0,      0ull,   0ull},
41072         {"PAUSE"                       ,        7,      2,      618,    "RO",   0,      0,      0ull,   0ull},
41073         {"RESERVED_9_11"               ,        9,      3,      618,    "RAZ",  0,      0,      0ull,   0ull},
41074         {"REM_FLT"                     ,        12,     2,      618,    "RO",   0,      0,      0ull,   0ull},
41075         {"ACK"                         ,        14,     1,      618,    "RO",   0,      1,      0ull,   0},
41076         {"NP"                          ,        15,     1,      618,    "RO",   0,      0,      0ull,   0ull},
41077         {"RESERVED_16_63"              ,        16,     48,     618,    "RAZ",  1,      1,      0,      0},
41078         {"LINK_OK"                     ,        0,      1,      619,    "RO",   0,      0,      0ull,   0ull},
41079         {"DUP"                         ,        1,      1,      619,    "RO",   0,      0,      0ull,   0ull},
41080         {"AN_CPT"                      ,        2,      1,      619,    "RO",   0,      0,      0ull,   1ull},
41081         {"SPD"                         ,        3,      2,      619,    "RO",   0,      0,      0ull,   0ull},
41082         {"PAUSE"                       ,        5,      2,      619,    "RO",   0,      0,      0ull,   0ull},
41083         {"RESERVED_7_63"               ,        7,      57,     619,    "RAZ",  1,      1,      0,      0},
41084         {"LNKSPD_EN"                   ,        0,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41085         {"XMIT_EN"                     ,        1,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41086         {"AN_ERR_EN"                   ,        2,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41087         {"TXFIFU_EN"                   ,        3,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41088         {"TXFIFO_EN"                   ,        4,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41089         {"TXBAD_EN"                    ,        5,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41090         {"RXERR_EN"                    ,        6,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41091         {"RXBAD_EN"                    ,        7,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41092         {"RXLOCK_EN"                   ,        8,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41093         {"AN_BAD_EN"                   ,        9,      1,      620,    "R/W",  0,      0,      0ull,   1ull},
41094         {"SYNC_BAD_EN"                 ,        10,     1,      620,    "R/W",  0,      0,      0ull,   1ull},
41095         {"DUP"                         ,        11,     1,      620,    "R/W",  0,      0,      0ull,   1ull},
41096         {"RESERVED_12_63"              ,        12,     52,     620,    "RAZ",  1,      1,      0,      0},
41097         {"LNKSPD"                      ,        0,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41098         {"XMIT"                        ,        1,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41099         {"AN_ERR"                      ,        2,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41100         {"TXFIFU"                      ,        3,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41101         {"TXFIFO"                      ,        4,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41102         {"TXBAD"                       ,        5,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41103         {"RXERR"                       ,        6,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41104         {"RXBAD"                       ,        7,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41105         {"RXLOCK"                      ,        8,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41106         {"AN_BAD"                      ,        9,      1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41107         {"SYNC_BAD"                    ,        10,     1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41108         {"DUP"                         ,        11,     1,      621,    "R/W1C",        0,      0,      0ull,   0ull},
41109         {"RESERVED_12_63"              ,        12,     52,     621,    "RAZ",  1,      1,      0,      0},
41110         {"COUNT"                       ,        0,      16,     622,    "R/W",  0,      1,      1094ull,        0},
41111         {"RESERVED_16_63"              ,        16,     48,     622,    "RAZ",  1,      1,      0,      0},
41112         {"PKT_SZ"                      ,        0,      2,      623,    "R/W",  0,      0,      0ull,   0ull},
41113         {"LA_EN"                       ,        2,      1,      623,    "R/W",  0,      0,      0ull,   0ull},
41114         {"LAFIFOVFL"                   ,        3,      1,      623,    "R/W1C",        0,      0,      0ull,   0ull},
41115         {"RESERVED_4_63"               ,        4,      60,     623,    "RAZ",  1,      1,      0,      0},
41116         {"SAMP_PT"                     ,        0,      7,      624,    "R/W",  0,      1,      1ull,   0},
41117         {"AN_OVRD"                     ,        7,      1,      624,    "R/W",  0,      0,      0ull,   0ull},
41118         {"MODE"                        ,        8,      1,      624,    "R/W",  0,      0,      0ull,   0ull},
41119         {"MAC_PHY"                     ,        9,      1,      624,    "R/W",  0,      0,      0ull,   0ull},
41120         {"LOOPBCK2"                    ,        10,     1,      624,    "R/W",  0,      0,      0ull,   0ull},
41121         {"GMXENO"                      ,        11,     1,      624,    "R/W",  0,      0,      0ull,   0ull},
41122         {"SGMII"                       ,        12,     1,      624,    "RO",   1,      1,      0,      0},
41123         {"RESERVED_13_63"              ,        13,     51,     624,    "RAZ",  1,      1,      0,      0},
41124         {"RESERVED_0_4"                ,        0,      5,      625,    "RAZ",  1,      1,      0,      0},
41125         {"UNI"                         ,        5,      1,      625,    "R/W",  0,      0,      0ull,   0ull},
41126         {"SPDMSB"                      ,        6,      1,      625,    "R/W",  0,      0,      1ull,   1ull},
41127         {"COLTST"                      ,        7,      1,      625,    "R/W",  0,      0,      0ull,   0ull},
41128         {"DUP"                         ,        8,      1,      625,    "R/W",  0,      0,      1ull,   1ull},
41129         {"RST_AN"                      ,        9,      1,      625,    "R/W",  0,      0,      0ull,   0ull},
41130         {"RESERVED_10_10"              ,        10,     1,      625,    "RAZ",  1,      1,      0,      0},
41131         {"PWR_DN"                      ,        11,     1,      625,    "R/W",  0,      0,      1ull,   0ull},
41132         {"AN_EN"                       ,        12,     1,      625,    "R/W",  0,      0,      0ull,   0ull},
41133         {"SPDLSB"                      ,        13,     1,      625,    "R/W",  0,      0,      0ull,   0ull},
41134         {"LOOPBCK1"                    ,        14,     1,      625,    "R/W",  0,      0,      0ull,   0ull},
41135         {"RESET"                       ,        15,     1,      625,    "R/W",  0,      0,      0ull,   0ull},
41136         {"RESERVED_16_63"              ,        16,     48,     625,    "RAZ",  1,      1,      0,      0},
41137         {"EXTND"                       ,        0,      1,      626,    "RO",   0,      0,      0ull,   0ull},
41138         {"RESERVED_1_1"                ,        1,      1,      626,    "RAZ",  0,      0,      0ull,   0ull},
41139         {"LNK_ST"                      ,        2,      1,      626,    "RO",   0,      0,      0ull,   1ull},
41140         {"AN_ABIL"                     ,        3,      1,      626,    "RO",   0,      0,      1ull,   1ull},
41141         {"RM_FLT"                      ,        4,      1,      626,    "RO",   0,      0,      0ull,   0ull},
41142         {"AN_CPT"                      ,        5,      1,      626,    "RO",   0,      0,      0ull,   0ull},
41143         {"PRB_SUP"                     ,        6,      1,      626,    "RO",   0,      0,      1ull,   1ull},
41144         {"RESERVED_7_7"                ,        7,      1,      626,    "RAZ",  0,      0,      0ull,   0ull},
41145         {"EXT_ST"                      ,        8,      1,      626,    "RO",   0,      0,      1ull,   1ull},
41146         {"HUN_T2HD"                    ,        9,      1,      626,    "RO",   0,      0,      0ull,   0ull},
41147         {"HUN_T2FD"                    ,        10,     1,      626,    "RO",   0,      0,      0ull,   0ull},
41148         {"TEN_HD"                      ,        11,     1,      626,    "RO",   0,      0,      0ull,   0ull},
41149         {"TEN_FD"                      ,        12,     1,      626,    "RO",   0,      0,      0ull,   0ull},
41150         {"HUN_XHD"                     ,        13,     1,      626,    "RO",   0,      0,      0ull,   0ull},
41151         {"HUN_XFD"                     ,        14,     1,      626,    "RO",   0,      0,      0ull,   0ull},
41152         {"HUN_T4"                      ,        15,     1,      626,    "RO",   0,      0,      0ull,   0ull},
41153         {"RESERVED_16_63"              ,        16,     48,     626,    "RAZ",  1,      1,      0,      0},
41154         {"AN_ST"                       ,        0,      4,      627,    "RO",   0,      0,      0ull,   0ull},
41155         {"AN_BAD"                      ,        4,      1,      627,    "RO",   0,      0,      0ull,   0ull},
41156         {"SYNC"                        ,        5,      4,      627,    "RO",   0,      0,      0ull,   0ull},
41157         {"SYNC_BAD"                    ,        9,      1,      627,    "RO",   0,      0,      0ull,   0ull},
41158         {"RX_ST"                       ,        10,     5,      627,    "RO",   0,      0,      0ull,   0ull},
41159         {"RX_BAD"                      ,        15,     1,      627,    "RO",   0,      0,      0ull,   0ull},
41160         {"RESERVED_16_63"              ,        16,     48,     627,    "RAZ",  1,      1,      0,      0},
41161         {"BIT_LOCK"                    ,        0,      1,      628,    "RO",   0,      0,      0ull,   0ull},
41162         {"SYNC"                        ,        1,      1,      628,    "RO",   0,      0,      0ull,   0ull},
41163         {"RESERVED_2_63"               ,        2,      62,     628,    "RAZ",  1,      1,      0,      0},
41164         {"ONE"                         ,        0,      1,      629,    "RO",   0,      0,      1ull,   1ull},
41165         {"RESERVED_1_9"                ,        1,      9,      629,    "RAZ",  0,      1,      0ull,   0},
41166         {"SPEED"                       ,        10,     2,      629,    "R/W",  0,      0,      2ull,   2ull},
41167         {"DUP"                         ,        12,     1,      629,    "R/W",  0,      0,      1ull,   1ull},
41168         {"RESERVED_13_13"              ,        13,     1,      629,    "RAZ",  0,      1,      0ull,   0},
41169         {"ACK"                         ,        14,     1,      629,    "RO",   0,      0,      0ull,   0ull},
41170         {"LINK"                        ,        15,     1,      629,    "R/W",  0,      0,      0ull,   1ull},
41171         {"RESERVED_16_63"              ,        16,     48,     629,    "RAZ",  1,      1,      0,      0},
41172         {"ONE"                         ,        0,      1,      630,    "RO",   0,      0,      1ull,   1ull},
41173         {"RESERVED_1_9"                ,        1,      9,      630,    "RAZ",  0,      1,      0ull,   0},
41174         {"SPEED"                       ,        10,     2,      630,    "RO",   0,      0,      0ull,   2ull},
41175         {"DUP"                         ,        12,     1,      630,    "RO",   0,      0,      0ull,   1ull},
41176         {"RESERVED_13_14"              ,        13,     2,      630,    "RAZ",  0,      1,      0ull,   0},
41177         {"LINK"                        ,        15,     1,      630,    "RO",   0,      0,      0ull,   1ull},
41178         {"RESERVED_16_63"              ,        16,     48,     630,    "RAZ",  1,      1,      0,      0},
41179         {"ORD_ST"                      ,        0,      4,      631,    "RO",   0,      0,      0ull,   0ull},
41180         {"TX_BAD"                      ,        4,      1,      631,    "RO",   0,      0,      0ull,   0ull},
41181         {"XMIT"                        ,        5,      2,      631,    "RO",   0,      1,      0ull,   0},
41182         {"RESERVED_7_63"               ,        7,      57,     631,    "RAZ",  1,      1,      0,      0},
41183         {"TXPLRT"                      ,        0,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
41184         {"RXPLRT"                      ,        1,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
41185         {"AUTORXPL"                    ,        2,      1,      632,    "RO",   0,      0,      0ull,   0ull},
41186         {"RXOVRD"                      ,        3,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
41187         {"RESERVED_4_63"               ,        4,      60,     632,    "RAZ",  1,      1,      0,      0},
41188         {"L0SYNC"                      ,        0,      1,      633,    "RO",   0,      0,      0ull,   1ull},
41189         {"L1SYNC"                      ,        1,      1,      633,    "RO",   0,      0,      0ull,   1ull},
41190         {"L2SYNC"                      ,        2,      1,      633,    "RO",   0,      0,      0ull,   1ull},
41191         {"L3SYNC"                      ,        3,      1,      633,    "RO",   0,      0,      0ull,   1ull},
41192         {"RESERVED_4_10"               ,        4,      7,      633,    "RAZ",  1,      1,      0,      0},
41193         {"PATTST"                      ,        11,     1,      633,    "RO",   0,      0,      0ull,   0ull},
41194         {"ALIGND"                      ,        12,     1,      633,    "RO",   0,      0,      0ull,   1ull},
41195         {"RESERVED_13_63"              ,        13,     51,     633,    "RAZ",  1,      1,      0,      0},
41196         {"BIST_STATUS"                 ,        0,      1,      634,    "RO",   0,      0,      0ull,   0ull},
41197         {"RESERVED_1_63"               ,        1,      63,     634,    "RAZ",  1,      1,      0,      0},
41198         {"BITLCK0"                     ,        0,      1,      635,    "RO",   0,      1,      0ull,   0},
41199         {"BITLCK1"                     ,        1,      1,      635,    "RO",   0,      1,      0ull,   0},
41200         {"BITLCK2"                     ,        2,      1,      635,    "RO",   0,      1,      0ull,   0},
41201         {"BITLCK3"                     ,        3,      1,      635,    "RO",   0,      1,      0ull,   0},
41202         {"RESERVED_4_63"               ,        4,      60,     635,    "RAZ",  1,      1,      0,      0},
41203         {"RESERVED_0_1"                ,        0,      2,      636,    "RAZ",  1,      1,      0,      0},
41204         {"SPD"                         ,        2,      4,      636,    "RO",   0,      0,      0ull,   0ull},
41205         {"SPDSEL0"                     ,        6,      1,      636,    "RO",   0,      0,      1ull,   1ull},
41206         {"RESERVED_7_10"               ,        7,      4,      636,    "RAZ",  1,      1,      0,      0},
41207         {"LO_PWR"                      ,        11,     1,      636,    "R/W",  0,      0,      0ull,   0ull},
41208         {"RESERVED_12_12"              ,        12,     1,      636,    "RAZ",  1,      1,      0,      0},
41209         {"SPDSEL1"                     ,        13,     1,      636,    "RO",   0,      0,      1ull,   1ull},
41210         {"LOOPBCK1"                    ,        14,     1,      636,    "R/W",  0,      0,      0ull,   0ull},
41211         {"RESET"                       ,        15,     1,      636,    "R/W",  0,      0,      1ull,   0ull},
41212         {"RESERVED_16_63"              ,        16,     48,     636,    "RAZ",  1,      1,      0,      0},
41213         {"TYPE"                        ,        0,      2,      637,    "RO",   0,      0,      1ull,   1ull},
41214         {"RESERVED_2_63"               ,        2,      62,     637,    "RAZ",  1,      1,      0,      0},
41215         {"TXFLT_EN"                    ,        0,      1,      638,    "R/W",  0,      0,      0ull,   1ull},
41216         {"RXBAD_EN"                    ,        1,      1,      638,    "R/W",  0,      0,      0ull,   1ull},
41217         {"RXSYNBAD_EN"                 ,        2,      1,      638,    "R/W",  0,      0,      0ull,   1ull},
41218         {"BITLCKLS_EN"                 ,        3,      1,      638,    "R/W",  0,      0,      0ull,   1ull},
41219         {"SYNLOS_EN"                   ,        4,      1,      638,    "R/W",  0,      0,      0ull,   1ull},
41220         {"ALGNLOS_EN"                  ,        5,      1,      638,    "R/W",  0,      0,      0ull,   1ull},
41221         {"RESERVED_6_63"               ,        6,      58,     638,    "RAZ",  1,      1,      0,      0},
41222         {"TXFLT"                       ,        0,      1,      639,    "R/W1C",        0,      0,      0ull,   0ull},
41223         {"RXBAD"                       ,        1,      1,      639,    "R/W1C",        0,      0,      0ull,   0ull},
41224         {"RXSYNBAD"                    ,        2,      1,      639,    "R/W1C",        0,      0,      0ull,   0ull},
41225         {"BITLCKLS"                    ,        3,      1,      639,    "R/W1C",        0,      0,      0ull,   0ull},
41226         {"SYNLOS"                      ,        4,      1,      639,    "R/W1C",        0,      0,      0ull,   0ull},
41227         {"ALGNLOS"                     ,        5,      1,      639,    "R/W1C",        0,      0,      0ull,   0ull},
41228         {"RESERVED_6_63"               ,        6,      58,     639,    "RAZ",  1,      1,      0,      0},
41229         {"PKT_SZ"                      ,        0,      2,      640,    "R/W",  0,      0,      0ull,   0ull},
41230         {"LA_EN"                       ,        2,      1,      640,    "R/W",  0,      0,      0ull,   0ull},
41231         {"LAFIFOVFL"                   ,        3,      1,      640,    "R/W1C",        0,      0,      0ull,   0ull},
41232         {"DROP_LN"                     ,        4,      2,      640,    "R/W",  0,      0,      0ull,   0ull},
41233         {"ENC_MODE"                    ,        6,      1,      640,    "R/W",  0,      0,      0ull,   0ull},
41234         {"RESERVED_7_63"               ,        7,      57,     640,    "RAZ",  1,      1,      0,      0},
41235         {"GMXENO"                      ,        0,      1,      641,    "R/W",  0,      0,      0ull,   0ull},
41236         {"XAUI"                        ,        1,      1,      641,    "RO",   1,      1,      0,      0},
41237         {"RX_SWAP"                     ,        2,      1,      641,    "R/W",  0,      1,      0ull,   0},
41238         {"TX_SWAP"                     ,        3,      1,      641,    "R/W",  0,      1,      0ull,   0},
41239         {"RESERVED_4_63"               ,        4,      60,     641,    "RAZ",  1,      1,      0,      0},
41240         {"SYNC0ST"                     ,        0,      4,      642,    "RO",   0,      1,      0ull,   0},
41241         {"SYNC1ST"                     ,        4,      4,      642,    "RO",   0,      1,      0ull,   0},
41242         {"SYNC2ST"                     ,        8,      4,      642,    "RO",   0,      1,      0ull,   0},
41243         {"SYNC3ST"                     ,        12,     4,      642,    "RO",   0,      1,      0ull,   0},
41244         {"RESERVED_16_63"              ,        16,     48,     642,    "RAZ",  1,      1,      0,      0},
41245         {"TENGB"                       ,        0,      1,      643,    "RO",   0,      0,      1ull,   1ull},
41246         {"TENPASST"                    ,        1,      1,      643,    "RO",   0,      0,      0ull,   0ull},
41247         {"RESERVED_2_63"               ,        2,      62,     643,    "RAZ",  1,      1,      0,      0},
41248         {"RESERVED_0_0"                ,        0,      1,      644,    "RAZ",  1,      1,      0,      0},
41249         {"LPABLE"                      ,        1,      1,      644,    "RO",   0,      0,      1ull,   1ull},
41250         {"RCV_LNK"                     ,        2,      1,      644,    "RO",   0,      0,      0ull,   1ull},
41251         {"RESERVED_3_6"                ,        3,      4,      644,    "RAZ",  1,      1,      0,      0},
41252         {"FLT"                         ,        7,      1,      644,    "RO",   0,      0,      0ull,   0ull},
41253         {"RESERVED_8_63"               ,        8,      56,     644,    "RAZ",  1,      1,      0,      0},
41254         {"TENGB_R"                     ,        0,      1,      645,    "RO",   0,      0,      0ull,   0ull},
41255         {"TENGB_X"                     ,        1,      1,      645,    "RO",   0,      0,      1ull,   1ull},
41256         {"TENGB_W"                     ,        2,      1,      645,    "RO",   0,      0,      0ull,   0ull},
41257         {"RESERVED_3_9"                ,        3,      7,      645,    "RAZ",  1,      1,      0,      0},
41258         {"RCVFLT"                      ,        10,     1,      645,    "RC",   0,      0,      0ull,   0ull},
41259         {"XMTFLT"                      ,        11,     1,      645,    "RC",   0,      0,      0ull,   0ull},
41260         {"RESERVED_12_13"              ,        12,     2,      645,    "RAZ",  1,      1,      0,      0},
41261         {"DEV"                         ,        14,     2,      645,    "RO",   0,      0,      2ull,   2ull},
41262         {"RESERVED_16_63"              ,        16,     48,     645,    "RAZ",  1,      1,      0,      0},
41263         {"TXPLRT"                      ,        0,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
41264         {"RXPLRT"                      ,        1,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
41265         {"RESERVED_2_63"               ,        2,      62,     646,    "RAZ",  1,      1,      0,      0},
41266         {"TX_ST"                       ,        0,      3,      647,    "RO",   0,      1,      0ull,   0},
41267         {"RX_ST"                       ,        3,      2,      647,    "RO",   0,      1,      0ull,   0},
41268         {"ALGN_ST"                     ,        5,      3,      647,    "RO",   0,      1,      0ull,   0},
41269         {"RXBAD"                       ,        8,      1,      647,    "RO",   0,      0,      0ull,   0ull},
41270         {"SYN0BAD"                     ,        9,      1,      647,    "RO",   0,      0,      0ull,   0ull},
41271         {"SYN1BAD"                     ,        10,     1,      647,    "RO",   0,      0,      0ull,   0ull},
41272         {"SYN2BAD"                     ,        11,     1,      647,    "RO",   0,      0,      0ull,   0ull},
41273         {"SYN3BAD"                     ,        12,     1,      647,    "RO",   0,      0,      0ull,   0ull},
41274         {"RESERVED_13_63"              ,        13,     51,     647,    "RAZ",  1,      1,      0,      0},
41275         {"SOT"                         ,        0,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41276         {"RQHDR0"                      ,        1,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41277         {"RQHDR1"                      ,        2,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41278         {"RQDATA4"                     ,        3,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41279         {"RQDATA3"                     ,        4,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41280         {"RQDATA2"                     ,        5,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41281         {"RQDATA1"                     ,        6,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41282         {"RQDATA0"                     ,        7,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41283         {"RETRY"                       ,        8,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41284         {"PTLP_OR"                     ,        9,      1,      648,    "RO",   0,      0,      0ull,   0ull},
41285         {"NTLP_OR"                     ,        10,     1,      648,    "RO",   0,      0,      0ull,   0ull},
41286         {"CTLP_OR"                     ,        11,     1,      648,    "RO",   0,      0,      0ull,   0ull},
41287         {"RESERVED_12_63"              ,        12,     52,     648,    "RAZ",  1,      1,      0,      0},
41288         {"PPF"                         ,        0,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41289         {"PEF_TC0"                     ,        1,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41290         {"PEF_TCF1"                    ,        2,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41291         {"PEF_TNF"                     ,        3,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41292         {"PEF_TPF0"                    ,        4,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41293         {"PEF_TPF1"                    ,        5,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41294         {"RSL_P2E"                     ,        6,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41295         {"PEAI_P2E"                    ,        7,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41296         {"DBG_P2E"                     ,        8,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41297         {"E2P_RSL"                     ,        9,      1,      649,    "RO",   0,      0,      0ull,   0ull},
41298         {"E2P_P"                       ,        10,     1,      649,    "RO",   0,      0,      0ull,   0ull},
41299         {"E2P_N"                       ,        11,     1,      649,    "RO",   0,      0,      0ull,   0ull},
41300         {"E2P_CPL"                     ,        12,     1,      649,    "RO",   0,      0,      0ull,   0ull},
41301         {"CTO_P2E"                     ,        13,     1,      649,    "RO",   0,      0,      0ull,   0ull},
41302         {"RESERVED_14_63"              ,        14,     50,     649,    "RAZ",  1,      1,      0,      0},
41303         {"ADDR"                        ,        0,      32,     650,    "R/W",  0,      1,      0ull,   0},
41304         {"DATA"                        ,        32,     32,     650,    "R/W",  0,      1,      0ull,   0},
41305         {"ADDR"                        ,        0,      32,     651,    "R/W",  0,      1,      0ull,   0},
41306         {"DATA"                        ,        32,     32,     651,    "R/W",  0,      1,      0ull,   0},
41307         {"TAG"                         ,        0,      32,     652,    "RO",   0,      0,      0ull,   0ull},
41308         {"RESERVED_32_63"              ,        32,     32,     652,    "RAZ",  1,      1,      0,      0},
41309         {"INV_LCRC"                    ,        0,      1,      653,    "R/W",  0,      0,      0ull,   0ull},
41310         {"INV_ECRC"                    ,        1,      1,      653,    "R/W",  0,      0,      0ull,   0ull},
41311         {"RESERVED_2_2"                ,        2,      1,      653,    "RAZ",  0,      0,      0ull,   0ull},
41312         {"RO_CTLP"                     ,        3,      1,      653,    "R/W",  0,      0,      0ull,   0ull},
41313         {"LNK_ENB"                     ,        4,      1,      653,    "R/W",  0,      0,      0ull,   0ull},
41314         {"DLY_ONE"                     ,        5,      1,      653,    "R/W",  0,      0,      0ull,   0ull},
41315         {"NF_ECRC"                     ,        6,      1,      653,    "R/W",  0,      0,      0ull,   0ull},
41316         {"RESERVED_7_8"                ,        7,      2,      653,    "RAZ",  0,      0,      0ull,   0ull},
41317         {"OB_P_CMD"                    ,        9,      1,      653,    "R/W",  0,      0,      0ull,   0ull},
41318         {"PM_XPME"                     ,        10,     1,      653,    "R/W",  0,      0,      0ull,   0ull},
41319         {"PM_XTOFF"                    ,        11,     1,      653,    "R/W",  0,      0,      0ull,   0ull},
41320         {"RESERVED_12_12"              ,        12,     1,      653,    "RAZ",  0,      0,      0ull,   0ull},
41321         {"QLM_CFG"                     ,        13,     2,      653,    "RO",   1,      1,      0,      0},
41322         {"PBUS"                        ,        15,     8,      653,    "RO",   1,      1,      0,      0},
41323         {"DNUM"                        ,        23,     5,      653,    "RO",   1,      1,      0,      0},
41324         {"RESERVED_28_63"              ,        28,     36,     653,    "RAZ",  1,      1,      0,      0},
41325         {"PCIERST"                     ,        0,      1,      654,    "RO",   0,      0,      0ull,   0ull},
41326         {"RESERVED_1_63"               ,        1,      63,     654,    "RAZ",  1,      1,      0,      0},
41327         {"SPOISON"                     ,        0,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41328         {"RTLPMAL"                     ,        1,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41329         {"RTLPLLE"                     ,        2,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41330         {"RECRCE"                      ,        3,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41331         {"RPOISON"                     ,        4,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41332         {"RCEMRC"                      ,        5,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41333         {"RNFEMRC"                     ,        6,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41334         {"RFEMRC"                      ,        7,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41335         {"RPMERC"                      ,        8,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41336         {"RPTAMRC"                     ,        9,      1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41337         {"RUMEP"                       ,        10,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41338         {"RVDM"                        ,        11,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41339         {"ACTO"                        ,        12,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41340         {"RTE"                         ,        13,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41341         {"MRE"                         ,        14,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41342         {"RDWDLE"                      ,        15,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41343         {"RTWDLE"                      ,        16,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41344         {"DPEOOSD"                     ,        17,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41345         {"FCPVWT"                      ,        18,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41346         {"RPE"                         ,        19,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41347         {"FCUV"                        ,        20,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41348         {"RQO"                         ,        21,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41349         {"RAUC"                        ,        22,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41350         {"RACUR"                       ,        23,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41351         {"RACCA"                       ,        24,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41352         {"CAAR"                        ,        25,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41353         {"RARWDNS"                     ,        26,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41354         {"RAMTLP"                      ,        27,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41355         {"RACPP"                       ,        28,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41356         {"RAWWPP"                      ,        29,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41357         {"ECRC_E"                      ,        30,     1,      655,    "R/W1C",        0,      0,      0ull,   0ull},
41358         {"RESERVED_31_63"              ,        31,     33,     655,    "RAZ",  1,      1,      0,      0},
41359         {"SPOISON"                     ,        0,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41360         {"RTLPMAL"                     ,        1,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41361         {"RTLPLLE"                     ,        2,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41362         {"RECRCE"                      ,        3,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41363         {"RPOISON"                     ,        4,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41364         {"RCEMRC"                      ,        5,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41365         {"RNFEMRC"                     ,        6,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41366         {"RFEMRC"                      ,        7,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41367         {"RPMERC"                      ,        8,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41368         {"RPTAMRC"                     ,        9,      1,      656,    "R/W",  0,      0,      0ull,   0ull},
41369         {"RUMEP"                       ,        10,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41370         {"RVDM"                        ,        11,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41371         {"ACTO"                        ,        12,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41372         {"RTE"                         ,        13,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41373         {"MRE"                         ,        14,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41374         {"RDWDLE"                      ,        15,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41375         {"RTWDLE"                      ,        16,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41376         {"DPEOOSD"                     ,        17,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41377         {"FCPVWT"                      ,        18,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41378         {"RPE"                         ,        19,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41379         {"FCUV"                        ,        20,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41380         {"RQO"                         ,        21,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41381         {"RAUC"                        ,        22,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41382         {"RACUR"                       ,        23,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41383         {"RACCA"                       ,        24,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41384         {"CAAR"                        ,        25,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41385         {"RARWDNS"                     ,        26,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41386         {"RAMTLP"                      ,        27,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41387         {"RACPP"                       ,        28,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41388         {"RAWWPP"                      ,        29,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41389         {"ECRC_E"                      ,        30,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
41390         {"RESERVED_31_63"              ,        31,     33,     656,    "RAZ",  1,      1,      0,      0},
41391         {"AUX_EN"                      ,        0,      1,      657,    "RO",   0,      0,      0ull,   0ull},
41392         {"PM_EN"                       ,        1,      1,      657,    "RO",   0,      0,      0ull,   0ull},
41393         {"PM_STAT"                     ,        2,      1,      657,    "RO",   0,      0,      0ull,   0ull},
41394         {"PM_DST"                      ,        3,      1,      657,    "RO",   0,      0,      0ull,   0ull},
41395         {"RESERVED_4_63"               ,        4,      60,     657,    "RO",   1,      1,      0,      0},
41396         {"RESERVED_0_13"               ,        0,      14,     658,    "RAZ",  1,      1,      0,      0},
41397         {"ADDR"                        ,        14,     50,     658,    "R/W",  0,      0,      0ull,   0ull},
41398         {"RESERVED_0_25"               ,        0,      26,     659,    "RAZ",  1,      1,      0,      0},
41399         {"ADDR"                        ,        26,     38,     659,    "R/W",  0,      0,      0ull,   0ull},
41400         {"RESERVED_0_38"               ,        0,      39,     660,    "RAZ",  1,      1,      0,      0},
41401         {"ADDR"                        ,        39,     25,     660,    "R/W",  0,      0,      0ull,   0ull},
41402         {"RESERVED_0_11"               ,        0,      12,     661,    "RAZ",  1,      1,      0,      0},
41403         {"ADDR"                        ,        12,     52,     661,    "R/W",  0,      1,      4503599627370495ull,    0},
41404         {"RESERVED_0_11"               ,        0,      12,     662,    "RAZ",  1,      1,      0,      0},
41405         {"ADDR"                        ,        12,     52,     662,    "R/W",  0,      1,      4503599627370495ull,    0},
41406         {"NPEI_P"                      ,        0,      5,      663,    "R/W",  0,      0,      2ull,   2ull},
41407         {"NPEI_NP"                     ,        5,      5,      663,    "R/W",  0,      0,      2ull,   2ull},
41408         {"NPEI_CPL"                    ,        10,     5,      663,    "R/W",  0,      0,      2ull,   2ull},
41409         {"PESC_P"                      ,        15,     5,      663,    "R/W",  0,      0,      2ull,   2ull},
41410         {"PESC_NP"                     ,        20,     5,      663,    "R/W",  0,      0,      2ull,   2ull},
41411         {"PESC_CPL"                    ,        25,     5,      663,    "R/W",  0,      0,      2ull,   2ull},
41412         {"PEAI_PPF"                    ,        30,     8,      663,    "R/W",  0,      0,      3ull,   3ull},
41413         {"RESERVED_38_63"              ,        38,     26,     663,    "RAZ",  1,      1,      0,      0},
41414         {"LOWATER"                     ,        0,      5,      664,    "R/W",  0,      0,      4ull,   4ull},
41415         {"RESERVED_5_7"                ,        5,      3,      664,    "RAZ",  0,      1,      0ull,   0},
41416         {"HIWATER"                     ,        8,      5,      664,    "R/W",  0,      0,      24ull,  24ull},
41417         {"RESERVED_13_62"              ,        13,     50,     664,    "RAZ",  0,      1,      0ull,   0},
41418         {"BCKPRS"                      ,        63,     1,      664,    "RO",   0,      0,      0ull,   0ull},
41419         {"BIST"                        ,        0,      18,     665,    "RO",   0,      0,      0ull,   0ull},
41420         {"RESERVED_18_63"              ,        18,     46,     665,    "RAZ",  1,      1,      0,      0},
41421         {"DPRT"                        ,        0,      16,     666,    "R/W",  0,      0,      0ull,   0ull},
41422         {"UDP"                         ,        16,     1,      666,    "R/W",  0,      0,      0ull,   0ull},
41423         {"TCP"                         ,        17,     1,      666,    "R/W",  0,      0,      0ull,   0ull},
41424         {"RESERVED_18_63"              ,        18,     46,     666,    "RAZ",  1,      1,      0,      0},
41425         {"MINLEN"                      ,        0,      16,     667,    "R/W",  0,      0,      64ull,  64ull},
41426         {"MAXLEN"                      ,        16,     16,     667,    "R/W",  0,      0,      1536ull,        1536ull},
41427         {"RESERVED_32_63"              ,        32,     32,     667,    "RAZ",  1,      1,      0,      0},
41428         {"NIP_SHF"                     ,        0,      3,      668,    "R/W",  0,      0,      0ull,   0ull},
41429         {"RESERVED_3_7"                ,        3,      5,      668,    "RAZ",  1,      1,      0,      0},
41430         {"RAW_SHF"                     ,        8,      3,      668,    "R/W",  0,      0,      0ull,   0ull},
41431         {"RESERVED_11_15"              ,        11,     5,      668,    "RAZ",  1,      1,      0,      0},
41432         {"MAX_L2"                      ,        16,     1,      668,    "R/W",  0,      0,      0ull,   0ull},
41433         {"IP6_UDP"                     ,        17,     1,      668,    "R/W",  0,      0,      1ull,   1ull},
41434         {"TAG_SYN"                     ,        18,     1,      668,    "R/W",  0,      0,      0ull,   0ull},
41435         {"RESERVED_19_63"              ,        19,     45,     668,    "RAZ",  1,      1,      0,      0},
41436         {"IP_CHK"                      ,        0,      1,      669,    "R/W",  0,      0,      1ull,   1ull},
41437         {"IP_MAL"                      ,        1,      1,      669,    "R/W",  0,      0,      1ull,   1ull},
41438         {"IP_HOP"                      ,        2,      1,      669,    "R/W",  0,      0,      1ull,   1ull},
41439         {"IP4_OPTS"                    ,        3,      1,      669,    "R/W",  0,      0,      1ull,   1ull},
41440         {"IP6_EEXT"                    ,        4,      2,      669,    "R/W",  0,      0,      1ull,   3ull},
41441         {"RESERVED_6_7"                ,        6,      2,      669,    "RAZ",  1,      1,      0,      0},
41442         {"L4_MAL"                      ,        8,      1,      669,    "R/W",  0,      0,      1ull,   1ull},
41443         {"L4_PRT"                      ,        9,      1,      669,    "R/W",  0,      0,      1ull,   1ull},
41444         {"L4_CHK"                      ,        10,     1,      669,    "R/W",  0,      0,      1ull,   1ull},
41445         {"L4_LEN"                      ,        11,     1,      669,    "R/W",  0,      0,      1ull,   1ull},
41446         {"TCP_FLAG"                    ,        12,     1,      669,    "R/W",  0,      0,      1ull,   1ull},
41447         {"L2_MAL"                      ,        13,     1,      669,    "R/W",  0,      0,      1ull,   1ull},
41448         {"VS_QOS"                      ,        14,     1,      669,    "R/W",  0,      0,      0ull,   0ull},
41449         {"VS_WQE"                      ,        15,     1,      669,    "R/W",  0,      0,      0ull,   0ull},
41450         {"IGNRS"                       ,        16,     1,      669,    "R/W",  0,      0,      0ull,   0ull},
41451         {"RESERVED_17_19"              ,        17,     3,      669,    "RAZ",  0,      0,      0ull,   0ull},
41452         {"RING_EN"                     ,        20,     1,      669,    "R/W",  0,      0,      0ull,   1ull},
41453         {"RESERVED_21_63"              ,        21,     43,     669,    "RAZ",  1,      1,      0,      0},
41454         {"PKTDRP"                      ,        0,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41455         {"CRCERR"                      ,        1,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41456         {"BCKPRS"                      ,        2,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41457         {"PRTNXA"                      ,        3,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41458         {"BADTAG"                      ,        4,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41459         {"SKPRUNT"                     ,        5,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41460         {"TODOOVR"                     ,        6,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41461         {"FEPERR"                      ,        7,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41462         {"BEPERR"                      ,        8,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41463         {"MINERR"                      ,        9,      1,      670,    "R/W",  0,      0,      0ull,   0ull},
41464         {"MAXERR"                      ,        10,     1,      670,    "R/W",  0,      0,      0ull,   0ull},
41465         {"LENERR"                      ,        11,     1,      670,    "R/W",  0,      0,      0ull,   0ull},
41466         {"RESERVED_12_63"              ,        12,     52,     670,    "RAZ",  1,      1,      0,      0},
41467         {"PKTDRP"                      ,        0,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41468         {"CRCERR"                      ,        1,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41469         {"BCKPRS"                      ,        2,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41470         {"PRTNXA"                      ,        3,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41471         {"BADTAG"                      ,        4,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41472         {"SKPRUNT"                     ,        5,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41473         {"TODOOVR"                     ,        6,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41474         {"FEPERR"                      ,        7,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41475         {"BEPERR"                      ,        8,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41476         {"MINERR"                      ,        9,      1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41477         {"MAXERR"                      ,        10,     1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41478         {"LENERR"                      ,        11,     1,      671,    "R/W1C",        0,      0,      0ull,   0ull},
41479         {"RESERVED_12_63"              ,        12,     52,     671,    "RAZ",  1,      1,      0,      0},
41480         {"OFFSET"                      ,        0,      3,      672,    "R/W",  0,      0,      0ull,   0ull},
41481         {"RESERVED_3_63"               ,        3,      61,     672,    "RAZ",  1,      1,      0,      0},
41482         {"SKIP"                        ,        0,      7,      673,    "R/W",  0,      0,      0ull,   0ull},
41483         {"RESERVED_7_7"                ,        7,      1,      673,    "RAZ",  1,      1,      0,      0},
41484         {"MODE"                        ,        8,      2,      673,    "R/W",  0,      0,      0ull,   0ull},
41485         {"RESERVED_10_11"              ,        10,     2,      673,    "RAZ",  1,      1,      0,      0},
41486         {"CRC_EN"                      ,        12,     1,      673,    "RO",   0,      0,      0ull,   0ull},
41487         {"RESERVED_13_15"              ,        13,     3,      673,    "RAZ",  1,      1,      0,      0},
41488         {"QOS_VLAN"                    ,        16,     1,      673,    "R/W",  0,      0,      0ull,   0ull},
41489         {"QOS_DIFF"                    ,        17,     1,      673,    "R/W",  0,      0,      0ull,   0ull},
41490         {"QOS_VOD"                     ,        18,     1,      673,    "R/W",  0,      0,      0ull,   0ull},
41491         {"RESERVED_19_19"              ,        19,     1,      673,    "RAZ",  1,      1,      0,      0},
41492         {"QOS_WAT"                     ,        20,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
41493         {"QOS"                         ,        24,     3,      673,    "R/W",  0,      0,      0ull,   0ull},
41494         {"RESERVED_27_27"              ,        27,     1,      673,    "RAZ",  1,      1,      0,      0},
41495         {"GRP_WAT"                     ,        28,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
41496         {"INST_HDR"                    ,        32,     1,      673,    "R/W",  0,      0,      0ull,   0ull},
41497         {"DYN_RS"                      ,        33,     1,      673,    "R/W",  0,      0,      0ull,   0ull},
41498         {"TAG_INC"                     ,        34,     2,      673,    "R/W",  0,      0,      0ull,   0ull},
41499         {"RAWDRP"                      ,        36,     1,      673,    "R/W",  0,      0,      0ull,   0ull},
41500         {"RESERVED_37_39"              ,        37,     3,      673,    "RAZ",  1,      1,      0,      0},
41501         {"QOS_WAT_47"                  ,        40,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
41502         {"GRP_WAT_47"                  ,        44,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
41503         {"MINERR_EN"                   ,        48,     1,      673,    "R/W",  0,      0,      1ull,   1ull},
41504         {"MAXERR_EN"                   ,        49,     1,      673,    "R/W",  0,      0,      1ull,   1ull},
41505         {"LENERR_EN"                   ,        50,     1,      673,    "R/W",  0,      0,      1ull,   1ull},
41506         {"VLAN_LEN"                    ,        51,     1,      673,    "R/W",  0,      0,      0ull,   0ull},
41507         {"PAD_LEN"                     ,        52,     1,      673,    "R/W",  0,      0,      0ull,   0ull},
41508         {"RESERVED_53_63"              ,        53,     11,     673,    "RAZ",  1,      1,      0,      0},
41509         {"GRP"                         ,        0,      4,      674,    "R/W",  0,      0,      0ull,   0ull},
41510         {"NON_TAG_TYPE"                ,        4,      2,      674,    "R/W",  0,      0,      0ull,   0ull},
41511         {"IP4_TAG_TYPE"                ,        6,      2,      674,    "R/W",  0,      0,      0ull,   0ull},
41512         {"IP6_TAG_TYPE"                ,        8,      2,      674,    "R/W",  0,      0,      0ull,   0ull},
41513         {"TCP4_TAG_TYPE"               ,        10,     2,      674,    "R/W",  0,      0,      0ull,   0ull},
41514         {"TCP6_TAG_TYPE"               ,        12,     2,      674,    "R/W",  0,      0,      0ull,   0ull},
41515         {"IP4_SRC_FLAG"                ,        14,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41516         {"IP6_SRC_FLAG"                ,        15,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41517         {"IP4_DST_FLAG"                ,        16,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41518         {"IP6_DST_FLAG"                ,        17,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41519         {"IP4_PCTL_FLAG"               ,        18,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41520         {"IP6_NXTH_FLAG"               ,        19,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41521         {"IP4_SPRT_FLAG"               ,        20,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41522         {"IP6_SPRT_FLAG"               ,        21,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41523         {"IP4_DPRT_FLAG"               ,        22,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41524         {"IP6_DPRT_FLAG"               ,        23,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41525         {"INC_PRT_FLAG"                ,        24,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41526         {"INC_VLAN"                    ,        25,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41527         {"INC_VS"                      ,        26,     2,      674,    "R/W",  0,      0,      0ull,   0ull},
41528         {"TAG_MODE"                    ,        28,     2,      674,    "R/W",  0,      0,      0ull,   0ull},
41529         {"GRPTAG_MSKIP"                ,        30,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41530         {"GRPTAG"                      ,        31,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
41531         {"GRPTAGMASK"                  ,        32,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
41532         {"GRPTAGBASE"                  ,        36,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
41533         {"RESERVED_40_63"              ,        40,     24,     674,    "RAZ",  1,      1,      0,      0},
41534         {"QOS"                         ,        0,      3,      675,    "R/W",  0,      0,      0ull,   0ull},
41535         {"RESERVED_3_63"               ,        3,      61,     675,    "RAZ",  1,      1,      0,      0},
41536         {"QOS"                         ,        0,      3,      676,    "R/W",  0,      0,      0ull,   0ull},
41537         {"RESERVED_3_63"               ,        3,      61,     676,    "RAZ",  1,      1,      0,      0},
41538         {"MATCH_VALUE"                 ,        0,      16,     677,    "R/W",  0,      0,      0ull,   0ull},
41539         {"MATCH_TYPE"                  ,        16,     3,      677,    "R/W",  0,      0,      0ull,   0ull},
41540         {"RESERVED_19_19"              ,        19,     1,      677,    "RAZ",  1,      1,      0,      0},
41541         {"QOS"                         ,        20,     3,      677,    "R/W",  0,      0,      0ull,   0ull},
41542         {"RESERVED_23_23"              ,        23,     1,      677,    "RAZ",  1,      1,      0,      0},
41543         {"GRP"                         ,        24,     4,      677,    "R/W",  0,      0,      0ull,   0ull},
41544         {"RESERVED_28_31"              ,        28,     4,      677,    "RAZ",  1,      1,      0,      0},
41545         {"MASK"                        ,        32,     16,     677,    "R/W",  0,      0,      0ull,   0ull},
41546         {"RESERVED_48_63"              ,        48,     16,     677,    "RAZ",  1,      1,      0,      0},
41547         {"WORD"                        ,        0,      56,     678,    "R/W",  0,      0,      0ull,   0ull},
41548         {"RESERVED_56_63"              ,        56,     8,      678,    "RAZ",  1,      1,      0,      0},
41549         {"RST"                         ,        0,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
41550         {"RESERVED_1_63"               ,        1,      63,     679,    "RAZ",  1,      1,      0,      0},
41551         {"DRP_OCTS"                    ,        0,      32,     680,    "R/W",  0,      1,      0ull,   0},
41552         {"DRP_PKTS"                    ,        32,     32,     680,    "R/W",  0,      1,      0ull,   0},
41553         {"OCTS"                        ,        0,      48,     681,    "R/W",  0,      1,      0ull,   0},
41554         {"RESERVED_48_63"              ,        48,     16,     681,    "RAZ",  1,      1,      0,      0},
41555         {"RAW"                         ,        0,      32,     682,    "R/W",  0,      1,      0ull,   0},
41556         {"PKTS"                        ,        32,     32,     682,    "R/W",  0,      1,      0ull,   0},
41557         {"MCST"                        ,        0,      32,     683,    "R/W",  0,      1,      0ull,   0},
41558         {"BCST"                        ,        32,     32,     683,    "R/W",  0,      1,      0ull,   0},
41559         {"H64"                         ,        0,      32,     684,    "R/W",  0,      1,      0ull,   0},
41560         {"H65TO127"                    ,        32,     32,     684,    "R/W",  0,      1,      0ull,   0},
41561         {"H128TO255"                   ,        0,      32,     685,    "R/W",  0,      1,      0ull,   0},
41562         {"H256TO511"                   ,        32,     32,     685,    "R/W",  0,      1,      0ull,   0},
41563         {"H512TO1023"                  ,        0,      32,     686,    "R/W",  0,      1,      0ull,   0},
41564         {"H1024TO1518"                 ,        32,     32,     686,    "R/W",  0,      1,      0ull,   0},
41565         {"H1519"                       ,        0,      32,     687,    "R/W",  0,      1,      0ull,   0},
41566         {"FCS"                         ,        32,     32,     687,    "R/W",  0,      1,      0ull,   0},
41567         {"UNDERSZ"                     ,        0,      32,     688,    "R/W",  0,      1,      0ull,   0},
41568         {"FRAG"                        ,        32,     32,     688,    "R/W",  0,      1,      0ull,   0},
41569         {"OVERSZ"                      ,        0,      32,     689,    "R/W",  0,      1,      0ull,   0},
41570         {"JABBER"                      ,        32,     32,     689,    "R/W",  0,      1,      0ull,   0},
41571         {"RDCLR"                       ,        0,      1,      690,    "R/W",  0,      0,      1ull,   1ull},
41572         {"RESERVED_1_63"               ,        1,      63,     690,    "RAZ",  1,      1,      0,      0},
41573         {"ERRS"                        ,        0,      16,     691,    "R/W",  0,      1,      0ull,   0},
41574         {"RESERVED_16_63"              ,        16,     48,     691,    "RAZ",  1,      1,      0,      0},
41575         {"OCTS"                        ,        0,      48,     692,    "R/W",  0,      1,      0ull,   0},
41576         {"RESERVED_48_63"              ,        48,     16,     692,    "RAZ",  1,      1,      0,      0},
41577         {"PKTS"                        ,        0,      32,     693,    "R/W",  0,      1,      0ull,   0},
41578         {"RESERVED_32_63"              ,        32,     32,     693,    "RAZ",  1,      1,      0,      0},
41579         {"EN"                          ,        0,      8,      694,    "R/W",  0,      0,      0ull,   0ull},
41580         {"RESERVED_8_63"               ,        8,      56,     694,    "RAZ",  1,      1,      0,      0},
41581         {"MASK"                        ,        0,      16,     695,    "R/W",  0,      0,      0ull,   0ull},
41582         {"RESERVED_16_63"              ,        16,     48,     695,    "RAZ",  1,      1,      0,      0},
41583         {"SRC"                         ,        0,      16,     696,    "R/W",  0,      0,      0ull,   0ull},
41584         {"DST"                         ,        16,     16,     696,    "R/W",  0,      0,      0ull,   0ull},
41585         {"RESERVED_32_63"              ,        32,     32,     696,    "RAZ",  1,      1,      0,      0},
41586         {"ENTRY"                       ,        0,      62,     697,    "RO",   1,      1,      0,      0},
41587         {"RESERVED_62_62"              ,        62,     1,      697,    "RAZ",  1,      1,      0,      0},
41588         {"VAL"                         ,        63,     1,      697,    "RO",   1,      1,      0,      0},
41589         {"COUNT"                       ,        0,      32,     698,    "R/W1C",        1,      0,      0,      0ull},
41590         {"RESERVED_32_63"              ,        32,     32,     698,    "RAZ",  1,      1,      0,      0},
41591         {"COUNT"                       ,        0,      48,     699,    "R/W1C",        1,      0,      0,      0ull},
41592         {"RESERVED_48_63"              ,        48,     16,     699,    "RAZ",  1,      1,      0,      0},
41593         {"SIZE"                        ,        0,      16,     700,    "RO",   1,      0,      0,      0ull},
41594         {"SEGS"                        ,        16,     6,      700,    "RO",   1,      0,      0,      0ull},
41595         {"CMD"                         ,        22,     14,     700,    "RO",   1,      0,      0,      0ull},
41596         {"FAU"                         ,        36,     28,     700,    "RO",   1,      0,      0,      0ull},
41597         {"PTR"                         ,        0,      40,     701,    "RO",   1,      0,      0,      0ull},
41598         {"SIZE"                        ,        40,     16,     701,    "RO",   1,      0,      0,      0ull},
41599         {"POOL"                        ,        56,     3,      701,    "RO",   1,      0,      0,      0ull},
41600         {"BACK"                        ,        59,     4,      701,    "RO",   1,      0,      0,      0ull},
41601         {"I"                           ,        63,     1,      701,    "RO",   1,      0,      0,      0ull},
41602         {"PTRS2"                       ,        0,      17,     702,    "RO",   1,      0,      0,      0ull},
41603         {"RESERVED_17_31"              ,        17,     15,     702,    "RAZ",  1,      0,      0,      0ull},
41604         {"PTRS1"                       ,        32,     17,     702,    "RO",   1,      0,      0,      0ull},
41605         {"RESERVED_49_63"              ,        49,     15,     702,    "RAZ",  1,      0,      0,      0ull},
41606         {"MOD"                         ,        0,      3,      703,    "RO",   1,      0,      0,      0ull},
41607         {"CNT"                         ,        3,      13,     703,    "RO",   1,      0,      0,      0ull},
41608         {"CHK"                         ,        16,     1,      703,    "RO",   1,      0,      0,      0ull},
41609         {"LEN"                         ,        17,     1,      703,    "RO",   1,      0,      0,      0ull},
41610         {"SOP"                         ,        18,     1,      703,    "RO",   1,      0,      0,      0ull},
41611         {"UID"                         ,        19,     3,      703,    "RO",   1,      0,      0,      0ull},
41612         {"MAJ"                         ,        22,     1,      703,    "RO",   1,      0,      0,      0ull},
41613         {"RESERVED_23_63"              ,        23,     41,     703,    "RAZ",  1,      0,      0,      0ull},
41614         {"SIZE"                        ,        0,      16,     704,    "RO",   1,      0,      0,      0ull},
41615         {"SEGS"                        ,        16,     6,      704,    "RO",   1,      0,      0,      0ull},
41616         {"CMD"                         ,        22,     14,     704,    "RO",   1,      0,      0,      0ull},
41617         {"FAU"                         ,        36,     28,     704,    "RO",   1,      0,      0,      0ull},
41618         {"PTR"                         ,        0,      40,     705,    "RO",   1,      0,      0,      0ull},
41619         {"SIZE"                        ,        40,     16,     705,    "RO",   1,      0,      0,      0ull},
41620         {"POOL"                        ,        56,     3,      705,    "RO",   1,      0,      0,      0ull},
41621         {"BACK"                        ,        59,     4,      705,    "RO",   1,      0,      0,      0ull},
41622         {"I"                           ,        63,     1,      705,    "RO",   1,      0,      0,      0ull},
41623         {"DATA"                        ,        0,      64,     706,    "RO",   1,      0,      0,      0ull},
41624         {"PTR"                         ,        0,      40,     707,    "RO",   1,      0,      0,      0ull},
41625         {"SIZE"                        ,        40,     16,     707,    "RO",   1,      0,      0,      0ull},
41626         {"POOL"                        ,        56,     3,      707,    "RO",   1,      0,      0,      0ull},
41627         {"BACK"                        ,        59,     4,      707,    "RO",   1,      0,      0,      0ull},
41628         {"I"                           ,        63,     1,      707,    "RO",   1,      0,      0,      0ull},
41629         {"DATA"                        ,        0,      64,     708,    "RO",   1,      0,      0,      0ull},
41630         {"MAJOR"                       ,        0,      3,      709,    "RO",   1,      0,      0,      0ull},
41631         {"MINOR"                       ,        3,      2,      709,    "RO",   1,      0,      0,      0ull},
41632         {"WAIT"                        ,        5,      1,      709,    "RO",   1,      0,      0,      0ull},
41633         {"CHK_MODE"                    ,        6,      1,      709,    "RO",   1,      0,      0,      0ull},
41634         {"CHK_ONCE"                    ,        7,      1,      709,    "RO",   1,      0,      0,      0ull},
41635         {"INIT_DWRITE"                 ,        8,      1,      709,    "RO",   1,      0,      0,      0ull},
41636         {"DREAD_SOP"                   ,        9,      1,      709,    "RO",   1,      0,      0,      0ull},
41637         {"UID"                         ,        10,     2,      709,    "RO",   1,      0,      0,      0ull},
41638         {"CMND_OFF"                    ,        12,     6,      709,    "RO",   1,      0,      0,      0ull},
41639         {"CMND_SIZ"                    ,        18,     16,     709,    "RO",   1,      0,      0,      0ull},
41640         {"CMND_SEGS"                   ,        34,     6,      709,    "RO",   1,      0,      0,      0ull},
41641         {"CURR_OFF"                    ,        40,     16,     709,    "RO",   1,      0,      0,      0ull},
41642         {"CURR_SIZ"                    ,        56,     8,      709,    "RO",   1,      0,      0,      0ull},
41643         {"CURR_SIZ"                    ,        0,      8,      710,    "RO",   1,      0,      0,      0ull},
41644         {"CURR_PTR"                    ,        8,      40,     710,    "RO",   1,      0,      0,      0ull},
41645         {"NXT_INFLT"                   ,        48,     6,      710,    "RO",   1,      0,      0,      0ull},
41646         {"RESERVED_54_63"              ,        54,     10,     710,    "RAZ",  1,      0,      0,      0ull},
41647         {"QID_BASE"                    ,        0,      8,      711,    "RO",   1,      0,      0,      0ull},
41648         {"QID_OFF"                     ,        8,      4,      711,    "RO",   1,      0,      0,      0ull},
41649         {"QID_OFFMAX"                  ,        12,     4,      711,    "RO",   1,      0,      0,      0ull},
41650         {"QCB_RIDX"                    ,        16,     5,      711,    "RO",   1,      0,      0,      0ull},
41651         {"QOS"                         ,        21,     3,      711,    "RO",   1,      0,      0,      0ull},
41652         {"STATC"                       ,        24,     1,      711,    "RO",   1,      0,      0,      0ull},
41653         {"ACTIVE"                      ,        25,     1,      711,    "RO",   1,      0,      0,      0ull},
41654         {"PREEMPTED"                   ,        26,     1,      711,    "RO",   1,      0,      0,      0ull},
41655         {"PREEMPTEE"                   ,        27,     1,      711,    "RO",   1,      0,      0,      0ull},
41656         {"PREEMPTER"                   ,        28,     1,      711,    "RO",   1,      0,      0,      0ull},
41657         {"QID_OFFTHS"                  ,        29,     4,      711,    "RO",   1,      0,      0,      0ull},
41658         {"QID_OFFRES"                  ,        33,     4,      711,    "RO",   1,      0,      0,      0ull},
41659         {"RESERVED_37_63"              ,        37,     27,     711,    "RAZ",  1,      0,      0,      0ull},
41660         {"QCB_RIDX"                    ,        0,      6,      712,    "RO",   1,      0,      0,      0ull},
41661         {"QCB_WIDX"                    ,        6,      6,      712,    "RO",   1,      0,      0,      0ull},
41662         {"BUF_PTR"                     ,        12,     33,     712,    "RO",   1,      0,      0,      0ull},
41663         {"BUF_SIZ"                     ,        45,     13,     712,    "RO",   1,      0,      0,      0ull},
41664         {"TAIL"                        ,        58,     1,      712,    "RO",   1,      0,      0,      0ull},
41665         {"QOS"                         ,        59,     5,      712,    "RO",   1,      0,      0,      0ull},
41666         {"QOS"                         ,        0,      3,      713,    "RO",   1,      0,      0,      0ull},
41667         {"STATIC_Q"                    ,        3,      1,      713,    "RO",   1,      0,      0,      0ull},
41668         {"S_TAIL"                      ,        4,      1,      713,    "RO",   1,      0,      0,      0ull},
41669         {"STATIC_P"                    ,        5,      1,      713,    "RO",   1,      0,      0,      0ull},
41670         {"PREEMPTEE"                   ,        6,      1,      713,    "RO",   1,      0,      0,      0ull},
41671         {"RESERVED_7_7"                ,        7,      1,      713,    "RAZ",  1,      0,      0,      0ull},
41672         {"DOORBELL"                    ,        8,      20,     713,    "RO",   1,      0,      0,      0ull},
41673         {"PREEMPTER"                   ,        28,     1,      713,    "RO",   1,      0,      0,      0ull},
41674         {"RESERVED_29_63"              ,        29,     35,     713,    "RAZ",  1,      0,      0,      0ull},
41675         {"PTRS3"                       ,        0,      17,     714,    "RO",   1,      0,      0,      0ull},
41676         {"RESERVED_17_31"              ,        17,     15,     714,    "RAZ",  1,      0,      0,      0ull},
41677         {"PTRS0"                       ,        32,     17,     714,    "RO",   1,      0,      0,      0ull},
41678         {"RESERVED_49_63"              ,        49,     15,     714,    "RAZ",  1,      0,      0,      0ull},
41679         {"PID"                         ,        0,      6,      715,    "R/W",  1,      0,      0,      0ull},
41680         {"EID"                         ,        6,      4,      715,    "R/W",  1,      0,      0,      0ull},
41681         {"BP_PORT"                     ,        10,     6,      715,    "R/W",  1,      0,      0,      0ull},
41682         {"RESERVED_16_52"              ,        16,     37,     715,    "RAZ",  1,      0,      0,      0ull},
41683         {"QOS_MASK"                    ,        53,     8,      715,    "R/W",  1,      0,      0,      0ull},
41684         {"STATIC_P"                    ,        61,     1,      715,    "R/W",  1,      0,      0,      0ull},
41685         {"RESERVED_62_63"              ,        62,     2,      715,    "RAZ",  1,      0,      0,      0ull},
41686         {"PID"                         ,        0,      6,      716,    "R/W",  1,      0,      0,      0ull},
41687         {"EID"                         ,        6,      4,      716,    "R/W",  1,      0,      0,      0ull},
41688         {"RESERVED_10_52"              ,        10,     43,     716,    "RAZ",  1,      0,      0,      0ull},
41689         {"QOS_MASK"                    ,        53,     8,      716,    "R/W",  1,      0,      0,      0ull},
41690         {"RESERVED_61_63"              ,        61,     3,      716,    "RAZ",  1,      0,      0,      0ull},
41691         {"PID"                         ,        0,      6,      717,    "R/W",  1,      0,      0,      0ull},
41692         {"RESERVED_6_7"                ,        6,      2,      717,    "RAZ",  1,      0,      0,      0ull},
41693         {"RATE_PKT"                    ,        8,      24,     717,    "R/W",  1,      0,      0,      0ull},
41694         {"RATE_WORD"                   ,        32,     19,     717,    "R/W",  1,      0,      0,      0ull},
41695         {"RESERVED_51_63"              ,        51,     13,     717,    "RAZ",  1,      0,      0,      0ull},
41696         {"PID"                         ,        0,      6,      718,    "R/W",  1,      0,      0,      0ull},
41697         {"RESERVED_6_7"                ,        6,      2,      718,    "RAZ",  1,      0,      0,      0ull},
41698         {"RATE_LIM"                    ,        8,      24,     718,    "R/W",  1,      0,      0,      0ull},
41699         {"RESERVED_32_63"              ,        32,     32,     718,    "RAZ",  1,      0,      0,      0ull},
41700         {"QUEUE"                       ,        0,      7,      719,    "R/W",  1,      0,      0,      0ull},
41701         {"PORT"                        ,        7,      6,      719,    "WR0",  1,      0,      0,      0ull},
41702         {"INDEX"                       ,        13,     3,      719,    "WR0",  1,      0,      0,      0ull},
41703         {"TAIL"                        ,        16,     1,      719,    "R/W",  1,      0,      0,      0ull},
41704         {"BUF_PTR"                     ,        17,     36,     719,    "R/W",  1,      0,      0,      0ull},
41705         {"QOS_MASK"                    ,        53,     8,      719,    "R/W",  1,      0,      0,      0ull},
41706         {"STATIC_Q"                    ,        61,     1,      719,    "R/W",  1,      0,      0,      0ull},
41707         {"STATIC_P"                    ,        62,     1,      719,    "R/W",  1,      0,      0,      0ull},
41708         {"S_TAIL"                      ,        63,     1,      719,    "R/W",  1,      0,      0,      0ull},
41709         {"QID"                         ,        0,      7,      720,    "R/W",  1,      0,      0,      0ull},
41710         {"PID"                         ,        7,      6,      720,    "WR0",  1,      0,      0,      0ull},
41711         {"RESERVED_13_52"              ,        13,     40,     720,    "RAZ",  1,      0,      0,      0ull},
41712         {"QOS_MASK"                    ,        53,     8,      720,    "R/W",  1,      0,      0,      0ull},
41713         {"RESERVED_61_63"              ,        61,     3,      720,    "RAZ",  1,      0,      0,      0ull},
41714         {"DAT_PTR"                     ,        0,      4,      721,    "RO",   1,      0,      0,      0ull},
41715         {"DAT_DAT"                     ,        4,      2,      721,    "RO",   1,      0,      0,      0ull},
41716         {"PRT_CTL"                     ,        6,      2,      721,    "RO",   1,      0,      0,      0ull},
41717         {"PRT_QSB"                     ,        8,      3,      721,    "RO",   1,      0,      0,      0ull},
41718         {"PRT_QCB"                     ,        11,     2,      721,    "RO",   1,      0,      0,      0ull},
41719         {"NCB_INB"                     ,        13,     2,      721,    "RO",   1,      0,      0,      0ull},
41720         {"PRT_PSB"                     ,        15,     8,      721,    "RO",   1,      0,      0,      0ull},
41721         {"PRT_NXT"                     ,        23,     1,      721,    "RO",   1,      0,      0,      0ull},
41722         {"PRT_CHK"                     ,        24,     3,      721,    "RO",   1,      0,      0,      0ull},
41723         {"OUT_WIF"                     ,        27,     1,      721,    "RO",   1,      0,      0,      0ull},
41724         {"OUT_STA"                     ,        28,     1,      721,    "RO",   1,      0,      0,      0ull},
41725         {"OUT_CTL"                     ,        29,     3,      721,    "RO",   1,      0,      0,      0ull},
41726         {"OUT_DAT"                     ,        32,     1,      721,    "RO",   1,      0,      0,      0ull},
41727         {"IOB"                         ,        33,     1,      721,    "RO",   1,      0,      0,      0ull},
41728         {"CSR"                         ,        34,     1,      721,    "RO",   1,      0,      0,      0ull},
41729         {"RESERVED_35_63"              ,        35,     29,     721,    "RAZ",  1,      0,      0,      0ull},
41730         {"SIZE"                        ,        0,      13,     722,    "R/W",  0,      0,      0ull,   0ull},
41731         {"RESERVED_13_19"              ,        13,     7,      722,    "RAZ",  0,      0,      0ull,   0ull},
41732         {"POOL"                        ,        20,     3,      722,    "R/W",  0,      0,      0ull,   0ull},
41733         {"RESERVED_23_63"              ,        23,     41,     722,    "RAZ",  1,      0,      0,      0ull},
41734         {"ASSERTS"                     ,        0,      64,     723,    "RO",   0,      0,      0ull,   0ull},
41735         {"ASSERTS"                     ,        0,      64,     724,    "RO",   0,      0,      0ull,   0ull},
41736         {"ASSERTS"                     ,        0,      64,     725,    "RO",   0,      0,      0ull,   0ull},
41737         {"ASSERTS"                     ,        0,      64,     726,    "RO",   0,      0,      0ull,   0ull},
41738         {"ENGINE0"                     ,        0,      4,      727,    "R/W",  0,      0,      4ull,   4ull},
41739         {"ENGINE1"                     ,        4,      4,      727,    "R/W",  0,      0,      4ull,   4ull},
41740         {"ENGINE2"                     ,        8,      4,      727,    "R/W",  0,      0,      4ull,   4ull},
41741         {"ENGINE3"                     ,        12,     4,      727,    "R/W",  0,      0,      4ull,   4ull},
41742         {"ENGINE4"                     ,        16,     4,      727,    "R/W",  0,      0,      4ull,   4ull},
41743         {"ENGINE5"                     ,        20,     4,      727,    "R/W",  0,      0,      4ull,   4ull},
41744         {"ENGINE6"                     ,        24,     4,      727,    "R/W",  0,      0,      4ull,   4ull},
41745         {"ENGINE7"                     ,        28,     4,      727,    "R/W",  0,      0,      4ull,   4ull},
41746         {"ENGINE8"                     ,        32,     4,      727,    "R/W",  0,      0,      4ull,   4ull},
41747         {"ENGINE9"                     ,        36,     4,      727,    "R/W",  0,      0,      4ull,   4ull},
41748         {"RESERVED_40_63"              ,        40,     24,     727,    "RAZ",  1,      0,      0,      0ull},
41749         {"MASK"                        ,        0,      10,     728,    "R/W",  0,      0,      0ull,   0ull},
41750         {"RESERVED_10_63"              ,        10,     54,     728,    "RAZ",  1,      0,      0,      0ull},
41751         {"PARITY"                      ,        0,      1,      729,    "R/W1C",        0,      0,      0ull,   0ull},
41752         {"DOORBELL"                    ,        1,      1,      729,    "R/W1C",        0,      0,      0ull,   0ull},
41753         {"CURRZERO"                    ,        2,      1,      729,    "R/W1C",        0,      0,      0ull,   0ull},
41754         {"RESERVED_3_63"               ,        3,      61,     729,    "RAZ",  1,      0,      0,      0ull},
41755         {"ENA_PKO"                     ,        0,      1,      730,    "R/W",  0,      0,      0ull,   0ull},
41756         {"ENA_DWB"                     ,        1,      1,      730,    "R/W",  0,      0,      0ull,   0ull},
41757         {"STORE_BE"                    ,        2,      1,      730,    "R/W",  0,      0,      0ull,   0ull},
41758         {"RESET"                       ,        3,      1,      730,    "RAZ",  0,      0,      0ull,   0ull},
41759         {"RESERVED_4_63"               ,        4,      60,     730,    "RAZ",  1,      0,      0,      0ull},
41760         {"MODE0"                       ,        0,      3,      731,    "R/W",  0,      0,      2ull,   2ull},
41761         {"MODE1"                       ,        3,      3,      731,    "R/W",  0,      0,      2ull,   2ull},
41762         {"RESERVED_6_63"               ,        6,      58,     731,    "RAZ",  1,      0,      0,      0ull},
41763         {"PARITY"                      ,        0,      1,      732,    "R/W",  0,      0,      0ull,   0ull},
41764         {"DOORBELL"                    ,        1,      1,      732,    "R/W",  0,      0,      0ull,   0ull},
41765         {"CURRZERO"                    ,        2,      1,      732,    "R/W",  0,      0,      0ull,   0ull},
41766         {"RESERVED_3_63"               ,        3,      61,     732,    "RAZ",  1,      0,      0,      0ull},
41767         {"MODE"                        ,        0,      2,      733,    "R/W",  0,      0,      0ull,   0ull},
41768         {"RESERVED_2_63"               ,        2,      62,     733,    "RAZ",  1,      0,      0,      0ull},
41769         {"QID7"                        ,        0,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
41770         {"IDX3"                        ,        1,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
41771         {"RESERVED_2_63"               ,        2,      62,     734,    "RAZ",  1,      0,      0,      0ull},
41772         {"INDEX"                       ,        0,      8,      735,    "R/W",  0,      0,      0ull,   0ull},
41773         {"INC"                         ,        8,      8,      735,    "R/W",  0,      0,      0ull,   0ull},
41774         {"RESERVED_16_63"              ,        16,     48,     735,    "RAZ",  1,      0,      0,      0ull},
41775         {"ADR0"                        ,        0,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41776         {"ADR1"                        ,        1,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41777         {"PEND0"                       ,        2,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41778         {"PEND1"                       ,        3,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41779         {"NBR0"                        ,        4,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41780         {"NBR1"                        ,        5,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41781         {"FIDX"                        ,        6,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41782         {"INDEX"                       ,        7,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41783         {"NBT"                         ,        8,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41784         {"CAM"                         ,        9,      1,      736,    "RO",   0,      0,      0ull,   0ull},
41785         {"RESERVED_10_15"              ,        10,     6,      736,    "RAZ",  1,      1,      0,      0},
41786         {"PP"                          ,        16,     12,     736,    "RO",   0,      0,      0ull,   0ull},
41787         {"RESERVED_28_63"              ,        28,     36,     736,    "RAZ",  1,      1,      0,      0},
41788         {"DS_PC"                       ,        0,      32,     737,    "R/W1C",        0,      1,      0ull,   0},
41789         {"RESERVED_32_63"              ,        32,     32,     737,    "RAZ",  1,      1,      0,      0},
41790         {"SBE"                         ,        0,      1,      738,    "R/W1C",        0,      0,      0ull,   0ull},
41791         {"DBE"                         ,        1,      1,      738,    "R/W1C",        0,      0,      0ull,   0ull},
41792         {"SBE_IE"                      ,        2,      1,      738,    "R/W",  0,      1,      0ull,   0},
41793         {"DBE_IE"                      ,        3,      1,      738,    "R/W",  0,      1,      0ull,   0},
41794         {"SYN"                         ,        4,      5,      738,    "RO",   1,      1,      0,      0},
41795         {"RESERVED_9_11"               ,        9,      3,      738,    "RAZ",  1,      1,      0,      0},
41796         {"RPE"                         ,        12,     1,      738,    "R/W1C",        0,      0,      0ull,   0ull},
41797         {"RPE_IE"                      ,        13,     1,      738,    "R/W",  0,      1,      0ull,   0},
41798         {"RESERVED_14_15"              ,        14,     2,      738,    "RAZ",  1,      1,      0,      0},
41799         {"IOP"                         ,        16,     13,     738,    "R/W1C",        0,      0,      0ull,   0ull},
41800         {"RESERVED_29_31"              ,        29,     3,      738,    "RAZ",  1,      1,      0,      0},
41801         {"IOP_IE"                      ,        32,     13,     738,    "R/W",  0,      1,      0ull,   0},
41802         {"RESERVED_45_63"              ,        45,     19,     738,    "RAZ",  1,      1,      0,      0},
41803         {"NBR_THR"                     ,        0,      5,      739,    "R/W",  0,      0,      2ull,   2ull},
41804         {"PFR_DIS"                     ,        5,      1,      739,    "R/W",  0,      0,      0ull,   0ull},
41805         {"RESERVED_6_63"               ,        6,      58,     739,    "RAZ",  1,      1,      0,      0},
41806         {"IQ_CNT"                      ,        0,      32,     740,    "RO",   0,      1,      0ull,   0},
41807         {"RESERVED_32_63"              ,        32,     32,     740,    "RAZ",  1,      1,      0,      0},
41808         {"IQ_CNT"                      ,        0,      32,     741,    "RO",   0,      1,      0ull,   0},
41809         {"RESERVED_32_63"              ,        32,     32,     741,    "RAZ",  1,      1,      0,      0},
41810         {"IQ_INT"                      ,        0,      8,      742,    "R/W1C",        0,      1,      0ull,   0},
41811         {"RESERVED_8_63"               ,        8,      56,     742,    "RAZ",  1,      1,      0,      0},
41812         {"INT_EN"                      ,        0,      8,      743,    "R/W",  0,      1,      0ull,   0},
41813         {"RESERVED_8_63"               ,        8,      56,     743,    "RAZ",  1,      1,      0,      0},
41814         {"IQ_THR"                      ,        0,      32,     744,    "R/W",  0,      1,      4294967295ull,  0},
41815         {"RESERVED_32_63"              ,        32,     32,     744,    "RAZ",  1,      1,      0,      0},
41816         {"NOS_CNT"                     ,        0,      12,     745,    "RO",   0,      1,      0ull,   0},
41817         {"RESERVED_12_63"              ,        12,     52,     745,    "RAZ",  1,      1,      0,      0},
41818         {"NW_TIM"                      ,        0,      10,     746,    "R/W",  0,      0,      0ull,   1023ull},
41819         {"RESERVED_10_63"              ,        10,     54,     746,    "RAZ",  1,      1,      0,      0},
41820         {"RST_MSK"                     ,        0,      8,      747,    "R/W",  0,      1,      0ull,   0},
41821         {"RESERVED_8_63"               ,        8,      56,     747,    "RAZ",  1,      1,      0,      0},
41822         {"GRP_MSK"                     ,        0,      16,     748,    "R/W",  0,      0,      65535ull,       65535ull},
41823         {"QOS0_PRI"                    ,        16,     4,      748,    "R/W",  0,      1,      0ull,   0},
41824         {"QOS1_PRI"                    ,        20,     4,      748,    "R/W",  0,      1,      0ull,   0},
41825         {"QOS2_PRI"                    ,        24,     4,      748,    "R/W",  0,      1,      0ull,   0},
41826         {"QOS3_PRI"                    ,        28,     4,      748,    "R/W",  0,      1,      0ull,   0},
41827         {"QOS4_PRI"                    ,        32,     4,      748,    "R/W",  0,      1,      0ull,   0},
41828         {"QOS5_PRI"                    ,        36,     4,      748,    "R/W",  0,      1,      0ull,   0},
41829         {"QOS6_PRI"                    ,        40,     4,      748,    "R/W",  0,      1,      0ull,   0},
41830         {"QOS7_PRI"                    ,        44,     4,      748,    "R/W",  0,      1,      0ull,   0},
41831         {"RESERVED_48_63"              ,        48,     16,     748,    "RAZ",  1,      1,      0,      0},
41832         {"RND"                         ,        0,      8,      749,    "R/W",  0,      1,      255ull, 0},
41833         {"RND_P1"                      ,        8,      8,      749,    "R/W",  0,      1,      255ull, 0},
41834         {"RND_P2"                      ,        16,     8,      749,    "R/W",  0,      1,      255ull, 0},
41835         {"RND_P3"                      ,        24,     8,      749,    "R/W",  0,      1,      255ull, 0},
41836         {"RESERVED_32_63"              ,        32,     32,     749,    "RAZ",  1,      1,      0,      0},
41837         {"MIN_THR"                     ,        0,      11,     750,    "R/W",  0,      1,      0ull,   0},
41838         {"RESERVED_11_11"              ,        11,     1,      750,    "RAZ",  1,      1,      0,      0},
41839         {"MAX_THR"                     ,        12,     11,     750,    "R/W",  0,      1,      2047ull,        0},
41840         {"RESERVED_23_23"              ,        23,     1,      750,    "RAZ",  1,      1,      0,      0},
41841         {"FREE_CNT"                    ,        24,     12,     750,    "RO",   0,      1,      2027ull,        0},
41842         {"BUF_CNT"                     ,        36,     12,     750,    "RO",   0,      1,      0ull,   0},
41843         {"DES_CNT"                     ,        48,     12,     750,    "RO",   0,      1,      0ull,   0},
41844         {"RESERVED_60_63"              ,        60,     4,      750,    "RAZ",  1,      1,      0,      0},
41845         {"TS_PC"                       ,        0,      32,     751,    "R/W1C",        0,      1,      0ull,   0},
41846         {"RESERVED_32_63"              ,        32,     32,     751,    "RAZ",  1,      1,      0,      0},
41847         {"WA_PC"                       ,        0,      32,     752,    "R/W1C",        0,      1,      0ull,   0},
41848         {"RESERVED_32_63"              ,        32,     32,     752,    "RAZ",  1,      1,      0,      0},
41849         {"WA_PC"                       ,        0,      32,     753,    "R/W1C",        0,      1,      0ull,   0},
41850         {"RESERVED_32_63"              ,        32,     32,     753,    "RAZ",  1,      1,      0,      0},
41851         {"WQ_INT"                      ,        0,      16,     754,    "R/W1C",        0,      1,      0ull,   0},
41852         {"IQ_DIS"                      ,        16,     16,     754,    "R/W1", 0,      1,      0ull,   0},
41853         {"RESERVED_32_63"              ,        32,     32,     754,    "RAZ",  1,      1,      0,      0},
41854         {"IQ_CNT"                      ,        0,      12,     755,    "RO",   0,      1,      0ull,   0},
41855         {"DS_CNT"                      ,        12,     12,     755,    "RO",   0,      1,      0ull,   0},
41856         {"TC_CNT"                      ,        24,     4,      755,    "RO",   0,      1,      0ull,   0},
41857         {"RESERVED_28_63"              ,        28,     36,     755,    "RAZ",  1,      1,      0,      0},
41858         {"RESERVED_0_7"                ,        0,      8,      756,    "RAZ",  1,      1,      0,      0},
41859         {"PC_THR"                      ,        8,      20,     756,    "R/W",  0,      1,      0ull,   0},
41860         {"RESERVED_28_31"              ,        28,     4,      756,    "RAZ",  1,      1,      0,      0},
41861         {"PC"                          ,        32,     28,     756,    "RO",   0,      1,      0ull,   0},
41862         {"RESERVED_60_63"              ,        60,     4,      756,    "RAZ",  1,      1,      0,      0},
41863         {"IQ_THR"                      ,        0,      11,     757,    "R/W",  0,      1,      0ull,   0},
41864         {"RESERVED_11_11"              ,        11,     1,      757,    "RAZ",  1,      1,      0,      0},
41865         {"DS_THR"                      ,        12,     11,     757,    "R/W",  0,      1,      0ull,   0},
41866         {"RESERVED_23_23"              ,        23,     1,      757,    "RAZ",  1,      1,      0,      0},
41867         {"TC_THR"                      ,        24,     4,      757,    "R/W",  0,      1,      0ull,   0},
41868         {"TC_EN"                       ,        28,     1,      757,    "R/W",  0,      1,      0ull,   0},
41869         {"RESERVED_29_63"              ,        29,     35,     757,    "RAZ",  1,      1,      0,      0},
41870         {"WS_PC"                       ,        0,      32,     758,    "R/W1C",        0,      1,      0ull,   0},
41871         {"RESERVED_32_63"              ,        32,     32,     758,    "RAZ",  1,      1,      0,      0},
41872         {"IWORD"                       ,        0,      64,     759,    "RO",   1,      1,      0,      0},
41873         {"P_DAT"                       ,        0,      64,     760,    "RO",   1,      1,      0,      0},
41874         {"Q_DAT"                       ,        0,      64,     761,    "RO",   1,      1,      0,      0},
41875         {"DAT"                         ,        0,      2,      762,    "RO",   1,      0,      0,      0ull},
41876         {"NCB_INB"                     ,        2,      2,      762,    "RO",   1,      0,      0,      0ull},
41877         {"NCB_OUB"                     ,        4,      1,      762,    "RO",   1,      0,      0,      0ull},
41878         {"STA"                         ,        5,      1,      762,    "RO",   1,      0,      0,      0ull},
41879         {"RESERVED_6_63"               ,        6,      58,     762,    "RAZ",  0,      0,      0ull,   0ull},
41880         {"PTR"                         ,        0,      33,     763,    "R/W",  0,      1,      0ull,   0},
41881         {"SIZE"                        ,        33,     13,     763,    "R/W",  0,      1,      0ull,   0},
41882         {"POOL"                        ,        46,     3,      763,    "R/W",  0,      1,      0ull,   0},
41883         {"DWB"                         ,        49,     9,      763,    "R/W",  0,      1,      0ull,   0},
41884         {"RESERVED_58_63"              ,        58,     6,      763,    "RAZ",  0,      0,      0ull,   0ull},
41885         {"RESET"                       ,        0,      1,      764,    "RAZ",  0,      0,      0ull,   0ull},
41886         {"STORE_LE"                    ,        1,      1,      764,    "R/W",  0,      0,      0ull,   0ull},
41887         {"MAX_READ"                    ,        2,      4,      764,    "R/W",  0,      0,      8ull,   8ull},
41888         {"RESERVED_6_63"               ,        6,      58,     764,    "RAZ",  0,      0,      0ull,   0ull},
41889         {"STATE"                       ,        0,      5,      765,    "RO",   1,      1,      0,      0},
41890         {"COMMIT"                      ,        5,      1,      765,    "RO",   1,      1,      0,      0},
41891         {"OWORDPV"                     ,        6,      1,      765,    "RO",   1,      1,      0,      0},
41892         {"OWORDQV"                     ,        7,      1,      765,    "RO",   1,      1,      0,      0},
41893         {"IWIDX"                       ,        8,      6,      765,    "RO",   1,      1,      0,      0},
41894         {"RESERVED_14_15"              ,        14,     2,      765,    "RAZ",  1,      1,      0,      0},
41895         {"IRIDX"                       ,        16,     6,      765,    "RO",   1,      1,      0,      0},
41896         {"RESERVED_22_31"              ,        22,     10,     765,    "RAZ",  1,      1,      0,      0},
41897         {"LOOP"                        ,        32,     25,     765,    "RO",   1,      1,      0,      0},
41898         {"RESERVED_57_63"              ,        57,     7,      765,    "RAZ",  1,      1,      0,      0},
41899         {"CWORD"                       ,        0,      64,     766,    "RO",   1,      1,      0,      0},
41900         {"PTR"                         ,        0,      40,     767,    "RO",   1,      1,      0,      0},
41901         {"SIZE"                        ,        40,     16,     767,    "RO",   1,      1,      0,      0},
41902         {"FLAGS"                       ,        56,     8,      767,    "RO",   1,      1,      0,      0},
41903         {"INDEX"                       ,        0,      8,      768,    "RO",   1,      1,      0,      0},
41904         {"SOD"                         ,        8,      1,      768,    "RO",   1,      1,      0,      0},
41905         {"EOD"                         ,        9,      1,      768,    "RO",   1,      1,      0,      0},
41906         {"WC"                          ,        10,     1,      768,    "RO",   1,      1,      0,      0},
41907         {"P"                           ,        11,     1,      768,    "RO",   1,      1,      0,      0},
41908         {"Q"                           ,        12,     1,      768,    "RO",   1,      1,      0,      0},
41909         {"RESERVED_13_63"              ,        13,     51,     768,    "RAZ",  0,      0,      0ull,   0ull},
41910         {"ASSERTS"                     ,        0,      15,     769,    "RO",   1,      1,      0,      0},
41911         {"RESERVED_15_63"              ,        15,     49,     769,    "RAZ",  0,      0,      0ull,   0ull},
41912         {"OWORDP"                      ,        0,      64,     770,    "RO",   1,      1,      0,      0},
41913         {"OWORDQ"                      ,        0,      64,     771,    "RO",   1,      1,      0,      0},
41914         {"RWORD"                       ,        0,      64,     772,    "RO",   1,      1,      0,      0},
41915         {"N0CREDS"                     ,        0,      4,      773,    "RO",   0,      0,      8ull,   0ull},
41916         {"N1CREDS"                     ,        4,      4,      773,    "RO",   0,      0,      8ull,   0ull},
41917         {"POWCREDS"                    ,        8,      2,      773,    "RO",   0,      0,      2ull,   0ull},
41918         {"RESERVED_10_11"              ,        10,     2,      773,    "RAZ",  0,      0,      0ull,   0ull},
41919         {"FPACREDS"                    ,        12,     2,      773,    "RO",   0,      0,      1ull,   0ull},
41920         {"WCCREDS"                     ,        14,     2,      773,    "RO",   0,      0,      0ull,   0ull},
41921         {"NIWIDX0"                     ,        16,     4,      773,    "RO",   1,      1,      0,      0},
41922         {"NIRIDX0"                     ,        20,     4,      773,    "RO",   1,      1,      0,      0},
41923         {"NIWIDX1"                     ,        24,     4,      773,    "RO",   1,      1,      0,      0},
41924         {"NIRIDX1"                     ,        28,     4,      773,    "RO",   1,      1,      0,      0},
41925         {"NIRVAL6"                     ,        32,     5,      773,    "RO",   1,      1,      0,      0},
41926         {"NIRARB6"                     ,        37,     1,      773,    "RO",   1,      1,      0,      0},
41927         {"NIRQUE6"                     ,        38,     2,      773,    "RO",   1,      1,      0,      0},
41928         {"NIROPC6"                     ,        40,     3,      773,    "RO",   1,      1,      0,      0},
41929         {"NIRVAL7"                     ,        43,     5,      773,    "RO",   1,      1,      0,      0},
41930         {"NIRQUE7"                     ,        48,     2,      773,    "RO",   1,      1,      0,      0},
41931         {"NIROPC7"                     ,        50,     3,      773,    "RO",   1,      1,      0,      0},
41932         {"RESERVED_53_63"              ,        53,     11,     773,    "RAZ",  0,      0,      0ull,   0ull},
41933         {"PTR"                         ,        0,      40,     774,    "RO",   1,      1,      0,      0},
41934         {"SIZE"                        ,        40,     16,     774,    "RO",   1,      1,      0,      0},
41935         {"CNT"                         ,        56,     8,      774,    "RO",   1,      1,      0,      0},
41936         {"CNT"                         ,        0,      15,     775,    "RO",   1,      1,      0,      0},
41937         {"RESERVED_15_63"              ,        15,     49,     775,    "RAZ",  0,      0,      0ull,   0ull},
41938         {"PTR"                         ,        0,      40,     776,    "RO",   1,      1,      0,      0},
41939         {"SIZE"                        ,        40,     16,     776,    "RO",   1,      1,      0,      0},
41940         {"FLAGS"                       ,        56,     8,      776,    "RO",   1,      1,      0,      0},
41941         {"INDEX"                       ,        0,      8,      777,    "RO",   1,      1,      0,      0},
41942         {"MUL"                         ,        8,      8,      777,    "RO",   1,      1,      0,      0},
41943         {"P"                           ,        16,     1,      777,    "RO",   1,      1,      0,      0},
41944         {"Q"                           ,        17,     1,      777,    "RO",   1,      1,      0,      0},
41945         {"INI"                         ,        18,     1,      777,    "RO",   1,      1,      0,      0},
41946         {"EOD"                         ,        19,     1,      777,    "RO",   1,      1,      0,      0},
41947         {"RESERVED_20_63"              ,        20,     44,     777,    "RAZ",  0,      0,      0ull,   0ull},
41948         {"DOORBELL"                    ,        0,      1,      778,    "R/W1C",        0,      0,      0ull,   0ull},
41949         {"RESERVED_1_63"               ,        1,      63,     778,    "RAZ",  0,      0,      0ull,   0ull},
41950         {"DOORBELL"                    ,        0,      1,      779,    "R/W",  0,      0,      0ull,   0ull},
41951         {"RESERVED_1_63"               ,        1,      63,     779,    "RAZ",  0,      0,      0ull,   0ull},
41952         {"COEFFS"                      ,        0,      8,      780,    "R/W",  0,      0,      29ull,  29ull},
41953         {"RESERVED_8_63"               ,        8,      56,     780,    "RAZ",  0,      0,      0ull,   0ull},
41954         {"INDEX"                       ,        0,      16,     781,    "R/W",  0,      0,      0ull,   0ull},
41955         {"INC"                         ,        16,     16,     781,    "R/W",  0,      0,      0ull,   0ull},
41956         {"RESERVED_32_63"              ,        32,     32,     781,    "RAZ",  0,      0,      0ull,   0ull},
41957         {"MEM"                         ,        0,      1,      782,    "RO",   0,      0,      0ull,   0ull},
41958         {"RRC"                         ,        1,      1,      782,    "RO",   0,      0,      0ull,   0ull},
41959         {"RESERVED_2_63"               ,        2,      62,     782,    "RAZ",  1,      1,      0,      0},
41960         {"ENT_EN"                      ,        0,      1,      783,    "R/W",  0,      0,      0ull,   0ull},
41961         {"RNG_EN"                      ,        1,      1,      783,    "R/W",  0,      0,      0ull,   0ull},
41962         {"RNM_RST"                     ,        2,      1,      783,    "R/W",  0,      0,      0ull,   0ull},
41963         {"RNG_RST"                     ,        3,      1,      783,    "R/W",  0,      0,      0ull,   0ull},
41964         {"EXP_ENT"                     ,        4,      1,      783,    "R/W",  0,      0,      0ull,   0ull},
41965         {"ENT_SEL"                     ,        5,      4,      783,    "R/W",  0,      0,      0ull,   0ull},
41966         {"RESERVED_9_63"               ,        9,      55,     783,    "RAZ",  1,      1,      0,      0},
41967         {"PHASE"                       ,        0,      8,      784,    "R/W",  0,      0,      100ull, 100ull},
41968         {"SAMPLE"                      ,        8,      4,      784,    "R/W",  0,      0,      2ull,   2ull},
41969         {"PREAMBLE"                    ,        12,     1,      784,    "R/W",  0,      0,      1ull,   1ull},
41970         {"CLK_IDLE"                    ,        13,     1,      784,    "R/W",  0,      0,      0ull,   0ull},
41971         {"RESERVED_14_14"              ,        14,     1,      784,    "RAZ",  1,      1,      0,      0},
41972         {"SAMPLE_MODE"                 ,        15,     1,      784,    "RAZ",  0,      0,      0ull,   0ull},
41973         {"SAMPLE_HI"                   ,        16,     5,      784,    "R/W",  0,      0,      0ull,   0ull},
41974         {"RESERVED_21_23"              ,        21,     3,      784,    "RAZ",  1,      1,      0,      0},
41975         {"MODE"                        ,        24,     1,      784,    "R/W",  0,      0,      0ull,   0ull},
41976         {"RESERVED_25_63"              ,        25,     39,     784,    "RAZ",  1,      1,      0,      0},
41977         {"REG_ADR"                     ,        0,      5,      785,    "R/W",  0,      1,      0ull,   0},
41978         {"RESERVED_5_7"                ,        5,      3,      785,    "RAZ",  1,      1,      0,      0},
41979         {"PHY_ADR"                     ,        8,      5,      785,    "R/W",  0,      1,      0ull,   0},
41980         {"RESERVED_13_15"              ,        13,     3,      785,    "RAZ",  1,      1,      0,      0},
41981         {"PHY_OP"                      ,        16,     2,      785,    "R/W",  0,      1,      0ull,   0},
41982         {"RESERVED_18_63"              ,        18,     46,     785,    "RAZ",  1,      1,      0,      0},
41983         {"EN"                          ,        0,      1,      786,    "R/W",  0,      0,      0ull,   1ull},
41984         {"RESERVED_1_63"               ,        1,      63,     786,    "RAZ",  1,      1,      0,      0},
41985         {"DAT"                         ,        0,      16,     787,    "RO",   0,      1,      0ull,   0},
41986         {"VAL"                         ,        16,     1,      787,    "RO",   0,      1,      0ull,   0},
41987         {"PENDING"                     ,        17,     1,      787,    "RO",   0,      1,      0ull,   0},
41988         {"RESERVED_18_63"              ,        18,     46,     787,    "RAZ",  1,      1,      0,      0},
41989         {"DAT"                         ,        0,      16,     788,    "R/W",  0,      1,      0ull,   0},
41990         {"VAL"                         ,        16,     1,      788,    "RO",   0,      1,      0ull,   0},
41991         {"PENDING"                     ,        17,     1,      788,    "RO",   0,      1,      0ull,   0},
41992         {"RESERVED_18_63"              ,        18,     46,     788,    "RAZ",  1,      1,      0,      0},
41993         {"INTERVAL"                    ,        0,      22,     789,    "RO",   1,      0,      0,      0ull},
41994         {"RESERVED_22_23"              ,        22,     2,      789,    "RAZ",  1,      0,      0,      0ull},
41995         {"COUNT"                       ,        24,     22,     789,    "RO",   1,      0,      0,      0ull},
41996         {"RESERVED_46_46"              ,        46,     1,      789,    "RAZ",  1,      0,      0,      0ull},
41997         {"ENA"                         ,        47,     1,      789,    "RO",   1,      0,      0,      0ull},
41998         {"RESERVED_48_63"              ,        48,     16,     789,    "RAZ",  1,      0,      0,      0ull},
41999         {"BSIZE"                       ,        0,      20,     790,    "RO",   1,      0,      0,      0ull},
42000         {"BASE"                        ,        20,     31,     790,    "RO",   1,      0,      0,      0ull},
42001         {"BUCKET"                      ,        51,     13,     790,    "RO",   1,      0,      0,      0ull},
42002         {"BUCKET"                      ,        0,      7,      791,    "RO",   1,      0,      0,      0ull},
42003         {"RESERVED_7_7"                ,        7,      1,      791,    "RAZ",  1,      0,      0,      0ull},
42004         {"CSIZE"                       ,        8,      13,     791,    "RO",   1,      0,      0,      0ull},
42005         {"CPOOL"                       ,        21,     3,      791,    "RO",   1,      0,      0,      0ull},
42006         {"RESERVED_24_63"              ,        24,     40,     791,    "RAZ",  1,      0,      0,      0ull},
42007         {"RING"                        ,        0,      4,      792,    "R/W",  0,      0,      0ull,   0ull},
42008         {"NUM_BUCKETS"                 ,        4,      20,     792,    "R/W",  0,      0,      0ull,   0ull},
42009         {"FIRST_BUCKET"                ,        24,     31,     792,    "R/W",  0,      0,      0ull,   0ull},
42010         {"RESERVED_55_63"              ,        55,     9,      792,    "RAZ",  1,      0,      0,      0ull},
42011         {"RING"                        ,        0,      4,      793,    "R/W",  0,      0,      0ull,   0ull},
42012         {"INTERVAL"                    ,        4,      22,     793,    "R/W",  0,      0,      0ull,   0ull},
42013         {"WORDS_PER_CHUNK"             ,        26,     13,     793,    "R/W",  0,      0,      0ull,   0ull},
42014         {"POOL"                        ,        39,     3,      793,    "R/W",  0,      0,      0ull,   0ull},
42015         {"ENABLE"                      ,        42,     1,      793,    "R/W",  0,      0,      0ull,   0ull},
42016         {"RESERVED_43_63"              ,        43,     21,     793,    "RAZ",  1,      0,      0,      0ull},
42017         {"CTL"                         ,        0,      1,      794,    "RO",   1,      0,      0,      0ull},
42018         {"NCB"                         ,        1,      1,      794,    "RO",   1,      0,      0,      0ull},
42019         {"STA"                         ,        2,      2,      794,    "RO",   1,      0,      0,      0ull},
42020         {"RESERVED_4_63"               ,        4,      60,     794,    "RAZ",  1,      0,      0,      0ull},
42021         {"MASK"                        ,        0,      16,     795,    "R/W1C",        0,      0,      0ull,   0ull},
42022         {"RESERVED_16_63"              ,        16,     48,     795,    "RAZ",  1,      0,      0,      0ull},
42023         {"ENABLE_TIMERS"               ,        0,      1,      796,    "R/W",  0,      0,      0ull,   0ull},
42024         {"ENABLE_DWB"                  ,        1,      1,      796,    "R/W",  0,      0,      0ull,   0ull},
42025         {"RESET"                       ,        2,      1,      796,    "RAZ",  0,      0,      0ull,   0ull},
42026         {"RESERVED_3_63"               ,        3,      61,     796,    "RAZ",  1,      0,      0,      0ull},
42027         {"MASK"                        ,        0,      16,     797,    "R/W",  0,      0,      0ull,   0ull},
42028         {"RESERVED_16_63"              ,        16,     48,     797,    "RAZ",  1,      0,      0,      0ull},
42029         {"INDEX"                       ,        0,      8,      798,    "R/W",  0,      0,      0ull,   0ull},
42030         {"INC"                         ,        8,      8,      798,    "R/W",  0,      0,      0ull,   0ull},
42031         {"RESERVED_16_63"              ,        16,     48,     798,    "RAZ",  1,      0,      0,      0ull},
42032         {"TDF0"                        ,        0,      1,      799,    "RO",   0,      0,      0ull,   0ull},
42033         {"TDF1"                        ,        1,      1,      799,    "RO",   0,      0,      0ull,   0ull},
42034         {"TCF"                         ,        2,      1,      799,    "RO",   0,      0,      0ull,   0ull},
42035         {"RESERVED_3_63"               ,        3,      61,     799,    "RAZ",  0,      0,      0ull,   0ull},
42036         {"ENA"                         ,        0,      1,      800,    "R/W",  0,      0,      0ull,   0ull},
42037         {"WRAP"                        ,        1,      1,      800,    "R/W",  0,      0,      0ull,   0ull},
42038         {"TRIG_CTL"                    ,        2,      2,      800,    "R/W",  0,      0,      0ull,   0ull},
42039         {"TIME_GRN"                    ,        4,      3,      800,    "R/W",  0,      0,      0ull,   0ull},
42040         {"FULL_THR"                    ,        7,      2,      800,    "R/W",  0,      0,      0ull,   0ull},
42041         {"CIU_TRG"                     ,        9,      1,      800,    "R/W",  0,      0,      0ull,   0ull},
42042         {"CIU_THR"                     ,        10,     1,      800,    "R/W",  0,      0,      0ull,   0ull},
42043         {"MCD0_TRG"                    ,        11,     1,      800,    "R/W",  0,      0,      0ull,   0ull},
42044         {"MCD0_THR"                    ,        12,     1,      800,    "R/W",  0,      0,      0ull,   0ull},
42045         {"MCD0_ENA"                    ,        13,     1,      800,    "R/W",  0,      0,      0ull,   0ull},
42046         {"IGNORE_O"                    ,        14,     1,      800,    "R/W",  0,      0,      0ull,   0ull},
42047         {"RESERVED_15_63"              ,        15,     49,     800,    "RAZ",  0,      0,      0ull,   0ull},
42048         {"WPTR"                        ,        0,      8,      801,    "RO",   0,      0,      0ull,   0ull},
42049         {"RPTR"                        ,        8,      8,      801,    "RO",   0,      0,      0ull,   0ull},
42050         {"CYCLES"                      ,        16,     48,     801,    "RO",   0,      0,      0ull,   0ull},
42051         {"WPTR"                        ,        0,      10,     802,    "RO",   0,      0,      0ull,   0ull},
42052         {"RESERVED_10_11"              ,        10,     2,      802,    "RAZ",  0,      0,      0ull,   0ull},
42053         {"RPTR"                        ,        12,     10,     802,    "RO",   0,      0,      0ull,   0ull},
42054         {"RESERVED_22_23"              ,        22,     2,      802,    "RAZ",  0,      0,      0ull,   0ull},
42055         {"CYCLES"                      ,        24,     40,     802,    "RO",   0,      0,      0ull,   0ull},
42056         {"ADR"                         ,        0,      36,     803,    "R/W",  0,      1,      0ull,   0},
42057         {"RESERVED_36_63"              ,        36,     28,     803,    "RAZ",  0,      0,      0ull,   0ull},
42058         {"ADR"                         ,        0,      36,     804,    "R/W",  0,      0,      0ull,   0ull},
42059         {"RESERVED_36_63"              ,        36,     28,     804,    "RAZ",  0,      0,      0ull,   0ull},
42060         {"DWB"                         ,        0,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42061         {"PL2"                         ,        1,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42062         {"PSL1"                        ,        2,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42063         {"LDD"                         ,        3,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42064         {"LDI"                         ,        4,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42065         {"LDT"                         ,        5,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42066         {"STF"                         ,        6,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42067         {"STC"                         ,        7,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42068         {"STP"                         ,        8,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42069         {"STT"                         ,        9,      1,      805,    "R/W",  0,      0,      0ull,   1ull},
42070         {"IOBLD8"                      ,        10,     1,      805,    "R/W",  0,      0,      0ull,   1ull},
42071         {"IOBLD16"                     ,        11,     1,      805,    "R/W",  0,      0,      0ull,   1ull},
42072         {"IOBLD32"                     ,        12,     1,      805,    "R/W",  0,      0,      0ull,   1ull},
42073         {"IOBLD64"                     ,        13,     1,      805,    "R/W",  0,      0,      0ull,   1ull},
42074         {"IOBST"                       ,        14,     1,      805,    "R/W",  0,      0,      0ull,   1ull},
42075         {"IOBDMA"                      ,        15,     1,      805,    "R/W",  0,      0,      0ull,   1ull},
42076         {"SAA"                         ,        16,     1,      805,    "R/W",  0,      0,      0ull,   1ull},
42077         {"RESERVED_17_63"              ,        17,     47,     805,    "RAZ",  0,      0,      0ull,   0ull},
42078         {"MIO"                         ,        0,      1,      806,    "R/W",  0,      0,      0ull,   1ull},
42079         {"ILLEGAL3"                    ,        1,      2,      806,    "R/W",  0,      0,      0ull,   3ull},
42080         {"PCI"                         ,        3,      1,      806,    "R/W",  0,      0,      0ull,   1ull},
42081         {"KEY"                         ,        4,      1,      806,    "R/W",  0,      0,      0ull,   1ull},
42082         {"FPA"                         ,        5,      1,      806,    "R/W",  0,      0,      0ull,   1ull},
42083         {"DFA"                         ,        6,      1,      806,    "R/W",  0,      0,      0ull,   1ull},
42084         {"ZIP"                         ,        7,      1,      806,    "R/W",  0,      0,      0ull,   1ull},
42085         {"RNG"                         ,        8,      1,      806,    "R/W",  0,      0,      0ull,   1ull},
42086         {"ILLEGAL2"                    ,        9,      3,      806,    "R/W",  0,      0,      0ull,   7ull},
42087         {"POW"                         ,        12,     1,      806,    "R/W",  0,      0,      0ull,   1ull},
42088         {"ILLEGAL"                     ,        13,     19,     806,    "R/W",  0,      0,      0ull,   524287ull},
42089         {"RESERVED_32_63"              ,        32,     32,     806,    "RAZ",  0,      0,      0ull,   0ull},
42090         {"PP"                          ,        0,      16,     807,    "R/W",  0,      0,      0ull,   0ull},
42091         {"PKI"                         ,        16,     1,      807,    "R/W",  0,      0,      0ull,   0ull},
42092         {"PKO"                         ,        17,     1,      807,    "R/W",  0,      0,      0ull,   0ull},
42093         {"IOBREQ"                      ,        18,     1,      807,    "R/W",  0,      0,      0ull,   0ull},
42094         {"DWB"                         ,        19,     1,      807,    "R/W",  0,      0,      0ull,   0ull},
42095         {"RESERVED_20_63"              ,        20,     44,     807,    "RAZ",  0,      0,      0ull,   0ull},
42096         {"CIU_TRG"                     ,        0,      1,      808,    "R/W1C",        0,      0,      0ull,   0ull},
42097         {"CIU_THR"                     ,        1,      1,      808,    "R/W1C",        0,      0,      0ull,   0ull},
42098         {"MCD0_TRG"                    ,        2,      1,      808,    "R/W1C",        0,      0,      0ull,   0ull},
42099         {"MCD0_THR"                    ,        3,      1,      808,    "R/W1C",        0,      0,      0ull,   0ull},
42100         {"RESERVED_4_63"               ,        4,      60,     808,    "RAZ",  0,      0,      0ull,   0ull},
42101         {"DATA"                        ,        0,      64,     809,    "RO",   0,      0,      0ull,   0ull},
42102         {"ADR"                         ,        0,      36,     810,    "R/W",  0,      1,      0ull,   0},
42103         {"RESERVED_36_63"              ,        36,     28,     810,    "RAZ",  0,      0,      0ull,   0ull},
42104         {"ADR"                         ,        0,      36,     811,    "R/W",  0,      0,      0ull,   0ull},
42105         {"RESERVED_36_63"              ,        36,     28,     811,    "RAZ",  0,      0,      0ull,   0ull},
42106         {"DWB"                         ,        0,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42107         {"PL2"                         ,        1,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42108         {"PSL1"                        ,        2,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42109         {"LDD"                         ,        3,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42110         {"LDI"                         ,        4,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42111         {"LDT"                         ,        5,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42112         {"STF"                         ,        6,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42113         {"STC"                         ,        7,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42114         {"STP"                         ,        8,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42115         {"STT"                         ,        9,      1,      812,    "R/W",  0,      0,      0ull,   1ull},
42116         {"IOBLD8"                      ,        10,     1,      812,    "R/W",  0,      0,      0ull,   1ull},
42117         {"IOBLD16"                     ,        11,     1,      812,    "R/W",  0,      0,      0ull,   1ull},
42118         {"IOBLD32"                     ,        12,     1,      812,    "R/W",  0,      0,      0ull,   1ull},
42119         {"IOBLD64"                     ,        13,     1,      812,    "R/W",  0,      0,      0ull,   1ull},
42120         {"IOBST"                       ,        14,     1,      812,    "R/W",  0,      0,      0ull,   1ull},
42121         {"IOBDMA"                      ,        15,     1,      812,    "R/W",  0,      0,      0ull,   1ull},
42122         {"SAA"                         ,        16,     1,      812,    "R/W",  0,      0,      0ull,   1ull},
42123         {"RESERVED_17_63"              ,        17,     47,     812,    "RAZ",  0,      0,      0ull,   0ull},
42124         {"MIO"                         ,        0,      1,      813,    "R/W",  0,      0,      0ull,   1ull},
42125         {"ILLEGAL3"                    ,        1,      2,      813,    "R/W",  0,      0,      0ull,   3ull},
42126         {"PCI"                         ,        3,      1,      813,    "R/W",  0,      0,      0ull,   1ull},
42127         {"KEY"                         ,        4,      1,      813,    "R/W",  0,      0,      0ull,   1ull},
42128         {"FPA"                         ,        5,      1,      813,    "R/W",  0,      0,      0ull,   1ull},
42129         {"DFA"                         ,        6,      1,      813,    "R/W",  0,      0,      0ull,   1ull},
42130         {"ZIP"                         ,        7,      1,      813,    "R/W",  0,      0,      0ull,   1ull},
42131         {"RNG"                         ,        8,      1,      813,    "R/W",  0,      0,      0ull,   1ull},
42132         {"ILLEGAL2"                    ,        9,      3,      813,    "R/W",  0,      0,      0ull,   7ull},
42133         {"POW"                         ,        12,     1,      813,    "R/W",  0,      0,      0ull,   1ull},
42134         {"ILLEGAL"                     ,        13,     19,     813,    "R/W",  0,      0,      0ull,   524287ull},
42135         {"RESERVED_32_63"              ,        32,     32,     813,    "RAZ",  0,      0,      0ull,   0ull},
42136         {"PP"                          ,        0,      16,     814,    "R/W",  0,      0,      0ull,   0ull},
42137         {"PKI"                         ,        16,     1,      814,    "R/W",  0,      0,      0ull,   0ull},
42138         {"PKO"                         ,        17,     1,      814,    "R/W",  0,      0,      0ull,   0ull},
42139         {"IOBREQ"                      ,        18,     1,      814,    "R/W",  0,      0,      0ull,   0ull},
42140         {"DWB"                         ,        19,     1,      814,    "R/W",  0,      0,      0ull,   0ull},
42141         {"RESERVED_20_63"              ,        20,     44,     814,    "RAZ",  0,      0,      0ull,   0ull},
42142         {"ADR"                         ,        0,      36,     815,    "R/W",  0,      1,      0ull,   0},
42143         {"RESERVED_36_63"              ,        36,     28,     815,    "RAZ",  0,      0,      0ull,   0ull},
42144         {"ADR"                         ,        0,      36,     816,    "R/W",  0,      0,      0ull,   0ull},
42145         {"RESERVED_36_63"              ,        36,     28,     816,    "RAZ",  0,      0,      0ull,   0ull},
42146         {"DWB"                         ,        0,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42147         {"PL2"                         ,        1,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42148         {"PSL1"                        ,        2,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42149         {"LDD"                         ,        3,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42150         {"LDI"                         ,        4,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42151         {"LDT"                         ,        5,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42152         {"STF"                         ,        6,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42153         {"STC"                         ,        7,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42154         {"STP"                         ,        8,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42155         {"STT"                         ,        9,      1,      817,    "R/W",  0,      0,      0ull,   1ull},
42156         {"IOBLD8"                      ,        10,     1,      817,    "R/W",  0,      0,      0ull,   1ull},
42157         {"IOBLD16"                     ,        11,     1,      817,    "R/W",  0,      0,      0ull,   1ull},
42158         {"IOBLD32"                     ,        12,     1,      817,    "R/W",  0,      0,      0ull,   1ull},
42159         {"IOBLD64"                     ,        13,     1,      817,    "R/W",  0,      0,      0ull,   1ull},
42160         {"IOBST"                       ,        14,     1,      817,    "R/W",  0,      0,      0ull,   1ull},
42161         {"IOBDMA"                      ,        15,     1,      817,    "R/W",  0,      0,      0ull,   1ull},
42162         {"SAA"                         ,        16,     1,      817,    "R/W",  0,      0,      0ull,   1ull},
42163         {"RESERVED_17_63"              ,        17,     47,     817,    "RAZ",  0,      0,      0ull,   0ull},
42164         {"MIO"                         ,        0,      1,      818,    "R/W",  0,      0,      0ull,   1ull},
42165         {"ILLEGAL3"                    ,        1,      2,      818,    "R/W",  0,      0,      0ull,   3ull},
42166         {"PCI"                         ,        3,      1,      818,    "R/W",  0,      0,      0ull,   1ull},
42167         {"KEY"                         ,        4,      1,      818,    "R/W",  0,      0,      0ull,   1ull},
42168         {"FPA"                         ,        5,      1,      818,    "R/W",  0,      0,      0ull,   1ull},
42169         {"DFA"                         ,        6,      1,      818,    "R/W",  0,      0,      0ull,   1ull},
42170         {"ZIP"                         ,        7,      1,      818,    "R/W",  0,      0,      0ull,   1ull},
42171         {"RNG"                         ,        8,      1,      818,    "R/W",  0,      0,      0ull,   1ull},
42172         {"ILLEGAL2"                    ,        9,      3,      818,    "R/W",  0,      0,      0ull,   7ull},
42173         {"POW"                         ,        12,     1,      818,    "R/W",  0,      0,      0ull,   1ull},
42174         {"ILLEGAL"                     ,        13,     19,     818,    "R/W",  0,      0,      0ull,   524287ull},
42175         {"RESERVED_32_63"              ,        32,     32,     818,    "RAZ",  0,      0,      0ull,   0ull},
42176         {"PP"                          ,        0,      16,     819,    "R/W",  0,      0,      0ull,   0ull},
42177         {"PKI"                         ,        16,     1,      819,    "R/W",  0,      0,      0ull,   0ull},
42178         {"PKO"                         ,        17,     1,      819,    "R/W",  0,      0,      0ull,   0ull},
42179         {"IOBREQ"                      ,        18,     1,      819,    "R/W",  0,      0,      0ull,   0ull},
42180         {"DWB"                         ,        19,     1,      819,    "R/W",  0,      0,      0ull,   0ull},
42181         {"RESERVED_20_63"              ,        20,     44,     819,    "RAZ",  0,      0,      0ull,   0ull},
42182         {"INEPINT"                     ,        0,      16,     820,    "RO",   0,      0,      0ull,   0ull},
42183         {"OUTEPINT"                    ,        16,     16,     820,    "RO",   0,      0,      0ull,   0ull},
42184         {"INEPMSK"                     ,        0,      16,     821,    "R/W",  0,      0,      0ull,   0ull},
42185         {"OUTEPMSK"                    ,        16,     16,     821,    "R/W",  0,      0,      0ull,   0ull},
42186         {"DEVSPD"                      ,        0,      2,      822,    "R/W",  0,      0,      0ull,   0ull},
42187         {"NZSTSOUTHSHK"                ,        2,      1,      822,    "R/W",  0,      0,      0ull,   0ull},
42188         {"RESERVED_3_3"                ,        3,      1,      822,    "RAZ",  1,      1,      0,      0},
42189         {"DEVADDR"                     ,        4,      7,      822,    "R/W",  0,      0,      0ull,   0ull},
42190         {"PERFRINT"                    ,        11,     2,      822,    "R/W",  0,      0,      0ull,   0ull},
42191         {"RESERVED_13_17"              ,        13,     5,      822,    "RAZ",  1,      1,      0,      0},
42192         {"EPMISCNT"                    ,        18,     5,      822,    "R/W",  0,      0,      8ull,   0ull},
42193         {"RESERVED_23_31"              ,        23,     9,      822,    "RAZ",  1,      1,      0,      0},
42194         {"RMTWKUPSIG"                  ,        0,      1,      823,    "R/W",  0,      0,      0ull,   0ull},
42195         {"SFTDISCON"                   ,        1,      1,      823,    "R/W",  0,      0,      0ull,   0ull},
42196         {"GNPINNAKSTS"                 ,        2,      1,      823,    "RO",   0,      0,      0ull,   0ull},
42197         {"GOUTNAKSTS"                  ,        3,      1,      823,    "RO",   0,      0,      0ull,   0ull},
42198         {"TSTCTL"                      ,        4,      3,      823,    "R/W",  0,      0,      0ull,   0ull},
42199         {"SGNPINNAK"                   ,        7,      1,      823,    "WO",   0,      0,      0ull,   0ull},
42200         {"CGNPINNAK"                   ,        8,      1,      823,    "WO",   0,      0,      0ull,   0ull},
42201         {"SGOUTNAK"                    ,        9,      1,      823,    "WO",   0,      0,      0ull,   0ull},
42202         {"CGOUTNAK"                    ,        10,     1,      823,    "WO",   0,      0,      0ull,   0ull},
42203         {"PWRONPRGDONE"                ,        11,     1,      823,    "R/W",  0,      0,      0ull,   0ull},
42204         {"RESERVED_12_31"              ,        12,     20,     823,    "RAZ",  1,      1,      0,      0},
42205         {"MPS"                         ,        0,      11,     824,    "R/W",  0,      0,      0ull,   0ull},
42206         {"NEXTEP"                      ,        11,     4,      824,    "R/W",  0,      0,      0ull,   0ull},
42207         {"USBACTEP"                    ,        15,     1,      824,    "R/W",  0,      0,      1ull,   0ull},
42208         {"DPID"                        ,        16,     1,      824,    "RO",   0,      0,      0ull,   0ull},
42209         {"NAKSTS"                      ,        17,     1,      824,    "RO",   0,      0,      0ull,   0ull},
42210         {"EPTYPE"                      ,        18,     2,      824,    "R/W",  0,      0,      0ull,   0ull},
42211         {"RESERVED_20_20"              ,        20,     1,      824,    "RAZ",  1,      1,      0,      0},
42212         {"STALL"                       ,        21,     1,      824,    "R/W",  0,      0,      0ull,   0ull},
42213         {"TXFNUM"                      ,        22,     4,      824,    "R/W",  0,      0,      0ull,   0ull},
42214         {"CNAK"                        ,        26,     1,      824,    "WO",   0,      0,      0ull,   0ull},
42215         {"SNAK"                        ,        27,     1,      824,    "WO",   0,      0,      0ull,   0ull},
42216         {"SETD0PID"                    ,        28,     1,      824,    "WO",   0,      0,      0ull,   0ull},
42217         {"SETD1PID"                    ,        29,     1,      824,    "WO",   0,      0,      0ull,   0ull},
42218         {"EPDIS"                       ,        30,     1,      824,    "R/W",  0,      0,      0ull,   0ull},
42219         {"EPENA"                       ,        31,     1,      824,    "R/W",  0,      0,      0ull,   0ull},
42220         {"XFERCOMPL"                   ,        0,      1,      825,    "R/W1C",        0,      0,      0ull,   0ull},
42221         {"EPDISBLD"                    ,        1,      1,      825,    "R/W1C",        0,      0,      0ull,   0ull},
42222         {"AHBERR"                      ,        2,      1,      825,    "R/W1C",        0,      0,      0ull,   0ull},
42223         {"TIMEOUT"                     ,        3,      1,      825,    "R/W1C",        0,      0,      0ull,   0ull},
42224         {"INTKNTXFEMP"                 ,        4,      1,      825,    "R/W1C",        0,      0,      0ull,   0ull},
42225         {"INTKNEPMIS"                  ,        5,      1,      825,    "R/W1C",        0,      0,      0ull,   0ull},
42226         {"INEPNAKEFF"                  ,        6,      1,      825,    "RO",   0,      0,      0ull,   0ull},
42227         {"RESERVED_7_31"               ,        7,      25,     825,    "RAZ",  1,      1,      0,      0},
42228         {"XFERCOMPLMSK"                ,        0,      1,      826,    "R/W",  0,      0,      0ull,   0ull},
42229         {"EPDISBLDMSK"                 ,        1,      1,      826,    "R/W",  0,      0,      0ull,   0ull},
42230         {"AHBERRMSK"                   ,        2,      1,      826,    "R/W",  0,      0,      0ull,   0ull},
42231         {"TIMEOUTMSK"                  ,        3,      1,      826,    "R/W",  0,      0,      0ull,   0ull},
42232         {"INTKNTXFEMPMSK"              ,        4,      1,      826,    "R/W",  0,      0,      0ull,   0ull},
42233         {"INTKNEPMISMSK"               ,        5,      1,      826,    "R/W",  0,      0,      0ull,   0ull},
42234         {"INEPNAKEFFMSK"               ,        6,      1,      826,    "R/W",  0,      0,      0ull,   0ull},
42235         {"RESERVED_7_31"               ,        7,      25,     826,    "RAZ",  1,      1,      0,      0},
42236         {"XFERSIZE"                    ,        0,      19,     827,    "R/W",  0,      0,      0ull,   0ull},
42237         {"PKTCNT"                      ,        19,     10,     827,    "R/W",  0,      0,      0ull,   0ull},
42238         {"MC"                          ,        29,     2,      827,    "R/W",  0,      0,      0ull,   0ull},
42239         {"RESERVED_31_31"              ,        31,     1,      827,    "RAZ",  1,      1,      0,      0},
42240         {"MPS"                         ,        0,      11,     828,    "R/W",  0,      0,      0ull,   0ull},
42241         {"RESERVED_11_14"              ,        11,     4,      828,    "RAZ",  0,      0,      0ull,   0ull},
42242         {"USBACTEP"                    ,        15,     1,      828,    "R/W",  0,      0,      1ull,   0ull},
42243         {"DPID"                        ,        16,     1,      828,    "RO",   0,      0,      0ull,   0ull},
42244         {"NAKSTS"                      ,        17,     1,      828,    "RO",   0,      0,      0ull,   0ull},
42245         {"EPTYPE"                      ,        18,     2,      828,    "R/W",  0,      0,      0ull,   0ull},
42246         {"SNP"                         ,        20,     1,      828,    "R/W",  0,      0,      0ull,   0ull},
42247         {"STALL"                       ,        21,     1,      828,    "R/W",  0,      0,      0ull,   0ull},
42248         {"RESERVED_22_25"              ,        22,     4,      828,    "RAZ",  1,      1,      0,      0},
42249         {"CNAK"                        ,        26,     1,      828,    "WO",   0,      0,      0ull,   0ull},
42250         {"SNAK"                        ,        27,     1,      828,    "WO",   0,      0,      0ull,   0ull},
42251         {"SETD0PID"                    ,        28,     1,      828,    "WO",   0,      0,      0ull,   0ull},
42252         {"SETD1PID"                    ,        29,     1,      828,    "WO",   0,      0,      0ull,   0ull},
42253         {"EPDIS"                       ,        30,     1,      828,    "R/W",  0,      0,      0ull,   0ull},
42254         {"EPENA"                       ,        31,     1,      828,    "R/W",  0,      0,      0ull,   0ull},
42255         {"XFERCOMPL"                   ,        0,      1,      829,    "R/W1C",        0,      0,      0ull,   0ull},
42256         {"EPDISBLD"                    ,        1,      1,      829,    "R/W1C",        0,      0,      0ull,   0ull},
42257         {"AHBERR"                      ,        2,      1,      829,    "R/W1C",        0,      0,      0ull,   0ull},
42258         {"SETUP"                       ,        3,      1,      829,    "R/W1C",        0,      0,      0ull,   0ull},
42259         {"OUTTKNEPDIS"                 ,        4,      1,      829,    "R/W1C",        0,      0,      0ull,   0ull},
42260         {"RESERVED_5_31"               ,        5,      27,     829,    "RAZ",  1,      1,      0,      0},
42261         {"XFERCOMPLMSK"                ,        0,      1,      830,    "R/W",  0,      0,      0ull,   0ull},
42262         {"EPDISBLDMSK"                 ,        1,      1,      830,    "R/W",  0,      0,      0ull,   0ull},
42263         {"AHBERRMSK"                   ,        2,      1,      830,    "R/W",  0,      0,      0ull,   0ull},
42264         {"SETUPMSK"                    ,        3,      1,      830,    "R/W",  0,      0,      0ull,   0ull},
42265         {"OUTTKNEPDISMSK"              ,        4,      1,      830,    "R/W",  0,      0,      0ull,   0ull},
42266         {"RESERVED_5_31"               ,        5,      27,     830,    "RAZ",  1,      1,      0,      0},
42267         {"XFERSIZE"                    ,        0,      19,     831,    "R/W",  0,      0,      0ull,   0ull},
42268         {"PKTCNT"                      ,        19,     10,     831,    "R/W",  0,      0,      0ull,   0ull},
42269         {"MC"                          ,        29,     2,      831,    "R/W",  0,      0,      0ull,   0ull},
42270         {"RESERVED_31_31"              ,        31,     1,      831,    "RAZ",  1,      1,      0,      0},
42271         {"DPTXFSTADDR"                 ,        0,      16,     832,    "RO",   0,      0,      0ull,   0ull},
42272         {"DPTXFSIZE"                   ,        16,     16,     832,    "RO",   0,      0,      1896ull,        1896ull},
42273         {"SUSPSTS"                     ,        0,      1,      833,    "RO",   0,      0,      0ull,   0ull},
42274         {"ENUMSPD"                     ,        1,      2,      833,    "RO",   0,      0,      0ull,   0ull},
42275         {"ERRTICERR"                   ,        3,      1,      833,    "RO",   0,      0,      0ull,   0ull},
42276         {"RESERVED_4_7"                ,        4,      4,      833,    "RAZ",  1,      1,      0,      0},
42277         {"SOFFN"                       ,        8,      14,     833,    "RO",   0,      0,      0ull,   0ull},
42278         {"RESERVED_22_31"              ,        22,     10,     833,    "RAZ",  1,      1,      0,      0},
42279         {"INTKNWPTR"                   ,        0,      5,      834,    "RO",   0,      0,      0ull,   0ull},
42280         {"RESERVED_5_6"                ,        5,      2,      834,    "RAZ",  1,      1,      0,      0},
42281         {"WRAPBIT"                     ,        7,      1,      834,    "RO",   0,      0,      0ull,   0ull},
42282         {"EPTKN"                       ,        8,      24,     834,    "RO",   0,      0,      0ull,   0ull},
42283         {"EPTKN"                       ,        0,      32,     835,    "RO",   0,      0,      0ull,   0ull},
42284         {"EPTKN"                       ,        0,      32,     836,    "RO",   0,      0,      0ull,   0ull},
42285         {"EPTKN"                       ,        0,      32,     837,    "RO",   0,      0,      0ull,   0ull},
42286         {"GLBLINTRMSK"                 ,        0,      1,      838,    "R/W",  0,      0,      0ull,   1ull},
42287         {"HBSTLEN"                     ,        1,      4,      838,    "R/W",  0,      0,      0ull,   0ull},
42288         {"DMAEN"                       ,        5,      1,      838,    "R/W",  0,      0,      0ull,   0ull},
42289         {"RESERVED_6_6"                ,        6,      1,      838,    "RAZ",  1,      1,      0,      0},
42290         {"NPTXFEMPLVL"                 ,        7,      1,      838,    "R/W",  0,      0,      0ull,   1ull},
42291         {"PTXFEMPLVL"                  ,        8,      1,      838,    "R/W",  0,      0,      0ull,   1ull},
42292         {"RESERVED_9_31"               ,        9,      23,     838,    "RAZ",  1,      1,      0,      0},
42293         {"EPDIR"                       ,        0,      32,     839,    "RO",   0,      0,      0ull,   0ull},
42294         {"OTGMODE"                     ,        0,      3,      840,    "RO",   0,      0,      2ull,   2ull},
42295         {"OTGARCH"                     ,        3,      2,      840,    "RO",   0,      0,      1ull,   1ull},
42296         {"SINGPNT"                     ,        5,      1,      840,    "RO",   0,      0,      0ull,   0ull},
42297         {"HSPHYTYPE"                   ,        6,      2,      840,    "RO",   0,      0,      1ull,   1ull},
42298         {"FSPHYTYPE"                   ,        8,      2,      840,    "RO",   0,      0,      0ull,   0ull},
42299         {"NUMDEVEPS"                   ,        10,     4,      840,    "RO",   0,      0,      4ull,   4ull},
42300         {"NUMHSTCHNL"                  ,        14,     4,      840,    "RO",   0,      0,      7ull,   7ull},
42301         {"PERIOSUPPORT"                ,        18,     1,      840,    "RO",   0,      0,      1ull,   1ull},
42302         {"DYNFIFOSIZING"               ,        19,     1,      840,    "RO",   0,      0,      1ull,   1ull},
42303         {"RESERVED_20_21"              ,        20,     2,      840,    "RAZ",  1,      1,      0,      0},
42304         {"NPTXQDEPTH"                  ,        22,     2,      840,    "RO",   0,      0,      2ull,   2ull},
42305         {"PTXQDEPTH"                   ,        24,     2,      840,    "RO",   0,      0,      2ull,   2ull},
42306         {"TKNQDEPTH"                   ,        26,     5,      840,    "RO",   0,      0,      30ull,  30ull},
42307         {"RESERVED_31_31"              ,        31,     1,      840,    "RAZ",  1,      1,      0,      0},
42308         {"XFERSIZEWIDTH"               ,        0,      4,      841,    "RO",   0,      0,      8ull,   8ull},
42309         {"PKTSIZEWIDTH"                ,        4,      3,      841,    "RO",   0,      0,      6ull,   6ull},
42310         {"OTGEN"                       ,        7,      1,      841,    "RO",   0,      0,      1ull,   1ull},
42311         {"I2C_SELECTION"               ,        8,      1,      841,    "RO",   0,      0,      0ull,   0ull},
42312         {"VENDOR_CONTROL_INTERFACE_SUPPORT",    9,      1,      841,    "RO",   0,      0,      0ull,   0ull},
42313         {"OPTFEATURE"                  ,        10,     1,      841,    "RO",   0,      0,      1ull,   1ull},
42314         {"RSTTYPE"                     ,        11,     1,      841,    "RO",   0,      0,      1ull,   1ull},
42315         {"AHBPHYSYNC"                  ,        12,     1,      841,    "RO",   0,      0,      0ull,   0ull},
42316         {"RESERVED_13_15"              ,        13,     3,      841,    "RAZ",  1,      1,      0,      0},
42317         {"DFIFODEPTH"                  ,        16,     16,     841,    "RO",   0,      0,      1824ull,        1824ull},
42318         {"NUMDEVPERIOEPS"              ,        0,      4,      842,    "RO",   0,      0,      4ull,   4ull},
42319         {"ENABLEPWROPT"                ,        4,      1,      842,    "RO",   0,      0,      0ull,   0ull},
42320         {"AHBFREQ"                     ,        5,      1,      842,    "RO",   0,      0,      1ull,   1ull},
42321         {"RESERVED_6_13"               ,        6,      8,      842,    "RAZ",  1,      1,      0,      0},
42322         {"PHYDATAWIDTH"                ,        14,     2,      842,    "RO",   0,      0,      1ull,   1ull},
42323         {"NUMCTLEPS"                   ,        16,     4,      842,    "RO",   0,      0,      4ull,   4ull},
42324         {"IDDGFLTR"                    ,        20,     1,      842,    "RO",   0,      0,      1ull,   1ull},
42325         {"VBUSVALIDFLTR"               ,        21,     1,      842,    "RO",   0,      0,      1ull,   1ull},
42326         {"AVALIDFLTR"                  ,        22,     1,      842,    "RO",   0,      0,      0ull,   0ull},
42327         {"BVALIDFLTR"                  ,        23,     1,      842,    "RO",   0,      0,      0ull,   0ull},
42328         {"SESSENDFLTR"                 ,        24,     1,      842,    "RO",   0,      0,      0ull,   0ull},
42329         {"ENDEDTRFIFO"                 ,        25,     1,      842,    "RO",   0,      0,      0ull,   0ull},
42330         {"NUMDEVMODINEND"              ,        26,     4,      842,    "RO",   0,      0,      2ull,   2ull},
42331         {"RESERVED_30_31"              ,        30,     2,      842,    "RAZ",  1,      1,      0,      0},
42332         {"RESERVED_0_0"                ,        0,      1,      843,    "RAZ",  1,      1,      0,      0},
42333         {"MODEMISMSK"                  ,        1,      1,      843,    "R/W",  0,      0,      0ull,   0ull},
42334         {"OTGINTMSK"                   ,        2,      1,      843,    "R/W",  0,      0,      0ull,   0ull},
42335         {"SOFMSK"                      ,        3,      1,      843,    "R/W",  0,      0,      0ull,   0ull},
42336         {"RXFLVLMSK"                   ,        4,      1,      843,    "R/W",  0,      0,      0ull,   0ull},
42337         {"NPTXFEMPMSK"                 ,        5,      1,      843,    "R/W",  0,      0,      0ull,   0ull},
42338         {"GINNAKEFFMSK"                ,        6,      1,      843,    "R/W",  0,      0,      0ull,   0ull},
42339         {"GOUTNAKEFFMSK"               ,        7,      1,      843,    "R/W",  0,      0,      0ull,   0ull},
42340         {"ULPICKINTMSK"                ,        8,      1,      843,    "R/W",  0,      0,      0ull,   0ull},
42341         {"I2CINT"                      ,        9,      1,      843,    "R/W",  0,      0,      0ull,   0ull},
42342         {"ERLYSUSPMSK"                 ,        10,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42343         {"USBSUSPMSK"                  ,        11,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42344         {"USBRSTMSK"                   ,        12,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42345         {"ENUMDONEMSK"                 ,        13,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42346         {"ISOOUTDROPMSK"               ,        14,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42347         {"EOPFMSK"                     ,        15,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42348         {"RESERVED_16_16"              ,        16,     1,      843,    "RAZ",  1,      1,      0,      0},
42349         {"EPMISMSK"                    ,        17,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42350         {"INEPINTMSK"                  ,        18,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42351         {"OEPINTMSK"                   ,        19,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42352         {"INCOMPISOINMSK"              ,        20,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42353         {"INCOMPLPMSK"                 ,        21,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42354         {"FETSUSPMSK"                  ,        22,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42355         {"RESERVED_23_23"              ,        23,     1,      843,    "RAZ",  1,      1,      0,      0},
42356         {"PRTINTMSK"                   ,        24,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42357         {"HCHINTMSK"                   ,        25,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42358         {"PTXFEMPMSK"                  ,        26,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42359         {"RESERVED_27_27"              ,        27,     1,      843,    "RAZ",  1,      1,      0,      0},
42360         {"CONIDSTSCHNGMSK"             ,        28,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42361         {"DISCONNINTMSK"               ,        29,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42362         {"SESSREQINTMSK"               ,        30,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42363         {"WKUPINTMSK"                  ,        31,     1,      843,    "R/W",  0,      0,      0ull,   0ull},
42364         {"CURMOD"                      ,        0,      1,      844,    "RO",   0,      0,      0ull,   0ull},
42365         {"MODEMIS"                     ,        1,      1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42366         {"OTGINT"                      ,        2,      1,      844,    "RO",   0,      0,      0ull,   0ull},
42367         {"SOF"                         ,        3,      1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42368         {"RXFLVL"                      ,        4,      1,      844,    "RO",   0,      0,      0ull,   0ull},
42369         {"NPTXFEMP"                    ,        5,      1,      844,    "RO",   0,      0,      0ull,   0ull},
42370         {"GINNAKEFF"                   ,        6,      1,      844,    "RO",   0,      0,      0ull,   0ull},
42371         {"GOUTNAKEFF"                  ,        7,      1,      844,    "RO",   0,      0,      0ull,   0ull},
42372         {"ULPICKINT"                   ,        8,      1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42373         {"I2CINT"                      ,        9,      1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42374         {"ERLYSUSP"                    ,        10,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42375         {"USBSUSP"                     ,        11,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42376         {"USBRST"                      ,        12,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42377         {"ENUMDONE"                    ,        13,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42378         {"ISOOUTDROP"                  ,        14,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42379         {"EOPF"                        ,        15,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42380         {"RESERVED_16_16"              ,        16,     1,      844,    "RAZ",  1,      1,      0,      0},
42381         {"EPMIS"                       ,        17,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42382         {"IEPINT"                      ,        18,     1,      844,    "RO",   0,      0,      0ull,   0ull},
42383         {"OEPINT"                      ,        19,     1,      844,    "RO",   0,      0,      0ull,   0ull},
42384         {"INCOMPISOIN"                 ,        20,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42385         {"INCOMPLP"                    ,        21,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42386         {"FETSUSP"                     ,        22,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42387         {"RESERVED_23_23"              ,        23,     1,      844,    "RAZ",  1,      1,      0,      0},
42388         {"PRTINT"                      ,        24,     1,      844,    "RO",   0,      0,      0ull,   0ull},
42389         {"HCHINT"                      ,        25,     1,      844,    "RO",   0,      0,      0ull,   0ull},
42390         {"PTXFEMP"                     ,        26,     1,      844,    "RO",   0,      0,      0ull,   0ull},
42391         {"RESERVED_27_27"              ,        27,     1,      844,    "RAZ",  1,      1,      0,      0},
42392         {"CONIDSTSCHNG"                ,        28,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42393         {"DISCONNINT"                  ,        29,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42394         {"SESSREQINT"                  ,        30,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42395         {"WKUPINT"                     ,        31,     1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
42396         {"NPTXFSTADDR"                 ,        0,      16,     845,    "R/W",  0,      0,      1824ull,        456ull},
42397         {"NPTXFDEP"                    ,        16,     16,     845,    "R/W",  0,      0,      1824ull,        912ull},
42398         {"NPTXFSPCAVAIL"               ,        0,      16,     846,    "RO",   0,      0,      0ull,   0ull},
42399         {"NPTXQSPCAVAIL"               ,        16,     8,      846,    "RO",   0,      0,      0ull,   0ull},
42400         {"NPTXQTOP"                    ,        24,     7,      846,    "RO",   0,      0,      0ull,   0ull},
42401         {"RESERVED_31_31"              ,        31,     1,      846,    "RAZ",  1,      1,      0,      0},
42402         {"SESREQSCS"                   ,        0,      1,      847,    "R/W",  0,      0,      0ull,   0ull},
42403         {"SESREQ"                      ,        1,      1,      847,    "R/W",  0,      0,      0ull,   0ull},
42404         {"RESERVED_2_7"                ,        2,      6,      847,    "RAZ",  1,      1,      0,      0},
42405         {"HSTNEGSCS"                   ,        8,      1,      847,    "R/W",  0,      0,      0ull,   0ull},
42406         {"HNPREQ"                      ,        9,      1,      847,    "R/W",  0,      0,      0ull,   0ull},
42407         {"HSTSETHNPEN"                 ,        10,     1,      847,    "R/W",  0,      0,      0ull,   0ull},
42408         {"DEVHNPEN"                    ,        11,     1,      847,    "R/W",  0,      0,      0ull,   0ull},
42409         {"RESERVED_12_15"              ,        12,     4,      847,    "RAZ",  1,      1,      0,      0},
42410         {"CONIDSTS"                    ,        16,     1,      847,    "RO",   1,      1,      0,      0},
42411         {"DBNCTIME"                    ,        17,     1,      847,    "RO",   0,      0,      0ull,   0ull},
42412         {"ASESVLD"                     ,        18,     1,      847,    "RO",   1,      1,      0,      0},
42413         {"BSESVLD"                     ,        19,     1,      847,    "RO",   1,      1,      0,      0},
42414         {"RESERVED_20_31"              ,        20,     12,     847,    "RAZ",  1,      1,      0,      0},
42415         {"RESERVED_0_1"                ,        0,      2,      848,    "RAZ",  1,      1,      0,      0},
42416         {"SESENDDET"                   ,        2,      1,      848,    "R/W1C",        0,      0,      0ull,   0ull},
42417         {"RESERVED_3_7"                ,        3,      5,      848,    "RAZ",  1,      1,      0,      0},
42418         {"SESREQSUCSTSCHNG"            ,        8,      1,      848,    "R/W1C",        0,      0,      0ull,   0ull},
42419         {"HSTNEGSUCSTSCHNG"            ,        9,      1,      848,    "R/W1C",        0,      0,      0ull,   0ull},
42420         {"RESERVED_10_16"              ,        10,     7,      848,    "RAZ",  1,      1,      0,      0},
42421         {"HSTNEGDET"                   ,        17,     1,      848,    "R/W1C",        0,      0,      0ull,   0ull},
42422         {"ADEVTOUTCHG"                 ,        18,     1,      848,    "R/W1C",        0,      0,      0ull,   0ull},
42423         {"DBNCEDONE"                   ,        19,     1,      848,    "R/W1C",        0,      0,      0ull,   0ull},
42424         {"RESERVED_20_31"              ,        20,     12,     848,    "RAZ",  1,      1,      0,      0},
42425         {"CSFTRST"                     ,        0,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
42426         {"HSFTRST"                     ,        1,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
42427         {"FRMCNTRRST"                  ,        2,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
42428         {"INTKNQFLSH"                  ,        3,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
42429         {"RXFFLSH"                     ,        4,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
42430         {"TXFFLSH"                     ,        5,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
42431         {"TXFNUM"                      ,        6,      5,      849,    "R/W",  0,      0,      0ull,   0ull},
42432         {"RESERVED_11_29"              ,        11,     19,     849,    "RAZ",  1,      1,      0,      0},
42433         {"DMAREQ"                      ,        30,     1,      849,    "RO",   0,      0,      0ull,   0ull},
42434         {"AHBIDLE"                     ,        31,     1,      849,    "RO",   0,      0,      1ull,   1ull},
42435         {"RXFDEP"                      ,        0,      16,     850,    "R/W",  0,      0,      1824ull,        456ull},
42436         {"RESERVED_16_31"              ,        16,     16,     850,    "RAZ",  1,      1,      0,      0},
42437         {"EPNUM"                       ,        0,      4,      851,    "RO",   0,      0,      0ull,   0ull},
42438         {"BCNT"                        ,        4,      11,     851,    "RO",   0,      0,      0ull,   0ull},
42439         {"DPID"                        ,        15,     2,      851,    "RO",   0,      0,      0ull,   0ull},
42440         {"PKTSTS"                      ,        17,     4,      851,    "RO",   0,      0,      0ull,   0ull},
42441         {"FN"                          ,        21,     4,      851,    "RO",   0,      0,      0ull,   0ull},
42442         {"RESERVED_25_31"              ,        25,     7,      851,    "RAZ",  1,      1,      0,      0},
42443         {"CHNUM"                       ,        0,      4,      852,    "RO",   0,      0,      0ull,   0ull},
42444         {"BCNT"                        ,        4,      11,     852,    "RO",   0,      0,      0ull,   0ull},
42445         {"DPID"                        ,        15,     2,      852,    "RO",   0,      0,      0ull,   0ull},
42446         {"PKTSTS"                      ,        17,     4,      852,    "RO",   0,      0,      0ull,   0ull},
42447         {"RESERVED_21_31"              ,        21,     11,     852,    "RAZ",  1,      1,      0,      0},
42448         {"EPNUM"                       ,        0,      4,      853,    "RO",   0,      0,      0ull,   0ull},
42449         {"BCNT"                        ,        4,      11,     853,    "RO",   0,      0,      0ull,   0ull},
42450         {"DPID"                        ,        15,     2,      853,    "RO",   0,      0,      0ull,   0ull},
42451         {"PKTSTS"                      ,        17,     4,      853,    "RO",   0,      0,      0ull,   0ull},
42452         {"FN"                          ,        21,     4,      853,    "RO",   0,      0,      0ull,   0ull},
42453         {"RESERVED_25_31"              ,        25,     7,      853,    "RAZ",  1,      1,      0,      0},
42454         {"CHNUM"                       ,        0,      4,      854,    "RO",   0,      0,      0ull,   0ull},
42455         {"BCNT"                        ,        4,      11,     854,    "RO",   0,      0,      0ull,   0ull},
42456         {"DPID"                        ,        15,     2,      854,    "RO",   0,      0,      0ull,   0ull},
42457         {"PKTSTS"                      ,        17,     4,      854,    "RO",   0,      0,      0ull,   0ull},
42458         {"RESERVED_21_31"              ,        21,     11,     854,    "RAZ",  1,      1,      0,      0},
42459         {"SYNOPSYSID"                  ,        0,      32,     855,    "RO",   1,      1,      0,      0},
42460         {"TOUTCAL"                     ,        0,      3,      856,    "R/W",  0,      0,      0ull,   0ull},
42461         {"PHYIF"                       ,        3,      1,      856,    "RO",   0,      0,      1ull,   1ull},
42462         {"ULPI_UTMI_SEL"               ,        4,      1,      856,    "RO",   0,      0,      0ull,   0ull},
42463         {"FSINTF"                      ,        5,      1,      856,    "WO",   0,      0,      0ull,   0ull},
42464         {"PHYSEL"                      ,        6,      1,      856,    "WO",   0,      0,      0ull,   0ull},
42465         {"DDRSEL"                      ,        7,      1,      856,    "R/W",  0,      0,      0ull,   0ull},
42466         {"SRPCAP"                      ,        8,      1,      856,    "RO",   0,      0,      0ull,   0ull},
42467         {"HNPCAP"                      ,        9,      1,      856,    "RO",   0,      0,      0ull,   0ull},
42468         {"USBTRDTIM"                   ,        10,     4,      856,    "R/W",  0,      0,      5ull,   5ull},
42469         {"RESERVED_14_14"              ,        14,     1,      856,    "RAZ",  1,      1,      0,      0},
42470         {"PHYLPWRCLKSEL"               ,        15,     1,      856,    "R/W",  0,      0,      0ull,   0ull},
42471         {"OTGI2CSEL"                   ,        16,     1,      856,    "RO",   0,      0,      0ull,   0ull},
42472         {"RESERVED_17_31"              ,        17,     15,     856,    "RAZ",  1,      1,      0,      0},
42473         {"HAINT"                       ,        0,      16,     857,    "RO",   0,      0,      0ull,   0ull},
42474         {"RESERVED_16_31"              ,        16,     16,     857,    "RAZ",  1,      1,      0,      0},
42475         {"HAINTMSK"                    ,        0,      16,     858,    "R/W",  0,      0,      0ull,   0ull},
42476         {"RESERVED_16_31"              ,        16,     16,     858,    "RAZ",  1,      1,      0,      0},
42477         {"MPS"                         ,        0,      11,     859,    "R/W",  0,      0,      0ull,   0ull},
42478         {"EPNUM"                       ,        11,     4,      859,    "R/W",  0,      0,      0ull,   0ull},
42479         {"EPDIR"                       ,        15,     1,      859,    "R/W",  0,      0,      0ull,   0ull},
42480         {"RESERVED_16_16"              ,        16,     1,      859,    "RAZ",  1,      1,      0,      0},
42481         {"LSPDDEV"                     ,        17,     1,      859,    "R/W",  0,      0,      0ull,   0ull},
42482         {"EPTYPE"                      ,        18,     2,      859,    "R/W",  0,      0,      0ull,   0ull},
42483         {"EC"                          ,        20,     2,      859,    "R/W",  0,      0,      0ull,   0ull},
42484         {"DEVADDR"                     ,        22,     7,      859,    "R/W",  0,      0,      0ull,   0ull},
42485         {"ODDFRM"                      ,        29,     1,      859,    "R/W",  0,      0,      0ull,   0ull},
42486         {"CHDIS"                       ,        30,     1,      859,    "R/W",  0,      0,      0ull,   0ull},
42487         {"CHENA"                       ,        31,     1,      859,    "R/W",  0,      0,      0ull,   0ull},
42488         {"FSLSPCLKSEL"                 ,        0,      2,      860,    "R/W",  0,      0,      0ull,   0ull},
42489         {"FSLSSUPP"                    ,        2,      1,      860,    "R/W",  0,      0,      0ull,   0ull},
42490         {"RESERVED_3_31"               ,        3,      29,     860,    "RAZ",  1,      1,      0,      0},
42491         {"XFERCOMPL"                   ,        0,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42492         {"CHHLTD"                      ,        1,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42493         {"AHBERR"                      ,        2,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42494         {"STALL"                       ,        3,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42495         {"NAK"                         ,        4,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42496         {"ACK"                         ,        5,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42497         {"NYET"                        ,        6,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42498         {"XACTERR"                     ,        7,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42499         {"BBLERR"                      ,        8,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42500         {"FRMOVRUN"                    ,        9,      1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42501         {"DATATGLERR"                  ,        10,     1,      861,    "R/W1C",        0,      0,      0ull,   0ull},
42502         {"RESERVED_11_31"              ,        11,     21,     861,    "RAZ",  1,      1,      0,      0},
42503         {"XFERCOMPLMSK"                ,        0,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42504         {"CHHLTDMSK"                   ,        1,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42505         {"AHBERRMSK"                   ,        2,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42506         {"STALLMSK"                    ,        3,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42507         {"NAKMSK"                      ,        4,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42508         {"ACKMSK"                      ,        5,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42509         {"NYETMSK"                     ,        6,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42510         {"XACTERRMSK"                  ,        7,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42511         {"BBLERRMSK"                   ,        8,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42512         {"FRMOVRUNMSK"                 ,        9,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
42513         {"DATATGLERRMSK"               ,        10,     1,      862,    "R/W",  0,      0,      0ull,   0ull},
42514         {"RESERVED_11_31"              ,        11,     21,     862,    "RAZ",  1,      1,      0,      0},
42515         {"PRTADDR"                     ,        0,      7,      863,    "R/W",  0,      0,      0ull,   0ull},
42516         {"HUBADDR"                     ,        7,      7,      863,    "R/W",  0,      0,      0ull,   0ull},
42517         {"XACTPOS"                     ,        14,     2,      863,    "R/W",  0,      0,      0ull,   0ull},
42518         {"COMPSPLT"                    ,        16,     1,      863,    "R/W",  0,      0,      0ull,   0ull},
42519         {"RESERVED_17_30"              ,        17,     14,     863,    "RAZ",  1,      1,      0,      0},
42520         {"SPLTENA"                     ,        31,     1,      863,    "R/W",  0,      0,      0ull,   0ull},
42521         {"XFERSIZE"                    ,        0,      19,     864,    "R/W",  0,      0,      0ull,   0ull},
42522         {"PKTCNT"                      ,        19,     10,     864,    "R/W",  0,      0,      0ull,   0ull},
42523         {"PID"                         ,        29,     2,      864,    "R/W",  0,      0,      0ull,   0ull},
42524         {"DOPNG"                       ,        31,     1,      864,    "R/W",  0,      0,      0ull,   0ull},
42525         {"FRINT"                       ,        0,      16,     865,    "R/W",  0,      0,      2959ull,        3750ull},
42526         {"RESERVED_16_31"              ,        16,     16,     865,    "RAZ",  1,      1,      0,      0},
42527         {"FRNUM"                       ,        0,      16,     866,    "RO",   0,      0,      16383ull,       0ull},
42528         {"FRREM"                       ,        16,     16,     866,    "RO",   0,      0,      0ull,   0ull},
42529         {"PRTCONNSTS"                  ,        0,      1,      867,    "RO",   0,      0,      0ull,   0ull},
42530         {"PRTCONNDET"                  ,        1,      1,      867,    "R/W1C",        0,      0,      0ull,   0ull},
42531         {"PRTENA"                      ,        2,      1,      867,    "R/W1C",        0,      0,      0ull,   0ull},
42532         {"PRTENCHNG"                   ,        3,      1,      867,    "R/W1C",        0,      0,      0ull,   0ull},
42533         {"PRTOVRCURRACT"               ,        4,      1,      867,    "RO",   0,      0,      0ull,   0ull},
42534         {"PRTOVRCURRCHNG"              ,        5,      1,      867,    "R/W1C",        0,      0,      0ull,   0ull},
42535         {"PRTRES"                      ,        6,      1,      867,    "R/W",  0,      0,      0ull,   0ull},
42536         {"PRTSUSP"                     ,        7,      1,      867,    "R/W",  0,      0,      0ull,   0ull},
42537         {"PRTRST"                      ,        8,      1,      867,    "R/W",  0,      0,      0ull,   0ull},
42538         {"RESERVED_9_9"                ,        9,      1,      867,    "RAZ",  1,      1,      0,      0},
42539         {"PRTLNSTS"                    ,        10,     2,      867,    "RO",   0,      0,      0ull,   0ull},
42540         {"PRTPWR"                      ,        12,     1,      867,    "R/W",  0,      0,      0ull,   0ull},
42541         {"PRTTSTCTL"                   ,        13,     4,      867,    "R/W",  0,      0,      0ull,   0ull},
42542         {"PRTSPD"                      ,        17,     2,      867,    "RO",   0,      0,      0ull,   0ull},
42543         {"RESERVED_19_31"              ,        19,     13,     867,    "RAZ",  1,      1,      0,      0},
42544         {"PTXFSTADDR"                  ,        0,      16,     868,    "R/W",  0,      0,      3648ull,        912ull},
42545         {"PTXFSIZE"                    ,        16,     16,     868,    "R/W",  0,      0,      256ull, 456ull},
42546         {"PTXFSPCAVAIL"                ,        0,      16,     869,    "RO",   0,      0,      0ull,   0ull},
42547         {"PTXQSPCAVAIL"                ,        16,     8,      869,    "RO",   0,      0,      0ull,   0ull},
42548         {"PTXQTOP"                     ,        24,     8,      869,    "RO",   0,      0,      0ull,   0ull},
42549         {"DATA"                        ,        0,      32,     870,    "R/W",  0,      0,      0ull,   0ull},
42550         {"STOPPCLK"                    ,        0,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
42551         {"GATEHCLK"                    ,        1,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
42552         {"PWRCLMP"                     ,        2,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
42553         {"RSTPDWNMODULE"               ,        3,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
42554         {"PHYSUSPENDED"                ,        4,      1,      871,    "RO",   0,      0,      0ull,   0ull},
42555         {"RESERVED_5_31"               ,        5,      27,     871,    "RAZ",  1,      1,      0,      0},
42556         {"NOF_BIS"                     ,        0,      1,      872,    "RO",   0,      0,      0ull,   0ull},
42557         {"NIF_BIS"                     ,        1,      1,      872,    "RO",   0,      0,      0ull,   0ull},
42558         {"USBC_BIS"                    ,        2,      1,      872,    "RO",   0,      0,      0ull,   0ull},
42559         {"N2UF_BIS"                    ,        3,      1,      872,    "RO",   0,      0,      0ull,   0ull},
42560         {"E2HC_BIS"                    ,        4,      1,      872,    "RO",   0,      0,      0ull,   0ull},
42561         {"U2NF_BIS"                    ,        5,      1,      872,    "RO",   0,      0,      0ull,   0ull},
42562         {"U2NC_BIS"                    ,        6,      1,      872,    "RO",   0,      0,      0ull,   0ull},
42563         {"RESERVED_7_63"               ,        7,      57,     872,    "RAZ",  1,      1,      0,      0},
42564         {"DIVIDE"                      ,        0,      3,      873,    "R/W",  0,      0,      4ull,   0ull},
42565         {"HRST"                        ,        3,      1,      873,    "R/W",  0,      0,      0ull,   1ull},
42566         {"PRST"                        ,        4,      1,      873,    "R/W",  0,      0,      0ull,   1ull},
42567         {"ENABLE"                      ,        5,      1,      873,    "R/W",  0,      0,      1ull,   1ull},
42568         {"POR"                         ,        6,      1,      873,    "R/W",  0,      0,      1ull,   0ull},
42569         {"S_BIST"                      ,        7,      1,      873,    "R/W",  0,      0,      0ull,   1ull},
42570         {"SD_MODE"                     ,        8,      2,      873,    "R/W",  0,      0,      0ull,   0ull},
42571         {"CDIV_BYP"                    ,        10,     1,      873,    "R/W",  0,      0,      0ull,   0ull},
42572         {"P_C_SEL"                     ,        11,     2,      873,    "R/W",  0,      0,      2ull,   0ull},
42573         {"P_COM_ON"                    ,        13,     1,      873,    "R/W",  0,      0,      1ull,   1ull},
42574         {"P_RTYPE"                     ,        14,     2,      873,    "R/W",  0,      0,      0ull,   0ull},
42575         {"RESERVED_16_16"              ,        16,     1,      873,    "RAZ",  1,      1,      0,      0},
42576         {"HCLK_RST"                    ,        17,     1,      873,    "R/W",  0,      0,      1ull,   1ull},
42577         {"DIVIDE2"                     ,        18,     2,      873,    "R/W",  0,      0,      0ull,   1ull},
42578         {"RESERVED_20_63"              ,        20,     44,     873,    "RAZ",  1,      1,      0,      0},
42579         {"L2C_EMOD"                    ,        0,      2,      874,    "R/W",  0,      0,      1ull,   1ull},
42580         {"INV_A2"                      ,        2,      1,      874,    "R/W",  0,      0,      0ull,   0ull},
42581         {"DMA_TEST"                    ,        3,      1,      874,    "R/W",  0,      0,      0ull,   0ull},
42582         {"DMA_STT"                     ,        4,      1,      874,    "R/W",  0,      0,      0ull,   0ull},
42583         {"DMA_0PAG"                    ,        5,      1,      874,    "R/W",  0,      0,      0ull,   0ull},
42584         {"RESERVED_6_63"               ,        6,      58,     874,    "RAZ",  1,      1,      0,      0},
42585         {"ADDR"                        ,        0,      36,     875,    "R/W",  0,      1,      0ull,   0},
42586         {"RESERVED_36_63"              ,        36,     28,     875,    "RAZ",  1,      1,      0,      0},
42587         {"ADDR"                        ,        0,      36,     876,    "R/W",  0,      1,      0ull,   0},
42588         {"RESERVED_36_63"              ,        36,     28,     876,    "RAZ",  1,      1,      0,      0},
42589         {"ADDR"                        ,        0,      36,     877,    "R/W",  0,      1,      0ull,   0},
42590         {"RESERVED_36_63"              ,        36,     28,     877,    "RAZ",  1,      1,      0,      0},
42591         {"ADDR"                        ,        0,      36,     878,    "R/W",  0,      1,      0ull,   0},
42592         {"RESERVED_36_63"              ,        36,     28,     878,    "RAZ",  1,      1,      0,      0},
42593         {"ADDR"                        ,        0,      36,     879,    "R/W",  0,      1,      0ull,   0},
42594         {"RESERVED_36_63"              ,        36,     28,     879,    "RAZ",  1,      1,      0,      0},
42595         {"ADDR"                        ,        0,      36,     880,    "R/W",  0,      1,      0ull,   0},
42596         {"RESERVED_36_63"              ,        36,     28,     880,    "RAZ",  1,      1,      0,      0},
42597         {"ADDR"                        ,        0,      36,     881,    "R/W",  0,      1,      0ull,   0},
42598         {"RESERVED_36_63"              ,        36,     28,     881,    "RAZ",  1,      1,      0,      0},
42599         {"ADDR"                        ,        0,      36,     882,    "R/W",  0,      1,      0ull,   0},
42600         {"RESERVED_36_63"              ,        36,     28,     882,    "RAZ",  1,      1,      0,      0},
42601         {"ADDR"                        ,        0,      36,     883,    "R/W",  0,      1,      0ull,   0},
42602         {"RESERVED_36_63"              ,        36,     28,     883,    "RAZ",  1,      1,      0,      0},
42603         {"ADDR"                        ,        0,      36,     884,    "R/W",  0,      1,      0ull,   0},
42604         {"RESERVED_36_63"              ,        36,     28,     884,    "RAZ",  1,      1,      0,      0},
42605         {"ADDR"                        ,        0,      36,     885,    "R/W",  0,      1,      0ull,   0},
42606         {"RESERVED_36_63"              ,        36,     28,     885,    "RAZ",  1,      1,      0,      0},
42607         {"ADDR"                        ,        0,      36,     886,    "R/W",  0,      1,      0ull,   0},
42608         {"RESERVED_36_63"              ,        36,     28,     886,    "RAZ",  1,      1,      0,      0},
42609         {"ADDR"                        ,        0,      36,     887,    "R/W",  0,      1,      0ull,   0},
42610         {"RESERVED_36_63"              ,        36,     28,     887,    "RAZ",  1,      1,      0,      0},
42611         {"ADDR"                        ,        0,      36,     888,    "R/W",  0,      1,      0ull,   0},
42612         {"RESERVED_36_63"              ,        36,     28,     888,    "RAZ",  1,      1,      0,      0},
42613         {"ADDR"                        ,        0,      36,     889,    "R/W",  0,      1,      0ull,   0},
42614         {"RESERVED_36_63"              ,        36,     28,     889,    "RAZ",  1,      1,      0,      0},
42615         {"ADDR"                        ,        0,      36,     890,    "R/W",  0,      1,      0ull,   0},
42616         {"RESERVED_36_63"              ,        36,     28,     890,    "RAZ",  1,      1,      0,      0},
42617         {"BURST"                       ,        0,      4,      891,    "R/W",  0,      0,      0ull,   0ull},
42618         {"CHANNEL"                     ,        4,      5,      891,    "R/W",  0,      0,      0ull,   0ull},
42619         {"COUNT"                       ,        9,      11,     891,    "R/W",  0,      0,      0ull,   0ull},
42620         {"F_ADDR"                      ,        20,     18,     891,    "R/W",  0,      0,      0ull,   0ull},
42621         {"REQ"                         ,        38,     1,      891,    "R/W1C",        0,      0,      0ull,   0ull},
42622         {"DONE"                        ,        39,     1,      891,    "R/W1C",        0,      0,      0ull,   0ull},
42623         {"RESERVED_40_63"              ,        40,     24,     891,    "RAZ",  1,      1,      0,      0},
42624         {"PR_PO_E"                     ,        0,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42625         {"PR_PU_F"                     ,        1,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42626         {"NR_PO_E"                     ,        2,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42627         {"NR_PU_F"                     ,        3,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42628         {"LR_PO_E"                     ,        4,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42629         {"LR_PU_F"                     ,        5,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42630         {"PT_PO_E"                     ,        6,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42631         {"PT_PU_F"                     ,        7,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42632         {"NT_PO_E"                     ,        8,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42633         {"NT_PU_F"                     ,        9,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
42634         {"LT_PO_E"                     ,        10,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42635         {"LT_PU_F"                     ,        11,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42636         {"DCRED_E"                     ,        12,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42637         {"DCRED_F"                     ,        13,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42638         {"L2C_S_E"                     ,        14,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42639         {"L2C_A_F"                     ,        15,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42640         {"L2_FI_E"                     ,        16,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42641         {"L2_FI_F"                     ,        17,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42642         {"RG_FI_E"                     ,        18,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42643         {"RG_FI_F"                     ,        19,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42644         {"RQ_Q2_F"                     ,        20,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42645         {"RQ_Q2_E"                     ,        21,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42646         {"RQ_Q3_F"                     ,        22,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42647         {"RQ_Q3_E"                     ,        23,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42648         {"UOD_PE"                      ,        24,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42649         {"UOD_PF"                      ,        25,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42650         {"RESERVED_26_31"              ,        26,     6,      892,    "RAZ",  0,      0,      0ull,   0ull},
42651         {"LTL_F_PE"                    ,        32,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42652         {"LTL_F_PF"                    ,        33,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42653         {"ND4O_RPE"                    ,        34,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42654         {"ND4O_RPF"                    ,        35,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42655         {"ND4O_DPE"                    ,        36,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42656         {"ND4O_DPF"                    ,        37,     1,      892,    "R/W",  0,      0,      0ull,   0ull},
42657         {"RESERVED_38_63"              ,        38,     26,     892,    "RAZ",  1,      1,      0,      0},
42658         {"PR_PO_E"                     ,        0,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42659         {"PR_PU_F"                     ,        1,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42660         {"NR_PO_E"                     ,        2,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42661         {"NR_PU_F"                     ,        3,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42662         {"LR_PO_E"                     ,        4,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42663         {"LR_PU_F"                     ,        5,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42664         {"PT_PO_E"                     ,        6,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42665         {"PT_PU_F"                     ,        7,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42666         {"NT_PO_E"                     ,        8,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42667         {"NT_PU_F"                     ,        9,      1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42668         {"LT_PO_E"                     ,        10,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42669         {"LT_PU_F"                     ,        11,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42670         {"DCRED_E"                     ,        12,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42671         {"DCRED_F"                     ,        13,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42672         {"L2C_S_E"                     ,        14,     1,      893,    "R/W1C",        1,      0,      0,      0ull},
42673         {"L2C_A_F"                     ,        15,     1,      893,    "R/W1C",        1,      0,      0,      0ull},
42674         {"LT_FI_E"                     ,        16,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42675         {"LT_FI_F"                     ,        17,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42676         {"RG_FI_E"                     ,        18,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42677         {"RG_FI_F"                     ,        19,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42678         {"RQ_Q2_F"                     ,        20,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42679         {"RQ_Q2_E"                     ,        21,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42680         {"RQ_Q3_F"                     ,        22,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42681         {"RQ_Q3_E"                     ,        23,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42682         {"UOD_PE"                      ,        24,     1,      893,    "R/W1C",        1,      0,      0,      0ull},
42683         {"UOD_PF"                      ,        25,     1,      893,    "R/W1C",        1,      0,      0,      0ull},
42684         {"RESERVED_26_31"              ,        26,     6,      893,    "RAZ",  1,      0,      0,      0ull},
42685         {"LTL_F_PE"                    ,        32,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42686         {"LTL_F_PF"                    ,        33,     1,      893,    "R/W1C",        0,      0,      0ull,   0ull},
42687         {"ND4O_RPE"                    ,        34,     1,      893,    "R/W1C",        1,      0,      0,      0ull},
42688         {"ND4O_RPF"                    ,        35,     1,      893,    "R/W1C",        1,      0,      0,      0ull},
42689         {"ND4O_DPE"                    ,        36,     1,      893,    "R/W1C",        1,      0,      0,      0ull},
42690         {"ND4O_DPF"                    ,        37,     1,      893,    "R/W1C",        1,      0,      0,      0ull},
42691         {"RESERVED_38_63"              ,        38,     26,     893,    "RAZ",  1,      1,      0,      0},
42692         {"ATE_RESET"                   ,        0,      1,      894,    "R/W",  0,      0,      0ull,   0ull},
42693         {"TDATA_IN"                    ,        1,      8,      894,    "R/W",  0,      0,      0ull,   0ull},
42694         {"TADDR_IN"                    ,        9,      4,      894,    "R/W",  0,      0,      0ull,   0ull},
42695         {"TDATA_SEL"                   ,        13,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42696         {"BIST_ENB"                    ,        14,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42697         {"VTEST_ENB"                   ,        15,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42698         {"LOOP_ENB"                    ,        16,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42699         {"TX_BS_EN"                    ,        17,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42700         {"TX_BS_ENH"                   ,        18,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42701         {"RESERVED_19_22"              ,        19,     4,      894,    "RAZ",  0,      0,      0ull,   0ull},
42702         {"HST_MODE"                    ,        23,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42703         {"DM_PULLD"                    ,        24,     1,      894,    "R/W",  0,      0,      1ull,   1ull},
42704         {"DP_PULLD"                    ,        25,     1,      894,    "R/W",  0,      0,      1ull,   1ull},
42705         {"TCLK"                        ,        26,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42706         {"USBP_BIST"                   ,        27,     1,      894,    "R/W",  0,      0,      1ull,   1ull},
42707         {"USBC_END"                    ,        28,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42708         {"DMA_BMODE"                   ,        29,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42709         {"TXPREEMPHASISTUNE"           ,        30,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42710         {"RESERVED_31_31"              ,        31,     1,      894,    "RAZ",  0,      0,      0ull,   0ull},
42711         {"TDATA_OUT"                   ,        32,     4,      894,    "RO",   1,      1,      0,      0},
42712         {"BIST_ERR"                    ,        36,     1,      894,    "RO",   0,      0,      0ull,   0ull},
42713         {"BIST_DONE"                   ,        37,     1,      894,    "RO",   0,      0,      0ull,   0ull},
42714         {"HSBIST"                      ,        38,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42715         {"FSBIST"                      ,        39,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42716         {"LSBIST"                      ,        40,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42717         {"DRVVBUS"                     ,        41,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42718         {"PORTRESET"                   ,        42,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42719         {"OTGDISABLE"                  ,        43,     1,      894,    "R/W",  0,      0,      1ull,   1ull},
42720         {"OTGTUNE"                     ,        44,     3,      894,    "R/W",  0,      0,      2ull,   2ull},
42721         {"COMPDISTUNE"                 ,        47,     3,      894,    "R/W",  0,      0,      2ull,   2ull},
42722         {"SQRXTUNE"                    ,        50,     3,      894,    "R/W",  0,      0,      3ull,   3ull},
42723         {"TXHSXVTUNE"                  ,        53,     2,      894,    "R/W",  0,      0,      0ull,   0ull},
42724         {"TXFSLSTUNE"                  ,        55,     4,      894,    "R/W",  0,      0,      3ull,   3ull},
42725         {"TXVREFTUNE"                  ,        59,     4,      894,    "R/W",  0,      0,      7ull,   7ull},
42726         {"TXRISETUNE"                  ,        63,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
42727         {"ZIP_CTL"                     ,        0,      4,      895,    "RO",   1,      0,      0,      0ull},
42728         {"ZIP_CORE"                    ,        4,      27,     895,    "RO",   1,      0,      0,      0ull},
42729         {"RESERVED_31_63"              ,        31,     33,     895,    "RAZ",  1,      0,      0,      0ull},
42730         {"PTR"                         ,        0,      33,     896,    "R/W",  0,      0,      0ull,   0ull},
42731         {"SIZE"                        ,        33,     13,     896,    "R/W",  0,      0,      0ull,   0ull},
42732         {"POOL"                        ,        46,     3,      896,    "R/W",  0,      0,      0ull,   0ull},
42733         {"DWB"                         ,        49,     9,      896,    "R/W",  0,      0,      0ull,   0ull},
42734         {"RESERVED_58_63"              ,        58,     6,      896,    "RAZ",  0,      0,      0ull,   0ull},
42735         {"RESET"                       ,        0,      1,      897,    "RAZ",  0,      0,      0ull,   0ull},
42736         {"FORCECLK"                    ,        1,      1,      897,    "R/W",  0,      0,      0ull,   0ull},
42737         {"RESERVED_2_63"               ,        2,      62,     897,    "RAZ",  0,      0,      0ull,   0ull},
42738         {"DISABLED"                    ,        0,      1,      898,    "RO",   0,      0,      0ull,   0ull},
42739         {"RESERVED_1_7"                ,        1,      7,      898,    "RAZ",  0,      0,      0ull,   0ull},
42740         {"CTXSIZE"                     ,        8,      12,     898,    "RO",   0,      0,      1536ull,        1536ull},
42741         {"ONFSIZE"                     ,        20,     12,     898,    "RO",   0,      0,      512ull, 512ull},
42742         {"DEPTH"                       ,        32,     16,     898,    "RO",   0,      0,      31744ull,       31744ull},
42743         {"RESERVED_48_63"              ,        48,     16,     898,    "RAZ",  1,      0,      0,      0ull},
42744         {"ASSERTS"                     ,        0,      14,     899,    "RO",   0,      0,      0ull,   0ull},
42745         {"RESERVED_14_63"              ,        14,     50,     899,    "RAZ",  1,      0,      0,      0ull},
42746         {"DOORBELL"                    ,        0,      1,      900,    "R/W1C",        0,      0,      0ull,   0ull},
42747         {"RESERVED_1_63"               ,        1,      63,     900,    "RAZ",  1,      0,      0,      0ull},
42748         {"DOORBELL"                    ,        0,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
42749         {"RESERVED_1_63"               ,        1,      63,     901,    "RAZ",  1,      0,      0,      0ull},
42750         {NULL,0,0,0,0,0,0,0,0}
42751 };
42752 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn56xx[] = {
42753          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
42754         {"cvmx_agl_gmx_bad_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      11,     0},
42755         {"cvmx_agl_gmx_bist"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1,      2,      11},
42756         {"cvmx_agl_gmx_drv_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      6,      13},
42757         {"cvmx_agl_gmx_inf_mode"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     3,      3,      19},
42758         {"cvmx_agl_gmx_prt#_cfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      7,      22},
42759         {"cvmx_agl_gmx_rx#_adr_cam0"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     5,      1,      29},
42760         {"cvmx_agl_gmx_rx#_adr_cam1"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      1,      30},
42761         {"cvmx_agl_gmx_rx#_adr_cam2"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     7,      1,      31},
42762         {"cvmx_agl_gmx_rx#_adr_cam3"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     8,      1,      32},
42763         {"cvmx_agl_gmx_rx#_adr_cam4"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     9,      1,      33},
42764         {"cvmx_agl_gmx_rx#_adr_cam5"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     1,      34},
42765         {"cvmx_agl_gmx_rx#_adr_cam_en" ,        CVMX_CSR_DB_TYPE_RSL,   64,     11,     2,      35},
42766         {"cvmx_agl_gmx_rx#_adr_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     12,     4,      37},
42767         {"cvmx_agl_gmx_rx#_decision"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     13,     2,      41},
42768         {"cvmx_agl_gmx_rx#_frm_chk"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     10,     43},
42769         {"cvmx_agl_gmx_rx#_frm_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     15,     11,     53},
42770         {"cvmx_agl_gmx_rx#_frm_max"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     16,     2,      64},
42771         {"cvmx_agl_gmx_rx#_frm_min"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     17,     2,      66},
42772         {"cvmx_agl_gmx_rx#_ifg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     18,     2,      68},
42773         {"cvmx_agl_gmx_rx#_int_en"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     19,     19,     70},
42774         {"cvmx_agl_gmx_rx#_int_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     20,     19,     89},
42775         {"cvmx_agl_gmx_rx#_jabber"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     21,     2,      108},
42776         {"cvmx_agl_gmx_rx#_pause_drop_time",    CVMX_CSR_DB_TYPE_RSL,   64,     22,     2,      110},
42777         {"cvmx_agl_gmx_rx#_stats_ctl"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     23,     2,      112},
42778         {"cvmx_agl_gmx_rx#_stats_octs" ,        CVMX_CSR_DB_TYPE_RSL,   64,     24,     2,      114},
42779         {"cvmx_agl_gmx_rx#_stats_octs_ctl",     CVMX_CSR_DB_TYPE_RSL,   64,     25,     2,      116},
42780         {"cvmx_agl_gmx_rx#_stats_octs_dmac",    CVMX_CSR_DB_TYPE_RSL,   64,     26,     2,      118},
42781         {"cvmx_agl_gmx_rx#_stats_octs_drp",     CVMX_CSR_DB_TYPE_RSL,   64,     27,     2,      120},
42782         {"cvmx_agl_gmx_rx#_stats_pkts" ,        CVMX_CSR_DB_TYPE_RSL,   64,     28,     2,      122},
42783         {"cvmx_agl_gmx_rx#_stats_pkts_bad",     CVMX_CSR_DB_TYPE_RSL,   64,     29,     2,      124},
42784         {"cvmx_agl_gmx_rx#_stats_pkts_ctl",     CVMX_CSR_DB_TYPE_RSL,   64,     30,     2,      126},
42785         {"cvmx_agl_gmx_rx#_stats_pkts_dmac",    CVMX_CSR_DB_TYPE_RSL,   64,     31,     2,      128},
42786         {"cvmx_agl_gmx_rx#_stats_pkts_drp",     CVMX_CSR_DB_TYPE_RSL,   64,     32,     2,      130},
42787         {"cvmx_agl_gmx_rx#_udd_skp"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     33,     4,      132},
42788         {"cvmx_agl_gmx_rx_bp_drop#"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     34,     2,      136},
42789         {"cvmx_agl_gmx_rx_bp_off#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     35,     2,      138},
42790         {"cvmx_agl_gmx_rx_bp_on#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     36,     2,      140},
42791         {"cvmx_agl_gmx_rx_prt_info"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     37,     4,      142},
42792         {"cvmx_agl_gmx_rx_tx_status"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     38,     4,      146},
42793         {"cvmx_agl_gmx_smac#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     39,     2,      150},
42794         {"cvmx_agl_gmx_stat_bp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     40,     3,      152},
42795         {"cvmx_agl_gmx_tx#_append"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     41,     5,      155},
42796         {"cvmx_agl_gmx_tx#_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     42,     3,      160},
42797         {"cvmx_agl_gmx_tx#_min_pkt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     43,     2,      163},
42798         {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL,   64,     44,     2,      165},
42799         {"cvmx_agl_gmx_tx#_pause_pkt_time",     CVMX_CSR_DB_TYPE_RSL,   64,     45,     2,      167},
42800         {"cvmx_agl_gmx_tx#_pause_togo" ,        CVMX_CSR_DB_TYPE_RSL,   64,     46,     2,      169},
42801         {"cvmx_agl_gmx_tx#_pause_zero" ,        CVMX_CSR_DB_TYPE_RSL,   64,     47,     2,      171},
42802         {"cvmx_agl_gmx_tx#_soft_pause" ,        CVMX_CSR_DB_TYPE_RSL,   64,     48,     2,      173},
42803         {"cvmx_agl_gmx_tx#_stat0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     49,     2,      175},
42804         {"cvmx_agl_gmx_tx#_stat1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     50,     2,      177},
42805         {"cvmx_agl_gmx_tx#_stat2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     51,     2,      179},
42806         {"cvmx_agl_gmx_tx#_stat3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     52,     2,      181},
42807         {"cvmx_agl_gmx_tx#_stat4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     53,     2,      183},
42808         {"cvmx_agl_gmx_tx#_stat5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     54,     2,      185},
42809         {"cvmx_agl_gmx_tx#_stat6"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     55,     2,      187},
42810         {"cvmx_agl_gmx_tx#_stat7"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     56,     2,      189},
42811         {"cvmx_agl_gmx_tx#_stat8"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     57,     2,      191},
42812         {"cvmx_agl_gmx_tx#_stat9"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     58,     2,      193},
42813         {"cvmx_agl_gmx_tx#_stats_ctl"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     59,     2,      195},
42814         {"cvmx_agl_gmx_tx#_thresh"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     60,     2,      197},
42815         {"cvmx_agl_gmx_tx_bp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     61,     2,      199},
42816         {"cvmx_agl_gmx_tx_col_attempt" ,        CVMX_CSR_DB_TYPE_RSL,   64,     62,     2,      201},
42817         {"cvmx_agl_gmx_tx_ifg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     63,     3,      203},
42818         {"cvmx_agl_gmx_tx_int_en"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     64,     10,     206},
42819         {"cvmx_agl_gmx_tx_int_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     65,     10,     216},
42820         {"cvmx_agl_gmx_tx_jam"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     66,     2,      226},
42821         {"cvmx_agl_gmx_tx_lfsr"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     67,     2,      228},
42822         {"cvmx_agl_gmx_tx_ovr_bp"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     68,     6,      230},
42823         {"cvmx_agl_gmx_tx_pause_pkt_dmac",      CVMX_CSR_DB_TYPE_RSL,   64,     69,     2,      236},
42824         {"cvmx_agl_gmx_tx_pause_pkt_type",      CVMX_CSR_DB_TYPE_RSL,   64,     70,     2,      238},
42825         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     71,     2,      240},
42826         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     72,     2,      242},
42827         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     73,     2,      244},
42828         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     74,     2,      246},
42829         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     75,     21,     248},
42830         {"cvmx_ciu_int#_en0_w1c"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     100,    21,     269},
42831         {"cvmx_ciu_int#_en0_w1s"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     125,    21,     290},
42832         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     150,    2,      311},
42833         {"cvmx_ciu_int#_en1_w1c"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     175,    2,      313},
42834         {"cvmx_ciu_int#_en1_w1s"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     200,    2,      315},
42835         {"cvmx_ciu_int#_en4_0"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     225,    21,     317},
42836         {"cvmx_ciu_int#_en4_0_w1c"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     237,    21,     338},
42837         {"cvmx_ciu_int#_en4_0_w1s"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     249,    21,     359},
42838         {"cvmx_ciu_int#_en4_1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     261,    2,      380},
42839         {"cvmx_ciu_int#_en4_1_w1c"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     273,    2,      382},
42840         {"cvmx_ciu_int#_en4_1_w1s"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     285,    2,      384},
42841         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     297,    21,     386},
42842         {"cvmx_ciu_int#_sum4"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     322,    21,     407},
42843         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     334,    2,      428},
42844         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     335,    2,      430},
42845         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     347,    2,      432},
42846         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     359,    2,      434},
42847         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     360,    2,      436},
42848         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     361,    2,      438},
42849         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     362,    1,      440},
42850         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     374,    3,      441},
42851         {"cvmx_ciu_qlm_dcok"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     375,    2,      444},
42852         {"cvmx_ciu_qlm_jtgc"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     376,    5,      446},
42853         {"cvmx_ciu_qlm_jtgd"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     377,    8,      451},
42854         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     378,    2,      459},
42855         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     379,    2,      461},
42856         {"cvmx_ciu_soft_prst1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     380,    2,      463},
42857         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     381,    2,      465},
42858         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     382,    3,      467},
42859         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     386,    7,      470},
42860         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     398,    6,      477},
42861         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     399,    7,      483},
42862         {"cvmx_fpa_fpf#_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     400,    3,      490},
42863         {"cvmx_fpa_fpf#_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     407,    2,      493},
42864         {"cvmx_fpa_fpf0_marks"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     414,    3,      495},
42865         {"cvmx_fpa_fpf0_size"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     415,    2,      498},
42866         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     416,    29,     500},
42867         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     417,    29,     529},
42868         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     418,    2,      558},
42869         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     426,    2,      560},
42870         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     434,    3,      562},
42871         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     435,    3,      565},
42872         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     436,    2,      568},
42873         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     437,    2,      570},
42874         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     438,    7,      572},
42875         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     440,    2,      579},
42876         {"cvmx_gmx#_clk_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     442,    2,      581},
42877         {"cvmx_gmx#_hg2_control"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     444,    5,      583},
42878         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     446,    7,      588},
42879         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     448,    2,      595},
42880         {"cvmx_gmx#_prt#_cbfc_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     450,    8,      597},
42881         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     452,    10,     605},
42882         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     460,    1,      615},
42883         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     468,    1,      616},
42884         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     476,    1,      617},
42885         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     484,    1,      618},
42886         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     492,    1,      619},
42887         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     500,    1,      620},
42888         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     508,    2,      621},
42889         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     516,    4,      623},
42890         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     524,    2,      627},
42891         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     532,    9,      629},
42892         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     540,    11,     638},
42893         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     548,    2,      649},
42894         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     556,    27,     651},
42895         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     564,    27,     678},
42896         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     572,    2,      705},
42897         {"cvmx_gmx#_rx#_pause_drop_time",       CVMX_CSR_DB_TYPE_RSL,   64,     580,    2,      707},
42898         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     588,    2,      709},
42899         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     596,    2,      711},
42900         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     604,    2,      713},
42901         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     612,    2,      715},
42902         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     620,    2,      717},
42903         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     628,    2,      719},
42904         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     636,    2,      721},
42905         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     644,    2,      723},
42906         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     652,    2,      725},
42907         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     660,    2,      727},
42908         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     668,    4,      729},
42909         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     676,    2,      733},
42910         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     684,    2,      735},
42911         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     692,    2,      737},
42912         {"cvmx_gmx#_rx_hg2_status"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     700,    4,      739},
42913         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     702,    4,      743},
42914         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     704,    2,      747},
42915         {"cvmx_gmx#_rx_xaui_bad_col"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     706,    5,      749},
42916         {"cvmx_gmx#_rx_xaui_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     708,    2,      754},
42917         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     710,    2,      756},
42918         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     718,    3,      758},
42919         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     720,    5,      761},
42920         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     728,    2,      766},
42921         {"cvmx_gmx#_tx#_cbfc_xoff"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     736,    2,      768},
42922         {"cvmx_gmx#_tx#_cbfc_xon"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     738,    2,      770},
42923         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     740,    3,      772},
42924         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     748,    2,      775},
42925         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     756,    2,      777},
42926         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     764,    2,      779},
42927         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     772,    3,      781},
42928         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     780,    2,      784},
42929         {"cvmx_gmx#_tx#_sgmii_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     788,    2,      786},
42930         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     796,    2,      788},
42931         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     804,    2,      790},
42932         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     812,    2,      792},
42933         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     820,    2,      794},
42934         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     828,    2,      796},
42935         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     836,    2,      798},
42936         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     844,    2,      800},
42937         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     852,    2,      802},
42938         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     860,    2,      804},
42939         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     868,    2,      806},
42940         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     876,    2,      808},
42941         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     884,    2,      810},
42942         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     892,    2,      812},
42943         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     900,    2,      814},
42944         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     908,    2,      816},
42945         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     910,    2,      818},
42946         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     912,    2,      820},
42947         {"cvmx_gmx#_tx_hg2_reg1"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     914,    2,      822},
42948         {"cvmx_gmx#_tx_hg2_reg2"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     916,    2,      824},
42949         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     918,    3,      826},
42950         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     920,    8,      829},
42951         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     922,    8,      837},
42952         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     924,    2,      845},
42953         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     926,    2,      847},
42954         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     928,    6,      849},
42955         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     930,    2,      855},
42956         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     932,    2,      857},
42957         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     934,    2,      859},
42958         {"cvmx_gmx#_tx_xaui_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     936,    9,      861},
42959         {"cvmx_gmx#_xaui_ext_loopback" ,        CVMX_CSR_DB_TYPE_RSL,   64,     938,    3,      870},
42960         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     940,    9,      873},
42961         {"cvmx_gpio_clk_gen#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     956,    2,      882},
42962         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     960,    2,      884},
42963         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     961,    2,      886},
42964         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     962,    2,      888},
42965         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     963,    2,      890},
42966         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     964,    19,     892},
42967         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     965,    6,      911},
42968         {"cvmx_iob_dwb_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     966,    3,      917},
42969         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     967,    3,      920},
42970         {"cvmx_iob_i2c_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     968,    3,      923},
42971         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     969,    5,      926},
42972         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     970,    5,      931},
42973         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     971,    1,      936},
42974         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     972,    1,      937},
42975         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     973,    7,      938},
42976         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     974,    7,      945},
42977         {"cvmx_iob_n2c_l2c_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     975,    3,      952},
42978         {"cvmx_iob_n2c_rsp_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     976,    3,      955},
42979         {"cvmx_iob_outb_com_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     977,    3,      958},
42980         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     978,    5,      961},
42981         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     979,    5,      966},
42982         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     980,    1,      971},
42983         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     981,    1,      972},
42984         {"cvmx_iob_outb_fpa_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     982,    3,      973},
42985         {"cvmx_iob_outb_req_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     983,    3,      976},
42986         {"cvmx_iob_p2c_req_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     984,    3,      979},
42987         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     985,    2,      982},
42988         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     986,    2,      984},
42989         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     987,    2,      986},
42990         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     988,    2,      988},
42991         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     989,    19,     990},
42992         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     990,    2,      1009},
42993         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     991,    1,      1011},
42994         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     992,    15,     1012},
42995         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     993,    13,     1027},
42996         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     994,    13,     1040},
42997         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     995,    2,      1053},
42998         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     996,    2,      1055},
42999         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     997,    2,      1057},
43000         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     998,    3,      1059},
43001         {"cvmx_ipd_port#_bp_page_cnt2" ,        CVMX_CSR_DB_TYPE_NCB,   64,     1010,   3,      1062},
43002         {"cvmx_ipd_port_bp_counters2_pair#",    CVMX_CSR_DB_TYPE_NCB,   64,     1014,   2,      1065},
43003         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     1018,   2,      1067},
43004         {"cvmx_ipd_port_qos_#_cnt"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1030,   2,      1069},
43005         {"cvmx_ipd_port_qos_int#"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1158,   1,      1071},
43006         {"cvmx_ipd_port_qos_int_enb#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     1161,   1,      1072},
43007         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     1164,   6,      1073},
43008         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     1165,   5,      1079},
43009         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1166,   6,      1084},
43010         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1167,   7,      1090},
43011         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1168,   2,      1097},
43012         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     1176,   2,      1099},
43013         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1177,   3,      1101},
43014         {"cvmx_ipd_red_port_enable2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1178,   2,      1104},
43015         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     1179,   5,      1106},
43016         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     1187,   3,      1111},
43017         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1188,   4,      1114},
43018         {"cvmx_ipd_sub_port_qos_cnt"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1189,   3,      1118},
43019         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1190,   2,      1121},
43020         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     1191,   2,      1123},
43021         {"cvmx_key_bist_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1192,   4,      1125},
43022         {"cvmx_key_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1193,   3,      1129},
43023         {"cvmx_key_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1194,   5,      1132},
43024         {"cvmx_key_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1195,   5,      1137},
43025         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1196,   7,      1142},
43026         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1197,   11,     1149},
43027         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1198,   8,      1160},
43028         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1199,   15,     1168},
43029         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1200,   8,      1183},
43030         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1201,   5,      1191},
43031         {"cvmx_l2c_grpwrr0"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1202,   2,      1196},
43032         {"cvmx_l2c_grpwrr1"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1203,   2,      1198},
43033         {"cvmx_l2c_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1204,   10,     1200},
43034         {"cvmx_l2c_int_stat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1205,   10,     1210},
43035         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1206,   4,      1220},
43036         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1207,   2,      1224},
43037         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1208,   14,     1226},
43038         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1209,   19,     1240},
43039         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1210,   3,      1259},
43040         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1211,   3,      1262},
43041         {"cvmx_l2c_oob"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1212,   3,      1265},
43042         {"cvmx_l2c_oob1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1213,   6,      1268},
43043         {"cvmx_l2c_oob2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1214,   6,      1274},
43044         {"cvmx_l2c_oob3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1215,   6,      1280},
43045         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1216,   2,      1286},
43046         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1220,   17,     1288},
43047         {"cvmx_l2c_ppgrp"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1221,   13,     1305},
43048         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1222,   5,      1318},
43049         {"cvmx_l2c_spar1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1223,   5,      1323},
43050         {"cvmx_l2c_spar2"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1224,   5,      1328},
43051         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1225,   2,      1333},
43052         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1226,   3,      1335},
43053         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1227,   2,      1338},
43054         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1228,   2,      1340},
43055         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1229,   2,      1342},
43056         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1230,   7,      1344},
43057         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1231,   5,      1351},
43058         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1232,   3,      1356},
43059         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1233,   3,      1359},
43060         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1234,   2,      1362},
43061         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1235,   2,      1364},
43062         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1236,   2,      1366},
43063         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1237,   6,      1368},
43064         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1238,   14,     1374},
43065         {"cvmx_led_blink"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1239,   2,      1388},
43066         {"cvmx_led_clk_phase"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1240,   2,      1390},
43067         {"cvmx_led_cylon"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1241,   2,      1392},
43068         {"cvmx_led_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1242,   2,      1394},
43069         {"cvmx_led_en"                 ,        CVMX_CSR_DB_TYPE_RSL,   64,     1243,   2,      1396},
43070         {"cvmx_led_polarity"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1244,   2,      1398},
43071         {"cvmx_led_prt"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1245,   2,      1400},
43072         {"cvmx_led_prt_fmt"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1246,   2,      1402},
43073         {"cvmx_led_prt_status#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1247,   2,      1404},
43074         {"cvmx_led_udd_cnt#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1255,   2,      1406},
43075         {"cvmx_led_udd_dat#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1257,   2,      1408},
43076         {"cvmx_led_udd_dat_clr#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1259,   2,      1410},
43077         {"cvmx_led_udd_dat_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1261,   2,      1412},
43078         {"cvmx_lmc#_bist_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1263,   2,      1414},
43079         {"cvmx_lmc#_bist_result"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1265,   8,      1416},
43080         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1267,   7,      1424},
43081         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1269,   19,     1431},
43082         {"cvmx_lmc#_ctl1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1271,   8,      1450},
43083         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1273,   2,      1458},
43084         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1275,   2,      1460},
43085         {"cvmx_lmc#_dclk_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1277,   5,      1462},
43086         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1279,   18,     1467},
43087         {"cvmx_lmc#_delay_cfg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1281,   6,      1485},
43088         {"cvmx_lmc#_dll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1283,   5,      1491},
43089         {"cvmx_lmc#_dual_memcfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1285,   5,      1496},
43090         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1287,   5,      1501},
43091         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     1289,   6,      1506},
43092         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1291,   2,      1512},
43093         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1293,   2,      1514},
43094         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1295,   14,     1516},
43095         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1297,   9,      1530},
43096         {"cvmx_lmc#_nxm"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1299,   2,      1539},
43097         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1301,   2,      1541},
43098         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1303,   2,      1543},
43099         {"cvmx_lmc#_pll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1305,   13,     1545},
43100         {"cvmx_lmc#_pll_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1307,   6,      1558},
43101         {"cvmx_lmc#_read_level_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1309,   7,      1564},
43102         {"cvmx_lmc#_read_level_dbg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1311,   4,      1571},
43103         {"cvmx_lmc#_read_level_rank#"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1313,   11,     1575},
43104         {"cvmx_lmc#_rodt_comp_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1321,   6,      1586},
43105         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1323,   9,      1592},
43106         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1325,   5,      1601},
43107         {"cvmx_lmc#_wodt_ctl1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1327,   5,      1606},
43108         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1329,   5,      1611},
43109         {"cvmx_mio_boot_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1330,   3,      1616},
43110         {"cvmx_mio_boot_dma_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1331,   10,     1619},
43111         {"cvmx_mio_boot_dma_int#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1334,   3,      1629},
43112         {"cvmx_mio_boot_dma_int_en#"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1337,   3,      1632},
43113         {"cvmx_mio_boot_dma_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1340,   15,     1635},
43114         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1343,   3,      1650},
43115         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1344,   3,      1653},
43116         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1345,   3,      1656},
43117         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1346,   5,      1659},
43118         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1348,   1,      1664},
43119         {"cvmx_mio_boot_pin_defs"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1349,   8,      1665},
43120         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1350,   13,     1673},
43121         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1358,   13,     1686},
43122         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1366,   6,      1699},
43123         {"cvmx_mio_fus_bnk_dat#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1367,   1,      1705},
43124         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1371,   2,      1706},
43125         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1372,   2,      1708},
43126         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1373,   13,     1710},
43127         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1374,   8,      1723},
43128         {"cvmx_mio_fus_ema"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1375,   4,      1731},
43129         {"cvmx_mio_fus_pdf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1376,   1,      1735},
43130         {"cvmx_mio_fus_pll"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1377,   3,      1736},
43131         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1378,   2,      1739},
43132         {"cvmx_mio_fus_prog_times"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1379,   6,      1741},
43133         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1380,   7,      1747},
43134         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1381,   4,      1754},
43135         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1382,   2,      1758},
43136         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1383,   2,      1760},
43137         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1384,   13,     1762},
43138         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1386,   12,     1775},
43139         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1388,   3,      1787},
43140         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1390,   3,      1790},
43141         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1392,   2,      1793},
43142         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1394,   2,      1795},
43143         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1396,   2,      1797},
43144         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1398,   7,      1799},
43145         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1400,   2,      1806},
43146         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1402,   7,      1808},
43147         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1404,   4,      1815},
43148         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1406,   8,      1819},
43149         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1408,   9,      1827},
43150         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1410,   7,      1836},
43151         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1412,   9,      1843},
43152         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1414,   2,      1852},
43153         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1416,   2,      1854},
43154         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1418,   4,      1856},
43155         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1420,   2,      1860},
43156         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1422,   2,      1862},
43157         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1424,   2,      1864},
43158         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1426,   4,      1866},
43159         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1428,   2,      1870},
43160         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1430,   2,      1872},
43161         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1432,   2,      1874},
43162         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1434,   2,      1876},
43163         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1436,   2,      1878},
43164         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1438,   2,      1880},
43165         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1440,   6,      1882},
43166         {"cvmx_mix#_bist"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1442,   5,      1888},
43167         {"cvmx_mix#_ctl"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     1443,   8,      1893},
43168         {"cvmx_mix#_intena"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1444,   8,      1901},
43169         {"cvmx_mix#_ircnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1445,   2,      1909},
43170         {"cvmx_mix#_irhwm"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1446,   3,      1911},
43171         {"cvmx_mix#_iring1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1447,   5,      1914},
43172         {"cvmx_mix#_iring2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1448,   4,      1919},
43173         {"cvmx_mix#_isr"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     1449,   8,      1923},
43174         {"cvmx_mix#_orcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1450,   2,      1931},
43175         {"cvmx_mix#_orhwm"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1451,   2,      1933},
43176         {"cvmx_mix#_oring1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1452,   5,      1935},
43177         {"cvmx_mix#_oring2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1453,   4,      1940},
43178         {"cvmx_mix#_remcnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1454,   4,      1944},
43179         {"cvmx_npei_bar1_index#"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     1455,   5,      1948},
43180         {"cvmx_npei_bist_status"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1487,   58,     1953},
43181         {"cvmx_npei_bist_status2"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1488,   15,     2011},
43182         {"cvmx_npei_ctl_port0"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1489,   17,     2026},
43183         {"cvmx_npei_ctl_port1"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1490,   17,     2043},
43184         {"cvmx_npei_ctl_status"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1491,   10,     2060},
43185         {"cvmx_npei_ctl_status2"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1492,   11,     2070},
43186         {"cvmx_npei_data_out_cnt"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1493,   5,      2081},
43187         {"cvmx_npei_dbg_data"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1494,   8,      2086},
43188         {"cvmx_npei_dbg_select"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1495,   2,      2094},
43189         {"cvmx_npei_dma#_counts"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1496,   3,      2096},
43190         {"cvmx_npei_dma#_dbell"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     1501,   2,      2099},
43191         {"cvmx_npei_dma#_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1506,   4,      2101},
43192         {"cvmx_npei_dma#_naddr"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1511,   2,      2105},
43193         {"cvmx_npei_dma0_int_level"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1516,   2,      2107},
43194         {"cvmx_npei_dma1_int_level"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1517,   2,      2109},
43195         {"cvmx_npei_dma_cnts"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1518,   2,      2111},
43196         {"cvmx_npei_dma_control"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1519,   17,     2113},
43197         {"cvmx_npei_dma_pcie_req_num"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1520,   15,     2130},
43198         {"cvmx_npei_int_a_enb"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1521,   11,     2145},
43199         {"cvmx_npei_int_a_enb2"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1522,   11,     2156},
43200         {"cvmx_npei_int_a_sum"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1523,   11,     2167},
43201         {"cvmx_npei_int_enb"           ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1524,   64,     2178},
43202         {"cvmx_npei_int_enb2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1525,   63,     2242},
43203         {"cvmx_npei_int_info"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1526,   3,      2305},
43204         {"cvmx_npei_int_sum"           ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1527,   64,     2308},
43205         {"cvmx_npei_int_sum2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1528,   61,     2372},
43206         {"cvmx_npei_last_win_rdata0"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1529,   1,      2433},
43207         {"cvmx_npei_last_win_rdata1"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1530,   1,      2434},
43208         {"cvmx_npei_mem_access_ctl"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1531,   3,      2435},
43209         {"cvmx_npei_mem_access_subid#" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1532,   11,     2438},
43210         {"cvmx_npei_msi_enb0"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1548,   1,      2449},
43211         {"cvmx_npei_msi_enb1"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1549,   1,      2450},
43212         {"cvmx_npei_msi_enb2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1550,   1,      2451},
43213         {"cvmx_npei_msi_enb3"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1551,   1,      2452},
43214         {"cvmx_npei_msi_rcv0"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1552,   1,      2453},
43215         {"cvmx_npei_msi_rcv1"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1553,   1,      2454},
43216         {"cvmx_npei_msi_rcv2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1554,   1,      2455},
43217         {"cvmx_npei_msi_rcv3"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1555,   1,      2456},
43218         {"cvmx_npei_msi_rd_map"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1556,   3,      2457},
43219         {"cvmx_npei_msi_w1c_enb0"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1557,   1,      2460},
43220         {"cvmx_npei_msi_w1c_enb1"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1558,   1,      2461},
43221         {"cvmx_npei_msi_w1c_enb2"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1559,   1,      2462},
43222         {"cvmx_npei_msi_w1c_enb3"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1560,   1,      2463},
43223         {"cvmx_npei_msi_w1s_enb0"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1561,   1,      2464},
43224         {"cvmx_npei_msi_w1s_enb1"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1562,   1,      2465},
43225         {"cvmx_npei_msi_w1s_enb2"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1563,   1,      2466},
43226         {"cvmx_npei_msi_w1s_enb3"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1564,   1,      2467},
43227         {"cvmx_npei_msi_wr_map"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1565,   3,      2468},
43228         {"cvmx_npei_pcie_credit_cnt"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1566,   7,      2471},
43229         {"cvmx_npei_pcie_msi_rcv"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1567,   2,      2478},
43230         {"cvmx_npei_pcie_msi_rcv_b1"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1568,   3,      2480},
43231         {"cvmx_npei_pcie_msi_rcv_b2"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1569,   3,      2483},
43232         {"cvmx_npei_pcie_msi_rcv_b3"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1570,   3,      2486},
43233         {"cvmx_npei_pkt#_cnts"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1571,   3,      2489},
43234         {"cvmx_npei_pkt#_in_bp"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1603,   2,      2492},
43235         {"cvmx_npei_pkt#_instr_baddr"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1635,   2,      2494},
43236         {"cvmx_npei_pkt#_instr_baoff_dbell",    CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1667,   2,      2496},
43237         {"cvmx_npei_pkt#_instr_fifo_rsize",     CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1699,   5,      2498},
43238         {"cvmx_npei_pkt#_instr_header" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1731,   13,     2503},
43239         {"cvmx_npei_pkt#_slist_baddr"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1763,   2,      2516},
43240         {"cvmx_npei_pkt#_slist_baoff_dbell",    CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1795,   2,      2518},
43241         {"cvmx_npei_pkt#_slist_fifo_rsize",     CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1827,   2,      2520},
43242         {"cvmx_npei_pkt_cnt_int"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1859,   2,      2522},
43243         {"cvmx_npei_pkt_cnt_int_enb"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1860,   2,      2524},
43244         {"cvmx_npei_pkt_data_out_es"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1861,   1,      2526},
43245         {"cvmx_npei_pkt_data_out_ns"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1862,   2,      2527},
43246         {"cvmx_npei_pkt_data_out_ror"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1863,   2,      2529},
43247         {"cvmx_npei_pkt_dpaddr"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1864,   2,      2531},
43248         {"cvmx_npei_pkt_in_bp"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1865,   2,      2533},
43249         {"cvmx_npei_pkt_in_done#_cnts" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1866,   2,      2535},
43250         {"cvmx_npei_pkt_in_instr_counts",       CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1898,   2,      2537},
43251         {"cvmx_npei_pkt_in_pcie_port"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1899,   1,      2539},
43252         {"cvmx_npei_pkt_input_control" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1900,   10,     2540},
43253         {"cvmx_npei_pkt_instr_enb"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1901,   2,      2550},
43254         {"cvmx_npei_pkt_instr_rd_size" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1902,   1,      2552},
43255         {"cvmx_npei_pkt_instr_size"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1903,   2,      2553},
43256         {"cvmx_npei_pkt_int_levels"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1904,   3,      2555},
43257         {"cvmx_npei_pkt_iptr"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1905,   2,      2558},
43258         {"cvmx_npei_pkt_out_bmode"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1906,   2,      2560},
43259         {"cvmx_npei_pkt_out_enb"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1907,   2,      2562},
43260         {"cvmx_npei_pkt_output_wmark"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1908,   2,      2564},
43261         {"cvmx_npei_pkt_pcie_port"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1909,   1,      2566},
43262         {"cvmx_npei_pkt_port_in_rst"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1910,   2,      2567},
43263         {"cvmx_npei_pkt_slist_es"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1911,   1,      2569},
43264         {"cvmx_npei_pkt_slist_id_size" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1912,   3,      2570},
43265         {"cvmx_npei_pkt_slist_ns"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1913,   2,      2573},
43266         {"cvmx_npei_pkt_slist_ror"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1914,   2,      2575},
43267         {"cvmx_npei_pkt_time_int"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1915,   2,      2577},
43268         {"cvmx_npei_pkt_time_int_enb"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1916,   2,      2579},
43269         {"cvmx_npei_rsl_int_blocks"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1917,   29,     2581},
43270         {"cvmx_npei_scratch_1"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1918,   1,      2610},
43271         {"cvmx_npei_state1"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1919,   4,      2611},
43272         {"cvmx_npei_state2"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1920,   7,      2615},
43273         {"cvmx_npei_state3"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1921,   5,      2622},
43274         {"cvmx_npei_win_rd_addr"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1922,   4,      2627},
43275         {"cvmx_npei_win_rd_data"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1923,   1,      2631},
43276         {"cvmx_npei_win_wr_addr"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1924,   4,      2632},
43277         {"cvmx_npei_win_wr_data"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1925,   1,      2636},
43278         {"cvmx_npei_win_wr_mask"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1926,   2,      2637},
43279         {"cvmx_npei_window_ctl"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1927,   2,      2639},
43280         {"cvmx_pcieep_cfg000"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1928,   2,      2641},
43281         {"cvmx_pcieep_cfg001"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1929,   24,     2643},
43282         {"cvmx_pcieep_cfg002"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1930,   4,      2667},
43283         {"cvmx_pcieep_cfg003"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1931,   5,      2671},
43284         {"cvmx_pcieep_cfg004"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1932,   5,      2676},
43285         {"cvmx_pcieep_cfg004_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1933,   2,      2681},
43286         {"cvmx_pcieep_cfg005"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1934,   1,      2683},
43287         {"cvmx_pcieep_cfg005_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1935,   1,      2684},
43288         {"cvmx_pcieep_cfg006"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1936,   5,      2685},
43289         {"cvmx_pcieep_cfg006_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1937,   2,      2690},
43290         {"cvmx_pcieep_cfg007"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1938,   1,      2692},
43291         {"cvmx_pcieep_cfg007_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1939,   1,      2693},
43292         {"cvmx_pcieep_cfg008"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1940,   4,      2694},
43293         {"cvmx_pcieep_cfg008_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1941,   2,      2698},
43294         {"cvmx_pcieep_cfg009"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1942,   2,      2700},
43295         {"cvmx_pcieep_cfg009_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1943,   1,      2702},
43296         {"cvmx_pcieep_cfg010"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1944,   1,      2703},
43297         {"cvmx_pcieep_cfg011"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1945,   2,      2704},
43298         {"cvmx_pcieep_cfg012"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1946,   3,      2706},
43299         {"cvmx_pcieep_cfg012_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1947,   2,      2709},
43300         {"cvmx_pcieep_cfg013"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1948,   2,      2711},
43301         {"cvmx_pcieep_cfg015"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1949,   4,      2713},
43302         {"cvmx_pcieep_cfg016"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1950,   10,     2717},
43303         {"cvmx_pcieep_cfg017"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1951,   12,     2727},
43304         {"cvmx_pcieep_cfg020"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1952,   7,      2739},
43305         {"cvmx_pcieep_cfg021"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1953,   2,      2746},
43306         {"cvmx_pcieep_cfg022"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1954,   1,      2748},
43307         {"cvmx_pcieep_cfg023"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1955,   2,      2749},
43308         {"cvmx_pcieep_cfg028"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1956,   7,      2751},
43309         {"cvmx_pcieep_cfg029"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1957,   11,     2758},
43310         {"cvmx_pcieep_cfg030"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1958,   19,     2769},
43311         {"cvmx_pcieep_cfg031"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1959,   11,     2788},
43312         {"cvmx_pcieep_cfg032"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1960,   17,     2799},
43313         {"cvmx_pcieep_cfg033"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1961,   12,     2816},
43314         {"cvmx_pcieep_cfg034"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1962,   22,     2828},
43315         {"cvmx_pcieep_cfg037"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1963,   3,      2850},
43316         {"cvmx_pcieep_cfg038"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1964,   3,      2853},
43317         {"cvmx_pcieep_cfg039"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1965,   1,      2856},
43318         {"cvmx_pcieep_cfg040"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1966,   1,      2857},
43319         {"cvmx_pcieep_cfg041"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1967,   1,      2858},
43320         {"cvmx_pcieep_cfg042"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1968,   1,      2859},
43321         {"cvmx_pcieep_cfg064"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1969,   3,      2860},
43322         {"cvmx_pcieep_cfg065"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1970,   14,     2863},
43323         {"cvmx_pcieep_cfg066"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1971,   14,     2877},
43324         {"cvmx_pcieep_cfg067"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1972,   14,     2891},
43325         {"cvmx_pcieep_cfg068"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1973,   9,      2905},
43326         {"cvmx_pcieep_cfg069"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1974,   9,      2914},
43327         {"cvmx_pcieep_cfg070"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1975,   6,      2923},
43328         {"cvmx_pcieep_cfg071"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1976,   1,      2929},
43329         {"cvmx_pcieep_cfg072"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1977,   1,      2930},
43330         {"cvmx_pcieep_cfg073"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1978,   1,      2931},
43331         {"cvmx_pcieep_cfg074"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1979,   1,      2932},
43332         {"cvmx_pcieep_cfg448"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1980,   2,      2933},
43333         {"cvmx_pcieep_cfg449"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1981,   1,      2935},
43334         {"cvmx_pcieep_cfg450"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1982,   6,      2936},
43335         {"cvmx_pcieep_cfg451"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1983,   6,      2942},
43336         {"cvmx_pcieep_cfg452"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1984,   13,     2948},
43337         {"cvmx_pcieep_cfg453"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1985,   5,      2961},
43338         {"cvmx_pcieep_cfg454"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1986,   8,      2966},
43339         {"cvmx_pcieep_cfg455"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1987,   19,     2974},
43340         {"cvmx_pcieep_cfg456"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1988,   3,      2993},
43341         {"cvmx_pcieep_cfg458"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1989,   1,      2996},
43342         {"cvmx_pcieep_cfg459"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1990,   1,      2997},
43343         {"cvmx_pcieep_cfg460"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1991,   3,      2998},
43344         {"cvmx_pcieep_cfg461"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1992,   3,      3001},
43345         {"cvmx_pcieep_cfg462"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1993,   3,      3004},
43346         {"cvmx_pcieep_cfg463"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1994,   4,      3007},
43347         {"cvmx_pcieep_cfg464"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1995,   4,      3011},
43348         {"cvmx_pcieep_cfg465"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1996,   4,      3015},
43349         {"cvmx_pcieep_cfg466"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1997,   7,      3019},
43350         {"cvmx_pcieep_cfg467"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1998,   5,      3026},
43351         {"cvmx_pcieep_cfg468"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1999,   5,      3031},
43352         {"cvmx_pcieep_cfg490"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     2000,   4,      3036},
43353         {"cvmx_pcieep_cfg491"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     2001,   4,      3040},
43354         {"cvmx_pcieep_cfg492"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     2002,   4,      3044},
43355         {"cvmx_pcieep_cfg516"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     2003,   1,      3048},
43356         {"cvmx_pcieep_cfg517"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     2004,   1,      3049},
43357         {"cvmx_pcierc#_cfg000"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2005,   2,      3050},
43358         {"cvmx_pcierc#_cfg001"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2007,   24,     3052},
43359         {"cvmx_pcierc#_cfg002"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2009,   4,      3076},
43360         {"cvmx_pcierc#_cfg003"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2011,   5,      3080},
43361         {"cvmx_pcierc#_cfg004"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2013,   1,      3085},
43362         {"cvmx_pcierc#_cfg005"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2015,   1,      3086},
43363         {"cvmx_pcierc#_cfg006"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2017,   4,      3087},
43364         {"cvmx_pcierc#_cfg007"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2019,   17,     3091},
43365         {"cvmx_pcierc#_cfg008"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2021,   4,      3108},
43366         {"cvmx_pcierc#_cfg009"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2023,   6,      3112},
43367         {"cvmx_pcierc#_cfg010"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2025,   1,      3118},
43368         {"cvmx_pcierc#_cfg011"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2027,   1,      3119},
43369         {"cvmx_pcierc#_cfg012"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2029,   2,      3120},
43370         {"cvmx_pcierc#_cfg013"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2031,   2,      3122},
43371         {"cvmx_pcierc#_cfg014"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2033,   1,      3124},
43372         {"cvmx_pcierc#_cfg015"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2035,   15,     3125},
43373         {"cvmx_pcierc#_cfg016"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2037,   10,     3140},
43374         {"cvmx_pcierc#_cfg017"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2039,   12,     3150},
43375         {"cvmx_pcierc#_cfg020"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2041,   7,      3162},
43376         {"cvmx_pcierc#_cfg021"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2043,   2,      3169},
43377         {"cvmx_pcierc#_cfg022"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2045,   1,      3171},
43378         {"cvmx_pcierc#_cfg023"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2047,   2,      3172},
43379         {"cvmx_pcierc#_cfg028"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2049,   7,      3174},
43380         {"cvmx_pcierc#_cfg029"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2051,   11,     3181},
43381         {"cvmx_pcierc#_cfg030"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2053,   19,     3192},
43382         {"cvmx_pcierc#_cfg031"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2055,   11,     3211},
43383         {"cvmx_pcierc#_cfg032"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2057,   20,     3222},
43384         {"cvmx_pcierc#_cfg033"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2059,   12,     3242},
43385         {"cvmx_pcierc#_cfg034"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2061,   22,     3254},
43386         {"cvmx_pcierc#_cfg035"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2063,   8,      3276},
43387         {"cvmx_pcierc#_cfg036"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2065,   4,      3284},
43388         {"cvmx_pcierc#_cfg037"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2067,   3,      3288},
43389         {"cvmx_pcierc#_cfg038"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2069,   3,      3291},
43390         {"cvmx_pcierc#_cfg039"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2071,   1,      3294},
43391         {"cvmx_pcierc#_cfg040"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2073,   1,      3295},
43392         {"cvmx_pcierc#_cfg041"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2075,   1,      3296},
43393         {"cvmx_pcierc#_cfg042"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2077,   1,      3297},
43394         {"cvmx_pcierc#_cfg064"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2079,   3,      3298},
43395         {"cvmx_pcierc#_cfg065"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2081,   14,     3301},
43396         {"cvmx_pcierc#_cfg066"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2083,   14,     3315},
43397         {"cvmx_pcierc#_cfg067"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2085,   14,     3329},
43398         {"cvmx_pcierc#_cfg068"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2087,   9,      3343},
43399         {"cvmx_pcierc#_cfg069"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2089,   9,      3352},
43400         {"cvmx_pcierc#_cfg070"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2091,   6,      3361},
43401         {"cvmx_pcierc#_cfg071"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2093,   1,      3367},
43402         {"cvmx_pcierc#_cfg072"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2095,   1,      3368},
43403         {"cvmx_pcierc#_cfg073"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2097,   1,      3369},
43404         {"cvmx_pcierc#_cfg074"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2099,   1,      3370},
43405         {"cvmx_pcierc#_cfg075"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2101,   4,      3371},
43406         {"cvmx_pcierc#_cfg076"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2103,   9,      3375},
43407         {"cvmx_pcierc#_cfg077"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2105,   2,      3384},
43408         {"cvmx_pcierc#_cfg448"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2107,   2,      3386},
43409         {"cvmx_pcierc#_cfg449"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2109,   1,      3388},
43410         {"cvmx_pcierc#_cfg450"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2111,   6,      3389},
43411         {"cvmx_pcierc#_cfg451"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2113,   6,      3395},
43412         {"cvmx_pcierc#_cfg452"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2115,   13,     3401},
43413         {"cvmx_pcierc#_cfg453"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2117,   5,      3414},
43414         {"cvmx_pcierc#_cfg454"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2119,   8,      3419},
43415         {"cvmx_pcierc#_cfg455"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2121,   19,     3427},
43416         {"cvmx_pcierc#_cfg456"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2123,   3,      3446},
43417         {"cvmx_pcierc#_cfg458"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2125,   1,      3449},
43418         {"cvmx_pcierc#_cfg459"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2127,   1,      3450},
43419         {"cvmx_pcierc#_cfg460"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2129,   3,      3451},
43420         {"cvmx_pcierc#_cfg461"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2131,   3,      3454},
43421         {"cvmx_pcierc#_cfg462"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2133,   3,      3457},
43422         {"cvmx_pcierc#_cfg463"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2135,   4,      3460},
43423         {"cvmx_pcierc#_cfg464"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2137,   4,      3464},
43424         {"cvmx_pcierc#_cfg465"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2139,   4,      3468},
43425         {"cvmx_pcierc#_cfg466"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2141,   7,      3472},
43426         {"cvmx_pcierc#_cfg467"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2143,   5,      3479},
43427         {"cvmx_pcierc#_cfg468"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2145,   5,      3484},
43428         {"cvmx_pcierc#_cfg490"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2147,   4,      3489},
43429         {"cvmx_pcierc#_cfg491"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2149,   4,      3493},
43430         {"cvmx_pcierc#_cfg492"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2151,   4,      3497},
43431         {"cvmx_pcierc#_cfg516"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2153,   1,      3501},
43432         {"cvmx_pcierc#_cfg517"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     2155,   1,      3502},
43433         {"cvmx_pcs#_an#_adv_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2157,   9,      3503},
43434         {"cvmx_pcs#_an#_ext_st_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2165,   6,      3512},
43435         {"cvmx_pcs#_an#_lp_abil_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     2173,   9,      3518},
43436         {"cvmx_pcs#_an#_results_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     2181,   6,      3527},
43437         {"cvmx_pcs#_int#_en_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2189,   13,     3533},
43438         {"cvmx_pcs#_int#_reg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2197,   13,     3546},
43439         {"cvmx_pcs#_link#_timer_count_reg",     CVMX_CSR_DB_TYPE_RSL,   64,     2205,   2,      3559},
43440         {"cvmx_pcs#_log_anl#_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2213,   4,      3561},
43441         {"cvmx_pcs#_misc#_ctl_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2221,   8,      3565},
43442         {"cvmx_pcs#_mr#_control_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     2229,   13,     3573},
43443         {"cvmx_pcs#_mr#_status_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2237,   17,     3586},
43444         {"cvmx_pcs#_rx#_states_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2245,   7,      3603},
43445         {"cvmx_pcs#_rx#_sync_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2253,   3,      3610},
43446         {"cvmx_pcs#_sgm#_an_adv_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     2261,   8,      3613},
43447         {"cvmx_pcs#_sgm#_lp_adv_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     2269,   7,      3621},
43448         {"cvmx_pcs#_tx#_states_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2277,   4,      3628},
43449         {"cvmx_pcs#_tx_rx#_polarity_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     2285,   5,      3632},
43450         {"cvmx_pcsx#_10gbx_status_reg" ,        CVMX_CSR_DB_TYPE_RSL,   64,     2293,   8,      3637},
43451         {"cvmx_pcsx#_bist_status_reg"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2295,   2,      3645},
43452         {"cvmx_pcsx#_bit_lock_status_reg",      CVMX_CSR_DB_TYPE_RSL,   64,     2297,   5,      3647},
43453         {"cvmx_pcsx#_control1_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2299,   10,     3652},
43454         {"cvmx_pcsx#_control2_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2301,   2,      3662},
43455         {"cvmx_pcsx#_int_en_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2303,   7,      3664},
43456         {"cvmx_pcsx#_int_reg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2305,   7,      3671},
43457         {"cvmx_pcsx#_log_anl_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2307,   6,      3678},
43458         {"cvmx_pcsx#_misc_ctl_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2309,   5,      3684},
43459         {"cvmx_pcsx#_rx_sync_states_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     2311,   5,      3689},
43460         {"cvmx_pcsx#_spd_abil_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2313,   3,      3694},
43461         {"cvmx_pcsx#_status1_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2315,   6,      3697},
43462         {"cvmx_pcsx#_status2_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2317,   9,      3703},
43463         {"cvmx_pcsx#_tx_rx_polarity_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     2319,   5,      3712},
43464         {"cvmx_pcsx#_tx_rx_states_reg" ,        CVMX_CSR_DB_TYPE_RSL,   64,     2321,   10,     3717},
43465         {"cvmx_pesc#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2323,   14,     3727},
43466         {"cvmx_pesc#_bist_status2"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2325,   15,     3741},
43467         {"cvmx_pesc#_cfg_rd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2327,   2,      3756},
43468         {"cvmx_pesc#_cfg_wr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2329,   2,      3758},
43469         {"cvmx_pesc#_cpl_lut_valid"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2331,   2,      3760},
43470         {"cvmx_pesc#_ctl_status"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2333,   16,     3762},
43471         {"cvmx_pesc#_ctl_status2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2335,   3,      3778},
43472         {"cvmx_pesc#_dbg_info"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2337,   32,     3781},
43473         {"cvmx_pesc#_dbg_info_en"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2339,   32,     3813},
43474         {"cvmx_pesc#_diag_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2341,   5,      3845},
43475         {"cvmx_pesc#_p2n_bar0_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     2343,   2,      3850},
43476         {"cvmx_pesc#_p2n_bar1_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     2345,   2,      3852},
43477         {"cvmx_pesc#_p2n_bar2_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     2347,   2,      3854},
43478         {"cvmx_pesc#_p2p_bar#_end"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2349,   2,      3856},
43479         {"cvmx_pesc#_p2p_bar#_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     2357,   2,      3858},
43480         {"cvmx_pesc#_tlp_credits"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2365,   8,      3860},
43481         {"cvmx_pip_bck_prs"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2367,   5,      3868},
43482         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2368,   2,      3873},
43483         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2369,   4,      3875},
43484         {"cvmx_pip_dsa_src_grp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2373,   16,     3879},
43485         {"cvmx_pip_dsa_vid_grp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2374,   16,     3895},
43486         {"cvmx_pip_frm_len_chk#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2375,   3,      3911},
43487         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2377,   8,      3914},
43488         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2378,   22,     3922},
43489         {"cvmx_pip_hg_pri_qos"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2379,   6,      3944},
43490         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     2380,   14,     3950},
43491         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2381,   14,     3964},
43492         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2382,   2,      3978},
43493         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2383,   28,     3980},
43494         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2399,   25,     4008},
43495         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2415,   2,      4033},
43496         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2479,   4,      4035},
43497         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2487,   9,      4039},
43498         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2495,   2,      4048},
43499         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2496,   2,      4050},
43500         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2497,   2,      4052},
43501         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2513,   2,      4054},
43502         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2529,   2,      4056},
43503         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2545,   2,      4058},
43504         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2561,   2,      4060},
43505         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2577,   2,      4062},
43506         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2593,   2,      4064},
43507         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2609,   2,      4066},
43508         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2625,   2,      4068},
43509         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2641,   2,      4070},
43510         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2657,   2,      4072},
43511         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2658,   2,      4074},
43512         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2674,   2,      4076},
43513         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2690,   2,      4078},
43514         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2706,   2,      4080},
43515         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2770,   2,      4082},
43516         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2771,   3,      4084},
43517         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2772,   3,      4087},
43518         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2773,   2,      4090},
43519         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2774,   2,      4092},
43520         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2775,   4,      4094},
43521         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2776,   5,      4098},
43522         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2777,   4,      4103},
43523         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2778,   8,      4107},
43524         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2779,   4,      4115},
43525         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2780,   5,      4119},
43526         {"cvmx_pko_mem_debug14"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2781,   1,      4124},
43527         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2782,   5,      4125},
43528         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2783,   1,      4130},
43529         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2784,   13,     4131},
43530         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2785,   4,      4144},
43531         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2786,   13,     4148},
43532         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2787,   6,      4161},
43533         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2788,   9,      4167},
43534         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2789,   4,      4176},
43535         {"cvmx_pko_mem_port_ptrs"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2790,   7,      4180},
43536         {"cvmx_pko_mem_port_qos"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2791,   5,      4187},
43537         {"cvmx_pko_mem_port_rate0"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2792,   5,      4192},
43538         {"cvmx_pko_mem_port_rate1"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2793,   4,      4197},
43539         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2794,   9,      4201},
43540         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2795,   5,      4210},
43541         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2796,   16,     4215},
43542         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2797,   4,      4231},
43543         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2798,   1,      4235},
43544         {"cvmx_pko_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2799,   1,      4236},
43545         {"cvmx_pko_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2800,   1,      4237},
43546         {"cvmx_pko_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2801,   1,      4238},
43547         {"cvmx_pko_reg_engine_inflight",        CVMX_CSR_DB_TYPE_RSL,   64,     2802,   11,     4239},
43548         {"cvmx_pko_reg_engine_thresh"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2803,   2,      4250},
43549         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2804,   4,      4252},
43550         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2805,   5,      4256},
43551         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2806,   3,      4261},
43552         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2807,   4,      4264},
43553         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2808,   2,      4268},
43554         {"cvmx_pko_reg_queue_ptrs1"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2809,   3,      4270},
43555         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2810,   3,      4273},
43556         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2811,   13,     4276},
43557         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2812,   2,      4289},
43558         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2813,   13,     4291},
43559         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2814,   3,      4304},
43560         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2815,   2,      4307},
43561         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2823,   2,      4309},
43562         {"cvmx_pow_iq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2824,   2,      4311},
43563         {"cvmx_pow_iq_int_en"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2825,   2,      4313},
43564         {"cvmx_pow_iq_thr#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2826,   2,      4315},
43565         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2834,   2,      4317},
43566         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2835,   2,      4319},
43567         {"cvmx_pow_pf_rst_msk"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2836,   2,      4321},
43568         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2837,   10,     4323},
43569         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2849,   5,      4333},
43570         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2857,   8,      4338},
43571         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2865,   2,      4346},
43572         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2866,   2,      4348},
43573         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2867,   2,      4350},
43574         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2875,   3,      4352},
43575         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2876,   4,      4355},
43576         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2892,   5,      4359},
43577         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2893,   7,      4364},
43578         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2909,   2,      4371},
43579         {"cvmx_rad_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2925,   1,      4373},
43580         {"cvmx_rad_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2926,   1,      4374},
43581         {"cvmx_rad_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2927,   1,      4375},
43582         {"cvmx_rad_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2928,   5,      4376},
43583         {"cvmx_rad_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2929,   5,      4381},
43584         {"cvmx_rad_reg_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2930,   4,      4386},
43585         {"cvmx_rad_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2931,   10,     4390},
43586         {"cvmx_rad_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2932,   1,      4400},
43587         {"cvmx_rad_reg_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2933,   3,      4401},
43588         {"cvmx_rad_reg_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2934,   7,      4404},
43589         {"cvmx_rad_reg_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2935,   2,      4411},
43590         {"cvmx_rad_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2936,   1,      4413},
43591         {"cvmx_rad_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2937,   1,      4414},
43592         {"cvmx_rad_reg_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2938,   1,      4415},
43593         {"cvmx_rad_reg_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2939,   18,     4416},
43594         {"cvmx_rad_reg_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2940,   3,      4434},
43595         {"cvmx_rad_reg_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2941,   2,      4437},
43596         {"cvmx_rad_reg_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2942,   3,      4439},
43597         {"cvmx_rad_reg_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2943,   7,      4442},
43598         {"cvmx_rad_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2944,   2,      4449},
43599         {"cvmx_rad_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2945,   2,      4451},
43600         {"cvmx_rad_reg_polynomial"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2946,   2,      4453},
43601         {"cvmx_rad_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2947,   3,      4455},
43602         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2948,   3,      4458},
43603         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2949,   7,      4461},
43604         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2950,   10,     4468},
43605         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2952,   6,      4478},
43606         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2954,   2,      4484},
43607         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2956,   4,      4486},
43608         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2958,   4,      4490},
43609         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2960,   6,      4494},
43610         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2961,   3,      4500},
43611         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2962,   5,      4503},
43612         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2963,   4,      4508},
43613         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2964,   6,      4512},
43614         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2965,   4,      4518},
43615         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2966,   2,      4522},
43616         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2967,   4,      4524},
43617         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2968,   2,      4528},
43618         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2969,   3,      4530},
43619         {"cvmx_tra_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2970,   4,      4533},
43620         {"cvmx_tra_ctl"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2971,   12,     4537},
43621         {"cvmx_tra_cycles_since"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2972,   3,      4549},
43622         {"cvmx_tra_cycles_since1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2973,   5,      4552},
43623         {"cvmx_tra_filt_adr_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2974,   2,      4557},
43624         {"cvmx_tra_filt_adr_msk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2975,   2,      4559},
43625         {"cvmx_tra_filt_cmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2976,   18,     4561},
43626         {"cvmx_tra_filt_did"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2977,   12,     4579},
43627         {"cvmx_tra_filt_sid"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2978,   6,      4591},
43628         {"cvmx_tra_int_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2979,   5,      4597},
43629         {"cvmx_tra_read_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2980,   1,      4602},
43630         {"cvmx_tra_trig0_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2981,   2,      4603},
43631         {"cvmx_tra_trig0_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2982,   2,      4605},
43632         {"cvmx_tra_trig0_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2983,   18,     4607},
43633         {"cvmx_tra_trig0_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2984,   12,     4625},
43634         {"cvmx_tra_trig0_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2985,   6,      4637},
43635         {"cvmx_tra_trig1_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2986,   2,      4643},
43636         {"cvmx_tra_trig1_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2987,   2,      4645},
43637         {"cvmx_tra_trig1_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2988,   18,     4647},
43638         {"cvmx_tra_trig1_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2989,   12,     4665},
43639         {"cvmx_tra_trig1_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2990,   6,      4677},
43640         {"cvmx_usbc#_daint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     2991,   2,      4683},
43641         {"cvmx_usbc#_daintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2992,   2,      4685},
43642         {"cvmx_usbc#_dcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2993,   8,      4687},
43643         {"cvmx_usbc#_dctl"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2994,   11,     4695},
43644         {"cvmx_usbc#_diepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2995,   15,     4706},
43645         {"cvmx_usbc#_diepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3000,   8,      4721},
43646         {"cvmx_usbc#_diepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3005,   8,      4729},
43647         {"cvmx_usbc#_dieptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     3006,   4,      4737},
43648         {"cvmx_usbc#_doepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3011,   15,     4741},
43649         {"cvmx_usbc#_doepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3016,   6,      4756},
43650         {"cvmx_usbc#_doepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3021,   6,      4762},
43651         {"cvmx_usbc#_doeptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     3022,   4,      4768},
43652         {"cvmx_usbc#_dptxfsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     3027,   2,      4772},
43653         {"cvmx_usbc#_dsts"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     3031,   6,      4774},
43654         {"cvmx_usbc#_dtknqr1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3032,   4,      4780},
43655         {"cvmx_usbc#_dtknqr2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3033,   1,      4784},
43656         {"cvmx_usbc#_dtknqr3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3034,   1,      4785},
43657         {"cvmx_usbc#_dtknqr4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3035,   1,      4786},
43658         {"cvmx_usbc#_gahbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3036,   7,      4787},
43659         {"cvmx_usbc#_ghwcfg1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3037,   1,      4794},
43660         {"cvmx_usbc#_ghwcfg2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3038,   14,     4795},
43661         {"cvmx_usbc#_ghwcfg3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3039,   10,     4809},
43662         {"cvmx_usbc#_ghwcfg4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3040,   14,     4819},
43663         {"cvmx_usbc#_gintmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3041,   32,     4833},
43664         {"cvmx_usbc#_gintsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3042,   32,     4865},
43665         {"cvmx_usbc#_gnptxfsiz"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     3043,   2,      4897},
43666         {"cvmx_usbc#_gnptxsts"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3044,   4,      4899},
43667         {"cvmx_usbc#_gotgctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3045,   13,     4903},
43668         {"cvmx_usbc#_gotgint"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3046,   10,     4916},
43669         {"cvmx_usbc#_grstctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3047,   10,     4926},
43670         {"cvmx_usbc#_grxfsiz"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3048,   2,      4936},
43671         {"cvmx_usbc#_grxstspd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3049,   6,      4938},
43672         {"cvmx_usbc#_grxstsph"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3050,   5,      4944},
43673         {"cvmx_usbc#_grxstsrd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3051,   6,      4949},
43674         {"cvmx_usbc#_grxstsrh"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3052,   5,      4955},
43675         {"cvmx_usbc#_gsnpsid"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3053,   1,      4960},
43676         {"cvmx_usbc#_gusbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3054,   13,     4961},
43677         {"cvmx_usbc#_haint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     3055,   2,      4974},
43678         {"cvmx_usbc#_haintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3056,   2,      4976},
43679         {"cvmx_usbc#_hcchar#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3057,   11,     4978},
43680         {"cvmx_usbc#_hcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     3065,   3,      4989},
43681         {"cvmx_usbc#_hcint#"           ,        CVMX_CSR_DB_TYPE_NCB,   32,     3066,   12,     4992},
43682         {"cvmx_usbc#_hcintmsk#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     3074,   12,     5004},
43683         {"cvmx_usbc#_hcsplt#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3082,   6,      5016},
43684         {"cvmx_usbc#_hctsiz#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3090,   4,      5022},
43685         {"cvmx_usbc#_hfir"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     3098,   2,      5026},
43686         {"cvmx_usbc#_hfnum"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     3099,   2,      5028},
43687         {"cvmx_usbc#_hprt"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     3100,   15,     5030},
43688         {"cvmx_usbc#_hptxfsiz"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     3101,   2,      5045},
43689         {"cvmx_usbc#_hptxsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3102,   3,      5047},
43690         {"cvmx_usbc#_nptxdfifo#"       ,        CVMX_CSR_DB_TYPE_NCB,   32,     3103,   1,      5050},
43691         {"cvmx_usbc#_pcgcctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     3111,   6,      5051},
43692         {"cvmx_usbn#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     3112,   8,      5057},
43693         {"cvmx_usbn#_clk_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     3113,   15,     5065},
43694         {"cvmx_usbn#_ctl_status"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     3114,   6,      5080},
43695         {"cvmx_usbn#_dma0_inb_chn0"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     3115,   2,      5086},
43696         {"cvmx_usbn#_dma0_inb_chn1"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     3116,   2,      5088},
43697         {"cvmx_usbn#_dma0_inb_chn2"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     3117,   2,      5090},
43698         {"cvmx_usbn#_dma0_inb_chn3"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     3118,   2,      5092},
43699         {"cvmx_usbn#_dma0_inb_chn4"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     3119,   2,      5094},
43700         {"cvmx_usbn#_dma0_inb_chn5"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     3120,   2,      5096},
43701         {"cvmx_usbn#_dma0_inb_chn6"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     3121,   2,      5098},
43702         {"cvmx_usbn#_dma0_inb_chn7"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     3122,   2,      5100},
43703         {"cvmx_usbn#_dma0_outb_chn0"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     3123,   2,      5102},
43704         {"cvmx_usbn#_dma0_outb_chn1"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     3124,   2,      5104},
43705         {"cvmx_usbn#_dma0_outb_chn2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     3125,   2,      5106},
43706         {"cvmx_usbn#_dma0_outb_chn3"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     3126,   2,      5108},
43707         {"cvmx_usbn#_dma0_outb_chn4"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     3127,   2,      5110},
43708         {"cvmx_usbn#_dma0_outb_chn5"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     3128,   2,      5112},
43709         {"cvmx_usbn#_dma0_outb_chn6"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     3129,   2,      5114},
43710         {"cvmx_usbn#_dma0_outb_chn7"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     3130,   2,      5116},
43711         {"cvmx_usbn#_dma_test"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     3131,   7,      5118},
43712         {"cvmx_usbn#_int_enb"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     3132,   34,     5125},
43713         {"cvmx_usbn#_int_sum"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     3133,   34,     5159},
43714         {"cvmx_usbn#_usbp_ctl_status"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     3134,   35,     5193},
43715         {"cvmx_zip_cmd_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     3135,   3,      5228},
43716         {"cvmx_zip_cmd_buf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     3136,   5,      5231},
43717         {"cvmx_zip_cmd_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     3137,   3,      5236},
43718         {"cvmx_zip_constants"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     3138,   6,      5239},
43719         {"cvmx_zip_debug0"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     3139,   2,      5245},
43720         {"cvmx_zip_error"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     3140,   2,      5247},
43721         {"cvmx_zip_int_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     3141,   2,      5249},
43722         {NULL,0,0,0,0,0}
43723 };
43724 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn56xx[] = {
43725         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
43726         {"AGL_GMX_BAD_REG"             ,           0x11800E0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
43727         {"AGL_GMX_BIST"                ,           0x11800E0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
43728         {"AGL_GMX_DRV_CTL"             ,           0x11800E00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
43729         {"AGL_GMX_INF_MODE"            ,           0x11800E00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
43730         {"AGL_GMX_PRT0_CFG"            ,           0x11800E0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
43731         {"AGL_GMX_RX0_ADR_CAM0"        ,           0x11800E0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
43732         {"AGL_GMX_RX0_ADR_CAM1"        ,           0x11800E0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
43733         {"AGL_GMX_RX0_ADR_CAM2"        ,           0x11800E0000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
43734         {"AGL_GMX_RX0_ADR_CAM3"        ,           0x11800E0000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
43735         {"AGL_GMX_RX0_ADR_CAM4"        ,           0x11800E00001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
43736         {"AGL_GMX_RX0_ADR_CAM5"        ,           0x11800E00001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
43737         {"AGL_GMX_RX0_ADR_CAM_EN"      ,           0x11800E0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
43738         {"AGL_GMX_RX0_ADR_CTL"         ,           0x11800E0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
43739         {"AGL_GMX_RX0_DECISION"        ,           0x11800E0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
43740         {"AGL_GMX_RX0_FRM_CHK"         ,           0x11800E0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
43741         {"AGL_GMX_RX0_FRM_CTL"         ,           0x11800E0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
43742         {"AGL_GMX_RX0_FRM_MAX"         ,           0x11800E0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
43743         {"AGL_GMX_RX0_FRM_MIN"         ,           0x11800E0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
43744         {"AGL_GMX_RX0_IFG"             ,           0x11800E0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
43745         {"AGL_GMX_RX0_INT_EN"          ,           0x11800E0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
43746         {"AGL_GMX_RX0_INT_REG"         ,           0x11800E0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
43747         {"AGL_GMX_RX0_JABBER"          ,           0x11800E0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
43748         {"AGL_GMX_RX0_PAUSE_DROP_TIME" ,           0x11800E0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
43749         {"AGL_GMX_RX0_STATS_CTL"       ,           0x11800E0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     23},
43750         {"AGL_GMX_RX0_STATS_OCTS"      ,           0x11800E0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     24},
43751         {"AGL_GMX_RX0_STATS_OCTS_CTL"  ,           0x11800E0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     25},
43752         {"AGL_GMX_RX0_STATS_OCTS_DMAC" ,           0x11800E00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     26},
43753         {"AGL_GMX_RX0_STATS_OCTS_DRP"  ,           0x11800E00000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     27},
43754         {"AGL_GMX_RX0_STATS_PKTS"      ,           0x11800E0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     28},
43755         {"AGL_GMX_RX0_STATS_PKTS_BAD"  ,           0x11800E00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     29},
43756         {"AGL_GMX_RX0_STATS_PKTS_CTL"  ,           0x11800E0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     30},
43757         {"AGL_GMX_RX0_STATS_PKTS_DMAC" ,           0x11800E00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     31},
43758         {"AGL_GMX_RX0_STATS_PKTS_DRP"  ,           0x11800E00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     32},
43759         {"AGL_GMX_RX0_UDD_SKP"         ,           0x11800E0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     33},
43760         {"AGL_GMX_RX_BP_DROP0"         ,           0x11800E0000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     34},
43761         {"AGL_GMX_RX_BP_OFF0"          ,           0x11800E0000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     35},
43762         {"AGL_GMX_RX_BP_ON0"           ,           0x11800E0000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     36},
43763         {"AGL_GMX_RX_PRT_INFO"         ,           0x11800E00004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
43764         {"AGL_GMX_RX_TX_STATUS"        ,           0x11800E00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
43765         {"AGL_GMX_SMAC0"               ,           0x11800E0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     39},
43766         {"AGL_GMX_STAT_BP"             ,           0x11800E0000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
43767         {"AGL_GMX_TX0_APPEND"          ,           0x11800E0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
43768         {"AGL_GMX_TX0_CTL"             ,           0x11800E0000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     42},
43769         {"AGL_GMX_TX0_MIN_PKT"         ,           0x11800E0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     43},
43770         {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",         0x11800E0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
43771         {"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,           0x11800E0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     45},
43772         {"AGL_GMX_TX0_PAUSE_TOGO"      ,           0x11800E0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
43773         {"AGL_GMX_TX0_PAUSE_ZERO"      ,           0x11800E0000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
43774         {"AGL_GMX_TX0_SOFT_PAUSE"      ,           0x11800E0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
43775         {"AGL_GMX_TX0_STAT0"           ,           0x11800E0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
43776         {"AGL_GMX_TX0_STAT1"           ,           0x11800E0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
43777         {"AGL_GMX_TX0_STAT2"           ,           0x11800E0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
43778         {"AGL_GMX_TX0_STAT3"           ,           0x11800E0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
43779         {"AGL_GMX_TX0_STAT4"           ,           0x11800E00002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
43780         {"AGL_GMX_TX0_STAT5"           ,           0x11800E00002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
43781         {"AGL_GMX_TX0_STAT6"           ,           0x11800E00002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
43782         {"AGL_GMX_TX0_STAT7"           ,           0x11800E00002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
43783         {"AGL_GMX_TX0_STAT8"           ,           0x11800E00002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
43784         {"AGL_GMX_TX0_STAT9"           ,           0x11800E00002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
43785         {"AGL_GMX_TX0_STATS_CTL"       ,           0x11800E0000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
43786         {"AGL_GMX_TX0_THRESH"          ,           0x11800E0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
43787         {"AGL_GMX_TX_BP"               ,           0x11800E00004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
43788         {"AGL_GMX_TX_COL_ATTEMPT"      ,           0x11800E0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
43789         {"AGL_GMX_TX_IFG"              ,           0x11800E0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
43790         {"AGL_GMX_TX_INT_EN"           ,           0x11800E0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
43791         {"AGL_GMX_TX_INT_REG"          ,           0x11800E0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
43792         {"AGL_GMX_TX_JAM"              ,           0x11800E0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
43793         {"AGL_GMX_TX_LFSR"             ,           0x11800E00004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
43794         {"AGL_GMX_TX_OVR_BP"           ,           0x11800E00004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
43795         {"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,           0x11800E00004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
43796         {"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,           0x11800E00004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
43797         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     71},
43798         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     72},
43799         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     73},
43800         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     74},
43801         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43802         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43803         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43804         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43805         {"CIU_INT4_EN0"                ,           0x1070000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43806         {"CIU_INT5_EN0"                ,           0x1070000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43807         {"CIU_INT6_EN0"                ,           0x1070000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43808         {"CIU_INT7_EN0"                ,           0x1070000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43809         {"CIU_INT8_EN0"                ,           0x1070000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43810         {"CIU_INT9_EN0"                ,           0x1070000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43811         {"CIU_INT10_EN0"               ,           0x10700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43812         {"CIU_INT11_EN0"               ,           0x10700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43813         {"CIU_INT12_EN0"               ,           0x10700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43814         {"CIU_INT13_EN0"               ,           0x10700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43815         {"CIU_INT14_EN0"               ,           0x10700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43816         {"CIU_INT15_EN0"               ,           0x10700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43817         {"CIU_INT16_EN0"               ,           0x1070000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43818         {"CIU_INT17_EN0"               ,           0x1070000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43819         {"CIU_INT18_EN0"               ,           0x1070000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43820         {"CIU_INT19_EN0"               ,           0x1070000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43821         {"CIU_INT20_EN0"               ,           0x1070000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43822         {"CIU_INT21_EN0"               ,           0x1070000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43823         {"CIU_INT22_EN0"               ,           0x1070000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43824         {"CIU_INT23_EN0"               ,           0x1070000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43825         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
43826         {"CIU_INT0_EN0_W1C"            ,           0x1070000002200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43827         {"CIU_INT1_EN0_W1C"            ,           0x1070000002210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43828         {"CIU_INT2_EN0_W1C"            ,           0x1070000002220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43829         {"CIU_INT3_EN0_W1C"            ,           0x1070000002230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43830         {"CIU_INT4_EN0_W1C"            ,           0x1070000002240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43831         {"CIU_INT5_EN0_W1C"            ,           0x1070000002250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43832         {"CIU_INT6_EN0_W1C"            ,           0x1070000002260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43833         {"CIU_INT7_EN0_W1C"            ,           0x1070000002270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43834         {"CIU_INT8_EN0_W1C"            ,           0x1070000002280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43835         {"CIU_INT9_EN0_W1C"            ,           0x1070000002290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43836         {"CIU_INT10_EN0_W1C"           ,           0x10700000022A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43837         {"CIU_INT11_EN0_W1C"           ,           0x10700000022B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43838         {"CIU_INT12_EN0_W1C"           ,           0x10700000022C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43839         {"CIU_INT13_EN0_W1C"           ,           0x10700000022D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43840         {"CIU_INT14_EN0_W1C"           ,           0x10700000022E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43841         {"CIU_INT15_EN0_W1C"           ,           0x10700000022F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43842         {"CIU_INT16_EN0_W1C"           ,           0x1070000002300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43843         {"CIU_INT17_EN0_W1C"           ,           0x1070000002310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43844         {"CIU_INT18_EN0_W1C"           ,           0x1070000002320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43845         {"CIU_INT19_EN0_W1C"           ,           0x1070000002330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43846         {"CIU_INT20_EN0_W1C"           ,           0x1070000002340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43847         {"CIU_INT21_EN0_W1C"           ,           0x1070000002350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43848         {"CIU_INT22_EN0_W1C"           ,           0x1070000002360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43849         {"CIU_INT23_EN0_W1C"           ,           0x1070000002370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43850         {"CIU_INT32_EN0_W1C"           ,           0x1070000002400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
43851         {"CIU_INT0_EN0_W1S"            ,           0x1070000006200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43852         {"CIU_INT1_EN0_W1S"            ,           0x1070000006210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43853         {"CIU_INT2_EN0_W1S"            ,           0x1070000006220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43854         {"CIU_INT3_EN0_W1S"            ,           0x1070000006230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43855         {"CIU_INT4_EN0_W1S"            ,           0x1070000006240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43856         {"CIU_INT5_EN0_W1S"            ,           0x1070000006250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43857         {"CIU_INT6_EN0_W1S"            ,           0x1070000006260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43858         {"CIU_INT7_EN0_W1S"            ,           0x1070000006270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43859         {"CIU_INT8_EN0_W1S"            ,           0x1070000006280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43860         {"CIU_INT9_EN0_W1S"            ,           0x1070000006290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43861         {"CIU_INT10_EN0_W1S"           ,           0x10700000062A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43862         {"CIU_INT11_EN0_W1S"           ,           0x10700000062B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43863         {"CIU_INT12_EN0_W1S"           ,           0x10700000062C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43864         {"CIU_INT13_EN0_W1S"           ,           0x10700000062D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43865         {"CIU_INT14_EN0_W1S"           ,           0x10700000062E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43866         {"CIU_INT15_EN0_W1S"           ,           0x10700000062F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43867         {"CIU_INT16_EN0_W1S"           ,           0x1070000006300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43868         {"CIU_INT17_EN0_W1S"           ,           0x1070000006310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43869         {"CIU_INT18_EN0_W1S"           ,           0x1070000006320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43870         {"CIU_INT19_EN0_W1S"           ,           0x1070000006330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43871         {"CIU_INT20_EN0_W1S"           ,           0x1070000006340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43872         {"CIU_INT21_EN0_W1S"           ,           0x1070000006350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43873         {"CIU_INT22_EN0_W1S"           ,           0x1070000006360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43874         {"CIU_INT23_EN0_W1S"           ,           0x1070000006370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43875         {"CIU_INT32_EN0_W1S"           ,           0x1070000006400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
43876         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43877         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43878         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43879         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43880         {"CIU_INT4_EN1"                ,           0x1070000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43881         {"CIU_INT5_EN1"                ,           0x1070000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43882         {"CIU_INT6_EN1"                ,           0x1070000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43883         {"CIU_INT7_EN1"                ,           0x1070000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43884         {"CIU_INT8_EN1"                ,           0x1070000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43885         {"CIU_INT9_EN1"                ,           0x1070000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43886         {"CIU_INT10_EN1"               ,           0x10700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43887         {"CIU_INT11_EN1"               ,           0x10700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43888         {"CIU_INT12_EN1"               ,           0x10700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43889         {"CIU_INT13_EN1"               ,           0x10700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43890         {"CIU_INT14_EN1"               ,           0x10700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43891         {"CIU_INT15_EN1"               ,           0x10700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43892         {"CIU_INT16_EN1"               ,           0x1070000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43893         {"CIU_INT17_EN1"               ,           0x1070000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43894         {"CIU_INT18_EN1"               ,           0x1070000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43895         {"CIU_INT19_EN1"               ,           0x1070000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43896         {"CIU_INT20_EN1"               ,           0x1070000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43897         {"CIU_INT21_EN1"               ,           0x1070000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43898         {"CIU_INT22_EN1"               ,           0x1070000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43899         {"CIU_INT23_EN1"               ,           0x1070000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43900         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
43901         {"CIU_INT0_EN1_W1C"            ,           0x1070000002208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43902         {"CIU_INT1_EN1_W1C"            ,           0x1070000002218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43903         {"CIU_INT2_EN1_W1C"            ,           0x1070000002228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43904         {"CIU_INT3_EN1_W1C"            ,           0x1070000002238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43905         {"CIU_INT4_EN1_W1C"            ,           0x1070000002248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43906         {"CIU_INT5_EN1_W1C"            ,           0x1070000002258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43907         {"CIU_INT6_EN1_W1C"            ,           0x1070000002268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43908         {"CIU_INT7_EN1_W1C"            ,           0x1070000002278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43909         {"CIU_INT8_EN1_W1C"            ,           0x1070000002288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43910         {"CIU_INT9_EN1_W1C"            ,           0x1070000002298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43911         {"CIU_INT10_EN1_W1C"           ,           0x10700000022A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43912         {"CIU_INT11_EN1_W1C"           ,           0x10700000022B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43913         {"CIU_INT12_EN1_W1C"           ,           0x10700000022C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43914         {"CIU_INT13_EN1_W1C"           ,           0x10700000022D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43915         {"CIU_INT14_EN1_W1C"           ,           0x10700000022E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43916         {"CIU_INT15_EN1_W1C"           ,           0x10700000022F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43917         {"CIU_INT16_EN1_W1C"           ,           0x1070000002308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43918         {"CIU_INT17_EN1_W1C"           ,           0x1070000002318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43919         {"CIU_INT18_EN1_W1C"           ,           0x1070000002328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43920         {"CIU_INT19_EN1_W1C"           ,           0x1070000002338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43921         {"CIU_INT20_EN1_W1C"           ,           0x1070000002348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43922         {"CIU_INT21_EN1_W1C"           ,           0x1070000002358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43923         {"CIU_INT22_EN1_W1C"           ,           0x1070000002368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43924         {"CIU_INT23_EN1_W1C"           ,           0x1070000002378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43925         {"CIU_INT32_EN1_W1C"           ,           0x1070000002408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
43926         {"CIU_INT0_EN1_W1S"            ,           0x1070000006208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43927         {"CIU_INT1_EN1_W1S"            ,           0x1070000006218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43928         {"CIU_INT2_EN1_W1S"            ,           0x1070000006228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43929         {"CIU_INT3_EN1_W1S"            ,           0x1070000006238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43930         {"CIU_INT4_EN1_W1S"            ,           0x1070000006248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43931         {"CIU_INT5_EN1_W1S"            ,           0x1070000006258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43932         {"CIU_INT6_EN1_W1S"            ,           0x1070000006268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43933         {"CIU_INT7_EN1_W1S"            ,           0x1070000006278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43934         {"CIU_INT8_EN1_W1S"            ,           0x1070000006288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43935         {"CIU_INT9_EN1_W1S"            ,           0x1070000006298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43936         {"CIU_INT10_EN1_W1S"           ,           0x10700000062A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43937         {"CIU_INT11_EN1_W1S"           ,           0x10700000062B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43938         {"CIU_INT12_EN1_W1S"           ,           0x10700000062C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43939         {"CIU_INT13_EN1_W1S"           ,           0x10700000062D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43940         {"CIU_INT14_EN1_W1S"           ,           0x10700000062E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43941         {"CIU_INT15_EN1_W1S"           ,           0x10700000062F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43942         {"CIU_INT16_EN1_W1S"           ,           0x1070000006308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43943         {"CIU_INT17_EN1_W1S"           ,           0x1070000006318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43944         {"CIU_INT18_EN1_W1S"           ,           0x1070000006328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43945         {"CIU_INT19_EN1_W1S"           ,           0x1070000006338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43946         {"CIU_INT20_EN1_W1S"           ,           0x1070000006348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43947         {"CIU_INT21_EN1_W1S"           ,           0x1070000006358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43948         {"CIU_INT22_EN1_W1S"           ,           0x1070000006368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43949         {"CIU_INT23_EN1_W1S"           ,           0x1070000006378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43950         {"CIU_INT32_EN1_W1S"           ,           0x1070000006408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
43951         {"CIU_INT0_EN4_0"              ,           0x1070000000C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43952         {"CIU_INT1_EN4_0"              ,           0x1070000000C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43953         {"CIU_INT2_EN4_0"              ,           0x1070000000CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43954         {"CIU_INT3_EN4_0"              ,           0x1070000000CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43955         {"CIU_INT4_EN4_0"              ,           0x1070000000CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43956         {"CIU_INT5_EN4_0"              ,           0x1070000000CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43957         {"CIU_INT6_EN4_0"              ,           0x1070000000CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43958         {"CIU_INT7_EN4_0"              ,           0x1070000000CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43959         {"CIU_INT8_EN4_0"              ,           0x1070000000D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43960         {"CIU_INT9_EN4_0"              ,           0x1070000000D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43961         {"CIU_INT10_EN4_0"             ,           0x1070000000D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43962         {"CIU_INT11_EN4_0"             ,           0x1070000000D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
43963         {"CIU_INT0_EN4_0_W1C"          ,           0x1070000002C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43964         {"CIU_INT1_EN4_0_W1C"          ,           0x1070000002C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43965         {"CIU_INT2_EN4_0_W1C"          ,           0x1070000002CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43966         {"CIU_INT3_EN4_0_W1C"          ,           0x1070000002CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43967         {"CIU_INT4_EN4_0_W1C"          ,           0x1070000002CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43968         {"CIU_INT5_EN4_0_W1C"          ,           0x1070000002CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43969         {"CIU_INT6_EN4_0_W1C"          ,           0x1070000002CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43970         {"CIU_INT7_EN4_0_W1C"          ,           0x1070000002CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43971         {"CIU_INT8_EN4_0_W1C"          ,           0x1070000002D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43972         {"CIU_INT9_EN4_0_W1C"          ,           0x1070000002D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43973         {"CIU_INT10_EN4_0_W1C"         ,           0x1070000002D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43974         {"CIU_INT11_EN4_0_W1C"         ,           0x1070000002D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
43975         {"CIU_INT0_EN4_0_W1S"          ,           0x1070000006C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43976         {"CIU_INT1_EN4_0_W1S"          ,           0x1070000006C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43977         {"CIU_INT2_EN4_0_W1S"          ,           0x1070000006CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43978         {"CIU_INT3_EN4_0_W1S"          ,           0x1070000006CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43979         {"CIU_INT4_EN4_0_W1S"          ,           0x1070000006CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43980         {"CIU_INT5_EN4_0_W1S"          ,           0x1070000006CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43981         {"CIU_INT6_EN4_0_W1S"          ,           0x1070000006CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43982         {"CIU_INT7_EN4_0_W1S"          ,           0x1070000006CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43983         {"CIU_INT8_EN4_0_W1S"          ,           0x1070000006D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43984         {"CIU_INT9_EN4_0_W1S"          ,           0x1070000006D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43985         {"CIU_INT10_EN4_0_W1S"         ,           0x1070000006D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43986         {"CIU_INT11_EN4_0_W1S"         ,           0x1070000006D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
43987         {"CIU_INT0_EN4_1"              ,           0x1070000000C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43988         {"CIU_INT1_EN4_1"              ,           0x1070000000C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43989         {"CIU_INT2_EN4_1"              ,           0x1070000000CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43990         {"CIU_INT3_EN4_1"              ,           0x1070000000CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43991         {"CIU_INT4_EN4_1"              ,           0x1070000000CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43992         {"CIU_INT5_EN4_1"              ,           0x1070000000CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43993         {"CIU_INT6_EN4_1"              ,           0x1070000000CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43994         {"CIU_INT7_EN4_1"              ,           0x1070000000CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43995         {"CIU_INT8_EN4_1"              ,           0x1070000000D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43996         {"CIU_INT9_EN4_1"              ,           0x1070000000D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43997         {"CIU_INT10_EN4_1"             ,           0x1070000000D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43998         {"CIU_INT11_EN4_1"             ,           0x1070000000D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
43999         {"CIU_INT0_EN4_1_W1C"          ,           0x1070000002C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44000         {"CIU_INT1_EN4_1_W1C"          ,           0x1070000002C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44001         {"CIU_INT2_EN4_1_W1C"          ,           0x1070000002CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44002         {"CIU_INT3_EN4_1_W1C"          ,           0x1070000002CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44003         {"CIU_INT4_EN4_1_W1C"          ,           0x1070000002CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44004         {"CIU_INT5_EN4_1_W1C"          ,           0x1070000002CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44005         {"CIU_INT6_EN4_1_W1C"          ,           0x1070000002CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44006         {"CIU_INT7_EN4_1_W1C"          ,           0x1070000002CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44007         {"CIU_INT8_EN4_1_W1C"          ,           0x1070000002D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44008         {"CIU_INT9_EN4_1_W1C"          ,           0x1070000002D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44009         {"CIU_INT10_EN4_1_W1C"         ,           0x1070000002D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44010         {"CIU_INT11_EN4_1_W1C"         ,           0x1070000002D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
44011         {"CIU_INT0_EN4_1_W1S"          ,           0x1070000006C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44012         {"CIU_INT1_EN4_1_W1S"          ,           0x1070000006C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44013         {"CIU_INT2_EN4_1_W1S"          ,           0x1070000006CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44014         {"CIU_INT3_EN4_1_W1S"          ,           0x1070000006CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44015         {"CIU_INT4_EN4_1_W1S"          ,           0x1070000006CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44016         {"CIU_INT5_EN4_1_W1S"          ,           0x1070000006CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44017         {"CIU_INT6_EN4_1_W1S"          ,           0x1070000006CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44018         {"CIU_INT7_EN4_1_W1S"          ,           0x1070000006CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44019         {"CIU_INT8_EN4_1_W1S"          ,           0x1070000006D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44020         {"CIU_INT9_EN4_1_W1S"          ,           0x1070000006D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44021         {"CIU_INT10_EN4_1_W1S"         ,           0x1070000006D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44022         {"CIU_INT11_EN4_1_W1S"         ,           0x1070000006D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
44023         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44024         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44025         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44026         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44027         {"CIU_INT4_SUM0"               ,           0x1070000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44028         {"CIU_INT5_SUM0"               ,           0x1070000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44029         {"CIU_INT6_SUM0"               ,           0x1070000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44030         {"CIU_INT7_SUM0"               ,           0x1070000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44031         {"CIU_INT8_SUM0"               ,           0x1070000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44032         {"CIU_INT9_SUM0"               ,           0x1070000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44033         {"CIU_INT10_SUM0"              ,           0x1070000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44034         {"CIU_INT11_SUM0"              ,           0x1070000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44035         {"CIU_INT12_SUM0"              ,           0x1070000000060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44036         {"CIU_INT13_SUM0"              ,           0x1070000000068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44037         {"CIU_INT14_SUM0"              ,           0x1070000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44038         {"CIU_INT15_SUM0"              ,           0x1070000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44039         {"CIU_INT16_SUM0"              ,           0x1070000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44040         {"CIU_INT17_SUM0"              ,           0x1070000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44041         {"CIU_INT18_SUM0"              ,           0x1070000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44042         {"CIU_INT19_SUM0"              ,           0x1070000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44043         {"CIU_INT20_SUM0"              ,           0x10700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44044         {"CIU_INT21_SUM0"              ,           0x10700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44045         {"CIU_INT22_SUM0"              ,           0x10700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44046         {"CIU_INT23_SUM0"              ,           0x10700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44047         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
44048         {"CIU_INT0_SUM4"               ,           0x1070000000C00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44049         {"CIU_INT1_SUM4"               ,           0x1070000000C08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44050         {"CIU_INT2_SUM4"               ,           0x1070000000C10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44051         {"CIU_INT3_SUM4"               ,           0x1070000000C18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44052         {"CIU_INT4_SUM4"               ,           0x1070000000C20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44053         {"CIU_INT5_SUM4"               ,           0x1070000000C28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44054         {"CIU_INT6_SUM4"               ,           0x1070000000C30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44055         {"CIU_INT7_SUM4"               ,           0x1070000000C38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44056         {"CIU_INT8_SUM4"               ,           0x1070000000C40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44057         {"CIU_INT9_SUM4"               ,           0x1070000000C48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44058         {"CIU_INT10_SUM4"              ,           0x1070000000C50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44059         {"CIU_INT11_SUM4"              ,           0x1070000000C58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
44060         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     89},
44061         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44062         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44063         {"CIU_MBOX_CLR2"               ,           0x1070000000690ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44064         {"CIU_MBOX_CLR3"               ,           0x1070000000698ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44065         {"CIU_MBOX_CLR4"               ,           0x10700000006A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44066         {"CIU_MBOX_CLR5"               ,           0x10700000006A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44067         {"CIU_MBOX_CLR6"               ,           0x10700000006B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44068         {"CIU_MBOX_CLR7"               ,           0x10700000006B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44069         {"CIU_MBOX_CLR8"               ,           0x10700000006C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44070         {"CIU_MBOX_CLR9"               ,           0x10700000006C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44071         {"CIU_MBOX_CLR10"              ,           0x10700000006D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44072         {"CIU_MBOX_CLR11"              ,           0x10700000006D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
44073         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44074         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44075         {"CIU_MBOX_SET2"               ,           0x1070000000610ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44076         {"CIU_MBOX_SET3"               ,           0x1070000000618ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44077         {"CIU_MBOX_SET4"               ,           0x1070000000620ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44078         {"CIU_MBOX_SET5"               ,           0x1070000000628ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44079         {"CIU_MBOX_SET6"               ,           0x1070000000630ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44080         {"CIU_MBOX_SET7"               ,           0x1070000000638ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44081         {"CIU_MBOX_SET8"               ,           0x1070000000640ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44082         {"CIU_MBOX_SET9"               ,           0x1070000000648ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44083         {"CIU_MBOX_SET10"              ,           0x1070000000650ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44084         {"CIU_MBOX_SET11"              ,           0x1070000000658ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
44085         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     92},
44086         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     93},
44087         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     94},
44088         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44089         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44090         {"CIU_PP_POKE2"                ,           0x1070000000590ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44091         {"CIU_PP_POKE3"                ,           0x1070000000598ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44092         {"CIU_PP_POKE4"                ,           0x10700000005A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44093         {"CIU_PP_POKE5"                ,           0x10700000005A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44094         {"CIU_PP_POKE6"                ,           0x10700000005B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44095         {"CIU_PP_POKE7"                ,           0x10700000005B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44096         {"CIU_PP_POKE8"                ,           0x10700000005C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44097         {"CIU_PP_POKE9"                ,           0x10700000005C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44098         {"CIU_PP_POKE10"               ,           0x10700000005D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44099         {"CIU_PP_POKE11"               ,           0x10700000005D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
44100         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
44101         {"CIU_QLM_DCOK"                ,           0x1070000000760ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
44102         {"CIU_QLM_JTGC"                ,           0x1070000000768ull,  CVMX_CSR_DB_TYPE_NCB,   64,     98},
44103         {"CIU_QLM_JTGD"                ,           0x1070000000770ull,  CVMX_CSR_DB_TYPE_NCB,   64,     99},
44104         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     100},
44105         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     101},
44106         {"CIU_SOFT_PRST1"              ,           0x1070000000758ull,  CVMX_CSR_DB_TYPE_NCB,   64,     102},
44107         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     103},
44108         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     104},
44109         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     104},
44110         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     104},
44111         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     104},
44112         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44113         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44114         {"CIU_WDOG2"                   ,           0x1070000000510ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44115         {"CIU_WDOG3"                   ,           0x1070000000518ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44116         {"CIU_WDOG4"                   ,           0x1070000000520ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44117         {"CIU_WDOG5"                   ,           0x1070000000528ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44118         {"CIU_WDOG6"                   ,           0x1070000000530ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44119         {"CIU_WDOG7"                   ,           0x1070000000538ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44120         {"CIU_WDOG8"                   ,           0x1070000000540ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44121         {"CIU_WDOG9"                   ,           0x1070000000548ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44122         {"CIU_WDOG10"                  ,           0x1070000000550ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44123         {"CIU_WDOG11"                  ,           0x1070000000558ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
44124         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
44125         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
44126         {"FPA_FPF1_MARKS"              ,           0x1180028000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
44127         {"FPA_FPF2_MARKS"              ,           0x1180028000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
44128         {"FPA_FPF3_MARKS"              ,           0x1180028000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
44129         {"FPA_FPF4_MARKS"              ,           0x1180028000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
44130         {"FPA_FPF5_MARKS"              ,           0x1180028000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
44131         {"FPA_FPF6_MARKS"              ,           0x1180028000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
44132         {"FPA_FPF7_MARKS"              ,           0x1180028000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
44133         {"FPA_FPF1_SIZE"               ,           0x1180028000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
44134         {"FPA_FPF2_SIZE"               ,           0x1180028000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
44135         {"FPA_FPF3_SIZE"               ,           0x1180028000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
44136         {"FPA_FPF4_SIZE"               ,           0x1180028000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
44137         {"FPA_FPF5_SIZE"               ,           0x1180028000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
44138         {"FPA_FPF6_SIZE"               ,           0x1180028000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
44139         {"FPA_FPF7_SIZE"               ,           0x1180028000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
44140         {"FPA_FPF0_MARKS"              ,           0x1180028000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
44141         {"FPA_FPF0_SIZE"               ,           0x1180028000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
44142         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
44143         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
44144         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
44145         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
44146         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
44147         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
44148         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
44149         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
44150         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
44151         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
44152         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
44153         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
44154         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
44155         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
44156         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
44157         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
44158         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
44159         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
44160         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
44161         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
44162         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
44163         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
44164         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
44165         {"GMX1_BAD_REG"                ,           0x1180010000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
44166         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
44167         {"GMX1_BIST"                   ,           0x1180010000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
44168         {"GMX0_CLK_EN"                 ,           0x11800080007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
44169         {"GMX1_CLK_EN"                 ,           0x11800100007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
44170         {"GMX0_HG2_CONTROL"            ,           0x1180008000550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
44171         {"GMX1_HG2_CONTROL"            ,           0x1180010000550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
44172         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
44173         {"GMX1_INF_MODE"               ,           0x11800100007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
44174         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
44175         {"GMX1_NXA_ADR"                ,           0x1180010000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
44176         {"GMX0_PRT000_CBFC_CTL"        ,           0x1180008000580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
44177         {"GMX1_PRT000_CBFC_CTL"        ,           0x1180010000580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
44178         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
44179         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
44180         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
44181         {"GMX0_PRT003_CFG"             ,           0x1180008001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
44182         {"GMX1_PRT000_CFG"             ,           0x1180010000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
44183         {"GMX1_PRT001_CFG"             ,           0x1180010000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
44184         {"GMX1_PRT002_CFG"             ,           0x1180010001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
44185         {"GMX1_PRT003_CFG"             ,           0x1180010001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
44186         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
44187         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
44188         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
44189         {"GMX0_RX003_ADR_CAM0"         ,           0x1180008001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
44190         {"GMX1_RX000_ADR_CAM0"         ,           0x1180010000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
44191         {"GMX1_RX001_ADR_CAM0"         ,           0x1180010000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
44192         {"GMX1_RX002_ADR_CAM0"         ,           0x1180010001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
44193         {"GMX1_RX003_ADR_CAM0"         ,           0x1180010001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
44194         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
44195         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
44196         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
44197         {"GMX0_RX003_ADR_CAM1"         ,           0x1180008001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
44198         {"GMX1_RX000_ADR_CAM1"         ,           0x1180010000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
44199         {"GMX1_RX001_ADR_CAM1"         ,           0x1180010000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
44200         {"GMX1_RX002_ADR_CAM1"         ,           0x1180010001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
44201         {"GMX1_RX003_ADR_CAM1"         ,           0x1180010001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
44202         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
44203         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
44204         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
44205         {"GMX0_RX003_ADR_CAM2"         ,           0x1180008001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
44206         {"GMX1_RX000_ADR_CAM2"         ,           0x1180010000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
44207         {"GMX1_RX001_ADR_CAM2"         ,           0x1180010000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
44208         {"GMX1_RX002_ADR_CAM2"         ,           0x1180010001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
44209         {"GMX1_RX003_ADR_CAM2"         ,           0x1180010001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
44210         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
44211         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
44212         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
44213         {"GMX0_RX003_ADR_CAM3"         ,           0x1180008001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
44214         {"GMX1_RX000_ADR_CAM3"         ,           0x1180010000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
44215         {"GMX1_RX001_ADR_CAM3"         ,           0x1180010000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
44216         {"GMX1_RX002_ADR_CAM3"         ,           0x1180010001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
44217         {"GMX1_RX003_ADR_CAM3"         ,           0x1180010001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
44218         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
44219         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
44220         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
44221         {"GMX0_RX003_ADR_CAM4"         ,           0x11800080019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
44222         {"GMX1_RX000_ADR_CAM4"         ,           0x11800100001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
44223         {"GMX1_RX001_ADR_CAM4"         ,           0x11800100009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
44224         {"GMX1_RX002_ADR_CAM4"         ,           0x11800100011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
44225         {"GMX1_RX003_ADR_CAM4"         ,           0x11800100019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
44226         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
44227         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
44228         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
44229         {"GMX0_RX003_ADR_CAM5"         ,           0x11800080019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
44230         {"GMX1_RX000_ADR_CAM5"         ,           0x11800100001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
44231         {"GMX1_RX001_ADR_CAM5"         ,           0x11800100009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
44232         {"GMX1_RX002_ADR_CAM5"         ,           0x11800100011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
44233         {"GMX1_RX003_ADR_CAM5"         ,           0x11800100019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
44234         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
44235         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
44236         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
44237         {"GMX0_RX003_ADR_CAM_EN"       ,           0x1180008001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
44238         {"GMX1_RX000_ADR_CAM_EN"       ,           0x1180010000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
44239         {"GMX1_RX001_ADR_CAM_EN"       ,           0x1180010000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
44240         {"GMX1_RX002_ADR_CAM_EN"       ,           0x1180010001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
44241         {"GMX1_RX003_ADR_CAM_EN"       ,           0x1180010001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
44242         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
44243         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
44244         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
44245         {"GMX0_RX003_ADR_CTL"          ,           0x1180008001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
44246         {"GMX1_RX000_ADR_CTL"          ,           0x1180010000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
44247         {"GMX1_RX001_ADR_CTL"          ,           0x1180010000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
44248         {"GMX1_RX002_ADR_CTL"          ,           0x1180010001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
44249         {"GMX1_RX003_ADR_CTL"          ,           0x1180010001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
44250         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
44251         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
44252         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
44253         {"GMX0_RX003_DECISION"         ,           0x1180008001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
44254         {"GMX1_RX000_DECISION"         ,           0x1180010000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
44255         {"GMX1_RX001_DECISION"         ,           0x1180010000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
44256         {"GMX1_RX002_DECISION"         ,           0x1180010001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
44257         {"GMX1_RX003_DECISION"         ,           0x1180010001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
44258         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
44259         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
44260         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
44261         {"GMX0_RX003_FRM_CHK"          ,           0x1180008001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
44262         {"GMX1_RX000_FRM_CHK"          ,           0x1180010000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
44263         {"GMX1_RX001_FRM_CHK"          ,           0x1180010000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
44264         {"GMX1_RX002_FRM_CHK"          ,           0x1180010001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
44265         {"GMX1_RX003_FRM_CHK"          ,           0x1180010001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
44266         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
44267         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
44268         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
44269         {"GMX0_RX003_FRM_CTL"          ,           0x1180008001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
44270         {"GMX1_RX000_FRM_CTL"          ,           0x1180010000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
44271         {"GMX1_RX001_FRM_CTL"          ,           0x1180010000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
44272         {"GMX1_RX002_FRM_CTL"          ,           0x1180010001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
44273         {"GMX1_RX003_FRM_CTL"          ,           0x1180010001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
44274         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
44275         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
44276         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
44277         {"GMX0_RX003_IFG"              ,           0x1180008001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
44278         {"GMX1_RX000_IFG"              ,           0x1180010000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
44279         {"GMX1_RX001_IFG"              ,           0x1180010000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
44280         {"GMX1_RX002_IFG"              ,           0x1180010001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
44281         {"GMX1_RX003_IFG"              ,           0x1180010001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
44282         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
44283         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
44284         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
44285         {"GMX0_RX003_INT_EN"           ,           0x1180008001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
44286         {"GMX1_RX000_INT_EN"           ,           0x1180010000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
44287         {"GMX1_RX001_INT_EN"           ,           0x1180010000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
44288         {"GMX1_RX002_INT_EN"           ,           0x1180010001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
44289         {"GMX1_RX003_INT_EN"           ,           0x1180010001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
44290         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
44291         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
44292         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
44293         {"GMX0_RX003_INT_REG"          ,           0x1180008001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
44294         {"GMX1_RX000_INT_REG"          ,           0x1180010000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
44295         {"GMX1_RX001_INT_REG"          ,           0x1180010000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
44296         {"GMX1_RX002_INT_REG"          ,           0x1180010001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
44297         {"GMX1_RX003_INT_REG"          ,           0x1180010001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
44298         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
44299         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
44300         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
44301         {"GMX0_RX003_JABBER"           ,           0x1180008001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
44302         {"GMX1_RX000_JABBER"           ,           0x1180010000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
44303         {"GMX1_RX001_JABBER"           ,           0x1180010000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
44304         {"GMX1_RX002_JABBER"           ,           0x1180010001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
44305         {"GMX1_RX003_JABBER"           ,           0x1180010001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
44306         {"GMX0_RX000_PAUSE_DROP_TIME"  ,           0x1180008000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
44307         {"GMX0_RX001_PAUSE_DROP_TIME"  ,           0x1180008000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
44308         {"GMX0_RX002_PAUSE_DROP_TIME"  ,           0x1180008001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
44309         {"GMX0_RX003_PAUSE_DROP_TIME"  ,           0x1180008001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
44310         {"GMX1_RX000_PAUSE_DROP_TIME"  ,           0x1180010000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
44311         {"GMX1_RX001_PAUSE_DROP_TIME"  ,           0x1180010000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
44312         {"GMX1_RX002_PAUSE_DROP_TIME"  ,           0x1180010001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
44313         {"GMX1_RX003_PAUSE_DROP_TIME"  ,           0x1180010001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
44314         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
44315         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
44316         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
44317         {"GMX0_RX003_STATS_CTL"        ,           0x1180008001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
44318         {"GMX1_RX000_STATS_CTL"        ,           0x1180010000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
44319         {"GMX1_RX001_STATS_CTL"        ,           0x1180010000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
44320         {"GMX1_RX002_STATS_CTL"        ,           0x1180010001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
44321         {"GMX1_RX003_STATS_CTL"        ,           0x1180010001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
44322         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
44323         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
44324         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
44325         {"GMX0_RX003_STATS_OCTS"       ,           0x1180008001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
44326         {"GMX1_RX000_STATS_OCTS"       ,           0x1180010000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
44327         {"GMX1_RX001_STATS_OCTS"       ,           0x1180010000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
44328         {"GMX1_RX002_STATS_OCTS"       ,           0x1180010001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
44329         {"GMX1_RX003_STATS_OCTS"       ,           0x1180010001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
44330         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
44331         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
44332         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
44333         {"GMX0_RX003_STATS_OCTS_CTL"   ,           0x1180008001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
44334         {"GMX1_RX000_STATS_OCTS_CTL"   ,           0x1180010000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
44335         {"GMX1_RX001_STATS_OCTS_CTL"   ,           0x1180010000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
44336         {"GMX1_RX002_STATS_OCTS_CTL"   ,           0x1180010001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
44337         {"GMX1_RX003_STATS_OCTS_CTL"   ,           0x1180010001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
44338         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
44339         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
44340         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
44341         {"GMX0_RX003_STATS_OCTS_DMAC"  ,           0x11800080018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
44342         {"GMX1_RX000_STATS_OCTS_DMAC"  ,           0x11800100000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
44343         {"GMX1_RX001_STATS_OCTS_DMAC"  ,           0x11800100008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
44344         {"GMX1_RX002_STATS_OCTS_DMAC"  ,           0x11800100010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
44345         {"GMX1_RX003_STATS_OCTS_DMAC"  ,           0x11800100018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
44346         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
44347         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
44348         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
44349         {"GMX0_RX003_STATS_OCTS_DRP"   ,           0x11800080018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
44350         {"GMX1_RX000_STATS_OCTS_DRP"   ,           0x11800100000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
44351         {"GMX1_RX001_STATS_OCTS_DRP"   ,           0x11800100008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
44352         {"GMX1_RX002_STATS_OCTS_DRP"   ,           0x11800100010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
44353         {"GMX1_RX003_STATS_OCTS_DRP"   ,           0x11800100018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
44354         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
44355         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
44356         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
44357         {"GMX0_RX003_STATS_PKTS"       ,           0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
44358         {"GMX1_RX000_STATS_PKTS"       ,           0x1180010000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
44359         {"GMX1_RX001_STATS_PKTS"       ,           0x1180010000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
44360         {"GMX1_RX002_STATS_PKTS"       ,           0x1180010001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
44361         {"GMX1_RX003_STATS_PKTS"       ,           0x1180010001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
44362         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
44363         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
44364         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
44365         {"GMX0_RX003_STATS_PKTS_BAD"   ,           0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
44366         {"GMX1_RX000_STATS_PKTS_BAD"   ,           0x11800100000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
44367         {"GMX1_RX001_STATS_PKTS_BAD"   ,           0x11800100008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
44368         {"GMX1_RX002_STATS_PKTS_BAD"   ,           0x11800100010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
44369         {"GMX1_RX003_STATS_PKTS_BAD"   ,           0x11800100018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
44370         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
44371         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
44372         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
44373         {"GMX0_RX003_STATS_PKTS_CTL"   ,           0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
44374         {"GMX1_RX000_STATS_PKTS_CTL"   ,           0x1180010000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
44375         {"GMX1_RX001_STATS_PKTS_CTL"   ,           0x1180010000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
44376         {"GMX1_RX002_STATS_PKTS_CTL"   ,           0x1180010001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
44377         {"GMX1_RX003_STATS_PKTS_CTL"   ,           0x1180010001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
44378         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
44379         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
44380         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
44381         {"GMX0_RX003_STATS_PKTS_DMAC"  ,           0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
44382         {"GMX1_RX000_STATS_PKTS_DMAC"  ,           0x11800100000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
44383         {"GMX1_RX001_STATS_PKTS_DMAC"  ,           0x11800100008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
44384         {"GMX1_RX002_STATS_PKTS_DMAC"  ,           0x11800100010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
44385         {"GMX1_RX003_STATS_PKTS_DMAC"  ,           0x11800100018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
44386         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
44387         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
44388         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
44389         {"GMX0_RX003_STATS_PKTS_DRP"   ,           0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
44390         {"GMX1_RX000_STATS_PKTS_DRP"   ,           0x11800100000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
44391         {"GMX1_RX001_STATS_PKTS_DRP"   ,           0x11800100008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
44392         {"GMX1_RX002_STATS_PKTS_DRP"   ,           0x11800100010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
44393         {"GMX1_RX003_STATS_PKTS_DRP"   ,           0x11800100018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
44394         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
44395         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
44396         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
44397         {"GMX0_RX003_UDD_SKP"          ,           0x1180008001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
44398         {"GMX1_RX000_UDD_SKP"          ,           0x1180010000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
44399         {"GMX1_RX001_UDD_SKP"          ,           0x1180010000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
44400         {"GMX1_RX002_UDD_SKP"          ,           0x1180010001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
44401         {"GMX1_RX003_UDD_SKP"          ,           0x1180010001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
44402         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
44403         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
44404         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
44405         {"GMX0_RX_BP_DROP003"          ,           0x1180008000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
44406         {"GMX1_RX_BP_DROP000"          ,           0x1180010000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
44407         {"GMX1_RX_BP_DROP001"          ,           0x1180010000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
44408         {"GMX1_RX_BP_DROP002"          ,           0x1180010000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
44409         {"GMX1_RX_BP_DROP003"          ,           0x1180010000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
44410         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
44411         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
44412         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
44413         {"GMX0_RX_BP_OFF003"           ,           0x1180008000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
44414         {"GMX1_RX_BP_OFF000"           ,           0x1180010000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
44415         {"GMX1_RX_BP_OFF001"           ,           0x1180010000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
44416         {"GMX1_RX_BP_OFF002"           ,           0x1180010000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
44417         {"GMX1_RX_BP_OFF003"           ,           0x1180010000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
44418         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
44419         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
44420         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
44421         {"GMX0_RX_BP_ON003"            ,           0x1180008000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
44422         {"GMX1_RX_BP_ON000"            ,           0x1180010000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
44423         {"GMX1_RX_BP_ON001"            ,           0x1180010000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
44424         {"GMX1_RX_BP_ON002"            ,           0x1180010000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
44425         {"GMX1_RX_BP_ON003"            ,           0x1180010000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
44426         {"GMX0_RX_HG2_STATUS"          ,           0x1180008000548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
44427         {"GMX1_RX_HG2_STATUS"          ,           0x1180010000548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
44428         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
44429         {"GMX1_RX_PRT_INFO"            ,           0x11800100004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
44430         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
44431         {"GMX1_RX_PRTS"                ,           0x1180010000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
44432         {"GMX0_RX_XAUI_BAD_COL"        ,           0x1180008000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
44433         {"GMX1_RX_XAUI_BAD_COL"        ,           0x1180010000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
44434         {"GMX0_RX_XAUI_CTL"            ,           0x1180008000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
44435         {"GMX1_RX_XAUI_CTL"            ,           0x1180010000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
44436         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
44437         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
44438         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
44439         {"GMX0_SMAC003"                ,           0x1180008001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
44440         {"GMX1_SMAC000"                ,           0x1180010000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
44441         {"GMX1_SMAC001"                ,           0x1180010000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
44442         {"GMX1_SMAC002"                ,           0x1180010001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
44443         {"GMX1_SMAC003"                ,           0x1180010001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
44444         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
44445         {"GMX1_STAT_BP"                ,           0x1180010000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
44446         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
44447         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
44448         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
44449         {"GMX0_TX003_APPEND"           ,           0x1180008001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
44450         {"GMX1_TX000_APPEND"           ,           0x1180010000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
44451         {"GMX1_TX001_APPEND"           ,           0x1180010000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
44452         {"GMX1_TX002_APPEND"           ,           0x1180010001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
44453         {"GMX1_TX003_APPEND"           ,           0x1180010001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
44454         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
44455         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
44456         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
44457         {"GMX0_TX003_BURST"            ,           0x1180008001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
44458         {"GMX1_TX000_BURST"            ,           0x1180010000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
44459         {"GMX1_TX001_BURST"            ,           0x1180010000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
44460         {"GMX1_TX002_BURST"            ,           0x1180010001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
44461         {"GMX1_TX003_BURST"            ,           0x1180010001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
44462         {"GMX0_TX000_CBFC_XOFF"        ,           0x11800080005A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
44463         {"GMX1_TX000_CBFC_XOFF"        ,           0x11800100005A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
44464         {"GMX0_TX000_CBFC_XON"         ,           0x11800080005C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
44465         {"GMX1_TX000_CBFC_XON"         ,           0x11800100005C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
44466         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
44467         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
44468         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
44469         {"GMX0_TX003_CTL"              ,           0x1180008001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
44470         {"GMX1_TX000_CTL"              ,           0x1180010000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
44471         {"GMX1_TX001_CTL"              ,           0x1180010000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
44472         {"GMX1_TX002_CTL"              ,           0x1180010001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
44473         {"GMX1_TX003_CTL"              ,           0x1180010001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
44474         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
44475         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
44476         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
44477         {"GMX0_TX003_MIN_PKT"          ,           0x1180008001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
44478         {"GMX1_TX000_MIN_PKT"          ,           0x1180010000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
44479         {"GMX1_TX001_MIN_PKT"          ,           0x1180010000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
44480         {"GMX1_TX002_MIN_PKT"          ,           0x1180010001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
44481         {"GMX1_TX003_MIN_PKT"          ,           0x1180010001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
44482         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
44483         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
44484         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
44485         {"GMX0_TX003_PAUSE_PKT_INTERVAL",          0x1180008001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
44486         {"GMX1_TX000_PAUSE_PKT_INTERVAL",          0x1180010000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
44487         {"GMX1_TX001_PAUSE_PKT_INTERVAL",          0x1180010000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
44488         {"GMX1_TX002_PAUSE_PKT_INTERVAL",          0x1180010001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
44489         {"GMX1_TX003_PAUSE_PKT_INTERVAL",          0x1180010001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
44490         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
44491         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
44492         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
44493         {"GMX0_TX003_PAUSE_PKT_TIME"   ,           0x1180008001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
44494         {"GMX1_TX000_PAUSE_PKT_TIME"   ,           0x1180010000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
44495         {"GMX1_TX001_PAUSE_PKT_TIME"   ,           0x1180010000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
44496         {"GMX1_TX002_PAUSE_PKT_TIME"   ,           0x1180010001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
44497         {"GMX1_TX003_PAUSE_PKT_TIME"   ,           0x1180010001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
44498         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
44499         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
44500         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
44501         {"GMX0_TX003_PAUSE_TOGO"       ,           0x1180008001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
44502         {"GMX1_TX000_PAUSE_TOGO"       ,           0x1180010000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
44503         {"GMX1_TX001_PAUSE_TOGO"       ,           0x1180010000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
44504         {"GMX1_TX002_PAUSE_TOGO"       ,           0x1180010001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
44505         {"GMX1_TX003_PAUSE_TOGO"       ,           0x1180010001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
44506         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
44507         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
44508         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
44509         {"GMX0_TX003_PAUSE_ZERO"       ,           0x1180008001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
44510         {"GMX1_TX000_PAUSE_ZERO"       ,           0x1180010000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
44511         {"GMX1_TX001_PAUSE_ZERO"       ,           0x1180010000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
44512         {"GMX1_TX002_PAUSE_ZERO"       ,           0x1180010001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
44513         {"GMX1_TX003_PAUSE_ZERO"       ,           0x1180010001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
44514         {"GMX0_TX000_SGMII_CTL"        ,           0x1180008000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
44515         {"GMX0_TX001_SGMII_CTL"        ,           0x1180008000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
44516         {"GMX0_TX002_SGMII_CTL"        ,           0x1180008001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
44517         {"GMX0_TX003_SGMII_CTL"        ,           0x1180008001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
44518         {"GMX1_TX000_SGMII_CTL"        ,           0x1180010000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
44519         {"GMX1_TX001_SGMII_CTL"        ,           0x1180010000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
44520         {"GMX1_TX002_SGMII_CTL"        ,           0x1180010001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
44521         {"GMX1_TX003_SGMII_CTL"        ,           0x1180010001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
44522         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
44523         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
44524         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
44525         {"GMX0_TX003_SLOT"             ,           0x1180008001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
44526         {"GMX1_TX000_SLOT"             ,           0x1180010000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
44527         {"GMX1_TX001_SLOT"             ,           0x1180010000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
44528         {"GMX1_TX002_SLOT"             ,           0x1180010001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
44529         {"GMX1_TX003_SLOT"             ,           0x1180010001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
44530         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
44531         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
44532         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
44533         {"GMX0_TX003_SOFT_PAUSE"       ,           0x1180008001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
44534         {"GMX1_TX000_SOFT_PAUSE"       ,           0x1180010000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
44535         {"GMX1_TX001_SOFT_PAUSE"       ,           0x1180010000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
44536         {"GMX1_TX002_SOFT_PAUSE"       ,           0x1180010001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
44537         {"GMX1_TX003_SOFT_PAUSE"       ,           0x1180010001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
44538         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
44539         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
44540         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
44541         {"GMX0_TX003_STAT0"            ,           0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
44542         {"GMX1_TX000_STAT0"            ,           0x1180010000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
44543         {"GMX1_TX001_STAT0"            ,           0x1180010000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
44544         {"GMX1_TX002_STAT0"            ,           0x1180010001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
44545         {"GMX1_TX003_STAT0"            ,           0x1180010001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
44546         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
44547         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
44548         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
44549         {"GMX0_TX003_STAT1"            ,           0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
44550         {"GMX1_TX000_STAT1"            ,           0x1180010000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
44551         {"GMX1_TX001_STAT1"            ,           0x1180010000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
44552         {"GMX1_TX002_STAT1"            ,           0x1180010001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
44553         {"GMX1_TX003_STAT1"            ,           0x1180010001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
44554         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
44555         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
44556         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
44557         {"GMX0_TX003_STAT2"            ,           0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
44558         {"GMX1_TX000_STAT2"            ,           0x1180010000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
44559         {"GMX1_TX001_STAT2"            ,           0x1180010000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
44560         {"GMX1_TX002_STAT2"            ,           0x1180010001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
44561         {"GMX1_TX003_STAT2"            ,           0x1180010001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
44562         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
44563         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
44564         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
44565         {"GMX0_TX003_STAT3"            ,           0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
44566         {"GMX1_TX000_STAT3"            ,           0x1180010000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
44567         {"GMX1_TX001_STAT3"            ,           0x1180010000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
44568         {"GMX1_TX002_STAT3"            ,           0x1180010001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
44569         {"GMX1_TX003_STAT3"            ,           0x1180010001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
44570         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
44571         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
44572         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
44573         {"GMX0_TX003_STAT4"            ,           0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
44574         {"GMX1_TX000_STAT4"            ,           0x11800100002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
44575         {"GMX1_TX001_STAT4"            ,           0x1180010000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
44576         {"GMX1_TX002_STAT4"            ,           0x11800100012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
44577         {"GMX1_TX003_STAT4"            ,           0x1180010001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
44578         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
44579         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
44580         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
44581         {"GMX0_TX003_STAT5"            ,           0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
44582         {"GMX1_TX000_STAT5"            ,           0x11800100002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
44583         {"GMX1_TX001_STAT5"            ,           0x1180010000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
44584         {"GMX1_TX002_STAT5"            ,           0x11800100012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
44585         {"GMX1_TX003_STAT5"            ,           0x1180010001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
44586         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
44587         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
44588         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
44589         {"GMX0_TX003_STAT6"            ,           0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
44590         {"GMX1_TX000_STAT6"            ,           0x11800100002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
44591         {"GMX1_TX001_STAT6"            ,           0x1180010000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
44592         {"GMX1_TX002_STAT6"            ,           0x11800100012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
44593         {"GMX1_TX003_STAT6"            ,           0x1180010001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
44594         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
44595         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
44596         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
44597         {"GMX0_TX003_STAT7"            ,           0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
44598         {"GMX1_TX000_STAT7"            ,           0x11800100002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
44599         {"GMX1_TX001_STAT7"            ,           0x1180010000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
44600         {"GMX1_TX002_STAT7"            ,           0x11800100012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
44601         {"GMX1_TX003_STAT7"            ,           0x1180010001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
44602         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
44603         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
44604         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
44605         {"GMX0_TX003_STAT8"            ,           0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
44606         {"GMX1_TX000_STAT8"            ,           0x11800100002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
44607         {"GMX1_TX001_STAT8"            ,           0x1180010000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
44608         {"GMX1_TX002_STAT8"            ,           0x11800100012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
44609         {"GMX1_TX003_STAT8"            ,           0x1180010001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
44610         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
44611         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
44612         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
44613         {"GMX0_TX003_STAT9"            ,           0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
44614         {"GMX1_TX000_STAT9"            ,           0x11800100002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
44615         {"GMX1_TX001_STAT9"            ,           0x1180010000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
44616         {"GMX1_TX002_STAT9"            ,           0x11800100012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
44617         {"GMX1_TX003_STAT9"            ,           0x1180010001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
44618         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
44619         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
44620         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
44621         {"GMX0_TX003_STATS_CTL"        ,           0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
44622         {"GMX1_TX000_STATS_CTL"        ,           0x1180010000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
44623         {"GMX1_TX001_STATS_CTL"        ,           0x1180010000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
44624         {"GMX1_TX002_STATS_CTL"        ,           0x1180010001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
44625         {"GMX1_TX003_STATS_CTL"        ,           0x1180010001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
44626         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
44627         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
44628         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
44629         {"GMX0_TX003_THRESH"           ,           0x1180008001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
44630         {"GMX1_TX000_THRESH"           ,           0x1180010000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
44631         {"GMX1_TX001_THRESH"           ,           0x1180010000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
44632         {"GMX1_TX002_THRESH"           ,           0x1180010001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
44633         {"GMX1_TX003_THRESH"           ,           0x1180010001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
44634         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
44635         {"GMX1_TX_BP"                  ,           0x11800100004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
44636         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     191},
44637         {"GMX1_TX_COL_ATTEMPT"         ,           0x1180010000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     191},
44638         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     192},
44639         {"GMX1_TX_CORRUPT"             ,           0x11800100004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     192},
44640         {"GMX0_TX_HG2_REG1"            ,           0x1180008000558ull,  CVMX_CSR_DB_TYPE_RSL,   64,     193},
44641         {"GMX1_TX_HG2_REG1"            ,           0x1180010000558ull,  CVMX_CSR_DB_TYPE_RSL,   64,     193},
44642         {"GMX0_TX_HG2_REG2"            ,           0x1180008000560ull,  CVMX_CSR_DB_TYPE_RSL,   64,     194},
44643         {"GMX1_TX_HG2_REG2"            ,           0x1180010000560ull,  CVMX_CSR_DB_TYPE_RSL,   64,     194},
44644         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     195},
44645         {"GMX1_TX_IFG"                 ,           0x1180010000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     195},
44646         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     196},
44647         {"GMX1_TX_INT_EN"              ,           0x1180010000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     196},
44648         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     197},
44649         {"GMX1_TX_INT_REG"             ,           0x1180010000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     197},
44650         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     198},
44651         {"GMX1_TX_JAM"                 ,           0x1180010000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     198},
44652         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     199},
44653         {"GMX1_TX_LFSR"                ,           0x11800100004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     199},
44654         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     200},
44655         {"GMX1_TX_OVR_BP"              ,           0x11800100004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     200},
44656         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
44657         {"GMX1_TX_PAUSE_PKT_DMAC"      ,           0x11800100004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
44658         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     202},
44659         {"GMX1_TX_PAUSE_PKT_TYPE"      ,           0x11800100004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     202},
44660         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     203},
44661         {"GMX1_TX_PRTS"                ,           0x1180010000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     203},
44662         {"GMX0_TX_XAUI_CTL"            ,           0x1180008000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     204},
44663         {"GMX1_TX_XAUI_CTL"            ,           0x1180010000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     204},
44664         {"GMX0_XAUI_EXT_LOOPBACK"      ,           0x1180008000540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     205},
44665         {"GMX1_XAUI_EXT_LOOPBACK"      ,           0x1180010000540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     205},
44666         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44667         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44668         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44669         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44670         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44671         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44672         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44673         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44674         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44675         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44676         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44677         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44678         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44679         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44680         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44681         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
44682         {"GPIO_CLK_GEN0"               ,           0x10700000008C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     207},
44683         {"GPIO_CLK_GEN1"               ,           0x10700000008C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     207},
44684         {"GPIO_CLK_GEN2"               ,           0x10700000008D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     207},
44685         {"GPIO_CLK_GEN3"               ,           0x10700000008D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     207},
44686         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     208},
44687         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     209},
44688         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     210},
44689         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     211},
44690         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     212},
44691         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     213},
44692         {"IOB_DWB_PRI_CNT"             ,           0x11800F0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
44693         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
44694         {"IOB_I2C_PRI_CNT"             ,           0x11800F0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
44695         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
44696         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
44697         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     219},
44698         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     220},
44699         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     221},
44700         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
44701         {"IOB_N2C_L2C_PRI_CNT"         ,           0x11800F0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
44702         {"IOB_N2C_RSP_PRI_CNT"         ,           0x11800F0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
44703         {"IOB_OUTB_COM_PRI_CNT"        ,           0x11800F0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     225},
44704         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     226},
44705         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     227},
44706         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
44707         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
44708         {"IOB_OUTB_FPA_PRI_CNT"        ,           0x11800F0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
44709         {"IOB_OUTB_REQ_PRI_CNT"        ,           0x11800F0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
44710         {"IOB_P2C_REQ_PRI_CNT"         ,           0x11800F0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     232},
44711         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
44712         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
44713         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
44714         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     236},
44715         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     237},
44716         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     238},
44717         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     239},
44718         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     240},
44719         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     241},
44720         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
44721         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
44722         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     244},
44723         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     245},
44724         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44725         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44726         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44727         {"IPD_PORT3_BP_PAGE_CNT"       ,           0x14F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44728         {"IPD_PORT16_BP_PAGE_CNT"      ,           0x14F00000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44729         {"IPD_PORT17_BP_PAGE_CNT"      ,           0x14F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44730         {"IPD_PORT18_BP_PAGE_CNT"      ,           0x14F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44731         {"IPD_PORT19_BP_PAGE_CNT"      ,           0x14F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44732         {"IPD_PORT32_BP_PAGE_CNT"      ,           0x14F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44733         {"IPD_PORT33_BP_PAGE_CNT"      ,           0x14F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44734         {"IPD_PORT34_BP_PAGE_CNT"      ,           0x14F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44735         {"IPD_PORT35_BP_PAGE_CNT"      ,           0x14F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
44736         {"IPD_PORT36_BP_PAGE_CNT2"     ,           0x14F0000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
44737         {"IPD_PORT37_BP_PAGE_CNT2"     ,           0x14F0000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
44738         {"IPD_PORT38_BP_PAGE_CNT2"     ,           0x14F0000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
44739         {"IPD_PORT39_BP_PAGE_CNT2"     ,           0x14F0000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
44740         {"IPD_PORT_BP_COUNTERS2_PAIR36",           0x14F0000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     248},
44741         {"IPD_PORT_BP_COUNTERS2_PAIR37",           0x14F0000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     248},
44742         {"IPD_PORT_BP_COUNTERS2_PAIR38",           0x14F0000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     248},
44743         {"IPD_PORT_BP_COUNTERS2_PAIR39",           0x14F00000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     248},
44744         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44745         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44746         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44747         {"IPD_PORT_BP_COUNTERS_PAIR3"  ,           0x14F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44748         {"IPD_PORT_BP_COUNTERS_PAIR16" ,           0x14F0000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44749         {"IPD_PORT_BP_COUNTERS_PAIR17" ,           0x14F0000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44750         {"IPD_PORT_BP_COUNTERS_PAIR18" ,           0x14F0000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44751         {"IPD_PORT_BP_COUNTERS_PAIR19" ,           0x14F0000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44752         {"IPD_PORT_BP_COUNTERS_PAIR32" ,           0x14F00000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44753         {"IPD_PORT_BP_COUNTERS_PAIR33" ,           0x14F00000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44754         {"IPD_PORT_BP_COUNTERS_PAIR34" ,           0x14F00000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44755         {"IPD_PORT_BP_COUNTERS_PAIR35" ,           0x14F00000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
44756         {"IPD_PORT_QOS_0_CNT"          ,           0x14F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44757         {"IPD_PORT_QOS_1_CNT"          ,           0x14F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44758         {"IPD_PORT_QOS_2_CNT"          ,           0x14F0000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44759         {"IPD_PORT_QOS_3_CNT"          ,           0x14F00000008A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44760         {"IPD_PORT_QOS_4_CNT"          ,           0x14F00000008A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44761         {"IPD_PORT_QOS_5_CNT"          ,           0x14F00000008B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44762         {"IPD_PORT_QOS_6_CNT"          ,           0x14F00000008B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44763         {"IPD_PORT_QOS_7_CNT"          ,           0x14F00000008C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44764         {"IPD_PORT_QOS_8_CNT"          ,           0x14F00000008C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44765         {"IPD_PORT_QOS_9_CNT"          ,           0x14F00000008D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44766         {"IPD_PORT_QOS_10_CNT"         ,           0x14F00000008D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44767         {"IPD_PORT_QOS_11_CNT"         ,           0x14F00000008E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44768         {"IPD_PORT_QOS_12_CNT"         ,           0x14F00000008E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44769         {"IPD_PORT_QOS_13_CNT"         ,           0x14F00000008F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44770         {"IPD_PORT_QOS_14_CNT"         ,           0x14F00000008F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44771         {"IPD_PORT_QOS_15_CNT"         ,           0x14F0000000900ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44772         {"IPD_PORT_QOS_16_CNT"         ,           0x14F0000000908ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44773         {"IPD_PORT_QOS_17_CNT"         ,           0x14F0000000910ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44774         {"IPD_PORT_QOS_18_CNT"         ,           0x14F0000000918ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44775         {"IPD_PORT_QOS_19_CNT"         ,           0x14F0000000920ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44776         {"IPD_PORT_QOS_20_CNT"         ,           0x14F0000000928ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44777         {"IPD_PORT_QOS_21_CNT"         ,           0x14F0000000930ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44778         {"IPD_PORT_QOS_22_CNT"         ,           0x14F0000000938ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44779         {"IPD_PORT_QOS_23_CNT"         ,           0x14F0000000940ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44780         {"IPD_PORT_QOS_24_CNT"         ,           0x14F0000000948ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44781         {"IPD_PORT_QOS_25_CNT"         ,           0x14F0000000950ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44782         {"IPD_PORT_QOS_26_CNT"         ,           0x14F0000000958ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44783         {"IPD_PORT_QOS_27_CNT"         ,           0x14F0000000960ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44784         {"IPD_PORT_QOS_28_CNT"         ,           0x14F0000000968ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44785         {"IPD_PORT_QOS_29_CNT"         ,           0x14F0000000970ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44786         {"IPD_PORT_QOS_30_CNT"         ,           0x14F0000000978ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44787         {"IPD_PORT_QOS_31_CNT"         ,           0x14F0000000980ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44788         {"IPD_PORT_QOS_128_CNT"        ,           0x14F0000000C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44789         {"IPD_PORT_QOS_129_CNT"        ,           0x14F0000000C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44790         {"IPD_PORT_QOS_130_CNT"        ,           0x14F0000000C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44791         {"IPD_PORT_QOS_131_CNT"        ,           0x14F0000000CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44792         {"IPD_PORT_QOS_132_CNT"        ,           0x14F0000000CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44793         {"IPD_PORT_QOS_133_CNT"        ,           0x14F0000000CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44794         {"IPD_PORT_QOS_134_CNT"        ,           0x14F0000000CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44795         {"IPD_PORT_QOS_135_CNT"        ,           0x14F0000000CC0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44796         {"IPD_PORT_QOS_136_CNT"        ,           0x14F0000000CC8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44797         {"IPD_PORT_QOS_137_CNT"        ,           0x14F0000000CD0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44798         {"IPD_PORT_QOS_138_CNT"        ,           0x14F0000000CD8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44799         {"IPD_PORT_QOS_139_CNT"        ,           0x14F0000000CE0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44800         {"IPD_PORT_QOS_140_CNT"        ,           0x14F0000000CE8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44801         {"IPD_PORT_QOS_141_CNT"        ,           0x14F0000000CF0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44802         {"IPD_PORT_QOS_142_CNT"        ,           0x14F0000000CF8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44803         {"IPD_PORT_QOS_143_CNT"        ,           0x14F0000000D00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44804         {"IPD_PORT_QOS_144_CNT"        ,           0x14F0000000D08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44805         {"IPD_PORT_QOS_145_CNT"        ,           0x14F0000000D10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44806         {"IPD_PORT_QOS_146_CNT"        ,           0x14F0000000D18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44807         {"IPD_PORT_QOS_147_CNT"        ,           0x14F0000000D20ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44808         {"IPD_PORT_QOS_148_CNT"        ,           0x14F0000000D28ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44809         {"IPD_PORT_QOS_149_CNT"        ,           0x14F0000000D30ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44810         {"IPD_PORT_QOS_150_CNT"        ,           0x14F0000000D38ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44811         {"IPD_PORT_QOS_151_CNT"        ,           0x14F0000000D40ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44812         {"IPD_PORT_QOS_152_CNT"        ,           0x14F0000000D48ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44813         {"IPD_PORT_QOS_153_CNT"        ,           0x14F0000000D50ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44814         {"IPD_PORT_QOS_154_CNT"        ,           0x14F0000000D58ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44815         {"IPD_PORT_QOS_155_CNT"        ,           0x14F0000000D60ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44816         {"IPD_PORT_QOS_156_CNT"        ,           0x14F0000000D68ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44817         {"IPD_PORT_QOS_157_CNT"        ,           0x14F0000000D70ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44818         {"IPD_PORT_QOS_158_CNT"        ,           0x14F0000000D78ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44819         {"IPD_PORT_QOS_159_CNT"        ,           0x14F0000000D80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44820         {"IPD_PORT_QOS_256_CNT"        ,           0x14F0000001088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44821         {"IPD_PORT_QOS_257_CNT"        ,           0x14F0000001090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44822         {"IPD_PORT_QOS_258_CNT"        ,           0x14F0000001098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44823         {"IPD_PORT_QOS_259_CNT"        ,           0x14F00000010A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44824         {"IPD_PORT_QOS_260_CNT"        ,           0x14F00000010A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44825         {"IPD_PORT_QOS_261_CNT"        ,           0x14F00000010B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44826         {"IPD_PORT_QOS_262_CNT"        ,           0x14F00000010B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44827         {"IPD_PORT_QOS_263_CNT"        ,           0x14F00000010C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44828         {"IPD_PORT_QOS_264_CNT"        ,           0x14F00000010C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44829         {"IPD_PORT_QOS_265_CNT"        ,           0x14F00000010D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44830         {"IPD_PORT_QOS_266_CNT"        ,           0x14F00000010D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44831         {"IPD_PORT_QOS_267_CNT"        ,           0x14F00000010E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44832         {"IPD_PORT_QOS_268_CNT"        ,           0x14F00000010E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44833         {"IPD_PORT_QOS_269_CNT"        ,           0x14F00000010F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44834         {"IPD_PORT_QOS_270_CNT"        ,           0x14F00000010F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44835         {"IPD_PORT_QOS_271_CNT"        ,           0x14F0000001100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44836         {"IPD_PORT_QOS_272_CNT"        ,           0x14F0000001108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44837         {"IPD_PORT_QOS_273_CNT"        ,           0x14F0000001110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44838         {"IPD_PORT_QOS_274_CNT"        ,           0x14F0000001118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44839         {"IPD_PORT_QOS_275_CNT"        ,           0x14F0000001120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44840         {"IPD_PORT_QOS_276_CNT"        ,           0x14F0000001128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44841         {"IPD_PORT_QOS_277_CNT"        ,           0x14F0000001130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44842         {"IPD_PORT_QOS_278_CNT"        ,           0x14F0000001138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44843         {"IPD_PORT_QOS_279_CNT"        ,           0x14F0000001140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44844         {"IPD_PORT_QOS_280_CNT"        ,           0x14F0000001148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44845         {"IPD_PORT_QOS_281_CNT"        ,           0x14F0000001150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44846         {"IPD_PORT_QOS_282_CNT"        ,           0x14F0000001158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44847         {"IPD_PORT_QOS_283_CNT"        ,           0x14F0000001160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44848         {"IPD_PORT_QOS_284_CNT"        ,           0x14F0000001168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44849         {"IPD_PORT_QOS_285_CNT"        ,           0x14F0000001170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44850         {"IPD_PORT_QOS_286_CNT"        ,           0x14F0000001178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44851         {"IPD_PORT_QOS_287_CNT"        ,           0x14F0000001180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44852         {"IPD_PORT_QOS_288_CNT"        ,           0x14F0000001188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44853         {"IPD_PORT_QOS_289_CNT"        ,           0x14F0000001190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44854         {"IPD_PORT_QOS_290_CNT"        ,           0x14F0000001198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44855         {"IPD_PORT_QOS_291_CNT"        ,           0x14F00000011A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44856         {"IPD_PORT_QOS_292_CNT"        ,           0x14F00000011A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44857         {"IPD_PORT_QOS_293_CNT"        ,           0x14F00000011B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44858         {"IPD_PORT_QOS_294_CNT"        ,           0x14F00000011B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44859         {"IPD_PORT_QOS_295_CNT"        ,           0x14F00000011C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44860         {"IPD_PORT_QOS_296_CNT"        ,           0x14F00000011C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44861         {"IPD_PORT_QOS_297_CNT"        ,           0x14F00000011D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44862         {"IPD_PORT_QOS_298_CNT"        ,           0x14F00000011D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44863         {"IPD_PORT_QOS_299_CNT"        ,           0x14F00000011E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44864         {"IPD_PORT_QOS_300_CNT"        ,           0x14F00000011E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44865         {"IPD_PORT_QOS_301_CNT"        ,           0x14F00000011F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44866         {"IPD_PORT_QOS_302_CNT"        ,           0x14F00000011F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44867         {"IPD_PORT_QOS_303_CNT"        ,           0x14F0000001200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44868         {"IPD_PORT_QOS_304_CNT"        ,           0x14F0000001208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44869         {"IPD_PORT_QOS_305_CNT"        ,           0x14F0000001210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44870         {"IPD_PORT_QOS_306_CNT"        ,           0x14F0000001218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44871         {"IPD_PORT_QOS_307_CNT"        ,           0x14F0000001220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44872         {"IPD_PORT_QOS_308_CNT"        ,           0x14F0000001228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44873         {"IPD_PORT_QOS_309_CNT"        ,           0x14F0000001230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44874         {"IPD_PORT_QOS_310_CNT"        ,           0x14F0000001238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44875         {"IPD_PORT_QOS_311_CNT"        ,           0x14F0000001240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44876         {"IPD_PORT_QOS_312_CNT"        ,           0x14F0000001248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44877         {"IPD_PORT_QOS_313_CNT"        ,           0x14F0000001250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44878         {"IPD_PORT_QOS_314_CNT"        ,           0x14F0000001258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44879         {"IPD_PORT_QOS_315_CNT"        ,           0x14F0000001260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44880         {"IPD_PORT_QOS_316_CNT"        ,           0x14F0000001268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44881         {"IPD_PORT_QOS_317_CNT"        ,           0x14F0000001270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44882         {"IPD_PORT_QOS_318_CNT"        ,           0x14F0000001278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44883         {"IPD_PORT_QOS_319_CNT"        ,           0x14F0000001280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
44884         {"IPD_PORT_QOS_INT0"           ,           0x14F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     251},
44885         {"IPD_PORT_QOS_INT2"           ,           0x14F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     251},
44886         {"IPD_PORT_QOS_INT4"           ,           0x14F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     251},
44887         {"IPD_PORT_QOS_INT_ENB0"       ,           0x14F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     252},
44888         {"IPD_PORT_QOS_INT_ENB2"       ,           0x14F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     252},
44889         {"IPD_PORT_QOS_INT_ENB4"       ,           0x14F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     252},
44890         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     253},
44891         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     254},
44892         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     255},
44893         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     256},
44894         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     257},
44895         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     257},
44896         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     257},
44897         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     257},
44898         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     257},
44899         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     257},
44900         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     257},
44901         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     257},
44902         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     258},
44903         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     259},
44904         {"IPD_RED_PORT_ENABLE2"        ,           0x14F00000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     260},
44905         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     261},
44906         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     261},
44907         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     261},
44908         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     261},
44909         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     261},
44910         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     261},
44911         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     261},
44912         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     261},
44913         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     262},
44914         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     263},
44915         {"IPD_SUB_PORT_QOS_CNT"        ,           0x14F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     264},
44916         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     265},
44917         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     266},
44918         {"KEY_BIST_REG"                ,           0x1180020000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
44919         {"KEY_CTL_STATUS"              ,           0x1180020000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
44920         {"KEY_INT_ENB"                 ,           0x1180020000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
44921         {"KEY_INT_SUM"                 ,           0x1180020000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
44922         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
44923         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
44924         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
44925         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
44926         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
44927         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
44928         {"L2C_GRPWRR0"                 ,           0x11800800000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
44929         {"L2C_GRPWRR1"                 ,           0x11800800000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
44930         {"L2C_INT_EN"                  ,           0x1180080000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
44931         {"L2C_INT_STAT"                ,           0x11800800000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
44932         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
44933         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
44934         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
44935         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
44936         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
44937         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
44938         {"L2C_OOB"                     ,           0x11800800000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     287},
44939         {"L2C_OOB1"                    ,           0x11800800000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     288},
44940         {"L2C_OOB2"                    ,           0x11800800000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     289},
44941         {"L2C_OOB3"                    ,           0x11800800000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
44942         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
44943         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
44944         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
44945         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
44946         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     292},
44947         {"L2C_PPGRP"                   ,           0x11800800000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
44948         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     294},
44949         {"L2C_SPAR1"                   ,           0x1180080000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     295},
44950         {"L2C_SPAR2"                   ,           0x1180080000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     296},
44951         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
44952         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     298},
44953         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
44954         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
44955         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
44956         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
44957         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
44958         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
44959         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
44960         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
44961         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
44962         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
44963         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
44964         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
44965         {"LED_BLINK"                   ,           0x1180000001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
44966         {"LED_CLK_PHASE"               ,           0x1180000001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
44967         {"LED_CYLON"                   ,           0x1180000001AF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
44968         {"LED_DBG"                     ,           0x1180000001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
44969         {"LED_EN"                      ,           0x1180000001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
44970         {"LED_POLARITY"                ,           0x1180000001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
44971         {"LED_PRT"                     ,           0x1180000001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
44972         {"LED_PRT_FMT"                 ,           0x1180000001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
44973         {"LED_PRT_STATUS0"             ,           0x1180000001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
44974         {"LED_PRT_STATUS1"             ,           0x1180000001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
44975         {"LED_PRT_STATUS2"             ,           0x1180000001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
44976         {"LED_PRT_STATUS3"             ,           0x1180000001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
44977         {"LED_PRT_STATUS4"             ,           0x1180000001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
44978         {"LED_PRT_STATUS5"             ,           0x1180000001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
44979         {"LED_PRT_STATUS6"             ,           0x1180000001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
44980         {"LED_PRT_STATUS7"             ,           0x1180000001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
44981         {"LED_UDD_CNT0"                ,           0x1180000001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
44982         {"LED_UDD_CNT1"                ,           0x1180000001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
44983         {"LED_UDD_DAT0"                ,           0x1180000001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
44984         {"LED_UDD_DAT1"                ,           0x1180000001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
44985         {"LED_UDD_DAT_CLR0"            ,           0x1180000001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
44986         {"LED_UDD_DAT_CLR1"            ,           0x1180000001AD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
44987         {"LED_UDD_DAT_SET0"            ,           0x1180000001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
44988         {"LED_UDD_DAT_SET1"            ,           0x1180000001AD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
44989         {"LMC0_BIST_CTL"               ,           0x11800880000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
44990         {"LMC1_BIST_CTL"               ,           0x11800E80000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
44991         {"LMC0_BIST_RESULT"            ,           0x11800880000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
44992         {"LMC1_BIST_RESULT"            ,           0x11800E80000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
44993         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
44994         {"LMC1_COMP_CTL"               ,           0x11800E8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
44995         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
44996         {"LMC1_CTL"                    ,           0x11800E8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
44997         {"LMC0_CTL1"                   ,           0x1180088000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
44998         {"LMC1_CTL1"                   ,           0x11800E8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
44999         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
45000         {"LMC1_DCLK_CNT_HI"            ,           0x11800E8000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
45001         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
45002         {"LMC1_DCLK_CNT_LO"            ,           0x11800E8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
45003         {"LMC0_DCLK_CTL"               ,           0x11800880000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
45004         {"LMC1_DCLK_CTL"               ,           0x11800E80000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
45005         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
45006         {"LMC1_DDR2_CTL"               ,           0x11800E8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
45007         {"LMC0_DELAY_CFG"              ,           0x1180088000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
45008         {"LMC1_DELAY_CFG"              ,           0x11800E8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
45009         {"LMC0_DLL_CTL"                ,           0x11800880000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
45010         {"LMC1_DLL_CTL"                ,           0x11800E80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
45011         {"LMC0_DUAL_MEMCFG"            ,           0x1180088000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     335},
45012         {"LMC1_DUAL_MEMCFG"            ,           0x11800E8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     335},
45013         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     336},
45014         {"LMC1_ECC_SYND"               ,           0x11800E8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     336},
45015         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     337},
45016         {"LMC1_FADR"                   ,           0x11800E8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     337},
45017         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     338},
45018         {"LMC1_IFB_CNT_HI"             ,           0x11800E8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     338},
45019         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     339},
45020         {"LMC1_IFB_CNT_LO"             ,           0x11800E8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     339},
45021         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
45022         {"LMC1_MEM_CFG0"               ,           0x11800E8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
45023         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     341},
45024         {"LMC1_MEM_CFG1"               ,           0x11800E8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     341},
45025         {"LMC0_NXM"                    ,           0x11800880000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     342},
45026         {"LMC1_NXM"                    ,           0x11800E80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     342},
45027         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
45028         {"LMC1_OPS_CNT_HI"             ,           0x11800E8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
45029         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
45030         {"LMC1_OPS_CNT_LO"             ,           0x11800E8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
45031         {"LMC0_PLL_CTL"                ,           0x11800880000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     345},
45032         {"LMC1_PLL_CTL"                ,           0x11800E80000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     345},
45033         {"LMC0_PLL_STATUS"             ,           0x11800880000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     346},
45034         {"LMC1_PLL_STATUS"             ,           0x11800E80000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     346},
45035         {"LMC0_READ_LEVEL_CTL"         ,           0x1180088000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     347},
45036         {"LMC1_READ_LEVEL_CTL"         ,           0x11800E8000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     347},
45037         {"LMC0_READ_LEVEL_DBG"         ,           0x1180088000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     348},
45038         {"LMC1_READ_LEVEL_DBG"         ,           0x11800E8000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     348},
45039         {"LMC0_READ_LEVEL_RANK000"     ,           0x1180088000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
45040         {"LMC0_READ_LEVEL_RANK001"     ,           0x1180088000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
45041         {"LMC0_READ_LEVEL_RANK002"     ,           0x1180088000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
45042         {"LMC0_READ_LEVEL_RANK003"     ,           0x1180088000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
45043         {"LMC1_READ_LEVEL_RANK000"     ,           0x11800E8000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
45044         {"LMC1_READ_LEVEL_RANK001"     ,           0x11800E8000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
45045         {"LMC1_READ_LEVEL_RANK002"     ,           0x11800E8000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
45046         {"LMC1_READ_LEVEL_RANK003"     ,           0x11800E8000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
45047         {"LMC0_RODT_COMP_CTL"          ,           0x11800880000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
45048         {"LMC1_RODT_COMP_CTL"          ,           0x11800E80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
45049         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     351},
45050         {"LMC1_RODT_CTL"               ,           0x11800E8000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     351},
45051         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     352},
45052         {"LMC1_WODT_CTL0"              ,           0x11800E8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     352},
45053         {"LMC0_WODT_CTL1"              ,           0x1180088000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     353},
45054         {"LMC1_WODT_CTL1"              ,           0x11800E8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     353},
45055         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     354},
45056         {"MIO_BOOT_COMP"               ,           0x11800000000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     355},
45057         {"MIO_BOOT_DMA_CFG0"           ,           0x1180000000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     356},
45058         {"MIO_BOOT_DMA_CFG1"           ,           0x1180000000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     356},
45059         {"MIO_BOOT_DMA_CFG2"           ,           0x1180000000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     356},
45060         {"MIO_BOOT_DMA_INT0"           ,           0x1180000000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     357},
45061         {"MIO_BOOT_DMA_INT1"           ,           0x1180000000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     357},
45062         {"MIO_BOOT_DMA_INT2"           ,           0x1180000000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     357},
45063         {"MIO_BOOT_DMA_INT_EN0"        ,           0x1180000000150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     358},
45064         {"MIO_BOOT_DMA_INT_EN1"        ,           0x1180000000158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     358},
45065         {"MIO_BOOT_DMA_INT_EN2"        ,           0x1180000000160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     358},
45066         {"MIO_BOOT_DMA_TIM0"           ,           0x1180000000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     359},
45067         {"MIO_BOOT_DMA_TIM1"           ,           0x1180000000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     359},
45068         {"MIO_BOOT_DMA_TIM2"           ,           0x1180000000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     359},
45069         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     360},
45070         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     361},
45071         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     362},
45072         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     363},
45073         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     363},
45074         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     364},
45075         {"MIO_BOOT_PIN_DEFS"           ,           0x11800000000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     365},
45076         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
45077         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
45078         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
45079         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
45080         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
45081         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
45082         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
45083         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
45084         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
45085         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
45086         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
45087         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
45088         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
45089         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
45090         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
45091         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
45092         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     368},
45093         {"MIO_FUS_BNK_DAT0"            ,           0x1180000001520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
45094         {"MIO_FUS_BNK_DAT1"            ,           0x1180000001528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
45095         {"MIO_FUS_BNK_DAT2"            ,           0x1180000001530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
45096         {"MIO_FUS_BNK_DAT3"            ,           0x1180000001538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
45097         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     370},
45098         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     371},
45099         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     372},
45100         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     373},
45101         {"MIO_FUS_EMA"                 ,           0x1180000001550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     374},
45102         {"MIO_FUS_PDF"                 ,           0x1180000001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     375},
45103         {"MIO_FUS_PLL"                 ,           0x1180000001580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     376},
45104         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     377},
45105         {"MIO_FUS_PROG_TIMES"          ,           0x1180000001518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     378},
45106         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     379},
45107         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     380},
45108         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     381},
45109         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     382},
45110         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     383},
45111         {"MIO_TWS1_INT"                ,           0x1180000001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     383},
45112         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     384},
45113         {"MIO_TWS1_SW_TWSI"            ,           0x1180000001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     384},
45114         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     385},
45115         {"MIO_TWS1_SW_TWSI_EXT"        ,           0x1180000001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     385},
45116         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     386},
45117         {"MIO_TWS1_TWSI_SW"            ,           0x1180000001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     386},
45118         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     387},
45119         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     387},
45120         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     388},
45121         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     388},
45122         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     389},
45123         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     389},
45124         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     390},
45125         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     390},
45126         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     391},
45127         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     391},
45128         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     392},
45129         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     392},
45130         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
45131         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
45132         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     394},
45133         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     394},
45134         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     395},
45135         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     395},
45136         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     396},
45137         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     396},
45138         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     397},
45139         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     397},
45140         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     398},
45141         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     398},
45142         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     399},
45143         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     399},
45144         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     400},
45145         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     400},
45146         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
45147         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
45148         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
45149         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
45150         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     403},
45151         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     403},
45152         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     404},
45153         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     404},
45154         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     405},
45155         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     405},
45156         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
45157         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
45158         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
45159         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
45160         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     408},
45161         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     408},
45162         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     409},
45163         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     409},
45164         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
45165         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
45166         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
45167         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
45168         {"MIX0_BIST"                   ,           0x1070000100078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     412},
45169         {"MIX0_CTL"                    ,           0x1070000100020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     413},
45170         {"MIX0_INTENA"                 ,           0x1070000100050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     414},
45171         {"MIX0_IRCNT"                  ,           0x1070000100030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     415},
45172         {"MIX0_IRHWM"                  ,           0x1070000100028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     416},
45173         {"MIX0_IRING1"                 ,           0x1070000100010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     417},
45174         {"MIX0_IRING2"                 ,           0x1070000100018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     418},
45175         {"MIX0_ISR"                    ,           0x1070000100048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     419},
45176         {"MIX0_ORCNT"                  ,           0x1070000100040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     420},
45177         {"MIX0_ORHWM"                  ,           0x1070000100038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     421},
45178         {"MIX0_ORING1"                 ,           0x1070000100000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     422},
45179         {"MIX0_ORING2"                 ,           0x1070000100008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     423},
45180         {"MIX0_REMCNT"                 ,           0x1070000100058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     424},
45181         {"NPEI_BAR1_INDEX0"            ,           0x11F0000008000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45182         {"NPEI_BAR1_INDEX1"            ,           0x11F0000008010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45183         {"NPEI_BAR1_INDEX2"            ,           0x11F0000008020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45184         {"NPEI_BAR1_INDEX3"            ,           0x11F0000008030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45185         {"NPEI_BAR1_INDEX4"            ,           0x11F0000008040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45186         {"NPEI_BAR1_INDEX5"            ,           0x11F0000008050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45187         {"NPEI_BAR1_INDEX6"            ,           0x11F0000008060ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45188         {"NPEI_BAR1_INDEX7"            ,           0x11F0000008070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45189         {"NPEI_BAR1_INDEX8"            ,           0x11F0000008080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45190         {"NPEI_BAR1_INDEX9"            ,           0x11F0000008090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45191         {"NPEI_BAR1_INDEX10"           ,           0x11F00000080A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45192         {"NPEI_BAR1_INDEX11"           ,           0x11F00000080B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45193         {"NPEI_BAR1_INDEX12"           ,           0x11F00000080C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45194         {"NPEI_BAR1_INDEX13"           ,           0x11F00000080D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45195         {"NPEI_BAR1_INDEX14"           ,           0x11F00000080E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45196         {"NPEI_BAR1_INDEX15"           ,           0x11F00000080F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45197         {"NPEI_BAR1_INDEX16"           ,           0x11F0000008100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45198         {"NPEI_BAR1_INDEX17"           ,           0x11F0000008110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45199         {"NPEI_BAR1_INDEX18"           ,           0x11F0000008120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45200         {"NPEI_BAR1_INDEX19"           ,           0x11F0000008130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45201         {"NPEI_BAR1_INDEX20"           ,           0x11F0000008140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45202         {"NPEI_BAR1_INDEX21"           ,           0x11F0000008150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45203         {"NPEI_BAR1_INDEX22"           ,           0x11F0000008160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45204         {"NPEI_BAR1_INDEX23"           ,           0x11F0000008170ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45205         {"NPEI_BAR1_INDEX24"           ,           0x11F0000008180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45206         {"NPEI_BAR1_INDEX25"           ,           0x11F0000008190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45207         {"NPEI_BAR1_INDEX26"           ,           0x11F00000081A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45208         {"NPEI_BAR1_INDEX27"           ,           0x11F00000081B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45209         {"NPEI_BAR1_INDEX28"           ,           0x11F00000081C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45210         {"NPEI_BAR1_INDEX29"           ,           0x11F00000081D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45211         {"NPEI_BAR1_INDEX30"           ,           0x11F00000081E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45212         {"NPEI_BAR1_INDEX31"           ,           0x11F00000081F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     425},
45213         {"NPEI_BIST_STATUS"            ,           0x11F0000008580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     426},
45214         {"NPEI_BIST_STATUS2"           ,           0x11F0000008680ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     427},
45215         {"NPEI_CTL_PORT0"              ,           0x11F0000008250ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     428},
45216         {"NPEI_CTL_PORT1"              ,           0x11F0000008260ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     429},
45217         {"NPEI_CTL_STATUS"             ,           0x11F0000008570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     430},
45218         {"NPEI_CTL_STATUS2"            ,           0x11F000000BC00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     431},
45219         {"NPEI_DATA_OUT_CNT"           ,           0x11F00000085F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     432},
45220         {"NPEI_DBG_DATA"               ,           0x11F0000008510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     433},
45221         {"NPEI_DBG_SELECT"             ,           0x11F0000008500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     434},
45222         {"NPEI_DMA0_COUNTS"            ,           0x11F0000008450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     435},
45223         {"NPEI_DMA1_COUNTS"            ,           0x11F0000008460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     435},
45224         {"NPEI_DMA2_COUNTS"            ,           0x11F0000008470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     435},
45225         {"NPEI_DMA3_COUNTS"            ,           0x11F0000008480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     435},
45226         {"NPEI_DMA4_COUNTS"            ,           0x11F0000008490ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     435},
45227         {"NPEI_DMA0_DBELL"             ,           0x11F00000083B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     436},
45228         {"NPEI_DMA1_DBELL"             ,           0x11F00000083C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     436},
45229         {"NPEI_DMA2_DBELL"             ,           0x11F00000083D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     436},
45230         {"NPEI_DMA3_DBELL"             ,           0x11F00000083E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     436},
45231         {"NPEI_DMA4_DBELL"             ,           0x11F00000083F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     436},
45232         {"NPEI_DMA0_IBUFF_SADDR"       ,           0x11F0000008400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
45233         {"NPEI_DMA1_IBUFF_SADDR"       ,           0x11F0000008410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
45234         {"NPEI_DMA2_IBUFF_SADDR"       ,           0x11F0000008420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
45235         {"NPEI_DMA3_IBUFF_SADDR"       ,           0x11F0000008430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
45236         {"NPEI_DMA4_IBUFF_SADDR"       ,           0x11F0000008440ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
45237         {"NPEI_DMA0_NADDR"             ,           0x11F00000084A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     438},
45238         {"NPEI_DMA1_NADDR"             ,           0x11F00000084B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     438},
45239         {"NPEI_DMA2_NADDR"             ,           0x11F00000084C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     438},
45240         {"NPEI_DMA3_NADDR"             ,           0x11F00000084D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     438},
45241         {"NPEI_DMA4_NADDR"             ,           0x11F00000084E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     438},
45242         {"NPEI_DMA0_INT_LEVEL"         ,           0x11F00000085C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     439},
45243         {"NPEI_DMA1_INT_LEVEL"         ,           0x11F00000085D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     440},
45244         {"NPEI_DMA_CNTS"               ,           0x11F00000085E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     441},
45245         {"NPEI_DMA_CONTROL"            ,           0x11F00000083A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     442},
45246         {"NPEI_DMA_PCIE_REQ_NUM"       ,           0x11F00000085B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     443},
45247         {"NPEI_INT_A_ENB"              ,           0x11F0000008560ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
45248         {"NPEI_INT_A_ENB2"             ,           0x11F000000BCE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     445},
45249         {"NPEI_INT_A_SUM"              ,           0x11F0000008550ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     446},
45250         {"NPEI_INT_ENB"                ,           0x11F0000008540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     447},
45251         {"NPEI_INT_ENB2"               ,           0x11F000000BCD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     448},
45252         {"NPEI_INT_INFO"               ,           0x11F0000008590ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     449},
45253         {"NPEI_INT_SUM"                ,           0x11F0000008530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     450},
45254         {"NPEI_INT_SUM2"               ,           0x11F000000BCC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     451},
45255         {"NPEI_LAST_WIN_RDATA0"        ,           0x11F0000008600ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     452},
45256         {"NPEI_LAST_WIN_RDATA1"        ,           0x11F0000008610ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     453},
45257         {"NPEI_MEM_ACCESS_CTL"         ,           0x11F00000084F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     454},
45258         {"NPEI_MEM_ACCESS_SUBID12"     ,           0x11F0000008280ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45259         {"NPEI_MEM_ACCESS_SUBID13"     ,           0x11F0000008290ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45260         {"NPEI_MEM_ACCESS_SUBID14"     ,           0x11F00000082A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45261         {"NPEI_MEM_ACCESS_SUBID15"     ,           0x11F00000082B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45262         {"NPEI_MEM_ACCESS_SUBID16"     ,           0x11F00000082C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45263         {"NPEI_MEM_ACCESS_SUBID17"     ,           0x11F00000082D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45264         {"NPEI_MEM_ACCESS_SUBID18"     ,           0x11F00000082E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45265         {"NPEI_MEM_ACCESS_SUBID19"     ,           0x11F00000082F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45266         {"NPEI_MEM_ACCESS_SUBID20"     ,           0x11F0000008300ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45267         {"NPEI_MEM_ACCESS_SUBID21"     ,           0x11F0000008310ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45268         {"NPEI_MEM_ACCESS_SUBID22"     ,           0x11F0000008320ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45269         {"NPEI_MEM_ACCESS_SUBID23"     ,           0x11F0000008330ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45270         {"NPEI_MEM_ACCESS_SUBID24"     ,           0x11F0000008340ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45271         {"NPEI_MEM_ACCESS_SUBID25"     ,           0x11F0000008350ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45272         {"NPEI_MEM_ACCESS_SUBID26"     ,           0x11F0000008360ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45273         {"NPEI_MEM_ACCESS_SUBID27"     ,           0x11F0000008370ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
45274         {"NPEI_MSI_ENB0"               ,           0x11F000000BC50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     456},
45275         {"NPEI_MSI_ENB1"               ,           0x11F000000BC60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     457},
45276         {"NPEI_MSI_ENB2"               ,           0x11F000000BC70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     458},
45277         {"NPEI_MSI_ENB3"               ,           0x11F000000BC80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     459},
45278         {"NPEI_MSI_RCV0"               ,           0x11F000000BC10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     460},
45279         {"NPEI_MSI_RCV1"               ,           0x11F000000BC20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     461},
45280         {"NPEI_MSI_RCV2"               ,           0x11F000000BC30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     462},
45281         {"NPEI_MSI_RCV3"               ,           0x11F000000BC40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     463},
45282         {"NPEI_MSI_RD_MAP"             ,           0x11F000000BCA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     464},
45283         {"NPEI_MSI_W1C_ENB0"           ,           0x11F000000BCF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     465},
45284         {"NPEI_MSI_W1C_ENB1"           ,           0x11F000000BD00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     466},
45285         {"NPEI_MSI_W1C_ENB2"           ,           0x11F000000BD10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     467},
45286         {"NPEI_MSI_W1C_ENB3"           ,           0x11F000000BD20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     468},
45287         {"NPEI_MSI_W1S_ENB0"           ,           0x11F000000BD30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     469},
45288         {"NPEI_MSI_W1S_ENB1"           ,           0x11F000000BD40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
45289         {"NPEI_MSI_W1S_ENB2"           ,           0x11F000000BD50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     471},
45290         {"NPEI_MSI_W1S_ENB3"           ,           0x11F000000BD60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     472},
45291         {"NPEI_MSI_WR_MAP"             ,           0x11F000000BC90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     473},
45292         {"NPEI_PCIE_CREDIT_CNT"        ,           0x11F000000BD70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     474},
45293         {"NPEI_PCIE_MSI_RCV"           ,           0x11F000000BCB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     475},
45294         {"NPEI_PCIE_MSI_RCV_B1"        ,           0x11F0000008650ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     476},
45295         {"NPEI_PCIE_MSI_RCV_B2"        ,           0x11F0000008660ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     477},
45296         {"NPEI_PCIE_MSI_RCV_B3"        ,           0x11F0000008670ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     478},
45297         {"NPEI_PKT0_CNTS"              ,           0x11F000000A400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45298         {"NPEI_PKT1_CNTS"              ,           0x11F000000A410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45299         {"NPEI_PKT2_CNTS"              ,           0x11F000000A420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45300         {"NPEI_PKT3_CNTS"              ,           0x11F000000A430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45301         {"NPEI_PKT4_CNTS"              ,           0x11F000000A440ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45302         {"NPEI_PKT5_CNTS"              ,           0x11F000000A450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45303         {"NPEI_PKT6_CNTS"              ,           0x11F000000A460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45304         {"NPEI_PKT7_CNTS"              ,           0x11F000000A470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45305         {"NPEI_PKT8_CNTS"              ,           0x11F000000A480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45306         {"NPEI_PKT9_CNTS"              ,           0x11F000000A490ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45307         {"NPEI_PKT10_CNTS"             ,           0x11F000000A4A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45308         {"NPEI_PKT11_CNTS"             ,           0x11F000000A4B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45309         {"NPEI_PKT12_CNTS"             ,           0x11F000000A4C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45310         {"NPEI_PKT13_CNTS"             ,           0x11F000000A4D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45311         {"NPEI_PKT14_CNTS"             ,           0x11F000000A4E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45312         {"NPEI_PKT15_CNTS"             ,           0x11F000000A4F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45313         {"NPEI_PKT16_CNTS"             ,           0x11F000000A500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45314         {"NPEI_PKT17_CNTS"             ,           0x11F000000A510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45315         {"NPEI_PKT18_CNTS"             ,           0x11F000000A520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45316         {"NPEI_PKT19_CNTS"             ,           0x11F000000A530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45317         {"NPEI_PKT20_CNTS"             ,           0x11F000000A540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45318         {"NPEI_PKT21_CNTS"             ,           0x11F000000A550ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45319         {"NPEI_PKT22_CNTS"             ,           0x11F000000A560ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45320         {"NPEI_PKT23_CNTS"             ,           0x11F000000A570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45321         {"NPEI_PKT24_CNTS"             ,           0x11F000000A580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45322         {"NPEI_PKT25_CNTS"             ,           0x11F000000A590ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45323         {"NPEI_PKT26_CNTS"             ,           0x11F000000A5A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45324         {"NPEI_PKT27_CNTS"             ,           0x11F000000A5B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45325         {"NPEI_PKT28_CNTS"             ,           0x11F000000A5C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45326         {"NPEI_PKT29_CNTS"             ,           0x11F000000A5D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45327         {"NPEI_PKT30_CNTS"             ,           0x11F000000A5E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45328         {"NPEI_PKT31_CNTS"             ,           0x11F000000A5F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
45329         {"NPEI_PKT0_IN_BP"             ,           0x11F000000B800ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45330         {"NPEI_PKT1_IN_BP"             ,           0x11F000000B810ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45331         {"NPEI_PKT2_IN_BP"             ,           0x11F000000B820ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45332         {"NPEI_PKT3_IN_BP"             ,           0x11F000000B830ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45333         {"NPEI_PKT4_IN_BP"             ,           0x11F000000B840ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45334         {"NPEI_PKT5_IN_BP"             ,           0x11F000000B850ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45335         {"NPEI_PKT6_IN_BP"             ,           0x11F000000B860ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45336         {"NPEI_PKT7_IN_BP"             ,           0x11F000000B870ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45337         {"NPEI_PKT8_IN_BP"             ,           0x11F000000B880ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45338         {"NPEI_PKT9_IN_BP"             ,           0x11F000000B890ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45339         {"NPEI_PKT10_IN_BP"            ,           0x11F000000B8A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45340         {"NPEI_PKT11_IN_BP"            ,           0x11F000000B8B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45341         {"NPEI_PKT12_IN_BP"            ,           0x11F000000B8C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45342         {"NPEI_PKT13_IN_BP"            ,           0x11F000000B8D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45343         {"NPEI_PKT14_IN_BP"            ,           0x11F000000B8E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45344         {"NPEI_PKT15_IN_BP"            ,           0x11F000000B8F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45345         {"NPEI_PKT16_IN_BP"            ,           0x11F000000B900ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45346         {"NPEI_PKT17_IN_BP"            ,           0x11F000000B910ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45347         {"NPEI_PKT18_IN_BP"            ,           0x11F000000B920ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45348         {"NPEI_PKT19_IN_BP"            ,           0x11F000000B930ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45349         {"NPEI_PKT20_IN_BP"            ,           0x11F000000B940ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45350         {"NPEI_PKT21_IN_BP"            ,           0x11F000000B950ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45351         {"NPEI_PKT22_IN_BP"            ,           0x11F000000B960ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45352         {"NPEI_PKT23_IN_BP"            ,           0x11F000000B970ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45353         {"NPEI_PKT24_IN_BP"            ,           0x11F000000B980ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45354         {"NPEI_PKT25_IN_BP"            ,           0x11F000000B990ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45355         {"NPEI_PKT26_IN_BP"            ,           0x11F000000B9A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45356         {"NPEI_PKT27_IN_BP"            ,           0x11F000000B9B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45357         {"NPEI_PKT28_IN_BP"            ,           0x11F000000B9C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45358         {"NPEI_PKT29_IN_BP"            ,           0x11F000000B9D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45359         {"NPEI_PKT30_IN_BP"            ,           0x11F000000B9E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45360         {"NPEI_PKT31_IN_BP"            ,           0x11F000000B9F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
45361         {"NPEI_PKT0_INSTR_BADDR"       ,           0x11F000000A800ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45362         {"NPEI_PKT1_INSTR_BADDR"       ,           0x11F000000A810ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45363         {"NPEI_PKT2_INSTR_BADDR"       ,           0x11F000000A820ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45364         {"NPEI_PKT3_INSTR_BADDR"       ,           0x11F000000A830ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45365         {"NPEI_PKT4_INSTR_BADDR"       ,           0x11F000000A840ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45366         {"NPEI_PKT5_INSTR_BADDR"       ,           0x11F000000A850ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45367         {"NPEI_PKT6_INSTR_BADDR"       ,           0x11F000000A860ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45368         {"NPEI_PKT7_INSTR_BADDR"       ,           0x11F000000A870ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45369         {"NPEI_PKT8_INSTR_BADDR"       ,           0x11F000000A880ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45370         {"NPEI_PKT9_INSTR_BADDR"       ,           0x11F000000A890ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45371         {"NPEI_PKT10_INSTR_BADDR"      ,           0x11F000000A8A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45372         {"NPEI_PKT11_INSTR_BADDR"      ,           0x11F000000A8B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45373         {"NPEI_PKT12_INSTR_BADDR"      ,           0x11F000000A8C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45374         {"NPEI_PKT13_INSTR_BADDR"      ,           0x11F000000A8D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45375         {"NPEI_PKT14_INSTR_BADDR"      ,           0x11F000000A8E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45376         {"NPEI_PKT15_INSTR_BADDR"      ,           0x11F000000A8F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45377         {"NPEI_PKT16_INSTR_BADDR"      ,           0x11F000000A900ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45378         {"NPEI_PKT17_INSTR_BADDR"      ,           0x11F000000A910ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45379         {"NPEI_PKT18_INSTR_BADDR"      ,           0x11F000000A920ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45380         {"NPEI_PKT19_INSTR_BADDR"      ,           0x11F000000A930ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45381         {"NPEI_PKT20_INSTR_BADDR"      ,           0x11F000000A940ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45382         {"NPEI_PKT21_INSTR_BADDR"      ,           0x11F000000A950ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45383         {"NPEI_PKT22_INSTR_BADDR"      ,           0x11F000000A960ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45384         {"NPEI_PKT23_INSTR_BADDR"      ,           0x11F000000A970ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45385         {"NPEI_PKT24_INSTR_BADDR"      ,           0x11F000000A980ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45386         {"NPEI_PKT25_INSTR_BADDR"      ,           0x11F000000A990ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45387         {"NPEI_PKT26_INSTR_BADDR"      ,           0x11F000000A9A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45388         {"NPEI_PKT27_INSTR_BADDR"      ,           0x11F000000A9B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45389         {"NPEI_PKT28_INSTR_BADDR"      ,           0x11F000000A9C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45390         {"NPEI_PKT29_INSTR_BADDR"      ,           0x11F000000A9D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45391         {"NPEI_PKT30_INSTR_BADDR"      ,           0x11F000000A9E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45392         {"NPEI_PKT31_INSTR_BADDR"      ,           0x11F000000A9F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
45393         {"NPEI_PKT0_INSTR_BAOFF_DBELL" ,           0x11F000000AC00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45394         {"NPEI_PKT1_INSTR_BAOFF_DBELL" ,           0x11F000000AC10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45395         {"NPEI_PKT2_INSTR_BAOFF_DBELL" ,           0x11F000000AC20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45396         {"NPEI_PKT3_INSTR_BAOFF_DBELL" ,           0x11F000000AC30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45397         {"NPEI_PKT4_INSTR_BAOFF_DBELL" ,           0x11F000000AC40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45398         {"NPEI_PKT5_INSTR_BAOFF_DBELL" ,           0x11F000000AC50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45399         {"NPEI_PKT6_INSTR_BAOFF_DBELL" ,           0x11F000000AC60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45400         {"NPEI_PKT7_INSTR_BAOFF_DBELL" ,           0x11F000000AC70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45401         {"NPEI_PKT8_INSTR_BAOFF_DBELL" ,           0x11F000000AC80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45402         {"NPEI_PKT9_INSTR_BAOFF_DBELL" ,           0x11F000000AC90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45403         {"NPEI_PKT10_INSTR_BAOFF_DBELL",           0x11F000000ACA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45404         {"NPEI_PKT11_INSTR_BAOFF_DBELL",           0x11F000000ACB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45405         {"NPEI_PKT12_INSTR_BAOFF_DBELL",           0x11F000000ACC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45406         {"NPEI_PKT13_INSTR_BAOFF_DBELL",           0x11F000000ACD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45407         {"NPEI_PKT14_INSTR_BAOFF_DBELL",           0x11F000000ACE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45408         {"NPEI_PKT15_INSTR_BAOFF_DBELL",           0x11F000000ACF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45409         {"NPEI_PKT16_INSTR_BAOFF_DBELL",           0x11F000000AD00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45410         {"NPEI_PKT17_INSTR_BAOFF_DBELL",           0x11F000000AD10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45411         {"NPEI_PKT18_INSTR_BAOFF_DBELL",           0x11F000000AD20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45412         {"NPEI_PKT19_INSTR_BAOFF_DBELL",           0x11F000000AD30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45413         {"NPEI_PKT20_INSTR_BAOFF_DBELL",           0x11F000000AD40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45414         {"NPEI_PKT21_INSTR_BAOFF_DBELL",           0x11F000000AD50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45415         {"NPEI_PKT22_INSTR_BAOFF_DBELL",           0x11F000000AD60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45416         {"NPEI_PKT23_INSTR_BAOFF_DBELL",           0x11F000000AD70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45417         {"NPEI_PKT24_INSTR_BAOFF_DBELL",           0x11F000000AD80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45418         {"NPEI_PKT25_INSTR_BAOFF_DBELL",           0x11F000000AD90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45419         {"NPEI_PKT26_INSTR_BAOFF_DBELL",           0x11F000000ADA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45420         {"NPEI_PKT27_INSTR_BAOFF_DBELL",           0x11F000000ADB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45421         {"NPEI_PKT28_INSTR_BAOFF_DBELL",           0x11F000000ADC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45422         {"NPEI_PKT29_INSTR_BAOFF_DBELL",           0x11F000000ADD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45423         {"NPEI_PKT30_INSTR_BAOFF_DBELL",           0x11F000000ADE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45424         {"NPEI_PKT31_INSTR_BAOFF_DBELL",           0x11F000000ADF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
45425         {"NPEI_PKT0_INSTR_FIFO_RSIZE"  ,           0x11F000000B000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45426         {"NPEI_PKT1_INSTR_FIFO_RSIZE"  ,           0x11F000000B010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45427         {"NPEI_PKT2_INSTR_FIFO_RSIZE"  ,           0x11F000000B020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45428         {"NPEI_PKT3_INSTR_FIFO_RSIZE"  ,           0x11F000000B030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45429         {"NPEI_PKT4_INSTR_FIFO_RSIZE"  ,           0x11F000000B040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45430         {"NPEI_PKT5_INSTR_FIFO_RSIZE"  ,           0x11F000000B050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45431         {"NPEI_PKT6_INSTR_FIFO_RSIZE"  ,           0x11F000000B060ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45432         {"NPEI_PKT7_INSTR_FIFO_RSIZE"  ,           0x11F000000B070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45433         {"NPEI_PKT8_INSTR_FIFO_RSIZE"  ,           0x11F000000B080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45434         {"NPEI_PKT9_INSTR_FIFO_RSIZE"  ,           0x11F000000B090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45435         {"NPEI_PKT10_INSTR_FIFO_RSIZE" ,           0x11F000000B0A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45436         {"NPEI_PKT11_INSTR_FIFO_RSIZE" ,           0x11F000000B0B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45437         {"NPEI_PKT12_INSTR_FIFO_RSIZE" ,           0x11F000000B0C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45438         {"NPEI_PKT13_INSTR_FIFO_RSIZE" ,           0x11F000000B0D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45439         {"NPEI_PKT14_INSTR_FIFO_RSIZE" ,           0x11F000000B0E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45440         {"NPEI_PKT15_INSTR_FIFO_RSIZE" ,           0x11F000000B0F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45441         {"NPEI_PKT16_INSTR_FIFO_RSIZE" ,           0x11F000000B100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45442         {"NPEI_PKT17_INSTR_FIFO_RSIZE" ,           0x11F000000B110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45443         {"NPEI_PKT18_INSTR_FIFO_RSIZE" ,           0x11F000000B120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45444         {"NPEI_PKT19_INSTR_FIFO_RSIZE" ,           0x11F000000B130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45445         {"NPEI_PKT20_INSTR_FIFO_RSIZE" ,           0x11F000000B140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45446         {"NPEI_PKT21_INSTR_FIFO_RSIZE" ,           0x11F000000B150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45447         {"NPEI_PKT22_INSTR_FIFO_RSIZE" ,           0x11F000000B160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45448         {"NPEI_PKT23_INSTR_FIFO_RSIZE" ,           0x11F000000B170ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45449         {"NPEI_PKT24_INSTR_FIFO_RSIZE" ,           0x11F000000B180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45450         {"NPEI_PKT25_INSTR_FIFO_RSIZE" ,           0x11F000000B190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45451         {"NPEI_PKT26_INSTR_FIFO_RSIZE" ,           0x11F000000B1A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45452         {"NPEI_PKT27_INSTR_FIFO_RSIZE" ,           0x11F000000B1B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45453         {"NPEI_PKT28_INSTR_FIFO_RSIZE" ,           0x11F000000B1C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45454         {"NPEI_PKT29_INSTR_FIFO_RSIZE" ,           0x11F000000B1D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45455         {"NPEI_PKT30_INSTR_FIFO_RSIZE" ,           0x11F000000B1E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45456         {"NPEI_PKT31_INSTR_FIFO_RSIZE" ,           0x11F000000B1F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
45457         {"NPEI_PKT0_INSTR_HEADER"      ,           0x11F000000B400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45458         {"NPEI_PKT1_INSTR_HEADER"      ,           0x11F000000B410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45459         {"NPEI_PKT2_INSTR_HEADER"      ,           0x11F000000B420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45460         {"NPEI_PKT3_INSTR_HEADER"      ,           0x11F000000B430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45461         {"NPEI_PKT4_INSTR_HEADER"      ,           0x11F000000B440ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45462         {"NPEI_PKT5_INSTR_HEADER"      ,           0x11F000000B450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45463         {"NPEI_PKT6_INSTR_HEADER"      ,           0x11F000000B460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45464         {"NPEI_PKT7_INSTR_HEADER"      ,           0x11F000000B470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45465         {"NPEI_PKT8_INSTR_HEADER"      ,           0x11F000000B480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45466         {"NPEI_PKT9_INSTR_HEADER"      ,           0x11F000000B490ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45467         {"NPEI_PKT10_INSTR_HEADER"     ,           0x11F000000B4A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45468         {"NPEI_PKT11_INSTR_HEADER"     ,           0x11F000000B4B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45469         {"NPEI_PKT12_INSTR_HEADER"     ,           0x11F000000B4C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45470         {"NPEI_PKT13_INSTR_HEADER"     ,           0x11F000000B4D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45471         {"NPEI_PKT14_INSTR_HEADER"     ,           0x11F000000B4E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45472         {"NPEI_PKT15_INSTR_HEADER"     ,           0x11F000000B4F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45473         {"NPEI_PKT16_INSTR_HEADER"     ,           0x11F000000B500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45474         {"NPEI_PKT17_INSTR_HEADER"     ,           0x11F000000B510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45475         {"NPEI_PKT18_INSTR_HEADER"     ,           0x11F000000B520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45476         {"NPEI_PKT19_INSTR_HEADER"     ,           0x11F000000B530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45477         {"NPEI_PKT20_INSTR_HEADER"     ,           0x11F000000B540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45478         {"NPEI_PKT21_INSTR_HEADER"     ,           0x11F000000B550ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45479         {"NPEI_PKT22_INSTR_HEADER"     ,           0x11F000000B560ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45480         {"NPEI_PKT23_INSTR_HEADER"     ,           0x11F000000B570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45481         {"NPEI_PKT24_INSTR_HEADER"     ,           0x11F000000B580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45482         {"NPEI_PKT25_INSTR_HEADER"     ,           0x11F000000B590ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45483         {"NPEI_PKT26_INSTR_HEADER"     ,           0x11F000000B5A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45484         {"NPEI_PKT27_INSTR_HEADER"     ,           0x11F000000B5B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45485         {"NPEI_PKT28_INSTR_HEADER"     ,           0x11F000000B5C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45486         {"NPEI_PKT29_INSTR_HEADER"     ,           0x11F000000B5D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45487         {"NPEI_PKT30_INSTR_HEADER"     ,           0x11F000000B5E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45488         {"NPEI_PKT31_INSTR_HEADER"     ,           0x11F000000B5F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
45489         {"NPEI_PKT0_SLIST_BADDR"       ,           0x11F0000009400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45490         {"NPEI_PKT1_SLIST_BADDR"       ,           0x11F0000009410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45491         {"NPEI_PKT2_SLIST_BADDR"       ,           0x11F0000009420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45492         {"NPEI_PKT3_SLIST_BADDR"       ,           0x11F0000009430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45493         {"NPEI_PKT4_SLIST_BADDR"       ,           0x11F0000009440ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45494         {"NPEI_PKT5_SLIST_BADDR"       ,           0x11F0000009450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45495         {"NPEI_PKT6_SLIST_BADDR"       ,           0x11F0000009460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45496         {"NPEI_PKT7_SLIST_BADDR"       ,           0x11F0000009470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45497         {"NPEI_PKT8_SLIST_BADDR"       ,           0x11F0000009480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45498         {"NPEI_PKT9_SLIST_BADDR"       ,           0x11F0000009490ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45499         {"NPEI_PKT10_SLIST_BADDR"      ,           0x11F00000094A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45500         {"NPEI_PKT11_SLIST_BADDR"      ,           0x11F00000094B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45501         {"NPEI_PKT12_SLIST_BADDR"      ,           0x11F00000094C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45502         {"NPEI_PKT13_SLIST_BADDR"      ,           0x11F00000094D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45503         {"NPEI_PKT14_SLIST_BADDR"      ,           0x11F00000094E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45504         {"NPEI_PKT15_SLIST_BADDR"      ,           0x11F00000094F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45505         {"NPEI_PKT16_SLIST_BADDR"      ,           0x11F0000009500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45506         {"NPEI_PKT17_SLIST_BADDR"      ,           0x11F0000009510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45507         {"NPEI_PKT18_SLIST_BADDR"      ,           0x11F0000009520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45508         {"NPEI_PKT19_SLIST_BADDR"      ,           0x11F0000009530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45509         {"NPEI_PKT20_SLIST_BADDR"      ,           0x11F0000009540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45510         {"NPEI_PKT21_SLIST_BADDR"      ,           0x11F0000009550ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45511         {"NPEI_PKT22_SLIST_BADDR"      ,           0x11F0000009560ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45512         {"NPEI_PKT23_SLIST_BADDR"      ,           0x11F0000009570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45513         {"NPEI_PKT24_SLIST_BADDR"      ,           0x11F0000009580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45514         {"NPEI_PKT25_SLIST_BADDR"      ,           0x11F0000009590ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45515         {"NPEI_PKT26_SLIST_BADDR"      ,           0x11F00000095A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45516         {"NPEI_PKT27_SLIST_BADDR"      ,           0x11F00000095B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45517         {"NPEI_PKT28_SLIST_BADDR"      ,           0x11F00000095C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45518         {"NPEI_PKT29_SLIST_BADDR"      ,           0x11F00000095D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45519         {"NPEI_PKT30_SLIST_BADDR"      ,           0x11F00000095E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45520         {"NPEI_PKT31_SLIST_BADDR"      ,           0x11F00000095F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
45521         {"NPEI_PKT0_SLIST_BAOFF_DBELL" ,           0x11F0000009800ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45522         {"NPEI_PKT1_SLIST_BAOFF_DBELL" ,           0x11F0000009810ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45523         {"NPEI_PKT2_SLIST_BAOFF_DBELL" ,           0x11F0000009820ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45524         {"NPEI_PKT3_SLIST_BAOFF_DBELL" ,           0x11F0000009830ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45525         {"NPEI_PKT4_SLIST_BAOFF_DBELL" ,           0x11F0000009840ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45526         {"NPEI_PKT5_SLIST_BAOFF_DBELL" ,           0x11F0000009850ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45527         {"NPEI_PKT6_SLIST_BAOFF_DBELL" ,           0x11F0000009860ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45528         {"NPEI_PKT7_SLIST_BAOFF_DBELL" ,           0x11F0000009870ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45529         {"NPEI_PKT8_SLIST_BAOFF_DBELL" ,           0x11F0000009880ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45530         {"NPEI_PKT9_SLIST_BAOFF_DBELL" ,           0x11F0000009890ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45531         {"NPEI_PKT10_SLIST_BAOFF_DBELL",           0x11F00000098A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45532         {"NPEI_PKT11_SLIST_BAOFF_DBELL",           0x11F00000098B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45533         {"NPEI_PKT12_SLIST_BAOFF_DBELL",           0x11F00000098C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45534         {"NPEI_PKT13_SLIST_BAOFF_DBELL",           0x11F00000098D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45535         {"NPEI_PKT14_SLIST_BAOFF_DBELL",           0x11F00000098E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45536         {"NPEI_PKT15_SLIST_BAOFF_DBELL",           0x11F00000098F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45537         {"NPEI_PKT16_SLIST_BAOFF_DBELL",           0x11F0000009900ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45538         {"NPEI_PKT17_SLIST_BAOFF_DBELL",           0x11F0000009910ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45539         {"NPEI_PKT18_SLIST_BAOFF_DBELL",           0x11F0000009920ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45540         {"NPEI_PKT19_SLIST_BAOFF_DBELL",           0x11F0000009930ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45541         {"NPEI_PKT20_SLIST_BAOFF_DBELL",           0x11F0000009940ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45542         {"NPEI_PKT21_SLIST_BAOFF_DBELL",           0x11F0000009950ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45543         {"NPEI_PKT22_SLIST_BAOFF_DBELL",           0x11F0000009960ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45544         {"NPEI_PKT23_SLIST_BAOFF_DBELL",           0x11F0000009970ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45545         {"NPEI_PKT24_SLIST_BAOFF_DBELL",           0x11F0000009980ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45546         {"NPEI_PKT25_SLIST_BAOFF_DBELL",           0x11F0000009990ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45547         {"NPEI_PKT26_SLIST_BAOFF_DBELL",           0x11F00000099A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45548         {"NPEI_PKT27_SLIST_BAOFF_DBELL",           0x11F00000099B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45549         {"NPEI_PKT28_SLIST_BAOFF_DBELL",           0x11F00000099C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45550         {"NPEI_PKT29_SLIST_BAOFF_DBELL",           0x11F00000099D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45551         {"NPEI_PKT30_SLIST_BAOFF_DBELL",           0x11F00000099E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45552         {"NPEI_PKT31_SLIST_BAOFF_DBELL",           0x11F00000099F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
45553         {"NPEI_PKT0_SLIST_FIFO_RSIZE"  ,           0x11F0000009C00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45554         {"NPEI_PKT1_SLIST_FIFO_RSIZE"  ,           0x11F0000009C10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45555         {"NPEI_PKT2_SLIST_FIFO_RSIZE"  ,           0x11F0000009C20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45556         {"NPEI_PKT3_SLIST_FIFO_RSIZE"  ,           0x11F0000009C30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45557         {"NPEI_PKT4_SLIST_FIFO_RSIZE"  ,           0x11F0000009C40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45558         {"NPEI_PKT5_SLIST_FIFO_RSIZE"  ,           0x11F0000009C50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45559         {"NPEI_PKT6_SLIST_FIFO_RSIZE"  ,           0x11F0000009C60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45560         {"NPEI_PKT7_SLIST_FIFO_RSIZE"  ,           0x11F0000009C70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45561         {"NPEI_PKT8_SLIST_FIFO_RSIZE"  ,           0x11F0000009C80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45562         {"NPEI_PKT9_SLIST_FIFO_RSIZE"  ,           0x11F0000009C90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45563         {"NPEI_PKT10_SLIST_FIFO_RSIZE" ,           0x11F0000009CA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45564         {"NPEI_PKT11_SLIST_FIFO_RSIZE" ,           0x11F0000009CB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45565         {"NPEI_PKT12_SLIST_FIFO_RSIZE" ,           0x11F0000009CC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45566         {"NPEI_PKT13_SLIST_FIFO_RSIZE" ,           0x11F0000009CD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45567         {"NPEI_PKT14_SLIST_FIFO_RSIZE" ,           0x11F0000009CE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45568         {"NPEI_PKT15_SLIST_FIFO_RSIZE" ,           0x11F0000009CF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45569         {"NPEI_PKT16_SLIST_FIFO_RSIZE" ,           0x11F0000009D00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45570         {"NPEI_PKT17_SLIST_FIFO_RSIZE" ,           0x11F0000009D10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45571         {"NPEI_PKT18_SLIST_FIFO_RSIZE" ,           0x11F0000009D20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45572         {"NPEI_PKT19_SLIST_FIFO_RSIZE" ,           0x11F0000009D30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45573         {"NPEI_PKT20_SLIST_FIFO_RSIZE" ,           0x11F0000009D40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45574         {"NPEI_PKT21_SLIST_FIFO_RSIZE" ,           0x11F0000009D50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45575         {"NPEI_PKT22_SLIST_FIFO_RSIZE" ,           0x11F0000009D60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45576         {"NPEI_PKT23_SLIST_FIFO_RSIZE" ,           0x11F0000009D70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45577         {"NPEI_PKT24_SLIST_FIFO_RSIZE" ,           0x11F0000009D80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45578         {"NPEI_PKT25_SLIST_FIFO_RSIZE" ,           0x11F0000009D90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45579         {"NPEI_PKT26_SLIST_FIFO_RSIZE" ,           0x11F0000009DA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45580         {"NPEI_PKT27_SLIST_FIFO_RSIZE" ,           0x11F0000009DB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45581         {"NPEI_PKT28_SLIST_FIFO_RSIZE" ,           0x11F0000009DC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45582         {"NPEI_PKT29_SLIST_FIFO_RSIZE" ,           0x11F0000009DD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45583         {"NPEI_PKT30_SLIST_FIFO_RSIZE" ,           0x11F0000009DE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45584         {"NPEI_PKT31_SLIST_FIFO_RSIZE" ,           0x11F0000009DF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
45585         {"NPEI_PKT_CNT_INT"            ,           0x11F0000009110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     488},
45586         {"NPEI_PKT_CNT_INT_ENB"        ,           0x11F0000009130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     489},
45587         {"NPEI_PKT_DATA_OUT_ES"        ,           0x11F00000090B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     490},
45588         {"NPEI_PKT_DATA_OUT_NS"        ,           0x11F00000090A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     491},
45589         {"NPEI_PKT_DATA_OUT_ROR"       ,           0x11F0000009090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     492},
45590         {"NPEI_PKT_DPADDR"             ,           0x11F0000009080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     493},
45591         {"NPEI_PKT_IN_BP"              ,           0x11F00000086B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
45592         {"NPEI_PKT_IN_DONE0_CNTS"      ,           0x11F000000A000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45593         {"NPEI_PKT_IN_DONE1_CNTS"      ,           0x11F000000A010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45594         {"NPEI_PKT_IN_DONE2_CNTS"      ,           0x11F000000A020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45595         {"NPEI_PKT_IN_DONE3_CNTS"      ,           0x11F000000A030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45596         {"NPEI_PKT_IN_DONE4_CNTS"      ,           0x11F000000A040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45597         {"NPEI_PKT_IN_DONE5_CNTS"      ,           0x11F000000A050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45598         {"NPEI_PKT_IN_DONE6_CNTS"      ,           0x11F000000A060ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45599         {"NPEI_PKT_IN_DONE7_CNTS"      ,           0x11F000000A070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45600         {"NPEI_PKT_IN_DONE8_CNTS"      ,           0x11F000000A080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45601         {"NPEI_PKT_IN_DONE9_CNTS"      ,           0x11F000000A090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45602         {"NPEI_PKT_IN_DONE10_CNTS"     ,           0x11F000000A0A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45603         {"NPEI_PKT_IN_DONE11_CNTS"     ,           0x11F000000A0B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45604         {"NPEI_PKT_IN_DONE12_CNTS"     ,           0x11F000000A0C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45605         {"NPEI_PKT_IN_DONE13_CNTS"     ,           0x11F000000A0D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45606         {"NPEI_PKT_IN_DONE14_CNTS"     ,           0x11F000000A0E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45607         {"NPEI_PKT_IN_DONE15_CNTS"     ,           0x11F000000A0F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45608         {"NPEI_PKT_IN_DONE16_CNTS"     ,           0x11F000000A100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45609         {"NPEI_PKT_IN_DONE17_CNTS"     ,           0x11F000000A110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45610         {"NPEI_PKT_IN_DONE18_CNTS"     ,           0x11F000000A120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45611         {"NPEI_PKT_IN_DONE19_CNTS"     ,           0x11F000000A130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45612         {"NPEI_PKT_IN_DONE20_CNTS"     ,           0x11F000000A140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45613         {"NPEI_PKT_IN_DONE21_CNTS"     ,           0x11F000000A150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45614         {"NPEI_PKT_IN_DONE22_CNTS"     ,           0x11F000000A160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45615         {"NPEI_PKT_IN_DONE23_CNTS"     ,           0x11F000000A170ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45616         {"NPEI_PKT_IN_DONE24_CNTS"     ,           0x11F000000A180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45617         {"NPEI_PKT_IN_DONE25_CNTS"     ,           0x11F000000A190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45618         {"NPEI_PKT_IN_DONE26_CNTS"     ,           0x11F000000A1A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45619         {"NPEI_PKT_IN_DONE27_CNTS"     ,           0x11F000000A1B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45620         {"NPEI_PKT_IN_DONE28_CNTS"     ,           0x11F000000A1C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45621         {"NPEI_PKT_IN_DONE29_CNTS"     ,           0x11F000000A1D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45622         {"NPEI_PKT_IN_DONE30_CNTS"     ,           0x11F000000A1E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45623         {"NPEI_PKT_IN_DONE31_CNTS"     ,           0x11F000000A1F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
45624         {"NPEI_PKT_IN_INSTR_COUNTS"    ,           0x11F00000086A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
45625         {"NPEI_PKT_IN_PCIE_PORT"       ,           0x11F00000091A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
45626         {"NPEI_PKT_INPUT_CONTROL"      ,           0x11F0000009150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
45627         {"NPEI_PKT_INSTR_ENB"          ,           0x11F0000009000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
45628         {"NPEI_PKT_INSTR_RD_SIZE"      ,           0x11F0000009190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
45629         {"NPEI_PKT_INSTR_SIZE"         ,           0x11F0000009020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
45630         {"NPEI_PKT_INT_LEVELS"         ,           0x11F0000009100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
45631         {"NPEI_PKT_IPTR"               ,           0x11F0000009070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     503},
45632         {"NPEI_PKT_OUT_BMODE"          ,           0x11F00000090D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     504},
45633         {"NPEI_PKT_OUT_ENB"            ,           0x11F0000009010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     505},
45634         {"NPEI_PKT_OUTPUT_WMARK"       ,           0x11F0000009160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     506},
45635         {"NPEI_PKT_PCIE_PORT"          ,           0x11F00000090E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     507},
45636         {"NPEI_PKT_PORT_IN_RST"        ,           0x11F0000008690ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     508},
45637         {"NPEI_PKT_SLIST_ES"           ,           0x11F0000009050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     509},
45638         {"NPEI_PKT_SLIST_ID_SIZE"      ,           0x11F0000009180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
45639         {"NPEI_PKT_SLIST_NS"           ,           0x11F0000009040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     511},
45640         {"NPEI_PKT_SLIST_ROR"          ,           0x11F0000009030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     512},
45641         {"NPEI_PKT_TIME_INT"           ,           0x11F0000009120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     513},
45642         {"NPEI_PKT_TIME_INT_ENB"       ,           0x11F0000009140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     514},
45643         {"NPEI_RSL_INT_BLOCKS"         ,           0x11F0000008520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     515},
45644         {"NPEI_SCRATCH_1"              ,           0x11F0000008270ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     516},
45645         {"NPEI_STATE1"                 ,           0x11F0000008620ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     517},
45646         {"NPEI_STATE2"                 ,           0x11F0000008630ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     518},
45647         {"NPEI_STATE3"                 ,           0x11F0000008640ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     519},
45648         {"NPEI_WIN_RD_ADDR"            ,                     0x210ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     520},
45649         {"NPEI_WIN_RD_DATA"            ,                     0x240ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     521},
45650         {"NPEI_WIN_WR_ADDR"            ,                     0x200ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     522},
45651         {"NPEI_WIN_WR_DATA"            ,                     0x220ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     523},
45652         {"NPEI_WIN_WR_MASK"            ,                     0x230ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     524},
45653         {"NPEI_WINDOW_CTL"             ,           0x11F0000008380ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     525},
45654         {"PCIEEP_CFG000"               ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     526},
45655         {"PCIEEP_CFG001"               ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     527},
45656         {"PCIEEP_CFG002"               ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     528},
45657         {"PCIEEP_CFG003"               ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     529},
45658         {"PCIEEP_CFG004"               ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     530},
45659         {"PCIEEP_CFG004_MASK"          ,                0x80000010ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     531},
45660         {"PCIEEP_CFG005"               ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     532},
45661         {"PCIEEP_CFG005_MASK"          ,                0x80000014ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     533},
45662         {"PCIEEP_CFG006"               ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     534},
45663         {"PCIEEP_CFG006_MASK"          ,                0x80000018ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     535},
45664         {"PCIEEP_CFG007"               ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     536},
45665         {"PCIEEP_CFG007_MASK"          ,                0x8000001Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     537},
45666         {"PCIEEP_CFG008"               ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     538},
45667         {"PCIEEP_CFG008_MASK"          ,                0x80000020ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     539},
45668         {"PCIEEP_CFG009"               ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     540},
45669         {"PCIEEP_CFG009_MASK"          ,                0x80000024ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     541},
45670         {"PCIEEP_CFG010"               ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     542},
45671         {"PCIEEP_CFG011"               ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     543},
45672         {"PCIEEP_CFG012"               ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     544},
45673         {"PCIEEP_CFG012_MASK"          ,                0x80000030ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     545},
45674         {"PCIEEP_CFG013"               ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     546},
45675         {"PCIEEP_CFG015"               ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     547},
45676         {"PCIEEP_CFG016"               ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     548},
45677         {"PCIEEP_CFG017"               ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     549},
45678         {"PCIEEP_CFG020"               ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     550},
45679         {"PCIEEP_CFG021"               ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     551},
45680         {"PCIEEP_CFG022"               ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     552},
45681         {"PCIEEP_CFG023"               ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     553},
45682         {"PCIEEP_CFG028"               ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     554},
45683         {"PCIEEP_CFG029"               ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     555},
45684         {"PCIEEP_CFG030"               ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     556},
45685         {"PCIEEP_CFG031"               ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     557},
45686         {"PCIEEP_CFG032"               ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     558},
45687         {"PCIEEP_CFG033"               ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     559},
45688         {"PCIEEP_CFG034"               ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     560},
45689         {"PCIEEP_CFG037"               ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     561},
45690         {"PCIEEP_CFG038"               ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     562},
45691         {"PCIEEP_CFG039"               ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     563},
45692         {"PCIEEP_CFG040"               ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     564},
45693         {"PCIEEP_CFG041"               ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     565},
45694         {"PCIEEP_CFG042"               ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     566},
45695         {"PCIEEP_CFG064"               ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     567},
45696         {"PCIEEP_CFG065"               ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     568},
45697         {"PCIEEP_CFG066"               ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     569},
45698         {"PCIEEP_CFG067"               ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     570},
45699         {"PCIEEP_CFG068"               ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     571},
45700         {"PCIEEP_CFG069"               ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     572},
45701         {"PCIEEP_CFG070"               ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     573},
45702         {"PCIEEP_CFG071"               ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     574},
45703         {"PCIEEP_CFG072"               ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     575},
45704         {"PCIEEP_CFG073"               ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     576},
45705         {"PCIEEP_CFG074"               ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     577},
45706         {"PCIEEP_CFG448"               ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     578},
45707         {"PCIEEP_CFG449"               ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     579},
45708         {"PCIEEP_CFG450"               ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     580},
45709         {"PCIEEP_CFG451"               ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     581},
45710         {"PCIEEP_CFG452"               ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     582},
45711         {"PCIEEP_CFG453"               ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     583},
45712         {"PCIEEP_CFG454"               ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     584},
45713         {"PCIEEP_CFG455"               ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     585},
45714         {"PCIEEP_CFG456"               ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     586},
45715         {"PCIEEP_CFG458"               ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     587},
45716         {"PCIEEP_CFG459"               ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     588},
45717         {"PCIEEP_CFG460"               ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     589},
45718         {"PCIEEP_CFG461"               ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     590},
45719         {"PCIEEP_CFG462"               ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     591},
45720         {"PCIEEP_CFG463"               ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     592},
45721         {"PCIEEP_CFG464"               ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     593},
45722         {"PCIEEP_CFG465"               ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     594},
45723         {"PCIEEP_CFG466"               ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     595},
45724         {"PCIEEP_CFG467"               ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     596},
45725         {"PCIEEP_CFG468"               ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     597},
45726         {"PCIEEP_CFG490"               ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     598},
45727         {"PCIEEP_CFG491"               ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     599},
45728         {"PCIEEP_CFG492"               ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     600},
45729         {"PCIEEP_CFG516"               ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     601},
45730         {"PCIEEP_CFG517"               ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     602},
45731         {"PCIERC0_CFG000"              ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     603},
45732         {"PCIERC1_CFG000"              ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     603},
45733         {"PCIERC0_CFG001"              ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     604},
45734         {"PCIERC1_CFG001"              ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     604},
45735         {"PCIERC0_CFG002"              ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     605},
45736         {"PCIERC1_CFG002"              ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     605},
45737         {"PCIERC0_CFG003"              ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     606},
45738         {"PCIERC1_CFG003"              ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     606},
45739         {"PCIERC0_CFG004"              ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     607},
45740         {"PCIERC1_CFG004"              ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     607},
45741         {"PCIERC0_CFG005"              ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     608},
45742         {"PCIERC1_CFG005"              ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     608},
45743         {"PCIERC0_CFG006"              ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     609},
45744         {"PCIERC1_CFG006"              ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     609},
45745         {"PCIERC0_CFG007"              ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     610},
45746         {"PCIERC1_CFG007"              ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     610},
45747         {"PCIERC0_CFG008"              ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     611},
45748         {"PCIERC1_CFG008"              ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     611},
45749         {"PCIERC0_CFG009"              ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     612},
45750         {"PCIERC1_CFG009"              ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     612},
45751         {"PCIERC0_CFG010"              ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     613},
45752         {"PCIERC1_CFG010"              ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     613},
45753         {"PCIERC0_CFG011"              ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     614},
45754         {"PCIERC1_CFG011"              ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     614},
45755         {"PCIERC0_CFG012"              ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     615},
45756         {"PCIERC1_CFG012"              ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     615},
45757         {"PCIERC0_CFG013"              ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     616},
45758         {"PCIERC1_CFG013"              ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     616},
45759         {"PCIERC0_CFG014"              ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     617},
45760         {"PCIERC1_CFG014"              ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     617},
45761         {"PCIERC0_CFG015"              ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     618},
45762         {"PCIERC1_CFG015"              ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     618},
45763         {"PCIERC0_CFG016"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     619},
45764         {"PCIERC1_CFG016"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     619},
45765         {"PCIERC0_CFG017"              ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     620},
45766         {"PCIERC1_CFG017"              ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     620},
45767         {"PCIERC0_CFG020"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     621},
45768         {"PCIERC1_CFG020"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     621},
45769         {"PCIERC0_CFG021"              ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     622},
45770         {"PCIERC1_CFG021"              ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     622},
45771         {"PCIERC0_CFG022"              ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     623},
45772         {"PCIERC1_CFG022"              ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     623},
45773         {"PCIERC0_CFG023"              ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     624},
45774         {"PCIERC1_CFG023"              ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     624},
45775         {"PCIERC0_CFG028"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     625},
45776         {"PCIERC1_CFG028"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     625},
45777         {"PCIERC0_CFG029"              ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     626},
45778         {"PCIERC1_CFG029"              ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     626},
45779         {"PCIERC0_CFG030"              ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     627},
45780         {"PCIERC1_CFG030"              ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     627},
45781         {"PCIERC0_CFG031"              ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     628},
45782         {"PCIERC1_CFG031"              ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     628},
45783         {"PCIERC0_CFG032"              ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     629},
45784         {"PCIERC1_CFG032"              ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     629},
45785         {"PCIERC0_CFG033"              ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     630},
45786         {"PCIERC1_CFG033"              ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     630},
45787         {"PCIERC0_CFG034"              ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     631},
45788         {"PCIERC1_CFG034"              ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     631},
45789         {"PCIERC0_CFG035"              ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     632},
45790         {"PCIERC1_CFG035"              ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     632},
45791         {"PCIERC0_CFG036"              ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     633},
45792         {"PCIERC1_CFG036"              ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     633},
45793         {"PCIERC0_CFG037"              ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     634},
45794         {"PCIERC1_CFG037"              ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     634},
45795         {"PCIERC0_CFG038"              ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     635},
45796         {"PCIERC1_CFG038"              ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     635},
45797         {"PCIERC0_CFG039"              ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     636},
45798         {"PCIERC1_CFG039"              ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     636},
45799         {"PCIERC0_CFG040"              ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     637},
45800         {"PCIERC1_CFG040"              ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     637},
45801         {"PCIERC0_CFG041"              ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     638},
45802         {"PCIERC1_CFG041"              ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     638},
45803         {"PCIERC0_CFG042"              ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     639},
45804         {"PCIERC1_CFG042"              ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     639},
45805         {"PCIERC0_CFG064"              ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     640},
45806         {"PCIERC1_CFG064"              ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     640},
45807         {"PCIERC0_CFG065"              ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     641},
45808         {"PCIERC1_CFG065"              ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     641},
45809         {"PCIERC0_CFG066"              ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     642},
45810         {"PCIERC1_CFG066"              ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     642},
45811         {"PCIERC0_CFG067"              ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     643},
45812         {"PCIERC1_CFG067"              ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     643},
45813         {"PCIERC0_CFG068"              ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     644},
45814         {"PCIERC1_CFG068"              ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     644},
45815         {"PCIERC0_CFG069"              ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     645},
45816         {"PCIERC1_CFG069"              ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     645},
45817         {"PCIERC0_CFG070"              ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     646},
45818         {"PCIERC1_CFG070"              ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     646},
45819         {"PCIERC0_CFG071"              ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     647},
45820         {"PCIERC1_CFG071"              ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     647},
45821         {"PCIERC0_CFG072"              ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     648},
45822         {"PCIERC1_CFG072"              ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     648},
45823         {"PCIERC0_CFG073"              ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     649},
45824         {"PCIERC1_CFG073"              ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     649},
45825         {"PCIERC0_CFG074"              ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     650},
45826         {"PCIERC1_CFG074"              ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     650},
45827         {"PCIERC0_CFG075"              ,                     0x12Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     651},
45828         {"PCIERC1_CFG075"              ,                     0x12Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     651},
45829         {"PCIERC0_CFG076"              ,                     0x130ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     652},
45830         {"PCIERC1_CFG076"              ,                     0x130ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     652},
45831         {"PCIERC0_CFG077"              ,                     0x134ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     653},
45832         {"PCIERC1_CFG077"              ,                     0x134ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     653},
45833         {"PCIERC0_CFG448"              ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     654},
45834         {"PCIERC1_CFG448"              ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     654},
45835         {"PCIERC0_CFG449"              ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     655},
45836         {"PCIERC1_CFG449"              ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     655},
45837         {"PCIERC0_CFG450"              ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     656},
45838         {"PCIERC1_CFG450"              ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     656},
45839         {"PCIERC0_CFG451"              ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     657},
45840         {"PCIERC1_CFG451"              ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     657},
45841         {"PCIERC0_CFG452"              ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     658},
45842         {"PCIERC1_CFG452"              ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     658},
45843         {"PCIERC0_CFG453"              ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     659},
45844         {"PCIERC1_CFG453"              ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     659},
45845         {"PCIERC0_CFG454"              ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     660},
45846         {"PCIERC1_CFG454"              ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     660},
45847         {"PCIERC0_CFG455"              ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     661},
45848         {"PCIERC1_CFG455"              ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     661},
45849         {"PCIERC0_CFG456"              ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     662},
45850         {"PCIERC1_CFG456"              ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     662},
45851         {"PCIERC0_CFG458"              ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     663},
45852         {"PCIERC1_CFG458"              ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     663},
45853         {"PCIERC0_CFG459"              ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     664},
45854         {"PCIERC1_CFG459"              ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     664},
45855         {"PCIERC0_CFG460"              ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     665},
45856         {"PCIERC1_CFG460"              ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     665},
45857         {"PCIERC0_CFG461"              ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     666},
45858         {"PCIERC1_CFG461"              ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     666},
45859         {"PCIERC0_CFG462"              ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     667},
45860         {"PCIERC1_CFG462"              ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     667},
45861         {"PCIERC0_CFG463"              ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     668},
45862         {"PCIERC1_CFG463"              ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     668},
45863         {"PCIERC0_CFG464"              ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     669},
45864         {"PCIERC1_CFG464"              ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     669},
45865         {"PCIERC0_CFG465"              ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     670},
45866         {"PCIERC1_CFG465"              ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     670},
45867         {"PCIERC0_CFG466"              ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     671},
45868         {"PCIERC1_CFG466"              ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     671},
45869         {"PCIERC0_CFG467"              ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     672},
45870         {"PCIERC1_CFG467"              ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     672},
45871         {"PCIERC0_CFG468"              ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     673},
45872         {"PCIERC1_CFG468"              ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     673},
45873         {"PCIERC0_CFG490"              ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     674},
45874         {"PCIERC1_CFG490"              ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     674},
45875         {"PCIERC0_CFG491"              ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     675},
45876         {"PCIERC1_CFG491"              ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     675},
45877         {"PCIERC0_CFG492"              ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     676},
45878         {"PCIERC1_CFG492"              ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     676},
45879         {"PCIERC0_CFG516"              ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     677},
45880         {"PCIERC1_CFG516"              ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     677},
45881         {"PCIERC0_CFG517"              ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     678},
45882         {"PCIERC1_CFG517"              ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     678},
45883         {"PCS0_AN000_ADV_REG"          ,           0x11800B0001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
45884         {"PCS0_AN001_ADV_REG"          ,           0x11800B0001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
45885         {"PCS0_AN002_ADV_REG"          ,           0x11800B0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
45886         {"PCS0_AN003_ADV_REG"          ,           0x11800B0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
45887         {"PCS1_AN000_ADV_REG"          ,           0x11800B8001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
45888         {"PCS1_AN001_ADV_REG"          ,           0x11800B8001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
45889         {"PCS1_AN002_ADV_REG"          ,           0x11800B8001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
45890         {"PCS1_AN003_ADV_REG"          ,           0x11800B8001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
45891         {"PCS0_AN000_EXT_ST_REG"       ,           0x11800B0001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
45892         {"PCS0_AN001_EXT_ST_REG"       ,           0x11800B0001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
45893         {"PCS0_AN002_EXT_ST_REG"       ,           0x11800B0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
45894         {"PCS0_AN003_EXT_ST_REG"       ,           0x11800B0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
45895         {"PCS1_AN000_EXT_ST_REG"       ,           0x11800B8001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
45896         {"PCS1_AN001_EXT_ST_REG"       ,           0x11800B8001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
45897         {"PCS1_AN002_EXT_ST_REG"       ,           0x11800B8001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
45898         {"PCS1_AN003_EXT_ST_REG"       ,           0x11800B8001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
45899         {"PCS0_AN000_LP_ABIL_REG"      ,           0x11800B0001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
45900         {"PCS0_AN001_LP_ABIL_REG"      ,           0x11800B0001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
45901         {"PCS0_AN002_LP_ABIL_REG"      ,           0x11800B0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
45902         {"PCS0_AN003_LP_ABIL_REG"      ,           0x11800B0001C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
45903         {"PCS1_AN000_LP_ABIL_REG"      ,           0x11800B8001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
45904         {"PCS1_AN001_LP_ABIL_REG"      ,           0x11800B8001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
45905         {"PCS1_AN002_LP_ABIL_REG"      ,           0x11800B8001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
45906         {"PCS1_AN003_LP_ABIL_REG"      ,           0x11800B8001C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
45907         {"PCS0_AN000_RESULTS_REG"      ,           0x11800B0001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
45908         {"PCS0_AN001_RESULTS_REG"      ,           0x11800B0001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
45909         {"PCS0_AN002_RESULTS_REG"      ,           0x11800B0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
45910         {"PCS0_AN003_RESULTS_REG"      ,           0x11800B0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
45911         {"PCS1_AN000_RESULTS_REG"      ,           0x11800B8001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
45912         {"PCS1_AN001_RESULTS_REG"      ,           0x11800B8001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
45913         {"PCS1_AN002_RESULTS_REG"      ,           0x11800B8001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
45914         {"PCS1_AN003_RESULTS_REG"      ,           0x11800B8001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
45915         {"PCS0_INT000_EN_REG"          ,           0x11800B0001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
45916         {"PCS0_INT001_EN_REG"          ,           0x11800B0001488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
45917         {"PCS0_INT002_EN_REG"          ,           0x11800B0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
45918         {"PCS0_INT003_EN_REG"          ,           0x11800B0001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
45919         {"PCS1_INT000_EN_REG"          ,           0x11800B8001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
45920         {"PCS1_INT001_EN_REG"          ,           0x11800B8001488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
45921         {"PCS1_INT002_EN_REG"          ,           0x11800B8001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
45922         {"PCS1_INT003_EN_REG"          ,           0x11800B8001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
45923         {"PCS0_INT000_REG"             ,           0x11800B0001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
45924         {"PCS0_INT001_REG"             ,           0x11800B0001480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
45925         {"PCS0_INT002_REG"             ,           0x11800B0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
45926         {"PCS0_INT003_REG"             ,           0x11800B0001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
45927         {"PCS1_INT000_REG"             ,           0x11800B8001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
45928         {"PCS1_INT001_REG"             ,           0x11800B8001480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
45929         {"PCS1_INT002_REG"             ,           0x11800B8001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
45930         {"PCS1_INT003_REG"             ,           0x11800B8001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
45931         {"PCS0_LINK000_TIMER_COUNT_REG",           0x11800B0001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
45932         {"PCS0_LINK001_TIMER_COUNT_REG",           0x11800B0001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
45933         {"PCS0_LINK002_TIMER_COUNT_REG",           0x11800B0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
45934         {"PCS0_LINK003_TIMER_COUNT_REG",           0x11800B0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
45935         {"PCS1_LINK000_TIMER_COUNT_REG",           0x11800B8001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
45936         {"PCS1_LINK001_TIMER_COUNT_REG",           0x11800B8001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
45937         {"PCS1_LINK002_TIMER_COUNT_REG",           0x11800B8001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
45938         {"PCS1_LINK003_TIMER_COUNT_REG",           0x11800B8001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
45939         {"PCS0_LOG_ANL000_REG"         ,           0x11800B0001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
45940         {"PCS0_LOG_ANL001_REG"         ,           0x11800B0001490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
45941         {"PCS0_LOG_ANL002_REG"         ,           0x11800B0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
45942         {"PCS0_LOG_ANL003_REG"         ,           0x11800B0001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
45943         {"PCS1_LOG_ANL000_REG"         ,           0x11800B8001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
45944         {"PCS1_LOG_ANL001_REG"         ,           0x11800B8001490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
45945         {"PCS1_LOG_ANL002_REG"         ,           0x11800B8001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
45946         {"PCS1_LOG_ANL003_REG"         ,           0x11800B8001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
45947         {"PCS0_MISC000_CTL_REG"        ,           0x11800B0001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
45948         {"PCS0_MISC001_CTL_REG"        ,           0x11800B0001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
45949         {"PCS0_MISC002_CTL_REG"        ,           0x11800B0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
45950         {"PCS0_MISC003_CTL_REG"        ,           0x11800B0001C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
45951         {"PCS1_MISC000_CTL_REG"        ,           0x11800B8001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
45952         {"PCS1_MISC001_CTL_REG"        ,           0x11800B8001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
45953         {"PCS1_MISC002_CTL_REG"        ,           0x11800B8001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
45954         {"PCS1_MISC003_CTL_REG"        ,           0x11800B8001C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
45955         {"PCS0_MR000_CONTROL_REG"      ,           0x11800B0001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
45956         {"PCS0_MR001_CONTROL_REG"      ,           0x11800B0001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
45957         {"PCS0_MR002_CONTROL_REG"      ,           0x11800B0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
45958         {"PCS0_MR003_CONTROL_REG"      ,           0x11800B0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
45959         {"PCS1_MR000_CONTROL_REG"      ,           0x11800B8001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
45960         {"PCS1_MR001_CONTROL_REG"      ,           0x11800B8001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
45961         {"PCS1_MR002_CONTROL_REG"      ,           0x11800B8001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
45962         {"PCS1_MR003_CONTROL_REG"      ,           0x11800B8001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
45963         {"PCS0_MR000_STATUS_REG"       ,           0x11800B0001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
45964         {"PCS0_MR001_STATUS_REG"       ,           0x11800B0001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
45965         {"PCS0_MR002_STATUS_REG"       ,           0x11800B0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
45966         {"PCS0_MR003_STATUS_REG"       ,           0x11800B0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
45967         {"PCS1_MR000_STATUS_REG"       ,           0x11800B8001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
45968         {"PCS1_MR001_STATUS_REG"       ,           0x11800B8001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
45969         {"PCS1_MR002_STATUS_REG"       ,           0x11800B8001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
45970         {"PCS1_MR003_STATUS_REG"       ,           0x11800B8001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
45971         {"PCS0_RX000_STATES_REG"       ,           0x11800B0001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
45972         {"PCS0_RX001_STATES_REG"       ,           0x11800B0001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
45973         {"PCS0_RX002_STATES_REG"       ,           0x11800B0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
45974         {"PCS0_RX003_STATES_REG"       ,           0x11800B0001C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
45975         {"PCS1_RX000_STATES_REG"       ,           0x11800B8001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
45976         {"PCS1_RX001_STATES_REG"       ,           0x11800B8001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
45977         {"PCS1_RX002_STATES_REG"       ,           0x11800B8001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
45978         {"PCS1_RX003_STATES_REG"       ,           0x11800B8001C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
45979         {"PCS0_RX000_SYNC_REG"         ,           0x11800B0001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
45980         {"PCS0_RX001_SYNC_REG"         ,           0x11800B0001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
45981         {"PCS0_RX002_SYNC_REG"         ,           0x11800B0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
45982         {"PCS0_RX003_SYNC_REG"         ,           0x11800B0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
45983         {"PCS1_RX000_SYNC_REG"         ,           0x11800B8001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
45984         {"PCS1_RX001_SYNC_REG"         ,           0x11800B8001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
45985         {"PCS1_RX002_SYNC_REG"         ,           0x11800B8001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
45986         {"PCS1_RX003_SYNC_REG"         ,           0x11800B8001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
45987         {"PCS0_SGM000_AN_ADV_REG"      ,           0x11800B0001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
45988         {"PCS0_SGM001_AN_ADV_REG"      ,           0x11800B0001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
45989         {"PCS0_SGM002_AN_ADV_REG"      ,           0x11800B0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
45990         {"PCS0_SGM003_AN_ADV_REG"      ,           0x11800B0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
45991         {"PCS1_SGM000_AN_ADV_REG"      ,           0x11800B8001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
45992         {"PCS1_SGM001_AN_ADV_REG"      ,           0x11800B8001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
45993         {"PCS1_SGM002_AN_ADV_REG"      ,           0x11800B8001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
45994         {"PCS1_SGM003_AN_ADV_REG"      ,           0x11800B8001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
45995         {"PCS0_SGM000_LP_ADV_REG"      ,           0x11800B0001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
45996         {"PCS0_SGM001_LP_ADV_REG"      ,           0x11800B0001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
45997         {"PCS0_SGM002_LP_ADV_REG"      ,           0x11800B0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
45998         {"PCS0_SGM003_LP_ADV_REG"      ,           0x11800B0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
45999         {"PCS1_SGM000_LP_ADV_REG"      ,           0x11800B8001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
46000         {"PCS1_SGM001_LP_ADV_REG"      ,           0x11800B8001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
46001         {"PCS1_SGM002_LP_ADV_REG"      ,           0x11800B8001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
46002         {"PCS1_SGM003_LP_ADV_REG"      ,           0x11800B8001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
46003         {"PCS0_TX000_STATES_REG"       ,           0x11800B0001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
46004         {"PCS0_TX001_STATES_REG"       ,           0x11800B0001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
46005         {"PCS0_TX002_STATES_REG"       ,           0x11800B0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
46006         {"PCS0_TX003_STATES_REG"       ,           0x11800B0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
46007         {"PCS1_TX000_STATES_REG"       ,           0x11800B8001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
46008         {"PCS1_TX001_STATES_REG"       ,           0x11800B8001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
46009         {"PCS1_TX002_STATES_REG"       ,           0x11800B8001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
46010         {"PCS1_TX003_STATES_REG"       ,           0x11800B8001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
46011         {"PCS0_TX_RX000_POLARITY_REG"  ,           0x11800B0001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
46012         {"PCS0_TX_RX001_POLARITY_REG"  ,           0x11800B0001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
46013         {"PCS0_TX_RX002_POLARITY_REG"  ,           0x11800B0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
46014         {"PCS0_TX_RX003_POLARITY_REG"  ,           0x11800B0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
46015         {"PCS1_TX_RX000_POLARITY_REG"  ,           0x11800B8001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
46016         {"PCS1_TX_RX001_POLARITY_REG"  ,           0x11800B8001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
46017         {"PCS1_TX_RX002_POLARITY_REG"  ,           0x11800B8001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
46018         {"PCS1_TX_RX003_POLARITY_REG"  ,           0x11800B8001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
46019         {"PCSX0_10GBX_STATUS_REG"      ,           0x11800B0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
46020         {"PCSX1_10GBX_STATUS_REG"      ,           0x11800B8000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
46021         {"PCSX0_BIST_STATUS_REG"       ,           0x11800B0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
46022         {"PCSX1_BIST_STATUS_REG"       ,           0x11800B8000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
46023         {"PCSX0_BIT_LOCK_STATUS_REG"   ,           0x11800B0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
46024         {"PCSX1_BIT_LOCK_STATUS_REG"   ,           0x11800B8000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
46025         {"PCSX0_CONTROL1_REG"          ,           0x11800B0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     699},
46026         {"PCSX1_CONTROL1_REG"          ,           0x11800B8000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     699},
46027         {"PCSX0_CONTROL2_REG"          ,           0x11800B0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
46028         {"PCSX1_CONTROL2_REG"          ,           0x11800B8000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
46029         {"PCSX0_INT_EN_REG"            ,           0x11800B0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
46030         {"PCSX1_INT_EN_REG"            ,           0x11800B8000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
46031         {"PCSX0_INT_REG"               ,           0x11800B0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
46032         {"PCSX1_INT_REG"               ,           0x11800B8000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
46033         {"PCSX0_LOG_ANL_REG"           ,           0x11800B0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
46034         {"PCSX1_LOG_ANL_REG"           ,           0x11800B8000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
46035         {"PCSX0_MISC_CTL_REG"          ,           0x11800B0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     704},
46036         {"PCSX1_MISC_CTL_REG"          ,           0x11800B8000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     704},
46037         {"PCSX0_RX_SYNC_STATES_REG"    ,           0x11800B0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     705},
46038         {"PCSX1_RX_SYNC_STATES_REG"    ,           0x11800B8000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     705},
46039         {"PCSX0_SPD_ABIL_REG"          ,           0x11800B0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     706},
46040         {"PCSX1_SPD_ABIL_REG"          ,           0x11800B8000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     706},
46041         {"PCSX0_STATUS1_REG"           ,           0x11800B0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     707},
46042         {"PCSX1_STATUS1_REG"           ,           0x11800B8000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     707},
46043         {"PCSX0_STATUS2_REG"           ,           0x11800B0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     708},
46044         {"PCSX1_STATUS2_REG"           ,           0x11800B8000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     708},
46045         {"PCSX0_TX_RX_POLARITY_REG"    ,           0x11800B0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     709},
46046         {"PCSX1_TX_RX_POLARITY_REG"    ,           0x11800B8000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     709},
46047         {"PCSX0_TX_RX_STATES_REG"      ,           0x11800B0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     710},
46048         {"PCSX1_TX_RX_STATES_REG"      ,           0x11800B8000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     710},
46049         {"PESC0_BIST_STATUS"           ,           0x11800C8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     711},
46050         {"PESC1_BIST_STATUS"           ,           0x11800D0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     711},
46051         {"PESC0_BIST_STATUS2"          ,           0x11800C8000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     712},
46052         {"PESC1_BIST_STATUS2"          ,           0x11800D0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     712},
46053         {"PESC0_CFG_RD"                ,           0x11800C8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     713},
46054         {"PESC1_CFG_RD"                ,           0x11800D0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     713},
46055         {"PESC0_CFG_WR"                ,           0x11800C8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     714},
46056         {"PESC1_CFG_WR"                ,           0x11800D0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     714},
46057         {"PESC0_CPL_LUT_VALID"         ,           0x11800C8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     715},
46058         {"PESC1_CPL_LUT_VALID"         ,           0x11800D0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     715},
46059         {"PESC0_CTL_STATUS"            ,           0x11800C8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     716},
46060         {"PESC1_CTL_STATUS"            ,           0x11800D0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     716},
46061         {"PESC0_CTL_STATUS2"           ,           0x11800C8000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     717},
46062         {"PESC1_CTL_STATUS2"           ,           0x11800D0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     717},
46063         {"PESC0_DBG_INFO"              ,           0x11800C8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     718},
46064         {"PESC1_DBG_INFO"              ,           0x11800D0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     718},
46065         {"PESC0_DBG_INFO_EN"           ,           0x11800C80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     719},
46066         {"PESC1_DBG_INFO_EN"           ,           0x11800D00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     719},
46067         {"PESC0_DIAG_STATUS"           ,           0x11800C8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     720},
46068         {"PESC1_DIAG_STATUS"           ,           0x11800D0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     720},
46069         {"PESC0_P2N_BAR0_START"        ,           0x11800C8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     721},
46070         {"PESC1_P2N_BAR0_START"        ,           0x11800D0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     721},
46071         {"PESC0_P2N_BAR1_START"        ,           0x11800C8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     722},
46072         {"PESC1_P2N_BAR1_START"        ,           0x11800D0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     722},
46073         {"PESC0_P2N_BAR2_START"        ,           0x11800C8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     723},
46074         {"PESC1_P2N_BAR2_START"        ,           0x11800D0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     723},
46075         {"PESC0_P2P_BAR000_END"        ,           0x11800C8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
46076         {"PESC0_P2P_BAR001_END"        ,           0x11800C8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
46077         {"PESC0_P2P_BAR002_END"        ,           0x11800C8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
46078         {"PESC0_P2P_BAR003_END"        ,           0x11800C8000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
46079         {"PESC1_P2P_BAR000_END"        ,           0x11800D0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
46080         {"PESC1_P2P_BAR001_END"        ,           0x11800D0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
46081         {"PESC1_P2P_BAR002_END"        ,           0x11800D0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
46082         {"PESC1_P2P_BAR003_END"        ,           0x11800D0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
46083         {"PESC0_P2P_BAR000_START"      ,           0x11800C8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
46084         {"PESC0_P2P_BAR001_START"      ,           0x11800C8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
46085         {"PESC0_P2P_BAR002_START"      ,           0x11800C8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
46086         {"PESC0_P2P_BAR003_START"      ,           0x11800C8000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
46087         {"PESC1_P2P_BAR000_START"      ,           0x11800D0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
46088         {"PESC1_P2P_BAR001_START"      ,           0x11800D0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
46089         {"PESC1_P2P_BAR002_START"      ,           0x11800D0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
46090         {"PESC1_P2P_BAR003_START"      ,           0x11800D0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
46091         {"PESC0_TLP_CREDITS"           ,           0x11800C8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     726},
46092         {"PESC1_TLP_CREDITS"           ,           0x11800D0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     726},
46093         {"PIP_BCK_PRS"                 ,           0x11800A0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     727},
46094         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     728},
46095         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     729},
46096         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     729},
46097         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     729},
46098         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     729},
46099         {"PIP_DSA_SRC_GRP"             ,           0x11800A0000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     730},
46100         {"PIP_DSA_VID_GRP"             ,           0x11800A0000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     731},
46101         {"PIP_FRM_LEN_CHK0"            ,           0x11800A0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     732},
46102         {"PIP_FRM_LEN_CHK1"            ,           0x11800A0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     732},
46103         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     733},
46104         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     734},
46105         {"PIP_HG_PRI_QOS"              ,           0x11800A00001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     735},
46106         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     736},
46107         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     737},
46108         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     738},
46109         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46110         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46111         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46112         {"PIP_PRT_CFG3"                ,           0x11800A0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46113         {"PIP_PRT_CFG16"               ,           0x11800A0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46114         {"PIP_PRT_CFG17"               ,           0x11800A0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46115         {"PIP_PRT_CFG18"               ,           0x11800A0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46116         {"PIP_PRT_CFG19"               ,           0x11800A0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46117         {"PIP_PRT_CFG32"               ,           0x11800A0000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46118         {"PIP_PRT_CFG33"               ,           0x11800A0000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46119         {"PIP_PRT_CFG34"               ,           0x11800A0000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46120         {"PIP_PRT_CFG35"               ,           0x11800A0000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46121         {"PIP_PRT_CFG36"               ,           0x11800A0000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46122         {"PIP_PRT_CFG37"               ,           0x11800A0000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46123         {"PIP_PRT_CFG38"               ,           0x11800A0000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46124         {"PIP_PRT_CFG39"               ,           0x11800A0000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
46125         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46126         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46127         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46128         {"PIP_PRT_TAG3"                ,           0x11800A0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46129         {"PIP_PRT_TAG16"               ,           0x11800A0000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46130         {"PIP_PRT_TAG17"               ,           0x11800A0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46131         {"PIP_PRT_TAG18"               ,           0x11800A0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46132         {"PIP_PRT_TAG19"               ,           0x11800A0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46133         {"PIP_PRT_TAG32"               ,           0x11800A0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46134         {"PIP_PRT_TAG33"               ,           0x11800A0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46135         {"PIP_PRT_TAG34"               ,           0x11800A0000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46136         {"PIP_PRT_TAG35"               ,           0x11800A0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46137         {"PIP_PRT_TAG36"               ,           0x11800A0000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46138         {"PIP_PRT_TAG37"               ,           0x11800A0000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46139         {"PIP_PRT_TAG38"               ,           0x11800A0000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46140         {"PIP_PRT_TAG39"               ,           0x11800A0000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
46141         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46142         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46143         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46144         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46145         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46146         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46147         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46148         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46149         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46150         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46151         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46152         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46153         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46154         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46155         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46156         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46157         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46158         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46159         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46160         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46161         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46162         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46163         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46164         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46165         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46166         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46167         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46168         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46169         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46170         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46171         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46172         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46173         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46174         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46175         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46176         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46177         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46178         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46179         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46180         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46181         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46182         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46183         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46184         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46185         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46186         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46187         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46188         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46189         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46190         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46191         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46192         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46193         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46194         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46195         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46196         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46197         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46198         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46199         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46200         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46201         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46202         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46203         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46204         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
46205         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
46206         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
46207         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
46208         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
46209         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
46210         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
46211         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
46212         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
46213         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
46214         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
46215         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
46216         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
46217         {"PIP_QOS_WATCH4"              ,           0x11800A0000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
46218         {"PIP_QOS_WATCH5"              ,           0x11800A0000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
46219         {"PIP_QOS_WATCH6"              ,           0x11800A0000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
46220         {"PIP_QOS_WATCH7"              ,           0x11800A0000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
46221         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     744},
46222         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     745},
46223         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46224         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46225         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46226         {"PIP_STAT0_PRT3"              ,           0x11800A00008F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46227         {"PIP_STAT0_PRT16"             ,           0x11800A0000D00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46228         {"PIP_STAT0_PRT17"             ,           0x11800A0000D50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46229         {"PIP_STAT0_PRT18"             ,           0x11800A0000DA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46230         {"PIP_STAT0_PRT19"             ,           0x11800A0000DF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46231         {"PIP_STAT0_PRT32"             ,           0x11800A0001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46232         {"PIP_STAT0_PRT33"             ,           0x11800A0001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46233         {"PIP_STAT0_PRT34"             ,           0x11800A00012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46234         {"PIP_STAT0_PRT35"             ,           0x11800A00012F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46235         {"PIP_STAT0_PRT36"             ,           0x11800A0001340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46236         {"PIP_STAT0_PRT37"             ,           0x11800A0001390ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46237         {"PIP_STAT0_PRT38"             ,           0x11800A00013E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46238         {"PIP_STAT0_PRT39"             ,           0x11800A0001430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
46239         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46240         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46241         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46242         {"PIP_STAT1_PRT3"              ,           0x11800A00008F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46243         {"PIP_STAT1_PRT16"             ,           0x11800A0000D08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46244         {"PIP_STAT1_PRT17"             ,           0x11800A0000D58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46245         {"PIP_STAT1_PRT18"             ,           0x11800A0000DA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46246         {"PIP_STAT1_PRT19"             ,           0x11800A0000DF8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46247         {"PIP_STAT1_PRT32"             ,           0x11800A0001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46248         {"PIP_STAT1_PRT33"             ,           0x11800A0001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46249         {"PIP_STAT1_PRT34"             ,           0x11800A00012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46250         {"PIP_STAT1_PRT35"             ,           0x11800A00012F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46251         {"PIP_STAT1_PRT36"             ,           0x11800A0001348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46252         {"PIP_STAT1_PRT37"             ,           0x11800A0001398ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46253         {"PIP_STAT1_PRT38"             ,           0x11800A00013E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46254         {"PIP_STAT1_PRT39"             ,           0x11800A0001438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
46255         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46256         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46257         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46258         {"PIP_STAT2_PRT3"              ,           0x11800A0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46259         {"PIP_STAT2_PRT16"             ,           0x11800A0000D10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46260         {"PIP_STAT2_PRT17"             ,           0x11800A0000D60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46261         {"PIP_STAT2_PRT18"             ,           0x11800A0000DB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46262         {"PIP_STAT2_PRT19"             ,           0x11800A0000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46263         {"PIP_STAT2_PRT32"             ,           0x11800A0001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46264         {"PIP_STAT2_PRT33"             ,           0x11800A0001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46265         {"PIP_STAT2_PRT34"             ,           0x11800A00012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46266         {"PIP_STAT2_PRT35"             ,           0x11800A0001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46267         {"PIP_STAT2_PRT36"             ,           0x11800A0001350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46268         {"PIP_STAT2_PRT37"             ,           0x11800A00013A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46269         {"PIP_STAT2_PRT38"             ,           0x11800A00013F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46270         {"PIP_STAT2_PRT39"             ,           0x11800A0001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
46271         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46272         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46273         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46274         {"PIP_STAT3_PRT3"              ,           0x11800A0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46275         {"PIP_STAT3_PRT16"             ,           0x11800A0000D18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46276         {"PIP_STAT3_PRT17"             ,           0x11800A0000D68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46277         {"PIP_STAT3_PRT18"             ,           0x11800A0000DB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46278         {"PIP_STAT3_PRT19"             ,           0x11800A0000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46279         {"PIP_STAT3_PRT32"             ,           0x11800A0001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46280         {"PIP_STAT3_PRT33"             ,           0x11800A0001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46281         {"PIP_STAT3_PRT34"             ,           0x11800A00012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46282         {"PIP_STAT3_PRT35"             ,           0x11800A0001308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46283         {"PIP_STAT3_PRT36"             ,           0x11800A0001358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46284         {"PIP_STAT3_PRT37"             ,           0x11800A00013A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46285         {"PIP_STAT3_PRT38"             ,           0x11800A00013F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46286         {"PIP_STAT3_PRT39"             ,           0x11800A0001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
46287         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46288         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46289         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46290         {"PIP_STAT4_PRT3"              ,           0x11800A0000910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46291         {"PIP_STAT4_PRT16"             ,           0x11800A0000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46292         {"PIP_STAT4_PRT17"             ,           0x11800A0000D70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46293         {"PIP_STAT4_PRT18"             ,           0x11800A0000DC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46294         {"PIP_STAT4_PRT19"             ,           0x11800A0000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46295         {"PIP_STAT4_PRT32"             ,           0x11800A0001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46296         {"PIP_STAT4_PRT33"             ,           0x11800A0001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46297         {"PIP_STAT4_PRT34"             ,           0x11800A00012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46298         {"PIP_STAT4_PRT35"             ,           0x11800A0001310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46299         {"PIP_STAT4_PRT36"             ,           0x11800A0001360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46300         {"PIP_STAT4_PRT37"             ,           0x11800A00013B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46301         {"PIP_STAT4_PRT38"             ,           0x11800A0001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46302         {"PIP_STAT4_PRT39"             ,           0x11800A0001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
46303         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46304         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46305         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46306         {"PIP_STAT5_PRT3"              ,           0x11800A0000918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46307         {"PIP_STAT5_PRT16"             ,           0x11800A0000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46308         {"PIP_STAT5_PRT17"             ,           0x11800A0000D78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46309         {"PIP_STAT5_PRT18"             ,           0x11800A0000DC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46310         {"PIP_STAT5_PRT19"             ,           0x11800A0000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46311         {"PIP_STAT5_PRT32"             ,           0x11800A0001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46312         {"PIP_STAT5_PRT33"             ,           0x11800A0001278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46313         {"PIP_STAT5_PRT34"             ,           0x11800A00012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46314         {"PIP_STAT5_PRT35"             ,           0x11800A0001318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46315         {"PIP_STAT5_PRT36"             ,           0x11800A0001368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46316         {"PIP_STAT5_PRT37"             ,           0x11800A00013B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46317         {"PIP_STAT5_PRT38"             ,           0x11800A0001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46318         {"PIP_STAT5_PRT39"             ,           0x11800A0001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
46319         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46320         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46321         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46322         {"PIP_STAT6_PRT3"              ,           0x11800A0000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46323         {"PIP_STAT6_PRT16"             ,           0x11800A0000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46324         {"PIP_STAT6_PRT17"             ,           0x11800A0000D80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46325         {"PIP_STAT6_PRT18"             ,           0x11800A0000DD0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46326         {"PIP_STAT6_PRT19"             ,           0x11800A0000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46327         {"PIP_STAT6_PRT32"             ,           0x11800A0001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46328         {"PIP_STAT6_PRT33"             ,           0x11800A0001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46329         {"PIP_STAT6_PRT34"             ,           0x11800A00012D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46330         {"PIP_STAT6_PRT35"             ,           0x11800A0001320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46331         {"PIP_STAT6_PRT36"             ,           0x11800A0001370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46332         {"PIP_STAT6_PRT37"             ,           0x11800A00013C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46333         {"PIP_STAT6_PRT38"             ,           0x11800A0001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46334         {"PIP_STAT6_PRT39"             ,           0x11800A0001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
46335         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46336         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46337         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46338         {"PIP_STAT7_PRT3"              ,           0x11800A0000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46339         {"PIP_STAT7_PRT16"             ,           0x11800A0000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46340         {"PIP_STAT7_PRT17"             ,           0x11800A0000D88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46341         {"PIP_STAT7_PRT18"             ,           0x11800A0000DD8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46342         {"PIP_STAT7_PRT19"             ,           0x11800A0000E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46343         {"PIP_STAT7_PRT32"             ,           0x11800A0001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46344         {"PIP_STAT7_PRT33"             ,           0x11800A0001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46345         {"PIP_STAT7_PRT34"             ,           0x11800A00012D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46346         {"PIP_STAT7_PRT35"             ,           0x11800A0001328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46347         {"PIP_STAT7_PRT36"             ,           0x11800A0001378ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46348         {"PIP_STAT7_PRT37"             ,           0x11800A00013C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46349         {"PIP_STAT7_PRT38"             ,           0x11800A0001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46350         {"PIP_STAT7_PRT39"             ,           0x11800A0001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
46351         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46352         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46353         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46354         {"PIP_STAT8_PRT3"              ,           0x11800A0000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46355         {"PIP_STAT8_PRT16"             ,           0x11800A0000D40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46356         {"PIP_STAT8_PRT17"             ,           0x11800A0000D90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46357         {"PIP_STAT8_PRT18"             ,           0x11800A0000DE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46358         {"PIP_STAT8_PRT19"             ,           0x11800A0000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46359         {"PIP_STAT8_PRT32"             ,           0x11800A0001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46360         {"PIP_STAT8_PRT33"             ,           0x11800A0001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46361         {"PIP_STAT8_PRT34"             ,           0x11800A00012E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46362         {"PIP_STAT8_PRT35"             ,           0x11800A0001330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46363         {"PIP_STAT8_PRT36"             ,           0x11800A0001380ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46364         {"PIP_STAT8_PRT37"             ,           0x11800A00013D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46365         {"PIP_STAT8_PRT38"             ,           0x11800A0001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46366         {"PIP_STAT8_PRT39"             ,           0x11800A0001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
46367         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46368         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46369         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46370         {"PIP_STAT9_PRT3"              ,           0x11800A0000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46371         {"PIP_STAT9_PRT16"             ,           0x11800A0000D48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46372         {"PIP_STAT9_PRT17"             ,           0x11800A0000D98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46373         {"PIP_STAT9_PRT18"             ,           0x11800A0000DE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46374         {"PIP_STAT9_PRT19"             ,           0x11800A0000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46375         {"PIP_STAT9_PRT32"             ,           0x11800A0001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46376         {"PIP_STAT9_PRT33"             ,           0x11800A0001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46377         {"PIP_STAT9_PRT34"             ,           0x11800A00012E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46378         {"PIP_STAT9_PRT35"             ,           0x11800A0001338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46379         {"PIP_STAT9_PRT36"             ,           0x11800A0001388ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46380         {"PIP_STAT9_PRT37"             ,           0x11800A00013D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46381         {"PIP_STAT9_PRT38"             ,           0x11800A0001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46382         {"PIP_STAT9_PRT39"             ,           0x11800A0001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
46383         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     756},
46384         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46385         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46386         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46387         {"PIP_STAT_INB_ERRS3"          ,           0x11800A0001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46388         {"PIP_STAT_INB_ERRS16"         ,           0x11800A0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46389         {"PIP_STAT_INB_ERRS17"         ,           0x11800A0001C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46390         {"PIP_STAT_INB_ERRS18"         ,           0x11800A0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46391         {"PIP_STAT_INB_ERRS19"         ,           0x11800A0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46392         {"PIP_STAT_INB_ERRS32"         ,           0x11800A0001E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46393         {"PIP_STAT_INB_ERRS33"         ,           0x11800A0001E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46394         {"PIP_STAT_INB_ERRS34"         ,           0x11800A0001E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46395         {"PIP_STAT_INB_ERRS35"         ,           0x11800A0001E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46396         {"PIP_STAT_INB_ERRS36"         ,           0x11800A0001E90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46397         {"PIP_STAT_INB_ERRS37"         ,           0x11800A0001EB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46398         {"PIP_STAT_INB_ERRS38"         ,           0x11800A0001ED0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46399         {"PIP_STAT_INB_ERRS39"         ,           0x11800A0001EF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
46400         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46401         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46402         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46403         {"PIP_STAT_INB_OCTS3"          ,           0x11800A0001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46404         {"PIP_STAT_INB_OCTS16"         ,           0x11800A0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46405         {"PIP_STAT_INB_OCTS17"         ,           0x11800A0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46406         {"PIP_STAT_INB_OCTS18"         ,           0x11800A0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46407         {"PIP_STAT_INB_OCTS19"         ,           0x11800A0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46408         {"PIP_STAT_INB_OCTS32"         ,           0x11800A0001E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46409         {"PIP_STAT_INB_OCTS33"         ,           0x11800A0001E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46410         {"PIP_STAT_INB_OCTS34"         ,           0x11800A0001E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46411         {"PIP_STAT_INB_OCTS35"         ,           0x11800A0001E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46412         {"PIP_STAT_INB_OCTS36"         ,           0x11800A0001E88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46413         {"PIP_STAT_INB_OCTS37"         ,           0x11800A0001EA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46414         {"PIP_STAT_INB_OCTS38"         ,           0x11800A0001EC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46415         {"PIP_STAT_INB_OCTS39"         ,           0x11800A0001EE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
46416         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46417         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46418         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46419         {"PIP_STAT_INB_PKTS3"          ,           0x11800A0001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46420         {"PIP_STAT_INB_PKTS16"         ,           0x11800A0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46421         {"PIP_STAT_INB_PKTS17"         ,           0x11800A0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46422         {"PIP_STAT_INB_PKTS18"         ,           0x11800A0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46423         {"PIP_STAT_INB_PKTS19"         ,           0x11800A0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46424         {"PIP_STAT_INB_PKTS32"         ,           0x11800A0001E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46425         {"PIP_STAT_INB_PKTS33"         ,           0x11800A0001E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46426         {"PIP_STAT_INB_PKTS34"         ,           0x11800A0001E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46427         {"PIP_STAT_INB_PKTS35"         ,           0x11800A0001E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46428         {"PIP_STAT_INB_PKTS36"         ,           0x11800A0001E80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46429         {"PIP_STAT_INB_PKTS37"         ,           0x11800A0001EA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46430         {"PIP_STAT_INB_PKTS38"         ,           0x11800A0001EC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46431         {"PIP_STAT_INB_PKTS39"         ,           0x11800A0001EE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
46432         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46433         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46434         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46435         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46436         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46437         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46438         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46439         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46440         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46441         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46442         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46443         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46444         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46445         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46446         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46447         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46448         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46449         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46450         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46451         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46452         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46453         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46454         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46455         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46456         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46457         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46458         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46459         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46460         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46461         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46462         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46463         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46464         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46465         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46466         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46467         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46468         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46469         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46470         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46471         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46472         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46473         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46474         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46475         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46476         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46477         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46478         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46479         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46480         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46481         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46482         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46483         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46484         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46485         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46486         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46487         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46488         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46489         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46490         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46491         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46492         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46493         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46494         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46495         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
46496         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
46497         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
46498         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
46499         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
46500         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
46501         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
46502         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
46503         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
46504         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
46505         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     770},
46506         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
46507         {"PKO_MEM_DEBUG14"             ,           0x1180050001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
46508         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
46509         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
46510         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     775},
46511         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     776},
46512         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     777},
46513         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     778},
46514         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     779},
46515         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     780},
46516         {"PKO_MEM_PORT_PTRS"           ,           0x1180050001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     781},
46517         {"PKO_MEM_PORT_QOS"            ,           0x1180050001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     782},
46518         {"PKO_MEM_PORT_RATE0"          ,           0x1180050001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     783},
46519         {"PKO_MEM_PORT_RATE1"          ,           0x1180050001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     784},
46520         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     785},
46521         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     786},
46522         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     787},
46523         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     788},
46524         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     789},
46525         {"PKO_REG_DEBUG1"              ,           0x11800500000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     790},
46526         {"PKO_REG_DEBUG2"              ,           0x11800500000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     791},
46527         {"PKO_REG_DEBUG3"              ,           0x11800500000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     792},
46528         {"PKO_REG_ENGINE_INFLIGHT"     ,           0x1180050000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     793},
46529         {"PKO_REG_ENGINE_THRESH"       ,           0x1180050000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     794},
46530         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     795},
46531         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     796},
46532         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     797},
46533         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     798},
46534         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     799},
46535         {"PKO_REG_QUEUE_PTRS1"         ,           0x1180050000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     800},
46536         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     801},
46537         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     802},
46538         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     803},
46539         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     804},
46540         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     805},
46541         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     806},
46542         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     806},
46543         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     806},
46544         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     806},
46545         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     806},
46546         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     806},
46547         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     806},
46548         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     806},
46549         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     807},
46550         {"POW_IQ_INT"                  ,           0x1670000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     808},
46551         {"POW_IQ_INT_EN"               ,           0x1670000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     809},
46552         {"POW_IQ_THR0"                 ,           0x16700000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     810},
46553         {"POW_IQ_THR1"                 ,           0x16700000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     810},
46554         {"POW_IQ_THR2"                 ,           0x16700000003B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     810},
46555         {"POW_IQ_THR3"                 ,           0x16700000003B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     810},
46556         {"POW_IQ_THR4"                 ,           0x16700000003C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     810},
46557         {"POW_IQ_THR5"                 ,           0x16700000003C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     810},
46558         {"POW_IQ_THR6"                 ,           0x16700000003D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     810},
46559         {"POW_IQ_THR7"                 ,           0x16700000003D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     810},
46560         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     811},
46561         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     812},
46562         {"POW_PF_RST_MSK"              ,           0x1670000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     813},
46563         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46564         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46565         {"POW_PP_GRP_MSK2"             ,           0x1670000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46566         {"POW_PP_GRP_MSK3"             ,           0x1670000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46567         {"POW_PP_GRP_MSK4"             ,           0x1670000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46568         {"POW_PP_GRP_MSK5"             ,           0x1670000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46569         {"POW_PP_GRP_MSK6"             ,           0x1670000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46570         {"POW_PP_GRP_MSK7"             ,           0x1670000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46571         {"POW_PP_GRP_MSK8"             ,           0x1670000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46572         {"POW_PP_GRP_MSK9"             ,           0x1670000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46573         {"POW_PP_GRP_MSK10"            ,           0x1670000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46574         {"POW_PP_GRP_MSK11"            ,           0x1670000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     814},
46575         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     815},
46576         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     815},
46577         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     815},
46578         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     815},
46579         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     815},
46580         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     815},
46581         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     815},
46582         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     815},
46583         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     816},
46584         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     816},
46585         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     816},
46586         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     816},
46587         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     816},
46588         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     816},
46589         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     816},
46590         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     816},
46591         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     817},
46592         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     818},
46593         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     819},
46594         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     819},
46595         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     819},
46596         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     819},
46597         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     819},
46598         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     819},
46599         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     819},
46600         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     819},
46601         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     820},
46602         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46603         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46604         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46605         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46606         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46607         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46608         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46609         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46610         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46611         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46612         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46613         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46614         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46615         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46616         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46617         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
46618         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     822},
46619         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46620         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46621         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46622         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46623         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46624         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46625         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46626         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46627         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46628         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46629         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46630         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46631         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46632         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46633         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46634         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
46635         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46636         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46637         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46638         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46639         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46640         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46641         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46642         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46643         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46644         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46645         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46646         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46647         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46648         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46649         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46650         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
46651         {"RAD_MEM_DEBUG0"              ,           0x1180070001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     825},
46652         {"RAD_MEM_DEBUG1"              ,           0x1180070001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     826},
46653         {"RAD_MEM_DEBUG2"              ,           0x1180070001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     827},
46654         {"RAD_REG_BIST_RESULT"         ,           0x1180070000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     828},
46655         {"RAD_REG_CMD_BUF"             ,           0x1180070000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     829},
46656         {"RAD_REG_CTL"                 ,           0x1180070000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     830},
46657         {"RAD_REG_DEBUG0"              ,           0x1180070000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     831},
46658         {"RAD_REG_DEBUG1"              ,           0x1180070000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     832},
46659         {"RAD_REG_DEBUG10"             ,           0x1180070000150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     833},
46660         {"RAD_REG_DEBUG11"             ,           0x1180070000158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     834},
46661         {"RAD_REG_DEBUG12"             ,           0x1180070000160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     835},
46662         {"RAD_REG_DEBUG2"              ,           0x1180070000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     836},
46663         {"RAD_REG_DEBUG3"              ,           0x1180070000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     837},
46664         {"RAD_REG_DEBUG4"              ,           0x1180070000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     838},
46665         {"RAD_REG_DEBUG5"              ,           0x1180070000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     839},
46666         {"RAD_REG_DEBUG6"              ,           0x1180070000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     840},
46667         {"RAD_REG_DEBUG7"              ,           0x1180070000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     841},
46668         {"RAD_REG_DEBUG8"              ,           0x1180070000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     842},
46669         {"RAD_REG_DEBUG9"              ,           0x1180070000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     843},
46670         {"RAD_REG_ERROR"               ,           0x1180070000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     844},
46671         {"RAD_REG_INT_MASK"            ,           0x1180070000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     845},
46672         {"RAD_REG_POLYNOMIAL"          ,           0x1180070000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     846},
46673         {"RAD_REG_READ_IDX"            ,           0x1180070000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     847},
46674         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     848},
46675         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     849},
46676         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     850},
46677         {"SMI1_CLK"                    ,           0x1180000001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     850},
46678         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     851},
46679         {"SMI1_CMD"                    ,           0x1180000001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     851},
46680         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     852},
46681         {"SMI1_EN"                     ,           0x1180000001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     852},
46682         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     853},
46683         {"SMI1_RD_DAT"                 ,           0x1180000001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     853},
46684         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     854},
46685         {"SMI1_WR_DAT"                 ,           0x1180000001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     854},
46686         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     855},
46687         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     856},
46688         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     857},
46689         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     858},
46690         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     859},
46691         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     860},
46692         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     861},
46693         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     862},
46694         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     863},
46695         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     864},
46696         {"TRA_BIST_STATUS"             ,           0x11800A8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     865},
46697         {"TRA_CTL"                     ,           0x11800A8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     866},
46698         {"TRA_CYCLES_SINCE"            ,           0x11800A8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     867},
46699         {"TRA_CYCLES_SINCE1"           ,           0x11800A8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     868},
46700         {"TRA_FILT_ADR_ADR"            ,           0x11800A8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     869},
46701         {"TRA_FILT_ADR_MSK"            ,           0x11800A8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     870},
46702         {"TRA_FILT_CMD"                ,           0x11800A8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     871},
46703         {"TRA_FILT_DID"                ,           0x11800A8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     872},
46704         {"TRA_FILT_SID"                ,           0x11800A8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     873},
46705         {"TRA_INT_STATUS"              ,           0x11800A8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     874},
46706         {"TRA_READ_DAT"                ,           0x11800A8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     875},
46707         {"TRA_TRIG0_ADR_ADR"           ,           0x11800A8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     876},
46708         {"TRA_TRIG0_ADR_MSK"           ,           0x11800A80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     877},
46709         {"TRA_TRIG0_CMD"               ,           0x11800A8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     878},
46710         {"TRA_TRIG0_DID"               ,           0x11800A8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     879},
46711         {"TRA_TRIG0_SID"               ,           0x11800A8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     880},
46712         {"TRA_TRIG1_ADR_ADR"           ,           0x11800A80000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     881},
46713         {"TRA_TRIG1_ADR_MSK"           ,           0x11800A80000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     882},
46714         {"TRA_TRIG1_CMD"               ,           0x11800A80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     883},
46715         {"TRA_TRIG1_DID"               ,           0x11800A80000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     884},
46716         {"TRA_TRIG1_SID"               ,           0x11800A80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     885},
46717         {"USBC0_DAINT"                 ,           0x16F0010000818ull,  CVMX_CSR_DB_TYPE_NCB,   32,     886},
46718         {"USBC0_DAINTMSK"              ,           0x16F001000081Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     887},
46719         {"USBC0_DCFG"                  ,           0x16F0010000800ull,  CVMX_CSR_DB_TYPE_NCB,   32,     888},
46720         {"USBC0_DCTL"                  ,           0x16F0010000804ull,  CVMX_CSR_DB_TYPE_NCB,   32,     889},
46721         {"USBC0_DIEPCTL000"            ,           0x16F0010000900ull,  CVMX_CSR_DB_TYPE_NCB,   32,     890},
46722         {"USBC0_DIEPCTL001"            ,           0x16F0010000920ull,  CVMX_CSR_DB_TYPE_NCB,   32,     890},
46723         {"USBC0_DIEPCTL002"            ,           0x16F0010000940ull,  CVMX_CSR_DB_TYPE_NCB,   32,     890},
46724         {"USBC0_DIEPCTL003"            ,           0x16F0010000960ull,  CVMX_CSR_DB_TYPE_NCB,   32,     890},
46725         {"USBC0_DIEPCTL004"            ,           0x16F0010000980ull,  CVMX_CSR_DB_TYPE_NCB,   32,     890},
46726         {"USBC0_DIEPINT000"            ,           0x16F0010000908ull,  CVMX_CSR_DB_TYPE_NCB,   32,     891},
46727         {"USBC0_DIEPINT001"            ,           0x16F0010000928ull,  CVMX_CSR_DB_TYPE_NCB,   32,     891},
46728         {"USBC0_DIEPINT002"            ,           0x16F0010000948ull,  CVMX_CSR_DB_TYPE_NCB,   32,     891},
46729         {"USBC0_DIEPINT003"            ,           0x16F0010000968ull,  CVMX_CSR_DB_TYPE_NCB,   32,     891},
46730         {"USBC0_DIEPINT004"            ,           0x16F0010000988ull,  CVMX_CSR_DB_TYPE_NCB,   32,     891},
46731         {"USBC0_DIEPMSK"               ,           0x16F0010000810ull,  CVMX_CSR_DB_TYPE_NCB,   32,     892},
46732         {"USBC0_DIEPTSIZ000"           ,           0x16F0010000910ull,  CVMX_CSR_DB_TYPE_NCB,   32,     893},
46733         {"USBC0_DIEPTSIZ001"           ,           0x16F0010000930ull,  CVMX_CSR_DB_TYPE_NCB,   32,     893},
46734         {"USBC0_DIEPTSIZ002"           ,           0x16F0010000950ull,  CVMX_CSR_DB_TYPE_NCB,   32,     893},
46735         {"USBC0_DIEPTSIZ003"           ,           0x16F0010000970ull,  CVMX_CSR_DB_TYPE_NCB,   32,     893},
46736         {"USBC0_DIEPTSIZ004"           ,           0x16F0010000990ull,  CVMX_CSR_DB_TYPE_NCB,   32,     893},
46737         {"USBC0_DOEPCTL000"            ,           0x16F0010000B00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     894},
46738         {"USBC0_DOEPCTL001"            ,           0x16F0010000B20ull,  CVMX_CSR_DB_TYPE_NCB,   32,     894},
46739         {"USBC0_DOEPCTL002"            ,           0x16F0010000B40ull,  CVMX_CSR_DB_TYPE_NCB,   32,     894},
46740         {"USBC0_DOEPCTL003"            ,           0x16F0010000B60ull,  CVMX_CSR_DB_TYPE_NCB,   32,     894},
46741         {"USBC0_DOEPCTL004"            ,           0x16F0010000B80ull,  CVMX_CSR_DB_TYPE_NCB,   32,     894},
46742         {"USBC0_DOEPINT000"            ,           0x16F0010000B08ull,  CVMX_CSR_DB_TYPE_NCB,   32,     895},
46743         {"USBC0_DOEPINT001"            ,           0x16F0010000B28ull,  CVMX_CSR_DB_TYPE_NCB,   32,     895},
46744         {"USBC0_DOEPINT002"            ,           0x16F0010000B48ull,  CVMX_CSR_DB_TYPE_NCB,   32,     895},
46745         {"USBC0_DOEPINT003"            ,           0x16F0010000B68ull,  CVMX_CSR_DB_TYPE_NCB,   32,     895},
46746         {"USBC0_DOEPINT004"            ,           0x16F0010000B88ull,  CVMX_CSR_DB_TYPE_NCB,   32,     895},
46747         {"USBC0_DOEPMSK"               ,           0x16F0010000814ull,  CVMX_CSR_DB_TYPE_NCB,   32,     896},
46748         {"USBC0_DOEPTSIZ000"           ,           0x16F0010000B10ull,  CVMX_CSR_DB_TYPE_NCB,   32,     897},
46749         {"USBC0_DOEPTSIZ001"           ,           0x16F0010000B30ull,  CVMX_CSR_DB_TYPE_NCB,   32,     897},
46750         {"USBC0_DOEPTSIZ002"           ,           0x16F0010000B50ull,  CVMX_CSR_DB_TYPE_NCB,   32,     897},
46751         {"USBC0_DOEPTSIZ003"           ,           0x16F0010000B70ull,  CVMX_CSR_DB_TYPE_NCB,   32,     897},
46752         {"USBC0_DOEPTSIZ004"           ,           0x16F0010000B90ull,  CVMX_CSR_DB_TYPE_NCB,   32,     897},
46753         {"USBC0_DPTXFSIZ001"           ,           0x16F0010000104ull,  CVMX_CSR_DB_TYPE_NCB,   32,     898},
46754         {"USBC0_DPTXFSIZ002"           ,           0x16F0010000108ull,  CVMX_CSR_DB_TYPE_NCB,   32,     898},
46755         {"USBC0_DPTXFSIZ003"           ,           0x16F001000010Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     898},
46756         {"USBC0_DPTXFSIZ004"           ,           0x16F0010000110ull,  CVMX_CSR_DB_TYPE_NCB,   32,     898},
46757         {"USBC0_DSTS"                  ,           0x16F0010000808ull,  CVMX_CSR_DB_TYPE_NCB,   32,     899},
46758         {"USBC0_DTKNQR1"               ,           0x16F0010000820ull,  CVMX_CSR_DB_TYPE_NCB,   32,     900},
46759         {"USBC0_DTKNQR2"               ,           0x16F0010000824ull,  CVMX_CSR_DB_TYPE_NCB,   32,     901},
46760         {"USBC0_DTKNQR3"               ,           0x16F0010000830ull,  CVMX_CSR_DB_TYPE_NCB,   32,     902},
46761         {"USBC0_DTKNQR4"               ,           0x16F0010000834ull,  CVMX_CSR_DB_TYPE_NCB,   32,     903},
46762         {"USBC0_GAHBCFG"               ,           0x16F0010000008ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
46763         {"USBC0_GHWCFG1"               ,           0x16F0010000044ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
46764         {"USBC0_GHWCFG2"               ,           0x16F0010000048ull,  CVMX_CSR_DB_TYPE_NCB,   32,     906},
46765         {"USBC0_GHWCFG3"               ,           0x16F001000004Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
46766         {"USBC0_GHWCFG4"               ,           0x16F0010000050ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
46767         {"USBC0_GINTMSK"               ,           0x16F0010000018ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
46768         {"USBC0_GINTSTS"               ,           0x16F0010000014ull,  CVMX_CSR_DB_TYPE_NCB,   32,     910},
46769         {"USBC0_GNPTXFSIZ"             ,           0x16F0010000028ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
46770         {"USBC0_GNPTXSTS"              ,           0x16F001000002Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     912},
46771         {"USBC0_GOTGCTL"               ,           0x16F0010000000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     913},
46772         {"USBC0_GOTGINT"               ,           0x16F0010000004ull,  CVMX_CSR_DB_TYPE_NCB,   32,     914},
46773         {"USBC0_GRSTCTL"               ,           0x16F0010000010ull,  CVMX_CSR_DB_TYPE_NCB,   32,     915},
46774         {"USBC0_GRXFSIZ"               ,           0x16F0010000024ull,  CVMX_CSR_DB_TYPE_NCB,   32,     916},
46775         {"USBC0_GRXSTSPD"              ,           0x16F0010040020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     917},
46776         {"USBC0_GRXSTSPH"              ,           0x16F0010000020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     918},
46777         {"USBC0_GRXSTSRD"              ,           0x16F001004001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     919},
46778         {"USBC0_GRXSTSRH"              ,           0x16F001000001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     920},
46779         {"USBC0_GSNPSID"               ,           0x16F0010000040ull,  CVMX_CSR_DB_TYPE_NCB,   32,     921},
46780         {"USBC0_GUSBCFG"               ,           0x16F001000000Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     922},
46781         {"USBC0_HAINT"                 ,           0x16F0010000414ull,  CVMX_CSR_DB_TYPE_NCB,   32,     923},
46782         {"USBC0_HAINTMSK"              ,           0x16F0010000418ull,  CVMX_CSR_DB_TYPE_NCB,   32,     924},
46783         {"USBC0_HCCHAR000"             ,           0x16F0010000500ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
46784         {"USBC0_HCCHAR001"             ,           0x16F0010000520ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
46785         {"USBC0_HCCHAR002"             ,           0x16F0010000540ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
46786         {"USBC0_HCCHAR003"             ,           0x16F0010000560ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
46787         {"USBC0_HCCHAR004"             ,           0x16F0010000580ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
46788         {"USBC0_HCCHAR005"             ,           0x16F00100005A0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
46789         {"USBC0_HCCHAR006"             ,           0x16F00100005C0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
46790         {"USBC0_HCCHAR007"             ,           0x16F00100005E0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
46791         {"USBC0_HCFG"                  ,           0x16F0010000400ull,  CVMX_CSR_DB_TYPE_NCB,   32,     926},
46792         {"USBC0_HCINT000"              ,           0x16F0010000508ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
46793         {"USBC0_HCINT001"              ,           0x16F0010000528ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
46794         {"USBC0_HCINT002"              ,           0x16F0010000548ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
46795         {"USBC0_HCINT003"              ,           0x16F0010000568ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
46796         {"USBC0_HCINT004"              ,           0x16F0010000588ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
46797         {"USBC0_HCINT005"              ,           0x16F00100005A8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
46798         {"USBC0_HCINT006"              ,           0x16F00100005C8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
46799         {"USBC0_HCINT007"              ,           0x16F00100005E8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
46800         {"USBC0_HCINTMSK000"           ,           0x16F001000050Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
46801         {"USBC0_HCINTMSK001"           ,           0x16F001000052Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
46802         {"USBC0_HCINTMSK002"           ,           0x16F001000054Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
46803         {"USBC0_HCINTMSK003"           ,           0x16F001000056Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
46804         {"USBC0_HCINTMSK004"           ,           0x16F001000058Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
46805         {"USBC0_HCINTMSK005"           ,           0x16F00100005ACull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
46806         {"USBC0_HCINTMSK006"           ,           0x16F00100005CCull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
46807         {"USBC0_HCINTMSK007"           ,           0x16F00100005ECull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
46808         {"USBC0_HCSPLT000"             ,           0x16F0010000504ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
46809         {"USBC0_HCSPLT001"             ,           0x16F0010000524ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
46810         {"USBC0_HCSPLT002"             ,           0x16F0010000544ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
46811         {"USBC0_HCSPLT003"             ,           0x16F0010000564ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
46812         {"USBC0_HCSPLT004"             ,           0x16F0010000584ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
46813         {"USBC0_HCSPLT005"             ,           0x16F00100005A4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
46814         {"USBC0_HCSPLT006"             ,           0x16F00100005C4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
46815         {"USBC0_HCSPLT007"             ,           0x16F00100005E4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
46816         {"USBC0_HCTSIZ000"             ,           0x16F0010000510ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
46817         {"USBC0_HCTSIZ001"             ,           0x16F0010000530ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
46818         {"USBC0_HCTSIZ002"             ,           0x16F0010000550ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
46819         {"USBC0_HCTSIZ003"             ,           0x16F0010000570ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
46820         {"USBC0_HCTSIZ004"             ,           0x16F0010000590ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
46821         {"USBC0_HCTSIZ005"             ,           0x16F00100005B0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
46822         {"USBC0_HCTSIZ006"             ,           0x16F00100005D0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
46823         {"USBC0_HCTSIZ007"             ,           0x16F00100005F0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
46824         {"USBC0_HFIR"                  ,           0x16F0010000404ull,  CVMX_CSR_DB_TYPE_NCB,   32,     931},
46825         {"USBC0_HFNUM"                 ,           0x16F0010000408ull,  CVMX_CSR_DB_TYPE_NCB,   32,     932},
46826         {"USBC0_HPRT"                  ,           0x16F0010000440ull,  CVMX_CSR_DB_TYPE_NCB,   32,     933},
46827         {"USBC0_HPTXFSIZ"              ,           0x16F0010000100ull,  CVMX_CSR_DB_TYPE_NCB,   32,     934},
46828         {"USBC0_HPTXSTS"               ,           0x16F0010000410ull,  CVMX_CSR_DB_TYPE_NCB,   32,     935},
46829         {"USBC0_NPTXDFIFO000"          ,           0x16F0010001000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
46830         {"USBC0_NPTXDFIFO001"          ,           0x16F0010002000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
46831         {"USBC0_NPTXDFIFO002"          ,           0x16F0010003000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
46832         {"USBC0_NPTXDFIFO003"          ,           0x16F0010004000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
46833         {"USBC0_NPTXDFIFO004"          ,           0x16F0010005000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
46834         {"USBC0_NPTXDFIFO005"          ,           0x16F0010006000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
46835         {"USBC0_NPTXDFIFO006"          ,           0x16F0010007000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
46836         {"USBC0_NPTXDFIFO007"          ,           0x16F0010008000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
46837         {"USBC0_PCGCCTL"               ,           0x16F0010000E00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     937},
46838         {"USBN0_BIST_STATUS"           ,           0x11800680007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     938},
46839         {"USBN0_CLK_CTL"               ,           0x1180068000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     939},
46840         {"USBN0_CTL_STATUS"            ,           0x16F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     940},
46841         {"USBN0_DMA0_INB_CHN0"         ,           0x16F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     941},
46842         {"USBN0_DMA0_INB_CHN1"         ,           0x16F0000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     942},
46843         {"USBN0_DMA0_INB_CHN2"         ,           0x16F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     943},
46844         {"USBN0_DMA0_INB_CHN3"         ,           0x16F0000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     944},
46845         {"USBN0_DMA0_INB_CHN4"         ,           0x16F0000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     945},
46846         {"USBN0_DMA0_INB_CHN5"         ,           0x16F0000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     946},
46847         {"USBN0_DMA0_INB_CHN6"         ,           0x16F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     947},
46848         {"USBN0_DMA0_INB_CHN7"         ,           0x16F0000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     948},
46849         {"USBN0_DMA0_OUTB_CHN0"        ,           0x16F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     949},
46850         {"USBN0_DMA0_OUTB_CHN1"        ,           0x16F0000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     950},
46851         {"USBN0_DMA0_OUTB_CHN2"        ,           0x16F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     951},
46852         {"USBN0_DMA0_OUTB_CHN3"        ,           0x16F0000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     952},
46853         {"USBN0_DMA0_OUTB_CHN4"        ,           0x16F0000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     953},
46854         {"USBN0_DMA0_OUTB_CHN5"        ,           0x16F0000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     954},
46855         {"USBN0_DMA0_OUTB_CHN6"        ,           0x16F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     955},
46856         {"USBN0_DMA0_OUTB_CHN7"        ,           0x16F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     956},
46857         {"USBN0_DMA_TEST"              ,           0x16F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     957},
46858         {"USBN0_INT_ENB"               ,           0x1180068000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     958},
46859         {"USBN0_INT_SUM"               ,           0x1180068000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     959},
46860         {"USBN0_USBP_CTL_STATUS"       ,           0x1180068000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     960},
46861         {"ZIP_CMD_BIST_RESULT"         ,           0x1180038000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     961},
46862         {"ZIP_CMD_BUF"                 ,           0x1180038000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     962},
46863         {"ZIP_CMD_CTL"                 ,           0x1180038000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     963},
46864         {"ZIP_CONSTANTS"               ,           0x11800380000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     964},
46865         {"ZIP_DEBUG0"                  ,           0x1180038000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     965},
46866         {"ZIP_ERROR"                   ,           0x1180038000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     966},
46867         {"ZIP_INT_MASK"                ,           0x1180038000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     967},
46868         {NULL,0,0,0,0}
46869 };
46870 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn56xx[] = {
46871         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
46872         {"RESERVED_0_1"                ,        0,      2,      0,      "RAZ",  0,      0,      0ull,   0ull},
46873         {"OUT_OVR"                     ,        2,      1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
46874         {"RESERVED_3_21"               ,        3,      19,     0,      "RAZ",  0,      0,      0ull,   0ull},
46875         {"LOSTSTAT"                    ,        22,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
46876         {"RESERVED_23_25"              ,        23,     3,      0,      "RAZ",  0,      0,      0ull,   0ull},
46877         {"STATOVR"                     ,        26,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
46878         {"RESERVED_27_31"              ,        27,     5,      0,      "RAZ",  0,      0,      0ull,   0ull},
46879         {"OVRFLW"                      ,        32,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
46880         {"TXPOP"                       ,        33,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
46881         {"TXPSH"                       ,        34,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
46882         {"RESERVED_35_63"              ,        35,     29,     0,      "RAZ",  1,      1,      0,      0},
46883         {"STATUS"                      ,        0,      10,     1,      "RO",   0,      0,      0ull,   0ull},
46884         {"RESERVED_10_63"              ,        10,     54,     1,      "RAZ",  1,      1,      0,      0},
46885         {"NCTL"                        ,        0,      5,      2,      "R/W",  0,      1,      16ull,  0},
46886         {"RESERVED_5_7"                ,        5,      3,      2,      "RAZ",  1,      1,      0,      0},
46887         {"PCTL"                        ,        8,      5,      2,      "R/W",  0,      1,      16ull,  0},
46888         {"RESERVED_13_15"              ,        13,     3,      2,      "RAZ",  1,      1,      0,      0},
46889         {"BYP_EN"                      ,        16,     1,      2,      "R/W",  0,      0,      0ull,   0ull},
46890         {"RESERVED_17_63"              ,        17,     47,     2,      "RAZ",  1,      1,      0,      0},
46891         {"RESERVED_0_0"                ,        0,      1,      3,      "RAZ",  1,      1,      0,      0},
46892         {"EN"                          ,        1,      1,      3,      "R/W",  0,      0,      0ull,   1ull},
46893         {"RESERVED_2_63"               ,        2,      62,     3,      "RAZ",  1,      1,      0,      0},
46894         {"EN"                          ,        0,      1,      4,      "R/W",  0,      1,      0ull,   0},
46895         {"SPEED"                       ,        1,      1,      4,      "RO",   0,      0,      0ull,   0ull},
46896         {"DUPLEX"                      ,        2,      1,      4,      "R/W",  0,      1,      1ull,   0},
46897         {"SLOTTIME"                    ,        3,      1,      4,      "RO",   0,      0,      0ull,   0ull},
46898         {"RX_EN"                       ,        4,      1,      4,      "R/W",  0,      1,      0ull,   0},
46899         {"TX_EN"                       ,        5,      1,      4,      "R/W",  0,      1,      0ull,   0},
46900         {"RESERVED_6_63"               ,        6,      58,     4,      "RAZ",  1,      1,      0,      0},
46901         {"ADR"                         ,        0,      64,     5,      "R/W",  0,      1,      0ull,   0},
46902         {"ADR"                         ,        0,      64,     6,      "R/W",  0,      1,      0ull,   0},
46903         {"ADR"                         ,        0,      64,     7,      "R/W",  0,      1,      0ull,   0},
46904         {"ADR"                         ,        0,      64,     8,      "R/W",  0,      1,      0ull,   0},
46905         {"ADR"                         ,        0,      64,     9,      "R/W",  0,      1,      0ull,   0},
46906         {"ADR"                         ,        0,      64,     10,     "R/W",  0,      1,      0ull,   0},
46907         {"EN"                          ,        0,      8,      11,     "R/W",  0,      1,      0ull,   0},
46908         {"RESERVED_8_63"               ,        8,      56,     11,     "RAZ",  1,      1,      0,      0},
46909         {"BCST"                        ,        0,      1,      12,     "R/W",  0,      1,      1ull,   0},
46910         {"MCST"                        ,        1,      2,      12,     "R/W",  0,      1,      0ull,   0},
46911         {"CAM_MODE"                    ,        3,      1,      12,     "R/W",  0,      1,      0ull,   0},
46912         {"RESERVED_4_63"               ,        4,      60,     12,     "RAZ",  1,      1,      0,      0},
46913         {"CNT"                         ,        0,      5,      13,     "R/W",  0,      0,      24ull,  24ull},
46914         {"RESERVED_5_63"               ,        5,      59,     13,     "RAZ",  1,      1,      0,      0},
46915         {"MINERR"                      ,        0,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
46916         {"RESERVED_1_1"                ,        1,      1,      14,     "RAZ",  0,      0,      0ull,   0ull},
46917         {"MAXERR"                      ,        2,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
46918         {"JABBER"                      ,        3,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
46919         {"FCSERR"                      ,        4,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
46920         {"ALNERR"                      ,        5,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
46921         {"LENERR"                      ,        6,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
46922         {"RCVERR"                      ,        7,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
46923         {"SKPERR"                      ,        8,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
46924         {"RESERVED_9_63"               ,        9,      55,     14,     "RAZ",  1,      1,      0,      0},
46925         {"PRE_CHK"                     ,        0,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
46926         {"PRE_STRP"                    ,        1,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
46927         {"CTL_DRP"                     ,        2,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
46928         {"CTL_BCK"                     ,        3,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
46929         {"CTL_MCST"                    ,        4,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
46930         {"CTL_SMAC"                    ,        5,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
46931         {"PRE_FREE"                    ,        6,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
46932         {"VLAN_LEN"                    ,        7,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
46933         {"PAD_LEN"                     ,        8,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
46934         {"PRE_ALIGN"                   ,        9,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
46935         {"RESERVED_10_63"              ,        10,     54,     15,     "RAZ",  1,      1,      0,      0},
46936         {"LEN"                         ,        0,      16,     16,     "R/W",  0,      0,      1536ull,        1536ull},
46937         {"RESERVED_16_63"              ,        16,     48,     16,     "RAZ",  1,      1,      0,      0},
46938         {"LEN"                         ,        0,      16,     17,     "R/W",  0,      0,      64ull,  64ull},
46939         {"RESERVED_16_63"              ,        16,     48,     17,     "RAZ",  1,      1,      0,      0},
46940         {"IFG"                         ,        0,      4,      18,     "R/W",  0,      0,      12ull,  12ull},
46941         {"RESERVED_4_63"               ,        4,      60,     18,     "RAZ",  1,      1,      0,      0},
46942         {"MINERR"                      ,        0,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
46943         {"RESERVED_1_1"                ,        1,      1,      19,     "RAZ",  1,      1,      0,      0},
46944         {"MAXERR"                      ,        2,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
46945         {"JABBER"                      ,        3,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
46946         {"FCSERR"                      ,        4,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
46947         {"ALNERR"                      ,        5,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
46948         {"LENERR"                      ,        6,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
46949         {"RCVERR"                      ,        7,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
46950         {"SKPERR"                      ,        8,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
46951         {"RESERVED_9_9"                ,        9,      1,      19,     "RAZ",  1,      1,      0,      0},
46952         {"OVRERR"                      ,        10,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
46953         {"PCTERR"                      ,        11,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
46954         {"RSVERR"                      ,        12,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
46955         {"FALERR"                      ,        13,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
46956         {"COLDET"                      ,        14,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
46957         {"IFGERR"                      ,        15,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
46958         {"RESERVED_16_18"              ,        16,     3,      19,     "RAZ",  1,      1,      0,      0},
46959         {"PAUSE_DRP"                   ,        19,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
46960         {"RESERVED_20_63"              ,        20,     44,     19,     "RAZ",  1,      1,      0,      0},
46961         {"MINERR"                      ,        0,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46962         {"RESERVED_1_1"                ,        1,      1,      20,     "RAZ",  0,      0,      0ull,   0ull},
46963         {"MAXERR"                      ,        2,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46964         {"JABBER"                      ,        3,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46965         {"FCSERR"                      ,        4,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46966         {"ALNERR"                      ,        5,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46967         {"LENERR"                      ,        6,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46968         {"RCVERR"                      ,        7,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46969         {"SKPERR"                      ,        8,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46970         {"RESERVED_9_9"                ,        9,      1,      20,     "RAZ",  0,      0,      0ull,   0ull},
46971         {"OVRERR"                      ,        10,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46972         {"PCTERR"                      ,        11,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46973         {"RSVERR"                      ,        12,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46974         {"FALERR"                      ,        13,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46975         {"COLDET"                      ,        14,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46976         {"IFGERR"                      ,        15,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46977         {"RESERVED_16_18"              ,        16,     3,      20,     "RAZ",  0,      0,      0ull,   0ull},
46978         {"PAUSE_DRP"                   ,        19,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
46979         {"RESERVED_20_63"              ,        20,     44,     20,     "RAZ",  1,      1,      0,      0},
46980         {"CNT"                         ,        0,      16,     21,     "R/W",  0,      0,      10240ull,       10240ull},
46981         {"RESERVED_16_63"              ,        16,     48,     21,     "RAZ",  1,      1,      0,      0},
46982         {"STATUS"                      ,        0,      16,     22,     "R/W1C",        0,      1,      0ull,   0},
46983         {"RESERVED_16_63"              ,        16,     48,     22,     "RAZ",  1,      1,      0,      0},
46984         {"RD_CLR"                      ,        0,      1,      23,     "R/W",  0,      0,      0ull,   0ull},
46985         {"RESERVED_1_63"               ,        1,      63,     23,     "RAZ",  1,      1,      0,      0},
46986         {"CNT"                         ,        0,      48,     24,     "RC/W", 0,      1,      0ull,   0},
46987         {"RESERVED_48_63"              ,        48,     16,     24,     "RAZ",  1,      1,      0,      0},
46988         {"CNT"                         ,        0,      48,     25,     "RC/W", 0,      1,      0ull,   0},
46989         {"RESERVED_48_63"              ,        48,     16,     25,     "RAZ",  1,      1,      0,      0},
46990         {"CNT"                         ,        0,      48,     26,     "RC/W", 0,      1,      0ull,   0},
46991         {"RESERVED_48_63"              ,        48,     16,     26,     "RAZ",  1,      1,      0,      0},
46992         {"CNT"                         ,        0,      48,     27,     "RC/W", 0,      1,      0ull,   0},
46993         {"RESERVED_48_63"              ,        48,     16,     27,     "RAZ",  1,      1,      0,      0},
46994         {"CNT"                         ,        0,      32,     28,     "RC/W", 0,      1,      0ull,   0},
46995         {"RESERVED_32_63"              ,        32,     32,     28,     "RAZ",  1,      1,      0,      0},
46996         {"CNT"                         ,        0,      32,     29,     "RC/W", 0,      1,      0ull,   0},
46997         {"RESERVED_32_63"              ,        32,     32,     29,     "RAZ",  1,      1,      0,      0},
46998         {"CNT"                         ,        0,      32,     30,     "RC/W", 0,      1,      0ull,   0},
46999         {"RESERVED_32_63"              ,        32,     32,     30,     "RAZ",  1,      1,      0,      0},
47000         {"CNT"                         ,        0,      32,     31,     "RC/W", 0,      1,      0ull,   0},
47001         {"RESERVED_32_63"              ,        32,     32,     31,     "RAZ",  1,      1,      0,      0},
47002         {"CNT"                         ,        0,      32,     32,     "RC/W", 0,      1,      0ull,   0},
47003         {"RESERVED_32_63"              ,        32,     32,     32,     "RAZ",  1,      1,      0,      0},
47004         {"LEN"                         ,        0,      7,      33,     "R/W",  0,      0,      0ull,   0ull},
47005         {"RESERVED_7_7"                ,        7,      1,      33,     "RAZ",  1,      1,      0,      0},
47006         {"FCSSEL"                      ,        8,      1,      33,     "R/W",  0,      0,      0ull,   0ull},
47007         {"RESERVED_9_63"               ,        9,      55,     33,     "RAZ",  1,      1,      0,      0},
47008         {"MARK"                        ,        0,      6,      34,     "R/W",  0,      0,      2ull,   2ull},
47009         {"RESERVED_6_63"               ,        6,      58,     34,     "RAZ",  1,      1,      0,      0},
47010         {"MARK"                        ,        0,      6,      35,     "R/W",  0,      0,      16ull,  16ull},
47011         {"RESERVED_6_63"               ,        6,      58,     35,     "RAZ",  1,      1,      0,      0},
47012         {"MARK"                        ,        0,      9,      36,     "R/W",  0,      0,      32ull,  32ull},
47013         {"RESERVED_9_63"               ,        9,      55,     36,     "RAZ",  1,      1,      0,      0},
47014         {"COMMIT"                      ,        0,      1,      37,     "RO",   0,      0,      0ull,   0ull},
47015         {"RESERVED_1_15"               ,        1,      15,     37,     "RAZ",  1,      1,      0,      0},
47016         {"DROP"                        ,        16,     1,      37,     "RO",   0,      0,      0ull,   0ull},
47017         {"RESERVED_17_63"              ,        17,     47,     37,     "RAZ",  1,      1,      0,      0},
47018         {"RX"                          ,        0,      1,      38,     "RC",   0,      0,      0ull,   0ull},
47019         {"RESERVED_1_3"                ,        1,      3,      38,     "RAZ",  1,      1,      0,      0},
47020         {"TX"                          ,        4,      1,      38,     "RC",   0,      0,      0ull,   0ull},
47021         {"RESERVED_5_63"               ,        5,      59,     38,     "RAZ",  1,      1,      0,      0},
47022         {"SMAC"                        ,        0,      48,     39,     "R/W",  0,      1,      0ull,   0},
47023         {"RESERVED_48_63"              ,        48,     16,     39,     "RAZ",  1,      1,      0,      0},
47024         {"CNT"                         ,        0,      16,     40,     "R/W1C",        0,      0,      0ull,   0ull},
47025         {"BP"                          ,        16,     1,      40,     "RO",   0,      0,      0ull,   0ull},
47026         {"RESERVED_17_63"              ,        17,     47,     40,     "RAZ",  1,      1,      0,      0},
47027         {"PREAMBLE"                    ,        0,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
47028         {"PAD"                         ,        1,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
47029         {"FCS"                         ,        2,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
47030         {"FORCE_FCS"                   ,        3,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
47031         {"RESERVED_4_63"               ,        4,      60,     41,     "RAZ",  1,      1,      0,      0},
47032         {"XSCOL_EN"                    ,        0,      1,      42,     "R/W",  0,      0,      1ull,   1ull},
47033         {"XSDEF_EN"                    ,        1,      1,      42,     "R/W",  0,      0,      1ull,   1ull},
47034         {"RESERVED_2_63"               ,        2,      62,     42,     "RAZ",  1,      1,      0,      0},
47035         {"MIN_SIZE"                    ,        0,      8,      43,     "R/W",  0,      0,      59ull,  59ull},
47036         {"RESERVED_8_63"               ,        8,      56,     43,     "RAZ",  1,      1,      0,      0},
47037         {"INTERVAL"                    ,        0,      16,     44,     "R/W",  0,      1,      16ull,  0},
47038         {"RESERVED_16_63"              ,        16,     48,     44,     "RAZ",  1,      1,      0,      0},
47039         {"TIME"                        ,        0,      16,     45,     "R/W",  0,      1,      96ull,  0},
47040         {"RESERVED_16_63"              ,        16,     48,     45,     "RAZ",  1,      1,      0,      0},
47041         {"TIME"                        ,        0,      16,     46,     "RO",   1,      1,      0,      0},
47042         {"RESERVED_16_63"              ,        16,     48,     46,     "RAZ",  1,      1,      0,      0},
47043         {"SEND"                        ,        0,      1,      47,     "R/W",  0,      0,      1ull,   1ull},
47044         {"RESERVED_1_63"               ,        1,      63,     47,     "RAZ",  1,      1,      0,      0},
47045         {"TIME"                        ,        0,      16,     48,     "R/W",  0,      1,      0ull,   0},
47046         {"RESERVED_16_63"              ,        16,     48,     48,     "RAZ",  1,      1,      0,      0},
47047         {"XSCOL"                       ,        0,      32,     49,     "RC/W", 0,      1,      0ull,   0},
47048         {"XSDEF"                       ,        32,     32,     49,     "RC/W", 0,      1,      0ull,   0},
47049         {"MCOL"                        ,        0,      32,     50,     "RC/W", 0,      1,      0ull,   0},
47050         {"SCOL"                        ,        32,     32,     50,     "RC/W", 0,      1,      0ull,   0},
47051         {"OCTS"                        ,        0,      48,     51,     "RC/W", 0,      1,      0ull,   0},
47052         {"RESERVED_48_63"              ,        48,     16,     51,     "RAZ",  1,      1,      0,      0},
47053         {"PKTS"                        ,        0,      32,     52,     "RC/W", 0,      1,      0ull,   0},
47054         {"RESERVED_32_63"              ,        32,     32,     52,     "RAZ",  1,      1,      0,      0},
47055         {"HIST0"                       ,        0,      32,     53,     "RC/W", 0,      1,      0ull,   0},
47056         {"HIST1"                       ,        32,     32,     53,     "RC/W", 0,      1,      0ull,   0},
47057         {"HIST2"                       ,        0,      32,     54,     "RC/W", 0,      1,      0ull,   0},
47058         {"HIST3"                       ,        32,     32,     54,     "RC/W", 0,      1,      0ull,   0},
47059         {"HIST4"                       ,        0,      32,     55,     "RC/W", 0,      1,      0ull,   0},
47060         {"HIST5"                       ,        32,     32,     55,     "RC/W", 0,      1,      0ull,   0},
47061         {"HIST6"                       ,        0,      32,     56,     "RC/W", 0,      1,      0ull,   0},
47062         {"HIST7"                       ,        32,     32,     56,     "RC/W", 0,      1,      0ull,   0},
47063         {"BCST"                        ,        0,      32,     57,     "RC/W", 0,      1,      0ull,   0},
47064         {"MCST"                        ,        32,     32,     57,     "RC/W", 0,      1,      0ull,   0},
47065         {"CTL"                         ,        0,      32,     58,     "RC/W", 0,      1,      0ull,   0},
47066         {"UNDFLW"                      ,        32,     32,     58,     "RC/W", 0,      1,      0ull,   0},
47067         {"RD_CLR"                      ,        0,      1,      59,     "R/W",  0,      0,      0ull,   0ull},
47068         {"RESERVED_1_63"               ,        1,      63,     59,     "RAZ",  1,      1,      0,      0},
47069         {"CNT"                         ,        0,      6,      60,     "R/W",  0,      0,      16ull,  16ull},
47070         {"RESERVED_6_63"               ,        6,      58,     60,     "RAZ",  1,      1,      0,      0},
47071         {"BP"                          ,        0,      1,      61,     "RO",   0,      0,      0ull,   0ull},
47072         {"RESERVED_1_63"               ,        1,      63,     61,     "RAZ",  1,      1,      0,      0},
47073         {"LIMIT"                       ,        0,      5,      62,     "R/W",  0,      0,      16ull,  16ull},
47074         {"RESERVED_5_63"               ,        5,      59,     62,     "RAZ",  1,      1,      0,      0},
47075         {"IFG1"                        ,        0,      4,      63,     "R/W",  0,      1,      8ull,   0},
47076         {"IFG2"                        ,        4,      4,      63,     "R/W",  0,      1,      4ull,   0},
47077         {"RESERVED_8_63"               ,        8,      56,     63,     "RAZ",  1,      1,      0,      0},
47078         {"PKO_NXA"                     ,        0,      1,      64,     "R/W",  0,      0,      0ull,   0ull},
47079         {"RESERVED_1_1"                ,        1,      1,      64,     "RAZ",  0,      0,      0ull,   0ull},
47080         {"UNDFLW"                      ,        2,      1,      64,     "R/W",  0,      0,      0ull,   0ull},
47081         {"RESERVED_3_7"                ,        3,      5,      64,     "RAZ",  0,      0,      0ull,   0ull},
47082         {"XSCOL"                       ,        8,      1,      64,     "R/W",  0,      0,      0ull,   0ull},
47083         {"RESERVED_9_11"               ,        9,      3,      64,     "RAZ",  0,      0,      0ull,   0ull},
47084         {"XSDEF"                       ,        12,     1,      64,     "R/W",  0,      0,      0ull,   0ull},
47085         {"RESERVED_13_15"              ,        13,     3,      64,     "RAZ",  0,      0,      0ull,   0ull},
47086         {"LATE_COL"                    ,        16,     1,      64,     "R/W",  0,      0,      0ull,   0ull},
47087         {"RESERVED_17_63"              ,        17,     47,     64,     "RAZ",  0,      0,      0ull,   0ull},
47088         {"PKO_NXA"                     ,        0,      1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
47089         {"RESERVED_1_1"                ,        1,      1,      65,     "RAZ",  0,      0,      0ull,   0ull},
47090         {"UNDFLW"                      ,        2,      1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
47091         {"RESERVED_3_7"                ,        3,      5,      65,     "RAZ",  0,      0,      0ull,   0ull},
47092         {"XSCOL"                       ,        8,      1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
47093         {"RESERVED_9_11"               ,        9,      3,      65,     "RAZ",  0,      0,      0ull,   0ull},
47094         {"XSDEF"                       ,        12,     1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
47095         {"RESERVED_13_15"              ,        13,     3,      65,     "RAZ",  0,      0,      0ull,   0ull},
47096         {"LATE_COL"                    ,        16,     1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
47097         {"RESERVED_17_63"              ,        17,     47,     65,     "RAZ",  0,      0,      0ull,   0ull},
47098         {"JAM"                         ,        0,      8,      66,     "R/W",  0,      1,      238ull, 0},
47099         {"RESERVED_8_63"               ,        8,      56,     66,     "RAZ",  1,      1,      0,      0},
47100         {"LFSR"                        ,        0,      16,     67,     "R/W",  0,      1,      65535ull,       0},
47101         {"RESERVED_16_63"              ,        16,     48,     67,     "RAZ",  1,      1,      0,      0},
47102         {"IGN_FULL"                    ,        0,      1,      68,     "R/W",  0,      0,      0ull,   0ull},
47103         {"RESERVED_1_3"                ,        1,      3,      68,     "RAZ",  0,      0,      0ull,   0ull},
47104         {"BP"                          ,        4,      1,      68,     "R/W",  0,      0,      0ull,   0ull},
47105         {"RESERVED_5_7"                ,        5,      3,      68,     "RAZ",  0,      0,      0ull,   0ull},
47106         {"EN"                          ,        8,      1,      68,     "R/W",  0,      0,      0ull,   0ull},
47107         {"RESERVED_9_63"               ,        9,      55,     68,     "RAZ",  0,      0,      0ull,   0ull},
47108         {"DMAC"                        ,        0,      48,     69,     "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
47109         {"RESERVED_48_63"              ,        48,     16,     69,     "RAZ",  1,      1,      0,      0},
47110         {"TYPE"                        ,        0,      16,     70,     "R/W",  0,      0,      34824ull,       34824ull},
47111         {"RESERVED_16_63"              ,        16,     48,     70,     "RAZ",  1,      1,      0,      0},
47112         {"BIST"                        ,        0,      4,      71,     "RO",   0,      0,      0ull,   0ull},
47113         {"RESERVED_4_63"               ,        4,      60,     71,     "RAZ",  1,      1,      0,      0},
47114         {"DINT"                        ,        0,      12,     72,     "WO",   0,      0,      0ull,   0ull},
47115         {"RESERVED_12_63"              ,        12,     52,     72,     "RAZ",  1,      1,      0,      0},
47116         {"FUSE"                        ,        0,      12,     73,     "RO",   1,      1,      0,      0},
47117         {"RESERVED_12_63"              ,        12,     52,     73,     "RAZ",  1,      1,      0,      0},
47118         {"GSTOP"                       ,        0,      1,      74,     "R/W",  0,      0,      0ull,   0ull},
47119         {"RESERVED_1_63"               ,        1,      63,     74,     "RAZ",  1,      1,      0,      0},
47120         {"WORKQ"                       ,        0,      16,     75,     "R/W",  0,      0,      0ull,   0ull},
47121         {"GPIO"                        ,        16,     16,     75,     "R/W",  0,      0,      0ull,   0ull},
47122         {"MBOX"                        ,        32,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
47123         {"UART"                        ,        34,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
47124         {"PCI_INT"                     ,        36,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
47125         {"PCI_MSI"                     ,        40,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
47126         {"RESERVED_44_44"              ,        44,     1,      75,     "RAZ",  1,      1,      0,      0},
47127         {"TWSI"                        ,        45,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47128         {"RML"                         ,        46,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47129         {"TRACE"                       ,        47,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47130         {"GMX_DRP"                     ,        48,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
47131         {"IPD_DRP"                     ,        50,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47132         {"KEY_ZERO"                    ,        51,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47133         {"TIMER"                       ,        52,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
47134         {"USB"                         ,        56,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47135         {"RESERVED_57_58"              ,        57,     2,      75,     "RAZ",  0,      0,      0ull,   0ull},
47136         {"TWSI2"                       ,        59,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47137         {"POWIQ"                       ,        60,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47138         {"IPDPPTHR"                    ,        61,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47139         {"MII"                         ,        62,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47140         {"BOOTDMA"                     ,        63,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
47141         {"WORKQ"                       ,        0,      16,     76,     "R/W1C",        0,      0,      0ull,   0ull},
47142         {"GPIO"                        ,        16,     16,     76,     "R/W1C",        0,      0,      0ull,   0ull},
47143         {"MBOX"                        ,        32,     2,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47144         {"UART"                        ,        34,     2,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47145         {"PCI_INT"                     ,        36,     4,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47146         {"PCI_MSI"                     ,        40,     4,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47147         {"RESERVED_44_44"              ,        44,     1,      76,     "RAZ",  1,      1,      0,      0},
47148         {"TWSI"                        ,        45,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47149         {"RML"                         ,        46,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47150         {"TRACE"                       ,        47,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47151         {"GMX_DRP"                     ,        48,     2,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47152         {"IPD_DRP"                     ,        50,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47153         {"KEY_ZERO"                    ,        51,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47154         {"TIMER"                       ,        52,     4,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47155         {"USB"                         ,        56,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47156         {"RESERVED_57_58"              ,        57,     2,      76,     "RAZ",  0,      0,      0ull,   0ull},
47157         {"TWSI2"                       ,        59,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47158         {"POWIQ"                       ,        60,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47159         {"IPDPPTHR"                    ,        61,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47160         {"MII"                         ,        62,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47161         {"BOOTDMA"                     ,        63,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
47162         {"WORKQ"                       ,        0,      16,     77,     "R/W1", 0,      0,      0ull,   0ull},
47163         {"GPIO"                        ,        16,     16,     77,     "R/W1", 0,      0,      0ull,   0ull},
47164         {"MBOX"                        ,        32,     2,      77,     "R/W1", 0,      0,      0ull,   0ull},
47165         {"UART"                        ,        34,     2,      77,     "R/W1", 0,      0,      0ull,   0ull},
47166         {"PCI_INT"                     ,        36,     4,      77,     "R/W1", 0,      0,      0ull,   0ull},
47167         {"PCI_MSI"                     ,        40,     4,      77,     "R/W1", 0,      0,      0ull,   0ull},
47168         {"RESERVED_44_44"              ,        44,     1,      77,     "RAZ",  1,      1,      0,      0},
47169         {"TWSI"                        ,        45,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47170         {"RML"                         ,        46,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47171         {"TRACE"                       ,        47,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47172         {"GMX_DRP"                     ,        48,     2,      77,     "R/W1", 0,      0,      0ull,   0ull},
47173         {"IPD_DRP"                     ,        50,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47174         {"KEY_ZERO"                    ,        51,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47175         {"TIMER"                       ,        52,     4,      77,     "R/W1", 0,      0,      0ull,   0ull},
47176         {"USB"                         ,        56,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47177         {"RESERVED_57_58"              ,        57,     2,      77,     "RAZ",  0,      0,      0ull,   0ull},
47178         {"TWSI2"                       ,        59,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47179         {"POWIQ"                       ,        60,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47180         {"IPDPPTHR"                    ,        61,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47181         {"MII"                         ,        62,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47182         {"BOOTDMA"                     ,        63,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
47183         {"WDOG"                        ,        0,      12,     78,     "R/W",  0,      0,      0ull,   0ull},
47184         {"RESERVED_12_63"              ,        12,     52,     78,     "RAZ",  1,      1,      0,      0},
47185         {"WDOG"                        ,        0,      12,     79,     "R/W1C",        0,      0,      0ull,   0ull},
47186         {"RESERVED_12_63"              ,        12,     52,     79,     "RAZ",  1,      1,      0,      0},
47187         {"WDOG"                        ,        0,      12,     80,     "R/W1", 0,      0,      0ull,   0ull},
47188         {"RESERVED_12_63"              ,        12,     52,     80,     "RAZ",  1,      1,      0,      0},
47189         {"WORKQ"                       ,        0,      16,     81,     "R/W",  0,      0,      0ull,   0ull},
47190         {"GPIO"                        ,        16,     16,     81,     "R/W",  0,      0,      0ull,   0ull},
47191         {"MBOX"                        ,        32,     2,      81,     "R/W",  0,      0,      0ull,   0ull},
47192         {"UART"                        ,        34,     2,      81,     "R/W",  0,      0,      0ull,   0ull},
47193         {"PCI_INT"                     ,        36,     4,      81,     "R/W",  0,      0,      0ull,   0ull},
47194         {"PCI_MSI"                     ,        40,     4,      81,     "R/W",  0,      0,      0ull,   0ull},
47195         {"RESERVED_44_44"              ,        44,     1,      81,     "RAZ",  1,      1,      0,      0},
47196         {"TWSI"                        ,        45,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47197         {"RML"                         ,        46,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47198         {"TRACE"                       ,        47,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47199         {"GMX_DRP"                     ,        48,     2,      81,     "R/W",  0,      0,      0ull,   0ull},
47200         {"IPD_DRP"                     ,        50,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47201         {"KEY_ZERO"                    ,        51,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47202         {"TIMER"                       ,        52,     4,      81,     "R/W",  0,      0,      0ull,   0ull},
47203         {"USB"                         ,        56,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47204         {"RESERVED_57_58"              ,        57,     2,      81,     "RAZ",  0,      0,      0ull,   0ull},
47205         {"TWSI2"                       ,        59,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47206         {"POWIQ"                       ,        60,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47207         {"IPDPPTHR"                    ,        61,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47208         {"MII"                         ,        62,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47209         {"BOOTDMA"                     ,        63,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
47210         {"WORKQ"                       ,        0,      16,     82,     "R/W1C",        0,      0,      0ull,   0ull},
47211         {"GPIO"                        ,        16,     16,     82,     "R/W1C",        0,      0,      0ull,   0ull},
47212         {"MBOX"                        ,        32,     2,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47213         {"UART"                        ,        34,     2,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47214         {"PCI_INT"                     ,        36,     4,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47215         {"PCI_MSI"                     ,        40,     4,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47216         {"RESERVED_44_44"              ,        44,     1,      82,     "RAZ",  1,      1,      0,      0},
47217         {"TWSI"                        ,        45,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47218         {"RML"                         ,        46,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47219         {"TRACE"                       ,        47,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47220         {"GMX_DRP"                     ,        48,     2,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47221         {"IPD_DRP"                     ,        50,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47222         {"KEY_ZERO"                    ,        51,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47223         {"TIMER"                       ,        52,     4,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47224         {"USB"                         ,        56,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47225         {"RESERVED_57_58"              ,        57,     2,      82,     "RAZ",  0,      0,      0ull,   0ull},
47226         {"TWSI2"                       ,        59,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47227         {"POWIQ"                       ,        60,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47228         {"IPDPPTHR"                    ,        61,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47229         {"MII"                         ,        62,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47230         {"BOOTDMA"                     ,        63,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
47231         {"WORKQ"                       ,        0,      16,     83,     "R/W1", 0,      0,      0ull,   0ull},
47232         {"GPIO"                        ,        16,     16,     83,     "R/W1", 0,      0,      0ull,   0ull},
47233         {"MBOX"                        ,        32,     2,      83,     "R/W1", 0,      0,      0ull,   0ull},
47234         {"UART"                        ,        34,     2,      83,     "R/W1", 0,      0,      0ull,   0ull},
47235         {"PCI_INT"                     ,        36,     4,      83,     "R/W1", 0,      0,      0ull,   0ull},
47236         {"PCI_MSI"                     ,        40,     4,      83,     "R/W1", 0,      0,      0ull,   0ull},
47237         {"RESERVED_44_44"              ,        44,     1,      83,     "RAZ",  1,      1,      0,      0},
47238         {"TWSI"                        ,        45,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47239         {"RML"                         ,        46,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47240         {"TRACE"                       ,        47,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47241         {"GMX_DRP"                     ,        48,     2,      83,     "R/W1", 0,      0,      0ull,   0ull},
47242         {"IPD_DRP"                     ,        50,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47243         {"KEY_ZERO"                    ,        51,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47244         {"TIMER"                       ,        52,     4,      83,     "R/W1", 0,      0,      0ull,   0ull},
47245         {"USB"                         ,        56,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47246         {"RESERVED_57_58"              ,        57,     2,      83,     "RAZ",  0,      0,      0ull,   0ull},
47247         {"TWSI2"                       ,        59,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47248         {"POWIQ"                       ,        60,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47249         {"IPDPPTHR"                    ,        61,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47250         {"MII"                         ,        62,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47251         {"BOOTDMA"                     ,        63,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
47252         {"WDOG"                        ,        0,      12,     84,     "R/W",  0,      0,      0ull,   0ull},
47253         {"RESERVED_12_63"              ,        12,     52,     84,     "RAZ",  1,      1,      0,      0},
47254         {"WDOG"                        ,        0,      12,     85,     "R/W1C",        0,      0,      0ull,   0ull},
47255         {"RESERVED_12_63"              ,        12,     52,     85,     "RAZ",  1,      1,      0,      0},
47256         {"WDOG"                        ,        0,      12,     86,     "R/W1", 0,      0,      0ull,   0ull},
47257         {"RESERVED_12_63"              ,        12,     52,     86,     "RAZ",  1,      1,      0,      0},
47258         {"WORKQ"                       ,        0,      16,     87,     "RO",   0,      0,      0ull,   0ull},
47259         {"GPIO"                        ,        16,     16,     87,     "RO",   0,      0,      0ull,   0ull},
47260         {"MBOX"                        ,        32,     2,      87,     "RO",   0,      0,      0ull,   0ull},
47261         {"UART"                        ,        34,     2,      87,     "RO",   0,      0,      0ull,   0ull},
47262         {"PCI_INT"                     ,        36,     4,      87,     "RO",   0,      0,      0ull,   0ull},
47263         {"PCI_MSI"                     ,        40,     4,      87,     "RO",   0,      0,      0ull,   0ull},
47264         {"WDOG_SUM"                    ,        44,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47265         {"TWSI"                        ,        45,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47266         {"RML"                         ,        46,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47267         {"TRACE"                       ,        47,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47268         {"GMX_DRP"                     ,        48,     2,      87,     "R/W1C",        0,      0,      0ull,   0ull},
47269         {"IPD_DRP"                     ,        50,     1,      87,     "R/W1C",        0,      0,      0ull,   0ull},
47270         {"KEY_ZERO"                    ,        51,     1,      87,     "R/W1C",        0,      0,      0ull,   0ull},
47271         {"TIMER"                       ,        52,     4,      87,     "R/W1C",        0,      0,      0ull,   0ull},
47272         {"USB"                         ,        56,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47273         {"RESERVED_57_58"              ,        57,     2,      87,     "RAZ",  0,      0,      0ull,   0ull},
47274         {"TWSI2"                       ,        59,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47275         {"POWIQ"                       ,        60,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47276         {"IPDPPTHR"                    ,        61,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47277         {"MII"                         ,        62,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47278         {"BOOTDMA"                     ,        63,     1,      87,     "RO",   0,      0,      0ull,   0ull},
47279         {"WORKQ"                       ,        0,      16,     88,     "RO",   0,      0,      0ull,   0ull},
47280         {"GPIO"                        ,        16,     16,     88,     "RO",   0,      0,      0ull,   0ull},
47281         {"MBOX"                        ,        32,     2,      88,     "RO",   0,      0,      0ull,   0ull},
47282         {"UART"                        ,        34,     2,      88,     "RO",   0,      0,      0ull,   0ull},
47283         {"PCI_INT"                     ,        36,     4,      88,     "RO",   0,      0,      0ull,   0ull},
47284         {"PCI_MSI"                     ,        40,     4,      88,     "RO",   0,      0,      0ull,   0ull},
47285         {"WDOG_SUM"                    ,        44,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47286         {"TWSI"                        ,        45,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47287         {"RML"                         ,        46,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47288         {"TRACE"                       ,        47,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47289         {"GMX_DRP"                     ,        48,     2,      88,     "R/W1C",        0,      0,      0ull,   0ull},
47290         {"IPD_DRP"                     ,        50,     1,      88,     "R/W1C",        0,      0,      0ull,   0ull},
47291         {"KEY_ZERO"                    ,        51,     1,      88,     "R/W1C",        0,      0,      0ull,   0ull},
47292         {"TIMER"                       ,        52,     4,      88,     "R/W1C",        0,      0,      0ull,   0ull},
47293         {"USB"                         ,        56,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47294         {"RESERVED_57_58"              ,        57,     2,      88,     "RAZ",  0,      0,      0ull,   0ull},
47295         {"TWSI2"                       ,        59,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47296         {"POWIQ"                       ,        60,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47297         {"IPDPPTHR"                    ,        61,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47298         {"MII"                         ,        62,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47299         {"BOOTDMA"                     ,        63,     1,      88,     "RO",   0,      0,      0ull,   0ull},
47300         {"WDOG"                        ,        0,      12,     89,     "RO",   0,      0,      0ull,   0ull},
47301         {"RESERVED_12_63"              ,        12,     52,     89,     "RAZ",  1,      1,      0,      0},
47302         {"BITS"                        ,        0,      32,     90,     "R/W1C",        0,      0,      0ull,   0ull},
47303         {"RESERVED_32_63"              ,        32,     32,     90,     "RAZ",  1,      1,      0,      0},
47304         {"BITS"                        ,        0,      32,     91,     "R/W1", 0,      0,      0ull,   0ull},
47305         {"RESERVED_32_63"              ,        32,     32,     91,     "RAZ",  1,      1,      0,      0},
47306         {"NMI"                         ,        0,      12,     92,     "WO",   0,      0,      0ull,   0ull},
47307         {"RESERVED_12_63"              ,        12,     52,     92,     "RAZ",  1,      1,      0,      0},
47308         {"INTR"                        ,        0,      2,      93,     "R/W",  0,      0,      0ull,   0ull},
47309         {"RESERVED_2_63"               ,        2,      62,     93,     "RAZ",  1,      1,      0,      0},
47310         {"PPDBG"                       ,        0,      12,     94,     "RO",   0,      0,      0ull,   0ull},
47311         {"RESERVED_12_63"              ,        12,     52,     94,     "RAZ",  1,      1,      0,      0},
47312         {"POKE"                        ,        0,      64,     95,     "RAZ",  1,      1,      0,      0},
47313         {"RST0"                        ,        0,      1,      96,     "R/W",  1,      1,      0,      0},
47314         {"RST"                         ,        1,      11,     96,     "R/W",  0,      0,      32767ull,       0ull},
47315         {"RESERVED_12_63"              ,        12,     52,     96,     "RAZ",  1,      1,      0,      0},
47316         {"QLM_DCOK"                    ,        0,      4,      97,     "R/W",  0,      0,      1ull,   1ull},
47317         {"RESERVED_4_63"               ,        4,      60,     97,     "RAZ",  1,      1,      0,      0},
47318         {"BYPASS"                      ,        0,      4,      98,     "R/W",  0,      1,      0ull,   0},
47319         {"MUX_SEL"                     ,        4,      2,      98,     "R/W",  0,      1,      0ull,   0},
47320         {"RESERVED_6_7"                ,        6,      2,      98,     "RAZ",  1,      1,      0,      0},
47321         {"CLK_DIV"                     ,        8,      3,      98,     "R/W",  0,      1,      0ull,   0},
47322         {"RESERVED_11_63"              ,        11,     53,     98,     "RAZ",  1,      1,      0,      0},
47323         {"SHFT_REG"                    ,        0,      32,     99,     "R/W",  0,      1,      0ull,   0},
47324         {"SHFT_CNT"                    ,        32,     5,      99,     "R/W",  0,      1,      0ull,   0},
47325         {"RESERVED_37_39"              ,        37,     3,      99,     "RAZ",  1,      1,      0,      0},
47326         {"SELECT"                      ,        40,     4,      99,     "R/W",  0,      1,      0ull,   0},
47327         {"RESERVED_44_60"              ,        44,     17,     99,     "RAZ",  1,      1,      0,      0},
47328         {"UPDATE"                      ,        61,     1,      99,     "R/W",  0,      1,      0ull,   0},
47329         {"SHIFT"                       ,        62,     1,      99,     "R/W",  0,      1,      0ull,   0},
47330         {"CAPTURE"                     ,        63,     1,      99,     "R/W",  0,      1,      0ull,   0},
47331         {"SOFT_BIST"                   ,        0,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
47332         {"RESERVED_1_63"               ,        1,      63,     100,    "RAZ",  1,      1,      0,      0},
47333         {"SOFT_PRST"                   ,        0,      1,      101,    "R/W",  0,      0,      1ull,   0ull},
47334         {"RESERVED_1_63"               ,        1,      63,     101,    "RAZ",  1,      1,      0,      0},
47335         {"SOFT_PRST"                   ,        0,      1,      102,    "R/W",  0,      0,      1ull,   0ull},
47336         {"RESERVED_1_63"               ,        1,      63,     102,    "RAZ",  1,      1,      0,      0},
47337         {"SOFT_RST"                    ,        0,      1,      103,    "WO",   0,      0,      0ull,   0ull},
47338         {"RESERVED_1_63"               ,        1,      63,     103,    "RAZ",  1,      1,      0,      0},
47339         {"LEN"                         ,        0,      36,     104,    "R/W",  0,      0,      0ull,   0ull},
47340         {"ONE_SHOT"                    ,        36,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
47341         {"RESERVED_37_63"              ,        37,     27,     104,    "RAZ",  1,      1,      0,      0},
47342         {"MODE"                        ,        0,      2,      105,    "R/W",  0,      0,      0ull,   0ull},
47343         {"STATE"                       ,        2,      2,      105,    "RO",   0,      0,      0ull,   0ull},
47344         {"LEN"                         ,        4,      16,     105,    "R/W",  0,      0,      0ull,   0ull},
47345         {"CNT"                         ,        20,     24,     105,    "RO",   0,      0,      0ull,   0ull},
47346         {"DSTOP"                       ,        44,     1,      105,    "R/W",  0,      0,      0ull,   0ull},
47347         {"GSTOPEN"                     ,        45,     1,      105,    "R/W",  0,      0,      0ull,   0ull},
47348         {"RESERVED_46_63"              ,        46,     18,     105,    "RAZ",  1,      1,      0,      0},
47349         {"FDR"                         ,        0,      1,      106,    "RO",   0,      0,      0ull,   0ull},
47350         {"FFR"                         ,        1,      1,      106,    "RO",   0,      0,      0ull,   0ull},
47351         {"FPF1"                        ,        2,      1,      106,    "RO",   0,      0,      0ull,   0ull},
47352         {"FPF0"                        ,        3,      1,      106,    "RO",   0,      0,      0ull,   0ull},
47353         {"FRD"                         ,        4,      1,      106,    "RO",   0,      0,      0ull,   0ull},
47354         {"RESERVED_5_63"               ,        5,      59,     106,    "RAZ",  1,      1,      0,      0},
47355         {"MEM0_ERR"                    ,        0,      7,      107,    "R/W",  0,      0,      0ull,   0ull},
47356         {"MEM1_ERR"                    ,        7,      7,      107,    "R/W",  0,      0,      0ull,   0ull},
47357         {"ENB"                         ,        14,     1,      107,    "R/W",  0,      0,      0ull,   0ull},
47358         {"USE_STT"                     ,        15,     1,      107,    "R/W",  0,      0,      0ull,   0ull},
47359         {"USE_LDT"                     ,        16,     1,      107,    "R/W",  0,      0,      0ull,   0ull},
47360         {"RESET"                       ,        17,     1,      107,    "R/W",  0,      0,      0ull,   0ull},
47361         {"RESERVED_18_63"              ,        18,     46,     107,    "RAZ",  1,      1,      0,      0},
47362         {"FPF_RD"                      ,        0,      11,     108,    "R/W",  0,      0,      64ull,  0ull},
47363         {"FPF_WR"                      ,        11,     11,     108,    "R/W",  0,      0,      196ull, 0ull},
47364         {"RESERVED_22_63"              ,        22,     42,     108,    "RAZ",  1,      1,      0,      0},
47365         {"FPF_SIZ"                     ,        0,      11,     109,    "R/W",  0,      0,      256ull, 0ull},
47366         {"RESERVED_11_63"              ,        11,     53,     109,    "RAZ",  1,      1,      0,      0},
47367         {"FPF_RD"                      ,        0,      12,     110,    "R/W",  0,      0,      64ull,  0ull},
47368         {"FPF_WR"                      ,        12,     12,     110,    "R/W",  0,      0,      196ull, 0ull},
47369         {"RESERVED_24_63"              ,        24,     40,     110,    "RAZ",  1,      1,      0,      0},
47370         {"FPF_SIZ"                     ,        0,      12,     111,    "R/W",  0,      0,      256ull, 0ull},
47371         {"RESERVED_12_63"              ,        12,     52,     111,    "RAZ",  1,      1,      0,      0},
47372         {"FED0_SBE"                    ,        0,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47373         {"FED0_DBE"                    ,        1,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47374         {"FED1_SBE"                    ,        2,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47375         {"FED1_DBE"                    ,        3,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47376         {"Q0_UND"                      ,        4,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47377         {"Q0_COFF"                     ,        5,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47378         {"Q0_PERR"                     ,        6,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47379         {"Q1_UND"                      ,        7,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47380         {"Q1_COFF"                     ,        8,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47381         {"Q1_PERR"                     ,        9,      1,      112,    "R/W",  0,      0,      0ull,   0ull},
47382         {"Q2_UND"                      ,        10,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47383         {"Q2_COFF"                     ,        11,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47384         {"Q2_PERR"                     ,        12,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47385         {"Q3_UND"                      ,        13,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47386         {"Q3_COFF"                     ,        14,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47387         {"Q3_PERR"                     ,        15,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47388         {"Q4_UND"                      ,        16,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47389         {"Q4_COFF"                     ,        17,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47390         {"Q4_PERR"                     ,        18,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47391         {"Q5_UND"                      ,        19,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47392         {"Q5_COFF"                     ,        20,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47393         {"Q5_PERR"                     ,        21,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47394         {"Q6_UND"                      ,        22,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47395         {"Q6_COFF"                     ,        23,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47396         {"Q6_PERR"                     ,        24,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47397         {"Q7_UND"                      ,        25,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47398         {"Q7_COFF"                     ,        26,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47399         {"Q7_PERR"                     ,        27,     1,      112,    "R/W",  0,      0,      0ull,   0ull},
47400         {"RESERVED_28_63"              ,        28,     36,     112,    "RAZ",  1,      1,      0,      0},
47401         {"FED0_SBE"                    ,        0,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47402         {"FED0_DBE"                    ,        1,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47403         {"FED1_SBE"                    ,        2,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47404         {"FED1_DBE"                    ,        3,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47405         {"Q0_UND"                      ,        4,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47406         {"Q0_COFF"                     ,        5,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47407         {"Q0_PERR"                     ,        6,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47408         {"Q1_UND"                      ,        7,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47409         {"Q1_COFF"                     ,        8,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47410         {"Q1_PERR"                     ,        9,      1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47411         {"Q2_UND"                      ,        10,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47412         {"Q2_COFF"                     ,        11,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47413         {"Q2_PERR"                     ,        12,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47414         {"Q3_UND"                      ,        13,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47415         {"Q3_COFF"                     ,        14,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47416         {"Q3_PERR"                     ,        15,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47417         {"Q4_UND"                      ,        16,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47418         {"Q4_COFF"                     ,        17,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47419         {"Q4_PERR"                     ,        18,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47420         {"Q5_UND"                      ,        19,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47421         {"Q5_COFF"                     ,        20,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47422         {"Q5_PERR"                     ,        21,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47423         {"Q6_UND"                      ,        22,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47424         {"Q6_COFF"                     ,        23,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47425         {"Q6_PERR"                     ,        24,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47426         {"Q7_UND"                      ,        25,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47427         {"Q7_COFF"                     ,        26,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47428         {"Q7_PERR"                     ,        27,     1,      113,    "R/W1C",        0,      0,      0ull,   0ull},
47429         {"RESERVED_28_63"              ,        28,     36,     113,    "RAZ",  1,      1,      0,      0},
47430         {"QUE_SIZ"                     ,        0,      29,     114,    "RO",   0,      0,      0ull,   0ull},
47431         {"RESERVED_29_63"              ,        29,     35,     114,    "RAZ",  1,      1,      0,      0},
47432         {"PG_NUM"                      ,        0,      25,     115,    "RO",   0,      1,      0ull,   0},
47433         {"RESERVED_25_63"              ,        25,     39,     115,    "RAZ",  1,      1,      0,      0},
47434         {"ACT_INDX"                    ,        0,      26,     116,    "RO",   0,      1,      0ull,   0},
47435         {"ACT_QUE"                     ,        26,     3,      116,    "RO",   0,      1,      0ull,   0},
47436         {"RESERVED_29_63"              ,        29,     35,     116,    "RAZ",  0,      0,      0ull,   7ull},
47437         {"EXP_INDX"                    ,        0,      26,     117,    "RO",   0,      1,      0ull,   0},
47438         {"EXP_QUE"                     ,        26,     3,      117,    "RO",   0,      1,      0ull,   0},
47439         {"RESERVED_29_63"              ,        29,     35,     117,    "RAZ",  0,      0,      0ull,   7ull},
47440         {"CTL"                         ,        0,      16,     118,    "R/W",  1,      0,      0,      0ull},
47441         {"RESERVED_16_63"              ,        16,     48,     118,    "RAZ",  1,      1,      0,      0},
47442         {"STATUS"                      ,        0,      32,     119,    "RO",   0,      0,      0ull,   0ull},
47443         {"RESERVED_32_63"              ,        32,     32,     119,    "RAZ",  1,      1,      0,      0},
47444         {"RESERVED_0_1"                ,        0,      2,      120,    "RAZ",  1,      1,      0,      0},
47445         {"OUT_OVR"                     ,        2,      4,      120,    "R/W1C",        0,      0,      0ull,   0ull},
47446         {"RESERVED_6_21"               ,        6,      16,     120,    "RAZ",  1,      1,      0,      0},
47447         {"LOSTSTAT"                    ,        22,     4,      120,    "R/W1C",        0,      0,      0ull,   0ull},
47448         {"STATOVR"                     ,        26,     1,      120,    "R/W1C",        0,      0,      0ull,   0ull},
47449         {"INB_NXA"                     ,        27,     4,      120,    "R/W1C",        0,      0,      0ull,   0ull},
47450         {"RESERVED_31_63"              ,        31,     33,     120,    "RAZ",  1,      1,      0,      0},
47451         {"STATUS"                      ,        0,      16,     121,    "RO",   0,      0,      0ull,   0ull},
47452         {"RESERVED_16_63"              ,        16,     48,     121,    "RAZ",  1,      1,      0,      0},
47453         {"CLK_EN"                      ,        0,      1,      122,    "R/W",  0,      0,      0ull,   0ull},
47454         {"RESERVED_1_63"               ,        1,      63,     122,    "RAZ",  1,      1,      0,      0},
47455         {"LOGL_EN"                     ,        0,      16,     123,    "R/W",  0,      1,      65535ull,       0},
47456         {"PHYS_EN"                     ,        16,     1,      123,    "R/W",  0,      1,      1ull,   0},
47457         {"HG2RX_EN"                    ,        17,     1,      123,    "R/W",  0,      0,      0ull,   0ull},
47458         {"HG2TX_EN"                    ,        18,     1,      123,    "R/W",  0,      0,      0ull,   0ull},
47459         {"RESERVED_19_63"              ,        19,     45,     123,    "RAZ",  1,      1,      0,      0},
47460         {"TYPE"                        ,        0,      1,      124,    "RO",   0,      1,      0ull,   0},
47461         {"EN"                          ,        1,      1,      124,    "R/W",  0,      1,      0ull,   0},
47462         {"RESERVED_2_3"                ,        2,      2,      124,    "RAZ",  1,      1,      0,      0},
47463         {"MODE"                        ,        4,      2,      124,    "RO",   0,      1,      0ull,   0},
47464         {"RESERVED_6_7"                ,        6,      2,      124,    "RAZ",  1,      1,      0,      0},
47465         {"SPEED"                       ,        8,      2,      124,    "RO",   1,      1,      0,      0},
47466         {"RESERVED_10_63"              ,        10,     54,     124,    "RAZ",  1,      1,      0,      0},
47467         {"PRT"                         ,        0,      6,      125,    "RO",   0,      1,      0ull,   0},
47468         {"RESERVED_6_63"               ,        6,      58,     125,    "RAZ",  1,      1,      0,      0},
47469         {"RX_EN"                       ,        0,      1,      126,    "R/W",  0,      0,      0ull,   0ull},
47470         {"TX_EN"                       ,        1,      1,      126,    "R/W",  0,      0,      0ull,   0ull},
47471         {"DRP_EN"                      ,        2,      1,      126,    "R/W",  0,      0,      0ull,   0ull},
47472         {"BCK_EN"                      ,        3,      1,      126,    "R/W",  0,      0,      0ull,   0ull},
47473         {"RESERVED_4_15"               ,        4,      12,     126,    "RAZ",  1,      1,      0,      0},
47474         {"PHYS_BP"                     ,        16,     16,     126,    "R/W",  0,      1,      0ull,   0},
47475         {"LOGL_EN"                     ,        32,     16,     126,    "R/W",  0,      0,      255ull, 255ull},
47476         {"PHYS_EN"                     ,        48,     16,     126,    "R/W",  0,      0,      255ull, 255ull},
47477         {"EN"                          ,        0,      1,      127,    "R/W",  0,      1,      0ull,   0},
47478         {"SPEED"                       ,        1,      1,      127,    "R/W",  0,      1,      1ull,   0},
47479         {"DUPLEX"                      ,        2,      1,      127,    "R/W",  0,      1,      1ull,   0},
47480         {"SLOTTIME"                    ,        3,      1,      127,    "R/W",  0,      1,      1ull,   0},
47481         {"RESERVED_4_7"                ,        4,      4,      127,    "RAZ",  1,      1,      0,      0},
47482         {"SPEED_MSB"                   ,        8,      1,      127,    "R/W",  0,      1,      0ull,   0},
47483         {"RESERVED_9_11"               ,        9,      3,      127,    "RAZ",  1,      1,      0,      0},
47484         {"RX_IDLE"                     ,        12,     1,      127,    "RO",   0,      1,      1ull,   0},
47485         {"TX_IDLE"                     ,        13,     1,      127,    "RO",   0,      1,      1ull,   0},
47486         {"RESERVED_14_63"              ,        14,     50,     127,    "RAZ",  1,      1,      0,      0},
47487         {"ADR"                         ,        0,      64,     128,    "R/W",  0,      1,      0ull,   0},
47488         {"ADR"                         ,        0,      64,     129,    "R/W",  0,      1,      0ull,   0},
47489         {"ADR"                         ,        0,      64,     130,    "R/W",  0,      1,      0ull,   0},
47490         {"ADR"                         ,        0,      64,     131,    "R/W",  0,      1,      0ull,   0},
47491         {"ADR"                         ,        0,      64,     132,    "R/W",  0,      1,      0ull,   0},
47492         {"ADR"                         ,        0,      64,     133,    "R/W",  0,      1,      0ull,   0},
47493         {"EN"                          ,        0,      8,      134,    "R/W",  0,      1,      0ull,   0},
47494         {"RESERVED_8_63"               ,        8,      56,     134,    "RAZ",  1,      1,      0,      0},
47495         {"BCST"                        ,        0,      1,      135,    "R/W",  0,      1,      1ull,   0},
47496         {"MCST"                        ,        1,      2,      135,    "R/W",  0,      1,      0ull,   0},
47497         {"CAM_MODE"                    ,        3,      1,      135,    "R/W",  0,      1,      0ull,   0},
47498         {"RESERVED_4_63"               ,        4,      60,     135,    "RAZ",  1,      1,      0,      0},
47499         {"CNT"                         ,        0,      5,      136,    "R/W",  0,      0,      24ull,  24ull},
47500         {"RESERVED_5_63"               ,        5,      59,     136,    "RAZ",  1,      1,      0,      0},
47501         {"RESERVED_0_0"                ,        0,      1,      137,    "RAZ",  1,      1,      0,      0},
47502         {"CAREXT"                      ,        1,      1,      137,    "R/W",  0,      0,      1ull,   1ull},
47503         {"RESERVED_2_2"                ,        2,      1,      137,    "RAZ",  1,      1,      0,      0},
47504         {"JABBER"                      ,        3,      1,      137,    "R/W",  0,      0,      1ull,   1ull},
47505         {"FCSERR"                      ,        4,      1,      137,    "R/W",  0,      0,      1ull,   1ull},
47506         {"RESERVED_5_6"                ,        5,      2,      137,    "RAZ",  1,      1,      0,      0},
47507         {"RCVERR"                      ,        7,      1,      137,    "R/W",  0,      0,      1ull,   1ull},
47508         {"SKPERR"                      ,        8,      1,      137,    "R/W",  0,      0,      1ull,   1ull},
47509         {"RESERVED_9_63"               ,        9,      55,     137,    "RAZ",  1,      1,      0,      0},
47510         {"PRE_CHK"                     ,        0,      1,      138,    "R/W",  0,      0,      1ull,   1ull},
47511         {"PRE_STRP"                    ,        1,      1,      138,    "R/W",  0,      0,      1ull,   1ull},
47512         {"CTL_DRP"                     ,        2,      1,      138,    "R/W",  0,      0,      1ull,   1ull},
47513         {"CTL_BCK"                     ,        3,      1,      138,    "R/W",  0,      0,      1ull,   1ull},
47514         {"CTL_MCST"                    ,        4,      1,      138,    "R/W",  0,      0,      1ull,   1ull},
47515         {"CTL_SMAC"                    ,        5,      1,      138,    "R/W",  0,      0,      0ull,   0ull},
47516         {"PRE_FREE"                    ,        6,      1,      138,    "RO",   0,      0,      1ull,   1ull},
47517         {"RESERVED_7_8"                ,        7,      2,      138,    "RAZ",  1,      1,      0,      0},
47518         {"PRE_ALIGN"                   ,        9,      1,      138,    "R/W",  0,      0,      0ull,   0ull},
47519         {"NULL_DIS"                    ,        10,     1,      138,    "R/W",  0,      0,      0ull,   0ull},
47520         {"RESERVED_11_63"              ,        11,     53,     138,    "RAZ",  1,      1,      0,      0},
47521         {"IFG"                         ,        0,      4,      139,    "R/W",  0,      0,      8ull,   8ull},
47522         {"RESERVED_4_63"               ,        4,      60,     139,    "RAZ",  1,      1,      0,      0},
47523         {"RESERVED_0_0"                ,        0,      1,      140,    "RAZ",  1,      1,      0,      0},
47524         {"CAREXT"                      ,        1,      1,      140,    "R/W",  0,      0,      0ull,   0ull},
47525         {"RESERVED_2_2"                ,        2,      1,      140,    "RAZ",  1,      1,      0,      0},
47526         {"JABBER"                      ,        3,      1,      140,    "R/W",  0,      0,      0ull,   0ull},
47527         {"FCSERR"                      ,        4,      1,      140,    "R/W",  0,      0,      0ull,   0ull},
47528         {"RESERVED_5_6"                ,        5,      2,      140,    "RAZ",  1,      1,      0,      0},
47529         {"RCVERR"                      ,        7,      1,      140,    "R/W",  0,      0,      0ull,   0ull},
47530         {"SKPERR"                      ,        8,      1,      140,    "R/W",  0,      0,      0ull,   0ull},
47531         {"RESERVED_9_9"                ,        9,      1,      140,    "RAZ",  1,      1,      0,      0},
47532         {"OVRERR"                      ,        10,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47533         {"PCTERR"                      ,        11,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47534         {"RSVERR"                      ,        12,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47535         {"FALERR"                      ,        13,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47536         {"COLDET"                      ,        14,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47537         {"IFGERR"                      ,        15,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47538         {"RESERVED_16_18"              ,        16,     3,      140,    "RAZ",  1,      1,      0,      0},
47539         {"PAUSE_DRP"                   ,        19,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47540         {"LOC_FAULT"                   ,        20,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47541         {"REM_FAULT"                   ,        21,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47542         {"BAD_SEQ"                     ,        22,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47543         {"BAD_TERM"                    ,        23,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47544         {"UNSOP"                       ,        24,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47545         {"UNEOP"                       ,        25,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47546         {"UNDAT"                       ,        26,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47547         {"HG2FLD"                      ,        27,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47548         {"HG2CC"                       ,        28,     1,      140,    "R/W",  0,      0,      0ull,   0ull},
47549         {"RESERVED_29_63"              ,        29,     35,     140,    "RAZ",  1,      1,      0,      0},
47550         {"RESERVED_0_0"                ,        0,      1,      141,    "RAZ",  1,      1,      0,      0},
47551         {"CAREXT"                      ,        1,      1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47552         {"RESERVED_2_2"                ,        2,      1,      141,    "RAZ",  1,      1,      0,      0},
47553         {"JABBER"                      ,        3,      1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47554         {"FCSERR"                      ,        4,      1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47555         {"RESERVED_5_6"                ,        5,      2,      141,    "RAZ",  1,      1,      0,      0},
47556         {"RCVERR"                      ,        7,      1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47557         {"SKPERR"                      ,        8,      1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47558         {"RESERVED_9_9"                ,        9,      1,      141,    "RAZ",  1,      1,      0,      0},
47559         {"OVRERR"                      ,        10,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47560         {"PCTERR"                      ,        11,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47561         {"RSVERR"                      ,        12,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47562         {"FALERR"                      ,        13,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47563         {"COLDET"                      ,        14,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47564         {"IFGERR"                      ,        15,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47565         {"RESERVED_16_18"              ,        16,     3,      141,    "RAZ",  1,      1,      0,      0},
47566         {"PAUSE_DRP"                   ,        19,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47567         {"LOC_FAULT"                   ,        20,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47568         {"REM_FAULT"                   ,        21,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47569         {"BAD_SEQ"                     ,        22,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47570         {"BAD_TERM"                    ,        23,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47571         {"UNSOP"                       ,        24,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47572         {"UNEOP"                       ,        25,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47573         {"UNDAT"                       ,        26,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47574         {"HG2FLD"                      ,        27,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47575         {"HG2CC"                       ,        28,     1,      141,    "R/W1C",        0,      0,      0ull,   0ull},
47576         {"RESERVED_29_63"              ,        29,     35,     141,    "RAZ",  1,      1,      0,      0},
47577         {"CNT"                         ,        0,      16,     142,    "R/W",  0,      0,      10240ull,       10240ull},
47578         {"RESERVED_16_63"              ,        16,     48,     142,    "RAZ",  1,      1,      0,      0},
47579         {"STATUS"                      ,        0,      16,     143,    "R/W1C",        0,      1,      0ull,   0},
47580         {"RESERVED_16_63"              ,        16,     48,     143,    "RAZ",  1,      1,      0,      0},
47581         {"RD_CLR"                      ,        0,      1,      144,    "R/W",  0,      0,      0ull,   0ull},
47582         {"RESERVED_1_63"               ,        1,      63,     144,    "RAZ",  1,      1,      0,      0},
47583         {"CNT"                         ,        0,      48,     145,    "RC/W", 0,      1,      0ull,   0},
47584         {"RESERVED_48_63"              ,        48,     16,     145,    "RAZ",  1,      1,      0,      0},
47585         {"CNT"                         ,        0,      48,     146,    "RC/W", 0,      1,      0ull,   0},
47586         {"RESERVED_48_63"              ,        48,     16,     146,    "RAZ",  1,      1,      0,      0},
47587         {"CNT"                         ,        0,      48,     147,    "RC/W", 0,      1,      0ull,   0},
47588         {"RESERVED_48_63"              ,        48,     16,     147,    "RAZ",  1,      1,      0,      0},
47589         {"CNT"                         ,        0,      48,     148,    "RC/W", 0,      1,      0ull,   0},
47590         {"RESERVED_48_63"              ,        48,     16,     148,    "RAZ",  1,      1,      0,      0},
47591         {"CNT"                         ,        0,      32,     149,    "RC/W", 0,      1,      0ull,   0},
47592         {"RESERVED_32_63"              ,        32,     32,     149,    "RAZ",  1,      1,      0,      0},
47593         {"CNT"                         ,        0,      32,     150,    "RC/W", 0,      1,      0ull,   0},
47594         {"RESERVED_32_63"              ,        32,     32,     150,    "RAZ",  1,      1,      0,      0},
47595         {"CNT"                         ,        0,      32,     151,    "RC/W", 0,      1,      0ull,   0},
47596         {"RESERVED_32_63"              ,        32,     32,     151,    "RAZ",  1,      1,      0,      0},
47597         {"CNT"                         ,        0,      32,     152,    "RC/W", 0,      1,      0ull,   0},
47598         {"RESERVED_32_63"              ,        32,     32,     152,    "RAZ",  1,      1,      0,      0},
47599         {"CNT"                         ,        0,      32,     153,    "RC/W", 0,      1,      0ull,   0},
47600         {"RESERVED_32_63"              ,        32,     32,     153,    "RAZ",  1,      1,      0,      0},
47601         {"LEN"                         ,        0,      7,      154,    "R/W",  0,      0,      0ull,   0ull},
47602         {"RESERVED_7_7"                ,        7,      1,      154,    "RAZ",  1,      1,      0,      0},
47603         {"FCSSEL"                      ,        8,      1,      154,    "R/W",  0,      0,      0ull,   0ull},
47604         {"RESERVED_9_63"               ,        9,      55,     154,    "RAZ",  1,      1,      0,      0},
47605         {"MARK"                        ,        0,      6,      155,    "R/W",  0,      0,      2ull,   2ull},
47606         {"RESERVED_6_63"               ,        6,      58,     155,    "RAZ",  1,      1,      0,      0},
47607         {"MARK"                        ,        0,      6,      156,    "R/W",  0,      0,      16ull,  16ull},
47608         {"RESERVED_6_63"               ,        6,      58,     156,    "RAZ",  1,      1,      0,      0},
47609         {"MARK"                        ,        0,      9,      157,    "R/W",  0,      0,      64ull,  64ull},
47610         {"RESERVED_9_63"               ,        9,      55,     157,    "RAZ",  1,      1,      0,      0},
47611         {"LGTIM2GO"                    ,        0,      16,     158,    "RO",   0,      1,      0ull,   0},
47612         {"XOF"                         ,        16,     16,     158,    "RO",   0,      0,      0ull,   0ull},
47613         {"PHTIM2GO"                    ,        32,     16,     158,    "RO",   0,      1,      0ull,   0},
47614         {"RESERVED_48_63"              ,        48,     16,     158,    "RAZ",  1,      1,      0,      0},
47615         {"COMMIT"                      ,        0,      4,      159,    "RO",   0,      0,      0ull,   0ull},
47616         {"RESERVED_4_15"               ,        4,      12,     159,    "RAZ",  1,      1,      0,      0},
47617         {"DROP"                        ,        16,     4,      159,    "RO",   0,      0,      0ull,   0ull},
47618         {"RESERVED_20_63"              ,        20,     44,     159,    "RAZ",  1,      1,      0,      0},
47619         {"PRTS"                        ,        0,      3,      160,    "R/W",  0,      0,      4ull,   4ull},
47620         {"RESERVED_3_63"               ,        3,      61,     160,    "RAZ",  1,      1,      0,      0},
47621         {"LANE_RXD"                    ,        0,      32,     161,    "RO",   0,      1,      0ull,   0},
47622         {"LANE_RXC"                    ,        32,     4,      161,    "RO",   0,      1,      0ull,   0},
47623         {"STATE"                       ,        36,     3,      161,    "RO",   0,      1,      0ull,   0},
47624         {"VAL"                         ,        39,     1,      161,    "R/W1C",        0,      1,      0ull,   0},
47625         {"RESERVED_40_63"              ,        40,     24,     161,    "RAZ",  1,      1,      0,      0},
47626         {"STATUS"                      ,        0,      2,      162,    "RO",   0,      0,      0ull,   0ull},
47627         {"RESERVED_2_63"               ,        2,      62,     162,    "RAZ",  1,      1,      0,      0},
47628         {"SMAC"                        ,        0,      48,     163,    "R/W",  0,      1,      0ull,   0},
47629         {"RESERVED_48_63"              ,        48,     16,     163,    "RAZ",  1,      1,      0,      0},
47630         {"CNT"                         ,        0,      16,     164,    "R/W1C",        0,      0,      0ull,   0ull},
47631         {"BP"                          ,        16,     1,      164,    "RO",   0,      0,      0ull,   0ull},
47632         {"RESERVED_17_63"              ,        17,     47,     164,    "RAZ",  1,      1,      0,      0},
47633         {"PREAMBLE"                    ,        0,      1,      165,    "R/W",  0,      0,      1ull,   1ull},
47634         {"PAD"                         ,        1,      1,      165,    "R/W",  0,      0,      1ull,   1ull},
47635         {"FCS"                         ,        2,      1,      165,    "R/W",  0,      0,      1ull,   1ull},
47636         {"FORCE_FCS"                   ,        3,      1,      165,    "R/W",  0,      0,      1ull,   1ull},
47637         {"RESERVED_4_63"               ,        4,      60,     165,    "RAZ",  1,      1,      0,      0},
47638         {"BURST"                       ,        0,      16,     166,    "R/W",  0,      0,      8192ull,        8192ull},
47639         {"RESERVED_16_63"              ,        16,     48,     166,    "RAZ",  1,      1,      0,      0},
47640         {"XOFF"                        ,        0,      16,     167,    "R/W1", 0,      0,      0ull,   0ull},
47641         {"RESERVED_16_63"              ,        16,     48,     167,    "RAZ",  1,      1,      0,      0},
47642         {"XON"                         ,        0,      16,     168,    "R/W1C",        0,      0,      0ull,   0ull},
47643         {"RESERVED_16_63"              ,        16,     48,     168,    "RAZ",  1,      1,      0,      0},
47644         {"XSCOL_EN"                    ,        0,      1,      169,    "R/W",  0,      0,      1ull,   1ull},
47645         {"XSDEF_EN"                    ,        1,      1,      169,    "R/W",  0,      0,      1ull,   1ull},
47646         {"RESERVED_2_63"               ,        2,      62,     169,    "RAZ",  1,      1,      0,      0},
47647         {"MIN_SIZE"                    ,        0,      8,      170,    "R/W",  0,      0,      59ull,  59ull},
47648         {"RESERVED_8_63"               ,        8,      56,     170,    "RAZ",  1,      1,      0,      0},
47649         {"INTERVAL"                    ,        0,      16,     171,    "R/W",  0,      1,      16ull,  0},
47650         {"RESERVED_16_63"              ,        16,     48,     171,    "RAZ",  1,      1,      0,      0},
47651         {"TIME"                        ,        0,      16,     172,    "R/W",  0,      1,      96ull,  0},
47652         {"RESERVED_16_63"              ,        16,     48,     172,    "RAZ",  1,      1,      0,      0},
47653         {"TIME"                        ,        0,      16,     173,    "RO",   1,      1,      0,      0},
47654         {"MSG_TIME"                    ,        16,     16,     173,    "RO",   1,      1,      0,      0},
47655         {"RESERVED_32_63"              ,        32,     32,     173,    "RAZ",  1,      1,      0,      0},
47656         {"SEND"                        ,        0,      1,      174,    "R/W",  0,      0,      1ull,   1ull},
47657         {"RESERVED_1_63"               ,        1,      63,     174,    "RAZ",  1,      1,      0,      0},
47658         {"ALIGN"                       ,        0,      1,      175,    "R/W",  0,      0,      1ull,   1ull},
47659         {"RESERVED_1_63"               ,        1,      63,     175,    "RAZ",  1,      1,      0,      0},
47660         {"SLOT"                        ,        0,      10,     176,    "R/W",  0,      0,      512ull, 512ull},
47661         {"RESERVED_10_63"              ,        10,     54,     176,    "RAZ",  1,      1,      0,      0},
47662         {"TIME"                        ,        0,      16,     177,    "R/W",  0,      1,      0ull,   0},
47663         {"RESERVED_16_63"              ,        16,     48,     177,    "RAZ",  1,      1,      0,      0},
47664         {"XSCOL"                       ,        0,      32,     178,    "RC/W", 0,      1,      0ull,   0},
47665         {"XSDEF"                       ,        32,     32,     178,    "RC/W", 0,      1,      0ull,   0},
47666         {"MCOL"                        ,        0,      32,     179,    "RC/W", 0,      1,      0ull,   0},
47667         {"SCOL"                        ,        32,     32,     179,    "RC/W", 0,      1,      0ull,   0},
47668         {"OCTS"                        ,        0,      48,     180,    "RC/W", 0,      1,      0ull,   0},
47669         {"RESERVED_48_63"              ,        48,     16,     180,    "RAZ",  1,      1,      0,      0},
47670         {"PKTS"                        ,        0,      32,     181,    "RC/W", 0,      1,      0ull,   0},
47671         {"RESERVED_32_63"              ,        32,     32,     181,    "RAZ",  1,      1,      0,      0},
47672         {"HIST0"                       ,        0,      32,     182,    "RC/W", 0,      1,      0ull,   0},
47673         {"HIST1"                       ,        32,     32,     182,    "RC/W", 0,      1,      0ull,   0},
47674         {"HIST2"                       ,        0,      32,     183,    "RC/W", 0,      1,      0ull,   0},
47675         {"HIST3"                       ,        32,     32,     183,    "RC/W", 0,      1,      0ull,   0},
47676         {"HIST4"                       ,        0,      32,     184,    "RC/W", 0,      1,      0ull,   0},
47677         {"HIST5"                       ,        32,     32,     184,    "RC/W", 0,      1,      0ull,   0},
47678         {"HIST6"                       ,        0,      32,     185,    "RC/W", 0,      1,      0ull,   0},
47679         {"HIST7"                       ,        32,     32,     185,    "RC/W", 0,      1,      0ull,   0},
47680         {"BCST"                        ,        0,      32,     186,    "RC/W", 0,      1,      0ull,   0},
47681         {"MCST"                        ,        32,     32,     186,    "RC/W", 0,      1,      0ull,   0},
47682         {"CTL"                         ,        0,      32,     187,    "RC/W", 0,      1,      0ull,   0},
47683         {"UNDFLW"                      ,        32,     32,     187,    "RC/W", 0,      1,      0ull,   0},
47684         {"RD_CLR"                      ,        0,      1,      188,    "R/W",  0,      0,      0ull,   0ull},
47685         {"RESERVED_1_63"               ,        1,      63,     188,    "RAZ",  1,      1,      0,      0},
47686         {"CNT"                         ,        0,      9,      189,    "R/W",  0,      0,      32ull,  32ull},
47687         {"RESERVED_9_63"               ,        9,      55,     189,    "RAZ",  1,      1,      0,      0},
47688         {"BP"                          ,        0,      4,      190,    "RO",   0,      0,      0ull,   0ull},
47689         {"RESERVED_4_63"               ,        4,      60,     190,    "RAZ",  1,      1,      0,      0},
47690         {"LIMIT"                       ,        0,      5,      191,    "R/W",  0,      0,      16ull,  16ull},
47691         {"RESERVED_5_63"               ,        5,      59,     191,    "RAZ",  1,      1,      0,      0},
47692         {"CORRUPT"                     ,        0,      4,      192,    "R/W",  0,      0,      15ull,  15ull},
47693         {"RESERVED_4_63"               ,        4,      60,     192,    "RAZ",  1,      1,      0,      0},
47694         {"TX_XOF"                      ,        0,      16,     193,    "R/W1", 0,      1,      0ull,   0},
47695         {"RESERVED_16_63"              ,        16,     48,     193,    "RAZ",  1,      1,      0,      0},
47696         {"TX_XON"                      ,        0,      16,     194,    "R/W1C",        0,      1,      0ull,   0},
47697         {"RESERVED_16_63"              ,        16,     48,     194,    "RAZ",  1,      1,      0,      0},
47698         {"IFG1"                        ,        0,      4,      195,    "R/W",  0,      1,      8ull,   0},
47699         {"IFG2"                        ,        4,      4,      195,    "R/W",  0,      1,      4ull,   0},
47700         {"RESERVED_8_63"               ,        8,      56,     195,    "RAZ",  1,      1,      0,      0},
47701         {"PKO_NXA"                     ,        0,      1,      196,    "R/W",  0,      0,      0ull,   0ull},
47702         {"RESERVED_1_1"                ,        1,      1,      196,    "RAZ",  0,      0,      0ull,   0ull},
47703         {"UNDFLW"                      ,        2,      4,      196,    "R/W",  0,      0,      0ull,   0ull},
47704         {"RESERVED_6_7"                ,        6,      2,      196,    "RAZ",  0,      0,      0ull,   0ull},
47705         {"XSCOL"                       ,        8,      4,      196,    "R/W",  0,      0,      0ull,   0ull},
47706         {"XSDEF"                       ,        12,     4,      196,    "R/W",  0,      0,      0ull,   0ull},
47707         {"LATE_COL"                    ,        16,     4,      196,    "R/W",  0,      0,      0ull,   0ull},
47708         {"RESERVED_20_63"              ,        20,     44,     196,    "RAZ",  1,      1,      0,      0},
47709         {"PKO_NXA"                     ,        0,      1,      197,    "R/W1C",        0,      0,      0ull,   0ull},
47710         {"RESERVED_1_1"                ,        1,      1,      197,    "RAZ",  0,      0,      0ull,   0ull},
47711         {"UNDFLW"                      ,        2,      4,      197,    "R/W1C",        0,      0,      0ull,   0ull},
47712         {"RESERVED_6_7"                ,        6,      2,      197,    "RAZ",  0,      0,      0ull,   0ull},
47713         {"XSCOL"                       ,        8,      4,      197,    "R/W1C",        0,      0,      0ull,   0ull},
47714         {"XSDEF"                       ,        12,     4,      197,    "R/W1C",        0,      0,      0ull,   0ull},
47715         {"LATE_COL"                    ,        16,     4,      197,    "R/W1C",        0,      0,      0ull,   0ull},
47716         {"RESERVED_20_63"              ,        20,     44,     197,    "RAZ",  1,      1,      0,      0},
47717         {"JAM"                         ,        0,      8,      198,    "R/W",  0,      1,      238ull, 0},
47718         {"RESERVED_8_63"               ,        8,      56,     198,    "RAZ",  1,      1,      0,      0},
47719         {"LFSR"                        ,        0,      16,     199,    "R/W",  0,      1,      65535ull,       0},
47720         {"RESERVED_16_63"              ,        16,     48,     199,    "RAZ",  1,      1,      0,      0},
47721         {"IGN_FULL"                    ,        0,      4,      200,    "R/W",  0,      0,      0ull,   0ull},
47722         {"BP"                          ,        4,      4,      200,    "R/W",  0,      0,      0ull,   0ull},
47723         {"EN"                          ,        8,      4,      200,    "R/W",  0,      0,      0ull,   0ull},
47724         {"RESERVED_12_31"              ,        12,     20,     200,    "RAZ",  1,      1,      0,      0},
47725         {"TX_PRT_BP"                   ,        32,     16,     200,    "R/W",  0,      0,      0ull,   0ull},
47726         {"RESERVED_48_63"              ,        48,     16,     200,    "RAZ",  1,      1,      0,      0},
47727         {"DMAC"                        ,        0,      48,     201,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
47728         {"RESERVED_48_63"              ,        48,     16,     201,    "RAZ",  1,      1,      0,      0},
47729         {"TYPE"                        ,        0,      16,     202,    "R/W",  0,      0,      34824ull,       34824ull},
47730         {"RESERVED_16_63"              ,        16,     48,     202,    "RAZ",  1,      1,      0,      0},
47731         {"PRTS"                        ,        0,      5,      203,    "R/W",  0,      1,      4ull,   0},
47732         {"RESERVED_5_63"               ,        5,      59,     203,    "RAZ",  1,      1,      0,      0},
47733         {"DIC_EN"                      ,        0,      1,      204,    "R/W",  0,      0,      0ull,   1ull},
47734         {"UNI_EN"                      ,        1,      1,      204,    "R/W",  0,      0,      0ull,   0ull},
47735         {"RESERVED_2_3"                ,        2,      2,      204,    "RAZ",  1,      1,      0,      0},
47736         {"LS"                          ,        4,      2,      204,    "R/W",  0,      0,      0ull,   0ull},
47737         {"LS_BYP"                      ,        6,      1,      204,    "R/W",  0,      0,      0ull,   0ull},
47738         {"RESERVED_7_7"                ,        7,      1,      204,    "RAZ",  1,      1,      0,      0},
47739         {"HG_EN"                       ,        8,      1,      204,    "R/W",  0,      0,      0ull,   0ull},
47740         {"HG_PAUSE_HGI"                ,        9,      2,      204,    "R/W",  0,      0,      2ull,   2ull},
47741         {"RESERVED_11_63"              ,        11,     53,     204,    "RAZ",  1,      1,      0,      0},
47742         {"THRESH"                      ,        0,      4,      205,    "R/W",  0,      0,      6ull,   6ull},
47743         {"EN"                          ,        4,      1,      205,    "R/W",  0,      0,      0ull,   0ull},
47744         {"RESERVED_5_63"               ,        5,      59,     205,    "RAZ",  1,      1,      0,      0},
47745         {"TX_OE"                       ,        0,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
47746         {"RX_XOR"                      ,        1,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
47747         {"INT_EN"                      ,        2,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
47748         {"INT_TYPE"                    ,        3,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
47749         {"FIL_CNT"                     ,        4,      4,      206,    "R/W",  0,      0,      0ull,   0ull},
47750         {"FIL_SEL"                     ,        8,      4,      206,    "R/W",  0,      0,      0ull,   0ull},
47751         {"CLK_SEL"                     ,        12,     2,      206,    "R/W",  0,      0,      0ull,   0ull},
47752         {"CLK_GEN"                     ,        14,     1,      206,    "R/W",  0,      0,      0ull,   0ull},
47753         {"RESERVED_15_63"              ,        15,     49,     206,    "RAZ",  1,      1,      0,      0},
47754         {"N"                           ,        0,      32,     207,    "R/W",  0,      1,      0ull,   0},
47755         {"RESERVED_32_63"              ,        32,     32,     207,    "RAZ",  1,      1,      0,      0},
47756         {"TYPE"                        ,        0,      16,     208,    "R/W1C",        0,      0,      0ull,   0ull},
47757         {"RESERVED_16_63"              ,        16,     48,     208,    "RAZ",  1,      1,      0,      0},
47758         {"DAT"                         ,        0,      16,     209,    "RO",   0,      0,      0ull,   0ull},
47759         {"RESERVED_16_63"              ,        16,     48,     209,    "RAZ",  1,      1,      0,      0},
47760         {"CLR"                         ,        0,      16,     210,    "R/W1C",        0,      0,      0ull,   0ull},
47761         {"RESERVED_16_63"              ,        16,     48,     210,    "RAZ",  1,      1,      0,      0},
47762         {"SET"                         ,        0,      16,     211,    "R/W1", 0,      0,      0ull,   0ull},
47763         {"RESERVED_16_63"              ,        16,     48,     211,    "RAZ",  1,      1,      0,      0},
47764         {"ICD"                         ,        0,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47765         {"IBD"                         ,        1,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47766         {"ICRP1"                       ,        2,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47767         {"ICRP0"                       ,        3,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47768         {"ICRN1"                       ,        4,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47769         {"ICRN0"                       ,        5,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47770         {"IBRQ1"                       ,        6,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47771         {"IBRQ0"                       ,        7,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47772         {"ICNRT"                       ,        8,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47773         {"IBR1"                        ,        9,      1,      212,    "RO",   0,      0,      0ull,   0ull},
47774         {"IBR0"                        ,        10,     1,      212,    "RO",   0,      0,      0ull,   0ull},
47775         {"IBDR1"                       ,        11,     1,      212,    "RO",   0,      0,      0ull,   0ull},
47776         {"IBDR0"                       ,        12,     1,      212,    "RO",   0,      0,      0ull,   0ull},
47777         {"ICNR0"                       ,        13,     1,      212,    "RO",   0,      0,      0ull,   0ull},
47778         {"ICNR1"                       ,        14,     1,      212,    "RO",   0,      0,      0ull,   0ull},
47779         {"ICR1"                        ,        15,     1,      212,    "RO",   0,      0,      0ull,   0ull},
47780         {"ICR0"                        ,        16,     1,      212,    "RO",   0,      0,      0ull,   0ull},
47781         {"ICNRCB"                      ,        17,     1,      212,    "RO",   0,      0,      0ull,   0ull},
47782         {"RESERVED_18_63"              ,        18,     46,     212,    "RAZ",  1,      1,      0,      0},
47783         {"FAU_END"                     ,        0,      1,      213,    "R/W",  0,      0,      0ull,   0ull},
47784         {"DWB_ENB"                     ,        1,      1,      213,    "R/W",  0,      0,      1ull,   1ull},
47785         {"PKO_ENB"                     ,        2,      1,      213,    "R/W",  0,      0,      0ull,   0ull},
47786         {"INB_MAT"                     ,        3,      1,      213,    "R/W1C",        0,      0,      0ull,   0ull},
47787         {"OUTB_MAT"                    ,        4,      1,      213,    "R/W1C",        0,      0,      0ull,   0ull},
47788         {"RESERVED_5_63"               ,        5,      59,     213,    "RAZ",  1,      1,      0,      0},
47789         {"CNT_VAL"                     ,        0,      15,     214,    "R/W",  0,      0,      0ull,   0ull},
47790         {"CNT_ENB"                     ,        15,     1,      214,    "R/W",  0,      0,      0ull,   0ull},
47791         {"RESERVED_16_63"              ,        16,     48,     214,    "RAZ",  1,      1,      0,      0},
47792         {"TOUT_VAL"                    ,        0,      12,     215,    "R/W",  0,      0,      4ull,   4ull},
47793         {"TOUT_ENB"                    ,        12,     1,      215,    "R/W",  0,      0,      1ull,   0ull},
47794         {"RESERVED_13_63"              ,        13,     51,     215,    "RAZ",  1,      1,      0,      0},
47795         {"CNT_VAL"                     ,        0,      15,     216,    "R/W",  0,      0,      0ull,   0ull},
47796         {"CNT_ENB"                     ,        15,     1,      216,    "R/W",  0,      0,      0ull,   0ull},
47797         {"RESERVED_16_63"              ,        16,     48,     216,    "RAZ",  1,      1,      0,      0},
47798         {"SRC"                         ,        0,      8,      217,    "R/W",  0,      1,      0ull,   0},
47799         {"DST"                         ,        8,      9,      217,    "R/W",  0,      1,      0ull,   0},
47800         {"OPC"                         ,        17,     4,      217,    "R/W",  0,      1,      0ull,   0},
47801         {"MASK"                        ,        21,     8,      217,    "R/W",  0,      1,      0ull,   0},
47802         {"RESERVED_29_63"              ,        29,     35,     217,    "RAZ",  1,      1,      0,      0},
47803         {"SRC"                         ,        0,      8,      218,    "R/W",  0,      1,      0ull,   0},
47804         {"DST"                         ,        8,      9,      218,    "R/W",  0,      1,      0ull,   0},
47805         {"OPC"                         ,        17,     4,      218,    "R/W",  0,      1,      0ull,   0},
47806         {"MASK"                        ,        21,     8,      218,    "R/W",  0,      1,      0ull,   0},
47807         {"RESERVED_29_63"              ,        29,     35,     218,    "RAZ",  1,      1,      0,      0},
47808         {"DATA"                        ,        0,      64,     219,    "R/W",  0,      1,      0ull,   0},
47809         {"DATA"                        ,        0,      64,     220,    "R/W",  0,      1,      0ull,   0},
47810         {"NP_SOP"                      ,        0,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
47811         {"NP_EOP"                      ,        1,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
47812         {"P_SOP"                       ,        2,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
47813         {"P_EOP"                       ,        3,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
47814         {"NP_DAT"                      ,        4,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
47815         {"P_DAT"                       ,        5,      1,      221,    "R/W",  0,      0,      0ull,   0ull},
47816         {"RESERVED_6_63"               ,        6,      58,     221,    "RAZ",  1,      1,      0,      0},
47817         {"NP_SOP"                      ,        0,      1,      222,    "R/W1C",        0,      0,      0ull,   0ull},
47818         {"NP_EOP"                      ,        1,      1,      222,    "R/W1C",        0,      0,      0ull,   0ull},
47819         {"P_SOP"                       ,        2,      1,      222,    "R/W1C",        0,      0,      0ull,   0ull},
47820         {"P_EOP"                       ,        3,      1,      222,    "R/W1C",        0,      0,      0ull,   0ull},
47821         {"NP_DAT"                      ,        4,      1,      222,    "R/W1C",        0,      0,      0ull,   0ull},
47822         {"P_DAT"                       ,        5,      1,      222,    "R/W1C",        0,      0,      0ull,   0ull},
47823         {"RESERVED_6_63"               ,        6,      58,     222,    "RAZ",  1,      1,      0,      0},
47824         {"CNT_VAL"                     ,        0,      15,     223,    "R/W",  0,      0,      0ull,   0ull},
47825         {"CNT_ENB"                     ,        15,     1,      223,    "R/W",  0,      0,      0ull,   0ull},
47826         {"RESERVED_16_63"              ,        16,     48,     223,    "RAZ",  1,      1,      0,      0},
47827         {"CNT_VAL"                     ,        0,      15,     224,    "R/W",  0,      0,      0ull,   0ull},
47828         {"CNT_ENB"                     ,        15,     1,      224,    "R/W",  0,      0,      0ull,   0ull},
47829         {"RESERVED_16_63"              ,        16,     48,     224,    "RAZ",  1,      1,      0,      0},
47830         {"CNT_VAL"                     ,        0,      15,     225,    "R/W",  0,      0,      0ull,   0ull},
47831         {"CNT_ENB"                     ,        15,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
47832         {"RESERVED_16_63"              ,        16,     48,     225,    "RAZ",  1,      1,      0,      0},
47833         {"SRC"                         ,        0,      9,      226,    "R/W",  0,      1,      0ull,   0},
47834         {"DST"                         ,        9,      8,      226,    "R/W",  0,      1,      0ull,   0},
47835         {"EOT"                         ,        17,     1,      226,    "R/W",  0,      1,      0ull,   0},
47836         {"MASK"                        ,        18,     8,      226,    "R/W",  0,      1,      0ull,   0},
47837         {"RESERVED_26_63"              ,        26,     38,     226,    "RAZ",  1,      1,      0,      0},
47838         {"SRC"                         ,        0,      9,      227,    "R/W",  0,      1,      0ull,   0},
47839         {"DST"                         ,        9,      8,      227,    "R/W",  0,      1,      0ull,   0},
47840         {"EOT"                         ,        17,     1,      227,    "R/W",  0,      1,      0ull,   0},
47841         {"MASK"                        ,        18,     8,      227,    "R/W",  0,      1,      0ull,   0},
47842         {"RESERVED_26_63"              ,        26,     38,     227,    "RAZ",  1,      1,      0,      0},
47843         {"DATA"                        ,        0,      64,     228,    "R/W",  0,      1,      0ull,   0},
47844         {"DATA"                        ,        0,      64,     229,    "R/W",  0,      1,      0ull,   0},
47845         {"CNT_VAL"                     ,        0,      15,     230,    "R/W",  0,      0,      0ull,   0ull},
47846         {"CNT_ENB"                     ,        15,     1,      230,    "R/W",  0,      0,      0ull,   0ull},
47847         {"RESERVED_16_63"              ,        16,     48,     230,    "RAZ",  1,      1,      0,      0},
47848         {"CNT_VAL"                     ,        0,      15,     231,    "R/W",  0,      0,      0ull,   0ull},
47849         {"CNT_ENB"                     ,        15,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
47850         {"RESERVED_16_63"              ,        16,     48,     231,    "RAZ",  1,      1,      0,      0},
47851         {"CNT_VAL"                     ,        0,      15,     232,    "R/W",  0,      0,      0ull,   0ull},
47852         {"CNT_ENB"                     ,        15,     1,      232,    "R/W",  0,      0,      0ull,   0ull},
47853         {"RESERVED_16_63"              ,        16,     48,     232,    "RAZ",  1,      1,      0,      0},
47854         {"PORT"                        ,        0,      6,      233,    "RO",   0,      1,      0ull,   0},
47855         {"RESERVED_6_63"               ,        6,      58,     233,    "RAZ",  1,      1,      0,      0},
47856         {"SKIP_SZ"                     ,        0,      6,      234,    "R/W",  0,      0,      0ull,   0ull},
47857         {"RESERVED_6_63"               ,        6,      58,     234,    "RAZ",  1,      1,      0,      0},
47858         {"BACK"                        ,        0,      4,      235,    "R/W",  0,      0,      0ull,   0ull},
47859         {"RESERVED_4_63"               ,        4,      60,     235,    "RAZ",  1,      1,      0,      0},
47860         {"BACK"                        ,        0,      4,      236,    "R/W",  0,      0,      0ull,   0ull},
47861         {"RESERVED_4_63"               ,        4,      60,     236,    "RAZ",  1,      1,      0,      0},
47862         {"PWP"                         ,        0,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47863         {"IPD_NEW"                     ,        1,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47864         {"IPD_OLD"                     ,        2,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47865         {"PRC_OFF"                     ,        3,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47866         {"PWQ0"                        ,        4,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47867         {"PWQ1"                        ,        5,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47868         {"PBM_WORD"                    ,        6,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47869         {"PBM0"                        ,        7,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47870         {"PBM1"                        ,        8,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47871         {"PBM2"                        ,        9,      1,      237,    "RO",   0,      0,      0ull,   0ull},
47872         {"PBM3"                        ,        10,     1,      237,    "RO",   0,      0,      0ull,   0ull},
47873         {"IPQ_PBE0"                    ,        11,     1,      237,    "RO",   0,      0,      0ull,   0ull},
47874         {"IPQ_PBE1"                    ,        12,     1,      237,    "RO",   0,      0,      0ull,   0ull},
47875         {"PWQ_POW"                     ,        13,     1,      237,    "RO",   0,      0,      0ull,   0ull},
47876         {"PWQ_WP1"                     ,        14,     1,      237,    "RO",   0,      0,      0ull,   0ull},
47877         {"PWQ_WQED"                    ,        15,     1,      237,    "RO",   0,      0,      0ull,   0ull},
47878         {"CSR_NCMD"                    ,        16,     1,      237,    "RO",   0,      0,      0ull,   0ull},
47879         {"CSR_MEM"                     ,        17,     1,      237,    "RO",   0,      0,      0ull,   0ull},
47880         {"RESERVED_18_63"              ,        18,     46,     237,    "RAZ",  1,      1,      0,      0},
47881         {"PRT_ENB"                     ,        0,      40,     238,    "R/W",  0,      0,      0ull,   0ull},
47882         {"RESERVED_40_63"              ,        40,     24,     238,    "RAZ",  1,      1,      0,      0},
47883         {"CLK_CNT"                     ,        0,      64,     239,    "RO",   0,      0,      0ull,   0ull},
47884         {"IPD_EN"                      ,        0,      1,      240,    "R/W",  0,      0,      0ull,   0ull},
47885         {"OPC_MODE"                    ,        1,      2,      240,    "R/W",  0,      0,      0ull,   0ull},
47886         {"PBP_EN"                      ,        3,      1,      240,    "R/W",  0,      0,      0ull,   0ull},
47887         {"WQE_LEND"                    ,        4,      1,      240,    "R/W",  0,      0,      0ull,   0ull},
47888         {"PKT_LEND"                    ,        5,      1,      240,    "R/W",  0,      0,      0ull,   0ull},
47889         {"NADDBUF"                     ,        6,      1,      240,    "R/W",  0,      0,      0ull,   0ull},
47890         {"ADDPKT"                      ,        7,      1,      240,    "R/W",  0,      0,      0ull,   0ull},
47891         {"RESET"                       ,        8,      1,      240,    "R/W",  0,      0,      0ull,   0ull},
47892         {"LEN_M8"                      ,        9,      1,      240,    "R/W",  0,      0,      0ull,   1ull},
47893         {"PKT_OFF"                     ,        10,     1,      240,    "R/W",  0,      0,      0ull,   0ull},
47894         {"IPD_FULL"                    ,        11,     1,      240,    "R/W",  0,      0,      0ull,   0ull},
47895         {"PQ_NABUF"                    ,        12,     1,      240,    "R/W",  0,      0,      0ull,   0ull},
47896         {"PQ_APKT"                     ,        13,     1,      240,    "R/W",  0,      0,      0ull,   0ull},
47897         {"NO_WPTR"                     ,        14,     1,      240,    "R/W",  0,      0,      0ull,   0ull},
47898         {"RESERVED_15_63"              ,        15,     49,     240,    "RAZ",  1,      1,      0,      0},
47899         {"PRC_PAR0"                    ,        0,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47900         {"PRC_PAR1"                    ,        1,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47901         {"PRC_PAR2"                    ,        2,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47902         {"PRC_PAR3"                    ,        3,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47903         {"BP_SUB"                      ,        4,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47904         {"DC_OVR"                      ,        5,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47905         {"CC_OVR"                      ,        6,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47906         {"C_COLL"                      ,        7,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47907         {"D_COLL"                      ,        8,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47908         {"BC_OVR"                      ,        9,      1,      241,    "R/W",  0,      0,      0ull,   0ull},
47909         {"PQ_ADD"                      ,        10,     1,      241,    "R/W",  0,      0,      0ull,   0ull},
47910         {"PQ_SUB"                      ,        11,     1,      241,    "R/W",  0,      0,      0ull,   0ull},
47911         {"RESERVED_12_63"              ,        12,     52,     241,    "RAZ",  1,      1,      0,      0},
47912         {"PRC_PAR0"                    ,        0,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47913         {"PRC_PAR1"                    ,        1,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47914         {"PRC_PAR2"                    ,        2,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47915         {"PRC_PAR3"                    ,        3,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47916         {"BP_SUB"                      ,        4,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47917         {"DC_OVR"                      ,        5,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47918         {"CC_OVR"                      ,        6,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47919         {"C_COLL"                      ,        7,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47920         {"D_COLL"                      ,        8,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47921         {"BC_OVR"                      ,        9,      1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47922         {"PQ_ADD"                      ,        10,     1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47923         {"PQ_SUB"                      ,        11,     1,      242,    "R/W1C",        0,      0,      0ull,   0ull},
47924         {"RESERVED_12_63"              ,        12,     52,     242,    "RAZ",  1,      1,      0,      0},
47925         {"SKIP_SZ"                     ,        0,      6,      243,    "R/W",  0,      0,      0ull,   0ull},
47926         {"RESERVED_6_63"               ,        6,      58,     243,    "RAZ",  1,      1,      0,      0},
47927         {"MB_SIZE"                     ,        0,      12,     244,    "R/W",  0,      0,      32ull,  32ull},
47928         {"RESERVED_12_63"              ,        12,     52,     244,    "RAZ",  1,      1,      0,      0},
47929         {"PTR"                         ,        0,      29,     245,    "RO",   1,      1,      0,      0},
47930         {"RESERVED_29_63"              ,        29,     35,     245,    "RAZ",  1,      1,      0,      0},
47931         {"PAGE_CNT"                    ,        0,      17,     246,    "R/W",  0,      0,      0ull,   0ull},
47932         {"BP_ENB"                      ,        17,     1,      246,    "R/W",  0,      0,      0ull,   0ull},
47933         {"RESERVED_18_63"              ,        18,     46,     246,    "RAZ",  1,      1,      0,      0},
47934         {"PAGE_CNT"                    ,        0,      17,     247,    "R/W",  0,      0,      0ull,   0ull},
47935         {"BP_ENB"                      ,        17,     1,      247,    "R/W",  0,      0,      0ull,   0ull},
47936         {"RESERVED_18_63"              ,        18,     46,     247,    "RAZ",  1,      1,      0,      0},
47937         {"CNT_VAL"                     ,        0,      25,     248,    "RO",   0,      1,      0ull,   0},
47938         {"RESERVED_25_63"              ,        25,     39,     248,    "RAZ",  1,      1,      0,      0},
47939         {"CNT_VAL"                     ,        0,      25,     249,    "RO",   0,      1,      0ull,   0},
47940         {"RESERVED_25_63"              ,        25,     39,     249,    "RAZ",  1,      1,      0,      0},
47941         {"CNT"                         ,        0,      32,     250,    "RO",   0,      1,      0ull,   0},
47942         {"WMARK"                       ,        32,     32,     250,    "R/W",  0,      1,      4294967295ull,  0},
47943         {"INTR"                        ,        0,      64,     251,    "R/W1C",        0,      0,      0ull,   0ull},
47944         {"ENB"                         ,        0,      64,     252,    "R/W",  0,      0,      0ull,   1ull},
47945         {"RADDR"                       ,        0,      3,      253,    "R/W",  0,      0,      0ull,   0ull},
47946         {"CENA"                        ,        3,      1,      253,    "R/W",  0,      0,      1ull,   1ull},
47947         {"PTR"                         ,        4,      29,     253,    "RO",   1,      1,      0,      0},
47948         {"PRADDR"                      ,        33,     3,      253,    "RO",   1,      1,      0,      0},
47949         {"MAX_PKT"                     ,        36,     3,      253,    "RO",   0,      0,      5ull,   5ull},
47950         {"RESERVED_39_63"              ,        39,     25,     253,    "RAZ",  1,      1,      0,      0},
47951         {"RADDR"                       ,        0,      7,      254,    "R/W",  0,      0,      0ull,   0ull},
47952         {"CENA"                        ,        7,      1,      254,    "R/W",  0,      0,      1ull,   1ull},
47953         {"PTR"                         ,        8,      29,     254,    "RO",   1,      1,      0,      0},
47954         {"MAX_PKT"                     ,        37,     7,      254,    "RO",   0,      0,      16ull,  16ull},
47955         {"RESERVED_44_63"              ,        44,     20,     254,    "RAZ",  1,      1,      0,      0},
47956         {"WQE_PCNT"                    ,        0,      7,      255,    "RO",   0,      0,      0ull,   0ull},
47957         {"PKT_PCNT"                    ,        7,      7,      255,    "RO",   0,      0,      0ull,   0ull},
47958         {"PFIF_CNT"                    ,        14,     3,      255,    "RO",   0,      0,      0ull,   0ull},
47959         {"WQEV_CNT"                    ,        17,     1,      255,    "RO",   0,      0,      0ull,   0ull},
47960         {"PKTV_CNT"                    ,        18,     1,      255,    "RO",   0,      0,      0ull,   0ull},
47961         {"RESERVED_19_63"              ,        19,     45,     255,    "RAZ",  1,      1,      0,      0},
47962         {"RADDR"                       ,        0,      8,      256,    "R/W",  0,      0,      0ull,   0ull},
47963         {"CENA"                        ,        8,      1,      256,    "R/W",  0,      0,      1ull,   1ull},
47964         {"PTR"                         ,        9,      29,     256,    "RO",   1,      1,      0,      0},
47965         {"PRADDR"                      ,        38,     8,      256,    "RO",   1,      1,      0,      0},
47966         {"WRADDR"                      ,        46,     8,      256,    "RO",   1,      1,      0,      0},
47967         {"MAX_CNTS"                    ,        54,     7,      256,    "RO",   0,      0,      64ull,  64ull},
47968         {"RESERVED_61_63"              ,        61,     3,      256,    "RAZ",  1,      1,      0,      0},
47969         {"PASS"                        ,        0,      32,     257,    "R/W",  0,      1,      0ull,   0},
47970         {"DROP"                        ,        32,     32,     257,    "R/W",  0,      1,      0ull,   0},
47971         {"Q0_PCNT"                     ,        0,      32,     258,    "RO",   0,      0,      0ull,   0ull},
47972         {"RESERVED_32_63"              ,        32,     32,     258,    "RAZ",  1,      1,      0,      0},
47973         {"PRT_ENB"                     ,        0,      36,     259,    "R/W",  0,      0,      0ull,   0ull},
47974         {"AVG_DLY"                     ,        36,     14,     259,    "R/W",  0,      1,      0ull,   0},
47975         {"PRB_DLY"                     ,        50,     14,     259,    "R/W",  0,      0,      0ull,   0ull},
47976         {"PRT_ENB"                     ,        0,      4,      260,    "R/W",  0,      0,      0ull,   0ull},
47977         {"RESERVED_4_63"               ,        4,      60,     260,    "RAZ",  1,      1,      0,      0},
47978         {"PRB_CON"                     ,        0,      32,     261,    "R/W",  0,      1,      0ull,   0},
47979         {"AVG_CON"                     ,        32,     8,      261,    "R/W",  0,      1,      0ull,   0},
47980         {"NEW_CON"                     ,        40,     8,      261,    "R/W",  0,      1,      0ull,   0},
47981         {"USE_PCNT"                    ,        48,     1,      261,    "R/W",  0,      0,      0ull,   0ull},
47982         {"RESERVED_49_63"              ,        49,     15,     261,    "RAZ",  1,      1,      0,      0},
47983         {"PAGE_CNT"                    ,        0,      25,     262,    "R/W",  1,      0,      0,      0ull},
47984         {"PORT"                        ,        25,     6,      262,    "R/W",  1,      0,      0,      0ull},
47985         {"RESERVED_31_63"              ,        31,     33,     262,    "RAZ",  1,      1,      0,      0},
47986         {"PORT_BIT"                    ,        0,      32,     263,    "R/W",  0,      0,      4294967295ull,  4294967295ull},
47987         {"RESERVED_32_35"              ,        32,     4,      263,    "RAZ",  1,      1,      0,      0},
47988         {"PORT_BIT2"                   ,        36,     4,      263,    "R/W",  0,      0,      15ull,  15ull},
47989         {"RESERVED_40_63"              ,        40,     24,     263,    "RAZ",  1,      1,      0,      0},
47990         {"CNT"                         ,        0,      32,     264,    "R/W",  1,      0,      0,      0ull},
47991         {"PORT_QOS"                    ,        32,     9,      264,    "R/W",  1,      0,      0,      0ull},
47992         {"RESERVED_41_63"              ,        41,     23,     264,    "RAZ",  1,      1,      0,      0},
47993         {"WQE_POOL"                    ,        0,      3,      265,    "R/W",  0,      0,      1ull,   1ull},
47994         {"RESERVED_3_63"               ,        3,      61,     265,    "RAZ",  1,      1,      0,      0},
47995         {"PTR"                         ,        0,      29,     266,    "RO",   1,      1,      0,      0},
47996         {"RESERVED_29_63"              ,        29,     35,     266,    "RAZ",  1,      1,      0,      0},
47997         {"MEM0"                        ,        0,      1,      267,    "RO",   0,      0,      0ull,   0ull},
47998         {"MEM1"                        ,        1,      1,      267,    "RO",   0,      0,      0ull,   0ull},
47999         {"RRC"                         ,        2,      1,      267,    "RO",   0,      0,      0ull,   0ull},
48000         {"RESERVED_3_63"               ,        3,      61,     267,    "RAZ",  1,      1,      0,      0},
48001         {"MEM0_ERR"                    ,        0,      7,      268,    "R/W",  0,      0,      0ull,   0ull},
48002         {"MEM1_ERR"                    ,        7,      7,      268,    "R/W",  0,      0,      0ull,   0ull},
48003         {"RESERVED_14_63"              ,        14,     50,     268,    "RAZ",  1,      1,      0,      0},
48004         {"KED0_SBE"                    ,        0,      1,      269,    "R/W",  0,      0,      0ull,   0ull},
48005         {"KED0_DBE"                    ,        1,      1,      269,    "R/W",  0,      0,      0ull,   0ull},
48006         {"KED1_SBE"                    ,        2,      1,      269,    "R/W",  0,      0,      0ull,   0ull},
48007         {"KED1_DBE"                    ,        3,      1,      269,    "R/W",  0,      0,      0ull,   0ull},
48008         {"RESERVED_4_63"               ,        4,      60,     269,    "RAZ",  1,      1,      0,      0},
48009         {"KED0_SBE"                    ,        0,      1,      270,    "R/W1C",        0,      0,      0ull,   0ull},
48010         {"KED0_DBE"                    ,        1,      1,      270,    "R/W1C",        0,      0,      0ull,   0ull},
48011         {"KED1_SBE"                    ,        2,      1,      270,    "R/W1C",        0,      0,      0ull,   0ull},
48012         {"KED1_DBE"                    ,        3,      1,      270,    "R/W1C",        0,      0,      0ull,   0ull},
48013         {"RESERVED_4_63"               ,        4,      60,     270,    "RAZ",  1,      1,      0,      0},
48014         {"WLB_DAT"                     ,        0,      4,      271,    "RO",   0,      0,      0ull,   0ull},
48015         {"STIN_MSK"                    ,        4,      1,      271,    "RO",   0,      0,      0ull,   0ull},
48016         {"DT"                          ,        5,      1,      271,    "RO",   0,      0,      0ull,   0ull},
48017         {"DTCNT"                       ,        6,      13,     271,    "RO",   0,      0,      0ull,   0ull},
48018         {"WLB_MSK"                     ,        19,     4,      271,    "RO",   0,      0,      0ull,   0ull},
48019         {"DTBNK"                       ,        23,     1,      271,    "RO",   0,      0,      0ull,   0ull},
48020         {"RESERVED_24_63"              ,        24,     40,     271,    "RAZ",  0,      0,      0ull,   0ull},
48021         {"L2T"                         ,        0,      9,      272,    "RO",   0,      0,      0ull,   0ull},
48022         {"VAB_VWCF0"                   ,        9,      1,      272,    "RO",   0,      0,      0ull,   0ull},
48023         {"RESERVED_10_10"              ,        10,     1,      272,    "RAZ",  0,      0,      0ull,   0ull},
48024         {"VAB_VWCF1"                   ,        11,     1,      272,    "RO",   0,      0,      0ull,   0ull},
48025         {"VWDF0"                       ,        12,     4,      272,    "RO",   0,      0,      0ull,   0ull},
48026         {"VWDF1"                       ,        16,     4,      272,    "RO",   0,      0,      0ull,   0ull},
48027         {"ILC"                         ,        20,     1,      272,    "RO",   0,      0,      0ull,   0ull},
48028         {"PLC0"                        ,        21,     1,      272,    "RO",   0,      0,      0ull,   0ull},
48029         {"PLC1"                        ,        22,     1,      272,    "RO",   0,      0,      0ull,   0ull},
48030         {"PLC2"                        ,        23,     1,      272,    "RO",   0,      0,      0ull,   0ull},
48031         {"RESERVED_24_63"              ,        24,     40,     272,    "RAZ",  0,      0,      0ull,   0ull},
48032         {"XRDDAT"                      ,        0,      1,      273,    "RO",   0,      0,      0ull,   0ull},
48033         {"XRDMSK"                      ,        1,      1,      273,    "RO",   0,      0,      0ull,   0ull},
48034         {"PICBST"                      ,        2,      1,      273,    "RO",   0,      0,      0ull,   0ull},
48035         {"IPCBST"                      ,        3,      1,      273,    "RO",   0,      0,      0ull,   0ull},
48036         {"RHDB"                        ,        4,      4,      273,    "RO",   0,      0,      0ull,   0ull},
48037         {"RMDB"                        ,        8,      4,      273,    "RO",   0,      0,      0ull,   0ull},
48038         {"MRB"                         ,        12,     4,      273,    "RO",   0,      0,      0ull,   0ull},
48039         {"RESERVED_16_63"              ,        16,     48,     273,    "RAZ",  0,      0,      0ull,   0ull},
48040         {"LRF_ARB_MODE"                ,        0,      1,      274,    "R/W",  0,      0,      1ull,   1ull},
48041         {"RFB_ARB_MODE"                ,        1,      1,      274,    "R/W",  0,      0,      1ull,   1ull},
48042         {"RSP_ARB_MODE"                ,        2,      1,      274,    "R/W",  0,      0,      1ull,   1ull},
48043         {"MWF_CRD"                     ,        3,      4,      274,    "R/W",  0,      0,      2ull,   2ull},
48044         {"IDXALIAS"                    ,        7,      1,      274,    "R/W",  0,      0,      0ull,   1ull},
48045         {"FPEN"                        ,        8,      1,      274,    "R/W",  0,      0,      0ull,   0ull},
48046         {"FPEMPTY"                     ,        9,      1,      274,    "R/W",  0,      0,      0ull,   0ull},
48047         {"FPEXP"                       ,        10,     4,      274,    "R/W",  0,      0,      0ull,   0ull},
48048         {"DFILL_DIS"                   ,        14,     1,      274,    "R/W",  0,      0,      0ull,   0ull},
48049         {"DPRES0"                      ,        15,     1,      274,    "R/W",  0,      0,      0ull,   0ull},
48050         {"DPRES1"                      ,        16,     1,      274,    "R/W",  0,      0,      0ull,   0ull},
48051         {"XOR_BANK"                    ,        17,     1,      274,    "R/W",  0,      0,      0ull,   0ull},
48052         {"LBIST"                       ,        18,     1,      274,    "R/W",  0,      0,      0ull,   0ull},
48053         {"BSTRUN"                      ,        19,     1,      274,    "RO",   0,      0,      0ull,   0ull},
48054         {"RESERVED_20_63"              ,        20,     44,     274,    "RAZ",  1,      1,      0,      0},
48055         {"L2T"                         ,        0,      1,      275,    "R/W",  0,      0,      0ull,   0ull},
48056         {"L2D"                         ,        1,      1,      275,    "R/W",  0,      0,      0ull,   0ull},
48057         {"FINV"                        ,        2,      1,      275,    "R/W",  0,      0,      0ull,   0ull},
48058         {"SET"                         ,        3,      3,      275,    "R/W",  0,      0,      0ull,   0ull},
48059         {"PPNUM"                       ,        6,      4,      275,    "R/W",  0,      0,      0ull,   0ull},
48060         {"LFB_DMP"                     ,        10,     1,      275,    "R/W",  0,      0,      0ull,   0ull},
48061         {"LFB_ENUM"                    ,        11,     4,      275,    "R/W",  0,      0,      0ull,   0ull},
48062         {"RESERVED_15_63"              ,        15,     49,     275,    "RAZ",  0,      0,      0ull,   0ull},
48063         {"DT_TAG"                      ,        0,      29,     276,    "RO",   0,      0,      0ull,   0ull},
48064         {"DT_VLD"                      ,        29,     1,      276,    "RO",   0,      0,      0ull,   0ull},
48065         {"RESERVED_30_30"              ,        30,     1,      276,    "RAZ",  0,      0,      0ull,   0ull},
48066         {"DTENA"                       ,        31,     1,      276,    "R/W",  0,      0,      0ull,   0ull},
48067         {"RESERVED_32_63"              ,        32,     32,     276,    "RAZ",  0,      0,      0ull,   0ull},
48068         {"PLC0RMSK"                    ,        0,      32,     277,    "R/W",  0,      0,      0ull,   0ull},
48069         {"PLC1RMSK"                    ,        32,     32,     277,    "R/W",  0,      0,      0ull,   0ull},
48070         {"PLC2RMSK"                    ,        0,      32,     278,    "R/W",  0,      0,      0ull,   0ull},
48071         {"ILCRMSK"                     ,        32,     32,     278,    "R/W",  0,      0,      0ull,   0ull},
48072         {"OOB1EN"                      ,        0,      1,      279,    "R/W",  0,      0,      0ull,   1ull},
48073         {"OOB2EN"                      ,        1,      1,      279,    "R/W",  0,      0,      0ull,   1ull},
48074         {"OOB3EN"                      ,        2,      1,      279,    "R/W",  0,      0,      0ull,   1ull},
48075         {"L2TSECEN"                    ,        3,      1,      279,    "R/W",  0,      0,      0ull,   1ull},
48076         {"L2TDEDEN"                    ,        4,      1,      279,    "R/W",  0,      0,      0ull,   1ull},
48077         {"L2DSECEN"                    ,        5,      1,      279,    "R/W",  0,      0,      0ull,   1ull},
48078         {"L2DDEDEN"                    ,        6,      1,      279,    "R/W",  0,      0,      0ull,   1ull},
48079         {"LCKENA"                      ,        7,      1,      279,    "R/W",  0,      0,      0ull,   1ull},
48080         {"LCK2ENA"                     ,        8,      1,      279,    "R/W",  0,      0,      0ull,   1ull},
48081         {"RESERVED_9_63"               ,        9,      55,     279,    "RAZ",  0,      0,      0ull,   0ull},
48082         {"OOB1"                        ,        0,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
48083         {"OOB2"                        ,        1,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
48084         {"OOB3"                        ,        2,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
48085         {"L2TSEC"                      ,        3,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
48086         {"L2TDED"                      ,        4,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
48087         {"L2DSEC"                      ,        5,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
48088         {"L2DDED"                      ,        6,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
48089         {"LCK"                         ,        7,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
48090         {"LCK2"                        ,        8,      1,      280,    "R/W1C",        0,      0,      0ull,   0ull},
48091         {"RESERVED_9_63"               ,        9,      55,     280,    "RAZ",  0,      0,      0ull,   0ull},
48092         {"LCK_ENA"                     ,        0,      1,      281,    "R/W",  0,      0,      0ull,   0ull},
48093         {"RESERVED_1_3"                ,        1,      3,      281,    "RAZ",  0,      0,      0ull,   0ull},
48094         {"LCK_BASE"                    ,        4,      27,     281,    "R/W",  0,      0,      0ull,   0ull},
48095         {"RESERVED_31_63"              ,        31,     33,     281,    "RAZ",  0,      0,      0ull,   0ull},
48096         {"LCK_OFFSET"                  ,        0,      10,     282,    "R/W",  0,      0,      0ull,   0ull},
48097         {"RESERVED_10_63"              ,        10,     54,     282,    "RAZ",  0,      0,      0ull,   0ull},
48098         {"VLD"                         ,        0,      1,      283,    "RO",   0,      0,      0ull,   0ull},
48099         {"CMD"                         ,        1,      4,      283,    "RO",   0,      0,      0ull,   0ull},
48100         {"SID"                         ,        5,      9,      283,    "RO",   0,      0,      0ull,   0ull},
48101         {"VABNUM"                      ,        14,     4,      283,    "RO",   0,      0,      0ull,   0ull},
48102         {"SET"                         ,        18,     3,      283,    "RO",   0,      0,      0ull,   0ull},
48103         {"IHD"                         ,        21,     1,      283,    "RO",   0,      0,      0ull,   0ull},
48104         {"ITL"                         ,        22,     1,      283,    "RO",   0,      0,      0ull,   0ull},
48105         {"INXT"                        ,        23,     4,      283,    "RO",   0,      0,      0ull,   0ull},
48106         {"VAM"                         ,        27,     1,      283,    "RO",   0,      0,      0ull,   0ull},
48107         {"STCFL"                       ,        28,     1,      283,    "RO",   0,      0,      0ull,   0ull},
48108         {"STINV"                       ,        29,     1,      283,    "RO",   0,      0,      0ull,   0ull},
48109         {"STPND"                       ,        30,     1,      283,    "RO",   0,      0,      0ull,   0ull},
48110         {"STCPND"                      ,        31,     1,      283,    "RO",   0,      0,      0ull,   0ull},
48111         {"RESERVED_32_63"              ,        32,     32,     283,    "RAZ",  0,      0,      0ull,   0ull},
48112         {"VLD"                         ,        0,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48113         {"WTPRB"                       ,        1,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48114         {"PRBRTY"                      ,        2,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48115         {"WTMFL"                       ,        3,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48116         {"WTVTM"                       ,        4,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48117         {"WTSTRSC"                     ,        5,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48118         {"WTSTRSP"                     ,        6,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48119         {"WTSTDT"                      ,        7,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48120         {"WTRDA"                       ,        8,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48121         {"WTSTM"                       ,        9,      1,      284,    "RO",   0,      0,      0ull,   0ull},
48122         {"WTWRM"                       ,        10,     1,      284,    "RO",   0,      0,      0ull,   0ull},
48123         {"WTWHF"                       ,        11,     1,      284,    "RO",   0,      0,      0ull,   0ull},
48124         {"WTWHP"                       ,        12,     1,      284,    "RO",   0,      0,      0ull,   0ull},
48125         {"WTDQ"                        ,        13,     1,      284,    "RO",   0,      0,      0ull,   0ull},
48126         {"WTDW"                        ,        14,     1,      284,    "RO",   0,      0,      0ull,   0ull},
48127         {"WTRSP"                       ,        15,     1,      284,    "RO",   0,      0,      0ull,   0ull},
48128         {"BID"                         ,        16,     2,      284,    "RO",   0,      0,      0ull,   0ull},
48129         {"DSGOING"                     ,        18,     1,      284,    "RO",   0,      0,      0ull,   0ull},
48130         {"RESERVED_19_63"              ,        19,     45,     284,    "RAZ",  0,      0,      0ull,   0ull},
48131         {"LFB_IDX"                     ,        0,      11,     285,    "RO",   0,      0,      0ull,   0ull},
48132         {"LFB_TAG"                     ,        11,     16,     285,    "RO",   0,      0,      0ull,   0ull},
48133         {"RESERVED_27_63"              ,        27,     37,     285,    "RAZ",  0,      0,      0ull,   0ull},
48134         {"LFB_HWM"                     ,        0,      4,      286,    "R/W",  0,      0,      15ull,  15ull},
48135         {"STPARTDIS"                   ,        4,      1,      286,    "R/W",  0,      0,      0ull,   0ull},
48136         {"RESERVED_5_63"               ,        5,      59,     286,    "RAZ",  0,      0,      0ull,   0ull},
48137         {"STENA"                       ,        0,      1,      287,    "R/W",  0,      0,      0ull,   0ull},
48138         {"DWBENA"                      ,        1,      1,      287,    "R/W",  0,      0,      0ull,   0ull},
48139         {"RESERVED_2_63"               ,        2,      62,     287,    "RAZ",  0,      0,      0ull,   0ull},
48140         {"SIZE"                        ,        0,      14,     288,    "R/W",  0,      0,      0ull,   0ull},
48141         {"RESERVED_14_19"              ,        14,     6,      288,    "RAZ",  0,      0,      0ull,   0ull},
48142         {"SADR"                        ,        20,     14,     288,    "R/W",  0,      0,      0ull,   0ull},
48143         {"RESERVED_34_35"              ,        34,     2,      288,    "RAZ",  0,      0,      0ull,   0ull},
48144         {"FSRC"                        ,        36,     1,      288,    "RO",   0,      0,      0ull,   0ull},
48145         {"FADR"                        ,        37,     27,     288,    "RO",   0,      0,      0ull,   0ull},
48146         {"SIZE"                        ,        0,      14,     289,    "R/W",  0,      0,      0ull,   0ull},
48147         {"RESERVED_14_19"              ,        14,     6,      289,    "RAZ",  0,      0,      0ull,   0ull},
48148         {"SADR"                        ,        20,     14,     289,    "R/W",  0,      0,      0ull,   0ull},
48149         {"RESERVED_34_35"              ,        34,     2,      289,    "RAZ",  0,      0,      0ull,   0ull},
48150         {"FSRC"                        ,        36,     1,      289,    "RO",   0,      0,      0ull,   0ull},
48151         {"FADR"                        ,        37,     27,     289,    "RO",   0,      0,      0ull,   0ull},
48152         {"SIZE"                        ,        0,      14,     290,    "R/W",  0,      0,      0ull,   0ull},
48153         {"RESERVED_14_19"              ,        14,     6,      290,    "RAZ",  0,      0,      0ull,   0ull},
48154         {"SADR"                        ,        20,     14,     290,    "R/W",  0,      0,      0ull,   0ull},
48155         {"RESERVED_34_35"              ,        34,     2,      290,    "RAZ",  0,      0,      0ull,   0ull},
48156         {"FSRC"                        ,        36,     1,      290,    "RO",   0,      0,      0ull,   0ull},
48157         {"FADR"                        ,        37,     27,     290,    "RO",   0,      0,      0ull,   0ull},
48158         {"PFCNT0"                      ,        0,      36,     291,    "RO",   0,      0,      0ull,   0ull},
48159         {"RESERVED_36_63"              ,        36,     28,     291,    "RAZ",  0,      0,      0ull,   0ull},
48160         {"CNT0SEL"                     ,        0,      6,      292,    "R/W",  0,      0,      0ull,   0ull},
48161         {"CNT0CLR"                     ,        6,      1,      292,    "R/W",  0,      0,      0ull,   0ull},
48162         {"CNT0ENA"                     ,        7,      1,      292,    "R/W",  0,      0,      0ull,   0ull},
48163         {"CNT1SEL"                     ,        8,      6,      292,    "R/W",  0,      0,      0ull,   0ull},
48164         {"CNT1CLR"                     ,        14,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48165         {"CNT1ENA"                     ,        15,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48166         {"CNT2SEL"                     ,        16,     6,      292,    "R/W",  0,      0,      0ull,   0ull},
48167         {"CNT2CLR"                     ,        22,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48168         {"CNT2ENA"                     ,        23,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48169         {"CNT3SEL"                     ,        24,     6,      292,    "R/W",  0,      0,      0ull,   0ull},
48170         {"CNT3CLR"                     ,        30,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48171         {"CNT3ENA"                     ,        31,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48172         {"CNT0RDCLR"                   ,        32,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48173         {"CNT1RDCLR"                   ,        33,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48174         {"CNT2RDCLR"                   ,        34,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48175         {"CNT3RDCLR"                   ,        35,     1,      292,    "R/W",  0,      0,      0ull,   0ull},
48176         {"RESERVED_36_63"              ,        36,     28,     292,    "RAZ",  0,      0,      0ull,   0ull},
48177         {"PP0GRP"                      ,        0,      2,      293,    "R/W",  0,      0,      0ull,   0ull},
48178         {"PP1GRP"                      ,        2,      2,      293,    "R/W",  0,      0,      0ull,   0ull},
48179         {"PP2GRP"                      ,        4,      2,      293,    "R/W",  0,      0,      0ull,   0ull},
48180         {"PP3GRP"                      ,        6,      2,      293,    "R/W",  0,      0,      0ull,   0ull},
48181         {"PP4GRP"                      ,        8,      2,      293,    "R/W",  0,      0,      0ull,   0ull},
48182         {"PP5GRP"                      ,        10,     2,      293,    "R/W",  0,      0,      0ull,   0ull},
48183         {"PP6GRP"                      ,        12,     2,      293,    "R/W",  0,      0,      0ull,   0ull},
48184         {"PP7GRP"                      ,        14,     2,      293,    "R/W",  0,      0,      0ull,   0ull},
48185         {"PP8GRP"                      ,        16,     2,      293,    "R/W",  0,      0,      0ull,   0ull},
48186         {"PP9GRP"                      ,        18,     2,      293,    "R/W",  0,      0,      0ull,   0ull},
48187         {"PP10GRP"                     ,        20,     2,      293,    "R/W",  0,      0,      0ull,   0ull},
48188         {"PP11GRP"                     ,        22,     2,      293,    "R/W",  0,      0,      0ull,   0ull},
48189         {"RESERVED_24_63"              ,        24,     40,     293,    "RAZ",  0,      0,      0ull,   0ull},
48190         {"UMSK0"                       ,        0,      8,      294,    "R/W",  0,      0,      0ull,   0ull},
48191         {"UMSK1"                       ,        8,      8,      294,    "R/W",  0,      0,      0ull,   0ull},
48192         {"UMSK2"                       ,        16,     8,      294,    "R/W",  0,      0,      0ull,   0ull},
48193         {"UMSK3"                       ,        24,     8,      294,    "R/W",  0,      0,      0ull,   0ull},
48194         {"RESERVED_32_63"              ,        32,     32,     294,    "RAZ",  0,      0,      0ull,   0ull},
48195         {"UMSK4"                       ,        0,      8,      295,    "R/W",  0,      0,      0ull,   0ull},
48196         {"UMSK5"                       ,        8,      8,      295,    "R/W",  0,      0,      0ull,   0ull},
48197         {"UMSK6"                       ,        16,     8,      295,    "R/W",  0,      0,      0ull,   0ull},
48198         {"UMSK7"                       ,        24,     8,      295,    "R/W",  0,      0,      0ull,   0ull},
48199         {"RESERVED_32_63"              ,        32,     32,     295,    "RAZ",  0,      0,      0ull,   0ull},
48200         {"UMSK8"                       ,        0,      8,      296,    "R/W",  0,      0,      0ull,   0ull},
48201         {"UMSK9"                       ,        8,      8,      296,    "R/W",  0,      0,      0ull,   0ull},
48202         {"UMSK10"                      ,        16,     8,      296,    "R/W",  0,      0,      0ull,   0ull},
48203         {"UMSK11"                      ,        24,     8,      296,    "R/W",  0,      0,      0ull,   0ull},
48204         {"RESERVED_32_63"              ,        32,     32,     296,    "RAZ",  0,      0,      0ull,   0ull},
48205         {"UMSKIOB"                     ,        0,      8,      297,    "R/W",  0,      0,      0ull,   0ull},
48206         {"RESERVED_8_63"               ,        8,      56,     297,    "RAZ",  0,      0,      0ull,   0ull},
48207         {"Q0STAT"                      ,        0,      34,     298,    "RO",   0,      0,      0ull,   0ull},
48208         {"FTL"                         ,        34,     1,      298,    "RO",   0,      0,      0ull,   0ull},
48209         {"RESERVED_35_63"              ,        35,     29,     298,    "RAZ",  0,      0,      0ull,   0ull},
48210         {"Q1STAT"                      ,        0,      34,     299,    "RO",   0,      0,      0ull,   0ull},
48211         {"RESERVED_34_63"              ,        34,     30,     299,    "RAZ",  0,      0,      0ull,   0ull},
48212         {"Q2STAT"                      ,        0,      34,     300,    "RO",   0,      0,      0ull,   0ull},
48213         {"RESERVED_34_63"              ,        34,     30,     300,    "RAZ",  0,      0,      0ull,   0ull},
48214         {"Q3STAT"                      ,        0,      34,     301,    "RO",   0,      0,      0ull,   0ull},
48215         {"RESERVED_34_63"              ,        34,     30,     301,    "RAZ",  0,      0,      0ull,   0ull},
48216         {"ECC_ENA"                     ,        0,      1,      302,    "R/W",  0,      0,      0ull,   1ull},
48217         {"SEC_INTENA"                  ,        1,      1,      302,    "R/W",  0,      0,      0ull,   1ull},
48218         {"DED_INTENA"                  ,        2,      1,      302,    "R/W",  0,      0,      0ull,   1ull},
48219         {"SEC_ERR"                     ,        3,      1,      302,    "R/W1C",        0,      0,      0ull,   0ull},
48220         {"DED_ERR"                     ,        4,      1,      302,    "R/W1C",        0,      0,      0ull,   0ull},
48221         {"BMHCLSEL"                    ,        5,      1,      302,    "R/W",  0,      0,      0ull,   0ull},
48222         {"RESERVED_6_63"               ,        6,      58,     302,    "RAZ",  0,      0,      0ull,   0ull},
48223         {"FADR"                        ,        0,      11,     303,    "RO",   0,      0,      0ull,   0ull},
48224         {"FSET"                        ,        11,     3,      303,    "RO",   0,      0,      0ull,   0ull},
48225         {"FOWMSK"                      ,        14,     4,      303,    "RO",   0,      0,      0ull,   0ull},
48226         {"FADRU"                       ,        18,     1,      303,    "RO",   0,      0,      0ull,   0ull},
48227         {"RESERVED_19_63"              ,        19,     45,     303,    "RAZ",  0,      0,      0ull,   0ull},
48228         {"FSYN_OW0"                    ,        0,      10,     304,    "RO",   0,      0,      0ull,   0ull},
48229         {"FSYN_OW1"                    ,        10,     10,     304,    "RO",   0,      0,      0ull,   0ull},
48230         {"RESERVED_20_63"              ,        20,     44,     304,    "RAZ",  0,      0,      0ull,   0ull},
48231         {"FSYN_OW2"                    ,        0,      10,     305,    "RO",   0,      0,      0ull,   0ull},
48232         {"FSYN_OW3"                    ,        10,     10,     305,    "RO",   0,      0,      0ull,   0ull},
48233         {"RESERVED_20_63"              ,        20,     44,     305,    "RAZ",  0,      0,      0ull,   0ull},
48234         {"Q0FUS"                       ,        0,      34,     306,    "RO",   0,      0,      0ull,   0ull},
48235         {"RESERVED_34_63"              ,        34,     30,     306,    "RAZ",  0,      0,      0ull,   0ull},
48236         {"Q1FUS"                       ,        0,      34,     307,    "RO",   0,      0,      0ull,   0ull},
48237         {"RESERVED_34_63"              ,        34,     30,     307,    "RAZ",  0,      0,      0ull,   0ull},
48238         {"Q2FUS"                       ,        0,      34,     308,    "RO",   0,      0,      0ull,   0ull},
48239         {"RESERVED_34_63"              ,        34,     30,     308,    "RAZ",  0,      0,      0ull,   0ull},
48240         {"Q3FUS"                       ,        0,      34,     309,    "RO",   0,      0,      0ull,   0ull},
48241         {"CRIP_1024K"                  ,        34,     1,      309,    "RO",   0,      0,      0ull,   0ull},
48242         {"CRIP_512K"                   ,        35,     1,      309,    "RO",   0,      0,      0ull,   0ull},
48243         {"RESERVED_36_36"              ,        36,     1,      309,    "RAZ",  0,      0,      0ull,   0ull},
48244         {"EMA_CTL"                     ,        37,     3,      309,    "RO",   0,      0,      0ull,   0ull},
48245         {"RESERVED_40_63"              ,        40,     24,     309,    "RAZ",  0,      0,      0ull,   0ull},
48246         {"ECC_ENA"                     ,        0,      1,      310,    "R/W",  0,      0,      0ull,   1ull},
48247         {"SEC_INTENA"                  ,        1,      1,      310,    "R/W",  0,      0,      0ull,   1ull},
48248         {"DED_INTENA"                  ,        2,      1,      310,    "R/W",  0,      0,      0ull,   1ull},
48249         {"SEC_ERR"                     ,        3,      1,      310,    "R/W1C",        0,      0,      0ull,   0ull},
48250         {"DED_ERR"                     ,        4,      1,      310,    "R/W1C",        0,      0,      0ull,   0ull},
48251         {"FSYN"                        ,        5,      6,      310,    "RO",   0,      0,      0ull,   0ull},
48252         {"FADR"                        ,        11,     10,     310,    "RO",   0,      0,      0ull,   0ull},
48253         {"FSET"                        ,        21,     3,      310,    "RO",   0,      0,      0ull,   0ull},
48254         {"LCKERR"                      ,        24,     1,      310,    "R/W1C",        0,      0,      0ull,   0ull},
48255         {"LCK_INTENA"                  ,        25,     1,      310,    "R/W",  0,      0,      0ull,   1ull},
48256         {"LCKERR2"                     ,        26,     1,      310,    "R/W1C",        0,      0,      0ull,   0ull},
48257         {"LCK_INTENA2"                 ,        27,     1,      310,    "R/W",  0,      0,      0ull,   1ull},
48258         {"FADRU"                       ,        28,     1,      310,    "RO",   0,      0,      0ull,   0ull},
48259         {"RESERVED_29_63"              ,        29,     35,     310,    "RAZ",  0,      0,      0ull,   0ull},
48260         {"RATE"                        ,        0,      8,      311,    "R/W",  0,      0,      4ull,   4ull},
48261         {"RESERVED_8_63"               ,        8,      56,     311,    "RAZ",  1,      1,      0,      0},
48262         {"PHASE"                       ,        0,      7,      312,    "R/W",  0,      0,      4ull,   4ull},
48263         {"RESERVED_7_63"               ,        7,      57,     312,    "RAZ",  1,      1,      0,      0},
48264         {"RATE"                        ,        0,      16,     313,    "R/W",  0,      0,      0ull,   0ull},
48265         {"RESERVED_16_63"              ,        16,     48,     313,    "RAZ",  1,      1,      0,      0},
48266         {"DBG_EN"                      ,        0,      1,      314,    "R/W",  0,      0,      0ull,   0ull},
48267         {"RESERVED_1_63"               ,        1,      63,     314,    "RAZ",  1,      1,      0,      0},
48268         {"EN"                          ,        0,      1,      315,    "R/W",  0,      0,      0ull,   1ull},
48269         {"RESERVED_1_63"               ,        1,      63,     315,    "RAZ",  1,      1,      0,      0},
48270         {"POLARITY"                    ,        0,      1,      316,    "R/W",  0,      0,      0ull,   0ull},
48271         {"RESERVED_1_63"               ,        1,      63,     316,    "RAZ",  1,      1,      0,      0},
48272         {"PRT_EN"                      ,        0,      8,      317,    "R/W",  0,      1,      0ull,   0},
48273         {"RESERVED_8_63"               ,        8,      56,     317,    "RAZ",  1,      1,      0,      0},
48274         {"FORMAT"                      ,        0,      4,      318,    "R/W",  0,      1,      0ull,   0},
48275         {"RESERVED_4_63"               ,        4,      60,     318,    "RAZ",  1,      1,      0,      0},
48276         {"STATUS"                      ,        0,      6,      319,    "R/W",  0,      0,      0ull,   0ull},
48277         {"RESERVED_6_63"               ,        6,      58,     319,    "RAZ",  1,      1,      0,      0},
48278         {"CNT"                         ,        0,      6,      320,    "R/W",  0,      0,      0ull,   0ull},
48279         {"RESERVED_6_63"               ,        6,      58,     320,    "RAZ",  1,      1,      0,      0},
48280         {"DAT"                         ,        0,      32,     321,    "R/W",  0,      1,      0ull,   0},
48281         {"RESERVED_32_63"              ,        32,     32,     321,    "RAZ",  1,      1,      0,      0},
48282         {"CLR"                         ,        0,      32,     322,    "WO",   0,      1,      0ull,   0},
48283         {"RESERVED_32_63"              ,        32,     32,     322,    "RAZ",  1,      1,      0,      0},
48284         {"SET"                         ,        0,      32,     323,    "WO",   0,      1,      0ull,   0},
48285         {"RESERVED_32_63"              ,        32,     32,     323,    "RAZ",  1,      1,      0,      0},
48286         {"START"                       ,        0,      1,      324,    "R/W",  0,      0,      0ull,   0ull},
48287         {"RESERVED_1_63"               ,        1,      63,     324,    "RAZ",  1,      0,      0,      0ull},
48288         {"MRD"                         ,        0,      3,      325,    "RO",   1,      0,      0,      0ull},
48289         {"MRF"                         ,        3,      1,      325,    "RO",   1,      0,      0,      0ull},
48290         {"MWC"                         ,        4,      1,      325,    "RO",   1,      0,      0,      0ull},
48291         {"MWD"                         ,        5,      3,      325,    "RO",   1,      0,      0,      0ull},
48292         {"MWF"                         ,        8,      1,      325,    "RO",   1,      0,      0,      0ull},
48293         {"CSRE2D"                      ,        9,      1,      325,    "RO",   1,      0,      0,      0ull},
48294         {"CSRD2E"                      ,        10,     1,      325,    "RO",   1,      0,      0,      0ull},
48295         {"RESERVED_11_63"              ,        11,     53,     325,    "RAZ",  1,      0,      0,      0ull},
48296         {"PCTL_DAT"                    ,        0,      5,      326,    "R/W",  0,      1,      0ull,   0},
48297         {"RESERVED_5_11"               ,        5,      7,      326,    "RAZ",  0,      1,      0ull,   0},
48298         {"PCTL_CSR"                    ,        12,     4,      326,    "R/W",  0,      1,      15ull,  0},
48299         {"NCTL_DAT"                    ,        16,     4,      326,    "R/W",  0,      1,      0ull,   0},
48300         {"RESERVED_20_27"              ,        20,     8,      326,    "RAZ",  0,      1,      0ull,   0},
48301         {"NCTL_CSR"                    ,        28,     4,      326,    "R/W",  0,      1,      15ull,  0},
48302         {"RESERVED_32_63"              ,        32,     32,     326,    "RAZ",  0,      0,      0ull,   0ull},
48303         {"DIC"                         ,        0,      2,      327,    "R/W",  0,      0,      0ull,   0ull},
48304         {"QS_DIC"                      ,        2,      2,      327,    "R/W",  0,      0,      2ull,   2ull},
48305         {"TSKW"                        ,        4,      2,      327,    "R/W",  0,      0,      0ull,   1ull},
48306         {"SIL_LAT"                     ,        6,      2,      327,    "R/W",  0,      0,      1ull,   1ull},
48307         {"BPRCH"                       ,        8,      1,      327,    "R/W",  0,      1,      0ull,   0},
48308         {"FPRCH2"                      ,        9,      1,      327,    "R/W",  0,      0,      0ull,   1ull},
48309         {"MODE32B"                     ,        10,     1,      327,    "R/W",  0,      0,      0ull,   0ull},
48310         {"DRESET"                      ,        11,     1,      327,    "R/W",  0,      0,      0ull,   0ull},
48311         {"INORDER_MRF"                 ,        12,     1,      327,    "R/W",  0,      0,      0ull,   0ull},
48312         {"INORDER_MWF"                 ,        13,     1,      327,    "RAZ",  0,      0,      0ull,   0ull},
48313         {"R2R_SLOT"                    ,        14,     1,      327,    "R/W",  0,      0,      0ull,   0ull},
48314         {"RDIMM_ENA"                   ,        15,     1,      327,    "R/W",  0,      1,      0ull,   0},
48315         {"RESERVED_16_17"              ,        16,     2,      327,    "RAZ",  0,      0,      0ull,   0ull},
48316         {"MAX_WRITE_BATCH"             ,        18,     4,      327,    "R/W",  0,      0,      8ull,   8ull},
48317         {"XOR_BANK"                    ,        22,     1,      327,    "R/W",  0,      0,      0ull,   1ull},
48318         {"SLOW_SCF"                    ,        23,     1,      327,    "R/W",  0,      0,      0ull,   0ull},
48319         {"DDR__PCTL"                   ,        24,     4,      327,    "RO",   1,      1,      0,      0},
48320         {"DDR__NCTL"                   ,        28,     4,      327,    "RO",   1,      1,      0,      0},
48321         {"RESERVED_32_63"              ,        32,     32,     327,    "RAZ",  1,      1,      0,      0},
48322         {"RESERVED_0_7"                ,        0,      8,      328,    "RAZ",  0,      1,      0ull,   0},
48323         {"DCC_ENABLE"                  ,        8,      1,      328,    "R/W",  0,      0,      0ull,   0ull},
48324         {"SIL_MODE"                    ,        9,      1,      328,    "R/W",  0,      0,      0ull,   1ull},
48325         {"SEQUENCE"                    ,        10,     3,      328,    "R/W",  0,      0,      0ull,   0ull},
48326         {"IDLEPOWER"                   ,        13,     3,      328,    "R/W",  0,      0,      0ull,   6ull},
48327         {"FORCEWRITE"                  ,        16,     4,      328,    "R/W",  0,      0,      0ull,   0ull},
48328         {"ECC_ADR"                     ,        20,     1,      328,    "R/W",  0,      0,      0ull,   1ull},
48329         {"RESERVED_21_63"              ,        21,     43,     328,    "RAZ",  1,      1,      0,      0},
48330         {"DCLKCNT_HI"                  ,        0,      32,     329,    "RO",   0,      0,      0ull,   0ull},
48331         {"RESERVED_32_63"              ,        32,     32,     329,    "RAZ",  1,      1,      0,      0},
48332         {"DCLKCNT_LO"                  ,        0,      32,     330,    "RO",   0,      0,      0ull,   0ull},
48333         {"RESERVED_32_63"              ,        32,     32,     330,    "RAZ",  1,      1,      0,      0},
48334         {"DCLK90_VLU"                  ,        0,      5,      331,    "R/W",  0,      1,      0ull,   0},
48335         {"DCLK90_LD"                   ,        5,      1,      331,    "R/W",  0,      1,      0ull,   0},
48336         {"DCLK90_BYP"                  ,        6,      1,      331,    "R/W",  0,      1,      0ull,   0},
48337         {"OFF90_ENA"                   ,        7,      1,      331,    "R/W",  0,      1,      0ull,   0},
48338         {"RESERVED_8_63"               ,        8,      56,     331,    "RAZ",  1,      1,      0,      0},
48339         {"DDR2"                        ,        0,      1,      332,    "R/W",  0,      0,      1ull,   1ull},
48340         {"RDQS"                        ,        1,      1,      332,    "R/W",  0,      0,      0ull,   0ull},
48341         {"DLL90_BYP"                   ,        2,      1,      332,    "R/W",  0,      0,      0ull,   0ull},
48342         {"DLL90_VLU"                   ,        3,      5,      332,    "R/W",  0,      1,      0ull,   0},
48343         {"QDLL_ENA"                    ,        8,      1,      332,    "R/W",  0,      0,      0ull,   0ull},
48344         {"ODT_ENA"                     ,        9,      1,      332,    "R/W",  0,      0,      0ull,   0ull},
48345         {"DDR2T"                       ,        10,     1,      332,    "R/W",  0,      1,      0ull,   0},
48346         {"CRIP_MODE"                   ,        11,     1,      332,    "R/W",  0,      0,      0ull,   0ull},
48347         {"TFAW"                        ,        12,     5,      332,    "R/W",  0,      0,      0ull,   9ull},
48348         {"DDR_EOF"                     ,        17,     4,      332,    "R/W",  0,      0,      0ull,   0ull},
48349         {"SILO_HC"                     ,        21,     1,      332,    "R/W",  0,      1,      1ull,   0},
48350         {"TWR"                         ,        22,     3,      332,    "R/W",  0,      0,      3ull,   1ull},
48351         {"BWCNT"                       ,        25,     1,      332,    "R/W",  0,      0,      0ull,   0ull},
48352         {"POCAS"                       ,        26,     1,      332,    "R/W",  0,      0,      0ull,   0ull},
48353         {"ADDLAT"                      ,        27,     3,      332,    "R/W",  0,      0,      0ull,   0ull},
48354         {"BURST8"                      ,        30,     1,      332,    "R/W",  0,      0,      0ull,   1ull},
48355         {"BANK8"                       ,        31,     1,      332,    "R/W",  0,      1,      0ull,   0},
48356         {"RESERVED_32_63"              ,        32,     32,     332,    "RAZ",  0,      0,      0ull,   0ull},
48357         {"CLK"                         ,        0,      4,      333,    "R/W",  0,      0,      0ull,   0ull},
48358         {"RESERVED_4_4"                ,        4,      1,      333,    "RAZ",  0,      0,      0ull,   0ull},
48359         {"CMD"                         ,        5,      4,      333,    "R/W",  0,      0,      0ull,   0ull},
48360         {"RESERVED_9_9"                ,        9,      1,      333,    "RAZ",  0,      0,      0ull,   0ull},
48361         {"DQ"                          ,        10,     4,      333,    "R/W",  0,      0,      0ull,   0ull},
48362         {"RESERVED_14_63"              ,        14,     50,     333,    "RAZ",  0,      0,      0ull,   0ull},
48363         {"DLL90_VLU"                   ,        0,      5,      334,    "R/W",  0,      1,      0ull,   0},
48364         {"DLL90_ENA"                   ,        5,      1,      334,    "R/W",  0,      0,      0ull,   0ull},
48365         {"DLL90_BYP"                   ,        6,      1,      334,    "R/W",  0,      0,      0ull,   0ull},
48366         {"DRESET"                      ,        7,      1,      334,    "R/W",  0,      0,      1ull,   0ull},
48367         {"RESERVED_8_63"               ,        8,      56,     334,    "RAZ",  1,      1,      0,      0},
48368         {"CS_MASK"                     ,        0,      8,      335,    "R/W",  0,      1,      0ull,   0},
48369         {"RESERVED_8_15"               ,        8,      8,      335,    "RAZ",  0,      1,      0ull,   0},
48370         {"ROW_LSB"                     ,        16,     3,      335,    "R/W",  0,      1,      3ull,   0},
48371         {"BANK8"                       ,        19,     1,      335,    "R/W",  0,      1,      0ull,   0},
48372         {"RESERVED_20_63"              ,        20,     44,     335,    "RAZ",  0,      1,      0ull,   0},
48373         {"MRDSYN0"                     ,        0,      8,      336,    "RO",   0,      0,      0ull,   0ull},
48374         {"MRDSYN1"                     ,        8,      8,      336,    "RO",   0,      0,      0ull,   0ull},
48375         {"MRDSYN2"                     ,        16,     8,      336,    "RO",   0,      0,      0ull,   0ull},
48376         {"MRDSYN3"                     ,        24,     8,      336,    "RO",   0,      0,      0ull,   0ull},
48377         {"RESERVED_32_63"              ,        32,     32,     336,    "RAZ",  1,      1,      0,      0},
48378         {"FCOL"                        ,        0,      12,     337,    "RO",   0,      0,      0ull,   0ull},
48379         {"FROW"                        ,        12,     14,     337,    "RO",   0,      0,      0ull,   0ull},
48380         {"FBANK"                       ,        26,     3,      337,    "RO",   0,      0,      0ull,   0ull},
48381         {"FBUNK"                       ,        29,     1,      337,    "RO",   0,      0,      0ull,   0ull},
48382         {"FDIMM"                       ,        30,     2,      337,    "RO",   0,      0,      0ull,   0ull},
48383         {"RESERVED_32_63"              ,        32,     32,     337,    "RAZ",  1,      1,      0,      0},
48384         {"IFBCNT_HI"                   ,        0,      32,     338,    "RO",   0,      0,      0ull,   0ull},
48385         {"RESERVED_32_63"              ,        32,     32,     338,    "RAZ",  1,      1,      0,      0},
48386         {"IFBCNT_LO"                   ,        0,      32,     339,    "RO",   0,      0,      0ull,   0ull},
48387         {"RESERVED_32_63"              ,        32,     32,     339,    "RAZ",  1,      1,      0,      0},
48388         {"INIT_START"                  ,        0,      1,      340,    "WR0",  0,      0,      0ull,   0ull},
48389         {"ECC_ENA"                     ,        1,      1,      340,    "R/W",  0,      0,      0ull,   1ull},
48390         {"ROW_LSB"                     ,        2,      3,      340,    "R/W",  0,      1,      3ull,   0},
48391         {"PBANK_LSB"                   ,        5,      4,      340,    "R/W",  0,      1,      5ull,   0},
48392         {"REF_INT"                     ,        9,      6,      340,    "R/W",  0,      0,      1ull,   2ull},
48393         {"TCL"                         ,        15,     4,      340,    "R/W",  0,      1,      3ull,   0},
48394         {"INTR_SEC_ENA"                ,        19,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
48395         {"INTR_DED_ENA"                ,        20,     1,      340,    "R/W",  0,      0,      0ull,   1ull},
48396         {"SEC_ERR"                     ,        21,     4,      340,    "R/W1C",        0,      0,      0ull,   0ull},
48397         {"DED_ERR"                     ,        25,     4,      340,    "R/W1C",        0,      0,      0ull,   0ull},
48398         {"BUNK_ENA"                    ,        29,     1,      340,    "R/W",  0,      1,      0ull,   0},
48399         {"SILO_QC"                     ,        30,     1,      340,    "R/W",  0,      1,      0ull,   0},
48400         {"RESET"                       ,        31,     1,      340,    "RAZ",  1,      1,      0,      0},
48401         {"RESERVED_32_63"              ,        32,     32,     340,    "RAZ",  1,      1,      0,      0},
48402         {"TRAS"                        ,        0,      5,      341,    "R/W",  0,      0,      12ull,  12ull},
48403         {"TRCD"                        ,        5,      4,      341,    "R/W",  0,      0,      4ull,   4ull},
48404         {"TWTR"                        ,        9,      4,      341,    "R/W",  0,      0,      2ull,   2ull},
48405         {"TRP"                         ,        13,     4,      341,    "R/W",  0,      0,      5ull,   4ull},
48406         {"TRFC"                        ,        17,     5,      341,    "R/W",  0,      0,      6ull,   7ull},
48407         {"TMRD"                        ,        22,     3,      341,    "R/W",  0,      0,      2ull,   2ull},
48408         {"CASLAT"                      ,        25,     3,      341,    "R/W",  0,      0,      4ull,   4ull},
48409         {"TRRD"                        ,        28,     3,      341,    "R/W",  0,      0,      2ull,   2ull},
48410         {"RESERVED_31_63"              ,        31,     33,     341,    "RAZ",  1,      1,      0,      0},
48411         {"CS_MASK"                     ,        0,      8,      342,    "R/W",  0,      1,      0ull,   0},
48412         {"RESERVED_8_63"               ,        8,      56,     342,    "RAZ",  1,      1,      0,      0},
48413         {"OPSCNT_HI"                   ,        0,      32,     343,    "RO",   0,      0,      0ull,   0ull},
48414         {"RESERVED_32_63"              ,        32,     32,     343,    "RAZ",  1,      1,      0,      0},
48415         {"OPSCNT_LO"                   ,        0,      32,     344,    "RO",   0,      0,      0ull,   0ull},
48416         {"RESERVED_32_63"              ,        32,     32,     344,    "RAZ",  1,      1,      0,      0},
48417         {"EN2"                         ,        0,      1,      345,    "R/W",  0,      1,      0ull,   0},
48418         {"EN4"                         ,        1,      1,      345,    "R/W",  0,      1,      0ull,   0},
48419         {"EN6"                         ,        2,      1,      345,    "R/W",  0,      1,      0ull,   0},
48420         {"EN8"                         ,        3,      1,      345,    "R/W",  0,      1,      1ull,   0},
48421         {"EN12"                        ,        4,      1,      345,    "R/W",  0,      1,      0ull,   0},
48422         {"EN16"                        ,        5,      1,      345,    "R/W",  0,      1,      0ull,   0},
48423         {"RESERVED_6_7"                ,        6,      2,      345,    "RAZ",  0,      1,      0ull,   0},
48424         {"CLKR"                        ,        8,      6,      345,    "R/W",  0,      1,      0ull,   0},
48425         {"CLKF"                        ,        14,     12,     345,    "R/W",  0,      1,      31ull,  0},
48426         {"RESET_N"                     ,        26,     1,      345,    "R/W",  0,      0,      0ull,   1ull},
48427         {"DIV_RESET"                   ,        27,     1,      345,    "R/W",  0,      0,      1ull,   0ull},
48428         {"FASTEN_N"                    ,        28,     1,      345,    "R/W",  0,      0,      0ull,   1ull},
48429         {"RESERVED_29_63"              ,        29,     35,     345,    "RAZ",  0,      1,      0ull,   0},
48430         {"FBSLIP"                      ,        0,      1,      346,    "R/W1C",        0,      1,      0ull,   0},
48431         {"RFSLIP"                      ,        1,      1,      346,    "R/W1C",        0,      1,      0ull,   0},
48432         {"RESERVED_2_21"               ,        2,      20,     346,    "RAZ",  1,      1,      0,      0},
48433         {"DDR__PCTL"                   ,        22,     5,      346,    "RO",   1,      1,      0,      0},
48434         {"DDR__NCTL"                   ,        27,     5,      346,    "RO",   1,      1,      0,      0},
48435         {"RESERVED_32_63"              ,        32,     32,     346,    "RAZ",  1,      1,      0,      0},
48436         {"BNK"                         ,        0,      3,      347,    "R/W",  0,      0,      0ull,   0ull},
48437         {"RESERVED_3_3"                ,        3,      1,      347,    "RAZ",  0,      0,      0ull,   0ull},
48438         {"COL"                         ,        4,      12,     347,    "R/W",  0,      0,      0ull,   0ull},
48439         {"ROW"                         ,        16,     16,     347,    "R/W",  0,      0,      0ull,   0ull},
48440         {"PATTERN"                     ,        32,     8,      347,    "R/W",  0,      0,      170ull, 170ull},
48441         {"RANKMASK"                    ,        40,     4,      347,    "R/W",  0,      0,      0ull,   0ull},
48442         {"RESERVED_44_63"              ,        44,     20,     347,    "RAZ",  0,      0,      0ull,   0ull},
48443         {"BYTE"                        ,        0,      4,      348,    "R/W",  0,      0,      0ull,   0ull},
48444         {"RESERVED_4_15"               ,        4,      12,     348,    "RAZ",  0,      0,      0ull,   0ull},
48445         {"BITMASK"                     ,        16,     16,     348,    "RO",   0,      0,      0ull,   0ull},
48446         {"RESERVED_32_63"              ,        32,     32,     348,    "RAZ",  0,      0,      0ull,   0ull},
48447         {"BYTE0"                       ,        0,      4,      349,    "R/W",  0,      1,      0ull,   0},
48448         {"BYTE1"                       ,        4,      4,      349,    "R/W",  0,      1,      0ull,   0},
48449         {"BYTE2"                       ,        8,      4,      349,    "R/W",  0,      1,      0ull,   0},
48450         {"BYTE3"                       ,        12,     4,      349,    "R/W",  0,      1,      0ull,   0},
48451         {"BYTE4"                       ,        16,     4,      349,    "R/W",  0,      1,      0ull,   0},
48452         {"BYTE5"                       ,        20,     4,      349,    "R/W",  0,      1,      0ull,   0},
48453         {"BYTE6"                       ,        24,     4,      349,    "R/W",  0,      1,      0ull,   0},
48454         {"BYTE7"                       ,        28,     4,      349,    "R/W",  0,      1,      0ull,   0},
48455         {"BYTE8"                       ,        32,     4,      349,    "R/W",  0,      1,      0ull,   0},
48456         {"STATUS"                      ,        36,     2,      349,    "RO",   0,      1,      0ull,   0},
48457         {"RESERVED_38_63"              ,        38,     26,     349,    "RAZ",  1,      0,      0,      0ull},
48458         {"PCTL"                        ,        0,      5,      350,    "R/W",  0,      1,      0ull,   0},
48459         {"RESERVED_5_7"                ,        5,      3,      350,    "RAZ",  0,      1,      0ull,   0},
48460         {"NCTL"                        ,        8,      4,      350,    "R/W",  0,      1,      0ull,   0},
48461         {"RESERVED_12_15"              ,        12,     4,      350,    "RAZ",  0,      1,      0ull,   0},
48462         {"ENABLE"                      ,        16,     1,      350,    "R/W",  0,      1,      0ull,   0},
48463         {"RESERVED_17_63"              ,        17,     47,     350,    "RAZ",  0,      1,      0ull,   0},
48464         {"RODT_LO0"                    ,        0,      4,      351,    "R/W",  0,      0,      15ull,  15ull},
48465         {"RODT_LO1"                    ,        4,      4,      351,    "R/W",  0,      0,      15ull,  15ull},
48466         {"RODT_LO2"                    ,        8,      4,      351,    "R/W",  0,      0,      15ull,  15ull},
48467         {"RODT_LO3"                    ,        12,     4,      351,    "R/W",  0,      0,      15ull,  15ull},
48468         {"RODT_HI0"                    ,        16,     4,      351,    "R/W",  0,      0,      15ull,  15ull},
48469         {"RODT_HI1"                    ,        20,     4,      351,    "R/W",  0,      0,      15ull,  15ull},
48470         {"RODT_HI2"                    ,        24,     4,      351,    "R/W",  0,      0,      15ull,  15ull},
48471         {"RODT_HI3"                    ,        28,     4,      351,    "R/W",  0,      0,      15ull,  15ull},
48472         {"RESERVED_32_63"              ,        32,     32,     351,    "RAZ",  1,      1,      0,      0},
48473         {"WODT_D0_R0"                  ,        0,      8,      352,    "R/W",  0,      0,      255ull, 255ull},
48474         {"WODT_D0_R1"                  ,        8,      8,      352,    "R/W",  0,      0,      255ull, 255ull},
48475         {"WODT_D1_R0"                  ,        16,     8,      352,    "R/W",  0,      0,      255ull, 255ull},
48476         {"WODT_D1_R1"                  ,        24,     8,      352,    "R/W",  0,      0,      255ull, 255ull},
48477         {"RESERVED_32_63"              ,        32,     32,     352,    "RAZ",  0,      0,      0ull,   0ull},
48478         {"WODT_D2_R0"                  ,        0,      8,      353,    "R/W",  0,      0,      255ull, 255ull},
48479         {"WODT_D2_R1"                  ,        8,      8,      353,    "R/W",  0,      0,      255ull, 255ull},
48480         {"WODT_D3_R0"                  ,        16,     8,      353,    "R/W",  0,      0,      255ull, 255ull},
48481         {"WODT_D3_R1"                  ,        24,     8,      353,    "R/W",  0,      0,      255ull, 255ull},
48482         {"RESERVED_32_63"              ,        32,     32,     353,    "RAZ",  0,      0,      0ull,   0ull},
48483         {"NCBI"                        ,        0,      1,      354,    "RO",   0,      0,      0ull,   0ull},
48484         {"LOC"                         ,        1,      1,      354,    "RO",   0,      0,      0ull,   0ull},
48485         {"DMA"                         ,        2,      1,      354,    "RO",   0,      0,      0ull,   0ull},
48486         {"NCBO_0"                      ,        3,      1,      354,    "RO",   0,      0,      0ull,   0ull},
48487         {"RESERVED_4_63"               ,        4,      60,     354,    "RAZ",  1,      1,      0,      0},
48488         {"NCTL"                        ,        0,      5,      355,    "R/W",  1,      1,      0,      0},
48489         {"PCTL"                        ,        5,      5,      355,    "R/W",  1,      1,      0,      0},
48490         {"RESERVED_10_63"              ,        10,     54,     355,    "RAZ",  1,      1,      0,      0},
48491         {"ADR"                         ,        0,      36,     356,    "R/W",  0,      1,      0ull,   0},
48492         {"SIZE"                        ,        36,     20,     356,    "R/W",  0,      1,      0ull,   0},
48493         {"ENDIAN"                      ,        56,     1,      356,    "R/W",  0,      1,      0ull,   0},
48494         {"SWAP8"                       ,        57,     1,      356,    "R/W",  0,      1,      0ull,   0},
48495         {"SWAP16"                      ,        58,     1,      356,    "R/W",  0,      1,      0ull,   0},
48496         {"SWAP32"                      ,        59,     1,      356,    "R/W",  0,      1,      0ull,   0},
48497         {"RESERVED_60_60"              ,        60,     1,      356,    "RAZ",  1,      1,      0,      0},
48498         {"CLR"                         ,        61,     1,      356,    "R/W",  0,      1,      0ull,   0},
48499         {"RW"                          ,        62,     1,      356,    "R/W",  0,      1,      0ull,   0},
48500         {"EN"                          ,        63,     1,      356,    "R/W",  0,      1,      0ull,   0},
48501         {"DONE"                        ,        0,      1,      357,    "R/W1C",        0,      1,      0ull,   0},
48502         {"DMARQ"                       ,        1,      1,      357,    "RO",   1,      1,      0,      0},
48503         {"RESERVED_2_63"               ,        2,      62,     357,    "RAZ",  1,      1,      0,      0},
48504         {"DONE"                        ,        0,      1,      358,    "R/W",  0,      1,      0ull,   0},
48505         {"DMARQ"                       ,        1,      1,      358,    "R/W",  0,      1,      0ull,   0},
48506         {"RESERVED_2_63"               ,        2,      62,     358,    "RAZ",  1,      1,      0,      0},
48507         {"DMARQ"                       ,        0,      6,      359,    "R/W",  0,      1,      63ull,  0},
48508         {"DMACK_S"                     ,        6,      6,      359,    "R/W",  0,      1,      63ull,  0},
48509         {"OE_A"                        ,        12,     6,      359,    "R/W",  0,      1,      63ull,  0},
48510         {"OE_N"                        ,        18,     6,      359,    "R/W",  0,      1,      63ull,  0},
48511         {"WE_A"                        ,        24,     6,      359,    "R/W",  0,      1,      63ull,  0},
48512         {"WE_N"                        ,        30,     6,      359,    "R/W",  0,      1,      63ull,  0},
48513         {"DMACK_H"                     ,        36,     6,      359,    "R/W",  0,      1,      63ull,  0},
48514         {"PAUSE"                       ,        42,     6,      359,    "R/W",  0,      1,      63ull,  0},
48515         {"RESERVED_48_54"              ,        48,     7,      359,    "RAZ",  1,      1,      0,      0},
48516         {"WIDTH"                       ,        55,     1,      359,    "R/W",  0,      1,      0ull,   0},
48517         {"DDR"                         ,        56,     1,      359,    "R/W",  0,      1,      0ull,   0},
48518         {"RD_DLY"                      ,        57,     3,      359,    "R/W",  0,      1,      0ull,   0},
48519         {"TIM_MULT"                    ,        60,     2,      359,    "R/W",  0,      1,      0ull,   0},
48520         {"DMARQ_PI"                    ,        62,     1,      359,    "R/W",  0,      1,      0ull,   0},
48521         {"DMACK_PI"                    ,        63,     1,      359,    "R/W",  0,      1,      0ull,   0},
48522         {"ADR_ERR"                     ,        0,      1,      360,    "R/W1C",        0,      0,      0ull,   0ull},
48523         {"WAIT_ERR"                    ,        1,      1,      360,    "R/W1C",        0,      0,      0ull,   0ull},
48524         {"RESERVED_2_63"               ,        2,      62,     360,    "RAZ",  1,      1,      0,      0},
48525         {"ADR_INT"                     ,        0,      1,      361,    "R/W",  0,      1,      0ull,   0},
48526         {"WAIT_INT"                    ,        1,      1,      361,    "R/W",  0,      1,      0ull,   0},
48527         {"RESERVED_2_63"               ,        2,      62,     361,    "RAZ",  1,      1,      0,      0},
48528         {"RESERVED_0_2"                ,        0,      3,      362,    "RAZ",  1,      1,      0,      0},
48529         {"ADR"                         ,        3,      5,      362,    "R/W",  0,      1,      0ull,   0},
48530         {"RESERVED_8_63"               ,        8,      56,     362,    "RAZ",  1,      1,      0,      0},
48531         {"RESERVED_0_2"                ,        0,      3,      363,    "RAZ",  1,      1,      0,      0},
48532         {"BASE"                        ,        3,      25,     363,    "R/W",  0,      1,      0ull,   0},
48533         {"RESERVED_28_30"              ,        28,     3,      363,    "RAZ",  1,      1,      0,      0},
48534         {"EN"                          ,        31,     1,      363,    "R/W",  0,      1,      0ull,   0},
48535         {"RESERVED_32_63"              ,        32,     32,     363,    "RAZ",  1,      1,      0,      0},
48536         {"DATA"                        ,        0,      64,     364,    "R/W",  1,      1,      0,      0},
48537         {"RESERVED_0_8"                ,        0,      9,      365,    "RAZ",  1,      1,      0,      0},
48538         {"TERM"                        ,        9,      2,      365,    "RO",   1,      1,      0,      0},
48539         {"DMACK_P0"                    ,        11,     1,      365,    "RO",   1,      1,      0,      0},
48540         {"DMACK_P1"                    ,        12,     1,      365,    "RO",   1,      1,      0,      0},
48541         {"DMACK_P2"                    ,        13,     1,      365,    "RO",   1,      1,      0,      0},
48542         {"WIDTH"                       ,        14,     1,      365,    "RO",   1,      1,      0,      0},
48543         {"ALE"                         ,        15,     1,      365,    "RO",   1,      1,      0,      0},
48544         {"RESERVED_16_63"              ,        16,     48,     365,    "RAZ",  1,      1,      0,      0},
48545         {"BASE"                        ,        0,      16,     366,    "R/W",  0,      1,      0ull,   0},
48546         {"SIZE"                        ,        16,     12,     366,    "R/W",  0,      1,      0ull,   0},
48547         {"WIDTH"                       ,        28,     1,      366,    "R/W",  0,      1,      0ull,   0},
48548         {"ALE"                         ,        29,     1,      366,    "R/W",  0,      1,      0ull,   0},
48549         {"ORBIT"                       ,        30,     1,      366,    "R/W",  0,      1,      0ull,   0},
48550         {"EN"                          ,        31,     1,      366,    "R/W",  0,      1,      0ull,   0},
48551         {"OE_EXT"                      ,        32,     2,      366,    "R/W",  0,      1,      0ull,   0},
48552         {"WE_EXT"                      ,        34,     2,      366,    "R/W",  0,      1,      0ull,   0},
48553         {"SAM"                         ,        36,     1,      366,    "R/W",  0,      1,      0ull,   0},
48554         {"RD_DLY"                      ,        37,     3,      366,    "R/W",  0,      1,      0ull,   0},
48555         {"TIM_MULT"                    ,        40,     2,      366,    "R/W",  0,      1,      0ull,   0},
48556         {"DMACK"                       ,        42,     2,      366,    "R/W",  0,      1,      0ull,   0},
48557         {"RESERVED_44_63"              ,        44,     20,     366,    "RAZ",  1,      1,      0,      0},
48558         {"ADR"                         ,        0,      6,      367,    "R/W",  0,      1,      63ull,  0},
48559         {"CE"                          ,        6,      6,      367,    "R/W",  0,      1,      63ull,  0},
48560         {"OE"                          ,        12,     6,      367,    "R/W",  0,      1,      63ull,  0},
48561         {"WE"                          ,        18,     6,      367,    "R/W",  0,      1,      63ull,  0},
48562         {"RD_HLD"                      ,        24,     6,      367,    "R/W",  0,      1,      63ull,  0},
48563         {"WR_HLD"                      ,        30,     6,      367,    "R/W",  0,      1,      63ull,  0},
48564         {"PAUSE"                       ,        36,     6,      367,    "R/W",  0,      1,      63ull,  0},
48565         {"WAIT"                        ,        42,     6,      367,    "R/W",  0,      1,      63ull,  0},
48566         {"PAGE"                        ,        48,     6,      367,    "R/W",  0,      1,      63ull,  0},
48567         {"ALE"                         ,        54,     6,      367,    "R/W",  0,      1,      63ull,  0},
48568         {"PAGES"                       ,        60,     2,      367,    "R/W",  0,      1,      0ull,   0},
48569         {"WAITM"                       ,        62,     1,      367,    "R/W",  0,      1,      0ull,   0},
48570         {"PAGEM"                       ,        63,     1,      367,    "R/W",  0,      1,      0ull,   0},
48571         {"FIF_THR"                     ,        0,      6,      368,    "R/W",  0,      0,      26ull,  26ull},
48572         {"RESERVED_6_7"                ,        6,      2,      368,    "RAZ",  1,      1,      0,      0},
48573         {"FIF_CNT"                     ,        8,      6,      368,    "RO",   0,      1,      0ull,   0},
48574         {"RESERVED_14_15"              ,        14,     2,      368,    "RAZ",  1,      1,      0,      0},
48575         {"DMA_THR"                     ,        16,     6,      368,    "R/W",  0,      1,      0ull,   0},
48576         {"RESERVED_22_63"              ,        22,     42,     368,    "RAZ",  1,      1,      0,      0},
48577         {"DAT"                         ,        0,      64,     369,    "R/W",  1,      1,      0,      0},
48578         {"MAN_INFO"                    ,        0,      32,     370,    "RO",   1,      1,      0,      0},
48579         {"RESERVED_32_63"              ,        32,     32,     370,    "RAZ",  1,      1,      0,      0},
48580         {"MAN_INFO"                    ,        0,      32,     371,    "RO",   1,      1,      0,      0},
48581         {"RESERVED_32_63"              ,        32,     32,     371,    "RAZ",  1,      1,      0,      0},
48582         {"PP_DIS"                      ,        0,      12,     372,    "RO",   1,      1,      0,      0},
48583         {"RESERVED_12_15"              ,        12,     4,      372,    "RO",   1,      1,      0,      0},
48584         {"CHIP_ID"                     ,        16,     8,      372,    "RO",   1,      1,      0,      0},
48585         {"BIST_DIS"                    ,        24,     1,      372,    "RO",   1,      1,      0,      0},
48586         {"RST_SHT"                     ,        25,     1,      372,    "RO",   1,      1,      0,      0},
48587         {"NOCRYPTO"                    ,        26,     1,      372,    "RO",   1,      1,      0,      0},
48588         {"NOMUL"                       ,        27,     1,      372,    "RO",   1,      1,      0,      0},
48589         {"NODFA_CP2"                   ,        28,     1,      372,    "RO",   1,      1,      0,      0},
48590         {"NOKASU"                      ,        29,     1,      372,    "RO",   1,      1,      0,      0},
48591         {"RESERVED_30_31"              ,        30,     2,      372,    "RAZ",  1,      1,      0,      0},
48592         {"RAID_EN"                     ,        32,     1,      372,    "RO",   1,      1,      0,      0},
48593         {"FUS318"                      ,        33,     1,      372,    "RO",   1,      1,      0,      0},
48594         {"RESERVED_34_63"              ,        34,     30,     372,    "RAZ",  1,      1,      0,      0},
48595         {"ICACHE"                      ,        0,      24,     373,    "RO",   1,      1,      0,      0},
48596         {"NODFA_DTE"                   ,        24,     1,      373,    "RO",   1,      1,      0,      0},
48597         {"NOZIP"                       ,        25,     1,      373,    "RO",   1,      1,      0,      0},
48598         {"EFUS_IGN"                    ,        26,     1,      373,    "RO",   1,      1,      0,      0},
48599         {"EFUS_LCK"                    ,        27,     1,      373,    "RO",   1,      1,      0,      0},
48600         {"BAR2_EN"                     ,        28,     1,      373,    "RO",   1,      1,      0,      0},
48601         {"ZIP_CRIP"                    ,        29,     2,      373,    "RO",   1,      1,      0,      0},
48602         {"RESERVED_31_63"              ,        31,     33,     373,    "RAZ",  1,      1,      0,      0},
48603         {"EMA"                         ,        0,      3,      374,    "R/W",  1,      0,      0,      0ull},
48604         {"RESERVED_3_3"                ,        3,      1,      374,    "RAZ",  1,      1,      0,      0},
48605         {"EFF_EMA"                     ,        4,      3,      374,    "RO",   1,      0,      0,      0ull},
48606         {"RESERVED_7_63"               ,        7,      57,     374,    "RAZ",  1,      1,      0,      0},
48607         {"PDF"                         ,        0,      64,     375,    "RO",   1,      1,      0,      0},
48608         {"FBSLIP"                      ,        0,      1,      376,    "R/W1C",        0,      1,      0ull,   0},
48609         {"RFSLIP"                      ,        1,      1,      376,    "R/W1C",        0,      1,      0ull,   0},
48610         {"RESERVED_2_63"               ,        2,      62,     376,    "RAZ",  1,      1,      0,      0},
48611         {"PROG"                        ,        0,      1,      377,    "R/W",  1,      1,      0,      0},
48612         {"RESERVED_1_63"               ,        1,      63,     377,    "RAZ",  1,      1,      0,      0},
48613         {"SETUP"                       ,        0,      8,      378,    "R/W",  0,      1,      3ull,   0},
48614         {"SCLK_HI"                     ,        8,      12,     378,    "R/W",  0,      1,      100ull, 0},
48615         {"SCLK_LO"                     ,        20,     4,      378,    "R/W",  0,      1,      2ull,   0},
48616         {"OUT"                         ,        24,     8,      378,    "R/W",  0,      1,      3ull,   0},
48617         {"PROG_PIN"                    ,        32,     1,      378,    "RO",   0,      0,      0ull,   0ull},
48618         {"RESERVED_33_63"              ,        33,     31,     378,    "RAZ",  1,      1,      0,      0},
48619         {"ADDR"                        ,        0,      8,      379,    "R/W",  0,      0,      0ull,   0ull},
48620         {"EFUSE"                       ,        8,      1,      379,    "R/W",  0,      0,      0ull,   0ull},
48621         {"RESERVED_9_11"               ,        9,      3,      379,    "RAZ",  1,      1,      0,      0},
48622         {"PEND"                        ,        12,     1,      379,    "R/W",  0,      0,      0ull,   0ull},
48623         {"RESERVED_13_15"              ,        13,     3,      379,    "RAZ",  1,      1,      0,      0},
48624         {"DAT"                         ,        16,     8,      379,    "RO",   1,      1,      0,      0},
48625         {"RESERVED_24_63"              ,        24,     40,     379,    "RAZ",  1,      1,      0,      0},
48626         {"REPAIR0"                     ,        0,      14,     380,    "RO",   0,      0,      0ull,   0ull},
48627         {"REPAIR1"                     ,        14,     14,     380,    "RO",   0,      0,      0ull,   0ull},
48628         {"REPAIR2"                     ,        28,     14,     380,    "RO",   0,      0,      0ull,   0ull},
48629         {"RESERVED_42_63"              ,        42,     22,     380,    "RAZ",  1,      1,      0,      0},
48630         {"TOO_MANY"                    ,        0,      1,      381,    "RO",   0,      0,      0ull,   0ull},
48631         {"RESERVED_1_63"               ,        1,      63,     381,    "RAZ",  1,      1,      0,      0},
48632         {"ADDR"                        ,        0,      3,      382,    "R/W",  1,      1,      0,      0},
48633         {"RESERVED_3_63"               ,        3,      61,     382,    "RAZ",  1,      1,      0,      0},
48634         {"ST_INT"                      ,        0,      1,      383,    "R/W1C",        0,      1,      0ull,   0},
48635         {"TS_INT"                      ,        1,      1,      383,    "R/W1C",        0,      1,      0ull,   0},
48636         {"CORE_INT"                    ,        2,      1,      383,    "RO",   0,      1,      0ull,   0},
48637         {"RESERVED_3_3"                ,        3,      1,      383,    "RAZ",  1,      1,      0,      0},
48638         {"ST_EN"                       ,        4,      1,      383,    "R/W",  0,      1,      0ull,   0},
48639         {"TS_EN"                       ,        5,      1,      383,    "R/W",  0,      1,      0ull,   0},
48640         {"CORE_EN"                     ,        6,      1,      383,    "R/W",  0,      1,      0ull,   0},
48641         {"RESERVED_7_7"                ,        7,      1,      383,    "RAZ",  1,      1,      0,      0},
48642         {"SDA_OVR"                     ,        8,      1,      383,    "R/W",  0,      1,      0ull,   0},
48643         {"SCL_OVR"                     ,        9,      1,      383,    "R/W",  0,      1,      0ull,   0},
48644         {"SDA"                         ,        10,     1,      383,    "RO",   1,      1,      0,      0},
48645         {"SCL"                         ,        11,     1,      383,    "RO",   1,      1,      0,      0},
48646         {"RESERVED_12_63"              ,        12,     52,     383,    "RAZ",  1,      1,      0,      0},
48647         {"D"                           ,        0,      32,     384,    "R/W",  0,      1,      0ull,   0},
48648         {"EOP_IA"                      ,        32,     3,      384,    "R/W",  0,      1,      0ull,   0},
48649         {"IA"                          ,        35,     5,      384,    "R/W",  0,      1,      0ull,   0},
48650         {"A"                           ,        40,     10,     384,    "R/W",  0,      1,      0ull,   0},
48651         {"SCR"                         ,        50,     2,      384,    "R/W",  0,      1,      0ull,   0},
48652         {"SIZE"                        ,        52,     3,      384,    "R/W",  0,      1,      0ull,   0},
48653         {"SOVR"                        ,        55,     1,      384,    "R/W",  0,      1,      0ull,   0},
48654         {"R"                           ,        56,     1,      384,    "R/W",  0,      1,      0ull,   0},
48655         {"OP"                          ,        57,     4,      384,    "R/W",  0,      1,      0ull,   0},
48656         {"EIA"                         ,        61,     1,      384,    "R/W",  0,      1,      0ull,   0},
48657         {"SLONLY"                      ,        62,     1,      384,    "R/W",  0,      1,      0ull,   0},
48658         {"V"                           ,        63,     1,      384,    "RC/W", 0,      1,      0ull,   0},
48659         {"D"                           ,        0,      32,     385,    "R/W",  0,      1,      0ull,   0},
48660         {"IA"                          ,        32,     8,      385,    "R/W",  0,      1,      0ull,   0},
48661         {"RESERVED_40_63"              ,        40,     24,     385,    "RAZ",  1,      1,      0,      0},
48662         {"D"                           ,        0,      32,     386,    "R/W",  1,      1,      0,      0},
48663         {"RESERVED_32_61"              ,        32,     30,     386,    "RAZ",  1,      1,      0,      0},
48664         {"V"                           ,        62,     2,      386,    "RC/W", 0,      1,      0ull,   0},
48665         {"DLH"                         ,        0,      8,      387,    "R/W",  0,      1,      0ull,   0},
48666         {"RESERVED_8_63"               ,        8,      56,     387,    "RAZ",  1,      1,      0,      0},
48667         {"DLL"                         ,        0,      8,      388,    "R/W",  0,      1,      0ull,   0},
48668         {"RESERVED_8_63"               ,        8,      56,     388,    "RAZ",  1,      1,      0,      0},
48669         {"FAR"                         ,        0,      1,      389,    "R/W",  0,      1,      0ull,   0},
48670         {"RESERVED_1_63"               ,        1,      63,     389,    "RAZ",  1,      1,      0,      0},
48671         {"EN"                          ,        0,      1,      390,    "WO",   0,      1,      0ull,   0},
48672         {"RXFR"                        ,        1,      1,      390,    "WO",   0,      1,      0ull,   0},
48673         {"TXFR"                        ,        2,      1,      390,    "WO",   0,      1,      0ull,   0},
48674         {"RESERVED_3_3"                ,        3,      1,      390,    "RAZ",  0,      1,      0ull,   0},
48675         {"TXTRIG"                      ,        4,      2,      390,    "WO",   0,      1,      0ull,   0},
48676         {"RXTRIG"                      ,        6,      2,      390,    "WO",   0,      1,      0ull,   0},
48677         {"RESERVED_8_63"               ,        8,      56,     390,    "RAZ",  1,      1,      0,      0},
48678         {"HTX"                         ,        0,      1,      391,    "R/W",  0,      1,      0ull,   0},
48679         {"RESERVED_1_63"               ,        1,      63,     391,    "RAZ",  1,      1,      0,      0},
48680         {"ERBFI"                       ,        0,      1,      392,    "R/W",  0,      1,      0ull,   0},
48681         {"ETBEI"                       ,        1,      1,      392,    "R/W",  0,      1,      0ull,   0},
48682         {"ELSI"                        ,        2,      1,      392,    "R/W",  0,      1,      0ull,   0},
48683         {"EDSSI"                       ,        3,      1,      392,    "R/W",  0,      1,      0ull,   0},
48684         {"RESERVED_4_6"                ,        4,      3,      392,    "RAZ",  0,      1,      0ull,   0},
48685         {"PTIME"                       ,        7,      1,      392,    "R/W",  0,      1,      0ull,   0},
48686         {"RESERVED_8_63"               ,        8,      56,     392,    "RAZ",  1,      1,      0,      0},
48687         {"IID"                         ,        0,      4,      393,    "RO",   0,      1,      1ull,   0},
48688         {"RESERVED_4_5"                ,        4,      2,      393,    "RAZ",  0,      1,      0ull,   0},
48689         {"FEN"                         ,        6,      2,      393,    "RO",   0,      1,      0ull,   0},
48690         {"RESERVED_8_63"               ,        8,      56,     393,    "RAZ",  1,      1,      0,      0},
48691         {"CLS"                         ,        0,      2,      394,    "R/W",  0,      1,      0ull,   0},
48692         {"STOP"                        ,        2,      1,      394,    "R/W",  0,      1,      0ull,   0},
48693         {"PEN"                         ,        3,      1,      394,    "R/W",  0,      1,      0ull,   0},
48694         {"EPS"                         ,        4,      1,      394,    "R/W",  0,      1,      0ull,   0},
48695         {"RESERVED_5_5"                ,        5,      1,      394,    "RAZ",  0,      1,      0ull,   0},
48696         {"BRK"                         ,        6,      1,      394,    "R/W",  0,      1,      0ull,   0},
48697         {"DLAB"                        ,        7,      1,      394,    "R/W",  0,      1,      0ull,   0},
48698         {"RESERVED_8_63"               ,        8,      56,     394,    "RAZ",  1,      1,      0,      0},
48699         {"DR"                          ,        0,      1,      395,    "RO",   0,      1,      0ull,   0},
48700         {"OE"                          ,        1,      1,      395,    "RC",   0,      1,      0ull,   0},
48701         {"PE"                          ,        2,      1,      395,    "RC",   0,      1,      0ull,   0},
48702         {"FE"                          ,        3,      1,      395,    "RC",   0,      1,      0ull,   0},
48703         {"BI"                          ,        4,      1,      395,    "RC",   0,      1,      0ull,   0},
48704         {"THRE"                        ,        5,      1,      395,    "RO",   0,      1,      1ull,   0},
48705         {"TEMT"                        ,        6,      1,      395,    "RO",   0,      1,      1ull,   0},
48706         {"FERR"                        ,        7,      1,      395,    "RC",   0,      1,      0ull,   0},
48707         {"RESERVED_8_63"               ,        8,      56,     395,    "RAZ",  1,      1,      0,      0},
48708         {"DTR"                         ,        0,      1,      396,    "R/W",  0,      1,      0ull,   0},
48709         {"RTS"                         ,        1,      1,      396,    "R/W",  0,      1,      0ull,   0},
48710         {"OUT1"                        ,        2,      1,      396,    "R/W",  0,      1,      0ull,   0},
48711         {"OUT2"                        ,        3,      1,      396,    "R/W",  0,      1,      0ull,   0},
48712         {"LOOP"                        ,        4,      1,      396,    "R/W",  0,      1,      0ull,   0},
48713         {"AFCE"                        ,        5,      1,      396,    "R/W",  0,      1,      0ull,   0},
48714         {"RESERVED_6_63"               ,        6,      58,     396,    "RAZ",  0,      1,      0ull,   0},
48715         {"DCTS"                        ,        0,      1,      397,    "RC",   0,      1,      0ull,   0},
48716         {"DDSR"                        ,        1,      1,      397,    "RC",   0,      1,      0ull,   0},
48717         {"TERI"                        ,        2,      1,      397,    "RC",   0,      1,      0ull,   0},
48718         {"DDCD"                        ,        3,      1,      397,    "RC",   0,      1,      0ull,   0},
48719         {"CTS"                         ,        4,      1,      397,    "RO",   1,      1,      0,      0},
48720         {"DSR"                         ,        5,      1,      397,    "RO",   0,      1,      0ull,   0},
48721         {"RI"                          ,        6,      1,      397,    "RO",   0,      1,      0ull,   0},
48722         {"DCD"                         ,        7,      1,      397,    "RO",   0,      1,      0ull,   0},
48723         {"RESERVED_8_63"               ,        8,      56,     397,    "RAZ",  1,      1,      0,      0},
48724         {"RBR"                         ,        0,      8,      398,    "RO",   0,      1,      0ull,   0},
48725         {"RESERVED_8_63"               ,        8,      56,     398,    "RAZ",  1,      1,      0,      0},
48726         {"RFL"                         ,        0,      7,      399,    "RO",   0,      1,      0ull,   0},
48727         {"RESERVED_7_63"               ,        7,      57,     399,    "RAZ",  1,      1,      0,      0},
48728         {"RFWD"                        ,        0,      8,      400,    "WO",   0,      1,      0ull,   0},
48729         {"RFPE"                        ,        8,      1,      400,    "WO",   0,      1,      0ull,   0},
48730         {"RFFE"                        ,        9,      1,      400,    "WO",   0,      1,      0ull,   0},
48731         {"RESERVED_10_63"              ,        10,     54,     400,    "RAZ",  1,      1,      0,      0},
48732         {"SBCR"                        ,        0,      1,      401,    "R/W",  0,      1,      0ull,   0},
48733         {"RESERVED_1_63"               ,        1,      63,     401,    "RAZ",  1,      1,      0,      0},
48734         {"SCR"                         ,        0,      8,      402,    "R/W",  0,      1,      0ull,   0},
48735         {"RESERVED_8_63"               ,        8,      56,     402,    "RAZ",  1,      1,      0,      0},
48736         {"SFE"                         ,        0,      1,      403,    "R/W",  0,      1,      0ull,   0},
48737         {"RESERVED_1_63"               ,        1,      63,     403,    "RAZ",  1,      1,      0,      0},
48738         {"USR"                         ,        0,      1,      404,    "WO",   0,      1,      0ull,   0},
48739         {"SRFR"                        ,        1,      1,      404,    "WO",   0,      1,      0ull,   0},
48740         {"STFR"                        ,        2,      1,      404,    "WO",   0,      1,      0ull,   0},
48741         {"RESERVED_3_63"               ,        3,      61,     404,    "RAZ",  1,      1,      0,      0},
48742         {"SRT"                         ,        0,      2,      405,    "R/W",  0,      1,      0ull,   0},
48743         {"RESERVED_2_63"               ,        2,      62,     405,    "RAZ",  1,      1,      0,      0},
48744         {"SRTS"                        ,        0,      1,      406,    "R/W",  0,      1,      0ull,   0},
48745         {"RESERVED_1_63"               ,        1,      63,     406,    "RAZ",  1,      1,      0,      0},
48746         {"STT"                         ,        0,      2,      407,    "R/W",  0,      1,      0ull,   0},
48747         {"RESERVED_2_63"               ,        2,      62,     407,    "RAZ",  1,      1,      0,      0},
48748         {"TFL"                         ,        0,      7,      408,    "RO",   0,      1,      0ull,   0},
48749         {"RESERVED_7_63"               ,        7,      57,     408,    "RAZ",  1,      1,      0,      0},
48750         {"TFR"                         ,        0,      8,      409,    "RO",   0,      1,      0ull,   0},
48751         {"RESERVED_8_63"               ,        8,      56,     409,    "RAZ",  1,      1,      0,      0},
48752         {"THR"                         ,        0,      8,      410,    "WO",   0,      1,      0ull,   0},
48753         {"RESERVED_8_63"               ,        8,      56,     410,    "RAZ",  1,      1,      0,      0},
48754         {"BUSY"                        ,        0,      1,      411,    "RO",   0,      1,      0ull,   0},
48755         {"TFNF"                        ,        1,      1,      411,    "RO",   0,      1,      1ull,   0},
48756         {"TFE"                         ,        2,      1,      411,    "RO",   0,      1,      1ull,   0},
48757         {"RFNE"                        ,        3,      1,      411,    "RO",   0,      1,      0ull,   0},
48758         {"RFF"                         ,        4,      1,      411,    "RO",   0,      1,      0ull,   0},
48759         {"RESERVED_5_63"               ,        5,      59,     411,    "RAZ",  1,      1,      0,      0},
48760         {"ORFDAT"                      ,        0,      1,      412,    "RO",   0,      0,      0ull,   0ull},
48761         {"IRFDAT"                      ,        1,      1,      412,    "RO",   0,      0,      0ull,   0ull},
48762         {"IPFDAT"                      ,        2,      1,      412,    "RO",   0,      0,      0ull,   0ull},
48763         {"MRQDAT"                      ,        3,      1,      412,    "RO",   0,      0,      0ull,   0ull},
48764         {"RESERVED_4_63"               ,        4,      60,     412,    "RAZ",  0,      0,      0ull,   0ull},
48765         {"MRQ_HWM"                     ,        0,      2,      413,    "R/W",  0,      0,      1ull,   1ull},
48766         {"NBTARB"                      ,        2,      1,      413,    "R/W",  0,      0,      0ull,   0ull},
48767         {"LENDIAN"                     ,        3,      1,      413,    "R/W",  0,      0,      0ull,   0ull},
48768         {"RESET"                       ,        4,      1,      413,    "RAZ",  0,      0,      0ull,   0ull},
48769         {"EN"                          ,        5,      1,      413,    "R/W",  0,      0,      0ull,   0ull},
48770         {"BUSY"                        ,        6,      1,      413,    "RO",   0,      0,      0ull,   0ull},
48771         {"CRC_STRIP"                   ,        7,      1,      413,    "R/W",  0,      0,      0ull,   0ull},
48772         {"RESERVED_8_63"               ,        8,      56,     413,    "RAZ",  1,      1,      0,      0},
48773         {"OVFENA"                      ,        0,      1,      414,    "R/W",  0,      0,      0ull,   0ull},
48774         {"IVFENA"                      ,        1,      1,      414,    "R/W",  0,      0,      0ull,   0ull},
48775         {"OTHENA"                      ,        2,      1,      414,    "R/W",  0,      0,      0ull,   0ull},
48776         {"ITHENA"                      ,        3,      1,      414,    "R/W",  0,      0,      0ull,   0ull},
48777         {"DATA_DRPENA"                 ,        4,      1,      414,    "R/W",  0,      0,      0ull,   0ull},
48778         {"IRUNENA"                     ,        5,      1,      414,    "R/W",  0,      0,      0ull,   0ull},
48779         {"ORUNENA"                     ,        6,      1,      414,    "R/W",  0,      0,      0ull,   0ull},
48780         {"RESERVED_7_63"               ,        7,      57,     414,    "RAZ",  1,      1,      0,      0},
48781         {"IRCNT"                       ,        0,      20,     415,    "R/W",  0,      0,      0ull,   0ull},
48782         {"RESERVED_20_63"              ,        20,     44,     415,    "RAZ",  1,      1,      0,      0},
48783         {"IRHWM"                       ,        0,      20,     416,    "R/W",  0,      0,      0ull,   0ull},
48784         {"IBPLWM"                      ,        20,     20,     416,    "R/W",  0,      0,      0ull,   0ull},
48785         {"RESERVED_40_63"              ,        40,     24,     416,    "RAZ",  1,      1,      0,      0},
48786         {"RESERVED_0_2"                ,        0,      3,      417,    "RAZ",  1,      1,      0,      0},
48787         {"IBASE"                       ,        3,      33,     417,    "R/W",  0,      1,      0ull,   0},
48788         {"RESERVED_36_39"              ,        36,     4,      417,    "RAZ",  1,      1,      0,      0},
48789         {"ISIZE"                       ,        40,     20,     417,    "R/W",  0,      1,      0ull,   0},
48790         {"RESERVED_60_63"              ,        60,     4,      417,    "RAZ",  1,      1,      0,      0},
48791         {"IDBELL"                      ,        0,      20,     418,    "R/W",  0,      1,      0ull,   0},
48792         {"RESERVED_20_31"              ,        20,     12,     418,    "RAZ",  1,      1,      0,      0},
48793         {"ITLPTR"                      ,        32,     20,     418,    "RO",   0,      1,      0ull,   0},
48794         {"RESERVED_52_63"              ,        52,     12,     418,    "RAZ",  1,      1,      0,      0},
48795         {"ODBLOVF"                     ,        0,      1,      419,    "R/W1C",        0,      0,      0ull,   0ull},
48796         {"IDBLOVF"                     ,        1,      1,      419,    "R/W1C",        0,      0,      0ull,   0ull},
48797         {"ORTHRESH"                    ,        2,      1,      419,    "RO",   0,      0,      0ull,   0ull},
48798         {"IRTHRESH"                    ,        3,      1,      419,    "RO",   0,      0,      0ull,   0ull},
48799         {"DATA_DRP"                    ,        4,      1,      419,    "R/W1C",        0,      0,      0ull,   0ull},
48800         {"IRUN"                        ,        5,      1,      419,    "R/W1C",        0,      0,      0ull,   0ull},
48801         {"ORUN"                        ,        6,      1,      419,    "R/W1C",        0,      0,      0ull,   0ull},
48802         {"RESERVED_7_63"               ,        7,      57,     419,    "RAZ",  1,      1,      0,      0},
48803         {"ORCNT"                       ,        0,      20,     420,    "R/W",  0,      0,      0ull,   0ull},
48804         {"RESERVED_20_63"              ,        20,     44,     420,    "RAZ",  1,      1,      0,      0},
48805         {"ORHWM"                       ,        0,      20,     421,    "R/W",  0,      0,      0ull,   0ull},
48806         {"RESERVED_20_63"              ,        20,     44,     421,    "RAZ",  1,      1,      0,      0},
48807         {"RESERVED_0_2"                ,        0,      3,      422,    "RAZ",  1,      1,      0,      0},
48808         {"OBASE"                       ,        3,      33,     422,    "R/W",  0,      1,      0ull,   0},
48809         {"RESERVED_36_39"              ,        36,     4,      422,    "RAZ",  1,      1,      0,      0},
48810         {"OSIZE"                       ,        40,     20,     422,    "R/W",  0,      1,      0ull,   0},
48811         {"RESERVED_60_63"              ,        60,     4,      422,    "RAZ",  1,      1,      0,      0},
48812         {"ODBELL"                      ,        0,      20,     423,    "R/W",  0,      1,      0ull,   0},
48813         {"RESERVED_20_31"              ,        20,     12,     423,    "RAZ",  1,      1,      0,      0},
48814         {"OTLPTR"                      ,        32,     20,     423,    "RO",   0,      1,      0ull,   0},
48815         {"RESERVED_52_63"              ,        52,     12,     423,    "RAZ",  1,      1,      0,      0},
48816         {"OREMCNT"                     ,        0,      20,     424,    "RO",   0,      0,      0ull,   0ull},
48817         {"RESERVED_20_31"              ,        20,     12,     424,    "RAZ",  1,      1,      0,      0},
48818         {"IREMCNT"                     ,        32,     20,     424,    "RO",   0,      0,      0ull,   0ull},
48819         {"RESERVED_52_63"              ,        52,     12,     424,    "RAZ",  1,      1,      0,      0},
48820         {"ADDR_V"                      ,        0,      1,      425,    "R/W",  0,      1,      0ull,   0},
48821         {"END_SWP"                     ,        1,      2,      425,    "R/W",  0,      1,      0ull,   0},
48822         {"CA"                          ,        3,      1,      425,    "R/W",  0,      0,      0ull,   0ull},
48823         {"ADDR_IDX"                    ,        4,      14,     425,    "R/W",  0,      1,      0ull,   0},
48824         {"RESERVED_18_31"              ,        18,     14,     425,    "RAZ",  1,      1,      0,      0},
48825         {"NCB_CMD"                     ,        0,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48826         {"MSI"                         ,        1,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48827         {"DIF4"                        ,        2,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48828         {"DIF3"                        ,        3,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48829         {"DIF2"                        ,        4,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48830         {"DIF1"                        ,        5,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48831         {"DIF0"                        ,        6,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48832         {"CSM1"                        ,        7,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48833         {"CSM0"                        ,        8,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48834         {"P2N1_P1"                     ,        9,      1,      426,    "RO",   0,      0,      0ull,   0ull},
48835         {"P2N1_P0"                     ,        10,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48836         {"P2N1_N"                      ,        11,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48837         {"P2N1_C1"                     ,        12,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48838         {"P2N1_C0"                     ,        13,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48839         {"P2N0_P1"                     ,        14,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48840         {"P2N0_P0"                     ,        15,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48841         {"P2N0_N"                      ,        16,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48842         {"P2N0_C1"                     ,        17,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48843         {"P2N0_C0"                     ,        18,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48844         {"P2N0_CO"                     ,        19,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48845         {"P2N0_NO"                     ,        20,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48846         {"P2N0_PO"                     ,        21,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48847         {"P2N1_CO"                     ,        22,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48848         {"P2N1_NO"                     ,        23,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48849         {"P2N1_PO"                     ,        24,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48850         {"CPL_P1"                      ,        25,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48851         {"CPL_P0"                      ,        26,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48852         {"N2P1_O"                      ,        27,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48853         {"N2P1_C"                      ,        28,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48854         {"N2P0_O"                      ,        29,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48855         {"N2P0_C"                      ,        30,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48856         {"D4_PST"                      ,        31,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48857         {"D3_PST"                      ,        32,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48858         {"D2_PST"                      ,        33,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48859         {"D1_PST"                      ,        34,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48860         {"D0_PST"                      ,        35,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48861         {"RESERVED_36_39"              ,        36,     4,      426,    "RAZ",  1,      1,      0,      0},
48862         {"DS_MEM"                      ,        40,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48863         {"D4_MEM"                      ,        41,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48864         {"D3_MEM"                      ,        42,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48865         {"D2_MEM"                      ,        43,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48866         {"D1_MEM"                      ,        44,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48867         {"D0_MEM"                      ,        45,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48868         {"PKT_POP1"                    ,        46,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48869         {"PKT_POP0"                    ,        47,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48870         {"RESERVED_48_49"              ,        48,     2,      426,    "RAZ",  1,      1,      0,      0},
48871         {"PKT_POF"                     ,        50,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48872         {"PKT_PFM"                     ,        51,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48873         {"PKT_IMEM"                    ,        52,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48874         {"PCSR_SL"                     ,        53,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48875         {"PCSR_ID"                     ,        54,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48876         {"PCSR_CNT"                    ,        55,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48877         {"PCSR_IM"                     ,        56,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48878         {"PCSR_INT"                    ,        57,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48879         {"PKT_PIF"                     ,        58,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48880         {"PCR_GIM"                     ,        59,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48881         {"RESERVED_60_62"              ,        60,     3,      426,    "RAZ",  1,      1,      0,      0},
48882         {"PKT_RDF"                     ,        63,     1,      426,    "RO",   0,      0,      0ull,   0ull},
48883         {"PKT_BLK"                     ,        0,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48884         {"PKT_GL"                      ,        1,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48885         {"PKT_GD"                      ,        2,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48886         {"PSC_P1"                      ,        3,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48887         {"PSC_P0"                      ,        4,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48888         {"PKT_RD"                      ,        5,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48889         {"NWE_WR1"                     ,        6,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48890         {"NWE_WR0"                     ,        7,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48891         {"NWE_ST"                      ,        8,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48892         {"NRD_ST"                      ,        9,      1,      427,    "RO",   0,      0,      0ull,   0ull},
48893         {"PRD_ERR"                     ,        10,     1,      427,    "RO",   0,      0,      0ull,   0ull},
48894         {"PRD_ST1"                     ,        11,     1,      427,    "RO",   0,      0,      0ull,   0ull},
48895         {"PRD_ST0"                     ,        12,     1,      427,    "RO",   0,      0,      0ull,   0ull},
48896         {"PRD_TAG"                     ,        13,     1,      427,    "RO",   0,      0,      0ull,   0ull},
48897         {"RESERVED_14_63"              ,        14,     50,     427,    "RAZ",  1,      1,      0,      0},
48898         {"WAIT_COM"                    ,        0,      1,      428,    "R/W",  0,      0,      0ull,   0ull},
48899         {"BAR2_CAX"                    ,        1,      1,      428,    "R/W",  0,      0,      0ull,   0ull},
48900         {"BAR2_ESX"                    ,        2,      2,      428,    "R/W",  0,      1,      0ull,   0},
48901         {"BAR2_ENB"                    ,        4,      1,      428,    "R/W",  0,      0,      0ull,   1ull},
48902         {"PTLP_RO"                     ,        5,      1,      428,    "R/W",  0,      0,      0ull,   1ull},
48903         {"RESERVED_6_6"                ,        6,      1,      428,    "RAZ",  0,      0,      0ull,   0ull},
48904         {"CTLP_RO"                     ,        7,      1,      428,    "R/W",  0,      0,      0ull,   1ull},
48905         {"INTA_MAP"                    ,        8,      2,      428,    "R/W",  0,      0,      0ull,   0ull},
48906         {"INTB_MAP"                    ,        10,     2,      428,    "R/W",  0,      0,      1ull,   1ull},
48907         {"INTC_MAP"                    ,        12,     2,      428,    "R/W",  0,      0,      2ull,   2ull},
48908         {"INTD_MAP"                    ,        14,     2,      428,    "R/W",  0,      0,      3ull,   3ull},
48909         {"INTA"                        ,        16,     1,      428,    "RO",   0,      0,      1ull,   1ull},
48910         {"INTB"                        ,        17,     1,      428,    "RO",   0,      0,      1ull,   1ull},
48911         {"INTC"                        ,        18,     1,      428,    "RO",   0,      0,      1ull,   1ull},
48912         {"INTD"                        ,        19,     1,      428,    "RO",   0,      0,      1ull,   1ull},
48913         {"WAITL_COM"                   ,        20,     1,      428,    "R/W",  0,      1,      0ull,   0},
48914         {"RESERVED_21_63"              ,        21,     43,     428,    "RAZ",  1,      1,      0,      0},
48915         {"WAIT_COM"                    ,        0,      1,      429,    "R/W",  0,      0,      0ull,   0ull},
48916         {"BAR2_CAX"                    ,        1,      1,      429,    "R/W",  0,      0,      0ull,   0ull},
48917         {"BAR2_ESX"                    ,        2,      2,      429,    "R/W",  0,      1,      0ull,   0},
48918         {"BAR2_ENB"                    ,        4,      1,      429,    "R/W",  0,      0,      0ull,   1ull},
48919         {"PTLP_RO"                     ,        5,      1,      429,    "R/W",  0,      0,      0ull,   1ull},
48920         {"RESERVED_6_6"                ,        6,      1,      429,    "RAZ",  0,      0,      0ull,   0ull},
48921         {"CTLP_RO"                     ,        7,      1,      429,    "R/W",  0,      0,      0ull,   1ull},
48922         {"INTA_MAP"                    ,        8,      2,      429,    "R/W",  0,      0,      0ull,   0ull},
48923         {"INTB_MAP"                    ,        10,     2,      429,    "R/W",  0,      0,      1ull,   1ull},
48924         {"INTC_MAP"                    ,        12,     2,      429,    "R/W",  0,      0,      2ull,   2ull},
48925         {"INTD_MAP"                    ,        14,     2,      429,    "R/W",  0,      0,      3ull,   3ull},
48926         {"INTA"                        ,        16,     1,      429,    "RO",   0,      0,      1ull,   1ull},
48927         {"INTB"                        ,        17,     1,      429,    "RO",   0,      0,      1ull,   1ull},
48928         {"INTC"                        ,        18,     1,      429,    "RO",   0,      0,      1ull,   1ull},
48929         {"INTD"                        ,        19,     1,      429,    "RO",   0,      0,      1ull,   1ull},
48930         {"WAITL_COM"                   ,        20,     1,      429,    "R/W",  0,      1,      0ull,   0},
48931         {"RESERVED_21_63"              ,        21,     43,     429,    "RAZ",  1,      1,      0,      0},
48932         {"CHIP_REV"                    ,        0,      8,      430,    "RO",   1,      1,      0,      0},
48933         {"HOST_MODE"                   ,        8,      1,      430,    "RO",   1,      1,      0,      0},
48934         {"PKT_BP"                      ,        9,      4,      430,    "R/W",  0,      0,      15ull,  15ull},
48935         {"ARB"                         ,        13,     1,      430,    "R/W",  0,      0,      0ull,   1ull},
48936         {"LNK_RST"                     ,        14,     1,      430,    "R/W1C",        0,      0,      0ull,   0ull},
48937         {"RING_EN"                     ,        15,     1,      430,    "R/W",  0,      0,      0ull,   0ull},
48938         {"CFG_RTRY"                    ,        16,     16,     430,    "R/W",  0,      0,      0ull,   32ull},
48939         {"P0_NTAGS"                    ,        32,     6,      430,    "R/W",  0,      0,      32ull,  32ull},
48940         {"P1_NTAGS"                    ,        38,     6,      430,    "R/W",  0,      0,      32ull,  32ull},
48941         {"RESERVED_44_63"              ,        44,     20,     430,    "RAZ",  1,      1,      0,      0},
48942         {"C0_B0_D"                     ,        0,      1,      431,    "R/W",  0,      0,      0ull,   0ull},
48943         {"C0_WI_D"                     ,        1,      1,      431,    "R/W",  0,      0,      0ull,   0ull},
48944         {"C1_B0_D"                     ,        2,      1,      431,    "R/W",  0,      0,      0ull,   0ull},
48945         {"C1_WI_D"                     ,        3,      1,      431,    "R/W",  0,      0,      0ull,   0ull},
48946         {"C0_B1_S"                     ,        4,      3,      431,    "R/W",  0,      0,      1ull,   1ull},
48947         {"C1_B1_S"                     ,        7,      3,      431,    "R/W",  0,      0,      1ull,   1ull},
48948         {"C0_W_FLT"                    ,        10,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
48949         {"C1_W_FLT"                    ,        11,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
48950         {"MRRS"                        ,        12,     3,      431,    "R/W",  0,      0,      2ull,   2ull},
48951         {"MPS"                         ,        15,     1,      431,    "R/W",  0,      0,      0ull,   0ull},
48952         {"RESERVED_16_63"              ,        16,     48,     431,    "RAZ",  1,      1,      0,      0},
48953         {"P0_FCNT"                     ,        0,      6,      432,    "RO",   0,      1,      0ull,   0},
48954         {"P0_UCNT"                     ,        6,      16,     432,    "RO",   0,      1,      0ull,   0},
48955         {"P1_FCNT"                     ,        22,     6,      432,    "RO",   0,      1,      0ull,   0},
48956         {"P1_UCNT"                     ,        28,     16,     432,    "RO",   0,      1,      0ull,   0},
48957         {"RESERVED_44_63"              ,        44,     20,     432,    "RAZ",  1,      1,      0,      0},
48958         {"DATA"                        ,        0,      17,     433,    "RO",   0,      1,      0ull,   0},
48959         {"DSEL_EXT"                    ,        17,     1,      433,    "R/W",  0,      0,      1ull,   0ull},
48960         {"C_MUL"                       ,        18,     5,      433,    "RO",   1,      1,      0,      0},
48961         {"QLM1_SPD"                    ,        23,     2,      433,    "RO",   1,      1,      0,      0},
48962         {"QLM3_SPD"                    ,        25,     2,      433,    "RO",   1,      1,      0,      0},
48963         {"QLM0_REV_LANES"              ,        27,     1,      433,    "RO",   1,      1,      0,      0},
48964         {"QLM2_REV_LANES"              ,        28,     1,      433,    "RO",   1,      1,      0,      0},
48965         {"RESERVED_29_63"              ,        29,     35,     433,    "RAZ",  1,      1,      0,      0},
48966         {"DBG_SEL"                     ,        0,      16,     434,    "R/W",  0,      1,      0ull,   0},
48967         {"RESERVED_16_63"              ,        16,     48,     434,    "RAZ",  1,      1,      0,      0},
48968         {"DBELL"                       ,        0,      32,     435,    "RO",   0,      0,      0ull,   0ull},
48969         {"FCNT"                        ,        32,     7,      435,    "RO",   0,      0,      0ull,   0ull},
48970         {"RESERVED_39_63"              ,        39,     25,     435,    "RAZ",  1,      1,      0,      0},
48971         {"DBELL"                       ,        0,      16,     436,    "R/W",  0,      1,      0ull,   0},
48972         {"RESERVED_16_31"              ,        16,     16,     436,    "RAZ",  1,      1,      0,      0},
48973         {"RESERVED_0_6"                ,        0,      7,      437,    "RAZ",  1,      1,      0,      0},
48974         {"SADDR"                       ,        7,      29,     437,    "R/W",  0,      1,      0ull,   0},
48975         {"IDLE"                        ,        36,     1,      437,    "RO",   0,      1,      1ull,   0},
48976         {"RESERVED_37_63"              ,        37,     27,     437,    "RAZ",  1,      1,      0,      0},
48977         {"ADDR"                        ,        0,      36,     438,    "RO",   0,      1,      0ull,   0},
48978         {"RESERVED_36_63"              ,        36,     28,     438,    "RAZ",  1,      1,      0,      0},
48979         {"CNT"                         ,        0,      32,     439,    "R/W",  0,      1,      0ull,   0},
48980         {"TIME"                        ,        32,     32,     439,    "R/W",  0,      1,      0ull,   0},
48981         {"CNT"                         ,        0,      32,     440,    "R/W",  0,      1,      0ull,   0},
48982         {"TIME"                        ,        32,     32,     440,    "R/W",  0,      1,      0ull,   0},
48983         {"DMA0"                        ,        0,      32,     441,    "R/W",  0,      1,      0ull,   0},
48984         {"DMA1"                        ,        32,     32,     441,    "R/W",  0,      1,      0ull,   0},
48985         {"CSIZE"                       ,        0,      14,     442,    "R/W",  0,      1,      0ull,   0},
48986         {"O_MODE"                      ,        14,     1,      442,    "R/W",  0,      0,      0ull,   1ull},
48987         {"O_ES"                        ,        15,     2,      442,    "R/W",  0,      1,      0ull,   0},
48988         {"O_NS"                        ,        17,     1,      442,    "R/W",  0,      1,      0ull,   0},
48989         {"O_RO"                        ,        18,     1,      442,    "R/W",  0,      1,      0ull,   0},
48990         {"O_ADD1"                      ,        19,     1,      442,    "R/W",  0,      0,      0ull,   1ull},
48991         {"FPA_QUE"                     ,        20,     3,      442,    "R/W",  0,      1,      0ull,   0},
48992         {"DWB_ICHK"                    ,        23,     9,      442,    "R/W",  0,      1,      0ull,   0},
48993         {"DWB_DENB"                    ,        32,     1,      442,    "R/W",  0,      0,      0ull,   1ull},
48994         {"B0_LEND"                     ,        33,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
48995         {"DMA0_ENB"                    ,        34,     1,      442,    "R/W",  0,      0,      0ull,   1ull},
48996         {"DMA1_ENB"                    ,        35,     1,      442,    "R/W",  0,      0,      0ull,   1ull},
48997         {"DMA2_ENB"                    ,        36,     1,      442,    "R/W",  0,      0,      0ull,   1ull},
48998         {"DMA3_ENB"                    ,        37,     1,      442,    "R/W",  0,      0,      0ull,   1ull},
48999         {"DMA4_ENB"                    ,        38,     1,      442,    "R/W",  0,      0,      0ull,   1ull},
49000         {"P_32B_M"                     ,        39,     1,      442,    "R/W",  0,      0,      0ull,   0ull},
49001         {"RESERVED_40_63"              ,        40,     24,     442,    "RAZ",  1,      1,      0,      0},
49002         {"DMA_CNT"                     ,        0,      5,      443,    "R/W",  0,      1,      16ull,  0},
49003         {"RESERVED_5_7"                ,        5,      3,      443,    "RAZ",  1,      1,      0,      0},
49004         {"DMA0_CNT"                    ,        8,      5,      443,    "R/W",  0,      1,      16ull,  0},
49005         {"RESERVED_13_15"              ,        13,     3,      443,    "RAZ",  1,      1,      0,      0},
49006         {"DMA1_CNT"                    ,        16,     5,      443,    "R/W",  0,      1,      16ull,  0},
49007         {"RESERVED_21_23"              ,        21,     3,      443,    "RAZ",  1,      1,      0,      0},
49008         {"DMA2_CNT"                    ,        24,     5,      443,    "R/W",  0,      1,      16ull,  0},
49009         {"RESERVED_29_31"              ,        29,     3,      443,    "RAZ",  1,      1,      0,      0},
49010         {"DMA3_CNT"                    ,        32,     5,      443,    "R/W",  0,      1,      16ull,  0},
49011         {"RESERVED_37_39"              ,        37,     3,      443,    "RAZ",  1,      1,      0,      0},
49012         {"DMA4_CNT"                    ,        40,     5,      443,    "R/W",  0,      1,      16ull,  0},
49013         {"RESERVED_45_47"              ,        45,     3,      443,    "RAZ",  1,      1,      0,      0},
49014         {"PKT_CNT"                     ,        48,     5,      443,    "R/W",  0,      1,      16ull,  0},
49015         {"RESERVED_53_62"              ,        53,     10,     443,    "RAZ",  1,      1,      0,      0},
49016         {"DMA_ARB"                     ,        63,     1,      443,    "R/W",  0,      1,      1ull,   0},
49017         {"DMA0_CPL"                    ,        0,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49018         {"DMA1_CPL"                    ,        1,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49019         {"PINS_ERR"                    ,        2,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49020         {"POP_ERR"                     ,        3,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49021         {"PDI_ERR"                     ,        4,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49022         {"PGL_ERR"                     ,        5,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49023         {"P0_RDLK"                     ,        6,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49024         {"P1_RDLK"                     ,        7,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49025         {"PIN_BP"                      ,        8,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49026         {"POUT_ERR"                    ,        9,      1,      444,    "R/W",  0,      0,      0ull,   1ull},
49027         {"RESERVED_10_63"              ,        10,     54,     444,    "RAZ",  0,      1,      0ull,   0},
49028         {"DMA0_CPL"                    ,        0,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49029         {"DMA1_CPL"                    ,        1,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49030         {"PINS_ERR"                    ,        2,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49031         {"POP_ERR"                     ,        3,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49032         {"PDI_ERR"                     ,        4,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49033         {"PGL_ERR"                     ,        5,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49034         {"P0_RDLK"                     ,        6,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49035         {"P1_RDLK"                     ,        7,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49036         {"PIN_BP"                      ,        8,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49037         {"POUT_ERR"                    ,        9,      1,      445,    "R/W",  0,      0,      0ull,   1ull},
49038         {"RESERVED_10_63"              ,        10,     54,     445,    "RAZ",  0,      1,      0ull,   0},
49039         {"DMA0_CPL"                    ,        0,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49040         {"DMA1_CPL"                    ,        1,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49041         {"PINS_ERR"                    ,        2,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49042         {"POP_ERR"                     ,        3,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49043         {"PDI_ERR"                     ,        4,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49044         {"PGL_ERR"                     ,        5,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49045         {"P0_RDLK"                     ,        6,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49046         {"P1_RDLK"                     ,        7,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49047         {"PIN_BP"                      ,        8,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49048         {"POUT_ERR"                    ,        9,      1,      446,    "R/W1C",        0,      0,      0ull,   0ull},
49049         {"RESERVED_10_63"              ,        10,     54,     446,    "RAZ",  0,      0,      0ull,   0ull},
49050         {"RML_RTO"                     ,        0,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49051         {"RML_WTO"                     ,        1,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49052         {"BAR0_TO"                     ,        2,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49053         {"IOB2BIG"                     ,        3,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49054         {"DMA0DBO"                     ,        4,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49055         {"DMA1DBO"                     ,        5,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49056         {"DMA2DBO"                     ,        6,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49057         {"DMA3DBO"                     ,        7,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49058         {"DMA4DBO"                     ,        8,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49059         {"DMA0FI"                      ,        9,      1,      447,    "R/W",  0,      0,      0ull,   1ull},
49060         {"DMA1FI"                      ,        10,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49061         {"DCNT0"                       ,        11,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49062         {"DCNT1"                       ,        12,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49063         {"DTIME0"                      ,        13,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49064         {"DTIME1"                      ,        14,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49065         {"PSLDBOF"                     ,        15,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49066         {"PIDBOF"                      ,        16,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49067         {"PCNT"                        ,        17,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49068         {"PTIME"                       ,        18,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49069         {"C0_AERI"                     ,        19,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49070         {"CRS0_ER"                     ,        20,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49071         {"C0_SE"                       ,        21,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49072         {"CRS0_DR"                     ,        22,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49073         {"C0_WAKE"                     ,        23,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49074         {"C0_PMEI"                     ,        24,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49075         {"C0_HPINT"                    ,        25,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49076         {"C1_AERI"                     ,        26,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49077         {"CRS1_ER"                     ,        27,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49078         {"C1_SE"                       ,        28,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49079         {"CRS1_DR"                     ,        29,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49080         {"C1_WAKE"                     ,        30,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49081         {"C1_PMEI"                     ,        31,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49082         {"C1_HPINT"                    ,        32,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49083         {"C0_UP_B0"                    ,        33,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49084         {"C0_UP_B1"                    ,        34,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49085         {"C0_UP_B2"                    ,        35,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49086         {"C0_UP_WI"                    ,        36,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49087         {"C0_UP_BX"                    ,        37,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49088         {"C0_UN_B0"                    ,        38,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49089         {"C0_UN_B1"                    ,        39,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49090         {"C0_UN_B2"                    ,        40,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49091         {"C0_UN_WI"                    ,        41,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49092         {"C0_UN_BX"                    ,        42,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49093         {"C1_UP_B0"                    ,        43,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49094         {"C1_UP_B1"                    ,        44,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49095         {"C1_UP_B2"                    ,        45,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49096         {"C1_UP_WI"                    ,        46,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49097         {"C1_UP_BX"                    ,        47,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49098         {"C1_UN_B0"                    ,        48,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49099         {"C1_UN_B1"                    ,        49,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49100         {"C1_UN_B2"                    ,        50,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49101         {"C1_UN_WI"                    ,        51,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49102         {"C1_UN_BX"                    ,        52,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49103         {"C0_UN_WF"                    ,        53,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49104         {"C1_UN_WF"                    ,        54,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49105         {"C0_UP_WF"                    ,        55,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49106         {"C1_UP_WF"                    ,        56,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49107         {"C0_EXC"                      ,        57,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49108         {"C1_EXC"                      ,        58,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49109         {"C0_LDWN"                     ,        59,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49110         {"C1_LDWN"                     ,        60,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49111         {"INT_A"                       ,        61,     1,      447,    "RO",   0,      0,      1ull,   1ull},
49112         {"RESERVED_62_62"              ,        62,     1,      447,    "RAZ",  0,      1,      0ull,   0},
49113         {"MIO_INTA"                    ,        63,     1,      447,    "R/W",  0,      0,      0ull,   1ull},
49114         {"RML_RTO"                     ,        0,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49115         {"RML_WTO"                     ,        1,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49116         {"BAR0_TO"                     ,        2,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49117         {"IOB2BIG"                     ,        3,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49118         {"DMA0DBO"                     ,        4,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49119         {"DMA1DBO"                     ,        5,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49120         {"DMA2DBO"                     ,        6,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49121         {"DMA3DBO"                     ,        7,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49122         {"DMA4DBO"                     ,        8,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49123         {"DMA0FI"                      ,        9,      1,      448,    "R/W",  0,      0,      0ull,   1ull},
49124         {"DMA1FI"                      ,        10,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49125         {"DCNT0"                       ,        11,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49126         {"DCNT1"                       ,        12,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49127         {"DTIME0"                      ,        13,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49128         {"DTIME1"                      ,        14,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49129         {"PSLDBOF"                     ,        15,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49130         {"PIDBOF"                      ,        16,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49131         {"PCNT"                        ,        17,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49132         {"PTIME"                       ,        18,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49133         {"C0_AERI"                     ,        19,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49134         {"CRS0_ER"                     ,        20,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49135         {"C0_SE"                       ,        21,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49136         {"CRS0_DR"                     ,        22,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49137         {"C0_WAKE"                     ,        23,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49138         {"C0_PMEI"                     ,        24,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49139         {"C0_HPINT"                    ,        25,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49140         {"C1_AERI"                     ,        26,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49141         {"CRS1_ER"                     ,        27,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49142         {"C1_SE"                       ,        28,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49143         {"CRS1_DR"                     ,        29,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49144         {"C1_WAKE"                     ,        30,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49145         {"C1_PMEI"                     ,        31,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49146         {"C1_HPINT"                    ,        32,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49147         {"C0_UP_B0"                    ,        33,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49148         {"C0_UP_B1"                    ,        34,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49149         {"C0_UP_B2"                    ,        35,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49150         {"C0_UP_WI"                    ,        36,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49151         {"C0_UP_BX"                    ,        37,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49152         {"C0_UN_B0"                    ,        38,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49153         {"C0_UN_B1"                    ,        39,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49154         {"C0_UN_B2"                    ,        40,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49155         {"C0_UN_WI"                    ,        41,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49156         {"C0_UN_BX"                    ,        42,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49157         {"C1_UP_B0"                    ,        43,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49158         {"C1_UP_B1"                    ,        44,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49159         {"C1_UP_B2"                    ,        45,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49160         {"C1_UP_WI"                    ,        46,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49161         {"C1_UP_BX"                    ,        47,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49162         {"C1_UN_B0"                    ,        48,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49163         {"C1_UN_B1"                    ,        49,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49164         {"C1_UN_B2"                    ,        50,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49165         {"C1_UN_WI"                    ,        51,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49166         {"C1_UN_BX"                    ,        52,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49167         {"C0_UN_WF"                    ,        53,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49168         {"C1_UN_WF"                    ,        54,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49169         {"C0_UP_WF"                    ,        55,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49170         {"C1_UP_WF"                    ,        56,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49171         {"C0_EXC"                      ,        57,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49172         {"C1_EXC"                      ,        58,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49173         {"C0_LDWN"                     ,        59,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49174         {"C1_LDWN"                     ,        60,     1,      448,    "R/W",  0,      0,      0ull,   1ull},
49175         {"INT_A"                       ,        61,     1,      448,    "RO",   0,      0,      1ull,   1ull},
49176         {"RESERVED_62_63"              ,        62,     2,      448,    "RAZ",  0,      1,      0ull,   0},
49177         {"PSLDBOF"                     ,        0,      6,      449,    "RO",   0,      1,      0ull,   0},
49178         {"PIDBOF"                      ,        6,      6,      449,    "RO",   0,      1,      0ull,   0},
49179         {"RESERVED_12_63"              ,        12,     52,     449,    "RAZ",  1,      1,      0,      0},
49180         {"RML_RTO"                     ,        0,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49181         {"RML_WTO"                     ,        1,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49182         {"BAR0_TO"                     ,        2,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49183         {"IOB2BIG"                     ,        3,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49184         {"DMA0DBO"                     ,        4,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49185         {"DMA1DBO"                     ,        5,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49186         {"DMA2DBO"                     ,        6,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49187         {"DMA3DBO"                     ,        7,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49188         {"DMA4DBO"                     ,        8,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49189         {"DMA0FI"                      ,        9,      1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49190         {"DMA1FI"                      ,        10,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49191         {"DCNT0"                       ,        11,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49192         {"DCNT1"                       ,        12,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49193         {"DTIME0"                      ,        13,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49194         {"DTIME1"                      ,        14,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49195         {"PSLDBOF"                     ,        15,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49196         {"PIDBOF"                      ,        16,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49197         {"PCNT"                        ,        17,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49198         {"PTIME"                       ,        18,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49199         {"C0_AERI"                     ,        19,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49200         {"CRS0_ER"                     ,        20,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49201         {"C0_SE"                       ,        21,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49202         {"CRS0_DR"                     ,        22,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49203         {"C0_WAKE"                     ,        23,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49204         {"C0_PMEI"                     ,        24,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49205         {"C0_HPINT"                    ,        25,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49206         {"C1_AERI"                     ,        26,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49207         {"CRS1_ER"                     ,        27,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49208         {"C1_SE"                       ,        28,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49209         {"CRS1_DR"                     ,        29,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49210         {"C1_WAKE"                     ,        30,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49211         {"C1_PMEI"                     ,        31,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49212         {"C1_HPINT"                    ,        32,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49213         {"C0_UP_B0"                    ,        33,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49214         {"C0_UP_B1"                    ,        34,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49215         {"C0_UP_B2"                    ,        35,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49216         {"C0_UP_WI"                    ,        36,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49217         {"C0_UP_BX"                    ,        37,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49218         {"C0_UN_B0"                    ,        38,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49219         {"C0_UN_B1"                    ,        39,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49220         {"C0_UN_B2"                    ,        40,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49221         {"C0_UN_WI"                    ,        41,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49222         {"C0_UN_BX"                    ,        42,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49223         {"C1_UP_B0"                    ,        43,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49224         {"C1_UP_B1"                    ,        44,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49225         {"C1_UP_B2"                    ,        45,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49226         {"C1_UP_WI"                    ,        46,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49227         {"C1_UP_BX"                    ,        47,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49228         {"C1_UN_B0"                    ,        48,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49229         {"C1_UN_B1"                    ,        49,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49230         {"C1_UN_B2"                    ,        50,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49231         {"C1_UN_WI"                    ,        51,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49232         {"C1_UN_BX"                    ,        52,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49233         {"C0_UN_WF"                    ,        53,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49234         {"C1_UN_WF"                    ,        54,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49235         {"C0_UP_WF"                    ,        55,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49236         {"C1_UP_WF"                    ,        56,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49237         {"C0_EXC"                      ,        57,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49238         {"C1_EXC"                      ,        58,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49239         {"C0_LDWN"                     ,        59,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49240         {"C1_LDWN"                     ,        60,     1,      450,    "R/W1C",        0,      0,      0ull,   0ull},
49241         {"INT_A"                       ,        61,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49242         {"RESERVED_62_62"              ,        62,     1,      450,    "RAZ",  0,      0,      0ull,   0ull},
49243         {"MIO_INTA"                    ,        63,     1,      450,    "RO",   0,      0,      0ull,   0ull},
49244         {"RML_RTO"                     ,        0,      1,      451,    "RO",   0,      0,      0ull,   0ull},
49245         {"RML_WTO"                     ,        1,      1,      451,    "RO",   0,      0,      0ull,   0ull},
49246         {"BAR0_TO"                     ,        2,      1,      451,    "RO",   0,      0,      0ull,   0ull},
49247         {"IOB2BIG"                     ,        3,      1,      451,    "RO",   0,      0,      0ull,   0ull},
49248         {"DMA0DBO"                     ,        4,      1,      451,    "RO",   0,      0,      0ull,   0ull},
49249         {"DMA1DBO"                     ,        5,      1,      451,    "RO",   0,      0,      0ull,   0ull},
49250         {"DMA2DBO"                     ,        6,      1,      451,    "RO",   0,      0,      0ull,   0ull},
49251         {"DMA3DBO"                     ,        7,      1,      451,    "RO",   0,      0,      0ull,   0ull},
49252         {"RESERVED_8_8"                ,        8,      1,      451,    "RAZ",  1,      1,      0,      0},
49253         {"DMA0FI"                      ,        9,      1,      451,    "RO",   0,      0,      0ull,   0ull},
49254         {"DMA1FI"                      ,        10,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49255         {"DCNT0"                       ,        11,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49256         {"DCNT1"                       ,        12,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49257         {"DTIME0"                      ,        13,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49258         {"DTIME1"                      ,        14,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49259         {"RESERVED_15_18"              ,        15,     4,      451,    "RAZ",  0,      0,      0ull,   0ull},
49260         {"C0_AERI"                     ,        19,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49261         {"CRS0_ER"                     ,        20,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49262         {"C0_SE"                       ,        21,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49263         {"CRS0_DR"                     ,        22,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49264         {"C0_WAKE"                     ,        23,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49265         {"C0_PMEI"                     ,        24,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49266         {"C0_HPINT"                    ,        25,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49267         {"C1_AERI"                     ,        26,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49268         {"CRS1_ER"                     ,        27,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49269         {"C1_SE"                       ,        28,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49270         {"CRS1_DR"                     ,        29,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49271         {"C1_WAKE"                     ,        30,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49272         {"C1_PMEI"                     ,        31,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49273         {"C1_HPINT"                    ,        32,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49274         {"C0_UP_B0"                    ,        33,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49275         {"C0_UP_B1"                    ,        34,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49276         {"C0_UP_B2"                    ,        35,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49277         {"C0_UP_WI"                    ,        36,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49278         {"C0_UP_BX"                    ,        37,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49279         {"C0_UN_B0"                    ,        38,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49280         {"C0_UN_B1"                    ,        39,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49281         {"C0_UN_B2"                    ,        40,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49282         {"C0_UN_WI"                    ,        41,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49283         {"C0_UN_BX"                    ,        42,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49284         {"C1_UP_B0"                    ,        43,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49285         {"C1_UP_B1"                    ,        44,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49286         {"C1_UP_B2"                    ,        45,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49287         {"C1_UP_WI"                    ,        46,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49288         {"C1_UP_BX"                    ,        47,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49289         {"C1_UN_B0"                    ,        48,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49290         {"C1_UN_B1"                    ,        49,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49291         {"C1_UN_B2"                    ,        50,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49292         {"C1_UN_WI"                    ,        51,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49293         {"C1_UN_BX"                    ,        52,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49294         {"C0_UN_WF"                    ,        53,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49295         {"C1_UN_WF"                    ,        54,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49296         {"C0_UP_WF"                    ,        55,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49297         {"C1_UP_WF"                    ,        56,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49298         {"C0_EXC"                      ,        57,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49299         {"C1_EXC"                      ,        58,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49300         {"C0_LDWN"                     ,        59,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49301         {"C1_LDWN"                     ,        60,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49302         {"INT_A"                       ,        61,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49303         {"RESERVED_62_62"              ,        62,     1,      451,    "RAZ",  0,      0,      0ull,   0ull},
49304         {"MIO_INTA"                    ,        63,     1,      451,    "RO",   0,      0,      0ull,   0ull},
49305         {"DATA"                        ,        0,      64,     452,    "RO",   0,      1,      0ull,   0},
49306         {"DATA"                        ,        0,      64,     453,    "RO",   0,      1,      0ull,   0},
49307         {"TIMER"                       ,        0,      10,     454,    "R/W",  0,      0,      0ull,   50ull},
49308         {"MAX_WORD"                    ,        10,     4,      454,    "R/W",  0,      0,      0ull,   0ull},
49309         {"RESERVED_14_63"              ,        14,     50,     454,    "RAZ",  1,      1,      0,      0},
49310         {"BA"                          ,        0,      30,     455,    "R/W",  0,      1,      0ull,   0},
49311         {"ROW"                         ,        30,     1,      455,    "R/W",  0,      1,      0ull,   0},
49312         {"ROR"                         ,        31,     1,      455,    "R/W",  0,      1,      0ull,   0},
49313         {"NSW"                         ,        32,     1,      455,    "R/W",  0,      1,      0ull,   0},
49314         {"NSR"                         ,        33,     1,      455,    "R/W",  0,      1,      0ull,   0},
49315         {"ESW"                         ,        34,     2,      455,    "R/W",  0,      1,      0ull,   0},
49316         {"ESR"                         ,        36,     2,      455,    "R/W",  0,      1,      0ull,   0},
49317         {"NMERGE"                      ,        38,     1,      455,    "R/W",  0,      0,      0ull,   0ull},
49318         {"PORT"                        ,        39,     2,      455,    "R/W",  0,      1,      0ull,   0},
49319         {"ZERO"                        ,        41,     1,      455,    "R/W",  0,      0,      0ull,   0ull},
49320         {"RESERVED_42_63"              ,        42,     22,     455,    "RAZ",  1,      1,      0,      0},
49321         {"ENB"                         ,        0,      64,     456,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
49322         {"ENB"                         ,        0,      64,     457,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
49323         {"ENB"                         ,        0,      64,     458,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
49324         {"ENB"                         ,        0,      64,     459,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
49325         {"INTR"                        ,        0,      64,     460,    "R/W1C",        0,      0,      0ull,   0ull},
49326         {"INTR"                        ,        0,      64,     461,    "R/W1C",        0,      0,      0ull,   0ull},
49327         {"INTR"                        ,        0,      64,     462,    "R/W1C",        0,      0,      0ull,   0ull},
49328         {"INTR"                        ,        0,      64,     463,    "R/W1C",        0,      0,      0ull,   0ull},
49329         {"MSI_INT"                     ,        0,      8,      464,    "R/W",  0,      1,      0ull,   0},
49330         {"RD_INT"                      ,        8,      8,      464,    "RO",   0,      1,      0ull,   0},
49331         {"RESERVED_16_63"              ,        16,     48,     464,    "RAZ",  1,      1,      0,      0},
49332         {"CLR"                         ,        0,      64,     465,    "R/W",  0,      0,      0ull,   0ull},
49333         {"CLR"                         ,        0,      64,     466,    "R/W",  0,      0,      0ull,   0ull},
49334         {"CLR"                         ,        0,      64,     467,    "R/W",  0,      0,      0ull,   0ull},
49335         {"CLR"                         ,        0,      64,     468,    "R/W",  0,      0,      0ull,   0ull},
49336         {"SET"                         ,        0,      64,     469,    "R/W",  0,      0,      0ull,   0ull},
49337         {"SET"                         ,        0,      64,     470,    "R/W",  0,      0,      0ull,   0ull},
49338         {"SET"                         ,        0,      64,     471,    "R/W",  0,      0,      0ull,   0ull},
49339         {"SET"                         ,        0,      64,     472,    "R/W",  0,      0,      0ull,   0ull},
49340         {"MSI_INT"                     ,        0,      8,      473,    "R/W",  0,      1,      0ull,   0},
49341         {"CIU_INT"                     ,        8,      8,      473,    "R/W",  0,      1,      0ull,   0},
49342         {"RESERVED_16_63"              ,        16,     48,     473,    "RAZ",  1,      1,      0,      0},
49343         {"P0_PCNT"                     ,        0,      8,      474,    "R/W",  0,      0,      128ull, 128ull},
49344         {"P0_NCNT"                     ,        8,      8,      474,    "R/W",  0,      0,      16ull,  16ull},
49345         {"P0_CCNT"                     ,        16,     8,      474,    "R/W",  0,      0,      128ull, 128ull},
49346         {"P1_PCNT"                     ,        24,     8,      474,    "R/W",  0,      0,      128ull, 128ull},
49347         {"P1_NCNT"                     ,        32,     8,      474,    "R/W",  0,      0,      16ull,  16ull},
49348         {"P1_CCNT"                     ,        40,     8,      474,    "R/W",  0,      0,      128ull, 128ull},
49349         {"RESERVED_48_63"              ,        48,     16,     474,    "RAZ",  1,      1,      0,      0},
49350         {"INTR"                        ,        0,      8,      475,    "R/W",  0,      1,      0ull,   0},
49351         {"RESERVED_8_63"               ,        8,      56,     475,    "RAZ",  1,      1,      0,      0},
49352         {"RESERVED_0_7"                ,        0,      8,      476,    "RAZ",  1,      1,      0,      0},
49353         {"INTR"                        ,        8,      8,      476,    "R/W",  0,      1,      0ull,   0},
49354         {"RESERVED_16_63"              ,        16,     48,     476,    "RAZ",  1,      1,      0,      0},
49355         {"RESERVED_0_15"               ,        0,      16,     477,    "RAZ",  1,      1,      0,      0},
49356         {"INTR"                        ,        16,     8,      477,    "R/W",  0,      1,      0ull,   0},
49357         {"RESERVED_24_63"              ,        24,     40,     477,    "RAZ",  1,      1,      0,      0},
49358         {"RESERVED_0_23"               ,        0,      24,     478,    "RAZ",  1,      1,      0,      0},
49359         {"INTR"                        ,        24,     8,      478,    "R/W",  0,      1,      0ull,   0},
49360         {"RESERVED_32_63"              ,        32,     32,     478,    "RAZ",  1,      1,      0,      0},
49361         {"CNT"                         ,        0,      32,     479,    "R/W",  0,      0,      0ull,   0ull},
49362         {"TIMER"                       ,        32,     22,     479,    "RO",   0,      0,      0ull,   0ull},
49363         {"RESERVED_54_63"              ,        54,     10,     479,    "RAZ",  1,      1,      0,      0},
49364         {"CNT"                         ,        0,      32,     480,    "R/W",  0,      0,      0ull,   0ull},
49365         {"WMARK"                       ,        32,     32,     480,    "R/W",  0,      1,      4294967295ull,  0},
49366         {"RESERVED_0_2"                ,        0,      3,      481,    "RAZ",  1,      1,      0,      0},
49367         {"ADDR"                        ,        3,      61,     481,    "R/W",  0,      1,      0ull,   0},
49368         {"DBELL"                       ,        0,      32,     482,    "R/W",  0,      0,      0ull,   0ull},
49369         {"AOFF"                        ,        32,     32,     482,    "RO",   0,      1,      0ull,   0},
49370         {"RSIZE"                       ,        0,      32,     483,    "R/W",  0,      1,      0ull,   0},
49371         {"FCNT"                        ,        32,     5,      483,    "RO",   0,      1,      0ull,   0},
49372         {"WRP"                         ,        37,     9,      483,    "RO",   0,      1,      0ull,   0},
49373         {"RRP"                         ,        46,     9,      483,    "RO",   0,      1,      0ull,   0},
49374         {"MAX"                         ,        55,     9,      483,    "RO",   0,      1,      16ull,  0},
49375         {"RESERVED_0_5"                ,        0,      6,      484,    "RAZ",  0,      1,      0ull,   0},
49376         {"SKP_LEN"                     ,        6,      7,      484,    "R/W",  0,      1,      0ull,   0},
49377         {"RESERVED_13_13"              ,        13,     1,      484,    "RAZ",  0,      1,      0ull,   0},
49378         {"PAR_MODE"                    ,        14,     2,      484,    "R/W",  0,      1,      0ull,   0},
49379         {"RESERVED_16_20"              ,        16,     5,      484,    "RAZ",  0,      1,      0ull,   0},
49380         {"USE_IHDR"                    ,        21,     1,      484,    "R/W",  0,      1,      0ull,   0},
49381         {"RESERVED_22_27"              ,        22,     6,      484,    "R/W",  0,      1,      0ull,   0},
49382         {"RSKP_LEN"                    ,        28,     7,      484,    "R/W",  0,      1,      0ull,   0},
49383         {"RESERVED_35_35"              ,        35,     1,      484,    "RAZ",  0,      1,      0ull,   0},
49384         {"RPARMODE"                    ,        36,     2,      484,    "R/W",  0,      1,      0ull,   0},
49385         {"RESERVED_38_42"              ,        38,     5,      484,    "RAZ",  0,      1,      0ull,   0},
49386         {"PBP"                         ,        43,     1,      484,    "R/W",  0,      1,      0ull,   0},
49387         {"RESERVED_44_63"              ,        44,     20,     484,    "RAZ",  1,      1,      0,      0},
49388         {"RESERVED_0_3"                ,        0,      4,      485,    "RAZ",  1,      1,      0,      0},
49389         {"ADDR"                        ,        4,      60,     485,    "R/W",  0,      1,      0ull,   0},
49390         {"DBELL"                       ,        0,      32,     486,    "R/W",  0,      0,      0ull,   0ull},
49391         {"AOFF"                        ,        32,     32,     486,    "RO",   0,      1,      0ull,   0},
49392         {"RSIZE"                       ,        0,      32,     487,    "R/W",  0,      1,      0ull,   0},
49393         {"RESERVED_32_63"              ,        32,     32,     487,    "RAZ",  0,      1,      0ull,   0},
49394         {"PORT"                        ,        0,      32,     488,    "R/W1C",        0,      1,      0ull,   0},
49395         {"RESERVED_32_63"              ,        32,     32,     488,    "RAZ",  1,      1,      0,      0},
49396         {"PORT"                        ,        0,      32,     489,    "R/W",  0,      1,      0ull,   0},
49397         {"RESERVED_32_63"              ,        32,     32,     489,    "RAZ",  1,      1,      0,      0},
49398         {"ES"                          ,        0,      64,     490,    "R/W",  0,      1,      0ull,   0},
49399         {"NSR"                         ,        0,      32,     491,    "R/W",  0,      1,      0ull,   0},
49400         {"RESERVED_32_63"              ,        32,     32,     491,    "RAZ",  1,      1,      0,      0},
49401         {"ROR"                         ,        0,      32,     492,    "R/W",  0,      1,      0ull,   0},
49402         {"RESERVED_32_63"              ,        32,     32,     492,    "RAZ",  1,      1,      0,      0},
49403         {"DPTR"                        ,        0,      32,     493,    "R/W",  0,      0,      0ull,   4294967295ull},
49404         {"RESERVED_32_63"              ,        32,     32,     493,    "RAZ",  1,      1,      0,      0},
49405         {"BP"                          ,        0,      32,     494,    "RO",   0,      1,      0ull,   0},
49406         {"RESERVED_32_63"              ,        32,     32,     494,    "RAZ",  1,      1,      0,      0},
49407         {"CNT"                         ,        0,      32,     495,    "RO",   0,      1,      0ull,   0},
49408         {"RESERVED_32_63"              ,        32,     32,     495,    "RAZ",  0,      1,      0ull,   0},
49409         {"RD_CNT"                      ,        0,      32,     496,    "RO",   0,      1,      0ull,   0},
49410         {"WR_CNT"                      ,        32,     32,     496,    "RO",   0,      1,      0ull,   0},
49411         {"PP"                          ,        0,      64,     497,    "R/W",  0,      1,      0ull,   0},
49412         {"ROR"                         ,        0,      1,      498,    "R/W",  0,      1,      0ull,   0},
49413         {"ESR"                         ,        1,      2,      498,    "R/W",  0,      1,      0ull,   0},
49414         {"NSR"                         ,        3,      1,      498,    "R/W",  0,      1,      0ull,   0},
49415         {"USE_CSR"                     ,        4,      1,      498,    "R/W",  0,      0,      0ull,   1ull},
49416         {"D_ROR"                       ,        5,      1,      498,    "R/W",  0,      1,      0ull,   0},
49417         {"D_ESR"                       ,        6,      2,      498,    "R/W",  0,      1,      0ull,   0},
49418         {"D_NSR"                       ,        8,      1,      498,    "R/W",  0,      1,      0ull,   0},
49419         {"PBP_DHI"                     ,        9,      13,     498,    "R/W",  0,      0,      0ull,   0ull},
49420         {"PKT_RR"                      ,        22,     1,      498,    "R/W",  0,      0,      0ull,   1ull},
49421         {"RESERVED_23_63"              ,        23,     41,     498,    "RAZ",  1,      1,      0,      0},
49422         {"ENB"                         ,        0,      32,     499,    "R/W",  0,      1,      0ull,   0},
49423         {"RESERVED_32_63"              ,        32,     32,     499,    "RAZ",  1,      1,      0,      0},
49424         {"RDSIZE"                      ,        0,      64,     500,    "R/W",  0,      1,      0ull,   0},
49425         {"IS_64B"                      ,        0,      32,     501,    "R/W",  0,      1,      0ull,   0},
49426         {"RESERVED_32_63"              ,        32,     32,     501,    "RAZ",  1,      1,      0,      0},
49427         {"CNT"                         ,        0,      32,     502,    "R/W",  0,      1,      0ull,   0},
49428         {"TIME"                        ,        32,     22,     502,    "R/W",  0,      1,      0ull,   0},
49429         {"RESERVED_54_63"              ,        54,     10,     502,    "RAZ",  1,      1,      0,      0},
49430         {"IPTR"                        ,        0,      32,     503,    "R/W",  0,      1,      0ull,   0},
49431         {"RESERVED_32_63"              ,        32,     32,     503,    "RAZ",  1,      1,      0,      0},
49432         {"BMODE"                       ,        0,      32,     504,    "R/W",  0,      1,      0ull,   0},
49433         {"RESERVED_32_63"              ,        32,     32,     504,    "RAZ",  1,      1,      0,      0},
49434         {"ENB"                         ,        0,      32,     505,    "R/W",  0,      1,      0ull,   0},
49435         {"RESERVED_32_63"              ,        32,     32,     505,    "RAZ",  1,      1,      0,      0},
49436         {"WMARK"                       ,        0,      32,     506,    "R/W",  0,      0,      0ull,   14ull},
49437         {"RESERVED_32_63"              ,        32,     32,     506,    "RAZ",  1,      1,      0,      0},
49438         {"PP"                          ,        0,      64,     507,    "R/W",  0,      1,      0ull,   0},
49439         {"OUT_RST"                     ,        0,      32,     508,    "RO",   0,      1,      0ull,   0},
49440         {"IN_RST"                      ,        32,     32,     508,    "RO",   0,      1,      0ull,   0},
49441         {"ES"                          ,        0,      64,     509,    "R/W",  0,      1,      0ull,   0},
49442         {"BSIZE"                       ,        0,      16,     510,    "R/W",  0,      1,      0ull,   0},
49443         {"ISIZE"                       ,        16,     7,      510,    "R/W",  0,      1,      0ull,   0},
49444         {"RESERVED_23_63"              ,        23,     41,     510,    "RAZ",  1,      1,      0,      0},
49445         {"NSR"                         ,        0,      32,     511,    "R/W",  0,      1,      0ull,   0},
49446         {"RESERVED_32_63"              ,        32,     32,     511,    "RAZ",  1,      1,      0,      0},
49447         {"ROR"                         ,        0,      32,     512,    "R/W",  0,      1,      0ull,   0},
49448         {"RESERVED_32_63"              ,        32,     32,     512,    "RAZ",  1,      1,      0,      0},
49449         {"PORT"                        ,        0,      32,     513,    "R/W1C",        0,      1,      0ull,   0},
49450         {"RESERVED_32_63"              ,        32,     32,     513,    "RAZ",  1,      1,      0,      0},
49451         {"PORT"                        ,        0,      32,     514,    "R/W",  0,      1,      0ull,   0},
49452         {"RESERVED_32_63"              ,        32,     32,     514,    "RAZ",  1,      1,      0,      0},
49453         {"MIO"                         ,        0,      1,      515,    "RO",   0,      0,      0ull,   0ull},
49454         {"GMX0"                        ,        1,      1,      515,    "RO",   0,      0,      0ull,   0ull},
49455         {"GMX1"                        ,        2,      1,      515,    "RO",   0,      0,      0ull,   0ull},
49456         {"NPEI"                        ,        3,      1,      515,    "RO",   0,      0,      0ull,   0ull},
49457         {"KEY"                         ,        4,      1,      515,    "RO",   0,      0,      0ull,   0ull},
49458         {"FPA"                         ,        5,      1,      515,    "RO",   0,      0,      0ull,   0ull},
49459         {"DFA"                         ,        6,      1,      515,    "RAZ",  0,      0,      0ull,   0ull},
49460         {"ZIP"                         ,        7,      1,      515,    "RO",   0,      0,      0ull,   0ull},
49461         {"RESERVED_8_8"                ,        8,      1,      515,    "RAZ",  0,      0,      0ull,   0ull},
49462         {"IPD"                         ,        9,      1,      515,    "RO",   0,      0,      0ull,   0ull},
49463         {"PKO"                         ,        10,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49464         {"TIM"                         ,        11,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49465         {"POW"                         ,        12,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49466         {"USB"                         ,        13,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49467         {"RAD"                         ,        14,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49468         {"USB1"                        ,        15,     1,      515,    "RAZ",  0,      0,      0ull,   0ull},
49469         {"L2C"                         ,        16,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49470         {"LMC0"                        ,        17,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49471         {"SPX0"                        ,        18,     1,      515,    "RAZ",  0,      0,      0ull,   0ull},
49472         {"SPX1"                        ,        19,     1,      515,    "RAZ",  0,      0,      0ull,   0ull},
49473         {"PIP"                         ,        20,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49474         {"RESERVED_21_21"              ,        21,     1,      515,    "RAZ",  0,      0,      0ull,   0ull},
49475         {"ASXPCS0"                     ,        22,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49476         {"ASXPCS1"                     ,        23,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49477         {"RESERVED_24_27"              ,        24,     4,      515,    "RAZ",  0,      0,      0ull,   0ull},
49478         {"AGL"                         ,        28,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49479         {"LMC1"                        ,        29,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49480         {"IOB"                         ,        30,     1,      515,    "RO",   0,      0,      0ull,   0ull},
49481         {"RESERVED_31_63"              ,        31,     33,     515,    "RAZ",  0,      0,      0ull,   0ull},
49482         {"DATA"                        ,        0,      64,     516,    "R/W",  0,      1,      0ull,   0},
49483         {"CSR"                         ,        0,      39,     517,    "RO",   0,      1,      1ull,   0},
49484         {"ARB"                         ,        39,     1,      517,    "RO",   0,      1,      0ull,   0},
49485         {"CPL0"                        ,        40,     12,     517,    "RO",   0,      1,      1ull,   0},
49486         {"CPL1"                        ,        52,     12,     517,    "RO",   0,      1,      1ull,   0},
49487         {"NND"                         ,        0,      8,      518,    "RO",   0,      1,      1ull,   0},
49488         {"NNP0"                        ,        8,      8,      518,    "RO",   0,      1,      1ull,   0},
49489         {"CSM0"                        ,        16,     15,     518,    "RO",   0,      1,      1ull,   0},
49490         {"CSM1"                        ,        31,     15,     518,    "RO",   0,      1,      1ull,   0},
49491         {"RAC"                         ,        46,     1,      518,    "RO",   0,      1,      1ull,   0},
49492         {"NPEI"                        ,        47,     1,      518,    "RO",   0,      1,      1ull,   0},
49493         {"RESERVED_48_63"              ,        48,     16,     518,    "RAZ",  1,      1,      0,      0},
49494         {"NSM0"                        ,        0,      13,     519,    "RO",   0,      1,      1ull,   0},
49495         {"NSM1"                        ,        13,     13,     519,    "RO",   0,      1,      1ull,   0},
49496         {"PSM0"                        ,        26,     15,     519,    "RO",   0,      1,      1ull,   0},
49497         {"PSM1"                        ,        41,     15,     519,    "RO",   0,      1,      1ull,   0},
49498         {"RESERVED_56_63"              ,        56,     8,      519,    "RAZ",  1,      1,      0,      0},
49499         {"RD_ADDR"                     ,        0,      48,     520,    "R/W",  0,      1,      0ull,   0},
49500         {"IOBIT"                       ,        48,     1,      520,    "RAZ",  0,      0,      0ull,   0ull},
49501         {"LD_CMD"                      ,        49,     2,      520,    "R/W",  0,      1,      0ull,   0},
49502         {"RESERVED_51_63"              ,        51,     13,     520,    "RAZ",  1,      1,      0,      0},
49503         {"RD_DATA"                     ,        0,      64,     521,    "RO",   0,      1,      0ull,   0},
49504         {"RESERVED_0_1"                ,        0,      2,      522,    "RAZ",  1,      1,      0,      0},
49505         {"WR_ADDR"                     ,        2,      46,     522,    "R/W",  0,      1,      0ull,   0},
49506         {"IOBIT"                       ,        48,     1,      522,    "RAZ",  0,      0,      0ull,   0ull},
49507         {"RESERVED_49_63"              ,        49,     15,     522,    "RAZ",  1,      1,      0,      0},
49508         {"WR_DATA"                     ,        0,      64,     523,    "R/W",  0,      1,      0ull,   0},
49509         {"WR_MASK"                     ,        0,      8,      524,    "R/W",  0,      0,      0ull,   0ull},
49510         {"RESERVED_8_63"               ,        8,      56,     524,    "RAZ",  1,      1,      0,      0},
49511         {"TIME"                        ,        0,      32,     525,    "R/W",  0,      0,      0ull,   2097152ull},
49512         {"RESERVED_32_63"              ,        32,     32,     525,    "RAZ",  1,      1,      0,      0},
49513         {"VENDID"                      ,        0,      16,     526,    "RO/WRSL",      0,      0,      6013ull,        6013ull},
49514         {"DEVID"                       ,        16,     16,     526,    "RO/WRSL",      0,      0,      80ull,  80ull},
49515         {"ISAE"                        ,        0,      1,      527,    "R/W",  0,      0,      0ull,   0ull},
49516         {"MSAE"                        ,        1,      1,      527,    "R/W",  0,      0,      0ull,   0ull},
49517         {"ME"                          ,        2,      1,      527,    "R/W",  0,      0,      0ull,   0ull},
49518         {"SCSE"                        ,        3,      1,      527,    "RO",   0,      0,      0ull,   0ull},
49519         {"MWICE"                       ,        4,      1,      527,    "RO",   0,      0,      0ull,   0ull},
49520         {"VPS"                         ,        5,      1,      527,    "RO",   0,      0,      0ull,   0ull},
49521         {"PER"                         ,        6,      1,      527,    "R/W",  0,      0,      0ull,   0ull},
49522         {"IDS_WCC"                     ,        7,      1,      527,    "RO",   0,      0,      0ull,   0ull},
49523         {"SEE"                         ,        8,      1,      527,    "R/W",  0,      0,      0ull,   0ull},
49524         {"FBBE"                        ,        9,      1,      527,    "RO",   0,      0,      0ull,   0ull},
49525         {"I_DIS"                       ,        10,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
49526         {"RESERVED_11_18"              ,        11,     8,      527,    "RAZ",  1,      1,      0,      0},
49527         {"I_STAT"                      ,        19,     1,      527,    "RO",   0,      0,      0ull,   0ull},
49528         {"CL"                          ,        20,     1,      527,    "RO",   0,      0,      1ull,   1ull},
49529         {"M66"                         ,        21,     1,      527,    "RO",   0,      0,      0ull,   0ull},
49530         {"RESERVED_22_22"              ,        22,     1,      527,    "RAZ",  1,      1,      0,      0},
49531         {"FBB"                         ,        23,     1,      527,    "RO",   0,      0,      0ull,   0ull},
49532         {"MDPE"                        ,        24,     1,      527,    "R/W1C",        0,      0,      0ull,   0ull},
49533         {"DEVT"                        ,        25,     2,      527,    "RO",   0,      0,      0ull,   0ull},
49534         {"STA"                         ,        27,     1,      527,    "R/W1C",        0,      0,      0ull,   0ull},
49535         {"RTA"                         ,        28,     1,      527,    "R/W1C",        0,      0,      0ull,   0ull},
49536         {"RMA"                         ,        29,     1,      527,    "R/W1C",        0,      0,      0ull,   0ull},
49537         {"SSE"                         ,        30,     1,      527,    "R/W1C",        0,      0,      0ull,   0ull},
49538         {"DPE"                         ,        31,     1,      527,    "R/W1C",        0,      0,      0ull,   0ull},
49539         {"RID"                         ,        0,      8,      528,    "RO/WRSL",      0,      0,      8ull,   8ull},
49540         {"PI"                          ,        8,      8,      528,    "RO/WRSL",      0,      0,      0ull,   0ull},
49541         {"SC"                          ,        16,     8,      528,    "RO/WRSL",      0,      0,      48ull,  48ull},
49542         {"BCC"                         ,        24,     8,      528,    "RO/WRSL",      0,      0,      11ull,  11ull},
49543         {"CLS"                         ,        0,      8,      529,    "R/W",  0,      0,      0ull,   0ull},
49544         {"LT"                          ,        8,      8,      529,    "RO",   0,      0,      0ull,   0ull},
49545         {"CHF"                         ,        16,     7,      529,    "RO",   0,      0,      0ull,   0ull},
49546         {"MFD"                         ,        23,     1,      529,    "RO/WRSL",      0,      0,      0ull,   0ull},
49547         {"BIST"                        ,        24,     8,      529,    "RO",   0,      0,      0ull,   0ull},
49548         {"MSPC"                        ,        0,      1,      530,    "RO/WRSL",      0,      0,      0ull,   0ull},
49549         {"TYP"                         ,        1,      2,      530,    "RO/WRSL",      0,      0,      2ull,   2ull},
49550         {"PF"                          ,        3,      1,      530,    "RO/WRSL",      0,      0,      1ull,   1ull},
49551         {"RESERVED_4_13"               ,        4,      10,     530,    "RAZ",  1,      1,      0,      0},
49552         {"LBAB"                        ,        14,     18,     530,    "R/W",  0,      0,      0ull,   0ull},
49553         {"ENB"                         ,        0,      1,      531,    "WORSL",        0,      0,      1ull,   1ull},
49554         {"LMASK"                       ,        1,      31,     531,    "WORSL",        0,      0,      8191ull,        8191ull},
49555         {"UBAB"                        ,        0,      32,     532,    "R/W",  0,      0,      0ull,   0ull},
49556         {"UMASK"                       ,        0,      32,     533,    "WORSL",        0,      0,      0ull,   0ull},
49557         {"MSPC"                        ,        0,      1,      534,    "RO/WRSL",      0,      0,      0ull,   0ull},
49558         {"TYP"                         ,        1,      2,      534,    "RO/WRSL",      0,      0,      2ull,   2ull},
49559         {"PF"                          ,        3,      1,      534,    "RO/WRSL",      0,      0,      1ull,   1ull},
49560         {"RESERVED_4_25"               ,        4,      22,     534,    "RAZ",  1,      1,      0,      0},
49561         {"LBAB"                        ,        26,     6,      534,    "R/W",  0,      0,      0ull,   0ull},
49562         {"ENB"                         ,        0,      1,      535,    "WORSL",        0,      0,      1ull,   1ull},
49563         {"LMASK"                       ,        1,      31,     535,    "WORSL",        0,      0,      33554431ull,    33554431ull},
49564         {"UBAB"                        ,        0,      32,     536,    "R/W",  0,      0,      0ull,   0ull},
49565         {"UMASK"                       ,        0,      32,     537,    "WORSL",        0,      0,      0ull,   0ull},
49566         {"MSPC"                        ,        0,      1,      538,    "RO/WRSL",      0,      0,      0ull,   0ull},
49567         {"TYP"                         ,        1,      2,      538,    "RO/WRSL",      0,      0,      2ull,   2ull},
49568         {"PF"                          ,        3,      1,      538,    "RO/WRSL",      0,      0,      1ull,   1ull},
49569         {"RESERVED_4_31"               ,        4,      28,     538,    "RAZ",  1,      1,      0,      0},
49570         {"ENB"                         ,        0,      1,      539,    "WORSL",        0,      0,      1ull,   1ull},
49571         {"LMASK"                       ,        1,      31,     539,    "WORSL",        0,      0,      2147483647ull,  2147483647ull},
49572         {"RESERVED_0_6"                ,        0,      7,      540,    "RAZ",  1,      1,      0,      0},
49573         {"UBAB"                        ,        7,      25,     540,    "R/W",  0,      0,      0ull,   0ull},
49574         {"UMASK"                       ,        0,      32,     541,    "WORSL",        0,      0,      127ull, 127ull},
49575         {"CISP"                        ,        0,      32,     542,    "RO/WRSL",      0,      0,      0ull,   0ull},
49576         {"SSVID"                       ,        0,      16,     543,    "RO/WRSL",      0,      0,      6013ull,        6013ull},
49577         {"SSID"                        ,        16,     16,     543,    "RO/WRSL",      0,      0,      1ull,   1ull},
49578         {"ER_EN"                       ,        0,      1,      544,    "R/W",  0,      0,      0ull,   0ull},
49579         {"RESERVED_1_15"               ,        1,      15,     544,    "RAZ",  1,      1,      0,      0},
49580         {"ERADDR"                      ,        16,     16,     544,    "R/W",  0,      0,      0ull,   0ull},
49581         {"ENB"                         ,        0,      1,      545,    "WORSL",        0,      0,      1ull,   1ull},
49582         {"MASK"                        ,        1,      31,     545,    "WORSL",        0,      0,      2147483647ull,  2147483647ull},
49583         {"CP"                          ,        0,      8,      546,    "RO/WRSL",      0,      0,      64ull,  64ull},
49584         {"RESERVED_8_31"               ,        8,      24,     546,    "RAZ",  1,      1,      0,      0},
49585         {"IL"                          ,        0,      8,      547,    "R/W",  0,      0,      255ull, 255ull},
49586         {"INTA"                        ,        8,      8,      547,    "RO/WRSL",      0,      0,      1ull,   1ull},
49587         {"MG"                          ,        16,     8,      547,    "RO",   0,      0,      0ull,   0ull},
49588         {"ML"                          ,        24,     8,      547,    "RO",   0,      0,      0ull,   0ull},
49589         {"PMCID"                       ,        0,      8,      548,    "RO",   0,      0,      1ull,   0ull},
49590         {"NCP"                         ,        8,      8,      548,    "RO/WRSL",      0,      0,      80ull,  0ull},
49591         {"PMSV"                        ,        16,     3,      548,    "RO/WRSL",      0,      0,      3ull,   0ull},
49592         {"PME_CLOCK"                   ,        19,     1,      548,    "RO",   0,      0,      0ull,   0ull},
49593         {"RESERVED_20_20"              ,        20,     1,      548,    "RAZ",  1,      1,      0,      0},
49594         {"DSI"                         ,        21,     1,      548,    "RO/WRSL",      0,      0,      0ull,   0ull},
49595         {"AUXC"                        ,        22,     3,      548,    "RO/WRSL",      0,      0,      0ull,   0ull},
49596         {"D1S"                         ,        25,     1,      548,    "RO/WRSL",      0,      0,      0ull,   0ull},
49597         {"D2S"                         ,        26,     1,      548,    "RO/WRSL",      0,      0,      0ull,   0ull},
49598         {"PMES"                        ,        27,     5,      548,    "RO/WRSL",      0,      0,      0ull,   0ull},
49599         {"PS"                          ,        0,      2,      549,    "R/W",  0,      0,      0ull,   0ull},
49600         {"RESERVED_2_2"                ,        2,      1,      549,    "RAZ",  1,      1,      0,      0},
49601         {"NSR"                         ,        3,      1,      549,    "RO/WRSL",      0,      0,      0ull,   0ull},
49602         {"RESERVED_4_7"                ,        4,      4,      549,    "RAZ",  1,      1,      0,      0},
49603         {"PMEENS"                      ,        8,      1,      549,    "R/W",  0,      0,      0ull,   0ull},
49604         {"PMDS"                        ,        9,      4,      549,    "RO",   0,      0,      0ull,   0ull},
49605         {"PMEDSIA"                     ,        13,     2,      549,    "RO",   0,      0,      0ull,   0ull},
49606         {"PMESS"                       ,        15,     1,      549,    "R/W1C",        0,      0,      0ull,   0ull},
49607         {"RESERVED_16_21"              ,        16,     6,      549,    "RAZ",  1,      1,      0,      0},
49608         {"BD3H"                        ,        22,     1,      549,    "RO",   0,      0,      0ull,   0ull},
49609         {"BPCCEE"                      ,        23,     1,      549,    "RO",   0,      0,      0ull,   0ull},
49610         {"PMDIA"                       ,        24,     8,      549,    "RO",   0,      0,      0ull,   0ull},
49611         {"MSICID"                      ,        0,      8,      550,    "RO",   0,      0,      5ull,   5ull},
49612         {"NCP"                         ,        8,      8,      550,    "RO/WRSL",      0,      0,      112ull, 112ull},
49613         {"MSIEN"                       ,        16,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
49614         {"MMC"                         ,        17,     3,      550,    "RO/WRSL",      0,      0,      0ull,   0ull},
49615         {"MME"                         ,        20,     3,      550,    "R/W",  0,      0,      0ull,   0ull},
49616         {"M64"                         ,        23,     1,      550,    "RO/WRSL",      0,      0,      1ull,   1ull},
49617         {"RESERVED_24_31"              ,        24,     8,      550,    "RAZ",  1,      1,      0,      0},
49618         {"RESERVED_0_1"                ,        0,      2,      551,    "RAZ",  1,      1,      0,      0},
49619         {"LMSI"                        ,        2,      30,     551,    "R/W",  0,      0,      0ull,   0ull},
49620         {"UMSI"                        ,        0,      32,     552,    "R/W",  0,      0,      0ull,   0ull},
49621         {"MSIMD"                       ,        0,      16,     553,    "R/W",  0,      0,      0ull,   0ull},
49622         {"RESERVED_16_31"              ,        16,     16,     553,    "RAZ",  1,      1,      0,      0},
49623         {"PCIEID"                      ,        0,      8,      554,    "RO",   0,      0,      16ull,  16ull},
49624         {"NCP"                         ,        8,      8,      554,    "RO/WRSL",      0,      0,      0ull,   0ull},
49625         {"PCIECV"                      ,        16,     4,      554,    "RO",   0,      0,      2ull,   2ull},
49626         {"DPT"                         ,        20,     4,      554,    "RO",   0,      0,      0ull,   0ull},
49627         {"SI"                          ,        24,     1,      554,    "RO/WRSL",      0,      0,      0ull,   0ull},
49628         {"IMN"                         ,        25,     5,      554,    "RO/WRSL",      0,      0,      0ull,   0ull},
49629         {"RESERVED_30_31"              ,        30,     2,      554,    "RAZ",  1,      1,      0,      0},
49630         {"MPSS"                        ,        0,      3,      555,    "RO/WRSL",      0,      0,      1ull,   1ull},
49631         {"PFS"                         ,        3,      2,      555,    "RO/WRSL",      0,      0,      0ull,   0ull},
49632         {"ETFS"                        ,        5,      1,      555,    "RO/WRSL",      0,      0,      0ull,   0ull},
49633         {"EL0AL"                       ,        6,      3,      555,    "RO/WRSL",      0,      0,      4ull,   4ull},
49634         {"EL1AL"                       ,        9,      3,      555,    "RO/WRSL",      0,      0,      3ull,   3ull},
49635         {"RESERVED_12_14"              ,        12,     3,      555,    "RAZ",  1,      1,      0,      0},
49636         {"RBER"                        ,        15,     1,      555,    "RO/WRSL",      0,      0,      1ull,   1ull},
49637         {"RESERVED_16_17"              ,        16,     2,      555,    "RAZ",  1,      1,      0,      0},
49638         {"CSPLV"                       ,        18,     8,      555,    "RO",   0,      0,      0ull,   0ull},
49639         {"CSPLS"                       ,        26,     2,      555,    "RO",   0,      0,      0ull,   0ull},
49640         {"RESERVED_28_31"              ,        28,     4,      555,    "RAZ",  1,      1,      0,      0},
49641         {"CE_EN"                       ,        0,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
49642         {"NFE_EN"                      ,        1,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
49643         {"FE_EN"                       ,        2,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
49644         {"UR_EN"                       ,        3,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
49645         {"RO_EN"                       ,        4,      1,      556,    "R/W",  0,      0,      1ull,   1ull},
49646         {"MPS"                         ,        5,      3,      556,    "R/W",  0,      0,      0ull,   0ull},
49647         {"ETF_EN"                      ,        8,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
49648         {"PF_EN"                       ,        9,      1,      556,    "R/W",  0,      0,      0ull,   0ull},
49649         {"AP_EN"                       ,        10,     1,      556,    "R/W",  0,      0,      0ull,   0ull},
49650         {"NS_EN"                       ,        11,     1,      556,    "R/W",  0,      0,      1ull,   1ull},
49651         {"MRRS"                        ,        12,     3,      556,    "R/W",  0,      0,      2ull,   2ull},
49652         {"RESERVED_15_15"              ,        15,     1,      556,    "RAZ",  1,      1,      0,      0},
49653         {"CE_D"                        ,        16,     1,      556,    "R/W1C",        0,      0,      0ull,   0ull},
49654         {"NFE_D"                       ,        17,     1,      556,    "R/W1C",        0,      0,      0ull,   0ull},
49655         {"FE_D"                        ,        18,     1,      556,    "R/W1C",        0,      0,      0ull,   0ull},
49656         {"UR_D"                        ,        19,     1,      556,    "R/W1C",        0,      0,      0ull,   0ull},
49657         {"AP_D"                        ,        20,     1,      556,    "RO",   0,      0,      0ull,   0ull},
49658         {"TP"                          ,        21,     1,      556,    "RO",   0,      0,      0ull,   0ull},
49659         {"RESERVED_22_31"              ,        22,     10,     556,    "RAZ",  1,      1,      0,      0},
49660         {"MLS"                         ,        0,      4,      557,    "RO/WRSL",      0,      0,      1ull,   1ull},
49661         {"MLW"                         ,        4,      6,      557,    "RO/WRSL",      0,      0,      8ull,   8ull},
49662         {"ASLPMS"                      ,        10,     2,      557,    "RO/WRSL",      0,      0,      3ull,   3ull},
49663         {"L0EL"                        ,        12,     3,      557,    "RO/WRSL",      0,      0,      6ull,   6ull},
49664         {"L1EL"                        ,        15,     3,      557,    "RO/WRSL",      0,      0,      6ull,   6ull},
49665         {"CPM"                         ,        18,     1,      557,    "RO/WRSL",      0,      0,      0ull,   0ull},
49666         {"SDERC"                       ,        19,     1,      557,    "RO",   0,      0,      0ull,   0ull},
49667         {"DLLARC"                      ,        20,     1,      557,    "RO",   0,      0,      0ull,   0ull},
49668         {"LBNC"                        ,        21,     1,      557,    "RO",   0,      0,      0ull,   0ull},
49669         {"RESERVED_22_23"              ,        22,     2,      557,    "RAZ",  1,      1,      0,      0},
49670         {"PNUM"                        ,        24,     8,      557,    "RO/WRSL",      0,      0,      0ull,   0ull},
49671         {"ASLPC"                       ,        0,      2,      558,    "R/W",  0,      0,      0ull,   0ull},
49672         {"RESERVED_2_2"                ,        2,      1,      558,    "RAZ",  1,      1,      0,      0},
49673         {"RCB"                         ,        3,      1,      558,    "RO",   0,      0,      0ull,   0ull},
49674         {"LD"                          ,        4,      1,      558,    "RO",   0,      0,      0ull,   0ull},
49675         {"RL"                          ,        5,      1,      558,    "RO",   0,      0,      0ull,   0ull},
49676         {"CCC"                         ,        6,      1,      558,    "R/W",  0,      0,      0ull,   0ull},
49677         {"ES"                          ,        7,      1,      558,    "R/W",  0,      0,      0ull,   0ull},
49678         {"ECPM"                        ,        8,      1,      558,    "R/W",  0,      0,      0ull,   0ull},
49679         {"HAWD"                        ,        9,      1,      558,    "R/W",  0,      0,      0ull,   0ull},
49680         {"RESERVED_10_15"              ,        10,     6,      558,    "RAZ",  1,      1,      0,      0},
49681         {"LS"                          ,        16,     4,      558,    "RO",   0,      0,      1ull,   1ull},
49682         {"NLW"                         ,        20,     6,      558,    "RO",   0,      0,      0ull,   8ull},
49683         {"RESERVED_26_26"              ,        26,     1,      558,    "RAZ",  1,      1,      0,      0},
49684         {"LT"                          ,        27,     1,      558,    "RO",   0,      0,      0ull,   0ull},
49685         {"SCC"                         ,        28,     1,      558,    "RO/WRSL",      0,      0,      1ull,   1ull},
49686         {"DLLA"                        ,        29,     1,      558,    "RO",   0,      0,      0ull,   0ull},
49687         {"RESERVED_30_31"              ,        30,     2,      558,    "RAZ",  1,      1,      0,      0},
49688         {"ABP"                         ,        0,      1,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49689         {"PCP"                         ,        1,      1,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49690         {"MRLSP"                       ,        2,      1,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49691         {"AIP"                         ,        3,      1,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49692         {"PIP"                         ,        4,      1,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49693         {"HP_S"                        ,        5,      1,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49694         {"HP_C"                        ,        6,      1,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49695         {"SP_LV"                       ,        7,      8,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49696         {"SP_LS"                       ,        15,     2,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49697         {"EMIP"                        ,        17,     1,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49698         {"NCCS"                        ,        18,     1,      559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49699         {"PS_NUM"                      ,        19,     13,     559,    "RO/WRSL",      0,      0,      0ull,   0ull},
49700         {"ABP_EN"                      ,        0,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
49701         {"PF_EN"                       ,        1,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
49702         {"MRLS_EN"                     ,        2,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
49703         {"PD_EN"                       ,        3,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
49704         {"CCINT_EN"                    ,        4,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
49705         {"HPINT_EN"                    ,        5,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
49706         {"AIC"                         ,        6,      2,      560,    "R/W",  0,      0,      0ull,   0ull},
49707         {"PIC"                         ,        8,      2,      560,    "R/W",  0,      0,      0ull,   0ull},
49708         {"PCC"                         ,        10,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
49709         {"EMIC"                        ,        11,     1,      560,    "R/W",  0,      0,      0ull,   0ull},
49710         {"DLLS_EN"                     ,        12,     1,      560,    "RO",   0,      0,      0ull,   0ull},
49711         {"RESERVED_13_15"              ,        13,     3,      560,    "RAZ",  1,      1,      0,      0},
49712         {"ABP_D"                       ,        16,     1,      560,    "R/W1C",        0,      0,      0ull,   0ull},
49713         {"PF_D"                        ,        17,     1,      560,    "R/W1C",        0,      0,      0ull,   0ull},
49714         {"MRLS_C"                      ,        18,     1,      560,    "R/W1C",        0,      0,      0ull,   0ull},
49715         {"PD_C"                        ,        19,     1,      560,    "R/W1C",        0,      0,      0ull,   0ull},
49716         {"CCINT_D"                     ,        20,     1,      560,    "R/W1C",        0,      0,      0ull,   0ull},
49717         {"MRLSS"                       ,        21,     1,      560,    "RO",   0,      0,      0ull,   0ull},
49718         {"PDS"                         ,        22,     1,      560,    "RO",   0,      0,      0ull,   0ull},
49719         {"EMIS"                        ,        23,     1,      560,    "RO",   0,      0,      0ull,   0ull},
49720         {"DLLS_C"                      ,        24,     1,      560,    "RO",   0,      0,      0ull,   0ull},
49721         {"RESERVED_25_31"              ,        25,     7,      560,    "RAZ",  1,      1,      0,      0},
49722         {"CTRS"                        ,        0,      4,      561,    "RO",   0,      0,      0ull,   0ull},
49723         {"CTDS"                        ,        4,      1,      561,    "RO",   0,      0,      1ull,   1ull},
49724         {"RESERVED_5_31"               ,        5,      27,     561,    "RAZ",  1,      1,      0,      0},
49725         {"CTV"                         ,        0,      4,      562,    "RO",   0,      0,      0ull,   0ull},
49726         {"CTD"                         ,        4,      1,      562,    "R/W",  0,      0,      0ull,   0ull},
49727         {"RESERVED_5_31"               ,        5,      27,     562,    "RAZ",  1,      1,      0,      0},
49728         {"RESERVED_0_31"               ,        0,      32,     563,    "RAZ",  1,      1,      0,      0},
49729         {"RESERVED_0_31"               ,        0,      32,     564,    "RAZ",  1,      1,      0,      0},
49730         {"RESERVED_0_31"               ,        0,      32,     565,    "RAZ",  1,      1,      0,      0},
49731         {"RESERVED_0_31"               ,        0,      32,     566,    "RAZ",  1,      1,      0,      0},
49732         {"PCIEEC"                      ,        0,      16,     567,    "RO",   0,      0,      1ull,   0ull},
49733         {"CV"                          ,        16,     4,      567,    "RO",   0,      0,      1ull,   0ull},
49734         {"NCO"                         ,        20,     12,     567,    "RO",   0,      0,      0ull,   0ull},
49735         {"RESERVED_0_3"                ,        0,      4,      568,    "RAZ",  1,      1,      0,      0},
49736         {"DLPES"                       ,        4,      1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49737         {"SDES"                        ,        5,      1,      568,    "RO",   0,      0,      0ull,   0ull},
49738         {"RESERVED_6_11"               ,        6,      6,      568,    "RAZ",  1,      1,      0,      0},
49739         {"PTLPS"                       ,        12,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49740         {"FCPES"                       ,        13,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49741         {"CTS"                         ,        14,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49742         {"CAS"                         ,        15,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49743         {"UCS"                         ,        16,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49744         {"ROS"                         ,        17,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49745         {"MTLPS"                       ,        18,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49746         {"ECRCES"                      ,        19,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49747         {"URES"                        ,        20,     1,      568,    "R/W1C",        0,      0,      0ull,   0ull},
49748         {"RESERVED_21_31"              ,        21,     11,     568,    "RAZ",  1,      1,      0,      0},
49749         {"RESERVED_0_3"                ,        0,      4,      569,    "RAZ",  1,      1,      0,      0},
49750         {"DLPEM"                       ,        4,      1,      569,    "R/W",  0,      0,      0ull,   0ull},
49751         {"SDEM"                        ,        5,      1,      569,    "RO",   0,      0,      0ull,   0ull},
49752         {"RESERVED_6_11"               ,        6,      6,      569,    "RAZ",  1,      1,      0,      0},
49753         {"PTLPM"                       ,        12,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
49754         {"FCPEM"                       ,        13,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
49755         {"CTM"                         ,        14,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
49756         {"CAM"                         ,        15,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
49757         {"UCM"                         ,        16,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
49758         {"ROM"                         ,        17,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
49759         {"MTLPM"                       ,        18,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
49760         {"ECRCEM"                      ,        19,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
49761         {"UREM"                        ,        20,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
49762         {"RESERVED_21_31"              ,        21,     11,     569,    "RAZ",  1,      1,      0,      0},
49763         {"RESERVED_0_3"                ,        0,      4,      570,    "RAZ",  1,      1,      0,      0},
49764         {"DLPES"                       ,        4,      1,      570,    "R/W",  0,      0,      1ull,   1ull},
49765         {"SDES"                        ,        5,      1,      570,    "RO",   0,      0,      1ull,   1ull},
49766         {"RESERVED_6_11"               ,        6,      6,      570,    "RAZ",  1,      1,      0,      0},
49767         {"PTLPS"                       ,        12,     1,      570,    "R/W",  0,      0,      0ull,   0ull},
49768         {"FCPES"                       ,        13,     1,      570,    "R/W",  0,      0,      1ull,   1ull},
49769         {"CTS"                         ,        14,     1,      570,    "R/W",  0,      0,      0ull,   0ull},
49770         {"CAS"                         ,        15,     1,      570,    "R/W",  0,      0,      0ull,   0ull},
49771         {"UCS"                         ,        16,     1,      570,    "R/W",  0,      0,      0ull,   0ull},
49772         {"ROS"                         ,        17,     1,      570,    "R/W",  0,      0,      1ull,   1ull},
49773         {"MTLPS"                       ,        18,     1,      570,    "R/W",  0,      0,      1ull,   1ull},
49774         {"ECRCES"                      ,        19,     1,      570,    "R/W",  0,      0,      0ull,   0ull},
49775         {"URES"                        ,        20,     1,      570,    "R/W",  0,      0,      0ull,   0ull},
49776         {"RESERVED_21_31"              ,        21,     11,     570,    "RAZ",  1,      1,      0,      0},
49777         {"RES"                         ,        0,      1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
49778         {"RESERVED_1_5"                ,        1,      5,      571,    "RAZ",  1,      1,      0,      0},
49779         {"BTLPS"                       ,        6,      1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
49780         {"BDLLPS"                      ,        7,      1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
49781         {"RNRS"                        ,        8,      1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
49782         {"RESERVED_9_11"               ,        9,      3,      571,    "RAZ",  1,      1,      0,      0},
49783         {"RTTS"                        ,        12,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
49784         {"ANFES"                       ,        13,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
49785         {"RESERVED_14_31"              ,        14,     18,     571,    "RAZ",  1,      1,      0,      0},
49786         {"REM"                         ,        0,      1,      572,    "R/W",  0,      0,      0ull,   0ull},
49787         {"RESERVED_1_5"                ,        1,      5,      572,    "RAZ",  1,      1,      0,      0},
49788         {"BTLPM"                       ,        6,      1,      572,    "R/W",  0,      0,      0ull,   0ull},
49789         {"BDLLPM"                      ,        7,      1,      572,    "R/W",  0,      0,      0ull,   0ull},
49790         {"RNRM"                        ,        8,      1,      572,    "R/W",  0,      0,      0ull,   0ull},
49791         {"RESERVED_9_11"               ,        9,      3,      572,    "RAZ",  1,      1,      0,      0},
49792         {"RTTM"                        ,        12,     1,      572,    "R/W",  0,      0,      0ull,   0ull},
49793         {"ANFEM"                       ,        13,     1,      572,    "R/W",  0,      0,      1ull,   1ull},
49794         {"RESERVED_14_31"              ,        14,     18,     572,    "RAZ",  1,      1,      0,      0},
49795         {"FEP"                         ,        0,      5,      573,    "RO",   0,      0,      0ull,   0ull},
49796         {"GC"                          ,        5,      1,      573,    "RO",   0,      0,      1ull,   1ull},
49797         {"GE"                          ,        6,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
49798         {"CC"                          ,        7,      1,      573,    "RO",   0,      0,      1ull,   1ull},
49799         {"CE"                          ,        8,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
49800         {"RESERVED_9_31"               ,        9,      23,     573,    "RAZ",  1,      1,      0,      0},
49801         {"DWORD1"                      ,        0,      32,     574,    "RO",   0,      0,      0ull,   0ull},
49802         {"DWORD2"                      ,        0,      32,     575,    "RO",   0,      0,      0ull,   0ull},
49803         {"DWORD3"                      ,        0,      32,     576,    "RO",   0,      0,      0ull,   0ull},
49804         {"DWORD4"                      ,        0,      32,     577,    "RO",   0,      0,      0ull,   0ull},
49805         {"RTLTL"                       ,        0,      16,     578,    "R/W",  0,      0,      4143ull,        4143ull},
49806         {"RTL"                         ,        16,     16,     578,    "R/W",  0,      0,      12429ull,       12429ull},
49807         {"OMR"                         ,        0,      32,     579,    "R/W",  0,      1,      4294967295ull,  0},
49808         {"LINK_NUM"                    ,        0,      8,      580,    "RO",   0,      0,      0ull,   0ull},
49809         {"RESERVED_8_14"               ,        8,      7,      580,    "RAZ",  1,      1,      0,      0},
49810         {"FORCE_LINK"                  ,        15,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
49811         {"LINK_STATE"                  ,        16,     6,      580,    "R/W",  0,      0,      0ull,   0ull},
49812         {"RESERVED_22_23"              ,        22,     2,      580,    "RAZ",  1,      1,      0,      0},
49813         {"LPEC"                        ,        24,     8,      580,    "R/W",  0,      0,      7ull,   7ull},
49814         {"ACK_FREQ"                    ,        0,      8,      581,    "R/W",  0,      0,      0ull,   0ull},
49815         {"N_FTS"                       ,        8,      8,      581,    "R/W",  0,      0,      128ull, 128ull},
49816         {"N_FTS_CC"                    ,        16,     8,      581,    "R/W",  0,      0,      128ull, 128ull},
49817         {"L0EL"                        ,        24,     3,      581,    "R/W",  0,      0,      3ull,   3ull},
49818         {"L1EL"                        ,        27,     3,      581,    "R/W",  0,      0,      3ull,   3ull},
49819         {"RESERVED_30_31"              ,        30,     2,      581,    "RAZ",  1,      1,      0,      0},
49820         {"OMR"                         ,        0,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
49821         {"SD"                          ,        1,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
49822         {"LE"                          ,        2,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
49823         {"RA"                          ,        3,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
49824         {"RESERVED_4_4"                ,        4,      1,      582,    "RAZ",  1,      1,      0,      0},
49825         {"DLLLE"                       ,        5,      1,      582,    "R/W",  0,      0,      1ull,   1ull},
49826         {"RESERVED_6_6"                ,        6,      1,      582,    "RAZ",  1,      1,      0,      0},
49827         {"FLM"                         ,        7,      1,      582,    "R/W",  0,      0,      0ull,   0ull},
49828         {"RESERVED_8_15"               ,        8,      8,      582,    "RO",   0,      0,      1ull,   1ull},
49829         {"LME"                         ,        16,     6,      582,    "R/W",  0,      0,      15ull,  15ull},
49830         {"RESERVED_22_24"              ,        22,     3,      582,    "RAZ",  1,      1,      0,      0},
49831         {"ECCRC"                       ,        25,     1,      582,    "R/W",  0,      0,      0ull,   0ull},
49832         {"RESERVED_26_31"              ,        26,     6,      582,    "RAZ",  1,      1,      0,      0},
49833         {"ILST"                        ,        0,      24,     583,    "R/W",  0,      0,      0ull,   0ull},
49834         {"FCD"                         ,        24,     1,      583,    "R/W",  0,      0,      0ull,   0ull},
49835         {"ACK_NAK"                     ,        25,     1,      583,    "R/W",  0,      0,      0ull,   0ull},
49836         {"RESERVED_26_30"              ,        26,     5,      583,    "RAZ",  1,      1,      0,      0},
49837         {"DLLD"                        ,        31,     1,      583,    "R/W",  0,      0,      0ull,   0ull},
49838         {"NTSS"                        ,        0,      4,      584,    "R/W",  0,      0,      10ull,  10ull},
49839         {"RESERVED_4_7"                ,        4,      4,      584,    "RO",   1,      1,      0,      0},
49840         {"NSKPS"                       ,        8,      3,      584,    "R/W",  0,      0,      3ull,   3ull},
49841         {"RESERVED_11_13"              ,        11,     3,      584,    "RAZ",  1,      1,      0,      0},
49842         {"TMRT"                        ,        14,     5,      584,    "R/W",  0,      0,      8ull,   8ull},
49843         {"TMANLT"                      ,        19,     5,      584,    "R/W",  0,      0,      0ull,   0ull},
49844         {"TMFCWT"                      ,        24,     5,      584,    "R/W",  0,      0,      0ull,   0ull},
49845         {"RESERVED_29_31"              ,        29,     3,      584,    "RO",   1,      1,      0,      0},
49846         {"SKPIV"                       ,        0,      11,     585,    "R/W",  0,      0,      1280ull,        1280ull},
49847         {"RESERVED_11_14"              ,        11,     4,      585,    "RAZ",  1,      1,      0,      0},
49848         {"DFCWT"                       ,        15,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49849         {"M_FUN"                       ,        16,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49850         {"M_POIS_FILT"                 ,        17,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49851         {"M_BAR_MATCH"                 ,        18,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49852         {"M_CFG1_FILT"                 ,        19,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49853         {"M_LK_FILT"                   ,        20,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49854         {"M_CPL_TAG_ERR"               ,        21,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49855         {"M_CPL_RID_ERR"               ,        22,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49856         {"M_CPL_FUN_ERR"               ,        23,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49857         {"M_CPL_TC_ERR"                ,        24,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49858         {"M_CPL_ATTR_ERR"              ,        25,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49859         {"M_CPL_LEN_ERR"               ,        26,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49860         {"M_ECRC_FILT"                 ,        27,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49861         {"M_CPL_ECRC_FILT"             ,        28,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49862         {"MSG_CTRL"                    ,        29,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49863         {"M_IO_FILT"                   ,        30,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49864         {"M_CFG0_FILT"                 ,        31,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
49865         {"M_VEND0_DRP"                 ,        0,      1,      586,    "R/W",  0,      0,      0ull,   0ull},
49866         {"M_VEND1_DRP"                 ,        1,      1,      586,    "R/W",  0,      0,      0ull,   0ull},
49867         {"RESERVED_2_31"               ,        2,      30,     586,    "RAZ",  1,      1,      0,      0},
49868         {"DBG_INFO_L32"                ,        0,      32,     587,    "RO",   0,      0,      0ull,   0ull},
49869         {"DBG_INFO_U32"                ,        0,      32,     588,    "RO",   0,      0,      0ull,   0ull},
49870         {"TPDFCC"                      ,        0,      12,     589,    "RO",   0,      0,      0ull,   0ull},
49871         {"TPHFCC"                      ,        12,     8,      589,    "RO",   0,      0,      0ull,   0ull},
49872         {"RESERVED_20_31"              ,        20,     12,     589,    "RAZ",  1,      1,      0,      0},
49873         {"TCDFCC"                      ,        0,      12,     590,    "RO",   0,      0,      0ull,   0ull},
49874         {"TCHFCC"                      ,        12,     8,      590,    "RO",   0,      0,      0ull,   0ull},
49875         {"RESERVED_20_31"              ,        20,     12,     590,    "RAZ",  1,      1,      0,      0},
49876         {"TCDFCC"                      ,        0,      12,     591,    "RO",   0,      0,      0ull,   0ull},
49877         {"TCHFCC"                      ,        12,     8,      591,    "RO",   0,      0,      0ull,   0ull},
49878         {"RESERVED_20_31"              ,        20,     12,     591,    "RAZ",  1,      1,      0,      0},
49879         {"RTLPFCCNR"                   ,        0,      1,      592,    "RO",   0,      0,      0ull,   0ull},
49880         {"TRBNE"                       ,        1,      1,      592,    "RO",   0,      0,      0ull,   0ull},
49881         {"RQNE"                        ,        2,      1,      592,    "RO",   0,      0,      0ull,   0ull},
49882         {"RESERVED_3_31"               ,        3,      29,     592,    "RAZ",  1,      1,      0,      0},
49883         {"WRR_VC0"                     ,        0,      8,      593,    "RO",   0,      0,      15ull,  15ull},
49884         {"WRR_VC1"                     ,        8,      8,      593,    "RO",   0,      0,      0ull,   0ull},
49885         {"WRR_VC2"                     ,        16,     8,      593,    "RO",   0,      0,      0ull,   0ull},
49886         {"WRR_VC3"                     ,        24,     8,      593,    "RO",   0,      0,      0ull,   0ull},
49887         {"WRR_VC4"                     ,        0,      8,      594,    "RO",   0,      0,      0ull,   0ull},
49888         {"WRR_VC5"                     ,        8,      8,      594,    "RO",   0,      0,      0ull,   0ull},
49889         {"WRR_VC6"                     ,        16,     8,      594,    "RO",   0,      0,      0ull,   0ull},
49890         {"WRR_VC7"                     ,        24,     8,      594,    "RO",   0,      0,      0ull,   0ull},
49891         {"DATA_CREDITS"                ,        0,      12,     595,    "RO/WRSL",      0,      0,      128ull, 128ull},
49892         {"HEADER_CREDITS"              ,        12,     8,      595,    "RO/WRSL",      0,      0,      35ull,  35ull},
49893         {"RESERVED_20_20"              ,        20,     1,      595,    "RAZ",  1,      1,      0,      0},
49894         {"QUEUE_MODE"                  ,        21,     3,      595,    "RO/WRSL",      0,      0,      2ull,   2ull},
49895         {"RESERVED_24_29"              ,        24,     6,      595,    "RAZ",  1,      1,      0,      0},
49896         {"TYPE_ORDERING"               ,        30,     1,      595,    "RO/WRSL",      0,      0,      1ull,   1ull},
49897         {"RX_QUEUE_ORDER"              ,        31,     1,      595,    "RO/WRSL",      0,      0,      0ull,   0ull},
49898         {"DATA_CREDITS"                ,        0,      12,     596,    "RO/WRSL",      0,      0,      4ull,   4ull},
49899         {"HEADER_CREDITS"              ,        12,     8,      596,    "RO/WRSL",      0,      0,      8ull,   8ull},
49900         {"RESERVED_20_20"              ,        20,     1,      596,    "RAZ",  1,      1,      0,      0},
49901         {"QUEUE_MODE"                  ,        21,     3,      596,    "RO/WRSL",      0,      0,      2ull,   2ull},
49902         {"RESERVED_24_31"              ,        24,     8,      596,    "RAZ",  1,      1,      0,      0},
49903         {"DATA_CREDITS"                ,        0,      12,     597,    "RO/WRSL",      0,      0,      0ull,   0ull},
49904         {"HEADER_CREDITS"              ,        12,     8,      597,    "RO/WRSL",      0,      0,      0ull,   0ull},
49905         {"RESERVED_20_20"              ,        20,     1,      597,    "RAZ",  1,      1,      0,      0},
49906         {"QUEUE_MODE"                  ,        21,     3,      597,    "RO/WRSL",      0,      0,      2ull,   2ull},
49907         {"RESERVED_24_31"              ,        24,     8,      597,    "RAZ",  1,      1,      0,      0},
49908         {"DATA_DEPTH"                  ,        0,      14,     598,    "RO/WRSL",      0,      0,      331ull, 331ull},
49909         {"RESERVED_14_15"              ,        14,     2,      598,    "RAZ",  1,      1,      0,      0},
49910         {"HEADER_DEPTH"                ,        16,     10,     598,    "RO/WRSL",      0,      0,      41ull,  41ull},
49911         {"RESERVED_26_31"              ,        26,     6,      598,    "RAZ",  1,      1,      0,      0},
49912         {"DATA_DEPTH"                  ,        0,      14,     599,    "RO/WRSL",      0,      0,      56ull,  56ull},
49913         {"RESERVED_14_15"              ,        14,     2,      599,    "RAZ",  1,      1,      0,      0},
49914         {"HEADER_DEPTH"                ,        16,     10,     599,    "RO/WRSL",      0,      0,      14ull,  14ull},
49915         {"RESERVED_26_31"              ,        26,     6,      599,    "RAZ",  1,      1,      0,      0},
49916         {"DATA_DEPTH"                  ,        0,      14,     600,    "RO/WRSL",      0,      0,      360ull, 360ull},
49917         {"RESERVED_14_15"              ,        14,     2,      600,    "RAZ",  1,      1,      0,      0},
49918         {"HEADER_DEPTH"                ,        16,     10,     600,    "RO/WRSL",      0,      0,      70ull,  70ull},
49919         {"RESERVED_26_31"              ,        26,     6,      600,    "RAZ",  1,      1,      0,      0},
49920         {"PHY_STAT"                    ,        0,      32,     601,    "RO",   0,      0,      0ull,   0ull},
49921         {"PHY_CTRL"                    ,        0,      32,     602,    "R/W",  0,      0,      0ull,   0ull},
49922         {"VENDID"                      ,        0,      16,     603,    "R/W",  0,      0,      6013ull,        6013ull},
49923         {"DEVID"                       ,        16,     16,     603,    "R/W",  0,      0,      80ull,  80ull},
49924         {"ISAE"                        ,        0,      1,      604,    "R/W",  0,      0,      0ull,   0ull},
49925         {"MSAE"                        ,        1,      1,      604,    "R/W",  0,      0,      0ull,   0ull},
49926         {"ME"                          ,        2,      1,      604,    "R/W",  0,      0,      0ull,   0ull},
49927         {"SCSE"                        ,        3,      1,      604,    "RO",   0,      0,      0ull,   0ull},
49928         {"MWICE"                       ,        4,      1,      604,    "RO",   0,      0,      0ull,   0ull},
49929         {"VPS"                         ,        5,      1,      604,    "RO",   0,      0,      0ull,   0ull},
49930         {"PER"                         ,        6,      1,      604,    "R/W",  0,      0,      0ull,   0ull},
49931         {"IDS_WCC"                     ,        7,      1,      604,    "RO",   0,      0,      0ull,   0ull},
49932         {"SEE"                         ,        8,      1,      604,    "R/W",  0,      0,      0ull,   0ull},
49933         {"FBBE"                        ,        9,      1,      604,    "RO",   0,      0,      0ull,   0ull},
49934         {"I_DIS"                       ,        10,     1,      604,    "R/W",  0,      0,      0ull,   0ull},
49935         {"RESERVED_11_18"              ,        11,     8,      604,    "RAZ",  1,      1,      0,      0},
49936         {"I_STAT"                      ,        19,     1,      604,    "RO",   0,      0,      0ull,   0ull},
49937         {"CL"                          ,        20,     1,      604,    "RO",   0,      0,      1ull,   1ull},
49938         {"M66"                         ,        21,     1,      604,    "RO",   0,      0,      0ull,   0ull},
49939         {"RESERVED_22_22"              ,        22,     1,      604,    "RO",   1,      1,      0,      0},
49940         {"FBB"                         ,        23,     1,      604,    "RO",   0,      0,      0ull,   0ull},
49941         {"MDPE"                        ,        24,     1,      604,    "R/W1C",        0,      0,      0ull,   0ull},
49942         {"DEVT"                        ,        25,     2,      604,    "RO",   0,      0,      0ull,   0ull},
49943         {"STA"                         ,        27,     1,      604,    "R/W1C",        0,      0,      0ull,   0ull},
49944         {"RTA"                         ,        28,     1,      604,    "R/W1C",        0,      0,      0ull,   0ull},
49945         {"RMA"                         ,        29,     1,      604,    "R/W1C",        0,      0,      0ull,   0ull},
49946         {"SSE"                         ,        30,     1,      604,    "R/W1C",        0,      0,      0ull,   0ull},
49947         {"DPE"                         ,        31,     1,      604,    "R/W1C",        0,      0,      0ull,   0ull},
49948         {"RID"                         ,        0,      8,      605,    "R/W",  0,      0,      8ull,   8ull},
49949         {"PI"                          ,        8,      8,      605,    "R/W",  0,      0,      0ull,   0ull},
49950         {"SC"                          ,        16,     8,      605,    "R/W",  0,      0,      48ull,  48ull},
49951         {"BCC"                         ,        24,     8,      605,    "R/W",  0,      0,      11ull,  11ull},
49952         {"CLS"                         ,        0,      8,      606,    "R/W",  0,      0,      0ull,   0ull},
49953         {"LT"                          ,        8,      8,      606,    "RO",   0,      0,      0ull,   0ull},
49954         {"CHF"                         ,        16,     7,      606,    "RO",   0,      0,      1ull,   1ull},
49955         {"MFD"                         ,        23,     1,      606,    "R/W",  0,      0,      0ull,   0ull},
49956         {"BIST"                        ,        24,     8,      606,    "RO",   0,      0,      0ull,   0ull},
49957         {"RESERVED_0_31"               ,        0,      32,     607,    "RO",   1,      1,      0,      0},
49958         {"RESERVED_0_31"               ,        0,      32,     608,    "RO",   1,      1,      0,      0},
49959         {"PBNUM"                       ,        0,      8,      609,    "R/W",  0,      0,      0ull,   0ull},
49960         {"SBNUM"                       ,        8,      8,      609,    "R/W",  0,      0,      0ull,   0ull},
49961         {"SUBBNUM"                     ,        16,     8,      609,    "R/W",  0,      0,      0ull,   0ull},
49962         {"SLT"                         ,        24,     8,      609,    "RO",   0,      0,      0ull,   0ull},
49963         {"IO32A"                       ,        0,      1,      610,    "R/W",  0,      0,      1ull,   1ull},
49964         {"RESERVED_1_3"                ,        1,      3,      610,    "RAZ",  0,      0,      0ull,   0ull},
49965         {"LIO_BASE"                    ,        4,      4,      610,    "R/W",  0,      0,      0ull,   0ull},
49966         {"IO32B"                       ,        8,      1,      610,    "RO",   0,      0,      1ull,   1ull},
49967         {"RESERVED_9_11"               ,        9,      3,      610,    "RAZ",  0,      0,      0ull,   0ull},
49968         {"LIO_LIMI"                    ,        12,     4,      610,    "R/W",  0,      0,      0ull,   0ull},
49969         {"RESERVED_16_20"              ,        16,     5,      610,    "RAZ",  1,      1,      0,      0},
49970         {"M66"                         ,        21,     1,      610,    "RO",   0,      0,      0ull,   0ull},
49971         {"RESERVED_22_22"              ,        22,     1,      610,    "RO",   1,      1,      0,      0},
49972         {"FBB"                         ,        23,     1,      610,    "RO",   0,      0,      0ull,   0ull},
49973         {"MDPE"                        ,        24,     1,      610,    "R/W1C",        0,      0,      0ull,   0ull},
49974         {"DEVT"                        ,        25,     2,      610,    "RO",   0,      0,      0ull,   0ull},
49975         {"STA"                         ,        27,     1,      610,    "R/W1C",        0,      0,      0ull,   0ull},
49976         {"RTA"                         ,        28,     1,      610,    "R/W1C",        0,      0,      0ull,   0ull},
49977         {"RMA"                         ,        29,     1,      610,    "R/W1C",        0,      0,      0ull,   0ull},
49978         {"SSE"                         ,        30,     1,      610,    "R/W1C",        0,      0,      0ull,   0ull},
49979         {"DPE"                         ,        31,     1,      610,    "R/W1C",        0,      0,      0ull,   0ull},
49980         {"RESERVED_0_3"                ,        0,      4,      611,    "RO",   1,      1,      0,      0},
49981         {"MB_ADDR"                     ,        4,      12,     611,    "R/W",  0,      0,      0ull,   0ull},
49982         {"RESERVED_16_19"              ,        16,     4,      611,    "RO",   1,      1,      0,      0},
49983         {"ML_ADDR"                     ,        20,     12,     611,    "R/W",  0,      0,      0ull,   0ull},
49984         {"MEM64A"                      ,        0,      1,      612,    "R/W",  0,      0,      1ull,   1ull},
49985         {"RESERVED_1_3"                ,        1,      3,      612,    "RO",   1,      1,      0,      0},
49986         {"LMEM_BASE"                   ,        4,      12,     612,    "R/W",  0,      0,      0ull,   0ull},
49987         {"MEM64B"                      ,        16,     1,      612,    "RO",   0,      0,      1ull,   1ull},
49988         {"RESERVED_17_19"              ,        17,     3,      612,    "RO",   1,      1,      0,      0},
49989         {"LMEM_LIMIT"                  ,        20,     12,     612,    "R/W",  0,      0,      0ull,   0ull},
49990         {"UMEM_BASE"                   ,        0,      32,     613,    "R/W",  0,      0,      0ull,   0ull},
49991         {"UMEM_LIMIT"                  ,        0,      32,     614,    "R/W",  0,      0,      0ull,   0ull},
49992         {"UIO_BASE"                    ,        0,      16,     615,    "R/W",  0,      0,      0ull,   0ull},
49993         {"UIO_LIMIT"                   ,        16,     16,     615,    "R/W",  0,      0,      0ull,   0ull},
49994         {"CP"                          ,        0,      8,      616,    "R/W",  0,      0,      64ull,  64ull},
49995         {"RESERVED_8_31"               ,        8,      24,     616,    "RAZ",  1,      1,      0,      0},
49996         {"RESERVED_0_31"               ,        0,      32,     617,    "RAZ",  1,      1,      0,      0},
49997         {"IL"                          ,        0,      8,      618,    "R/W",  0,      0,      255ull, 255ull},
49998         {"INTA"                        ,        8,      8,      618,    "R/W",  0,      0,      1ull,   1ull},
49999         {"PERE"                        ,        16,     1,      618,    "R/W",  0,      0,      0ull,   0ull},
50000         {"SEE"                         ,        17,     1,      618,    "R/W",  0,      0,      0ull,   0ull},
50001         {"ISAE"                        ,        18,     1,      618,    "R/W",  0,      0,      0ull,   0ull},
50002         {"VGAE"                        ,        19,     1,      618,    "R/W",  0,      0,      0ull,   0ull},
50003         {"VGA16D"                      ,        20,     1,      618,    "R/W",  0,      0,      0ull,   0ull},
50004         {"MAM"                         ,        21,     1,      618,    "RO",   0,      0,      0ull,   0ull},
50005         {"SBRST"                       ,        22,     1,      618,    "R/W",  0,      0,      0ull,   0ull},
50006         {"FBBE"                        ,        23,     1,      618,    "RO",   0,      0,      0ull,   0ull},
50007         {"PDT"                         ,        24,     1,      618,    "RO",   0,      0,      0ull,   0ull},
50008         {"SDT"                         ,        25,     1,      618,    "RO",   0,      0,      0ull,   0ull},
50009         {"DTS"                         ,        26,     1,      618,    "RO",   0,      0,      0ull,   0ull},
50010         {"DTSEES"                      ,        27,     1,      618,    "RO",   0,      0,      0ull,   0ull},
50011         {"RESERVED_28_31"              ,        28,     4,      618,    "RO",   1,      1,      0,      0},
50012         {"PMCID"                       ,        0,      8,      619,    "RO",   0,      0,      1ull,   1ull},
50013         {"NCP"                         ,        8,      8,      619,    "R/W",  0,      0,      80ull,  80ull},
50014         {"PMSV"                        ,        16,     3,      619,    "R/W",  0,      0,      3ull,   3ull},
50015         {"PME_CLOCK"                   ,        19,     1,      619,    "RO",   0,      0,      0ull,   0ull},
50016         {"RESERVED_20_20"              ,        20,     1,      619,    "RAZ",  1,      1,      0,      0},
50017         {"DSI"                         ,        21,     1,      619,    "R/W",  0,      0,      0ull,   0ull},
50018         {"AUXC"                        ,        22,     3,      619,    "R/W",  0,      0,      0ull,   0ull},
50019         {"D1S"                         ,        25,     1,      619,    "R/W",  0,      0,      0ull,   0ull},
50020         {"D2S"                         ,        26,     1,      619,    "R/W",  0,      0,      0ull,   0ull},
50021         {"PMES"                        ,        27,     5,      619,    "R/W",  0,      0,      0ull,   0ull},
50022         {"PS"                          ,        0,      2,      620,    "R/W",  0,      0,      0ull,   0ull},
50023         {"RESERVED_2_2"                ,        2,      1,      620,    "RAZ",  1,      1,      0,      0},
50024         {"NSR"                         ,        3,      1,      620,    "R/W",  0,      0,      0ull,   0ull},
50025         {"RESERVED_4_7"                ,        4,      4,      620,    "RAZ",  1,      1,      0,      0},
50026         {"PMEENS"                      ,        8,      1,      620,    "R/W",  0,      0,      0ull,   0ull},
50027         {"PMDS"                        ,        9,      4,      620,    "RO",   0,      0,      0ull,   0ull},
50028         {"PMEDSIA"                     ,        13,     2,      620,    "RO",   0,      0,      0ull,   0ull},
50029         {"PMESS"                       ,        15,     1,      620,    "R/W1C",        0,      0,      0ull,   0ull},
50030         {"RESERVED_16_21"              ,        16,     6,      620,    "RAZ",  1,      1,      0,      0},
50031         {"BD3H"                        ,        22,     1,      620,    "RO",   0,      0,      0ull,   0ull},
50032         {"BPCCEE"                      ,        23,     1,      620,    "RO",   0,      0,      0ull,   0ull},
50033         {"PMDIA"                       ,        24,     8,      620,    "RO",   0,      0,      0ull,   0ull},
50034         {"MSICID"                      ,        0,      8,      621,    "RO",   0,      0,      5ull,   5ull},
50035         {"NCP"                         ,        8,      8,      621,    "R/W",  0,      0,      112ull, 112ull},
50036         {"MSIEN"                       ,        16,     1,      621,    "R/W",  0,      0,      0ull,   0ull},
50037         {"MMC"                         ,        17,     3,      621,    "R/W",  0,      0,      0ull,   0ull},
50038         {"MME"                         ,        20,     3,      621,    "R/W",  0,      0,      0ull,   0ull},
50039         {"M64"                         ,        23,     1,      621,    "R/W",  0,      0,      1ull,   1ull},
50040         {"RESERVED_24_31"              ,        24,     8,      621,    "RAZ",  1,      1,      0,      0},
50041         {"RESERVED_0_1"                ,        0,      2,      622,    "RAZ",  1,      1,      0,      0},
50042         {"LMSI"                        ,        2,      30,     622,    "R/W",  0,      0,      0ull,   0ull},
50043         {"UMSI"                        ,        0,      32,     623,    "R/W",  0,      0,      0ull,   0ull},
50044         {"MSIMD"                       ,        0,      16,     624,    "R/W",  0,      0,      0ull,   0ull},
50045         {"RESERVED_16_31"              ,        16,     16,     624,    "RAZ",  1,      1,      0,      0},
50046         {"PCIEID"                      ,        0,      8,      625,    "RO",   0,      0,      16ull,  16ull},
50047         {"NCP"                         ,        8,      8,      625,    "R/W",  0,      0,      0ull,   0ull},
50048         {"PCIECV"                      ,        16,     4,      625,    "RO",   0,      0,      2ull,   2ull},
50049         {"DPT"                         ,        20,     4,      625,    "RO",   0,      0,      4ull,   4ull},
50050         {"SI"                          ,        24,     1,      625,    "R/W",  0,      0,      0ull,   0ull},
50051         {"IMN"                         ,        25,     5,      625,    "R/W",  0,      0,      0ull,   0ull},
50052         {"RESERVED_30_31"              ,        30,     2,      625,    "RAZ",  1,      1,      0,      0},
50053         {"MPSS"                        ,        0,      3,      626,    "R/W",  0,      0,      1ull,   1ull},
50054         {"PFS"                         ,        3,      2,      626,    "R/W",  0,      0,      0ull,   0ull},
50055         {"ETFS"                        ,        5,      1,      626,    "R/W",  0,      0,      0ull,   0ull},
50056         {"EL0AL"                       ,        6,      3,      626,    "R/W",  0,      0,      0ull,   0ull},
50057         {"EL1AL"                       ,        9,      3,      626,    "R/W",  0,      0,      0ull,   0ull},
50058         {"RESERVED_12_14"              ,        12,     3,      626,    "RAZ",  1,      1,      0,      0},
50059         {"RBER"                        ,        15,     1,      626,    "R/W",  0,      0,      1ull,   1ull},
50060         {"RESERVED_16_17"              ,        16,     2,      626,    "RAZ",  1,      1,      0,      0},
50061         {"CSPLV"                       ,        18,     8,      626,    "RO",   0,      0,      0ull,   0ull},
50062         {"CSPLS"                       ,        26,     2,      626,    "RO",   0,      0,      0ull,   0ull},
50063         {"RESERVED_28_31"              ,        28,     4,      626,    "RAZ",  1,      1,      0,      0},
50064         {"CE_EN"                       ,        0,      1,      627,    "R/W",  0,      0,      0ull,   0ull},
50065         {"NFE_EN"                      ,        1,      1,      627,    "R/W",  0,      0,      0ull,   0ull},
50066         {"FE_EN"                       ,        2,      1,      627,    "R/W",  0,      0,      0ull,   0ull},
50067         {"UR_EN"                       ,        3,      1,      627,    "R/W",  0,      0,      0ull,   0ull},
50068         {"RO_EN"                       ,        4,      1,      627,    "R/W",  0,      0,      1ull,   1ull},
50069         {"MPS"                         ,        5,      3,      627,    "R/W",  0,      0,      0ull,   0ull},
50070         {"ETF_EN"                      ,        8,      1,      627,    "R/W",  0,      0,      0ull,   0ull},
50071         {"PF_EN"                       ,        9,      1,      627,    "R/W",  0,      0,      0ull,   0ull},
50072         {"AP_EN"                       ,        10,     1,      627,    "R/W",  0,      0,      0ull,   0ull},
50073         {"NS_EN"                       ,        11,     1,      627,    "R/W",  0,      0,      1ull,   1ull},
50074         {"MRRS"                        ,        12,     3,      627,    "R/W",  0,      0,      2ull,   2ull},
50075         {"RESERVED_15_15"              ,        15,     1,      627,    "RAZ",  1,      1,      0,      0},
50076         {"CE_D"                        ,        16,     1,      627,    "R/W1C",        0,      0,      0ull,   0ull},
50077         {"NFE_D"                       ,        17,     1,      627,    "R/W1C",        0,      0,      0ull,   0ull},
50078         {"FE_D"                        ,        18,     1,      627,    "R/W1C",        0,      0,      0ull,   0ull},
50079         {"UR_D"                        ,        19,     1,      627,    "R/W1C",        0,      0,      0ull,   0ull},
50080         {"AP_D"                        ,        20,     1,      627,    "RO",   0,      0,      0ull,   0ull},
50081         {"TP"                          ,        21,     1,      627,    "RO",   0,      0,      0ull,   0ull},
50082         {"RESERVED_22_31"              ,        22,     10,     627,    "RAZ",  1,      1,      0,      0},
50083         {"MLS"                         ,        0,      4,      628,    "R/W",  0,      0,      1ull,   1ull},
50084         {"MLW"                         ,        4,      6,      628,    "R/W",  0,      0,      8ull,   8ull},
50085         {"ASLPMS"                      ,        10,     2,      628,    "R/W",  0,      0,      3ull,   3ull},
50086         {"L0EL"                        ,        12,     3,      628,    "R/W",  0,      0,      6ull,   6ull},
50087         {"L1EL"                        ,        15,     3,      628,    "R/W",  0,      0,      6ull,   6ull},
50088         {"CPM"                         ,        18,     1,      628,    "R/W",  0,      0,      0ull,   0ull},
50089         {"SDERC"                       ,        19,     1,      628,    "RO",   0,      0,      0ull,   0ull},
50090         {"DLLARC"                      ,        20,     1,      628,    "RO",   0,      0,      1ull,   1ull},
50091         {"LBNC"                        ,        21,     1,      628,    "RO",   0,      0,      1ull,   1ull},
50092         {"RESERVED_22_23"              ,        22,     2,      628,    "RAZ",  1,      1,      0,      0},
50093         {"PNUM"                        ,        24,     8,      628,    "R/W",  0,      0,      0ull,   0ull},
50094         {"ASLPC"                       ,        0,      2,      629,    "R/W",  0,      0,      0ull,   0ull},
50095         {"RESERVED_2_2"                ,        2,      1,      629,    "RAZ",  1,      1,      0,      0},
50096         {"RCB"                         ,        3,      1,      629,    "R/W",  0,      0,      1ull,   1ull},
50097         {"LD"                          ,        4,      1,      629,    "R/W",  0,      0,      0ull,   0ull},
50098         {"RL"                          ,        5,      1,      629,    "R/W",  0,      0,      0ull,   0ull},
50099         {"CCC"                         ,        6,      1,      629,    "R/W",  0,      0,      0ull,   0ull},
50100         {"ES"                          ,        7,      1,      629,    "R/W",  0,      0,      0ull,   0ull},
50101         {"ECPM"                        ,        8,      1,      629,    "R/W",  0,      0,      0ull,   0ull},
50102         {"HAWD"                        ,        9,      1,      629,    "R/W",  0,      0,      0ull,   0ull},
50103         {"LBM_INT_ENB"                 ,        10,     1,      629,    "R/W",  0,      0,      0ull,   0ull},
50104         {"LAB_INT_ENB"                 ,        11,     1,      629,    "R/W",  0,      0,      0ull,   0ull},
50105         {"RESERVED_12_15"              ,        12,     4,      629,    "RAZ",  1,      1,      0,      0},
50106         {"LS"                          ,        16,     4,      629,    "RO",   0,      0,      1ull,   1ull},
50107         {"NLW"                         ,        20,     6,      629,    "RO",   0,      0,      0ull,   0ull},
50108         {"RESERVED_26_26"              ,        26,     1,      629,    "RAZ",  1,      1,      0,      0},
50109         {"LT"                          ,        27,     1,      629,    "RO",   0,      0,      0ull,   0ull},
50110         {"SCC"                         ,        28,     1,      629,    "R/W",  0,      0,      1ull,   0ull},
50111         {"DLLA"                        ,        29,     1,      629,    "RO",   0,      0,      0ull,   1ull},
50112         {"LBM"                         ,        30,     1,      629,    "R/W1C",        0,      0,      0ull,   0ull},
50113         {"LAB"                         ,        31,     1,      629,    "R/W1C",        0,      0,      0ull,   0ull},
50114         {"ABP"                         ,        0,      1,      630,    "R/W",  0,      0,      0ull,   0ull},
50115         {"PCP"                         ,        1,      1,      630,    "R/W",  0,      0,      0ull,   0ull},
50116         {"MRLSP"                       ,        2,      1,      630,    "R/W",  0,      0,      0ull,   0ull},
50117         {"AIP"                         ,        3,      1,      630,    "R/W",  0,      0,      0ull,   0ull},
50118         {"PIP"                         ,        4,      1,      630,    "R/W",  0,      0,      0ull,   0ull},
50119         {"HP_S"                        ,        5,      1,      630,    "R/W",  0,      0,      0ull,   0ull},
50120         {"HP_C"                        ,        6,      1,      630,    "R/W",  0,      0,      0ull,   0ull},
50121         {"SP_LV"                       ,        7,      8,      630,    "R/W",  0,      0,      0ull,   0ull},
50122         {"SP_LS"                       ,        15,     2,      630,    "R/W",  0,      0,      0ull,   0ull},
50123         {"EMIP"                        ,        17,     1,      630,    "R/W",  0,      0,      0ull,   0ull},
50124         {"NCCS"                        ,        18,     1,      630,    "R/W",  0,      0,      0ull,   0ull},
50125         {"PS_NUM"                      ,        19,     13,     630,    "R/W",  0,      0,      0ull,   0ull},
50126         {"ABP_EN"                      ,        0,      1,      631,    "R/W",  0,      0,      0ull,   0ull},
50127         {"PF_EN"                       ,        1,      1,      631,    "R/W",  0,      0,      0ull,   0ull},
50128         {"MRLS_EN"                     ,        2,      1,      631,    "R/W",  0,      0,      0ull,   0ull},
50129         {"PD_EN"                       ,        3,      1,      631,    "R/W",  0,      0,      0ull,   0ull},
50130         {"CCINT_EN"                    ,        4,      1,      631,    "R/W",  0,      0,      0ull,   0ull},
50131         {"HPINT_EN"                    ,        5,      1,      631,    "R/W",  0,      0,      0ull,   0ull},
50132         {"AIC"                         ,        6,      2,      631,    "R/W",  0,      0,      3ull,   3ull},
50133         {"PIC"                         ,        8,      2,      631,    "R/W",  0,      0,      3ull,   3ull},
50134         {"PCC"                         ,        10,     1,      631,    "R/W",  0,      0,      0ull,   0ull},
50135         {"EMIC"                        ,        11,     1,      631,    "R/W",  0,      0,      0ull,   0ull},
50136         {"DLLS_EN"                     ,        12,     1,      631,    "R/W",  0,      0,      0ull,   0ull},
50137         {"RESERVED_13_15"              ,        13,     3,      631,    "RAZ",  1,      1,      0,      0},
50138         {"ABP_D"                       ,        16,     1,      631,    "R/W1C",        0,      0,      0ull,   0ull},
50139         {"PF_D"                        ,        17,     1,      631,    "R/W1C",        0,      0,      0ull,   0ull},
50140         {"MRLS_C"                      ,        18,     1,      631,    "R/W1C",        0,      0,      0ull,   0ull},
50141         {"PD_C"                        ,        19,     1,      631,    "R/W1C",        0,      0,      0ull,   0ull},
50142         {"CCINT_D"                     ,        20,     1,      631,    "R/W1C",        0,      0,      0ull,   0ull},
50143         {"MRLSS"                       ,        21,     1,      631,    "RO",   0,      0,      0ull,   0ull},
50144         {"PDS"                         ,        22,     1,      631,    "RO",   0,      0,      1ull,   1ull},
50145         {"EMIS"                        ,        23,     1,      631,    "RO",   0,      0,      0ull,   0ull},
50146         {"DLLS_C"                      ,        24,     1,      631,    "R/W1C",        0,      0,      0ull,   0ull},
50147         {"RESERVED_25_31"              ,        25,     7,      631,    "RAZ",  1,      1,      0,      0},
50148         {"SECEE"                       ,        0,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
50149         {"SENFEE"                      ,        1,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
50150         {"SEFEE"                       ,        2,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
50151         {"PMEIE"                       ,        3,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
50152         {"CRSSVE"                      ,        4,      1,      632,    "RO",   0,      0,      0ull,   0ull},
50153         {"RESERVED_5_15"               ,        5,      11,     632,    "RAZ",  1,      1,      0,      0},
50154         {"CRSSV"                       ,        16,     1,      632,    "RO",   0,      0,      0ull,   0ull},
50155         {"RESERVED_17_31"              ,        17,     15,     632,    "RAZ",  1,      1,      0,      0},
50156         {"PME_RID"                     ,        0,      16,     633,    "RO",   0,      0,      0ull,   0ull},
50157         {"PME_STAT"                    ,        16,     1,      633,    "R/W1C",        0,      0,      0ull,   0ull},
50158         {"PME_PEND"                    ,        17,     1,      633,    "RO",   0,      0,      0ull,   0ull},
50159         {"RESERVED_18_31"              ,        18,     14,     633,    "RAZ",  0,      0,      0ull,   0ull},
50160         {"CTRS"                        ,        0,      4,      634,    "RO",   0,      0,      0ull,   0ull},
50161         {"CTDS"                        ,        4,      1,      634,    "RO",   0,      0,      1ull,   1ull},
50162         {"RESERVED_5_31"               ,        5,      27,     634,    "RAZ",  1,      1,      0,      0},
50163         {"CTV"                         ,        0,      4,      635,    "RO",   0,      0,      0ull,   0ull},
50164         {"CTD"                         ,        4,      1,      635,    "R/W",  0,      0,      0ull,   0ull},
50165         {"RESERVED_5_31"               ,        5,      27,     635,    "RAZ",  1,      1,      0,      0},
50166         {"RESERVED_0_31"               ,        0,      32,     636,    "RAZ",  1,      1,      0,      0},
50167         {"RESERVED_0_31"               ,        0,      32,     637,    "RAZ",  1,      1,      0,      0},
50168         {"RESERVED_0_31"               ,        0,      32,     638,    "RAZ",  1,      1,      0,      0},
50169         {"RESERVED_0_31"               ,        0,      32,     639,    "RAZ",  1,      1,      0,      0},
50170         {"PCIEEC"                      ,        0,      16,     640,    "RO",   0,      0,      1ull,   1ull},
50171         {"CV"                          ,        16,     4,      640,    "RO",   0,      0,      1ull,   1ull},
50172         {"NCO"                         ,        20,     12,     640,    "RO",   0,      0,      0ull,   0ull},
50173         {"RESERVED_0_3"                ,        0,      4,      641,    "RAZ",  1,      1,      0,      0},
50174         {"DLPES"                       ,        4,      1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50175         {"SDES"                        ,        5,      1,      641,    "RO",   0,      0,      0ull,   0ull},
50176         {"RESERVED_6_11"               ,        6,      6,      641,    "RAZ",  1,      1,      0,      0},
50177         {"PTLPS"                       ,        12,     1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50178         {"FCPES"                       ,        13,     1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50179         {"CTS"                         ,        14,     1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50180         {"CAS"                         ,        15,     1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50181         {"UCS"                         ,        16,     1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50182         {"ROS"                         ,        17,     1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50183         {"MTLPS"                       ,        18,     1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50184         {"ECRCES"                      ,        19,     1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50185         {"URES"                        ,        20,     1,      641,    "R/W1C",        0,      0,      0ull,   0ull},
50186         {"RESERVED_21_31"              ,        21,     11,     641,    "RAZ",  1,      1,      0,      0},
50187         {"RESERVED_0_3"                ,        0,      4,      642,    "RAZ",  1,      1,      0,      0},
50188         {"DLPEM"                       ,        4,      1,      642,    "R/W",  0,      0,      0ull,   0ull},
50189         {"SDEM"                        ,        5,      1,      642,    "RO",   0,      0,      0ull,   0ull},
50190         {"RESERVED_6_11"               ,        6,      6,      642,    "RAZ",  1,      1,      0,      0},
50191         {"PTLPM"                       ,        12,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
50192         {"FCPEM"                       ,        13,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
50193         {"CTM"                         ,        14,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
50194         {"CAM"                         ,        15,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
50195         {"UCM"                         ,        16,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
50196         {"ROM"                         ,        17,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
50197         {"MTLPM"                       ,        18,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
50198         {"ECRCEM"                      ,        19,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
50199         {"UREM"                        ,        20,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
50200         {"RESERVED_21_31"              ,        21,     11,     642,    "RAZ",  1,      1,      0,      0},
50201         {"RESERVED_0_3"                ,        0,      4,      643,    "RAZ",  1,      1,      0,      0},
50202         {"DLPES"                       ,        4,      1,      643,    "R/W",  0,      0,      1ull,   1ull},
50203         {"SDES"                        ,        5,      1,      643,    "RO",   0,      0,      1ull,   1ull},
50204         {"RESERVED_6_11"               ,        6,      6,      643,    "RAZ",  1,      1,      0,      0},
50205         {"PTLPS"                       ,        12,     1,      643,    "R/W",  0,      0,      0ull,   0ull},
50206         {"FCPES"                       ,        13,     1,      643,    "R/W",  0,      0,      1ull,   1ull},
50207         {"CTS"                         ,        14,     1,      643,    "R/W",  0,      0,      0ull,   0ull},
50208         {"CAS"                         ,        15,     1,      643,    "R/W",  0,      0,      0ull,   0ull},
50209         {"UCS"                         ,        16,     1,      643,    "R/W",  0,      0,      0ull,   0ull},
50210         {"ROS"                         ,        17,     1,      643,    "R/W",  0,      0,      1ull,   1ull},
50211         {"MTLPS"                       ,        18,     1,      643,    "R/W",  0,      0,      1ull,   1ull},
50212         {"ECRCES"                      ,        19,     1,      643,    "R/W",  0,      0,      0ull,   0ull},
50213         {"URES"                        ,        20,     1,      643,    "R/W",  0,      0,      0ull,   0ull},
50214         {"RESERVED_21_31"              ,        21,     11,     643,    "RAZ",  1,      1,      0,      0},
50215         {"RES"                         ,        0,      1,      644,    "R/W1C",        0,      0,      0ull,   0ull},
50216         {"RESERVED_1_5"                ,        1,      5,      644,    "RAZ",  1,      1,      0,      0},
50217         {"BTLPS"                       ,        6,      1,      644,    "R/W1C",        0,      0,      0ull,   0ull},
50218         {"BDLLPS"                      ,        7,      1,      644,    "R/W1C",        0,      0,      0ull,   0ull},
50219         {"RNRS"                        ,        8,      1,      644,    "R/W1C",        0,      0,      0ull,   0ull},
50220         {"RESERVED_9_11"               ,        9,      3,      644,    "RAZ",  1,      1,      0,      0},
50221         {"RTTS"                        ,        12,     1,      644,    "R/W1C",        0,      0,      0ull,   0ull},
50222         {"ANFES"                       ,        13,     1,      644,    "R/W1C",        0,      0,      0ull,   0ull},
50223         {"RESERVED_14_31"              ,        14,     18,     644,    "RAZ",  1,      1,      0,      0},
50224         {"REM"                         ,        0,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
50225         {"RESERVED_1_5"                ,        1,      5,      645,    "RAZ",  1,      1,      0,      0},
50226         {"BTLPM"                       ,        6,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
50227         {"BDLLPM"                      ,        7,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
50228         {"RNRM"                        ,        8,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
50229         {"RESERVED_9_11"               ,        9,      3,      645,    "RAZ",  1,      1,      0,      0},
50230         {"RTTM"                        ,        12,     1,      645,    "R/W",  0,      0,      0ull,   0ull},
50231         {"ANFEM"                       ,        13,     1,      645,    "R/W",  0,      0,      1ull,   1ull},
50232         {"RESERVED_14_31"              ,        14,     18,     645,    "RAZ",  1,      1,      0,      0},
50233         {"FEP"                         ,        0,      5,      646,    "RO",   0,      0,      0ull,   0ull},
50234         {"GC"                          ,        5,      1,      646,    "RO",   0,      0,      1ull,   1ull},
50235         {"GE"                          ,        6,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
50236         {"CC"                          ,        7,      1,      646,    "RO",   0,      0,      1ull,   1ull},
50237         {"CE"                          ,        8,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
50238         {"RESERVED_9_31"               ,        9,      23,     646,    "RAZ",  1,      1,      0,      0},
50239         {"DWORD1"                      ,        0,      32,     647,    "RO",   0,      0,      0ull,   0ull},
50240         {"DWORD2"                      ,        0,      32,     648,    "RO",   0,      0,      0ull,   0ull},
50241         {"DWORD3"                      ,        0,      32,     649,    "RO",   0,      0,      0ull,   0ull},
50242         {"DWORD4"                      ,        0,      32,     650,    "RO",   0,      0,      0ull,   0ull},
50243         {"CERE"                        ,        0,      1,      651,    "R/W",  0,      0,      0ull,   0ull},
50244         {"NFERE"                       ,        1,      1,      651,    "R/W",  0,      0,      0ull,   0ull},
50245         {"FERE"                        ,        2,      1,      651,    "R/W",  0,      0,      0ull,   0ull},
50246         {"RESERVED_3_31"               ,        3,      29,     651,    "RAZ",  1,      1,      0,      0},
50247         {"ECR"                         ,        0,      1,      652,    "R/W1C",        0,      0,      0ull,   0ull},
50248         {"MULTI_ECR"                   ,        1,      1,      652,    "R/W1C",        0,      0,      0ull,   0ull},
50249         {"EFNFR"                       ,        2,      1,      652,    "R/W1C",        0,      0,      0ull,   0ull},
50250         {"MULTI_EFNFR"                 ,        3,      1,      652,    "R/W1C",        0,      0,      0ull,   0ull},
50251         {"FUF"                         ,        4,      1,      652,    "R/W1C",        0,      0,      0ull,   0ull},
50252         {"NFEMR"                       ,        5,      1,      652,    "R/W1C",        0,      0,      0ull,   0ull},
50253         {"FEMR"                        ,        6,      1,      652,    "R/W1C",        0,      0,      0ull,   0ull},
50254         {"RESERVED_7_26"               ,        7,      20,     652,    "RAZ",  1,      1,      0,      0},
50255         {"AEIMN"                       ,        27,     5,      652,    "R/W",  0,      0,      0ull,   0ull},
50256         {"ECSI"                        ,        0,      16,     653,    "RO",   0,      0,      0ull,   0ull},
50257         {"EFNFSI"                      ,        16,     16,     653,    "RO",   0,      0,      0ull,   0ull},
50258         {"RTLTL"                       ,        0,      16,     654,    "R/W",  0,      0,      4143ull,        4143ull},
50259         {"RTL"                         ,        16,     16,     654,    "R/W",  0,      0,      12429ull,       12429ull},
50260         {"OMR"                         ,        0,      32,     655,    "R/W",  0,      1,      4294967295ull,  0},
50261         {"LINK_NUM"                    ,        0,      8,      656,    "R/W",  0,      0,      4ull,   4ull},
50262         {"RESERVED_8_14"               ,        8,      7,      656,    "RAZ",  1,      1,      0,      0},
50263         {"FORCE_LINK"                  ,        15,     1,      656,    "R/W",  0,      0,      0ull,   0ull},
50264         {"LINK_STATE"                  ,        16,     6,      656,    "R/W",  0,      0,      0ull,   0ull},
50265         {"RESERVED_22_23"              ,        22,     2,      656,    "RAZ",  1,      1,      0,      0},
50266         {"LPEC"                        ,        24,     8,      656,    "RO",   0,      0,      7ull,   7ull},
50267         {"ACK_FREQ"                    ,        0,      8,      657,    "R/W",  0,      0,      0ull,   0ull},
50268         {"N_FTS"                       ,        8,      8,      657,    "R/W",  0,      0,      128ull, 128ull},
50269         {"N_FTS_CC"                    ,        16,     8,      657,    "R/W",  0,      0,      128ull, 128ull},
50270         {"L0EL"                        ,        24,     3,      657,    "R/W",  0,      0,      3ull,   3ull},
50271         {"L1EL"                        ,        27,     3,      657,    "R/W",  0,      0,      3ull,   3ull},
50272         {"RESERVED_30_31"              ,        30,     2,      657,    "RAZ",  1,      1,      0,      0},
50273         {"OMR"                         ,        0,      1,      658,    "R/W",  0,      0,      0ull,   0ull},
50274         {"SD"                          ,        1,      1,      658,    "R/W",  0,      0,      0ull,   0ull},
50275         {"LE"                          ,        2,      1,      658,    "R/W",  0,      0,      0ull,   0ull},
50276         {"RA"                          ,        3,      1,      658,    "R/W",  0,      0,      0ull,   0ull},
50277         {"RESERVED_4_4"                ,        4,      1,      658,    "RAZ",  1,      1,      0,      0},
50278         {"DLLLE"                       ,        5,      1,      658,    "R/W",  0,      0,      1ull,   1ull},
50279         {"RESERVED_6_6"                ,        6,      1,      658,    "RAZ",  1,      1,      0,      0},
50280         {"FLM"                         ,        7,      1,      658,    "R/W",  0,      0,      0ull,   0ull},
50281         {"RESERVED_8_15"               ,        8,      8,      658,    "RO",   0,      0,      1ull,   1ull},
50282         {"LME"                         ,        16,     6,      658,    "R/W",  0,      0,      15ull,  15ull},
50283         {"RESERVED_22_24"              ,        22,     3,      658,    "RAZ",  1,      1,      0,      0},
50284         {"ECCRC"                       ,        25,     1,      658,    "R/W",  0,      0,      0ull,   0ull},
50285         {"RESERVED_26_31"              ,        26,     6,      658,    "RAZ",  1,      1,      0,      0},
50286         {"ILST"                        ,        0,      24,     659,    "R/W",  0,      0,      0ull,   0ull},
50287         {"FCD"                         ,        24,     1,      659,    "R/W",  0,      0,      0ull,   0ull},
50288         {"ACK_NAK"                     ,        25,     1,      659,    "R/W",  0,      0,      0ull,   0ull},
50289         {"RESERVED_26_30"              ,        26,     5,      659,    "RAZ",  1,      1,      0,      0},
50290         {"DLLD"                        ,        31,     1,      659,    "R/W",  0,      0,      0ull,   0ull},
50291         {"NTSS"                        ,        0,      4,      660,    "R/W",  0,      0,      10ull,  10ull},
50292         {"RESERVED_4_7"                ,        4,      4,      660,    "RO",   1,      1,      0,      0},
50293         {"NSKPS"                       ,        8,      3,      660,    "R/W",  0,      0,      3ull,   3ull},
50294         {"RESERVED_11_13"              ,        11,     3,      660,    "RAZ",  1,      1,      0,      0},
50295         {"TMRT"                        ,        14,     5,      660,    "R/W",  0,      0,      8ull,   8ull},
50296         {"TMANLT"                      ,        19,     5,      660,    "R/W",  0,      0,      0ull,   0ull},
50297         {"TMFCWT"                      ,        24,     5,      660,    "R/W",  0,      0,      0ull,   0ull},
50298         {"RESERVED_29_31"              ,        29,     3,      660,    "RO",   1,      1,      0,      0},
50299         {"SKPIV"                       ,        0,      11,     661,    "R/W",  0,      0,      1280ull,        1280ull},
50300         {"RESERVED_11_14"              ,        11,     4,      661,    "RAZ",  1,      1,      0,      0},
50301         {"DFCWT"                       ,        15,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50302         {"M_FUN"                       ,        16,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50303         {"M_POIS_FILT"                 ,        17,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50304         {"M_BAR_MATCH"                 ,        18,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50305         {"M_CFG1_FILT"                 ,        19,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50306         {"M_LK_FILT"                   ,        20,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50307         {"M_CPL_TAG_ERR"               ,        21,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50308         {"M_CPL_RID_ERR"               ,        22,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50309         {"M_CPL_FUN_ERR"               ,        23,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50310         {"M_CPL_TC_ERR"                ,        24,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50311         {"M_CPL_ATTR_ERR"              ,        25,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50312         {"M_CPL_LEN_ERR"               ,        26,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50313         {"M_ECRC_FILT"                 ,        27,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50314         {"M_CPL_ECRC_FILT"             ,        28,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50315         {"MSG_CTRL"                    ,        29,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50316         {"M_IO_FILT"                   ,        30,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50317         {"M_CFG0_FILT"                 ,        31,     1,      661,    "R/W",  0,      0,      0ull,   0ull},
50318         {"M_VEND0_DRP"                 ,        0,      1,      662,    "R/W",  0,      0,      0ull,   0ull},
50319         {"M_VEND1_DRP"                 ,        1,      1,      662,    "R/W",  0,      0,      0ull,   0ull},
50320         {"RESERVED_2_31"               ,        2,      30,     662,    "RAZ",  1,      1,      0,      0},
50321         {"DBG_INFO_L32"                ,        0,      32,     663,    "RO",   0,      0,      0ull,   0ull},
50322         {"DBG_INFO_U32"                ,        0,      32,     664,    "RO",   0,      0,      0ull,   0ull},
50323         {"TPDFCC"                      ,        0,      12,     665,    "RO",   0,      0,      0ull,   0ull},
50324         {"TPHFCC"                      ,        12,     8,      665,    "RO",   0,      0,      0ull,   0ull},
50325         {"RESERVED_20_31"              ,        20,     12,     665,    "RAZ",  1,      1,      0,      0},
50326         {"TCDFCC"                      ,        0,      12,     666,    "RO",   0,      0,      0ull,   0ull},
50327         {"TCHFCC"                      ,        12,     8,      666,    "RO",   0,      0,      0ull,   0ull},
50328         {"RESERVED_20_31"              ,        20,     12,     666,    "RAZ",  1,      1,      0,      0},
50329         {"TCDFCC"                      ,        0,      12,     667,    "RO",   0,      0,      0ull,   0ull},
50330         {"TCHFCC"                      ,        12,     8,      667,    "RO",   0,      0,      0ull,   0ull},
50331         {"RESERVED_20_31"              ,        20,     12,     667,    "RAZ",  1,      1,      0,      0},
50332         {"RTLPFCCNR"                   ,        0,      1,      668,    "RO",   0,      0,      0ull,   0ull},
50333         {"TRBNE"                       ,        1,      1,      668,    "RO",   0,      0,      0ull,   0ull},
50334         {"RQNE"                        ,        2,      1,      668,    "RO",   0,      0,      0ull,   0ull},
50335         {"RESERVED_3_31"               ,        3,      29,     668,    "RAZ",  1,      1,      0,      0},
50336         {"WRR_VC0"                     ,        0,      8,      669,    "RO",   0,      0,      15ull,  15ull},
50337         {"WRR_VC1"                     ,        8,      8,      669,    "RO",   0,      0,      0ull,   0ull},
50338         {"WRR_VC2"                     ,        16,     8,      669,    "RO",   0,      0,      0ull,   0ull},
50339         {"WRR_VC3"                     ,        24,     8,      669,    "RO",   0,      0,      0ull,   0ull},
50340         {"WRR_VC4"                     ,        0,      8,      670,    "RO",   0,      0,      0ull,   0ull},
50341         {"WRR_VC5"                     ,        8,      8,      670,    "RO",   0,      0,      0ull,   0ull},
50342         {"WRR_VC6"                     ,        16,     8,      670,    "RO",   0,      0,      0ull,   0ull},
50343         {"WRR_VC7"                     ,        24,     8,      670,    "RO",   0,      0,      0ull,   0ull},
50344         {"DATA_CREDITS"                ,        0,      12,     671,    "R/W",  0,      0,      128ull, 128ull},
50345         {"HEADER_CREDITS"              ,        12,     8,      671,    "R/W",  0,      0,      35ull,  35ull},
50346         {"RESERVED_20_20"              ,        20,     1,      671,    "RAZ",  1,      1,      0,      0},
50347         {"QUEUE_MODE"                  ,        21,     3,      671,    "R/W",  0,      0,      2ull,   2ull},
50348         {"RESERVED_24_29"              ,        24,     6,      671,    "RAZ",  1,      1,      0,      0},
50349         {"TYPE_ORDERING"               ,        30,     1,      671,    "R/W",  0,      0,      1ull,   1ull},
50350         {"RX_QUEUE_ORDER"              ,        31,     1,      671,    "R/W",  0,      0,      0ull,   0ull},
50351         {"DATA_CREDITS"                ,        0,      12,     672,    "R/W",  0,      0,      4ull,   4ull},
50352         {"HEADER_CREDITS"              ,        12,     8,      672,    "R/W",  0,      0,      8ull,   8ull},
50353         {"RESERVED_20_20"              ,        20,     1,      672,    "RAZ",  1,      1,      0,      0},
50354         {"QUEUE_MODE"                  ,        21,     3,      672,    "R/W",  0,      0,      2ull,   2ull},
50355         {"RESERVED_24_31"              ,        24,     8,      672,    "RAZ",  1,      1,      0,      0},
50356         {"DATA_CREDITS"                ,        0,      12,     673,    "R/W",  0,      0,      128ull, 128ull},
50357         {"HEADER_CREDITS"              ,        12,     8,      673,    "R/W",  0,      0,      64ull,  64ull},
50358         {"RESERVED_20_20"              ,        20,     1,      673,    "RAZ",  1,      1,      0,      0},
50359         {"QUEUE_MODE"                  ,        21,     3,      673,    "R/W",  0,      0,      2ull,   2ull},
50360         {"RESERVED_24_31"              ,        24,     8,      673,    "RAZ",  1,      1,      0,      0},
50361         {"DATA_DEPTH"                  ,        0,      14,     674,    "R/W",  0,      0,      331ull, 331ull},
50362         {"RESERVED_14_15"              ,        14,     2,      674,    "RAZ",  1,      1,      0,      0},
50363         {"HEADER_DEPTH"                ,        16,     10,     674,    "R/W",  0,      0,      41ull,  41ull},
50364         {"RESERVED_26_31"              ,        26,     6,      674,    "RAZ",  1,      1,      0,      0},
50365         {"DATA_DEPTH"                  ,        0,      14,     675,    "R/W",  0,      0,      56ull,  56ull},
50366         {"RESERVED_14_15"              ,        14,     2,      675,    "RAZ",  1,      1,      0,      0},
50367         {"HEADER_DEPTH"                ,        16,     10,     675,    "R/W",  0,      0,      14ull,  14ull},
50368         {"RESERVED_26_31"              ,        26,     6,      675,    "RAZ",  1,      1,      0,      0},
50369         {"DATA_DEPTH"                  ,        0,      14,     676,    "R/W",  0,      0,      360ull, 360ull},
50370         {"RESERVED_14_15"              ,        14,     2,      676,    "RAZ",  1,      1,      0,      0},
50371         {"HEADER_DEPTH"                ,        16,     10,     676,    "R/W",  0,      0,      70ull,  70ull},
50372         {"RESERVED_26_31"              ,        26,     6,      676,    "RAZ",  1,      1,      0,      0},
50373         {"PHY_STAT"                    ,        0,      32,     677,    "RO",   0,      0,      0ull,   0ull},
50374         {"PHY_CTRL"                    ,        0,      32,     678,    "R/W",  0,      0,      0ull,   0ull},
50375         {"RESERVED_0_4"                ,        0,      5,      679,    "RAZ",  0,      0,      0ull,   0ull},
50376         {"FD"                          ,        5,      1,      679,    "R/W",  0,      0,      1ull,   1ull},
50377         {"HFD"                         ,        6,      1,      679,    "R/W",  0,      0,      1ull,   1ull},
50378         {"PAUSE"                       ,        7,      2,      679,    "R/W",  0,      0,      0ull,   0ull},
50379         {"RESERVED_9_11"               ,        9,      3,      679,    "RAZ",  0,      0,      0ull,   0ull},
50380         {"REM_FLT"                     ,        12,     2,      679,    "R/W",  0,      0,      0ull,   0ull},
50381         {"RESERVED_14_14"              ,        14,     1,      679,    "RAZ",  0,      0,      0ull,   0ull},
50382         {"NP"                          ,        15,     1,      679,    "RO",   0,      0,      0ull,   0ull},
50383         {"RESERVED_16_63"              ,        16,     48,     679,    "RAZ",  1,      1,      0,      0},
50384         {"RESERVED_0_11"               ,        0,      12,     680,    "RAZ",  0,      0,      0ull,   0ull},
50385         {"THOU_THD"                    ,        12,     1,      680,    "RO",   0,      0,      0ull,   0ull},
50386         {"THOU_TFD"                    ,        13,     1,      680,    "RO",   0,      0,      0ull,   0ull},
50387         {"THOU_XHD"                    ,        14,     1,      680,    "RO",   0,      0,      1ull,   1ull},
50388         {"THOU_XFD"                    ,        15,     1,      680,    "RO",   0,      0,      1ull,   1ull},
50389         {"RESERVED_16_63"              ,        16,     48,     680,    "RAZ",  1,      1,      0,      0},
50390         {"RESERVED_0_4"                ,        0,      5,      681,    "RAZ",  0,      0,      0ull,   0ull},
50391         {"FD"                          ,        5,      1,      681,    "RO",   0,      0,      0ull,   0ull},
50392         {"HFD"                         ,        6,      1,      681,    "RO",   0,      0,      0ull,   0ull},
50393         {"PAUSE"                       ,        7,      2,      681,    "RO",   0,      0,      0ull,   0ull},
50394         {"RESERVED_9_11"               ,        9,      3,      681,    "RAZ",  0,      0,      0ull,   0ull},
50395         {"REM_FLT"                     ,        12,     2,      681,    "RO",   0,      0,      0ull,   0ull},
50396         {"ACK"                         ,        14,     1,      681,    "RO",   0,      1,      0ull,   0},
50397         {"NP"                          ,        15,     1,      681,    "RO",   0,      0,      0ull,   0ull},
50398         {"RESERVED_16_63"              ,        16,     48,     681,    "RAZ",  1,      1,      0,      0},
50399         {"LINK_OK"                     ,        0,      1,      682,    "RO",   0,      0,      0ull,   0ull},
50400         {"DUP"                         ,        1,      1,      682,    "RO",   0,      0,      0ull,   0ull},
50401         {"AN_CPT"                      ,        2,      1,      682,    "RO",   0,      0,      0ull,   1ull},
50402         {"SPD"                         ,        3,      2,      682,    "RO",   0,      0,      0ull,   0ull},
50403         {"PAUSE"                       ,        5,      2,      682,    "RO",   0,      0,      0ull,   0ull},
50404         {"RESERVED_7_63"               ,        7,      57,     682,    "RAZ",  1,      1,      0,      0},
50405         {"LNKSPD_EN"                   ,        0,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50406         {"XMIT_EN"                     ,        1,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50407         {"AN_ERR_EN"                   ,        2,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50408         {"TXFIFU_EN"                   ,        3,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50409         {"TXFIFO_EN"                   ,        4,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50410         {"TXBAD_EN"                    ,        5,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50411         {"RXERR_EN"                    ,        6,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50412         {"RXBAD_EN"                    ,        7,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50413         {"RXLOCK_EN"                   ,        8,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50414         {"AN_BAD_EN"                   ,        9,      1,      683,    "R/W",  0,      0,      0ull,   1ull},
50415         {"SYNC_BAD_EN"                 ,        10,     1,      683,    "R/W",  0,      0,      0ull,   1ull},
50416         {"DUP"                         ,        11,     1,      683,    "R/W",  0,      0,      0ull,   1ull},
50417         {"RESERVED_12_63"              ,        12,     52,     683,    "RAZ",  1,      1,      0,      0},
50418         {"LNKSPD"                      ,        0,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50419         {"XMIT"                        ,        1,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50420         {"AN_ERR"                      ,        2,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50421         {"TXFIFU"                      ,        3,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50422         {"TXFIFO"                      ,        4,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50423         {"TXBAD"                       ,        5,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50424         {"RXERR"                       ,        6,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50425         {"RXBAD"                       ,        7,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50426         {"RXLOCK"                      ,        8,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50427         {"AN_BAD"                      ,        9,      1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50428         {"SYNC_BAD"                    ,        10,     1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50429         {"DUP"                         ,        11,     1,      684,    "R/W1C",        0,      0,      0ull,   0ull},
50430         {"RESERVED_12_63"              ,        12,     52,     684,    "RAZ",  1,      1,      0,      0},
50431         {"COUNT"                       ,        0,      16,     685,    "R/W",  0,      1,      1094ull,        0},
50432         {"RESERVED_16_63"              ,        16,     48,     685,    "RAZ",  1,      1,      0,      0},
50433         {"PKT_SZ"                      ,        0,      2,      686,    "R/W",  0,      0,      0ull,   0ull},
50434         {"LA_EN"                       ,        2,      1,      686,    "R/W",  0,      0,      0ull,   0ull},
50435         {"LAFIFOVFL"                   ,        3,      1,      686,    "R/W1C",        0,      0,      0ull,   0ull},
50436         {"RESERVED_4_63"               ,        4,      60,     686,    "RAZ",  1,      1,      0,      0},
50437         {"SAMP_PT"                     ,        0,      7,      687,    "R/W",  0,      1,      1ull,   0},
50438         {"AN_OVRD"                     ,        7,      1,      687,    "R/W",  0,      0,      0ull,   0ull},
50439         {"MODE"                        ,        8,      1,      687,    "R/W",  0,      0,      0ull,   0ull},
50440         {"MAC_PHY"                     ,        9,      1,      687,    "R/W",  0,      0,      0ull,   0ull},
50441         {"LOOPBCK2"                    ,        10,     1,      687,    "R/W",  0,      0,      0ull,   0ull},
50442         {"GMXENO"                      ,        11,     1,      687,    "R/W",  0,      0,      0ull,   0ull},
50443         {"SGMII"                       ,        12,     1,      687,    "RO",   1,      1,      0,      0},
50444         {"RESERVED_13_63"              ,        13,     51,     687,    "RAZ",  1,      1,      0,      0},
50445         {"RESERVED_0_4"                ,        0,      5,      688,    "RAZ",  1,      1,      0,      0},
50446         {"UNI"                         ,        5,      1,      688,    "R/W",  0,      0,      0ull,   0ull},
50447         {"SPDMSB"                      ,        6,      1,      688,    "R/W",  0,      0,      1ull,   1ull},
50448         {"COLTST"                      ,        7,      1,      688,    "R/W",  0,      0,      0ull,   0ull},
50449         {"DUP"                         ,        8,      1,      688,    "R/W",  0,      0,      1ull,   1ull},
50450         {"RST_AN"                      ,        9,      1,      688,    "R/W",  0,      0,      0ull,   0ull},
50451         {"RESERVED_10_10"              ,        10,     1,      688,    "RAZ",  1,      1,      0,      0},
50452         {"PWR_DN"                      ,        11,     1,      688,    "R/W",  0,      0,      1ull,   0ull},
50453         {"AN_EN"                       ,        12,     1,      688,    "R/W",  0,      0,      0ull,   0ull},
50454         {"SPDLSB"                      ,        13,     1,      688,    "R/W",  0,      0,      0ull,   0ull},
50455         {"LOOPBCK1"                    ,        14,     1,      688,    "R/W",  0,      0,      0ull,   0ull},
50456         {"RESET"                       ,        15,     1,      688,    "R/W",  0,      0,      0ull,   0ull},
50457         {"RESERVED_16_63"              ,        16,     48,     688,    "RAZ",  1,      1,      0,      0},
50458         {"EXTND"                       ,        0,      1,      689,    "RO",   0,      0,      0ull,   0ull},
50459         {"RESERVED_1_1"                ,        1,      1,      689,    "RAZ",  0,      0,      0ull,   0ull},
50460         {"LNK_ST"                      ,        2,      1,      689,    "RO",   0,      0,      0ull,   1ull},
50461         {"AN_ABIL"                     ,        3,      1,      689,    "RO",   0,      0,      1ull,   1ull},
50462         {"RM_FLT"                      ,        4,      1,      689,    "RO",   0,      0,      0ull,   0ull},
50463         {"AN_CPT"                      ,        5,      1,      689,    "RO",   0,      0,      0ull,   0ull},
50464         {"PRB_SUP"                     ,        6,      1,      689,    "RO",   0,      0,      1ull,   1ull},
50465         {"RESERVED_7_7"                ,        7,      1,      689,    "RAZ",  0,      0,      0ull,   0ull},
50466         {"EXT_ST"                      ,        8,      1,      689,    "RO",   0,      0,      1ull,   1ull},
50467         {"HUN_T2HD"                    ,        9,      1,      689,    "RO",   0,      0,      0ull,   0ull},
50468         {"HUN_T2FD"                    ,        10,     1,      689,    "RO",   0,      0,      0ull,   0ull},
50469         {"TEN_HD"                      ,        11,     1,      689,    "RO",   0,      0,      0ull,   0ull},
50470         {"TEN_FD"                      ,        12,     1,      689,    "RO",   0,      0,      0ull,   0ull},
50471         {"HUN_XHD"                     ,        13,     1,      689,    "RO",   0,      0,      0ull,   0ull},
50472         {"HUN_XFD"                     ,        14,     1,      689,    "RO",   0,      0,      0ull,   0ull},
50473         {"HUN_T4"                      ,        15,     1,      689,    "RO",   0,      0,      0ull,   0ull},
50474         {"RESERVED_16_63"              ,        16,     48,     689,    "RAZ",  1,      1,      0,      0},
50475         {"AN_ST"                       ,        0,      4,      690,    "RO",   0,      0,      0ull,   0ull},
50476         {"AN_BAD"                      ,        4,      1,      690,    "RO",   0,      0,      0ull,   0ull},
50477         {"SYNC"                        ,        5,      4,      690,    "RO",   0,      0,      0ull,   0ull},
50478         {"SYNC_BAD"                    ,        9,      1,      690,    "RO",   0,      0,      0ull,   0ull},
50479         {"RX_ST"                       ,        10,     5,      690,    "RO",   0,      0,      0ull,   0ull},
50480         {"RX_BAD"                      ,        15,     1,      690,    "RO",   0,      0,      0ull,   0ull},
50481         {"RESERVED_16_63"              ,        16,     48,     690,    "RAZ",  1,      1,      0,      0},
50482         {"BIT_LOCK"                    ,        0,      1,      691,    "RO",   0,      0,      0ull,   0ull},
50483         {"SYNC"                        ,        1,      1,      691,    "RO",   0,      0,      0ull,   0ull},
50484         {"RESERVED_2_63"               ,        2,      62,     691,    "RAZ",  1,      1,      0,      0},
50485         {"ONE"                         ,        0,      1,      692,    "RO",   0,      0,      1ull,   1ull},
50486         {"RESERVED_1_9"                ,        1,      9,      692,    "RAZ",  0,      1,      0ull,   0},
50487         {"SPEED"                       ,        10,     2,      692,    "R/W",  0,      0,      2ull,   2ull},
50488         {"DUP"                         ,        12,     1,      692,    "R/W",  0,      0,      1ull,   1ull},
50489         {"RESERVED_13_13"              ,        13,     1,      692,    "RAZ",  0,      1,      0ull,   0},
50490         {"ACK"                         ,        14,     1,      692,    "RO",   0,      0,      0ull,   0ull},
50491         {"LINK"                        ,        15,     1,      692,    "R/W",  0,      0,      0ull,   1ull},
50492         {"RESERVED_16_63"              ,        16,     48,     692,    "RAZ",  1,      1,      0,      0},
50493         {"ONE"                         ,        0,      1,      693,    "RO",   0,      0,      1ull,   1ull},
50494         {"RESERVED_1_9"                ,        1,      9,      693,    "RAZ",  0,      1,      0ull,   0},
50495         {"SPEED"                       ,        10,     2,      693,    "RO",   0,      0,      0ull,   2ull},
50496         {"DUP"                         ,        12,     1,      693,    "RO",   0,      0,      0ull,   1ull},
50497         {"RESERVED_13_14"              ,        13,     2,      693,    "RAZ",  0,      1,      0ull,   0},
50498         {"LINK"                        ,        15,     1,      693,    "RO",   0,      0,      0ull,   1ull},
50499         {"RESERVED_16_63"              ,        16,     48,     693,    "RAZ",  1,      1,      0,      0},
50500         {"ORD_ST"                      ,        0,      4,      694,    "RO",   0,      0,      0ull,   0ull},
50501         {"TX_BAD"                      ,        4,      1,      694,    "RO",   0,      0,      0ull,   0ull},
50502         {"XMIT"                        ,        5,      2,      694,    "RO",   0,      1,      0ull,   0},
50503         {"RESERVED_7_63"               ,        7,      57,     694,    "RAZ",  1,      1,      0,      0},
50504         {"TXPLRT"                      ,        0,      1,      695,    "R/W",  0,      0,      0ull,   0ull},
50505         {"RXPLRT"                      ,        1,      1,      695,    "R/W",  0,      0,      0ull,   0ull},
50506         {"AUTORXPL"                    ,        2,      1,      695,    "RO",   0,      0,      0ull,   0ull},
50507         {"RXOVRD"                      ,        3,      1,      695,    "R/W",  0,      0,      0ull,   0ull},
50508         {"RESERVED_4_63"               ,        4,      60,     695,    "RAZ",  1,      1,      0,      0},
50509         {"L0SYNC"                      ,        0,      1,      696,    "RO",   0,      0,      0ull,   1ull},
50510         {"L1SYNC"                      ,        1,      1,      696,    "RO",   0,      0,      0ull,   1ull},
50511         {"L2SYNC"                      ,        2,      1,      696,    "RO",   0,      0,      0ull,   1ull},
50512         {"L3SYNC"                      ,        3,      1,      696,    "RO",   0,      0,      0ull,   1ull},
50513         {"RESERVED_4_10"               ,        4,      7,      696,    "RAZ",  1,      1,      0,      0},
50514         {"PATTST"                      ,        11,     1,      696,    "RO",   0,      0,      0ull,   0ull},
50515         {"ALIGND"                      ,        12,     1,      696,    "RO",   0,      0,      0ull,   1ull},
50516         {"RESERVED_13_63"              ,        13,     51,     696,    "RAZ",  1,      1,      0,      0},
50517         {"BIST_STATUS"                 ,        0,      1,      697,    "RO",   0,      0,      0ull,   0ull},
50518         {"RESERVED_1_63"               ,        1,      63,     697,    "RAZ",  1,      1,      0,      0},
50519         {"BITLCK0"                     ,        0,      1,      698,    "RO",   0,      1,      0ull,   0},
50520         {"BITLCK1"                     ,        1,      1,      698,    "RO",   0,      1,      0ull,   0},
50521         {"BITLCK2"                     ,        2,      1,      698,    "RO",   0,      1,      0ull,   0},
50522         {"BITLCK3"                     ,        3,      1,      698,    "RO",   0,      1,      0ull,   0},
50523         {"RESERVED_4_63"               ,        4,      60,     698,    "RAZ",  1,      1,      0,      0},
50524         {"RESERVED_0_1"                ,        0,      2,      699,    "RAZ",  1,      1,      0,      0},
50525         {"SPD"                         ,        2,      4,      699,    "RO",   0,      0,      0ull,   0ull},
50526         {"SPDSEL0"                     ,        6,      1,      699,    "RO",   0,      0,      1ull,   1ull},
50527         {"RESERVED_7_10"               ,        7,      4,      699,    "RAZ",  1,      1,      0,      0},
50528         {"LO_PWR"                      ,        11,     1,      699,    "R/W",  0,      0,      0ull,   0ull},
50529         {"RESERVED_12_12"              ,        12,     1,      699,    "RAZ",  1,      1,      0,      0},
50530         {"SPDSEL1"                     ,        13,     1,      699,    "RO",   0,      0,      1ull,   1ull},
50531         {"LOOPBCK1"                    ,        14,     1,      699,    "R/W",  0,      0,      0ull,   0ull},
50532         {"RESET"                       ,        15,     1,      699,    "R/W",  0,      0,      1ull,   0ull},
50533         {"RESERVED_16_63"              ,        16,     48,     699,    "RAZ",  1,      1,      0,      0},
50534         {"TYPE"                        ,        0,      2,      700,    "RO",   0,      0,      1ull,   1ull},
50535         {"RESERVED_2_63"               ,        2,      62,     700,    "RAZ",  1,      1,      0,      0},
50536         {"TXFLT_EN"                    ,        0,      1,      701,    "R/W",  0,      0,      0ull,   1ull},
50537         {"RXBAD_EN"                    ,        1,      1,      701,    "R/W",  0,      0,      0ull,   1ull},
50538         {"RXSYNBAD_EN"                 ,        2,      1,      701,    "R/W",  0,      0,      0ull,   1ull},
50539         {"BITLCKLS_EN"                 ,        3,      1,      701,    "R/W",  0,      0,      0ull,   1ull},
50540         {"SYNLOS_EN"                   ,        4,      1,      701,    "R/W",  0,      0,      0ull,   1ull},
50541         {"ALGNLOS_EN"                  ,        5,      1,      701,    "R/W",  0,      0,      0ull,   1ull},
50542         {"RESERVED_6_63"               ,        6,      58,     701,    "RAZ",  1,      1,      0,      0},
50543         {"TXFLT"                       ,        0,      1,      702,    "R/W1C",        0,      0,      0ull,   0ull},
50544         {"RXBAD"                       ,        1,      1,      702,    "R/W1C",        0,      0,      0ull,   0ull},
50545         {"RXSYNBAD"                    ,        2,      1,      702,    "R/W1C",        0,      0,      0ull,   0ull},
50546         {"BITLCKLS"                    ,        3,      1,      702,    "R/W1C",        0,      0,      0ull,   0ull},
50547         {"SYNLOS"                      ,        4,      1,      702,    "R/W1C",        0,      0,      0ull,   0ull},
50548         {"ALGNLOS"                     ,        5,      1,      702,    "R/W1C",        0,      0,      0ull,   0ull},
50549         {"RESERVED_6_63"               ,        6,      58,     702,    "RAZ",  1,      1,      0,      0},
50550         {"PKT_SZ"                      ,        0,      2,      703,    "R/W",  0,      0,      0ull,   0ull},
50551         {"LA_EN"                       ,        2,      1,      703,    "R/W",  0,      0,      0ull,   0ull},
50552         {"LAFIFOVFL"                   ,        3,      1,      703,    "R/W1C",        0,      0,      0ull,   0ull},
50553         {"DROP_LN"                     ,        4,      2,      703,    "R/W",  0,      0,      0ull,   0ull},
50554         {"ENC_MODE"                    ,        6,      1,      703,    "R/W",  0,      0,      0ull,   0ull},
50555         {"RESERVED_7_63"               ,        7,      57,     703,    "RAZ",  1,      1,      0,      0},
50556         {"GMXENO"                      ,        0,      1,      704,    "R/W",  0,      0,      0ull,   0ull},
50557         {"XAUI"                        ,        1,      1,      704,    "RO",   1,      1,      0,      0},
50558         {"RX_SWAP"                     ,        2,      1,      704,    "R/W",  0,      1,      0ull,   0},
50559         {"TX_SWAP"                     ,        3,      1,      704,    "R/W",  0,      1,      0ull,   0},
50560         {"RESERVED_4_63"               ,        4,      60,     704,    "RAZ",  1,      1,      0,      0},
50561         {"SYNC0ST"                     ,        0,      4,      705,    "RO",   0,      1,      0ull,   0},
50562         {"SYNC1ST"                     ,        4,      4,      705,    "RO",   0,      1,      0ull,   0},
50563         {"SYNC2ST"                     ,        8,      4,      705,    "RO",   0,      1,      0ull,   0},
50564         {"SYNC3ST"                     ,        12,     4,      705,    "RO",   0,      1,      0ull,   0},
50565         {"RESERVED_16_63"              ,        16,     48,     705,    "RAZ",  1,      1,      0,      0},
50566         {"TENGB"                       ,        0,      1,      706,    "RO",   0,      0,      1ull,   1ull},
50567         {"TENPASST"                    ,        1,      1,      706,    "RO",   0,      0,      0ull,   0ull},
50568         {"RESERVED_2_63"               ,        2,      62,     706,    "RAZ",  1,      1,      0,      0},
50569         {"RESERVED_0_0"                ,        0,      1,      707,    "RAZ",  1,      1,      0,      0},
50570         {"LPABLE"                      ,        1,      1,      707,    "RO",   0,      0,      1ull,   1ull},
50571         {"RCV_LNK"                     ,        2,      1,      707,    "RO",   0,      0,      0ull,   1ull},
50572         {"RESERVED_3_6"                ,        3,      4,      707,    "RAZ",  1,      1,      0,      0},
50573         {"FLT"                         ,        7,      1,      707,    "RO",   0,      0,      0ull,   0ull},
50574         {"RESERVED_8_63"               ,        8,      56,     707,    "RAZ",  1,      1,      0,      0},
50575         {"TENGB_R"                     ,        0,      1,      708,    "RO",   0,      0,      0ull,   0ull},
50576         {"TENGB_X"                     ,        1,      1,      708,    "RO",   0,      0,      1ull,   1ull},
50577         {"TENGB_W"                     ,        2,      1,      708,    "RO",   0,      0,      0ull,   0ull},
50578         {"RESERVED_3_9"                ,        3,      7,      708,    "RAZ",  1,      1,      0,      0},
50579         {"RCVFLT"                      ,        10,     1,      708,    "RC",   0,      0,      0ull,   0ull},
50580         {"XMTFLT"                      ,        11,     1,      708,    "RC",   0,      0,      0ull,   0ull},
50581         {"RESERVED_12_13"              ,        12,     2,      708,    "RAZ",  1,      1,      0,      0},
50582         {"DEV"                         ,        14,     2,      708,    "RO",   0,      0,      2ull,   2ull},
50583         {"RESERVED_16_63"              ,        16,     48,     708,    "RAZ",  1,      1,      0,      0},
50584         {"TXPLRT"                      ,        0,      1,      709,    "R/W",  0,      0,      0ull,   0ull},
50585         {"RXPLRT"                      ,        1,      1,      709,    "R/W",  0,      0,      0ull,   0ull},
50586         {"XOR_TXPLRT"                  ,        2,      4,      709,    "R/W",  0,      0,      0ull,   0ull},
50587         {"XOR_RXPLRT"                  ,        6,      4,      709,    "R/W",  0,      0,      0ull,   0ull},
50588         {"RESERVED_10_63"              ,        10,     54,     709,    "RAZ",  1,      1,      0,      0},
50589         {"TX_ST"                       ,        0,      3,      710,    "RO",   0,      1,      0ull,   0},
50590         {"RX_ST"                       ,        3,      2,      710,    "RO",   0,      1,      0ull,   0},
50591         {"ALGN_ST"                     ,        5,      3,      710,    "RO",   0,      1,      0ull,   0},
50592         {"RXBAD"                       ,        8,      1,      710,    "RO",   0,      0,      0ull,   0ull},
50593         {"SYN0BAD"                     ,        9,      1,      710,    "RO",   0,      0,      0ull,   0ull},
50594         {"SYN1BAD"                     ,        10,     1,      710,    "RO",   0,      0,      0ull,   0ull},
50595         {"SYN2BAD"                     ,        11,     1,      710,    "RO",   0,      0,      0ull,   0ull},
50596         {"SYN3BAD"                     ,        12,     1,      710,    "RO",   0,      0,      0ull,   0ull},
50597         {"TERM_ERR"                    ,        13,     1,      710,    "R/W1C",        0,      0,      0ull,   0ull},
50598         {"RESERVED_14_63"              ,        14,     50,     710,    "RAZ",  1,      1,      0,      0},
50599         {"SOT"                         ,        0,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50600         {"RQHDR0"                      ,        1,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50601         {"RQHDR1"                      ,        2,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50602         {"RQDATA4"                     ,        3,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50603         {"RQDATA3"                     ,        4,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50604         {"RQDATA2"                     ,        5,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50605         {"RQDATA1"                     ,        6,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50606         {"RQDATA0"                     ,        7,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50607         {"RETRY"                       ,        8,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50608         {"PTLP_OR"                     ,        9,      1,      711,    "RO",   0,      0,      0ull,   0ull},
50609         {"NTLP_OR"                     ,        10,     1,      711,    "RO",   0,      0,      0ull,   0ull},
50610         {"CTLP_OR"                     ,        11,     1,      711,    "RO",   0,      0,      0ull,   0ull},
50611         {"RQDATA5"                     ,        12,     1,      711,    "RO",   0,      0,      0ull,   0ull},
50612         {"RESERVED_13_63"              ,        13,     51,     711,    "RAZ",  1,      1,      0,      0},
50613         {"PPF"                         ,        0,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50614         {"PEF_TC0"                     ,        1,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50615         {"PEF_TCF1"                    ,        2,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50616         {"PEF_TNF"                     ,        3,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50617         {"PEF_TPF0"                    ,        4,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50618         {"PEF_TPF1"                    ,        5,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50619         {"RSL_P2E"                     ,        6,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50620         {"PEAI_P2E"                    ,        7,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50621         {"DBG_P2E"                     ,        8,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50622         {"E2P_RSL"                     ,        9,      1,      712,    "RO",   0,      0,      0ull,   0ull},
50623         {"E2P_P"                       ,        10,     1,      712,    "RO",   0,      0,      0ull,   0ull},
50624         {"E2P_N"                       ,        11,     1,      712,    "RO",   0,      0,      0ull,   0ull},
50625         {"E2P_CPL"                     ,        12,     1,      712,    "RO",   0,      0,      0ull,   0ull},
50626         {"CTO_P2E"                     ,        13,     1,      712,    "RO",   0,      0,      0ull,   0ull},
50627         {"RESERVED_14_63"              ,        14,     50,     712,    "RAZ",  1,      1,      0,      0},
50628         {"ADDR"                        ,        0,      32,     713,    "R/W",  0,      1,      0ull,   0},
50629         {"DATA"                        ,        32,     32,     713,    "R/W",  0,      1,      0ull,   0},
50630         {"ADDR"                        ,        0,      32,     714,    "R/W",  0,      1,      0ull,   0},
50631         {"DATA"                        ,        32,     32,     714,    "R/W",  0,      1,      0ull,   0},
50632         {"TAG"                         ,        0,      32,     715,    "RO",   0,      0,      0ull,   0ull},
50633         {"RESERVED_32_63"              ,        32,     32,     715,    "RAZ",  1,      1,      0,      0},
50634         {"INV_LCRC"                    ,        0,      1,      716,    "R/W",  0,      0,      0ull,   0ull},
50635         {"INV_ECRC"                    ,        1,      1,      716,    "R/W",  0,      0,      0ull,   0ull},
50636         {"RESERVED_2_2"                ,        2,      1,      716,    "RAZ",  0,      0,      0ull,   0ull},
50637         {"RO_CTLP"                     ,        3,      1,      716,    "R/W",  0,      0,      0ull,   0ull},
50638         {"LNK_ENB"                     ,        4,      1,      716,    "R/W",  0,      0,      0ull,   0ull},
50639         {"DLY_ONE"                     ,        5,      1,      716,    "R/W",  0,      0,      0ull,   0ull},
50640         {"NF_ECRC"                     ,        6,      1,      716,    "R/W",  0,      0,      0ull,   0ull},
50641         {"RESERVED_7_8"                ,        7,      2,      716,    "RAZ",  0,      0,      0ull,   0ull},
50642         {"OB_P_CMD"                    ,        9,      1,      716,    "R/W",  0,      0,      0ull,   0ull},
50643         {"PM_XPME"                     ,        10,     1,      716,    "R/W",  0,      0,      0ull,   0ull},
50644         {"PM_XTOFF"                    ,        11,     1,      716,    "R/W",  0,      0,      0ull,   0ull},
50645         {"RESERVED_12_12"              ,        12,     1,      716,    "RAZ",  0,      0,      0ull,   0ull},
50646         {"QLM_CFG"                     ,        13,     2,      716,    "RO",   1,      1,      0,      0},
50647         {"PBUS"                        ,        15,     8,      716,    "RO",   1,      1,      0,      0},
50648         {"DNUM"                        ,        23,     5,      716,    "RO",   1,      1,      0,      0},
50649         {"RESERVED_28_63"              ,        28,     36,     716,    "RAZ",  1,      1,      0,      0},
50650         {"PCIERST"                     ,        0,      1,      717,    "RO",   0,      0,      0ull,   0ull},
50651         {"PCLK_RUN"                    ,        1,      1,      717,    "R/W1C",        0,      0,      0ull,   1ull},
50652         {"RESERVED_2_63"               ,        2,      62,     717,    "RAZ",  1,      1,      0,      0},
50653         {"SPOISON"                     ,        0,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50654         {"RTLPMAL"                     ,        1,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50655         {"RTLPLLE"                     ,        2,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50656         {"RECRCE"                      ,        3,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50657         {"RPOISON"                     ,        4,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50658         {"RCEMRC"                      ,        5,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50659         {"RNFEMRC"                     ,        6,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50660         {"RFEMRC"                      ,        7,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50661         {"RPMERC"                      ,        8,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50662         {"RPTAMRC"                     ,        9,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50663         {"RUMEP"                       ,        10,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50664         {"RVDM"                        ,        11,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50665         {"ACTO"                        ,        12,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50666         {"RTE"                         ,        13,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50667         {"MRE"                         ,        14,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50668         {"RDWDLE"                      ,        15,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50669         {"RTWDLE"                      ,        16,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50670         {"DPEOOSD"                     ,        17,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50671         {"FCPVWT"                      ,        18,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50672         {"RPE"                         ,        19,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50673         {"FCUV"                        ,        20,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50674         {"RQO"                         ,        21,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50675         {"RAUC"                        ,        22,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50676         {"RACUR"                       ,        23,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50677         {"RACCA"                       ,        24,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50678         {"CAAR"                        ,        25,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50679         {"RARWDNS"                     ,        26,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50680         {"RAMTLP"                      ,        27,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50681         {"RACPP"                       ,        28,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50682         {"RAWWPP"                      ,        29,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50683         {"ECRC_E"                      ,        30,     1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
50684         {"RESERVED_31_63"              ,        31,     33,     718,    "RAZ",  1,      1,      0,      0},
50685         {"SPOISON"                     ,        0,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50686         {"RTLPMAL"                     ,        1,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50687         {"RTLPLLE"                     ,        2,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50688         {"RECRCE"                      ,        3,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50689         {"RPOISON"                     ,        4,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50690         {"RCEMRC"                      ,        5,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50691         {"RNFEMRC"                     ,        6,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50692         {"RFEMRC"                      ,        7,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50693         {"RPMERC"                      ,        8,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50694         {"RPTAMRC"                     ,        9,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
50695         {"RUMEP"                       ,        10,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50696         {"RVDM"                        ,        11,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50697         {"ACTO"                        ,        12,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50698         {"RTE"                         ,        13,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50699         {"MRE"                         ,        14,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50700         {"RDWDLE"                      ,        15,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50701         {"RTWDLE"                      ,        16,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50702         {"DPEOOSD"                     ,        17,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50703         {"FCPVWT"                      ,        18,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50704         {"RPE"                         ,        19,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50705         {"FCUV"                        ,        20,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50706         {"RQO"                         ,        21,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50707         {"RAUC"                        ,        22,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50708         {"RACUR"                       ,        23,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50709         {"RACCA"                       ,        24,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50710         {"CAAR"                        ,        25,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50711         {"RARWDNS"                     ,        26,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50712         {"RAMTLP"                      ,        27,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50713         {"RACPP"                       ,        28,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50714         {"RAWWPP"                      ,        29,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50715         {"ECRC_E"                      ,        30,     1,      719,    "R/W",  0,      0,      0ull,   0ull},
50716         {"RESERVED_31_63"              ,        31,     33,     719,    "RAZ",  1,      1,      0,      0},
50717         {"AUX_EN"                      ,        0,      1,      720,    "RO",   0,      0,      0ull,   0ull},
50718         {"PM_EN"                       ,        1,      1,      720,    "RO",   0,      0,      0ull,   0ull},
50719         {"PM_STAT"                     ,        2,      1,      720,    "RO",   0,      0,      0ull,   0ull},
50720         {"PM_DST"                      ,        3,      1,      720,    "RO",   0,      0,      0ull,   0ull},
50721         {"RESERVED_4_63"               ,        4,      60,     720,    "RO",   1,      1,      0,      0},
50722         {"RESERVED_0_13"               ,        0,      14,     721,    "RAZ",  1,      1,      0,      0},
50723         {"ADDR"                        ,        14,     50,     721,    "R/W",  0,      0,      0ull,   0ull},
50724         {"RESERVED_0_25"               ,        0,      26,     722,    "RAZ",  1,      1,      0,      0},
50725         {"ADDR"                        ,        26,     38,     722,    "R/W",  0,      0,      0ull,   0ull},
50726         {"RESERVED_0_38"               ,        0,      39,     723,    "RAZ",  1,      1,      0,      0},
50727         {"ADDR"                        ,        39,     25,     723,    "R/W",  0,      0,      0ull,   0ull},
50728         {"RESERVED_0_11"               ,        0,      12,     724,    "RAZ",  1,      1,      0,      0},
50729         {"ADDR"                        ,        12,     52,     724,    "R/W",  0,      1,      4503599627370495ull,    0},
50730         {"RESERVED_0_11"               ,        0,      12,     725,    "RAZ",  1,      1,      0,      0},
50731         {"ADDR"                        ,        12,     52,     725,    "R/W",  0,      1,      4503599627370495ull,    0},
50732         {"NPEI_P"                      ,        0,      8,      726,    "R/W",  0,      0,      128ull, 128ull},
50733         {"NPEI_NP"                     ,        8,      8,      726,    "R/W",  0,      0,      16ull,  16ull},
50734         {"NPEI_CPL"                    ,        16,     8,      726,    "R/W",  0,      0,      128ull, 128ull},
50735         {"PESC_P"                      ,        24,     8,      726,    "R/W",  0,      0,      128ull, 128ull},
50736         {"PESC_NP"                     ,        32,     8,      726,    "R/W",  0,      0,      16ull,  16ull},
50737         {"PESC_CPL"                    ,        40,     8,      726,    "R/W",  0,      0,      128ull, 128ull},
50738         {"PEAI_PPF"                    ,        48,     8,      726,    "R/W",  0,      0,      128ull, 128ull},
50739         {"RESERVED_56_63"              ,        56,     8,      726,    "RAZ",  1,      1,      0,      0},
50740         {"LOWATER"                     ,        0,      5,      727,    "R/W",  0,      0,      4ull,   4ull},
50741         {"RESERVED_5_7"                ,        5,      3,      727,    "RAZ",  0,      1,      0ull,   0},
50742         {"HIWATER"                     ,        8,      5,      727,    "R/W",  0,      0,      24ull,  24ull},
50743         {"RESERVED_13_62"              ,        13,     50,     727,    "RAZ",  0,      1,      0ull,   0},
50744         {"BCKPRS"                      ,        63,     1,      727,    "RO",   0,      0,      0ull,   0ull},
50745         {"BIST"                        ,        0,      18,     728,    "RO",   0,      0,      0ull,   0ull},
50746         {"RESERVED_18_63"              ,        18,     46,     728,    "RAZ",  1,      1,      0,      0},
50747         {"DPRT"                        ,        0,      16,     729,    "R/W",  0,      0,      0ull,   0ull},
50748         {"UDP"                         ,        16,     1,      729,    "R/W",  0,      0,      0ull,   0ull},
50749         {"TCP"                         ,        17,     1,      729,    "R/W",  0,      0,      0ull,   0ull},
50750         {"RESERVED_18_63"              ,        18,     46,     729,    "RAZ",  1,      1,      0,      0},
50751         {"MAP0"                        ,        0,      4,      730,    "R/W",  0,      0,      0ull,   0ull},
50752         {"MAP1"                        ,        4,      4,      730,    "R/W",  0,      0,      0ull,   0ull},
50753         {"MAP2"                        ,        8,      4,      730,    "R/W",  0,      0,      0ull,   0ull},
50754         {"MAP3"                        ,        12,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50755         {"MAP4"                        ,        16,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50756         {"MAP5"                        ,        20,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50757         {"MAP6"                        ,        24,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50758         {"MAP7"                        ,        28,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50759         {"MAP8"                        ,        32,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50760         {"MAP9"                        ,        36,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50761         {"MAP10"                       ,        40,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50762         {"MAP11"                       ,        44,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50763         {"MAP12"                       ,        48,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50764         {"MAP13"                       ,        52,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50765         {"MAP14"                       ,        56,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50766         {"MAP15"                       ,        60,     4,      730,    "R/W",  0,      0,      0ull,   0ull},
50767         {"MAP0"                        ,        0,      4,      731,    "R/W",  0,      0,      0ull,   0ull},
50768         {"MAP1"                        ,        4,      4,      731,    "R/W",  0,      0,      0ull,   0ull},
50769         {"MAP2"                        ,        8,      4,      731,    "R/W",  0,      0,      0ull,   0ull},
50770         {"MAP3"                        ,        12,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50771         {"MAP4"                        ,        16,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50772         {"MAP5"                        ,        20,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50773         {"MAP6"                        ,        24,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50774         {"MAP7"                        ,        28,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50775         {"MAP8"                        ,        32,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50776         {"MAP9"                        ,        36,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50777         {"MAP10"                       ,        40,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50778         {"MAP11"                       ,        44,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50779         {"MAP12"                       ,        48,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50780         {"MAP13"                       ,        52,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50781         {"MAP14"                       ,        56,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50782         {"MAP15"                       ,        60,     4,      731,    "R/W",  0,      0,      0ull,   0ull},
50783         {"MINLEN"                      ,        0,      16,     732,    "R/W",  0,      0,      64ull,  64ull},
50784         {"MAXLEN"                      ,        16,     16,     732,    "R/W",  0,      0,      1536ull,        1536ull},
50785         {"RESERVED_32_63"              ,        32,     32,     732,    "RAZ",  1,      1,      0,      0},
50786         {"NIP_SHF"                     ,        0,      3,      733,    "R/W",  0,      0,      0ull,   0ull},
50787         {"RESERVED_3_7"                ,        3,      5,      733,    "RAZ",  1,      1,      0,      0},
50788         {"RAW_SHF"                     ,        8,      3,      733,    "R/W",  0,      0,      0ull,   0ull},
50789         {"RESERVED_11_15"              ,        11,     5,      733,    "RAZ",  1,      1,      0,      0},
50790         {"MAX_L2"                      ,        16,     1,      733,    "R/W",  0,      0,      0ull,   0ull},
50791         {"IP6_UDP"                     ,        17,     1,      733,    "R/W",  0,      0,      1ull,   1ull},
50792         {"TAG_SYN"                     ,        18,     1,      733,    "R/W",  0,      0,      0ull,   0ull},
50793         {"RESERVED_19_63"              ,        19,     45,     733,    "RAZ",  1,      1,      0,      0},
50794         {"IP_CHK"                      ,        0,      1,      734,    "R/W",  0,      0,      1ull,   1ull},
50795         {"IP_MAL"                      ,        1,      1,      734,    "R/W",  0,      0,      1ull,   1ull},
50796         {"IP_HOP"                      ,        2,      1,      734,    "R/W",  0,      0,      1ull,   1ull},
50797         {"IP4_OPTS"                    ,        3,      1,      734,    "R/W",  0,      0,      1ull,   1ull},
50798         {"IP6_EEXT"                    ,        4,      2,      734,    "R/W",  0,      0,      1ull,   3ull},
50799         {"RESERVED_6_7"                ,        6,      2,      734,    "RAZ",  1,      1,      0,      0},
50800         {"L4_MAL"                      ,        8,      1,      734,    "R/W",  0,      0,      1ull,   1ull},
50801         {"L4_PRT"                      ,        9,      1,      734,    "R/W",  0,      0,      1ull,   1ull},
50802         {"L4_CHK"                      ,        10,     1,      734,    "R/W",  0,      0,      1ull,   1ull},
50803         {"L4_LEN"                      ,        11,     1,      734,    "R/W",  0,      0,      1ull,   1ull},
50804         {"TCP_FLAG"                    ,        12,     1,      734,    "R/W",  0,      0,      1ull,   1ull},
50805         {"L2_MAL"                      ,        13,     1,      734,    "R/W",  0,      0,      1ull,   1ull},
50806         {"VS_QOS"                      ,        14,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
50807         {"VS_WQE"                      ,        15,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
50808         {"IGNRS"                       ,        16,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
50809         {"RESERVED_17_19"              ,        17,     3,      734,    "RAZ",  0,      0,      0ull,   0ull},
50810         {"RING_EN"                     ,        20,     1,      734,    "R/W",  0,      0,      0ull,   1ull},
50811         {"RESERVED_21_23"              ,        21,     3,      734,    "RAZ",  1,      1,      0,      0},
50812         {"DSA_GRP_SID"                 ,        24,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
50813         {"DSA_GRP_SCMD"                ,        25,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
50814         {"DSA_GRP_TVID"                ,        26,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
50815         {"RESERVED_27_63"              ,        27,     37,     734,    "RAZ",  1,      1,      0,      0},
50816         {"PRI"                         ,        0,      6,      735,    "R/W",  0,      1,      0ull,   0},
50817         {"RESERVED_6_7"                ,        6,      2,      735,    "RAZ",  1,      1,      0,      0},
50818         {"QOS"                         ,        8,      3,      735,    "R/W",  0,      1,      0ull,   0},
50819         {"RESERVED_11_11"              ,        11,     1,      735,    "RAZ",  1,      1,      0,      0},
50820         {"UP_QOS"                      ,        12,     1,      735,    "RAZ",  0,      1,      0ull,   0},
50821         {"RESERVED_13_63"              ,        13,     51,     735,    "RAZ",  1,      1,      0,      0},
50822         {"PKTDRP"                      ,        0,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50823         {"CRCERR"                      ,        1,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50824         {"BCKPRS"                      ,        2,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50825         {"PRTNXA"                      ,        3,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50826         {"BADTAG"                      ,        4,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50827         {"SKPRUNT"                     ,        5,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50828         {"TODOOVR"                     ,        6,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50829         {"FEPERR"                      ,        7,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50830         {"BEPERR"                      ,        8,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50831         {"MINERR"                      ,        9,      1,      736,    "R/W",  0,      0,      0ull,   0ull},
50832         {"MAXERR"                      ,        10,     1,      736,    "R/W",  0,      0,      0ull,   0ull},
50833         {"LENERR"                      ,        11,     1,      736,    "R/W",  0,      0,      0ull,   0ull},
50834         {"PUNYERR"                     ,        12,     1,      736,    "R/W",  0,      0,      0ull,   0ull},
50835         {"RESERVED_13_63"              ,        13,     51,     736,    "RAZ",  1,      1,      0,      0},
50836         {"PKTDRP"                      ,        0,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50837         {"CRCERR"                      ,        1,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50838         {"BCKPRS"                      ,        2,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50839         {"PRTNXA"                      ,        3,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50840         {"BADTAG"                      ,        4,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50841         {"SKPRUNT"                     ,        5,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50842         {"TODOOVR"                     ,        6,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50843         {"FEPERR"                      ,        7,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50844         {"BEPERR"                      ,        8,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50845         {"MINERR"                      ,        9,      1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50846         {"MAXERR"                      ,        10,     1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50847         {"LENERR"                      ,        11,     1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50848         {"PUNYERR"                     ,        12,     1,      737,    "R/W1C",        0,      0,      0ull,   0ull},
50849         {"RESERVED_13_63"              ,        13,     51,     737,    "RAZ",  1,      1,      0,      0},
50850         {"OFFSET"                      ,        0,      3,      738,    "R/W",  0,      0,      0ull,   0ull},
50851         {"RESERVED_3_63"               ,        3,      61,     738,    "RAZ",  1,      1,      0,      0},
50852         {"SKIP"                        ,        0,      7,      739,    "R/W",  0,      0,      0ull,   0ull},
50853         {"RESERVED_7_7"                ,        7,      1,      739,    "RAZ",  1,      1,      0,      0},
50854         {"MODE"                        ,        8,      2,      739,    "R/W",  0,      0,      0ull,   0ull},
50855         {"DSA_EN"                      ,        10,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50856         {"HIGIG_EN"                    ,        11,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50857         {"CRC_EN"                      ,        12,     1,      739,    "RO",   0,      0,      0ull,   0ull},
50858         {"RESERVED_13_15"              ,        13,     3,      739,    "RAZ",  1,      1,      0,      0},
50859         {"QOS_VLAN"                    ,        16,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50860         {"QOS_DIFF"                    ,        17,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50861         {"QOS_VOD"                     ,        18,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50862         {"QOS_VSEL"                    ,        19,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50863         {"QOS_WAT"                     ,        20,     4,      739,    "R/W",  0,      0,      0ull,   0ull},
50864         {"QOS"                         ,        24,     3,      739,    "R/W",  0,      0,      0ull,   0ull},
50865         {"HG_QOS"                      ,        27,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50866         {"GRP_WAT"                     ,        28,     4,      739,    "R/W",  0,      0,      0ull,   0ull},
50867         {"INST_HDR"                    ,        32,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50868         {"DYN_RS"                      ,        33,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50869         {"TAG_INC"                     ,        34,     2,      739,    "R/W",  0,      0,      0ull,   0ull},
50870         {"RAWDRP"                      ,        36,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50871         {"RESERVED_37_39"              ,        37,     3,      739,    "RAZ",  1,      1,      0,      0},
50872         {"QOS_WAT_47"                  ,        40,     4,      739,    "R/W",  0,      0,      0ull,   0ull},
50873         {"GRP_WAT_47"                  ,        44,     4,      739,    "R/W",  0,      0,      0ull,   0ull},
50874         {"MINERR_EN"                   ,        48,     1,      739,    "R/W",  0,      0,      1ull,   1ull},
50875         {"MAXERR_EN"                   ,        49,     1,      739,    "R/W",  0,      0,      1ull,   1ull},
50876         {"LENERR_EN"                   ,        50,     1,      739,    "R/W",  0,      0,      1ull,   1ull},
50877         {"VLAN_LEN"                    ,        51,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50878         {"PAD_LEN"                     ,        52,     1,      739,    "R/W",  0,      0,      0ull,   0ull},
50879         {"RESERVED_53_63"              ,        53,     11,     739,    "RAZ",  1,      1,      0,      0},
50880         {"GRP"                         ,        0,      4,      740,    "R/W",  0,      0,      0ull,   0ull},
50881         {"NON_TAG_TYPE"                ,        4,      2,      740,    "R/W",  0,      0,      0ull,   0ull},
50882         {"IP4_TAG_TYPE"                ,        6,      2,      740,    "R/W",  0,      0,      0ull,   0ull},
50883         {"IP6_TAG_TYPE"                ,        8,      2,      740,    "R/W",  0,      0,      0ull,   0ull},
50884         {"TCP4_TAG_TYPE"               ,        10,     2,      740,    "R/W",  0,      0,      0ull,   0ull},
50885         {"TCP6_TAG_TYPE"               ,        12,     2,      740,    "R/W",  0,      0,      0ull,   0ull},
50886         {"IP4_SRC_FLAG"                ,        14,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50887         {"IP6_SRC_FLAG"                ,        15,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50888         {"IP4_DST_FLAG"                ,        16,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50889         {"IP6_DST_FLAG"                ,        17,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50890         {"IP4_PCTL_FLAG"               ,        18,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50891         {"IP6_NXTH_FLAG"               ,        19,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50892         {"IP4_SPRT_FLAG"               ,        20,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50893         {"IP6_SPRT_FLAG"               ,        21,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50894         {"IP4_DPRT_FLAG"               ,        22,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50895         {"IP6_DPRT_FLAG"               ,        23,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50896         {"INC_PRT_FLAG"                ,        24,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50897         {"INC_VLAN"                    ,        25,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50898         {"INC_VS"                      ,        26,     2,      740,    "R/W",  0,      0,      0ull,   0ull},
50899         {"TAG_MODE"                    ,        28,     2,      740,    "R/W",  0,      0,      0ull,   0ull},
50900         {"GRPTAG_MSKIP"                ,        30,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50901         {"GRPTAG"                      ,        31,     1,      740,    "R/W",  0,      0,      0ull,   0ull},
50902         {"GRPTAGMASK"                  ,        32,     4,      740,    "R/W",  0,      0,      0ull,   0ull},
50903         {"GRPTAGBASE"                  ,        36,     4,      740,    "R/W",  0,      0,      0ull,   0ull},
50904         {"RESERVED_40_63"              ,        40,     24,     740,    "RAZ",  1,      1,      0,      0},
50905         {"QOS"                         ,        0,      3,      741,    "R/W",  0,      0,      0ull,   0ull},
50906         {"RESERVED_3_63"               ,        3,      61,     741,    "RAZ",  1,      1,      0,      0},
50907         {"QOS"                         ,        0,      3,      742,    "R/W",  0,      0,      0ull,   0ull},
50908         {"RESERVED_3_3"                ,        3,      1,      742,    "RAZ",  1,      1,      0,      0},
50909         {"QOS1"                        ,        4,      3,      742,    "R/W",  0,      0,      0ull,   0ull},
50910         {"RESERVED_7_63"               ,        7,      57,     742,    "RAZ",  1,      1,      0,      0},
50911         {"MATCH_VALUE"                 ,        0,      16,     743,    "R/W",  0,      0,      0ull,   0ull},
50912         {"MATCH_TYPE"                  ,        16,     3,      743,    "R/W",  0,      0,      0ull,   0ull},
50913         {"RESERVED_19_19"              ,        19,     1,      743,    "RAZ",  1,      1,      0,      0},
50914         {"QOS"                         ,        20,     3,      743,    "R/W",  0,      0,      0ull,   0ull},
50915         {"RESERVED_23_23"              ,        23,     1,      743,    "RAZ",  1,      1,      0,      0},
50916         {"GRP"                         ,        24,     4,      743,    "R/W",  0,      0,      0ull,   0ull},
50917         {"RESERVED_28_31"              ,        28,     4,      743,    "RAZ",  1,      1,      0,      0},
50918         {"MASK"                        ,        32,     16,     743,    "R/W",  0,      0,      0ull,   0ull},
50919         {"RESERVED_48_63"              ,        48,     16,     743,    "RAZ",  1,      1,      0,      0},
50920         {"WORD"                        ,        0,      56,     744,    "R/W",  0,      0,      0ull,   0ull},
50921         {"RESERVED_56_63"              ,        56,     8,      744,    "RAZ",  1,      1,      0,      0},
50922         {"RST"                         ,        0,      1,      745,    "R/W",  0,      0,      0ull,   0ull},
50923         {"RESERVED_1_63"               ,        1,      63,     745,    "RAZ",  1,      1,      0,      0},
50924         {"DRP_OCTS"                    ,        0,      32,     746,    "R/W",  0,      1,      0ull,   0},
50925         {"DRP_PKTS"                    ,        32,     32,     746,    "R/W",  0,      1,      0ull,   0},
50926         {"OCTS"                        ,        0,      48,     747,    "R/W",  0,      1,      0ull,   0},
50927         {"RESERVED_48_63"              ,        48,     16,     747,    "RAZ",  1,      1,      0,      0},
50928         {"RAW"                         ,        0,      32,     748,    "R/W",  0,      1,      0ull,   0},
50929         {"PKTS"                        ,        32,     32,     748,    "R/W",  0,      1,      0ull,   0},
50930         {"MCST"                        ,        0,      32,     749,    "R/W",  0,      1,      0ull,   0},
50931         {"BCST"                        ,        32,     32,     749,    "R/W",  0,      1,      0ull,   0},
50932         {"H64"                         ,        0,      32,     750,    "R/W",  0,      1,      0ull,   0},
50933         {"H65TO127"                    ,        32,     32,     750,    "R/W",  0,      1,      0ull,   0},
50934         {"H128TO255"                   ,        0,      32,     751,    "R/W",  0,      1,      0ull,   0},
50935         {"H256TO511"                   ,        32,     32,     751,    "R/W",  0,      1,      0ull,   0},
50936         {"H512TO1023"                  ,        0,      32,     752,    "R/W",  0,      1,      0ull,   0},
50937         {"H1024TO1518"                 ,        32,     32,     752,    "R/W",  0,      1,      0ull,   0},
50938         {"H1519"                       ,        0,      32,     753,    "R/W",  0,      1,      0ull,   0},
50939         {"FCS"                         ,        32,     32,     753,    "R/W",  0,      1,      0ull,   0},
50940         {"UNDERSZ"                     ,        0,      32,     754,    "R/W",  0,      1,      0ull,   0},
50941         {"FRAG"                        ,        32,     32,     754,    "R/W",  0,      1,      0ull,   0},
50942         {"OVERSZ"                      ,        0,      32,     755,    "R/W",  0,      1,      0ull,   0},
50943         {"JABBER"                      ,        32,     32,     755,    "R/W",  0,      1,      0ull,   0},
50944         {"RDCLR"                       ,        0,      1,      756,    "R/W",  0,      0,      1ull,   1ull},
50945         {"RESERVED_1_63"               ,        1,      63,     756,    "RAZ",  1,      1,      0,      0},
50946         {"ERRS"                        ,        0,      16,     757,    "R/W",  0,      1,      0ull,   0},
50947         {"RESERVED_16_63"              ,        16,     48,     757,    "RAZ",  1,      1,      0,      0},
50948         {"OCTS"                        ,        0,      48,     758,    "R/W",  0,      1,      0ull,   0},
50949         {"RESERVED_48_63"              ,        48,     16,     758,    "RAZ",  1,      1,      0,      0},
50950         {"PKTS"                        ,        0,      32,     759,    "R/W",  0,      1,      0ull,   0},
50951         {"RESERVED_32_63"              ,        32,     32,     759,    "RAZ",  1,      1,      0,      0},
50952         {"EN"                          ,        0,      8,      760,    "R/W",  0,      0,      0ull,   0ull},
50953         {"RESERVED_8_63"               ,        8,      56,     760,    "RAZ",  1,      1,      0,      0},
50954         {"MASK"                        ,        0,      16,     761,    "R/W",  0,      0,      0ull,   0ull},
50955         {"RESERVED_16_63"              ,        16,     48,     761,    "RAZ",  1,      1,      0,      0},
50956         {"SRC"                         ,        0,      16,     762,    "R/W",  0,      0,      0ull,   0ull},
50957         {"DST"                         ,        16,     16,     762,    "R/W",  0,      0,      0ull,   0ull},
50958         {"RESERVED_32_63"              ,        32,     32,     762,    "RAZ",  1,      1,      0,      0},
50959         {"ENTRY"                       ,        0,      62,     763,    "RO",   1,      1,      0,      0},
50960         {"RESERVED_62_62"              ,        62,     1,      763,    "RAZ",  1,      1,      0,      0},
50961         {"VAL"                         ,        63,     1,      763,    "RO",   1,      1,      0,      0},
50962         {"COUNT"                       ,        0,      32,     764,    "R/W1C",        1,      0,      0,      0ull},
50963         {"RESERVED_32_63"              ,        32,     32,     764,    "RAZ",  1,      1,      0,      0},
50964         {"COUNT"                       ,        0,      48,     765,    "R/W1C",        1,      0,      0,      0ull},
50965         {"RESERVED_48_63"              ,        48,     16,     765,    "RAZ",  1,      1,      0,      0},
50966         {"SIZE"                        ,        0,      16,     766,    "RO",   1,      0,      0,      0ull},
50967         {"SEGS"                        ,        16,     6,      766,    "RO",   1,      0,      0,      0ull},
50968         {"CMD"                         ,        22,     14,     766,    "RO",   1,      0,      0,      0ull},
50969         {"FAU"                         ,        36,     28,     766,    "RO",   1,      0,      0,      0ull},
50970         {"PTR"                         ,        0,      40,     767,    "RO",   1,      0,      0,      0ull},
50971         {"SIZE"                        ,        40,     16,     767,    "RO",   1,      0,      0,      0ull},
50972         {"POOL"                        ,        56,     3,      767,    "RO",   1,      0,      0,      0ull},
50973         {"BACK"                        ,        59,     4,      767,    "RO",   1,      0,      0,      0ull},
50974         {"I"                           ,        63,     1,      767,    "RO",   1,      0,      0,      0ull},
50975         {"PTRS2"                       ,        0,      17,     768,    "RO",   1,      0,      0,      0ull},
50976         {"RESERVED_17_31"              ,        17,     15,     768,    "RAZ",  1,      0,      0,      0ull},
50977         {"PTRS1"                       ,        32,     17,     768,    "RO",   1,      0,      0,      0ull},
50978         {"RESERVED_49_63"              ,        49,     15,     768,    "RAZ",  1,      0,      0,      0ull},
50979         {"MOD"                         ,        0,      3,      769,    "RO",   1,      0,      0,      0ull},
50980         {"CNT"                         ,        3,      13,     769,    "RO",   1,      0,      0,      0ull},
50981         {"CHK"                         ,        16,     1,      769,    "RO",   1,      0,      0,      0ull},
50982         {"LEN"                         ,        17,     1,      769,    "RO",   1,      0,      0,      0ull},
50983         {"SOP"                         ,        18,     1,      769,    "RO",   1,      0,      0,      0ull},
50984         {"UID"                         ,        19,     3,      769,    "RO",   1,      0,      0,      0ull},
50985         {"MAJ"                         ,        22,     1,      769,    "RO",   1,      0,      0,      0ull},
50986         {"RESERVED_23_63"              ,        23,     41,     769,    "RAZ",  1,      0,      0,      0ull},
50987         {"SIZE"                        ,        0,      16,     770,    "RO",   1,      0,      0,      0ull},
50988         {"SEGS"                        ,        16,     6,      770,    "RO",   1,      0,      0,      0ull},
50989         {"CMD"                         ,        22,     14,     770,    "RO",   1,      0,      0,      0ull},
50990         {"FAU"                         ,        36,     28,     770,    "RO",   1,      0,      0,      0ull},
50991         {"PTR"                         ,        0,      40,     771,    "RO",   1,      0,      0,      0ull},
50992         {"SIZE"                        ,        40,     16,     771,    "RO",   1,      0,      0,      0ull},
50993         {"POOL"                        ,        56,     3,      771,    "RO",   1,      0,      0,      0ull},
50994         {"BACK"                        ,        59,     4,      771,    "RO",   1,      0,      0,      0ull},
50995         {"I"                           ,        63,     1,      771,    "RO",   1,      0,      0,      0ull},
50996         {"DATA"                        ,        0,      64,     772,    "RO",   1,      0,      0,      0ull},
50997         {"PTR"                         ,        0,      40,     773,    "RO",   1,      0,      0,      0ull},
50998         {"SIZE"                        ,        40,     16,     773,    "RO",   1,      0,      0,      0ull},
50999         {"POOL"                        ,        56,     3,      773,    "RO",   1,      0,      0,      0ull},
51000         {"BACK"                        ,        59,     4,      773,    "RO",   1,      0,      0,      0ull},
51001         {"I"                           ,        63,     1,      773,    "RO",   1,      0,      0,      0ull},
51002         {"DATA"                        ,        0,      64,     774,    "RO",   1,      0,      0,      0ull},
51003         {"MAJOR"                       ,        0,      3,      775,    "RO",   1,      0,      0,      0ull},
51004         {"MINOR"                       ,        3,      2,      775,    "RO",   1,      0,      0,      0ull},
51005         {"WAIT"                        ,        5,      1,      775,    "RO",   1,      0,      0,      0ull},
51006         {"CHK_MODE"                    ,        6,      1,      775,    "RO",   1,      0,      0,      0ull},
51007         {"CHK_ONCE"                    ,        7,      1,      775,    "RO",   1,      0,      0,      0ull},
51008         {"INIT_DWRITE"                 ,        8,      1,      775,    "RO",   1,      0,      0,      0ull},
51009         {"DREAD_SOP"                   ,        9,      1,      775,    "RO",   1,      0,      0,      0ull},
51010         {"UID"                         ,        10,     2,      775,    "RO",   1,      0,      0,      0ull},
51011         {"CMND_OFF"                    ,        12,     6,      775,    "RO",   1,      0,      0,      0ull},
51012         {"CMND_SIZ"                    ,        18,     16,     775,    "RO",   1,      0,      0,      0ull},
51013         {"CMND_SEGS"                   ,        34,     6,      775,    "RO",   1,      0,      0,      0ull},
51014         {"CURR_OFF"                    ,        40,     16,     775,    "RO",   1,      0,      0,      0ull},
51015         {"CURR_SIZ"                    ,        56,     8,      775,    "RO",   1,      0,      0,      0ull},
51016         {"CURR_SIZ"                    ,        0,      8,      776,    "RO",   1,      0,      0,      0ull},
51017         {"CURR_PTR"                    ,        8,      40,     776,    "RO",   1,      0,      0,      0ull},
51018         {"NXT_INFLT"                   ,        48,     6,      776,    "RO",   1,      0,      0,      0ull},
51019         {"RESERVED_54_63"              ,        54,     10,     776,    "RAZ",  1,      0,      0,      0ull},
51020         {"QID_BASE"                    ,        0,      8,      777,    "RO",   1,      0,      0,      0ull},
51021         {"QID_OFF"                     ,        8,      4,      777,    "RO",   1,      0,      0,      0ull},
51022         {"QID_OFFMAX"                  ,        12,     4,      777,    "RO",   1,      0,      0,      0ull},
51023         {"QCB_RIDX"                    ,        16,     5,      777,    "RO",   1,      0,      0,      0ull},
51024         {"QOS"                         ,        21,     3,      777,    "RO",   1,      0,      0,      0ull},
51025         {"STATC"                       ,        24,     1,      777,    "RO",   1,      0,      0,      0ull},
51026         {"ACTIVE"                      ,        25,     1,      777,    "RO",   1,      0,      0,      0ull},
51027         {"PREEMPTED"                   ,        26,     1,      777,    "RO",   1,      0,      0,      0ull},
51028         {"PREEMPTEE"                   ,        27,     1,      777,    "RO",   1,      0,      0,      0ull},
51029         {"PREEMPTER"                   ,        28,     1,      777,    "RO",   1,      0,      0,      0ull},
51030         {"QID_OFFTHS"                  ,        29,     4,      777,    "RO",   1,      0,      0,      0ull},
51031         {"QID_OFFRES"                  ,        33,     4,      777,    "RO",   1,      0,      0,      0ull},
51032         {"RESERVED_37_63"              ,        37,     27,     777,    "RAZ",  1,      0,      0,      0ull},
51033         {"QCB_RIDX"                    ,        0,      6,      778,    "RO",   1,      0,      0,      0ull},
51034         {"QCB_WIDX"                    ,        6,      6,      778,    "RO",   1,      0,      0,      0ull},
51035         {"BUF_PTR"                     ,        12,     33,     778,    "RO",   1,      0,      0,      0ull},
51036         {"BUF_SIZ"                     ,        45,     13,     778,    "RO",   1,      0,      0,      0ull},
51037         {"TAIL"                        ,        58,     1,      778,    "RO",   1,      0,      0,      0ull},
51038         {"QOS"                         ,        59,     5,      778,    "RO",   1,      0,      0,      0ull},
51039         {"QOS"                         ,        0,      3,      779,    "RO",   1,      0,      0,      0ull},
51040         {"STATIC_Q"                    ,        3,      1,      779,    "RO",   1,      0,      0,      0ull},
51041         {"S_TAIL"                      ,        4,      1,      779,    "RO",   1,      0,      0,      0ull},
51042         {"STATIC_P"                    ,        5,      1,      779,    "RO",   1,      0,      0,      0ull},
51043         {"PREEMPTEE"                   ,        6,      1,      779,    "RO",   1,      0,      0,      0ull},
51044         {"RESERVED_7_7"                ,        7,      1,      779,    "RAZ",  1,      0,      0,      0ull},
51045         {"DOORBELL"                    ,        8,      20,     779,    "RO",   1,      0,      0,      0ull},
51046         {"PREEMPTER"                   ,        28,     1,      779,    "RO",   1,      0,      0,      0ull},
51047         {"RESERVED_29_63"              ,        29,     35,     779,    "RAZ",  1,      0,      0,      0ull},
51048         {"PTRS3"                       ,        0,      17,     780,    "RO",   1,      0,      0,      0ull},
51049         {"RESERVED_17_31"              ,        17,     15,     780,    "RAZ",  1,      0,      0,      0ull},
51050         {"PTRS0"                       ,        32,     17,     780,    "RO",   1,      0,      0,      0ull},
51051         {"RESERVED_49_63"              ,        49,     15,     780,    "RAZ",  1,      0,      0,      0ull},
51052         {"PID"                         ,        0,      6,      781,    "R/W",  1,      0,      0,      0ull},
51053         {"EID"                         ,        6,      4,      781,    "R/W",  1,      0,      0,      0ull},
51054         {"BP_PORT"                     ,        10,     6,      781,    "R/W",  1,      0,      0,      0ull},
51055         {"RESERVED_16_52"              ,        16,     37,     781,    "RAZ",  1,      0,      0,      0ull},
51056         {"QOS_MASK"                    ,        53,     8,      781,    "R/W",  1,      0,      0,      0ull},
51057         {"STATIC_P"                    ,        61,     1,      781,    "R/W",  1,      0,      0,      0ull},
51058         {"RESERVED_62_63"              ,        62,     2,      781,    "RAZ",  1,      0,      0,      0ull},
51059         {"PID"                         ,        0,      6,      782,    "R/W",  1,      0,      0,      0ull},
51060         {"EID"                         ,        6,      4,      782,    "R/W",  1,      0,      0,      0ull},
51061         {"RESERVED_10_52"              ,        10,     43,     782,    "RAZ",  1,      0,      0,      0ull},
51062         {"QOS_MASK"                    ,        53,     8,      782,    "R/W",  1,      0,      0,      0ull},
51063         {"RESERVED_61_63"              ,        61,     3,      782,    "RAZ",  1,      0,      0,      0ull},
51064         {"PID"                         ,        0,      6,      783,    "R/W",  1,      0,      0,      0ull},
51065         {"RESERVED_6_7"                ,        6,      2,      783,    "RAZ",  1,      0,      0,      0ull},
51066         {"RATE_PKT"                    ,        8,      24,     783,    "R/W",  1,      0,      0,      0ull},
51067         {"RATE_WORD"                   ,        32,     19,     783,    "R/W",  1,      0,      0,      0ull},
51068         {"RESERVED_51_63"              ,        51,     13,     783,    "RAZ",  1,      0,      0,      0ull},
51069         {"PID"                         ,        0,      6,      784,    "R/W",  1,      0,      0,      0ull},
51070         {"RESERVED_6_7"                ,        6,      2,      784,    "RAZ",  1,      0,      0,      0ull},
51071         {"RATE_LIM"                    ,        8,      24,     784,    "R/W",  1,      0,      0,      0ull},
51072         {"RESERVED_32_63"              ,        32,     32,     784,    "RAZ",  1,      0,      0,      0ull},
51073         {"QUEUE"                       ,        0,      7,      785,    "R/W",  1,      0,      0,      0ull},
51074         {"PORT"                        ,        7,      6,      785,    "WR0",  1,      0,      0,      0ull},
51075         {"INDEX"                       ,        13,     3,      785,    "WR0",  1,      0,      0,      0ull},
51076         {"TAIL"                        ,        16,     1,      785,    "R/W",  1,      0,      0,      0ull},
51077         {"BUF_PTR"                     ,        17,     36,     785,    "R/W",  1,      0,      0,      0ull},
51078         {"QOS_MASK"                    ,        53,     8,      785,    "R/W",  1,      0,      0,      0ull},
51079         {"STATIC_Q"                    ,        61,     1,      785,    "R/W",  1,      0,      0,      0ull},
51080         {"STATIC_P"                    ,        62,     1,      785,    "R/W",  1,      0,      0,      0ull},
51081         {"S_TAIL"                      ,        63,     1,      785,    "R/W",  1,      0,      0,      0ull},
51082         {"QID"                         ,        0,      7,      786,    "R/W",  1,      0,      0,      0ull},
51083         {"PID"                         ,        7,      6,      786,    "WR0",  1,      0,      0,      0ull},
51084         {"RESERVED_13_52"              ,        13,     40,     786,    "RAZ",  1,      0,      0,      0ull},
51085         {"QOS_MASK"                    ,        53,     8,      786,    "R/W",  1,      0,      0,      0ull},
51086         {"RESERVED_61_63"              ,        61,     3,      786,    "RAZ",  1,      0,      0,      0ull},
51087         {"DAT_PTR"                     ,        0,      4,      787,    "RO",   1,      0,      0,      0ull},
51088         {"DAT_DAT"                     ,        4,      2,      787,    "RO",   1,      0,      0,      0ull},
51089         {"PRT_CTL"                     ,        6,      2,      787,    "RO",   1,      0,      0,      0ull},
51090         {"PRT_QSB"                     ,        8,      3,      787,    "RO",   1,      0,      0,      0ull},
51091         {"PRT_QCB"                     ,        11,     2,      787,    "RO",   1,      0,      0,      0ull},
51092         {"NCB_INB"                     ,        13,     2,      787,    "RO",   1,      0,      0,      0ull},
51093         {"PRT_PSB"                     ,        15,     8,      787,    "RO",   1,      0,      0,      0ull},
51094         {"PRT_NXT"                     ,        23,     1,      787,    "RO",   1,      0,      0,      0ull},
51095         {"PRT_CHK"                     ,        24,     3,      787,    "RO",   1,      0,      0,      0ull},
51096         {"OUT_WIF"                     ,        27,     1,      787,    "RO",   1,      0,      0,      0ull},
51097         {"OUT_STA"                     ,        28,     1,      787,    "RO",   1,      0,      0,      0ull},
51098         {"OUT_CTL"                     ,        29,     3,      787,    "RO",   1,      0,      0,      0ull},
51099         {"OUT_DAT"                     ,        32,     1,      787,    "RO",   1,      0,      0,      0ull},
51100         {"IOB"                         ,        33,     1,      787,    "RO",   1,      0,      0,      0ull},
51101         {"CSR"                         ,        34,     1,      787,    "RO",   1,      0,      0,      0ull},
51102         {"RESERVED_35_63"              ,        35,     29,     787,    "RAZ",  1,      0,      0,      0ull},
51103         {"SIZE"                        ,        0,      13,     788,    "R/W",  0,      0,      0ull,   0ull},
51104         {"RESERVED_13_19"              ,        13,     7,      788,    "RAZ",  0,      0,      0ull,   0ull},
51105         {"POOL"                        ,        20,     3,      788,    "R/W",  0,      0,      0ull,   0ull},
51106         {"RESERVED_23_63"              ,        23,     41,     788,    "RAZ",  1,      0,      0,      0ull},
51107         {"ASSERTS"                     ,        0,      64,     789,    "RO",   0,      0,      0ull,   0ull},
51108         {"ASSERTS"                     ,        0,      64,     790,    "RO",   0,      0,      0ull,   0ull},
51109         {"ASSERTS"                     ,        0,      64,     791,    "RO",   0,      0,      0ull,   0ull},
51110         {"ASSERTS"                     ,        0,      64,     792,    "RO",   0,      0,      0ull,   0ull},
51111         {"ENGINE0"                     ,        0,      4,      793,    "R/W",  0,      0,      4ull,   4ull},
51112         {"ENGINE1"                     ,        4,      4,      793,    "R/W",  0,      0,      4ull,   4ull},
51113         {"ENGINE2"                     ,        8,      4,      793,    "R/W",  0,      0,      4ull,   4ull},
51114         {"ENGINE3"                     ,        12,     4,      793,    "R/W",  0,      0,      4ull,   4ull},
51115         {"ENGINE4"                     ,        16,     4,      793,    "R/W",  0,      0,      4ull,   4ull},
51116         {"ENGINE5"                     ,        20,     4,      793,    "R/W",  0,      0,      4ull,   4ull},
51117         {"ENGINE6"                     ,        24,     4,      793,    "R/W",  0,      0,      4ull,   4ull},
51118         {"ENGINE7"                     ,        28,     4,      793,    "R/W",  0,      0,      4ull,   4ull},
51119         {"ENGINE8"                     ,        32,     4,      793,    "R/W",  0,      0,      4ull,   4ull},
51120         {"ENGINE9"                     ,        36,     4,      793,    "R/W",  0,      0,      4ull,   4ull},
51121         {"RESERVED_40_63"              ,        40,     24,     793,    "RAZ",  1,      0,      0,      0ull},
51122         {"MASK"                        ,        0,      10,     794,    "R/W",  0,      0,      0ull,   0ull},
51123         {"RESERVED_10_63"              ,        10,     54,     794,    "RAZ",  1,      0,      0,      0ull},
51124         {"PARITY"                      ,        0,      1,      795,    "R/W1C",        0,      0,      0ull,   0ull},
51125         {"DOORBELL"                    ,        1,      1,      795,    "R/W1C",        0,      0,      0ull,   0ull},
51126         {"CURRZERO"                    ,        2,      1,      795,    "R/W1C",        0,      0,      0ull,   0ull},
51127         {"RESERVED_3_63"               ,        3,      61,     795,    "RAZ",  1,      0,      0,      0ull},
51128         {"ENA_PKO"                     ,        0,      1,      796,    "R/W",  0,      0,      0ull,   0ull},
51129         {"ENA_DWB"                     ,        1,      1,      796,    "R/W",  0,      0,      0ull,   0ull},
51130         {"STORE_BE"                    ,        2,      1,      796,    "R/W",  0,      0,      0ull,   0ull},
51131         {"RESET"                       ,        3,      1,      796,    "RAZ",  0,      0,      0ull,   0ull},
51132         {"RESERVED_4_63"               ,        4,      60,     796,    "RAZ",  1,      0,      0,      0ull},
51133         {"MODE0"                       ,        0,      3,      797,    "R/W",  0,      0,      2ull,   2ull},
51134         {"MODE1"                       ,        3,      3,      797,    "R/W",  0,      0,      2ull,   2ull},
51135         {"RESERVED_6_63"               ,        6,      58,     797,    "RAZ",  1,      0,      0,      0ull},
51136         {"PARITY"                      ,        0,      1,      798,    "R/W",  0,      0,      0ull,   0ull},
51137         {"DOORBELL"                    ,        1,      1,      798,    "R/W",  0,      0,      0ull,   0ull},
51138         {"CURRZERO"                    ,        2,      1,      798,    "R/W",  0,      0,      0ull,   0ull},
51139         {"RESERVED_3_63"               ,        3,      61,     798,    "RAZ",  1,      0,      0,      0ull},
51140         {"MODE"                        ,        0,      2,      799,    "R/W",  0,      0,      0ull,   0ull},
51141         {"RESERVED_2_63"               ,        2,      62,     799,    "RAZ",  1,      0,      0,      0ull},
51142         {"QID7"                        ,        0,      1,      800,    "R/W",  0,      0,      0ull,   0ull},
51143         {"IDX3"                        ,        1,      1,      800,    "R/W",  0,      0,      0ull,   0ull},
51144         {"RESERVED_2_63"               ,        2,      62,     800,    "RAZ",  1,      0,      0,      0ull},
51145         {"INDEX"                       ,        0,      8,      801,    "R/W",  0,      0,      0ull,   0ull},
51146         {"INC"                         ,        8,      8,      801,    "R/W",  0,      0,      0ull,   0ull},
51147         {"RESERVED_16_63"              ,        16,     48,     801,    "RAZ",  1,      0,      0,      0ull},
51148         {"ADR0"                        ,        0,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51149         {"ADR1"                        ,        1,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51150         {"PEND0"                       ,        2,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51151         {"PEND1"                       ,        3,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51152         {"NBR0"                        ,        4,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51153         {"NBR1"                        ,        5,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51154         {"FIDX"                        ,        6,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51155         {"INDEX"                       ,        7,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51156         {"NBT"                         ,        8,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51157         {"CAM"                         ,        9,      1,      802,    "RO",   0,      0,      0ull,   0ull},
51158         {"RESERVED_10_15"              ,        10,     6,      802,    "RAZ",  1,      1,      0,      0},
51159         {"PP"                          ,        16,     12,     802,    "RO",   0,      0,      0ull,   0ull},
51160         {"RESERVED_28_63"              ,        28,     36,     802,    "RAZ",  1,      1,      0,      0},
51161         {"DS_PC"                       ,        0,      32,     803,    "R/W1C",        0,      1,      0ull,   0},
51162         {"RESERVED_32_63"              ,        32,     32,     803,    "RAZ",  1,      1,      0,      0},
51163         {"SBE"                         ,        0,      1,      804,    "R/W1C",        0,      0,      0ull,   0ull},
51164         {"DBE"                         ,        1,      1,      804,    "R/W1C",        0,      0,      0ull,   0ull},
51165         {"SBE_IE"                      ,        2,      1,      804,    "R/W",  0,      1,      0ull,   0},
51166         {"DBE_IE"                      ,        3,      1,      804,    "R/W",  0,      1,      0ull,   0},
51167         {"SYN"                         ,        4,      5,      804,    "RO",   1,      1,      0,      0},
51168         {"RESERVED_9_11"               ,        9,      3,      804,    "RAZ",  1,      1,      0,      0},
51169         {"RPE"                         ,        12,     1,      804,    "R/W1C",        0,      0,      0ull,   0ull},
51170         {"RPE_IE"                      ,        13,     1,      804,    "R/W",  0,      1,      0ull,   0},
51171         {"RESERVED_14_15"              ,        14,     2,      804,    "RAZ",  1,      1,      0,      0},
51172         {"IOP"                         ,        16,     13,     804,    "R/W1C",        0,      0,      0ull,   0ull},
51173         {"RESERVED_29_31"              ,        29,     3,      804,    "RAZ",  1,      1,      0,      0},
51174         {"IOP_IE"                      ,        32,     13,     804,    "R/W",  0,      1,      0ull,   0},
51175         {"RESERVED_45_63"              ,        45,     19,     804,    "RAZ",  1,      1,      0,      0},
51176         {"NBR_THR"                     ,        0,      5,      805,    "R/W",  0,      0,      2ull,   2ull},
51177         {"PFR_DIS"                     ,        5,      1,      805,    "R/W",  0,      0,      0ull,   0ull},
51178         {"RESERVED_6_63"               ,        6,      58,     805,    "RAZ",  1,      1,      0,      0},
51179         {"IQ_CNT"                      ,        0,      32,     806,    "RO",   0,      1,      0ull,   0},
51180         {"RESERVED_32_63"              ,        32,     32,     806,    "RAZ",  1,      1,      0,      0},
51181         {"IQ_CNT"                      ,        0,      32,     807,    "RO",   0,      1,      0ull,   0},
51182         {"RESERVED_32_63"              ,        32,     32,     807,    "RAZ",  1,      1,      0,      0},
51183         {"IQ_INT"                      ,        0,      8,      808,    "R/W1C",        0,      1,      0ull,   0},
51184         {"RESERVED_8_63"               ,        8,      56,     808,    "RAZ",  1,      1,      0,      0},
51185         {"INT_EN"                      ,        0,      8,      809,    "R/W",  0,      1,      0ull,   0},
51186         {"RESERVED_8_63"               ,        8,      56,     809,    "RAZ",  1,      1,      0,      0},
51187         {"IQ_THR"                      ,        0,      32,     810,    "R/W",  0,      1,      4294967295ull,  0},
51188         {"RESERVED_32_63"              ,        32,     32,     810,    "RAZ",  1,      1,      0,      0},
51189         {"NOS_CNT"                     ,        0,      12,     811,    "RO",   0,      1,      0ull,   0},
51190         {"RESERVED_12_63"              ,        12,     52,     811,    "RAZ",  1,      1,      0,      0},
51191         {"NW_TIM"                      ,        0,      10,     812,    "R/W",  0,      0,      0ull,   1023ull},
51192         {"RESERVED_10_63"              ,        10,     54,     812,    "RAZ",  1,      1,      0,      0},
51193         {"RST_MSK"                     ,        0,      8,      813,    "R/W",  0,      1,      0ull,   0},
51194         {"RESERVED_8_63"               ,        8,      56,     813,    "RAZ",  1,      1,      0,      0},
51195         {"GRP_MSK"                     ,        0,      16,     814,    "R/W",  0,      0,      65535ull,       65535ull},
51196         {"QOS0_PRI"                    ,        16,     4,      814,    "R/W",  0,      1,      0ull,   0},
51197         {"QOS1_PRI"                    ,        20,     4,      814,    "R/W",  0,      1,      0ull,   0},
51198         {"QOS2_PRI"                    ,        24,     4,      814,    "R/W",  0,      1,      0ull,   0},
51199         {"QOS3_PRI"                    ,        28,     4,      814,    "R/W",  0,      1,      0ull,   0},
51200         {"QOS4_PRI"                    ,        32,     4,      814,    "R/W",  0,      1,      0ull,   0},
51201         {"QOS5_PRI"                    ,        36,     4,      814,    "R/W",  0,      1,      0ull,   0},
51202         {"QOS6_PRI"                    ,        40,     4,      814,    "R/W",  0,      1,      0ull,   0},
51203         {"QOS7_PRI"                    ,        44,     4,      814,    "R/W",  0,      1,      0ull,   0},
51204         {"RESERVED_48_63"              ,        48,     16,     814,    "RAZ",  1,      1,      0,      0},
51205         {"RND"                         ,        0,      8,      815,    "R/W",  0,      1,      255ull, 0},
51206         {"RND_P1"                      ,        8,      8,      815,    "R/W",  0,      1,      255ull, 0},
51207         {"RND_P2"                      ,        16,     8,      815,    "R/W",  0,      1,      255ull, 0},
51208         {"RND_P3"                      ,        24,     8,      815,    "R/W",  0,      1,      255ull, 0},
51209         {"RESERVED_32_63"              ,        32,     32,     815,    "RAZ",  1,      1,      0,      0},
51210         {"MIN_THR"                     ,        0,      11,     816,    "R/W",  0,      1,      0ull,   0},
51211         {"RESERVED_11_11"              ,        11,     1,      816,    "RAZ",  1,      1,      0,      0},
51212         {"MAX_THR"                     ,        12,     11,     816,    "R/W",  0,      1,      2047ull,        0},
51213         {"RESERVED_23_23"              ,        23,     1,      816,    "RAZ",  1,      1,      0,      0},
51214         {"FREE_CNT"                    ,        24,     12,     816,    "RO",   0,      1,      2027ull,        0},
51215         {"BUF_CNT"                     ,        36,     12,     816,    "RO",   0,      1,      0ull,   0},
51216         {"DES_CNT"                     ,        48,     12,     816,    "RO",   0,      1,      0ull,   0},
51217         {"RESERVED_60_63"              ,        60,     4,      816,    "RAZ",  1,      1,      0,      0},
51218         {"TS_PC"                       ,        0,      32,     817,    "R/W1C",        0,      1,      0ull,   0},
51219         {"RESERVED_32_63"              ,        32,     32,     817,    "RAZ",  1,      1,      0,      0},
51220         {"WA_PC"                       ,        0,      32,     818,    "R/W1C",        0,      1,      0ull,   0},
51221         {"RESERVED_32_63"              ,        32,     32,     818,    "RAZ",  1,      1,      0,      0},
51222         {"WA_PC"                       ,        0,      32,     819,    "R/W1C",        0,      1,      0ull,   0},
51223         {"RESERVED_32_63"              ,        32,     32,     819,    "RAZ",  1,      1,      0,      0},
51224         {"WQ_INT"                      ,        0,      16,     820,    "R/W1C",        0,      1,      0ull,   0},
51225         {"IQ_DIS"                      ,        16,     16,     820,    "R/W1", 0,      1,      0ull,   0},
51226         {"RESERVED_32_63"              ,        32,     32,     820,    "RAZ",  1,      1,      0,      0},
51227         {"IQ_CNT"                      ,        0,      12,     821,    "RO",   0,      1,      0ull,   0},
51228         {"DS_CNT"                      ,        12,     12,     821,    "RO",   0,      1,      0ull,   0},
51229         {"TC_CNT"                      ,        24,     4,      821,    "RO",   0,      1,      0ull,   0},
51230         {"RESERVED_28_63"              ,        28,     36,     821,    "RAZ",  1,      1,      0,      0},
51231         {"RESERVED_0_7"                ,        0,      8,      822,    "RAZ",  1,      1,      0,      0},
51232         {"PC_THR"                      ,        8,      20,     822,    "R/W",  0,      1,      0ull,   0},
51233         {"RESERVED_28_31"              ,        28,     4,      822,    "RAZ",  1,      1,      0,      0},
51234         {"PC"                          ,        32,     28,     822,    "RO",   0,      1,      0ull,   0},
51235         {"RESERVED_60_63"              ,        60,     4,      822,    "RAZ",  1,      1,      0,      0},
51236         {"IQ_THR"                      ,        0,      11,     823,    "R/W",  0,      1,      0ull,   0},
51237         {"RESERVED_11_11"              ,        11,     1,      823,    "RAZ",  1,      1,      0,      0},
51238         {"DS_THR"                      ,        12,     11,     823,    "R/W",  0,      1,      0ull,   0},
51239         {"RESERVED_23_23"              ,        23,     1,      823,    "RAZ",  1,      1,      0,      0},
51240         {"TC_THR"                      ,        24,     4,      823,    "R/W",  0,      1,      0ull,   0},
51241         {"TC_EN"                       ,        28,     1,      823,    "R/W",  0,      1,      0ull,   0},
51242         {"RESERVED_29_63"              ,        29,     35,     823,    "RAZ",  1,      1,      0,      0},
51243         {"WS_PC"                       ,        0,      32,     824,    "R/W1C",        0,      1,      0ull,   0},
51244         {"RESERVED_32_63"              ,        32,     32,     824,    "RAZ",  1,      1,      0,      0},
51245         {"IWORD"                       ,        0,      64,     825,    "RO",   1,      1,      0,      0},
51246         {"P_DAT"                       ,        0,      64,     826,    "RO",   1,      1,      0,      0},
51247         {"Q_DAT"                       ,        0,      64,     827,    "RO",   1,      1,      0,      0},
51248         {"DAT"                         ,        0,      2,      828,    "RO",   1,      0,      0,      0ull},
51249         {"NCB_INB"                     ,        2,      2,      828,    "RO",   1,      0,      0,      0ull},
51250         {"NCB_OUB"                     ,        4,      1,      828,    "RO",   1,      0,      0,      0ull},
51251         {"STA"                         ,        5,      1,      828,    "RO",   1,      0,      0,      0ull},
51252         {"RESERVED_6_63"               ,        6,      58,     828,    "RAZ",  0,      0,      0ull,   0ull},
51253         {"PTR"                         ,        0,      33,     829,    "R/W",  0,      1,      0ull,   0},
51254         {"SIZE"                        ,        33,     13,     829,    "R/W",  0,      1,      0ull,   0},
51255         {"POOL"                        ,        46,     3,      829,    "R/W",  0,      1,      0ull,   0},
51256         {"DWB"                         ,        49,     9,      829,    "R/W",  0,      1,      0ull,   0},
51257         {"RESERVED_58_63"              ,        58,     6,      829,    "RAZ",  0,      0,      0ull,   0ull},
51258         {"RESET"                       ,        0,      1,      830,    "RAZ",  0,      0,      0ull,   0ull},
51259         {"STORE_LE"                    ,        1,      1,      830,    "R/W",  0,      0,      0ull,   0ull},
51260         {"MAX_READ"                    ,        2,      4,      830,    "R/W",  0,      0,      8ull,   8ull},
51261         {"RESERVED_6_63"               ,        6,      58,     830,    "RAZ",  0,      0,      0ull,   0ull},
51262         {"STATE"                       ,        0,      5,      831,    "RO",   1,      1,      0,      0},
51263         {"COMMIT"                      ,        5,      1,      831,    "RO",   1,      1,      0,      0},
51264         {"OWORDPV"                     ,        6,      1,      831,    "RO",   1,      1,      0,      0},
51265         {"OWORDQV"                     ,        7,      1,      831,    "RO",   1,      1,      0,      0},
51266         {"IWIDX"                       ,        8,      6,      831,    "RO",   1,      1,      0,      0},
51267         {"RESERVED_14_15"              ,        14,     2,      831,    "RAZ",  1,      1,      0,      0},
51268         {"IRIDX"                       ,        16,     6,      831,    "RO",   1,      1,      0,      0},
51269         {"RESERVED_22_31"              ,        22,     10,     831,    "RAZ",  1,      1,      0,      0},
51270         {"LOOP"                        ,        32,     25,     831,    "RO",   1,      1,      0,      0},
51271         {"RESERVED_57_63"              ,        57,     7,      831,    "RAZ",  1,      1,      0,      0},
51272         {"CWORD"                       ,        0,      64,     832,    "RO",   1,      1,      0,      0},
51273         {"PTR"                         ,        0,      40,     833,    "RO",   1,      1,      0,      0},
51274         {"SIZE"                        ,        40,     16,     833,    "RO",   1,      1,      0,      0},
51275         {"FLAGS"                       ,        56,     8,      833,    "RO",   1,      1,      0,      0},
51276         {"INDEX"                       ,        0,      8,      834,    "RO",   1,      1,      0,      0},
51277         {"SOD"                         ,        8,      1,      834,    "RO",   1,      1,      0,      0},
51278         {"EOD"                         ,        9,      1,      834,    "RO",   1,      1,      0,      0},
51279         {"WC"                          ,        10,     1,      834,    "RO",   1,      1,      0,      0},
51280         {"P"                           ,        11,     1,      834,    "RO",   1,      1,      0,      0},
51281         {"Q"                           ,        12,     1,      834,    "RO",   1,      1,      0,      0},
51282         {"RESERVED_13_63"              ,        13,     51,     834,    "RAZ",  0,      0,      0ull,   0ull},
51283         {"ASSERTS"                     ,        0,      15,     835,    "RO",   1,      1,      0,      0},
51284         {"RESERVED_15_63"              ,        15,     49,     835,    "RAZ",  0,      0,      0ull,   0ull},
51285         {"OWORDP"                      ,        0,      64,     836,    "RO",   1,      1,      0,      0},
51286         {"OWORDQ"                      ,        0,      64,     837,    "RO",   1,      1,      0,      0},
51287         {"RWORD"                       ,        0,      64,     838,    "RO",   1,      1,      0,      0},
51288         {"N0CREDS"                     ,        0,      4,      839,    "RO",   0,      0,      8ull,   0ull},
51289         {"N1CREDS"                     ,        4,      4,      839,    "RO",   0,      0,      8ull,   0ull},
51290         {"POWCREDS"                    ,        8,      2,      839,    "RO",   0,      0,      2ull,   0ull},
51291         {"RESERVED_10_11"              ,        10,     2,      839,    "RAZ",  0,      0,      0ull,   0ull},
51292         {"FPACREDS"                    ,        12,     2,      839,    "RO",   0,      0,      1ull,   0ull},
51293         {"WCCREDS"                     ,        14,     2,      839,    "RO",   0,      0,      0ull,   0ull},
51294         {"NIWIDX0"                     ,        16,     4,      839,    "RO",   1,      1,      0,      0},
51295         {"NIRIDX0"                     ,        20,     4,      839,    "RO",   1,      1,      0,      0},
51296         {"NIWIDX1"                     ,        24,     4,      839,    "RO",   1,      1,      0,      0},
51297         {"NIRIDX1"                     ,        28,     4,      839,    "RO",   1,      1,      0,      0},
51298         {"NIRVAL6"                     ,        32,     5,      839,    "RO",   1,      1,      0,      0},
51299         {"NIRARB6"                     ,        37,     1,      839,    "RO",   1,      1,      0,      0},
51300         {"NIRQUE6"                     ,        38,     2,      839,    "RO",   1,      1,      0,      0},
51301         {"NIROPC6"                     ,        40,     3,      839,    "RO",   1,      1,      0,      0},
51302         {"NIRVAL7"                     ,        43,     5,      839,    "RO",   1,      1,      0,      0},
51303         {"NIRQUE7"                     ,        48,     2,      839,    "RO",   1,      1,      0,      0},
51304         {"NIROPC7"                     ,        50,     3,      839,    "RO",   1,      1,      0,      0},
51305         {"RESERVED_53_63"              ,        53,     11,     839,    "RAZ",  0,      0,      0ull,   0ull},
51306         {"PTR"                         ,        0,      40,     840,    "RO",   1,      1,      0,      0},
51307         {"SIZE"                        ,        40,     16,     840,    "RO",   1,      1,      0,      0},
51308         {"CNT"                         ,        56,     8,      840,    "RO",   1,      1,      0,      0},
51309         {"CNT"                         ,        0,      15,     841,    "RO",   1,      1,      0,      0},
51310         {"RESERVED_15_63"              ,        15,     49,     841,    "RAZ",  0,      0,      0ull,   0ull},
51311         {"PTR"                         ,        0,      40,     842,    "RO",   1,      1,      0,      0},
51312         {"SIZE"                        ,        40,     16,     842,    "RO",   1,      1,      0,      0},
51313         {"FLAGS"                       ,        56,     8,      842,    "RO",   1,      1,      0,      0},
51314         {"INDEX"                       ,        0,      8,      843,    "RO",   1,      1,      0,      0},
51315         {"MUL"                         ,        8,      8,      843,    "RO",   1,      1,      0,      0},
51316         {"P"                           ,        16,     1,      843,    "RO",   1,      1,      0,      0},
51317         {"Q"                           ,        17,     1,      843,    "RO",   1,      1,      0,      0},
51318         {"INI"                         ,        18,     1,      843,    "RO",   1,      1,      0,      0},
51319         {"EOD"                         ,        19,     1,      843,    "RO",   1,      1,      0,      0},
51320         {"RESERVED_20_63"              ,        20,     44,     843,    "RAZ",  0,      0,      0ull,   0ull},
51321         {"DOORBELL"                    ,        0,      1,      844,    "R/W1C",        0,      0,      0ull,   0ull},
51322         {"RESERVED_1_63"               ,        1,      63,     844,    "RAZ",  0,      0,      0ull,   0ull},
51323         {"DOORBELL"                    ,        0,      1,      845,    "R/W",  0,      0,      0ull,   0ull},
51324         {"RESERVED_1_63"               ,        1,      63,     845,    "RAZ",  0,      0,      0ull,   0ull},
51325         {"COEFFS"                      ,        0,      8,      846,    "R/W",  0,      0,      29ull,  29ull},
51326         {"RESERVED_8_63"               ,        8,      56,     846,    "RAZ",  0,      0,      0ull,   0ull},
51327         {"INDEX"                       ,        0,      16,     847,    "R/W",  0,      0,      0ull,   0ull},
51328         {"INC"                         ,        16,     16,     847,    "R/W",  0,      0,      0ull,   0ull},
51329         {"RESERVED_32_63"              ,        32,     32,     847,    "RAZ",  0,      0,      0ull,   0ull},
51330         {"MEM"                         ,        0,      1,      848,    "RO",   0,      0,      0ull,   0ull},
51331         {"RRC"                         ,        1,      1,      848,    "RO",   0,      0,      0ull,   0ull},
51332         {"RESERVED_2_63"               ,        2,      62,     848,    "RAZ",  1,      1,      0,      0},
51333         {"ENT_EN"                      ,        0,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
51334         {"RNG_EN"                      ,        1,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
51335         {"RNM_RST"                     ,        2,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
51336         {"RNG_RST"                     ,        3,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
51337         {"EXP_ENT"                     ,        4,      1,      849,    "R/W",  0,      0,      0ull,   0ull},
51338         {"ENT_SEL"                     ,        5,      4,      849,    "R/W",  0,      0,      0ull,   0ull},
51339         {"RESERVED_9_63"               ,        9,      55,     849,    "RAZ",  1,      1,      0,      0},
51340         {"PHASE"                       ,        0,      8,      850,    "R/W",  0,      0,      100ull, 100ull},
51341         {"SAMPLE"                      ,        8,      4,      850,    "R/W",  0,      0,      2ull,   2ull},
51342         {"PREAMBLE"                    ,        12,     1,      850,    "R/W",  0,      0,      1ull,   1ull},
51343         {"CLK_IDLE"                    ,        13,     1,      850,    "R/W",  0,      0,      0ull,   0ull},
51344         {"RESERVED_14_14"              ,        14,     1,      850,    "RAZ",  1,      1,      0,      0},
51345         {"SAMPLE_MODE"                 ,        15,     1,      850,    "R/W",  0,      0,      0ull,   0ull},
51346         {"SAMPLE_HI"                   ,        16,     5,      850,    "R/W",  0,      0,      0ull,   0ull},
51347         {"RESERVED_21_23"              ,        21,     3,      850,    "RAZ",  1,      1,      0,      0},
51348         {"MODE"                        ,        24,     1,      850,    "R/W",  0,      0,      0ull,   0ull},
51349         {"RESERVED_25_63"              ,        25,     39,     850,    "RAZ",  1,      1,      0,      0},
51350         {"REG_ADR"                     ,        0,      5,      851,    "R/W",  0,      1,      0ull,   0},
51351         {"RESERVED_5_7"                ,        5,      3,      851,    "RAZ",  1,      1,      0,      0},
51352         {"PHY_ADR"                     ,        8,      5,      851,    "R/W",  0,      1,      0ull,   0},
51353         {"RESERVED_13_15"              ,        13,     3,      851,    "RAZ",  1,      1,      0,      0},
51354         {"PHY_OP"                      ,        16,     2,      851,    "R/W",  0,      1,      0ull,   0},
51355         {"RESERVED_18_63"              ,        18,     46,     851,    "RAZ",  1,      1,      0,      0},
51356         {"EN"                          ,        0,      1,      852,    "R/W",  0,      0,      0ull,   1ull},
51357         {"RESERVED_1_63"               ,        1,      63,     852,    "RAZ",  1,      1,      0,      0},
51358         {"DAT"                         ,        0,      16,     853,    "RO",   0,      1,      0ull,   0},
51359         {"VAL"                         ,        16,     1,      853,    "RO",   0,      1,      0ull,   0},
51360         {"PENDING"                     ,        17,     1,      853,    "RO",   0,      1,      0ull,   0},
51361         {"RESERVED_18_63"              ,        18,     46,     853,    "RAZ",  1,      1,      0,      0},
51362         {"DAT"                         ,        0,      16,     854,    "R/W",  0,      1,      0ull,   0},
51363         {"VAL"                         ,        16,     1,      854,    "RO",   0,      1,      0ull,   0},
51364         {"PENDING"                     ,        17,     1,      854,    "RO",   0,      1,      0ull,   0},
51365         {"RESERVED_18_63"              ,        18,     46,     854,    "RAZ",  1,      1,      0,      0},
51366         {"INTERVAL"                    ,        0,      22,     855,    "RO",   1,      0,      0,      0ull},
51367         {"RESERVED_22_23"              ,        22,     2,      855,    "RAZ",  1,      0,      0,      0ull},
51368         {"COUNT"                       ,        24,     22,     855,    "RO",   1,      0,      0,      0ull},
51369         {"RESERVED_46_46"              ,        46,     1,      855,    "RAZ",  1,      0,      0,      0ull},
51370         {"ENA"                         ,        47,     1,      855,    "RO",   1,      0,      0,      0ull},
51371         {"RESERVED_48_63"              ,        48,     16,     855,    "RAZ",  1,      0,      0,      0ull},
51372         {"BSIZE"                       ,        0,      20,     856,    "RO",   1,      0,      0,      0ull},
51373         {"BASE"                        ,        20,     31,     856,    "RO",   1,      0,      0,      0ull},
51374         {"BUCKET"                      ,        51,     13,     856,    "RO",   1,      0,      0,      0ull},
51375         {"BUCKET"                      ,        0,      7,      857,    "RO",   1,      0,      0,      0ull},
51376         {"RESERVED_7_7"                ,        7,      1,      857,    "RAZ",  1,      0,      0,      0ull},
51377         {"CSIZE"                       ,        8,      13,     857,    "RO",   1,      0,      0,      0ull},
51378         {"CPOOL"                       ,        21,     3,      857,    "RO",   1,      0,      0,      0ull},
51379         {"RESERVED_24_63"              ,        24,     40,     857,    "RAZ",  1,      0,      0,      0ull},
51380         {"RING"                        ,        0,      4,      858,    "R/W",  0,      0,      0ull,   0ull},
51381         {"NUM_BUCKETS"                 ,        4,      20,     858,    "R/W",  0,      0,      0ull,   0ull},
51382         {"FIRST_BUCKET"                ,        24,     31,     858,    "R/W",  0,      0,      0ull,   0ull},
51383         {"RESERVED_55_63"              ,        55,     9,      858,    "RAZ",  1,      0,      0,      0ull},
51384         {"RING"                        ,        0,      4,      859,    "R/W",  0,      0,      0ull,   0ull},
51385         {"INTERVAL"                    ,        4,      22,     859,    "R/W",  0,      0,      0ull,   0ull},
51386         {"WORDS_PER_CHUNK"             ,        26,     13,     859,    "R/W",  0,      0,      0ull,   0ull},
51387         {"POOL"                        ,        39,     3,      859,    "R/W",  0,      0,      0ull,   0ull},
51388         {"ENABLE"                      ,        42,     1,      859,    "R/W",  0,      0,      0ull,   0ull},
51389         {"RESERVED_43_63"              ,        43,     21,     859,    "RAZ",  1,      0,      0,      0ull},
51390         {"CTL"                         ,        0,      1,      860,    "RO",   1,      0,      0,      0ull},
51391         {"NCB"                         ,        1,      1,      860,    "RO",   1,      0,      0,      0ull},
51392         {"STA"                         ,        2,      2,      860,    "RO",   1,      0,      0,      0ull},
51393         {"RESERVED_4_63"               ,        4,      60,     860,    "RAZ",  1,      0,      0,      0ull},
51394         {"MASK"                        ,        0,      16,     861,    "R/W1C",        0,      0,      0ull,   0ull},
51395         {"RESERVED_16_63"              ,        16,     48,     861,    "RAZ",  1,      0,      0,      0ull},
51396         {"ENABLE_TIMERS"               ,        0,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
51397         {"ENABLE_DWB"                  ,        1,      1,      862,    "R/W",  0,      0,      0ull,   0ull},
51398         {"RESET"                       ,        2,      1,      862,    "RAZ",  0,      0,      0ull,   0ull},
51399         {"RESERVED_3_63"               ,        3,      61,     862,    "RAZ",  1,      0,      0,      0ull},
51400         {"MASK"                        ,        0,      16,     863,    "R/W",  0,      0,      0ull,   0ull},
51401         {"RESERVED_16_63"              ,        16,     48,     863,    "RAZ",  1,      0,      0,      0ull},
51402         {"INDEX"                       ,        0,      8,      864,    "R/W",  0,      0,      0ull,   0ull},
51403         {"INC"                         ,        8,      8,      864,    "R/W",  0,      0,      0ull,   0ull},
51404         {"RESERVED_16_63"              ,        16,     48,     864,    "RAZ",  1,      0,      0,      0ull},
51405         {"TDF0"                        ,        0,      1,      865,    "RO",   0,      0,      0ull,   0ull},
51406         {"TDF1"                        ,        1,      1,      865,    "RO",   0,      0,      0ull,   0ull},
51407         {"TCF"                         ,        2,      1,      865,    "RO",   0,      0,      0ull,   0ull},
51408         {"RESERVED_3_63"               ,        3,      61,     865,    "RAZ",  0,      0,      0ull,   0ull},
51409         {"ENA"                         ,        0,      1,      866,    "R/W",  0,      0,      0ull,   0ull},
51410         {"WRAP"                        ,        1,      1,      866,    "R/W",  0,      0,      0ull,   0ull},
51411         {"TRIG_CTL"                    ,        2,      2,      866,    "R/W",  0,      0,      0ull,   0ull},
51412         {"TIME_GRN"                    ,        4,      3,      866,    "R/W",  0,      0,      0ull,   0ull},
51413         {"FULL_THR"                    ,        7,      2,      866,    "R/W",  0,      0,      0ull,   0ull},
51414         {"CIU_TRG"                     ,        9,      1,      866,    "R/W",  0,      0,      0ull,   0ull},
51415         {"CIU_THR"                     ,        10,     1,      866,    "R/W",  0,      0,      0ull,   0ull},
51416         {"MCD0_TRG"                    ,        11,     1,      866,    "R/W",  0,      0,      0ull,   0ull},
51417         {"MCD0_THR"                    ,        12,     1,      866,    "R/W",  0,      0,      0ull,   0ull},
51418         {"MCD0_ENA"                    ,        13,     1,      866,    "R/W",  0,      0,      0ull,   0ull},
51419         {"IGNORE_O"                    ,        14,     1,      866,    "R/W",  0,      0,      0ull,   0ull},
51420         {"RESERVED_15_63"              ,        15,     49,     866,    "RAZ",  0,      0,      0ull,   0ull},
51421         {"WPTR"                        ,        0,      8,      867,    "RO",   0,      0,      0ull,   0ull},
51422         {"RPTR"                        ,        8,      8,      867,    "RO",   0,      0,      0ull,   0ull},
51423         {"CYCLES"                      ,        16,     48,     867,    "RO",   0,      0,      0ull,   0ull},
51424         {"WPTR"                        ,        0,      10,     868,    "RO",   0,      0,      0ull,   0ull},
51425         {"RESERVED_10_11"              ,        10,     2,      868,    "RAZ",  0,      0,      0ull,   0ull},
51426         {"RPTR"                        ,        12,     10,     868,    "RO",   0,      0,      0ull,   0ull},
51427         {"RESERVED_22_23"              ,        22,     2,      868,    "RAZ",  0,      0,      0ull,   0ull},
51428         {"CYCLES"                      ,        24,     40,     868,    "RO",   0,      0,      0ull,   0ull},
51429         {"ADR"                         ,        0,      36,     869,    "R/W",  0,      1,      0ull,   0},
51430         {"RESERVED_36_63"              ,        36,     28,     869,    "RAZ",  0,      0,      0ull,   0ull},
51431         {"ADR"                         ,        0,      36,     870,    "R/W",  0,      0,      0ull,   0ull},
51432         {"RESERVED_36_63"              ,        36,     28,     870,    "RAZ",  0,      0,      0ull,   0ull},
51433         {"DWB"                         ,        0,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51434         {"PL2"                         ,        1,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51435         {"PSL1"                        ,        2,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51436         {"LDD"                         ,        3,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51437         {"LDI"                         ,        4,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51438         {"LDT"                         ,        5,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51439         {"STF"                         ,        6,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51440         {"STC"                         ,        7,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51441         {"STP"                         ,        8,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51442         {"STT"                         ,        9,      1,      871,    "R/W",  0,      0,      0ull,   1ull},
51443         {"IOBLD8"                      ,        10,     1,      871,    "R/W",  0,      0,      0ull,   1ull},
51444         {"IOBLD16"                     ,        11,     1,      871,    "R/W",  0,      0,      0ull,   1ull},
51445         {"IOBLD32"                     ,        12,     1,      871,    "R/W",  0,      0,      0ull,   1ull},
51446         {"IOBLD64"                     ,        13,     1,      871,    "R/W",  0,      0,      0ull,   1ull},
51447         {"IOBST"                       ,        14,     1,      871,    "R/W",  0,      0,      0ull,   1ull},
51448         {"IOBDMA"                      ,        15,     1,      871,    "R/W",  0,      0,      0ull,   1ull},
51449         {"SAA"                         ,        16,     1,      871,    "R/W",  0,      0,      0ull,   1ull},
51450         {"RESERVED_17_63"              ,        17,     47,     871,    "RAZ",  0,      0,      0ull,   0ull},
51451         {"MIO"                         ,        0,      1,      872,    "R/W",  0,      0,      0ull,   1ull},
51452         {"ILLEGAL3"                    ,        1,      2,      872,    "R/W",  0,      0,      0ull,   3ull},
51453         {"PCI"                         ,        3,      1,      872,    "R/W",  0,      0,      0ull,   1ull},
51454         {"KEY"                         ,        4,      1,      872,    "R/W",  0,      0,      0ull,   1ull},
51455         {"FPA"                         ,        5,      1,      872,    "R/W",  0,      0,      0ull,   1ull},
51456         {"DFA"                         ,        6,      1,      872,    "R/W",  0,      0,      0ull,   1ull},
51457         {"ZIP"                         ,        7,      1,      872,    "R/W",  0,      0,      0ull,   1ull},
51458         {"RNG"                         ,        8,      1,      872,    "R/W",  0,      0,      0ull,   1ull},
51459         {"ILLEGAL2"                    ,        9,      3,      872,    "R/W",  0,      0,      0ull,   7ull},
51460         {"POW"                         ,        12,     1,      872,    "R/W",  0,      0,      0ull,   1ull},
51461         {"ILLEGAL"                     ,        13,     19,     872,    "R/W",  0,      0,      0ull,   524287ull},
51462         {"RESERVED_32_63"              ,        32,     32,     872,    "RAZ",  0,      0,      0ull,   0ull},
51463         {"PP"                          ,        0,      16,     873,    "R/W",  0,      0,      0ull,   0ull},
51464         {"PKI"                         ,        16,     1,      873,    "R/W",  0,      0,      0ull,   0ull},
51465         {"PKO"                         ,        17,     1,      873,    "R/W",  0,      0,      0ull,   0ull},
51466         {"IOBREQ"                      ,        18,     1,      873,    "R/W",  0,      0,      0ull,   0ull},
51467         {"DWB"                         ,        19,     1,      873,    "R/W",  0,      0,      0ull,   0ull},
51468         {"RESERVED_20_63"              ,        20,     44,     873,    "RAZ",  0,      0,      0ull,   0ull},
51469         {"CIU_TRG"                     ,        0,      1,      874,    "R/W1C",        0,      0,      0ull,   0ull},
51470         {"CIU_THR"                     ,        1,      1,      874,    "R/W1C",        0,      0,      0ull,   0ull},
51471         {"MCD0_TRG"                    ,        2,      1,      874,    "R/W1C",        0,      0,      0ull,   0ull},
51472         {"MCD0_THR"                    ,        3,      1,      874,    "R/W1C",        0,      0,      0ull,   0ull},
51473         {"RESERVED_4_63"               ,        4,      60,     874,    "RAZ",  0,      0,      0ull,   0ull},
51474         {"DATA"                        ,        0,      64,     875,    "RO",   0,      0,      0ull,   0ull},
51475         {"ADR"                         ,        0,      36,     876,    "R/W",  0,      1,      0ull,   0},
51476         {"RESERVED_36_63"              ,        36,     28,     876,    "RAZ",  0,      0,      0ull,   0ull},
51477         {"ADR"                         ,        0,      36,     877,    "R/W",  0,      0,      0ull,   0ull},
51478         {"RESERVED_36_63"              ,        36,     28,     877,    "RAZ",  0,      0,      0ull,   0ull},
51479         {"DWB"                         ,        0,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51480         {"PL2"                         ,        1,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51481         {"PSL1"                        ,        2,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51482         {"LDD"                         ,        3,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51483         {"LDI"                         ,        4,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51484         {"LDT"                         ,        5,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51485         {"STF"                         ,        6,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51486         {"STC"                         ,        7,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51487         {"STP"                         ,        8,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51488         {"STT"                         ,        9,      1,      878,    "R/W",  0,      0,      0ull,   1ull},
51489         {"IOBLD8"                      ,        10,     1,      878,    "R/W",  0,      0,      0ull,   1ull},
51490         {"IOBLD16"                     ,        11,     1,      878,    "R/W",  0,      0,      0ull,   1ull},
51491         {"IOBLD32"                     ,        12,     1,      878,    "R/W",  0,      0,      0ull,   1ull},
51492         {"IOBLD64"                     ,        13,     1,      878,    "R/W",  0,      0,      0ull,   1ull},
51493         {"IOBST"                       ,        14,     1,      878,    "R/W",  0,      0,      0ull,   1ull},
51494         {"IOBDMA"                      ,        15,     1,      878,    "R/W",  0,      0,      0ull,   1ull},
51495         {"SAA"                         ,        16,     1,      878,    "R/W",  0,      0,      0ull,   1ull},
51496         {"RESERVED_17_63"              ,        17,     47,     878,    "RAZ",  0,      0,      0ull,   0ull},
51497         {"MIO"                         ,        0,      1,      879,    "R/W",  0,      0,      0ull,   1ull},
51498         {"ILLEGAL3"                    ,        1,      2,      879,    "R/W",  0,      0,      0ull,   3ull},
51499         {"PCI"                         ,        3,      1,      879,    "R/W",  0,      0,      0ull,   1ull},
51500         {"KEY"                         ,        4,      1,      879,    "R/W",  0,      0,      0ull,   1ull},
51501         {"FPA"                         ,        5,      1,      879,    "R/W",  0,      0,      0ull,   1ull},
51502         {"DFA"                         ,        6,      1,      879,    "R/W",  0,      0,      0ull,   1ull},
51503         {"ZIP"                         ,        7,      1,      879,    "R/W",  0,      0,      0ull,   1ull},
51504         {"RNG"                         ,        8,      1,      879,    "R/W",  0,      0,      0ull,   1ull},
51505         {"ILLEGAL2"                    ,        9,      3,      879,    "R/W",  0,      0,      0ull,   7ull},
51506         {"POW"                         ,        12,     1,      879,    "R/W",  0,      0,      0ull,   1ull},
51507         {"ILLEGAL"                     ,        13,     19,     879,    "R/W",  0,      0,      0ull,   524287ull},
51508         {"RESERVED_32_63"              ,        32,     32,     879,    "RAZ",  0,      0,      0ull,   0ull},
51509         {"PP"                          ,        0,      16,     880,    "R/W",  0,      0,      0ull,   0ull},
51510         {"PKI"                         ,        16,     1,      880,    "R/W",  0,      0,      0ull,   0ull},
51511         {"PKO"                         ,        17,     1,      880,    "R/W",  0,      0,      0ull,   0ull},
51512         {"IOBREQ"                      ,        18,     1,      880,    "R/W",  0,      0,      0ull,   0ull},
51513         {"DWB"                         ,        19,     1,      880,    "R/W",  0,      0,      0ull,   0ull},
51514         {"RESERVED_20_63"              ,        20,     44,     880,    "RAZ",  0,      0,      0ull,   0ull},
51515         {"ADR"                         ,        0,      36,     881,    "R/W",  0,      1,      0ull,   0},
51516         {"RESERVED_36_63"              ,        36,     28,     881,    "RAZ",  0,      0,      0ull,   0ull},
51517         {"ADR"                         ,        0,      36,     882,    "R/W",  0,      0,      0ull,   0ull},
51518         {"RESERVED_36_63"              ,        36,     28,     882,    "RAZ",  0,      0,      0ull,   0ull},
51519         {"DWB"                         ,        0,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51520         {"PL2"                         ,        1,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51521         {"PSL1"                        ,        2,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51522         {"LDD"                         ,        3,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51523         {"LDI"                         ,        4,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51524         {"LDT"                         ,        5,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51525         {"STF"                         ,        6,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51526         {"STC"                         ,        7,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51527         {"STP"                         ,        8,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51528         {"STT"                         ,        9,      1,      883,    "R/W",  0,      0,      0ull,   1ull},
51529         {"IOBLD8"                      ,        10,     1,      883,    "R/W",  0,      0,      0ull,   1ull},
51530         {"IOBLD16"                     ,        11,     1,      883,    "R/W",  0,      0,      0ull,   1ull},
51531         {"IOBLD32"                     ,        12,     1,      883,    "R/W",  0,      0,      0ull,   1ull},
51532         {"IOBLD64"                     ,        13,     1,      883,    "R/W",  0,      0,      0ull,   1ull},
51533         {"IOBST"                       ,        14,     1,      883,    "R/W",  0,      0,      0ull,   1ull},
51534         {"IOBDMA"                      ,        15,     1,      883,    "R/W",  0,      0,      0ull,   1ull},
51535         {"SAA"                         ,        16,     1,      883,    "R/W",  0,      0,      0ull,   1ull},
51536         {"RESERVED_17_63"              ,        17,     47,     883,    "RAZ",  0,      0,      0ull,   0ull},
51537         {"MIO"                         ,        0,      1,      884,    "R/W",  0,      0,      0ull,   1ull},
51538         {"ILLEGAL3"                    ,        1,      2,      884,    "R/W",  0,      0,      0ull,   3ull},
51539         {"PCI"                         ,        3,      1,      884,    "R/W",  0,      0,      0ull,   1ull},
51540         {"KEY"                         ,        4,      1,      884,    "R/W",  0,      0,      0ull,   1ull},
51541         {"FPA"                         ,        5,      1,      884,    "R/W",  0,      0,      0ull,   1ull},
51542         {"DFA"                         ,        6,      1,      884,    "R/W",  0,      0,      0ull,   1ull},
51543         {"ZIP"                         ,        7,      1,      884,    "R/W",  0,      0,      0ull,   1ull},
51544         {"RNG"                         ,        8,      1,      884,    "R/W",  0,      0,      0ull,   1ull},
51545         {"ILLEGAL2"                    ,        9,      3,      884,    "R/W",  0,      0,      0ull,   7ull},
51546         {"POW"                         ,        12,     1,      884,    "R/W",  0,      0,      0ull,   1ull},
51547         {"ILLEGAL"                     ,        13,     19,     884,    "R/W",  0,      0,      0ull,   524287ull},
51548         {"RESERVED_32_63"              ,        32,     32,     884,    "RAZ",  0,      0,      0ull,   0ull},
51549         {"PP"                          ,        0,      16,     885,    "R/W",  0,      0,      0ull,   0ull},
51550         {"PKI"                         ,        16,     1,      885,    "R/W",  0,      0,      0ull,   0ull},
51551         {"PKO"                         ,        17,     1,      885,    "R/W",  0,      0,      0ull,   0ull},
51552         {"IOBREQ"                      ,        18,     1,      885,    "R/W",  0,      0,      0ull,   0ull},
51553         {"DWB"                         ,        19,     1,      885,    "R/W",  0,      0,      0ull,   0ull},
51554         {"RESERVED_20_63"              ,        20,     44,     885,    "RAZ",  0,      0,      0ull,   0ull},
51555         {"INEPINT"                     ,        0,      16,     886,    "RO",   0,      0,      0ull,   0ull},
51556         {"OUTEPINT"                    ,        16,     16,     886,    "RO",   0,      0,      0ull,   0ull},
51557         {"INEPMSK"                     ,        0,      16,     887,    "R/W",  0,      0,      0ull,   0ull},
51558         {"OUTEPMSK"                    ,        16,     16,     887,    "R/W",  0,      0,      0ull,   0ull},
51559         {"DEVSPD"                      ,        0,      2,      888,    "R/W",  0,      0,      0ull,   0ull},
51560         {"NZSTSOUTHSHK"                ,        2,      1,      888,    "R/W",  0,      0,      0ull,   0ull},
51561         {"RESERVED_3_3"                ,        3,      1,      888,    "RAZ",  1,      1,      0,      0},
51562         {"DEVADDR"                     ,        4,      7,      888,    "R/W",  0,      0,      0ull,   0ull},
51563         {"PERFRINT"                    ,        11,     2,      888,    "R/W",  0,      0,      0ull,   0ull},
51564         {"RESERVED_13_17"              ,        13,     5,      888,    "RAZ",  1,      1,      0,      0},
51565         {"EPMISCNT"                    ,        18,     5,      888,    "R/W",  0,      0,      8ull,   0ull},
51566         {"RESERVED_23_31"              ,        23,     9,      888,    "RAZ",  1,      1,      0,      0},
51567         {"RMTWKUPSIG"                  ,        0,      1,      889,    "R/W",  0,      0,      0ull,   0ull},
51568         {"SFTDISCON"                   ,        1,      1,      889,    "R/W",  0,      0,      0ull,   0ull},
51569         {"GNPINNAKSTS"                 ,        2,      1,      889,    "RO",   0,      0,      0ull,   0ull},
51570         {"GOUTNAKSTS"                  ,        3,      1,      889,    "RO",   0,      0,      0ull,   0ull},
51571         {"TSTCTL"                      ,        4,      3,      889,    "R/W",  0,      0,      0ull,   0ull},
51572         {"SGNPINNAK"                   ,        7,      1,      889,    "WO",   0,      0,      0ull,   0ull},
51573         {"CGNPINNAK"                   ,        8,      1,      889,    "WO",   0,      0,      0ull,   0ull},
51574         {"SGOUTNAK"                    ,        9,      1,      889,    "WO",   0,      0,      0ull,   0ull},
51575         {"CGOUTNAK"                    ,        10,     1,      889,    "WO",   0,      0,      0ull,   0ull},
51576         {"PWRONPRGDONE"                ,        11,     1,      889,    "R/W",  0,      0,      0ull,   0ull},
51577         {"RESERVED_12_31"              ,        12,     20,     889,    "RAZ",  1,      1,      0,      0},
51578         {"MPS"                         ,        0,      11,     890,    "R/W",  0,      0,      0ull,   0ull},
51579         {"NEXTEP"                      ,        11,     4,      890,    "R/W",  0,      0,      0ull,   0ull},
51580         {"USBACTEP"                    ,        15,     1,      890,    "R/W",  0,      0,      1ull,   0ull},
51581         {"DPID"                        ,        16,     1,      890,    "RO",   0,      0,      0ull,   0ull},
51582         {"NAKSTS"                      ,        17,     1,      890,    "RO",   0,      0,      0ull,   0ull},
51583         {"EPTYPE"                      ,        18,     2,      890,    "R/W",  0,      0,      0ull,   0ull},
51584         {"RESERVED_20_20"              ,        20,     1,      890,    "RAZ",  1,      1,      0,      0},
51585         {"STALL"                       ,        21,     1,      890,    "R/W",  0,      0,      0ull,   0ull},
51586         {"TXFNUM"                      ,        22,     4,      890,    "R/W",  0,      0,      0ull,   0ull},
51587         {"CNAK"                        ,        26,     1,      890,    "WO",   0,      0,      0ull,   0ull},
51588         {"SNAK"                        ,        27,     1,      890,    "WO",   0,      0,      0ull,   0ull},
51589         {"SETD0PID"                    ,        28,     1,      890,    "WO",   0,      0,      0ull,   0ull},
51590         {"SETD1PID"                    ,        29,     1,      890,    "WO",   0,      0,      0ull,   0ull},
51591         {"EPDIS"                       ,        30,     1,      890,    "R/W",  0,      0,      0ull,   0ull},
51592         {"EPENA"                       ,        31,     1,      890,    "R/W",  0,      0,      0ull,   0ull},
51593         {"XFERCOMPL"                   ,        0,      1,      891,    "R/W1C",        0,      0,      0ull,   0ull},
51594         {"EPDISBLD"                    ,        1,      1,      891,    "R/W1C",        0,      0,      0ull,   0ull},
51595         {"AHBERR"                      ,        2,      1,      891,    "R/W1C",        0,      0,      0ull,   0ull},
51596         {"TIMEOUT"                     ,        3,      1,      891,    "R/W1C",        0,      0,      0ull,   0ull},
51597         {"INTKNTXFEMP"                 ,        4,      1,      891,    "R/W1C",        0,      0,      0ull,   0ull},
51598         {"INTKNEPMIS"                  ,        5,      1,      891,    "R/W1C",        0,      0,      0ull,   0ull},
51599         {"INEPNAKEFF"                  ,        6,      1,      891,    "RO",   0,      0,      0ull,   0ull},
51600         {"RESERVED_7_31"               ,        7,      25,     891,    "RAZ",  1,      1,      0,      0},
51601         {"XFERCOMPLMSK"                ,        0,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
51602         {"EPDISBLDMSK"                 ,        1,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
51603         {"AHBERRMSK"                   ,        2,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
51604         {"TIMEOUTMSK"                  ,        3,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
51605         {"INTKNTXFEMPMSK"              ,        4,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
51606         {"INTKNEPMISMSK"               ,        5,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
51607         {"INEPNAKEFFMSK"               ,        6,      1,      892,    "R/W",  0,      0,      0ull,   0ull},
51608         {"RESERVED_7_31"               ,        7,      25,     892,    "RAZ",  1,      1,      0,      0},
51609         {"XFERSIZE"                    ,        0,      19,     893,    "R/W",  0,      0,      0ull,   0ull},
51610         {"PKTCNT"                      ,        19,     10,     893,    "R/W",  0,      0,      0ull,   0ull},
51611         {"MC"                          ,        29,     2,      893,    "R/W",  0,      0,      0ull,   0ull},
51612         {"RESERVED_31_31"              ,        31,     1,      893,    "RAZ",  1,      1,      0,      0},
51613         {"MPS"                         ,        0,      11,     894,    "R/W",  0,      0,      0ull,   0ull},
51614         {"RESERVED_11_14"              ,        11,     4,      894,    "RAZ",  0,      0,      0ull,   0ull},
51615         {"USBACTEP"                    ,        15,     1,      894,    "R/W",  0,      0,      1ull,   0ull},
51616         {"DPID"                        ,        16,     1,      894,    "RO",   0,      0,      0ull,   0ull},
51617         {"NAKSTS"                      ,        17,     1,      894,    "RO",   0,      0,      0ull,   0ull},
51618         {"EPTYPE"                      ,        18,     2,      894,    "R/W",  0,      0,      0ull,   0ull},
51619         {"SNP"                         ,        20,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
51620         {"STALL"                       ,        21,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
51621         {"RESERVED_22_25"              ,        22,     4,      894,    "RAZ",  1,      1,      0,      0},
51622         {"CNAK"                        ,        26,     1,      894,    "WO",   0,      0,      0ull,   0ull},
51623         {"SNAK"                        ,        27,     1,      894,    "WO",   0,      0,      0ull,   0ull},
51624         {"SETD0PID"                    ,        28,     1,      894,    "WO",   0,      0,      0ull,   0ull},
51625         {"SETD1PID"                    ,        29,     1,      894,    "WO",   0,      0,      0ull,   0ull},
51626         {"EPDIS"                       ,        30,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
51627         {"EPENA"                       ,        31,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
51628         {"XFERCOMPL"                   ,        0,      1,      895,    "R/W1C",        0,      0,      0ull,   0ull},
51629         {"EPDISBLD"                    ,        1,      1,      895,    "R/W1C",        0,      0,      0ull,   0ull},
51630         {"AHBERR"                      ,        2,      1,      895,    "R/W1C",        0,      0,      0ull,   0ull},
51631         {"SETUP"                       ,        3,      1,      895,    "R/W1C",        0,      0,      0ull,   0ull},
51632         {"OUTTKNEPDIS"                 ,        4,      1,      895,    "R/W1C",        0,      0,      0ull,   0ull},
51633         {"RESERVED_5_31"               ,        5,      27,     895,    "RAZ",  1,      1,      0,      0},
51634         {"XFERCOMPLMSK"                ,        0,      1,      896,    "R/W",  0,      0,      0ull,   0ull},
51635         {"EPDISBLDMSK"                 ,        1,      1,      896,    "R/W",  0,      0,      0ull,   0ull},
51636         {"AHBERRMSK"                   ,        2,      1,      896,    "R/W",  0,      0,      0ull,   0ull},
51637         {"SETUPMSK"                    ,        3,      1,      896,    "R/W",  0,      0,      0ull,   0ull},
51638         {"OUTTKNEPDISMSK"              ,        4,      1,      896,    "R/W",  0,      0,      0ull,   0ull},
51639         {"RESERVED_5_31"               ,        5,      27,     896,    "RAZ",  1,      1,      0,      0},
51640         {"XFERSIZE"                    ,        0,      19,     897,    "R/W",  0,      0,      0ull,   0ull},
51641         {"PKTCNT"                      ,        19,     10,     897,    "R/W",  0,      0,      0ull,   0ull},
51642         {"MC"                          ,        29,     2,      897,    "R/W",  0,      0,      0ull,   0ull},
51643         {"RESERVED_31_31"              ,        31,     1,      897,    "RAZ",  1,      1,      0,      0},
51644         {"DPTXFSTADDR"                 ,        0,      16,     898,    "RO",   0,      0,      0ull,   0ull},
51645         {"DPTXFSIZE"                   ,        16,     16,     898,    "RO",   0,      0,      1896ull,        1896ull},
51646         {"SUSPSTS"                     ,        0,      1,      899,    "RO",   0,      0,      0ull,   0ull},
51647         {"ENUMSPD"                     ,        1,      2,      899,    "RO",   0,      0,      0ull,   0ull},
51648         {"ERRTICERR"                   ,        3,      1,      899,    "RO",   0,      0,      0ull,   0ull},
51649         {"RESERVED_4_7"                ,        4,      4,      899,    "RAZ",  1,      1,      0,      0},
51650         {"SOFFN"                       ,        8,      14,     899,    "RO",   0,      0,      0ull,   0ull},
51651         {"RESERVED_22_31"              ,        22,     10,     899,    "RAZ",  1,      1,      0,      0},
51652         {"INTKNWPTR"                   ,        0,      5,      900,    "RO",   0,      0,      0ull,   0ull},
51653         {"RESERVED_5_6"                ,        5,      2,      900,    "RAZ",  1,      1,      0,      0},
51654         {"WRAPBIT"                     ,        7,      1,      900,    "RO",   0,      0,      0ull,   0ull},
51655         {"EPTKN"                       ,        8,      24,     900,    "RO",   0,      0,      0ull,   0ull},
51656         {"EPTKN"                       ,        0,      32,     901,    "RO",   0,      0,      0ull,   0ull},
51657         {"EPTKN"                       ,        0,      32,     902,    "RO",   0,      0,      0ull,   0ull},
51658         {"EPTKN"                       ,        0,      32,     903,    "RO",   0,      0,      0ull,   0ull},
51659         {"GLBLINTRMSK"                 ,        0,      1,      904,    "R/W",  0,      0,      0ull,   1ull},
51660         {"HBSTLEN"                     ,        1,      4,      904,    "R/W",  0,      0,      0ull,   0ull},
51661         {"DMAEN"                       ,        5,      1,      904,    "R/W",  0,      0,      0ull,   0ull},
51662         {"RESERVED_6_6"                ,        6,      1,      904,    "RAZ",  1,      1,      0,      0},
51663         {"NPTXFEMPLVL"                 ,        7,      1,      904,    "R/W",  0,      0,      0ull,   1ull},
51664         {"PTXFEMPLVL"                  ,        8,      1,      904,    "R/W",  0,      0,      0ull,   1ull},
51665         {"RESERVED_9_31"               ,        9,      23,     904,    "RAZ",  1,      1,      0,      0},
51666         {"EPDIR"                       ,        0,      32,     905,    "RO",   0,      0,      0ull,   0ull},
51667         {"OTGMODE"                     ,        0,      3,      906,    "RO",   0,      0,      2ull,   2ull},
51668         {"OTGARCH"                     ,        3,      2,      906,    "RO",   0,      0,      1ull,   1ull},
51669         {"SINGPNT"                     ,        5,      1,      906,    "RO",   0,      0,      0ull,   0ull},
51670         {"HSPHYTYPE"                   ,        6,      2,      906,    "RO",   0,      0,      1ull,   1ull},
51671         {"FSPHYTYPE"                   ,        8,      2,      906,    "RO",   0,      0,      0ull,   0ull},
51672         {"NUMDEVEPS"                   ,        10,     4,      906,    "RO",   0,      0,      4ull,   4ull},
51673         {"NUMHSTCHNL"                  ,        14,     4,      906,    "RO",   0,      0,      7ull,   7ull},
51674         {"PERIOSUPPORT"                ,        18,     1,      906,    "RO",   0,      0,      1ull,   1ull},
51675         {"DYNFIFOSIZING"               ,        19,     1,      906,    "RO",   0,      0,      1ull,   1ull},
51676         {"RESERVED_20_21"              ,        20,     2,      906,    "RAZ",  1,      1,      0,      0},
51677         {"NPTXQDEPTH"                  ,        22,     2,      906,    "RO",   0,      0,      2ull,   2ull},
51678         {"PTXQDEPTH"                   ,        24,     2,      906,    "RO",   0,      0,      2ull,   2ull},
51679         {"TKNQDEPTH"                   ,        26,     5,      906,    "RO",   0,      0,      30ull,  30ull},
51680         {"RESERVED_31_31"              ,        31,     1,      906,    "RAZ",  1,      1,      0,      0},
51681         {"XFERSIZEWIDTH"               ,        0,      4,      907,    "RO",   0,      0,      8ull,   8ull},
51682         {"PKTSIZEWIDTH"                ,        4,      3,      907,    "RO",   0,      0,      6ull,   6ull},
51683         {"OTGEN"                       ,        7,      1,      907,    "RO",   0,      0,      1ull,   1ull},
51684         {"I2C_SELECTION"               ,        8,      1,      907,    "RO",   0,      0,      0ull,   0ull},
51685         {"VENDOR_CONTROL_INTERFACE_SUPPORT",    9,      1,      907,    "RO",   0,      0,      0ull,   0ull},
51686         {"OPTFEATURE"                  ,        10,     1,      907,    "RO",   0,      0,      1ull,   1ull},
51687         {"RSTTYPE"                     ,        11,     1,      907,    "RO",   0,      0,      0ull,   0ull},
51688         {"AHBPHYSYNC"                  ,        12,     1,      907,    "RO",   0,      0,      0ull,   0ull},
51689         {"RESERVED_13_15"              ,        13,     3,      907,    "RAZ",  1,      1,      0,      0},
51690         {"DFIFODEPTH"                  ,        16,     16,     907,    "RO",   0,      0,      1824ull,        1824ull},
51691         {"NUMDEVPERIOEPS"              ,        0,      4,      908,    "RO",   0,      0,      4ull,   4ull},
51692         {"ENABLEPWROPT"                ,        4,      1,      908,    "RO",   0,      0,      0ull,   0ull},
51693         {"AHBFREQ"                     ,        5,      1,      908,    "RO",   0,      0,      1ull,   1ull},
51694         {"RESERVED_6_13"               ,        6,      8,      908,    "RAZ",  1,      1,      0,      0},
51695         {"PHYDATAWIDTH"                ,        14,     2,      908,    "RO",   0,      0,      1ull,   1ull},
51696         {"NUMCTLEPS"                   ,        16,     4,      908,    "RO",   0,      0,      4ull,   4ull},
51697         {"IDDGFLTR"                    ,        20,     1,      908,    "RO",   0,      0,      1ull,   1ull},
51698         {"VBUSVALIDFLTR"               ,        21,     1,      908,    "RO",   0,      0,      1ull,   1ull},
51699         {"AVALIDFLTR"                  ,        22,     1,      908,    "RO",   0,      0,      0ull,   0ull},
51700         {"BVALIDFLTR"                  ,        23,     1,      908,    "RO",   0,      0,      0ull,   0ull},
51701         {"SESSENDFLTR"                 ,        24,     1,      908,    "RO",   0,      0,      0ull,   0ull},
51702         {"ENDEDTRFIFO"                 ,        25,     1,      908,    "RO",   0,      0,      0ull,   0ull},
51703         {"NUMDEVMODINEND"              ,        26,     4,      908,    "RO",   0,      0,      2ull,   2ull},
51704         {"RESERVED_30_31"              ,        30,     2,      908,    "RAZ",  1,      1,      0,      0},
51705         {"RESERVED_0_0"                ,        0,      1,      909,    "RAZ",  1,      1,      0,      0},
51706         {"MODEMISMSK"                  ,        1,      1,      909,    "R/W",  0,      0,      0ull,   0ull},
51707         {"OTGINTMSK"                   ,        2,      1,      909,    "R/W",  0,      0,      0ull,   0ull},
51708         {"SOFMSK"                      ,        3,      1,      909,    "R/W",  0,      0,      0ull,   0ull},
51709         {"RXFLVLMSK"                   ,        4,      1,      909,    "R/W",  0,      0,      0ull,   0ull},
51710         {"NPTXFEMPMSK"                 ,        5,      1,      909,    "R/W",  0,      0,      0ull,   0ull},
51711         {"GINNAKEFFMSK"                ,        6,      1,      909,    "R/W",  0,      0,      0ull,   0ull},
51712         {"GOUTNAKEFFMSK"               ,        7,      1,      909,    "R/W",  0,      0,      0ull,   0ull},
51713         {"ULPICKINTMSK"                ,        8,      1,      909,    "R/W",  0,      0,      0ull,   0ull},
51714         {"I2CINT"                      ,        9,      1,      909,    "R/W",  0,      0,      0ull,   0ull},
51715         {"ERLYSUSPMSK"                 ,        10,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51716         {"USBSUSPMSK"                  ,        11,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51717         {"USBRSTMSK"                   ,        12,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51718         {"ENUMDONEMSK"                 ,        13,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51719         {"ISOOUTDROPMSK"               ,        14,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51720         {"EOPFMSK"                     ,        15,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51721         {"RESERVED_16_16"              ,        16,     1,      909,    "RAZ",  1,      1,      0,      0},
51722         {"EPMISMSK"                    ,        17,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51723         {"INEPINTMSK"                  ,        18,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51724         {"OEPINTMSK"                   ,        19,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51725         {"INCOMPISOINMSK"              ,        20,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51726         {"INCOMPLPMSK"                 ,        21,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51727         {"FETSUSPMSK"                  ,        22,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51728         {"RESERVED_23_23"              ,        23,     1,      909,    "RAZ",  1,      1,      0,      0},
51729         {"PRTINTMSK"                   ,        24,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51730         {"HCHINTMSK"                   ,        25,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51731         {"PTXFEMPMSK"                  ,        26,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51732         {"RESERVED_27_27"              ,        27,     1,      909,    "RAZ",  1,      1,      0,      0},
51733         {"CONIDSTSCHNGMSK"             ,        28,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51734         {"DISCONNINTMSK"               ,        29,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51735         {"SESSREQINTMSK"               ,        30,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51736         {"WKUPINTMSK"                  ,        31,     1,      909,    "R/W",  0,      0,      0ull,   0ull},
51737         {"CURMOD"                      ,        0,      1,      910,    "RO",   0,      0,      0ull,   0ull},
51738         {"MODEMIS"                     ,        1,      1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51739         {"OTGINT"                      ,        2,      1,      910,    "RO",   0,      0,      0ull,   0ull},
51740         {"SOF"                         ,        3,      1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51741         {"RXFLVL"                      ,        4,      1,      910,    "RO",   0,      0,      0ull,   0ull},
51742         {"NPTXFEMP"                    ,        5,      1,      910,    "RO",   0,      0,      0ull,   0ull},
51743         {"GINNAKEFF"                   ,        6,      1,      910,    "RO",   0,      0,      0ull,   0ull},
51744         {"GOUTNAKEFF"                  ,        7,      1,      910,    "RO",   0,      0,      0ull,   0ull},
51745         {"ULPICKINT"                   ,        8,      1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51746         {"I2CINT"                      ,        9,      1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51747         {"ERLYSUSP"                    ,        10,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51748         {"USBSUSP"                     ,        11,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51749         {"USBRST"                      ,        12,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51750         {"ENUMDONE"                    ,        13,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51751         {"ISOOUTDROP"                  ,        14,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51752         {"EOPF"                        ,        15,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51753         {"RESERVED_16_16"              ,        16,     1,      910,    "RAZ",  1,      1,      0,      0},
51754         {"EPMIS"                       ,        17,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51755         {"IEPINT"                      ,        18,     1,      910,    "RO",   0,      0,      0ull,   0ull},
51756         {"OEPINT"                      ,        19,     1,      910,    "RO",   0,      0,      0ull,   0ull},
51757         {"INCOMPISOIN"                 ,        20,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51758         {"INCOMPLP"                    ,        21,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51759         {"FETSUSP"                     ,        22,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51760         {"RESERVED_23_23"              ,        23,     1,      910,    "RAZ",  1,      1,      0,      0},
51761         {"PRTINT"                      ,        24,     1,      910,    "RO",   0,      0,      0ull,   0ull},
51762         {"HCHINT"                      ,        25,     1,      910,    "RO",   0,      0,      0ull,   0ull},
51763         {"PTXFEMP"                     ,        26,     1,      910,    "RO",   0,      0,      0ull,   0ull},
51764         {"RESERVED_27_27"              ,        27,     1,      910,    "RAZ",  1,      1,      0,      0},
51765         {"CONIDSTSCHNG"                ,        28,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51766         {"DISCONNINT"                  ,        29,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51767         {"SESSREQINT"                  ,        30,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51768         {"WKUPINT"                     ,        31,     1,      910,    "R/W1C",        0,      0,      0ull,   0ull},
51769         {"NPTXFSTADDR"                 ,        0,      16,     911,    "R/W",  0,      0,      1824ull,        456ull},
51770         {"NPTXFDEP"                    ,        16,     16,     911,    "R/W",  0,      0,      1824ull,        912ull},
51771         {"NPTXFSPCAVAIL"               ,        0,      16,     912,    "RO",   0,      0,      0ull,   0ull},
51772         {"NPTXQSPCAVAIL"               ,        16,     8,      912,    "RO",   0,      0,      0ull,   0ull},
51773         {"NPTXQTOP"                    ,        24,     7,      912,    "RO",   0,      0,      0ull,   0ull},
51774         {"RESERVED_31_31"              ,        31,     1,      912,    "RAZ",  1,      1,      0,      0},
51775         {"SESREQSCS"                   ,        0,      1,      913,    "R/W",  0,      0,      0ull,   0ull},
51776         {"SESREQ"                      ,        1,      1,      913,    "R/W",  0,      0,      0ull,   0ull},
51777         {"RESERVED_2_7"                ,        2,      6,      913,    "RAZ",  1,      1,      0,      0},
51778         {"HSTNEGSCS"                   ,        8,      1,      913,    "R/W",  0,      0,      0ull,   0ull},
51779         {"HNPREQ"                      ,        9,      1,      913,    "R/W",  0,      0,      0ull,   0ull},
51780         {"HSTSETHNPEN"                 ,        10,     1,      913,    "R/W",  0,      0,      0ull,   0ull},
51781         {"DEVHNPEN"                    ,        11,     1,      913,    "R/W",  0,      0,      0ull,   0ull},
51782         {"RESERVED_12_15"              ,        12,     4,      913,    "RAZ",  1,      1,      0,      0},
51783         {"CONIDSTS"                    ,        16,     1,      913,    "RO",   1,      1,      0,      0},
51784         {"DBNCTIME"                    ,        17,     1,      913,    "RO",   0,      0,      0ull,   0ull},
51785         {"ASESVLD"                     ,        18,     1,      913,    "RO",   1,      1,      0,      0},
51786         {"BSESVLD"                     ,        19,     1,      913,    "RO",   1,      1,      0,      0},
51787         {"RESERVED_20_31"              ,        20,     12,     913,    "RAZ",  1,      1,      0,      0},
51788         {"RESERVED_0_1"                ,        0,      2,      914,    "RAZ",  1,      1,      0,      0},
51789         {"SESENDDET"                   ,        2,      1,      914,    "R/W1C",        0,      0,      0ull,   0ull},
51790         {"RESERVED_3_7"                ,        3,      5,      914,    "RAZ",  1,      1,      0,      0},
51791         {"SESREQSUCSTSCHNG"            ,        8,      1,      914,    "R/W1C",        0,      0,      0ull,   0ull},
51792         {"HSTNEGSUCSTSCHNG"            ,        9,      1,      914,    "R/W1C",        0,      0,      0ull,   0ull},
51793         {"RESERVED_10_16"              ,        10,     7,      914,    "RAZ",  1,      1,      0,      0},
51794         {"HSTNEGDET"                   ,        17,     1,      914,    "R/W1C",        0,      0,      0ull,   0ull},
51795         {"ADEVTOUTCHG"                 ,        18,     1,      914,    "R/W1C",        0,      0,      0ull,   0ull},
51796         {"DBNCEDONE"                   ,        19,     1,      914,    "R/W1C",        0,      0,      0ull,   0ull},
51797         {"RESERVED_20_31"              ,        20,     12,     914,    "RAZ",  1,      1,      0,      0},
51798         {"CSFTRST"                     ,        0,      1,      915,    "R/W",  0,      0,      0ull,   0ull},
51799         {"HSFTRST"                     ,        1,      1,      915,    "R/W",  0,      0,      0ull,   0ull},
51800         {"FRMCNTRRST"                  ,        2,      1,      915,    "R/W",  0,      0,      0ull,   0ull},
51801         {"INTKNQFLSH"                  ,        3,      1,      915,    "R/W",  0,      0,      0ull,   0ull},
51802         {"RXFFLSH"                     ,        4,      1,      915,    "R/W",  0,      0,      0ull,   0ull},
51803         {"TXFFLSH"                     ,        5,      1,      915,    "R/W",  0,      0,      0ull,   0ull},
51804         {"TXFNUM"                      ,        6,      5,      915,    "R/W",  0,      0,      0ull,   0ull},
51805         {"RESERVED_11_29"              ,        11,     19,     915,    "RAZ",  1,      1,      0,      0},
51806         {"DMAREQ"                      ,        30,     1,      915,    "RO",   0,      0,      0ull,   0ull},
51807         {"AHBIDLE"                     ,        31,     1,      915,    "RO",   0,      0,      1ull,   1ull},
51808         {"RXFDEP"                      ,        0,      16,     916,    "R/W",  0,      0,      1824ull,        456ull},
51809         {"RESERVED_16_31"              ,        16,     16,     916,    "RAZ",  1,      1,      0,      0},
51810         {"EPNUM"                       ,        0,      4,      917,    "RO",   0,      0,      0ull,   0ull},
51811         {"BCNT"                        ,        4,      11,     917,    "RO",   0,      0,      0ull,   0ull},
51812         {"DPID"                        ,        15,     2,      917,    "RO",   0,      0,      0ull,   0ull},
51813         {"PKTSTS"                      ,        17,     4,      917,    "RO",   0,      0,      0ull,   0ull},
51814         {"FN"                          ,        21,     4,      917,    "RO",   0,      0,      0ull,   0ull},
51815         {"RESERVED_25_31"              ,        25,     7,      917,    "RAZ",  1,      1,      0,      0},
51816         {"CHNUM"                       ,        0,      4,      918,    "RO",   0,      0,      0ull,   0ull},
51817         {"BCNT"                        ,        4,      11,     918,    "RO",   0,      0,      0ull,   0ull},
51818         {"DPID"                        ,        15,     2,      918,    "RO",   0,      0,      0ull,   0ull},
51819         {"PKTSTS"                      ,        17,     4,      918,    "RO",   0,      0,      0ull,   0ull},
51820         {"RESERVED_21_31"              ,        21,     11,     918,    "RAZ",  1,      1,      0,      0},
51821         {"EPNUM"                       ,        0,      4,      919,    "RO",   0,      0,      0ull,   0ull},
51822         {"BCNT"                        ,        4,      11,     919,    "RO",   0,      0,      0ull,   0ull},
51823         {"DPID"                        ,        15,     2,      919,    "RO",   0,      0,      0ull,   0ull},
51824         {"PKTSTS"                      ,        17,     4,      919,    "RO",   0,      0,      0ull,   0ull},
51825         {"FN"                          ,        21,     4,      919,    "RO",   0,      0,      0ull,   0ull},
51826         {"RESERVED_25_31"              ,        25,     7,      919,    "RAZ",  1,      1,      0,      0},
51827         {"CHNUM"                       ,        0,      4,      920,    "RO",   0,      0,      0ull,   0ull},
51828         {"BCNT"                        ,        4,      11,     920,    "RO",   0,      0,      0ull,   0ull},
51829         {"DPID"                        ,        15,     2,      920,    "RO",   0,      0,      0ull,   0ull},
51830         {"PKTSTS"                      ,        17,     4,      920,    "RO",   0,      0,      0ull,   0ull},
51831         {"RESERVED_21_31"              ,        21,     11,     920,    "RAZ",  1,      1,      0,      0},
51832         {"SYNOPSYSID"                  ,        0,      32,     921,    "RO",   1,      1,      0,      0},
51833         {"TOUTCAL"                     ,        0,      3,      922,    "R/W",  0,      0,      0ull,   0ull},
51834         {"PHYIF"                       ,        3,      1,      922,    "RO",   0,      0,      1ull,   1ull},
51835         {"ULPI_UTMI_SEL"               ,        4,      1,      922,    "RO",   0,      0,      0ull,   0ull},
51836         {"FSINTF"                      ,        5,      1,      922,    "WO",   0,      0,      0ull,   0ull},
51837         {"PHYSEL"                      ,        6,      1,      922,    "WO",   0,      0,      0ull,   0ull},
51838         {"DDRSEL"                      ,        7,      1,      922,    "R/W",  0,      0,      0ull,   0ull},
51839         {"SRPCAP"                      ,        8,      1,      922,    "RO",   0,      0,      0ull,   0ull},
51840         {"HNPCAP"                      ,        9,      1,      922,    "RO",   0,      0,      0ull,   0ull},
51841         {"USBTRDTIM"                   ,        10,     4,      922,    "R/W",  0,      0,      5ull,   5ull},
51842         {"RESERVED_14_14"              ,        14,     1,      922,    "RAZ",  1,      1,      0,      0},
51843         {"PHYLPWRCLKSEL"               ,        15,     1,      922,    "R/W",  0,      0,      0ull,   0ull},
51844         {"OTGI2CSEL"                   ,        16,     1,      922,    "RO",   0,      0,      0ull,   0ull},
51845         {"RESERVED_17_31"              ,        17,     15,     922,    "RAZ",  1,      1,      0,      0},
51846         {"HAINT"                       ,        0,      16,     923,    "RO",   0,      0,      0ull,   0ull},
51847         {"RESERVED_16_31"              ,        16,     16,     923,    "RAZ",  1,      1,      0,      0},
51848         {"HAINTMSK"                    ,        0,      16,     924,    "R/W",  0,      0,      0ull,   0ull},
51849         {"RESERVED_16_31"              ,        16,     16,     924,    "RAZ",  1,      1,      0,      0},
51850         {"MPS"                         ,        0,      11,     925,    "R/W",  0,      0,      0ull,   0ull},
51851         {"EPNUM"                       ,        11,     4,      925,    "R/W",  0,      0,      0ull,   0ull},
51852         {"EPDIR"                       ,        15,     1,      925,    "R/W",  0,      0,      0ull,   0ull},
51853         {"RESERVED_16_16"              ,        16,     1,      925,    "RAZ",  1,      1,      0,      0},
51854         {"LSPDDEV"                     ,        17,     1,      925,    "R/W",  0,      0,      0ull,   0ull},
51855         {"EPTYPE"                      ,        18,     2,      925,    "R/W",  0,      0,      0ull,   0ull},
51856         {"EC"                          ,        20,     2,      925,    "R/W",  0,      0,      0ull,   0ull},
51857         {"DEVADDR"                     ,        22,     7,      925,    "R/W",  0,      0,      0ull,   0ull},
51858         {"ODDFRM"                      ,        29,     1,      925,    "R/W",  0,      0,      0ull,   0ull},
51859         {"CHDIS"                       ,        30,     1,      925,    "R/W",  0,      0,      0ull,   0ull},
51860         {"CHENA"                       ,        31,     1,      925,    "R/W",  0,      0,      0ull,   0ull},
51861         {"FSLSPCLKSEL"                 ,        0,      2,      926,    "R/W",  0,      0,      0ull,   0ull},
51862         {"FSLSSUPP"                    ,        2,      1,      926,    "R/W",  0,      0,      0ull,   0ull},
51863         {"RESERVED_3_31"               ,        3,      29,     926,    "RAZ",  1,      1,      0,      0},
51864         {"XFERCOMPL"                   ,        0,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51865         {"CHHLTD"                      ,        1,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51866         {"AHBERR"                      ,        2,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51867         {"STALL"                       ,        3,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51868         {"NAK"                         ,        4,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51869         {"ACK"                         ,        5,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51870         {"NYET"                        ,        6,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51871         {"XACTERR"                     ,        7,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51872         {"BBLERR"                      ,        8,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51873         {"FRMOVRUN"                    ,        9,      1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51874         {"DATATGLERR"                  ,        10,     1,      927,    "R/W1C",        0,      0,      0ull,   0ull},
51875         {"RESERVED_11_31"              ,        11,     21,     927,    "RAZ",  1,      1,      0,      0},
51876         {"XFERCOMPLMSK"                ,        0,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51877         {"CHHLTDMSK"                   ,        1,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51878         {"AHBERRMSK"                   ,        2,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51879         {"STALLMSK"                    ,        3,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51880         {"NAKMSK"                      ,        4,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51881         {"ACKMSK"                      ,        5,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51882         {"NYETMSK"                     ,        6,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51883         {"XACTERRMSK"                  ,        7,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51884         {"BBLERRMSK"                   ,        8,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51885         {"FRMOVRUNMSK"                 ,        9,      1,      928,    "R/W",  0,      0,      0ull,   0ull},
51886         {"DATATGLERRMSK"               ,        10,     1,      928,    "R/W",  0,      0,      0ull,   0ull},
51887         {"RESERVED_11_31"              ,        11,     21,     928,    "RAZ",  1,      1,      0,      0},
51888         {"PRTADDR"                     ,        0,      7,      929,    "R/W",  0,      0,      0ull,   0ull},
51889         {"HUBADDR"                     ,        7,      7,      929,    "R/W",  0,      0,      0ull,   0ull},
51890         {"XACTPOS"                     ,        14,     2,      929,    "R/W",  0,      0,      0ull,   0ull},
51891         {"COMPSPLT"                    ,        16,     1,      929,    "R/W",  0,      0,      0ull,   0ull},
51892         {"RESERVED_17_30"              ,        17,     14,     929,    "RAZ",  1,      1,      0,      0},
51893         {"SPLTENA"                     ,        31,     1,      929,    "R/W",  0,      0,      0ull,   0ull},
51894         {"XFERSIZE"                    ,        0,      19,     930,    "R/W",  0,      0,      0ull,   0ull},
51895         {"PKTCNT"                      ,        19,     10,     930,    "R/W",  0,      0,      0ull,   0ull},
51896         {"PID"                         ,        29,     2,      930,    "R/W",  0,      0,      0ull,   0ull},
51897         {"DOPNG"                       ,        31,     1,      930,    "R/W",  0,      0,      0ull,   0ull},
51898         {"FRINT"                       ,        0,      16,     931,    "R/W",  0,      0,      2959ull,        3750ull},
51899         {"RESERVED_16_31"              ,        16,     16,     931,    "RAZ",  1,      1,      0,      0},
51900         {"FRNUM"                       ,        0,      16,     932,    "RO",   0,      0,      16383ull,       0ull},
51901         {"FRREM"                       ,        16,     16,     932,    "RO",   0,      0,      0ull,   0ull},
51902         {"PRTCONNSTS"                  ,        0,      1,      933,    "RO",   0,      0,      0ull,   0ull},
51903         {"PRTCONNDET"                  ,        1,      1,      933,    "R/W1C",        0,      0,      0ull,   0ull},
51904         {"PRTENA"                      ,        2,      1,      933,    "R/W1C",        0,      0,      0ull,   0ull},
51905         {"PRTENCHNG"                   ,        3,      1,      933,    "R/W1C",        0,      0,      0ull,   0ull},
51906         {"PRTOVRCURRACT"               ,        4,      1,      933,    "RO",   0,      0,      0ull,   0ull},
51907         {"PRTOVRCURRCHNG"              ,        5,      1,      933,    "R/W1C",        0,      0,      0ull,   0ull},
51908         {"PRTRES"                      ,        6,      1,      933,    "R/W",  0,      0,      0ull,   0ull},
51909         {"PRTSUSP"                     ,        7,      1,      933,    "R/W",  0,      0,      0ull,   0ull},
51910         {"PRTRST"                      ,        8,      1,      933,    "R/W",  0,      0,      0ull,   0ull},
51911         {"RESERVED_9_9"                ,        9,      1,      933,    "RAZ",  1,      1,      0,      0},
51912         {"PRTLNSTS"                    ,        10,     2,      933,    "RO",   0,      0,      0ull,   0ull},
51913         {"PRTPWR"                      ,        12,     1,      933,    "R/W",  0,      0,      0ull,   0ull},
51914         {"PRTTSTCTL"                   ,        13,     4,      933,    "R/W",  0,      0,      0ull,   0ull},
51915         {"PRTSPD"                      ,        17,     2,      933,    "RO",   0,      0,      0ull,   0ull},
51916         {"RESERVED_19_31"              ,        19,     13,     933,    "RAZ",  1,      1,      0,      0},
51917         {"PTXFSTADDR"                  ,        0,      16,     934,    "R/W",  0,      0,      3648ull,        912ull},
51918         {"PTXFSIZE"                    ,        16,     16,     934,    "R/W",  0,      0,      256ull, 456ull},
51919         {"PTXFSPCAVAIL"                ,        0,      16,     935,    "RO",   0,      0,      0ull,   0ull},
51920         {"PTXQSPCAVAIL"                ,        16,     8,      935,    "RO",   0,      0,      0ull,   0ull},
51921         {"PTXQTOP"                     ,        24,     8,      935,    "RO",   0,      0,      0ull,   0ull},
51922         {"DATA"                        ,        0,      32,     936,    "R/W",  0,      0,      0ull,   0ull},
51923         {"STOPPCLK"                    ,        0,      1,      937,    "R/W",  0,      0,      0ull,   0ull},
51924         {"GATEHCLK"                    ,        1,      1,      937,    "R/W",  0,      0,      0ull,   0ull},
51925         {"PWRCLMP"                     ,        2,      1,      937,    "R/W",  0,      0,      0ull,   0ull},
51926         {"RSTPDWNMODULE"               ,        3,      1,      937,    "R/W",  0,      0,      0ull,   0ull},
51927         {"PHYSUSPENDED"                ,        4,      1,      937,    "RO",   0,      0,      0ull,   0ull},
51928         {"RESERVED_5_31"               ,        5,      27,     937,    "RAZ",  1,      1,      0,      0},
51929         {"NOF_BIS"                     ,        0,      1,      938,    "RO",   0,      0,      0ull,   0ull},
51930         {"NIF_BIS"                     ,        1,      1,      938,    "RO",   0,      0,      0ull,   0ull},
51931         {"USBC_BIS"                    ,        2,      1,      938,    "RO",   0,      0,      0ull,   0ull},
51932         {"N2UF_BIS"                    ,        3,      1,      938,    "RO",   0,      0,      0ull,   0ull},
51933         {"E2HC_BIS"                    ,        4,      1,      938,    "RO",   0,      0,      0ull,   0ull},
51934         {"U2NF_BIS"                    ,        5,      1,      938,    "RO",   0,      0,      0ull,   0ull},
51935         {"U2NC_BIS"                    ,        6,      1,      938,    "RO",   0,      0,      0ull,   0ull},
51936         {"RESERVED_7_63"               ,        7,      57,     938,    "RAZ",  1,      1,      0,      0},
51937         {"DIVIDE"                      ,        0,      3,      939,    "R/W",  0,      0,      4ull,   0ull},
51938         {"HRST"                        ,        3,      1,      939,    "R/W",  0,      0,      0ull,   1ull},
51939         {"PRST"                        ,        4,      1,      939,    "R/W",  0,      0,      0ull,   1ull},
51940         {"ENABLE"                      ,        5,      1,      939,    "R/W",  0,      0,      1ull,   1ull},
51941         {"POR"                         ,        6,      1,      939,    "R/W",  0,      0,      1ull,   0ull},
51942         {"S_BIST"                      ,        7,      1,      939,    "R/W",  0,      0,      0ull,   1ull},
51943         {"SD_MODE"                     ,        8,      2,      939,    "R/W",  0,      0,      0ull,   0ull},
51944         {"CDIV_BYP"                    ,        10,     1,      939,    "R/W",  0,      0,      0ull,   0ull},
51945         {"P_C_SEL"                     ,        11,     2,      939,    "R/W",  0,      0,      2ull,   0ull},
51946         {"P_COM_ON"                    ,        13,     1,      939,    "R/W",  0,      0,      1ull,   1ull},
51947         {"P_RTYPE"                     ,        14,     2,      939,    "R/W",  0,      0,      0ull,   0ull},
51948         {"RESERVED_16_16"              ,        16,     1,      939,    "RAZ",  1,      1,      0,      0},
51949         {"HCLK_RST"                    ,        17,     1,      939,    "R/W",  0,      0,      1ull,   1ull},
51950         {"DIVIDE2"                     ,        18,     2,      939,    "R/W",  0,      0,      0ull,   1ull},
51951         {"RESERVED_20_63"              ,        20,     44,     939,    "RAZ",  1,      1,      0,      0},
51952         {"L2C_EMOD"                    ,        0,      2,      940,    "R/W",  0,      0,      1ull,   1ull},
51953         {"INV_A2"                      ,        2,      1,      940,    "R/W",  0,      0,      0ull,   0ull},
51954         {"DMA_TEST"                    ,        3,      1,      940,    "R/W",  0,      0,      0ull,   0ull},
51955         {"DMA_STT"                     ,        4,      1,      940,    "R/W",  0,      0,      0ull,   0ull},
51956         {"DMA_0PAG"                    ,        5,      1,      940,    "R/W",  0,      0,      0ull,   0ull},
51957         {"RESERVED_6_63"               ,        6,      58,     940,    "RAZ",  1,      1,      0,      0},
51958         {"ADDR"                        ,        0,      36,     941,    "R/W",  0,      1,      0ull,   0},
51959         {"RESERVED_36_63"              ,        36,     28,     941,    "RAZ",  1,      1,      0,      0},
51960         {"ADDR"                        ,        0,      36,     942,    "R/W",  0,      1,      0ull,   0},
51961         {"RESERVED_36_63"              ,        36,     28,     942,    "RAZ",  1,      1,      0,      0},
51962         {"ADDR"                        ,        0,      36,     943,    "R/W",  0,      1,      0ull,   0},
51963         {"RESERVED_36_63"              ,        36,     28,     943,    "RAZ",  1,      1,      0,      0},
51964         {"ADDR"                        ,        0,      36,     944,    "R/W",  0,      1,      0ull,   0},
51965         {"RESERVED_36_63"              ,        36,     28,     944,    "RAZ",  1,      1,      0,      0},
51966         {"ADDR"                        ,        0,      36,     945,    "R/W",  0,      1,      0ull,   0},
51967         {"RESERVED_36_63"              ,        36,     28,     945,    "RAZ",  1,      1,      0,      0},
51968         {"ADDR"                        ,        0,      36,     946,    "R/W",  0,      1,      0ull,   0},
51969         {"RESERVED_36_63"              ,        36,     28,     946,    "RAZ",  1,      1,      0,      0},
51970         {"ADDR"                        ,        0,      36,     947,    "R/W",  0,      1,      0ull,   0},
51971         {"RESERVED_36_63"              ,        36,     28,     947,    "RAZ",  1,      1,      0,      0},
51972         {"ADDR"                        ,        0,      36,     948,    "R/W",  0,      1,      0ull,   0},
51973         {"RESERVED_36_63"              ,        36,     28,     948,    "RAZ",  1,      1,      0,      0},
51974         {"ADDR"                        ,        0,      36,     949,    "R/W",  0,      1,      0ull,   0},
51975         {"RESERVED_36_63"              ,        36,     28,     949,    "RAZ",  1,      1,      0,      0},
51976         {"ADDR"                        ,        0,      36,     950,    "R/W",  0,      1,      0ull,   0},
51977         {"RESERVED_36_63"              ,        36,     28,     950,    "RAZ",  1,      1,      0,      0},
51978         {"ADDR"                        ,        0,      36,     951,    "R/W",  0,      1,      0ull,   0},
51979         {"RESERVED_36_63"              ,        36,     28,     951,    "RAZ",  1,      1,      0,      0},
51980         {"ADDR"                        ,        0,      36,     952,    "R/W",  0,      1,      0ull,   0},
51981         {"RESERVED_36_63"              ,        36,     28,     952,    "RAZ",  1,      1,      0,      0},
51982         {"ADDR"                        ,        0,      36,     953,    "R/W",  0,      1,      0ull,   0},
51983         {"RESERVED_36_63"              ,        36,     28,     953,    "RAZ",  1,      1,      0,      0},
51984         {"ADDR"                        ,        0,      36,     954,    "R/W",  0,      1,      0ull,   0},
51985         {"RESERVED_36_63"              ,        36,     28,     954,    "RAZ",  1,      1,      0,      0},
51986         {"ADDR"                        ,        0,      36,     955,    "R/W",  0,      1,      0ull,   0},
51987         {"RESERVED_36_63"              ,        36,     28,     955,    "RAZ",  1,      1,      0,      0},
51988         {"ADDR"                        ,        0,      36,     956,    "R/W",  0,      1,      0ull,   0},
51989         {"RESERVED_36_63"              ,        36,     28,     956,    "RAZ",  1,      1,      0,      0},
51990         {"BURST"                       ,        0,      4,      957,    "R/W",  0,      0,      0ull,   0ull},
51991         {"CHANNEL"                     ,        4,      5,      957,    "R/W",  0,      0,      0ull,   0ull},
51992         {"COUNT"                       ,        9,      11,     957,    "R/W",  0,      0,      0ull,   0ull},
51993         {"F_ADDR"                      ,        20,     18,     957,    "R/W",  0,      0,      0ull,   0ull},
51994         {"REQ"                         ,        38,     1,      957,    "R/W1C",        0,      0,      0ull,   0ull},
51995         {"DONE"                        ,        39,     1,      957,    "R/W1C",        0,      0,      0ull,   0ull},
51996         {"RESERVED_40_63"              ,        40,     24,     957,    "RAZ",  1,      1,      0,      0},
51997         {"PR_PO_E"                     ,        0,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
51998         {"PR_PU_F"                     ,        1,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
51999         {"NR_PO_E"                     ,        2,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
52000         {"NR_PU_F"                     ,        3,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
52001         {"LR_PO_E"                     ,        4,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
52002         {"LR_PU_F"                     ,        5,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
52003         {"PT_PO_E"                     ,        6,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
52004         {"PT_PU_F"                     ,        7,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
52005         {"NT_PO_E"                     ,        8,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
52006         {"NT_PU_F"                     ,        9,      1,      958,    "R/W",  0,      0,      0ull,   0ull},
52007         {"LT_PO_E"                     ,        10,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52008         {"LT_PU_F"                     ,        11,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52009         {"DCRED_E"                     ,        12,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52010         {"DCRED_F"                     ,        13,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52011         {"L2C_S_E"                     ,        14,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52012         {"L2C_A_F"                     ,        15,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52013         {"L2_FI_E"                     ,        16,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52014         {"L2_FI_F"                     ,        17,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52015         {"RG_FI_E"                     ,        18,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52016         {"RG_FI_F"                     ,        19,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52017         {"RQ_Q2_F"                     ,        20,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52018         {"RQ_Q2_E"                     ,        21,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52019         {"RQ_Q3_F"                     ,        22,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52020         {"RQ_Q3_E"                     ,        23,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52021         {"UOD_PE"                      ,        24,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52022         {"UOD_PF"                      ,        25,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52023         {"RESERVED_26_31"              ,        26,     6,      958,    "RAZ",  0,      0,      0ull,   0ull},
52024         {"LTL_F_PE"                    ,        32,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52025         {"LTL_F_PF"                    ,        33,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52026         {"ND4O_RPE"                    ,        34,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52027         {"ND4O_RPF"                    ,        35,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52028         {"ND4O_DPE"                    ,        36,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52029         {"ND4O_DPF"                    ,        37,     1,      958,    "R/W",  0,      0,      0ull,   0ull},
52030         {"RESERVED_38_63"              ,        38,     26,     958,    "RAZ",  1,      1,      0,      0},
52031         {"PR_PO_E"                     ,        0,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52032         {"PR_PU_F"                     ,        1,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52033         {"NR_PO_E"                     ,        2,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52034         {"NR_PU_F"                     ,        3,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52035         {"LR_PO_E"                     ,        4,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52036         {"LR_PU_F"                     ,        5,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52037         {"PT_PO_E"                     ,        6,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52038         {"PT_PU_F"                     ,        7,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52039         {"NT_PO_E"                     ,        8,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52040         {"NT_PU_F"                     ,        9,      1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52041         {"LT_PO_E"                     ,        10,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52042         {"LT_PU_F"                     ,        11,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52043         {"DCRED_E"                     ,        12,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52044         {"DCRED_F"                     ,        13,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52045         {"L2C_S_E"                     ,        14,     1,      959,    "R/W1C",        1,      0,      0,      0ull},
52046         {"L2C_A_F"                     ,        15,     1,      959,    "R/W1C",        1,      0,      0,      0ull},
52047         {"LT_FI_E"                     ,        16,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52048         {"LT_FI_F"                     ,        17,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52049         {"RG_FI_E"                     ,        18,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52050         {"RG_FI_F"                     ,        19,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52051         {"RQ_Q2_F"                     ,        20,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52052         {"RQ_Q2_E"                     ,        21,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52053         {"RQ_Q3_F"                     ,        22,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52054         {"RQ_Q3_E"                     ,        23,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52055         {"UOD_PE"                      ,        24,     1,      959,    "R/W1C",        1,      0,      0,      0ull},
52056         {"UOD_PF"                      ,        25,     1,      959,    "R/W1C",        1,      0,      0,      0ull},
52057         {"RESERVED_26_31"              ,        26,     6,      959,    "RAZ",  1,      0,      0,      0ull},
52058         {"LTL_F_PE"                    ,        32,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52059         {"LTL_F_PF"                    ,        33,     1,      959,    "R/W1C",        0,      0,      0ull,   0ull},
52060         {"ND4O_RPE"                    ,        34,     1,      959,    "R/W1C",        1,      0,      0,      0ull},
52061         {"ND4O_RPF"                    ,        35,     1,      959,    "R/W1C",        1,      0,      0,      0ull},
52062         {"ND4O_DPE"                    ,        36,     1,      959,    "R/W1C",        1,      0,      0,      0ull},
52063         {"ND4O_DPF"                    ,        37,     1,      959,    "R/W1C",        1,      0,      0,      0ull},
52064         {"RESERVED_38_63"              ,        38,     26,     959,    "RAZ",  1,      1,      0,      0},
52065         {"ATE_RESET"                   ,        0,      1,      960,    "R/W",  0,      0,      0ull,   0ull},
52066         {"TDATA_IN"                    ,        1,      8,      960,    "R/W",  0,      0,      0ull,   0ull},
52067         {"TADDR_IN"                    ,        9,      4,      960,    "R/W",  0,      0,      0ull,   0ull},
52068         {"TDATA_SEL"                   ,        13,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52069         {"BIST_ENB"                    ,        14,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52070         {"VTEST_ENB"                   ,        15,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52071         {"LOOP_ENB"                    ,        16,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52072         {"TX_BS_EN"                    ,        17,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52073         {"TX_BS_ENH"                   ,        18,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52074         {"RESERVED_19_22"              ,        19,     4,      960,    "RAZ",  0,      0,      0ull,   0ull},
52075         {"HST_MODE"                    ,        23,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52076         {"DM_PULLD"                    ,        24,     1,      960,    "R/W",  0,      0,      1ull,   1ull},
52077         {"DP_PULLD"                    ,        25,     1,      960,    "R/W",  0,      0,      1ull,   1ull},
52078         {"TCLK"                        ,        26,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52079         {"USBP_BIST"                   ,        27,     1,      960,    "R/W",  0,      0,      1ull,   1ull},
52080         {"USBC_END"                    ,        28,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52081         {"DMA_BMODE"                   ,        29,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52082         {"TXPREEMPHASISTUNE"           ,        30,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52083         {"SIDDQ"                       ,        31,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52084         {"TDATA_OUT"                   ,        32,     4,      960,    "RO",   1,      1,      0,      0},
52085         {"BIST_ERR"                    ,        36,     1,      960,    "RO",   0,      0,      0ull,   0ull},
52086         {"BIST_DONE"                   ,        37,     1,      960,    "RO",   0,      0,      0ull,   0ull},
52087         {"HSBIST"                      ,        38,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52088         {"FSBIST"                      ,        39,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52089         {"LSBIST"                      ,        40,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52090         {"DRVVBUS"                     ,        41,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52091         {"PORTRESET"                   ,        42,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52092         {"OTGDISABLE"                  ,        43,     1,      960,    "R/W",  0,      0,      1ull,   1ull},
52093         {"OTGTUNE"                     ,        44,     3,      960,    "R/W",  0,      0,      2ull,   2ull},
52094         {"COMPDISTUNE"                 ,        47,     3,      960,    "R/W",  0,      0,      2ull,   2ull},
52095         {"SQRXTUNE"                    ,        50,     3,      960,    "R/W",  0,      0,      3ull,   3ull},
52096         {"TXHSXVTUNE"                  ,        53,     2,      960,    "R/W",  0,      0,      0ull,   0ull},
52097         {"TXFSLSTUNE"                  ,        55,     4,      960,    "R/W",  0,      0,      3ull,   3ull},
52098         {"TXVREFTUNE"                  ,        59,     4,      960,    "R/W",  0,      0,      7ull,   7ull},
52099         {"TXRISETUNE"                  ,        63,     1,      960,    "R/W",  0,      0,      0ull,   0ull},
52100         {"ZIP_CTL"                     ,        0,      4,      961,    "RO",   1,      0,      0,      0ull},
52101         {"ZIP_CORE"                    ,        4,      27,     961,    "RO",   1,      0,      0,      0ull},
52102         {"RESERVED_31_63"              ,        31,     33,     961,    "RAZ",  1,      0,      0,      0ull},
52103         {"PTR"                         ,        0,      33,     962,    "R/W",  0,      0,      0ull,   0ull},
52104         {"SIZE"                        ,        33,     13,     962,    "R/W",  0,      0,      0ull,   0ull},
52105         {"POOL"                        ,        46,     3,      962,    "R/W",  0,      0,      0ull,   0ull},
52106         {"DWB"                         ,        49,     9,      962,    "R/W",  0,      0,      0ull,   0ull},
52107         {"RESERVED_58_63"              ,        58,     6,      962,    "RAZ",  0,      0,      0ull,   0ull},
52108         {"RESET"                       ,        0,      1,      963,    "RAZ",  0,      0,      0ull,   0ull},
52109         {"FORCECLK"                    ,        1,      1,      963,    "R/W",  0,      0,      0ull,   0ull},
52110         {"RESERVED_2_63"               ,        2,      62,     963,    "RAZ",  0,      0,      0ull,   0ull},
52111         {"DISABLED"                    ,        0,      1,      964,    "RO",   0,      0,      0ull,   0ull},
52112         {"RESERVED_1_7"                ,        1,      7,      964,    "RAZ",  0,      0,      0ull,   0ull},
52113         {"CTXSIZE"                     ,        8,      12,     964,    "RO",   0,      0,      1536ull,        1536ull},
52114         {"ONFSIZE"                     ,        20,     12,     964,    "RO",   0,      0,      512ull, 512ull},
52115         {"DEPTH"                       ,        32,     16,     964,    "RO",   0,      0,      31744ull,       31744ull},
52116         {"RESERVED_48_63"              ,        48,     16,     964,    "RAZ",  1,      0,      0,      0ull},
52117         {"ASSERTS"                     ,        0,      14,     965,    "RO",   0,      0,      0ull,   0ull},
52118         {"RESERVED_14_63"              ,        14,     50,     965,    "RAZ",  1,      0,      0,      0ull},
52119         {"DOORBELL"                    ,        0,      1,      966,    "R/W1C",        0,      0,      0ull,   0ull},
52120         {"RESERVED_1_63"               ,        1,      63,     966,    "RAZ",  1,      0,      0,      0ull},
52121         {"DOORBELL"                    ,        0,      1,      967,    "R/W",  0,      0,      0ull,   0ull},
52122         {"RESERVED_1_63"               ,        1,      63,     967,    "RAZ",  1,      0,      0,      0ull},
52123         {NULL,0,0,0,0,0,0,0,0}
52124 };
52125 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn50xx[] = {
52126          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
52127         {"cvmx_asx#_gmii_rx_clk_set"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      2,      0},
52128         {"cvmx_asx#_gmii_rx_dat_set"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1,      2,      2},
52129         {"cvmx_asx#_int_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      6,      4},
52130         {"cvmx_asx#_int_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     3,      6,      10},
52131         {"cvmx_asx#_mii_rx_dat_set"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      2,      16},
52132         {"cvmx_asx#_prt_loop"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     5,      4,      18},
52133         {"cvmx_asx#_rx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      2,      22},
52134         {"cvmx_asx#_rx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     9,      2,      24},
52135         {"cvmx_asx#_tx_clk_set#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     2,      26},
52136         {"cvmx_asx#_tx_comp_byp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     13,     6,      28},
52137         {"cvmx_asx#_tx_hi_water#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     2,      34},
52138         {"cvmx_asx#_tx_prt_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     17,     2,      36},
52139         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     18,     2,      38},
52140         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     19,     2,      40},
52141         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     20,     2,      42},
52142         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     21,     2,      44},
52143         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     22,     19,     46},
52144         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     27,     2,      65},
52145         {"cvmx_ciu_int#_en4_0"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     32,     19,     67},
52146         {"cvmx_ciu_int#_en4_1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     34,     2,      86},
52147         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     36,     19,     88},
52148         {"cvmx_ciu_int#_sum4"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     41,     19,     107},
52149         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     43,     2,      126},
52150         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     44,     2,      128},
52151         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     46,     2,      130},
52152         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     48,     2,      132},
52153         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     49,     2,      134},
52154         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     50,     2,      136},
52155         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     51,     1,      138},
52156         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     53,     3,      139},
52157         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     54,     2,      142},
52158         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     55,     4,      144},
52159         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     56,     2,      148},
52160         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     57,     3,      150},
52161         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     61,     7,      153},
52162         {"cvmx_dbg_data"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     63,     6,      160},
52163         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     64,     6,      166},
52164         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     65,     7,      172},
52165         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     66,     29,     179},
52166         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     67,     29,     208},
52167         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     68,     2,      237},
52168         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     76,     2,      239},
52169         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     84,     3,      241},
52170         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     85,     3,      244},
52171         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     86,     2,      247},
52172         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     87,     2,      249},
52173         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     88,     8,      251},
52174         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     89,     2,      259},
52175         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     90,     4,      261},
52176         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     91,     2,      265},
52177         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     92,     5,      267},
52178         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     95,     1,      272},
52179         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     98,     1,      273},
52180         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     101,    1,      274},
52181         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     104,    1,      275},
52182         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     107,    1,      276},
52183         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     110,    1,      277},
52184         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     113,    2,      278},
52185         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     116,    4,      280},
52186         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     119,    2,      284},
52187         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     122,    11,     286},
52188         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     125,    11,     297},
52189         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     128,    2,      308},
52190         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     131,    21,     310},
52191         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     134,    21,     331},
52192         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     137,    2,      352},
52193         {"cvmx_gmx#_rx#_pause_drop_time",       CVMX_CSR_DB_TYPE_RSL,   64,     140,    2,      354},
52194         {"cvmx_gmx#_rx#_rx_inbnd"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     143,    4,      356},
52195         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     146,    2,      360},
52196         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     149,    2,      362},
52197         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     152,    2,      364},
52198         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     155,    2,      366},
52199         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     158,    2,      368},
52200         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     161,    2,      370},
52201         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     164,    2,      372},
52202         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     167,    2,      374},
52203         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     170,    2,      376},
52204         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     173,    2,      378},
52205         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     176,    4,      380},
52206         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     179,    2,      384},
52207         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     182,    2,      386},
52208         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     185,    2,      388},
52209         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     188,    4,      390},
52210         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     189,    2,      394},
52211         {"cvmx_gmx#_rx_tx_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     190,    4,      396},
52212         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     191,    2,      400},
52213         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     194,    3,      402},
52214         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     195,    5,      405},
52215         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     198,    2,      410},
52216         {"cvmx_gmx#_tx#_clk"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     201,    2,      412},
52217         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     204,    3,      414},
52218         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     207,    2,      417},
52219         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     210,    2,      419},
52220         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     213,    2,      421},
52221         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     216,    2,      423},
52222         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     219,    2,      425},
52223         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     222,    2,      427},
52224         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     225,    2,      429},
52225         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     228,    2,      431},
52226         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     231,    2,      433},
52227         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     234,    2,      435},
52228         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     237,    2,      437},
52229         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     240,    2,      439},
52230         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     243,    2,      441},
52231         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     246,    2,      443},
52232         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     249,    2,      445},
52233         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     252,    2,      447},
52234         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     255,    2,      449},
52235         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     258,    2,      451},
52236         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     261,    2,      453},
52237         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     264,    2,      455},
52238         {"cvmx_gmx#_tx_clk_msk#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     265,    2,      457},
52239         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     267,    2,      459},
52240         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     268,    2,      461},
52241         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     269,    3,      463},
52242         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     270,    10,     466},
52243         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     271,    10,     476},
52244         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     272,    2,      486},
52245         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     273,    2,      488},
52246         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     274,    6,      490},
52247         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     275,    2,      496},
52248         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     276,    2,      498},
52249         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     277,    2,      500},
52250         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     278,    7,      502},
52251         {"cvmx_gpio_boot_ena"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     294,    3,      509},
52252         {"cvmx_gpio_dbg_ena"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     295,    2,      512},
52253         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     296,    2,      514},
52254         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     297,    2,      516},
52255         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     298,    2,      518},
52256         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     299,    2,      520},
52257         {"cvmx_gpio_xbit_cfg#"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     300,    6,      522},
52258         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     308,    19,     528},
52259         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     309,    6,      547},
52260         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     310,    3,      553},
52261         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     311,    5,      556},
52262         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     312,    5,      561},
52263         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     313,    1,      566},
52264         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     314,    1,      567},
52265         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     315,    7,      568},
52266         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     316,    7,      575},
52267         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     317,    5,      582},
52268         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     318,    5,      587},
52269         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     319,    1,      592},
52270         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     320,    1,      593},
52271         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     321,    2,      594},
52272         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     322,    2,      596},
52273         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     323,    2,      598},
52274         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     324,    2,      600},
52275         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     325,    17,     602},
52276         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     326,    2,      619},
52277         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     327,    1,      621},
52278         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     328,    15,     622},
52279         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     329,    11,     637},
52280         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     330,    11,     648},
52281         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     331,    2,      659},
52282         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     332,    2,      661},
52283         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     333,    2,      663},
52284         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     334,    3,      665},
52285         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     339,    2,      668},
52286         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     344,    6,      670},
52287         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     345,    5,      676},
52288         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     346,    6,      681},
52289         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     347,    7,      687},
52290         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     348,    2,      694},
52291         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     356,    2,      696},
52292         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     357,    3,      698},
52293         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     358,    5,      701},
52294         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     366,    3,      706},
52295         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     367,    2,      709},
52296         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     368,    2,      711},
52297         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     369,    2,      713},
52298         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     370,    8,      715},
52299         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     371,    5,      723},
52300         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     372,    8,      728},
52301         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     373,    12,     736},
52302         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     374,    9,      748},
52303         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     375,    5,      757},
52304         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     376,    4,      762},
52305         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     377,    2,      766},
52306         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     378,    16,     768},
52307         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     379,    19,     784},
52308         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     380,    3,      803},
52309         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     381,    4,      806},
52310         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     382,    2,      810},
52311         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     386,    17,     812},
52312         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     387,    3,      829},
52313         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     388,    2,      832},
52314         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     389,    3,      834},
52315         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     390,    2,      837},
52316         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     391,    2,      839},
52317         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     392,    2,      841},
52318         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     393,    7,      843},
52319         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     394,    5,      850},
52320         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     395,    3,      855},
52321         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     396,    3,      858},
52322         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     397,    2,      861},
52323         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     398,    2,      863},
52324         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     399,    2,      865},
52325         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     400,    6,      867},
52326         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     401,    14,     873},
52327         {"cvmx_lmc#_bist_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     402,    2,      887},
52328         {"cvmx_lmc#_bist_result"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     403,    6,      889},
52329         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     404,    7,      895},
52330         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     405,    20,     902},
52331         {"cvmx_lmc#_ctl1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     406,    5,      922},
52332         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     407,    2,      927},
52333         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     408,    2,      929},
52334         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     409,    18,     931},
52335         {"cvmx_lmc#_delay_cfg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     410,    6,      949},
52336         {"cvmx_lmc#_dual_memcfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     411,    5,      955},
52337         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     412,    5,      960},
52338         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     413,    6,      965},
52339         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     414,    2,      971},
52340         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     415,    2,      973},
52341         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     416,    14,     975},
52342         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     417,    10,     989},
52343         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     418,    2,      999},
52344         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     419,    2,      1001},
52345         {"cvmx_lmc#_pll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     420,    13,     1003},
52346         {"cvmx_lmc#_pll_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     421,    6,      1016},
52347         {"cvmx_lmc#_rodt_comp_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     422,    6,      1022},
52348         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     423,    9,      1028},
52349         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     424,    9,      1037},
52350         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     425,    7,      1046},
52351         {"cvmx_mio_boot_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     426,    3,      1053},
52352         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     427,    3,      1056},
52353         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     428,    3,      1059},
52354         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     429,    3,      1062},
52355         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     430,    5,      1065},
52356         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     432,    1,      1070},
52357         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     433,    12,     1071},
52358         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     441,    13,     1083},
52359         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     449,    4,      1096},
52360         {"cvmx_mio_fus_bnk_dat#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     450,    1,      1100},
52361         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     454,    2,      1101},
52362         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     455,    2,      1103},
52363         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     456,    13,     1105},
52364         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     457,    8,      1118},
52365         {"cvmx_mio_fus_ema"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     458,    4,      1126},
52366         {"cvmx_mio_fus_pdf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     459,    1,      1130},
52367         {"cvmx_mio_fus_pll"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     460,    3,      1131},
52368         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     461,    2,      1134},
52369         {"cvmx_mio_fus_prog_times"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     462,    6,      1136},
52370         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     463,    8,      1142},
52371         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     464,    4,      1150},
52372         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     465,    2,      1154},
52373         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     466,    2,      1156},
52374         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     467,    13,     1158},
52375         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     468,    12,     1171},
52376         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     469,    3,      1183},
52377         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     470,    3,      1186},
52378         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     471,    2,      1189},
52379         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     473,    2,      1191},
52380         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     475,    2,      1193},
52381         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     477,    7,      1195},
52382         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     479,    2,      1202},
52383         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     481,    7,      1204},
52384         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     483,    4,      1211},
52385         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     485,    8,      1215},
52386         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     487,    9,      1223},
52387         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     489,    7,      1232},
52388         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     491,    9,      1239},
52389         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     493,    2,      1248},
52390         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     495,    2,      1250},
52391         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     497,    4,      1252},
52392         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     499,    2,      1256},
52393         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     501,    2,      1258},
52394         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     503,    2,      1260},
52395         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     505,    4,      1262},
52396         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     507,    2,      1266},
52397         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     509,    2,      1268},
52398         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     511,    2,      1270},
52399         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     513,    2,      1272},
52400         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     515,    2,      1274},
52401         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     517,    2,      1276},
52402         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     519,    6,      1278},
52403         {"cvmx_mpi_cfg"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     521,    14,     1284},
52404         {"cvmx_mpi_dat#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     522,    2,      1298},
52405         {"cvmx_mpi_sts"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     531,    4,      1300},
52406         {"cvmx_mpi_tx"                 ,        CVMX_CSR_DB_TYPE_NCB,   64,     532,    6,      1304},
52407         {"cvmx_npi_base_addr_input#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     533,    2,      1310},
52408         {"cvmx_npi_base_addr_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     535,    2,      1312},
52409         {"cvmx_npi_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     537,    20,     1314},
52410         {"cvmx_npi_buff_size_output#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     538,    3,      1334},
52411         {"cvmx_npi_comp_ctl"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     540,    3,      1337},
52412         {"cvmx_npi_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     541,    18,     1340},
52413         {"cvmx_npi_dbg_select"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     542,    2,      1358},
52414         {"cvmx_npi_dma_control"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     543,    13,     1360},
52415         {"cvmx_npi_dma_highp_counts"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     544,    3,      1373},
52416         {"cvmx_npi_dma_highp_naddr"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     545,    3,      1376},
52417         {"cvmx_npi_dma_lowp_counts"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     546,    3,      1379},
52418         {"cvmx_npi_dma_lowp_naddr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     547,    3,      1382},
52419         {"cvmx_npi_highp_dbell"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     548,    2,      1385},
52420         {"cvmx_npi_highp_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     549,    2,      1387},
52421         {"cvmx_npi_input_control"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     550,    10,     1389},
52422         {"cvmx_npi_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     551,    54,     1399},
52423         {"cvmx_npi_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     552,    54,     1453},
52424         {"cvmx_npi_lowp_dbell"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     553,    2,      1507},
52425         {"cvmx_npi_lowp_ibuff_saddr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     554,    2,      1509},
52426         {"cvmx_npi_mem_access_subid#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     555,    10,     1511},
52427         {"cvmx_npi_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     559,    1,      1521},
52428         {"cvmx_npi_num_desc_output#"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     560,    2,      1522},
52429         {"cvmx_npi_output_control"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     562,    25,     1524},
52430         {"cvmx_npi_p#_dbpair_addr"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     563,    3,      1549},
52431         {"cvmx_npi_p#_instr_addr"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     565,    2,      1552},
52432         {"cvmx_npi_p#_instr_cnts"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     567,    3,      1554},
52433         {"cvmx_npi_p#_pair_cnts"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     569,    3,      1557},
52434         {"cvmx_npi_pci_burst_size"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     571,    3,      1560},
52435         {"cvmx_npi_pci_int_arb_cfg"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     572,    7,      1563},
52436         {"cvmx_npi_pci_read_cmd"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     573,    2,      1570},
52437         {"cvmx_npi_port32_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     574,    13,     1572},
52438         {"cvmx_npi_port33_instr_hdr"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     575,    13,     1585},
52439         {"cvmx_npi_port_bp_control"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     576,    3,      1598},
52440         {"cvmx_npi_rsl_int_blocks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     577,    29,     1601},
52441         {"cvmx_npi_size_input#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     578,    2,      1630},
52442         {"cvmx_npi_win_read_to"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     580,    2,      1632},
52443         {"cvmx_pci_bar1_index#"        ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     581,    5,      1634},
52444         {"cvmx_pci_bist_reg"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     613,    11,     1639},
52445         {"cvmx_pci_cfg00"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     614,    2,      1650},
52446         {"cvmx_pci_cfg01"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     615,    24,     1652},
52447         {"cvmx_pci_cfg02"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     616,    2,      1676},
52448         {"cvmx_pci_cfg03"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     617,    7,      1678},
52449         {"cvmx_pci_cfg04"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     618,    5,      1685},
52450         {"cvmx_pci_cfg05"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     619,    1,      1690},
52451         {"cvmx_pci_cfg06"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     620,    5,      1691},
52452         {"cvmx_pci_cfg07"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     621,    1,      1696},
52453         {"cvmx_pci_cfg08"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     622,    4,      1697},
52454         {"cvmx_pci_cfg09"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     623,    2,      1701},
52455         {"cvmx_pci_cfg10"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     624,    1,      1703},
52456         {"cvmx_pci_cfg11"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     625,    2,      1704},
52457         {"cvmx_pci_cfg12"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     626,    4,      1706},
52458         {"cvmx_pci_cfg13"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     627,    2,      1710},
52459         {"cvmx_pci_cfg15"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     628,    4,      1712},
52460         {"cvmx_pci_cfg16"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     629,    16,     1716},
52461         {"cvmx_pci_cfg17"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     630,    1,      1732},
52462         {"cvmx_pci_cfg18"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     631,    1,      1733},
52463         {"cvmx_pci_cfg19"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     632,    18,     1734},
52464         {"cvmx_pci_cfg20"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     633,    1,      1752},
52465         {"cvmx_pci_cfg21"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     634,    1,      1753},
52466         {"cvmx_pci_cfg22"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     635,    7,      1754},
52467         {"cvmx_pci_cfg56"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     636,    7,      1761},
52468         {"cvmx_pci_cfg57"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     637,    13,     1768},
52469         {"cvmx_pci_cfg58"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     638,    10,     1781},
52470         {"cvmx_pci_cfg59"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     639,    10,     1791},
52471         {"cvmx_pci_cfg60"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     640,    7,      1801},
52472         {"cvmx_pci_cfg61"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     641,    2,      1808},
52473         {"cvmx_pci_cfg62"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     642,    1,      1810},
52474         {"cvmx_pci_cfg63"              ,        CVMX_CSR_DB_TYPE_PCICONFIG,     32,     643,    2,      1811},
52475         {"cvmx_pci_cnt_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     644,    6,      1813},
52476         {"cvmx_pci_ctl_status_2"       ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     645,    22,     1819},
52477         {"cvmx_pci_dbell#"             ,        CVMX_CSR_DB_TYPE_PCI,   32,     646,    2,      1841},
52478         {"cvmx_pci_dma_cnt#"           ,        CVMX_CSR_DB_TYPE_PCI,   32,     648,    1,      1843},
52479         {"cvmx_pci_dma_int_lev#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     650,    1,      1844},
52480         {"cvmx_pci_dma_time#"          ,        CVMX_CSR_DB_TYPE_PCI,   32,     652,    1,      1845},
52481         {"cvmx_pci_instr_count#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     654,    1,      1846},
52482         {"cvmx_pci_int_enb"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     656,    33,     1847},
52483         {"cvmx_pci_int_enb2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     657,    33,     1880},
52484         {"cvmx_pci_int_sum"            ,        CVMX_CSR_DB_TYPE_PCI,   64,     658,    33,     1913},
52485         {"cvmx_pci_int_sum2"           ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     659,    33,     1946},
52486         {"cvmx_pci_msi_rcv"            ,        CVMX_CSR_DB_TYPE_PCI,   32,     660,    2,      1979},
52487         {"cvmx_pci_pkt_credits#"       ,        CVMX_CSR_DB_TYPE_PCI,   32,     661,    2,      1981},
52488         {"cvmx_pci_pkts_sent#"         ,        CVMX_CSR_DB_TYPE_PCI,   32,     663,    1,      1983},
52489         {"cvmx_pci_pkts_sent_int_lev#" ,        CVMX_CSR_DB_TYPE_PCI,   32,     665,    1,      1984},
52490         {"cvmx_pci_pkts_sent_time#"    ,        CVMX_CSR_DB_TYPE_PCI,   32,     667,    1,      1985},
52491         {"cvmx_pci_read_cmd_6"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     669,    3,      1986},
52492         {"cvmx_pci_read_cmd_c"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     670,    3,      1989},
52493         {"cvmx_pci_read_cmd_e"         ,        CVMX_CSR_DB_TYPE_PCI_NCB,       32,     671,    3,      1992},
52494         {"cvmx_pci_read_timeout"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     672,    3,      1995},
52495         {"cvmx_pci_scm_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     673,    2,      1998},
52496         {"cvmx_pci_tsr_reg"            ,        CVMX_CSR_DB_TYPE_PCI_NCB,       64,     674,    2,      2000},
52497         {"cvmx_pci_win_rd_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     675,    4,      2002},
52498         {"cvmx_pci_win_rd_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     676,    1,      2006},
52499         {"cvmx_pci_win_wr_addr"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     677,    4,      2007},
52500         {"cvmx_pci_win_wr_data"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     678,    1,      2011},
52501         {"cvmx_pci_win_wr_mask"        ,        CVMX_CSR_DB_TYPE_PCI,   64,     679,    2,      2012},
52502         {"cvmx_pcm#_dma_cfg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     680,    12,     2014},
52503         {"cvmx_pcm#_int_ena"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     684,    9,      2026},
52504         {"cvmx_pcm#_int_sum"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     688,    9,      2035},
52505         {"cvmx_pcm#_rxaddr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     692,    2,      2044},
52506         {"cvmx_pcm#_rxcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     696,    2,      2046},
52507         {"cvmx_pcm#_rxmsk0"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     700,    1,      2048},
52508         {"cvmx_pcm#_rxmsk1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     704,    1,      2049},
52509         {"cvmx_pcm#_rxmsk2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     708,    1,      2050},
52510         {"cvmx_pcm#_rxmsk3"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     712,    1,      2051},
52511         {"cvmx_pcm#_rxmsk4"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     716,    1,      2052},
52512         {"cvmx_pcm#_rxmsk5"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     720,    1,      2053},
52513         {"cvmx_pcm#_rxmsk6"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     724,    1,      2054},
52514         {"cvmx_pcm#_rxmsk7"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     728,    1,      2055},
52515         {"cvmx_pcm#_rxstart"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     732,    3,      2056},
52516         {"cvmx_pcm#_tdm_cfg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     736,    6,      2059},
52517         {"cvmx_pcm#_tdm_dbg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     740,    1,      2065},
52518         {"cvmx_pcm#_txaddr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     744,    3,      2066},
52519         {"cvmx_pcm#_txcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     748,    2,      2069},
52520         {"cvmx_pcm#_txmsk0"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     752,    1,      2071},
52521         {"cvmx_pcm#_txmsk1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     756,    1,      2072},
52522         {"cvmx_pcm#_txmsk2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     760,    1,      2073},
52523         {"cvmx_pcm#_txmsk3"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     764,    1,      2074},
52524         {"cvmx_pcm#_txmsk4"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     768,    1,      2075},
52525         {"cvmx_pcm#_txmsk5"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     772,    1,      2076},
52526         {"cvmx_pcm#_txmsk6"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     776,    1,      2077},
52527         {"cvmx_pcm#_txmsk7"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     780,    1,      2078},
52528         {"cvmx_pcm#_txstart"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     784,    3,      2079},
52529         {"cvmx_pcm_clk#_cfg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     788,    12,     2082},
52530         {"cvmx_pcm_clk#_dbg"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     790,    1,      2094},
52531         {"cvmx_pcm_clk#_gen"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     792,    3,      2095},
52532         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     794,    2,      2098},
52533         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     795,    4,      2100},
52534         {"cvmx_pip_frm_len_chk#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     799,    3,      2104},
52535         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     801,    8,      2107},
52536         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     802,    16,     2115},
52537         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     803,    13,     2131},
52538         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     804,    13,     2144},
52539         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     805,    2,      2157},
52540         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     806,    27,     2159},
52541         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     811,    25,     2186},
52542         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     816,    2,      2211},
52543         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     880,    2,      2213},
52544         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     888,    9,      2215},
52545         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     896,    2,      2224},
52546         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     897,    2,      2226},
52547         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     898,    2,      2228},
52548         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     903,    2,      2230},
52549         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     908,    2,      2232},
52550         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     913,    2,      2234},
52551         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     918,    2,      2236},
52552         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     923,    2,      2238},
52553         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     928,    2,      2240},
52554         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     933,    2,      2242},
52555         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     938,    2,      2244},
52556         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     943,    2,      2246},
52557         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     948,    2,      2248},
52558         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     949,    2,      2250},
52559         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     954,    2,      2252},
52560         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     959,    2,      2254},
52561         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     964,    2,      2256},
52562         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1028,   2,      2258},
52563         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1029,   3,      2260},
52564         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1030,   3,      2263},
52565         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1031,   2,      2266},
52566         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1032,   2,      2268},
52567         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1033,   4,      2270},
52568         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1034,   5,      2274},
52569         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1035,   4,      2279},
52570         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1036,   8,      2283},
52571         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1037,   4,      2291},
52572         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1038,   5,      2295},
52573         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1039,   5,      2300},
52574         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1040,   1,      2305},
52575         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1041,   18,     2306},
52576         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1042,   4,      2324},
52577         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1043,   2,      2328},
52578         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1044,   6,      2330},
52579         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1045,   7,      2336},
52580         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1046,   4,      2343},
52581         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1047,   9,      2347},
52582         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1048,   5,      2356},
52583         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1049,   15,     2361},
52584         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1050,   4,      2376},
52585         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1051,   1,      2380},
52586         {"cvmx_pko_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1052,   1,      2381},
52587         {"cvmx_pko_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1053,   1,      2382},
52588         {"cvmx_pko_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1054,   1,      2383},
52589         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1055,   4,      2384},
52590         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1056,   5,      2388},
52591         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1057,   3,      2393},
52592         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1058,   4,      2396},
52593         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1059,   2,      2400},
52594         {"cvmx_pko_reg_queue_ptrs1"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1060,   3,      2402},
52595         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1061,   3,      2405},
52596         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1062,   12,     2408},
52597         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1063,   2,      2420},
52598         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1064,   13,     2422},
52599         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1065,   3,      2435},
52600         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1066,   2,      2438},
52601         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1074,   2,      2440},
52602         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1075,   2,      2442},
52603         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1076,   2,      2444},
52604         {"cvmx_pow_pf_rst_msk"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1077,   2,      2446},
52605         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1078,   10,     2448},
52606         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1080,   5,      2458},
52607         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1088,   10,     2463},
52608         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1096,   2,      2473},
52609         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1097,   2,      2475},
52610         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1098,   2,      2477},
52611         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1106,   3,      2479},
52612         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1107,   6,      2482},
52613         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1123,   5,      2488},
52614         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1124,   7,      2493},
52615         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1140,   2,      2500},
52616         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1156,   3,      2502},
52617         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1157,   7,      2505},
52618         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1158,   10,     2512},
52619         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1159,   6,      2522},
52620         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1160,   2,      2528},
52621         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1161,   4,      2530},
52622         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1162,   4,      2534},
52623         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1163,   6,      2538},
52624         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1164,   3,      2544},
52625         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1165,   5,      2547},
52626         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1166,   4,      2552},
52627         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1167,   6,      2556},
52628         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1168,   4,      2562},
52629         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1169,   2,      2566},
52630         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1170,   4,      2568},
52631         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1171,   2,      2572},
52632         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1172,   3,      2574},
52633         {"cvmx_usbc#_daint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1173,   2,      2577},
52634         {"cvmx_usbc#_daintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1174,   2,      2579},
52635         {"cvmx_usbc#_dcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1175,   8,      2581},
52636         {"cvmx_usbc#_dctl"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1176,   11,     2589},
52637         {"cvmx_usbc#_diepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1177,   15,     2600},
52638         {"cvmx_usbc#_diepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1182,   8,      2615},
52639         {"cvmx_usbc#_diepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1187,   8,      2623},
52640         {"cvmx_usbc#_dieptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1188,   4,      2631},
52641         {"cvmx_usbc#_doepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1193,   15,     2635},
52642         {"cvmx_usbc#_doepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1198,   6,      2650},
52643         {"cvmx_usbc#_doepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1203,   6,      2656},
52644         {"cvmx_usbc#_doeptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1204,   4,      2662},
52645         {"cvmx_usbc#_dptxfsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1209,   2,      2666},
52646         {"cvmx_usbc#_dsts"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1213,   6,      2668},
52647         {"cvmx_usbc#_dtknqr1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1214,   4,      2674},
52648         {"cvmx_usbc#_dtknqr2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1215,   1,      2678},
52649         {"cvmx_usbc#_dtknqr3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1216,   1,      2679},
52650         {"cvmx_usbc#_dtknqr4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1217,   1,      2680},
52651         {"cvmx_usbc#_gahbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1218,   7,      2681},
52652         {"cvmx_usbc#_ghwcfg1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1219,   1,      2688},
52653         {"cvmx_usbc#_ghwcfg2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1220,   14,     2689},
52654         {"cvmx_usbc#_ghwcfg3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1221,   10,     2703},
52655         {"cvmx_usbc#_ghwcfg4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1222,   14,     2713},
52656         {"cvmx_usbc#_gintmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1223,   32,     2727},
52657         {"cvmx_usbc#_gintsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1224,   32,     2759},
52658         {"cvmx_usbc#_gnptxfsiz"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1225,   2,      2791},
52659         {"cvmx_usbc#_gnptxsts"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1226,   4,      2793},
52660         {"cvmx_usbc#_gotgctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1227,   13,     2797},
52661         {"cvmx_usbc#_gotgint"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1228,   10,     2810},
52662         {"cvmx_usbc#_grstctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1229,   10,     2820},
52663         {"cvmx_usbc#_grxfsiz"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1230,   2,      2830},
52664         {"cvmx_usbc#_grxstspd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1231,   6,      2832},
52665         {"cvmx_usbc#_grxstsph"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1232,   5,      2838},
52666         {"cvmx_usbc#_grxstsrd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1233,   6,      2843},
52667         {"cvmx_usbc#_grxstsrh"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1234,   5,      2849},
52668         {"cvmx_usbc#_gsnpsid"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1235,   1,      2854},
52669         {"cvmx_usbc#_gusbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1236,   13,     2855},
52670         {"cvmx_usbc#_haint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1237,   2,      2868},
52671         {"cvmx_usbc#_haintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1238,   2,      2870},
52672         {"cvmx_usbc#_hcchar#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1239,   11,     2872},
52673         {"cvmx_usbc#_hcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1247,   3,      2883},
52674         {"cvmx_usbc#_hcint#"           ,        CVMX_CSR_DB_TYPE_NCB,   32,     1248,   12,     2886},
52675         {"cvmx_usbc#_hcintmsk#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1256,   12,     2898},
52676         {"cvmx_usbc#_hcsplt#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1264,   6,      2910},
52677         {"cvmx_usbc#_hctsiz#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1272,   4,      2916},
52678         {"cvmx_usbc#_hfir"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1280,   2,      2920},
52679         {"cvmx_usbc#_hfnum"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1281,   2,      2922},
52680         {"cvmx_usbc#_hprt"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1282,   15,     2924},
52681         {"cvmx_usbc#_hptxfsiz"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1283,   2,      2939},
52682         {"cvmx_usbc#_hptxsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1284,   3,      2941},
52683         {"cvmx_usbc#_nptxdfifo#"       ,        CVMX_CSR_DB_TYPE_NCB,   32,     1285,   1,      2944},
52684         {"cvmx_usbc#_pcgcctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1293,   6,      2945},
52685         {"cvmx_usbn#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1294,   8,      2951},
52686         {"cvmx_usbn#_clk_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1295,   15,     2959},
52687         {"cvmx_usbn#_ctl_status"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     1296,   6,      2974},
52688         {"cvmx_usbn#_dma0_inb_chn0"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1297,   2,      2980},
52689         {"cvmx_usbn#_dma0_inb_chn1"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1298,   2,      2982},
52690         {"cvmx_usbn#_dma0_inb_chn2"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1299,   2,      2984},
52691         {"cvmx_usbn#_dma0_inb_chn3"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1300,   2,      2986},
52692         {"cvmx_usbn#_dma0_inb_chn4"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1301,   2,      2988},
52693         {"cvmx_usbn#_dma0_inb_chn5"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1302,   2,      2990},
52694         {"cvmx_usbn#_dma0_inb_chn6"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1303,   2,      2992},
52695         {"cvmx_usbn#_dma0_inb_chn7"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     1304,   2,      2994},
52696         {"cvmx_usbn#_dma0_outb_chn0"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1305,   2,      2996},
52697         {"cvmx_usbn#_dma0_outb_chn1"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1306,   2,      2998},
52698         {"cvmx_usbn#_dma0_outb_chn2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1307,   2,      3000},
52699         {"cvmx_usbn#_dma0_outb_chn3"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1308,   2,      3002},
52700         {"cvmx_usbn#_dma0_outb_chn4"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1309,   2,      3004},
52701         {"cvmx_usbn#_dma0_outb_chn5"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1310,   2,      3006},
52702         {"cvmx_usbn#_dma0_outb_chn6"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1311,   2,      3008},
52703         {"cvmx_usbn#_dma0_outb_chn7"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     1312,   2,      3010},
52704         {"cvmx_usbn#_dma_test"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1313,   7,      3012},
52705         {"cvmx_usbn#_int_enb"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1314,   34,     3019},
52706         {"cvmx_usbn#_int_sum"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1315,   34,     3053},
52707         {"cvmx_usbn#_usbp_ctl_status"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1316,   35,     3087},
52708         {NULL,0,0,0,0,0}
52709 };
52710 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn50xx[] = {
52711         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
52712         {"ASX0_GMII_RX_CLK_SET"        ,           0x11800B0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
52713         {"ASX0_GMII_RX_DAT_SET"        ,           0x11800B0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
52714         {"ASX0_INT_EN"                 ,           0x11800B0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
52715         {"ASX0_INT_REG"                ,           0x11800B0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
52716         {"ASX0_MII_RX_DAT_SET"         ,           0x11800B0000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
52717         {"ASX0_PRT_LOOP"               ,           0x11800B0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
52718         {"ASX0_RX_CLK_SET000"          ,           0x11800B0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
52719         {"ASX0_RX_CLK_SET001"          ,           0x11800B0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
52720         {"ASX0_RX_CLK_SET002"          ,           0x11800B0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
52721         {"ASX0_RX_PRT_EN"              ,           0x11800B0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
52722         {"ASX0_TX_CLK_SET000"          ,           0x11800B0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
52723         {"ASX0_TX_CLK_SET001"          ,           0x11800B0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
52724         {"ASX0_TX_CLK_SET002"          ,           0x11800B0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
52725         {"ASX0_TX_COMP_BYP"            ,           0x11800B0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
52726         {"ASX0_TX_HI_WATER000"         ,           0x11800B0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
52727         {"ASX0_TX_HI_WATER001"         ,           0x11800B0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
52728         {"ASX0_TX_HI_WATER002"         ,           0x11800B0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
52729         {"ASX0_TX_PRT_EN"              ,           0x11800B0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
52730         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     12},
52731         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     13},
52732         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     14},
52733         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     15},
52734         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
52735         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
52736         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
52737         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
52738         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     16},
52739         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
52740         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
52741         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
52742         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
52743         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     17},
52744         {"CIU_INT0_EN4_0"              ,           0x1070000000C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     18},
52745         {"CIU_INT1_EN4_0"              ,           0x1070000000C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     18},
52746         {"CIU_INT0_EN4_1"              ,           0x1070000000C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     19},
52747         {"CIU_INT1_EN4_1"              ,           0x1070000000C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     19},
52748         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
52749         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
52750         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
52751         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
52752         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     20},
52753         {"CIU_INT0_SUM4"               ,           0x1070000000C00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     21},
52754         {"CIU_INT1_SUM4"               ,           0x1070000000C08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     21},
52755         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     22},
52756         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     23},
52757         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     23},
52758         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
52759         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     24},
52760         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     25},
52761         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     26},
52762         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     27},
52763         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
52764         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     28},
52765         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     29},
52766         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     30},
52767         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     31},
52768         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     32},
52769         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
52770         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
52771         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
52772         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     33},
52773         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
52774         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     34},
52775         {"DBG_DATA"                    ,           0x11F00000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     35},
52776         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     36},
52777         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
52778         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
52779         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     39},
52780         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
52781         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
52782         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
52783         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
52784         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
52785         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
52786         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
52787         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
52788         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
52789         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
52790         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
52791         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
52792         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
52793         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
52794         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
52795         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
52796         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     42},
52797         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     43},
52798         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
52799         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     45},
52800         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
52801         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
52802         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
52803         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
52804         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
52805         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
52806         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
52807         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
52808         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
52809         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
52810         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
52811         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
52812         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
52813         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
52814         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
52815         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
52816         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
52817         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
52818         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
52819         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
52820         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
52821         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
52822         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
52823         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
52824         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
52825         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
52826         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
52827         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
52828         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
52829         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
52830         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
52831         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
52832         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
52833         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
52834         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
52835         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
52836         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
52837         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
52838         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
52839         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
52840         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
52841         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
52842         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
52843         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
52844         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
52845         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
52846         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
52847         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
52848         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
52849         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
52850         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
52851         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
52852         {"GMX0_RX000_PAUSE_DROP_TIME"  ,           0x1180008000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
52853         {"GMX0_RX001_PAUSE_DROP_TIME"  ,           0x1180008000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
52854         {"GMX0_RX002_PAUSE_DROP_TIME"  ,           0x1180008001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
52855         {"GMX0_RX000_RX_INBND"         ,           0x1180008000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
52856         {"GMX0_RX001_RX_INBND"         ,           0x1180008000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
52857         {"GMX0_RX002_RX_INBND"         ,           0x1180008001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
52858         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
52859         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
52860         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
52861         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
52862         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
52863         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
52864         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
52865         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
52866         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
52867         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
52868         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
52869         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     71},
52870         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
52871         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
52872         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     72},
52873         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
52874         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
52875         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     73},
52876         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
52877         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
52878         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     74},
52879         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
52880         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
52881         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     75},
52882         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
52883         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
52884         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     76},
52885         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
52886         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
52887         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     77},
52888         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
52889         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
52890         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     78},
52891         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
52892         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
52893         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     79},
52894         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
52895         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
52896         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     80},
52897         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
52898         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
52899         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     81},
52900         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     82},
52901         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     83},
52902         {"GMX0_RX_TX_STATUS"           ,           0x11800080007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     84},
52903         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
52904         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
52905         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     85},
52906         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     86},
52907         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
52908         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
52909         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     87},
52910         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
52911         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
52912         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     88},
52913         {"GMX0_TX000_CLK"              ,           0x1180008000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
52914         {"GMX0_TX001_CLK"              ,           0x1180008000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
52915         {"GMX0_TX002_CLK"              ,           0x1180008001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     89},
52916         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
52917         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
52918         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     90},
52919         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
52920         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
52921         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     91},
52922         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
52923         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
52924         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     92},
52925         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
52926         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
52927         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     93},
52928         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
52929         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
52930         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     94},
52931         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
52932         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
52933         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     95},
52934         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
52935         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
52936         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     96},
52937         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
52938         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
52939         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     97},
52940         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
52941         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
52942         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
52943         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
52944         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
52945         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
52946         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
52947         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
52948         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
52949         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
52950         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
52951         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
52952         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
52953         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
52954         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
52955         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
52956         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
52957         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
52958         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
52959         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
52960         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
52961         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
52962         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
52963         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
52964         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
52965         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
52966         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
52967         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
52968         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
52969         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
52970         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
52971         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
52972         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
52973         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
52974         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
52975         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
52976         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
52977         {"GMX0_TX_CLK_MSK000"          ,           0x1180008000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
52978         {"GMX0_TX_CLK_MSK001"          ,           0x1180008000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
52979         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
52980         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
52981         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
52982         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
52983         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
52984         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
52985         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
52986         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
52987         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
52988         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
52989         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
52990         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
52991         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
52992         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
52993         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
52994         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
52995         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
52996         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
52997         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
52998         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
52999         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
53000         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
53001         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
53002         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
53003         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
53004         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
53005         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     123},
53006         {"GPIO_BOOT_ENA"               ,           0x10700000008A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     124},
53007         {"GPIO_DBG_ENA"                ,           0x10700000008A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     125},
53008         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     126},
53009         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     127},
53010         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     128},
53011         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     129},
53012         {"GPIO_XBIT_CFG16"             ,           0x1070000000900ull,  CVMX_CSR_DB_TYPE_NCB,   64,     130},
53013         {"GPIO_XBIT_CFG17"             ,           0x1070000000908ull,  CVMX_CSR_DB_TYPE_NCB,   64,     130},
53014         {"GPIO_XBIT_CFG18"             ,           0x1070000000910ull,  CVMX_CSR_DB_TYPE_NCB,   64,     130},
53015         {"GPIO_XBIT_CFG19"             ,           0x1070000000918ull,  CVMX_CSR_DB_TYPE_NCB,   64,     130},
53016         {"GPIO_XBIT_CFG20"             ,           0x1070000000920ull,  CVMX_CSR_DB_TYPE_NCB,   64,     130},
53017         {"GPIO_XBIT_CFG21"             ,           0x1070000000928ull,  CVMX_CSR_DB_TYPE_NCB,   64,     130},
53018         {"GPIO_XBIT_CFG22"             ,           0x1070000000930ull,  CVMX_CSR_DB_TYPE_NCB,   64,     130},
53019         {"GPIO_XBIT_CFG23"             ,           0x1070000000938ull,  CVMX_CSR_DB_TYPE_NCB,   64,     130},
53020         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
53021         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
53022         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
53023         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
53024         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
53025         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
53026         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
53027         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
53028         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
53029         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
53030         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
53031         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
53032         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
53033         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
53034         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     145},
53035         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     146},
53036         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     147},
53037         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     148},
53038         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     149},
53039         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     150},
53040         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     151},
53041         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     152},
53042         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     153},
53043         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     154},
53044         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     155},
53045         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     156},
53046         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     157},
53047         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     157},
53048         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     157},
53049         {"IPD_PORT32_BP_PAGE_CNT"      ,           0x14F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     157},
53050         {"IPD_PORT33_BP_PAGE_CNT"      ,           0x14F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     157},
53051         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
53052         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
53053         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
53054         {"IPD_PORT_BP_COUNTERS_PAIR32" ,           0x14F00000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
53055         {"IPD_PORT_BP_COUNTERS_PAIR33" ,           0x14F00000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     158},
53056         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     159},
53057         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     160},
53058         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     161},
53059         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     162},
53060         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
53061         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
53062         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
53063         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
53064         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
53065         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
53066         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
53067         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     163},
53068         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     164},
53069         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     165},
53070         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
53071         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
53072         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
53073         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
53074         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
53075         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
53076         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
53077         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     166},
53078         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     167},
53079         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     168},
53080         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     169},
53081         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     170},
53082         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
53083         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
53084         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
53085         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
53086         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
53087         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
53088         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
53089         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
53090         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
53091         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
53092         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
53093         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
53094         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
53095         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
53096         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
53097         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
53098         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
53099         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
53100         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
53101         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
53102         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
53103         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
53104         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
53105         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     191},
53106         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     192},
53107         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     193},
53108         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     194},
53109         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     195},
53110         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     196},
53111         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     197},
53112         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     198},
53113         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     199},
53114         {"LMC0_BIST_CTL"               ,           0x11800880000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     200},
53115         {"LMC0_BIST_RESULT"            ,           0x11800880000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
53116         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     202},
53117         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     203},
53118         {"LMC0_CTL1"                   ,           0x1180088000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     204},
53119         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     205},
53120         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     206},
53121         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     207},
53122         {"LMC0_DELAY_CFG"              ,           0x1180088000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     208},
53123         {"LMC0_DUAL_MEMCFG"            ,           0x1180088000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     209},
53124         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     210},
53125         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     211},
53126         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     212},
53127         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     213},
53128         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
53129         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
53130         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
53131         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
53132         {"LMC0_PLL_CTL"                ,           0x11800880000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
53133         {"LMC0_PLL_STATUS"             ,           0x11800880000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     219},
53134         {"LMC0_RODT_COMP_CTL"          ,           0x11800880000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     220},
53135         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     221},
53136         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
53137         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
53138         {"MIO_BOOT_COMP"               ,           0x11800000000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
53139         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     225},
53140         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     226},
53141         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     227},
53142         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
53143         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
53144         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
53145         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
53146         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
53147         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
53148         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
53149         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
53150         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
53151         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
53152         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
53153         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
53154         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
53155         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
53156         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
53157         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
53158         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
53159         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
53160         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     231},
53161         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     232},
53162         {"MIO_FUS_BNK_DAT0"            ,           0x1180000001520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
53163         {"MIO_FUS_BNK_DAT1"            ,           0x1180000001528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
53164         {"MIO_FUS_BNK_DAT2"            ,           0x1180000001530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
53165         {"MIO_FUS_BNK_DAT3"            ,           0x1180000001538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     233},
53166         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     234},
53167         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     235},
53168         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     236},
53169         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     237},
53170         {"MIO_FUS_EMA"                 ,           0x1180000001550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     238},
53171         {"MIO_FUS_PDF"                 ,           0x1180000001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     239},
53172         {"MIO_FUS_PLL"                 ,           0x1180000001580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     240},
53173         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     241},
53174         {"MIO_FUS_PROG_TIMES"          ,           0x1180000001518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     242},
53175         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     243},
53176         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     244},
53177         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     245},
53178         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     246},
53179         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     247},
53180         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     248},
53181         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     249},
53182         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     250},
53183         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
53184         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     251},
53185         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
53186         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
53187         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
53188         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
53189         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
53190         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
53191         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
53192         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
53193         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
53194         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
53195         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
53196         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
53197         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
53198         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
53199         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
53200         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
53201         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
53202         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
53203         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
53204         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
53205         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
53206         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
53207         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
53208         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
53209         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
53210         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
53211         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
53212         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
53213         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
53214         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
53215         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
53216         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
53217         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
53218         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
53219         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
53220         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
53221         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
53222         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
53223         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
53224         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
53225         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
53226         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
53227         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
53228         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
53229         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
53230         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
53231         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
53232         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
53233         {"MPI_CFG"                     ,           0x1070000001000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     276},
53234         {"MPI_DAT0"                    ,           0x1070000001080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
53235         {"MPI_DAT1"                    ,           0x1070000001088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
53236         {"MPI_DAT2"                    ,           0x1070000001090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
53237         {"MPI_DAT3"                    ,           0x1070000001098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
53238         {"MPI_DAT4"                    ,           0x10700000010A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
53239         {"MPI_DAT5"                    ,           0x10700000010A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
53240         {"MPI_DAT6"                    ,           0x10700000010B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
53241         {"MPI_DAT7"                    ,           0x10700000010B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
53242         {"MPI_DAT8"                    ,           0x10700000010C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     277},
53243         {"MPI_STS"                     ,           0x1070000001008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     278},
53244         {"MPI_TX"                      ,           0x1070000001010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     279},
53245         {"NPI_BASE_ADDR_INPUT0"        ,           0x11F0000000070ull,  CVMX_CSR_DB_TYPE_NCB,   64,     280},
53246         {"NPI_BASE_ADDR_INPUT1"        ,           0x11F0000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     280},
53247         {"NPI_BASE_ADDR_OUTPUT0"       ,           0x11F00000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     281},
53248         {"NPI_BASE_ADDR_OUTPUT1"       ,           0x11F00000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     281},
53249         {"NPI_BIST_STATUS"             ,           0x11F00000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     282},
53250         {"NPI_BUFF_SIZE_OUTPUT0"       ,           0x11F00000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     283},
53251         {"NPI_BUFF_SIZE_OUTPUT1"       ,           0x11F00000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     283},
53252         {"NPI_COMP_CTL"                ,           0x11F0000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     284},
53253         {"NPI_CTL_STATUS"              ,           0x11F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     285},
53254         {"NPI_DBG_SELECT"              ,           0x11F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     286},
53255         {"NPI_DMA_CONTROL"             ,           0x11F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     287},
53256         {"NPI_DMA_HIGHP_COUNTS"        ,           0x11F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     288},
53257         {"NPI_DMA_HIGHP_NADDR"         ,           0x11F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     289},
53258         {"NPI_DMA_LOWP_COUNTS"         ,           0x11F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     290},
53259         {"NPI_DMA_LOWP_NADDR"          ,           0x11F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     291},
53260         {"NPI_HIGHP_DBELL"             ,           0x11F0000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     292},
53261         {"NPI_HIGHP_IBUFF_SADDR"       ,           0x11F0000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     293},
53262         {"NPI_INPUT_CONTROL"           ,           0x11F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     294},
53263         {"NPI_INT_ENB"                 ,           0x11F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     295},
53264         {"NPI_INT_SUM"                 ,           0x11F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     296},
53265         {"NPI_LOWP_DBELL"              ,           0x11F0000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     297},
53266         {"NPI_LOWP_IBUFF_SADDR"        ,           0x11F0000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     298},
53267         {"NPI_MEM_ACCESS_SUBID3"       ,           0x11F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     299},
53268         {"NPI_MEM_ACCESS_SUBID4"       ,           0x11F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     299},
53269         {"NPI_MEM_ACCESS_SUBID5"       ,           0x11F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     299},
53270         {"NPI_MEM_ACCESS_SUBID6"       ,           0x11F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     299},
53271         {"NPI_MSI_RCV"                 ,           0x11F0000001190ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     300},
53272         {"NPI_NUM_DESC_OUTPUT0"        ,           0x11F0000000050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     301},
53273         {"NPI_NUM_DESC_OUTPUT1"        ,           0x11F0000000058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     301},
53274         {"NPI_OUTPUT_CONTROL"          ,           0x11F0000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     302},
53275         {"NPI_P0_DBPAIR_ADDR"          ,           0x11F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     303},
53276         {"NPI_P1_DBPAIR_ADDR"          ,           0x11F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     303},
53277         {"NPI_P0_INSTR_ADDR"           ,           0x11F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     304},
53278         {"NPI_P1_INSTR_ADDR"           ,           0x11F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     304},
53279         {"NPI_P0_INSTR_CNTS"           ,           0x11F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     305},
53280         {"NPI_P1_INSTR_CNTS"           ,           0x11F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     305},
53281         {"NPI_P0_PAIR_CNTS"            ,           0x11F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     306},
53282         {"NPI_P1_PAIR_CNTS"            ,           0x11F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     306},
53283         {"NPI_PCI_BURST_SIZE"          ,           0x11F00000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     307},
53284         {"NPI_PCI_INT_ARB_CFG"         ,           0x11F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     308},
53285         {"NPI_PCI_READ_CMD"            ,           0x11F0000000048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     309},
53286         {"NPI_PORT32_INSTR_HDR"        ,           0x11F00000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     310},
53287         {"NPI_PORT33_INSTR_HDR"        ,           0x11F0000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     311},
53288         {"NPI_PORT_BP_CONTROL"         ,           0x11F00000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     312},
53289         {"NPI_RSL_INT_BLOCKS"          ,           0x11F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     313},
53290         {"NPI_SIZE_INPUT0"             ,           0x11F0000000078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     314},
53291         {"NPI_SIZE_INPUT1"             ,           0x11F0000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     314},
53292         {"NPI_WIN_READ_TO"             ,           0x11F00000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     315},
53293         {"PCI_BAR1_INDEX0"             ,           0x11F0000001100ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53294         {"PCI_BAR1_INDEX1"             ,           0x11F0000001104ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53295         {"PCI_BAR1_INDEX2"             ,           0x11F0000001108ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53296         {"PCI_BAR1_INDEX3"             ,           0x11F000000110Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53297         {"PCI_BAR1_INDEX4"             ,           0x11F0000001110ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53298         {"PCI_BAR1_INDEX5"             ,           0x11F0000001114ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53299         {"PCI_BAR1_INDEX6"             ,           0x11F0000001118ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53300         {"PCI_BAR1_INDEX7"             ,           0x11F000000111Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53301         {"PCI_BAR1_INDEX8"             ,           0x11F0000001120ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53302         {"PCI_BAR1_INDEX9"             ,           0x11F0000001124ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53303         {"PCI_BAR1_INDEX10"            ,           0x11F0000001128ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53304         {"PCI_BAR1_INDEX11"            ,           0x11F000000112Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53305         {"PCI_BAR1_INDEX12"            ,           0x11F0000001130ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53306         {"PCI_BAR1_INDEX13"            ,           0x11F0000001134ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53307         {"PCI_BAR1_INDEX14"            ,           0x11F0000001138ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53308         {"PCI_BAR1_INDEX15"            ,           0x11F000000113Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53309         {"PCI_BAR1_INDEX16"            ,           0x11F0000001140ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53310         {"PCI_BAR1_INDEX17"            ,           0x11F0000001144ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53311         {"PCI_BAR1_INDEX18"            ,           0x11F0000001148ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53312         {"PCI_BAR1_INDEX19"            ,           0x11F000000114Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53313         {"PCI_BAR1_INDEX20"            ,           0x11F0000001150ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53314         {"PCI_BAR1_INDEX21"            ,           0x11F0000001154ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53315         {"PCI_BAR1_INDEX22"            ,           0x11F0000001158ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53316         {"PCI_BAR1_INDEX23"            ,           0x11F000000115Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53317         {"PCI_BAR1_INDEX24"            ,           0x11F0000001160ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53318         {"PCI_BAR1_INDEX25"            ,           0x11F0000001164ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53319         {"PCI_BAR1_INDEX26"            ,           0x11F0000001168ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53320         {"PCI_BAR1_INDEX27"            ,           0x11F000000116Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53321         {"PCI_BAR1_INDEX28"            ,           0x11F0000001170ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53322         {"PCI_BAR1_INDEX29"            ,           0x11F0000001174ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53323         {"PCI_BAR1_INDEX30"            ,           0x11F0000001178ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53324         {"PCI_BAR1_INDEX31"            ,           0x11F000000117Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     316},
53325         {"PCI_BIST_REG"                ,           0x11F00000011C0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     317},
53326         {"PCI_CFG00"                   ,           0x11F0000001800ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     318},
53327         {"PCI_CFG01"                   ,           0x11F0000001804ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     319},
53328         {"PCI_CFG02"                   ,           0x11F0000001808ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     320},
53329         {"PCI_CFG03"                   ,           0x11F000000180Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     321},
53330         {"PCI_CFG04"                   ,           0x11F0000001810ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     322},
53331         {"PCI_CFG05"                   ,           0x11F0000001814ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     323},
53332         {"PCI_CFG06"                   ,           0x11F0000001818ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     324},
53333         {"PCI_CFG07"                   ,           0x11F000000181Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     325},
53334         {"PCI_CFG08"                   ,           0x11F0000001820ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     326},
53335         {"PCI_CFG09"                   ,           0x11F0000001824ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     327},
53336         {"PCI_CFG10"                   ,           0x11F0000001828ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     328},
53337         {"PCI_CFG11"                   ,           0x11F000000182Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     329},
53338         {"PCI_CFG12"                   ,           0x11F0000001830ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     330},
53339         {"PCI_CFG13"                   ,           0x11F0000001834ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     331},
53340         {"PCI_CFG15"                   ,           0x11F000000183Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     332},
53341         {"PCI_CFG16"                   ,           0x11F0000001840ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     333},
53342         {"PCI_CFG17"                   ,           0x11F0000001844ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     334},
53343         {"PCI_CFG18"                   ,           0x11F0000001848ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     335},
53344         {"PCI_CFG19"                   ,           0x11F000000184Cull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     336},
53345         {"PCI_CFG20"                   ,           0x11F0000001850ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     337},
53346         {"PCI_CFG21"                   ,           0x11F0000001854ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     338},
53347         {"PCI_CFG22"                   ,           0x11F0000001858ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     339},
53348         {"PCI_CFG56"                   ,           0x11F00000018E0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     340},
53349         {"PCI_CFG57"                   ,           0x11F00000018E4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     341},
53350         {"PCI_CFG58"                   ,           0x11F00000018E8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     342},
53351         {"PCI_CFG59"                   ,           0x11F00000018ECull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     343},
53352         {"PCI_CFG60"                   ,           0x11F00000018F0ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     344},
53353         {"PCI_CFG61"                   ,           0x11F00000018F4ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     345},
53354         {"PCI_CFG62"                   ,           0x11F00000018F8ull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     346},
53355         {"PCI_CFG63"                   ,           0x11F00000018FCull,  CVMX_CSR_DB_TYPE_PCICONFIG,     32,     347},
53356         {"PCI_CNT_REG"                 ,           0x11F00000011B8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     348},
53357         {"PCI_CTL_STATUS_2"            ,           0x11F000000118Cull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     349},
53358         {"PCI_DBELL0"                  ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCI,   32,     350},
53359         {"PCI_DBELL1"                  ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCI,   32,     350},
53360         {"PCI_DMA_CNT0"                ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     351},
53361         {"PCI_DMA_CNT1"                ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCI,   32,     351},
53362         {"PCI_DMA_INT_LEV0"            ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     352},
53363         {"PCI_DMA_INT_LEV1"            ,                      0xACull,  CVMX_CSR_DB_TYPE_PCI,   32,     352},
53364         {"PCI_DMA_TIME0"               ,                      0xB0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     353},
53365         {"PCI_DMA_TIME1"               ,                      0xB4ull,  CVMX_CSR_DB_TYPE_PCI,   32,     353},
53366         {"PCI_INSTR_COUNT0"            ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCI,   32,     354},
53367         {"PCI_INSTR_COUNT1"            ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     354},
53368         {"PCI_INT_ENB"                 ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCI,   64,     355},
53369         {"PCI_INT_ENB2"                ,           0x11F00000011A0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     356},
53370         {"PCI_INT_SUM"                 ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCI,   64,     357},
53371         {"PCI_INT_SUM2"                ,           0x11F0000001198ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     358},
53372         {"PCI_MSI_RCV"                 ,                      0xF0ull,  CVMX_CSR_DB_TYPE_PCI,   32,     359},
53373         {"PCI_PKT_CREDITS0"            ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCI,   32,     360},
53374         {"PCI_PKT_CREDITS1"            ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCI,   32,     360},
53375         {"PCI_PKTS_SENT0"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCI,   32,     361},
53376         {"PCI_PKTS_SENT1"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCI,   32,     361},
53377         {"PCI_PKTS_SENT_INT_LEV0"      ,                      0x48ull,  CVMX_CSR_DB_TYPE_PCI,   32,     362},
53378         {"PCI_PKTS_SENT_INT_LEV1"      ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCI,   32,     362},
53379         {"PCI_PKTS_SENT_TIME0"         ,                      0x4Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     363},
53380         {"PCI_PKTS_SENT_TIME1"         ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCI,   32,     363},
53381         {"PCI_READ_CMD_6"              ,           0x11F0000001180ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     364},
53382         {"PCI_READ_CMD_C"              ,           0x11F0000001184ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     365},
53383         {"PCI_READ_CMD_E"              ,           0x11F0000001188ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       32,     366},
53384         {"PCI_READ_TIMEOUT"            ,           0x11F00000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     367},
53385         {"PCI_SCM_REG"                 ,           0x11F00000011A8ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     368},
53386         {"PCI_TSR_REG"                 ,           0x11F00000011B0ull,  CVMX_CSR_DB_TYPE_PCI_NCB,       64,     369},
53387         {"PCI_WIN_RD_ADDR"             ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCI,   64,     370},
53388         {"PCI_WIN_RD_DATA"             ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCI,   64,     371},
53389         {"PCI_WIN_WR_ADDR"             ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCI,   64,     372},
53390         {"PCI_WIN_WR_DATA"             ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCI,   64,     373},
53391         {"PCI_WIN_WR_MASK"             ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCI,   64,     374},
53392         {"PCM0_DMA_CFG"                ,           0x1070000010018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     375},
53393         {"PCM1_DMA_CFG"                ,           0x1070000014018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     375},
53394         {"PCM2_DMA_CFG"                ,           0x1070000018018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     375},
53395         {"PCM3_DMA_CFG"                ,           0x107000001C018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     375},
53396         {"PCM0_INT_ENA"                ,           0x1070000010020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     376},
53397         {"PCM1_INT_ENA"                ,           0x1070000014020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     376},
53398         {"PCM2_INT_ENA"                ,           0x1070000018020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     376},
53399         {"PCM3_INT_ENA"                ,           0x107000001C020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     376},
53400         {"PCM0_INT_SUM"                ,           0x1070000010028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     377},
53401         {"PCM1_INT_SUM"                ,           0x1070000014028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     377},
53402         {"PCM2_INT_SUM"                ,           0x1070000018028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     377},
53403         {"PCM3_INT_SUM"                ,           0x107000001C028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     377},
53404         {"PCM0_RXADDR"                 ,           0x1070000010068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     378},
53405         {"PCM1_RXADDR"                 ,           0x1070000014068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     378},
53406         {"PCM2_RXADDR"                 ,           0x1070000018068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     378},
53407         {"PCM3_RXADDR"                 ,           0x107000001C068ull,  CVMX_CSR_DB_TYPE_NCB,   64,     378},
53408         {"PCM0_RXCNT"                  ,           0x1070000010060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     379},
53409         {"PCM1_RXCNT"                  ,           0x1070000014060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     379},
53410         {"PCM2_RXCNT"                  ,           0x1070000018060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     379},
53411         {"PCM3_RXCNT"                  ,           0x107000001C060ull,  CVMX_CSR_DB_TYPE_NCB,   64,     379},
53412         {"PCM0_RXMSK0"                 ,           0x10700000100C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     380},
53413         {"PCM1_RXMSK0"                 ,           0x10700000140C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     380},
53414         {"PCM2_RXMSK0"                 ,           0x10700000180C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     380},
53415         {"PCM3_RXMSK0"                 ,           0x107000001C0C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     380},
53416         {"PCM0_RXMSK1"                 ,           0x10700000100C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
53417         {"PCM1_RXMSK1"                 ,           0x10700000140C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
53418         {"PCM2_RXMSK1"                 ,           0x10700000180C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
53419         {"PCM3_RXMSK1"                 ,           0x107000001C0C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     381},
53420         {"PCM0_RXMSK2"                 ,           0x10700000100D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
53421         {"PCM1_RXMSK2"                 ,           0x10700000140D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
53422         {"PCM2_RXMSK2"                 ,           0x10700000180D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
53423         {"PCM3_RXMSK2"                 ,           0x107000001C0D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     382},
53424         {"PCM0_RXMSK3"                 ,           0x10700000100D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
53425         {"PCM1_RXMSK3"                 ,           0x10700000140D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
53426         {"PCM2_RXMSK3"                 ,           0x10700000180D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
53427         {"PCM3_RXMSK3"                 ,           0x107000001C0D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     383},
53428         {"PCM0_RXMSK4"                 ,           0x10700000100E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
53429         {"PCM1_RXMSK4"                 ,           0x10700000140E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
53430         {"PCM2_RXMSK4"                 ,           0x10700000180E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
53431         {"PCM3_RXMSK4"                 ,           0x107000001C0E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     384},
53432         {"PCM0_RXMSK5"                 ,           0x10700000100E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
53433         {"PCM1_RXMSK5"                 ,           0x10700000140E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
53434         {"PCM2_RXMSK5"                 ,           0x10700000180E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
53435         {"PCM3_RXMSK5"                 ,           0x107000001C0E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     385},
53436         {"PCM0_RXMSK6"                 ,           0x10700000100F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
53437         {"PCM1_RXMSK6"                 ,           0x10700000140F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
53438         {"PCM2_RXMSK6"                 ,           0x10700000180F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
53439         {"PCM3_RXMSK6"                 ,           0x107000001C0F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     386},
53440         {"PCM0_RXMSK7"                 ,           0x10700000100F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
53441         {"PCM1_RXMSK7"                 ,           0x10700000140F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
53442         {"PCM2_RXMSK7"                 ,           0x10700000180F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
53443         {"PCM3_RXMSK7"                 ,           0x107000001C0F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     387},
53444         {"PCM0_RXSTART"                ,           0x1070000010058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
53445         {"PCM1_RXSTART"                ,           0x1070000014058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
53446         {"PCM2_RXSTART"                ,           0x1070000018058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
53447         {"PCM3_RXSTART"                ,           0x107000001C058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     388},
53448         {"PCM0_TDM_CFG"                ,           0x1070000010010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
53449         {"PCM1_TDM_CFG"                ,           0x1070000014010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
53450         {"PCM2_TDM_CFG"                ,           0x1070000018010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
53451         {"PCM3_TDM_CFG"                ,           0x107000001C010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     389},
53452         {"PCM0_TDM_DBG"                ,           0x1070000010030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
53453         {"PCM1_TDM_DBG"                ,           0x1070000014030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
53454         {"PCM2_TDM_DBG"                ,           0x1070000018030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
53455         {"PCM3_TDM_DBG"                ,           0x107000001C030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     390},
53456         {"PCM0_TXADDR"                 ,           0x1070000010050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
53457         {"PCM1_TXADDR"                 ,           0x1070000014050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
53458         {"PCM2_TXADDR"                 ,           0x1070000018050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
53459         {"PCM3_TXADDR"                 ,           0x107000001C050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     391},
53460         {"PCM0_TXCNT"                  ,           0x1070000010048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     392},
53461         {"PCM1_TXCNT"                  ,           0x1070000014048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     392},
53462         {"PCM2_TXCNT"                  ,           0x1070000018048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     392},
53463         {"PCM3_TXCNT"                  ,           0x107000001C048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     392},
53464         {"PCM0_TXMSK0"                 ,           0x1070000010080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     393},
53465         {"PCM1_TXMSK0"                 ,           0x1070000014080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     393},
53466         {"PCM2_TXMSK0"                 ,           0x1070000018080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     393},
53467         {"PCM3_TXMSK0"                 ,           0x107000001C080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     393},
53468         {"PCM0_TXMSK1"                 ,           0x1070000010088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     394},
53469         {"PCM1_TXMSK1"                 ,           0x1070000014088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     394},
53470         {"PCM2_TXMSK1"                 ,           0x1070000018088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     394},
53471         {"PCM3_TXMSK1"                 ,           0x107000001C088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     394},
53472         {"PCM0_TXMSK2"                 ,           0x1070000010090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     395},
53473         {"PCM1_TXMSK2"                 ,           0x1070000014090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     395},
53474         {"PCM2_TXMSK2"                 ,           0x1070000018090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     395},
53475         {"PCM3_TXMSK2"                 ,           0x107000001C090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     395},
53476         {"PCM0_TXMSK3"                 ,           0x1070000010098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     396},
53477         {"PCM1_TXMSK3"                 ,           0x1070000014098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     396},
53478         {"PCM2_TXMSK3"                 ,           0x1070000018098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     396},
53479         {"PCM3_TXMSK3"                 ,           0x107000001C098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     396},
53480         {"PCM0_TXMSK4"                 ,           0x10700000100A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     397},
53481         {"PCM1_TXMSK4"                 ,           0x10700000140A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     397},
53482         {"PCM2_TXMSK4"                 ,           0x10700000180A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     397},
53483         {"PCM3_TXMSK4"                 ,           0x107000001C0A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     397},
53484         {"PCM0_TXMSK5"                 ,           0x10700000100A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     398},
53485         {"PCM1_TXMSK5"                 ,           0x10700000140A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     398},
53486         {"PCM2_TXMSK5"                 ,           0x10700000180A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     398},
53487         {"PCM3_TXMSK5"                 ,           0x107000001C0A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     398},
53488         {"PCM0_TXMSK6"                 ,           0x10700000100B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     399},
53489         {"PCM1_TXMSK6"                 ,           0x10700000140B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     399},
53490         {"PCM2_TXMSK6"                 ,           0x10700000180B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     399},
53491         {"PCM3_TXMSK6"                 ,           0x107000001C0B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     399},
53492         {"PCM0_TXMSK7"                 ,           0x10700000100B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
53493         {"PCM1_TXMSK7"                 ,           0x10700000140B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
53494         {"PCM2_TXMSK7"                 ,           0x10700000180B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
53495         {"PCM3_TXMSK7"                 ,           0x107000001C0B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
53496         {"PCM0_TXSTART"                ,           0x1070000010040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
53497         {"PCM1_TXSTART"                ,           0x1070000014040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
53498         {"PCM2_TXSTART"                ,           0x1070000018040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
53499         {"PCM3_TXSTART"                ,           0x107000001C040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
53500         {"PCM_CLK0_CFG"                ,           0x1070000010000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
53501         {"PCM_CLK1_CFG"                ,           0x1070000014000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
53502         {"PCM_CLK0_DBG"                ,           0x1070000010038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     403},
53503         {"PCM_CLK1_DBG"                ,           0x1070000014038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     403},
53504         {"PCM_CLK0_GEN"                ,           0x1070000010008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     404},
53505         {"PCM_CLK1_GEN"                ,           0x1070000014008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     404},
53506         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     405},
53507         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
53508         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
53509         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
53510         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
53511         {"PIP_FRM_LEN_CHK0"            ,           0x11800A0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
53512         {"PIP_FRM_LEN_CHK1"            ,           0x11800A0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
53513         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     408},
53514         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     409},
53515         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
53516         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
53517         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
53518         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
53519         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
53520         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
53521         {"PIP_PRT_CFG32"               ,           0x11800A0000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
53522         {"PIP_PRT_CFG33"               ,           0x11800A0000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
53523         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
53524         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
53525         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
53526         {"PIP_PRT_TAG32"               ,           0x11800A0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
53527         {"PIP_PRT_TAG33"               ,           0x11800A0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
53528         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53529         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53530         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53531         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53532         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53533         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53534         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53535         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53536         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53537         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53538         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53539         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53540         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53541         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53542         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53543         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53544         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53545         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53546         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53547         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53548         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53549         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53550         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53551         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53552         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53553         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53554         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53555         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53556         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53557         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53558         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53559         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53560         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53561         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53562         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53563         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53564         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53565         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53566         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53567         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53568         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53569         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53570         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53571         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53572         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53573         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53574         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53575         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53576         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53577         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53578         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53579         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53580         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53581         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53582         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53583         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53584         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53585         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53586         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53587         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53588         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53589         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53590         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53591         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
53592         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
53593         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
53594         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
53595         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
53596         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
53597         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
53598         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
53599         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
53600         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
53601         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
53602         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
53603         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
53604         {"PIP_QOS_WATCH4"              ,           0x11800A0000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
53605         {"PIP_QOS_WATCH5"              ,           0x11800A0000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
53606         {"PIP_QOS_WATCH6"              ,           0x11800A0000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
53607         {"PIP_QOS_WATCH7"              ,           0x11800A0000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     417},
53608         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     418},
53609         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     419},
53610         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
53611         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
53612         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
53613         {"PIP_STAT0_PRT32"             ,           0x11800A0001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
53614         {"PIP_STAT0_PRT33"             ,           0x11800A0001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     420},
53615         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
53616         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
53617         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
53618         {"PIP_STAT1_PRT32"             ,           0x11800A0001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
53619         {"PIP_STAT1_PRT33"             ,           0x11800A0001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     421},
53620         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
53621         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
53622         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
53623         {"PIP_STAT2_PRT32"             ,           0x11800A0001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
53624         {"PIP_STAT2_PRT33"             ,           0x11800A0001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     422},
53625         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
53626         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
53627         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
53628         {"PIP_STAT3_PRT32"             ,           0x11800A0001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
53629         {"PIP_STAT3_PRT33"             ,           0x11800A0001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     423},
53630         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
53631         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
53632         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
53633         {"PIP_STAT4_PRT32"             ,           0x11800A0001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
53634         {"PIP_STAT4_PRT33"             ,           0x11800A0001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     424},
53635         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
53636         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
53637         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
53638         {"PIP_STAT5_PRT32"             ,           0x11800A0001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
53639         {"PIP_STAT5_PRT33"             ,           0x11800A0001278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     425},
53640         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
53641         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
53642         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
53643         {"PIP_STAT6_PRT32"             ,           0x11800A0001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
53644         {"PIP_STAT6_PRT33"             ,           0x11800A0001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     426},
53645         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
53646         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
53647         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
53648         {"PIP_STAT7_PRT32"             ,           0x11800A0001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
53649         {"PIP_STAT7_PRT33"             ,           0x11800A0001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     427},
53650         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
53651         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
53652         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
53653         {"PIP_STAT8_PRT32"             ,           0x11800A0001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
53654         {"PIP_STAT8_PRT33"             ,           0x11800A0001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     428},
53655         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
53656         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
53657         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
53658         {"PIP_STAT9_PRT32"             ,           0x11800A0001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
53659         {"PIP_STAT9_PRT33"             ,           0x11800A0001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     429},
53660         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     430},
53661         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
53662         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
53663         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
53664         {"PIP_STAT_INB_ERRS32"         ,           0x11800A0001E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
53665         {"PIP_STAT_INB_ERRS33"         ,           0x11800A0001E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     431},
53666         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
53667         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
53668         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
53669         {"PIP_STAT_INB_OCTS32"         ,           0x11800A0001E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
53670         {"PIP_STAT_INB_OCTS33"         ,           0x11800A0001E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     432},
53671         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
53672         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
53673         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
53674         {"PIP_STAT_INB_PKTS32"         ,           0x11800A0001E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
53675         {"PIP_STAT_INB_PKTS33"         ,           0x11800A0001E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     433},
53676         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53677         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53678         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53679         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53680         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53681         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53682         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53683         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53684         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53685         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53686         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53687         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53688         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53689         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53690         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53691         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53692         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53693         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53694         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53695         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53696         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53697         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53698         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53699         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53700         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53701         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53702         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53703         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53704         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53705         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53706         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53707         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53708         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53709         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53710         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53711         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53712         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53713         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53714         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53715         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53716         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53717         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53718         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53719         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53720         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53721         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53722         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53723         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53724         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53725         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53726         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53727         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53728         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53729         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53730         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53731         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53732         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53733         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53734         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53735         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53736         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53737         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53738         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53739         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     434},
53740         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     435},
53741         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     436},
53742         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     437},
53743         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     438},
53744         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     439},
53745         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     440},
53746         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     441},
53747         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     442},
53748         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     443},
53749         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     444},
53750         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     445},
53751         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     446},
53752         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     447},
53753         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     448},
53754         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     449},
53755         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     450},
53756         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     451},
53757         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     452},
53758         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     453},
53759         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     454},
53760         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     455},
53761         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     456},
53762         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     457},
53763         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     458},
53764         {"PKO_REG_DEBUG1"              ,           0x11800500000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     459},
53765         {"PKO_REG_DEBUG2"              ,           0x11800500000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     460},
53766         {"PKO_REG_DEBUG3"              ,           0x11800500000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     461},
53767         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     462},
53768         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     463},
53769         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     464},
53770         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     465},
53771         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     466},
53772         {"PKO_REG_QUEUE_PTRS1"         ,           0x1180050000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     467},
53773         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     468},
53774         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     469},
53775         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     470},
53776         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     471},
53777         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     472},
53778         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     473},
53779         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     473},
53780         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     473},
53781         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     473},
53782         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     473},
53783         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     473},
53784         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     473},
53785         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     473},
53786         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     474},
53787         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     475},
53788         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     476},
53789         {"POW_PF_RST_MSK"              ,           0x1670000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     477},
53790         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     478},
53791         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     478},
53792         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
53793         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
53794         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
53795         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
53796         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
53797         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
53798         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
53799         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     479},
53800         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
53801         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
53802         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
53803         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
53804         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
53805         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
53806         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
53807         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     480},
53808         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     481},
53809         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     482},
53810         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
53811         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
53812         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
53813         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
53814         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
53815         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
53816         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
53817         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     483},
53818         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     484},
53819         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53820         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53821         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53822         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53823         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53824         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53825         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53826         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53827         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53828         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53829         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53830         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53831         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53832         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53833         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53834         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     485},
53835         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     486},
53836         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53837         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53838         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53839         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53840         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53841         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53842         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53843         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53844         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53845         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53846         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53847         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53848         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53849         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53850         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53851         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     487},
53852         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53853         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53854         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53855         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53856         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53857         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53858         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53859         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53860         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53861         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53862         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53863         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53864         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53865         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53866         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53867         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     488},
53868         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     489},
53869         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     490},
53870         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     491},
53871         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     492},
53872         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     493},
53873         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     494},
53874         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     495},
53875         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     496},
53876         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     497},
53877         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     498},
53878         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     499},
53879         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     500},
53880         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     501},
53881         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     502},
53882         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     503},
53883         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     504},
53884         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     505},
53885         {"USBC0_DAINT"                 ,           0x16F0010000818ull,  CVMX_CSR_DB_TYPE_NCB,   32,     506},
53886         {"USBC0_DAINTMSK"              ,           0x16F001000081Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     507},
53887         {"USBC0_DCFG"                  ,           0x16F0010000800ull,  CVMX_CSR_DB_TYPE_NCB,   32,     508},
53888         {"USBC0_DCTL"                  ,           0x16F0010000804ull,  CVMX_CSR_DB_TYPE_NCB,   32,     509},
53889         {"USBC0_DIEPCTL000"            ,           0x16F0010000900ull,  CVMX_CSR_DB_TYPE_NCB,   32,     510},
53890         {"USBC0_DIEPCTL001"            ,           0x16F0010000920ull,  CVMX_CSR_DB_TYPE_NCB,   32,     510},
53891         {"USBC0_DIEPCTL002"            ,           0x16F0010000940ull,  CVMX_CSR_DB_TYPE_NCB,   32,     510},
53892         {"USBC0_DIEPCTL003"            ,           0x16F0010000960ull,  CVMX_CSR_DB_TYPE_NCB,   32,     510},
53893         {"USBC0_DIEPCTL004"            ,           0x16F0010000980ull,  CVMX_CSR_DB_TYPE_NCB,   32,     510},
53894         {"USBC0_DIEPINT000"            ,           0x16F0010000908ull,  CVMX_CSR_DB_TYPE_NCB,   32,     511},
53895         {"USBC0_DIEPINT001"            ,           0x16F0010000928ull,  CVMX_CSR_DB_TYPE_NCB,   32,     511},
53896         {"USBC0_DIEPINT002"            ,           0x16F0010000948ull,  CVMX_CSR_DB_TYPE_NCB,   32,     511},
53897         {"USBC0_DIEPINT003"            ,           0x16F0010000968ull,  CVMX_CSR_DB_TYPE_NCB,   32,     511},
53898         {"USBC0_DIEPINT004"            ,           0x16F0010000988ull,  CVMX_CSR_DB_TYPE_NCB,   32,     511},
53899         {"USBC0_DIEPMSK"               ,           0x16F0010000810ull,  CVMX_CSR_DB_TYPE_NCB,   32,     512},
53900         {"USBC0_DIEPTSIZ000"           ,           0x16F0010000910ull,  CVMX_CSR_DB_TYPE_NCB,   32,     513},
53901         {"USBC0_DIEPTSIZ001"           ,           0x16F0010000930ull,  CVMX_CSR_DB_TYPE_NCB,   32,     513},
53902         {"USBC0_DIEPTSIZ002"           ,           0x16F0010000950ull,  CVMX_CSR_DB_TYPE_NCB,   32,     513},
53903         {"USBC0_DIEPTSIZ003"           ,           0x16F0010000970ull,  CVMX_CSR_DB_TYPE_NCB,   32,     513},
53904         {"USBC0_DIEPTSIZ004"           ,           0x16F0010000990ull,  CVMX_CSR_DB_TYPE_NCB,   32,     513},
53905         {"USBC0_DOEPCTL000"            ,           0x16F0010000B00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     514},
53906         {"USBC0_DOEPCTL001"            ,           0x16F0010000B20ull,  CVMX_CSR_DB_TYPE_NCB,   32,     514},
53907         {"USBC0_DOEPCTL002"            ,           0x16F0010000B40ull,  CVMX_CSR_DB_TYPE_NCB,   32,     514},
53908         {"USBC0_DOEPCTL003"            ,           0x16F0010000B60ull,  CVMX_CSR_DB_TYPE_NCB,   32,     514},
53909         {"USBC0_DOEPCTL004"            ,           0x16F0010000B80ull,  CVMX_CSR_DB_TYPE_NCB,   32,     514},
53910         {"USBC0_DOEPINT000"            ,           0x16F0010000B08ull,  CVMX_CSR_DB_TYPE_NCB,   32,     515},
53911         {"USBC0_DOEPINT001"            ,           0x16F0010000B28ull,  CVMX_CSR_DB_TYPE_NCB,   32,     515},
53912         {"USBC0_DOEPINT002"            ,           0x16F0010000B48ull,  CVMX_CSR_DB_TYPE_NCB,   32,     515},
53913         {"USBC0_DOEPINT003"            ,           0x16F0010000B68ull,  CVMX_CSR_DB_TYPE_NCB,   32,     515},
53914         {"USBC0_DOEPINT004"            ,           0x16F0010000B88ull,  CVMX_CSR_DB_TYPE_NCB,   32,     515},
53915         {"USBC0_DOEPMSK"               ,           0x16F0010000814ull,  CVMX_CSR_DB_TYPE_NCB,   32,     516},
53916         {"USBC0_DOEPTSIZ000"           ,           0x16F0010000B10ull,  CVMX_CSR_DB_TYPE_NCB,   32,     517},
53917         {"USBC0_DOEPTSIZ001"           ,           0x16F0010000B30ull,  CVMX_CSR_DB_TYPE_NCB,   32,     517},
53918         {"USBC0_DOEPTSIZ002"           ,           0x16F0010000B50ull,  CVMX_CSR_DB_TYPE_NCB,   32,     517},
53919         {"USBC0_DOEPTSIZ003"           ,           0x16F0010000B70ull,  CVMX_CSR_DB_TYPE_NCB,   32,     517},
53920         {"USBC0_DOEPTSIZ004"           ,           0x16F0010000B90ull,  CVMX_CSR_DB_TYPE_NCB,   32,     517},
53921         {"USBC0_DPTXFSIZ001"           ,           0x16F0010000104ull,  CVMX_CSR_DB_TYPE_NCB,   32,     518},
53922         {"USBC0_DPTXFSIZ002"           ,           0x16F0010000108ull,  CVMX_CSR_DB_TYPE_NCB,   32,     518},
53923         {"USBC0_DPTXFSIZ003"           ,           0x16F001000010Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     518},
53924         {"USBC0_DPTXFSIZ004"           ,           0x16F0010000110ull,  CVMX_CSR_DB_TYPE_NCB,   32,     518},
53925         {"USBC0_DSTS"                  ,           0x16F0010000808ull,  CVMX_CSR_DB_TYPE_NCB,   32,     519},
53926         {"USBC0_DTKNQR1"               ,           0x16F0010000820ull,  CVMX_CSR_DB_TYPE_NCB,   32,     520},
53927         {"USBC0_DTKNQR2"               ,           0x16F0010000824ull,  CVMX_CSR_DB_TYPE_NCB,   32,     521},
53928         {"USBC0_DTKNQR3"               ,           0x16F0010000830ull,  CVMX_CSR_DB_TYPE_NCB,   32,     522},
53929         {"USBC0_DTKNQR4"               ,           0x16F0010000834ull,  CVMX_CSR_DB_TYPE_NCB,   32,     523},
53930         {"USBC0_GAHBCFG"               ,           0x16F0010000008ull,  CVMX_CSR_DB_TYPE_NCB,   32,     524},
53931         {"USBC0_GHWCFG1"               ,           0x16F0010000044ull,  CVMX_CSR_DB_TYPE_NCB,   32,     525},
53932         {"USBC0_GHWCFG2"               ,           0x16F0010000048ull,  CVMX_CSR_DB_TYPE_NCB,   32,     526},
53933         {"USBC0_GHWCFG3"               ,           0x16F001000004Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     527},
53934         {"USBC0_GHWCFG4"               ,           0x16F0010000050ull,  CVMX_CSR_DB_TYPE_NCB,   32,     528},
53935         {"USBC0_GINTMSK"               ,           0x16F0010000018ull,  CVMX_CSR_DB_TYPE_NCB,   32,     529},
53936         {"USBC0_GINTSTS"               ,           0x16F0010000014ull,  CVMX_CSR_DB_TYPE_NCB,   32,     530},
53937         {"USBC0_GNPTXFSIZ"             ,           0x16F0010000028ull,  CVMX_CSR_DB_TYPE_NCB,   32,     531},
53938         {"USBC0_GNPTXSTS"              ,           0x16F001000002Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     532},
53939         {"USBC0_GOTGCTL"               ,           0x16F0010000000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     533},
53940         {"USBC0_GOTGINT"               ,           0x16F0010000004ull,  CVMX_CSR_DB_TYPE_NCB,   32,     534},
53941         {"USBC0_GRSTCTL"               ,           0x16F0010000010ull,  CVMX_CSR_DB_TYPE_NCB,   32,     535},
53942         {"USBC0_GRXFSIZ"               ,           0x16F0010000024ull,  CVMX_CSR_DB_TYPE_NCB,   32,     536},
53943         {"USBC0_GRXSTSPD"              ,           0x16F0010040020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     537},
53944         {"USBC0_GRXSTSPH"              ,           0x16F0010000020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     538},
53945         {"USBC0_GRXSTSRD"              ,           0x16F001004001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     539},
53946         {"USBC0_GRXSTSRH"              ,           0x16F001000001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     540},
53947         {"USBC0_GSNPSID"               ,           0x16F0010000040ull,  CVMX_CSR_DB_TYPE_NCB,   32,     541},
53948         {"USBC0_GUSBCFG"               ,           0x16F001000000Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     542},
53949         {"USBC0_HAINT"                 ,           0x16F0010000414ull,  CVMX_CSR_DB_TYPE_NCB,   32,     543},
53950         {"USBC0_HAINTMSK"              ,           0x16F0010000418ull,  CVMX_CSR_DB_TYPE_NCB,   32,     544},
53951         {"USBC0_HCCHAR000"             ,           0x16F0010000500ull,  CVMX_CSR_DB_TYPE_NCB,   32,     545},
53952         {"USBC0_HCCHAR001"             ,           0x16F0010000520ull,  CVMX_CSR_DB_TYPE_NCB,   32,     545},
53953         {"USBC0_HCCHAR002"             ,           0x16F0010000540ull,  CVMX_CSR_DB_TYPE_NCB,   32,     545},
53954         {"USBC0_HCCHAR003"             ,           0x16F0010000560ull,  CVMX_CSR_DB_TYPE_NCB,   32,     545},
53955         {"USBC0_HCCHAR004"             ,           0x16F0010000580ull,  CVMX_CSR_DB_TYPE_NCB,   32,     545},
53956         {"USBC0_HCCHAR005"             ,           0x16F00100005A0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     545},
53957         {"USBC0_HCCHAR006"             ,           0x16F00100005C0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     545},
53958         {"USBC0_HCCHAR007"             ,           0x16F00100005E0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     545},
53959         {"USBC0_HCFG"                  ,           0x16F0010000400ull,  CVMX_CSR_DB_TYPE_NCB,   32,     546},
53960         {"USBC0_HCINT000"              ,           0x16F0010000508ull,  CVMX_CSR_DB_TYPE_NCB,   32,     547},
53961         {"USBC0_HCINT001"              ,           0x16F0010000528ull,  CVMX_CSR_DB_TYPE_NCB,   32,     547},
53962         {"USBC0_HCINT002"              ,           0x16F0010000548ull,  CVMX_CSR_DB_TYPE_NCB,   32,     547},
53963         {"USBC0_HCINT003"              ,           0x16F0010000568ull,  CVMX_CSR_DB_TYPE_NCB,   32,     547},
53964         {"USBC0_HCINT004"              ,           0x16F0010000588ull,  CVMX_CSR_DB_TYPE_NCB,   32,     547},
53965         {"USBC0_HCINT005"              ,           0x16F00100005A8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     547},
53966         {"USBC0_HCINT006"              ,           0x16F00100005C8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     547},
53967         {"USBC0_HCINT007"              ,           0x16F00100005E8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     547},
53968         {"USBC0_HCINTMSK000"           ,           0x16F001000050Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     548},
53969         {"USBC0_HCINTMSK001"           ,           0x16F001000052Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     548},
53970         {"USBC0_HCINTMSK002"           ,           0x16F001000054Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     548},
53971         {"USBC0_HCINTMSK003"           ,           0x16F001000056Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     548},
53972         {"USBC0_HCINTMSK004"           ,           0x16F001000058Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     548},
53973         {"USBC0_HCINTMSK005"           ,           0x16F00100005ACull,  CVMX_CSR_DB_TYPE_NCB,   32,     548},
53974         {"USBC0_HCINTMSK006"           ,           0x16F00100005CCull,  CVMX_CSR_DB_TYPE_NCB,   32,     548},
53975         {"USBC0_HCINTMSK007"           ,           0x16F00100005ECull,  CVMX_CSR_DB_TYPE_NCB,   32,     548},
53976         {"USBC0_HCSPLT000"             ,           0x16F0010000504ull,  CVMX_CSR_DB_TYPE_NCB,   32,     549},
53977         {"USBC0_HCSPLT001"             ,           0x16F0010000524ull,  CVMX_CSR_DB_TYPE_NCB,   32,     549},
53978         {"USBC0_HCSPLT002"             ,           0x16F0010000544ull,  CVMX_CSR_DB_TYPE_NCB,   32,     549},
53979         {"USBC0_HCSPLT003"             ,           0x16F0010000564ull,  CVMX_CSR_DB_TYPE_NCB,   32,     549},
53980         {"USBC0_HCSPLT004"             ,           0x16F0010000584ull,  CVMX_CSR_DB_TYPE_NCB,   32,     549},
53981         {"USBC0_HCSPLT005"             ,           0x16F00100005A4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     549},
53982         {"USBC0_HCSPLT006"             ,           0x16F00100005C4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     549},
53983         {"USBC0_HCSPLT007"             ,           0x16F00100005E4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     549},
53984         {"USBC0_HCTSIZ000"             ,           0x16F0010000510ull,  CVMX_CSR_DB_TYPE_NCB,   32,     550},
53985         {"USBC0_HCTSIZ001"             ,           0x16F0010000530ull,  CVMX_CSR_DB_TYPE_NCB,   32,     550},
53986         {"USBC0_HCTSIZ002"             ,           0x16F0010000550ull,  CVMX_CSR_DB_TYPE_NCB,   32,     550},
53987         {"USBC0_HCTSIZ003"             ,           0x16F0010000570ull,  CVMX_CSR_DB_TYPE_NCB,   32,     550},
53988         {"USBC0_HCTSIZ004"             ,           0x16F0010000590ull,  CVMX_CSR_DB_TYPE_NCB,   32,     550},
53989         {"USBC0_HCTSIZ005"             ,           0x16F00100005B0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     550},
53990         {"USBC0_HCTSIZ006"             ,           0x16F00100005D0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     550},
53991         {"USBC0_HCTSIZ007"             ,           0x16F00100005F0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     550},
53992         {"USBC0_HFIR"                  ,           0x16F0010000404ull,  CVMX_CSR_DB_TYPE_NCB,   32,     551},
53993         {"USBC0_HFNUM"                 ,           0x16F0010000408ull,  CVMX_CSR_DB_TYPE_NCB,   32,     552},
53994         {"USBC0_HPRT"                  ,           0x16F0010000440ull,  CVMX_CSR_DB_TYPE_NCB,   32,     553},
53995         {"USBC0_HPTXFSIZ"              ,           0x16F0010000100ull,  CVMX_CSR_DB_TYPE_NCB,   32,     554},
53996         {"USBC0_HPTXSTS"               ,           0x16F0010000410ull,  CVMX_CSR_DB_TYPE_NCB,   32,     555},
53997         {"USBC0_NPTXDFIFO000"          ,           0x16F0010001000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     556},
53998         {"USBC0_NPTXDFIFO001"          ,           0x16F0010002000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     556},
53999         {"USBC0_NPTXDFIFO002"          ,           0x16F0010003000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     556},
54000         {"USBC0_NPTXDFIFO003"          ,           0x16F0010004000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     556},
54001         {"USBC0_NPTXDFIFO004"          ,           0x16F0010005000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     556},
54002         {"USBC0_NPTXDFIFO005"          ,           0x16F0010006000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     556},
54003         {"USBC0_NPTXDFIFO006"          ,           0x16F0010007000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     556},
54004         {"USBC0_NPTXDFIFO007"          ,           0x16F0010008000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     556},
54005         {"USBC0_PCGCCTL"               ,           0x16F0010000E00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     557},
54006         {"USBN0_BIST_STATUS"           ,           0x11800680007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     558},
54007         {"USBN0_CLK_CTL"               ,           0x1180068000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     559},
54008         {"USBN0_CTL_STATUS"            ,           0x16F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     560},
54009         {"USBN0_DMA0_INB_CHN0"         ,           0x16F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     561},
54010         {"USBN0_DMA0_INB_CHN1"         ,           0x16F0000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     562},
54011         {"USBN0_DMA0_INB_CHN2"         ,           0x16F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     563},
54012         {"USBN0_DMA0_INB_CHN3"         ,           0x16F0000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     564},
54013         {"USBN0_DMA0_INB_CHN4"         ,           0x16F0000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     565},
54014         {"USBN0_DMA0_INB_CHN5"         ,           0x16F0000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     566},
54015         {"USBN0_DMA0_INB_CHN6"         ,           0x16F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     567},
54016         {"USBN0_DMA0_INB_CHN7"         ,           0x16F0000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     568},
54017         {"USBN0_DMA0_OUTB_CHN0"        ,           0x16F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     569},
54018         {"USBN0_DMA0_OUTB_CHN1"        ,           0x16F0000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     570},
54019         {"USBN0_DMA0_OUTB_CHN2"        ,           0x16F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     571},
54020         {"USBN0_DMA0_OUTB_CHN3"        ,           0x16F0000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     572},
54021         {"USBN0_DMA0_OUTB_CHN4"        ,           0x16F0000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     573},
54022         {"USBN0_DMA0_OUTB_CHN5"        ,           0x16F0000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     574},
54023         {"USBN0_DMA0_OUTB_CHN6"        ,           0x16F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     575},
54024         {"USBN0_DMA0_OUTB_CHN7"        ,           0x16F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     576},
54025         {"USBN0_DMA_TEST"              ,           0x16F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     577},
54026         {"USBN0_INT_ENB"               ,           0x1180068000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     578},
54027         {"USBN0_INT_SUM"               ,           0x1180068000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     579},
54028         {"USBN0_USBP_CTL_STATUS"       ,           0x1180068000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     580},
54029         {NULL,0,0,0,0}
54030 };
54031 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn50xx[] = {
54032         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
54033         {"SETTING"                     ,        0,      5,      0,      "R/W",  0,      0,      0ull,   0ull},
54034         {"RESERVED_5_63"               ,        5,      59,     0,      "RAZ",  1,      1,      0,      0},
54035         {"SETTING"                     ,        0,      5,      1,      "R/W",  0,      0,      0ull,   0ull},
54036         {"RESERVED_5_63"               ,        5,      59,     1,      "RAZ",  1,      1,      0,      0},
54037         {"OVRFLW"                      ,        0,      3,      2,      "R/W",  0,      0,      0ull,   1ull},
54038         {"RESERVED_3_3"                ,        3,      1,      2,      "RAZ",  1,      1,      0,      0},
54039         {"TXPOP"                       ,        4,      3,      2,      "R/W",  0,      0,      0ull,   1ull},
54040         {"RESERVED_7_7"                ,        7,      1,      2,      "RAZ",  1,      1,      0,      0},
54041         {"TXPSH"                       ,        8,      3,      2,      "R/W",  0,      0,      0ull,   1ull},
54042         {"RESERVED_11_63"              ,        11,     53,     2,      "RAZ",  1,      1,      0,      0},
54043         {"OVRFLW"                      ,        0,      3,      3,      "R/W1C",        0,      0,      0ull,   0ull},
54044         {"RESERVED_3_3"                ,        3,      1,      3,      "RAZ",  1,      1,      0,      0},
54045         {"TXPOP"                       ,        4,      3,      3,      "R/W1C",        0,      0,      0ull,   0ull},
54046         {"RESERVED_7_7"                ,        7,      1,      3,      "RAZ",  1,      1,      0,      0},
54047         {"TXPSH"                       ,        8,      3,      3,      "R/W1C",        0,      0,      0ull,   0ull},
54048         {"RESERVED_11_63"              ,        11,     53,     3,      "RAZ",  1,      1,      0,      0},
54049         {"SETTING"                     ,        0,      5,      4,      "R/W",  0,      0,      0ull,   0ull},
54050         {"RESERVED_5_63"               ,        5,      59,     4,      "RAZ",  1,      1,      0,      0},
54051         {"INT_LOOP"                    ,        0,      3,      5,      "R/W",  0,      0,      0ull,   0ull},
54052         {"RESERVED_3_3"                ,        3,      1,      5,      "RAZ",  1,      1,      0,      0},
54053         {"EXT_LOOP"                    ,        4,      3,      5,      "R/W",  0,      0,      0ull,   0ull},
54054         {"RESERVED_7_63"               ,        7,      57,     5,      "RAZ",  1,      1,      0,      0},
54055         {"SETTING"                     ,        0,      5,      6,      "R/W",  0,      0,      24ull,  0ull},
54056         {"RESERVED_5_63"               ,        5,      59,     6,      "RAZ",  1,      1,      0,      0},
54057         {"PRT_EN"                      ,        0,      3,      7,      "R/W",  0,      0,      0ull,   1ull},
54058         {"RESERVED_3_63"               ,        3,      61,     7,      "RAZ",  1,      1,      0,      0},
54059         {"SETTING"                     ,        0,      5,      8,      "R/W",  0,      0,      24ull,  0ull},
54060         {"RESERVED_5_63"               ,        5,      59,     8,      "RAZ",  1,      1,      0,      0},
54061         {"NCTL"                        ,        0,      5,      9,      "R/W",  0,      1,      16ull,  0},
54062         {"RESERVED_5_7"                ,        5,      3,      9,      "RAZ",  1,      1,      0,      0},
54063         {"PCTL"                        ,        8,      5,      9,      "R/W",  0,      1,      16ull,  0},
54064         {"RESERVED_13_15"              ,        13,     3,      9,      "RAZ",  1,      1,      0,      0},
54065         {"BYPASS"                      ,        16,     1,      9,      "R/W",  0,      0,      0ull,   0ull},
54066         {"RESERVED_17_63"              ,        17,     47,     9,      "RAZ",  1,      1,      0,      0},
54067         {"MARK"                        ,        0,      3,      10,     "R/W",  0,      0,      0ull,   0ull},
54068         {"RESERVED_3_63"               ,        3,      61,     10,     "RAZ",  1,      1,      0,      0},
54069         {"PRT_EN"                      ,        0,      3,      11,     "R/W",  0,      0,      0ull,   1ull},
54070         {"RESERVED_3_63"               ,        3,      61,     11,     "RAZ",  1,      1,      0,      0},
54071         {"BIST"                        ,        0,      2,      12,     "RO",   0,      0,      0ull,   0ull},
54072         {"RESERVED_2_63"               ,        2,      62,     12,     "RAZ",  1,      1,      0,      0},
54073         {"DINT"                        ,        0,      2,      13,     "WO",   0,      0,      0ull,   0ull},
54074         {"RESERVED_2_63"               ,        2,      62,     13,     "RAZ",  1,      1,      0,      0},
54075         {"FUSE"                        ,        0,      2,      14,     "RO",   1,      1,      0,      0},
54076         {"RESERVED_2_63"               ,        2,      62,     14,     "RAZ",  1,      1,      0,      0},
54077         {"GSTOP"                       ,        0,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
54078         {"RESERVED_1_63"               ,        1,      63,     15,     "RAZ",  1,      1,      0,      0},
54079         {"WORKQ"                       ,        0,      16,     16,     "R/W",  0,      0,      0ull,   0ull},
54080         {"GPIO"                        ,        16,     16,     16,     "R/W",  0,      0,      0ull,   0ull},
54081         {"MBOX"                        ,        32,     2,      16,     "R/W",  0,      0,      0ull,   0ull},
54082         {"UART"                        ,        34,     2,      16,     "R/W",  0,      0,      0ull,   0ull},
54083         {"PCI_INT"                     ,        36,     4,      16,     "R/W",  0,      0,      0ull,   0ull},
54084         {"PCI_MSI"                     ,        40,     4,      16,     "R/W",  0,      0,      0ull,   0ull},
54085         {"RESERVED_44_44"              ,        44,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54086         {"TWSI"                        ,        45,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54087         {"RML"                         ,        46,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54088         {"RESERVED_47_47"              ,        47,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54089         {"GMX_DRP"                     ,        48,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54090         {"RESERVED_49_49"              ,        49,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54091         {"IPD_DRP"                     ,        50,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54092         {"RESERVED_51_51"              ,        51,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54093         {"TIMER"                       ,        52,     4,      16,     "R/W",  0,      0,      0ull,   0ull},
54094         {"USB"                         ,        56,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54095         {"PCM"                         ,        57,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54096         {"MPI"                         ,        58,     1,      16,     "R/W",  0,      0,      0ull,   0ull},
54097         {"RESERVED_59_63"              ,        59,     5,      16,     "RAZ",  1,      1,      0,      0},
54098         {"WDOG"                        ,        0,      2,      17,     "R/W",  0,      0,      0ull,   0ull},
54099         {"RESERVED_2_63"               ,        2,      62,     17,     "RAZ",  1,      1,      0,      0},
54100         {"WORKQ"                       ,        0,      16,     18,     "R/W",  0,      0,      0ull,   0ull},
54101         {"GPIO"                        ,        16,     16,     18,     "R/W",  0,      0,      0ull,   0ull},
54102         {"MBOX"                        ,        32,     2,      18,     "R/W",  0,      0,      0ull,   0ull},
54103         {"UART"                        ,        34,     2,      18,     "R/W",  0,      0,      0ull,   0ull},
54104         {"PCI_INT"                     ,        36,     4,      18,     "R/W",  0,      0,      0ull,   0ull},
54105         {"PCI_MSI"                     ,        40,     4,      18,     "R/W",  0,      0,      0ull,   0ull},
54106         {"RESERVED_44_44"              ,        44,     1,      18,     "RAZ",  1,      1,      0,      0},
54107         {"TWSI"                        ,        45,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54108         {"RML"                         ,        46,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54109         {"RESERVED_47_47"              ,        47,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54110         {"GMX_DRP"                     ,        48,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54111         {"RESERVED_49_49"              ,        49,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54112         {"IPD_DRP"                     ,        50,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54113         {"RESERVED_51_51"              ,        51,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54114         {"TIMER"                       ,        52,     4,      18,     "R/W",  0,      0,      0ull,   0ull},
54115         {"USB"                         ,        56,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54116         {"PCM"                         ,        57,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54117         {"MPI"                         ,        58,     1,      18,     "R/W",  0,      0,      0ull,   0ull},
54118         {"RESERVED_59_63"              ,        59,     5,      18,     "RAZ",  1,      1,      0,      0},
54119         {"WDOG"                        ,        0,      2,      19,     "R/W",  0,      0,      0ull,   0ull},
54120         {"RESERVED_2_63"               ,        2,      62,     19,     "RAZ",  1,      1,      0,      0},
54121         {"WORKQ"                       ,        0,      16,     20,     "RO",   0,      0,      0ull,   0ull},
54122         {"GPIO"                        ,        16,     16,     20,     "RO",   0,      0,      0ull,   0ull},
54123         {"MBOX"                        ,        32,     2,      20,     "RO",   0,      0,      0ull,   0ull},
54124         {"UART"                        ,        34,     2,      20,     "RO",   0,      0,      0ull,   0ull},
54125         {"PCI_INT"                     ,        36,     4,      20,     "RO",   0,      0,      0ull,   0ull},
54126         {"PCI_MSI"                     ,        40,     4,      20,     "RO",   0,      0,      0ull,   0ull},
54127         {"WDOG_SUM"                    ,        44,     1,      20,     "RO",   0,      0,      0ull,   0ull},
54128         {"TWSI"                        ,        45,     1,      20,     "RO",   0,      0,      0ull,   0ull},
54129         {"RML"                         ,        46,     1,      20,     "RO",   0,      0,      0ull,   0ull},
54130         {"RESERVED_47_47"              ,        47,     1,      20,     "RAZ",  0,      0,      0ull,   0ull},
54131         {"GMX_DRP"                     ,        48,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
54132         {"RESERVED_49_49"              ,        49,     1,      20,     "RAZ",  1,      1,      0,      0},
54133         {"IPD_DRP"                     ,        50,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
54134         {"RESERVED_51_51"              ,        51,     1,      20,     "RAZ",  1,      1,      0,      0},
54135         {"TIMER"                       ,        52,     4,      20,     "R/W1C",        0,      0,      0ull,   0ull},
54136         {"USB"                         ,        56,     1,      20,     "RO",   0,      0,      0ull,   0ull},
54137         {"PCM"                         ,        57,     1,      20,     "RO",   0,      0,      0ull,   0ull},
54138         {"MPI"                         ,        58,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
54139         {"RESERVED_59_63"              ,        59,     5,      20,     "RAZ",  1,      1,      0,      0},
54140         {"WORKQ"                       ,        0,      16,     21,     "RO",   0,      0,      0ull,   0ull},
54141         {"GPIO"                        ,        16,     16,     21,     "RO",   0,      0,      0ull,   0ull},
54142         {"MBOX"                        ,        32,     2,      21,     "RO",   0,      0,      0ull,   0ull},
54143         {"UART"                        ,        34,     2,      21,     "RO",   0,      0,      0ull,   0ull},
54144         {"PCI_INT"                     ,        36,     4,      21,     "RO",   0,      0,      0ull,   0ull},
54145         {"PCI_MSI"                     ,        40,     4,      21,     "RO",   0,      0,      0ull,   0ull},
54146         {"WDOG_SUM"                    ,        44,     1,      21,     "RO",   0,      0,      0ull,   0ull},
54147         {"TWSI"                        ,        45,     1,      21,     "RO",   0,      0,      0ull,   0ull},
54148         {"RML"                         ,        46,     1,      21,     "RO",   0,      0,      0ull,   0ull},
54149         {"RESERVED_47_47"              ,        47,     1,      21,     "RAZ",  0,      0,      0ull,   0ull},
54150         {"GMX_DRP"                     ,        48,     1,      21,     "R/W1C",        0,      0,      0ull,   0ull},
54151         {"RESERVED_49_49"              ,        49,     1,      21,     "RAZ",  1,      1,      0,      0},
54152         {"IPD_DRP"                     ,        50,     1,      21,     "R/W1C",        0,      0,      0ull,   0ull},
54153         {"RESERVED_51_51"              ,        51,     1,      21,     "RAZ",  1,      1,      0,      0},
54154         {"TIMER"                       ,        52,     4,      21,     "R/W1C",        0,      0,      0ull,   0ull},
54155         {"USB"                         ,        56,     1,      21,     "RO",   0,      0,      0ull,   0ull},
54156         {"PCM"                         ,        57,     1,      21,     "RO",   0,      0,      0ull,   0ull},
54157         {"MPI"                         ,        58,     1,      21,     "R/W1C",        0,      0,      0ull,   0ull},
54158         {"RESERVED_59_63"              ,        59,     5,      21,     "RAZ",  1,      1,      0,      0},
54159         {"WDOG"                        ,        0,      2,      22,     "RO",   0,      0,      0ull,   0ull},
54160         {"RESERVED_2_63"               ,        2,      62,     22,     "RAZ",  1,      1,      0,      0},
54161         {"BITS"                        ,        0,      32,     23,     "R/W1C",        0,      0,      0ull,   0ull},
54162         {"RESERVED_32_63"              ,        32,     32,     23,     "RAZ",  1,      1,      0,      0},
54163         {"BITS"                        ,        0,      32,     24,     "R/W1", 0,      0,      0ull,   0ull},
54164         {"RESERVED_32_63"              ,        32,     32,     24,     "RAZ",  1,      1,      0,      0},
54165         {"NMI"                         ,        0,      2,      25,     "WO",   0,      0,      0ull,   0ull},
54166         {"RESERVED_2_63"               ,        2,      62,     25,     "RAZ",  1,      1,      0,      0},
54167         {"INTR"                        ,        0,      2,      26,     "R/W",  0,      0,      0ull,   0ull},
54168         {"RESERVED_2_63"               ,        2,      62,     26,     "RAZ",  1,      1,      0,      0},
54169         {"PPDBG"                       ,        0,      2,      27,     "RO",   0,      0,      0ull,   0ull},
54170         {"RESERVED_2_63"               ,        2,      62,     27,     "RAZ",  1,      1,      0,      0},
54171         {"POKE"                        ,        0,      64,     28,     "RAZ",  1,      1,      0,      0},
54172         {"RST0"                        ,        0,      1,      29,     "R/W",  1,      1,      0,      0},
54173         {"RST"                         ,        1,      1,      29,     "R/W",  0,      0,      1ull,   0ull},
54174         {"RESERVED_2_63"               ,        2,      62,     29,     "RAZ",  1,      1,      0,      0},
54175         {"SOFT_BIST"                   ,        0,      1,      30,     "R/W",  0,      0,      0ull,   0ull},
54176         {"RESERVED_1_63"               ,        1,      63,     30,     "RAZ",  1,      1,      0,      0},
54177         {"SOFT_PRST"                   ,        0,      1,      31,     "R/W",  0,      0,      1ull,   0ull},
54178         {"NPI"                         ,        1,      1,      31,     "R/W",  0,      0,      0ull,   0ull},
54179         {"HOST64"                      ,        2,      1,      31,     "RO",   0,      0,      0ull,   0ull},
54180         {"RESERVED_3_63"               ,        3,      61,     31,     "RAZ",  1,      1,      0,      0},
54181         {"SOFT_RST"                    ,        0,      1,      32,     "WO",   0,      0,      0ull,   0ull},
54182         {"RESERVED_1_63"               ,        1,      63,     32,     "RAZ",  1,      1,      0,      0},
54183         {"LEN"                         ,        0,      36,     33,     "R/W",  0,      0,      0ull,   0ull},
54184         {"ONE_SHOT"                    ,        36,     1,      33,     "R/W",  0,      0,      0ull,   0ull},
54185         {"RESERVED_37_63"              ,        37,     27,     33,     "RAZ",  1,      1,      0,      0},
54186         {"MODE"                        ,        0,      2,      34,     "R/W",  0,      0,      0ull,   0ull},
54187         {"STATE"                       ,        2,      2,      34,     "RO",   0,      0,      0ull,   0ull},
54188         {"LEN"                         ,        4,      16,     34,     "R/W",  0,      0,      0ull,   0ull},
54189         {"CNT"                         ,        20,     24,     34,     "RO",   0,      0,      0ull,   0ull},
54190         {"DSTOP"                       ,        44,     1,      34,     "R/W",  0,      0,      0ull,   0ull},
54191         {"GSTOPEN"                     ,        45,     1,      34,     "R/W",  0,      0,      0ull,   0ull},
54192         {"RESERVED_46_63"              ,        46,     18,     34,     "RAZ",  1,      1,      0,      0},
54193         {"DATA"                        ,        0,      17,     35,     "RO",   0,      1,      0ull,   0},
54194         {"DSEL_EXT"                    ,        17,     1,      35,     "R/W",  0,      0,      1ull,   0ull},
54195         {"C_MUL"                       ,        18,     5,      35,     "RO",   1,      1,      0,      0},
54196         {"RESERVED_23_27"              ,        23,     5,      35,     "RAZ",  1,      1,      0,      0},
54197         {"PLL_MUL"                     ,        28,     3,      35,     "RO",   1,      1,      0,      0},
54198         {"RESERVED_31_63"              ,        31,     33,     35,     "RAZ",  1,      1,      0,      0},
54199         {"FDR"                         ,        0,      1,      36,     "RO",   0,      0,      0ull,   0ull},
54200         {"FFR"                         ,        1,      1,      36,     "RO",   0,      0,      0ull,   0ull},
54201         {"FPF1"                        ,        2,      1,      36,     "RO",   0,      0,      0ull,   0ull},
54202         {"FPF0"                        ,        3,      1,      36,     "RO",   0,      0,      0ull,   0ull},
54203         {"FRD"                         ,        4,      1,      36,     "RO",   0,      0,      0ull,   0ull},
54204         {"RESERVED_5_63"               ,        5,      59,     36,     "RAZ",  1,      1,      0,      0},
54205         {"MEM0_ERR"                    ,        0,      7,      37,     "R/W",  0,      0,      0ull,   0ull},
54206         {"MEM1_ERR"                    ,        7,      7,      37,     "R/W",  0,      0,      0ull,   0ull},
54207         {"ENB"                         ,        14,     1,      37,     "R/W",  0,      0,      0ull,   0ull},
54208         {"USE_STT"                     ,        15,     1,      37,     "R/W",  0,      0,      0ull,   0ull},
54209         {"USE_LDT"                     ,        16,     1,      37,     "R/W",  0,      0,      0ull,   0ull},
54210         {"RESET"                       ,        17,     1,      37,     "R/W",  0,      0,      0ull,   0ull},
54211         {"RESERVED_18_63"              ,        18,     46,     37,     "RAZ",  1,      1,      0,      0},
54212         {"FED0_SBE"                    ,        0,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54213         {"FED0_DBE"                    ,        1,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54214         {"FED1_SBE"                    ,        2,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54215         {"FED1_DBE"                    ,        3,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54216         {"Q0_UND"                      ,        4,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54217         {"Q0_COFF"                     ,        5,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54218         {"Q0_PERR"                     ,        6,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54219         {"Q1_UND"                      ,        7,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54220         {"Q1_COFF"                     ,        8,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54221         {"Q1_PERR"                     ,        9,      1,      38,     "R/W",  0,      0,      0ull,   0ull},
54222         {"Q2_UND"                      ,        10,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54223         {"Q2_COFF"                     ,        11,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54224         {"Q2_PERR"                     ,        12,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54225         {"Q3_UND"                      ,        13,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54226         {"Q3_COFF"                     ,        14,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54227         {"Q3_PERR"                     ,        15,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54228         {"Q4_UND"                      ,        16,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54229         {"Q4_COFF"                     ,        17,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54230         {"Q4_PERR"                     ,        18,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54231         {"Q5_UND"                      ,        19,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54232         {"Q5_COFF"                     ,        20,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54233         {"Q5_PERR"                     ,        21,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54234         {"Q6_UND"                      ,        22,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54235         {"Q6_COFF"                     ,        23,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54236         {"Q6_PERR"                     ,        24,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54237         {"Q7_UND"                      ,        25,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54238         {"Q7_COFF"                     ,        26,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54239         {"Q7_PERR"                     ,        27,     1,      38,     "R/W",  0,      0,      0ull,   0ull},
54240         {"RESERVED_28_63"              ,        28,     36,     38,     "RAZ",  1,      1,      0,      0},
54241         {"FED0_SBE"                    ,        0,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54242         {"FED0_DBE"                    ,        1,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54243         {"FED1_SBE"                    ,        2,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54244         {"FED1_DBE"                    ,        3,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54245         {"Q0_UND"                      ,        4,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54246         {"Q0_COFF"                     ,        5,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54247         {"Q0_PERR"                     ,        6,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54248         {"Q1_UND"                      ,        7,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54249         {"Q1_COFF"                     ,        8,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54250         {"Q1_PERR"                     ,        9,      1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54251         {"Q2_UND"                      ,        10,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54252         {"Q2_COFF"                     ,        11,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54253         {"Q2_PERR"                     ,        12,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54254         {"Q3_UND"                      ,        13,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54255         {"Q3_COFF"                     ,        14,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54256         {"Q3_PERR"                     ,        15,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54257         {"Q4_UND"                      ,        16,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54258         {"Q4_COFF"                     ,        17,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54259         {"Q4_PERR"                     ,        18,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54260         {"Q5_UND"                      ,        19,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54261         {"Q5_COFF"                     ,        20,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54262         {"Q5_PERR"                     ,        21,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54263         {"Q6_UND"                      ,        22,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54264         {"Q6_COFF"                     ,        23,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54265         {"Q6_PERR"                     ,        24,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54266         {"Q7_UND"                      ,        25,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54267         {"Q7_COFF"                     ,        26,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54268         {"Q7_PERR"                     ,        27,     1,      39,     "R/W1C",        0,      0,      0ull,   0ull},
54269         {"RESERVED_28_63"              ,        28,     36,     39,     "RAZ",  1,      1,      0,      0},
54270         {"QUE_SIZ"                     ,        0,      29,     40,     "RO",   0,      0,      0ull,   0ull},
54271         {"RESERVED_29_63"              ,        29,     35,     40,     "RAZ",  1,      1,      0,      0},
54272         {"PG_NUM"                      ,        0,      25,     41,     "RO",   0,      1,      0ull,   0},
54273         {"RESERVED_25_63"              ,        25,     39,     41,     "RAZ",  1,      1,      0,      0},
54274         {"ACT_INDX"                    ,        0,      26,     42,     "RO",   0,      1,      0ull,   0},
54275         {"ACT_QUE"                     ,        26,     3,      42,     "RO",   0,      1,      0ull,   0},
54276         {"RESERVED_29_63"              ,        29,     35,     42,     "RAZ",  0,      0,      0ull,   7ull},
54277         {"EXP_INDX"                    ,        0,      26,     43,     "RO",   0,      1,      0ull,   0},
54278         {"EXP_QUE"                     ,        26,     3,      43,     "RO",   0,      1,      0ull,   0},
54279         {"RESERVED_29_63"              ,        29,     35,     43,     "RAZ",  0,      0,      0ull,   7ull},
54280         {"CTL"                         ,        0,      16,     44,     "R/W",  1,      0,      0,      0ull},
54281         {"RESERVED_16_63"              ,        16,     48,     44,     "RAZ",  1,      1,      0,      0},
54282         {"STATUS"                      ,        0,      32,     45,     "RO",   0,      0,      0ull,   0ull},
54283         {"RESERVED_32_63"              ,        32,     32,     45,     "RAZ",  1,      1,      0,      0},
54284         {"RESERVED_0_1"                ,        0,      2,      46,     "RAZ",  0,      0,      0ull,   0ull},
54285         {"OUT_OVR"                     ,        2,      3,      46,     "R/W1C",        0,      0,      0ull,   0ull},
54286         {"RESERVED_5_21"               ,        5,      17,     46,     "RAZ",  0,      0,      0ull,   0ull},
54287         {"LOSTSTAT"                    ,        22,     3,      46,     "R/W1C",        0,      0,      0ull,   0ull},
54288         {"RESERVED_25_25"              ,        25,     1,      46,     "RAZ",  0,      0,      0ull,   0ull},
54289         {"STATOVR"                     ,        26,     1,      46,     "R/W1C",        0,      0,      0ull,   0ull},
54290         {"INB_NXA"                     ,        27,     4,      46,     "R/W1C",        0,      0,      0ull,   0ull},
54291         {"RESERVED_31_63"              ,        31,     33,     46,     "RAZ",  1,      1,      0,      0},
54292         {"STATUS"                      ,        0,      12,     47,     "RO",   0,      0,      0ull,   0ull},
54293         {"RESERVED_12_63"              ,        12,     52,     47,     "RAZ",  1,      1,      0,      0},
54294         {"TYPE"                        ,        0,      1,      48,     "R/W",  0,      1,      0ull,   0},
54295         {"EN"                          ,        1,      1,      48,     "R/W",  0,      0,      0ull,   1ull},
54296         {"P0MII"                       ,        2,      1,      48,     "R/W",  0,      1,      0ull,   0},
54297         {"RESERVED_3_63"               ,        3,      61,     48,     "RAZ",  1,      1,      0,      0},
54298         {"PRT"                         ,        0,      6,      49,     "RO",   0,      1,      0ull,   0},
54299         {"RESERVED_6_63"               ,        6,      58,     49,     "RAZ",  1,      1,      0,      0},
54300         {"EN"                          ,        0,      1,      50,     "R/W",  0,      1,      0ull,   0},
54301         {"SPEED"                       ,        1,      1,      50,     "R/W",  0,      1,      1ull,   0},
54302         {"DUPLEX"                      ,        2,      1,      50,     "R/W",  0,      1,      1ull,   0},
54303         {"SLOTTIME"                    ,        3,      1,      50,     "R/W",  0,      1,      1ull,   0},
54304         {"RESERVED_4_63"               ,        4,      60,     50,     "RAZ",  1,      1,      0,      0},
54305         {"ADR"                         ,        0,      64,     51,     "R/W",  0,      1,      0ull,   0},
54306         {"ADR"                         ,        0,      64,     52,     "R/W",  0,      1,      0ull,   0},
54307         {"ADR"                         ,        0,      64,     53,     "R/W",  0,      1,      0ull,   0},
54308         {"ADR"                         ,        0,      64,     54,     "R/W",  0,      1,      0ull,   0},
54309         {"ADR"                         ,        0,      64,     55,     "R/W",  0,      1,      0ull,   0},
54310         {"ADR"                         ,        0,      64,     56,     "R/W",  0,      1,      0ull,   0},
54311         {"EN"                          ,        0,      8,      57,     "R/W",  0,      1,      0ull,   0},
54312         {"RESERVED_8_63"               ,        8,      56,     57,     "RAZ",  1,      1,      0,      0},
54313         {"BCST"                        ,        0,      1,      58,     "R/W",  0,      1,      1ull,   0},
54314         {"MCST"                        ,        1,      2,      58,     "R/W",  0,      1,      0ull,   0},
54315         {"CAM_MODE"                    ,        3,      1,      58,     "R/W",  0,      1,      0ull,   0},
54316         {"RESERVED_4_63"               ,        4,      60,     58,     "RAZ",  1,      1,      0,      0},
54317         {"CNT"                         ,        0,      5,      59,     "R/W",  0,      0,      24ull,  24ull},
54318         {"RESERVED_5_63"               ,        5,      59,     59,     "RAZ",  1,      1,      0,      0},
54319         {"RESERVED_0_0"                ,        0,      1,      60,     "RAZ",  1,      1,      0,      0},
54320         {"CAREXT"                      ,        1,      1,      60,     "R/W",  0,      0,      1ull,   1ull},
54321         {"RESERVED_2_2"                ,        2,      1,      60,     "RAZ",  1,      1,      0,      0},
54322         {"JABBER"                      ,        3,      1,      60,     "R/W",  0,      0,      1ull,   1ull},
54323         {"FCSERR"                      ,        4,      1,      60,     "R/W",  0,      0,      1ull,   1ull},
54324         {"ALNERR"                      ,        5,      1,      60,     "R/W",  0,      0,      1ull,   1ull},
54325         {"RESERVED_6_6"                ,        6,      1,      60,     "RAZ",  1,      1,      0,      0},
54326         {"RCVERR"                      ,        7,      1,      60,     "R/W",  0,      0,      1ull,   1ull},
54327         {"SKPERR"                      ,        8,      1,      60,     "R/W",  0,      0,      1ull,   1ull},
54328         {"NIBERR"                      ,        9,      1,      60,     "R/W",  0,      0,      1ull,   1ull},
54329         {"RESERVED_10_63"              ,        10,     54,     60,     "RAZ",  1,      1,      0,      0},
54330         {"PRE_CHK"                     ,        0,      1,      61,     "R/W",  0,      0,      1ull,   1ull},
54331         {"PRE_STRP"                    ,        1,      1,      61,     "R/W",  0,      0,      1ull,   1ull},
54332         {"CTL_DRP"                     ,        2,      1,      61,     "R/W",  0,      0,      1ull,   1ull},
54333         {"CTL_BCK"                     ,        3,      1,      61,     "R/W",  0,      0,      1ull,   1ull},
54334         {"CTL_MCST"                    ,        4,      1,      61,     "R/W",  0,      0,      1ull,   1ull},
54335         {"CTL_SMAC"                    ,        5,      1,      61,     "R/W",  0,      0,      0ull,   0ull},
54336         {"PRE_FREE"                    ,        6,      1,      61,     "R/W",  0,      0,      1ull,   1ull},
54337         {"RESERVED_7_8"                ,        7,      2,      61,     "RAZ",  1,      1,      0,      0},
54338         {"PRE_ALIGN"                   ,        9,      1,      61,     "R/W",  0,      0,      1ull,   1ull},
54339         {"NULL_DIS"                    ,        10,     1,      61,     "R/W",  0,      0,      0ull,   0ull},
54340         {"RESERVED_11_63"              ,        11,     53,     61,     "RAZ",  1,      1,      0,      0},
54341         {"IFG"                         ,        0,      4,      62,     "R/W",  0,      0,      12ull,  12ull},
54342         {"RESERVED_4_63"               ,        4,      60,     62,     "RAZ",  1,      1,      0,      0},
54343         {"RESERVED_0_0"                ,        0,      1,      63,     "RAZ",  1,      1,      0,      0},
54344         {"CAREXT"                      ,        1,      1,      63,     "R/W",  0,      0,      0ull,   0ull},
54345         {"RESERVED_2_2"                ,        2,      1,      63,     "RAZ",  1,      1,      0,      0},
54346         {"JABBER"                      ,        3,      1,      63,     "R/W",  0,      0,      0ull,   0ull},
54347         {"FCSERR"                      ,        4,      1,      63,     "R/W",  0,      0,      0ull,   0ull},
54348         {"ALNERR"                      ,        5,      1,      63,     "R/W",  0,      0,      0ull,   0ull},
54349         {"RESERVED_6_6"                ,        6,      1,      63,     "RAZ",  1,      1,      0,      0},
54350         {"RCVERR"                      ,        7,      1,      63,     "R/W",  0,      0,      0ull,   0ull},
54351         {"SKPERR"                      ,        8,      1,      63,     "R/W",  0,      0,      0ull,   0ull},
54352         {"NIBERR"                      ,        9,      1,      63,     "R/W",  0,      0,      0ull,   0ull},
54353         {"OVRERR"                      ,        10,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54354         {"PCTERR"                      ,        11,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54355         {"RSVERR"                      ,        12,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54356         {"FALERR"                      ,        13,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54357         {"COLDET"                      ,        14,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54358         {"IFGERR"                      ,        15,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54359         {"PHY_LINK"                    ,        16,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54360         {"PHY_SPD"                     ,        17,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54361         {"PHY_DUPX"                    ,        18,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54362         {"PAUSE_DRP"                   ,        19,     1,      63,     "R/W",  0,      0,      0ull,   0ull},
54363         {"RESERVED_20_63"              ,        20,     44,     63,     "RAZ",  1,      1,      0,      0},
54364         {"RESERVED_0_0"                ,        0,      1,      64,     "RAZ",  1,      1,      0,      0},
54365         {"CAREXT"                      ,        1,      1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54366         {"RESERVED_2_2"                ,        2,      1,      64,     "RAZ",  1,      1,      0,      0},
54367         {"JABBER"                      ,        3,      1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54368         {"FCSERR"                      ,        4,      1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54369         {"ALNERR"                      ,        5,      1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54370         {"RESERVED_6_6"                ,        6,      1,      64,     "RAZ",  1,      1,      0,      0},
54371         {"RCVERR"                      ,        7,      1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54372         {"SKPERR"                      ,        8,      1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54373         {"NIBERR"                      ,        9,      1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54374         {"OVRERR"                      ,        10,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54375         {"PCTERR"                      ,        11,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54376         {"RSVERR"                      ,        12,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54377         {"FALERR"                      ,        13,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54378         {"COLDET"                      ,        14,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54379         {"IFGERR"                      ,        15,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54380         {"PHY_LINK"                    ,        16,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54381         {"PHY_SPD"                     ,        17,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54382         {"PHY_DUPX"                    ,        18,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54383         {"PAUSE_DRP"                   ,        19,     1,      64,     "R/W1C",        0,      0,      0ull,   0ull},
54384         {"RESERVED_20_63"              ,        20,     44,     64,     "RAZ",  1,      1,      0,      0},
54385         {"CNT"                         ,        0,      16,     65,     "R/W",  0,      0,      10240ull,       10240ull},
54386         {"RESERVED_16_63"              ,        16,     48,     65,     "RAZ",  1,      1,      0,      0},
54387         {"STATUS"                      ,        0,      16,     66,     "R/W1C",        0,      1,      0ull,   0},
54388         {"RESERVED_16_63"              ,        16,     48,     66,     "RAZ",  1,      1,      0,      0},
54389         {"STATUS"                      ,        0,      1,      67,     "RO",   0,      1,      0ull,   0},
54390         {"SPEED"                       ,        1,      2,      67,     "RO",   0,      1,      0ull,   0},
54391         {"DUPLEX"                      ,        3,      1,      67,     "RO",   0,      1,      0ull,   0},
54392         {"RESERVED_4_63"               ,        4,      60,     67,     "RAZ",  1,      1,      0,      0},
54393         {"RD_CLR"                      ,        0,      1,      68,     "R/W",  0,      0,      0ull,   0ull},
54394         {"RESERVED_1_63"               ,        1,      63,     68,     "RAZ",  1,      1,      0,      0},
54395         {"CNT"                         ,        0,      48,     69,     "RC/W", 0,      1,      0ull,   0},
54396         {"RESERVED_48_63"              ,        48,     16,     69,     "RAZ",  1,      1,      0,      0},
54397         {"CNT"                         ,        0,      48,     70,     "RC/W", 0,      1,      0ull,   0},
54398         {"RESERVED_48_63"              ,        48,     16,     70,     "RAZ",  1,      1,      0,      0},
54399         {"CNT"                         ,        0,      48,     71,     "RC/W", 0,      1,      0ull,   0},
54400         {"RESERVED_48_63"              ,        48,     16,     71,     "RAZ",  1,      1,      0,      0},
54401         {"CNT"                         ,        0,      48,     72,     "RC/W", 0,      1,      0ull,   0},
54402         {"RESERVED_48_63"              ,        48,     16,     72,     "RAZ",  1,      1,      0,      0},
54403         {"CNT"                         ,        0,      32,     73,     "RC/W", 0,      1,      0ull,   0},
54404         {"RESERVED_32_63"              ,        32,     32,     73,     "RAZ",  1,      1,      0,      0},
54405         {"CNT"                         ,        0,      32,     74,     "RC/W", 0,      1,      0ull,   0},
54406         {"RESERVED_32_63"              ,        32,     32,     74,     "RAZ",  1,      1,      0,      0},
54407         {"CNT"                         ,        0,      32,     75,     "RC/W", 0,      1,      0ull,   0},
54408         {"RESERVED_32_63"              ,        32,     32,     75,     "RAZ",  1,      1,      0,      0},
54409         {"CNT"                         ,        0,      32,     76,     "RC/W", 0,      1,      0ull,   0},
54410         {"RESERVED_32_63"              ,        32,     32,     76,     "RAZ",  1,      1,      0,      0},
54411         {"CNT"                         ,        0,      32,     77,     "RC/W", 0,      1,      0ull,   0},
54412         {"RESERVED_32_63"              ,        32,     32,     77,     "RAZ",  1,      1,      0,      0},
54413         {"LEN"                         ,        0,      7,      78,     "R/W",  0,      0,      0ull,   0ull},
54414         {"RESERVED_7_7"                ,        7,      1,      78,     "RAZ",  1,      1,      0,      0},
54415         {"FCSSEL"                      ,        8,      1,      78,     "R/W",  0,      0,      0ull,   0ull},
54416         {"RESERVED_9_63"               ,        9,      55,     78,     "RAZ",  1,      1,      0,      0},
54417         {"MARK"                        ,        0,      6,      79,     "R/W",  1,      1,      0,      0},
54418         {"RESERVED_6_63"               ,        6,      58,     79,     "RAZ",  1,      1,      0,      0},
54419         {"MARK"                        ,        0,      6,      80,     "R/W",  0,      0,      16ull,  16ull},
54420         {"RESERVED_6_63"               ,        6,      58,     80,     "RAZ",  1,      1,      0,      0},
54421         {"MARK"                        ,        0,      9,      81,     "R/W",  1,      1,      0,      0},
54422         {"RESERVED_9_63"               ,        9,      55,     81,     "RAZ",  1,      1,      0,      0},
54423         {"COMMIT"                      ,        0,      3,      82,     "RO",   0,      0,      0ull,   0ull},
54424         {"RESERVED_3_15"               ,        3,      13,     82,     "RAZ",  1,      1,      0,      0},
54425         {"DROP"                        ,        16,     3,      82,     "RO",   0,      0,      0ull,   0ull},
54426         {"RESERVED_19_63"              ,        19,     45,     82,     "RAZ",  1,      1,      0,      0},
54427         {"PRTS"                        ,        0,      3,      83,     "R/W",  0,      0,      3ull,   3ull},
54428         {"RESERVED_3_63"               ,        3,      61,     83,     "RAZ",  1,      1,      0,      0},
54429         {"RX"                          ,        0,      3,      84,     "RC",   0,      0,      0ull,   0ull},
54430         {"RESERVED_3_3"                ,        3,      1,      84,     "RAZ",  1,      1,      0,      0},
54431         {"TX"                          ,        4,      3,      84,     "RC",   0,      0,      0ull,   0ull},
54432         {"RESERVED_7_63"               ,        7,      57,     84,     "RAZ",  1,      1,      0,      0},
54433         {"SMAC"                        ,        0,      48,     85,     "R/W",  0,      1,      0ull,   0},
54434         {"RESERVED_48_63"              ,        48,     16,     85,     "RAZ",  1,      1,      0,      0},
54435         {"CNT"                         ,        0,      16,     86,     "R/W1C",        0,      0,      0ull,   0ull},
54436         {"BP"                          ,        16,     1,      86,     "RO",   0,      0,      0ull,   0ull},
54437         {"RESERVED_17_63"              ,        17,     47,     86,     "RAZ",  1,      1,      0,      0},
54438         {"PREAMBLE"                    ,        0,      1,      87,     "R/W",  0,      0,      1ull,   1ull},
54439         {"PAD"                         ,        1,      1,      87,     "R/W",  0,      0,      1ull,   1ull},
54440         {"FCS"                         ,        2,      1,      87,     "R/W",  0,      0,      1ull,   1ull},
54441         {"FORCE_FCS"                   ,        3,      1,      87,     "R/W",  0,      0,      1ull,   1ull},
54442         {"RESERVED_4_63"               ,        4,      60,     87,     "RAZ",  1,      1,      0,      0},
54443         {"BURST"                       ,        0,      16,     88,     "R/W",  0,      0,      8192ull,        8192ull},
54444         {"RESERVED_16_63"              ,        16,     48,     88,     "RAZ",  1,      1,      0,      0},
54445         {"CLK_CNT"                     ,        0,      6,      89,     "R/W",  0,      0,      1ull,   1ull},
54446         {"RESERVED_6_63"               ,        6,      58,     89,     "RAZ",  1,      1,      0,      0},
54447         {"XSCOL_EN"                    ,        0,      1,      90,     "R/W",  0,      0,      1ull,   1ull},
54448         {"XSDEF_EN"                    ,        1,      1,      90,     "R/W",  0,      0,      1ull,   1ull},
54449         {"RESERVED_2_63"               ,        2,      62,     90,     "RAZ",  1,      1,      0,      0},
54450         {"MIN_SIZE"                    ,        0,      8,      91,     "R/W",  0,      0,      59ull,  59ull},
54451         {"RESERVED_8_63"               ,        8,      56,     91,     "RAZ",  1,      1,      0,      0},
54452         {"INTERVAL"                    ,        0,      16,     92,     "R/W",  0,      1,      16ull,  0},
54453         {"RESERVED_16_63"              ,        16,     48,     92,     "RAZ",  1,      1,      0,      0},
54454         {"TIME"                        ,        0,      16,     93,     "R/W",  0,      1,      96ull,  0},
54455         {"RESERVED_16_63"              ,        16,     48,     93,     "RAZ",  1,      1,      0,      0},
54456         {"TIME"                        ,        0,      16,     94,     "RO",   1,      1,      0,      0},
54457         {"RESERVED_16_63"              ,        16,     48,     94,     "RAZ",  1,      1,      0,      0},
54458         {"SEND"                        ,        0,      1,      95,     "R/W",  0,      0,      1ull,   1ull},
54459         {"RESERVED_1_63"               ,        1,      63,     95,     "RAZ",  1,      1,      0,      0},
54460         {"SLOT"                        ,        0,      10,     96,     "R/W",  0,      0,      512ull, 512ull},
54461         {"RESERVED_10_63"              ,        10,     54,     96,     "RAZ",  1,      1,      0,      0},
54462         {"TIME"                        ,        0,      16,     97,     "R/W",  0,      1,      0ull,   0},
54463         {"RESERVED_16_63"              ,        16,     48,     97,     "RAZ",  1,      1,      0,      0},
54464         {"XSCOL"                       ,        0,      32,     98,     "RC/W", 0,      1,      0ull,   0},
54465         {"XSDEF"                       ,        32,     32,     98,     "RC/W", 0,      1,      0ull,   0},
54466         {"MCOL"                        ,        0,      32,     99,     "RC/W", 0,      1,      0ull,   0},
54467         {"SCOL"                        ,        32,     32,     99,     "RC/W", 0,      1,      0ull,   0},
54468         {"OCTS"                        ,        0,      48,     100,    "RC/W", 0,      1,      0ull,   0},
54469         {"RESERVED_48_63"              ,        48,     16,     100,    "RAZ",  1,      1,      0,      0},
54470         {"PKTS"                        ,        0,      32,     101,    "RC/W", 0,      1,      0ull,   0},
54471         {"RESERVED_32_63"              ,        32,     32,     101,    "RAZ",  1,      1,      0,      0},
54472         {"HIST0"                       ,        0,      32,     102,    "RC/W", 0,      1,      0ull,   0},
54473         {"HIST1"                       ,        32,     32,     102,    "RC/W", 0,      1,      0ull,   0},
54474         {"HIST2"                       ,        0,      32,     103,    "RC/W", 0,      1,      0ull,   0},
54475         {"HIST3"                       ,        32,     32,     103,    "RC/W", 0,      1,      0ull,   0},
54476         {"HIST4"                       ,        0,      32,     104,    "RC/W", 0,      1,      0ull,   0},
54477         {"HIST5"                       ,        32,     32,     104,    "RC/W", 0,      1,      0ull,   0},
54478         {"HIST6"                       ,        0,      32,     105,    "RC/W", 0,      1,      0ull,   0},
54479         {"HIST7"                       ,        32,     32,     105,    "RC/W", 0,      1,      0ull,   0},
54480         {"BCST"                        ,        0,      32,     106,    "RC/W", 0,      1,      0ull,   0},
54481         {"MCST"                        ,        32,     32,     106,    "RC/W", 0,      1,      0ull,   0},
54482         {"CTL"                         ,        0,      32,     107,    "RC/W", 0,      1,      0ull,   0},
54483         {"UNDFLW"                      ,        32,     32,     107,    "RC/W", 0,      1,      0ull,   0},
54484         {"RD_CLR"                      ,        0,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
54485         {"RESERVED_1_63"               ,        1,      63,     108,    "RAZ",  1,      1,      0,      0},
54486         {"CNT"                         ,        0,      7,      109,    "R/W",  0,      0,      32ull,  32ull},
54487         {"RESERVED_7_63"               ,        7,      57,     109,    "RAZ",  1,      1,      0,      0},
54488         {"BP"                          ,        0,      3,      110,    "RO",   0,      0,      0ull,   0ull},
54489         {"RESERVED_3_63"               ,        3,      61,     110,    "RAZ",  1,      1,      0,      0},
54490         {"MSK"                         ,        0,      1,      111,    "R/W",  0,      1,      0ull,   0},
54491         {"RESERVED_1_63"               ,        1,      63,     111,    "RAZ",  1,      1,      0,      0},
54492         {"LIMIT"                       ,        0,      5,      112,    "R/W",  0,      0,      16ull,  16ull},
54493         {"RESERVED_5_63"               ,        5,      59,     112,    "RAZ",  1,      1,      0,      0},
54494         {"CORRUPT"                     ,        0,      3,      113,    "R/W",  0,      0,      15ull,  15ull},
54495         {"RESERVED_3_63"               ,        3,      61,     113,    "RAZ",  1,      1,      0,      0},
54496         {"IFG1"                        ,        0,      4,      114,    "R/W",  0,      1,      8ull,   0},
54497         {"IFG2"                        ,        4,      4,      114,    "R/W",  0,      1,      4ull,   0},
54498         {"RESERVED_8_63"               ,        8,      56,     114,    "RAZ",  1,      1,      0,      0},
54499         {"PKO_NXA"                     ,        0,      1,      115,    "R/W",  0,      0,      0ull,   0ull},
54500         {"RESERVED_1_1"                ,        1,      1,      115,    "RAZ",  0,      0,      0ull,   0ull},
54501         {"UNDFLW"                      ,        2,      3,      115,    "R/W",  0,      0,      0ull,   0ull},
54502         {"RESERVED_5_7"                ,        5,      3,      115,    "RAZ",  0,      0,      0ull,   0ull},
54503         {"XSCOL"                       ,        8,      3,      115,    "R/W",  0,      0,      0ull,   0ull},
54504         {"RESERVED_11_11"              ,        11,     1,      115,    "RAZ",  0,      0,      0ull,   0ull},
54505         {"XSDEF"                       ,        12,     3,      115,    "R/W",  0,      0,      0ull,   0ull},
54506         {"RESERVED_15_15"              ,        15,     1,      115,    "RAZ",  0,      0,      0ull,   0ull},
54507         {"LATE_COL"                    ,        16,     3,      115,    "R/W",  0,      0,      0ull,   0ull},
54508         {"RESERVED_19_63"              ,        19,     45,     115,    "RAZ",  0,      0,      0ull,   0ull},
54509         {"PKO_NXA"                     ,        0,      1,      116,    "R/W1C",        0,      0,      0ull,   0ull},
54510         {"RESERVED_1_1"                ,        1,      1,      116,    "RAZ",  0,      0,      0ull,   0ull},
54511         {"UNDFLW"                      ,        2,      3,      116,    "R/W1C",        0,      0,      0ull,   0ull},
54512         {"RESERVED_5_7"                ,        5,      3,      116,    "RAZ",  0,      0,      0ull,   0ull},
54513         {"XSCOL"                       ,        8,      3,      116,    "R/W1C",        0,      0,      0ull,   0ull},
54514         {"RESERVED_11_11"              ,        11,     1,      116,    "RAZ",  0,      0,      0ull,   0ull},
54515         {"XSDEF"                       ,        12,     3,      116,    "R/W1C",        0,      0,      0ull,   0ull},
54516         {"RESERVED_15_15"              ,        15,     1,      116,    "RAZ",  0,      0,      0ull,   0ull},
54517         {"LATE_COL"                    ,        16,     3,      116,    "R/W1C",        0,      0,      0ull,   0ull},
54518         {"RESERVED_19_63"              ,        19,     45,     116,    "RAZ",  0,      0,      0ull,   0ull},
54519         {"JAM"                         ,        0,      8,      117,    "R/W",  0,      1,      238ull, 0},
54520         {"RESERVED_8_63"               ,        8,      56,     117,    "RAZ",  1,      1,      0,      0},
54521         {"LFSR"                        ,        0,      16,     118,    "R/W",  0,      1,      65535ull,       0},
54522         {"RESERVED_16_63"              ,        16,     48,     118,    "RAZ",  1,      1,      0,      0},
54523         {"IGN_FULL"                    ,        0,      3,      119,    "R/W",  0,      0,      0ull,   0ull},
54524         {"RESERVED_3_3"                ,        3,      1,      119,    "RAZ",  0,      0,      0ull,   0ull},
54525         {"BP"                          ,        4,      3,      119,    "R/W",  0,      0,      0ull,   0ull},
54526         {"RESERVED_7_7"                ,        7,      1,      119,    "RAZ",  0,      0,      0ull,   0ull},
54527         {"EN"                          ,        8,      3,      119,    "R/W",  0,      0,      0ull,   0ull},
54528         {"RESERVED_11_63"              ,        11,     53,     119,    "RAZ",  0,      0,      0ull,   0ull},
54529         {"DMAC"                        ,        0,      48,     120,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
54530         {"RESERVED_48_63"              ,        48,     16,     120,    "RAZ",  1,      1,      0,      0},
54531         {"TYPE"                        ,        0,      16,     121,    "R/W",  0,      0,      34824ull,       34824ull},
54532         {"RESERVED_16_63"              ,        16,     48,     121,    "RAZ",  1,      1,      0,      0},
54533         {"PRTS"                        ,        0,      5,      122,    "R/W",  0,      1,      3ull,   0},
54534         {"RESERVED_5_63"               ,        5,      59,     122,    "RAZ",  1,      1,      0,      0},
54535         {"TX_OE"                       ,        0,      1,      123,    "R/W",  0,      0,      0ull,   0ull},
54536         {"RX_XOR"                      ,        1,      1,      123,    "R/W",  0,      0,      0ull,   0ull},
54537         {"INT_EN"                      ,        2,      1,      123,    "R/W",  0,      0,      0ull,   0ull},
54538         {"INT_TYPE"                    ,        3,      1,      123,    "R/W",  0,      0,      0ull,   0ull},
54539         {"FIL_CNT"                     ,        4,      4,      123,    "R/W",  0,      0,      0ull,   0ull},
54540         {"FIL_SEL"                     ,        8,      4,      123,    "R/W",  0,      0,      0ull,   0ull},
54541         {"RESERVED_12_63"              ,        12,     52,     123,    "RAZ",  1,      1,      0,      0},
54542         {"RESERVED_0_7"                ,        0,      8,      124,    "RAZ",  1,      1,      0,      0},
54543         {"BOOT_ENA"                    ,        8,      4,      124,    "R/W",  0,      1,      0ull,   0},
54544         {"RESERVED_12_63"              ,        12,     52,     124,    "RAZ",  1,      1,      0,      0},
54545         {"DBG_ENA"                     ,        0,      21,     125,    "R/W",  0,      0,      0ull,   0ull},
54546         {"RESERVED_21_63"              ,        21,     43,     125,    "RAZ",  1,      1,      0,      0},
54547         {"TYPE"                        ,        0,      16,     126,    "WO",   0,      0,      0ull,   0ull},
54548         {"RESERVED_16_63"              ,        16,     48,     126,    "RAZ",  1,      1,      0,      0},
54549         {"DAT"                         ,        0,      24,     127,    "RO",   0,      0,      0ull,   0ull},
54550         {"RESERVED_24_63"              ,        24,     40,     127,    "RAZ",  1,      1,      0,      0},
54551         {"CLR"                         ,        0,      24,     128,    "WO",   0,      0,      0ull,   0ull},
54552         {"RESERVED_24_63"              ,        24,     40,     128,    "RAZ",  1,      1,      0,      0},
54553         {"SET"                         ,        0,      24,     129,    "WO",   0,      0,      0ull,   0ull},
54554         {"RESERVED_24_63"              ,        24,     40,     129,    "RAZ",  1,      1,      0,      0},
54555         {"TX_OE"                       ,        0,      1,      130,    "R/W",  0,      0,      0ull,   0ull},
54556         {"RX_XOR"                      ,        1,      1,      130,    "R/W",  0,      0,      0ull,   0ull},
54557         {"RESERVED_2_3"                ,        2,      2,      130,    "RAZ",  1,      1,      0,      0},
54558         {"FIL_CNT"                     ,        4,      4,      130,    "R/W",  0,      0,      0ull,   0ull},
54559         {"FIL_SEL"                     ,        8,      4,      130,    "R/W",  0,      0,      0ull,   0ull},
54560         {"RESERVED_12_63"              ,        12,     52,     130,    "RAZ",  1,      1,      0,      0},
54561         {"ICD"                         ,        0,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54562         {"IBD"                         ,        1,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54563         {"ICRP1"                       ,        2,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54564         {"ICRP0"                       ,        3,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54565         {"ICRN1"                       ,        4,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54566         {"ICRN0"                       ,        5,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54567         {"IBRQ1"                       ,        6,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54568         {"IBRQ0"                       ,        7,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54569         {"ICNRT"                       ,        8,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54570         {"IBR1"                        ,        9,      1,      131,    "RO",   0,      0,      0ull,   0ull},
54571         {"IBR0"                        ,        10,     1,      131,    "RO",   0,      0,      0ull,   0ull},
54572         {"IBDR1"                       ,        11,     1,      131,    "RO",   0,      0,      0ull,   0ull},
54573         {"IBDR0"                       ,        12,     1,      131,    "RO",   0,      0,      0ull,   0ull},
54574         {"ICNR0"                       ,        13,     1,      131,    "RO",   0,      0,      0ull,   0ull},
54575         {"ICNR1"                       ,        14,     1,      131,    "RO",   0,      0,      0ull,   0ull},
54576         {"ICR1"                        ,        15,     1,      131,    "RO",   0,      0,      0ull,   0ull},
54577         {"ICR0"                        ,        16,     1,      131,    "RO",   0,      0,      0ull,   0ull},
54578         {"ICNRCB"                      ,        17,     1,      131,    "RO",   0,      0,      0ull,   0ull},
54579         {"RESERVED_18_63"              ,        18,     46,     131,    "RAZ",  1,      1,      0,      0},
54580         {"FAU_END"                     ,        0,      1,      132,    "R/W",  0,      0,      0ull,   0ull},
54581         {"DWB_ENB"                     ,        1,      1,      132,    "R/W",  0,      0,      1ull,   1ull},
54582         {"PKO_ENB"                     ,        2,      1,      132,    "R/W",  0,      0,      0ull,   0ull},
54583         {"INB_MAT"                     ,        3,      1,      132,    "R/W1C",        0,      0,      0ull,   0ull},
54584         {"OUTB_MAT"                    ,        4,      1,      132,    "R/W1C",        0,      0,      0ull,   0ull},
54585         {"RESERVED_5_63"               ,        5,      59,     132,    "RAZ",  1,      1,      0,      0},
54586         {"TOUT_VAL"                    ,        0,      12,     133,    "R/W",  0,      0,      4ull,   4ull},
54587         {"TOUT_ENB"                    ,        12,     1,      133,    "R/W",  0,      0,      1ull,   0ull},
54588         {"RESERVED_13_63"              ,        13,     51,     133,    "RAZ",  1,      1,      0,      0},
54589         {"SRC"                         ,        0,      8,      134,    "R/W",  0,      1,      0ull,   0},
54590         {"DST"                         ,        8,      9,      134,    "R/W",  0,      1,      0ull,   0},
54591         {"OPC"                         ,        17,     4,      134,    "R/W",  0,      1,      0ull,   0},
54592         {"MASK"                        ,        21,     8,      134,    "R/W",  0,      1,      0ull,   0},
54593         {"RESERVED_29_63"              ,        29,     35,     134,    "RAZ",  1,      1,      0,      0},
54594         {"SRC"                         ,        0,      8,      135,    "R/W",  0,      1,      0ull,   0},
54595         {"DST"                         ,        8,      9,      135,    "R/W",  0,      1,      0ull,   0},
54596         {"OPC"                         ,        17,     4,      135,    "R/W",  0,      1,      0ull,   0},
54597         {"MASK"                        ,        21,     8,      135,    "R/W",  0,      1,      0ull,   0},
54598         {"RESERVED_29_63"              ,        29,     35,     135,    "RAZ",  1,      1,      0,      0},
54599         {"DATA"                        ,        0,      64,     136,    "R/W",  0,      1,      0ull,   0},
54600         {"DATA"                        ,        0,      64,     137,    "R/W",  0,      1,      0ull,   0},
54601         {"NP_SOP"                      ,        0,      1,      138,    "R/W",  0,      0,      0ull,   0ull},
54602         {"NP_EOP"                      ,        1,      1,      138,    "R/W",  0,      0,      0ull,   0ull},
54603         {"P_SOP"                       ,        2,      1,      138,    "R/W",  0,      0,      0ull,   0ull},
54604         {"P_EOP"                       ,        3,      1,      138,    "R/W",  0,      0,      0ull,   0ull},
54605         {"NP_DAT"                      ,        4,      1,      138,    "R/W",  0,      0,      0ull,   0ull},
54606         {"P_DAT"                       ,        5,      1,      138,    "R/W",  0,      0,      0ull,   0ull},
54607         {"RESERVED_6_63"               ,        6,      58,     138,    "RAZ",  1,      1,      0,      0},
54608         {"NP_SOP"                      ,        0,      1,      139,    "R/W1C",        0,      0,      0ull,   0ull},
54609         {"NP_EOP"                      ,        1,      1,      139,    "R/W1C",        0,      0,      0ull,   0ull},
54610         {"P_SOP"                       ,        2,      1,      139,    "R/W1C",        0,      0,      0ull,   0ull},
54611         {"P_EOP"                       ,        3,      1,      139,    "R/W1C",        0,      0,      0ull,   0ull},
54612         {"NP_DAT"                      ,        4,      1,      139,    "R/W1C",        0,      0,      0ull,   0ull},
54613         {"P_DAT"                       ,        5,      1,      139,    "R/W1C",        0,      0,      0ull,   0ull},
54614         {"RESERVED_6_63"               ,        6,      58,     139,    "RAZ",  1,      1,      0,      0},
54615         {"SRC"                         ,        0,      9,      140,    "R/W",  0,      1,      0ull,   0},
54616         {"DST"                         ,        9,      8,      140,    "R/W",  0,      1,      0ull,   0},
54617         {"EOT"                         ,        17,     1,      140,    "R/W",  0,      1,      0ull,   0},
54618         {"MASK"                        ,        18,     8,      140,    "R/W",  0,      1,      0ull,   0},
54619         {"RESERVED_26_63"              ,        26,     38,     140,    "RAZ",  1,      1,      0,      0},
54620         {"SRC"                         ,        0,      9,      141,    "R/W",  0,      1,      0ull,   0},
54621         {"DST"                         ,        9,      8,      141,    "R/W",  0,      1,      0ull,   0},
54622         {"EOT"                         ,        17,     1,      141,    "R/W",  0,      1,      0ull,   0},
54623         {"MASK"                        ,        18,     8,      141,    "R/W",  0,      1,      0ull,   0},
54624         {"RESERVED_26_63"              ,        26,     38,     141,    "RAZ",  1,      1,      0,      0},
54625         {"DATA"                        ,        0,      64,     142,    "R/W",  0,      1,      0ull,   0},
54626         {"DATA"                        ,        0,      64,     143,    "R/W",  0,      1,      0ull,   0},
54627         {"PORT"                        ,        0,      6,      144,    "RO",   0,      1,      0ull,   0},
54628         {"RESERVED_6_63"               ,        6,      58,     144,    "RAZ",  1,      1,      0,      0},
54629         {"SKIP_SZ"                     ,        0,      6,      145,    "R/W",  0,      0,      0ull,   0ull},
54630         {"RESERVED_6_63"               ,        6,      58,     145,    "RAZ",  1,      1,      0,      0},
54631         {"BACK"                        ,        0,      4,      146,    "R/W",  0,      0,      0ull,   0ull},
54632         {"RESERVED_4_63"               ,        4,      60,     146,    "RAZ",  1,      1,      0,      0},
54633         {"BACK"                        ,        0,      4,      147,    "R/W",  0,      0,      0ull,   0ull},
54634         {"RESERVED_4_63"               ,        4,      60,     147,    "RAZ",  1,      1,      0,      0},
54635         {"PWP"                         ,        0,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54636         {"IPD_NEW"                     ,        1,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54637         {"IPD_OLD"                     ,        2,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54638         {"PRC_OFF"                     ,        3,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54639         {"PWQ0"                        ,        4,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54640         {"PWQ1"                        ,        5,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54641         {"PBM_WORD"                    ,        6,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54642         {"PBM0"                        ,        7,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54643         {"PBM1"                        ,        8,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54644         {"PBM2"                        ,        9,      1,      148,    "RO",   0,      0,      0ull,   0ull},
54645         {"PBM3"                        ,        10,     1,      148,    "RO",   0,      0,      0ull,   0ull},
54646         {"IPQ_PBE0"                    ,        11,     1,      148,    "RO",   0,      0,      0ull,   0ull},
54647         {"IPQ_PBE1"                    ,        12,     1,      148,    "RO",   0,      0,      0ull,   0ull},
54648         {"PWQ_POW"                     ,        13,     1,      148,    "RO",   0,      0,      0ull,   0ull},
54649         {"PWQ_WP1"                     ,        14,     1,      148,    "RO",   0,      0,      0ull,   0ull},
54650         {"PWQ_WQED"                    ,        15,     1,      148,    "RO",   0,      0,      0ull,   0ull},
54651         {"RESERVED_16_63"              ,        16,     48,     148,    "RAZ",  1,      1,      0,      0},
54652         {"PRT_ENB"                     ,        0,      36,     149,    "R/W",  0,      0,      0ull,   0ull},
54653         {"RESERVED_36_63"              ,        36,     28,     149,    "RAZ",  1,      1,      0,      0},
54654         {"CLK_CNT"                     ,        0,      64,     150,    "RO",   0,      0,      0ull,   0ull},
54655         {"IPD_EN"                      ,        0,      1,      151,    "R/W",  0,      0,      0ull,   0ull},
54656         {"OPC_MODE"                    ,        1,      2,      151,    "R/W",  0,      0,      0ull,   0ull},
54657         {"PBP_EN"                      ,        3,      1,      151,    "R/W",  0,      0,      0ull,   0ull},
54658         {"WQE_LEND"                    ,        4,      1,      151,    "R/W",  0,      0,      0ull,   0ull},
54659         {"PKT_LEND"                    ,        5,      1,      151,    "R/W",  0,      0,      0ull,   0ull},
54660         {"NADDBUF"                     ,        6,      1,      151,    "R/W",  0,      0,      0ull,   0ull},
54661         {"ADDPKT"                      ,        7,      1,      151,    "R/W",  0,      0,      0ull,   0ull},
54662         {"RESET"                       ,        8,      1,      151,    "R/W",  0,      0,      0ull,   0ull},
54663         {"LEN_M8"                      ,        9,      1,      151,    "R/W",  0,      0,      0ull,   1ull},
54664         {"PKT_OFF"                     ,        10,     1,      151,    "R/W",  0,      0,      0ull,   0ull},
54665         {"IPD_FULL"                    ,        11,     1,      151,    "R/W",  0,      0,      0ull,   0ull},
54666         {"PQ_NABUF"                    ,        12,     1,      151,    "R/W",  0,      0,      0ull,   0ull},
54667         {"PQ_APKT"                     ,        13,     1,      151,    "R/W",  0,      0,      0ull,   0ull},
54668         {"NO_WPTR"                     ,        14,     1,      151,    "R/W",  0,      0,      0ull,   0ull},
54669         {"RESERVED_15_63"              ,        15,     49,     151,    "RAZ",  1,      1,      0,      0},
54670         {"PRC_PAR0"                    ,        0,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54671         {"PRC_PAR1"                    ,        1,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54672         {"PRC_PAR2"                    ,        2,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54673         {"PRC_PAR3"                    ,        3,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54674         {"BP_SUB"                      ,        4,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54675         {"DC_OVR"                      ,        5,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54676         {"CC_OVR"                      ,        6,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54677         {"C_COLL"                      ,        7,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54678         {"D_COLL"                      ,        8,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54679         {"BC_OVR"                      ,        9,      1,      152,    "R/W",  0,      0,      0ull,   0ull},
54680         {"RESERVED_10_63"              ,        10,     54,     152,    "RAZ",  1,      1,      0,      0},
54681         {"PRC_PAR0"                    ,        0,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54682         {"PRC_PAR1"                    ,        1,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54683         {"PRC_PAR2"                    ,        2,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54684         {"PRC_PAR3"                    ,        3,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54685         {"BP_SUB"                      ,        4,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54686         {"DC_OVR"                      ,        5,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54687         {"CC_OVR"                      ,        6,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54688         {"C_COLL"                      ,        7,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54689         {"D_COLL"                      ,        8,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54690         {"BC_OVR"                      ,        9,      1,      153,    "R/W1C",        0,      0,      0ull,   0ull},
54691         {"RESERVED_10_63"              ,        10,     54,     153,    "RAZ",  1,      1,      0,      0},
54692         {"SKIP_SZ"                     ,        0,      6,      154,    "R/W",  0,      0,      0ull,   0ull},
54693         {"RESERVED_6_63"               ,        6,      58,     154,    "RAZ",  1,      1,      0,      0},
54694         {"MB_SIZE"                     ,        0,      12,     155,    "R/W",  0,      0,      32ull,  32ull},
54695         {"RESERVED_12_63"              ,        12,     52,     155,    "RAZ",  1,      1,      0,      0},
54696         {"PTR"                         ,        0,      29,     156,    "RO",   1,      1,      0,      0},
54697         {"RESERVED_29_63"              ,        29,     35,     156,    "RAZ",  1,      1,      0,      0},
54698         {"PAGE_CNT"                    ,        0,      17,     157,    "R/W",  0,      0,      0ull,   0ull},
54699         {"BP_ENB"                      ,        17,     1,      157,    "R/W",  0,      0,      0ull,   0ull},
54700         {"RESERVED_18_63"              ,        18,     46,     157,    "RAZ",  1,      1,      0,      0},
54701         {"CNT_VAL"                     ,        0,      25,     158,    "RO",   0,      1,      0ull,   0},
54702         {"RESERVED_25_63"              ,        25,     39,     158,    "RAZ",  1,      1,      0,      0},
54703         {"RADDR"                       ,        0,      3,      159,    "R/W",  0,      0,      0ull,   0ull},
54704         {"CENA"                        ,        3,      1,      159,    "R/W",  0,      0,      1ull,   1ull},
54705         {"PTR"                         ,        4,      29,     159,    "RO",   1,      1,      0,      0},
54706         {"PRADDR"                      ,        33,     3,      159,    "RO",   1,      1,      0,      0},
54707         {"MAX_PKT"                     ,        36,     3,      159,    "RO",   0,      0,      5ull,   5ull},
54708         {"RESERVED_39_63"              ,        39,     25,     159,    "RAZ",  1,      1,      0,      0},
54709         {"RADDR"                       ,        0,      7,      160,    "R/W",  0,      0,      0ull,   0ull},
54710         {"CENA"                        ,        7,      1,      160,    "R/W",  0,      0,      1ull,   1ull},
54711         {"PTR"                         ,        8,      29,     160,    "RO",   1,      1,      0,      0},
54712         {"MAX_PKT"                     ,        37,     7,      160,    "RO",   0,      0,      5ull,   5ull},
54713         {"RESERVED_44_63"              ,        44,     20,     160,    "RAZ",  1,      1,      0,      0},
54714         {"WQE_PCNT"                    ,        0,      7,      161,    "RO",   0,      0,      0ull,   0ull},
54715         {"PKT_PCNT"                    ,        7,      7,      161,    "RO",   0,      0,      0ull,   0ull},
54716         {"PFIF_CNT"                    ,        14,     3,      161,    "RO",   0,      0,      0ull,   0ull},
54717         {"WQEV_CNT"                    ,        17,     1,      161,    "RO",   0,      0,      0ull,   0ull},
54718         {"PKTV_CNT"                    ,        18,     1,      161,    "RO",   0,      0,      0ull,   0ull},
54719         {"RESERVED_19_63"              ,        19,     45,     161,    "RAZ",  1,      1,      0,      0},
54720         {"RADDR"                       ,        0,      8,      162,    "R/W",  0,      0,      0ull,   0ull},
54721         {"CENA"                        ,        8,      1,      162,    "R/W",  0,      0,      1ull,   1ull},
54722         {"PTR"                         ,        9,      29,     162,    "RO",   1,      1,      0,      0},
54723         {"PRADDR"                      ,        38,     8,      162,    "RO",   1,      1,      0,      0},
54724         {"WRADDR"                      ,        46,     8,      162,    "RO",   1,      1,      0,      0},
54725         {"MAX_CNTS"                    ,        54,     7,      162,    "RO",   0,      0,      8ull,   8ull},
54726         {"RESERVED_61_63"              ,        61,     3,      162,    "RAZ",  1,      1,      0,      0},
54727         {"PASS"                        ,        0,      32,     163,    "R/W",  0,      1,      0ull,   0},
54728         {"DROP"                        ,        32,     32,     163,    "R/W",  0,      1,      0ull,   0},
54729         {"Q0_PCNT"                     ,        0,      32,     164,    "RO",   0,      0,      0ull,   0ull},
54730         {"RESERVED_32_63"              ,        32,     32,     164,    "RAZ",  1,      1,      0,      0},
54731         {"PRT_ENB"                     ,        0,      36,     165,    "R/W",  0,      0,      0ull,   0ull},
54732         {"AVG_DLY"                     ,        36,     14,     165,    "R/W",  0,      1,      0ull,   0},
54733         {"PRB_DLY"                     ,        50,     14,     165,    "R/W",  0,      0,      0ull,   0ull},
54734         {"PRB_CON"                     ,        0,      32,     166,    "R/W",  0,      1,      0ull,   0},
54735         {"AVG_CON"                     ,        32,     8,      166,    "R/W",  0,      1,      0ull,   0},
54736         {"NEW_CON"                     ,        40,     8,      166,    "R/W",  0,      1,      0ull,   0},
54737         {"USE_PCNT"                    ,        48,     1,      166,    "R/W",  0,      0,      0ull,   0ull},
54738         {"RESERVED_49_63"              ,        49,     15,     166,    "RAZ",  1,      1,      0,      0},
54739         {"PAGE_CNT"                    ,        0,      25,     167,    "R/W",  1,      0,      0,      0ull},
54740         {"PORT"                        ,        25,     6,      167,    "R/W",  1,      0,      0,      0ull},
54741         {"RESERVED_31_63"              ,        31,     33,     167,    "RAZ",  1,      1,      0,      0},
54742         {"PORT_BIT"                    ,        0,      3,      168,    "R/W",  0,      0,      7ull,   7ull},
54743         {"RESERVED_3_63"               ,        3,      61,     168,    "RAZ",  1,      1,      0,      0},
54744         {"WQE_POOL"                    ,        0,      3,      169,    "R/W",  0,      0,      1ull,   1ull},
54745         {"RESERVED_3_63"               ,        3,      61,     169,    "RAZ",  1,      1,      0,      0},
54746         {"PTR"                         ,        0,      29,     170,    "RO",   1,      1,      0,      0},
54747         {"RESERVED_29_63"              ,        29,     35,     170,    "RAZ",  1,      1,      0,      0},
54748         {"WLB_DAT"                     ,        0,      4,      171,    "RO",   0,      0,      0ull,   0ull},
54749         {"STIN_MSK"                    ,        4,      1,      171,    "RO",   0,      0,      0ull,   0ull},
54750         {"DT"                          ,        5,      1,      171,    "RO",   0,      0,      0ull,   0ull},
54751         {"DTCNT"                       ,        6,      10,     171,    "RO",   0,      0,      0ull,   0ull},
54752         {"RESERVED_16_18"              ,        16,     3,      171,    "RAZ",  0,      0,      0ull,   0ull},
54753         {"WLB_MSK"                     ,        19,     4,      171,    "RO",   0,      0,      0ull,   0ull},
54754         {"DTBNK"                       ,        23,     1,      171,    "RO",   0,      0,      0ull,   0ull},
54755         {"RESERVED_24_63"              ,        24,     40,     171,    "RAZ",  0,      0,      0ull,   0ull},
54756         {"L2T"                         ,        0,      9,      172,    "RO",   0,      0,      0ull,   0ull},
54757         {"VAB_VWCF"                    ,        9,      1,      172,    "RO",   0,      0,      0ull,   0ull},
54758         {"LRF"                         ,        10,     2,      172,    "RO",   0,      0,      0ull,   0ull},
54759         {"VWDF"                        ,        12,     4,      172,    "RO",   0,      0,      0ull,   0ull},
54760         {"RESERVED_16_63"              ,        16,     48,     172,    "RAZ",  0,      0,      0ull,   0ull},
54761         {"XRDDAT"                      ,        0,      1,      173,    "RO",   0,      0,      0ull,   0ull},
54762         {"XRDMSK"                      ,        1,      1,      173,    "RO",   0,      0,      0ull,   0ull},
54763         {"RESERVED_2_2"                ,        2,      1,      173,    "RAZ",  0,      0,      0ull,   0ull},
54764         {"IPCBST"                      ,        3,      1,      173,    "RO",   0,      0,      0ull,   0ull},
54765         {"RESERVED_4_7"                ,        4,      4,      173,    "RAZ",  0,      0,      0ull,   0ull},
54766         {"RMDF"                        ,        8,      4,      173,    "RO",   0,      0,      0ull,   0ull},
54767         {"MRB"                         ,        12,     4,      173,    "RO",   0,      0,      0ull,   0ull},
54768         {"RESERVED_16_63"              ,        16,     48,     173,    "RAZ",  0,      0,      0ull,   0ull},
54769         {"LRF_ARB_MODE"                ,        0,      1,      174,    "R/W",  0,      0,      1ull,   1ull},
54770         {"RFB_ARB_MODE"                ,        1,      1,      174,    "R/W",  0,      0,      1ull,   1ull},
54771         {"RSP_ARB_MODE"                ,        2,      1,      174,    "R/W",  0,      0,      1ull,   1ull},
54772         {"MWF_CRD"                     ,        3,      4,      174,    "R/W",  0,      0,      2ull,   2ull},
54773         {"IDXALIAS"                    ,        7,      1,      174,    "R/W",  0,      0,      0ull,   1ull},
54774         {"FPEN"                        ,        8,      1,      174,    "R/W",  0,      0,      0ull,   0ull},
54775         {"FPEMPTY"                     ,        9,      1,      174,    "R/W",  0,      0,      0ull,   0ull},
54776         {"FPEXP"                       ,        10,     4,      174,    "R/W",  0,      0,      0ull,   0ull},
54777         {"RESERVED_14_17"              ,        14,     4,      174,    "RAZ",  1,      1,      0,      0},
54778         {"LBIST"                       ,        18,     1,      174,    "R/W",  0,      0,      0ull,   0ull},
54779         {"BSTRUN"                      ,        19,     1,      174,    "RO",   0,      0,      0ull,   0ull},
54780         {"RESERVED_20_63"              ,        20,     44,     174,    "RAZ",  1,      1,      0,      0},
54781         {"L2T"                         ,        0,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
54782         {"L2D"                         ,        1,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
54783         {"FINV"                        ,        2,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
54784         {"SET"                         ,        3,      3,      175,    "R/W",  0,      0,      0ull,   0ull},
54785         {"PPNUM"                       ,        6,      1,      175,    "R/W",  0,      0,      0ull,   0ull},
54786         {"RESERVED_7_9"                ,        7,      3,      175,    "RAZ",  0,      0,      0ull,   0ull},
54787         {"LFB_DMP"                     ,        10,     1,      175,    "R/W",  0,      0,      0ull,   0ull},
54788         {"LFB_ENUM"                    ,        11,     3,      175,    "R/W",  0,      0,      0ull,   0ull},
54789         {"RESERVED_14_63"              ,        14,     50,     175,    "RAZ",  0,      0,      0ull,   0ull},
54790         {"DT_TAG"                      ,        0,      29,     176,    "RO",   0,      0,      0ull,   0ull},
54791         {"DT_VLD"                      ,        29,     1,      176,    "RO",   0,      0,      0ull,   0ull},
54792         {"RESERVED_30_30"              ,        30,     1,      176,    "RAZ",  0,      0,      0ull,   0ull},
54793         {"DTENA"                       ,        31,     1,      176,    "R/W",  0,      0,      0ull,   0ull},
54794         {"RESERVED_32_63"              ,        32,     32,     176,    "RAZ",  0,      0,      0ull,   0ull},
54795         {"LCK_ENA"                     ,        0,      1,      177,    "R/W",  0,      0,      0ull,   0ull},
54796         {"RESERVED_1_3"                ,        1,      3,      177,    "RAZ",  0,      0,      0ull,   0ull},
54797         {"LCK_BASE"                    ,        4,      27,     177,    "R/W",  0,      0,      0ull,   0ull},
54798         {"RESERVED_31_63"              ,        31,     33,     177,    "RAZ",  0,      0,      0ull,   0ull},
54799         {"LCK_OFFSET"                  ,        0,      10,     178,    "R/W",  0,      0,      0ull,   0ull},
54800         {"RESERVED_10_63"              ,        10,     54,     178,    "RAZ",  0,      0,      0ull,   0ull},
54801         {"VLD"                         ,        0,      1,      179,    "RO",   0,      0,      0ull,   0ull},
54802         {"CMD"                         ,        1,      4,      179,    "RO",   0,      0,      0ull,   0ull},
54803         {"SID"                         ,        5,      9,      179,    "RO",   0,      0,      0ull,   0ull},
54804         {"VABNUM"                      ,        14,     3,      179,    "RO",   0,      0,      0ull,   0ull},
54805         {"RESERVED_17_17"              ,        17,     1,      179,    "RAZ",  0,      0,      0ull,   0ull},
54806         {"SET"                         ,        18,     3,      179,    "RO",   0,      0,      0ull,   0ull},
54807         {"IHD"                         ,        21,     1,      179,    "RO",   0,      0,      0ull,   0ull},
54808         {"ITL"                         ,        22,     1,      179,    "RO",   0,      0,      0ull,   0ull},
54809         {"INXT"                        ,        23,     3,      179,    "RO",   0,      0,      0ull,   0ull},
54810         {"RESERVED_26_26"              ,        26,     1,      179,    "RAZ",  0,      0,      0ull,   0ull},
54811         {"VAM"                         ,        27,     1,      179,    "RO",   0,      0,      0ull,   0ull},
54812         {"STCFL"                       ,        28,     1,      179,    "RO",   0,      0,      0ull,   0ull},
54813         {"STINV"                       ,        29,     1,      179,    "RO",   0,      0,      0ull,   0ull},
54814         {"STPND"                       ,        30,     1,      179,    "RO",   0,      0,      0ull,   0ull},
54815         {"STCPND"                      ,        31,     1,      179,    "RO",   0,      0,      0ull,   0ull},
54816         {"RESERVED_32_63"              ,        32,     32,     179,    "RAZ",  0,      0,      0ull,   0ull},
54817         {"VLD"                         ,        0,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54818         {"WTPRB"                       ,        1,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54819         {"PRBRTY"                      ,        2,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54820         {"WTMFL"                       ,        3,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54821         {"WTVTM"                       ,        4,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54822         {"WTSTRSC"                     ,        5,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54823         {"WTSTRSP"                     ,        6,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54824         {"WTSTDT"                      ,        7,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54825         {"WTRDA"                       ,        8,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54826         {"WTSTM"                       ,        9,      1,      180,    "RO",   0,      0,      0ull,   0ull},
54827         {"WTWRM"                       ,        10,     1,      180,    "RO",   0,      0,      0ull,   0ull},
54828         {"WTWHF"                       ,        11,     1,      180,    "RO",   0,      0,      0ull,   0ull},
54829         {"WTWHP"                       ,        12,     1,      180,    "RO",   0,      0,      0ull,   0ull},
54830         {"WTDQ"                        ,        13,     1,      180,    "RO",   0,      0,      0ull,   0ull},
54831         {"WTDW"                        ,        14,     1,      180,    "RO",   0,      0,      0ull,   0ull},
54832         {"WTRSP"                       ,        15,     1,      180,    "RO",   0,      0,      0ull,   0ull},
54833         {"BID"                         ,        16,     2,      180,    "RO",   0,      0,      0ull,   0ull},
54834         {"DSGOING"                     ,        18,     1,      180,    "RO",   0,      0,      0ull,   0ull},
54835         {"RESERVED_19_63"              ,        19,     45,     180,    "RAZ",  0,      0,      0ull,   0ull},
54836         {"LFB_IDX"                     ,        0,      7,      181,    "RO",   0,      0,      0ull,   0ull},
54837         {"LFB_TAG"                     ,        7,      20,     181,    "RO",   0,      0,      0ull,   0ull},
54838         {"RESERVED_27_63"              ,        27,     37,     181,    "RAZ",  0,      0,      0ull,   0ull},
54839         {"LFB_HWM"                     ,        0,      3,      182,    "R/W",  0,      0,      7ull,   7ull},
54840         {"RESERVED_3_3"                ,        3,      1,      182,    "RAZ",  0,      0,      0ull,   0ull},
54841         {"STPARTDIS"                   ,        4,      1,      182,    "R/W",  0,      0,      0ull,   0ull},
54842         {"RESERVED_5_63"               ,        5,      59,     182,    "RAZ",  0,      0,      0ull,   0ull},
54843         {"PFCNT0"                      ,        0,      36,     183,    "RO",   0,      0,      0ull,   0ull},
54844         {"RESERVED_36_63"              ,        36,     28,     183,    "RAZ",  0,      0,      0ull,   0ull},
54845         {"CNT0SEL"                     ,        0,      6,      184,    "R/W",  0,      0,      0ull,   0ull},
54846         {"CNT0CLR"                     ,        6,      1,      184,    "R/W",  0,      0,      0ull,   0ull},
54847         {"CNT0ENA"                     ,        7,      1,      184,    "R/W",  0,      0,      0ull,   0ull},
54848         {"CNT1SEL"                     ,        8,      6,      184,    "R/W",  0,      0,      0ull,   0ull},
54849         {"CNT1CLR"                     ,        14,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54850         {"CNT1ENA"                     ,        15,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54851         {"CNT2SEL"                     ,        16,     6,      184,    "R/W",  0,      0,      0ull,   0ull},
54852         {"CNT2CLR"                     ,        22,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54853         {"CNT2ENA"                     ,        23,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54854         {"CNT3SEL"                     ,        24,     6,      184,    "R/W",  0,      0,      0ull,   0ull},
54855         {"CNT3CLR"                     ,        30,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54856         {"CNT3ENA"                     ,        31,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54857         {"CNT0RDCLR"                   ,        32,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54858         {"CNT1RDCLR"                   ,        33,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54859         {"CNT2RDCLR"                   ,        34,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54860         {"CNT3RDCLR"                   ,        35,     1,      184,    "R/W",  0,      0,      0ull,   0ull},
54861         {"RESERVED_36_63"              ,        36,     28,     184,    "RAZ",  0,      0,      0ull,   0ull},
54862         {"UMSK0"                       ,        0,      8,      185,    "R/W",  0,      0,      0ull,   0ull},
54863         {"UMSK1"                       ,        8,      8,      185,    "R/W",  0,      0,      0ull,   0ull},
54864         {"RESERVED_16_63"              ,        16,     48,     185,    "RAZ",  0,      0,      0ull,   0ull},
54865         {"UMSKIOB"                     ,        0,      8,      186,    "R/W",  0,      0,      0ull,   0ull},
54866         {"RESERVED_8_63"               ,        8,      56,     186,    "RAZ",  0,      0,      0ull,   0ull},
54867         {"Q0STAT"                      ,        0,      34,     187,    "RO",   0,      0,      0ull,   0ull},
54868         {"FTL"                         ,        34,     1,      187,    "RO",   0,      0,      0ull,   0ull},
54869         {"RESERVED_35_63"              ,        35,     29,     187,    "RAZ",  0,      0,      0ull,   0ull},
54870         {"Q1STAT"                      ,        0,      34,     188,    "RO",   0,      0,      0ull,   0ull},
54871         {"RESERVED_34_63"              ,        34,     30,     188,    "RAZ",  0,      0,      0ull,   0ull},
54872         {"Q2STAT"                      ,        0,      34,     189,    "RO",   0,      0,      0ull,   0ull},
54873         {"RESERVED_34_63"              ,        34,     30,     189,    "RAZ",  0,      0,      0ull,   0ull},
54874         {"Q3STAT"                      ,        0,      34,     190,    "RO",   0,      0,      0ull,   0ull},
54875         {"RESERVED_34_63"              ,        34,     30,     190,    "RAZ",  0,      0,      0ull,   0ull},
54876         {"ECC_ENA"                     ,        0,      1,      191,    "R/W",  0,      0,      0ull,   1ull},
54877         {"SEC_INTENA"                  ,        1,      1,      191,    "R/W",  0,      0,      0ull,   1ull},
54878         {"DED_INTENA"                  ,        2,      1,      191,    "R/W",  0,      0,      0ull,   1ull},
54879         {"SEC_ERR"                     ,        3,      1,      191,    "R/W1C",        0,      0,      0ull,   0ull},
54880         {"DED_ERR"                     ,        4,      1,      191,    "R/W1C",        0,      0,      0ull,   0ull},
54881         {"BMHCLSEL"                    ,        5,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
54882         {"RESERVED_6_63"               ,        6,      58,     191,    "RAZ",  0,      0,      0ull,   0ull},
54883         {"FADR"                        ,        0,      8,      192,    "RO",   0,      0,      0ull,   0ull},
54884         {"RESERVED_8_10"               ,        8,      3,      192,    "RAZ",  0,      0,      0ull,   0ull},
54885         {"FSET"                        ,        11,     3,      192,    "RO",   0,      0,      0ull,   0ull},
54886         {"FOWMSK"                      ,        14,     4,      192,    "RO",   0,      0,      0ull,   0ull},
54887         {"RESERVED_18_63"              ,        18,     46,     192,    "RAZ",  0,      0,      0ull,   0ull},
54888         {"FSYN_OW0"                    ,        0,      10,     193,    "RO",   0,      0,      0ull,   0ull},
54889         {"FSYN_OW1"                    ,        10,     10,     193,    "RO",   0,      0,      0ull,   0ull},
54890         {"RESERVED_20_63"              ,        20,     44,     193,    "RAZ",  0,      0,      0ull,   0ull},
54891         {"FSYN_OW2"                    ,        0,      10,     194,    "RO",   0,      0,      0ull,   0ull},
54892         {"FSYN_OW3"                    ,        10,     10,     194,    "RO",   0,      0,      0ull,   0ull},
54893         {"RESERVED_20_63"              ,        20,     44,     194,    "RAZ",  0,      0,      0ull,   0ull},
54894         {"Q0FUS"                       ,        0,      34,     195,    "RO",   0,      0,      0ull,   0ull},
54895         {"RESERVED_34_63"              ,        34,     30,     195,    "RAZ",  0,      0,      0ull,   0ull},
54896         {"Q1FUS"                       ,        0,      34,     196,    "RO",   0,      0,      0ull,   0ull},
54897         {"RESERVED_34_63"              ,        34,     30,     196,    "RAZ",  0,      0,      0ull,   0ull},
54898         {"Q2FUS"                       ,        0,      34,     197,    "RO",   0,      0,      0ull,   0ull},
54899         {"RESERVED_34_63"              ,        34,     30,     197,    "RAZ",  0,      0,      0ull,   0ull},
54900         {"Q3FUS"                       ,        0,      34,     198,    "RO",   0,      0,      0ull,   0ull},
54901         {"CRIP_64K"                    ,        34,     1,      198,    "RO",   0,      0,      0ull,   0ull},
54902         {"CRIP_32K"                    ,        35,     1,      198,    "RO",   0,      0,      0ull,   0ull},
54903         {"RESERVED_36_36"              ,        36,     1,      198,    "RAZ",  0,      0,      0ull,   0ull},
54904         {"EMA_CTL"                     ,        37,     3,      198,    "RO",   0,      0,      0ull,   0ull},
54905         {"RESERVED_40_63"              ,        40,     24,     198,    "RAZ",  0,      0,      0ull,   0ull},
54906         {"ECC_ENA"                     ,        0,      1,      199,    "R/W",  0,      0,      0ull,   1ull},
54907         {"SEC_INTENA"                  ,        1,      1,      199,    "R/W",  0,      0,      0ull,   1ull},
54908         {"DED_INTENA"                  ,        2,      1,      199,    "R/W",  0,      0,      0ull,   1ull},
54909         {"SEC_ERR"                     ,        3,      1,      199,    "R/W1C",        0,      0,      0ull,   0ull},
54910         {"DED_ERR"                     ,        4,      1,      199,    "R/W1C",        0,      0,      0ull,   0ull},
54911         {"FSYN"                        ,        5,      6,      199,    "RO",   0,      0,      0ull,   0ull},
54912         {"FADR"                        ,        11,     7,      199,    "RO",   0,      0,      0ull,   0ull},
54913         {"RESERVED_18_20"              ,        18,     3,      199,    "RAZ",  0,      0,      0ull,   0ull},
54914         {"FSET"                        ,        21,     3,      199,    "RO",   0,      0,      0ull,   0ull},
54915         {"LCKERR"                      ,        24,     1,      199,    "R/W1C",        0,      0,      0ull,   0ull},
54916         {"LCK_INTENA"                  ,        25,     1,      199,    "R/W",  0,      0,      0ull,   1ull},
54917         {"LCKERR2"                     ,        26,     1,      199,    "R/W1C",        0,      0,      0ull,   0ull},
54918         {"LCK_INTENA2"                 ,        27,     1,      199,    "R/W",  0,      0,      0ull,   1ull},
54919         {"RESERVED_28_63"              ,        28,     36,     199,    "RAZ",  0,      0,      0ull,   0ull},
54920         {"START"                       ,        0,      1,      200,    "R/W",  0,      0,      0ull,   0ull},
54921         {"RESERVED_1_63"               ,        1,      63,     200,    "RAZ",  1,      0,      0,      0ull},
54922         {"MRD"                         ,        0,      3,      201,    "RO",   1,      0,      0,      0ull},
54923         {"MRF"                         ,        3,      1,      201,    "RO",   1,      0,      0,      0ull},
54924         {"MWC"                         ,        4,      1,      201,    "RO",   1,      0,      0,      0ull},
54925         {"MWD"                         ,        5,      3,      201,    "RO",   1,      0,      0,      0ull},
54926         {"MWF"                         ,        8,      1,      201,    "RO",   1,      0,      0,      0ull},
54927         {"RESERVED_9_63"               ,        9,      55,     201,    "RAZ",  1,      0,      0,      0ull},
54928         {"PCTL_DAT"                    ,        0,      5,      202,    "R/W",  0,      1,      0ull,   0},
54929         {"RESERVED_5_11"               ,        5,      7,      202,    "RAZ",  0,      1,      0ull,   0},
54930         {"PCTL_CSR"                    ,        12,     4,      202,    "R/W",  0,      1,      15ull,  0},
54931         {"NCTL_DAT"                    ,        16,     4,      202,    "R/W",  0,      1,      0ull,   0},
54932         {"RESERVED_20_27"              ,        20,     8,      202,    "RAZ",  0,      1,      0ull,   0},
54933         {"NCTL_CSR"                    ,        28,     4,      202,    "R/W",  0,      1,      15ull,  0},
54934         {"RESERVED_32_63"              ,        32,     32,     202,    "RAZ",  0,      0,      0ull,   0ull},
54935         {"DIC"                         ,        0,      2,      203,    "R/W",  0,      0,      0ull,   0ull},
54936         {"QS_DIC"                      ,        2,      2,      203,    "R/W",  0,      0,      2ull,   2ull},
54937         {"TSKW"                        ,        4,      2,      203,    "R/W",  0,      0,      0ull,   1ull},
54938         {"SIL_LAT"                     ,        6,      2,      203,    "R/W",  0,      0,      1ull,   1ull},
54939         {"BPRCH"                       ,        8,      1,      203,    "R/W",  0,      1,      0ull,   0},
54940         {"FPRCH2"                      ,        9,      1,      203,    "R/W",  0,      0,      0ull,   1ull},
54941         {"MODE32B"                     ,        10,     1,      203,    "R/W",  0,      0,      1ull,   1ull},
54942         {"DRESET"                      ,        11,     1,      203,    "R/W",  0,      0,      1ull,   0ull},
54943         {"INORDER_MRF"                 ,        12,     1,      203,    "R/W",  0,      0,      0ull,   0ull},
54944         {"INORDER_MWF"                 ,        13,     1,      203,    "RAZ",  0,      0,      0ull,   0ull},
54945         {"R2R_SLOT"                    ,        14,     1,      203,    "R/W",  0,      0,      0ull,   0ull},
54946         {"RDIMM_ENA"                   ,        15,     1,      203,    "R/W",  0,      1,      0ull,   0},
54947         {"PLL_BYPASS"                  ,        16,     1,      203,    "R/W",  0,      0,      0ull,   0ull},
54948         {"RESERVED_17_17"              ,        17,     1,      203,    "RAZ",  0,      0,      0ull,   0ull},
54949         {"MAX_WRITE_BATCH"             ,        18,     4,      203,    "R/W",  0,      0,      8ull,   8ull},
54950         {"XOR_BANK"                    ,        22,     1,      203,    "R/W",  0,      0,      0ull,   1ull},
54951         {"SLOW_SCF"                    ,        23,     1,      203,    "R/W",  0,      0,      0ull,   0ull},
54952         {"DDR__PCTL"                   ,        24,     4,      203,    "RO",   1,      1,      0,      0},
54953         {"DDR__NCTL"                   ,        28,     4,      203,    "RO",   1,      1,      0,      0},
54954         {"RESERVED_32_63"              ,        32,     32,     203,    "RAZ",  1,      1,      0,      0},
54955         {"DATA_LAYOUT"                 ,        0,      2,      204,    "R/W",  0,      0,      0ull,   0ull},
54956         {"RESERVED_2_7"                ,        2,      6,      204,    "RAZ",  0,      1,      0ull,   0},
54957         {"DCC_ENABLE"                  ,        8,      1,      204,    "R/W",  0,      0,      0ull,   0ull},
54958         {"SIL_MODE"                    ,        9,      1,      204,    "R/W",  0,      0,      0ull,   1ull},
54959         {"RESERVED_10_63"              ,        10,     54,     204,    "RAZ",  1,      1,      0,      0},
54960         {"DCLKCNT_HI"                  ,        0,      32,     205,    "RO",   0,      0,      0ull,   0ull},
54961         {"RESERVED_32_63"              ,        32,     32,     205,    "RAZ",  1,      1,      0,      0},
54962         {"DCLKCNT_LO"                  ,        0,      32,     206,    "RO",   0,      0,      0ull,   0ull},
54963         {"RESERVED_32_63"              ,        32,     32,     206,    "RAZ",  1,      1,      0,      0},
54964         {"DDR2"                        ,        0,      1,      207,    "R/W",  0,      0,      1ull,   1ull},
54965         {"RDQS"                        ,        1,      1,      207,    "R/W",  0,      0,      0ull,   0ull},
54966         {"DLL90_BYP"                   ,        2,      1,      207,    "R/W",  0,      0,      0ull,   0ull},
54967         {"DLL90_VLU"                   ,        3,      5,      207,    "R/W",  0,      1,      0ull,   0},
54968         {"QDLL_ENA"                    ,        8,      1,      207,    "R/W",  0,      0,      0ull,   0ull},
54969         {"ODT_ENA"                     ,        9,      1,      207,    "R/W",  0,      0,      0ull,   0ull},
54970         {"DDR2T"                       ,        10,     1,      207,    "R/W",  0,      1,      0ull,   0},
54971         {"CRIP_MODE"                   ,        11,     1,      207,    "R/W",  0,      0,      0ull,   0ull},
54972         {"TFAW"                        ,        12,     5,      207,    "R/W",  0,      0,      0ull,   9ull},
54973         {"DDR_EOF"                     ,        17,     4,      207,    "R/W",  0,      0,      0ull,   0ull},
54974         {"SILO_HC"                     ,        21,     1,      207,    "R/W",  0,      1,      1ull,   0},
54975         {"TWR"                         ,        22,     3,      207,    "R/W",  0,      0,      3ull,   1ull},
54976         {"BWCNT"                       ,        25,     1,      207,    "R/W",  0,      0,      0ull,   0ull},
54977         {"POCAS"                       ,        26,     1,      207,    "R/W",  0,      0,      0ull,   0ull},
54978         {"ADDLAT"                      ,        27,     3,      207,    "R/W",  0,      0,      0ull,   0ull},
54979         {"BURST8"                      ,        30,     1,      207,    "R/W",  0,      0,      0ull,   1ull},
54980         {"BANK8"                       ,        31,     1,      207,    "R/W",  0,      1,      0ull,   0},
54981         {"RESERVED_32_63"              ,        32,     32,     207,    "RAZ",  0,      0,      0ull,   0ull},
54982         {"CLK"                         ,        0,      4,      208,    "R/W",  0,      0,      0ull,   0ull},
54983         {"RESERVED_4_4"                ,        4,      1,      208,    "RAZ",  0,      0,      0ull,   0ull},
54984         {"CMD"                         ,        5,      4,      208,    "R/W",  0,      0,      0ull,   0ull},
54985         {"RESERVED_9_9"                ,        9,      1,      208,    "RAZ",  0,      0,      0ull,   0ull},
54986         {"DQ"                          ,        10,     4,      208,    "R/W",  0,      0,      0ull,   0ull},
54987         {"RESERVED_14_63"              ,        14,     50,     208,    "RAZ",  0,      0,      0ull,   0ull},
54988         {"CS_MASK"                     ,        0,      8,      209,    "R/W",  0,      1,      0ull,   0},
54989         {"RESERVED_8_15"               ,        8,      8,      209,    "RAZ",  0,      1,      0ull,   0},
54990         {"ROW_LSB"                     ,        16,     3,      209,    "R/W",  0,      1,      3ull,   0},
54991         {"BANK8"                       ,        19,     1,      209,    "R/W",  0,      1,      0ull,   0},
54992         {"RESERVED_20_63"              ,        20,     44,     209,    "RAZ",  0,      1,      0ull,   0},
54993         {"MRDSYN0"                     ,        0,      8,      210,    "RO",   0,      0,      0ull,   0ull},
54994         {"MRDSYN1"                     ,        8,      8,      210,    "RO",   0,      0,      0ull,   0ull},
54995         {"MRDSYN2"                     ,        16,     8,      210,    "RO",   0,      0,      0ull,   0ull},
54996         {"MRDSYN3"                     ,        24,     8,      210,    "RO",   0,      0,      0ull,   0ull},
54997         {"RESERVED_32_63"              ,        32,     32,     210,    "RAZ",  1,      1,      0,      0},
54998         {"FCOL"                        ,        0,      12,     211,    "RO",   0,      0,      0ull,   0ull},
54999         {"FROW"                        ,        12,     14,     211,    "RO",   0,      0,      0ull,   0ull},
55000         {"FBANK"                       ,        26,     3,      211,    "RO",   0,      0,      0ull,   0ull},
55001         {"FBUNK"                       ,        29,     1,      211,    "RO",   0,      0,      0ull,   0ull},
55002         {"FDIMM"                       ,        30,     2,      211,    "RO",   0,      0,      0ull,   0ull},
55003         {"RESERVED_32_63"              ,        32,     32,     211,    "RAZ",  1,      1,      0,      0},
55004         {"IFBCNT_HI"                   ,        0,      32,     212,    "RO",   0,      0,      0ull,   0ull},
55005         {"RESERVED_32_63"              ,        32,     32,     212,    "RAZ",  1,      1,      0,      0},
55006         {"IFBCNT_LO"                   ,        0,      32,     213,    "RO",   0,      0,      0ull,   0ull},
55007         {"RESERVED_32_63"              ,        32,     32,     213,    "RAZ",  1,      1,      0,      0},
55008         {"INIT_START"                  ,        0,      1,      214,    "R/W",  0,      0,      0ull,   0ull},
55009         {"ECC_ENA"                     ,        1,      1,      214,    "R/W",  0,      0,      0ull,   1ull},
55010         {"ROW_LSB"                     ,        2,      3,      214,    "R/W",  0,      1,      3ull,   0},
55011         {"PBANK_LSB"                   ,        5,      4,      214,    "R/W",  0,      1,      5ull,   0},
55012         {"REF_INT"                     ,        9,      6,      214,    "R/W",  0,      0,      1ull,   2ull},
55013         {"TCL"                         ,        15,     4,      214,    "R/W",  0,      1,      3ull,   0},
55014         {"INTR_SEC_ENA"                ,        19,     1,      214,    "R/W",  0,      0,      0ull,   1ull},
55015         {"INTR_DED_ENA"                ,        20,     1,      214,    "R/W",  0,      0,      0ull,   1ull},
55016         {"SEC_ERR"                     ,        21,     4,      214,    "R/W1C",        0,      0,      0ull,   0ull},
55017         {"DED_ERR"                     ,        25,     4,      214,    "R/W1C",        0,      0,      0ull,   0ull},
55018         {"BUNK_ENA"                    ,        29,     1,      214,    "R/W",  0,      1,      0ull,   0},
55019         {"SILO_QC"                     ,        30,     1,      214,    "R/W",  0,      1,      0ull,   0},
55020         {"RESET"                       ,        31,     1,      214,    "RAZ",  1,      1,      0,      0},
55021         {"RESERVED_32_63"              ,        32,     32,     214,    "RAZ",  1,      1,      0,      0},
55022         {"TRAS"                        ,        0,      5,      215,    "R/W",  0,      0,      12ull,  12ull},
55023         {"TRCD"                        ,        5,      4,      215,    "R/W",  0,      0,      4ull,   4ull},
55024         {"TWTR"                        ,        9,      4,      215,    "R/W",  0,      0,      2ull,   2ull},
55025         {"TRP"                         ,        13,     4,      215,    "R/W",  0,      0,      5ull,   4ull},
55026         {"TRFC"                        ,        17,     5,      215,    "R/W",  0,      0,      6ull,   7ull},
55027         {"TMRD"                        ,        22,     3,      215,    "R/W",  0,      0,      2ull,   2ull},
55028         {"CASLAT"                      ,        25,     3,      215,    "R/W",  0,      0,      4ull,   4ull},
55029         {"TRRD"                        ,        28,     3,      215,    "R/W",  0,      0,      2ull,   2ull},
55030         {"COMP_BYPASS"                 ,        31,     1,      215,    "R/W",  0,      0,      0ull,   0ull},
55031         {"RESERVED_32_63"              ,        32,     32,     215,    "RAZ",  1,      1,      0,      0},
55032         {"OPSCNT_HI"                   ,        0,      32,     216,    "RO",   0,      0,      0ull,   0ull},
55033         {"RESERVED_32_63"              ,        32,     32,     216,    "RAZ",  1,      1,      0,      0},
55034         {"OPSCNT_LO"                   ,        0,      32,     217,    "RO",   0,      0,      0ull,   0ull},
55035         {"RESERVED_32_63"              ,        32,     32,     217,    "RAZ",  1,      1,      0,      0},
55036         {"EN2"                         ,        0,      1,      218,    "R/W",  0,      1,      0ull,   0},
55037         {"EN4"                         ,        1,      1,      218,    "R/W",  0,      1,      0ull,   0},
55038         {"EN6"                         ,        2,      1,      218,    "R/W",  0,      1,      0ull,   0},
55039         {"EN8"                         ,        3,      1,      218,    "R/W",  0,      1,      1ull,   0},
55040         {"EN12"                        ,        4,      1,      218,    "R/W",  0,      1,      0ull,   0},
55041         {"EN16"                        ,        5,      1,      218,    "R/W",  0,      1,      0ull,   0},
55042         {"RESERVED_6_7"                ,        6,      2,      218,    "RAZ",  0,      1,      0ull,   0},
55043         {"CLKR"                        ,        8,      6,      218,    "R/W",  0,      1,      0ull,   0},
55044         {"CLKF"                        ,        14,     12,     218,    "R/W",  0,      1,      31ull,  0},
55045         {"RESET_N"                     ,        26,     1,      218,    "R/W",  0,      0,      0ull,   1ull},
55046         {"DIV_RESET"                   ,        27,     1,      218,    "R/W",  0,      0,      1ull,   0ull},
55047         {"FASTEN_N"                    ,        28,     1,      218,    "R/W",  0,      0,      0ull,   0ull},
55048         {"RESERVED_29_63"              ,        29,     35,     218,    "RAZ",  0,      1,      0ull,   0},
55049         {"FBSLIP"                      ,        0,      1,      219,    "R/W1C",        0,      1,      0ull,   0},
55050         {"RFSLIP"                      ,        1,      1,      219,    "R/W1C",        0,      1,      0ull,   0},
55051         {"RESERVED_2_21"               ,        2,      20,     219,    "RAZ",  1,      1,      0,      0},
55052         {"DDR__PCTL"                   ,        22,     5,      219,    "RO",   1,      1,      0,      0},
55053         {"DDR__NCTL"                   ,        27,     5,      219,    "RO",   1,      1,      0,      0},
55054         {"RESERVED_32_63"              ,        32,     32,     219,    "RAZ",  1,      1,      0,      0},
55055         {"PCTL"                        ,        0,      5,      220,    "R/W",  0,      1,      0ull,   0},
55056         {"RESERVED_5_7"                ,        5,      3,      220,    "RAZ",  0,      1,      0ull,   0},
55057         {"NCTL"                        ,        8,      4,      220,    "R/W",  0,      1,      0ull,   0},
55058         {"RESERVED_12_15"              ,        12,     4,      220,    "RAZ",  0,      1,      0ull,   0},
55059         {"ENABLE"                      ,        16,     1,      220,    "R/W",  0,      1,      0ull,   0},
55060         {"RESERVED_17_63"              ,        17,     47,     220,    "RAZ",  0,      1,      0ull,   0},
55061         {"RODT_LO0"                    ,        0,      4,      221,    "R/W",  0,      0,      15ull,  15ull},
55062         {"RODT_LO1"                    ,        4,      4,      221,    "R/W",  0,      0,      15ull,  15ull},
55063         {"RODT_LO2"                    ,        8,      4,      221,    "R/W",  0,      0,      15ull,  15ull},
55064         {"RODT_LO3"                    ,        12,     4,      221,    "R/W",  0,      0,      15ull,  15ull},
55065         {"RODT_HI0"                    ,        16,     4,      221,    "R/W",  0,      0,      15ull,  15ull},
55066         {"RODT_HI1"                    ,        20,     4,      221,    "R/W",  0,      0,      15ull,  15ull},
55067         {"RODT_HI2"                    ,        24,     4,      221,    "R/W",  0,      0,      15ull,  15ull},
55068         {"RODT_HI3"                    ,        28,     4,      221,    "R/W",  0,      0,      15ull,  15ull},
55069         {"RESERVED_32_63"              ,        32,     32,     221,    "RAZ",  1,      1,      0,      0},
55070         {"WODT_LO0"                    ,        0,      4,      222,    "R/W",  0,      0,      15ull,  15ull},
55071         {"WODT_LO1"                    ,        4,      4,      222,    "R/W",  0,      0,      15ull,  15ull},
55072         {"WODT_LO2"                    ,        8,      4,      222,    "R/W",  0,      0,      15ull,  15ull},
55073         {"WODT_LO3"                    ,        12,     4,      222,    "R/W",  0,      0,      15ull,  15ull},
55074         {"WODT_HI0"                    ,        16,     4,      222,    "R/W",  0,      0,      15ull,  15ull},
55075         {"WODT_HI1"                    ,        20,     4,      222,    "R/W",  0,      0,      15ull,  15ull},
55076         {"WODT_HI2"                    ,        24,     4,      222,    "R/W",  0,      0,      15ull,  15ull},
55077         {"WODT_HI3"                    ,        28,     4,      222,    "R/W",  0,      0,      15ull,  15ull},
55078         {"RESERVED_32_63"              ,        32,     32,     222,    "RAZ",  1,      1,      0,      0},
55079         {"NCBI"                        ,        0,      1,      223,    "RO",   0,      0,      0ull,   0ull},
55080         {"LOC"                         ,        1,      1,      223,    "RO",   0,      0,      0ull,   0ull},
55081         {"NCBO_0"                      ,        2,      1,      223,    "RO",   0,      0,      0ull,   0ull},
55082         {"NCBO_1"                      ,        3,      1,      223,    "RO",   0,      0,      0ull,   0ull},
55083         {"PCM_0"                       ,        4,      1,      223,    "RO",   0,      0,      0ull,   0ull},
55084         {"PCM_1"                       ,        5,      1,      223,    "RO",   0,      0,      0ull,   0ull},
55085         {"RESERVED_6_63"               ,        6,      58,     223,    "RAZ",  1,      1,      0,      0},
55086         {"NCTL"                        ,        0,      5,      224,    "R/W",  0,      1,      31ull,  0},
55087         {"PCTL"                        ,        5,      5,      224,    "R/W",  0,      1,      31ull,  0},
55088         {"RESERVED_10_63"              ,        10,     54,     224,    "RAZ",  1,      1,      0,      0},
55089         {"ADR_ERR"                     ,        0,      1,      225,    "R/W1C",        0,      0,      0ull,   0ull},
55090         {"WAIT_ERR"                    ,        1,      1,      225,    "R/W1C",        0,      0,      0ull,   0ull},
55091         {"RESERVED_2_63"               ,        2,      62,     225,    "RAZ",  1,      1,      0,      0},
55092         {"ADR_INT"                     ,        0,      1,      226,    "R/W",  0,      1,      0ull,   0},
55093         {"WAIT_INT"                    ,        1,      1,      226,    "R/W",  0,      1,      0ull,   0},
55094         {"RESERVED_2_63"               ,        2,      62,     226,    "RAZ",  1,      1,      0,      0},
55095         {"RESERVED_0_2"                ,        0,      3,      227,    "RAZ",  1,      1,      0,      0},
55096         {"ADR"                         ,        3,      5,      227,    "R/W",  0,      1,      0ull,   0},
55097         {"RESERVED_8_63"               ,        8,      56,     227,    "RAZ",  1,      1,      0,      0},
55098         {"RESERVED_0_2"                ,        0,      3,      228,    "RAZ",  1,      1,      0,      0},
55099         {"BASE"                        ,        3,      25,     228,    "R/W",  0,      1,      0ull,   0},
55100         {"RESERVED_28_30"              ,        28,     3,      228,    "RAZ",  1,      1,      0,      0},
55101         {"EN"                          ,        31,     1,      228,    "R/W",  0,      1,      0ull,   0},
55102         {"RESERVED_32_63"              ,        32,     32,     228,    "RAZ",  1,      1,      0,      0},
55103         {"DATA"                        ,        0,      64,     229,    "R/W",  1,      1,      0,      0},
55104         {"BASE"                        ,        0,      16,     230,    "R/W",  0,      1,      0ull,   0},
55105         {"SIZE"                        ,        16,     12,     230,    "R/W",  0,      1,      0ull,   0},
55106         {"WIDTH"                       ,        28,     1,      230,    "R/W",  0,      1,      0ull,   0},
55107         {"ALE"                         ,        29,     1,      230,    "R/W",  0,      1,      0ull,   0},
55108         {"ORBIT"                       ,        30,     1,      230,    "R/W",  0,      1,      0ull,   0},
55109         {"EN"                          ,        31,     1,      230,    "R/W",  0,      1,      0ull,   0},
55110         {"OE_EXT"                      ,        32,     2,      230,    "R/W",  0,      1,      0ull,   0},
55111         {"WE_EXT"                      ,        34,     2,      230,    "R/W",  0,      1,      0ull,   0},
55112         {"SAM"                         ,        36,     1,      230,    "R/W",  0,      1,      0ull,   0},
55113         {"RD_DLY"                      ,        37,     3,      230,    "R/W",  0,      1,      0ull,   0},
55114         {"TIM_MULT"                    ,        40,     2,      230,    "R/W",  0,      1,      0ull,   0},
55115         {"RESERVED_42_63"              ,        42,     22,     230,    "RAZ",  1,      1,      0,      0},
55116         {"ADR"                         ,        0,      6,      231,    "R/W",  0,      1,      63ull,  0},
55117         {"CE"                          ,        6,      6,      231,    "R/W",  0,      1,      63ull,  0},
55118         {"OE"                          ,        12,     6,      231,    "R/W",  0,      1,      63ull,  0},
55119         {"WE"                          ,        18,     6,      231,    "R/W",  0,      1,      63ull,  0},
55120         {"RD_HLD"                      ,        24,     6,      231,    "R/W",  0,      1,      63ull,  0},
55121         {"WR_HLD"                      ,        30,     6,      231,    "R/W",  0,      1,      63ull,  0},
55122         {"PAUSE"                       ,        36,     6,      231,    "R/W",  0,      1,      63ull,  0},
55123         {"WAIT"                        ,        42,     6,      231,    "R/W",  0,      1,      63ull,  0},
55124         {"PAGE"                        ,        48,     6,      231,    "R/W",  0,      1,      63ull,  0},
55125         {"ALE"                         ,        54,     6,      231,    "R/W",  0,      1,      63ull,  0},
55126         {"PAGES"                       ,        60,     2,      231,    "R/W",  0,      1,      0ull,   0},
55127         {"WAITM"                       ,        62,     1,      231,    "R/W",  0,      1,      0ull,   0},
55128         {"PAGEM"                       ,        63,     1,      231,    "R/W",  0,      1,      0ull,   0},
55129         {"FIF_THR"                     ,        0,      6,      232,    "R/W",  0,      0,      26ull,  26ull},
55130         {"RESERVED_6_7"                ,        6,      2,      232,    "RAZ",  1,      1,      0,      0},
55131         {"FIF_CNT"                     ,        8,      6,      232,    "RO",   0,      1,      0ull,   0},
55132         {"RESERVED_14_63"              ,        14,     50,     232,    "RAZ",  1,      1,      0,      0},
55133         {"DAT"                         ,        0,      64,     233,    "R/W",  1,      1,      0,      0},
55134         {"MAN_INFO"                    ,        0,      32,     234,    "RO",   1,      1,      0,      0},
55135         {"RESERVED_32_63"              ,        32,     32,     234,    "RAZ",  1,      1,      0,      0},
55136         {"MAN_INFO"                    ,        0,      32,     235,    "RO",   1,      1,      0,      0},
55137         {"RESERVED_32_63"              ,        32,     32,     235,    "RAZ",  1,      1,      0,      0},
55138         {"PP_DIS"                      ,        0,      2,      236,    "RO",   1,      1,      0,      0},
55139         {"RESERVED_2_15"               ,        2,      14,     236,    "RAZ",  1,      1,      0,      0},
55140         {"CHIP_ID"                     ,        16,     8,      236,    "RO",   1,      1,      0,      0},
55141         {"BIST_DIS"                    ,        24,     1,      236,    "RO",   1,      1,      0,      0},
55142         {"RST_SHT"                     ,        25,     1,      236,    "RO",   1,      1,      0,      0},
55143         {"NOCRYPTO"                    ,        26,     1,      236,    "RO",   1,      1,      0,      0},
55144         {"NOMUL"                       ,        27,     1,      236,    "RO",   1,      1,      0,      0},
55145         {"NODFA_CP2"                   ,        28,     1,      236,    "RO",   0,      0,      1ull,   1ull},
55146         {"NOKASU"                      ,        29,     1,      236,    "RO",   1,      1,      0,      0},
55147         {"RESERVED_30_31"              ,        30,     2,      236,    "RAZ",  1,      1,      0,      0},
55148         {"RAID_EN"                     ,        32,     1,      236,    "RO",   0,      0,      0ull,   0ull},
55149         {"FUS318"                      ,        33,     1,      236,    "RO",   1,      1,      0,      0},
55150         {"RESERVED_34_63"              ,        34,     30,     236,    "RAZ",  1,      1,      0,      0},
55151         {"ICACHE"                      ,        0,      24,     237,    "RO",   1,      1,      0,      0},
55152         {"NODFA_DTE"                   ,        24,     1,      237,    "RO",   0,      0,      1ull,   1ull},
55153         {"NOZIP"                       ,        25,     1,      237,    "RO",   0,      0,      1ull,   1ull},
55154         {"EFUS_IGN"                    ,        26,     1,      237,    "RO",   1,      1,      0,      0},
55155         {"EFUS_LCK"                    ,        27,     1,      237,    "RO",   1,      1,      0,      0},
55156         {"BAR2_EN"                     ,        28,     1,      237,    "RO",   1,      1,      0,      0},
55157         {"ZIP_CRIP"                    ,        29,     2,      237,    "RO",   1,      1,      0,      0},
55158         {"RESERVED_31_63"              ,        31,     33,     237,    "RAZ",  1,      1,      0,      0},
55159         {"EMA"                         ,        0,      3,      238,    "R/W",  1,      0,      0,      0ull},
55160         {"RESERVED_3_3"                ,        3,      1,      238,    "RAZ",  1,      1,      0,      0},
55161         {"EFF_EMA"                     ,        4,      3,      238,    "RO",   1,      0,      0,      0ull},
55162         {"RESERVED_7_63"               ,        7,      57,     238,    "RAZ",  1,      1,      0,      0},
55163         {"PDF"                         ,        0,      64,     239,    "RO",   1,      1,      0,      0},
55164         {"FBSLIP"                      ,        0,      1,      240,    "R/W1C",        0,      1,      0ull,   0},
55165         {"RFSLIP"                      ,        1,      1,      240,    "R/W1C",        0,      1,      0ull,   0},
55166         {"RESERVED_2_63"               ,        2,      62,     240,    "RAZ",  1,      1,      0,      0},
55167         {"PROG"                        ,        0,      1,      241,    "R/W",  1,      1,      0,      0},
55168         {"RESERVED_1_63"               ,        1,      63,     241,    "RAZ",  1,      1,      0,      0},
55169         {"SETUP"                       ,        0,      8,      242,    "R/W",  0,      1,      3ull,   0},
55170         {"SCLK_HI"                     ,        8,      12,     242,    "R/W",  0,      1,      100ull, 0},
55171         {"SCLK_LO"                     ,        20,     4,      242,    "R/W",  0,      1,      2ull,   0},
55172         {"OUT"                         ,        24,     8,      242,    "R/W",  0,      1,      3ull,   0},
55173         {"PROG_PIN"                    ,        32,     1,      242,    "RO",   0,      0,      0ull,   0ull},
55174         {"RESERVED_33_63"              ,        33,     31,     242,    "RAZ",  1,      1,      0,      0},
55175         {"ADDR"                        ,        0,      7,      243,    "R/W",  0,      0,      0ull,   0ull},
55176         {"RESERVED_7_7"                ,        7,      1,      243,    "RAZ",  1,      1,      0,      0},
55177         {"EFUSE"                       ,        8,      1,      243,    "R/W",  0,      0,      0ull,   0ull},
55178         {"RESERVED_9_11"               ,        9,      3,      243,    "RAZ",  1,      1,      0,      0},
55179         {"PEND"                        ,        12,     1,      243,    "R/W",  0,      0,      0ull,   0ull},
55180         {"RESERVED_13_15"              ,        13,     3,      243,    "RAZ",  1,      1,      0,      0},
55181         {"DAT"                         ,        16,     8,      243,    "RO",   1,      1,      0,      0},
55182         {"RESERVED_24_63"              ,        24,     40,     243,    "RAZ",  1,      1,      0,      0},
55183         {"REPAIR0"                     ,        0,      14,     244,    "RO",   0,      0,      0ull,   0ull},
55184         {"REPAIR1"                     ,        14,     14,     244,    "RO",   0,      0,      0ull,   0ull},
55185         {"REPAIR2"                     ,        28,     14,     244,    "RO",   0,      0,      0ull,   0ull},
55186         {"RESERVED_42_63"              ,        42,     22,     244,    "RAZ",  1,      1,      0,      0},
55187         {"TOO_MANY"                    ,        0,      1,      245,    "RO",   0,      0,      0ull,   0ull},
55188         {"RESERVED_1_63"               ,        1,      63,     245,    "RAZ",  1,      1,      0,      0},
55189         {"ADDR"                        ,        0,      2,      246,    "R/W",  1,      1,      0,      0},
55190         {"RESERVED_2_63"               ,        2,      62,     246,    "RAZ",  1,      1,      0,      0},
55191         {"ST_INT"                      ,        0,      1,      247,    "R/W1C",        0,      1,      0ull,   0},
55192         {"TS_INT"                      ,        1,      1,      247,    "R/W1C",        0,      1,      0ull,   0},
55193         {"CORE_INT"                    ,        2,      1,      247,    "RO",   0,      1,      0ull,   0},
55194         {"RESERVED_3_3"                ,        3,      1,      247,    "RAZ",  1,      1,      0,      0},
55195         {"ST_EN"                       ,        4,      1,      247,    "R/W",  0,      1,      0ull,   0},
55196         {"TS_EN"                       ,        5,      1,      247,    "R/W",  0,      1,      0ull,   0},
55197         {"CORE_EN"                     ,        6,      1,      247,    "R/W",  0,      1,      0ull,   0},
55198         {"RESERVED_7_7"                ,        7,      1,      247,    "RAZ",  1,      1,      0,      0},
55199         {"SDA_OVR"                     ,        8,      1,      247,    "R/W",  0,      1,      0ull,   0},
55200         {"SCL_OVR"                     ,        9,      1,      247,    "R/W",  0,      1,      0ull,   0},
55201         {"SDA"                         ,        10,     1,      247,    "RO",   1,      1,      0,      0},
55202         {"SCL"                         ,        11,     1,      247,    "RO",   1,      1,      0,      0},
55203         {"RESERVED_12_63"              ,        12,     52,     247,    "RAZ",  1,      1,      0,      0},
55204         {"D"                           ,        0,      32,     248,    "R/W",  0,      1,      0ull,   0},
55205         {"EOP_IA"                      ,        32,     3,      248,    "R/W",  0,      1,      0ull,   0},
55206         {"IA"                          ,        35,     5,      248,    "R/W",  0,      1,      0ull,   0},
55207         {"A"                           ,        40,     10,     248,    "R/W",  0,      1,      0ull,   0},
55208         {"SCR"                         ,        50,     2,      248,    "R/W",  0,      1,      0ull,   0},
55209         {"SIZE"                        ,        52,     3,      248,    "R/W",  0,      1,      0ull,   0},
55210         {"SOVR"                        ,        55,     1,      248,    "R/W",  0,      1,      0ull,   0},
55211         {"R"                           ,        56,     1,      248,    "R/W",  0,      1,      0ull,   0},
55212         {"OP"                          ,        57,     4,      248,    "R/W",  0,      1,      0ull,   0},
55213         {"EIA"                         ,        61,     1,      248,    "R/W",  0,      1,      0ull,   0},
55214         {"SLONLY"                      ,        62,     1,      248,    "R/W",  0,      1,      0ull,   0},
55215         {"V"                           ,        63,     1,      248,    "RC/W", 0,      1,      0ull,   0},
55216         {"D"                           ,        0,      32,     249,    "R/W",  0,      1,      0ull,   0},
55217         {"IA"                          ,        32,     8,      249,    "R/W",  0,      1,      0ull,   0},
55218         {"RESERVED_40_63"              ,        40,     24,     249,    "RAZ",  1,      1,      0,      0},
55219         {"D"                           ,        0,      32,     250,    "R/W",  1,      1,      0,      0},
55220         {"RESERVED_32_61"              ,        32,     30,     250,    "RAZ",  1,      1,      0,      0},
55221         {"V"                           ,        62,     2,      250,    "RC/W", 0,      1,      0ull,   0},
55222         {"DLH"                         ,        0,      8,      251,    "R/W",  0,      1,      0ull,   0},
55223         {"RESERVED_8_63"               ,        8,      56,     251,    "RAZ",  1,      1,      0,      0},
55224         {"DLL"                         ,        0,      8,      252,    "R/W",  0,      1,      0ull,   0},
55225         {"RESERVED_8_63"               ,        8,      56,     252,    "RAZ",  1,      1,      0,      0},
55226         {"FAR"                         ,        0,      1,      253,    "R/W",  0,      1,      0ull,   0},
55227         {"RESERVED_1_63"               ,        1,      63,     253,    "RAZ",  1,      1,      0,      0},
55228         {"EN"                          ,        0,      1,      254,    "WO",   0,      1,      0ull,   0},
55229         {"RXFR"                        ,        1,      1,      254,    "WO",   0,      1,      0ull,   0},
55230         {"TXFR"                        ,        2,      1,      254,    "WO",   0,      1,      0ull,   0},
55231         {"RESERVED_3_3"                ,        3,      1,      254,    "RAZ",  0,      1,      0ull,   0},
55232         {"TXTRIG"                      ,        4,      2,      254,    "WO",   0,      1,      0ull,   0},
55233         {"RXTRIG"                      ,        6,      2,      254,    "WO",   0,      1,      0ull,   0},
55234         {"RESERVED_8_63"               ,        8,      56,     254,    "RAZ",  1,      1,      0,      0},
55235         {"HTX"                         ,        0,      1,      255,    "R/W",  0,      1,      0ull,   0},
55236         {"RESERVED_1_63"               ,        1,      63,     255,    "RAZ",  1,      1,      0,      0},
55237         {"ERBFI"                       ,        0,      1,      256,    "R/W",  0,      1,      0ull,   0},
55238         {"ETBEI"                       ,        1,      1,      256,    "R/W",  0,      1,      0ull,   0},
55239         {"ELSI"                        ,        2,      1,      256,    "R/W",  0,      1,      0ull,   0},
55240         {"EDSSI"                       ,        3,      1,      256,    "R/W",  0,      1,      0ull,   0},
55241         {"RESERVED_4_6"                ,        4,      3,      256,    "RAZ",  0,      1,      0ull,   0},
55242         {"PTIME"                       ,        7,      1,      256,    "R/W",  0,      1,      0ull,   0},
55243         {"RESERVED_8_63"               ,        8,      56,     256,    "RAZ",  1,      1,      0,      0},
55244         {"IID"                         ,        0,      4,      257,    "RO",   0,      1,      1ull,   0},
55245         {"RESERVED_4_5"                ,        4,      2,      257,    "RAZ",  0,      1,      0ull,   0},
55246         {"FEN"                         ,        6,      2,      257,    "RO",   0,      1,      0ull,   0},
55247         {"RESERVED_8_63"               ,        8,      56,     257,    "RAZ",  1,      1,      0,      0},
55248         {"CLS"                         ,        0,      2,      258,    "R/W",  0,      1,      0ull,   0},
55249         {"STOP"                        ,        2,      1,      258,    "R/W",  0,      1,      0ull,   0},
55250         {"PEN"                         ,        3,      1,      258,    "R/W",  0,      1,      0ull,   0},
55251         {"EPS"                         ,        4,      1,      258,    "R/W",  0,      1,      0ull,   0},
55252         {"RESERVED_5_5"                ,        5,      1,      258,    "RAZ",  0,      1,      0ull,   0},
55253         {"BRK"                         ,        6,      1,      258,    "R/W",  0,      1,      0ull,   0},
55254         {"DLAB"                        ,        7,      1,      258,    "R/W",  0,      1,      0ull,   0},
55255         {"RESERVED_8_63"               ,        8,      56,     258,    "RAZ",  1,      1,      0,      0},
55256         {"DR"                          ,        0,      1,      259,    "RO",   0,      1,      0ull,   0},
55257         {"OE"                          ,        1,      1,      259,    "RC",   0,      1,      0ull,   0},
55258         {"PE"                          ,        2,      1,      259,    "RC",   0,      1,      0ull,   0},
55259         {"FE"                          ,        3,      1,      259,    "RC",   0,      1,      0ull,   0},
55260         {"BI"                          ,        4,      1,      259,    "RC",   0,      1,      0ull,   0},
55261         {"THRE"                        ,        5,      1,      259,    "RO",   0,      1,      1ull,   0},
55262         {"TEMT"                        ,        6,      1,      259,    "RO",   0,      1,      1ull,   0},
55263         {"FERR"                        ,        7,      1,      259,    "RC",   0,      1,      0ull,   0},
55264         {"RESERVED_8_63"               ,        8,      56,     259,    "RAZ",  1,      1,      0,      0},
55265         {"DTR"                         ,        0,      1,      260,    "R/W",  0,      1,      0ull,   0},
55266         {"RTS"                         ,        1,      1,      260,    "R/W",  0,      1,      0ull,   0},
55267         {"OUT1"                        ,        2,      1,      260,    "R/W",  0,      1,      0ull,   0},
55268         {"OUT2"                        ,        3,      1,      260,    "R/W",  0,      1,      0ull,   0},
55269         {"LOOP"                        ,        4,      1,      260,    "R/W",  0,      1,      0ull,   0},
55270         {"AFCE"                        ,        5,      1,      260,    "R/W",  0,      1,      0ull,   0},
55271         {"RESERVED_6_63"               ,        6,      58,     260,    "RAZ",  0,      1,      0ull,   0},
55272         {"DCTS"                        ,        0,      1,      261,    "RC",   0,      1,      0ull,   0},
55273         {"DDSR"                        ,        1,      1,      261,    "RC",   0,      1,      0ull,   0},
55274         {"TERI"                        ,        2,      1,      261,    "RC",   0,      1,      0ull,   0},
55275         {"DDCD"                        ,        3,      1,      261,    "RC",   0,      1,      0ull,   0},
55276         {"CTS"                         ,        4,      1,      261,    "RO",   1,      1,      0,      0},
55277         {"DSR"                         ,        5,      1,      261,    "RO",   0,      1,      0ull,   0},
55278         {"RI"                          ,        6,      1,      261,    "RO",   0,      1,      0ull,   0},
55279         {"DCD"                         ,        7,      1,      261,    "RO",   0,      1,      0ull,   0},
55280         {"RESERVED_8_63"               ,        8,      56,     261,    "RAZ",  1,      1,      0,      0},
55281         {"RBR"                         ,        0,      8,      262,    "RO",   0,      1,      0ull,   0},
55282         {"RESERVED_8_63"               ,        8,      56,     262,    "RAZ",  1,      1,      0,      0},
55283         {"RFL"                         ,        0,      7,      263,    "RO",   0,      1,      0ull,   0},
55284         {"RESERVED_7_63"               ,        7,      57,     263,    "RAZ",  1,      1,      0,      0},
55285         {"RFWD"                        ,        0,      8,      264,    "WO",   0,      1,      0ull,   0},
55286         {"RFPE"                        ,        8,      1,      264,    "WO",   0,      1,      0ull,   0},
55287         {"RFFE"                        ,        9,      1,      264,    "WO",   0,      1,      0ull,   0},
55288         {"RESERVED_10_63"              ,        10,     54,     264,    "RAZ",  1,      1,      0,      0},
55289         {"SBCR"                        ,        0,      1,      265,    "R/W",  0,      1,      0ull,   0},
55290         {"RESERVED_1_63"               ,        1,      63,     265,    "RAZ",  1,      1,      0,      0},
55291         {"SCR"                         ,        0,      8,      266,    "R/W",  0,      1,      0ull,   0},
55292         {"RESERVED_8_63"               ,        8,      56,     266,    "RAZ",  1,      1,      0,      0},
55293         {"SFE"                         ,        0,      1,      267,    "R/W",  0,      1,      0ull,   0},
55294         {"RESERVED_1_63"               ,        1,      63,     267,    "RAZ",  1,      1,      0,      0},
55295         {"USR"                         ,        0,      1,      268,    "WO",   0,      1,      0ull,   0},
55296         {"SRFR"                        ,        1,      1,      268,    "WO",   0,      1,      0ull,   0},
55297         {"STFR"                        ,        2,      1,      268,    "WO",   0,      1,      0ull,   0},
55298         {"RESERVED_3_63"               ,        3,      61,     268,    "RAZ",  1,      1,      0,      0},
55299         {"SRT"                         ,        0,      2,      269,    "R/W",  0,      1,      0ull,   0},
55300         {"RESERVED_2_63"               ,        2,      62,     269,    "RAZ",  1,      1,      0,      0},
55301         {"SRTS"                        ,        0,      1,      270,    "R/W",  0,      1,      0ull,   0},
55302         {"RESERVED_1_63"               ,        1,      63,     270,    "RAZ",  1,      1,      0,      0},
55303         {"STT"                         ,        0,      2,      271,    "R/W",  0,      1,      0ull,   0},
55304         {"RESERVED_2_63"               ,        2,      62,     271,    "RAZ",  1,      1,      0,      0},
55305         {"TFL"                         ,        0,      7,      272,    "RO",   0,      1,      0ull,   0},
55306         {"RESERVED_7_63"               ,        7,      57,     272,    "RAZ",  1,      1,      0,      0},
55307         {"TFR"                         ,        0,      8,      273,    "RO",   0,      1,      0ull,   0},
55308         {"RESERVED_8_63"               ,        8,      56,     273,    "RAZ",  1,      1,      0,      0},
55309         {"THR"                         ,        0,      8,      274,    "WO",   0,      1,      0ull,   0},
55310         {"RESERVED_8_63"               ,        8,      56,     274,    "RAZ",  1,      1,      0,      0},
55311         {"BUSY"                        ,        0,      1,      275,    "RO",   0,      1,      0ull,   0},
55312         {"TFNF"                        ,        1,      1,      275,    "RO",   0,      1,      1ull,   0},
55313         {"TFE"                         ,        2,      1,      275,    "RO",   0,      1,      1ull,   0},
55314         {"RFNE"                        ,        3,      1,      275,    "RO",   0,      1,      0ull,   0},
55315         {"RFF"                         ,        4,      1,      275,    "RO",   0,      1,      0ull,   0},
55316         {"RESERVED_5_63"               ,        5,      59,     275,    "RAZ",  1,      1,      0,      0},
55317         {"ENABLE"                      ,        0,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
55318         {"IDLELO"                      ,        1,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
55319         {"CLK_CONT"                    ,        2,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
55320         {"WIREOR"                      ,        3,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
55321         {"LSBFIRST"                    ,        4,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
55322         {"INT_ENA"                     ,        5,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
55323         {"CSENA"                       ,        6,      1,      276,    "R/W",  0,      0,      0ull,   1ull},
55324         {"CSHI"                        ,        7,      1,      276,    "R/W",  0,      0,      0ull,   0ull},
55325         {"IDLECLKS"                    ,        8,      2,      276,    "R/W",  0,      0,      0ull,   0ull},
55326         {"TRITX"                       ,        10,     1,      276,    "R/W",  0,      0,      0ull,   0ull},
55327         {"CSLATE"                      ,        11,     1,      276,    "R/W",  0,      0,      0ull,   0ull},
55328         {"RESERVED_12_15"              ,        12,     4,      276,    "RAZ",  1,      1,      0,      0},
55329         {"CLKDIV"                      ,        16,     13,     276,    "R/W",  0,      0,      0ull,   0ull},
55330         {"RESERVED_29_63"              ,        29,     35,     276,    "RAZ",  1,      1,      0,      0},
55331         {"DATA"                        ,        0,      8,      277,    "R/W",  1,      1,      0,      0},
55332         {"RESERVED_8_63"               ,        8,      56,     277,    "RAZ",  1,      1,      0,      0},
55333         {"BUSY"                        ,        0,      1,      278,    "RO",   0,      0,      0ull,   0ull},
55334         {"RESERVED_1_7"                ,        1,      7,      278,    "RAZ",  1,      1,      0,      0},
55335         {"RXNUM"                       ,        8,      5,      278,    "RO",   0,      0,      0ull,   0ull},
55336         {"RESERVED_13_63"              ,        13,     51,     278,    "RAZ",  1,      1,      0,      0},
55337         {"TOTNUM"                      ,        0,      5,      279,    "WO",   1,      0,      0,      2ull},
55338         {"RESERVED_5_7"                ,        5,      3,      279,    "RAZ",  1,      1,      0,      0},
55339         {"TXNUM"                       ,        8,      5,      279,    "WO",   1,      0,      0,      1ull},
55340         {"RESERVED_13_15"              ,        13,     3,      279,    "RAZ",  1,      1,      0,      0},
55341         {"LEAVECS"                     ,        16,     1,      279,    "WO",   1,      0,      0,      0ull},
55342         {"RESERVED_17_63"              ,        17,     47,     279,    "RAZ",  1,      1,      0,      0},
55343         {"RESERVED_0_2"                ,        0,      3,      280,    "RAZ",  1,      1,      0,      0},
55344         {"BADDR"                       ,        3,      61,     280,    "R/W",  0,      1,      0ull,   0},
55345         {"RESERVED_0_2"                ,        0,      3,      281,    "RAZ",  1,      1,      0,      0},
55346         {"BADDR"                       ,        3,      61,     281,    "R/W",  0,      1,      0ull,   0},
55347         {"DPI_BS"                      ,        0,      1,      282,    "RO",   0,      0,      0ull,   0ull},
55348         {"PDF_BS"                      ,        1,      1,      282,    "RO",   0,      0,      0ull,   0ull},
55349         {"DOB_BS"                      ,        2,      1,      282,    "RO",   0,      0,      0ull,   0ull},
55350         {"NUS_BS"                      ,        3,      1,      282,    "RO",   0,      0,      0ull,   0ull},
55351         {"POS_BS"                      ,        4,      1,      282,    "RO",   0,      0,      0ull,   0ull},
55352         {"RESERVED_5_6"                ,        5,      2,      282,    "RAZ",  0,      0,      0ull,   0ull},
55353         {"POF1_BS"                     ,        7,      1,      282,    "RO",   0,      0,      0ull,   0ull},
55354         {"POF0_BS"                     ,        8,      1,      282,    "RO",   0,      0,      0ull,   0ull},
55355         {"PIG_BS"                      ,        9,      1,      282,    "RO",   0,      0,      0ull,   0ull},
55356         {"PGF_BS"                      ,        10,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55357         {"RDNL_BS"                     ,        11,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55358         {"PCAD_BS"                     ,        12,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55359         {"PCAC_BS"                     ,        13,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55360         {"RDN_BS"                      ,        14,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55361         {"PCN_BS"                      ,        15,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55362         {"PCNC_BS"                     ,        16,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55363         {"RDP_BS"                      ,        17,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55364         {"DIF_BS"                      ,        18,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55365         {"CSR_BS"                      ,        19,     1,      282,    "RO",   0,      0,      0ull,   0ull},
55366         {"RESERVED_20_63"              ,        20,     44,     282,    "RAZ",  1,      1,      0,      0},
55367         {"BSIZE"                       ,        0,      16,     283,    "R/W",  0,      1,      1024ull,        0},
55368         {"ISIZE"                       ,        16,     7,      283,    "R/W",  0,      1,      0ull,   0},
55369         {"RESERVED_23_63"              ,        23,     41,     283,    "RAZ",  1,      1,      0,      0},
55370         {"NCTL"                        ,        0,      5,      284,    "R/W",  0,      1,      16ull,  0},
55371         {"PCTL"                        ,        5,      5,      284,    "R/W",  0,      1,      16ull,  0},
55372         {"RESERVED_10_63"              ,        10,     54,     284,    "RAZ",  1,      1,      0,      0},
55373         {"TIMER"                       ,        0,      10,     285,    "R/W",  0,      0,      0ull,   50ull},
55374         {"RESERVED_10_31"              ,        10,     22,     285,    "RAZ",  0,      0,      0ull,   0ull},
55375         {"MAX_WORD"                    ,        32,     5,      285,    "R/W",  0,      0,      2ull,   0ull},
55376         {"RESERVED_37_39"              ,        37,     3,      285,    "RAZ",  0,      0,      0ull,   0ull},
55377         {"WAIT_COM"                    ,        40,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
55378         {"PCI_WDIS"                    ,        41,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
55379         {"INS0_64B"                    ,        42,     1,      285,    "R/W",  0,      1,      0ull,   0},
55380         {"INS1_64B"                    ,        43,     1,      285,    "R/W",  0,      1,      0ull,   0},
55381         {"RESERVED_44_45"              ,        44,     2,      285,    "RAZ",  0,      0,      0ull,   0ull},
55382         {"INS0_ENB"                    ,        46,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
55383         {"INS1_ENB"                    ,        47,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
55384         {"RESERVED_48_49"              ,        48,     2,      285,    "RAZ",  0,      0,      0ull,   0ull},
55385         {"OUT0_ENB"                    ,        50,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
55386         {"OUT1_ENB"                    ,        51,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
55387         {"RESERVED_52_53"              ,        52,     2,      285,    "RAZ",  0,      0,      0ull,   0ull},
55388         {"DIS_PNIW"                    ,        54,     1,      285,    "R/W",  0,      0,      0ull,   1ull},
55389         {"CHIP_REV"                    ,        55,     8,      285,    "RO",   1,      1,      0,      0},
55390         {"RESERVED_63_63"              ,        63,     1,      285,    "RAZ",  1,      1,      0,      0},
55391         {"DBG_SEL"                     ,        0,      16,     286,    "R/W",  0,      1,      0ull,   0},
55392         {"RESERVED_16_63"              ,        16,     48,     286,    "RAZ",  1,      1,      0,      0},
55393         {"CSIZE"                       ,        0,      14,     287,    "R/W",  0,      1,      0ull,   0},
55394         {"LP_ENB"                      ,        14,     1,      287,    "R/W",  0,      0,      0ull,   1ull},
55395         {"HP_ENB"                      ,        15,     1,      287,    "R/W",  0,      0,      0ull,   1ull},
55396         {"O_MODE"                      ,        16,     1,      287,    "R/W",  0,      0,      0ull,   1ull},
55397         {"O_ES"                        ,        17,     2,      287,    "R/W",  0,      1,      0ull,   0},
55398         {"O_NS"                        ,        19,     1,      287,    "R/W",  0,      1,      0ull,   0},
55399         {"O_RO"                        ,        20,     1,      287,    "R/W",  0,      1,      0ull,   0},
55400         {"O_ADD1"                      ,        21,     1,      287,    "R/W",  0,      0,      0ull,   1ull},
55401         {"FPA_QUE"                     ,        22,     3,      287,    "R/W",  0,      1,      0ull,   0},
55402         {"DWB_ICHK"                    ,        25,     9,      287,    "R/W",  0,      1,      0ull,   0},
55403         {"DWB_DENB"                    ,        34,     1,      287,    "R/W",  0,      0,      0ull,   1ull},
55404         {"B0_LEND"                     ,        35,     1,      287,    "R/W",  0,      0,      0ull,   0ull},
55405         {"RESERVED_36_63"              ,        36,     28,     287,    "RAZ",  1,      1,      0,      0},
55406         {"DBELL"                       ,        0,      32,     288,    "RO",   0,      0,      0ull,   0ull},
55407         {"FCNT"                        ,        32,     7,      288,    "RO",   0,      0,      0ull,   0ull},
55408         {"RESERVED_39_63"              ,        39,     25,     288,    "RAZ",  1,      1,      0,      0},
55409         {"ADDR"                        ,        0,      36,     289,    "RO",   0,      1,      0ull,   0},
55410         {"STATE"                       ,        36,     4,      289,    "RO",   0,      0,      0ull,   0ull},
55411         {"RESERVED_40_63"              ,        40,     24,     289,    "RAZ",  1,      1,      0,      0},
55412         {"DBELL"                       ,        0,      32,     290,    "RO",   0,      0,      0ull,   0ull},
55413         {"FCNT"                        ,        32,     7,      290,    "RO",   0,      0,      0ull,   0ull},
55414         {"RESERVED_39_63"              ,        39,     25,     290,    "RAZ",  1,      1,      0,      0},
55415         {"ADDR"                        ,        0,      36,     291,    "RO",   0,      1,      0ull,   0},
55416         {"STATE"                       ,        36,     4,      291,    "RO",   0,      0,      0ull,   0ull},
55417         {"RESERVED_40_63"              ,        40,     24,     291,    "RAZ",  1,      1,      0,      0},
55418         {"DBELL"                       ,        0,      16,     292,    "R/W",  0,      1,      0ull,   0},
55419         {"RESERVED_16_63"              ,        16,     48,     292,    "RAZ",  1,      1,      0,      0},
55420         {"SADDR"                       ,        0,      36,     293,    "R/W",  0,      1,      0ull,   0},
55421         {"RESERVED_36_63"              ,        36,     28,     293,    "RAZ",  1,      1,      0,      0},
55422         {"ROR"                         ,        0,      1,      294,    "R/W",  0,      1,      0ull,   0},
55423         {"ESR"                         ,        1,      2,      294,    "R/W",  0,      1,      0ull,   0},
55424         {"NSR"                         ,        3,      1,      294,    "R/W",  0,      1,      0ull,   0},
55425         {"USE_CSR"                     ,        4,      1,      294,    "R/W",  0,      0,      0ull,   1ull},
55426         {"D_ROR"                       ,        5,      1,      294,    "R/W",  0,      1,      0ull,   0},
55427         {"D_ESR"                       ,        6,      2,      294,    "R/W",  0,      1,      0ull,   0},
55428         {"D_NSR"                       ,        8,      1,      294,    "R/W",  0,      1,      0ull,   0},
55429         {"PBP_DHI"                     ,        9,      13,     294,    "R/W",  0,      1,      0ull,   0},
55430         {"PKT_RR"                      ,        22,     1,      294,    "R/W",  0,      0,      0ull,   0ull},
55431         {"RESERVED_23_63"              ,        23,     41,     294,    "RAZ",  1,      1,      0,      0},
55432         {"RML_RTO"                     ,        0,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
55433         {"RML_WTO"                     ,        1,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
55434         {"PCI_RSL"                     ,        2,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
55435         {"PO0_2SML"                    ,        3,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
55436         {"PO1_2SML"                    ,        4,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
55437         {"RESERVED_5_6"                ,        5,      2,      295,    "RAZ",  0,      0,      0ull,   1ull},
55438         {"I0_RTOUT"                    ,        7,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
55439         {"I1_RTOUT"                    ,        8,      1,      295,    "R/W",  0,      0,      0ull,   1ull},
55440         {"RESERVED_9_10"               ,        9,      2,      295,    "RAZ",  0,      0,      0ull,   1ull},
55441         {"I0_OVERF"                    ,        11,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55442         {"I1_OVERF"                    ,        12,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55443         {"RESERVED_13_14"              ,        13,     2,      295,    "RAZ",  0,      0,      0ull,   1ull},
55444         {"P0_RTOUT"                    ,        15,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55445         {"P1_RTOUT"                    ,        16,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55446         {"RESERVED_17_18"              ,        17,     2,      295,    "RAZ",  0,      0,      0ull,   1ull},
55447         {"P0_PERR"                     ,        19,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55448         {"P1_PERR"                     ,        20,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55449         {"RESERVED_21_22"              ,        21,     2,      295,    "RAZ",  0,      0,      0ull,   1ull},
55450         {"G0_RTOUT"                    ,        23,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55451         {"G1_RTOUT"                    ,        24,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55452         {"RESERVED_25_26"              ,        25,     2,      295,    "RAZ",  0,      0,      0ull,   1ull},
55453         {"P0_PPERR"                    ,        27,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55454         {"P1_PPERR"                    ,        28,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55455         {"RESERVED_29_30"              ,        29,     2,      295,    "RAZ",  0,      0,      0ull,   1ull},
55456         {"P0_PTOUT"                    ,        31,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55457         {"P1_PTOUT"                    ,        32,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55458         {"RESERVED_33_34"              ,        33,     2,      295,    "RAZ",  0,      0,      0ull,   1ull},
55459         {"I0_PPERR"                    ,        35,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55460         {"I1_PPERR"                    ,        36,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55461         {"RESERVED_37_38"              ,        37,     2,      295,    "RAZ",  0,      0,      0ull,   1ull},
55462         {"WIN_RTO"                     ,        39,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55463         {"P_DPERR"                     ,        40,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55464         {"IOBDMA"                      ,        41,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55465         {"FCR_S_E"                     ,        42,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55466         {"FCR_A_F"                     ,        43,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55467         {"PCR_S_E"                     ,        44,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55468         {"PCR_A_F"                     ,        45,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55469         {"Q2_S_E"                      ,        46,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55470         {"Q2_A_F"                      ,        47,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55471         {"Q3_S_E"                      ,        48,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55472         {"Q3_A_F"                      ,        49,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55473         {"COM_S_E"                     ,        50,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55474         {"COM_A_F"                     ,        51,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55475         {"PNC_S_E"                     ,        52,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55476         {"PNC_A_F"                     ,        53,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55477         {"RWX_S_E"                     ,        54,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55478         {"RDX_S_E"                     ,        55,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55479         {"PCF_P_E"                     ,        56,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55480         {"PCF_P_F"                     ,        57,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55481         {"PDF_P_E"                     ,        58,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55482         {"PDF_P_F"                     ,        59,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55483         {"Q1_S_E"                      ,        60,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55484         {"Q1_A_F"                      ,        61,     1,      295,    "R/W",  0,      0,      0ull,   1ull},
55485         {"RESERVED_62_63"              ,        62,     2,      295,    "RAZ",  1,      1,      0,      0},
55486         {"RML_RTO"                     ,        0,      1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55487         {"RML_WTO"                     ,        1,      1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55488         {"PCI_RSL"                     ,        2,      1,      296,    "RO",   0,      0,      0ull,   0ull},
55489         {"PO0_2SML"                    ,        3,      1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55490         {"PO1_2SML"                    ,        4,      1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55491         {"RESERVED_5_6"                ,        5,      2,      296,    "RAZ",  0,      0,      0ull,   0ull},
55492         {"I0_RTOUT"                    ,        7,      1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55493         {"I1_RTOUT"                    ,        8,      1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55494         {"RESERVED_9_10"               ,        9,      2,      296,    "RAZ",  0,      0,      0ull,   0ull},
55495         {"I0_OVERF"                    ,        11,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55496         {"I1_OVERF"                    ,        12,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55497         {"RESERVED_13_14"              ,        13,     2,      296,    "RAZ",  0,      0,      0ull,   0ull},
55498         {"P0_RTOUT"                    ,        15,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55499         {"P1_RTOUT"                    ,        16,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55500         {"RESERVED_17_18"              ,        17,     2,      296,    "RAZ",  0,      0,      0ull,   0ull},
55501         {"P0_PERR"                     ,        19,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55502         {"P1_PERR"                     ,        20,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55503         {"RESERVED_21_22"              ,        21,     2,      296,    "RAZ",  0,      0,      0ull,   0ull},
55504         {"G0_RTOUT"                    ,        23,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55505         {"G1_RTOUT"                    ,        24,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55506         {"RESERVED_25_26"              ,        25,     2,      296,    "RAZ",  0,      0,      0ull,   0ull},
55507         {"P0_PPERR"                    ,        27,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55508         {"P1_PPERR"                    ,        28,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55509         {"RESERVED_29_30"              ,        29,     2,      296,    "RAZ",  0,      0,      0ull,   0ull},
55510         {"P0_PTOUT"                    ,        31,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55511         {"P1_PTOUT"                    ,        32,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55512         {"RESERVED_33_34"              ,        33,     2,      296,    "RAZ",  0,      0,      0ull,   0ull},
55513         {"I0_PPERR"                    ,        35,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55514         {"I1_PPERR"                    ,        36,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55515         {"RESERVED_37_38"              ,        37,     2,      296,    "RAZ",  0,      0,      0ull,   0ull},
55516         {"WIN_RTO"                     ,        39,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55517         {"P_DPERR"                     ,        40,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55518         {"IOBDMA"                      ,        41,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55519         {"FCR_S_E"                     ,        42,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55520         {"FCR_A_F"                     ,        43,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55521         {"PCR_S_E"                     ,        44,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55522         {"PCR_A_F"                     ,        45,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55523         {"Q2_S_E"                      ,        46,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55524         {"Q2_A_F"                      ,        47,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55525         {"Q3_S_E"                      ,        48,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55526         {"Q3_A_F"                      ,        49,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55527         {"COM_S_E"                     ,        50,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55528         {"COM_A_F"                     ,        51,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55529         {"PNC_S_E"                     ,        52,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55530         {"PNC_A_F"                     ,        53,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55531         {"RWX_S_E"                     ,        54,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55532         {"RDX_S_E"                     ,        55,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55533         {"PCF_P_E"                     ,        56,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55534         {"PCF_P_F"                     ,        57,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55535         {"PDF_P_E"                     ,        58,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55536         {"PDF_P_F"                     ,        59,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55537         {"Q1_S_E"                      ,        60,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55538         {"Q1_A_F"                      ,        61,     1,      296,    "R/W1C",        0,      0,      0ull,   0ull},
55539         {"RESERVED_62_63"              ,        62,     2,      296,    "RAZ",  1,      1,      0,      0},
55540         {"DBELL"                       ,        0,      16,     297,    "R/W",  0,      1,      0ull,   0},
55541         {"RESERVED_16_63"              ,        16,     48,     297,    "RAZ",  1,      1,      0,      0},
55542         {"SADDR"                       ,        0,      36,     298,    "R/W",  0,      1,      0ull,   0},
55543         {"RESERVED_36_63"              ,        36,     28,     298,    "RAZ",  1,      1,      0,      0},
55544         {"BA"                          ,        0,      28,     299,    "R/W",  0,      1,      0ull,   0},
55545         {"ROW"                         ,        28,     1,      299,    "R/W",  0,      1,      0ull,   0},
55546         {"ROR"                         ,        29,     1,      299,    "R/W",  0,      1,      0ull,   0},
55547         {"NSW"                         ,        30,     1,      299,    "R/W",  0,      1,      0ull,   0},
55548         {"NSR"                         ,        31,     1,      299,    "R/W",  0,      1,      0ull,   0},
55549         {"ESW"                         ,        32,     2,      299,    "R/W",  0,      1,      0ull,   0},
55550         {"ESR"                         ,        34,     2,      299,    "R/W",  0,      1,      0ull,   0},
55551         {"NMERGE"                      ,        36,     1,      299,    "R/W",  0,      1,      0ull,   0},
55552         {"SHORTL"                      ,        37,     1,      299,    "R/W",  0,      1,      0ull,   0},
55553         {"RESERVED_38_63"              ,        38,     26,     299,    "RAZ",  1,      1,      0,      0},
55554         {"INT_VEC"                     ,        0,      64,     300,    "R/W1C",        0,      0,      0ull,   0ull},
55555         {"SIZE"                        ,        0,      32,     301,    "R/W",  0,      1,      0ull,   0},
55556         {"RESERVED_32_63"              ,        32,     32,     301,    "RAZ",  1,      1,      0,      0},
55557         {"ROR_SL0"                     ,        0,      1,      302,    "R/W",  0,      1,      0ull,   0},
55558         {"NSR_SL0"                     ,        1,      1,      302,    "R/W",  0,      1,      0ull,   0},
55559         {"ESR_SL0"                     ,        2,      2,      302,    "R/W",  0,      1,      0ull,   0},
55560         {"ROR_SL1"                     ,        4,      1,      302,    "R/W",  0,      1,      0ull,   0},
55561         {"NSR_SL1"                     ,        5,      1,      302,    "R/W",  0,      1,      0ull,   0},
55562         {"ESR_SL1"                     ,        6,      2,      302,    "R/W",  0,      1,      0ull,   0},
55563         {"RESERVED_8_15"               ,        8,      8,      302,    "RAZ",  0,      0,      0ull,   0ull},
55564         {"IPTR_O0"                     ,        16,     1,      302,    "R/W",  0,      0,      0ull,   1ull},
55565         {"IPTR_O1"                     ,        17,     1,      302,    "R/W",  0,      0,      0ull,   1ull},
55566         {"RESERVED_18_23"              ,        18,     6,      302,    "RAZ",  0,      0,      0ull,   0ull},
55567         {"O0_CSRM"                     ,        24,     1,      302,    "R/W",  0,      0,      0ull,   1ull},
55568         {"O1_CSRM"                     ,        25,     1,      302,    "R/W",  0,      0,      0ull,   1ull},
55569         {"RESERVED_26_27"              ,        26,     2,      302,    "RAZ",  0,      0,      0ull,   0ull},
55570         {"O0_RO"                       ,        28,     1,      302,    "R/W",  0,      1,      0ull,   0},
55571         {"O0_NS"                       ,        29,     1,      302,    "R/W",  0,      1,      0ull,   0},
55572         {"O0_ES"                       ,        30,     2,      302,    "R/W",  0,      1,      0ull,   0},
55573         {"O1_RO"                       ,        32,     1,      302,    "R/W",  0,      1,      0ull,   0},
55574         {"O1_NS"                       ,        33,     1,      302,    "R/W",  0,      1,      0ull,   0},
55575         {"O1_ES"                       ,        34,     2,      302,    "R/W",  0,      1,      0ull,   0},
55576         {"RESERVED_36_43"              ,        36,     8,      302,    "RAZ",  0,      0,      0ull,   0ull},
55577         {"P0_BMODE"                    ,        44,     1,      302,    "R/W",  0,      0,      0ull,   0ull},
55578         {"P1_BMODE"                    ,        45,     1,      302,    "R/W",  0,      0,      0ull,   0ull},
55579         {"RESERVED_46_47"              ,        46,     2,      302,    "RAZ",  0,      0,      0ull,   0ull},
55580         {"PKT_RR"                      ,        48,     1,      302,    "R/W",  0,      0,      0ull,   0ull},
55581         {"RESERVED_49_63"              ,        49,     15,     302,    "RAZ",  1,      1,      0,      0},
55582         {"NADDR"                       ,        0,      61,     303,    "RO",   0,      1,      0ull,   0},
55583         {"STATE"                       ,        61,     2,      303,    "RO",   0,      0,      0ull,   0ull},
55584         {"RESERVED_63_63"              ,        63,     1,      303,    "RAZ",  1,      1,      0,      0},
55585         {"NADDR"                       ,        0,      61,     304,    "RO",   0,      1,      0ull,   0},
55586         {"STATE"                       ,        61,     3,      304,    "RO",   0,      0,      0ull,   0ull},
55587         {"AVAIL"                       ,        0,      32,     305,    "RO",   0,      0,      0ull,   0ull},
55588         {"FCNT"                        ,        32,     6,      305,    "RO",   0,      0,      0ull,   0ull},
55589         {"RESERVED_38_63"              ,        38,     26,     305,    "RAZ",  1,      1,      0,      0},
55590         {"AVAIL"                       ,        0,      32,     306,    "RO",   0,      0,      0ull,   0ull},
55591         {"FCNT"                        ,        32,     5,      306,    "RO",   0,      0,      0ull,   0ull},
55592         {"RESERVED_37_63"              ,        37,     27,     306,    "RAZ",  1,      1,      0,      0},
55593         {"RD_BRST"                     ,        0,      7,      307,    "R/W",  0,      0,      17ull,  64ull},
55594         {"WR_BRST"                     ,        7,      7,      307,    "R/W",  0,      0,      16ull,  64ull},
55595         {"RESERVED_14_63"              ,        14,     50,     307,    "RAZ",  1,      1,      0,      0},
55596         {"PARK_DEV"                    ,        0,      3,      308,    "R/W",  0,      1,      0ull,   0},
55597         {"PARK_MOD"                    ,        3,      1,      308,    "R/W",  0,      1,      0ull,   0},
55598         {"EN"                          ,        4,      1,      308,    "R/W",  0,      1,      0ull,   0},
55599         {"RESERVED_5_7"                ,        5,      3,      308,    "RAZ",  1,      1,      0,      0},
55600         {"PCI_OVR"                     ,        8,      4,      308,    "R/W",  0,      1,      0ull,   0},
55601         {"HOSTMODE"                    ,        12,     1,      308,    "RO",   1,      1,      0,      0},
55602         {"RESERVED_13_63"              ,        13,     51,     308,    "RAZ",  1,      1,      0,      0},
55603         {"CMD_SIZE"                    ,        0,      11,     309,    "R/W",  0,      0,      9ull,   9ull},
55604         {"RESERVED_11_63"              ,        11,     53,     309,    "RAZ",  1,      1,      0,      0},
55605         {"RSV_A"                       ,        0,      6,      310,    "R/W",  0,      1,      0ull,   0},
55606         {"SKP_LEN"                     ,        6,      7,      310,    "R/W",  0,      1,      0ull,   0},
55607         {"RSV_B"                       ,        13,     1,      310,    "R/W",  0,      1,      0ull,   0},
55608         {"PAR_MODE"                    ,        14,     2,      310,    "R/W",  0,      1,      0ull,   0},
55609         {"RSV_C"                       ,        16,     5,      310,    "R/W",  0,      1,      0ull,   0},
55610         {"USE_IHDR"                    ,        21,     1,      310,    "R/W",  0,      1,      0ull,   0},
55611         {"RSV_D"                       ,        22,     6,      310,    "R/W",  0,      1,      0ull,   0},
55612         {"RSKP_LEN"                    ,        28,     7,      310,    "R/W",  0,      1,      8ull,   0},
55613         {"RSV_E"                       ,        35,     1,      310,    "R/W",  0,      1,      0ull,   0},
55614         {"RPARMODE"                    ,        36,     2,      310,    "R/W",  0,      1,      0ull,   0},
55615         {"RSV_F"                       ,        38,     5,      310,    "R/W",  0,      1,      0ull,   0},
55616         {"PBP"                         ,        43,     1,      310,    "R/W",  0,      1,      0ull,   0},
55617         {"RESERVED_44_63"              ,        44,     20,     310,    "RAZ",  1,      1,      0,      0},
55618         {"RSV_A"                       ,        0,      6,      311,    "R/W",  0,      1,      0ull,   0},
55619         {"SKP_LEN"                     ,        6,      7,      311,    "R/W",  0,      1,      0ull,   0},
55620         {"RSV_B"                       ,        13,     1,      311,    "R/W",  0,      1,      0ull,   0},
55621         {"PAR_MODE"                    ,        14,     2,      311,    "R/W",  0,      1,      0ull,   0},
55622         {"RSV_C"                       ,        16,     5,      311,    "R/W",  0,      1,      0ull,   0},
55623         {"USE_IHDR"                    ,        21,     1,      311,    "R/W",  0,      1,      0ull,   0},
55624         {"RSV_D"                       ,        22,     6,      311,    "R/W",  0,      1,      0ull,   0},
55625         {"RSKP_LEN"                    ,        28,     7,      311,    "R/W",  0,      1,      8ull,   0},
55626         {"RSV_E"                       ,        35,     1,      311,    "R/W",  0,      1,      0ull,   0},
55627         {"RPARMODE"                    ,        36,     2,      311,    "R/W",  0,      1,      0ull,   0},
55628         {"RSV_F"                       ,        38,     5,      311,    "R/W",  0,      1,      0ull,   0},
55629         {"PBP"                         ,        43,     1,      311,    "R/W",  0,      1,      0ull,   0},
55630         {"RESERVED_44_63"              ,        44,     20,     311,    "RAZ",  1,      1,      0,      0},
55631         {"ENB"                         ,        0,      4,      312,    "R/W",  0,      0,      15ull,  15ull},
55632         {"BP_ON"                       ,        4,      4,      312,    "RO",   0,      0,      0ull,   0ull},
55633         {"RESERVED_8_63"               ,        8,      56,     312,    "RAZ",  1,      1,      0,      0},
55634         {"MIO"                         ,        0,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55635         {"GMX0"                        ,        1,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55636         {"GMX1"                        ,        2,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55637         {"NPI"                         ,        3,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55638         {"KEY"                         ,        4,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55639         {"FPA"                         ,        5,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55640         {"DFA"                         ,        6,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55641         {"ZIP"                         ,        7,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55642         {"RESERVED_8_8"                ,        8,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55643         {"IPD"                         ,        9,      1,      313,    "RO",   0,      0,      0ull,   0ull},
55644         {"PKO"                         ,        10,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55645         {"TIM"                         ,        11,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55646         {"POW"                         ,        12,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55647         {"USB"                         ,        13,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55648         {"RAD"                         ,        14,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55649         {"RESERVED_15_15"              ,        15,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55650         {"L2C"                         ,        16,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55651         {"LMC"                         ,        17,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55652         {"SPX0"                        ,        18,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55653         {"SPX1"                        ,        19,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55654         {"PIP"                         ,        20,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55655         {"RESERVED_21_21"              ,        21,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55656         {"ASX0"                        ,        22,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55657         {"ASX1"                        ,        23,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55658         {"RESERVED_24_27"              ,        24,     4,      313,    "RO",   0,      0,      0ull,   0ull},
55659         {"AGL"                         ,        28,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55660         {"LMC1"                        ,        29,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55661         {"IOB"                         ,        30,     1,      313,    "RO",   0,      0,      0ull,   0ull},
55662         {"RESERVED_31_63"              ,        31,     33,     313,    "RO",   0,      0,      0ull,   0ull},
55663         {"SIZE"                        ,        0,      32,     314,    "R/W",  0,      1,      0ull,   0},
55664         {"RESERVED_32_63"              ,        32,     32,     314,    "RAZ",  1,      1,      0,      0},
55665         {"TIME"                        ,        0,      32,     315,    "R/W",  0,      0,      0ull,   131072ull},
55666         {"RESERVED_32_63"              ,        32,     32,     315,    "RAZ",  1,      1,      0,      0},
55667         {"ADDR_V"                      ,        0,      1,      316,    "R/W",  0,      1,      0ull,   0},
55668         {"END_SWP"                     ,        1,      2,      316,    "R/W",  0,      1,      0ull,   0},
55669         {"CA"                          ,        3,      1,      316,    "R/W",  0,      0,      0ull,   0ull},
55670         {"ADDR_IDX"                    ,        4,      14,     316,    "R/W",  0,      1,      0ull,   0},
55671         {"RESERVED_18_31"              ,        18,     14,     316,    "RAZ",  1,      1,      0,      0},
55672         {"DBG2N_BS"                    ,        0,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55673         {"DAT2N_BS"                    ,        1,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55674         {"CSR2N_BS"                    ,        2,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55675         {"RSP2P_BS"                    ,        3,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55676         {"CSRR_BS"                     ,        4,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55677         {"CSR2P_BS"                    ,        5,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55678         {"CMD_BS"                      ,        6,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55679         {"CMD0_BS"                     ,        7,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55680         {"DMA0_BS"                     ,        8,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55681         {"RSP_BS"                      ,        9,      1,      317,    "RO",   0,      0,      0ull,   0ull},
55682         {"RESERVED_10_63"              ,        10,     54,     317,    "RAZ",  1,      1,      0,      0},
55683         {"VENDID"                      ,        0,      16,     318,    "RO",   0,      0,      6013ull,        6013ull},
55684         {"DEVID"                       ,        16,     16,     318,    "RO",   0,      0,      112ull, 32ull},
55685         {"ISAE"                        ,        0,      1,      319,    "RO",   0,      0,      0ull,   0ull},
55686         {"MSAE"                        ,        1,      1,      319,    "R/W",  0,      0,      0ull,   1ull},
55687         {"ME"                          ,        2,      1,      319,    "R/W",  0,      0,      0ull,   1ull},
55688         {"SCSE"                        ,        3,      1,      319,    "RO",   0,      0,      0ull,   0ull},
55689         {"MWICE"                       ,        4,      1,      319,    "R/W",  0,      0,      0ull,   0ull},
55690         {"VPS"                         ,        5,      1,      319,    "RO",   0,      0,      0ull,   0ull},
55691         {"PEE"                         ,        6,      1,      319,    "R/W",  0,      0,      0ull,   1ull},
55692         {"ADS"                         ,        7,      1,      319,    "RO",   0,      0,      0ull,   0ull},
55693         {"SEE"                         ,        8,      1,      319,    "R/W",  0,      0,      0ull,   1ull},
55694         {"FBBE"                        ,        9,      1,      319,    "R/W",  0,      0,      0ull,   1ull},
55695         {"I_DIS"                       ,        10,     1,      319,    "R/W",  0,      0,      0ull,   0ull},
55696         {"RESERVED_11_18"              ,        11,     8,      319,    "RAZ",  1,      1,      0,      0},
55697         {"I_STAT"                      ,        19,     1,      319,    "RO",   0,      0,      0ull,   0ull},
55698         {"CLE"                         ,        20,     1,      319,    "RO",   0,      0,      1ull,   1ull},
55699         {"M66"                         ,        21,     1,      319,    "RO",   0,      0,      1ull,   1ull},
55700         {"RESERVED_22_22"              ,        22,     1,      319,    "RAZ",  1,      1,      0,      0},
55701         {"FBB"                         ,        23,     1,      319,    "RO",   0,      1,      1ull,   0},
55702         {"MDPE"                        ,        24,     1,      319,    "R/W1C",        0,      0,      0ull,   0ull},
55703         {"DEVT"                        ,        25,     2,      319,    "RO",   0,      0,      1ull,   1ull},
55704         {"STA"                         ,        27,     1,      319,    "R/W1C",        0,      0,      0ull,   0ull},
55705         {"RTA"                         ,        28,     1,      319,    "R/W1C",        0,      0,      0ull,   0ull},
55706         {"RMA"                         ,        29,     1,      319,    "R/W1C",        0,      0,      0ull,   0ull},
55707         {"SSE"                         ,        30,     1,      319,    "R/W1C",        0,      0,      0ull,   0ull},
55708         {"DPE"                         ,        31,     1,      319,    "R/W1C",        0,      0,      0ull,   0ull},
55709         {"RID"                         ,        0,      8,      320,    "RO",   0,      0,      0ull,   0ull},
55710         {"CC"                          ,        8,      24,     320,    "RO",   0,      0,      733184ull,      733184ull},
55711         {"CLS"                         ,        0,      8,      321,    "R/W",  0,      1,      0ull,   0},
55712         {"LT"                          ,        8,      8,      321,    "R/W",  0,      0,      0ull,   64ull},
55713         {"HT"                          ,        16,     8,      321,    "RO",   0,      0,      0ull,   0ull},
55714         {"BCOD"                        ,        24,     4,      321,    "RO",   0,      0,      0ull,   0ull},
55715         {"RESERVED_28_29"              ,        28,     2,      321,    "RAZ",  1,      1,      0,      0},
55716         {"BRB"                         ,        30,     1,      321,    "R/W",  0,      0,      0ull,   0ull},
55717         {"BCAP"                        ,        31,     1,      321,    "RO",   0,      0,      0ull,   0ull},
55718         {"MSPC"                        ,        0,      1,      322,    "RO",   0,      0,      0ull,   0ull},
55719         {"TYP"                         ,        1,      2,      322,    "RO",   0,      0,      2ull,   2ull},
55720         {"PF"                          ,        3,      1,      322,    "RO",   0,      0,      1ull,   1ull},
55721         {"LBASEZ"                      ,        4,      8,      322,    "RO",   0,      0,      0ull,   0ull},
55722         {"LBASE"                       ,        12,     20,     322,    "R/W",  0,      1,      0ull,   0},
55723         {"HBASE"                       ,        0,      32,     323,    "R/W",  0,      1,      0ull,   0},
55724         {"MSPC"                        ,        0,      1,      324,    "RO",   0,      0,      0ull,   0ull},
55725         {"TYP"                         ,        1,      2,      324,    "RO",   0,      0,      2ull,   2ull},
55726         {"PF"                          ,        3,      1,      324,    "RO",   0,      0,      1ull,   1ull},
55727         {"LBASEZ"                      ,        4,      23,     324,    "RO",   0,      0,      0ull,   0ull},
55728         {"LBASE"                       ,        27,     5,      324,    "R/W",  0,      1,      0ull,   0},
55729         {"HBASE"                       ,        0,      32,     325,    "R/W",  0,      1,      0ull,   0},
55730         {"MSPC"                        ,        0,      1,      326,    "RO",   0,      0,      0ull,   0ull},
55731         {"TYP"                         ,        1,      2,      326,    "RO",   0,      0,      2ull,   2ull},
55732         {"PF"                          ,        3,      1,      326,    "RO",   0,      0,      1ull,   1ull},
55733         {"LBASEZ"                      ,        4,      28,     326,    "RO",   0,      0,      0ull,   0ull},
55734         {"HBASEZ"                      ,        0,      7,      327,    "RO",   0,      0,      0ull,   0ull},
55735         {"HBASE"                       ,        7,      25,     327,    "R/W",  0,      1,      0ull,   0},
55736         {"CISP"                        ,        0,      32,     328,    "RO",   0,      0,      0ull,   0ull},
55737         {"SSVID"                       ,        0,      16,     329,    "RO",   0,      0,      6013ull,        6013ull},
55738         {"SSID"                        ,        16,     16,     329,    "RO",   0,      0,      1ull,   1ull},
55739         {"ERBAR_EN"                    ,        0,      1,      330,    "R/W",  0,      0,      0ull,   0ull},
55740         {"RESERVED_1_10"               ,        1,      10,     330,    "RAZ",  1,      1,      0,      0},
55741         {"ERBARZ"                      ,        11,     5,      330,    "RO",   0,      0,      0ull,   0ull},
55742         {"ERBAR"                       ,        16,     16,     330,    "R/W",  0,      1,      0ull,   0},
55743         {"CP"                          ,        0,      8,      331,    "RO",   0,      0,      224ull, 224ull},
55744         {"RESERVED_8_31"               ,        8,      24,     331,    "RAZ",  1,      1,      0,      0},
55745         {"IL"                          ,        0,      8,      332,    "R/W",  0,      1,      0ull,   0},
55746         {"INTA"                        ,        8,      8,      332,    "RO",   0,      0,      1ull,   1ull},
55747         {"MG"                          ,        16,     8,      332,    "RO",   0,      0,      64ull,  64ull},
55748         {"ML"                          ,        24,     8,      332,    "RO",   0,      0,      64ull,  64ull},
55749         {"MLTD"                        ,        0,      1,      333,    "R/W",  0,      0,      0ull,   1ull},
55750         {"TSWC"                        ,        1,      1,      333,    "R/W",  0,      0,      0ull,   0ull},
55751         {"RESERVED_2_2"                ,        2,      1,      333,    "RAZ",  1,      1,      0,      0},
55752         {"DPPMR"                       ,        3,      1,      333,    "R/W",  0,      0,      0ull,   0ull},
55753         {"PBE"                         ,        4,      12,     333,    "R/W",  0,      0,      0ull,   0ull},
55754         {"TILT"                        ,        16,     4,      333,    "R/W",  0,      0,      0ull,   0ull},
55755         {"TSLTE"                       ,        20,     3,      333,    "R/W",  0,      0,      0ull,   0ull},
55756         {"TMAE"                        ,        23,     1,      333,    "R/W",  0,      0,      0ull,   0ull},
55757         {"TWTAE"                       ,        24,     1,      333,    "R/W",  0,      0,      0ull,   0ull},
55758         {"TWSEN"                       ,        25,     1,      333,    "R/W",  0,      0,      0ull,   0ull},
55759         {"TWSEI"                       ,        26,     1,      333,    "R/W",  0,      0,      0ull,   0ull},
55760         {"TRTAE"                       ,        27,     1,      333,    "R/W",  0,      0,      0ull,   0ull},
55761         {"TRDRS"                       ,        28,     1,      333,    "R/W",  0,      0,      0ull,   0ull},
55762         {"RDSATI"                      ,        29,     1,      333,    "R/W",  0,      0,      0ull,   0ull},
55763         {"TRDARD"                      ,        30,     1,      333,    "R/W1C",        0,      0,      0ull,   0ull},
55764         {"TRDNPR"                      ,        31,     1,      333,    "R/W1C",        0,      0,      0ull,   0ull},
55765         {"TSCME"                       ,        0,      32,     334,    "R/W1C",        0,      1,      0ull,   0},
55766         {"TDSRPS"                      ,        0,      32,     335,    "R/W1C",        0,      0,      0ull,   0ull},
55767         {"TDOMC"                       ,        0,      5,      336,    "R/W",  0,      0,      1ull,   1ull},
55768         {"TIDOMC"                      ,        5,      1,      336,    "R/W",  0,      0,      0ull,   0ull},
55769         {"RESERVED_6_6"                ,        6,      1,      336,    "RAZ",  1,      1,      0,      0},
55770         {"TIBDE"                       ,        7,      1,      336,    "R/W",  0,      0,      0ull,   0ull},
55771         {"TIBCD"                       ,        8,      1,      336,    "R/W1C",        0,      0,      0ull,   0ull},
55772         {"RESERVED_9_10"               ,        9,      2,      336,    "RAZ",  1,      1,      0,      0},
55773         {"TMAPES"                      ,        11,     1,      336,    "R/W1C",        0,      0,      0ull,   0ull},
55774         {"TMDPES"                      ,        12,     1,      336,    "R/W1C",        0,      0,      0ull,   0ull},
55775         {"TMSE"                        ,        13,     1,      336,    "R/W1C",        0,      0,      0ull,   0ull},
55776         {"TMEI"                        ,        14,     1,      336,    "RO",   0,      0,      0ull,   0ull},
55777         {"TECI"                        ,        15,     1,      336,    "RO",   0,      0,      0ull,   0ull},
55778         {"TMES"                        ,        16,     8,      336,    "RO",   0,      0,      0ull,   0ull},
55779         {"MDRRMC"                      ,        24,     3,      336,    "R/W",  0,      0,      2ull,   2ull},
55780         {"MDRIMC"                      ,        27,     1,      336,    "R/W",  0,      0,      0ull,   0ull},
55781         {"MDRE"                        ,        28,     1,      336,    "R/W",  0,      0,      0ull,   0ull},
55782         {"MDWE"                        ,        29,     1,      336,    "R/W",  0,      0,      0ull,   0ull},
55783         {"MRBCI"                       ,        30,     1,      336,    "R/W",  0,      0,      0ull,   0ull},
55784         {"MRBCM"                       ,        31,     1,      336,    "R/W",  0,      0,      1ull,   1ull},
55785         {"MDSP"                        ,        0,      32,     337,    "R/W1C",        0,      1,      0ull,   0},
55786         {"SCMRE"                       ,        0,      32,     338,    "R/W1C",        0,      1,      0ull,   0},
55787         {"MTTV"                        ,        0,      8,      339,    "R/W",  0,      0,      0ull,   0ull},
55788         {"MRV"                         ,        8,      8,      339,    "R/W",  0,      0,      0ull,   255ull},
55789         {"MTTA"                        ,        16,     1,      339,    "R/W1C",        0,      0,      0ull,   0ull},
55790         {"MRA"                         ,        17,     1,      339,    "R/W1C",        0,      0,      0ull,   0ull},
55791         {"FLUSH"                       ,        18,     1,      339,    "R/W",  0,      0,      1ull,   1ull},
55792         {"RESERVED_19_24"              ,        19,     6,      339,    "RAZ",  1,      1,      0,      0},
55793         {"MAC"                         ,        25,     7,      339,    "R/W",  0,      0,      0ull,   0ull},
55794         {"PXCID"                       ,        0,      8,      340,    "RO",   0,      0,      7ull,   7ull},
55795         {"NCP"                         ,        8,      8,      340,    "RO",   0,      0,      232ull, 232ull},
55796         {"DPERE"                       ,        16,     1,      340,    "R/W",  0,      0,      0ull,   0ull},
55797         {"ROE"                         ,        17,     1,      340,    "R/W",  0,      0,      1ull,   1ull},
55798         {"MMBC"                        ,        18,     2,      340,    "R/W",  0,      0,      0ull,   0ull},
55799         {"MOST"                        ,        20,     3,      340,    "R/W",  0,      0,      3ull,   3ull},
55800         {"RESERVED_23_31"              ,        23,     9,      340,    "RAZ",  1,      1,      0,      0},
55801         {"FN"                          ,        0,      3,      341,    "RO",   0,      0,      0ull,   0ull},
55802         {"DN"                          ,        3,      5,      341,    "RO",   0,      0,      31ull,  31ull},
55803         {"BN"                          ,        8,      8,      341,    "RO",   0,      1,      17ull,  0},
55804         {"W64"                         ,        16,     1,      341,    "RO",   0,      0,      1ull,   1ull},
55805         {"M133"                        ,        17,     1,      341,    "RO",   0,      0,      1ull,   1ull},
55806         {"SCD"                         ,        18,     1,      341,    "R/W1C",        0,      1,      0ull,   0},
55807         {"USC"                         ,        19,     1,      341,    "R/W1C",        0,      1,      0ull,   0},
55808         {"DC"                          ,        20,     1,      341,    "RO",   0,      0,      0ull,   0ull},
55809         {"MMRBCD"                      ,        21,     2,      341,    "RO",   0,      0,      2ull,   2ull},
55810         {"MOSTD"                       ,        23,     3,      341,    "RO",   0,      0,      3ull,   3ull},
55811         {"MCRSD"                       ,        26,     3,      341,    "RO",   0,      0,      7ull,   7ull},
55812         {"SCEMR"                       ,        29,     1,      341,    "R/W1C",        0,      1,      0ull,   0},
55813         {"RESERVED_30_31"              ,        30,     2,      341,    "RAZ",  1,      1,      0,      0},
55814         {"PMCID"                       ,        0,      8,      342,    "RO",   0,      0,      1ull,   1ull},
55815         {"NCP"                         ,        8,      8,      342,    "RO",   0,      0,      240ull, 240ull},
55816         {"PCIMIV"                      ,        16,     3,      342,    "RO",   0,      0,      2ull,   2ull},
55817         {"PMEC"                        ,        19,     1,      342,    "RO",   0,      0,      0ull,   0ull},
55818         {"RESERVED_20_20"              ,        20,     1,      342,    "RAZ",  1,      1,      0,      0},
55819         {"DSI"                         ,        21,     1,      342,    "RO",   0,      0,      0ull,   0ull},
55820         {"AUXC"                        ,        22,     3,      342,    "RO",   0,      0,      0ull,   0ull},
55821         {"D1S"                         ,        25,     1,      342,    "RO",   0,      0,      0ull,   0ull},
55822         {"D2S"                         ,        26,     1,      342,    "RO",   0,      0,      0ull,   0ull},
55823         {"PMES"                        ,        27,     5,      342,    "RO",   0,      0,      0ull,   0ull},
55824         {"PS"                          ,        0,      2,      343,    "R/W",  0,      0,      0ull,   0ull},
55825         {"RESERVED_2_7"                ,        2,      6,      343,    "RAZ",  1,      1,      0,      0},
55826         {"PMEENS"                      ,        8,      1,      343,    "R/W",  0,      0,      0ull,   0ull},
55827         {"PMDS"                        ,        9,      4,      343,    "R/W",  0,      0,      0ull,   0ull},
55828         {"PMEDSIA"                     ,        13,     2,      343,    "RO",   0,      0,      0ull,   0ull},
55829         {"PMESS"                       ,        15,     1,      343,    "R/W1C",        0,      0,      0ull,   0ull},
55830         {"RESERVED_16_21"              ,        16,     6,      343,    "RAZ",  1,      1,      0,      0},
55831         {"BD3H"                        ,        22,     1,      343,    "RO",   0,      0,      0ull,   0ull},
55832         {"BPCCEN"                      ,        23,     1,      343,    "RO",   0,      0,      0ull,   0ull},
55833         {"PMDIA"                       ,        24,     8,      343,    "RO",   0,      0,      0ull,   0ull},
55834         {"MSICID"                      ,        0,      8,      344,    "RO",   0,      0,      5ull,   5ull},
55835         {"NCP"                         ,        8,      8,      344,    "RO",   0,      0,      0ull,   0ull},
55836         {"MSIEN"                       ,        16,     1,      344,    "R/W",  0,      0,      0ull,   0ull},
55837         {"MMC"                         ,        17,     3,      344,    "RO",   0,      0,      0ull,   0ull},
55838         {"MME"                         ,        20,     3,      344,    "R/W",  0,      0,      0ull,   0ull},
55839         {"M64"                         ,        23,     1,      344,    "RO",   0,      0,      1ull,   1ull},
55840         {"RESERVED_24_31"              ,        24,     8,      344,    "RAZ",  1,      1,      0,      0},
55841         {"RESERVED_0_1"                ,        0,      2,      345,    "RAZ",  1,      1,      0,      0},
55842         {"MSI31T2"                     ,        2,      30,     345,    "R/W",  0,      1,      0ull,   0},
55843         {"MSI"                         ,        0,      32,     346,    "R/W",  0,      1,      0ull,   0},
55844         {"MSIMD"                       ,        0,      16,     347,    "R/W",  0,      1,      0ull,   0},
55845         {"RESERVED_16_31"              ,        16,     16,     347,    "RAZ",  1,      1,      0,      0},
55846         {"PCICNT"                      ,        0,      32,     348,    "R/W",  0,      1,      0ull,   0},
55847         {"AP_SPEED"                    ,        32,     2,      348,    "RO",   1,      1,      0,      0},
55848         {"AP_PCIX"                     ,        34,     1,      348,    "RO",   1,      1,      0,      0},
55849         {"HM_SPEED"                    ,        35,     2,      348,    "RO",   0,      1,      0ull,   0},
55850         {"HM_PCIX"                     ,        37,     1,      348,    "RO",   0,      1,      0ull,   0},
55851         {"RESERVED_38_63"              ,        38,     26,     348,    "RAZ",  1,      1,      0,      0},
55852         {"BAR2_CAX"                    ,        0,      1,      349,    "R/W",  0,      0,      0ull,   0ull},
55853         {"BAR2_ESX"                    ,        1,      2,      349,    "R/W",  0,      1,      0ull,   0},
55854         {"BAR2_ENB"                    ,        3,      1,      349,    "R/W",  0,      0,      0ull,   1ull},
55855         {"TSR_HWM"                     ,        4,      3,      349,    "R/W",  0,      1,      1ull,   0},
55856         {"PMO_FPC"                     ,        7,      3,      349,    "R/W",  0,      0,      0ull,   0ull},
55857         {"PMO_AMOD"                    ,        10,     1,      349,    "R/W",  0,      0,      0ull,   0ull},
55858         {"B12_BIST"                    ,        11,     1,      349,    "RO",   0,      0,      0ull,   0ull},
55859         {"AP_64AD"                     ,        12,     1,      349,    "RO",   0,      1,      0ull,   0},
55860         {"AP_PCIX"                     ,        13,     1,      349,    "RO",   0,      1,      0ull,   0},
55861         {"RESERVED_14_14"              ,        14,     1,      349,    "RAZ",  0,      0,      0ull,   0ull},
55862         {"EN_WFILT"                    ,        15,     1,      349,    "R/W",  0,      0,      0ull,   1ull},
55863         {"SCM"                         ,        16,     1,      349,    "RO",   0,      1,      0ull,   0},
55864         {"SCMTYP"                      ,        17,     1,      349,    "RO",   0,      1,      0ull,   0},
55865         {"BAR2PRES"                    ,        18,     1,      349,    "R/W",  1,      1,      0,      0},
55866         {"ERST_N"                      ,        19,     1,      349,    "RO",   0,      0,      1ull,   1ull},
55867         {"BB0"                         ,        20,     1,      349,    "R/W",  0,      0,      0ull,   0ull},
55868         {"BB1"                         ,        21,     1,      349,    "R/W",  0,      0,      0ull,   0ull},
55869         {"BB_ES"                       ,        22,     2,      349,    "R/W",  0,      0,      0ull,   0ull},
55870         {"BB_CA"                       ,        24,     1,      349,    "R/W",  0,      0,      0ull,   0ull},
55871         {"BB1_SIZ"                     ,        25,     1,      349,    "R/W",  0,      0,      0ull,   0ull},
55872         {"BB1_HOLE"                    ,        26,     3,      349,    "R/W",  0,      0,      0ull,   0ull},
55873         {"RESERVED_29_31"              ,        29,     3,      349,    "RAZ",  1,      1,      0,      0},
55874         {"INC_VAL"                     ,        0,      16,     350,    "R/W",  0,      1,      0ull,   0},
55875         {"RESERVED_16_31"              ,        16,     16,     350,    "RAZ",  1,      1,      0,      0},
55876         {"DMA_CNT"                     ,        0,      32,     351,    "R/W",  0,      0,      0ull,   0ull},
55877         {"PKT_CNT"                     ,        0,      32,     352,    "R/W",  0,      1,      0ull,   0},
55878         {"DMA_TIME"                    ,        0,      32,     353,    "R/W",  0,      1,      0ull,   0},
55879         {"ICNT"                        ,        0,      32,     354,    "R/W1C",        0,      0,      0ull,   0ull},
55880         {"ITR_WABT"                    ,        0,      1,      355,    "R/W",  0,      1,      0ull,   0},
55881         {"IMR_WABT"                    ,        1,      1,      355,    "R/W",  0,      1,      0ull,   0},
55882         {"IMR_WTTO"                    ,        2,      1,      355,    "R/W",  0,      1,      0ull,   0},
55883         {"ITR_ABT"                     ,        3,      1,      355,    "R/W",  0,      1,      0ull,   0},
55884         {"IMR_ABT"                     ,        4,      1,      355,    "R/W",  0,      1,      0ull,   0},
55885         {"IMR_TTO"                     ,        5,      1,      355,    "R/W",  0,      1,      0ull,   0},
55886         {"IMSI_PER"                    ,        6,      1,      355,    "R/W",  0,      1,      0ull,   0},
55887         {"IMSI_TABT"                   ,        7,      1,      355,    "R/W",  0,      1,      0ull,   0},
55888         {"IMSI_MABT"                   ,        8,      1,      355,    "R/W",  0,      1,      0ull,   0},
55889         {"IMSC_MSG"                    ,        9,      1,      355,    "R/W",  0,      1,      0ull,   0},
55890         {"ITSR_ABT"                    ,        10,     1,      355,    "R/W",  0,      1,      0ull,   0},
55891         {"ISERR"                       ,        11,     1,      355,    "R/W",  0,      1,      0ull,   0},
55892         {"IAPERR"                      ,        12,     1,      355,    "R/W",  0,      1,      0ull,   0},
55893         {"IDPERR"                      ,        13,     1,      355,    "R/W",  0,      1,      0ull,   0},
55894         {"ILL_RWR"                     ,        14,     1,      355,    "R/W",  0,      1,      0ull,   0},
55895         {"ILL_RRD"                     ,        15,     1,      355,    "R/W",  0,      1,      0ull,   0},
55896         {"IRSL_INT"                    ,        16,     1,      355,    "R/W",  0,      1,      0ull,   0},
55897         {"IPCNT0"                      ,        17,     1,      355,    "R/W",  0,      1,      0ull,   0},
55898         {"IPCNT1"                      ,        18,     1,      355,    "R/W",  0,      1,      0ull,   0},
55899         {"RESERVED_19_20"              ,        19,     2,      355,    "RAZ",  0,      1,      0ull,   0},
55900         {"IPTIME0"                     ,        21,     1,      355,    "R/W",  0,      1,      0ull,   0},
55901         {"IPTIME1"                     ,        22,     1,      355,    "R/W",  0,      1,      0ull,   0},
55902         {"RESERVED_23_24"              ,        23,     2,      355,    "RAZ",  0,      1,      0ull,   0},
55903         {"IDCNT0"                      ,        25,     1,      355,    "R/W",  0,      1,      0ull,   0},
55904         {"IDCNT1"                      ,        26,     1,      355,    "R/W",  0,      1,      0ull,   0},
55905         {"IDTIME0"                     ,        27,     1,      355,    "R/W",  0,      1,      0ull,   0},
55906         {"IDTIME1"                     ,        28,     1,      355,    "R/W",  0,      1,      0ull,   0},
55907         {"DMA0_FI"                     ,        29,     1,      355,    "R/W",  0,      1,      0ull,   0},
55908         {"DMA1_FI"                     ,        30,     1,      355,    "R/W",  0,      1,      0ull,   0},
55909         {"WIN_WR"                      ,        31,     1,      355,    "R/W",  0,      1,      0ull,   0},
55910         {"ILL_WR"                      ,        32,     1,      355,    "R/W",  0,      1,      0ull,   0},
55911         {"ILL_RD"                      ,        33,     1,      355,    "R/W",  0,      1,      0ull,   0},
55912         {"RESERVED_34_63"              ,        34,     30,     355,    "RAZ",  1,      1,      0,      0},
55913         {"RTR_WABT"                    ,        0,      1,      356,    "R/W",  0,      1,      0ull,   0},
55914         {"RMR_WABT"                    ,        1,      1,      356,    "R/W",  0,      1,      0ull,   0},
55915         {"RMR_WTTO"                    ,        2,      1,      356,    "R/W",  0,      1,      0ull,   0},
55916         {"RTR_ABT"                     ,        3,      1,      356,    "R/W",  0,      1,      0ull,   0},
55917         {"RMR_ABT"                     ,        4,      1,      356,    "R/W",  0,      1,      0ull,   0},
55918         {"RMR_TTO"                     ,        5,      1,      356,    "R/W",  0,      1,      0ull,   0},
55919         {"RMSI_PER"                    ,        6,      1,      356,    "R/W",  0,      1,      0ull,   0},
55920         {"RMSI_TABT"                   ,        7,      1,      356,    "R/W",  0,      1,      0ull,   0},
55921         {"RMSI_MABT"                   ,        8,      1,      356,    "R/W",  0,      1,      0ull,   0},
55922         {"RMSC_MSG"                    ,        9,      1,      356,    "R/W",  0,      1,      0ull,   0},
55923         {"RTSR_ABT"                    ,        10,     1,      356,    "R/W",  0,      1,      0ull,   0},
55924         {"RSERR"                       ,        11,     1,      356,    "R/W",  0,      1,      0ull,   0},
55925         {"RAPERR"                      ,        12,     1,      356,    "R/W",  0,      1,      0ull,   0},
55926         {"RDPERR"                      ,        13,     1,      356,    "R/W",  0,      1,      0ull,   0},
55927         {"ILL_RWR"                     ,        14,     1,      356,    "R/W",  0,      1,      0ull,   0},
55928         {"ILL_RRD"                     ,        15,     1,      356,    "R/W",  0,      1,      0ull,   0},
55929         {"RRSL_INT"                    ,        16,     1,      356,    "R/W",  0,      1,      0ull,   0},
55930         {"RPCNT0"                      ,        17,     1,      356,    "R/W",  0,      1,      0ull,   0},
55931         {"RPCNT1"                      ,        18,     1,      356,    "R/W",  0,      1,      0ull,   0},
55932         {"RESERVED_19_20"              ,        19,     2,      356,    "RAZ",  0,      1,      0ull,   0},
55933         {"RPTIME0"                     ,        21,     1,      356,    "R/W",  0,      1,      0ull,   0},
55934         {"RPTIME1"                     ,        22,     1,      356,    "R/W",  0,      1,      0ull,   0},
55935         {"RESERVED_23_24"              ,        23,     2,      356,    "RAZ",  0,      1,      0ull,   0},
55936         {"RDCNT0"                      ,        25,     1,      356,    "R/W",  0,      1,      0ull,   0},
55937         {"RDCNT1"                      ,        26,     1,      356,    "R/W",  0,      1,      0ull,   0},
55938         {"RDTIME0"                     ,        27,     1,      356,    "R/W",  0,      1,      0ull,   0},
55939         {"RDTIME1"                     ,        28,     1,      356,    "R/W",  0,      1,      0ull,   0},
55940         {"DMA0_FI"                     ,        29,     1,      356,    "R/W",  0,      1,      0ull,   0},
55941         {"DMA1_FI"                     ,        30,     1,      356,    "R/W",  0,      1,      0ull,   0},
55942         {"WIN_WR"                      ,        31,     1,      356,    "R/W",  0,      1,      0ull,   0},
55943         {"ILL_WR"                      ,        32,     1,      356,    "R/W",  0,      1,      0ull,   0},
55944         {"ILL_RD"                      ,        33,     1,      356,    "R/W",  0,      1,      0ull,   0},
55945         {"RESERVED_34_63"              ,        34,     30,     356,    "RAZ",  1,      1,      0,      0},
55946         {"TR_WABT"                     ,        0,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55947         {"MR_WABT"                     ,        1,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55948         {"MR_WTTO"                     ,        2,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55949         {"TR_ABT"                      ,        3,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55950         {"MR_ABT"                      ,        4,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55951         {"MR_TTO"                      ,        5,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55952         {"MSI_PER"                     ,        6,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55953         {"MSI_TABT"                    ,        7,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55954         {"MSI_MABT"                    ,        8,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55955         {"MSC_MSG"                     ,        9,      1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55956         {"TSR_ABT"                     ,        10,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55957         {"SERR"                        ,        11,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55958         {"APERR"                       ,        12,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55959         {"DPERR"                       ,        13,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55960         {"ILL_RWR"                     ,        14,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55961         {"ILL_RRD"                     ,        15,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55962         {"RSL_INT"                     ,        16,     1,      357,    "RO",   0,      0,      0ull,   0ull},
55963         {"PCNT0"                       ,        17,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55964         {"PCNT1"                       ,        18,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55965         {"RESERVED_19_20"              ,        19,     2,      357,    "RAZ",  0,      0,      0ull,   0ull},
55966         {"PTIME0"                      ,        21,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55967         {"PTIME1"                      ,        22,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55968         {"RESERVED_23_24"              ,        23,     2,      357,    "RAZ",  0,      0,      0ull,   0ull},
55969         {"DCNT0"                       ,        25,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55970         {"DCNT1"                       ,        26,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55971         {"DTIME0"                      ,        27,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55972         {"DTIME1"                      ,        28,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55973         {"DMA0_FI"                     ,        29,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55974         {"DMA1_FI"                     ,        30,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55975         {"WIN_WR"                      ,        31,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55976         {"ILL_WR"                      ,        32,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55977         {"ILL_RD"                      ,        33,     1,      357,    "R/W1C",        0,      0,      0ull,   0ull},
55978         {"RESERVED_34_63"              ,        34,     30,     357,    "RAZ",  1,      1,      0,      0},
55979         {"TR_WABT"                     ,        0,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55980         {"MR_WABT"                     ,        1,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55981         {"MR_WTTO"                     ,        2,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55982         {"TR_ABT"                      ,        3,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55983         {"MR_ABT"                      ,        4,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55984         {"MR_TTO"                      ,        5,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55985         {"MSI_PER"                     ,        6,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55986         {"MSI_TABT"                    ,        7,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55987         {"MSI_MABT"                    ,        8,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55988         {"MSC_MSG"                     ,        9,      1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55989         {"TSR_ABT"                     ,        10,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55990         {"SERR"                        ,        11,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55991         {"APERR"                       ,        12,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55992         {"DPERR"                       ,        13,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55993         {"ILL_RWR"                     ,        14,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55994         {"ILL_RRD"                     ,        15,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55995         {"RSL_INT"                     ,        16,     1,      358,    "RO",   0,      0,      0ull,   0ull},
55996         {"PCNT0"                       ,        17,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55997         {"PCNT1"                       ,        18,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
55998         {"RESERVED_19_20"              ,        19,     2,      358,    "RAZ",  0,      0,      0ull,   0ull},
55999         {"PTIME0"                      ,        21,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56000         {"PTIME1"                      ,        22,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56001         {"RESERVED_23_24"              ,        23,     2,      358,    "RAZ",  0,      0,      0ull,   0ull},
56002         {"DCNT0"                       ,        25,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56003         {"DCNT1"                       ,        26,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56004         {"DTIME0"                      ,        27,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56005         {"DTIME1"                      ,        28,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56006         {"DMA0_FI"                     ,        29,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56007         {"DMA1_FI"                     ,        30,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56008         {"WIN_WR"                      ,        31,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56009         {"ILL_WR"                      ,        32,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56010         {"ILL_RD"                      ,        33,     1,      358,    "R/W1C",        0,      0,      0ull,   0ull},
56011         {"RESERVED_34_63"              ,        34,     30,     358,    "RAZ",  1,      1,      0,      0},
56012         {"INTR"                        ,        0,      6,      359,    "WO",   0,      1,      0ull,   0},
56013         {"RESERVED_6_31"               ,        6,      26,     359,    "R/W",  1,      1,      0,      0},
56014         {"PTR_CNT"                     ,        0,      16,     360,    "R/W",  0,      1,      0ull,   0},
56015         {"PKT_CNT"                     ,        16,     16,     360,    "R/W",  0,      1,      0ull,   0},
56016         {"PKT_CNT"                     ,        0,      32,     361,    "RO",   0,      0,      0ull,   0ull},
56017         {"PKT_CNT"                     ,        0,      32,     362,    "R/W",  0,      1,      0ull,   0},
56018         {"PKT_TIME"                    ,        0,      32,     363,    "R/W",  0,      1,      0ull,   0},
56019         {"PREFETCH"                    ,        0,      3,      364,    "R/W",  0,      0,      0ull,   2ull},
56020         {"MIN_DATA"                    ,        3,      6,      364,    "R/W",  0,      0,      0ull,   4ull},
56021         {"RESERVED_9_31"               ,        9,      23,     364,    "RAZ",  1,      1,      0,      0},
56022         {"PREFETCH"                    ,        0,      3,      365,    "R/W",  0,      0,      0ull,   3ull},
56023         {"MIN_DATA"                    ,        3,      6,      365,    "R/W",  0,      0,      0ull,   6ull},
56024         {"RESERVED_9_31"               ,        9,      23,     365,    "RAZ",  1,      1,      0,      0},
56025         {"PREFETCH"                    ,        0,      3,      366,    "R/W",  0,      0,      0ull,   3ull},
56026         {"MIN_DATA"                    ,        3,      6,      366,    "R/W",  0,      0,      0ull,   6ull},
56027         {"RESERVED_9_31"               ,        9,      23,     366,    "RAZ",  1,      1,      0,      0},
56028         {"CNT"                         ,        0,      31,     367,    "R/W",  0,      0,      10000ull,       10000ull},
56029         {"ENB"                         ,        31,     1,      367,    "R/W",  0,      0,      0ull,   1ull},
56030         {"RESERVED_32_63"              ,        32,     32,     367,    "RAZ",  1,      1,      0,      0},
56031         {"SCM"                         ,        0,      32,     368,    "RO",   0,      1,      0ull,   0},
56032         {"RESERVED_32_63"              ,        32,     32,     368,    "RAZ",  1,      1,      0,      0},
56033         {"TSR"                         ,        0,      36,     369,    "RO",   0,      1,      0ull,   0},
56034         {"RESERVED_36_63"              ,        36,     28,     369,    "RAZ",  1,      1,      0,      0},
56035         {"RESERVED_0_1"                ,        0,      2,      370,    "RAZ",  1,      1,      0,      0},
56036         {"RD_ADDR"                     ,        2,      46,     370,    "R/W",  0,      1,      0ull,   0},
56037         {"IOBIT"                       ,        48,     1,      370,    "RAZ",  0,      0,      0ull,   0ull},
56038         {"RESERVED_49_63"              ,        49,     15,     370,    "RAZ",  1,      1,      0,      0},
56039         {"RD_DATA"                     ,        0,      64,     371,    "RO",   0,      1,      0ull,   0},
56040         {"RESERVED_0_2"                ,        0,      3,      372,    "RAZ",  1,      1,      0,      0},
56041         {"WR_ADDR"                     ,        3,      45,     372,    "R/W",  0,      1,      0ull,   0},
56042         {"IOBIT"                       ,        48,     1,      372,    "RAZ",  0,      0,      0ull,   0ull},
56043         {"RESERVED_49_63"              ,        49,     15,     372,    "RAZ",  1,      1,      0,      0},
56044         {"WR_DATA"                     ,        0,      64,     373,    "R/W",  0,      1,      0ull,   0},
56045         {"WR_MASK"                     ,        0,      8,      374,    "R/W",  0,      0,      0ull,   0ull},
56046         {"RESERVED_8_63"               ,        8,      56,     374,    "RAZ",  1,      1,      0,      0},
56047         {"THRESH"                      ,        0,      4,      375,    "R/W",  0,      0,      0ull,   8ull},
56048         {"FETCHSIZ"                    ,        4,      4,      375,    "R/W",  0,      0,      0ull,   7ull},
56049         {"TXRD"                        ,        8,      10,     375,    "R/W",  0,      0,      0ull,   1ull},
56050         {"USELDT"                      ,        18,     1,      375,    "R/W",  0,      0,      0ull,   0ull},
56051         {"RESERVED_19_19"              ,        19,     1,      375,    "RAZ",  1,      1,      0,      0},
56052         {"RXST"                        ,        20,     10,     375,    "R/W",  0,      0,      0ull,   1ull},
56053         {"RESERVED_30_31"              ,        30,     2,      375,    "RAZ",  1,      1,      0,      0},
56054         {"TXSLOTS"                     ,        32,     10,     375,    "R/W",  0,      1,      0ull,   0},
56055         {"RESERVED_42_43"              ,        42,     2,      375,    "RAZ",  1,      1,      0,      0},
56056         {"RXSLOTS"                     ,        44,     10,     375,    "R/W",  0,      1,      0ull,   0},
56057         {"RESERVED_54_62"              ,        54,     9,      375,    "RAZ",  1,      1,      0,      0},
56058         {"RDPEND"                      ,        63,     1,      375,    "RO",   0,      0,      0ull,   0ull},
56059         {"FSYNCMISSED"                 ,        0,      1,      376,    "R/W",  0,      0,      0ull,   1ull},
56060         {"FSYNCEXTRA"                  ,        1,      1,      376,    "R/W",  0,      0,      0ull,   1ull},
56061         {"RXWRAP"                      ,        2,      1,      376,    "R/W",  0,      0,      0ull,   1ull},
56062         {"RXST"                        ,        3,      1,      376,    "R/W",  0,      0,      0ull,   1ull},
56063         {"TXWRAP"                      ,        4,      1,      376,    "R/W",  0,      0,      0ull,   1ull},
56064         {"TXRD"                        ,        5,      1,      376,    "R/W",  0,      0,      0ull,   1ull},
56065         {"TXEMPTY"                     ,        6,      1,      376,    "R/W",  0,      0,      0ull,   1ull},
56066         {"RXOVF"                       ,        7,      1,      376,    "R/W",  0,      0,      0ull,   1ull},
56067         {"RESERVED_8_63"               ,        8,      56,     376,    "RAZ",  1,      1,      0,      0},
56068         {"FSYNCMISSED"                 ,        0,      1,      377,    "R/W1C",        0,      0,      0ull,   0ull},
56069         {"FSYNCEXTRA"                  ,        1,      1,      377,    "R/W1C",        0,      0,      0ull,   0ull},
56070         {"RXWRAP"                      ,        2,      1,      377,    "R/W1C",        0,      0,      0ull,   0ull},
56071         {"RXST"                        ,        3,      1,      377,    "R/W1C",        0,      0,      0ull,   0ull},
56072         {"TXWRAP"                      ,        4,      1,      377,    "R/W1C",        0,      0,      0ull,   0ull},
56073         {"TXRD"                        ,        5,      1,      377,    "R/W1C",        0,      0,      0ull,   0ull},
56074         {"TXEMPTY"                     ,        6,      1,      377,    "R/W1C",        0,      0,      0ull,   0ull},
56075         {"RXOVF"                       ,        7,      1,      377,    "R/W1C",        0,      0,      0ull,   0ull},
56076         {"RESERVED_8_63"               ,        8,      56,     377,    "RAZ",  1,      1,      0,      0},
56077         {"ADDR"                        ,        0,      36,     378,    "R/W",  1,      1,      0,      0},
56078         {"RESERVED_36_63"              ,        36,     28,     378,    "RAZ",  1,      1,      0,      0},
56079         {"CNT"                         ,        0,      16,     379,    "R/W",  1,      1,      0,      0},
56080         {"RESERVED_16_63"              ,        16,     48,     379,    "RAZ",  1,      1,      0,      0},
56081         {"MASK"                        ,        0,      64,     380,    "R/W",  1,      1,      0,      0},
56082         {"MASK"                        ,        0,      64,     381,    "R/W",  1,      1,      0,      0},
56083         {"MASK"                        ,        0,      64,     382,    "R/W",  1,      1,      0,      0},
56084         {"MASK"                        ,        0,      64,     383,    "R/W",  1,      1,      0,      0},
56085         {"MASK"                        ,        0,      64,     384,    "R/W",  1,      1,      0,      0},
56086         {"MASK"                        ,        0,      64,     385,    "R/W",  1,      1,      0,      0},
56087         {"MASK"                        ,        0,      64,     386,    "R/W",  1,      1,      0,      0},
56088         {"MASK"                        ,        0,      64,     387,    "R/W",  1,      1,      0,      0},
56089         {"RESERVED_0_2"                ,        0,      3,      388,    "RAZ",  1,      1,      0,      0},
56090         {"ADDR"                        ,        3,      33,     388,    "R/W",  1,      1,      0,      0},
56091         {"RESERVED_36_63"              ,        36,     28,     388,    "RAZ",  1,      1,      0,      0},
56092         {"ENABLE"                      ,        0,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
56093         {"USECLK1"                     ,        1,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
56094         {"LSBFIRST"                    ,        2,      1,      389,    "R/W",  0,      0,      0ull,   0ull},
56095         {"RESERVED_3_31"               ,        3,      29,     389,    "RAZ",  1,      1,      0,      0},
56096         {"SAMPPT"                      ,        32,     16,     389,    "R/W",  0,      1,      0ull,   0},
56097         {"DRVTIM"                      ,        48,     16,     389,    "R/W",  0,      1,      0ull,   0},
56098         {"DEBUGINFO"                   ,        0,      64,     390,    "RO",   1,      1,      0,      0},
56099         {"FRAM"                        ,        0,      3,      391,    "R/W",  1,      1,      0,      0},
56100         {"ADDR"                        ,        3,      33,     391,    "R/W",  1,      1,      0,      0},
56101         {"RESERVED_36_63"              ,        36,     28,     391,    "RAZ",  1,      1,      0,      0},
56102         {"CNT"                         ,        0,      16,     392,    "R/W",  1,      1,      0,      0},
56103         {"RESERVED_16_63"              ,        16,     48,     392,    "RAZ",  1,      1,      0,      0},
56104         {"MASK"                        ,        0,      64,     393,    "R/W",  1,      1,      0,      0},
56105         {"MASK"                        ,        0,      64,     394,    "R/W",  1,      1,      0,      0},
56106         {"MASK"                        ,        0,      64,     395,    "R/W",  1,      1,      0,      0},
56107         {"MASK"                        ,        0,      64,     396,    "R/W",  1,      1,      0,      0},
56108         {"MASK"                        ,        0,      64,     397,    "R/W",  1,      1,      0,      0},
56109         {"MASK"                        ,        0,      64,     398,    "R/W",  1,      1,      0,      0},
56110         {"MASK"                        ,        0,      64,     399,    "R/W",  1,      1,      0,      0},
56111         {"MASK"                        ,        0,      64,     400,    "R/W",  1,      1,      0,      0},
56112         {"RESERVED_0_2"                ,        0,      3,      401,    "RAZ",  1,      1,      0,      0},
56113         {"ADDR"                        ,        3,      33,     401,    "R/W",  1,      1,      0,      0},
56114         {"RESERVED_36_63"              ,        36,     28,     401,    "RAZ",  1,      1,      0,      0},
56115         {"ENA"                         ,        0,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
56116         {"FSYNCPOL"                    ,        1,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
56117         {"BCLKPOL"                     ,        2,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
56118         {"BITLEN"                      ,        3,      2,      402,    "R/W",  0,      0,      0ull,   0ull},
56119         {"EXTRABIT"                    ,        5,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
56120         {"NUMSLOTS"                    ,        6,      10,     402,    "R/W",  0,      1,      0ull,   0},
56121         {"FSYNCLOC"                    ,        16,     5,      402,    "R/W",  0,      0,      0ull,   0ull},
56122         {"FSYNCLEN"                    ,        21,     5,      402,    "R/W",  0,      0,      0ull,   2ull},
56123         {"RESERVED_26_31"              ,        26,     6,      402,    "RAZ",  1,      1,      0,      0},
56124         {"FSYNCSAMP"                   ,        32,     16,     402,    "R/W",  0,      1,      0ull,   0},
56125         {"RESERVED_48_62"              ,        48,     15,     402,    "RAZ",  1,      1,      0,      0},
56126         {"FSYNCGOOD"                   ,        63,     1,      402,    "RO",   0,      0,      0ull,   1ull},
56127         {"DEBUGINFO"                   ,        0,      64,     403,    "RO",   1,      1,      0,      0},
56128         {"N"                           ,        0,      32,     404,    "R/W",  0,      1,      0ull,   0},
56129         {"NUMSAMP"                     ,        32,     16,     404,    "R/W",  0,      1,      0ull,   0},
56130         {"DELTASAMP"                   ,        48,     16,     404,    "R/W",  0,      0,      0ull,   0ull},
56131         {"BIST"                        ,        0,      17,     405,    "RO",   0,      0,      0ull,   0ull},
56132         {"RESERVED_17_63"              ,        17,     47,     405,    "RAZ",  1,      1,      0,      0},
56133         {"DPRT"                        ,        0,      16,     406,    "R/W",  0,      0,      0ull,   0ull},
56134         {"UDP"                         ,        16,     1,      406,    "R/W",  0,      0,      0ull,   0ull},
56135         {"TCP"                         ,        17,     1,      406,    "R/W",  0,      0,      0ull,   0ull},
56136         {"RESERVED_18_63"              ,        18,     46,     406,    "RAZ",  1,      1,      0,      0},
56137         {"MINLEN"                      ,        0,      16,     407,    "R/W",  0,      0,      64ull,  64ull},
56138         {"MAXLEN"                      ,        16,     16,     407,    "R/W",  0,      0,      1536ull,        1536ull},
56139         {"RESERVED_32_63"              ,        32,     32,     407,    "RAZ",  1,      1,      0,      0},
56140         {"NIP_SHF"                     ,        0,      3,      408,    "R/W",  0,      0,      0ull,   0ull},
56141         {"RESERVED_3_7"                ,        3,      5,      408,    "RAZ",  1,      1,      0,      0},
56142         {"RAW_SHF"                     ,        8,      3,      408,    "R/W",  0,      0,      0ull,   0ull},
56143         {"RESERVED_11_15"              ,        11,     5,      408,    "RAZ",  1,      1,      0,      0},
56144         {"MAX_L2"                      ,        16,     1,      408,    "R/W",  0,      0,      0ull,   0ull},
56145         {"IP6_UDP"                     ,        17,     1,      408,    "R/W",  0,      0,      1ull,   1ull},
56146         {"TAG_SYN"                     ,        18,     1,      408,    "R/W",  0,      0,      0ull,   0ull},
56147         {"RESERVED_19_63"              ,        19,     45,     408,    "RAZ",  1,      1,      0,      0},
56148         {"IP_CHK"                      ,        0,      1,      409,    "R/W",  0,      0,      1ull,   1ull},
56149         {"IP_MAL"                      ,        1,      1,      409,    "R/W",  0,      0,      1ull,   1ull},
56150         {"IP_HOP"                      ,        2,      1,      409,    "R/W",  0,      0,      1ull,   1ull},
56151         {"IP4_OPTS"                    ,        3,      1,      409,    "R/W",  0,      0,      1ull,   1ull},
56152         {"IP6_EEXT"                    ,        4,      2,      409,    "R/W",  0,      0,      1ull,   3ull},
56153         {"RESERVED_6_7"                ,        6,      2,      409,    "RAZ",  0,      1,      0ull,   0},
56154         {"L4_MAL"                      ,        8,      1,      409,    "R/W",  0,      0,      1ull,   1ull},
56155         {"L4_PRT"                      ,        9,      1,      409,    "R/W",  0,      0,      1ull,   1ull},
56156         {"L4_CHK"                      ,        10,     1,      409,    "R/W",  0,      0,      1ull,   1ull},
56157         {"L4_LEN"                      ,        11,     1,      409,    "R/W",  0,      0,      1ull,   1ull},
56158         {"TCP_FLAG"                    ,        12,     1,      409,    "R/W",  0,      0,      1ull,   1ull},
56159         {"L2_MAL"                      ,        13,     1,      409,    "R/W",  0,      0,      1ull,   1ull},
56160         {"VS_QOS"                      ,        14,     1,      409,    "R/W",  0,      0,      0ull,   0ull},
56161         {"VS_WQE"                      ,        15,     1,      409,    "R/W",  0,      0,      0ull,   0ull},
56162         {"IGNRS"                       ,        16,     1,      409,    "R/W",  0,      0,      0ull,   0ull},
56163         {"RESERVED_17_63"              ,        17,     47,     409,    "RAZ",  0,      0,      0ull,   0ull},
56164         {"PKTDRP"                      ,        0,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
56165         {"RESERVED_1_1"                ,        1,      1,      410,    "RAZ",  1,      1,      0,      0},
56166         {"BCKPRS"                      ,        2,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
56167         {"PRTNXA"                      ,        3,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
56168         {"BADTAG"                      ,        4,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
56169         {"SKPRUNT"                     ,        5,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
56170         {"TODOOVR"                     ,        6,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
56171         {"FEPERR"                      ,        7,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
56172         {"BEPERR"                      ,        8,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
56173         {"MINERR"                      ,        9,      1,      410,    "R/W",  0,      0,      0ull,   0ull},
56174         {"MAXERR"                      ,        10,     1,      410,    "R/W",  0,      0,      0ull,   0ull},
56175         {"LENERR"                      ,        11,     1,      410,    "R/W",  0,      0,      0ull,   0ull},
56176         {"RESERVED_12_63"              ,        12,     52,     410,    "RAZ",  1,      1,      0,      0},
56177         {"PKTDRP"                      ,        0,      1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56178         {"RESERVED_1_1"                ,        1,      1,      411,    "RAZ",  1,      1,      0,      0},
56179         {"BCKPRS"                      ,        2,      1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56180         {"PRTNXA"                      ,        3,      1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56181         {"BADTAG"                      ,        4,      1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56182         {"SKPRUNT"                     ,        5,      1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56183         {"TODOOVR"                     ,        6,      1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56184         {"FEPERR"                      ,        7,      1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56185         {"BEPERR"                      ,        8,      1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56186         {"MINERR"                      ,        9,      1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56187         {"MAXERR"                      ,        10,     1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56188         {"LENERR"                      ,        11,     1,      411,    "R/W1C",        0,      0,      0ull,   0ull},
56189         {"RESERVED_12_63"              ,        12,     52,     411,    "RAZ",  1,      1,      0,      0},
56190         {"OFFSET"                      ,        0,      3,      412,    "R/W",  0,      0,      0ull,   0ull},
56191         {"RESERVED_3_63"               ,        3,      61,     412,    "RAZ",  1,      1,      0,      0},
56192         {"SKIP"                        ,        0,      7,      413,    "R/W",  0,      0,      0ull,   0ull},
56193         {"RESERVED_7_7"                ,        7,      1,      413,    "RAZ",  1,      1,      0,      0},
56194         {"MODE"                        ,        8,      2,      413,    "R/W",  0,      0,      0ull,   0ull},
56195         {"RESERVED_10_11"              ,        10,     2,      413,    "RAZ",  1,      1,      0,      0},
56196         {"CRC_EN"                      ,        12,     1,      413,    "RO",   0,      0,      0ull,   0ull},
56197         {"RESERVED_13_15"              ,        13,     3,      413,    "RAZ",  1,      1,      0,      0},
56198         {"QOS_VLAN"                    ,        16,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
56199         {"QOS_DIFF"                    ,        17,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
56200         {"QOS_VOD"                     ,        18,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
56201         {"RESERVED_19_19"              ,        19,     1,      413,    "RAZ",  1,      1,      0,      0},
56202         {"QOS_WAT"                     ,        20,     4,      413,    "R/W",  0,      0,      0ull,   0ull},
56203         {"QOS"                         ,        24,     3,      413,    "R/W",  0,      0,      0ull,   0ull},
56204         {"RESERVED_27_27"              ,        27,     1,      413,    "RAZ",  1,      1,      0,      0},
56205         {"GRP_WAT"                     ,        28,     4,      413,    "R/W",  0,      0,      0ull,   0ull},
56206         {"INST_HDR"                    ,        32,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
56207         {"DYN_RS"                      ,        33,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
56208         {"TAG_INC"                     ,        34,     2,      413,    "R/W",  0,      0,      0ull,   0ull},
56209         {"RAWDRP"                      ,        36,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
56210         {"RESERVED_37_39"              ,        37,     3,      413,    "RAZ",  1,      1,      0,      0},
56211         {"QOS_WAT_47"                  ,        40,     4,      413,    "R/W",  0,      0,      0ull,   0ull},
56212         {"GRP_WAT_47"                  ,        44,     4,      413,    "R/W",  0,      0,      0ull,   0ull},
56213         {"MINERR_EN"                   ,        48,     1,      413,    "R/W",  0,      0,      1ull,   1ull},
56214         {"MAXERR_EN"                   ,        49,     1,      413,    "R/W",  0,      0,      1ull,   1ull},
56215         {"LENERR_EN"                   ,        50,     1,      413,    "R/W",  0,      0,      1ull,   1ull},
56216         {"VLAN_LEN"                    ,        51,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
56217         {"PAD_LEN"                     ,        52,     1,      413,    "R/W",  0,      0,      0ull,   0ull},
56218         {"RESERVED_53_63"              ,        53,     11,     413,    "RAZ",  1,      1,      0,      0},
56219         {"GRP"                         ,        0,      4,      414,    "R/W",  0,      0,      0ull,   0ull},
56220         {"NON_TAG_TYPE"                ,        4,      2,      414,    "R/W",  0,      0,      0ull,   0ull},
56221         {"IP4_TAG_TYPE"                ,        6,      2,      414,    "R/W",  0,      0,      0ull,   0ull},
56222         {"IP6_TAG_TYPE"                ,        8,      2,      414,    "R/W",  0,      0,      0ull,   0ull},
56223         {"TCP4_TAG_TYPE"               ,        10,     2,      414,    "R/W",  0,      0,      0ull,   0ull},
56224         {"TCP6_TAG_TYPE"               ,        12,     2,      414,    "R/W",  0,      0,      0ull,   0ull},
56225         {"IP4_SRC_FLAG"                ,        14,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56226         {"IP6_SRC_FLAG"                ,        15,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56227         {"IP4_DST_FLAG"                ,        16,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56228         {"IP6_DST_FLAG"                ,        17,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56229         {"IP4_PCTL_FLAG"               ,        18,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56230         {"IP6_NXTH_FLAG"               ,        19,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56231         {"IP4_SPRT_FLAG"               ,        20,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56232         {"IP6_SPRT_FLAG"               ,        21,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56233         {"IP4_DPRT_FLAG"               ,        22,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56234         {"IP6_DPRT_FLAG"               ,        23,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56235         {"INC_PRT_FLAG"                ,        24,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56236         {"INC_VLAN"                    ,        25,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56237         {"INC_VS"                      ,        26,     2,      414,    "R/W",  0,      0,      0ull,   0ull},
56238         {"TAG_MODE"                    ,        28,     2,      414,    "R/W",  0,      0,      0ull,   0ull},
56239         {"GRPTAG_MSKIP"                ,        30,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56240         {"GRPTAG"                      ,        31,     1,      414,    "R/W",  0,      0,      0ull,   0ull},
56241         {"GRPTAGMASK"                  ,        32,     4,      414,    "R/W",  0,      0,      0ull,   0ull},
56242         {"GRPTAGBASE"                  ,        36,     4,      414,    "R/W",  0,      0,      0ull,   0ull},
56243         {"RESERVED_40_63"              ,        40,     24,     414,    "RAZ",  1,      1,      0,      0},
56244         {"QOS"                         ,        0,      3,      415,    "R/W",  0,      0,      0ull,   0ull},
56245         {"RESERVED_3_63"               ,        3,      61,     415,    "RAZ",  1,      1,      0,      0},
56246         {"QOS"                         ,        0,      3,      416,    "R/W",  0,      0,      0ull,   0ull},
56247         {"RESERVED_3_63"               ,        3,      61,     416,    "RAZ",  1,      1,      0,      0},
56248         {"MATCH_VALUE"                 ,        0,      16,     417,    "R/W",  0,      0,      0ull,   0ull},
56249         {"MATCH_TYPE"                  ,        16,     3,      417,    "R/W",  0,      0,      0ull,   0ull},
56250         {"RESERVED_19_19"              ,        19,     1,      417,    "RAZ",  1,      1,      0,      0},
56251         {"QOS"                         ,        20,     3,      417,    "R/W",  0,      0,      0ull,   0ull},
56252         {"RESERVED_23_23"              ,        23,     1,      417,    "RAZ",  1,      1,      0,      0},
56253         {"GRP"                         ,        24,     4,      417,    "R/W",  0,      0,      0ull,   0ull},
56254         {"RESERVED_28_31"              ,        28,     4,      417,    "RAZ",  1,      1,      0,      0},
56255         {"MASK"                        ,        32,     16,     417,    "R/W",  0,      0,      0ull,   0ull},
56256         {"RESERVED_48_63"              ,        48,     16,     417,    "RAZ",  1,      1,      0,      0},
56257         {"WORD"                        ,        0,      56,     418,    "R/W",  0,      0,      0ull,   0ull},
56258         {"RESERVED_56_63"              ,        56,     8,      418,    "RAZ",  1,      1,      0,      0},
56259         {"RST"                         ,        0,      1,      419,    "R/W",  0,      0,      0ull,   0ull},
56260         {"RESERVED_1_63"               ,        1,      63,     419,    "RAZ",  1,      1,      0,      0},
56261         {"DRP_OCTS"                    ,        0,      32,     420,    "R/W",  0,      1,      0ull,   0},
56262         {"DRP_PKTS"                    ,        32,     32,     420,    "R/W",  0,      1,      0ull,   0},
56263         {"OCTS"                        ,        0,      48,     421,    "R/W",  0,      1,      0ull,   0},
56264         {"RESERVED_48_63"              ,        48,     16,     421,    "RAZ",  1,      1,      0,      0},
56265         {"RAW"                         ,        0,      32,     422,    "R/W",  0,      1,      0ull,   0},
56266         {"PKTS"                        ,        32,     32,     422,    "R/W",  0,      1,      0ull,   0},
56267         {"MCST"                        ,        0,      32,     423,    "R/W",  0,      1,      0ull,   0},
56268         {"BCST"                        ,        32,     32,     423,    "R/W",  0,      1,      0ull,   0},
56269         {"H64"                         ,        0,      32,     424,    "R/W",  0,      1,      0ull,   0},
56270         {"H65TO127"                    ,        32,     32,     424,    "R/W",  0,      1,      0ull,   0},
56271         {"H128TO255"                   ,        0,      32,     425,    "R/W",  0,      1,      0ull,   0},
56272         {"H256TO511"                   ,        32,     32,     425,    "R/W",  0,      1,      0ull,   0},
56273         {"H512TO1023"                  ,        0,      32,     426,    "R/W",  0,      1,      0ull,   0},
56274         {"H1024TO1518"                 ,        32,     32,     426,    "R/W",  0,      1,      0ull,   0},
56275         {"H1519"                       ,        0,      32,     427,    "R/W",  0,      1,      0ull,   0},
56276         {"FCS"                         ,        32,     32,     427,    "R/W",  0,      1,      0ull,   0},
56277         {"UNDERSZ"                     ,        0,      32,     428,    "R/W",  0,      1,      0ull,   0},
56278         {"FRAG"                        ,        32,     32,     428,    "R/W",  0,      1,      0ull,   0},
56279         {"OVERSZ"                      ,        0,      32,     429,    "R/W",  0,      1,      0ull,   0},
56280         {"JABBER"                      ,        32,     32,     429,    "R/W",  0,      1,      0ull,   0},
56281         {"RDCLR"                       ,        0,      1,      430,    "R/W",  0,      0,      1ull,   1ull},
56282         {"RESERVED_1_63"               ,        1,      63,     430,    "RAZ",  1,      1,      0,      0},
56283         {"ERRS"                        ,        0,      16,     431,    "R/W",  0,      1,      0ull,   0},
56284         {"RESERVED_16_63"              ,        16,     48,     431,    "RAZ",  1,      1,      0,      0},
56285         {"OCTS"                        ,        0,      48,     432,    "R/W",  0,      1,      0ull,   0},
56286         {"RESERVED_48_63"              ,        48,     16,     432,    "RAZ",  1,      1,      0,      0},
56287         {"PKTS"                        ,        0,      32,     433,    "R/W",  0,      1,      0ull,   0},
56288         {"RESERVED_32_63"              ,        32,     32,     433,    "RAZ",  1,      1,      0,      0},
56289         {"EN"                          ,        0,      8,      434,    "R/W",  0,      0,      0ull,   0ull},
56290         {"RESERVED_8_63"               ,        8,      56,     434,    "RAZ",  1,      1,      0,      0},
56291         {"MASK"                        ,        0,      16,     435,    "R/W",  0,      0,      0ull,   0ull},
56292         {"RESERVED_16_63"              ,        16,     48,     435,    "RAZ",  1,      1,      0,      0},
56293         {"SRC"                         ,        0,      16,     436,    "R/W",  0,      0,      0ull,   0ull},
56294         {"DST"                         ,        16,     16,     436,    "R/W",  0,      0,      0ull,   0ull},
56295         {"RESERVED_32_63"              ,        32,     32,     436,    "RAZ",  1,      1,      0,      0},
56296         {"ENTRY"                       ,        0,      62,     437,    "RO",   1,      1,      0,      0},
56297         {"RESERVED_62_62"              ,        62,     1,      437,    "RAZ",  1,      1,      0,      0},
56298         {"VAL"                         ,        63,     1,      437,    "RO",   1,      1,      0,      0},
56299         {"COUNT"                       ,        0,      32,     438,    "R/W1C",        1,      0,      0,      0ull},
56300         {"RESERVED_32_63"              ,        32,     32,     438,    "RAZ",  1,      1,      0,      0},
56301         {"COUNT"                       ,        0,      48,     439,    "R/W1C",        1,      0,      0,      0ull},
56302         {"RESERVED_48_63"              ,        48,     16,     439,    "RAZ",  1,      1,      0,      0},
56303         {"SIZE"                        ,        0,      16,     440,    "RO",   1,      0,      0,      0ull},
56304         {"SEGS"                        ,        16,     6,      440,    "RO",   1,      0,      0,      0ull},
56305         {"CMD"                         ,        22,     14,     440,    "RO",   1,      0,      0,      0ull},
56306         {"FAU"                         ,        36,     28,     440,    "RO",   1,      0,      0,      0ull},
56307         {"PTR"                         ,        0,      40,     441,    "RO",   1,      0,      0,      0ull},
56308         {"SIZE"                        ,        40,     16,     441,    "RO",   1,      0,      0,      0ull},
56309         {"POOL"                        ,        56,     3,      441,    "RO",   1,      0,      0,      0ull},
56310         {"BACK"                        ,        59,     4,      441,    "RO",   1,      0,      0,      0ull},
56311         {"I"                           ,        63,     1,      441,    "RO",   1,      0,      0,      0ull},
56312         {"PTRS2"                       ,        0,      17,     442,    "RO",   1,      0,      0,      0ull},
56313         {"RESERVED_17_31"              ,        17,     15,     442,    "RAZ",  1,      0,      0,      0ull},
56314         {"PTRS1"                       ,        32,     17,     442,    "RO",   1,      0,      0,      0ull},
56315         {"RESERVED_49_63"              ,        49,     15,     442,    "RAZ",  1,      0,      0,      0ull},
56316         {"MOD"                         ,        0,      3,      443,    "RO",   1,      0,      0,      0ull},
56317         {"CNT"                         ,        3,      13,     443,    "RO",   1,      0,      0,      0ull},
56318         {"CHK"                         ,        16,     1,      443,    "RO",   1,      0,      0,      0ull},
56319         {"LEN"                         ,        17,     1,      443,    "RO",   1,      0,      0,      0ull},
56320         {"SOP"                         ,        18,     1,      443,    "RO",   1,      0,      0,      0ull},
56321         {"UID"                         ,        19,     3,      443,    "RO",   1,      0,      0,      0ull},
56322         {"MAJ"                         ,        22,     1,      443,    "RO",   1,      0,      0,      0ull},
56323         {"RESERVED_23_63"              ,        23,     41,     443,    "RAZ",  1,      0,      0,      0ull},
56324         {"SIZE"                        ,        0,      16,     444,    "RO",   1,      0,      0,      0ull},
56325         {"SEGS"                        ,        16,     6,      444,    "RO",   1,      0,      0,      0ull},
56326         {"CMD"                         ,        22,     14,     444,    "RO",   1,      0,      0,      0ull},
56327         {"FAU"                         ,        36,     28,     444,    "RO",   1,      0,      0,      0ull},
56328         {"PTR"                         ,        0,      40,     445,    "RO",   1,      0,      0,      0ull},
56329         {"SIZE"                        ,        40,     16,     445,    "RO",   1,      0,      0,      0ull},
56330         {"POOL"                        ,        56,     3,      445,    "RO",   1,      0,      0,      0ull},
56331         {"BACK"                        ,        59,     4,      445,    "RO",   1,      0,      0,      0ull},
56332         {"I"                           ,        63,     1,      445,    "RO",   1,      0,      0,      0ull},
56333         {"PTR"                         ,        0,      40,     446,    "RO",   1,      0,      0,      0ull},
56334         {"SIZE"                        ,        40,     16,     446,    "RO",   1,      0,      0,      0ull},
56335         {"POOL"                        ,        56,     3,      446,    "RO",   1,      0,      0,      0ull},
56336         {"BACK"                        ,        59,     4,      446,    "RO",   1,      0,      0,      0ull},
56337         {"I"                           ,        63,     1,      446,    "RO",   1,      0,      0,      0ull},
56338         {"DATA"                        ,        0,      64,     447,    "RO",   1,      0,      0,      0ull},
56339         {"MAJOR"                       ,        0,      3,      448,    "RO",   1,      0,      0,      0ull},
56340         {"MINOR"                       ,        3,      2,      448,    "RO",   1,      0,      0,      0ull},
56341         {"WAIT"                        ,        5,      1,      448,    "RO",   1,      0,      0,      0ull},
56342         {"QID_BASE"                    ,        6,      8,      448,    "RO",   1,      0,      0,      0ull},
56343         {"QID_OFF"                     ,        14,     4,      448,    "RO",   1,      0,      0,      0ull},
56344         {"QID_OFF_MAX"                 ,        18,     4,      448,    "RO",   1,      0,      0,      0ull},
56345         {"QCB_RIDX"                    ,        22,     5,      448,    "RO",   1,      0,      0,      0ull},
56346         {"QOS"                         ,        27,     3,      448,    "RO",   1,      0,      0,      0ull},
56347         {"STATIC_P"                    ,        30,     1,      448,    "RO",   1,      0,      0,      0ull},
56348         {"ACTIVE"                      ,        31,     1,      448,    "RO",   1,      0,      0,      0ull},
56349         {"CHK_MODE"                    ,        32,     1,      448,    "RO",   1,      0,      0,      0ull},
56350         {"CHK_ONCE"                    ,        33,     1,      448,    "RO",   1,      0,      0,      0ull},
56351         {"INIT_DWRITE"                 ,        34,     1,      448,    "RO",   1,      0,      0,      0ull},
56352         {"DREAD_SOP"                   ,        35,     1,      448,    "RO",   1,      0,      0,      0ull},
56353         {"UID"                         ,        36,     3,      448,    "RO",   1,      0,      0,      0ull},
56354         {"CMND_OFF"                    ,        39,     6,      448,    "RO",   1,      0,      0,      0ull},
56355         {"CMND_SIZ"                    ,        45,     16,     448,    "RO",   1,      0,      0,      0ull},
56356         {"CMND_SEGS"                   ,        61,     3,      448,    "RO",   1,      0,      0,      0ull},
56357         {"CMND_SEGS"                   ,        0,      3,      449,    "RO",   1,      0,      0,      0ull},
56358         {"CURR_OFF"                    ,        3,      16,     449,    "RO",   1,      0,      0,      0ull},
56359         {"CURR_SIZ"                    ,        19,     16,     449,    "RO",   1,      0,      0,      0ull},
56360         {"CURR_PTR"                    ,        35,     29,     449,    "RO",   1,      0,      0,      0ull},
56361         {"CURR_PTR"                    ,        0,      11,     450,    "RO",   1,      0,      0,      0ull},
56362         {"RESERVED_11_63"              ,        11,     53,     450,    "RAZ",  1,      0,      0,      0ull},
56363         {"QCB_RIDX"                    ,        0,      6,      451,    "RO",   1,      0,      0,      0ull},
56364         {"QCB_WIDX"                    ,        6,      6,      451,    "RO",   1,      0,      0,      0ull},
56365         {"BUF_PTR"                     ,        12,     33,     451,    "RO",   1,      0,      0,      0ull},
56366         {"BUF_SIZ"                     ,        45,     13,     451,    "RO",   1,      0,      0,      0ull},
56367         {"TAIL"                        ,        58,     1,      451,    "RO",   1,      0,      0,      0ull},
56368         {"QOS"                         ,        59,     5,      451,    "RO",   1,      0,      0,      0ull},
56369         {"QOS"                         ,        0,      3,      452,    "RO",   1,      0,      0,      0ull},
56370         {"STATIC_Q"                    ,        3,      1,      452,    "RO",   1,      0,      0,      0ull},
56371         {"S_TAIL"                      ,        4,      1,      452,    "RO",   1,      0,      0,      0ull},
56372         {"STATIC_P"                    ,        5,      1,      452,    "RO",   1,      0,      0,      0ull},
56373         {"RESERVED_6_7"                ,        6,      2,      452,    "RAZ",  1,      0,      0,      0ull},
56374         {"DOORBELL"                    ,        8,      20,     452,    "RO",   1,      0,      0,      0ull},
56375         {"RESERVED_28_63"              ,        28,     36,     452,    "RAZ",  1,      0,      0,      0ull},
56376         {"PTRS3"                       ,        0,      17,     453,    "RO",   1,      0,      0,      0ull},
56377         {"RESERVED_17_31"              ,        17,     15,     453,    "RAZ",  1,      0,      0,      0ull},
56378         {"PTRS0"                       ,        32,     17,     453,    "RO",   1,      0,      0,      0ull},
56379         {"RESERVED_49_63"              ,        49,     15,     453,    "RAZ",  1,      0,      0,      0ull},
56380         {"QUEUE"                       ,        0,      7,      454,    "R/W",  1,      0,      0,      0ull},
56381         {"PORT"                        ,        7,      6,      454,    "WR0",  1,      0,      0,      0ull},
56382         {"INDEX"                       ,        13,     3,      454,    "WR0",  1,      0,      0,      0ull},
56383         {"TAIL"                        ,        16,     1,      454,    "R/W",  1,      0,      0,      0ull},
56384         {"BUF_PTR"                     ,        17,     36,     454,    "R/W",  1,      0,      0,      0ull},
56385         {"QOS_MASK"                    ,        53,     8,      454,    "R/W",  1,      0,      0,      0ull},
56386         {"STATIC_Q"                    ,        61,     1,      454,    "R/W",  1,      0,      0,      0ull},
56387         {"STATIC_P"                    ,        62,     1,      454,    "R/W",  1,      0,      0,      0ull},
56388         {"S_TAIL"                      ,        63,     1,      454,    "R/W",  1,      0,      0,      0ull},
56389         {"QID"                         ,        0,      7,      455,    "R/W",  1,      0,      0,      0ull},
56390         {"PID"                         ,        7,      6,      455,    "WR0",  1,      0,      0,      0ull},
56391         {"RESERVED_13_52"              ,        13,     40,     455,    "RAZ",  1,      0,      0,      0ull},
56392         {"QOS_MASK"                    ,        53,     8,      455,    "R/W",  1,      0,      0,      0ull},
56393         {"RESERVED_61_63"              ,        61,     3,      455,    "RAZ",  1,      0,      0,      0ull},
56394         {"DAT_PTR"                     ,        0,      4,      456,    "RO",   1,      0,      0,      0ull},
56395         {"DAT_DAT"                     ,        4,      4,      456,    "RO",   1,      0,      0,      0ull},
56396         {"PRT_QSB"                     ,        8,      3,      456,    "RO",   1,      0,      0,      0ull},
56397         {"PRT_QCB"                     ,        11,     2,      456,    "RO",   1,      0,      0,      0ull},
56398         {"NCB_INB"                     ,        13,     2,      456,    "RO",   1,      0,      0,      0ull},
56399         {"PRT_PSB"                     ,        15,     6,      456,    "RO",   1,      0,      0,      0ull},
56400         {"PRT_NXT"                     ,        21,     1,      456,    "RO",   1,      0,      0,      0ull},
56401         {"PRT_CHK"                     ,        22,     3,      456,    "RO",   1,      0,      0,      0ull},
56402         {"OUT_WIF"                     ,        25,     1,      456,    "RO",   1,      0,      0,      0ull},
56403         {"OUT_STA"                     ,        26,     1,      456,    "RO",   1,      0,      0,      0ull},
56404         {"OUT_CTL"                     ,        27,     3,      456,    "RO",   1,      0,      0,      0ull},
56405         {"OUT_CRC"                     ,        30,     1,      456,    "RO",   1,      0,      0,      0ull},
56406         {"IOB"                         ,        31,     1,      456,    "RO",   1,      0,      0,      0ull},
56407         {"CSR"                         ,        32,     1,      456,    "RO",   1,      0,      0,      0ull},
56408         {"RESERVED_33_63"              ,        33,     31,     456,    "RAZ",  1,      0,      0,      0ull},
56409         {"SIZE"                        ,        0,      13,     457,    "R/W",  0,      0,      0ull,   0ull},
56410         {"RESERVED_13_19"              ,        13,     7,      457,    "RAZ",  0,      0,      0ull,   0ull},
56411         {"POOL"                        ,        20,     3,      457,    "R/W",  0,      0,      0ull,   0ull},
56412         {"RESERVED_23_63"              ,        23,     41,     457,    "RAZ",  1,      0,      0,      0ull},
56413         {"ASSERTS"                     ,        0,      64,     458,    "RO",   0,      0,      0ull,   0ull},
56414         {"ASSERTS"                     ,        0,      64,     459,    "RO",   0,      0,      0ull,   0ull},
56415         {"ASSERTS"                     ,        0,      64,     460,    "RO",   0,      0,      0ull,   0ull},
56416         {"ASSERTS"                     ,        0,      64,     461,    "RO",   0,      0,      0ull,   0ull},
56417         {"PARITY"                      ,        0,      1,      462,    "R/W1C",        0,      0,      0ull,   0ull},
56418         {"DOORBELL"                    ,        1,      1,      462,    "R/W1C",        0,      0,      0ull,   0ull},
56419         {"CURRZERO"                    ,        2,      1,      462,    "R/W1C",        0,      0,      0ull,   0ull},
56420         {"RESERVED_3_63"               ,        3,      61,     462,    "RAZ",  1,      0,      0,      0ull},
56421         {"ENA_PKO"                     ,        0,      1,      463,    "R/W",  0,      0,      0ull,   0ull},
56422         {"ENA_DWB"                     ,        1,      1,      463,    "R/W",  0,      0,      0ull,   0ull},
56423         {"STORE_BE"                    ,        2,      1,      463,    "R/W",  0,      0,      0ull,   0ull},
56424         {"RESET"                       ,        3,      1,      463,    "RAZ",  0,      0,      0ull,   0ull},
56425         {"RESERVED_4_63"               ,        4,      60,     463,    "RAZ",  1,      0,      0,      0ull},
56426         {"MODE0"                       ,        0,      3,      464,    "R/W",  0,      0,      0ull,   0ull},
56427         {"MODE1"                       ,        3,      3,      464,    "R/W",  0,      0,      0ull,   0ull},
56428         {"RESERVED_6_63"               ,        6,      58,     464,    "RAZ",  1,      0,      0,      0ull},
56429         {"PARITY"                      ,        0,      1,      465,    "R/W",  0,      0,      0ull,   0ull},
56430         {"DOORBELL"                    ,        1,      1,      465,    "R/W",  0,      0,      0ull,   0ull},
56431         {"CURRZERO"                    ,        2,      1,      465,    "R/W",  0,      0,      0ull,   0ull},
56432         {"RESERVED_3_63"               ,        3,      61,     465,    "RAZ",  1,      0,      0,      0ull},
56433         {"MODE"                        ,        0,      2,      466,    "R/W",  0,      0,      0ull,   0ull},
56434         {"RESERVED_2_63"               ,        2,      62,     466,    "RAZ",  1,      0,      0,      0ull},
56435         {"QID7"                        ,        0,      1,      467,    "R/W",  0,      0,      0ull,   0ull},
56436         {"IDX3"                        ,        1,      1,      467,    "R/W",  0,      0,      0ull,   0ull},
56437         {"RESERVED_2_63"               ,        2,      62,     467,    "RAZ",  1,      0,      0,      0ull},
56438         {"INDEX"                       ,        0,      8,      468,    "R/W",  0,      0,      0ull,   0ull},
56439         {"INC"                         ,        8,      8,      468,    "R/W",  0,      0,      0ull,   0ull},
56440         {"RESERVED_16_63"              ,        16,     48,     468,    "RAZ",  1,      0,      0,      0ull},
56441         {"ADR"                         ,        0,      1,      469,    "RO",   0,      0,      0ull,   0ull},
56442         {"PEND"                        ,        1,      1,      469,    "RO",   0,      0,      0ull,   0ull},
56443         {"NBR0"                        ,        2,      1,      469,    "RO",   0,      0,      0ull,   0ull},
56444         {"NBR1"                        ,        3,      1,      469,    "RO",   0,      0,      0ull,   0ull},
56445         {"FIDX"                        ,        4,      1,      469,    "RO",   0,      0,      0ull,   0ull},
56446         {"INDEX"                       ,        5,      1,      469,    "RO",   0,      0,      0ull,   0ull},
56447         {"NBT0"                        ,        6,      1,      469,    "RO",   0,      0,      0ull,   0ull},
56448         {"NBT1"                        ,        7,      1,      469,    "RO",   0,      0,      0ull,   0ull},
56449         {"CAM"                         ,        8,      1,      469,    "RO",   0,      0,      0ull,   0ull},
56450         {"RESERVED_9_15"               ,        9,      7,      469,    "RAZ",  1,      1,      0,      0},
56451         {"PP"                          ,        16,     2,      469,    "RO",   0,      0,      0ull,   0ull},
56452         {"RESERVED_18_63"              ,        18,     46,     469,    "RAZ",  1,      1,      0,      0},
56453         {"DS_PC"                       ,        0,      32,     470,    "R/W1C",        0,      1,      0ull,   0},
56454         {"RESERVED_32_63"              ,        32,     32,     470,    "RAZ",  1,      1,      0,      0},
56455         {"SBE"                         ,        0,      1,      471,    "R/W1C",        0,      0,      0ull,   0ull},
56456         {"DBE"                         ,        1,      1,      471,    "R/W1C",        0,      0,      0ull,   0ull},
56457         {"SBE_IE"                      ,        2,      1,      471,    "R/W",  0,      1,      0ull,   0},
56458         {"DBE_IE"                      ,        3,      1,      471,    "R/W",  0,      1,      0ull,   0},
56459         {"SYN"                         ,        4,      5,      471,    "RO",   1,      1,      0,      0},
56460         {"RESERVED_9_11"               ,        9,      3,      471,    "RAZ",  1,      1,      0,      0},
56461         {"RPE"                         ,        12,     1,      471,    "R/W1C",        0,      0,      0ull,   0ull},
56462         {"RPE_IE"                      ,        13,     1,      471,    "R/W",  0,      1,      0ull,   0},
56463         {"RESERVED_14_15"              ,        14,     2,      471,    "RAZ",  1,      1,      0,      0},
56464         {"IOP"                         ,        16,     13,     471,    "R/W1C",        0,      0,      0ull,   0ull},
56465         {"RESERVED_29_31"              ,        29,     3,      471,    "RAZ",  1,      1,      0,      0},
56466         {"IOP_IE"                      ,        32,     13,     471,    "R/W",  0,      1,      0ull,   0},
56467         {"RESERVED_45_63"              ,        45,     19,     471,    "RAZ",  1,      1,      0,      0},
56468         {"NBR_THR"                     ,        0,      5,      472,    "R/W",  0,      0,      2ull,   2ull},
56469         {"PFR_DIS"                     ,        5,      1,      472,    "R/W",  0,      0,      0ull,   0ull},
56470         {"RESERVED_6_63"               ,        6,      58,     472,    "RAZ",  1,      1,      0,      0},
56471         {"IQ_CNT"                      ,        0,      32,     473,    "RO",   0,      1,      0ull,   0},
56472         {"RESERVED_32_63"              ,        32,     32,     473,    "RAZ",  1,      1,      0,      0},
56473         {"IQ_CNT"                      ,        0,      32,     474,    "RO",   0,      1,      0ull,   0},
56474         {"RESERVED_32_63"              ,        32,     32,     474,    "RAZ",  1,      1,      0,      0},
56475         {"NOS_CNT"                     ,        0,      9,      475,    "RO",   0,      1,      0ull,   0},
56476         {"RESERVED_9_63"               ,        9,      55,     475,    "RAZ",  1,      1,      0,      0},
56477         {"NW_TIM"                      ,        0,      10,     476,    "R/W",  0,      0,      0ull,   1023ull},
56478         {"RESERVED_10_63"              ,        10,     54,     476,    "RAZ",  1,      1,      0,      0},
56479         {"RST_MSK"                     ,        0,      8,      477,    "R/W",  0,      1,      0ull,   0},
56480         {"RESERVED_8_63"               ,        8,      56,     477,    "RAZ",  1,      1,      0,      0},
56481         {"GRP_MSK"                     ,        0,      16,     478,    "R/W",  0,      0,      65535ull,       65535ull},
56482         {"QOS0_PRI"                    ,        16,     4,      478,    "R/W",  0,      1,      0ull,   0},
56483         {"QOS1_PRI"                    ,        20,     4,      478,    "R/W",  0,      1,      0ull,   0},
56484         {"QOS2_PRI"                    ,        24,     4,      478,    "R/W",  0,      1,      0ull,   0},
56485         {"QOS3_PRI"                    ,        28,     4,      478,    "R/W",  0,      1,      0ull,   0},
56486         {"QOS4_PRI"                    ,        32,     4,      478,    "R/W",  0,      1,      0ull,   0},
56487         {"QOS5_PRI"                    ,        36,     4,      478,    "R/W",  0,      1,      0ull,   0},
56488         {"QOS6_PRI"                    ,        40,     4,      478,    "R/W",  0,      1,      0ull,   0},
56489         {"QOS7_PRI"                    ,        44,     4,      478,    "R/W",  0,      1,      0ull,   0},
56490         {"RESERVED_48_63"              ,        48,     16,     478,    "RAZ",  1,      1,      0,      0},
56491         {"RND"                         ,        0,      8,      479,    "R/W",  0,      1,      255ull, 0},
56492         {"RND_P1"                      ,        8,      8,      479,    "R/W",  0,      1,      255ull, 0},
56493         {"RND_P2"                      ,        16,     8,      479,    "R/W",  0,      1,      255ull, 0},
56494         {"RND_P3"                      ,        24,     8,      479,    "R/W",  0,      1,      255ull, 0},
56495         {"RESERVED_32_63"              ,        32,     32,     479,    "RAZ",  1,      1,      0,      0},
56496         {"MIN_THR"                     ,        0,      8,      480,    "R/W",  0,      1,      0ull,   0},
56497         {"RESERVED_8_11"               ,        8,      4,      480,    "RAZ",  1,      1,      0,      0},
56498         {"MAX_THR"                     ,        12,     8,      480,    "R/W",  0,      1,      255ull, 0},
56499         {"RESERVED_20_23"              ,        20,     4,      480,    "RAZ",  1,      1,      0,      0},
56500         {"FREE_CNT"                    ,        24,     9,      480,    "RO",   0,      1,      249ull, 0},
56501         {"RESERVED_33_35"              ,        33,     3,      480,    "RAZ",  1,      1,      0,      0},
56502         {"BUF_CNT"                     ,        36,     9,      480,    "RO",   0,      1,      0ull,   0},
56503         {"RESERVED_45_47"              ,        45,     3,      480,    "RAZ",  1,      1,      0,      0},
56504         {"DES_CNT"                     ,        48,     9,      480,    "RO",   0,      1,      0ull,   0},
56505         {"RESERVED_57_63"              ,        57,     7,      480,    "RAZ",  1,      1,      0,      0},
56506         {"TS_PC"                       ,        0,      32,     481,    "R/W1C",        0,      1,      0ull,   0},
56507         {"RESERVED_32_63"              ,        32,     32,     481,    "RAZ",  1,      1,      0,      0},
56508         {"WA_PC"                       ,        0,      32,     482,    "R/W1C",        0,      1,      0ull,   0},
56509         {"RESERVED_32_63"              ,        32,     32,     482,    "RAZ",  1,      1,      0,      0},
56510         {"WA_PC"                       ,        0,      32,     483,    "R/W1C",        0,      1,      0ull,   0},
56511         {"RESERVED_32_63"              ,        32,     32,     483,    "RAZ",  1,      1,      0,      0},
56512         {"WQ_INT"                      ,        0,      16,     484,    "R/W1C",        0,      1,      0ull,   0},
56513         {"IQ_DIS"                      ,        16,     16,     484,    "R/W1", 0,      1,      0ull,   0},
56514         {"RESERVED_32_63"              ,        32,     32,     484,    "RAZ",  1,      1,      0,      0},
56515         {"IQ_CNT"                      ,        0,      9,      485,    "RO",   0,      1,      0ull,   0},
56516         {"RESERVED_9_11"               ,        9,      3,      485,    "RAZ",  1,      1,      0,      0},
56517         {"DS_CNT"                      ,        12,     9,      485,    "RO",   0,      1,      0ull,   0},
56518         {"RESERVED_21_23"              ,        21,     3,      485,    "RAZ",  1,      1,      0,      0},
56519         {"TC_CNT"                      ,        24,     4,      485,    "RO",   0,      1,      0ull,   0},
56520         {"RESERVED_28_63"              ,        28,     36,     485,    "RAZ",  1,      1,      0,      0},
56521         {"RESERVED_0_7"                ,        0,      8,      486,    "RAZ",  1,      1,      0,      0},
56522         {"PC_THR"                      ,        8,      20,     486,    "R/W",  0,      1,      0ull,   0},
56523         {"RESERVED_28_31"              ,        28,     4,      486,    "RAZ",  1,      1,      0,      0},
56524         {"PC"                          ,        32,     28,     486,    "RO",   0,      1,      0ull,   0},
56525         {"RESERVED_60_63"              ,        60,     4,      486,    "RAZ",  1,      1,      0,      0},
56526         {"IQ_THR"                      ,        0,      8,      487,    "R/W",  0,      1,      0ull,   0},
56527         {"RESERVED_8_11"               ,        8,      4,      487,    "RAZ",  1,      1,      0,      0},
56528         {"DS_THR"                      ,        12,     8,      487,    "R/W",  0,      1,      0ull,   0},
56529         {"RESERVED_20_23"              ,        20,     4,      487,    "RAZ",  1,      1,      0,      0},
56530         {"TC_THR"                      ,        24,     4,      487,    "R/W",  0,      1,      0ull,   0},
56531         {"TC_EN"                       ,        28,     1,      487,    "R/W",  0,      1,      0ull,   0},
56532         {"RESERVED_29_63"              ,        29,     35,     487,    "RAZ",  1,      1,      0,      0},
56533         {"WS_PC"                       ,        0,      32,     488,    "R/W1C",        0,      1,      0ull,   0},
56534         {"RESERVED_32_63"              ,        32,     32,     488,    "RAZ",  1,      1,      0,      0},
56535         {"MEM"                         ,        0,      1,      489,    "RO",   0,      0,      0ull,   0ull},
56536         {"RRC"                         ,        1,      1,      489,    "RO",   0,      0,      0ull,   0ull},
56537         {"RESERVED_2_63"               ,        2,      62,     489,    "RAZ",  1,      1,      0,      0},
56538         {"ENT_EN"                      ,        0,      1,      490,    "R/W",  0,      0,      0ull,   0ull},
56539         {"RNG_EN"                      ,        1,      1,      490,    "R/W",  0,      0,      0ull,   0ull},
56540         {"RNM_RST"                     ,        2,      1,      490,    "R/W",  0,      0,      0ull,   0ull},
56541         {"RNG_RST"                     ,        3,      1,      490,    "R/W",  0,      0,      0ull,   0ull},
56542         {"EXP_ENT"                     ,        4,      1,      490,    "R/W",  0,      0,      0ull,   0ull},
56543         {"ENT_SEL"                     ,        5,      4,      490,    "R/W",  0,      0,      0ull,   0ull},
56544         {"RESERVED_9_63"               ,        9,      55,     490,    "RAZ",  1,      1,      0,      0},
56545         {"PHASE"                       ,        0,      8,      491,    "R/W",  0,      0,      100ull, 100ull},
56546         {"SAMPLE"                      ,        8,      4,      491,    "R/W",  0,      0,      2ull,   2ull},
56547         {"PREAMBLE"                    ,        12,     1,      491,    "R/W",  0,      0,      1ull,   1ull},
56548         {"CLK_IDLE"                    ,        13,     1,      491,    "R/W",  0,      0,      0ull,   0ull},
56549         {"RESERVED_14_14"              ,        14,     1,      491,    "RAZ",  1,      1,      0,      0},
56550         {"SAMPLE_MODE"                 ,        15,     1,      491,    "RAZ",  0,      0,      0ull,   0ull},
56551         {"SAMPLE_HI"                   ,        16,     5,      491,    "R/W",  0,      0,      0ull,   0ull},
56552         {"RESERVED_21_23"              ,        21,     3,      491,    "RAZ",  1,      1,      0,      0},
56553         {"MODE"                        ,        24,     1,      491,    "R/W",  0,      0,      0ull,   0ull},
56554         {"RESERVED_25_63"              ,        25,     39,     491,    "RAZ",  1,      1,      0,      0},
56555         {"REG_ADR"                     ,        0,      5,      492,    "R/W",  0,      1,      0ull,   0},
56556         {"RESERVED_5_7"                ,        5,      3,      492,    "RAZ",  1,      1,      0,      0},
56557         {"PHY_ADR"                     ,        8,      5,      492,    "R/W",  0,      1,      0ull,   0},
56558         {"RESERVED_13_15"              ,        13,     3,      492,    "RAZ",  1,      1,      0,      0},
56559         {"PHY_OP"                      ,        16,     2,      492,    "R/W",  0,      1,      0ull,   0},
56560         {"RESERVED_18_63"              ,        18,     46,     492,    "RAZ",  1,      1,      0,      0},
56561         {"EN"                          ,        0,      1,      493,    "R/W",  0,      0,      0ull,   1ull},
56562         {"RESERVED_1_63"               ,        1,      63,     493,    "RAZ",  1,      1,      0,      0},
56563         {"DAT"                         ,        0,      16,     494,    "RO",   0,      1,      0ull,   0},
56564         {"VAL"                         ,        16,     1,      494,    "RO",   0,      1,      0ull,   0},
56565         {"PENDING"                     ,        17,     1,      494,    "RO",   0,      1,      0ull,   0},
56566         {"RESERVED_18_63"              ,        18,     46,     494,    "RAZ",  1,      1,      0,      0},
56567         {"DAT"                         ,        0,      16,     495,    "R/W",  0,      1,      0ull,   0},
56568         {"VAL"                         ,        16,     1,      495,    "RO",   0,      1,      0ull,   0},
56569         {"PENDING"                     ,        17,     1,      495,    "RO",   0,      1,      0ull,   0},
56570         {"RESERVED_18_63"              ,        18,     46,     495,    "RAZ",  1,      1,      0,      0},
56571         {"INTERVAL"                    ,        0,      22,     496,    "RO",   1,      0,      0,      0ull},
56572         {"RESERVED_22_23"              ,        22,     2,      496,    "RAZ",  1,      0,      0,      0ull},
56573         {"COUNT"                       ,        24,     22,     496,    "RO",   1,      0,      0,      0ull},
56574         {"RESERVED_46_46"              ,        46,     1,      496,    "RAZ",  1,      0,      0,      0ull},
56575         {"ENA"                         ,        47,     1,      496,    "RO",   1,      0,      0,      0ull},
56576         {"RESERVED_48_63"              ,        48,     16,     496,    "RAZ",  1,      0,      0,      0ull},
56577         {"BSIZE"                       ,        0,      20,     497,    "RO",   1,      0,      0,      0ull},
56578         {"BASE"                        ,        20,     31,     497,    "RO",   1,      0,      0,      0ull},
56579         {"BUCKET"                      ,        51,     13,     497,    "RO",   1,      0,      0,      0ull},
56580         {"BUCKET"                      ,        0,      7,      498,    "RO",   1,      0,      0,      0ull},
56581         {"RESERVED_7_7"                ,        7,      1,      498,    "RAZ",  1,      0,      0,      0ull},
56582         {"CSIZE"                       ,        8,      13,     498,    "RO",   1,      0,      0,      0ull},
56583         {"CPOOL"                       ,        21,     3,      498,    "RO",   1,      0,      0,      0ull},
56584         {"RESERVED_24_63"              ,        24,     40,     498,    "RAZ",  1,      0,      0,      0ull},
56585         {"RING"                        ,        0,      4,      499,    "R/W",  0,      0,      0ull,   0ull},
56586         {"NUM_BUCKETS"                 ,        4,      20,     499,    "R/W",  0,      0,      0ull,   0ull},
56587         {"FIRST_BUCKET"                ,        24,     31,     499,    "R/W",  0,      0,      0ull,   0ull},
56588         {"RESERVED_55_63"              ,        55,     9,      499,    "RAZ",  1,      0,      0,      0ull},
56589         {"RING"                        ,        0,      4,      500,    "R/W",  0,      0,      0ull,   0ull},
56590         {"INTERVAL"                    ,        4,      22,     500,    "R/W",  0,      0,      0ull,   0ull},
56591         {"WORDS_PER_CHUNK"             ,        26,     13,     500,    "R/W",  0,      0,      0ull,   0ull},
56592         {"POOL"                        ,        39,     3,      500,    "R/W",  0,      0,      0ull,   0ull},
56593         {"ENABLE"                      ,        42,     1,      500,    "R/W",  0,      0,      0ull,   0ull},
56594         {"RESERVED_43_63"              ,        43,     21,     500,    "RAZ",  1,      0,      0,      0ull},
56595         {"CTL"                         ,        0,      1,      501,    "RO",   1,      0,      0,      0ull},
56596         {"NCB"                         ,        1,      1,      501,    "RO",   1,      0,      0,      0ull},
56597         {"STA"                         ,        2,      2,      501,    "RO",   1,      0,      0,      0ull},
56598         {"RESERVED_4_63"               ,        4,      60,     501,    "RAZ",  1,      0,      0,      0ull},
56599         {"MASK"                        ,        0,      16,     502,    "R/W1C",        0,      0,      0ull,   0ull},
56600         {"RESERVED_16_63"              ,        16,     48,     502,    "RAZ",  1,      0,      0,      0ull},
56601         {"ENABLE_TIMERS"               ,        0,      1,      503,    "R/W",  0,      0,      0ull,   0ull},
56602         {"ENABLE_DWB"                  ,        1,      1,      503,    "R/W",  0,      0,      0ull,   0ull},
56603         {"RESET"                       ,        2,      1,      503,    "RAZ",  0,      0,      0ull,   0ull},
56604         {"RESERVED_3_63"               ,        3,      61,     503,    "RAZ",  1,      0,      0,      0ull},
56605         {"MASK"                        ,        0,      16,     504,    "R/W",  0,      0,      0ull,   0ull},
56606         {"RESERVED_16_63"              ,        16,     48,     504,    "RAZ",  1,      0,      0,      0ull},
56607         {"INDEX"                       ,        0,      8,      505,    "R/W",  0,      0,      0ull,   0ull},
56608         {"INC"                         ,        8,      8,      505,    "R/W",  0,      0,      0ull,   0ull},
56609         {"RESERVED_16_63"              ,        16,     48,     505,    "RAZ",  1,      0,      0,      0ull},
56610         {"INEPINT"                     ,        0,      16,     506,    "RO",   0,      0,      0ull,   0ull},
56611         {"OUTEPINT"                    ,        16,     16,     506,    "RO",   0,      0,      0ull,   0ull},
56612         {"INEPMSK"                     ,        0,      16,     507,    "R/W",  0,      0,      0ull,   0ull},
56613         {"OUTEPMSK"                    ,        16,     16,     507,    "R/W",  0,      0,      0ull,   0ull},
56614         {"DEVSPD"                      ,        0,      2,      508,    "R/W",  0,      0,      0ull,   0ull},
56615         {"NZSTSOUTHSHK"                ,        2,      1,      508,    "R/W",  0,      0,      0ull,   0ull},
56616         {"RESERVED_3_3"                ,        3,      1,      508,    "RAZ",  1,      1,      0,      0},
56617         {"DEVADDR"                     ,        4,      7,      508,    "R/W",  0,      0,      0ull,   0ull},
56618         {"PERFRINT"                    ,        11,     2,      508,    "R/W",  0,      0,      0ull,   0ull},
56619         {"RESERVED_13_17"              ,        13,     5,      508,    "RAZ",  1,      1,      0,      0},
56620         {"EPMISCNT"                    ,        18,     5,      508,    "R/W",  0,      0,      8ull,   0ull},
56621         {"RESERVED_23_31"              ,        23,     9,      508,    "RAZ",  1,      1,      0,      0},
56622         {"RMTWKUPSIG"                  ,        0,      1,      509,    "R/W",  0,      0,      0ull,   0ull},
56623         {"SFTDISCON"                   ,        1,      1,      509,    "R/W",  0,      0,      0ull,   0ull},
56624         {"GNPINNAKSTS"                 ,        2,      1,      509,    "RO",   0,      0,      0ull,   0ull},
56625         {"GOUTNAKSTS"                  ,        3,      1,      509,    "RO",   0,      0,      0ull,   0ull},
56626         {"TSTCTL"                      ,        4,      3,      509,    "R/W",  0,      0,      0ull,   0ull},
56627         {"SGNPINNAK"                   ,        7,      1,      509,    "WO",   0,      0,      0ull,   0ull},
56628         {"CGNPINNAK"                   ,        8,      1,      509,    "WO",   0,      0,      0ull,   0ull},
56629         {"SGOUTNAK"                    ,        9,      1,      509,    "WO",   0,      0,      0ull,   0ull},
56630         {"CGOUTNAK"                    ,        10,     1,      509,    "WO",   0,      0,      0ull,   0ull},
56631         {"PWRONPRGDONE"                ,        11,     1,      509,    "R/W",  0,      0,      0ull,   0ull},
56632         {"RESERVED_12_31"              ,        12,     20,     509,    "RAZ",  1,      1,      0,      0},
56633         {"MPS"                         ,        0,      11,     510,    "R/W",  0,      0,      0ull,   0ull},
56634         {"NEXTEP"                      ,        11,     4,      510,    "R/W",  0,      0,      0ull,   0ull},
56635         {"USBACTEP"                    ,        15,     1,      510,    "R/W",  0,      0,      1ull,   0ull},
56636         {"DPID"                        ,        16,     1,      510,    "RO",   0,      0,      0ull,   0ull},
56637         {"NAKSTS"                      ,        17,     1,      510,    "RO",   0,      0,      0ull,   0ull},
56638         {"EPTYPE"                      ,        18,     2,      510,    "R/W",  0,      0,      0ull,   0ull},
56639         {"RESERVED_20_20"              ,        20,     1,      510,    "RAZ",  1,      1,      0,      0},
56640         {"STALL"                       ,        21,     1,      510,    "R/W",  0,      0,      0ull,   0ull},
56641         {"TXFNUM"                      ,        22,     4,      510,    "R/W",  0,      0,      0ull,   0ull},
56642         {"CNAK"                        ,        26,     1,      510,    "WO",   0,      0,      0ull,   0ull},
56643         {"SNAK"                        ,        27,     1,      510,    "WO",   0,      0,      0ull,   0ull},
56644         {"SETD0PID"                    ,        28,     1,      510,    "WO",   0,      0,      0ull,   0ull},
56645         {"SETD1PID"                    ,        29,     1,      510,    "WO",   0,      0,      0ull,   0ull},
56646         {"EPDIS"                       ,        30,     1,      510,    "R/W",  0,      0,      0ull,   0ull},
56647         {"EPENA"                       ,        31,     1,      510,    "R/W",  0,      0,      0ull,   0ull},
56648         {"XFERCOMPL"                   ,        0,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
56649         {"EPDISBLD"                    ,        1,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
56650         {"AHBERR"                      ,        2,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
56651         {"TIMEOUT"                     ,        3,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
56652         {"INTKNTXFEMP"                 ,        4,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
56653         {"INTKNEPMIS"                  ,        5,      1,      511,    "R/W1C",        0,      0,      0ull,   0ull},
56654         {"INEPNAKEFF"                  ,        6,      1,      511,    "RO",   0,      0,      0ull,   0ull},
56655         {"RESERVED_7_31"               ,        7,      25,     511,    "RAZ",  1,      1,      0,      0},
56656         {"XFERCOMPLMSK"                ,        0,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
56657         {"EPDISBLDMSK"                 ,        1,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
56658         {"AHBERRMSK"                   ,        2,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
56659         {"TIMEOUTMSK"                  ,        3,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
56660         {"INTKNTXFEMPMSK"              ,        4,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
56661         {"INTKNEPMISMSK"               ,        5,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
56662         {"INEPNAKEFFMSK"               ,        6,      1,      512,    "R/W",  0,      0,      0ull,   0ull},
56663         {"RESERVED_7_31"               ,        7,      25,     512,    "RAZ",  1,      1,      0,      0},
56664         {"XFERSIZE"                    ,        0,      19,     513,    "R/W",  0,      0,      0ull,   0ull},
56665         {"PKTCNT"                      ,        19,     10,     513,    "R/W",  0,      0,      0ull,   0ull},
56666         {"MC"                          ,        29,     2,      513,    "R/W",  0,      0,      0ull,   0ull},
56667         {"RESERVED_31_31"              ,        31,     1,      513,    "RAZ",  1,      1,      0,      0},
56668         {"MPS"                         ,        0,      11,     514,    "R/W",  0,      0,      0ull,   0ull},
56669         {"RESERVED_11_14"              ,        11,     4,      514,    "RAZ",  0,      0,      0ull,   0ull},
56670         {"USBACTEP"                    ,        15,     1,      514,    "R/W",  0,      0,      1ull,   0ull},
56671         {"DPID"                        ,        16,     1,      514,    "RO",   0,      0,      0ull,   0ull},
56672         {"NAKSTS"                      ,        17,     1,      514,    "RO",   0,      0,      0ull,   0ull},
56673         {"EPTYPE"                      ,        18,     2,      514,    "R/W",  0,      0,      0ull,   0ull},
56674         {"SNP"                         ,        20,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
56675         {"STALL"                       ,        21,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
56676         {"RESERVED_22_25"              ,        22,     4,      514,    "RAZ",  1,      1,      0,      0},
56677         {"CNAK"                        ,        26,     1,      514,    "WO",   0,      0,      0ull,   0ull},
56678         {"SNAK"                        ,        27,     1,      514,    "WO",   0,      0,      0ull,   0ull},
56679         {"SETD0PID"                    ,        28,     1,      514,    "WO",   0,      0,      0ull,   0ull},
56680         {"SETD1PID"                    ,        29,     1,      514,    "WO",   0,      0,      0ull,   0ull},
56681         {"EPDIS"                       ,        30,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
56682         {"EPENA"                       ,        31,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
56683         {"XFERCOMPL"                   ,        0,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
56684         {"EPDISBLD"                    ,        1,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
56685         {"AHBERR"                      ,        2,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
56686         {"SETUP"                       ,        3,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
56687         {"OUTTKNEPDIS"                 ,        4,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
56688         {"RESERVED_5_31"               ,        5,      27,     515,    "RAZ",  1,      1,      0,      0},
56689         {"XFERCOMPLMSK"                ,        0,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
56690         {"EPDISBLDMSK"                 ,        1,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
56691         {"AHBERRMSK"                   ,        2,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
56692         {"SETUPMSK"                    ,        3,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
56693         {"OUTTKNEPDISMSK"              ,        4,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
56694         {"RESERVED_5_31"               ,        5,      27,     516,    "RAZ",  1,      1,      0,      0},
56695         {"XFERSIZE"                    ,        0,      19,     517,    "R/W",  0,      0,      0ull,   0ull},
56696         {"PKTCNT"                      ,        19,     10,     517,    "R/W",  0,      0,      0ull,   0ull},
56697         {"MC"                          ,        29,     2,      517,    "R/W",  0,      0,      0ull,   0ull},
56698         {"RESERVED_31_31"              ,        31,     1,      517,    "RAZ",  1,      1,      0,      0},
56699         {"DPTXFSTADDR"                 ,        0,      16,     518,    "RO",   0,      0,      0ull,   0ull},
56700         {"DPTXFSIZE"                   ,        16,     16,     518,    "RO",   0,      0,      1896ull,        1896ull},
56701         {"SUSPSTS"                     ,        0,      1,      519,    "RO",   0,      0,      0ull,   0ull},
56702         {"ENUMSPD"                     ,        1,      2,      519,    "RO",   0,      0,      0ull,   0ull},
56703         {"ERRTICERR"                   ,        3,      1,      519,    "RO",   0,      0,      0ull,   0ull},
56704         {"RESERVED_4_7"                ,        4,      4,      519,    "RAZ",  1,      1,      0,      0},
56705         {"SOFFN"                       ,        8,      14,     519,    "RO",   0,      0,      0ull,   0ull},
56706         {"RESERVED_22_31"              ,        22,     10,     519,    "RAZ",  1,      1,      0,      0},
56707         {"INTKNWPTR"                   ,        0,      5,      520,    "RO",   0,      0,      0ull,   0ull},
56708         {"RESERVED_5_6"                ,        5,      2,      520,    "RAZ",  1,      1,      0,      0},
56709         {"WRAPBIT"                     ,        7,      1,      520,    "RO",   0,      0,      0ull,   0ull},
56710         {"EPTKN"                       ,        8,      24,     520,    "RO",   0,      0,      0ull,   0ull},
56711         {"EPTKN"                       ,        0,      32,     521,    "RO",   0,      0,      0ull,   0ull},
56712         {"EPTKN"                       ,        0,      32,     522,    "RO",   0,      0,      0ull,   0ull},
56713         {"EPTKN"                       ,        0,      32,     523,    "RO",   0,      0,      0ull,   0ull},
56714         {"GLBLINTRMSK"                 ,        0,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
56715         {"HBSTLEN"                     ,        1,      4,      524,    "R/W",  0,      0,      0ull,   0ull},
56716         {"DMAEN"                       ,        5,      1,      524,    "R/W",  0,      0,      0ull,   0ull},
56717         {"RESERVED_6_6"                ,        6,      1,      524,    "RAZ",  1,      1,      0,      0},
56718         {"NPTXFEMPLVL"                 ,        7,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
56719         {"PTXFEMPLVL"                  ,        8,      1,      524,    "R/W",  0,      0,      0ull,   1ull},
56720         {"RESERVED_9_31"               ,        9,      23,     524,    "RAZ",  1,      1,      0,      0},
56721         {"EPDIR"                       ,        0,      32,     525,    "RO",   0,      0,      0ull,   0ull},
56722         {"OTGMODE"                     ,        0,      3,      526,    "RO",   0,      0,      2ull,   2ull},
56723         {"OTGARCH"                     ,        3,      2,      526,    "RO",   0,      0,      1ull,   1ull},
56724         {"SINGPNT"                     ,        5,      1,      526,    "RO",   0,      0,      0ull,   0ull},
56725         {"HSPHYTYPE"                   ,        6,      2,      526,    "RO",   0,      0,      1ull,   1ull},
56726         {"FSPHYTYPE"                   ,        8,      2,      526,    "RO",   0,      0,      0ull,   0ull},
56727         {"NUMDEVEPS"                   ,        10,     4,      526,    "RO",   0,      0,      4ull,   4ull},
56728         {"NUMHSTCHNL"                  ,        14,     4,      526,    "RO",   0,      0,      7ull,   7ull},
56729         {"PERIOSUPPORT"                ,        18,     1,      526,    "RO",   0,      0,      1ull,   1ull},
56730         {"DYNFIFOSIZING"               ,        19,     1,      526,    "RO",   0,      0,      1ull,   1ull},
56731         {"RESERVED_20_21"              ,        20,     2,      526,    "RAZ",  1,      1,      0,      0},
56732         {"NPTXQDEPTH"                  ,        22,     2,      526,    "RO",   0,      0,      2ull,   2ull},
56733         {"PTXQDEPTH"                   ,        24,     2,      526,    "RO",   0,      0,      2ull,   2ull},
56734         {"TKNQDEPTH"                   ,        26,     5,      526,    "RO",   0,      0,      30ull,  30ull},
56735         {"RESERVED_31_31"              ,        31,     1,      526,    "RAZ",  1,      1,      0,      0},
56736         {"XFERSIZEWIDTH"               ,        0,      4,      527,    "RO",   0,      0,      8ull,   8ull},
56737         {"PKTSIZEWIDTH"                ,        4,      3,      527,    "RO",   0,      0,      6ull,   6ull},
56738         {"OTGEN"                       ,        7,      1,      527,    "RO",   0,      0,      1ull,   1ull},
56739         {"I2C_SELECTION"               ,        8,      1,      527,    "RO",   0,      0,      0ull,   0ull},
56740         {"VENDOR_CONTROL_INTERFACE_SUPPORT",    9,      1,      527,    "RO",   0,      0,      0ull,   0ull},
56741         {"OPTFEATURE"                  ,        10,     1,      527,    "RO",   0,      0,      1ull,   1ull},
56742         {"RSTTYPE"                     ,        11,     1,      527,    "RO",   0,      0,      1ull,   1ull},
56743         {"AHBPHYSYNC"                  ,        12,     1,      527,    "RO",   0,      0,      0ull,   0ull},
56744         {"RESERVED_13_15"              ,        13,     3,      527,    "RAZ",  1,      1,      0,      0},
56745         {"DFIFODEPTH"                  ,        16,     16,     527,    "RO",   0,      0,      1824ull,        1824ull},
56746         {"NUMDEVPERIOEPS"              ,        0,      4,      528,    "RO",   0,      0,      4ull,   4ull},
56747         {"ENABLEPWROPT"                ,        4,      1,      528,    "RO",   0,      0,      0ull,   0ull},
56748         {"AHBFREQ"                     ,        5,      1,      528,    "RO",   0,      0,      1ull,   1ull},
56749         {"RESERVED_6_13"               ,        6,      8,      528,    "RAZ",  1,      1,      0,      0},
56750         {"PHYDATAWIDTH"                ,        14,     2,      528,    "RO",   0,      0,      1ull,   1ull},
56751         {"NUMCTLEPS"                   ,        16,     4,      528,    "RO",   0,      0,      4ull,   4ull},
56752         {"IDDGFLTR"                    ,        20,     1,      528,    "RO",   0,      0,      1ull,   1ull},
56753         {"VBUSVALIDFLTR"               ,        21,     1,      528,    "RO",   0,      0,      1ull,   1ull},
56754         {"AVALIDFLTR"                  ,        22,     1,      528,    "RO",   0,      0,      0ull,   0ull},
56755         {"BVALIDFLTR"                  ,        23,     1,      528,    "RO",   0,      0,      0ull,   0ull},
56756         {"SESSENDFLTR"                 ,        24,     1,      528,    "RO",   0,      0,      0ull,   0ull},
56757         {"ENDEDTRFIFO"                 ,        25,     1,      528,    "RO",   0,      0,      0ull,   0ull},
56758         {"NUMDEVMODINEND"              ,        26,     4,      528,    "RO",   0,      0,      2ull,   2ull},
56759         {"RESERVED_30_31"              ,        30,     2,      528,    "RAZ",  1,      1,      0,      0},
56760         {"RESERVED_0_0"                ,        0,      1,      529,    "RAZ",  1,      1,      0,      0},
56761         {"MODEMISMSK"                  ,        1,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
56762         {"OTGINTMSK"                   ,        2,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
56763         {"SOFMSK"                      ,        3,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
56764         {"RXFLVLMSK"                   ,        4,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
56765         {"NPTXFEMPMSK"                 ,        5,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
56766         {"GINNAKEFFMSK"                ,        6,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
56767         {"GOUTNAKEFFMSK"               ,        7,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
56768         {"ULPICKINTMSK"                ,        8,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
56769         {"I2CINT"                      ,        9,      1,      529,    "R/W",  0,      0,      0ull,   0ull},
56770         {"ERLYSUSPMSK"                 ,        10,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56771         {"USBSUSPMSK"                  ,        11,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56772         {"USBRSTMSK"                   ,        12,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56773         {"ENUMDONEMSK"                 ,        13,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56774         {"ISOOUTDROPMSK"               ,        14,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56775         {"EOPFMSK"                     ,        15,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56776         {"RESERVED_16_16"              ,        16,     1,      529,    "RAZ",  1,      1,      0,      0},
56777         {"EPMISMSK"                    ,        17,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56778         {"INEPINTMSK"                  ,        18,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56779         {"OEPINTMSK"                   ,        19,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56780         {"INCOMPISOINMSK"              ,        20,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56781         {"INCOMPLPMSK"                 ,        21,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56782         {"FETSUSPMSK"                  ,        22,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56783         {"RESERVED_23_23"              ,        23,     1,      529,    "RAZ",  1,      1,      0,      0},
56784         {"PRTINTMSK"                   ,        24,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56785         {"HCHINTMSK"                   ,        25,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56786         {"PTXFEMPMSK"                  ,        26,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56787         {"RESERVED_27_27"              ,        27,     1,      529,    "RAZ",  1,      1,      0,      0},
56788         {"CONIDSTSCHNGMSK"             ,        28,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56789         {"DISCONNINTMSK"               ,        29,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56790         {"SESSREQINTMSK"               ,        30,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56791         {"WKUPINTMSK"                  ,        31,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
56792         {"CURMOD"                      ,        0,      1,      530,    "RO",   0,      0,      0ull,   0ull},
56793         {"MODEMIS"                     ,        1,      1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56794         {"OTGINT"                      ,        2,      1,      530,    "RO",   0,      0,      0ull,   0ull},
56795         {"SOF"                         ,        3,      1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56796         {"RXFLVL"                      ,        4,      1,      530,    "RO",   0,      0,      0ull,   0ull},
56797         {"NPTXFEMP"                    ,        5,      1,      530,    "RO",   0,      0,      0ull,   0ull},
56798         {"GINNAKEFF"                   ,        6,      1,      530,    "RO",   0,      0,      0ull,   0ull},
56799         {"GOUTNAKEFF"                  ,        7,      1,      530,    "RO",   0,      0,      0ull,   0ull},
56800         {"ULPICKINT"                   ,        8,      1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56801         {"I2CINT"                      ,        9,      1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56802         {"ERLYSUSP"                    ,        10,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56803         {"USBSUSP"                     ,        11,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56804         {"USBRST"                      ,        12,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56805         {"ENUMDONE"                    ,        13,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56806         {"ISOOUTDROP"                  ,        14,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56807         {"EOPF"                        ,        15,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56808         {"RESERVED_16_16"              ,        16,     1,      530,    "RAZ",  1,      1,      0,      0},
56809         {"EPMIS"                       ,        17,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56810         {"IEPINT"                      ,        18,     1,      530,    "RO",   0,      0,      0ull,   0ull},
56811         {"OEPINT"                      ,        19,     1,      530,    "RO",   0,      0,      0ull,   0ull},
56812         {"INCOMPISOIN"                 ,        20,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56813         {"INCOMPLP"                    ,        21,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56814         {"FETSUSP"                     ,        22,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56815         {"RESERVED_23_23"              ,        23,     1,      530,    "RAZ",  1,      1,      0,      0},
56816         {"PRTINT"                      ,        24,     1,      530,    "RO",   0,      0,      0ull,   0ull},
56817         {"HCHINT"                      ,        25,     1,      530,    "RO",   0,      0,      0ull,   0ull},
56818         {"PTXFEMP"                     ,        26,     1,      530,    "RO",   0,      0,      0ull,   0ull},
56819         {"RESERVED_27_27"              ,        27,     1,      530,    "RAZ",  1,      1,      0,      0},
56820         {"CONIDSTSCHNG"                ,        28,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56821         {"DISCONNINT"                  ,        29,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56822         {"SESSREQINT"                  ,        30,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56823         {"WKUPINT"                     ,        31,     1,      530,    "R/W1C",        0,      0,      0ull,   0ull},
56824         {"NPTXFSTADDR"                 ,        0,      16,     531,    "R/W",  0,      0,      1824ull,        456ull},
56825         {"NPTXFDEP"                    ,        16,     16,     531,    "R/W",  0,      0,      1824ull,        912ull},
56826         {"NPTXFSPCAVAIL"               ,        0,      16,     532,    "RO",   0,      0,      0ull,   0ull},
56827         {"NPTXQSPCAVAIL"               ,        16,     8,      532,    "RO",   0,      0,      0ull,   0ull},
56828         {"NPTXQTOP"                    ,        24,     7,      532,    "RO",   0,      0,      0ull,   0ull},
56829         {"RESERVED_31_31"              ,        31,     1,      532,    "RAZ",  1,      1,      0,      0},
56830         {"SESREQSCS"                   ,        0,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
56831         {"SESREQ"                      ,        1,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
56832         {"RESERVED_2_7"                ,        2,      6,      533,    "RAZ",  1,      1,      0,      0},
56833         {"HSTNEGSCS"                   ,        8,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
56834         {"HNPREQ"                      ,        9,      1,      533,    "R/W",  0,      0,      0ull,   0ull},
56835         {"HSTSETHNPEN"                 ,        10,     1,      533,    "R/W",  0,      0,      0ull,   0ull},
56836         {"DEVHNPEN"                    ,        11,     1,      533,    "R/W",  0,      0,      0ull,   0ull},
56837         {"RESERVED_12_15"              ,        12,     4,      533,    "RAZ",  1,      1,      0,      0},
56838         {"CONIDSTS"                    ,        16,     1,      533,    "RO",   1,      1,      0,      0},
56839         {"DBNCTIME"                    ,        17,     1,      533,    "RO",   0,      0,      0ull,   0ull},
56840         {"ASESVLD"                     ,        18,     1,      533,    "RO",   1,      1,      0,      0},
56841         {"BSESVLD"                     ,        19,     1,      533,    "RO",   1,      1,      0,      0},
56842         {"RESERVED_20_31"              ,        20,     12,     533,    "RAZ",  1,      1,      0,      0},
56843         {"RESERVED_0_1"                ,        0,      2,      534,    "RAZ",  1,      1,      0,      0},
56844         {"SESENDDET"                   ,        2,      1,      534,    "R/W1C",        0,      0,      0ull,   0ull},
56845         {"RESERVED_3_7"                ,        3,      5,      534,    "RAZ",  1,      1,      0,      0},
56846         {"SESREQSUCSTSCHNG"            ,        8,      1,      534,    "R/W1C",        0,      0,      0ull,   0ull},
56847         {"HSTNEGSUCSTSCHNG"            ,        9,      1,      534,    "R/W1C",        0,      0,      0ull,   0ull},
56848         {"RESERVED_10_16"              ,        10,     7,      534,    "RAZ",  1,      1,      0,      0},
56849         {"HSTNEGDET"                   ,        17,     1,      534,    "R/W1C",        0,      0,      0ull,   0ull},
56850         {"ADEVTOUTCHG"                 ,        18,     1,      534,    "R/W1C",        0,      0,      0ull,   0ull},
56851         {"DBNCEDONE"                   ,        19,     1,      534,    "R/W1C",        0,      0,      0ull,   0ull},
56852         {"RESERVED_20_31"              ,        20,     12,     534,    "RAZ",  1,      1,      0,      0},
56853         {"CSFTRST"                     ,        0,      1,      535,    "R/W",  0,      0,      0ull,   0ull},
56854         {"HSFTRST"                     ,        1,      1,      535,    "R/W",  0,      0,      0ull,   0ull},
56855         {"FRMCNTRRST"                  ,        2,      1,      535,    "R/W",  0,      0,      0ull,   0ull},
56856         {"INTKNQFLSH"                  ,        3,      1,      535,    "R/W",  0,      0,      0ull,   0ull},
56857         {"RXFFLSH"                     ,        4,      1,      535,    "R/W",  0,      0,      0ull,   0ull},
56858         {"TXFFLSH"                     ,        5,      1,      535,    "R/W",  0,      0,      0ull,   0ull},
56859         {"TXFNUM"                      ,        6,      5,      535,    "R/W",  0,      0,      0ull,   0ull},
56860         {"RESERVED_11_29"              ,        11,     19,     535,    "RAZ",  1,      1,      0,      0},
56861         {"DMAREQ"                      ,        30,     1,      535,    "RO",   0,      0,      0ull,   0ull},
56862         {"AHBIDLE"                     ,        31,     1,      535,    "RO",   0,      0,      1ull,   1ull},
56863         {"RXFDEP"                      ,        0,      16,     536,    "R/W",  0,      0,      1824ull,        456ull},
56864         {"RESERVED_16_31"              ,        16,     16,     536,    "RAZ",  1,      1,      0,      0},
56865         {"EPNUM"                       ,        0,      4,      537,    "RO",   0,      0,      0ull,   0ull},
56866         {"BCNT"                        ,        4,      11,     537,    "RO",   0,      0,      0ull,   0ull},
56867         {"DPID"                        ,        15,     2,      537,    "RO",   0,      0,      0ull,   0ull},
56868         {"PKTSTS"                      ,        17,     4,      537,    "RO",   0,      0,      0ull,   0ull},
56869         {"FN"                          ,        21,     4,      537,    "RO",   0,      0,      0ull,   0ull},
56870         {"RESERVED_25_31"              ,        25,     7,      537,    "RAZ",  1,      1,      0,      0},
56871         {"CHNUM"                       ,        0,      4,      538,    "RO",   0,      0,      0ull,   0ull},
56872         {"BCNT"                        ,        4,      11,     538,    "RO",   0,      0,      0ull,   0ull},
56873         {"DPID"                        ,        15,     2,      538,    "RO",   0,      0,      0ull,   0ull},
56874         {"PKTSTS"                      ,        17,     4,      538,    "RO",   0,      0,      0ull,   0ull},
56875         {"RESERVED_21_31"              ,        21,     11,     538,    "RAZ",  1,      1,      0,      0},
56876         {"EPNUM"                       ,        0,      4,      539,    "RO",   0,      0,      0ull,   0ull},
56877         {"BCNT"                        ,        4,      11,     539,    "RO",   0,      0,      0ull,   0ull},
56878         {"DPID"                        ,        15,     2,      539,    "RO",   0,      0,      0ull,   0ull},
56879         {"PKTSTS"                      ,        17,     4,      539,    "RO",   0,      0,      0ull,   0ull},
56880         {"FN"                          ,        21,     4,      539,    "RO",   0,      0,      0ull,   0ull},
56881         {"RESERVED_25_31"              ,        25,     7,      539,    "RAZ",  1,      1,      0,      0},
56882         {"CHNUM"                       ,        0,      4,      540,    "RO",   0,      0,      0ull,   0ull},
56883         {"BCNT"                        ,        4,      11,     540,    "RO",   0,      0,      0ull,   0ull},
56884         {"DPID"                        ,        15,     2,      540,    "RO",   0,      0,      0ull,   0ull},
56885         {"PKTSTS"                      ,        17,     4,      540,    "RO",   0,      0,      0ull,   0ull},
56886         {"RESERVED_21_31"              ,        21,     11,     540,    "RAZ",  1,      1,      0,      0},
56887         {"SYNOPSYSID"                  ,        0,      32,     541,    "RO",   1,      1,      0,      0},
56888         {"TOUTCAL"                     ,        0,      3,      542,    "R/W",  0,      0,      0ull,   0ull},
56889         {"PHYIF"                       ,        3,      1,      542,    "RO",   0,      0,      1ull,   1ull},
56890         {"ULPI_UTMI_SEL"               ,        4,      1,      542,    "RO",   0,      0,      0ull,   0ull},
56891         {"FSINTF"                      ,        5,      1,      542,    "WO",   0,      0,      0ull,   0ull},
56892         {"PHYSEL"                      ,        6,      1,      542,    "WO",   0,      0,      0ull,   0ull},
56893         {"DDRSEL"                      ,        7,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
56894         {"SRPCAP"                      ,        8,      1,      542,    "RO",   0,      0,      0ull,   0ull},
56895         {"HNPCAP"                      ,        9,      1,      542,    "RO",   0,      0,      0ull,   0ull},
56896         {"USBTRDTIM"                   ,        10,     4,      542,    "R/W",  0,      0,      5ull,   5ull},
56897         {"RESERVED_14_14"              ,        14,     1,      542,    "RAZ",  1,      1,      0,      0},
56898         {"PHYLPWRCLKSEL"               ,        15,     1,      542,    "R/W",  0,      0,      0ull,   0ull},
56899         {"OTGI2CSEL"                   ,        16,     1,      542,    "RO",   0,      0,      0ull,   0ull},
56900         {"RESERVED_17_31"              ,        17,     15,     542,    "RAZ",  1,      1,      0,      0},
56901         {"HAINT"                       ,        0,      16,     543,    "RO",   0,      0,      0ull,   0ull},
56902         {"RESERVED_16_31"              ,        16,     16,     543,    "RAZ",  1,      1,      0,      0},
56903         {"HAINTMSK"                    ,        0,      16,     544,    "R/W",  0,      0,      0ull,   0ull},
56904         {"RESERVED_16_31"              ,        16,     16,     544,    "RAZ",  1,      1,      0,      0},
56905         {"MPS"                         ,        0,      11,     545,    "R/W",  0,      0,      0ull,   0ull},
56906         {"EPNUM"                       ,        11,     4,      545,    "R/W",  0,      0,      0ull,   0ull},
56907         {"EPDIR"                       ,        15,     1,      545,    "R/W",  0,      0,      0ull,   0ull},
56908         {"RESERVED_16_16"              ,        16,     1,      545,    "RAZ",  1,      1,      0,      0},
56909         {"LSPDDEV"                     ,        17,     1,      545,    "R/W",  0,      0,      0ull,   0ull},
56910         {"EPTYPE"                      ,        18,     2,      545,    "R/W",  0,      0,      0ull,   0ull},
56911         {"EC"                          ,        20,     2,      545,    "R/W",  0,      0,      0ull,   0ull},
56912         {"DEVADDR"                     ,        22,     7,      545,    "R/W",  0,      0,      0ull,   0ull},
56913         {"ODDFRM"                      ,        29,     1,      545,    "R/W",  0,      0,      0ull,   0ull},
56914         {"CHDIS"                       ,        30,     1,      545,    "R/W",  0,      0,      0ull,   0ull},
56915         {"CHENA"                       ,        31,     1,      545,    "R/W",  0,      0,      0ull,   0ull},
56916         {"FSLSPCLKSEL"                 ,        0,      2,      546,    "R/W",  0,      0,      0ull,   0ull},
56917         {"FSLSSUPP"                    ,        2,      1,      546,    "R/W",  0,      0,      0ull,   0ull},
56918         {"RESERVED_3_31"               ,        3,      29,     546,    "RAZ",  1,      1,      0,      0},
56919         {"XFERCOMPL"                   ,        0,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56920         {"CHHLTD"                      ,        1,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56921         {"AHBERR"                      ,        2,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56922         {"STALL"                       ,        3,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56923         {"NAK"                         ,        4,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56924         {"ACK"                         ,        5,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56925         {"NYET"                        ,        6,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56926         {"XACTERR"                     ,        7,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56927         {"BBLERR"                      ,        8,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56928         {"FRMOVRUN"                    ,        9,      1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56929         {"DATATGLERR"                  ,        10,     1,      547,    "R/W1C",        0,      0,      0ull,   0ull},
56930         {"RESERVED_11_31"              ,        11,     21,     547,    "RAZ",  1,      1,      0,      0},
56931         {"XFERCOMPLMSK"                ,        0,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56932         {"CHHLTDMSK"                   ,        1,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56933         {"AHBERRMSK"                   ,        2,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56934         {"STALLMSK"                    ,        3,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56935         {"NAKMSK"                      ,        4,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56936         {"ACKMSK"                      ,        5,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56937         {"NYETMSK"                     ,        6,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56938         {"XACTERRMSK"                  ,        7,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56939         {"BBLERRMSK"                   ,        8,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56940         {"FRMOVRUNMSK"                 ,        9,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
56941         {"DATATGLERRMSK"               ,        10,     1,      548,    "R/W",  0,      0,      0ull,   0ull},
56942         {"RESERVED_11_31"              ,        11,     21,     548,    "RAZ",  1,      1,      0,      0},
56943         {"PRTADDR"                     ,        0,      7,      549,    "R/W",  0,      0,      0ull,   0ull},
56944         {"HUBADDR"                     ,        7,      7,      549,    "R/W",  0,      0,      0ull,   0ull},
56945         {"XACTPOS"                     ,        14,     2,      549,    "R/W",  0,      0,      0ull,   0ull},
56946         {"COMPSPLT"                    ,        16,     1,      549,    "R/W",  0,      0,      0ull,   0ull},
56947         {"RESERVED_17_30"              ,        17,     14,     549,    "RAZ",  1,      1,      0,      0},
56948         {"SPLTENA"                     ,        31,     1,      549,    "R/W",  0,      0,      0ull,   0ull},
56949         {"XFERSIZE"                    ,        0,      19,     550,    "R/W",  0,      0,      0ull,   0ull},
56950         {"PKTCNT"                      ,        19,     10,     550,    "R/W",  0,      0,      0ull,   0ull},
56951         {"PID"                         ,        29,     2,      550,    "R/W",  0,      0,      0ull,   0ull},
56952         {"DOPNG"                       ,        31,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
56953         {"FRINT"                       ,        0,      16,     551,    "R/W",  0,      0,      2959ull,        3750ull},
56954         {"RESERVED_16_31"              ,        16,     16,     551,    "RAZ",  1,      1,      0,      0},
56955         {"FRNUM"                       ,        0,      16,     552,    "RO",   0,      0,      16383ull,       0ull},
56956         {"FRREM"                       ,        16,     16,     552,    "RO",   0,      0,      0ull,   0ull},
56957         {"PRTCONNSTS"                  ,        0,      1,      553,    "RO",   0,      0,      0ull,   0ull},
56958         {"PRTCONNDET"                  ,        1,      1,      553,    "R/W1C",        0,      0,      0ull,   0ull},
56959         {"PRTENA"                      ,        2,      1,      553,    "R/W1C",        0,      0,      0ull,   0ull},
56960         {"PRTENCHNG"                   ,        3,      1,      553,    "R/W1C",        0,      0,      0ull,   0ull},
56961         {"PRTOVRCURRACT"               ,        4,      1,      553,    "RO",   0,      0,      0ull,   0ull},
56962         {"PRTOVRCURRCHNG"              ,        5,      1,      553,    "R/W1C",        0,      0,      0ull,   0ull},
56963         {"PRTRES"                      ,        6,      1,      553,    "R/W",  0,      0,      0ull,   0ull},
56964         {"PRTSUSP"                     ,        7,      1,      553,    "R/W",  0,      0,      0ull,   0ull},
56965         {"PRTRST"                      ,        8,      1,      553,    "R/W",  0,      0,      0ull,   0ull},
56966         {"RESERVED_9_9"                ,        9,      1,      553,    "RAZ",  1,      1,      0,      0},
56967         {"PRTLNSTS"                    ,        10,     2,      553,    "RO",   0,      0,      0ull,   0ull},
56968         {"PRTPWR"                      ,        12,     1,      553,    "R/W",  0,      0,      0ull,   0ull},
56969         {"PRTTSTCTL"                   ,        13,     4,      553,    "R/W",  0,      0,      0ull,   0ull},
56970         {"PRTSPD"                      ,        17,     2,      553,    "RO",   0,      0,      0ull,   0ull},
56971         {"RESERVED_19_31"              ,        19,     13,     553,    "RAZ",  1,      1,      0,      0},
56972         {"PTXFSTADDR"                  ,        0,      16,     554,    "R/W",  0,      0,      3648ull,        912ull},
56973         {"PTXFSIZE"                    ,        16,     16,     554,    "R/W",  0,      0,      256ull, 456ull},
56974         {"PTXFSPCAVAIL"                ,        0,      16,     555,    "RO",   0,      0,      0ull,   0ull},
56975         {"PTXQSPCAVAIL"                ,        16,     8,      555,    "RO",   0,      0,      0ull,   0ull},
56976         {"PTXQTOP"                     ,        24,     8,      555,    "RO",   0,      0,      0ull,   0ull},
56977         {"DATA"                        ,        0,      32,     556,    "R/W",  0,      0,      0ull,   0ull},
56978         {"STOPPCLK"                    ,        0,      1,      557,    "R/W",  0,      0,      0ull,   0ull},
56979         {"GATEHCLK"                    ,        1,      1,      557,    "R/W",  0,      0,      0ull,   0ull},
56980         {"PWRCLMP"                     ,        2,      1,      557,    "R/W",  0,      0,      0ull,   0ull},
56981         {"RSTPDWNMODULE"               ,        3,      1,      557,    "R/W",  0,      0,      0ull,   0ull},
56982         {"PHYSUSPENDED"                ,        4,      1,      557,    "RO",   0,      0,      0ull,   0ull},
56983         {"RESERVED_5_31"               ,        5,      27,     557,    "RAZ",  1,      1,      0,      0},
56984         {"NOF_BIS"                     ,        0,      1,      558,    "RO",   0,      0,      0ull,   0ull},
56985         {"NIF_BIS"                     ,        1,      1,      558,    "RO",   0,      0,      0ull,   0ull},
56986         {"USBC_BIS"                    ,        2,      1,      558,    "RO",   0,      0,      0ull,   0ull},
56987         {"N2UF_BIS"                    ,        3,      1,      558,    "RO",   0,      0,      0ull,   0ull},
56988         {"E2HC_BIS"                    ,        4,      1,      558,    "RO",   0,      0,      0ull,   0ull},
56989         {"U2NF_BIS"                    ,        5,      1,      558,    "RO",   0,      0,      0ull,   0ull},
56990         {"U2NC_BIS"                    ,        6,      1,      558,    "RO",   0,      0,      0ull,   0ull},
56991         {"RESERVED_7_63"               ,        7,      57,     558,    "RAZ",  1,      1,      0,      0},
56992         {"DIVIDE"                      ,        0,      3,      559,    "R/W",  0,      0,      4ull,   0ull},
56993         {"HRST"                        ,        3,      1,      559,    "R/W",  0,      0,      0ull,   1ull},
56994         {"PRST"                        ,        4,      1,      559,    "R/W",  0,      0,      0ull,   1ull},
56995         {"ENABLE"                      ,        5,      1,      559,    "R/W",  0,      0,      1ull,   1ull},
56996         {"POR"                         ,        6,      1,      559,    "R/W",  0,      0,      1ull,   0ull},
56997         {"S_BIST"                      ,        7,      1,      559,    "R/W",  0,      0,      0ull,   1ull},
56998         {"SD_MODE"                     ,        8,      2,      559,    "R/W",  0,      0,      0ull,   0ull},
56999         {"CDIV_BYP"                    ,        10,     1,      559,    "R/W",  0,      0,      0ull,   0ull},
57000         {"P_C_SEL"                     ,        11,     2,      559,    "R/W",  0,      0,      2ull,   0ull},
57001         {"P_COM_ON"                    ,        13,     1,      559,    "R/W",  0,      0,      1ull,   1ull},
57002         {"P_RTYPE"                     ,        14,     2,      559,    "R/W",  0,      0,      0ull,   0ull},
57003         {"RESERVED_16_16"              ,        16,     1,      559,    "RAZ",  1,      1,      0,      0},
57004         {"HCLK_RST"                    ,        17,     1,      559,    "R/W",  0,      0,      1ull,   1ull},
57005         {"DIVIDE2"                     ,        18,     2,      559,    "R/W",  0,      0,      0ull,   1ull},
57006         {"RESERVED_20_63"              ,        20,     44,     559,    "RAZ",  1,      1,      0,      0},
57007         {"L2C_EMOD"                    ,        0,      2,      560,    "R/W",  0,      0,      1ull,   1ull},
57008         {"INV_A2"                      ,        2,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
57009         {"DMA_TEST"                    ,        3,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
57010         {"DMA_STT"                     ,        4,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
57011         {"DMA_0PAG"                    ,        5,      1,      560,    "R/W",  0,      0,      0ull,   0ull},
57012         {"RESERVED_6_63"               ,        6,      58,     560,    "RAZ",  1,      1,      0,      0},
57013         {"ADDR"                        ,        0,      36,     561,    "R/W",  0,      1,      0ull,   0},
57014         {"RESERVED_36_63"              ,        36,     28,     561,    "RAZ",  1,      1,      0,      0},
57015         {"ADDR"                        ,        0,      36,     562,    "R/W",  0,      1,      0ull,   0},
57016         {"RESERVED_36_63"              ,        36,     28,     562,    "RAZ",  1,      1,      0,      0},
57017         {"ADDR"                        ,        0,      36,     563,    "R/W",  0,      1,      0ull,   0},
57018         {"RESERVED_36_63"              ,        36,     28,     563,    "RAZ",  1,      1,      0,      0},
57019         {"ADDR"                        ,        0,      36,     564,    "R/W",  0,      1,      0ull,   0},
57020         {"RESERVED_36_63"              ,        36,     28,     564,    "RAZ",  1,      1,      0,      0},
57021         {"ADDR"                        ,        0,      36,     565,    "R/W",  0,      1,      0ull,   0},
57022         {"RESERVED_36_63"              ,        36,     28,     565,    "RAZ",  1,      1,      0,      0},
57023         {"ADDR"                        ,        0,      36,     566,    "R/W",  0,      1,      0ull,   0},
57024         {"RESERVED_36_63"              ,        36,     28,     566,    "RAZ",  1,      1,      0,      0},
57025         {"ADDR"                        ,        0,      36,     567,    "R/W",  0,      1,      0ull,   0},
57026         {"RESERVED_36_63"              ,        36,     28,     567,    "RAZ",  1,      1,      0,      0},
57027         {"ADDR"                        ,        0,      36,     568,    "R/W",  0,      1,      0ull,   0},
57028         {"RESERVED_36_63"              ,        36,     28,     568,    "RAZ",  1,      1,      0,      0},
57029         {"ADDR"                        ,        0,      36,     569,    "R/W",  0,      1,      0ull,   0},
57030         {"RESERVED_36_63"              ,        36,     28,     569,    "RAZ",  1,      1,      0,      0},
57031         {"ADDR"                        ,        0,      36,     570,    "R/W",  0,      1,      0ull,   0},
57032         {"RESERVED_36_63"              ,        36,     28,     570,    "RAZ",  1,      1,      0,      0},
57033         {"ADDR"                        ,        0,      36,     571,    "R/W",  0,      1,      0ull,   0},
57034         {"RESERVED_36_63"              ,        36,     28,     571,    "RAZ",  1,      1,      0,      0},
57035         {"ADDR"                        ,        0,      36,     572,    "R/W",  0,      1,      0ull,   0},
57036         {"RESERVED_36_63"              ,        36,     28,     572,    "RAZ",  1,      1,      0,      0},
57037         {"ADDR"                        ,        0,      36,     573,    "R/W",  0,      1,      0ull,   0},
57038         {"RESERVED_36_63"              ,        36,     28,     573,    "RAZ",  1,      1,      0,      0},
57039         {"ADDR"                        ,        0,      36,     574,    "R/W",  0,      1,      0ull,   0},
57040         {"RESERVED_36_63"              ,        36,     28,     574,    "RAZ",  1,      1,      0,      0},
57041         {"ADDR"                        ,        0,      36,     575,    "R/W",  0,      1,      0ull,   0},
57042         {"RESERVED_36_63"              ,        36,     28,     575,    "RAZ",  1,      1,      0,      0},
57043         {"ADDR"                        ,        0,      36,     576,    "R/W",  0,      1,      0ull,   0},
57044         {"RESERVED_36_63"              ,        36,     28,     576,    "RAZ",  1,      1,      0,      0},
57045         {"BURST"                       ,        0,      4,      577,    "R/W",  0,      0,      0ull,   0ull},
57046         {"CHANNEL"                     ,        4,      5,      577,    "R/W",  0,      0,      0ull,   0ull},
57047         {"COUNT"                       ,        9,      11,     577,    "R/W",  0,      0,      0ull,   0ull},
57048         {"F_ADDR"                      ,        20,     18,     577,    "R/W",  0,      0,      0ull,   0ull},
57049         {"REQ"                         ,        38,     1,      577,    "R/W1C",        0,      0,      0ull,   0ull},
57050         {"DONE"                        ,        39,     1,      577,    "R/W1C",        0,      0,      0ull,   0ull},
57051         {"RESERVED_40_63"              ,        40,     24,     577,    "RAZ",  1,      1,      0,      0},
57052         {"PR_PO_E"                     ,        0,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57053         {"PR_PU_F"                     ,        1,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57054         {"NR_PO_E"                     ,        2,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57055         {"NR_PU_F"                     ,        3,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57056         {"LR_PO_E"                     ,        4,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57057         {"LR_PU_F"                     ,        5,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57058         {"PT_PO_E"                     ,        6,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57059         {"PT_PU_F"                     ,        7,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57060         {"NT_PO_E"                     ,        8,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57061         {"NT_PU_F"                     ,        9,      1,      578,    "R/W",  0,      0,      0ull,   0ull},
57062         {"LT_PO_E"                     ,        10,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57063         {"LT_PU_F"                     ,        11,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57064         {"DCRED_E"                     ,        12,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57065         {"DCRED_F"                     ,        13,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57066         {"L2C_S_E"                     ,        14,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57067         {"L2C_A_F"                     ,        15,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57068         {"L2_FI_E"                     ,        16,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57069         {"L2_FI_F"                     ,        17,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57070         {"RG_FI_E"                     ,        18,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57071         {"RG_FI_F"                     ,        19,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57072         {"RQ_Q2_F"                     ,        20,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57073         {"RQ_Q2_E"                     ,        21,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57074         {"RQ_Q3_F"                     ,        22,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57075         {"RQ_Q3_E"                     ,        23,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57076         {"UOD_PE"                      ,        24,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57077         {"UOD_PF"                      ,        25,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57078         {"RESERVED_26_31"              ,        26,     6,      578,    "RAZ",  0,      0,      0ull,   0ull},
57079         {"LTL_F_PE"                    ,        32,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57080         {"LTL_F_PF"                    ,        33,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57081         {"ND4O_RPE"                    ,        34,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57082         {"ND4O_RPF"                    ,        35,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57083         {"ND4O_DPE"                    ,        36,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57084         {"ND4O_DPF"                    ,        37,     1,      578,    "R/W",  0,      0,      0ull,   0ull},
57085         {"RESERVED_38_63"              ,        38,     26,     578,    "RAZ",  1,      1,      0,      0},
57086         {"PR_PO_E"                     ,        0,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57087         {"PR_PU_F"                     ,        1,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57088         {"NR_PO_E"                     ,        2,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57089         {"NR_PU_F"                     ,        3,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57090         {"LR_PO_E"                     ,        4,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57091         {"LR_PU_F"                     ,        5,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57092         {"PT_PO_E"                     ,        6,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57093         {"PT_PU_F"                     ,        7,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57094         {"NT_PO_E"                     ,        8,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57095         {"NT_PU_F"                     ,        9,      1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57096         {"LT_PO_E"                     ,        10,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57097         {"LT_PU_F"                     ,        11,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57098         {"DCRED_E"                     ,        12,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57099         {"DCRED_F"                     ,        13,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57100         {"L2C_S_E"                     ,        14,     1,      579,    "R/W1C",        1,      0,      0,      0ull},
57101         {"L2C_A_F"                     ,        15,     1,      579,    "R/W1C",        1,      0,      0,      0ull},
57102         {"LT_FI_E"                     ,        16,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57103         {"LT_FI_F"                     ,        17,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57104         {"RG_FI_E"                     ,        18,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57105         {"RG_FI_F"                     ,        19,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57106         {"RQ_Q2_F"                     ,        20,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57107         {"RQ_Q2_E"                     ,        21,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57108         {"RQ_Q3_F"                     ,        22,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57109         {"RQ_Q3_E"                     ,        23,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57110         {"UOD_PE"                      ,        24,     1,      579,    "R/W1C",        1,      0,      0,      0ull},
57111         {"UOD_PF"                      ,        25,     1,      579,    "R/W1C",        1,      0,      0,      0ull},
57112         {"RESERVED_26_31"              ,        26,     6,      579,    "RAZ",  1,      0,      0,      0ull},
57113         {"LTL_F_PE"                    ,        32,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57114         {"LTL_F_PF"                    ,        33,     1,      579,    "R/W1C",        0,      0,      0ull,   0ull},
57115         {"ND4O_RPE"                    ,        34,     1,      579,    "R/W1C",        1,      0,      0,      0ull},
57116         {"ND4O_RPF"                    ,        35,     1,      579,    "R/W1C",        1,      0,      0,      0ull},
57117         {"ND4O_DPE"                    ,        36,     1,      579,    "R/W1C",        1,      0,      0,      0ull},
57118         {"ND4O_DPF"                    ,        37,     1,      579,    "R/W1C",        1,      0,      0,      0ull},
57119         {"RESERVED_38_63"              ,        38,     26,     579,    "RAZ",  1,      1,      0,      0},
57120         {"ATE_RESET"                   ,        0,      1,      580,    "R/W",  0,      0,      0ull,   0ull},
57121         {"TDATA_IN"                    ,        1,      8,      580,    "R/W",  0,      0,      0ull,   0ull},
57122         {"TADDR_IN"                    ,        9,      4,      580,    "R/W",  0,      0,      0ull,   0ull},
57123         {"TDATA_SEL"                   ,        13,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57124         {"BIST_ENB"                    ,        14,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57125         {"VTEST_ENB"                   ,        15,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57126         {"LOOP_ENB"                    ,        16,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57127         {"TX_BS_EN"                    ,        17,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57128         {"TX_BS_ENH"                   ,        18,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57129         {"RESERVED_19_22"              ,        19,     4,      580,    "RAZ",  0,      0,      0ull,   0ull},
57130         {"HST_MODE"                    ,        23,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57131         {"DM_PULLD"                    ,        24,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
57132         {"DP_PULLD"                    ,        25,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
57133         {"TCLK"                        ,        26,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57134         {"USBP_BIST"                   ,        27,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
57135         {"USBC_END"                    ,        28,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57136         {"DMA_BMODE"                   ,        29,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57137         {"TXPREEMPHASISTUNE"           ,        30,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57138         {"RESERVED_31_31"              ,        31,     1,      580,    "RAZ",  0,      0,      0ull,   0ull},
57139         {"TDATA_OUT"                   ,        32,     4,      580,    "RO",   1,      1,      0,      0},
57140         {"BIST_ERR"                    ,        36,     1,      580,    "RO",   0,      0,      0ull,   0ull},
57141         {"BIST_DONE"                   ,        37,     1,      580,    "RO",   0,      0,      0ull,   0ull},
57142         {"HSBIST"                      ,        38,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57143         {"FSBIST"                      ,        39,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57144         {"LSBIST"                      ,        40,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57145         {"DRVVBUS"                     ,        41,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57146         {"PORTRESET"                   ,        42,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57147         {"OTGDISABLE"                  ,        43,     1,      580,    "R/W",  0,      0,      1ull,   1ull},
57148         {"OTGTUNE"                     ,        44,     3,      580,    "R/W",  0,      0,      2ull,   2ull},
57149         {"COMPDISTUNE"                 ,        47,     3,      580,    "R/W",  0,      0,      2ull,   2ull},
57150         {"SQRXTUNE"                    ,        50,     3,      580,    "R/W",  0,      0,      3ull,   3ull},
57151         {"TXHSXVTUNE"                  ,        53,     2,      580,    "R/W",  0,      0,      0ull,   0ull},
57152         {"TXFSLSTUNE"                  ,        55,     4,      580,    "R/W",  0,      0,      3ull,   3ull},
57153         {"TXVREFTUNE"                  ,        59,     4,      580,    "R/W",  0,      0,      7ull,   7ull},
57154         {"TXRISETUNE"                  ,        63,     1,      580,    "R/W",  0,      0,      0ull,   0ull},
57155         {NULL,0,0,0,0,0,0,0,0}
57156 };
57157 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xxp1[] = {
57158          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
57159         {"cvmx_agl_gmx_bad_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      14,     0},
57160         {"cvmx_agl_gmx_bist"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1,      2,      14},
57161         {"cvmx_agl_gmx_drv_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      12,     16},
57162         {"cvmx_agl_gmx_inf_mode"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     3,      3,      28},
57163         {"cvmx_agl_gmx_prt#_cfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      7,      31},
57164         {"cvmx_agl_gmx_rx#_adr_cam0"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      1,      38},
57165         {"cvmx_agl_gmx_rx#_adr_cam1"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     8,      1,      39},
57166         {"cvmx_agl_gmx_rx#_adr_cam2"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     1,      40},
57167         {"cvmx_agl_gmx_rx#_adr_cam3"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     12,     1,      41},
57168         {"cvmx_agl_gmx_rx#_adr_cam4"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     1,      42},
57169         {"cvmx_agl_gmx_rx#_adr_cam5"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     16,     1,      43},
57170         {"cvmx_agl_gmx_rx#_adr_cam_en" ,        CVMX_CSR_DB_TYPE_RSL,   64,     18,     2,      44},
57171         {"cvmx_agl_gmx_rx#_adr_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     20,     4,      46},
57172         {"cvmx_agl_gmx_rx#_decision"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     22,     2,      50},
57173         {"cvmx_agl_gmx_rx#_frm_chk"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     24,     10,     52},
57174         {"cvmx_agl_gmx_rx#_frm_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     26,     11,     62},
57175         {"cvmx_agl_gmx_rx#_frm_max"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     28,     2,      73},
57176         {"cvmx_agl_gmx_rx#_frm_min"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     30,     2,      75},
57177         {"cvmx_agl_gmx_rx#_ifg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     32,     2,      77},
57178         {"cvmx_agl_gmx_rx#_int_en"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     34,     19,     79},
57179         {"cvmx_agl_gmx_rx#_int_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     36,     19,     98},
57180         {"cvmx_agl_gmx_rx#_jabber"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     38,     2,      117},
57181         {"cvmx_agl_gmx_rx#_pause_drop_time",    CVMX_CSR_DB_TYPE_RSL,   64,     40,     2,      119},
57182         {"cvmx_agl_gmx_rx#_stats_ctl"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     42,     2,      121},
57183         {"cvmx_agl_gmx_rx#_stats_octs" ,        CVMX_CSR_DB_TYPE_RSL,   64,     44,     2,      123},
57184         {"cvmx_agl_gmx_rx#_stats_octs_ctl",     CVMX_CSR_DB_TYPE_RSL,   64,     46,     2,      125},
57185         {"cvmx_agl_gmx_rx#_stats_octs_dmac",    CVMX_CSR_DB_TYPE_RSL,   64,     48,     2,      127},
57186         {"cvmx_agl_gmx_rx#_stats_octs_drp",     CVMX_CSR_DB_TYPE_RSL,   64,     50,     2,      129},
57187         {"cvmx_agl_gmx_rx#_stats_pkts" ,        CVMX_CSR_DB_TYPE_RSL,   64,     52,     2,      131},
57188         {"cvmx_agl_gmx_rx#_stats_pkts_bad",     CVMX_CSR_DB_TYPE_RSL,   64,     54,     2,      133},
57189         {"cvmx_agl_gmx_rx#_stats_pkts_ctl",     CVMX_CSR_DB_TYPE_RSL,   64,     56,     2,      135},
57190         {"cvmx_agl_gmx_rx#_stats_pkts_dmac",    CVMX_CSR_DB_TYPE_RSL,   64,     58,     2,      137},
57191         {"cvmx_agl_gmx_rx#_stats_pkts_drp",     CVMX_CSR_DB_TYPE_RSL,   64,     60,     2,      139},
57192         {"cvmx_agl_gmx_rx#_udd_skp"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     62,     4,      141},
57193         {"cvmx_agl_gmx_rx_bp_drop#"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     64,     2,      145},
57194         {"cvmx_agl_gmx_rx_bp_off#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     66,     2,      147},
57195         {"cvmx_agl_gmx_rx_bp_on#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     68,     2,      149},
57196         {"cvmx_agl_gmx_rx_prt_info"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     70,     4,      151},
57197         {"cvmx_agl_gmx_rx_tx_status"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     71,     4,      155},
57198         {"cvmx_agl_gmx_smac#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     72,     2,      159},
57199         {"cvmx_agl_gmx_stat_bp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     74,     3,      161},
57200         {"cvmx_agl_gmx_tx#_append"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     75,     5,      164},
57201         {"cvmx_agl_gmx_tx#_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     77,     3,      169},
57202         {"cvmx_agl_gmx_tx#_min_pkt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     79,     2,      172},
57203         {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL,   64,     81,     2,      174},
57204         {"cvmx_agl_gmx_tx#_pause_pkt_time",     CVMX_CSR_DB_TYPE_RSL,   64,     83,     2,      176},
57205         {"cvmx_agl_gmx_tx#_pause_togo" ,        CVMX_CSR_DB_TYPE_RSL,   64,     85,     2,      178},
57206         {"cvmx_agl_gmx_tx#_pause_zero" ,        CVMX_CSR_DB_TYPE_RSL,   64,     87,     2,      180},
57207         {"cvmx_agl_gmx_tx#_soft_pause" ,        CVMX_CSR_DB_TYPE_RSL,   64,     89,     2,      182},
57208         {"cvmx_agl_gmx_tx#_stat0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     91,     2,      184},
57209         {"cvmx_agl_gmx_tx#_stat1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     93,     2,      186},
57210         {"cvmx_agl_gmx_tx#_stat2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     95,     2,      188},
57211         {"cvmx_agl_gmx_tx#_stat3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     97,     2,      190},
57212         {"cvmx_agl_gmx_tx#_stat4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     99,     2,      192},
57213         {"cvmx_agl_gmx_tx#_stat5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     101,    2,      194},
57214         {"cvmx_agl_gmx_tx#_stat6"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     103,    2,      196},
57215         {"cvmx_agl_gmx_tx#_stat7"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     105,    2,      198},
57216         {"cvmx_agl_gmx_tx#_stat8"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     107,    2,      200},
57217         {"cvmx_agl_gmx_tx#_stat9"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     109,    2,      202},
57218         {"cvmx_agl_gmx_tx#_stats_ctl"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     111,    2,      204},
57219         {"cvmx_agl_gmx_tx#_thresh"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     113,    2,      206},
57220         {"cvmx_agl_gmx_tx_bp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     115,    2,      208},
57221         {"cvmx_agl_gmx_tx_col_attempt" ,        CVMX_CSR_DB_TYPE_RSL,   64,     116,    2,      210},
57222         {"cvmx_agl_gmx_tx_ifg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     117,    3,      212},
57223         {"cvmx_agl_gmx_tx_int_en"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     118,    10,     215},
57224         {"cvmx_agl_gmx_tx_int_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     119,    10,     225},
57225         {"cvmx_agl_gmx_tx_jam"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     120,    2,      235},
57226         {"cvmx_agl_gmx_tx_lfsr"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     121,    2,      237},
57227         {"cvmx_agl_gmx_tx_ovr_bp"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     122,    6,      239},
57228         {"cvmx_agl_gmx_tx_pause_pkt_dmac",      CVMX_CSR_DB_TYPE_RSL,   64,     123,    2,      245},
57229         {"cvmx_agl_gmx_tx_pause_pkt_type",      CVMX_CSR_DB_TYPE_RSL,   64,     124,    2,      247},
57230         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     125,    2,      249},
57231         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     126,    2,      251},
57232         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     127,    2,      253},
57233         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     128,    2,      255},
57234         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     129,    22,     257},
57235         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     138,    6,      279},
57236         {"cvmx_ciu_int#_en4_0"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     147,    22,     285},
57237         {"cvmx_ciu_int#_en4_1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     151,    6,      307},
57238         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     155,    22,     313},
57239         {"cvmx_ciu_int#_sum4"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     164,    22,     335},
57240         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     168,    6,      357},
57241         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     169,    2,      363},
57242         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     173,    2,      365},
57243         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     177,    2,      367},
57244         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     178,    2,      369},
57245         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     179,    2,      371},
57246         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     180,    1,      373},
57247         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     184,    3,      374},
57248         {"cvmx_ciu_qlm_dcok"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     185,    2,      377},
57249         {"cvmx_ciu_qlm_jtgc"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     186,    6,      379},
57250         {"cvmx_ciu_qlm_jtgd"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     187,    8,      385},
57251         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     188,    2,      393},
57252         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     189,    2,      395},
57253         {"cvmx_ciu_soft_prst1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     190,    2,      397},
57254         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     191,    2,      399},
57255         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     192,    3,      401},
57256         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     196,    7,      404},
57257         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     200,    6,      411},
57258         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     201,    7,      417},
57259         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     202,    29,     424},
57260         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     203,    29,     453},
57261         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     204,    2,      482},
57262         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     212,    2,      484},
57263         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     220,    3,      486},
57264         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     221,    3,      489},
57265         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     222,    2,      492},
57266         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     223,    2,      494},
57267         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     224,    7,      496},
57268         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     225,    2,      503},
57269         {"cvmx_gmx#_clk_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     226,    2,      505},
57270         {"cvmx_gmx#_hg2_control"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     227,    5,      507},
57271         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     228,    7,      512},
57272         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     229,    2,      519},
57273         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     230,    10,     521},
57274         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     234,    1,      531},
57275         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     238,    1,      532},
57276         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     242,    1,      533},
57277         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     246,    1,      534},
57278         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     250,    1,      535},
57279         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     254,    1,      536},
57280         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     258,    2,      537},
57281         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     262,    4,      539},
57282         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     266,    2,      543},
57283         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     270,    9,      545},
57284         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     274,    11,     554},
57285         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     278,    2,      565},
57286         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     282,    27,     567},
57287         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     286,    27,     594},
57288         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     290,    2,      621},
57289         {"cvmx_gmx#_rx#_pause_drop_time",       CVMX_CSR_DB_TYPE_RSL,   64,     294,    2,      623},
57290         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     298,    2,      625},
57291         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     302,    2,      627},
57292         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     306,    2,      629},
57293         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     310,    2,      631},
57294         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     314,    2,      633},
57295         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     318,    2,      635},
57296         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     322,    2,      637},
57297         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     326,    2,      639},
57298         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     330,    2,      641},
57299         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     334,    2,      643},
57300         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     338,    4,      645},
57301         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     342,    2,      649},
57302         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     346,    2,      651},
57303         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     350,    2,      653},
57304         {"cvmx_gmx#_rx_hg2_status"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     354,    4,      655},
57305         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     355,    4,      659},
57306         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     356,    2,      663},
57307         {"cvmx_gmx#_rx_xaui_bad_col"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     357,    5,      665},
57308         {"cvmx_gmx#_rx_xaui_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     358,    2,      670},
57309         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     359,    2,      672},
57310         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     363,    3,      674},
57311         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     364,    5,      677},
57312         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     368,    2,      682},
57313         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     372,    3,      684},
57314         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     376,    2,      687},
57315         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     380,    2,      689},
57316         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     384,    2,      691},
57317         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     388,    3,      693},
57318         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     392,    2,      696},
57319         {"cvmx_gmx#_tx#_sgmii_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     396,    2,      698},
57320         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     400,    2,      700},
57321         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     404,    2,      702},
57322         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     408,    2,      704},
57323         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     412,    2,      706},
57324         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     416,    2,      708},
57325         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     420,    2,      710},
57326         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     424,    2,      712},
57327         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     428,    2,      714},
57328         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     432,    2,      716},
57329         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     436,    2,      718},
57330         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     440,    2,      720},
57331         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     444,    2,      722},
57332         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     448,    2,      724},
57333         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     452,    2,      726},
57334         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     456,    2,      728},
57335         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     457,    2,      730},
57336         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     458,    2,      732},
57337         {"cvmx_gmx#_tx_hg2_reg1"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     459,    2,      734},
57338         {"cvmx_gmx#_tx_hg2_reg2"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     460,    2,      736},
57339         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     461,    3,      738},
57340         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     462,    8,      741},
57341         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     463,    8,      749},
57342         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     464,    2,      757},
57343         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     465,    2,      759},
57344         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     466,    6,      761},
57345         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     467,    2,      767},
57346         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     468,    2,      769},
57347         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     469,    2,      771},
57348         {"cvmx_gmx#_tx_xaui_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     470,    9,      773},
57349         {"cvmx_gmx#_xaui_ext_loopback" ,        CVMX_CSR_DB_TYPE_RSL,   64,     471,    3,      782},
57350         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     472,    9,      785},
57351         {"cvmx_gpio_clk_gen#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     488,    2,      794},
57352         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     492,    2,      796},
57353         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     493,    2,      798},
57354         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     494,    2,      800},
57355         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     495,    2,      802},
57356         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     496,    19,     804},
57357         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     497,    6,      823},
57358         {"cvmx_iob_dwb_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     498,    3,      829},
57359         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     499,    3,      832},
57360         {"cvmx_iob_i2c_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     500,    3,      835},
57361         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     501,    5,      838},
57362         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     502,    5,      843},
57363         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     503,    1,      848},
57364         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     504,    1,      849},
57365         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     505,    7,      850},
57366         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     506,    7,      857},
57367         {"cvmx_iob_n2c_l2c_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     507,    3,      864},
57368         {"cvmx_iob_n2c_rsp_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     508,    3,      867},
57369         {"cvmx_iob_outb_com_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     509,    3,      870},
57370         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     510,    5,      873},
57371         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     511,    5,      878},
57372         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     512,    1,      883},
57373         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     513,    1,      884},
57374         {"cvmx_iob_outb_fpa_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     514,    3,      885},
57375         {"cvmx_iob_outb_req_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     515,    3,      888},
57376         {"cvmx_iob_p2c_req_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     516,    3,      891},
57377         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     517,    2,      894},
57378         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     518,    2,      896},
57379         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     519,    2,      898},
57380         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     520,    2,      900},
57381         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     521,    19,     902},
57382         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     522,    2,      921},
57383         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     523,    1,      923},
57384         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     524,    15,     924},
57385         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     525,    13,     939},
57386         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     526,    13,     952},
57387         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     527,    2,      965},
57388         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     528,    2,      967},
57389         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     529,    2,      969},
57390         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     530,    3,      971},
57391         {"cvmx_ipd_port#_bp_page_cnt2" ,        CVMX_CSR_DB_TYPE_NCB,   64,     534,    3,      974},
57392         {"cvmx_ipd_port_bp_counters2_pair#",    CVMX_CSR_DB_TYPE_NCB,   64,     538,    2,      977},
57393         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     542,    2,      979},
57394         {"cvmx_ipd_port_qos_#_cnt"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     546,    2,      981},
57395         {"cvmx_ipd_port_qos_int#"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     610,    1,      983},
57396         {"cvmx_ipd_port_qos_int_enb#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     612,    1,      984},
57397         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     614,    6,      985},
57398         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     615,    5,      991},
57399         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     616,    6,      996},
57400         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     617,    7,      1002},
57401         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     618,    2,      1009},
57402         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     626,    2,      1011},
57403         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     627,    3,      1013},
57404         {"cvmx_ipd_red_port_enable2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     628,    2,      1016},
57405         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     629,    5,      1018},
57406         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     637,    3,      1023},
57407         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     638,    4,      1026},
57408         {"cvmx_ipd_sub_port_qos_cnt"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     639,    3,      1030},
57409         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     640,    2,      1033},
57410         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     641,    2,      1035},
57411         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     642,    8,      1037},
57412         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     643,    9,      1045},
57413         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     644,    8,      1054},
57414         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     645,    12,     1062},
57415         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     646,    9,      1074},
57416         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     647,    5,      1083},
57417         {"cvmx_l2c_grpwrr0"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     648,    2,      1088},
57418         {"cvmx_l2c_grpwrr1"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     649,    2,      1090},
57419         {"cvmx_l2c_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     650,    10,     1092},
57420         {"cvmx_l2c_int_stat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     651,    10,     1102},
57421         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     652,    4,      1112},
57422         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     653,    2,      1116},
57423         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     654,    16,     1118},
57424         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     655,    19,     1134},
57425         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     656,    3,      1153},
57426         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     657,    4,      1156},
57427         {"cvmx_l2c_oob"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     658,    3,      1160},
57428         {"cvmx_l2c_oob1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     659,    6,      1163},
57429         {"cvmx_l2c_oob2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     660,    6,      1169},
57430         {"cvmx_l2c_oob3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     661,    6,      1175},
57431         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     662,    2,      1181},
57432         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     666,    17,     1183},
57433         {"cvmx_l2c_ppgrp"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     667,    5,      1200},
57434         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     668,    5,      1205},
57435         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     669,    2,      1210},
57436         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     670,    3,      1212},
57437         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     671,    2,      1215},
57438         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     672,    2,      1217},
57439         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     673,    2,      1219},
57440         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     674,    7,      1221},
57441         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     675,    5,      1228},
57442         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     676,    3,      1233},
57443         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     677,    3,      1236},
57444         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     678,    2,      1239},
57445         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     679,    2,      1241},
57446         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     680,    2,      1243},
57447         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     681,    6,      1245},
57448         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     682,    14,     1251},
57449         {"cvmx_lmc#_bist_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     683,    2,      1265},
57450         {"cvmx_lmc#_bist_result"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     684,    8,      1267},
57451         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     685,    7,      1275},
57452         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     686,    19,     1282},
57453         {"cvmx_lmc#_ctl1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     687,    8,      1301},
57454         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     688,    2,      1309},
57455         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     689,    2,      1311},
57456         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     690,    18,     1313},
57457         {"cvmx_lmc#_delay_cfg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     691,    6,      1331},
57458         {"cvmx_lmc#_dll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     692,    5,      1337},
57459         {"cvmx_lmc#_dual_memcfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     693,    5,      1342},
57460         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     694,    5,      1347},
57461         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     695,    6,      1352},
57462         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     696,    2,      1358},
57463         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     697,    2,      1360},
57464         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     698,    14,     1362},
57465         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     699,    9,      1376},
57466         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     700,    2,      1385},
57467         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     701,    2,      1387},
57468         {"cvmx_lmc#_pll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     702,    14,     1389},
57469         {"cvmx_lmc#_pll_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     703,    6,      1403},
57470         {"cvmx_lmc#_read_level_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     704,    7,      1409},
57471         {"cvmx_lmc#_read_level_dbg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     705,    4,      1416},
57472         {"cvmx_lmc#_read_level_rank#"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     706,    11,     1420},
57473         {"cvmx_lmc#_rodt_comp_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     710,    6,      1431},
57474         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     711,    9,      1437},
57475         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     712,    5,      1446},
57476         {"cvmx_lmc#_wodt_ctl1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     713,    5,      1451},
57477         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     714,    5,      1456},
57478         {"cvmx_mio_boot_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     715,    3,      1461},
57479         {"cvmx_mio_boot_dma_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     716,    10,     1464},
57480         {"cvmx_mio_boot_dma_int#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     718,    3,      1474},
57481         {"cvmx_mio_boot_dma_int_en#"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     720,    3,      1477},
57482         {"cvmx_mio_boot_dma_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     722,    15,     1480},
57483         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     724,    3,      1495},
57484         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     725,    3,      1498},
57485         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     726,    3,      1501},
57486         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     727,    5,      1504},
57487         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     729,    1,      1509},
57488         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     730,    13,     1510},
57489         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     738,    13,     1523},
57490         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     746,    6,      1536},
57491         {"cvmx_mio_fus_bnk_dat#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     747,    1,      1542},
57492         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     751,    2,      1543},
57493         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     752,    2,      1545},
57494         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     753,    13,     1547},
57495         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     754,    8,      1560},
57496         {"cvmx_mio_fus_ema"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     755,    4,      1568},
57497         {"cvmx_mio_fus_pdf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     756,    1,      1572},
57498         {"cvmx_mio_fus_pll"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     757,    3,      1573},
57499         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     758,    2,      1576},
57500         {"cvmx_mio_fus_prog_times"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     759,    6,      1578},
57501         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     760,    7,      1584},
57502         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     761,    4,      1591},
57503         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     762,    2,      1595},
57504         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     763,    2,      1597},
57505         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     764,    13,     1599},
57506         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     766,    12,     1612},
57507         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     768,    3,      1624},
57508         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     770,    3,      1627},
57509         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     772,    2,      1630},
57510         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     774,    2,      1632},
57511         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     776,    2,      1634},
57512         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     778,    7,      1636},
57513         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     780,    2,      1643},
57514         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     782,    7,      1645},
57515         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     784,    4,      1652},
57516         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     786,    8,      1656},
57517         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     788,    9,      1664},
57518         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     790,    7,      1673},
57519         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     792,    9,      1680},
57520         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     794,    2,      1689},
57521         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     796,    2,      1691},
57522         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     798,    4,      1693},
57523         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     800,    2,      1697},
57524         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     802,    2,      1699},
57525         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     804,    2,      1701},
57526         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     806,    4,      1703},
57527         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     808,    2,      1707},
57528         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     810,    2,      1709},
57529         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     812,    2,      1711},
57530         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     814,    2,      1713},
57531         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     816,    2,      1715},
57532         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     818,    2,      1717},
57533         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     820,    6,      1719},
57534         {"cvmx_mio_uart2_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     822,    2,      1725},
57535         {"cvmx_mio_uart2_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     823,    2,      1727},
57536         {"cvmx_mio_uart2_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     824,    2,      1729},
57537         {"cvmx_mio_uart2_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     825,    7,      1731},
57538         {"cvmx_mio_uart2_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     826,    2,      1738},
57539         {"cvmx_mio_uart2_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     827,    7,      1740},
57540         {"cvmx_mio_uart2_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     828,    4,      1747},
57541         {"cvmx_mio_uart2_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     829,    8,      1751},
57542         {"cvmx_mio_uart2_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     830,    9,      1759},
57543         {"cvmx_mio_uart2_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     831,    7,      1768},
57544         {"cvmx_mio_uart2_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     832,    9,      1775},
57545         {"cvmx_mio_uart2_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     833,    2,      1784},
57546         {"cvmx_mio_uart2_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     834,    2,      1786},
57547         {"cvmx_mio_uart2_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     835,    4,      1788},
57548         {"cvmx_mio_uart2_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     836,    2,      1792},
57549         {"cvmx_mio_uart2_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     837,    2,      1794},
57550         {"cvmx_mio_uart2_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     838,    2,      1796},
57551         {"cvmx_mio_uart2_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     839,    4,      1798},
57552         {"cvmx_mio_uart2_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     840,    2,      1802},
57553         {"cvmx_mio_uart2_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     841,    2,      1804},
57554         {"cvmx_mio_uart2_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     842,    2,      1806},
57555         {"cvmx_mio_uart2_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     843,    2,      1808},
57556         {"cvmx_mio_uart2_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     844,    2,      1810},
57557         {"cvmx_mio_uart2_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     845,    2,      1812},
57558         {"cvmx_mio_uart2_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     846,    6,      1814},
57559         {"cvmx_mix#_bist"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     847,    5,      1820},
57560         {"cvmx_mix#_ctl"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     849,    8,      1825},
57561         {"cvmx_mix#_intena"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     851,    8,      1833},
57562         {"cvmx_mix#_ircnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     853,    2,      1841},
57563         {"cvmx_mix#_irhwm"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     855,    3,      1843},
57564         {"cvmx_mix#_iring1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     857,    5,      1846},
57565         {"cvmx_mix#_iring2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     859,    4,      1851},
57566         {"cvmx_mix#_isr"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     861,    8,      1855},
57567         {"cvmx_mix#_orcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     863,    2,      1863},
57568         {"cvmx_mix#_orhwm"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     865,    2,      1865},
57569         {"cvmx_mix#_oring1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     867,    5,      1867},
57570         {"cvmx_mix#_oring2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     869,    4,      1872},
57571         {"cvmx_mix#_remcnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     871,    4,      1876},
57572         {"cvmx_npei_bar1_index#"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     873,    5,      1880},
57573         {"cvmx_npei_bist_status"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     905,    47,     1885},
57574         {"cvmx_npei_ctl_port0"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     906,    17,     1932},
57575         {"cvmx_npei_ctl_port1"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     907,    17,     1949},
57576         {"cvmx_npei_ctl_status"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     908,    10,     1966},
57577         {"cvmx_npei_ctl_status2"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     909,    11,     1976},
57578         {"cvmx_npei_data_out_cnt"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     910,    5,      1987},
57579         {"cvmx_npei_dbg_data"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     911,    8,      1992},
57580         {"cvmx_npei_dbg_select"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     912,    2,      2000},
57581         {"cvmx_npei_dma#_counts"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     913,    3,      2002},
57582         {"cvmx_npei_dma#_dbell"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     917,    2,      2005},
57583         {"cvmx_npei_dma#_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     921,    3,      2007},
57584         {"cvmx_npei_dma#_naddr"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     925,    2,      2010},
57585         {"cvmx_npei_dma0_int_level"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     929,    2,      2012},
57586         {"cvmx_npei_dma1_int_level"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     930,    2,      2014},
57587         {"cvmx_npei_dma_cnts"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     931,    2,      2016},
57588         {"cvmx_npei_dma_control"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     932,    15,     2018},
57589         {"cvmx_npei_dma_state1_p1"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     933,    11,     2033},
57590         {"cvmx_npei_dma_state2_p1"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     934,    6,      2044},
57591         {"cvmx_npei_dma_state3_p1"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     935,    5,      2050},
57592         {"cvmx_npei_dma_state4_p1"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     936,    5,      2055},
57593         {"cvmx_npei_int_a_enb"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     937,    3,      2060},
57594         {"cvmx_npei_int_a_enb2"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     938,    3,      2063},
57595         {"cvmx_npei_int_a_sum"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     939,    3,      2066},
57596         {"cvmx_npei_int_enb"           ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     940,    64,     2069},
57597         {"cvmx_npei_int_enb2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     941,    63,     2133},
57598         {"cvmx_npei_int_sum"           ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     942,    61,     2196},
57599         {"cvmx_npei_int_sum2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     943,    61,     2257},
57600         {"cvmx_npei_last_win_rdata0"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     944,    1,      2318},
57601         {"cvmx_npei_last_win_rdata1"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     945,    1,      2319},
57602         {"cvmx_npei_mem_access_ctl"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     946,    3,      2320},
57603         {"cvmx_npei_mem_access_subid#" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     947,    11,     2323},
57604         {"cvmx_npei_msi_enb0"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     963,    1,      2334},
57605         {"cvmx_npei_msi_enb1"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     964,    1,      2335},
57606         {"cvmx_npei_msi_enb2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     965,    1,      2336},
57607         {"cvmx_npei_msi_enb3"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     966,    1,      2337},
57608         {"cvmx_npei_msi_rcv0"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     967,    1,      2338},
57609         {"cvmx_npei_msi_rcv1"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     968,    1,      2339},
57610         {"cvmx_npei_msi_rcv2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     969,    1,      2340},
57611         {"cvmx_npei_msi_rcv3"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     970,    1,      2341},
57612         {"cvmx_npei_msi_rd_map"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     971,    3,      2342},
57613         {"cvmx_npei_msi_wr_map"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     972,    3,      2345},
57614         {"cvmx_npei_pcie_msi_rcv"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     973,    2,      2348},
57615         {"cvmx_npei_pcie_msi_rcv_b1"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     974,    3,      2350},
57616         {"cvmx_npei_pcie_msi_rcv_b2"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     975,    3,      2353},
57617         {"cvmx_npei_pcie_msi_rcv_b3"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     976,    3,      2356},
57618         {"cvmx_npei_rsl_int_blocks"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     977,    29,     2359},
57619         {"cvmx_npei_scratch_1"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     978,    1,      2388},
57620         {"cvmx_npei_state1"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     979,    4,      2389},
57621         {"cvmx_npei_state2"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     980,    7,      2393},
57622         {"cvmx_npei_state3"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     981,    5,      2400},
57623         {"cvmx_npei_win_rd_addr"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     982,    4,      2405},
57624         {"cvmx_npei_win_rd_data"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     983,    1,      2409},
57625         {"cvmx_npei_win_wr_addr"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     984,    4,      2410},
57626         {"cvmx_npei_win_wr_data"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     985,    1,      2414},
57627         {"cvmx_npei_win_wr_mask"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     986,    2,      2415},
57628         {"cvmx_npei_window_ctl"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     987,    2,      2417},
57629         {"cvmx_pcieep_cfg000"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     988,    2,      2419},
57630         {"cvmx_pcieep_cfg001"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     989,    24,     2421},
57631         {"cvmx_pcieep_cfg002"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     990,    4,      2445},
57632         {"cvmx_pcieep_cfg003"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     991,    5,      2449},
57633         {"cvmx_pcieep_cfg004"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     992,    5,      2454},
57634         {"cvmx_pcieep_cfg004_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     993,    2,      2459},
57635         {"cvmx_pcieep_cfg005"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     994,    1,      2461},
57636         {"cvmx_pcieep_cfg005_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     995,    1,      2462},
57637         {"cvmx_pcieep_cfg006"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     996,    5,      2463},
57638         {"cvmx_pcieep_cfg006_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     997,    2,      2468},
57639         {"cvmx_pcieep_cfg007"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     998,    1,      2470},
57640         {"cvmx_pcieep_cfg007_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     999,    1,      2471},
57641         {"cvmx_pcieep_cfg008"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1000,   4,      2472},
57642         {"cvmx_pcieep_cfg008_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1001,   2,      2476},
57643         {"cvmx_pcieep_cfg009"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1002,   2,      2478},
57644         {"cvmx_pcieep_cfg009_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1003,   1,      2480},
57645         {"cvmx_pcieep_cfg010"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1004,   1,      2481},
57646         {"cvmx_pcieep_cfg011"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1005,   2,      2482},
57647         {"cvmx_pcieep_cfg012"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1006,   3,      2484},
57648         {"cvmx_pcieep_cfg012_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1007,   2,      2487},
57649         {"cvmx_pcieep_cfg013"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1008,   2,      2489},
57650         {"cvmx_pcieep_cfg015"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1009,   4,      2491},
57651         {"cvmx_pcieep_cfg016"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1010,   10,     2495},
57652         {"cvmx_pcieep_cfg017"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1011,   12,     2505},
57653         {"cvmx_pcieep_cfg020"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1012,   7,      2517},
57654         {"cvmx_pcieep_cfg021"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1013,   2,      2524},
57655         {"cvmx_pcieep_cfg022"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1014,   1,      2526},
57656         {"cvmx_pcieep_cfg023"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1015,   2,      2527},
57657         {"cvmx_pcieep_cfg028"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1016,   7,      2529},
57658         {"cvmx_pcieep_cfg029"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1017,   11,     2536},
57659         {"cvmx_pcieep_cfg030"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1018,   19,     2547},
57660         {"cvmx_pcieep_cfg031"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1019,   11,     2566},
57661         {"cvmx_pcieep_cfg032"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1020,   17,     2577},
57662         {"cvmx_pcieep_cfg033"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1021,   12,     2594},
57663         {"cvmx_pcieep_cfg034"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1022,   22,     2606},
57664         {"cvmx_pcieep_cfg037"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1023,   3,      2628},
57665         {"cvmx_pcieep_cfg038"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1024,   3,      2631},
57666         {"cvmx_pcieep_cfg039"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1025,   1,      2634},
57667         {"cvmx_pcieep_cfg040"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1026,   1,      2635},
57668         {"cvmx_pcieep_cfg041"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1027,   1,      2636},
57669         {"cvmx_pcieep_cfg042"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1028,   1,      2637},
57670         {"cvmx_pcieep_cfg064"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1029,   3,      2638},
57671         {"cvmx_pcieep_cfg065"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1030,   14,     2641},
57672         {"cvmx_pcieep_cfg066"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1031,   14,     2655},
57673         {"cvmx_pcieep_cfg067"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1032,   14,     2669},
57674         {"cvmx_pcieep_cfg068"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1033,   9,      2683},
57675         {"cvmx_pcieep_cfg069"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1034,   9,      2692},
57676         {"cvmx_pcieep_cfg070"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1035,   6,      2701},
57677         {"cvmx_pcieep_cfg071"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1036,   1,      2707},
57678         {"cvmx_pcieep_cfg072"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1037,   1,      2708},
57679         {"cvmx_pcieep_cfg073"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1038,   1,      2709},
57680         {"cvmx_pcieep_cfg074"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1039,   1,      2710},
57681         {"cvmx_pcieep_cfg448"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1040,   2,      2711},
57682         {"cvmx_pcieep_cfg449"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1041,   1,      2713},
57683         {"cvmx_pcieep_cfg450"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1042,   6,      2714},
57684         {"cvmx_pcieep_cfg451"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1043,   6,      2720},
57685         {"cvmx_pcieep_cfg452"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1044,   13,     2726},
57686         {"cvmx_pcieep_cfg453"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1045,   5,      2739},
57687         {"cvmx_pcieep_cfg454"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1046,   8,      2744},
57688         {"cvmx_pcieep_cfg455"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1047,   19,     2752},
57689         {"cvmx_pcieep_cfg456"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1048,   3,      2771},
57690         {"cvmx_pcieep_cfg458"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1049,   1,      2774},
57691         {"cvmx_pcieep_cfg459"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1050,   1,      2775},
57692         {"cvmx_pcieep_cfg460"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1051,   3,      2776},
57693         {"cvmx_pcieep_cfg461"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1052,   3,      2779},
57694         {"cvmx_pcieep_cfg462"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1053,   3,      2782},
57695         {"cvmx_pcieep_cfg463"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1054,   4,      2785},
57696         {"cvmx_pcieep_cfg464"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1055,   4,      2789},
57697         {"cvmx_pcieep_cfg465"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1056,   4,      2793},
57698         {"cvmx_pcieep_cfg466"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1057,   7,      2797},
57699         {"cvmx_pcieep_cfg467"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1058,   5,      2804},
57700         {"cvmx_pcieep_cfg468"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1059,   5,      2809},
57701         {"cvmx_pcieep_cfg490"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1060,   4,      2814},
57702         {"cvmx_pcieep_cfg491"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1061,   4,      2818},
57703         {"cvmx_pcieep_cfg492"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1062,   4,      2822},
57704         {"cvmx_pcieep_cfg516"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1063,   1,      2826},
57705         {"cvmx_pcieep_cfg517"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1064,   1,      2827},
57706         {"cvmx_pcierc#_cfg000"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1065,   2,      2828},
57707         {"cvmx_pcierc#_cfg001"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1067,   24,     2830},
57708         {"cvmx_pcierc#_cfg002"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1069,   4,      2854},
57709         {"cvmx_pcierc#_cfg003"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1071,   5,      2858},
57710         {"cvmx_pcierc#_cfg004"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1073,   1,      2863},
57711         {"cvmx_pcierc#_cfg005"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1075,   1,      2864},
57712         {"cvmx_pcierc#_cfg006"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1077,   4,      2865},
57713         {"cvmx_pcierc#_cfg007"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1079,   17,     2869},
57714         {"cvmx_pcierc#_cfg008"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1081,   4,      2886},
57715         {"cvmx_pcierc#_cfg009"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1083,   6,      2890},
57716         {"cvmx_pcierc#_cfg010"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1085,   1,      2896},
57717         {"cvmx_pcierc#_cfg011"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1087,   1,      2897},
57718         {"cvmx_pcierc#_cfg012"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1089,   2,      2898},
57719         {"cvmx_pcierc#_cfg013"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1091,   2,      2900},
57720         {"cvmx_pcierc#_cfg014"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1093,   1,      2902},
57721         {"cvmx_pcierc#_cfg015"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1095,   15,     2903},
57722         {"cvmx_pcierc#_cfg016"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1097,   10,     2918},
57723         {"cvmx_pcierc#_cfg017"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1099,   12,     2928},
57724         {"cvmx_pcierc#_cfg020"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1101,   7,      2940},
57725         {"cvmx_pcierc#_cfg021"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1103,   2,      2947},
57726         {"cvmx_pcierc#_cfg022"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1105,   1,      2949},
57727         {"cvmx_pcierc#_cfg023"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1107,   2,      2950},
57728         {"cvmx_pcierc#_cfg028"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1109,   7,      2952},
57729         {"cvmx_pcierc#_cfg029"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1111,   11,     2959},
57730         {"cvmx_pcierc#_cfg030"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1113,   19,     2970},
57731         {"cvmx_pcierc#_cfg031"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1115,   11,     2989},
57732         {"cvmx_pcierc#_cfg032"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1117,   20,     3000},
57733         {"cvmx_pcierc#_cfg033"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1119,   12,     3020},
57734         {"cvmx_pcierc#_cfg034"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1121,   22,     3032},
57735         {"cvmx_pcierc#_cfg035"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1123,   8,      3054},
57736         {"cvmx_pcierc#_cfg036"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1125,   4,      3062},
57737         {"cvmx_pcierc#_cfg037"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1127,   3,      3066},
57738         {"cvmx_pcierc#_cfg038"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1129,   3,      3069},
57739         {"cvmx_pcierc#_cfg039"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1131,   1,      3072},
57740         {"cvmx_pcierc#_cfg040"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1133,   1,      3073},
57741         {"cvmx_pcierc#_cfg041"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1135,   1,      3074},
57742         {"cvmx_pcierc#_cfg042"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1137,   1,      3075},
57743         {"cvmx_pcierc#_cfg064"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1139,   3,      3076},
57744         {"cvmx_pcierc#_cfg065"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1141,   14,     3079},
57745         {"cvmx_pcierc#_cfg066"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1143,   14,     3093},
57746         {"cvmx_pcierc#_cfg067"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1145,   14,     3107},
57747         {"cvmx_pcierc#_cfg068"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1147,   9,      3121},
57748         {"cvmx_pcierc#_cfg069"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1149,   9,      3130},
57749         {"cvmx_pcierc#_cfg070"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1151,   6,      3139},
57750         {"cvmx_pcierc#_cfg071"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1153,   1,      3145},
57751         {"cvmx_pcierc#_cfg072"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1155,   1,      3146},
57752         {"cvmx_pcierc#_cfg073"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1157,   1,      3147},
57753         {"cvmx_pcierc#_cfg074"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1159,   1,      3148},
57754         {"cvmx_pcierc#_cfg075"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1161,   4,      3149},
57755         {"cvmx_pcierc#_cfg076"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1163,   9,      3153},
57756         {"cvmx_pcierc#_cfg077"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1165,   2,      3162},
57757         {"cvmx_pcierc#_cfg448"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1167,   2,      3164},
57758         {"cvmx_pcierc#_cfg449"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1169,   1,      3166},
57759         {"cvmx_pcierc#_cfg450"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1171,   6,      3167},
57760         {"cvmx_pcierc#_cfg451"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1173,   6,      3173},
57761         {"cvmx_pcierc#_cfg452"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1175,   13,     3179},
57762         {"cvmx_pcierc#_cfg453"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1177,   5,      3192},
57763         {"cvmx_pcierc#_cfg454"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1179,   8,      3197},
57764         {"cvmx_pcierc#_cfg455"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1181,   19,     3205},
57765         {"cvmx_pcierc#_cfg456"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1183,   3,      3224},
57766         {"cvmx_pcierc#_cfg458"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1185,   1,      3227},
57767         {"cvmx_pcierc#_cfg459"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1187,   1,      3228},
57768         {"cvmx_pcierc#_cfg460"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1189,   3,      3229},
57769         {"cvmx_pcierc#_cfg461"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1191,   3,      3232},
57770         {"cvmx_pcierc#_cfg462"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1193,   3,      3235},
57771         {"cvmx_pcierc#_cfg463"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1195,   4,      3238},
57772         {"cvmx_pcierc#_cfg464"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1197,   4,      3242},
57773         {"cvmx_pcierc#_cfg465"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1199,   4,      3246},
57774         {"cvmx_pcierc#_cfg466"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1201,   7,      3250},
57775         {"cvmx_pcierc#_cfg467"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1203,   5,      3257},
57776         {"cvmx_pcierc#_cfg468"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1205,   5,      3262},
57777         {"cvmx_pcierc#_cfg490"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1207,   4,      3267},
57778         {"cvmx_pcierc#_cfg491"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1209,   4,      3271},
57779         {"cvmx_pcierc#_cfg492"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1211,   4,      3275},
57780         {"cvmx_pcierc#_cfg516"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1213,   1,      3279},
57781         {"cvmx_pcierc#_cfg517"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1215,   1,      3280},
57782         {"cvmx_pcs#_an#_adv_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1217,   9,      3281},
57783         {"cvmx_pcs#_an#_ext_st_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1221,   6,      3290},
57784         {"cvmx_pcs#_an#_lp_abil_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1225,   9,      3296},
57785         {"cvmx_pcs#_an#_results_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1229,   6,      3305},
57786         {"cvmx_pcs#_int#_en_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1233,   13,     3311},
57787         {"cvmx_pcs#_int#_reg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1237,   13,     3324},
57788         {"cvmx_pcs#_link#_timer_count_reg",     CVMX_CSR_DB_TYPE_RSL,   64,     1241,   2,      3337},
57789         {"cvmx_pcs#_log_anl#_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1245,   4,      3339},
57790         {"cvmx_pcs#_misc#_ctl_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1249,   8,      3343},
57791         {"cvmx_pcs#_mr#_control_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1253,   13,     3351},
57792         {"cvmx_pcs#_mr#_status_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1257,   17,     3364},
57793         {"cvmx_pcs#_rx#_states_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1261,   7,      3381},
57794         {"cvmx_pcs#_rx#_sync_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1265,   3,      3388},
57795         {"cvmx_pcs#_sgm#_an_adv_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1269,   8,      3391},
57796         {"cvmx_pcs#_sgm#_lp_adv_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1273,   7,      3399},
57797         {"cvmx_pcs#_tx#_states_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1277,   4,      3406},
57798         {"cvmx_pcs#_tx_rx#_polarity_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     1281,   5,      3410},
57799         {"cvmx_pcsx#_10gbx_status_reg" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1285,   8,      3415},
57800         {"cvmx_pcsx#_bist_status_reg"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1287,   2,      3423},
57801         {"cvmx_pcsx#_bit_lock_status_reg",      CVMX_CSR_DB_TYPE_RSL,   64,     1289,   5,      3425},
57802         {"cvmx_pcsx#_control1_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1291,   10,     3430},
57803         {"cvmx_pcsx#_control2_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1293,   2,      3440},
57804         {"cvmx_pcsx#_int_en_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1295,   7,      3442},
57805         {"cvmx_pcsx#_int_reg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1297,   7,      3449},
57806         {"cvmx_pcsx#_log_anl_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1299,   6,      3456},
57807         {"cvmx_pcsx#_misc_ctl_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1301,   5,      3462},
57808         {"cvmx_pcsx#_rx_sync_states_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     1303,   5,      3467},
57809         {"cvmx_pcsx#_spd_abil_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1305,   3,      3472},
57810         {"cvmx_pcsx#_status1_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1307,   6,      3475},
57811         {"cvmx_pcsx#_status2_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1309,   9,      3481},
57812         {"cvmx_pcsx#_tx_rx_polarity_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     1311,   3,      3490},
57813         {"cvmx_pcsx#_tx_rx_states_reg" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1313,   9,      3493},
57814         {"cvmx_pesc#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1315,   13,     3502},
57815         {"cvmx_pesc#_bist_status2"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1317,   15,     3515},
57816         {"cvmx_pesc#_cfg_rd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1319,   2,      3530},
57817         {"cvmx_pesc#_cfg_wr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1321,   2,      3532},
57818         {"cvmx_pesc#_cpl_lut_valid"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1323,   2,      3534},
57819         {"cvmx_pesc#_ctl_status"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1325,   16,     3536},
57820         {"cvmx_pesc#_ctl_status2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1327,   2,      3552},
57821         {"cvmx_pesc#_dbg_info"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1329,   32,     3554},
57822         {"cvmx_pesc#_dbg_info_en"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1331,   32,     3586},
57823         {"cvmx_pesc#_diag_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1333,   5,      3618},
57824         {"cvmx_pesc#_p2n_bar0_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1335,   2,      3623},
57825         {"cvmx_pesc#_p2n_bar1_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1337,   2,      3625},
57826         {"cvmx_pesc#_p2n_bar2_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1339,   2,      3627},
57827         {"cvmx_pesc#_p2p_bar#_end"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1341,   2,      3629},
57828         {"cvmx_pesc#_p2p_bar#_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1349,   2,      3631},
57829         {"cvmx_pesc#_tlp_credits"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1357,   8,      3633},
57830         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1359,   2,      3641},
57831         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1360,   4,      3643},
57832         {"cvmx_pip_dsa_src_grp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1364,   16,     3647},
57833         {"cvmx_pip_dsa_vid_grp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1365,   16,     3663},
57834         {"cvmx_pip_frm_len_chk#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1366,   3,      3679},
57835         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1368,   8,      3682},
57836         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1369,   22,     3690},
57837         {"cvmx_pip_hg_pri_qos"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1370,   6,      3712},
57838         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1371,   14,     3718},
57839         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1372,   14,     3732},
57840         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1373,   2,      3746},
57841         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1374,   28,     3748},
57842         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1382,   25,     3776},
57843         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1390,   2,      3801},
57844         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1454,   4,      3803},
57845         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1462,   9,      3807},
57846         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1470,   2,      3816},
57847         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1471,   2,      3818},
57848         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1472,   2,      3820},
57849         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1480,   2,      3822},
57850         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1488,   2,      3824},
57851         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1496,   2,      3826},
57852         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1504,   2,      3828},
57853         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1512,   2,      3830},
57854         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1520,   2,      3832},
57855         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1528,   2,      3834},
57856         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1536,   2,      3836},
57857         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1544,   2,      3838},
57858         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1552,   2,      3840},
57859         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1553,   2,      3842},
57860         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1561,   2,      3844},
57861         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1569,   2,      3846},
57862         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1577,   2,      3848},
57863         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1641,   2,      3850},
57864         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1642,   3,      3852},
57865         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1643,   3,      3855},
57866         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1644,   2,      3858},
57867         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1645,   2,      3860},
57868         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1646,   4,      3862},
57869         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1647,   5,      3866},
57870         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1648,   4,      3871},
57871         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1649,   8,      3875},
57872         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1650,   4,      3883},
57873         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1651,   5,      3887},
57874         {"cvmx_pko_mem_debug14"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1652,   1,      3892},
57875         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1653,   5,      3893},
57876         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1654,   1,      3898},
57877         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1655,   13,     3899},
57878         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1656,   4,      3912},
57879         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1657,   13,     3916},
57880         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1658,   6,      3929},
57881         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1659,   9,      3935},
57882         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1660,   4,      3944},
57883         {"cvmx_pko_mem_port_ptrs"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1661,   7,      3948},
57884         {"cvmx_pko_mem_port_qos"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1662,   5,      3955},
57885         {"cvmx_pko_mem_port_rate0"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1663,   5,      3960},
57886         {"cvmx_pko_mem_port_rate1"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1664,   4,      3965},
57887         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1665,   9,      3969},
57888         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1666,   5,      3978},
57889         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1667,   16,     3983},
57890         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1668,   4,      3999},
57891         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1669,   1,      4003},
57892         {"cvmx_pko_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1670,   1,      4004},
57893         {"cvmx_pko_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1671,   1,      4005},
57894         {"cvmx_pko_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1672,   1,      4006},
57895         {"cvmx_pko_reg_engine_inflight",        CVMX_CSR_DB_TYPE_RSL,   64,     1673,   11,     4007},
57896         {"cvmx_pko_reg_engine_thresh"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1674,   2,      4018},
57897         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1675,   4,      4020},
57898         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1676,   5,      4024},
57899         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1677,   3,      4029},
57900         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1678,   4,      4032},
57901         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1679,   2,      4036},
57902         {"cvmx_pko_reg_queue_ptrs1"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1680,   3,      4038},
57903         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1681,   3,      4041},
57904         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1682,   12,     4044},
57905         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1683,   2,      4056},
57906         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1684,   13,     4058},
57907         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1685,   3,      4071},
57908         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1686,   2,      4074},
57909         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1694,   2,      4076},
57910         {"cvmx_pow_iq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1695,   2,      4078},
57911         {"cvmx_pow_iq_int_en"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1696,   2,      4080},
57912         {"cvmx_pow_iq_thr#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1697,   2,      4082},
57913         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     1705,   2,      4084},
57914         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1706,   2,      4086},
57915         {"cvmx_pow_pf_rst_msk"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     1707,   2,      4088},
57916         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1708,   10,     4090},
57917         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1712,   5,      4100},
57918         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     1720,   10,     4105},
57919         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     1728,   2,      4115},
57920         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1729,   2,      4117},
57921         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1730,   2,      4119},
57922         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1738,   3,      4121},
57923         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1739,   6,      4124},
57924         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     1755,   5,      4130},
57925         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     1756,   7,      4135},
57926         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     1772,   2,      4142},
57927         {"cvmx_rad_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1788,   1,      4144},
57928         {"cvmx_rad_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1789,   1,      4145},
57929         {"cvmx_rad_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1790,   1,      4146},
57930         {"cvmx_rad_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1791,   5,      4147},
57931         {"cvmx_rad_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1792,   5,      4152},
57932         {"cvmx_rad_reg_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1793,   4,      4157},
57933         {"cvmx_rad_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1794,   10,     4161},
57934         {"cvmx_rad_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1795,   1,      4171},
57935         {"cvmx_rad_reg_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1796,   3,      4172},
57936         {"cvmx_rad_reg_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1797,   7,      4175},
57937         {"cvmx_rad_reg_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1798,   2,      4182},
57938         {"cvmx_rad_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1799,   1,      4184},
57939         {"cvmx_rad_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1800,   1,      4185},
57940         {"cvmx_rad_reg_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1801,   1,      4186},
57941         {"cvmx_rad_reg_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1802,   18,     4187},
57942         {"cvmx_rad_reg_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1803,   3,      4205},
57943         {"cvmx_rad_reg_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1804,   2,      4208},
57944         {"cvmx_rad_reg_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1805,   3,      4210},
57945         {"cvmx_rad_reg_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1806,   7,      4213},
57946         {"cvmx_rad_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1807,   2,      4220},
57947         {"cvmx_rad_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1808,   2,      4222},
57948         {"cvmx_rad_reg_polynomial"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1809,   2,      4224},
57949         {"cvmx_rad_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1810,   3,      4226},
57950         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1811,   3,      4229},
57951         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1812,   7,      4232},
57952         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1813,   10,     4239},
57953         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     1815,   6,      4249},
57954         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1817,   2,      4255},
57955         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1819,   4,      4257},
57956         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1821,   4,      4261},
57957         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1823,   6,      4265},
57958         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1824,   3,      4271},
57959         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1825,   5,      4274},
57960         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1826,   4,      4279},
57961         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1827,   6,      4283},
57962         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1828,   4,      4289},
57963         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1829,   2,      4293},
57964         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1830,   4,      4295},
57965         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1831,   2,      4299},
57966         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1832,   3,      4301},
57967         {"cvmx_tra_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1833,   4,      4304},
57968         {"cvmx_tra_ctl"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     1834,   12,     4308},
57969         {"cvmx_tra_cycles_since"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1835,   3,      4320},
57970         {"cvmx_tra_cycles_since1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1836,   5,      4323},
57971         {"cvmx_tra_filt_adr_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1837,   2,      4328},
57972         {"cvmx_tra_filt_adr_msk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1838,   2,      4330},
57973         {"cvmx_tra_filt_cmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1839,   18,     4332},
57974         {"cvmx_tra_filt_did"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1840,   12,     4350},
57975         {"cvmx_tra_filt_sid"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1841,   6,      4362},
57976         {"cvmx_tra_int_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1842,   5,      4368},
57977         {"cvmx_tra_read_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1843,   1,      4373},
57978         {"cvmx_tra_trig0_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1844,   2,      4374},
57979         {"cvmx_tra_trig0_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1845,   2,      4376},
57980         {"cvmx_tra_trig0_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1846,   18,     4378},
57981         {"cvmx_tra_trig0_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1847,   12,     4396},
57982         {"cvmx_tra_trig0_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1848,   6,      4408},
57983         {"cvmx_tra_trig1_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1849,   2,      4414},
57984         {"cvmx_tra_trig1_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1850,   2,      4416},
57985         {"cvmx_tra_trig1_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1851,   18,     4418},
57986         {"cvmx_tra_trig1_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1852,   12,     4436},
57987         {"cvmx_tra_trig1_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1853,   6,      4448},
57988         {"cvmx_usbc#_daint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1854,   2,      4454},
57989         {"cvmx_usbc#_daintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1856,   2,      4456},
57990         {"cvmx_usbc#_dcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1858,   8,      4458},
57991         {"cvmx_usbc#_dctl"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1860,   11,     4466},
57992         {"cvmx_usbc#_diepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1862,   15,     4477},
57993         {"cvmx_usbc#_diepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1872,   8,      4492},
57994         {"cvmx_usbc#_diepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1882,   8,      4500},
57995         {"cvmx_usbc#_dieptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1884,   4,      4508},
57996         {"cvmx_usbc#_doepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1894,   15,     4512},
57997         {"cvmx_usbc#_doepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1904,   6,      4527},
57998         {"cvmx_usbc#_doepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1914,   6,      4533},
57999         {"cvmx_usbc#_doeptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1916,   4,      4539},
58000         {"cvmx_usbc#_dptxfsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1926,   2,      4543},
58001         {"cvmx_usbc#_dsts"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     1934,   6,      4545},
58002         {"cvmx_usbc#_dtknqr1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1936,   4,      4551},
58003         {"cvmx_usbc#_dtknqr2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1938,   1,      4555},
58004         {"cvmx_usbc#_dtknqr3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1940,   1,      4556},
58005         {"cvmx_usbc#_dtknqr4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1942,   1,      4557},
58006         {"cvmx_usbc#_gahbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1944,   7,      4558},
58007         {"cvmx_usbc#_ghwcfg1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1946,   1,      4565},
58008         {"cvmx_usbc#_ghwcfg2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1948,   14,     4566},
58009         {"cvmx_usbc#_ghwcfg3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1950,   10,     4580},
58010         {"cvmx_usbc#_ghwcfg4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1952,   14,     4590},
58011         {"cvmx_usbc#_gintmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1954,   32,     4604},
58012         {"cvmx_usbc#_gintsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1956,   32,     4636},
58013         {"cvmx_usbc#_gnptxfsiz"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     1958,   2,      4668},
58014         {"cvmx_usbc#_gnptxsts"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1960,   4,      4670},
58015         {"cvmx_usbc#_gotgctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1962,   13,     4674},
58016         {"cvmx_usbc#_gotgint"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1964,   10,     4687},
58017         {"cvmx_usbc#_grstctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1966,   10,     4697},
58018         {"cvmx_usbc#_grxfsiz"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1968,   2,      4707},
58019         {"cvmx_usbc#_grxstspd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1970,   6,      4709},
58020         {"cvmx_usbc#_grxstsph"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1972,   5,      4715},
58021         {"cvmx_usbc#_grxstsrd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1974,   6,      4720},
58022         {"cvmx_usbc#_grxstsrh"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1976,   5,      4726},
58023         {"cvmx_usbc#_gsnpsid"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1978,   1,      4731},
58024         {"cvmx_usbc#_gusbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1980,   13,     4732},
58025         {"cvmx_usbc#_haint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     1982,   2,      4745},
58026         {"cvmx_usbc#_haintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     1984,   2,      4747},
58027         {"cvmx_usbc#_hcchar#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     1986,   11,     4749},
58028         {"cvmx_usbc#_hcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2002,   3,      4760},
58029         {"cvmx_usbc#_hcint#"           ,        CVMX_CSR_DB_TYPE_NCB,   32,     2004,   12,     4763},
58030         {"cvmx_usbc#_hcintmsk#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2020,   12,     4775},
58031         {"cvmx_usbc#_hcsplt#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2036,   6,      4787},
58032         {"cvmx_usbc#_hctsiz#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2052,   4,      4793},
58033         {"cvmx_usbc#_hfir"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2068,   2,      4797},
58034         {"cvmx_usbc#_hfnum"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     2070,   2,      4799},
58035         {"cvmx_usbc#_hprt"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2072,   15,     4801},
58036         {"cvmx_usbc#_hptxfsiz"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2074,   2,      4816},
58037         {"cvmx_usbc#_hptxsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2076,   3,      4818},
58038         {"cvmx_usbc#_nptxdfifo#"       ,        CVMX_CSR_DB_TYPE_NCB,   32,     2078,   1,      4821},
58039         {"cvmx_usbc#_pcgcctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2094,   6,      4822},
58040         {"cvmx_usbn#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2096,   8,      4828},
58041         {"cvmx_usbn#_clk_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2098,   15,     4836},
58042         {"cvmx_usbn#_ctl_status"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     2100,   6,      4851},
58043         {"cvmx_usbn#_dma0_inb_chn0"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2102,   2,      4857},
58044         {"cvmx_usbn#_dma0_inb_chn1"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2104,   2,      4859},
58045         {"cvmx_usbn#_dma0_inb_chn2"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2106,   2,      4861},
58046         {"cvmx_usbn#_dma0_inb_chn3"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2108,   2,      4863},
58047         {"cvmx_usbn#_dma0_inb_chn4"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2110,   2,      4865},
58048         {"cvmx_usbn#_dma0_inb_chn5"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2112,   2,      4867},
58049         {"cvmx_usbn#_dma0_inb_chn6"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2114,   2,      4869},
58050         {"cvmx_usbn#_dma0_inb_chn7"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2116,   2,      4871},
58051         {"cvmx_usbn#_dma0_outb_chn0"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2118,   2,      4873},
58052         {"cvmx_usbn#_dma0_outb_chn1"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2120,   2,      4875},
58053         {"cvmx_usbn#_dma0_outb_chn2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2122,   2,      4877},
58054         {"cvmx_usbn#_dma0_outb_chn3"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2124,   2,      4879},
58055         {"cvmx_usbn#_dma0_outb_chn4"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2126,   2,      4881},
58056         {"cvmx_usbn#_dma0_outb_chn5"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2128,   2,      4883},
58057         {"cvmx_usbn#_dma0_outb_chn6"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2130,   2,      4885},
58058         {"cvmx_usbn#_dma0_outb_chn7"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2132,   2,      4887},
58059         {"cvmx_usbn#_dma_test"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2134,   7,      4889},
58060         {"cvmx_usbn#_int_enb"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2136,   34,     4896},
58061         {"cvmx_usbn#_int_sum"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2138,   34,     4930},
58062         {"cvmx_usbn#_usbp_ctl_status"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2140,   35,     4964},
58063         {NULL,0,0,0,0,0}
58064 };
58065 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xxp1[] = {
58066         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
58067         {"AGL_GMX_BAD_REG"             ,           0x11800E0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
58068         {"AGL_GMX_BIST"                ,           0x11800E0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
58069         {"AGL_GMX_DRV_CTL"             ,           0x11800E00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
58070         {"AGL_GMX_INF_MODE"            ,           0x11800E00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
58071         {"AGL_GMX_PRT0_CFG"            ,           0x11800E0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
58072         {"AGL_GMX_PRT1_CFG"            ,           0x11800E0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
58073         {"AGL_GMX_RX0_ADR_CAM0"        ,           0x11800E0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
58074         {"AGL_GMX_RX1_ADR_CAM0"        ,           0x11800E0000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
58075         {"AGL_GMX_RX0_ADR_CAM1"        ,           0x11800E0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
58076         {"AGL_GMX_RX1_ADR_CAM1"        ,           0x11800E0000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
58077         {"AGL_GMX_RX0_ADR_CAM2"        ,           0x11800E0000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
58078         {"AGL_GMX_RX1_ADR_CAM2"        ,           0x11800E0000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
58079         {"AGL_GMX_RX0_ADR_CAM3"        ,           0x11800E0000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
58080         {"AGL_GMX_RX1_ADR_CAM3"        ,           0x11800E0000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
58081         {"AGL_GMX_RX0_ADR_CAM4"        ,           0x11800E00001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
58082         {"AGL_GMX_RX1_ADR_CAM4"        ,           0x11800E00009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
58083         {"AGL_GMX_RX0_ADR_CAM5"        ,           0x11800E00001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
58084         {"AGL_GMX_RX1_ADR_CAM5"        ,           0x11800E00009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
58085         {"AGL_GMX_RX0_ADR_CAM_EN"      ,           0x11800E0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
58086         {"AGL_GMX_RX1_ADR_CAM_EN"      ,           0x11800E0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
58087         {"AGL_GMX_RX0_ADR_CTL"         ,           0x11800E0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
58088         {"AGL_GMX_RX1_ADR_CTL"         ,           0x11800E0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
58089         {"AGL_GMX_RX0_DECISION"        ,           0x11800E0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
58090         {"AGL_GMX_RX1_DECISION"        ,           0x11800E0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
58091         {"AGL_GMX_RX0_FRM_CHK"         ,           0x11800E0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
58092         {"AGL_GMX_RX1_FRM_CHK"         ,           0x11800E0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
58093         {"AGL_GMX_RX0_FRM_CTL"         ,           0x11800E0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
58094         {"AGL_GMX_RX1_FRM_CTL"         ,           0x11800E0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
58095         {"AGL_GMX_RX0_FRM_MAX"         ,           0x11800E0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
58096         {"AGL_GMX_RX1_FRM_MAX"         ,           0x11800E0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
58097         {"AGL_GMX_RX0_FRM_MIN"         ,           0x11800E0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
58098         {"AGL_GMX_RX1_FRM_MIN"         ,           0x11800E0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
58099         {"AGL_GMX_RX0_IFG"             ,           0x11800E0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
58100         {"AGL_GMX_RX1_IFG"             ,           0x11800E0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
58101         {"AGL_GMX_RX0_INT_EN"          ,           0x11800E0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
58102         {"AGL_GMX_RX1_INT_EN"          ,           0x11800E0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
58103         {"AGL_GMX_RX0_INT_REG"         ,           0x11800E0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
58104         {"AGL_GMX_RX1_INT_REG"         ,           0x11800E0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
58105         {"AGL_GMX_RX0_JABBER"          ,           0x11800E0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
58106         {"AGL_GMX_RX1_JABBER"          ,           0x11800E0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
58107         {"AGL_GMX_RX0_PAUSE_DROP_TIME" ,           0x11800E0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
58108         {"AGL_GMX_RX1_PAUSE_DROP_TIME" ,           0x11800E0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
58109         {"AGL_GMX_RX0_STATS_CTL"       ,           0x11800E0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     23},
58110         {"AGL_GMX_RX1_STATS_CTL"       ,           0x11800E0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     23},
58111         {"AGL_GMX_RX0_STATS_OCTS"      ,           0x11800E0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     24},
58112         {"AGL_GMX_RX1_STATS_OCTS"      ,           0x11800E0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     24},
58113         {"AGL_GMX_RX0_STATS_OCTS_CTL"  ,           0x11800E0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     25},
58114         {"AGL_GMX_RX1_STATS_OCTS_CTL"  ,           0x11800E0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     25},
58115         {"AGL_GMX_RX0_STATS_OCTS_DMAC" ,           0x11800E00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     26},
58116         {"AGL_GMX_RX1_STATS_OCTS_DMAC" ,           0x11800E00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     26},
58117         {"AGL_GMX_RX0_STATS_OCTS_DRP"  ,           0x11800E00000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     27},
58118         {"AGL_GMX_RX1_STATS_OCTS_DRP"  ,           0x11800E00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     27},
58119         {"AGL_GMX_RX0_STATS_PKTS"      ,           0x11800E0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     28},
58120         {"AGL_GMX_RX1_STATS_PKTS"      ,           0x11800E0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     28},
58121         {"AGL_GMX_RX0_STATS_PKTS_BAD"  ,           0x11800E00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     29},
58122         {"AGL_GMX_RX1_STATS_PKTS_BAD"  ,           0x11800E00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     29},
58123         {"AGL_GMX_RX0_STATS_PKTS_CTL"  ,           0x11800E0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     30},
58124         {"AGL_GMX_RX1_STATS_PKTS_CTL"  ,           0x11800E0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     30},
58125         {"AGL_GMX_RX0_STATS_PKTS_DMAC" ,           0x11800E00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     31},
58126         {"AGL_GMX_RX1_STATS_PKTS_DMAC" ,           0x11800E00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     31},
58127         {"AGL_GMX_RX0_STATS_PKTS_DRP"  ,           0x11800E00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     32},
58128         {"AGL_GMX_RX1_STATS_PKTS_DRP"  ,           0x11800E00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     32},
58129         {"AGL_GMX_RX0_UDD_SKP"         ,           0x11800E0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     33},
58130         {"AGL_GMX_RX1_UDD_SKP"         ,           0x11800E0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     33},
58131         {"AGL_GMX_RX_BP_DROP0"         ,           0x11800E0000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     34},
58132         {"AGL_GMX_RX_BP_DROP1"         ,           0x11800E0000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     34},
58133         {"AGL_GMX_RX_BP_OFF0"          ,           0x11800E0000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     35},
58134         {"AGL_GMX_RX_BP_OFF1"          ,           0x11800E0000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     35},
58135         {"AGL_GMX_RX_BP_ON0"           ,           0x11800E0000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     36},
58136         {"AGL_GMX_RX_BP_ON1"           ,           0x11800E0000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     36},
58137         {"AGL_GMX_RX_PRT_INFO"         ,           0x11800E00004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
58138         {"AGL_GMX_RX_TX_STATUS"        ,           0x11800E00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
58139         {"AGL_GMX_SMAC0"               ,           0x11800E0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     39},
58140         {"AGL_GMX_SMAC1"               ,           0x11800E0000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     39},
58141         {"AGL_GMX_STAT_BP"             ,           0x11800E0000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
58142         {"AGL_GMX_TX0_APPEND"          ,           0x11800E0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
58143         {"AGL_GMX_TX1_APPEND"          ,           0x11800E0000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
58144         {"AGL_GMX_TX0_CTL"             ,           0x11800E0000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     42},
58145         {"AGL_GMX_TX1_CTL"             ,           0x11800E0000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     42},
58146         {"AGL_GMX_TX0_MIN_PKT"         ,           0x11800E0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     43},
58147         {"AGL_GMX_TX1_MIN_PKT"         ,           0x11800E0000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     43},
58148         {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",         0x11800E0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
58149         {"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",         0x11800E0000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
58150         {"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,           0x11800E0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     45},
58151         {"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,           0x11800E0000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     45},
58152         {"AGL_GMX_TX0_PAUSE_TOGO"      ,           0x11800E0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
58153         {"AGL_GMX_TX1_PAUSE_TOGO"      ,           0x11800E0000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
58154         {"AGL_GMX_TX0_PAUSE_ZERO"      ,           0x11800E0000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
58155         {"AGL_GMX_TX1_PAUSE_ZERO"      ,           0x11800E0000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
58156         {"AGL_GMX_TX0_SOFT_PAUSE"      ,           0x11800E0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
58157         {"AGL_GMX_TX1_SOFT_PAUSE"      ,           0x11800E0000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
58158         {"AGL_GMX_TX0_STAT0"           ,           0x11800E0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
58159         {"AGL_GMX_TX1_STAT0"           ,           0x11800E0000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
58160         {"AGL_GMX_TX0_STAT1"           ,           0x11800E0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
58161         {"AGL_GMX_TX1_STAT1"           ,           0x11800E0000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
58162         {"AGL_GMX_TX0_STAT2"           ,           0x11800E0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
58163         {"AGL_GMX_TX1_STAT2"           ,           0x11800E0000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
58164         {"AGL_GMX_TX0_STAT3"           ,           0x11800E0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
58165         {"AGL_GMX_TX1_STAT3"           ,           0x11800E0000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
58166         {"AGL_GMX_TX0_STAT4"           ,           0x11800E00002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
58167         {"AGL_GMX_TX1_STAT4"           ,           0x11800E0000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
58168         {"AGL_GMX_TX0_STAT5"           ,           0x11800E00002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
58169         {"AGL_GMX_TX1_STAT5"           ,           0x11800E0000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
58170         {"AGL_GMX_TX0_STAT6"           ,           0x11800E00002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
58171         {"AGL_GMX_TX1_STAT6"           ,           0x11800E0000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
58172         {"AGL_GMX_TX0_STAT7"           ,           0x11800E00002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
58173         {"AGL_GMX_TX1_STAT7"           ,           0x11800E0000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
58174         {"AGL_GMX_TX0_STAT8"           ,           0x11800E00002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
58175         {"AGL_GMX_TX1_STAT8"           ,           0x11800E0000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
58176         {"AGL_GMX_TX0_STAT9"           ,           0x11800E00002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
58177         {"AGL_GMX_TX1_STAT9"           ,           0x11800E0000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
58178         {"AGL_GMX_TX0_STATS_CTL"       ,           0x11800E0000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
58179         {"AGL_GMX_TX1_STATS_CTL"       ,           0x11800E0000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
58180         {"AGL_GMX_TX0_THRESH"          ,           0x11800E0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
58181         {"AGL_GMX_TX1_THRESH"          ,           0x11800E0000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
58182         {"AGL_GMX_TX_BP"               ,           0x11800E00004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
58183         {"AGL_GMX_TX_COL_ATTEMPT"      ,           0x11800E0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
58184         {"AGL_GMX_TX_IFG"              ,           0x11800E0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
58185         {"AGL_GMX_TX_INT_EN"           ,           0x11800E0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
58186         {"AGL_GMX_TX_INT_REG"          ,           0x11800E0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
58187         {"AGL_GMX_TX_JAM"              ,           0x11800E0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
58188         {"AGL_GMX_TX_LFSR"             ,           0x11800E00004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
58189         {"AGL_GMX_TX_OVR_BP"           ,           0x11800E00004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
58190         {"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,           0x11800E00004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
58191         {"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,           0x11800E00004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
58192         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     71},
58193         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     72},
58194         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     73},
58195         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     74},
58196         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
58197         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
58198         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
58199         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
58200         {"CIU_INT4_EN0"                ,           0x1070000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
58201         {"CIU_INT5_EN0"                ,           0x1070000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
58202         {"CIU_INT6_EN0"                ,           0x1070000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
58203         {"CIU_INT7_EN0"                ,           0x1070000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
58204         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
58205         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
58206         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
58207         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
58208         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
58209         {"CIU_INT4_EN1"                ,           0x1070000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
58210         {"CIU_INT5_EN1"                ,           0x1070000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
58211         {"CIU_INT6_EN1"                ,           0x1070000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
58212         {"CIU_INT7_EN1"                ,           0x1070000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
58213         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
58214         {"CIU_INT0_EN4_0"              ,           0x1070000000C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
58215         {"CIU_INT1_EN4_0"              ,           0x1070000000C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
58216         {"CIU_INT2_EN4_0"              ,           0x1070000000CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
58217         {"CIU_INT3_EN4_0"              ,           0x1070000000CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
58218         {"CIU_INT0_EN4_1"              ,           0x1070000000C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
58219         {"CIU_INT1_EN4_1"              ,           0x1070000000C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
58220         {"CIU_INT2_EN4_1"              ,           0x1070000000CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
58221         {"CIU_INT3_EN4_1"              ,           0x1070000000CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
58222         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
58223         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
58224         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
58225         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
58226         {"CIU_INT4_SUM0"               ,           0x1070000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
58227         {"CIU_INT5_SUM0"               ,           0x1070000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
58228         {"CIU_INT6_SUM0"               ,           0x1070000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
58229         {"CIU_INT7_SUM0"               ,           0x1070000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
58230         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
58231         {"CIU_INT0_SUM4"               ,           0x1070000000C00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
58232         {"CIU_INT1_SUM4"               ,           0x1070000000C08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
58233         {"CIU_INT2_SUM4"               ,           0x1070000000C10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
58234         {"CIU_INT3_SUM4"               ,           0x1070000000C18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
58235         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
58236         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
58237         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
58238         {"CIU_MBOX_CLR2"               ,           0x1070000000690ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
58239         {"CIU_MBOX_CLR3"               ,           0x1070000000698ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
58240         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
58241         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
58242         {"CIU_MBOX_SET2"               ,           0x1070000000610ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
58243         {"CIU_MBOX_SET3"               ,           0x1070000000618ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
58244         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
58245         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
58246         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
58247         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
58248         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
58249         {"CIU_PP_POKE2"                ,           0x1070000000590ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
58250         {"CIU_PP_POKE3"                ,           0x1070000000598ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
58251         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
58252         {"CIU_QLM_DCOK"                ,           0x1070000000760ull,  CVMX_CSR_DB_TYPE_NCB,   64,     89},
58253         {"CIU_QLM_JTGC"                ,           0x1070000000768ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
58254         {"CIU_QLM_JTGD"                ,           0x1070000000770ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
58255         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     92},
58256         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     93},
58257         {"CIU_SOFT_PRST1"              ,           0x1070000000758ull,  CVMX_CSR_DB_TYPE_NCB,   64,     94},
58258         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
58259         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
58260         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
58261         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
58262         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
58263         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
58264         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
58265         {"CIU_WDOG2"                   ,           0x1070000000510ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
58266         {"CIU_WDOG3"                   ,           0x1070000000518ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
58267         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     98},
58268         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     99},
58269         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     100},
58270         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     101},
58271         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
58272         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
58273         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
58274         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
58275         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
58276         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
58277         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
58278         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     102},
58279         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
58280         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
58281         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
58282         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
58283         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
58284         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
58285         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
58286         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     103},
58287         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     104},
58288         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     105},
58289         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
58290         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
58291         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
58292         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
58293         {"GMX0_CLK_EN"                 ,           0x11800080007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
58294         {"GMX0_HG2_CONTROL"            ,           0x1180008000550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
58295         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
58296         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
58297         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
58298         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
58299         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
58300         {"GMX0_PRT003_CFG"             ,           0x1180008001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
58301         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
58302         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
58303         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
58304         {"GMX0_RX003_ADR_CAM0"         ,           0x1180008001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
58305         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
58306         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
58307         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
58308         {"GMX0_RX003_ADR_CAM1"         ,           0x1180008001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
58309         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
58310         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
58311         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
58312         {"GMX0_RX003_ADR_CAM2"         ,           0x1180008001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
58313         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
58314         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
58315         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
58316         {"GMX0_RX003_ADR_CAM3"         ,           0x1180008001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
58317         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
58318         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
58319         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
58320         {"GMX0_RX003_ADR_CAM4"         ,           0x11800080019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
58321         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
58322         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
58323         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
58324         {"GMX0_RX003_ADR_CAM5"         ,           0x11800080019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
58325         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
58326         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
58327         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
58328         {"GMX0_RX003_ADR_CAM_EN"       ,           0x1180008001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
58329         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
58330         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
58331         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
58332         {"GMX0_RX003_ADR_CTL"          ,           0x1180008001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
58333         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
58334         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
58335         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
58336         {"GMX0_RX003_DECISION"         ,           0x1180008001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
58337         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
58338         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
58339         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
58340         {"GMX0_RX003_FRM_CHK"          ,           0x1180008001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
58341         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
58342         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
58343         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
58344         {"GMX0_RX003_FRM_CTL"          ,           0x1180008001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
58345         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
58346         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
58347         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
58348         {"GMX0_RX003_IFG"              ,           0x1180008001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
58349         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
58350         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
58351         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
58352         {"GMX0_RX003_INT_EN"           ,           0x1180008001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
58353         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
58354         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
58355         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
58356         {"GMX0_RX003_INT_REG"          ,           0x1180008001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
58357         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
58358         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
58359         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
58360         {"GMX0_RX003_JABBER"           ,           0x1180008001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
58361         {"GMX0_RX000_PAUSE_DROP_TIME"  ,           0x1180008000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
58362         {"GMX0_RX001_PAUSE_DROP_TIME"  ,           0x1180008000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
58363         {"GMX0_RX002_PAUSE_DROP_TIME"  ,           0x1180008001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
58364         {"GMX0_RX003_PAUSE_DROP_TIME"  ,           0x1180008001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
58365         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
58366         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
58367         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
58368         {"GMX0_RX003_STATS_CTL"        ,           0x1180008001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
58369         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
58370         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
58371         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
58372         {"GMX0_RX003_STATS_OCTS"       ,           0x1180008001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
58373         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
58374         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
58375         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
58376         {"GMX0_RX003_STATS_OCTS_CTL"   ,           0x1180008001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
58377         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
58378         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
58379         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
58380         {"GMX0_RX003_STATS_OCTS_DMAC"  ,           0x11800080018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
58381         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
58382         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
58383         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
58384         {"GMX0_RX003_STATS_OCTS_DRP"   ,           0x11800080018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
58385         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
58386         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
58387         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
58388         {"GMX0_RX003_STATS_PKTS"       ,           0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
58389         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
58390         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
58391         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
58392         {"GMX0_RX003_STATS_PKTS_BAD"   ,           0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
58393         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
58394         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
58395         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
58396         {"GMX0_RX003_STATS_PKTS_CTL"   ,           0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
58397         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
58398         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
58399         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
58400         {"GMX0_RX003_STATS_PKTS_DMAC"  ,           0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
58401         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
58402         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
58403         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
58404         {"GMX0_RX003_STATS_PKTS_DRP"   ,           0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
58405         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
58406         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
58407         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
58408         {"GMX0_RX003_UDD_SKP"          ,           0x1180008001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
58409         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
58410         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
58411         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
58412         {"GMX0_RX_BP_DROP003"          ,           0x1180008000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
58413         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
58414         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
58415         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
58416         {"GMX0_RX_BP_OFF003"           ,           0x1180008000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
58417         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
58418         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
58419         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
58420         {"GMX0_RX_BP_ON003"            ,           0x1180008000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
58421         {"GMX0_RX_HG2_STATUS"          ,           0x1180008000548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
58422         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
58423         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
58424         {"GMX0_RX_XAUI_BAD_COL"        ,           0x1180008000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
58425         {"GMX0_RX_XAUI_CTL"            ,           0x1180008000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
58426         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
58427         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
58428         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
58429         {"GMX0_SMAC003"                ,           0x1180008001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
58430         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
58431         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
58432         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
58433         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
58434         {"GMX0_TX003_APPEND"           ,           0x1180008001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
58435         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
58436         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
58437         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
58438         {"GMX0_TX003_BURST"            ,           0x1180008001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
58439         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
58440         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
58441         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
58442         {"GMX0_TX003_CTL"              ,           0x1180008001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
58443         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
58444         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
58445         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
58446         {"GMX0_TX003_MIN_PKT"          ,           0x1180008001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
58447         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
58448         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
58449         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
58450         {"GMX0_TX003_PAUSE_PKT_INTERVAL",          0x1180008001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
58451         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
58452         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
58453         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
58454         {"GMX0_TX003_PAUSE_PKT_TIME"   ,           0x1180008001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
58455         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
58456         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
58457         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
58458         {"GMX0_TX003_PAUSE_TOGO"       ,           0x1180008001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
58459         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
58460         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
58461         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
58462         {"GMX0_TX003_PAUSE_ZERO"       ,           0x1180008001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
58463         {"GMX0_TX000_SGMII_CTL"        ,           0x1180008000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
58464         {"GMX0_TX001_SGMII_CTL"        ,           0x1180008000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
58465         {"GMX0_TX002_SGMII_CTL"        ,           0x1180008001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
58466         {"GMX0_TX003_SGMII_CTL"        ,           0x1180008001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
58467         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
58468         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
58469         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
58470         {"GMX0_TX003_SLOT"             ,           0x1180008001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
58471         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
58472         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
58473         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
58474         {"GMX0_TX003_SOFT_PAUSE"       ,           0x1180008001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
58475         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
58476         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
58477         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
58478         {"GMX0_TX003_STAT0"            ,           0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
58479         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
58480         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
58481         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
58482         {"GMX0_TX003_STAT1"            ,           0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
58483         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
58484         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
58485         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
58486         {"GMX0_TX003_STAT2"            ,           0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
58487         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
58488         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
58489         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
58490         {"GMX0_TX003_STAT3"            ,           0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
58491         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
58492         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
58493         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
58494         {"GMX0_TX003_STAT4"            ,           0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
58495         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
58496         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
58497         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
58498         {"GMX0_TX003_STAT5"            ,           0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
58499         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
58500         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
58501         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
58502         {"GMX0_TX003_STAT6"            ,           0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
58503         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
58504         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
58505         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
58506         {"GMX0_TX003_STAT7"            ,           0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
58507         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
58508         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
58509         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
58510         {"GMX0_TX003_STAT8"            ,           0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
58511         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
58512         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
58513         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
58514         {"GMX0_TX003_STAT9"            ,           0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
58515         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
58516         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
58517         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
58518         {"GMX0_TX003_STATS_CTL"        ,           0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
58519         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
58520         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
58521         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
58522         {"GMX0_TX003_THRESH"           ,           0x1180008001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
58523         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
58524         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
58525         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
58526         {"GMX0_TX_HG2_REG1"            ,           0x1180008000558ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
58527         {"GMX0_TX_HG2_REG2"            ,           0x1180008000560ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
58528         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
58529         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
58530         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
58531         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
58532         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
58533         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
58534         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
58535         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
58536         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
58537         {"GMX0_TX_XAUI_CTL"            ,           0x1180008000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
58538         {"GMX0_XAUI_EXT_LOOPBACK"      ,           0x1180008000540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
58539         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58540         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58541         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58542         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58543         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58544         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58545         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58546         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58547         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58548         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58549         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58550         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58551         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58552         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58553         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58554         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     191},
58555         {"GPIO_CLK_GEN0"               ,           0x10700000008C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
58556         {"GPIO_CLK_GEN1"               ,           0x10700000008C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
58557         {"GPIO_CLK_GEN2"               ,           0x10700000008D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
58558         {"GPIO_CLK_GEN3"               ,           0x10700000008D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     192},
58559         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     193},
58560         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     194},
58561         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     195},
58562         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     196},
58563         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     197},
58564         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     198},
58565         {"IOB_DWB_PRI_CNT"             ,           0x11800F0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     199},
58566         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     200},
58567         {"IOB_I2C_PRI_CNT"             ,           0x11800F0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
58568         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     202},
58569         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     203},
58570         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     204},
58571         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     205},
58572         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     206},
58573         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     207},
58574         {"IOB_N2C_L2C_PRI_CNT"         ,           0x11800F0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     208},
58575         {"IOB_N2C_RSP_PRI_CNT"         ,           0x11800F0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     209},
58576         {"IOB_OUTB_COM_PRI_CNT"        ,           0x11800F0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     210},
58577         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     211},
58578         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     212},
58579         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     213},
58580         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
58581         {"IOB_OUTB_FPA_PRI_CNT"        ,           0x11800F0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
58582         {"IOB_OUTB_REQ_PRI_CNT"        ,           0x11800F0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
58583         {"IOB_P2C_REQ_PRI_CNT"         ,           0x11800F0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
58584         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
58585         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     219},
58586         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     220},
58587         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     221},
58588         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     222},
58589         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     223},
58590         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     224},
58591         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     225},
58592         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     226},
58593         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     227},
58594         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     228},
58595         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     229},
58596         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     230},
58597         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
58598         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
58599         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
58600         {"IPD_PORT3_BP_PAGE_CNT"       ,           0x14F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
58601         {"IPD_PORT36_BP_PAGE_CNT2"     ,           0x14F0000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     232},
58602         {"IPD_PORT37_BP_PAGE_CNT2"     ,           0x14F0000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     232},
58603         {"IPD_PORT38_BP_PAGE_CNT2"     ,           0x14F0000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     232},
58604         {"IPD_PORT39_BP_PAGE_CNT2"     ,           0x14F0000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     232},
58605         {"IPD_PORT_BP_COUNTERS2_PAIR36",           0x14F0000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     233},
58606         {"IPD_PORT_BP_COUNTERS2_PAIR37",           0x14F0000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     233},
58607         {"IPD_PORT_BP_COUNTERS2_PAIR38",           0x14F0000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     233},
58608         {"IPD_PORT_BP_COUNTERS2_PAIR39",           0x14F00000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     233},
58609         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
58610         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
58611         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
58612         {"IPD_PORT_BP_COUNTERS_PAIR3"  ,           0x14F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
58613         {"IPD_PORT_QOS_0_CNT"          ,           0x14F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58614         {"IPD_PORT_QOS_1_CNT"          ,           0x14F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58615         {"IPD_PORT_QOS_2_CNT"          ,           0x14F0000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58616         {"IPD_PORT_QOS_3_CNT"          ,           0x14F00000008A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58617         {"IPD_PORT_QOS_4_CNT"          ,           0x14F00000008A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58618         {"IPD_PORT_QOS_5_CNT"          ,           0x14F00000008B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58619         {"IPD_PORT_QOS_6_CNT"          ,           0x14F00000008B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58620         {"IPD_PORT_QOS_7_CNT"          ,           0x14F00000008C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58621         {"IPD_PORT_QOS_8_CNT"          ,           0x14F00000008C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58622         {"IPD_PORT_QOS_9_CNT"          ,           0x14F00000008D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58623         {"IPD_PORT_QOS_10_CNT"         ,           0x14F00000008D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58624         {"IPD_PORT_QOS_11_CNT"         ,           0x14F00000008E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58625         {"IPD_PORT_QOS_12_CNT"         ,           0x14F00000008E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58626         {"IPD_PORT_QOS_13_CNT"         ,           0x14F00000008F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58627         {"IPD_PORT_QOS_14_CNT"         ,           0x14F00000008F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58628         {"IPD_PORT_QOS_15_CNT"         ,           0x14F0000000900ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58629         {"IPD_PORT_QOS_16_CNT"         ,           0x14F0000000908ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58630         {"IPD_PORT_QOS_17_CNT"         ,           0x14F0000000910ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58631         {"IPD_PORT_QOS_18_CNT"         ,           0x14F0000000918ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58632         {"IPD_PORT_QOS_19_CNT"         ,           0x14F0000000920ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58633         {"IPD_PORT_QOS_20_CNT"         ,           0x14F0000000928ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58634         {"IPD_PORT_QOS_21_CNT"         ,           0x14F0000000930ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58635         {"IPD_PORT_QOS_22_CNT"         ,           0x14F0000000938ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58636         {"IPD_PORT_QOS_23_CNT"         ,           0x14F0000000940ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58637         {"IPD_PORT_QOS_24_CNT"         ,           0x14F0000000948ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58638         {"IPD_PORT_QOS_25_CNT"         ,           0x14F0000000950ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58639         {"IPD_PORT_QOS_26_CNT"         ,           0x14F0000000958ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58640         {"IPD_PORT_QOS_27_CNT"         ,           0x14F0000000960ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58641         {"IPD_PORT_QOS_28_CNT"         ,           0x14F0000000968ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58642         {"IPD_PORT_QOS_29_CNT"         ,           0x14F0000000970ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58643         {"IPD_PORT_QOS_30_CNT"         ,           0x14F0000000978ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58644         {"IPD_PORT_QOS_31_CNT"         ,           0x14F0000000980ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58645         {"IPD_PORT_QOS_288_CNT"        ,           0x14F0000001188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58646         {"IPD_PORT_QOS_289_CNT"        ,           0x14F0000001190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58647         {"IPD_PORT_QOS_290_CNT"        ,           0x14F0000001198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58648         {"IPD_PORT_QOS_291_CNT"        ,           0x14F00000011A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58649         {"IPD_PORT_QOS_292_CNT"        ,           0x14F00000011A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58650         {"IPD_PORT_QOS_293_CNT"        ,           0x14F00000011B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58651         {"IPD_PORT_QOS_294_CNT"        ,           0x14F00000011B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58652         {"IPD_PORT_QOS_295_CNT"        ,           0x14F00000011C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58653         {"IPD_PORT_QOS_296_CNT"        ,           0x14F00000011C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58654         {"IPD_PORT_QOS_297_CNT"        ,           0x14F00000011D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58655         {"IPD_PORT_QOS_298_CNT"        ,           0x14F00000011D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58656         {"IPD_PORT_QOS_299_CNT"        ,           0x14F00000011E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58657         {"IPD_PORT_QOS_300_CNT"        ,           0x14F00000011E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58658         {"IPD_PORT_QOS_301_CNT"        ,           0x14F00000011F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58659         {"IPD_PORT_QOS_302_CNT"        ,           0x14F00000011F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58660         {"IPD_PORT_QOS_303_CNT"        ,           0x14F0000001200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58661         {"IPD_PORT_QOS_304_CNT"        ,           0x14F0000001208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58662         {"IPD_PORT_QOS_305_CNT"        ,           0x14F0000001210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58663         {"IPD_PORT_QOS_306_CNT"        ,           0x14F0000001218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58664         {"IPD_PORT_QOS_307_CNT"        ,           0x14F0000001220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58665         {"IPD_PORT_QOS_308_CNT"        ,           0x14F0000001228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58666         {"IPD_PORT_QOS_309_CNT"        ,           0x14F0000001230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58667         {"IPD_PORT_QOS_310_CNT"        ,           0x14F0000001238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58668         {"IPD_PORT_QOS_311_CNT"        ,           0x14F0000001240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58669         {"IPD_PORT_QOS_312_CNT"        ,           0x14F0000001248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58670         {"IPD_PORT_QOS_313_CNT"        ,           0x14F0000001250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58671         {"IPD_PORT_QOS_314_CNT"        ,           0x14F0000001258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58672         {"IPD_PORT_QOS_315_CNT"        ,           0x14F0000001260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58673         {"IPD_PORT_QOS_316_CNT"        ,           0x14F0000001268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58674         {"IPD_PORT_QOS_317_CNT"        ,           0x14F0000001270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58675         {"IPD_PORT_QOS_318_CNT"        ,           0x14F0000001278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58676         {"IPD_PORT_QOS_319_CNT"        ,           0x14F0000001280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
58677         {"IPD_PORT_QOS_INT0"           ,           0x14F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     236},
58678         {"IPD_PORT_QOS_INT4"           ,           0x14F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     236},
58679         {"IPD_PORT_QOS_INT_ENB0"       ,           0x14F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     237},
58680         {"IPD_PORT_QOS_INT_ENB4"       ,           0x14F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     237},
58681         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     238},
58682         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     239},
58683         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     240},
58684         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     241},
58685         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
58686         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
58687         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
58688         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
58689         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
58690         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
58691         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
58692         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
58693         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
58694         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     244},
58695         {"IPD_RED_PORT_ENABLE2"        ,           0x14F00000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     245},
58696         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
58697         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
58698         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
58699         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
58700         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
58701         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
58702         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
58703         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
58704         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
58705         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     248},
58706         {"IPD_SUB_PORT_QOS_CNT"        ,           0x14F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
58707         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
58708         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     251},
58709         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     252},
58710         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     253},
58711         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     254},
58712         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     255},
58713         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     256},
58714         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     257},
58715         {"L2C_GRPWRR0"                 ,           0x11800800000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     258},
58716         {"L2C_GRPWRR1"                 ,           0x11800800000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     259},
58717         {"L2C_INT_EN"                  ,           0x1180080000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     260},
58718         {"L2C_INT_STAT"                ,           0x11800800000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     261},
58719         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     262},
58720         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     263},
58721         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
58722         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
58723         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
58724         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
58725         {"L2C_OOB"                     ,           0x11800800000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
58726         {"L2C_OOB1"                    ,           0x11800800000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
58727         {"L2C_OOB2"                    ,           0x11800800000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
58728         {"L2C_OOB3"                    ,           0x11800800000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
58729         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
58730         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
58731         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
58732         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
58733         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
58734         {"L2C_PPGRP"                   ,           0x11800800000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
58735         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
58736         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
58737         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
58738         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
58739         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
58740         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
58741         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
58742         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
58743         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
58744         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
58745         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
58746         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
58747         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     287},
58748         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     288},
58749         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     289},
58750         {"LMC0_BIST_CTL"               ,           0x11800880000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
58751         {"LMC0_BIST_RESULT"            ,           0x11800880000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
58752         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     292},
58753         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
58754         {"LMC0_CTL1"                   ,           0x1180088000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     294},
58755         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     295},
58756         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     296},
58757         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
58758         {"LMC0_DELAY_CFG"              ,           0x1180088000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     298},
58759         {"LMC0_DLL_CTL"                ,           0x11800880000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
58760         {"LMC0_DUAL_MEMCFG"            ,           0x1180088000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
58761         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
58762         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
58763         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
58764         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
58765         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
58766         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
58767         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
58768         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
58769         {"LMC0_PLL_CTL"                ,           0x11800880000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
58770         {"LMC0_PLL_STATUS"             ,           0x11800880000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
58771         {"LMC0_READ_LEVEL_CTL"         ,           0x1180088000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
58772         {"LMC0_READ_LEVEL_DBG"         ,           0x1180088000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
58773         {"LMC0_READ_LEVEL_RANK000"     ,           0x1180088000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
58774         {"LMC0_READ_LEVEL_RANK001"     ,           0x1180088000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
58775         {"LMC0_READ_LEVEL_RANK002"     ,           0x1180088000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
58776         {"LMC0_READ_LEVEL_RANK003"     ,           0x1180088000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
58777         {"LMC0_RODT_COMP_CTL"          ,           0x11800880000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
58778         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
58779         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
58780         {"LMC0_WODT_CTL1"              ,           0x1180088000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
58781         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
58782         {"MIO_BOOT_COMP"               ,           0x11800000000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
58783         {"MIO_BOOT_DMA_CFG0"           ,           0x1180000000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
58784         {"MIO_BOOT_DMA_CFG1"           ,           0x1180000000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
58785         {"MIO_BOOT_DMA_INT0"           ,           0x1180000000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
58786         {"MIO_BOOT_DMA_INT1"           ,           0x1180000000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
58787         {"MIO_BOOT_DMA_INT_EN0"        ,           0x1180000000150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
58788         {"MIO_BOOT_DMA_INT_EN1"        ,           0x1180000000158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
58789         {"MIO_BOOT_DMA_TIM0"           ,           0x1180000000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
58790         {"MIO_BOOT_DMA_TIM1"           ,           0x1180000000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
58791         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
58792         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
58793         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
58794         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
58795         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
58796         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
58797         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
58798         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
58799         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
58800         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
58801         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
58802         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
58803         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
58804         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
58805         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
58806         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
58807         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
58808         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
58809         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
58810         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
58811         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
58812         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
58813         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
58814         {"MIO_FUS_BNK_DAT0"            ,           0x1180000001520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
58815         {"MIO_FUS_BNK_DAT1"            ,           0x1180000001528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
58816         {"MIO_FUS_BNK_DAT2"            ,           0x1180000001530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
58817         {"MIO_FUS_BNK_DAT3"            ,           0x1180000001538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
58818         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
58819         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
58820         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     335},
58821         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     336},
58822         {"MIO_FUS_EMA"                 ,           0x1180000001550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     337},
58823         {"MIO_FUS_PDF"                 ,           0x1180000001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     338},
58824         {"MIO_FUS_PLL"                 ,           0x1180000001580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     339},
58825         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
58826         {"MIO_FUS_PROG_TIMES"          ,           0x1180000001518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     341},
58827         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     342},
58828         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
58829         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
58830         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     345},
58831         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     346},
58832         {"MIO_TWS1_INT"                ,           0x1180000001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     346},
58833         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     347},
58834         {"MIO_TWS1_SW_TWSI"            ,           0x1180000001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     347},
58835         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     348},
58836         {"MIO_TWS1_SW_TWSI_EXT"        ,           0x1180000001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     348},
58837         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
58838         {"MIO_TWS1_TWSI_SW"            ,           0x1180000001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
58839         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
58840         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
58841         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     351},
58842         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     351},
58843         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     352},
58844         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     352},
58845         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     353},
58846         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     353},
58847         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     354},
58848         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     354},
58849         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     355},
58850         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     355},
58851         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     356},
58852         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     356},
58853         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     357},
58854         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     357},
58855         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     358},
58856         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     358},
58857         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     359},
58858         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     359},
58859         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     360},
58860         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     360},
58861         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     361},
58862         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     361},
58863         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     362},
58864         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     362},
58865         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     363},
58866         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     363},
58867         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     364},
58868         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     364},
58869         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     365},
58870         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     365},
58871         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
58872         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
58873         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
58874         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
58875         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     368},
58876         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     368},
58877         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
58878         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
58879         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     370},
58880         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     370},
58881         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     371},
58882         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     371},
58883         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     372},
58884         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     372},
58885         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     373},
58886         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     373},
58887         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     374},
58888         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     374},
58889         {"MIO_UART2_DLH"               ,           0x1180000000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     375},
58890         {"MIO_UART2_DLL"               ,           0x1180000000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     376},
58891         {"MIO_UART2_FAR"               ,           0x1180000000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     377},
58892         {"MIO_UART2_FCR"               ,           0x1180000000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     378},
58893         {"MIO_UART2_HTX"               ,           0x1180000000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     379},
58894         {"MIO_UART2_IER"               ,           0x1180000000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     380},
58895         {"MIO_UART2_IIR"               ,           0x1180000000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     381},
58896         {"MIO_UART2_LCR"               ,           0x1180000000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     382},
58897         {"MIO_UART2_LSR"               ,           0x1180000000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     383},
58898         {"MIO_UART2_MCR"               ,           0x1180000000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     384},
58899         {"MIO_UART2_MSR"               ,           0x1180000000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     385},
58900         {"MIO_UART2_RBR"               ,           0x1180000000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     386},
58901         {"MIO_UART2_RFL"               ,           0x1180000000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     387},
58902         {"MIO_UART2_RFW"               ,           0x1180000000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     388},
58903         {"MIO_UART2_SBCR"              ,           0x1180000000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     389},
58904         {"MIO_UART2_SCR"               ,           0x1180000000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     390},
58905         {"MIO_UART2_SFE"               ,           0x1180000000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     391},
58906         {"MIO_UART2_SRR"               ,           0x1180000000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     392},
58907         {"MIO_UART2_SRT"               ,           0x1180000000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
58908         {"MIO_UART2_SRTS"              ,           0x1180000000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     394},
58909         {"MIO_UART2_STT"               ,           0x1180000000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     395},
58910         {"MIO_UART2_TFL"               ,           0x1180000000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     396},
58911         {"MIO_UART2_TFR"               ,           0x1180000000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     397},
58912         {"MIO_UART2_THR"               ,           0x1180000000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     398},
58913         {"MIO_UART2_USR"               ,           0x1180000000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     399},
58914         {"MIX0_BIST"                   ,           0x1070000100078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
58915         {"MIX1_BIST"                   ,           0x1070000100878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     400},
58916         {"MIX0_CTL"                    ,           0x1070000100020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
58917         {"MIX1_CTL"                    ,           0x1070000100820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     401},
58918         {"MIX0_INTENA"                 ,           0x1070000100050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
58919         {"MIX1_INTENA"                 ,           0x1070000100850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     402},
58920         {"MIX0_IRCNT"                  ,           0x1070000100030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     403},
58921         {"MIX1_IRCNT"                  ,           0x1070000100830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     403},
58922         {"MIX0_IRHWM"                  ,           0x1070000100028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     404},
58923         {"MIX1_IRHWM"                  ,           0x1070000100828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     404},
58924         {"MIX0_IRING1"                 ,           0x1070000100010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     405},
58925         {"MIX1_IRING1"                 ,           0x1070000100810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     405},
58926         {"MIX0_IRING2"                 ,           0x1070000100018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     406},
58927         {"MIX1_IRING2"                 ,           0x1070000100818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     406},
58928         {"MIX0_ISR"                    ,           0x1070000100048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     407},
58929         {"MIX1_ISR"                    ,           0x1070000100848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     407},
58930         {"MIX0_ORCNT"                  ,           0x1070000100040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     408},
58931         {"MIX1_ORCNT"                  ,           0x1070000100840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     408},
58932         {"MIX0_ORHWM"                  ,           0x1070000100038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     409},
58933         {"MIX1_ORHWM"                  ,           0x1070000100838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     409},
58934         {"MIX0_ORING1"                 ,           0x1070000100000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     410},
58935         {"MIX1_ORING1"                 ,           0x1070000100800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     410},
58936         {"MIX0_ORING2"                 ,           0x1070000100008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     411},
58937         {"MIX1_ORING2"                 ,           0x1070000100808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     411},
58938         {"MIX0_REMCNT"                 ,           0x1070000100058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     412},
58939         {"MIX1_REMCNT"                 ,           0x1070000100858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     412},
58940         {"NPEI_BAR1_INDEX0"            ,           0x11F0000008000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58941         {"NPEI_BAR1_INDEX1"            ,           0x11F0000008010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58942         {"NPEI_BAR1_INDEX2"            ,           0x11F0000008020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58943         {"NPEI_BAR1_INDEX3"            ,           0x11F0000008030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58944         {"NPEI_BAR1_INDEX4"            ,           0x11F0000008040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58945         {"NPEI_BAR1_INDEX5"            ,           0x11F0000008050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58946         {"NPEI_BAR1_INDEX6"            ,           0x11F0000008060ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58947         {"NPEI_BAR1_INDEX7"            ,           0x11F0000008070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58948         {"NPEI_BAR1_INDEX8"            ,           0x11F0000008080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58949         {"NPEI_BAR1_INDEX9"            ,           0x11F0000008090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58950         {"NPEI_BAR1_INDEX10"           ,           0x11F00000080A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58951         {"NPEI_BAR1_INDEX11"           ,           0x11F00000080B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58952         {"NPEI_BAR1_INDEX12"           ,           0x11F00000080C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58953         {"NPEI_BAR1_INDEX13"           ,           0x11F00000080D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58954         {"NPEI_BAR1_INDEX14"           ,           0x11F00000080E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58955         {"NPEI_BAR1_INDEX15"           ,           0x11F00000080F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58956         {"NPEI_BAR1_INDEX16"           ,           0x11F0000008100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58957         {"NPEI_BAR1_INDEX17"           ,           0x11F0000008110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58958         {"NPEI_BAR1_INDEX18"           ,           0x11F0000008120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58959         {"NPEI_BAR1_INDEX19"           ,           0x11F0000008130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58960         {"NPEI_BAR1_INDEX20"           ,           0x11F0000008140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58961         {"NPEI_BAR1_INDEX21"           ,           0x11F0000008150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58962         {"NPEI_BAR1_INDEX22"           ,           0x11F0000008160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58963         {"NPEI_BAR1_INDEX23"           ,           0x11F0000008170ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58964         {"NPEI_BAR1_INDEX24"           ,           0x11F0000008180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58965         {"NPEI_BAR1_INDEX25"           ,           0x11F0000008190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58966         {"NPEI_BAR1_INDEX26"           ,           0x11F00000081A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58967         {"NPEI_BAR1_INDEX27"           ,           0x11F00000081B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58968         {"NPEI_BAR1_INDEX28"           ,           0x11F00000081C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58969         {"NPEI_BAR1_INDEX29"           ,           0x11F00000081D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58970         {"NPEI_BAR1_INDEX30"           ,           0x11F00000081E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58971         {"NPEI_BAR1_INDEX31"           ,           0x11F00000081F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     413},
58972         {"NPEI_BIST_STATUS"            ,           0x11F0000008580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     414},
58973         {"NPEI_CTL_PORT0"              ,           0x11F0000008250ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     415},
58974         {"NPEI_CTL_PORT1"              ,           0x11F0000008260ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     416},
58975         {"NPEI_CTL_STATUS"             ,           0x11F0000008570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     417},
58976         {"NPEI_CTL_STATUS2"            ,           0x11F000000BC00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     418},
58977         {"NPEI_DATA_OUT_CNT"           ,           0x11F00000085F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     419},
58978         {"NPEI_DBG_DATA"               ,           0x11F0000008510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     420},
58979         {"NPEI_DBG_SELECT"             ,           0x11F0000008500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     421},
58980         {"NPEI_DMA0_COUNTS"            ,           0x11F0000008450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     422},
58981         {"NPEI_DMA1_COUNTS"            ,           0x11F0000008460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     422},
58982         {"NPEI_DMA2_COUNTS"            ,           0x11F0000008470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     422},
58983         {"NPEI_DMA3_COUNTS"            ,           0x11F0000008480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     422},
58984         {"NPEI_DMA0_DBELL"             ,           0x11F00000083B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     423},
58985         {"NPEI_DMA1_DBELL"             ,           0x11F00000083C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     423},
58986         {"NPEI_DMA2_DBELL"             ,           0x11F00000083D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     423},
58987         {"NPEI_DMA3_DBELL"             ,           0x11F00000083E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     423},
58988         {"NPEI_DMA0_IBUFF_SADDR"       ,           0x11F0000008400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     424},
58989         {"NPEI_DMA1_IBUFF_SADDR"       ,           0x11F0000008410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     424},
58990         {"NPEI_DMA2_IBUFF_SADDR"       ,           0x11F0000008420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     424},
58991         {"NPEI_DMA3_IBUFF_SADDR"       ,           0x11F0000008430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     424},
58992         {"NPEI_DMA0_NADDR"             ,           0x11F00000084A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     425},
58993         {"NPEI_DMA1_NADDR"             ,           0x11F00000084B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     425},
58994         {"NPEI_DMA2_NADDR"             ,           0x11F00000084C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     425},
58995         {"NPEI_DMA3_NADDR"             ,           0x11F00000084D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     425},
58996         {"NPEI_DMA0_INT_LEVEL"         ,           0x11F00000085C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     426},
58997         {"NPEI_DMA1_INT_LEVEL"         ,           0x11F00000085D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     427},
58998         {"NPEI_DMA_CNTS"               ,           0x11F00000085E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     428},
58999         {"NPEI_DMA_CONTROL"            ,           0x11F00000083A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     429},
59000         {"NPEI_DMA_STATE1_P1"          ,           0x11F0000008680ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     430},
59001         {"NPEI_DMA_STATE2_P1"          ,           0x11F0000008690ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     431},
59002         {"NPEI_DMA_STATE3_P1"          ,           0x11F00000086A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     432},
59003         {"NPEI_DMA_STATE4_P1"          ,           0x11F00000086B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     433},
59004         {"NPEI_INT_A_ENB"              ,           0x11F0000008560ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     434},
59005         {"NPEI_INT_A_ENB2"             ,           0x11F000000BCE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     435},
59006         {"NPEI_INT_A_SUM"              ,           0x11F0000008550ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     436},
59007         {"NPEI_INT_ENB"                ,           0x11F0000008540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     437},
59008         {"NPEI_INT_ENB2"               ,           0x11F000000BCD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     438},
59009         {"NPEI_INT_SUM"                ,           0x11F0000008530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     439},
59010         {"NPEI_INT_SUM2"               ,           0x11F000000BCC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     440},
59011         {"NPEI_LAST_WIN_RDATA0"        ,           0x11F0000008600ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     441},
59012         {"NPEI_LAST_WIN_RDATA1"        ,           0x11F0000008610ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     442},
59013         {"NPEI_MEM_ACCESS_CTL"         ,           0x11F00000084F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     443},
59014         {"NPEI_MEM_ACCESS_SUBID12"     ,           0x11F0000008280ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59015         {"NPEI_MEM_ACCESS_SUBID13"     ,           0x11F0000008290ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59016         {"NPEI_MEM_ACCESS_SUBID14"     ,           0x11F00000082A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59017         {"NPEI_MEM_ACCESS_SUBID15"     ,           0x11F00000082B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59018         {"NPEI_MEM_ACCESS_SUBID16"     ,           0x11F00000082C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59019         {"NPEI_MEM_ACCESS_SUBID17"     ,           0x11F00000082D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59020         {"NPEI_MEM_ACCESS_SUBID18"     ,           0x11F00000082E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59021         {"NPEI_MEM_ACCESS_SUBID19"     ,           0x11F00000082F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59022         {"NPEI_MEM_ACCESS_SUBID20"     ,           0x11F0000008300ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59023         {"NPEI_MEM_ACCESS_SUBID21"     ,           0x11F0000008310ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59024         {"NPEI_MEM_ACCESS_SUBID22"     ,           0x11F0000008320ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59025         {"NPEI_MEM_ACCESS_SUBID23"     ,           0x11F0000008330ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59026         {"NPEI_MEM_ACCESS_SUBID24"     ,           0x11F0000008340ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59027         {"NPEI_MEM_ACCESS_SUBID25"     ,           0x11F0000008350ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59028         {"NPEI_MEM_ACCESS_SUBID26"     ,           0x11F0000008360ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59029         {"NPEI_MEM_ACCESS_SUBID27"     ,           0x11F0000008370ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
59030         {"NPEI_MSI_ENB0"               ,           0x11F000000BC50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     445},
59031         {"NPEI_MSI_ENB1"               ,           0x11F000000BC60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     446},
59032         {"NPEI_MSI_ENB2"               ,           0x11F000000BC70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     447},
59033         {"NPEI_MSI_ENB3"               ,           0x11F000000BC80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     448},
59034         {"NPEI_MSI_RCV0"               ,           0x11F000000BC10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     449},
59035         {"NPEI_MSI_RCV1"               ,           0x11F000000BC20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     450},
59036         {"NPEI_MSI_RCV2"               ,           0x11F000000BC30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     451},
59037         {"NPEI_MSI_RCV3"               ,           0x11F000000BC40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     452},
59038         {"NPEI_MSI_RD_MAP"             ,           0x11F000000BCA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     453},
59039         {"NPEI_MSI_WR_MAP"             ,           0x11F000000BC90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     454},
59040         {"NPEI_PCIE_MSI_RCV"           ,           0x11F000000BCB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
59041         {"NPEI_PCIE_MSI_RCV_B1"        ,           0x11F0000008650ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     456},
59042         {"NPEI_PCIE_MSI_RCV_B2"        ,           0x11F0000008660ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     457},
59043         {"NPEI_PCIE_MSI_RCV_B3"        ,           0x11F0000008670ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     458},
59044         {"NPEI_RSL_INT_BLOCKS"         ,           0x11F0000008520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     459},
59045         {"NPEI_SCRATCH_1"              ,           0x11F0000008270ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     460},
59046         {"NPEI_STATE1"                 ,           0x11F0000008620ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     461},
59047         {"NPEI_STATE2"                 ,           0x11F0000008630ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     462},
59048         {"NPEI_STATE3"                 ,           0x11F0000008640ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     463},
59049         {"NPEI_WIN_RD_ADDR"            ,                     0x210ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     464},
59050         {"NPEI_WIN_RD_DATA"            ,                     0x240ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     465},
59051         {"NPEI_WIN_WR_ADDR"            ,                     0x200ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     466},
59052         {"NPEI_WIN_WR_DATA"            ,                     0x220ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     467},
59053         {"NPEI_WIN_WR_MASK"            ,                     0x230ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     468},
59054         {"NPEI_WINDOW_CTL"             ,           0x11F0000008380ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     469},
59055         {"PCIEEP_CFG000"               ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     470},
59056         {"PCIEEP_CFG001"               ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     471},
59057         {"PCIEEP_CFG002"               ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     472},
59058         {"PCIEEP_CFG003"               ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     473},
59059         {"PCIEEP_CFG004"               ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     474},
59060         {"PCIEEP_CFG004_MASK"          ,                0x80000010ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     475},
59061         {"PCIEEP_CFG005"               ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     476},
59062         {"PCIEEP_CFG005_MASK"          ,                0x80000014ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     477},
59063         {"PCIEEP_CFG006"               ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     478},
59064         {"PCIEEP_CFG006_MASK"          ,                0x80000018ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     479},
59065         {"PCIEEP_CFG007"               ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     480},
59066         {"PCIEEP_CFG007_MASK"          ,                0x8000001Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     481},
59067         {"PCIEEP_CFG008"               ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     482},
59068         {"PCIEEP_CFG008_MASK"          ,                0x80000020ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     483},
59069         {"PCIEEP_CFG009"               ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     484},
59070         {"PCIEEP_CFG009_MASK"          ,                0x80000024ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     485},
59071         {"PCIEEP_CFG010"               ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     486},
59072         {"PCIEEP_CFG011"               ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     487},
59073         {"PCIEEP_CFG012"               ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     488},
59074         {"PCIEEP_CFG012_MASK"          ,                0x80000030ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     489},
59075         {"PCIEEP_CFG013"               ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     490},
59076         {"PCIEEP_CFG015"               ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     491},
59077         {"PCIEEP_CFG016"               ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     492},
59078         {"PCIEEP_CFG017"               ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     493},
59079         {"PCIEEP_CFG020"               ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     494},
59080         {"PCIEEP_CFG021"               ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     495},
59081         {"PCIEEP_CFG022"               ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     496},
59082         {"PCIEEP_CFG023"               ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     497},
59083         {"PCIEEP_CFG028"               ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     498},
59084         {"PCIEEP_CFG029"               ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     499},
59085         {"PCIEEP_CFG030"               ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     500},
59086         {"PCIEEP_CFG031"               ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     501},
59087         {"PCIEEP_CFG032"               ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     502},
59088         {"PCIEEP_CFG033"               ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     503},
59089         {"PCIEEP_CFG034"               ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     504},
59090         {"PCIEEP_CFG037"               ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     505},
59091         {"PCIEEP_CFG038"               ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     506},
59092         {"PCIEEP_CFG039"               ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     507},
59093         {"PCIEEP_CFG040"               ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     508},
59094         {"PCIEEP_CFG041"               ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     509},
59095         {"PCIEEP_CFG042"               ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     510},
59096         {"PCIEEP_CFG064"               ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     511},
59097         {"PCIEEP_CFG065"               ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     512},
59098         {"PCIEEP_CFG066"               ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     513},
59099         {"PCIEEP_CFG067"               ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     514},
59100         {"PCIEEP_CFG068"               ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     515},
59101         {"PCIEEP_CFG069"               ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     516},
59102         {"PCIEEP_CFG070"               ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     517},
59103         {"PCIEEP_CFG071"               ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     518},
59104         {"PCIEEP_CFG072"               ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     519},
59105         {"PCIEEP_CFG073"               ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     520},
59106         {"PCIEEP_CFG074"               ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     521},
59107         {"PCIEEP_CFG448"               ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     522},
59108         {"PCIEEP_CFG449"               ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     523},
59109         {"PCIEEP_CFG450"               ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     524},
59110         {"PCIEEP_CFG451"               ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     525},
59111         {"PCIEEP_CFG452"               ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     526},
59112         {"PCIEEP_CFG453"               ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     527},
59113         {"PCIEEP_CFG454"               ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     528},
59114         {"PCIEEP_CFG455"               ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     529},
59115         {"PCIEEP_CFG456"               ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     530},
59116         {"PCIEEP_CFG458"               ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     531},
59117         {"PCIEEP_CFG459"               ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     532},
59118         {"PCIEEP_CFG460"               ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     533},
59119         {"PCIEEP_CFG461"               ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     534},
59120         {"PCIEEP_CFG462"               ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     535},
59121         {"PCIEEP_CFG463"               ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     536},
59122         {"PCIEEP_CFG464"               ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     537},
59123         {"PCIEEP_CFG465"               ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     538},
59124         {"PCIEEP_CFG466"               ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     539},
59125         {"PCIEEP_CFG467"               ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     540},
59126         {"PCIEEP_CFG468"               ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     541},
59127         {"PCIEEP_CFG490"               ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     542},
59128         {"PCIEEP_CFG491"               ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     543},
59129         {"PCIEEP_CFG492"               ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     544},
59130         {"PCIEEP_CFG516"               ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     545},
59131         {"PCIEEP_CFG517"               ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     546},
59132         {"PCIERC0_CFG000"              ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     547},
59133         {"PCIERC1_CFG000"              ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     547},
59134         {"PCIERC0_CFG001"              ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     548},
59135         {"PCIERC1_CFG001"              ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     548},
59136         {"PCIERC0_CFG002"              ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     549},
59137         {"PCIERC1_CFG002"              ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     549},
59138         {"PCIERC0_CFG003"              ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     550},
59139         {"PCIERC1_CFG003"              ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     550},
59140         {"PCIERC0_CFG004"              ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     551},
59141         {"PCIERC1_CFG004"              ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     551},
59142         {"PCIERC0_CFG005"              ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     552},
59143         {"PCIERC1_CFG005"              ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     552},
59144         {"PCIERC0_CFG006"              ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     553},
59145         {"PCIERC1_CFG006"              ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     553},
59146         {"PCIERC0_CFG007"              ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     554},
59147         {"PCIERC1_CFG007"              ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     554},
59148         {"PCIERC0_CFG008"              ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     555},
59149         {"PCIERC1_CFG008"              ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     555},
59150         {"PCIERC0_CFG009"              ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     556},
59151         {"PCIERC1_CFG009"              ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     556},
59152         {"PCIERC0_CFG010"              ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     557},
59153         {"PCIERC1_CFG010"              ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     557},
59154         {"PCIERC0_CFG011"              ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     558},
59155         {"PCIERC1_CFG011"              ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     558},
59156         {"PCIERC0_CFG012"              ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     559},
59157         {"PCIERC1_CFG012"              ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     559},
59158         {"PCIERC0_CFG013"              ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     560},
59159         {"PCIERC1_CFG013"              ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     560},
59160         {"PCIERC0_CFG014"              ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     561},
59161         {"PCIERC1_CFG014"              ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     561},
59162         {"PCIERC0_CFG015"              ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     562},
59163         {"PCIERC1_CFG015"              ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     562},
59164         {"PCIERC0_CFG016"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     563},
59165         {"PCIERC1_CFG016"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     563},
59166         {"PCIERC0_CFG017"              ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     564},
59167         {"PCIERC1_CFG017"              ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     564},
59168         {"PCIERC0_CFG020"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     565},
59169         {"PCIERC1_CFG020"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     565},
59170         {"PCIERC0_CFG021"              ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     566},
59171         {"PCIERC1_CFG021"              ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     566},
59172         {"PCIERC0_CFG022"              ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     567},
59173         {"PCIERC1_CFG022"              ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     567},
59174         {"PCIERC0_CFG023"              ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     568},
59175         {"PCIERC1_CFG023"              ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     568},
59176         {"PCIERC0_CFG028"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     569},
59177         {"PCIERC1_CFG028"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     569},
59178         {"PCIERC0_CFG029"              ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     570},
59179         {"PCIERC1_CFG029"              ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     570},
59180         {"PCIERC0_CFG030"              ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     571},
59181         {"PCIERC1_CFG030"              ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     571},
59182         {"PCIERC0_CFG031"              ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     572},
59183         {"PCIERC1_CFG031"              ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     572},
59184         {"PCIERC0_CFG032"              ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     573},
59185         {"PCIERC1_CFG032"              ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     573},
59186         {"PCIERC0_CFG033"              ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     574},
59187         {"PCIERC1_CFG033"              ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     574},
59188         {"PCIERC0_CFG034"              ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     575},
59189         {"PCIERC1_CFG034"              ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     575},
59190         {"PCIERC0_CFG035"              ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     576},
59191         {"PCIERC1_CFG035"              ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     576},
59192         {"PCIERC0_CFG036"              ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     577},
59193         {"PCIERC1_CFG036"              ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     577},
59194         {"PCIERC0_CFG037"              ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     578},
59195         {"PCIERC1_CFG037"              ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     578},
59196         {"PCIERC0_CFG038"              ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     579},
59197         {"PCIERC1_CFG038"              ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     579},
59198         {"PCIERC0_CFG039"              ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     580},
59199         {"PCIERC1_CFG039"              ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     580},
59200         {"PCIERC0_CFG040"              ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     581},
59201         {"PCIERC1_CFG040"              ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     581},
59202         {"PCIERC0_CFG041"              ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     582},
59203         {"PCIERC1_CFG041"              ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     582},
59204         {"PCIERC0_CFG042"              ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     583},
59205         {"PCIERC1_CFG042"              ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     583},
59206         {"PCIERC0_CFG064"              ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     584},
59207         {"PCIERC1_CFG064"              ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     584},
59208         {"PCIERC0_CFG065"              ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     585},
59209         {"PCIERC1_CFG065"              ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     585},
59210         {"PCIERC0_CFG066"              ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     586},
59211         {"PCIERC1_CFG066"              ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     586},
59212         {"PCIERC0_CFG067"              ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     587},
59213         {"PCIERC1_CFG067"              ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     587},
59214         {"PCIERC0_CFG068"              ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     588},
59215         {"PCIERC1_CFG068"              ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     588},
59216         {"PCIERC0_CFG069"              ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     589},
59217         {"PCIERC1_CFG069"              ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     589},
59218         {"PCIERC0_CFG070"              ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     590},
59219         {"PCIERC1_CFG070"              ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     590},
59220         {"PCIERC0_CFG071"              ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     591},
59221         {"PCIERC1_CFG071"              ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     591},
59222         {"PCIERC0_CFG072"              ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     592},
59223         {"PCIERC1_CFG072"              ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     592},
59224         {"PCIERC0_CFG073"              ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     593},
59225         {"PCIERC1_CFG073"              ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     593},
59226         {"PCIERC0_CFG074"              ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     594},
59227         {"PCIERC1_CFG074"              ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     594},
59228         {"PCIERC0_CFG075"              ,                     0x12Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     595},
59229         {"PCIERC1_CFG075"              ,                     0x12Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     595},
59230         {"PCIERC0_CFG076"              ,                     0x130ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     596},
59231         {"PCIERC1_CFG076"              ,                     0x130ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     596},
59232         {"PCIERC0_CFG077"              ,                     0x134ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     597},
59233         {"PCIERC1_CFG077"              ,                     0x134ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     597},
59234         {"PCIERC0_CFG448"              ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     598},
59235         {"PCIERC1_CFG448"              ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     598},
59236         {"PCIERC0_CFG449"              ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     599},
59237         {"PCIERC1_CFG449"              ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     599},
59238         {"PCIERC0_CFG450"              ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     600},
59239         {"PCIERC1_CFG450"              ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     600},
59240         {"PCIERC0_CFG451"              ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     601},
59241         {"PCIERC1_CFG451"              ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     601},
59242         {"PCIERC0_CFG452"              ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     602},
59243         {"PCIERC1_CFG452"              ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     602},
59244         {"PCIERC0_CFG453"              ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     603},
59245         {"PCIERC1_CFG453"              ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     603},
59246         {"PCIERC0_CFG454"              ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     604},
59247         {"PCIERC1_CFG454"              ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     604},
59248         {"PCIERC0_CFG455"              ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     605},
59249         {"PCIERC1_CFG455"              ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     605},
59250         {"PCIERC0_CFG456"              ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     606},
59251         {"PCIERC1_CFG456"              ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     606},
59252         {"PCIERC0_CFG458"              ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     607},
59253         {"PCIERC1_CFG458"              ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     607},
59254         {"PCIERC0_CFG459"              ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     608},
59255         {"PCIERC1_CFG459"              ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     608},
59256         {"PCIERC0_CFG460"              ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     609},
59257         {"PCIERC1_CFG460"              ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     609},
59258         {"PCIERC0_CFG461"              ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     610},
59259         {"PCIERC1_CFG461"              ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     610},
59260         {"PCIERC0_CFG462"              ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     611},
59261         {"PCIERC1_CFG462"              ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     611},
59262         {"PCIERC0_CFG463"              ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     612},
59263         {"PCIERC1_CFG463"              ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     612},
59264         {"PCIERC0_CFG464"              ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     613},
59265         {"PCIERC1_CFG464"              ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     613},
59266         {"PCIERC0_CFG465"              ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     614},
59267         {"PCIERC1_CFG465"              ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     614},
59268         {"PCIERC0_CFG466"              ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     615},
59269         {"PCIERC1_CFG466"              ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     615},
59270         {"PCIERC0_CFG467"              ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     616},
59271         {"PCIERC1_CFG467"              ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     616},
59272         {"PCIERC0_CFG468"              ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     617},
59273         {"PCIERC1_CFG468"              ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     617},
59274         {"PCIERC0_CFG490"              ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     618},
59275         {"PCIERC1_CFG490"              ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     618},
59276         {"PCIERC0_CFG491"              ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     619},
59277         {"PCIERC1_CFG491"              ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     619},
59278         {"PCIERC0_CFG492"              ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     620},
59279         {"PCIERC1_CFG492"              ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     620},
59280         {"PCIERC0_CFG516"              ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     621},
59281         {"PCIERC1_CFG516"              ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     621},
59282         {"PCIERC0_CFG517"              ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     622},
59283         {"PCIERC1_CFG517"              ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     622},
59284         {"PCS0_AN000_ADV_REG"          ,           0x11800B0001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
59285         {"PCS0_AN001_ADV_REG"          ,           0x11800B0001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
59286         {"PCS0_AN002_ADV_REG"          ,           0x11800B0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
59287         {"PCS0_AN003_ADV_REG"          ,           0x11800B0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     623},
59288         {"PCS0_AN000_EXT_ST_REG"       ,           0x11800B0001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
59289         {"PCS0_AN001_EXT_ST_REG"       ,           0x11800B0001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
59290         {"PCS0_AN002_EXT_ST_REG"       ,           0x11800B0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
59291         {"PCS0_AN003_EXT_ST_REG"       ,           0x11800B0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     624},
59292         {"PCS0_AN000_LP_ABIL_REG"      ,           0x11800B0001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
59293         {"PCS0_AN001_LP_ABIL_REG"      ,           0x11800B0001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
59294         {"PCS0_AN002_LP_ABIL_REG"      ,           0x11800B0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
59295         {"PCS0_AN003_LP_ABIL_REG"      ,           0x11800B0001C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     625},
59296         {"PCS0_AN000_RESULTS_REG"      ,           0x11800B0001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
59297         {"PCS0_AN001_RESULTS_REG"      ,           0x11800B0001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
59298         {"PCS0_AN002_RESULTS_REG"      ,           0x11800B0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
59299         {"PCS0_AN003_RESULTS_REG"      ,           0x11800B0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     626},
59300         {"PCS0_INT000_EN_REG"          ,           0x11800B0001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
59301         {"PCS0_INT001_EN_REG"          ,           0x11800B0001488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
59302         {"PCS0_INT002_EN_REG"          ,           0x11800B0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
59303         {"PCS0_INT003_EN_REG"          ,           0x11800B0001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     627},
59304         {"PCS0_INT000_REG"             ,           0x11800B0001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
59305         {"PCS0_INT001_REG"             ,           0x11800B0001480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
59306         {"PCS0_INT002_REG"             ,           0x11800B0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
59307         {"PCS0_INT003_REG"             ,           0x11800B0001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     628},
59308         {"PCS0_LINK000_TIMER_COUNT_REG",           0x11800B0001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
59309         {"PCS0_LINK001_TIMER_COUNT_REG",           0x11800B0001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
59310         {"PCS0_LINK002_TIMER_COUNT_REG",           0x11800B0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
59311         {"PCS0_LINK003_TIMER_COUNT_REG",           0x11800B0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     629},
59312         {"PCS0_LOG_ANL000_REG"         ,           0x11800B0001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
59313         {"PCS0_LOG_ANL001_REG"         ,           0x11800B0001490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
59314         {"PCS0_LOG_ANL002_REG"         ,           0x11800B0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
59315         {"PCS0_LOG_ANL003_REG"         ,           0x11800B0001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     630},
59316         {"PCS0_MISC000_CTL_REG"        ,           0x11800B0001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
59317         {"PCS0_MISC001_CTL_REG"        ,           0x11800B0001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
59318         {"PCS0_MISC002_CTL_REG"        ,           0x11800B0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
59319         {"PCS0_MISC003_CTL_REG"        ,           0x11800B0001C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     631},
59320         {"PCS0_MR000_CONTROL_REG"      ,           0x11800B0001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
59321         {"PCS0_MR001_CONTROL_REG"      ,           0x11800B0001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
59322         {"PCS0_MR002_CONTROL_REG"      ,           0x11800B0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
59323         {"PCS0_MR003_CONTROL_REG"      ,           0x11800B0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     632},
59324         {"PCS0_MR000_STATUS_REG"       ,           0x11800B0001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     633},
59325         {"PCS0_MR001_STATUS_REG"       ,           0x11800B0001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     633},
59326         {"PCS0_MR002_STATUS_REG"       ,           0x11800B0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     633},
59327         {"PCS0_MR003_STATUS_REG"       ,           0x11800B0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     633},
59328         {"PCS0_RX000_STATES_REG"       ,           0x11800B0001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     634},
59329         {"PCS0_RX001_STATES_REG"       ,           0x11800B0001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     634},
59330         {"PCS0_RX002_STATES_REG"       ,           0x11800B0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     634},
59331         {"PCS0_RX003_STATES_REG"       ,           0x11800B0001C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     634},
59332         {"PCS0_RX000_SYNC_REG"         ,           0x11800B0001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     635},
59333         {"PCS0_RX001_SYNC_REG"         ,           0x11800B0001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     635},
59334         {"PCS0_RX002_SYNC_REG"         ,           0x11800B0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     635},
59335         {"PCS0_RX003_SYNC_REG"         ,           0x11800B0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     635},
59336         {"PCS0_SGM000_AN_ADV_REG"      ,           0x11800B0001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     636},
59337         {"PCS0_SGM001_AN_ADV_REG"      ,           0x11800B0001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     636},
59338         {"PCS0_SGM002_AN_ADV_REG"      ,           0x11800B0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     636},
59339         {"PCS0_SGM003_AN_ADV_REG"      ,           0x11800B0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     636},
59340         {"PCS0_SGM000_LP_ADV_REG"      ,           0x11800B0001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     637},
59341         {"PCS0_SGM001_LP_ADV_REG"      ,           0x11800B0001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     637},
59342         {"PCS0_SGM002_LP_ADV_REG"      ,           0x11800B0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     637},
59343         {"PCS0_SGM003_LP_ADV_REG"      ,           0x11800B0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     637},
59344         {"PCS0_TX000_STATES_REG"       ,           0x11800B0001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     638},
59345         {"PCS0_TX001_STATES_REG"       ,           0x11800B0001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     638},
59346         {"PCS0_TX002_STATES_REG"       ,           0x11800B0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     638},
59347         {"PCS0_TX003_STATES_REG"       ,           0x11800B0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     638},
59348         {"PCS0_TX_RX000_POLARITY_REG"  ,           0x11800B0001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     639},
59349         {"PCS0_TX_RX001_POLARITY_REG"  ,           0x11800B0001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     639},
59350         {"PCS0_TX_RX002_POLARITY_REG"  ,           0x11800B0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     639},
59351         {"PCS0_TX_RX003_POLARITY_REG"  ,           0x11800B0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     639},
59352         {"PCSX0_10GBX_STATUS_REG"      ,           0x11800B0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     640},
59353         {"PCSX1_10GBX_STATUS_REG"      ,           0x11800B8000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     640},
59354         {"PCSX0_BIST_STATUS_REG"       ,           0x11800B0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     641},
59355         {"PCSX1_BIST_STATUS_REG"       ,           0x11800B8000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     641},
59356         {"PCSX0_BIT_LOCK_STATUS_REG"   ,           0x11800B0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     642},
59357         {"PCSX1_BIT_LOCK_STATUS_REG"   ,           0x11800B8000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     642},
59358         {"PCSX0_CONTROL1_REG"          ,           0x11800B0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     643},
59359         {"PCSX1_CONTROL1_REG"          ,           0x11800B8000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     643},
59360         {"PCSX0_CONTROL2_REG"          ,           0x11800B0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     644},
59361         {"PCSX1_CONTROL2_REG"          ,           0x11800B8000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     644},
59362         {"PCSX0_INT_EN_REG"            ,           0x11800B0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     645},
59363         {"PCSX1_INT_EN_REG"            ,           0x11800B8000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     645},
59364         {"PCSX0_INT_REG"               ,           0x11800B0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     646},
59365         {"PCSX1_INT_REG"               ,           0x11800B8000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     646},
59366         {"PCSX0_LOG_ANL_REG"           ,           0x11800B0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     647},
59367         {"PCSX1_LOG_ANL_REG"           ,           0x11800B8000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     647},
59368         {"PCSX0_MISC_CTL_REG"          ,           0x11800B0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     648},
59369         {"PCSX1_MISC_CTL_REG"          ,           0x11800B8000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     648},
59370         {"PCSX0_RX_SYNC_STATES_REG"    ,           0x11800B0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     649},
59371         {"PCSX1_RX_SYNC_STATES_REG"    ,           0x11800B8000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     649},
59372         {"PCSX0_SPD_ABIL_REG"          ,           0x11800B0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     650},
59373         {"PCSX1_SPD_ABIL_REG"          ,           0x11800B8000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     650},
59374         {"PCSX0_STATUS1_REG"           ,           0x11800B0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     651},
59375         {"PCSX1_STATUS1_REG"           ,           0x11800B8000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     651},
59376         {"PCSX0_STATUS2_REG"           ,           0x11800B0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     652},
59377         {"PCSX1_STATUS2_REG"           ,           0x11800B8000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     652},
59378         {"PCSX0_TX_RX_POLARITY_REG"    ,           0x11800B0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     653},
59379         {"PCSX1_TX_RX_POLARITY_REG"    ,           0x11800B8000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     653},
59380         {"PCSX0_TX_RX_STATES_REG"      ,           0x11800B0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     654},
59381         {"PCSX1_TX_RX_STATES_REG"      ,           0x11800B8000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     654},
59382         {"PESC0_BIST_STATUS"           ,           0x11800C8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     655},
59383         {"PESC1_BIST_STATUS"           ,           0x11800D0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     655},
59384         {"PESC0_BIST_STATUS2"          ,           0x11800C8000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     656},
59385         {"PESC1_BIST_STATUS2"          ,           0x11800D0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     656},
59386         {"PESC0_CFG_RD"                ,           0x11800C8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     657},
59387         {"PESC1_CFG_RD"                ,           0x11800D0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     657},
59388         {"PESC0_CFG_WR"                ,           0x11800C8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     658},
59389         {"PESC1_CFG_WR"                ,           0x11800D0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     658},
59390         {"PESC0_CPL_LUT_VALID"         ,           0x11800C8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     659},
59391         {"PESC1_CPL_LUT_VALID"         ,           0x11800D0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     659},
59392         {"PESC0_CTL_STATUS"            ,           0x11800C8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     660},
59393         {"PESC1_CTL_STATUS"            ,           0x11800D0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     660},
59394         {"PESC0_CTL_STATUS2"           ,           0x11800C8000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
59395         {"PESC1_CTL_STATUS2"           ,           0x11800D0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     661},
59396         {"PESC0_DBG_INFO"              ,           0x11800C8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
59397         {"PESC1_DBG_INFO"              ,           0x11800D0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     662},
59398         {"PESC0_DBG_INFO_EN"           ,           0x11800C80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     663},
59399         {"PESC1_DBG_INFO_EN"           ,           0x11800D00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     663},
59400         {"PESC0_DIAG_STATUS"           ,           0x11800C8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     664},
59401         {"PESC1_DIAG_STATUS"           ,           0x11800D0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     664},
59402         {"PESC0_P2N_BAR0_START"        ,           0x11800C8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     665},
59403         {"PESC1_P2N_BAR0_START"        ,           0x11800D0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     665},
59404         {"PESC0_P2N_BAR1_START"        ,           0x11800C8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     666},
59405         {"PESC1_P2N_BAR1_START"        ,           0x11800D0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     666},
59406         {"PESC0_P2N_BAR2_START"        ,           0x11800C8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     667},
59407         {"PESC1_P2N_BAR2_START"        ,           0x11800D0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     667},
59408         {"PESC0_P2P_BAR000_END"        ,           0x11800C8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     668},
59409         {"PESC0_P2P_BAR001_END"        ,           0x11800C8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     668},
59410         {"PESC0_P2P_BAR002_END"        ,           0x11800C8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     668},
59411         {"PESC0_P2P_BAR003_END"        ,           0x11800C8000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     668},
59412         {"PESC1_P2P_BAR000_END"        ,           0x11800D0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     668},
59413         {"PESC1_P2P_BAR001_END"        ,           0x11800D0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     668},
59414         {"PESC1_P2P_BAR002_END"        ,           0x11800D0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     668},
59415         {"PESC1_P2P_BAR003_END"        ,           0x11800D0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     668},
59416         {"PESC0_P2P_BAR000_START"      ,           0x11800C8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     669},
59417         {"PESC0_P2P_BAR001_START"      ,           0x11800C8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     669},
59418         {"PESC0_P2P_BAR002_START"      ,           0x11800C8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     669},
59419         {"PESC0_P2P_BAR003_START"      ,           0x11800C8000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     669},
59420         {"PESC1_P2P_BAR000_START"      ,           0x11800D0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     669},
59421         {"PESC1_P2P_BAR001_START"      ,           0x11800D0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     669},
59422         {"PESC1_P2P_BAR002_START"      ,           0x11800D0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     669},
59423         {"PESC1_P2P_BAR003_START"      ,           0x11800D0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     669},
59424         {"PESC0_TLP_CREDITS"           ,           0x11800C8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     670},
59425         {"PESC1_TLP_CREDITS"           ,           0x11800D0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     670},
59426         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     671},
59427         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     672},
59428         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     672},
59429         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     672},
59430         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     672},
59431         {"PIP_DSA_SRC_GRP"             ,           0x11800A0000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     673},
59432         {"PIP_DSA_VID_GRP"             ,           0x11800A0000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     674},
59433         {"PIP_FRM_LEN_CHK0"            ,           0x11800A0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
59434         {"PIP_FRM_LEN_CHK1"            ,           0x11800A0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     675},
59435         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     676},
59436         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     677},
59437         {"PIP_HG_PRI_QOS"              ,           0x11800A00001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     678},
59438         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     679},
59439         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     680},
59440         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     681},
59441         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
59442         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
59443         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
59444         {"PIP_PRT_CFG3"                ,           0x11800A0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
59445         {"PIP_PRT_CFG36"               ,           0x11800A0000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
59446         {"PIP_PRT_CFG37"               ,           0x11800A0000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
59447         {"PIP_PRT_CFG38"               ,           0x11800A0000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
59448         {"PIP_PRT_CFG39"               ,           0x11800A0000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     682},
59449         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
59450         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
59451         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
59452         {"PIP_PRT_TAG3"                ,           0x11800A0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
59453         {"PIP_PRT_TAG36"               ,           0x11800A0000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
59454         {"PIP_PRT_TAG37"               ,           0x11800A0000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
59455         {"PIP_PRT_TAG38"               ,           0x11800A0000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
59456         {"PIP_PRT_TAG39"               ,           0x11800A0000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     683},
59457         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59458         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59459         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59460         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59461         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59462         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59463         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59464         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59465         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59466         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59467         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59468         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59469         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59470         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59471         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59472         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59473         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59474         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59475         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59476         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59477         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59478         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59479         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59480         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59481         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59482         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59483         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59484         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59485         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59486         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59487         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59488         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59489         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59490         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59491         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59492         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59493         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59494         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59495         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59496         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59497         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59498         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59499         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59500         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59501         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59502         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59503         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59504         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59505         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59506         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59507         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59508         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59509         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59510         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59511         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59512         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59513         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59514         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59515         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59516         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59517         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59518         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59519         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59520         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     684},
59521         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
59522         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
59523         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
59524         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
59525         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
59526         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
59527         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
59528         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     685},
59529         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
59530         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
59531         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
59532         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
59533         {"PIP_QOS_WATCH4"              ,           0x11800A0000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
59534         {"PIP_QOS_WATCH5"              ,           0x11800A0000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
59535         {"PIP_QOS_WATCH6"              ,           0x11800A0000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
59536         {"PIP_QOS_WATCH7"              ,           0x11800A0000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     686},
59537         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     687},
59538         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     688},
59539         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
59540         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
59541         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
59542         {"PIP_STAT0_PRT3"              ,           0x11800A00008F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
59543         {"PIP_STAT0_PRT36"             ,           0x11800A0001340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
59544         {"PIP_STAT0_PRT37"             ,           0x11800A0001390ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
59545         {"PIP_STAT0_PRT38"             ,           0x11800A00013E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
59546         {"PIP_STAT0_PRT39"             ,           0x11800A0001430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     689},
59547         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
59548         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
59549         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
59550         {"PIP_STAT1_PRT3"              ,           0x11800A00008F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
59551         {"PIP_STAT1_PRT36"             ,           0x11800A0001348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
59552         {"PIP_STAT1_PRT37"             ,           0x11800A0001398ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
59553         {"PIP_STAT1_PRT38"             ,           0x11800A00013E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
59554         {"PIP_STAT1_PRT39"             ,           0x11800A0001438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     690},
59555         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
59556         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
59557         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
59558         {"PIP_STAT2_PRT3"              ,           0x11800A0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
59559         {"PIP_STAT2_PRT36"             ,           0x11800A0001350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
59560         {"PIP_STAT2_PRT37"             ,           0x11800A00013A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
59561         {"PIP_STAT2_PRT38"             ,           0x11800A00013F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
59562         {"PIP_STAT2_PRT39"             ,           0x11800A0001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     691},
59563         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
59564         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
59565         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
59566         {"PIP_STAT3_PRT3"              ,           0x11800A0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
59567         {"PIP_STAT3_PRT36"             ,           0x11800A0001358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
59568         {"PIP_STAT3_PRT37"             ,           0x11800A00013A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
59569         {"PIP_STAT3_PRT38"             ,           0x11800A00013F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
59570         {"PIP_STAT3_PRT39"             ,           0x11800A0001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     692},
59571         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
59572         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
59573         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
59574         {"PIP_STAT4_PRT3"              ,           0x11800A0000910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
59575         {"PIP_STAT4_PRT36"             ,           0x11800A0001360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
59576         {"PIP_STAT4_PRT37"             ,           0x11800A00013B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
59577         {"PIP_STAT4_PRT38"             ,           0x11800A0001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
59578         {"PIP_STAT4_PRT39"             ,           0x11800A0001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     693},
59579         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
59580         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
59581         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
59582         {"PIP_STAT5_PRT3"              ,           0x11800A0000918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
59583         {"PIP_STAT5_PRT36"             ,           0x11800A0001368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
59584         {"PIP_STAT5_PRT37"             ,           0x11800A00013B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
59585         {"PIP_STAT5_PRT38"             ,           0x11800A0001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
59586         {"PIP_STAT5_PRT39"             ,           0x11800A0001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
59587         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
59588         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
59589         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
59590         {"PIP_STAT6_PRT3"              ,           0x11800A0000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
59591         {"PIP_STAT6_PRT36"             ,           0x11800A0001370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
59592         {"PIP_STAT6_PRT37"             ,           0x11800A00013C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
59593         {"PIP_STAT6_PRT38"             ,           0x11800A0001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
59594         {"PIP_STAT6_PRT39"             ,           0x11800A0001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
59595         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
59596         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
59597         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
59598         {"PIP_STAT7_PRT3"              ,           0x11800A0000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
59599         {"PIP_STAT7_PRT36"             ,           0x11800A0001378ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
59600         {"PIP_STAT7_PRT37"             ,           0x11800A00013C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
59601         {"PIP_STAT7_PRT38"             ,           0x11800A0001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
59602         {"PIP_STAT7_PRT39"             ,           0x11800A0001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
59603         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
59604         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
59605         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
59606         {"PIP_STAT8_PRT3"              ,           0x11800A0000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
59607         {"PIP_STAT8_PRT36"             ,           0x11800A0001380ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
59608         {"PIP_STAT8_PRT37"             ,           0x11800A00013D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
59609         {"PIP_STAT8_PRT38"             ,           0x11800A0001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
59610         {"PIP_STAT8_PRT39"             ,           0x11800A0001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
59611         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
59612         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
59613         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
59614         {"PIP_STAT9_PRT3"              ,           0x11800A0000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
59615         {"PIP_STAT9_PRT36"             ,           0x11800A0001388ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
59616         {"PIP_STAT9_PRT37"             ,           0x11800A00013D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
59617         {"PIP_STAT9_PRT38"             ,           0x11800A0001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
59618         {"PIP_STAT9_PRT39"             ,           0x11800A0001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
59619         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     699},
59620         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
59621         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
59622         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
59623         {"PIP_STAT_INB_ERRS3"          ,           0x11800A0001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
59624         {"PIP_STAT_INB_ERRS36"         ,           0x11800A0001E90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
59625         {"PIP_STAT_INB_ERRS37"         ,           0x11800A0001EB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
59626         {"PIP_STAT_INB_ERRS38"         ,           0x11800A0001ED0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
59627         {"PIP_STAT_INB_ERRS39"         ,           0x11800A0001EF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
59628         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
59629         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
59630         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
59631         {"PIP_STAT_INB_OCTS3"          ,           0x11800A0001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
59632         {"PIP_STAT_INB_OCTS36"         ,           0x11800A0001E88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
59633         {"PIP_STAT_INB_OCTS37"         ,           0x11800A0001EA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
59634         {"PIP_STAT_INB_OCTS38"         ,           0x11800A0001EC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
59635         {"PIP_STAT_INB_OCTS39"         ,           0x11800A0001EE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
59636         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
59637         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
59638         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
59639         {"PIP_STAT_INB_PKTS3"          ,           0x11800A0001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
59640         {"PIP_STAT_INB_PKTS36"         ,           0x11800A0001E80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
59641         {"PIP_STAT_INB_PKTS37"         ,           0x11800A0001EA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
59642         {"PIP_STAT_INB_PKTS38"         ,           0x11800A0001EC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
59643         {"PIP_STAT_INB_PKTS39"         ,           0x11800A0001EE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
59644         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59645         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59646         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59647         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59648         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59649         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59650         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59651         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59652         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59653         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59654         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59655         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59656         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59657         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59658         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59659         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59660         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59661         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59662         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59663         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59664         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59665         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59666         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59667         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59668         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59669         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59670         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59671         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59672         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59673         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59674         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59675         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59676         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59677         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59678         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59679         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59680         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59681         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59682         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59683         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59684         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59685         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59686         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59687         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59688         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59689         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59690         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59691         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59692         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59693         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59694         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59695         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59696         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59697         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59698         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59699         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59700         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59701         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59702         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59703         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59704         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59705         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59706         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59707         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
59708         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     704},
59709         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     705},
59710         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     706},
59711         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     707},
59712         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     708},
59713         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     709},
59714         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     710},
59715         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     711},
59716         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     712},
59717         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     713},
59718         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     714},
59719         {"PKO_MEM_DEBUG14"             ,           0x1180050001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     715},
59720         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     716},
59721         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     717},
59722         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     718},
59723         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     719},
59724         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     720},
59725         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     721},
59726         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     722},
59727         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     723},
59728         {"PKO_MEM_PORT_PTRS"           ,           0x1180050001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
59729         {"PKO_MEM_PORT_QOS"            ,           0x1180050001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
59730         {"PKO_MEM_PORT_RATE0"          ,           0x1180050001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     726},
59731         {"PKO_MEM_PORT_RATE1"          ,           0x1180050001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     727},
59732         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     728},
59733         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     729},
59734         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     730},
59735         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     731},
59736         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     732},
59737         {"PKO_REG_DEBUG1"              ,           0x11800500000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     733},
59738         {"PKO_REG_DEBUG2"              ,           0x11800500000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     734},
59739         {"PKO_REG_DEBUG3"              ,           0x11800500000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     735},
59740         {"PKO_REG_ENGINE_INFLIGHT"     ,           0x1180050000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     736},
59741         {"PKO_REG_ENGINE_THRESH"       ,           0x1180050000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     737},
59742         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     738},
59743         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
59744         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
59745         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
59746         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
59747         {"PKO_REG_QUEUE_PTRS1"         ,           0x1180050000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
59748         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     744},
59749         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     745},
59750         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     746},
59751         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     747},
59752         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     748},
59753         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
59754         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
59755         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
59756         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
59757         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
59758         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
59759         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
59760         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     749},
59761         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     750},
59762         {"POW_IQ_INT"                  ,           0x1670000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     751},
59763         {"POW_IQ_INT_EN"               ,           0x1670000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     752},
59764         {"POW_IQ_THR0"                 ,           0x16700000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
59765         {"POW_IQ_THR1"                 ,           0x16700000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
59766         {"POW_IQ_THR2"                 ,           0x16700000003B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
59767         {"POW_IQ_THR3"                 ,           0x16700000003B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
59768         {"POW_IQ_THR4"                 ,           0x16700000003C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
59769         {"POW_IQ_THR5"                 ,           0x16700000003C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
59770         {"POW_IQ_THR6"                 ,           0x16700000003D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
59771         {"POW_IQ_THR7"                 ,           0x16700000003D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     753},
59772         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     754},
59773         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     755},
59774         {"POW_PF_RST_MSK"              ,           0x1670000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     756},
59775         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
59776         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
59777         {"POW_PP_GRP_MSK2"             ,           0x1670000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
59778         {"POW_PP_GRP_MSK3"             ,           0x1670000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     757},
59779         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
59780         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
59781         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
59782         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
59783         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
59784         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
59785         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
59786         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     758},
59787         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     759},
59788         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     759},
59789         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     759},
59790         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     759},
59791         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     759},
59792         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     759},
59793         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     759},
59794         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     759},
59795         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     760},
59796         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     761},
59797         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     762},
59798         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     762},
59799         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     762},
59800         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     762},
59801         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     762},
59802         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     762},
59803         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     762},
59804         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     762},
59805         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     763},
59806         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59807         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59808         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59809         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59810         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59811         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59812         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59813         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59814         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59815         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59816         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59817         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59818         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59819         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59820         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59821         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     764},
59822         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     765},
59823         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59824         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59825         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59826         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59827         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59828         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59829         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59830         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59831         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59832         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59833         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59834         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59835         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59836         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59837         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59838         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     766},
59839         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59840         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59841         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59842         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59843         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59844         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59845         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59846         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59847         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59848         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59849         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59850         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59851         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59852         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59853         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59854         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     767},
59855         {"RAD_MEM_DEBUG0"              ,           0x1180070001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
59856         {"RAD_MEM_DEBUG1"              ,           0x1180070001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
59857         {"RAD_MEM_DEBUG2"              ,           0x1180070001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     770},
59858         {"RAD_REG_BIST_RESULT"         ,           0x1180070000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
59859         {"RAD_REG_CMD_BUF"             ,           0x1180070000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
59860         {"RAD_REG_CTL"                 ,           0x1180070000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
59861         {"RAD_REG_DEBUG0"              ,           0x1180070000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
59862         {"RAD_REG_DEBUG1"              ,           0x1180070000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     775},
59863         {"RAD_REG_DEBUG10"             ,           0x1180070000150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     776},
59864         {"RAD_REG_DEBUG11"             ,           0x1180070000158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     777},
59865         {"RAD_REG_DEBUG12"             ,           0x1180070000160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     778},
59866         {"RAD_REG_DEBUG2"              ,           0x1180070000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     779},
59867         {"RAD_REG_DEBUG3"              ,           0x1180070000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     780},
59868         {"RAD_REG_DEBUG4"              ,           0x1180070000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     781},
59869         {"RAD_REG_DEBUG5"              ,           0x1180070000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     782},
59870         {"RAD_REG_DEBUG6"              ,           0x1180070000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     783},
59871         {"RAD_REG_DEBUG7"              ,           0x1180070000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     784},
59872         {"RAD_REG_DEBUG8"              ,           0x1180070000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     785},
59873         {"RAD_REG_DEBUG9"              ,           0x1180070000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     786},
59874         {"RAD_REG_ERROR"               ,           0x1180070000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     787},
59875         {"RAD_REG_INT_MASK"            ,           0x1180070000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     788},
59876         {"RAD_REG_POLYNOMIAL"          ,           0x1180070000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     789},
59877         {"RAD_REG_READ_IDX"            ,           0x1180070000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     790},
59878         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     791},
59879         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     792},
59880         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     793},
59881         {"SMI1_CLK"                    ,           0x1180000001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     793},
59882         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     794},
59883         {"SMI1_CMD"                    ,           0x1180000001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     794},
59884         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     795},
59885         {"SMI1_EN"                     ,           0x1180000001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     795},
59886         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     796},
59887         {"SMI1_RD_DAT"                 ,           0x1180000001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     796},
59888         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     797},
59889         {"SMI1_WR_DAT"                 ,           0x1180000001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     797},
59890         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     798},
59891         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     799},
59892         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     800},
59893         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     801},
59894         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     802},
59895         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     803},
59896         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     804},
59897         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     805},
59898         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     806},
59899         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     807},
59900         {"TRA_BIST_STATUS"             ,           0x11800A8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     808},
59901         {"TRA_CTL"                     ,           0x11800A8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     809},
59902         {"TRA_CYCLES_SINCE"            ,           0x11800A8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     810},
59903         {"TRA_CYCLES_SINCE1"           ,           0x11800A8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     811},
59904         {"TRA_FILT_ADR_ADR"            ,           0x11800A8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     812},
59905         {"TRA_FILT_ADR_MSK"            ,           0x11800A8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     813},
59906         {"TRA_FILT_CMD"                ,           0x11800A8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     814},
59907         {"TRA_FILT_DID"                ,           0x11800A8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     815},
59908         {"TRA_FILT_SID"                ,           0x11800A8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     816},
59909         {"TRA_INT_STATUS"              ,           0x11800A8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     817},
59910         {"TRA_READ_DAT"                ,           0x11800A8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     818},
59911         {"TRA_TRIG0_ADR_ADR"           ,           0x11800A8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     819},
59912         {"TRA_TRIG0_ADR_MSK"           ,           0x11800A80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     820},
59913         {"TRA_TRIG0_CMD"               ,           0x11800A8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     821},
59914         {"TRA_TRIG0_DID"               ,           0x11800A8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     822},
59915         {"TRA_TRIG0_SID"               ,           0x11800A8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     823},
59916         {"TRA_TRIG1_ADR_ADR"           ,           0x11800A80000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     824},
59917         {"TRA_TRIG1_ADR_MSK"           ,           0x11800A80000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     825},
59918         {"TRA_TRIG1_CMD"               ,           0x11800A80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     826},
59919         {"TRA_TRIG1_DID"               ,           0x11800A80000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     827},
59920         {"TRA_TRIG1_SID"               ,           0x11800A80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     828},
59921         {"USBC0_DAINT"                 ,           0x16F0010000818ull,  CVMX_CSR_DB_TYPE_NCB,   32,     829},
59922         {"USBC1_DAINT"                 ,           0x17F0010000818ull,  CVMX_CSR_DB_TYPE_NCB,   32,     829},
59923         {"USBC0_DAINTMSK"              ,           0x16F001000081Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     830},
59924         {"USBC1_DAINTMSK"              ,           0x17F001000081Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     830},
59925         {"USBC0_DCFG"                  ,           0x16F0010000800ull,  CVMX_CSR_DB_TYPE_NCB,   32,     831},
59926         {"USBC1_DCFG"                  ,           0x17F0010000800ull,  CVMX_CSR_DB_TYPE_NCB,   32,     831},
59927         {"USBC0_DCTL"                  ,           0x16F0010000804ull,  CVMX_CSR_DB_TYPE_NCB,   32,     832},
59928         {"USBC1_DCTL"                  ,           0x17F0010000804ull,  CVMX_CSR_DB_TYPE_NCB,   32,     832},
59929         {"USBC0_DIEPCTL000"            ,           0x16F0010000900ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59930         {"USBC0_DIEPCTL001"            ,           0x16F0010000920ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59931         {"USBC0_DIEPCTL002"            ,           0x16F0010000940ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59932         {"USBC0_DIEPCTL003"            ,           0x16F0010000960ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59933         {"USBC0_DIEPCTL004"            ,           0x16F0010000980ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59934         {"USBC1_DIEPCTL000"            ,           0x17F0010000900ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59935         {"USBC1_DIEPCTL001"            ,           0x17F0010000920ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59936         {"USBC1_DIEPCTL002"            ,           0x17F0010000940ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59937         {"USBC1_DIEPCTL003"            ,           0x17F0010000960ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59938         {"USBC1_DIEPCTL004"            ,           0x17F0010000980ull,  CVMX_CSR_DB_TYPE_NCB,   32,     833},
59939         {"USBC0_DIEPINT000"            ,           0x16F0010000908ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59940         {"USBC0_DIEPINT001"            ,           0x16F0010000928ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59941         {"USBC0_DIEPINT002"            ,           0x16F0010000948ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59942         {"USBC0_DIEPINT003"            ,           0x16F0010000968ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59943         {"USBC0_DIEPINT004"            ,           0x16F0010000988ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59944         {"USBC1_DIEPINT000"            ,           0x17F0010000908ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59945         {"USBC1_DIEPINT001"            ,           0x17F0010000928ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59946         {"USBC1_DIEPINT002"            ,           0x17F0010000948ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59947         {"USBC1_DIEPINT003"            ,           0x17F0010000968ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59948         {"USBC1_DIEPINT004"            ,           0x17F0010000988ull,  CVMX_CSR_DB_TYPE_NCB,   32,     834},
59949         {"USBC0_DIEPMSK"               ,           0x16F0010000810ull,  CVMX_CSR_DB_TYPE_NCB,   32,     835},
59950         {"USBC1_DIEPMSK"               ,           0x17F0010000810ull,  CVMX_CSR_DB_TYPE_NCB,   32,     835},
59951         {"USBC0_DIEPTSIZ000"           ,           0x16F0010000910ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59952         {"USBC0_DIEPTSIZ001"           ,           0x16F0010000930ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59953         {"USBC0_DIEPTSIZ002"           ,           0x16F0010000950ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59954         {"USBC0_DIEPTSIZ003"           ,           0x16F0010000970ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59955         {"USBC0_DIEPTSIZ004"           ,           0x16F0010000990ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59956         {"USBC1_DIEPTSIZ000"           ,           0x17F0010000910ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59957         {"USBC1_DIEPTSIZ001"           ,           0x17F0010000930ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59958         {"USBC1_DIEPTSIZ002"           ,           0x17F0010000950ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59959         {"USBC1_DIEPTSIZ003"           ,           0x17F0010000970ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59960         {"USBC1_DIEPTSIZ004"           ,           0x17F0010000990ull,  CVMX_CSR_DB_TYPE_NCB,   32,     836},
59961         {"USBC0_DOEPCTL000"            ,           0x16F0010000B00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59962         {"USBC0_DOEPCTL001"            ,           0x16F0010000B20ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59963         {"USBC0_DOEPCTL002"            ,           0x16F0010000B40ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59964         {"USBC0_DOEPCTL003"            ,           0x16F0010000B60ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59965         {"USBC0_DOEPCTL004"            ,           0x16F0010000B80ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59966         {"USBC1_DOEPCTL000"            ,           0x17F0010000B00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59967         {"USBC1_DOEPCTL001"            ,           0x17F0010000B20ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59968         {"USBC1_DOEPCTL002"            ,           0x17F0010000B40ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59969         {"USBC1_DOEPCTL003"            ,           0x17F0010000B60ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59970         {"USBC1_DOEPCTL004"            ,           0x17F0010000B80ull,  CVMX_CSR_DB_TYPE_NCB,   32,     837},
59971         {"USBC0_DOEPINT000"            ,           0x16F0010000B08ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59972         {"USBC0_DOEPINT001"            ,           0x16F0010000B28ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59973         {"USBC0_DOEPINT002"            ,           0x16F0010000B48ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59974         {"USBC0_DOEPINT003"            ,           0x16F0010000B68ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59975         {"USBC0_DOEPINT004"            ,           0x16F0010000B88ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59976         {"USBC1_DOEPINT000"            ,           0x17F0010000B08ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59977         {"USBC1_DOEPINT001"            ,           0x17F0010000B28ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59978         {"USBC1_DOEPINT002"            ,           0x17F0010000B48ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59979         {"USBC1_DOEPINT003"            ,           0x17F0010000B68ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59980         {"USBC1_DOEPINT004"            ,           0x17F0010000B88ull,  CVMX_CSR_DB_TYPE_NCB,   32,     838},
59981         {"USBC0_DOEPMSK"               ,           0x16F0010000814ull,  CVMX_CSR_DB_TYPE_NCB,   32,     839},
59982         {"USBC1_DOEPMSK"               ,           0x17F0010000814ull,  CVMX_CSR_DB_TYPE_NCB,   32,     839},
59983         {"USBC0_DOEPTSIZ000"           ,           0x16F0010000B10ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59984         {"USBC0_DOEPTSIZ001"           ,           0x16F0010000B30ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59985         {"USBC0_DOEPTSIZ002"           ,           0x16F0010000B50ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59986         {"USBC0_DOEPTSIZ003"           ,           0x16F0010000B70ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59987         {"USBC0_DOEPTSIZ004"           ,           0x16F0010000B90ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59988         {"USBC1_DOEPTSIZ000"           ,           0x17F0010000B10ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59989         {"USBC1_DOEPTSIZ001"           ,           0x17F0010000B30ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59990         {"USBC1_DOEPTSIZ002"           ,           0x17F0010000B50ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59991         {"USBC1_DOEPTSIZ003"           ,           0x17F0010000B70ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59992         {"USBC1_DOEPTSIZ004"           ,           0x17F0010000B90ull,  CVMX_CSR_DB_TYPE_NCB,   32,     840},
59993         {"USBC0_DPTXFSIZ001"           ,           0x16F0010000104ull,  CVMX_CSR_DB_TYPE_NCB,   32,     841},
59994         {"USBC0_DPTXFSIZ002"           ,           0x16F0010000108ull,  CVMX_CSR_DB_TYPE_NCB,   32,     841},
59995         {"USBC0_DPTXFSIZ003"           ,           0x16F001000010Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     841},
59996         {"USBC0_DPTXFSIZ004"           ,           0x16F0010000110ull,  CVMX_CSR_DB_TYPE_NCB,   32,     841},
59997         {"USBC1_DPTXFSIZ001"           ,           0x17F0010000104ull,  CVMX_CSR_DB_TYPE_NCB,   32,     841},
59998         {"USBC1_DPTXFSIZ002"           ,           0x17F0010000108ull,  CVMX_CSR_DB_TYPE_NCB,   32,     841},
59999         {"USBC1_DPTXFSIZ003"           ,           0x17F001000010Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     841},
60000         {"USBC1_DPTXFSIZ004"           ,           0x17F0010000110ull,  CVMX_CSR_DB_TYPE_NCB,   32,     841},
60001         {"USBC0_DSTS"                  ,           0x16F0010000808ull,  CVMX_CSR_DB_TYPE_NCB,   32,     842},
60002         {"USBC1_DSTS"                  ,           0x17F0010000808ull,  CVMX_CSR_DB_TYPE_NCB,   32,     842},
60003         {"USBC0_DTKNQR1"               ,           0x16F0010000820ull,  CVMX_CSR_DB_TYPE_NCB,   32,     843},
60004         {"USBC1_DTKNQR1"               ,           0x17F0010000820ull,  CVMX_CSR_DB_TYPE_NCB,   32,     843},
60005         {"USBC0_DTKNQR2"               ,           0x16F0010000824ull,  CVMX_CSR_DB_TYPE_NCB,   32,     844},
60006         {"USBC1_DTKNQR2"               ,           0x17F0010000824ull,  CVMX_CSR_DB_TYPE_NCB,   32,     844},
60007         {"USBC0_DTKNQR3"               ,           0x16F0010000830ull,  CVMX_CSR_DB_TYPE_NCB,   32,     845},
60008         {"USBC1_DTKNQR3"               ,           0x17F0010000830ull,  CVMX_CSR_DB_TYPE_NCB,   32,     845},
60009         {"USBC0_DTKNQR4"               ,           0x16F0010000834ull,  CVMX_CSR_DB_TYPE_NCB,   32,     846},
60010         {"USBC1_DTKNQR4"               ,           0x17F0010000834ull,  CVMX_CSR_DB_TYPE_NCB,   32,     846},
60011         {"USBC0_GAHBCFG"               ,           0x16F0010000008ull,  CVMX_CSR_DB_TYPE_NCB,   32,     847},
60012         {"USBC1_GAHBCFG"               ,           0x17F0010000008ull,  CVMX_CSR_DB_TYPE_NCB,   32,     847},
60013         {"USBC0_GHWCFG1"               ,           0x16F0010000044ull,  CVMX_CSR_DB_TYPE_NCB,   32,     848},
60014         {"USBC1_GHWCFG1"               ,           0x17F0010000044ull,  CVMX_CSR_DB_TYPE_NCB,   32,     848},
60015         {"USBC0_GHWCFG2"               ,           0x16F0010000048ull,  CVMX_CSR_DB_TYPE_NCB,   32,     849},
60016         {"USBC1_GHWCFG2"               ,           0x17F0010000048ull,  CVMX_CSR_DB_TYPE_NCB,   32,     849},
60017         {"USBC0_GHWCFG3"               ,           0x16F001000004Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     850},
60018         {"USBC1_GHWCFG3"               ,           0x17F001000004Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     850},
60019         {"USBC0_GHWCFG4"               ,           0x16F0010000050ull,  CVMX_CSR_DB_TYPE_NCB,   32,     851},
60020         {"USBC1_GHWCFG4"               ,           0x17F0010000050ull,  CVMX_CSR_DB_TYPE_NCB,   32,     851},
60021         {"USBC0_GINTMSK"               ,           0x16F0010000018ull,  CVMX_CSR_DB_TYPE_NCB,   32,     852},
60022         {"USBC1_GINTMSK"               ,           0x17F0010000018ull,  CVMX_CSR_DB_TYPE_NCB,   32,     852},
60023         {"USBC0_GINTSTS"               ,           0x16F0010000014ull,  CVMX_CSR_DB_TYPE_NCB,   32,     853},
60024         {"USBC1_GINTSTS"               ,           0x17F0010000014ull,  CVMX_CSR_DB_TYPE_NCB,   32,     853},
60025         {"USBC0_GNPTXFSIZ"             ,           0x16F0010000028ull,  CVMX_CSR_DB_TYPE_NCB,   32,     854},
60026         {"USBC1_GNPTXFSIZ"             ,           0x17F0010000028ull,  CVMX_CSR_DB_TYPE_NCB,   32,     854},
60027         {"USBC0_GNPTXSTS"              ,           0x16F001000002Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     855},
60028         {"USBC1_GNPTXSTS"              ,           0x17F001000002Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     855},
60029         {"USBC0_GOTGCTL"               ,           0x16F0010000000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     856},
60030         {"USBC1_GOTGCTL"               ,           0x17F0010000000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     856},
60031         {"USBC0_GOTGINT"               ,           0x16F0010000004ull,  CVMX_CSR_DB_TYPE_NCB,   32,     857},
60032         {"USBC1_GOTGINT"               ,           0x17F0010000004ull,  CVMX_CSR_DB_TYPE_NCB,   32,     857},
60033         {"USBC0_GRSTCTL"               ,           0x16F0010000010ull,  CVMX_CSR_DB_TYPE_NCB,   32,     858},
60034         {"USBC1_GRSTCTL"               ,           0x17F0010000010ull,  CVMX_CSR_DB_TYPE_NCB,   32,     858},
60035         {"USBC0_GRXFSIZ"               ,           0x16F0010000024ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
60036         {"USBC1_GRXFSIZ"               ,           0x17F0010000024ull,  CVMX_CSR_DB_TYPE_NCB,   32,     859},
60037         {"USBC0_GRXSTSPD"              ,           0x16F0010040020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     860},
60038         {"USBC1_GRXSTSPD"              ,           0x17F0010040020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     860},
60039         {"USBC0_GRXSTSPH"              ,           0x16F0010000020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
60040         {"USBC1_GRXSTSPH"              ,           0x17F0010000020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     861},
60041         {"USBC0_GRXSTSRD"              ,           0x16F001004001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
60042         {"USBC1_GRXSTSRD"              ,           0x17F001004001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     862},
60043         {"USBC0_GRXSTSRH"              ,           0x16F001000001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
60044         {"USBC1_GRXSTSRH"              ,           0x17F001000001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     863},
60045         {"USBC0_GSNPSID"               ,           0x16F0010000040ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
60046         {"USBC1_GSNPSID"               ,           0x17F0010000040ull,  CVMX_CSR_DB_TYPE_NCB,   32,     864},
60047         {"USBC0_GUSBCFG"               ,           0x16F001000000Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     865},
60048         {"USBC1_GUSBCFG"               ,           0x17F001000000Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     865},
60049         {"USBC0_HAINT"                 ,           0x16F0010000414ull,  CVMX_CSR_DB_TYPE_NCB,   32,     866},
60050         {"USBC1_HAINT"                 ,           0x17F0010000414ull,  CVMX_CSR_DB_TYPE_NCB,   32,     866},
60051         {"USBC0_HAINTMSK"              ,           0x16F0010000418ull,  CVMX_CSR_DB_TYPE_NCB,   32,     867},
60052         {"USBC1_HAINTMSK"              ,           0x17F0010000418ull,  CVMX_CSR_DB_TYPE_NCB,   32,     867},
60053         {"USBC0_HCCHAR000"             ,           0x16F0010000500ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60054         {"USBC0_HCCHAR001"             ,           0x16F0010000520ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60055         {"USBC0_HCCHAR002"             ,           0x16F0010000540ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60056         {"USBC0_HCCHAR003"             ,           0x16F0010000560ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60057         {"USBC0_HCCHAR004"             ,           0x16F0010000580ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60058         {"USBC0_HCCHAR005"             ,           0x16F00100005A0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60059         {"USBC0_HCCHAR006"             ,           0x16F00100005C0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60060         {"USBC0_HCCHAR007"             ,           0x16F00100005E0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60061         {"USBC1_HCCHAR000"             ,           0x17F0010000500ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60062         {"USBC1_HCCHAR001"             ,           0x17F0010000520ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60063         {"USBC1_HCCHAR002"             ,           0x17F0010000540ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60064         {"USBC1_HCCHAR003"             ,           0x17F0010000560ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60065         {"USBC1_HCCHAR004"             ,           0x17F0010000580ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60066         {"USBC1_HCCHAR005"             ,           0x17F00100005A0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60067         {"USBC1_HCCHAR006"             ,           0x17F00100005C0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60068         {"USBC1_HCCHAR007"             ,           0x17F00100005E0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     868},
60069         {"USBC0_HCFG"                  ,           0x16F0010000400ull,  CVMX_CSR_DB_TYPE_NCB,   32,     869},
60070         {"USBC1_HCFG"                  ,           0x17F0010000400ull,  CVMX_CSR_DB_TYPE_NCB,   32,     869},
60071         {"USBC0_HCINT000"              ,           0x16F0010000508ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60072         {"USBC0_HCINT001"              ,           0x16F0010000528ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60073         {"USBC0_HCINT002"              ,           0x16F0010000548ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60074         {"USBC0_HCINT003"              ,           0x16F0010000568ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60075         {"USBC0_HCINT004"              ,           0x16F0010000588ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60076         {"USBC0_HCINT005"              ,           0x16F00100005A8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60077         {"USBC0_HCINT006"              ,           0x16F00100005C8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60078         {"USBC0_HCINT007"              ,           0x16F00100005E8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60079         {"USBC1_HCINT000"              ,           0x17F0010000508ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60080         {"USBC1_HCINT001"              ,           0x17F0010000528ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60081         {"USBC1_HCINT002"              ,           0x17F0010000548ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60082         {"USBC1_HCINT003"              ,           0x17F0010000568ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60083         {"USBC1_HCINT004"              ,           0x17F0010000588ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60084         {"USBC1_HCINT005"              ,           0x17F00100005A8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60085         {"USBC1_HCINT006"              ,           0x17F00100005C8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60086         {"USBC1_HCINT007"              ,           0x17F00100005E8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     870},
60087         {"USBC0_HCINTMSK000"           ,           0x16F001000050Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60088         {"USBC0_HCINTMSK001"           ,           0x16F001000052Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60089         {"USBC0_HCINTMSK002"           ,           0x16F001000054Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60090         {"USBC0_HCINTMSK003"           ,           0x16F001000056Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60091         {"USBC0_HCINTMSK004"           ,           0x16F001000058Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60092         {"USBC0_HCINTMSK005"           ,           0x16F00100005ACull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60093         {"USBC0_HCINTMSK006"           ,           0x16F00100005CCull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60094         {"USBC0_HCINTMSK007"           ,           0x16F00100005ECull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60095         {"USBC1_HCINTMSK000"           ,           0x17F001000050Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60096         {"USBC1_HCINTMSK001"           ,           0x17F001000052Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60097         {"USBC1_HCINTMSK002"           ,           0x17F001000054Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60098         {"USBC1_HCINTMSK003"           ,           0x17F001000056Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60099         {"USBC1_HCINTMSK004"           ,           0x17F001000058Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60100         {"USBC1_HCINTMSK005"           ,           0x17F00100005ACull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60101         {"USBC1_HCINTMSK006"           ,           0x17F00100005CCull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60102         {"USBC1_HCINTMSK007"           ,           0x17F00100005ECull,  CVMX_CSR_DB_TYPE_NCB,   32,     871},
60103         {"USBC0_HCSPLT000"             ,           0x16F0010000504ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60104         {"USBC0_HCSPLT001"             ,           0x16F0010000524ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60105         {"USBC0_HCSPLT002"             ,           0x16F0010000544ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60106         {"USBC0_HCSPLT003"             ,           0x16F0010000564ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60107         {"USBC0_HCSPLT004"             ,           0x16F0010000584ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60108         {"USBC0_HCSPLT005"             ,           0x16F00100005A4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60109         {"USBC0_HCSPLT006"             ,           0x16F00100005C4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60110         {"USBC0_HCSPLT007"             ,           0x16F00100005E4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60111         {"USBC1_HCSPLT000"             ,           0x17F0010000504ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60112         {"USBC1_HCSPLT001"             ,           0x17F0010000524ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60113         {"USBC1_HCSPLT002"             ,           0x17F0010000544ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60114         {"USBC1_HCSPLT003"             ,           0x17F0010000564ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60115         {"USBC1_HCSPLT004"             ,           0x17F0010000584ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60116         {"USBC1_HCSPLT005"             ,           0x17F00100005A4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60117         {"USBC1_HCSPLT006"             ,           0x17F00100005C4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60118         {"USBC1_HCSPLT007"             ,           0x17F00100005E4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     872},
60119         {"USBC0_HCTSIZ000"             ,           0x16F0010000510ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60120         {"USBC0_HCTSIZ001"             ,           0x16F0010000530ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60121         {"USBC0_HCTSIZ002"             ,           0x16F0010000550ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60122         {"USBC0_HCTSIZ003"             ,           0x16F0010000570ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60123         {"USBC0_HCTSIZ004"             ,           0x16F0010000590ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60124         {"USBC0_HCTSIZ005"             ,           0x16F00100005B0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60125         {"USBC0_HCTSIZ006"             ,           0x16F00100005D0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60126         {"USBC0_HCTSIZ007"             ,           0x16F00100005F0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60127         {"USBC1_HCTSIZ000"             ,           0x17F0010000510ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60128         {"USBC1_HCTSIZ001"             ,           0x17F0010000530ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60129         {"USBC1_HCTSIZ002"             ,           0x17F0010000550ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60130         {"USBC1_HCTSIZ003"             ,           0x17F0010000570ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60131         {"USBC1_HCTSIZ004"             ,           0x17F0010000590ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60132         {"USBC1_HCTSIZ005"             ,           0x17F00100005B0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60133         {"USBC1_HCTSIZ006"             ,           0x17F00100005D0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60134         {"USBC1_HCTSIZ007"             ,           0x17F00100005F0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     873},
60135         {"USBC0_HFIR"                  ,           0x16F0010000404ull,  CVMX_CSR_DB_TYPE_NCB,   32,     874},
60136         {"USBC1_HFIR"                  ,           0x17F0010000404ull,  CVMX_CSR_DB_TYPE_NCB,   32,     874},
60137         {"USBC0_HFNUM"                 ,           0x16F0010000408ull,  CVMX_CSR_DB_TYPE_NCB,   32,     875},
60138         {"USBC1_HFNUM"                 ,           0x17F0010000408ull,  CVMX_CSR_DB_TYPE_NCB,   32,     875},
60139         {"USBC0_HPRT"                  ,           0x16F0010000440ull,  CVMX_CSR_DB_TYPE_NCB,   32,     876},
60140         {"USBC1_HPRT"                  ,           0x17F0010000440ull,  CVMX_CSR_DB_TYPE_NCB,   32,     876},
60141         {"USBC0_HPTXFSIZ"              ,           0x16F0010000100ull,  CVMX_CSR_DB_TYPE_NCB,   32,     877},
60142         {"USBC1_HPTXFSIZ"              ,           0x17F0010000100ull,  CVMX_CSR_DB_TYPE_NCB,   32,     877},
60143         {"USBC0_HPTXSTS"               ,           0x16F0010000410ull,  CVMX_CSR_DB_TYPE_NCB,   32,     878},
60144         {"USBC1_HPTXSTS"               ,           0x17F0010000410ull,  CVMX_CSR_DB_TYPE_NCB,   32,     878},
60145         {"USBC0_NPTXDFIFO000"          ,           0x16F0010001000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60146         {"USBC0_NPTXDFIFO001"          ,           0x16F0010002000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60147         {"USBC0_NPTXDFIFO002"          ,           0x16F0010003000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60148         {"USBC0_NPTXDFIFO003"          ,           0x16F0010004000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60149         {"USBC0_NPTXDFIFO004"          ,           0x16F0010005000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60150         {"USBC0_NPTXDFIFO005"          ,           0x16F0010006000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60151         {"USBC0_NPTXDFIFO006"          ,           0x16F0010007000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60152         {"USBC0_NPTXDFIFO007"          ,           0x16F0010008000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60153         {"USBC1_NPTXDFIFO000"          ,           0x17F0010001000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60154         {"USBC1_NPTXDFIFO001"          ,           0x17F0010002000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60155         {"USBC1_NPTXDFIFO002"          ,           0x17F0010003000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60156         {"USBC1_NPTXDFIFO003"          ,           0x17F0010004000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60157         {"USBC1_NPTXDFIFO004"          ,           0x17F0010005000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60158         {"USBC1_NPTXDFIFO005"          ,           0x17F0010006000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60159         {"USBC1_NPTXDFIFO006"          ,           0x17F0010007000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60160         {"USBC1_NPTXDFIFO007"          ,           0x17F0010008000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     879},
60161         {"USBC0_PCGCCTL"               ,           0x16F0010000E00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     880},
60162         {"USBC1_PCGCCTL"               ,           0x17F0010000E00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     880},
60163         {"USBN0_BIST_STATUS"           ,           0x11800680007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     881},
60164         {"USBN1_BIST_STATUS"           ,           0x11800780007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     881},
60165         {"USBN0_CLK_CTL"               ,           0x1180068000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     882},
60166         {"USBN1_CLK_CTL"               ,           0x1180078000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     882},
60167         {"USBN0_CTL_STATUS"            ,           0x16F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     883},
60168         {"USBN1_CTL_STATUS"            ,           0x17F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     883},
60169         {"USBN0_DMA0_INB_CHN0"         ,           0x16F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     884},
60170         {"USBN1_DMA0_INB_CHN0"         ,           0x17F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     884},
60171         {"USBN0_DMA0_INB_CHN1"         ,           0x16F0000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     885},
60172         {"USBN1_DMA0_INB_CHN1"         ,           0x17F0000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     885},
60173         {"USBN0_DMA0_INB_CHN2"         ,           0x16F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     886},
60174         {"USBN1_DMA0_INB_CHN2"         ,           0x17F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     886},
60175         {"USBN0_DMA0_INB_CHN3"         ,           0x16F0000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     887},
60176         {"USBN1_DMA0_INB_CHN3"         ,           0x17F0000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     887},
60177         {"USBN0_DMA0_INB_CHN4"         ,           0x16F0000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     888},
60178         {"USBN1_DMA0_INB_CHN4"         ,           0x17F0000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     888},
60179         {"USBN0_DMA0_INB_CHN5"         ,           0x16F0000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     889},
60180         {"USBN1_DMA0_INB_CHN5"         ,           0x17F0000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     889},
60181         {"USBN0_DMA0_INB_CHN6"         ,           0x16F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     890},
60182         {"USBN1_DMA0_INB_CHN6"         ,           0x17F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     890},
60183         {"USBN0_DMA0_INB_CHN7"         ,           0x16F0000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     891},
60184         {"USBN1_DMA0_INB_CHN7"         ,           0x17F0000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     891},
60185         {"USBN0_DMA0_OUTB_CHN0"        ,           0x16F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     892},
60186         {"USBN1_DMA0_OUTB_CHN0"        ,           0x17F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     892},
60187         {"USBN0_DMA0_OUTB_CHN1"        ,           0x16F0000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     893},
60188         {"USBN1_DMA0_OUTB_CHN1"        ,           0x17F0000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     893},
60189         {"USBN0_DMA0_OUTB_CHN2"        ,           0x16F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     894},
60190         {"USBN1_DMA0_OUTB_CHN2"        ,           0x17F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     894},
60191         {"USBN0_DMA0_OUTB_CHN3"        ,           0x16F0000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     895},
60192         {"USBN1_DMA0_OUTB_CHN3"        ,           0x17F0000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     895},
60193         {"USBN0_DMA0_OUTB_CHN4"        ,           0x16F0000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     896},
60194         {"USBN1_DMA0_OUTB_CHN4"        ,           0x17F0000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     896},
60195         {"USBN0_DMA0_OUTB_CHN5"        ,           0x16F0000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     897},
60196         {"USBN1_DMA0_OUTB_CHN5"        ,           0x17F0000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     897},
60197         {"USBN0_DMA0_OUTB_CHN6"        ,           0x16F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     898},
60198         {"USBN1_DMA0_OUTB_CHN6"        ,           0x17F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     898},
60199         {"USBN0_DMA0_OUTB_CHN7"        ,           0x16F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     899},
60200         {"USBN1_DMA0_OUTB_CHN7"        ,           0x17F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     899},
60201         {"USBN0_DMA_TEST"              ,           0x16F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     900},
60202         {"USBN1_DMA_TEST"              ,           0x17F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     900},
60203         {"USBN0_INT_ENB"               ,           0x1180068000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     901},
60204         {"USBN1_INT_ENB"               ,           0x1180078000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     901},
60205         {"USBN0_INT_SUM"               ,           0x1180068000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     902},
60206         {"USBN1_INT_SUM"               ,           0x1180078000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     902},
60207         {"USBN0_USBP_CTL_STATUS"       ,           0x1180068000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     903},
60208         {"USBN1_USBP_CTL_STATUS"       ,           0x1180078000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     903},
60209         {NULL,0,0,0,0}
60210 };
60211 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xxp1[] = {
60212         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
60213         {"RESERVED_0_1"                ,        0,      2,      0,      "RAZ",  0,      0,      0ull,   0ull},
60214         {"OUT_OVR"                     ,        2,      2,      0,      "R/W1C",        0,      0,      0ull,   0ull},
60215         {"RESERVED_4_21"               ,        4,      18,     0,      "RAZ",  0,      0,      0ull,   0ull},
60216         {"LOSTSTAT"                    ,        22,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
60217         {"RESERVED_23_25"              ,        23,     3,      0,      "RAZ",  1,      1,      0,      0},
60218         {"STATOVR"                     ,        26,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
60219         {"RESERVED_27_31"              ,        27,     5,      0,      "RAZ",  1,      1,      0,      0},
60220         {"OVRFLW"                      ,        32,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
60221         {"TXPOP"                       ,        33,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
60222         {"TXPSH"                       ,        34,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
60223         {"OVRFLW1"                     ,        35,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
60224         {"TXPOP1"                      ,        36,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
60225         {"TXPSH1"                      ,        37,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
60226         {"RESERVED_38_63"              ,        38,     26,     0,      "RAZ",  1,      1,      0,      0},
60227         {"STATUS"                      ,        0,      10,     1,      "RO",   0,      0,      0ull,   0ull},
60228         {"RESERVED_10_63"              ,        10,     54,     1,      "RAZ",  1,      1,      0,      0},
60229         {"NCTL"                        ,        0,      5,      2,      "R/W",  0,      1,      16ull,  0},
60230         {"RESERVED_5_7"                ,        5,      3,      2,      "RAZ",  1,      1,      0,      0},
60231         {"PCTL"                        ,        8,      5,      2,      "R/W",  0,      1,      16ull,  0},
60232         {"RESERVED_13_15"              ,        13,     3,      2,      "RAZ",  1,      1,      0,      0},
60233         {"BYP_EN"                      ,        16,     1,      2,      "R/W",  0,      0,      0ull,   0ull},
60234         {"RESERVED_17_31"              ,        17,     15,     2,      "RAZ",  1,      1,      0,      0},
60235         {"NCTL1"                       ,        32,     5,      2,      "R/W",  0,      1,      16ull,  0},
60236         {"RESERVED_37_39"              ,        37,     3,      2,      "RAZ",  1,      1,      0,      0},
60237         {"PCTL1"                       ,        40,     5,      2,      "R/W",  0,      1,      16ull,  0},
60238         {"RESERVED_45_47"              ,        45,     3,      2,      "RAZ",  1,      1,      0,      0},
60239         {"BYP_EN1"                     ,        48,     1,      2,      "R/W",  0,      0,      0ull,   0ull},
60240         {"RESERVED_49_63"              ,        49,     15,     2,      "RAZ",  1,      1,      0,      0},
60241         {"RESERVED_0_0"                ,        0,      1,      3,      "RAZ",  1,      1,      0,      0},
60242         {"EN"                          ,        1,      1,      3,      "R/W",  0,      0,      0ull,   1ull},
60243         {"RESERVED_2_63"               ,        2,      62,     3,      "RAZ",  1,      1,      0,      0},
60244         {"EN"                          ,        0,      1,      4,      "R/W",  0,      1,      0ull,   0},
60245         {"SPEED"                       ,        1,      1,      4,      "RO",   0,      0,      0ull,   0ull},
60246         {"DUPLEX"                      ,        2,      1,      4,      "R/W",  0,      1,      1ull,   0},
60247         {"SLOTTIME"                    ,        3,      1,      4,      "RO",   0,      0,      0ull,   0ull},
60248         {"RX_EN"                       ,        4,      1,      4,      "R/W",  0,      1,      0ull,   0},
60249         {"TX_EN"                       ,        5,      1,      4,      "R/W",  0,      1,      0ull,   0},
60250         {"RESERVED_6_63"               ,        6,      58,     4,      "RAZ",  1,      1,      0,      0},
60251         {"ADR"                         ,        0,      64,     5,      "R/W",  0,      1,      0ull,   0},
60252         {"ADR"                         ,        0,      64,     6,      "R/W",  0,      1,      0ull,   0},
60253         {"ADR"                         ,        0,      64,     7,      "R/W",  0,      1,      0ull,   0},
60254         {"ADR"                         ,        0,      64,     8,      "R/W",  0,      1,      0ull,   0},
60255         {"ADR"                         ,        0,      64,     9,      "R/W",  0,      1,      0ull,   0},
60256         {"ADR"                         ,        0,      64,     10,     "R/W",  0,      1,      0ull,   0},
60257         {"EN"                          ,        0,      8,      11,     "R/W",  0,      1,      0ull,   0},
60258         {"RESERVED_8_63"               ,        8,      56,     11,     "RAZ",  1,      1,      0,      0},
60259         {"BCST"                        ,        0,      1,      12,     "R/W",  0,      1,      1ull,   0},
60260         {"MCST"                        ,        1,      2,      12,     "R/W",  0,      1,      0ull,   0},
60261         {"CAM_MODE"                    ,        3,      1,      12,     "R/W",  0,      1,      0ull,   0},
60262         {"RESERVED_4_63"               ,        4,      60,     12,     "RAZ",  1,      1,      0,      0},
60263         {"CNT"                         ,        0,      5,      13,     "R/W",  0,      0,      24ull,  24ull},
60264         {"RESERVED_5_63"               ,        5,      59,     13,     "RAZ",  1,      1,      0,      0},
60265         {"MINERR"                      ,        0,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
60266         {"RESERVED_1_1"                ,        1,      1,      14,     "RAZ",  0,      0,      0ull,   0ull},
60267         {"MAXERR"                      ,        2,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
60268         {"JABBER"                      ,        3,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
60269         {"FCSERR"                      ,        4,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
60270         {"ALNERR"                      ,        5,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
60271         {"LENERR"                      ,        6,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
60272         {"RCVERR"                      ,        7,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
60273         {"SKPERR"                      ,        8,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
60274         {"RESERVED_9_63"               ,        9,      55,     14,     "RAZ",  1,      1,      0,      0},
60275         {"PRE_CHK"                     ,        0,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
60276         {"PRE_STRP"                    ,        1,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
60277         {"CTL_DRP"                     ,        2,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
60278         {"CTL_BCK"                     ,        3,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
60279         {"CTL_MCST"                    ,        4,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
60280         {"CTL_SMAC"                    ,        5,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
60281         {"PRE_FREE"                    ,        6,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
60282         {"VLAN_LEN"                    ,        7,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
60283         {"PAD_LEN"                     ,        8,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
60284         {"PRE_ALIGN"                   ,        9,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
60285         {"RESERVED_10_63"              ,        10,     54,     15,     "RAZ",  1,      1,      0,      0},
60286         {"LEN"                         ,        0,      16,     16,     "R/W",  0,      0,      1536ull,        1536ull},
60287         {"RESERVED_16_63"              ,        16,     48,     16,     "RAZ",  1,      1,      0,      0},
60288         {"LEN"                         ,        0,      16,     17,     "R/W",  0,      0,      64ull,  64ull},
60289         {"RESERVED_16_63"              ,        16,     48,     17,     "RAZ",  1,      1,      0,      0},
60290         {"IFG"                         ,        0,      4,      18,     "R/W",  0,      0,      12ull,  12ull},
60291         {"RESERVED_4_63"               ,        4,      60,     18,     "RAZ",  1,      1,      0,      0},
60292         {"MINERR"                      ,        0,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
60293         {"RESERVED_1_1"                ,        1,      1,      19,     "RAZ",  1,      1,      0,      0},
60294         {"MAXERR"                      ,        2,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
60295         {"JABBER"                      ,        3,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
60296         {"FCSERR"                      ,        4,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
60297         {"ALNERR"                      ,        5,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
60298         {"LENERR"                      ,        6,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
60299         {"RCVERR"                      ,        7,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
60300         {"SKPERR"                      ,        8,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
60301         {"RESERVED_9_9"                ,        9,      1,      19,     "RAZ",  1,      1,      0,      0},
60302         {"OVRERR"                      ,        10,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
60303         {"PCTERR"                      ,        11,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
60304         {"RSVERR"                      ,        12,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
60305         {"FALERR"                      ,        13,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
60306         {"COLDET"                      ,        14,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
60307         {"IFGERR"                      ,        15,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
60308         {"RESERVED_16_18"              ,        16,     3,      19,     "RAZ",  1,      1,      0,      0},
60309         {"PAUSE_DRP"                   ,        19,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
60310         {"RESERVED_20_63"              ,        20,     44,     19,     "RAZ",  1,      1,      0,      0},
60311         {"MINERR"                      ,        0,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60312         {"RESERVED_1_1"                ,        1,      1,      20,     "RAZ",  0,      0,      0ull,   0ull},
60313         {"MAXERR"                      ,        2,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60314         {"JABBER"                      ,        3,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60315         {"FCSERR"                      ,        4,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60316         {"ALNERR"                      ,        5,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60317         {"LENERR"                      ,        6,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60318         {"RCVERR"                      ,        7,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60319         {"SKPERR"                      ,        8,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60320         {"RESERVED_9_9"                ,        9,      1,      20,     "RAZ",  0,      0,      0ull,   0ull},
60321         {"OVRERR"                      ,        10,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60322         {"PCTERR"                      ,        11,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60323         {"RSVERR"                      ,        12,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60324         {"FALERR"                      ,        13,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60325         {"COLDET"                      ,        14,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60326         {"IFGERR"                      ,        15,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60327         {"RESERVED_16_18"              ,        16,     3,      20,     "RAZ",  0,      0,      0ull,   0ull},
60328         {"PAUSE_DRP"                   ,        19,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
60329         {"RESERVED_20_63"              ,        20,     44,     20,     "RAZ",  1,      1,      0,      0},
60330         {"CNT"                         ,        0,      16,     21,     "R/W",  0,      0,      10240ull,       10240ull},
60331         {"RESERVED_16_63"              ,        16,     48,     21,     "RAZ",  1,      1,      0,      0},
60332         {"STATUS"                      ,        0,      16,     22,     "R/W1C",        0,      1,      0ull,   0},
60333         {"RESERVED_16_63"              ,        16,     48,     22,     "RAZ",  1,      1,      0,      0},
60334         {"RD_CLR"                      ,        0,      1,      23,     "R/W",  0,      0,      0ull,   0ull},
60335         {"RESERVED_1_63"               ,        1,      63,     23,     "RAZ",  1,      1,      0,      0},
60336         {"CNT"                         ,        0,      48,     24,     "RC/W", 0,      1,      0ull,   0},
60337         {"RESERVED_48_63"              ,        48,     16,     24,     "RAZ",  1,      1,      0,      0},
60338         {"CNT"                         ,        0,      48,     25,     "RC/W", 0,      1,      0ull,   0},
60339         {"RESERVED_48_63"              ,        48,     16,     25,     "RAZ",  1,      1,      0,      0},
60340         {"CNT"                         ,        0,      48,     26,     "RC/W", 0,      1,      0ull,   0},
60341         {"RESERVED_48_63"              ,        48,     16,     26,     "RAZ",  1,      1,      0,      0},
60342         {"CNT"                         ,        0,      48,     27,     "RC/W", 0,      1,      0ull,   0},
60343         {"RESERVED_48_63"              ,        48,     16,     27,     "RAZ",  1,      1,      0,      0},
60344         {"CNT"                         ,        0,      32,     28,     "RC/W", 0,      1,      0ull,   0},
60345         {"RESERVED_32_63"              ,        32,     32,     28,     "RAZ",  1,      1,      0,      0},
60346         {"CNT"                         ,        0,      32,     29,     "RC/W", 0,      1,      0ull,   0},
60347         {"RESERVED_32_63"              ,        32,     32,     29,     "RAZ",  1,      1,      0,      0},
60348         {"CNT"                         ,        0,      32,     30,     "RC/W", 0,      1,      0ull,   0},
60349         {"RESERVED_32_63"              ,        32,     32,     30,     "RAZ",  1,      1,      0,      0},
60350         {"CNT"                         ,        0,      32,     31,     "RC/W", 0,      1,      0ull,   0},
60351         {"RESERVED_32_63"              ,        32,     32,     31,     "RAZ",  1,      1,      0,      0},
60352         {"CNT"                         ,        0,      32,     32,     "RC/W", 0,      1,      0ull,   0},
60353         {"RESERVED_32_63"              ,        32,     32,     32,     "RAZ",  1,      1,      0,      0},
60354         {"LEN"                         ,        0,      7,      33,     "R/W",  0,      0,      0ull,   0ull},
60355         {"RESERVED_7_7"                ,        7,      1,      33,     "RAZ",  1,      1,      0,      0},
60356         {"FCSSEL"                      ,        8,      1,      33,     "R/W",  0,      0,      0ull,   0ull},
60357         {"RESERVED_9_63"               ,        9,      55,     33,     "RAZ",  1,      1,      0,      0},
60358         {"MARK"                        ,        0,      6,      34,     "R/W",  0,      0,      2ull,   2ull},
60359         {"RESERVED_6_63"               ,        6,      58,     34,     "RAZ",  1,      1,      0,      0},
60360         {"MARK"                        ,        0,      6,      35,     "R/W",  0,      0,      16ull,  16ull},
60361         {"RESERVED_6_63"               ,        6,      58,     35,     "RAZ",  1,      1,      0,      0},
60362         {"MARK"                        ,        0,      9,      36,     "R/W",  0,      0,      32ull,  32ull},
60363         {"RESERVED_9_63"               ,        9,      55,     36,     "RAZ",  1,      1,      0,      0},
60364         {"COMMIT"                      ,        0,      2,      37,     "RO",   0,      0,      0ull,   0ull},
60365         {"RESERVED_2_15"               ,        2,      14,     37,     "RAZ",  1,      1,      0,      0},
60366         {"DROP"                        ,        16,     2,      37,     "RO",   0,      0,      0ull,   0ull},
60367         {"RESERVED_18_63"              ,        18,     46,     37,     "RAZ",  1,      1,      0,      0},
60368         {"RX"                          ,        0,      2,      38,     "RC",   0,      0,      0ull,   0ull},
60369         {"RESERVED_2_3"                ,        2,      2,      38,     "RAZ",  1,      1,      0,      0},
60370         {"TX"                          ,        4,      2,      38,     "RC",   0,      0,      0ull,   0ull},
60371         {"RESERVED_6_63"               ,        6,      58,     38,     "RAZ",  1,      1,      0,      0},
60372         {"SMAC"                        ,        0,      48,     39,     "R/W",  0,      1,      0ull,   0},
60373         {"RESERVED_48_63"              ,        48,     16,     39,     "RAZ",  1,      1,      0,      0},
60374         {"CNT"                         ,        0,      16,     40,     "R/W1C",        0,      0,      0ull,   0ull},
60375         {"BP"                          ,        16,     1,      40,     "RO",   0,      0,      0ull,   0ull},
60376         {"RESERVED_17_63"              ,        17,     47,     40,     "RAZ",  1,      1,      0,      0},
60377         {"PREAMBLE"                    ,        0,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
60378         {"PAD"                         ,        1,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
60379         {"FCS"                         ,        2,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
60380         {"FORCE_FCS"                   ,        3,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
60381         {"RESERVED_4_63"               ,        4,      60,     41,     "RAZ",  1,      1,      0,      0},
60382         {"XSCOL_EN"                    ,        0,      1,      42,     "R/W",  0,      0,      1ull,   1ull},
60383         {"XSDEF_EN"                    ,        1,      1,      42,     "R/W",  0,      0,      1ull,   1ull},
60384         {"RESERVED_2_63"               ,        2,      62,     42,     "RAZ",  1,      1,      0,      0},
60385         {"MIN_SIZE"                    ,        0,      8,      43,     "R/W",  0,      0,      59ull,  59ull},
60386         {"RESERVED_8_63"               ,        8,      56,     43,     "RAZ",  1,      1,      0,      0},
60387         {"INTERVAL"                    ,        0,      16,     44,     "R/W",  0,      1,      16ull,  0},
60388         {"RESERVED_16_63"              ,        16,     48,     44,     "RAZ",  1,      1,      0,      0},
60389         {"TIME"                        ,        0,      16,     45,     "R/W",  0,      1,      96ull,  0},
60390         {"RESERVED_16_63"              ,        16,     48,     45,     "RAZ",  1,      1,      0,      0},
60391         {"TIME"                        ,        0,      16,     46,     "RO",   1,      1,      0,      0},
60392         {"RESERVED_16_63"              ,        16,     48,     46,     "RAZ",  1,      1,      0,      0},
60393         {"SEND"                        ,        0,      1,      47,     "R/W",  0,      0,      1ull,   1ull},
60394         {"RESERVED_1_63"               ,        1,      63,     47,     "RAZ",  1,      1,      0,      0},
60395         {"TIME"                        ,        0,      16,     48,     "R/W",  0,      1,      0ull,   0},
60396         {"RESERVED_16_63"              ,        16,     48,     48,     "RAZ",  1,      1,      0,      0},
60397         {"XSCOL"                       ,        0,      32,     49,     "RC/W", 0,      1,      0ull,   0},
60398         {"XSDEF"                       ,        32,     32,     49,     "RC/W", 0,      1,      0ull,   0},
60399         {"MCOL"                        ,        0,      32,     50,     "RC/W", 0,      1,      0ull,   0},
60400         {"SCOL"                        ,        32,     32,     50,     "RC/W", 0,      1,      0ull,   0},
60401         {"OCTS"                        ,        0,      48,     51,     "RC/W", 0,      1,      0ull,   0},
60402         {"RESERVED_48_63"              ,        48,     16,     51,     "RAZ",  1,      1,      0,      0},
60403         {"PKTS"                        ,        0,      32,     52,     "RC/W", 0,      1,      0ull,   0},
60404         {"RESERVED_32_63"              ,        32,     32,     52,     "RAZ",  1,      1,      0,      0},
60405         {"HIST0"                       ,        0,      32,     53,     "RC/W", 0,      1,      0ull,   0},
60406         {"HIST1"                       ,        32,     32,     53,     "RC/W", 0,      1,      0ull,   0},
60407         {"HIST2"                       ,        0,      32,     54,     "RC/W", 0,      1,      0ull,   0},
60408         {"HIST3"                       ,        32,     32,     54,     "RC/W", 0,      1,      0ull,   0},
60409         {"HIST4"                       ,        0,      32,     55,     "RC/W", 0,      1,      0ull,   0},
60410         {"HIST5"                       ,        32,     32,     55,     "RC/W", 0,      1,      0ull,   0},
60411         {"HIST6"                       ,        0,      32,     56,     "RC/W", 0,      1,      0ull,   0},
60412         {"HIST7"                       ,        32,     32,     56,     "RC/W", 0,      1,      0ull,   0},
60413         {"BCST"                        ,        0,      32,     57,     "RC/W", 0,      1,      0ull,   0},
60414         {"MCST"                        ,        32,     32,     57,     "RC/W", 0,      1,      0ull,   0},
60415         {"CTL"                         ,        0,      32,     58,     "RC/W", 0,      1,      0ull,   0},
60416         {"UNDFLW"                      ,        32,     32,     58,     "RC/W", 0,      1,      0ull,   0},
60417         {"RD_CLR"                      ,        0,      1,      59,     "R/W",  0,      0,      0ull,   0ull},
60418         {"RESERVED_1_63"               ,        1,      63,     59,     "RAZ",  1,      1,      0,      0},
60419         {"CNT"                         ,        0,      6,      60,     "R/W",  0,      0,      16ull,  16ull},
60420         {"RESERVED_6_63"               ,        6,      58,     60,     "RAZ",  1,      1,      0,      0},
60421         {"BP"                          ,        0,      2,      61,     "RO",   0,      0,      0ull,   0ull},
60422         {"RESERVED_2_63"               ,        2,      62,     61,     "RAZ",  1,      1,      0,      0},
60423         {"LIMIT"                       ,        0,      5,      62,     "R/W",  0,      0,      16ull,  16ull},
60424         {"RESERVED_5_63"               ,        5,      59,     62,     "RAZ",  1,      1,      0,      0},
60425         {"IFG1"                        ,        0,      4,      63,     "R/W",  0,      1,      8ull,   0},
60426         {"IFG2"                        ,        4,      4,      63,     "R/W",  0,      1,      4ull,   0},
60427         {"RESERVED_8_63"               ,        8,      56,     63,     "RAZ",  1,      1,      0,      0},
60428         {"PKO_NXA"                     ,        0,      1,      64,     "R/W",  0,      0,      0ull,   0ull},
60429         {"RESERVED_1_1"                ,        1,      1,      64,     "RAZ",  1,      1,      0,      0},
60430         {"UNDFLW"                      ,        2,      2,      64,     "R/W",  0,      0,      0ull,   0ull},
60431         {"RESERVED_4_7"                ,        4,      4,      64,     "RAZ",  1,      1,      0,      0},
60432         {"XSCOL"                       ,        8,      2,      64,     "R/W",  0,      0,      0ull,   0ull},
60433         {"RESERVED_10_11"              ,        10,     2,      64,     "RAZ",  1,      1,      0,      0},
60434         {"XSDEF"                       ,        12,     2,      64,     "R/W",  0,      0,      0ull,   0ull},
60435         {"RESERVED_14_15"              ,        14,     2,      64,     "RAZ",  1,      1,      0,      0},
60436         {"LATE_COL"                    ,        16,     2,      64,     "R/W",  0,      0,      0ull,   0ull},
60437         {"RESERVED_18_63"              ,        18,     46,     64,     "RAZ",  1,      1,      0,      0},
60438         {"PKO_NXA"                     ,        0,      1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
60439         {"RESERVED_1_1"                ,        1,      1,      65,     "RAZ",  1,      1,      0,      0},
60440         {"UNDFLW"                      ,        2,      2,      65,     "R/W1C",        0,      0,      0ull,   0ull},
60441         {"RESERVED_4_7"                ,        4,      4,      65,     "RAZ",  1,      1,      0,      0},
60442         {"XSCOL"                       ,        8,      2,      65,     "R/W1C",        0,      0,      0ull,   0ull},
60443         {"RESERVED_10_11"              ,        10,     2,      65,     "RAZ",  1,      1,      0,      0},
60444         {"XSDEF"                       ,        12,     2,      65,     "R/W1C",        0,      0,      0ull,   0ull},
60445         {"RESERVED_14_15"              ,        14,     2,      65,     "RAZ",  1,      1,      0,      0},
60446         {"LATE_COL"                    ,        16,     2,      65,     "R/W1C",        0,      0,      0ull,   0ull},
60447         {"RESERVED_18_63"              ,        18,     46,     65,     "RAZ",  1,      1,      0,      0},
60448         {"JAM"                         ,        0,      8,      66,     "R/W",  0,      1,      238ull, 0},
60449         {"RESERVED_8_63"               ,        8,      56,     66,     "RAZ",  1,      1,      0,      0},
60450         {"LFSR"                        ,        0,      16,     67,     "R/W",  0,      1,      65535ull,       0},
60451         {"RESERVED_16_63"              ,        16,     48,     67,     "RAZ",  1,      1,      0,      0},
60452         {"IGN_FULL"                    ,        0,      2,      68,     "R/W",  0,      0,      0ull,   0ull},
60453         {"RESERVED_2_3"                ,        2,      2,      68,     "RAZ",  1,      1,      0,      0},
60454         {"BP"                          ,        4,      2,      68,     "R/W",  0,      0,      0ull,   0ull},
60455         {"RESERVED_6_7"                ,        6,      2,      68,     "RAZ",  1,      1,      0,      0},
60456         {"EN"                          ,        8,      2,      68,     "R/W",  0,      0,      0ull,   0ull},
60457         {"RESERVED_10_63"              ,        10,     54,     68,     "RAZ",  1,      1,      0,      0},
60458         {"DMAC"                        ,        0,      48,     69,     "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
60459         {"RESERVED_48_63"              ,        48,     16,     69,     "RAZ",  1,      1,      0,      0},
60460         {"TYPE"                        ,        0,      16,     70,     "R/W",  0,      0,      34824ull,       34824ull},
60461         {"RESERVED_16_63"              ,        16,     48,     70,     "RAZ",  1,      1,      0,      0},
60462         {"BIST"                        ,        0,      3,      71,     "RO",   0,      0,      0ull,   0ull},
60463         {"RESERVED_3_63"               ,        3,      61,     71,     "RAZ",  1,      1,      0,      0},
60464         {"DINT"                        ,        0,      4,      72,     "WO",   0,      0,      0ull,   0ull},
60465         {"RESERVED_4_63"               ,        4,      60,     72,     "RAZ",  1,      1,      0,      0},
60466         {"FUSE"                        ,        0,      4,      73,     "RO",   1,      1,      0,      0},
60467         {"RESERVED_4_63"               ,        4,      60,     73,     "RAZ",  1,      1,      0,      0},
60468         {"GSTOP"                       ,        0,      1,      74,     "R/W",  0,      0,      0ull,   0ull},
60469         {"RESERVED_1_63"               ,        1,      63,     74,     "RAZ",  1,      1,      0,      0},
60470         {"WORKQ"                       ,        0,      16,     75,     "R/W",  0,      0,      0ull,   0ull},
60471         {"GPIO"                        ,        16,     16,     75,     "R/W",  0,      0,      0ull,   0ull},
60472         {"MBOX"                        ,        32,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
60473         {"UART"                        ,        34,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
60474         {"PCI_INT"                     ,        36,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
60475         {"PCI_MSI"                     ,        40,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
60476         {"RESERVED_44_44"              ,        44,     1,      75,     "RAZ",  1,      1,      0,      0},
60477         {"TWSI"                        ,        45,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60478         {"RML"                         ,        46,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60479         {"TRACE"                       ,        47,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60480         {"GMX_DRP"                     ,        48,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60481         {"RESERVED_49_49"              ,        49,     1,      75,     "RAZ",  0,      0,      0ull,   0ull},
60482         {"IPD_DRP"                     ,        50,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60483         {"RESERVED_51_51"              ,        51,     1,      75,     "RAZ",  0,      0,      0ull,   0ull},
60484         {"TIMER"                       ,        52,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
60485         {"USB"                         ,        56,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60486         {"RESERVED_57_58"              ,        57,     2,      75,     "RAZ",  0,      0,      0ull,   0ull},
60487         {"TWSI2"                       ,        59,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60488         {"POWIQ"                       ,        60,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60489         {"IPDPPTHR"                    ,        61,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60490         {"MII"                         ,        62,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60491         {"BOOTDMA"                     ,        63,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
60492         {"WDOG"                        ,        0,      4,      76,     "R/W",  0,      0,      0ull,   0ull},
60493         {"RESERVED_4_15"               ,        4,      12,     76,     "RAZ",  1,      1,      0,      0},
60494         {"UART2"                       ,        16,     1,      76,     "R/W",  0,      0,      0ull,   0ull},
60495         {"USB1"                        ,        17,     1,      76,     "R/W",  0,      0,      0ull,   0ull},
60496         {"MII1"                        ,        18,     1,      76,     "R/W",  0,      0,      0ull,   0ull},
60497         {"RESERVED_19_63"              ,        19,     45,     76,     "RAZ",  1,      1,      0,      0},
60498         {"WORKQ"                       ,        0,      16,     77,     "R/W",  0,      0,      0ull,   0ull},
60499         {"GPIO"                        ,        16,     16,     77,     "R/W",  0,      0,      0ull,   0ull},
60500         {"MBOX"                        ,        32,     2,      77,     "R/W",  0,      0,      0ull,   0ull},
60501         {"UART"                        ,        34,     2,      77,     "R/W",  0,      0,      0ull,   0ull},
60502         {"PCI_INT"                     ,        36,     4,      77,     "R/W",  0,      0,      0ull,   0ull},
60503         {"PCI_MSI"                     ,        40,     4,      77,     "R/W",  0,      0,      0ull,   0ull},
60504         {"RESERVED_44_44"              ,        44,     1,      77,     "RAZ",  1,      1,      0,      0},
60505         {"TWSI"                        ,        45,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60506         {"RML"                         ,        46,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60507         {"TRACE"                       ,        47,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60508         {"GMX_DRP"                     ,        48,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60509         {"RESERVED_49_49"              ,        49,     1,      77,     "RAZ",  0,      0,      0ull,   0ull},
60510         {"IPD_DRP"                     ,        50,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60511         {"RESERVED_51_51"              ,        51,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60512         {"TIMER"                       ,        52,     4,      77,     "R/W",  0,      0,      0ull,   0ull},
60513         {"USB"                         ,        56,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60514         {"RESERVED_57_58"              ,        57,     2,      77,     "R/W",  0,      0,      0ull,   0ull},
60515         {"TWSI2"                       ,        59,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60516         {"POWIQ"                       ,        60,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60517         {"IPDPPTHR"                    ,        61,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60518         {"MII"                         ,        62,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60519         {"BOOTDMA"                     ,        63,     1,      77,     "R/W",  0,      0,      0ull,   0ull},
60520         {"WDOG"                        ,        0,      4,      78,     "R/W",  0,      0,      0ull,   0ull},
60521         {"RESERVED_4_15"               ,        4,      12,     78,     "RAZ",  1,      1,      0,      0},
60522         {"UART2"                       ,        16,     1,      78,     "R/W",  0,      0,      0ull,   0ull},
60523         {"USB1"                        ,        17,     1,      78,     "R/W",  0,      0,      0ull,   0ull},
60524         {"MII1"                        ,        18,     1,      78,     "R/W",  0,      0,      0ull,   0ull},
60525         {"RESERVED_19_63"              ,        19,     45,     78,     "RAZ",  1,      1,      0,      0},
60526         {"WORKQ"                       ,        0,      16,     79,     "RO",   0,      0,      0ull,   0ull},
60527         {"GPIO"                        ,        16,     16,     79,     "RO",   0,      0,      0ull,   0ull},
60528         {"MBOX"                        ,        32,     2,      79,     "RO",   0,      0,      0ull,   0ull},
60529         {"UART"                        ,        34,     2,      79,     "RO",   0,      0,      0ull,   0ull},
60530         {"PCI_INT"                     ,        36,     4,      79,     "RO",   0,      0,      0ull,   0ull},
60531         {"PCI_MSI"                     ,        40,     4,      79,     "RO",   0,      0,      0ull,   0ull},
60532         {"WDOG_SUM"                    ,        44,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60533         {"TWSI"                        ,        45,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60534         {"RML"                         ,        46,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60535         {"TRACE"                       ,        47,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60536         {"GMX_DRP"                     ,        48,     1,      79,     "R/W1C",        0,      0,      0ull,   0ull},
60537         {"RESERVED_49_49"              ,        49,     1,      79,     "RAZ",  1,      1,      0,      0},
60538         {"IPD_DRP"                     ,        50,     1,      79,     "R/W1C",        0,      0,      0ull,   0ull},
60539         {"RESERVED_51_51"              ,        51,     1,      79,     "RAZ",  0,      0,      0ull,   0ull},
60540         {"TIMER"                       ,        52,     4,      79,     "R/W1C",        0,      0,      0ull,   0ull},
60541         {"USB"                         ,        56,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60542         {"RESERVED_57_58"              ,        57,     2,      79,     "RAZ",  0,      0,      0ull,   0ull},
60543         {"TWSI2"                       ,        59,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60544         {"POWIQ"                       ,        60,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60545         {"IPDPPTHR"                    ,        61,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60546         {"MII"                         ,        62,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60547         {"BOOTDMA"                     ,        63,     1,      79,     "RO",   0,      0,      0ull,   0ull},
60548         {"WORKQ"                       ,        0,      16,     80,     "RO",   0,      0,      0ull,   0ull},
60549         {"GPIO"                        ,        16,     16,     80,     "RO",   0,      0,      0ull,   0ull},
60550         {"MBOX"                        ,        32,     2,      80,     "RO",   0,      0,      0ull,   0ull},
60551         {"UART"                        ,        34,     2,      80,     "RO",   0,      0,      0ull,   0ull},
60552         {"PCI_INT"                     ,        36,     4,      80,     "RO",   0,      0,      0ull,   0ull},
60553         {"PCI_MSI"                     ,        40,     4,      80,     "RO",   0,      0,      0ull,   0ull},
60554         {"WDOG_SUM"                    ,        44,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60555         {"TWSI"                        ,        45,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60556         {"RML"                         ,        46,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60557         {"TRACE"                       ,        47,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60558         {"GMX_DRP"                     ,        48,     1,      80,     "R/W1C",        0,      0,      0ull,   0ull},
60559         {"RESERVED_49_49"              ,        49,     1,      80,     "RAZ",  0,      0,      0ull,   0ull},
60560         {"IPD_DRP"                     ,        50,     1,      80,     "R/W1C",        0,      0,      0ull,   0ull},
60561         {"RESERVED_51_51"              ,        51,     1,      80,     "RAZ",  0,      0,      0ull,   0ull},
60562         {"TIMER"                       ,        52,     4,      80,     "R/W1C",        0,      0,      0ull,   0ull},
60563         {"USB"                         ,        56,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60564         {"RESERVED_57_58"              ,        57,     2,      80,     "RAZ",  0,      0,      0ull,   0ull},
60565         {"TWSI2"                       ,        59,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60566         {"POWIQ"                       ,        60,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60567         {"IPDPPTHR"                    ,        61,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60568         {"MII"                         ,        62,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60569         {"BOOTDMA"                     ,        63,     1,      80,     "RO",   0,      0,      0ull,   0ull},
60570         {"WDOG"                        ,        0,      4,      81,     "RO",   0,      0,      0ull,   0ull},
60571         {"RESERVED_4_15"               ,        4,      12,     81,     "RAZ",  1,      1,      0,      0},
60572         {"UART2"                       ,        16,     1,      81,     "RO",   0,      0,      0ull,   0ull},
60573         {"USB1"                        ,        17,     1,      81,     "RO",   0,      0,      0ull,   0ull},
60574         {"MII1"                        ,        18,     1,      81,     "RO",   0,      0,      0ull,   0ull},
60575         {"RESERVED_19_63"              ,        19,     45,     81,     "RAZ",  1,      1,      0,      0},
60576         {"BITS"                        ,        0,      32,     82,     "R/W1C",        0,      0,      0ull,   0ull},
60577         {"RESERVED_32_63"              ,        32,     32,     82,     "RAZ",  1,      1,      0,      0},
60578         {"BITS"                        ,        0,      32,     83,     "R/W1", 0,      0,      0ull,   0ull},
60579         {"RESERVED_32_63"              ,        32,     32,     83,     "RAZ",  1,      1,      0,      0},
60580         {"NMI"                         ,        0,      4,      84,     "WO",   0,      0,      0ull,   0ull},
60581         {"RESERVED_4_63"               ,        4,      60,     84,     "RAZ",  1,      1,      0,      0},
60582         {"INTR"                        ,        0,      2,      85,     "R/W",  0,      0,      0ull,   0ull},
60583         {"RESERVED_2_63"               ,        2,      62,     85,     "RAZ",  1,      1,      0,      0},
60584         {"PPDBG"                       ,        0,      4,      86,     "RO",   0,      0,      0ull,   0ull},
60585         {"RESERVED_4_63"               ,        4,      60,     86,     "RAZ",  1,      1,      0,      0},
60586         {"POKE"                        ,        0,      64,     87,     "RAZ",  1,      1,      0,      0},
60587         {"RST0"                        ,        0,      1,      88,     "R/W",  1,      1,      0,      0},
60588         {"RST"                         ,        1,      3,      88,     "R/W",  0,      0,      32767ull,       0ull},
60589         {"RESERVED_4_63"               ,        4,      60,     88,     "RAZ",  1,      1,      0,      0},
60590         {"QLM_DCOK"                    ,        0,      2,      89,     "R/W",  0,      0,      1ull,   1ull},
60591         {"RESERVED_2_63"               ,        2,      62,     89,     "RAZ",  1,      1,      0,      0},
60592         {"BYPASS"                      ,        0,      2,      90,     "R/W",  0,      1,      0ull,   0},
60593         {"RESERVED_2_3"                ,        2,      2,      90,     "RAZ",  1,      1,      0,      0},
60594         {"MUX_SEL"                     ,        4,      1,      90,     "R/W",  0,      1,      0ull,   0},
60595         {"RESERVED_5_7"                ,        5,      3,      90,     "RAZ",  1,      1,      0,      0},
60596         {"CLK_DIV"                     ,        8,      3,      90,     "R/W",  0,      1,      0ull,   0},
60597         {"RESERVED_11_63"              ,        11,     53,     90,     "RAZ",  1,      1,      0,      0},
60598         {"SHFT_REG"                    ,        0,      32,     91,     "R/W",  0,      1,      0ull,   0},
60599         {"SHFT_CNT"                    ,        32,     5,      91,     "R/W",  0,      1,      0ull,   0},
60600         {"RESERVED_37_39"              ,        37,     3,      91,     "RAZ",  1,      1,      0,      0},
60601         {"SELECT"                      ,        40,     2,      91,     "R/W",  0,      1,      0ull,   0},
60602         {"RESERVED_42_60"              ,        42,     19,     91,     "RAZ",  1,      1,      0,      0},
60603         {"UPDATE"                      ,        61,     1,      91,     "R/W",  0,      1,      0ull,   0},
60604         {"SHIFT"                       ,        62,     1,      91,     "R/W",  0,      1,      0ull,   0},
60605         {"CAPTURE"                     ,        63,     1,      91,     "R/W",  0,      1,      0ull,   0},
60606         {"SOFT_BIST"                   ,        0,      1,      92,     "R/W",  0,      0,      0ull,   0ull},
60607         {"RESERVED_1_63"               ,        1,      63,     92,     "RAZ",  1,      1,      0,      0},
60608         {"SOFT_PRST"                   ,        0,      1,      93,     "R/W",  0,      0,      1ull,   0ull},
60609         {"RESERVED_1_63"               ,        1,      63,     93,     "RAZ",  1,      1,      0,      0},
60610         {"SOFT_PRST"                   ,        0,      1,      94,     "R/W",  0,      0,      1ull,   0ull},
60611         {"RESERVED_1_63"               ,        1,      63,     94,     "RAZ",  1,      1,      0,      0},
60612         {"SOFT_RST"                    ,        0,      1,      95,     "WO",   0,      0,      0ull,   0ull},
60613         {"RESERVED_1_63"               ,        1,      63,     95,     "RAZ",  1,      1,      0,      0},
60614         {"LEN"                         ,        0,      36,     96,     "R/W",  0,      0,      0ull,   0ull},
60615         {"ONE_SHOT"                    ,        36,     1,      96,     "R/W",  0,      0,      0ull,   0ull},
60616         {"RESERVED_37_63"              ,        37,     27,     96,     "RAZ",  1,      1,      0,      0},
60617         {"MODE"                        ,        0,      2,      97,     "R/W",  0,      0,      0ull,   0ull},
60618         {"STATE"                       ,        2,      2,      97,     "RO",   0,      0,      0ull,   0ull},
60619         {"LEN"                         ,        4,      16,     97,     "R/W",  0,      0,      0ull,   0ull},
60620         {"CNT"                         ,        20,     24,     97,     "RO",   0,      0,      0ull,   0ull},
60621         {"DSTOP"                       ,        44,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
60622         {"GSTOPEN"                     ,        45,     1,      97,     "R/W",  0,      0,      0ull,   0ull},
60623         {"RESERVED_46_63"              ,        46,     18,     97,     "RAZ",  1,      1,      0,      0},
60624         {"FDR"                         ,        0,      1,      98,     "RO",   0,      0,      0ull,   0ull},
60625         {"FFR"                         ,        1,      1,      98,     "RO",   0,      0,      0ull,   0ull},
60626         {"FPF1"                        ,        2,      1,      98,     "RO",   0,      0,      0ull,   0ull},
60627         {"FPF0"                        ,        3,      1,      98,     "RO",   0,      0,      0ull,   0ull},
60628         {"FRD"                         ,        4,      1,      98,     "RO",   0,      0,      0ull,   0ull},
60629         {"RESERVED_5_63"               ,        5,      59,     98,     "RAZ",  1,      1,      0,      0},
60630         {"MEM0_ERR"                    ,        0,      7,      99,     "R/W",  0,      0,      0ull,   0ull},
60631         {"MEM1_ERR"                    ,        7,      7,      99,     "R/W",  0,      0,      0ull,   0ull},
60632         {"ENB"                         ,        14,     1,      99,     "R/W",  0,      0,      0ull,   0ull},
60633         {"USE_STT"                     ,        15,     1,      99,     "R/W",  0,      0,      0ull,   0ull},
60634         {"USE_LDT"                     ,        16,     1,      99,     "R/W",  0,      0,      0ull,   0ull},
60635         {"RESET"                       ,        17,     1,      99,     "R/W",  0,      0,      0ull,   0ull},
60636         {"RESERVED_18_63"              ,        18,     46,     99,     "RAZ",  1,      1,      0,      0},
60637         {"FED0_SBE"                    ,        0,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60638         {"FED0_DBE"                    ,        1,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60639         {"FED1_SBE"                    ,        2,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60640         {"FED1_DBE"                    ,        3,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60641         {"Q0_UND"                      ,        4,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60642         {"Q0_COFF"                     ,        5,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60643         {"Q0_PERR"                     ,        6,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60644         {"Q1_UND"                      ,        7,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60645         {"Q1_COFF"                     ,        8,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60646         {"Q1_PERR"                     ,        9,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
60647         {"Q2_UND"                      ,        10,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60648         {"Q2_COFF"                     ,        11,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60649         {"Q2_PERR"                     ,        12,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60650         {"Q3_UND"                      ,        13,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60651         {"Q3_COFF"                     ,        14,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60652         {"Q3_PERR"                     ,        15,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60653         {"Q4_UND"                      ,        16,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60654         {"Q4_COFF"                     ,        17,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60655         {"Q4_PERR"                     ,        18,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60656         {"Q5_UND"                      ,        19,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60657         {"Q5_COFF"                     ,        20,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60658         {"Q5_PERR"                     ,        21,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60659         {"Q6_UND"                      ,        22,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60660         {"Q6_COFF"                     ,        23,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60661         {"Q6_PERR"                     ,        24,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60662         {"Q7_UND"                      ,        25,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60663         {"Q7_COFF"                     ,        26,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60664         {"Q7_PERR"                     ,        27,     1,      100,    "R/W",  0,      0,      0ull,   0ull},
60665         {"RESERVED_28_63"              ,        28,     36,     100,    "RAZ",  1,      1,      0,      0},
60666         {"FED0_SBE"                    ,        0,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60667         {"FED0_DBE"                    ,        1,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60668         {"FED1_SBE"                    ,        2,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60669         {"FED1_DBE"                    ,        3,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60670         {"Q0_UND"                      ,        4,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60671         {"Q0_COFF"                     ,        5,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60672         {"Q0_PERR"                     ,        6,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60673         {"Q1_UND"                      ,        7,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60674         {"Q1_COFF"                     ,        8,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60675         {"Q1_PERR"                     ,        9,      1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60676         {"Q2_UND"                      ,        10,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60677         {"Q2_COFF"                     ,        11,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60678         {"Q2_PERR"                     ,        12,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60679         {"Q3_UND"                      ,        13,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60680         {"Q3_COFF"                     ,        14,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60681         {"Q3_PERR"                     ,        15,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60682         {"Q4_UND"                      ,        16,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60683         {"Q4_COFF"                     ,        17,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60684         {"Q4_PERR"                     ,        18,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60685         {"Q5_UND"                      ,        19,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60686         {"Q5_COFF"                     ,        20,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60687         {"Q5_PERR"                     ,        21,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60688         {"Q6_UND"                      ,        22,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60689         {"Q6_COFF"                     ,        23,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60690         {"Q6_PERR"                     ,        24,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60691         {"Q7_UND"                      ,        25,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60692         {"Q7_COFF"                     ,        26,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60693         {"Q7_PERR"                     ,        27,     1,      101,    "R/W1C",        0,      0,      0ull,   0ull},
60694         {"RESERVED_28_63"              ,        28,     36,     101,    "RAZ",  1,      1,      0,      0},
60695         {"QUE_SIZ"                     ,        0,      29,     102,    "RO",   0,      0,      0ull,   0ull},
60696         {"RESERVED_29_63"              ,        29,     35,     102,    "RAZ",  1,      1,      0,      0},
60697         {"PG_NUM"                      ,        0,      25,     103,    "RO",   0,      1,      0ull,   0},
60698         {"RESERVED_25_63"              ,        25,     39,     103,    "RAZ",  1,      1,      0,      0},
60699         {"ACT_INDX"                    ,        0,      26,     104,    "RO",   0,      1,      0ull,   0},
60700         {"ACT_QUE"                     ,        26,     3,      104,    "RO",   0,      1,      0ull,   0},
60701         {"RESERVED_29_63"              ,        29,     35,     104,    "RAZ",  0,      0,      0ull,   7ull},
60702         {"EXP_INDX"                    ,        0,      26,     105,    "RO",   0,      1,      0ull,   0},
60703         {"EXP_QUE"                     ,        26,     3,      105,    "RO",   0,      1,      0ull,   0},
60704         {"RESERVED_29_63"              ,        29,     35,     105,    "RAZ",  0,      0,      0ull,   7ull},
60705         {"CTL"                         ,        0,      16,     106,    "R/W",  1,      0,      0,      0ull},
60706         {"RESERVED_16_63"              ,        16,     48,     106,    "RAZ",  1,      1,      0,      0},
60707         {"STATUS"                      ,        0,      32,     107,    "RO",   0,      0,      0ull,   0ull},
60708         {"RESERVED_32_63"              ,        32,     32,     107,    "RAZ",  1,      1,      0,      0},
60709         {"RESERVED_0_1"                ,        0,      2,      108,    "RAZ",  1,      1,      0,      0},
60710         {"OUT_OVR"                     ,        2,      4,      108,    "R/W1C",        0,      0,      0ull,   0ull},
60711         {"RESERVED_6_21"               ,        6,      16,     108,    "RAZ",  1,      1,      0,      0},
60712         {"LOSTSTAT"                    ,        22,     4,      108,    "R/W1C",        0,      0,      0ull,   0ull},
60713         {"STATOVR"                     ,        26,     1,      108,    "R/W1C",        0,      0,      0ull,   0ull},
60714         {"INB_NXA"                     ,        27,     4,      108,    "R/W1C",        0,      0,      0ull,   0ull},
60715         {"RESERVED_31_63"              ,        31,     33,     108,    "RAZ",  1,      1,      0,      0},
60716         {"STATUS"                      ,        0,      16,     109,    "RO",   0,      0,      0ull,   0ull},
60717         {"RESERVED_16_63"              ,        16,     48,     109,    "RAZ",  1,      1,      0,      0},
60718         {"CLK_EN"                      ,        0,      1,      110,    "R/W",  0,      0,      0ull,   0ull},
60719         {"RESERVED_1_63"               ,        1,      63,     110,    "RAZ",  1,      1,      0,      0},
60720         {"LOGL_EN"                     ,        0,      16,     111,    "R/W",  0,      1,      65535ull,       0},
60721         {"PHYS_EN"                     ,        16,     1,      111,    "R/W",  0,      1,      1ull,   0},
60722         {"HG2RX_EN"                    ,        17,     1,      111,    "R/W",  0,      0,      0ull,   0ull},
60723         {"HG2TX_EN"                    ,        18,     1,      111,    "R/W",  0,      0,      0ull,   0ull},
60724         {"RESERVED_19_63"              ,        19,     45,     111,    "RAZ",  1,      1,      0,      0},
60725         {"TYPE"                        ,        0,      1,      112,    "RO",   0,      1,      0ull,   0},
60726         {"EN"                          ,        1,      1,      112,    "R/W",  0,      1,      0ull,   0},
60727         {"RESERVED_2_3"                ,        2,      2,      112,    "RAZ",  1,      1,      0,      0},
60728         {"MODE"                        ,        4,      2,      112,    "RO",   0,      1,      0ull,   0},
60729         {"RESERVED_6_7"                ,        6,      2,      112,    "RAZ",  1,      1,      0,      0},
60730         {"SPEED"                       ,        8,      2,      112,    "RO",   1,      1,      0,      0},
60731         {"RESERVED_10_63"              ,        10,     54,     112,    "RAZ",  1,      1,      0,      0},
60732         {"PRT"                         ,        0,      6,      113,    "RO",   0,      1,      0ull,   0},
60733         {"RESERVED_6_63"               ,        6,      58,     113,    "RAZ",  1,      1,      0,      0},
60734         {"EN"                          ,        0,      1,      114,    "R/W",  0,      1,      0ull,   0},
60735         {"SPEED"                       ,        1,      1,      114,    "R/W",  0,      1,      1ull,   0},
60736         {"DUPLEX"                      ,        2,      1,      114,    "R/W",  0,      1,      1ull,   0},
60737         {"SLOTTIME"                    ,        3,      1,      114,    "R/W",  0,      1,      1ull,   0},
60738         {"RESERVED_4_7"                ,        4,      4,      114,    "RAZ",  1,      1,      0,      0},
60739         {"SPEED_MSB"                   ,        8,      1,      114,    "R/W",  0,      1,      0ull,   0},
60740         {"RESERVED_9_11"               ,        9,      3,      114,    "RAZ",  1,      1,      0,      0},
60741         {"RX_IDLE"                     ,        12,     1,      114,    "RO",   0,      1,      1ull,   0},
60742         {"TX_IDLE"                     ,        13,     1,      114,    "RO",   0,      1,      1ull,   0},
60743         {"RESERVED_14_63"              ,        14,     50,     114,    "RAZ",  1,      1,      0,      0},
60744         {"ADR"                         ,        0,      64,     115,    "R/W",  0,      1,      0ull,   0},
60745         {"ADR"                         ,        0,      64,     116,    "R/W",  0,      1,      0ull,   0},
60746         {"ADR"                         ,        0,      64,     117,    "R/W",  0,      1,      0ull,   0},
60747         {"ADR"                         ,        0,      64,     118,    "R/W",  0,      1,      0ull,   0},
60748         {"ADR"                         ,        0,      64,     119,    "R/W",  0,      1,      0ull,   0},
60749         {"ADR"                         ,        0,      64,     120,    "R/W",  0,      1,      0ull,   0},
60750         {"EN"                          ,        0,      8,      121,    "R/W",  0,      1,      0ull,   0},
60751         {"RESERVED_8_63"               ,        8,      56,     121,    "RAZ",  1,      1,      0,      0},
60752         {"BCST"                        ,        0,      1,      122,    "R/W",  0,      1,      1ull,   0},
60753         {"MCST"                        ,        1,      2,      122,    "R/W",  0,      1,      0ull,   0},
60754         {"CAM_MODE"                    ,        3,      1,      122,    "R/W",  0,      1,      0ull,   0},
60755         {"RESERVED_4_63"               ,        4,      60,     122,    "RAZ",  1,      1,      0,      0},
60756         {"CNT"                         ,        0,      5,      123,    "R/W",  0,      0,      24ull,  24ull},
60757         {"RESERVED_5_63"               ,        5,      59,     123,    "RAZ",  1,      1,      0,      0},
60758         {"RESERVED_0_0"                ,        0,      1,      124,    "RAZ",  1,      1,      0,      0},
60759         {"CAREXT"                      ,        1,      1,      124,    "R/W",  0,      0,      1ull,   1ull},
60760         {"RESERVED_2_2"                ,        2,      1,      124,    "RAZ",  1,      1,      0,      0},
60761         {"JABBER"                      ,        3,      1,      124,    "R/W",  0,      0,      1ull,   1ull},
60762         {"FCSERR"                      ,        4,      1,      124,    "R/W",  0,      0,      1ull,   1ull},
60763         {"RESERVED_5_6"                ,        5,      2,      124,    "RAZ",  1,      1,      0,      0},
60764         {"RCVERR"                      ,        7,      1,      124,    "R/W",  0,      0,      1ull,   1ull},
60765         {"SKPERR"                      ,        8,      1,      124,    "R/W",  0,      0,      1ull,   1ull},
60766         {"RESERVED_9_63"               ,        9,      55,     124,    "RAZ",  1,      1,      0,      0},
60767         {"PRE_CHK"                     ,        0,      1,      125,    "R/W",  0,      0,      1ull,   1ull},
60768         {"PRE_STRP"                    ,        1,      1,      125,    "R/W",  0,      0,      1ull,   1ull},
60769         {"CTL_DRP"                     ,        2,      1,      125,    "R/W",  0,      0,      1ull,   1ull},
60770         {"CTL_BCK"                     ,        3,      1,      125,    "R/W",  0,      0,      1ull,   1ull},
60771         {"CTL_MCST"                    ,        4,      1,      125,    "R/W",  0,      0,      1ull,   1ull},
60772         {"CTL_SMAC"                    ,        5,      1,      125,    "R/W",  0,      0,      0ull,   0ull},
60773         {"PRE_FREE"                    ,        6,      1,      125,    "RO",   0,      0,      1ull,   1ull},
60774         {"RESERVED_7_8"                ,        7,      2,      125,    "RAZ",  1,      1,      0,      0},
60775         {"PRE_ALIGN"                   ,        9,      1,      125,    "R/W",  0,      0,      0ull,   0ull},
60776         {"NULL_DIS"                    ,        10,     1,      125,    "R/W",  0,      0,      0ull,   0ull},
60777         {"RESERVED_11_63"              ,        11,     53,     125,    "RAZ",  1,      1,      0,      0},
60778         {"IFG"                         ,        0,      4,      126,    "R/W",  0,      0,      8ull,   8ull},
60779         {"RESERVED_4_63"               ,        4,      60,     126,    "RAZ",  1,      1,      0,      0},
60780         {"RESERVED_0_0"                ,        0,      1,      127,    "RAZ",  1,      1,      0,      0},
60781         {"CAREXT"                      ,        1,      1,      127,    "R/W",  0,      0,      0ull,   0ull},
60782         {"RESERVED_2_2"                ,        2,      1,      127,    "RAZ",  1,      1,      0,      0},
60783         {"JABBER"                      ,        3,      1,      127,    "R/W",  0,      0,      0ull,   0ull},
60784         {"FCSERR"                      ,        4,      1,      127,    "R/W",  0,      0,      0ull,   0ull},
60785         {"RESERVED_5_6"                ,        5,      2,      127,    "RAZ",  1,      1,      0,      0},
60786         {"RCVERR"                      ,        7,      1,      127,    "R/W",  0,      0,      0ull,   0ull},
60787         {"SKPERR"                      ,        8,      1,      127,    "R/W",  0,      0,      0ull,   0ull},
60788         {"RESERVED_9_9"                ,        9,      1,      127,    "RAZ",  1,      1,      0,      0},
60789         {"OVRERR"                      ,        10,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60790         {"PCTERR"                      ,        11,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60791         {"RSVERR"                      ,        12,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60792         {"FALERR"                      ,        13,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60793         {"COLDET"                      ,        14,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60794         {"IFGERR"                      ,        15,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60795         {"RESERVED_16_18"              ,        16,     3,      127,    "RAZ",  1,      1,      0,      0},
60796         {"PAUSE_DRP"                   ,        19,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60797         {"LOC_FAULT"                   ,        20,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60798         {"REM_FAULT"                   ,        21,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60799         {"BAD_SEQ"                     ,        22,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60800         {"BAD_TERM"                    ,        23,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60801         {"UNSOP"                       ,        24,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60802         {"UNEOP"                       ,        25,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60803         {"UNDAT"                       ,        26,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60804         {"HG2FLD"                      ,        27,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60805         {"HG2CC"                       ,        28,     1,      127,    "R/W",  0,      0,      0ull,   0ull},
60806         {"RESERVED_29_63"              ,        29,     35,     127,    "RAZ",  1,      1,      0,      0},
60807         {"RESERVED_0_0"                ,        0,      1,      128,    "RAZ",  1,      1,      0,      0},
60808         {"CAREXT"                      ,        1,      1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60809         {"RESERVED_2_2"                ,        2,      1,      128,    "RAZ",  1,      1,      0,      0},
60810         {"JABBER"                      ,        3,      1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60811         {"FCSERR"                      ,        4,      1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60812         {"RESERVED_5_6"                ,        5,      2,      128,    "RAZ",  1,      1,      0,      0},
60813         {"RCVERR"                      ,        7,      1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60814         {"SKPERR"                      ,        8,      1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60815         {"RESERVED_9_9"                ,        9,      1,      128,    "RAZ",  1,      1,      0,      0},
60816         {"OVRERR"                      ,        10,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60817         {"PCTERR"                      ,        11,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60818         {"RSVERR"                      ,        12,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60819         {"FALERR"                      ,        13,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60820         {"COLDET"                      ,        14,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60821         {"IFGERR"                      ,        15,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60822         {"RESERVED_16_18"              ,        16,     3,      128,    "RAZ",  1,      1,      0,      0},
60823         {"PAUSE_DRP"                   ,        19,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60824         {"LOC_FAULT"                   ,        20,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60825         {"REM_FAULT"                   ,        21,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60826         {"BAD_SEQ"                     ,        22,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60827         {"BAD_TERM"                    ,        23,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60828         {"UNSOP"                       ,        24,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60829         {"UNEOP"                       ,        25,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60830         {"UNDAT"                       ,        26,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60831         {"HG2FLD"                      ,        27,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60832         {"HG2CC"                       ,        28,     1,      128,    "R/W1C",        0,      0,      0ull,   0ull},
60833         {"RESERVED_29_63"              ,        29,     35,     128,    "RAZ",  1,      1,      0,      0},
60834         {"CNT"                         ,        0,      16,     129,    "R/W",  0,      0,      10240ull,       10240ull},
60835         {"RESERVED_16_63"              ,        16,     48,     129,    "RAZ",  1,      1,      0,      0},
60836         {"STATUS"                      ,        0,      16,     130,    "R/W1C",        0,      1,      0ull,   0},
60837         {"RESERVED_16_63"              ,        16,     48,     130,    "RAZ",  1,      1,      0,      0},
60838         {"RD_CLR"                      ,        0,      1,      131,    "R/W",  0,      0,      0ull,   0ull},
60839         {"RESERVED_1_63"               ,        1,      63,     131,    "RAZ",  1,      1,      0,      0},
60840         {"CNT"                         ,        0,      48,     132,    "RC/W", 0,      1,      0ull,   0},
60841         {"RESERVED_48_63"              ,        48,     16,     132,    "RAZ",  1,      1,      0,      0},
60842         {"CNT"                         ,        0,      48,     133,    "RC/W", 0,      1,      0ull,   0},
60843         {"RESERVED_48_63"              ,        48,     16,     133,    "RAZ",  1,      1,      0,      0},
60844         {"CNT"                         ,        0,      48,     134,    "RC/W", 0,      1,      0ull,   0},
60845         {"RESERVED_48_63"              ,        48,     16,     134,    "RAZ",  1,      1,      0,      0},
60846         {"CNT"                         ,        0,      48,     135,    "RC/W", 0,      1,      0ull,   0},
60847         {"RESERVED_48_63"              ,        48,     16,     135,    "RAZ",  1,      1,      0,      0},
60848         {"CNT"                         ,        0,      32,     136,    "RC/W", 0,      1,      0ull,   0},
60849         {"RESERVED_32_63"              ,        32,     32,     136,    "RAZ",  1,      1,      0,      0},
60850         {"CNT"                         ,        0,      32,     137,    "RC/W", 0,      1,      0ull,   0},
60851         {"RESERVED_32_63"              ,        32,     32,     137,    "RAZ",  1,      1,      0,      0},
60852         {"CNT"                         ,        0,      32,     138,    "RC/W", 0,      1,      0ull,   0},
60853         {"RESERVED_32_63"              ,        32,     32,     138,    "RAZ",  1,      1,      0,      0},
60854         {"CNT"                         ,        0,      32,     139,    "RC/W", 0,      1,      0ull,   0},
60855         {"RESERVED_32_63"              ,        32,     32,     139,    "RAZ",  1,      1,      0,      0},
60856         {"CNT"                         ,        0,      32,     140,    "RC/W", 0,      1,      0ull,   0},
60857         {"RESERVED_32_63"              ,        32,     32,     140,    "RAZ",  1,      1,      0,      0},
60858         {"LEN"                         ,        0,      7,      141,    "R/W",  0,      0,      0ull,   0ull},
60859         {"RESERVED_7_7"                ,        7,      1,      141,    "RAZ",  1,      1,      0,      0},
60860         {"FCSSEL"                      ,        8,      1,      141,    "R/W",  0,      0,      0ull,   0ull},
60861         {"RESERVED_9_63"               ,        9,      55,     141,    "RAZ",  1,      1,      0,      0},
60862         {"MARK"                        ,        0,      6,      142,    "R/W",  0,      0,      2ull,   2ull},
60863         {"RESERVED_6_63"               ,        6,      58,     142,    "RAZ",  1,      1,      0,      0},
60864         {"MARK"                        ,        0,      6,      143,    "R/W",  0,      0,      16ull,  16ull},
60865         {"RESERVED_6_63"               ,        6,      58,     143,    "RAZ",  1,      1,      0,      0},
60866         {"MARK"                        ,        0,      9,      144,    "R/W",  0,      0,      64ull,  64ull},
60867         {"RESERVED_9_63"               ,        9,      55,     144,    "RAZ",  1,      1,      0,      0},
60868         {"LGTIM2GO"                    ,        0,      16,     145,    "RO",   0,      1,      0ull,   0},
60869         {"XOF"                         ,        16,     16,     145,    "RO",   0,      0,      0ull,   0ull},
60870         {"PHTIM2GO"                    ,        32,     16,     145,    "RO",   0,      1,      0ull,   0},
60871         {"RESERVED_48_63"              ,        48,     16,     145,    "RAZ",  1,      1,      0,      0},
60872         {"COMMIT"                      ,        0,      4,      146,    "RO",   0,      0,      0ull,   0ull},
60873         {"RESERVED_4_15"               ,        4,      12,     146,    "RAZ",  1,      1,      0,      0},
60874         {"DROP"                        ,        16,     4,      146,    "RO",   0,      0,      0ull,   0ull},
60875         {"RESERVED_20_63"              ,        20,     44,     146,    "RAZ",  1,      1,      0,      0},
60876         {"PRTS"                        ,        0,      3,      147,    "R/W",  0,      0,      4ull,   4ull},
60877         {"RESERVED_3_63"               ,        3,      61,     147,    "RAZ",  1,      1,      0,      0},
60878         {"LANE_RXD"                    ,        0,      32,     148,    "RO",   0,      1,      0ull,   0},
60879         {"LANE_RXC"                    ,        32,     4,      148,    "RO",   0,      1,      0ull,   0},
60880         {"STATE"                       ,        36,     3,      148,    "RO",   0,      1,      0ull,   0},
60881         {"VAL"                         ,        39,     1,      148,    "R/W1C",        0,      1,      0ull,   0},
60882         {"RESERVED_40_63"              ,        40,     24,     148,    "RAZ",  1,      1,      0,      0},
60883         {"STATUS"                      ,        0,      2,      149,    "RO",   0,      0,      0ull,   0ull},
60884         {"RESERVED_2_63"               ,        2,      62,     149,    "RAZ",  1,      1,      0,      0},
60885         {"SMAC"                        ,        0,      48,     150,    "R/W",  0,      1,      0ull,   0},
60886         {"RESERVED_48_63"              ,        48,     16,     150,    "RAZ",  1,      1,      0,      0},
60887         {"CNT"                         ,        0,      16,     151,    "R/W1C",        0,      0,      0ull,   0ull},
60888         {"BP"                          ,        16,     1,      151,    "RO",   0,      0,      0ull,   0ull},
60889         {"RESERVED_17_63"              ,        17,     47,     151,    "RAZ",  1,      1,      0,      0},
60890         {"PREAMBLE"                    ,        0,      1,      152,    "R/W",  0,      0,      1ull,   1ull},
60891         {"PAD"                         ,        1,      1,      152,    "R/W",  0,      0,      1ull,   1ull},
60892         {"FCS"                         ,        2,      1,      152,    "R/W",  0,      0,      1ull,   1ull},
60893         {"FORCE_FCS"                   ,        3,      1,      152,    "R/W",  0,      0,      1ull,   1ull},
60894         {"RESERVED_4_63"               ,        4,      60,     152,    "RAZ",  1,      1,      0,      0},
60895         {"BURST"                       ,        0,      16,     153,    "R/W",  0,      0,      8192ull,        8192ull},
60896         {"RESERVED_16_63"              ,        16,     48,     153,    "RAZ",  1,      1,      0,      0},
60897         {"XSCOL_EN"                    ,        0,      1,      154,    "R/W",  0,      0,      1ull,   1ull},
60898         {"XSDEF_EN"                    ,        1,      1,      154,    "R/W",  0,      0,      1ull,   1ull},
60899         {"RESERVED_2_63"               ,        2,      62,     154,    "RAZ",  1,      1,      0,      0},
60900         {"MIN_SIZE"                    ,        0,      8,      155,    "R/W",  0,      0,      59ull,  59ull},
60901         {"RESERVED_8_63"               ,        8,      56,     155,    "RAZ",  1,      1,      0,      0},
60902         {"INTERVAL"                    ,        0,      16,     156,    "R/W",  0,      1,      16ull,  0},
60903         {"RESERVED_16_63"              ,        16,     48,     156,    "RAZ",  1,      1,      0,      0},
60904         {"TIME"                        ,        0,      16,     157,    "R/W",  0,      1,      96ull,  0},
60905         {"RESERVED_16_63"              ,        16,     48,     157,    "RAZ",  1,      1,      0,      0},
60906         {"TIME"                        ,        0,      16,     158,    "RO",   1,      1,      0,      0},
60907         {"MSG_TIME"                    ,        16,     16,     158,    "RO",   1,      1,      0,      0},
60908         {"RESERVED_32_63"              ,        32,     32,     158,    "RAZ",  1,      1,      0,      0},
60909         {"SEND"                        ,        0,      1,      159,    "R/W",  0,      0,      1ull,   1ull},
60910         {"RESERVED_1_63"               ,        1,      63,     159,    "RAZ",  1,      1,      0,      0},
60911         {"ALIGN"                       ,        0,      1,      160,    "R/W",  0,      0,      1ull,   1ull},
60912         {"RESERVED_1_63"               ,        1,      63,     160,    "RAZ",  1,      1,      0,      0},
60913         {"SLOT"                        ,        0,      10,     161,    "R/W",  0,      0,      512ull, 512ull},
60914         {"RESERVED_10_63"              ,        10,     54,     161,    "RAZ",  1,      1,      0,      0},
60915         {"TIME"                        ,        0,      16,     162,    "R/W",  0,      1,      0ull,   0},
60916         {"RESERVED_16_63"              ,        16,     48,     162,    "RAZ",  1,      1,      0,      0},
60917         {"XSCOL"                       ,        0,      32,     163,    "RC/W", 0,      1,      0ull,   0},
60918         {"XSDEF"                       ,        32,     32,     163,    "RC/W", 0,      1,      0ull,   0},
60919         {"MCOL"                        ,        0,      32,     164,    "RC/W", 0,      1,      0ull,   0},
60920         {"SCOL"                        ,        32,     32,     164,    "RC/W", 0,      1,      0ull,   0},
60921         {"OCTS"                        ,        0,      48,     165,    "RC/W", 0,      1,      0ull,   0},
60922         {"RESERVED_48_63"              ,        48,     16,     165,    "RAZ",  1,      1,      0,      0},
60923         {"PKTS"                        ,        0,      32,     166,    "RC/W", 0,      1,      0ull,   0},
60924         {"RESERVED_32_63"              ,        32,     32,     166,    "RAZ",  1,      1,      0,      0},
60925         {"HIST0"                       ,        0,      32,     167,    "RC/W", 0,      1,      0ull,   0},
60926         {"HIST1"                       ,        32,     32,     167,    "RC/W", 0,      1,      0ull,   0},
60927         {"HIST2"                       ,        0,      32,     168,    "RC/W", 0,      1,      0ull,   0},
60928         {"HIST3"                       ,        32,     32,     168,    "RC/W", 0,      1,      0ull,   0},
60929         {"HIST4"                       ,        0,      32,     169,    "RC/W", 0,      1,      0ull,   0},
60930         {"HIST5"                       ,        32,     32,     169,    "RC/W", 0,      1,      0ull,   0},
60931         {"HIST6"                       ,        0,      32,     170,    "RC/W", 0,      1,      0ull,   0},
60932         {"HIST7"                       ,        32,     32,     170,    "RC/W", 0,      1,      0ull,   0},
60933         {"BCST"                        ,        0,      32,     171,    "RC/W", 0,      1,      0ull,   0},
60934         {"MCST"                        ,        32,     32,     171,    "RC/W", 0,      1,      0ull,   0},
60935         {"CTL"                         ,        0,      32,     172,    "RC/W", 0,      1,      0ull,   0},
60936         {"UNDFLW"                      ,        32,     32,     172,    "RC/W", 0,      1,      0ull,   0},
60937         {"RD_CLR"                      ,        0,      1,      173,    "R/W",  0,      0,      0ull,   0ull},
60938         {"RESERVED_1_63"               ,        1,      63,     173,    "RAZ",  1,      1,      0,      0},
60939         {"CNT"                         ,        0,      9,      174,    "R/W",  0,      0,      32ull,  32ull},
60940         {"RESERVED_9_63"               ,        9,      55,     174,    "RAZ",  1,      1,      0,      0},
60941         {"BP"                          ,        0,      4,      175,    "RO",   0,      0,      0ull,   0ull},
60942         {"RESERVED_4_63"               ,        4,      60,     175,    "RAZ",  1,      1,      0,      0},
60943         {"LIMIT"                       ,        0,      5,      176,    "R/W",  0,      0,      16ull,  16ull},
60944         {"RESERVED_5_63"               ,        5,      59,     176,    "RAZ",  1,      1,      0,      0},
60945         {"CORRUPT"                     ,        0,      4,      177,    "R/W",  0,      0,      15ull,  15ull},
60946         {"RESERVED_4_63"               ,        4,      60,     177,    "RAZ",  1,      1,      0,      0},
60947         {"TX_XOF"                      ,        0,      16,     178,    "R/W1", 0,      1,      0ull,   0},
60948         {"RESERVED_16_63"              ,        16,     48,     178,    "RAZ",  1,      1,      0,      0},
60949         {"TX_XON"                      ,        0,      16,     179,    "R/W1C",        0,      1,      0ull,   0},
60950         {"RESERVED_16_63"              ,        16,     48,     179,    "RAZ",  1,      1,      0,      0},
60951         {"IFG1"                        ,        0,      4,      180,    "R/W",  0,      1,      8ull,   0},
60952         {"IFG2"                        ,        4,      4,      180,    "R/W",  0,      1,      4ull,   0},
60953         {"RESERVED_8_63"               ,        8,      56,     180,    "RAZ",  1,      1,      0,      0},
60954         {"PKO_NXA"                     ,        0,      1,      181,    "R/W",  0,      0,      0ull,   0ull},
60955         {"RESERVED_1_1"                ,        1,      1,      181,    "RAZ",  0,      0,      0ull,   0ull},
60956         {"UNDFLW"                      ,        2,      4,      181,    "R/W",  0,      0,      0ull,   0ull},
60957         {"RESERVED_6_7"                ,        6,      2,      181,    "RAZ",  0,      0,      0ull,   0ull},
60958         {"XSCOL"                       ,        8,      4,      181,    "R/W",  0,      0,      0ull,   0ull},
60959         {"XSDEF"                       ,        12,     4,      181,    "R/W",  0,      0,      0ull,   0ull},
60960         {"LATE_COL"                    ,        16,     4,      181,    "R/W",  0,      0,      0ull,   0ull},
60961         {"RESERVED_20_63"              ,        20,     44,     181,    "RAZ",  1,      1,      0,      0},
60962         {"PKO_NXA"                     ,        0,      1,      182,    "R/W1C",        0,      0,      0ull,   0ull},
60963         {"RESERVED_1_1"                ,        1,      1,      182,    "RAZ",  0,      0,      0ull,   0ull},
60964         {"UNDFLW"                      ,        2,      4,      182,    "R/W1C",        0,      0,      0ull,   0ull},
60965         {"RESERVED_6_7"                ,        6,      2,      182,    "RAZ",  0,      0,      0ull,   0ull},
60966         {"XSCOL"                       ,        8,      4,      182,    "R/W1C",        0,      0,      0ull,   0ull},
60967         {"XSDEF"                       ,        12,     4,      182,    "R/W1C",        0,      0,      0ull,   0ull},
60968         {"LATE_COL"                    ,        16,     4,      182,    "R/W1C",        0,      0,      0ull,   0ull},
60969         {"RESERVED_20_63"              ,        20,     44,     182,    "RAZ",  1,      1,      0,      0},
60970         {"JAM"                         ,        0,      8,      183,    "R/W",  0,      1,      238ull, 0},
60971         {"RESERVED_8_63"               ,        8,      56,     183,    "RAZ",  1,      1,      0,      0},
60972         {"LFSR"                        ,        0,      16,     184,    "R/W",  0,      1,      65535ull,       0},
60973         {"RESERVED_16_63"              ,        16,     48,     184,    "RAZ",  1,      1,      0,      0},
60974         {"IGN_FULL"                    ,        0,      4,      185,    "R/W",  0,      0,      0ull,   0ull},
60975         {"BP"                          ,        4,      4,      185,    "R/W",  0,      0,      0ull,   0ull},
60976         {"EN"                          ,        8,      4,      185,    "R/W",  0,      0,      0ull,   0ull},
60977         {"RESERVED_12_31"              ,        12,     20,     185,    "RAZ",  1,      1,      0,      0},
60978         {"TX_PRT_BP"                   ,        32,     16,     185,    "R/W",  0,      0,      0ull,   0ull},
60979         {"RESERVED_48_63"              ,        48,     16,     185,    "RAZ",  1,      1,      0,      0},
60980         {"DMAC"                        ,        0,      48,     186,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
60981         {"RESERVED_48_63"              ,        48,     16,     186,    "RAZ",  1,      1,      0,      0},
60982         {"TYPE"                        ,        0,      16,     187,    "R/W",  0,      0,      34824ull,       34824ull},
60983         {"RESERVED_16_63"              ,        16,     48,     187,    "RAZ",  1,      1,      0,      0},
60984         {"PRTS"                        ,        0,      5,      188,    "R/W",  0,      1,      4ull,   0},
60985         {"RESERVED_5_63"               ,        5,      59,     188,    "RAZ",  1,      1,      0,      0},
60986         {"DIC_EN"                      ,        0,      1,      189,    "R/W",  0,      0,      0ull,   1ull},
60987         {"UNI_EN"                      ,        1,      1,      189,    "R/W",  0,      0,      0ull,   0ull},
60988         {"RESERVED_2_3"                ,        2,      2,      189,    "RAZ",  1,      1,      0,      0},
60989         {"LS"                          ,        4,      2,      189,    "R/W",  0,      0,      0ull,   0ull},
60990         {"LS_BYP"                      ,        6,      1,      189,    "R/W",  0,      0,      0ull,   0ull},
60991         {"RESERVED_7_7"                ,        7,      1,      189,    "RAZ",  1,      1,      0,      0},
60992         {"HG_EN"                       ,        8,      1,      189,    "R/W",  0,      0,      0ull,   0ull},
60993         {"HG_PAUSE_HGI"                ,        9,      2,      189,    "R/W",  0,      0,      2ull,   2ull},
60994         {"RESERVED_11_63"              ,        11,     53,     189,    "RAZ",  1,      1,      0,      0},
60995         {"THRESH"                      ,        0,      4,      190,    "R/W",  0,      0,      8ull,   8ull},
60996         {"EN"                          ,        4,      1,      190,    "R/W",  0,      0,      0ull,   0ull},
60997         {"RESERVED_5_63"               ,        5,      59,     190,    "RAZ",  1,      1,      0,      0},
60998         {"TX_OE"                       ,        0,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
60999         {"RX_XOR"                      ,        1,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
61000         {"INT_EN"                      ,        2,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
61001         {"INT_TYPE"                    ,        3,      1,      191,    "R/W",  0,      0,      0ull,   0ull},
61002         {"FIL_CNT"                     ,        4,      4,      191,    "R/W",  0,      0,      0ull,   0ull},
61003         {"FIL_SEL"                     ,        8,      4,      191,    "R/W",  0,      0,      0ull,   0ull},
61004         {"CLK_SEL"                     ,        12,     2,      191,    "R/W",  0,      0,      0ull,   0ull},
61005         {"CLK_GEN"                     ,        14,     1,      191,    "R/W",  0,      0,      0ull,   0ull},
61006         {"RESERVED_15_63"              ,        15,     49,     191,    "RAZ",  1,      1,      0,      0},
61007         {"N"                           ,        0,      32,     192,    "WO",   0,      1,      0ull,   0},
61008         {"RESERVED_32_63"              ,        32,     32,     192,    "RAZ",  1,      1,      0,      0},
61009         {"TYPE"                        ,        0,      16,     193,    "WO",   0,      0,      0ull,   0ull},
61010         {"RESERVED_16_63"              ,        16,     48,     193,    "RAZ",  1,      1,      0,      0},
61011         {"DAT"                         ,        0,      16,     194,    "RO",   0,      0,      0ull,   0ull},
61012         {"RESERVED_16_63"              ,        16,     48,     194,    "RAZ",  1,      1,      0,      0},
61013         {"CLR"                         ,        0,      16,     195,    "WO",   0,      0,      0ull,   0ull},
61014         {"RESERVED_16_63"              ,        16,     48,     195,    "RAZ",  1,      1,      0,      0},
61015         {"SET"                         ,        0,      16,     196,    "WO",   0,      0,      0ull,   0ull},
61016         {"RESERVED_16_63"              ,        16,     48,     196,    "RAZ",  1,      1,      0,      0},
61017         {"ICD"                         ,        0,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61018         {"IBD"                         ,        1,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61019         {"ICRP1"                       ,        2,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61020         {"ICRP0"                       ,        3,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61021         {"ICRN1"                       ,        4,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61022         {"ICRN0"                       ,        5,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61023         {"IBRQ1"                       ,        6,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61024         {"IBRQ0"                       ,        7,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61025         {"ICNRT"                       ,        8,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61026         {"IBR1"                        ,        9,      1,      197,    "RO",   0,      0,      0ull,   0ull},
61027         {"IBR0"                        ,        10,     1,      197,    "RO",   0,      0,      0ull,   0ull},
61028         {"IBDR1"                       ,        11,     1,      197,    "RO",   0,      0,      0ull,   0ull},
61029         {"IBDR0"                       ,        12,     1,      197,    "RO",   0,      0,      0ull,   0ull},
61030         {"ICNR0"                       ,        13,     1,      197,    "RO",   0,      0,      0ull,   0ull},
61031         {"ICNR1"                       ,        14,     1,      197,    "RO",   0,      0,      0ull,   0ull},
61032         {"ICR1"                        ,        15,     1,      197,    "RO",   0,      0,      0ull,   0ull},
61033         {"ICR0"                        ,        16,     1,      197,    "RO",   0,      0,      0ull,   0ull},
61034         {"ICNRCB"                      ,        17,     1,      197,    "RO",   0,      0,      0ull,   0ull},
61035         {"RESERVED_18_63"              ,        18,     46,     197,    "RAZ",  1,      1,      0,      0},
61036         {"FAU_END"                     ,        0,      1,      198,    "R/W",  0,      0,      0ull,   0ull},
61037         {"DWB_ENB"                     ,        1,      1,      198,    "R/W",  0,      0,      1ull,   1ull},
61038         {"PKO_ENB"                     ,        2,      1,      198,    "R/W",  0,      0,      0ull,   0ull},
61039         {"INB_MAT"                     ,        3,      1,      198,    "R/W1C",        0,      0,      0ull,   0ull},
61040         {"OUTB_MAT"                    ,        4,      1,      198,    "R/W1C",        0,      0,      0ull,   0ull},
61041         {"RESERVED_5_63"               ,        5,      59,     198,    "RAZ",  1,      1,      0,      0},
61042         {"CNT_VAL"                     ,        0,      15,     199,    "R/W",  0,      0,      0ull,   0ull},
61043         {"CNT_ENB"                     ,        15,     1,      199,    "R/W",  0,      0,      0ull,   0ull},
61044         {"RESERVED_16_63"              ,        16,     48,     199,    "RAZ",  1,      1,      0,      0},
61045         {"TOUT_VAL"                    ,        0,      12,     200,    "R/W",  0,      0,      4ull,   4ull},
61046         {"TOUT_ENB"                    ,        12,     1,      200,    "R/W",  0,      0,      1ull,   0ull},
61047         {"RESERVED_13_63"              ,        13,     51,     200,    "RAZ",  1,      1,      0,      0},
61048         {"CNT_VAL"                     ,        0,      15,     201,    "R/W",  0,      0,      0ull,   0ull},
61049         {"CNT_ENB"                     ,        15,     1,      201,    "R/W",  0,      0,      0ull,   0ull},
61050         {"RESERVED_16_63"              ,        16,     48,     201,    "RAZ",  1,      1,      0,      0},
61051         {"SRC"                         ,        0,      8,      202,    "R/W",  0,      1,      0ull,   0},
61052         {"DST"                         ,        8,      9,      202,    "R/W",  0,      1,      0ull,   0},
61053         {"OPC"                         ,        17,     4,      202,    "R/W",  0,      1,      0ull,   0},
61054         {"MASK"                        ,        21,     8,      202,    "R/W",  0,      1,      0ull,   0},
61055         {"RESERVED_29_63"              ,        29,     35,     202,    "RAZ",  1,      1,      0,      0},
61056         {"SRC"                         ,        0,      8,      203,    "R/W",  0,      1,      0ull,   0},
61057         {"DST"                         ,        8,      9,      203,    "R/W",  0,      1,      0ull,   0},
61058         {"OPC"                         ,        17,     4,      203,    "R/W",  0,      1,      0ull,   0},
61059         {"MASK"                        ,        21,     8,      203,    "R/W",  0,      1,      0ull,   0},
61060         {"RESERVED_29_63"              ,        29,     35,     203,    "RAZ",  1,      1,      0,      0},
61061         {"DATA"                        ,        0,      64,     204,    "R/W",  0,      1,      0ull,   0},
61062         {"DATA"                        ,        0,      64,     205,    "R/W",  0,      1,      0ull,   0},
61063         {"NP_SOP"                      ,        0,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
61064         {"NP_EOP"                      ,        1,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
61065         {"P_SOP"                       ,        2,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
61066         {"P_EOP"                       ,        3,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
61067         {"NP_DAT"                      ,        4,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
61068         {"P_DAT"                       ,        5,      1,      206,    "R/W",  0,      0,      0ull,   0ull},
61069         {"RESERVED_6_63"               ,        6,      58,     206,    "RAZ",  1,      1,      0,      0},
61070         {"NP_SOP"                      ,        0,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
61071         {"NP_EOP"                      ,        1,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
61072         {"P_SOP"                       ,        2,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
61073         {"P_EOP"                       ,        3,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
61074         {"NP_DAT"                      ,        4,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
61075         {"P_DAT"                       ,        5,      1,      207,    "R/W1C",        0,      0,      0ull,   0ull},
61076         {"RESERVED_6_63"               ,        6,      58,     207,    "RAZ",  1,      1,      0,      0},
61077         {"CNT_VAL"                     ,        0,      15,     208,    "R/W",  0,      0,      0ull,   0ull},
61078         {"CNT_ENB"                     ,        15,     1,      208,    "R/W",  0,      0,      0ull,   0ull},
61079         {"RESERVED_16_63"              ,        16,     48,     208,    "RAZ",  1,      1,      0,      0},
61080         {"CNT_VAL"                     ,        0,      15,     209,    "R/W",  0,      0,      0ull,   0ull},
61081         {"CNT_ENB"                     ,        15,     1,      209,    "R/W",  0,      0,      0ull,   0ull},
61082         {"RESERVED_16_63"              ,        16,     48,     209,    "RAZ",  1,      1,      0,      0},
61083         {"CNT_VAL"                     ,        0,      15,     210,    "R/W",  0,      0,      0ull,   0ull},
61084         {"CNT_ENB"                     ,        15,     1,      210,    "R/W",  0,      0,      0ull,   0ull},
61085         {"RESERVED_16_63"              ,        16,     48,     210,    "RAZ",  1,      1,      0,      0},
61086         {"SRC"                         ,        0,      9,      211,    "R/W",  0,      1,      0ull,   0},
61087         {"DST"                         ,        9,      8,      211,    "R/W",  0,      1,      0ull,   0},
61088         {"EOT"                         ,        17,     1,      211,    "R/W",  0,      1,      0ull,   0},
61089         {"MASK"                        ,        18,     8,      211,    "R/W",  0,      1,      0ull,   0},
61090         {"RESERVED_26_63"              ,        26,     38,     211,    "RAZ",  1,      1,      0,      0},
61091         {"SRC"                         ,        0,      9,      212,    "R/W",  0,      1,      0ull,   0},
61092         {"DST"                         ,        9,      8,      212,    "R/W",  0,      1,      0ull,   0},
61093         {"EOT"                         ,        17,     1,      212,    "R/W",  0,      1,      0ull,   0},
61094         {"MASK"                        ,        18,     8,      212,    "R/W",  0,      1,      0ull,   0},
61095         {"RESERVED_26_63"              ,        26,     38,     212,    "RAZ",  1,      1,      0,      0},
61096         {"DATA"                        ,        0,      64,     213,    "R/W",  0,      1,      0ull,   0},
61097         {"DATA"                        ,        0,      64,     214,    "R/W",  0,      1,      0ull,   0},
61098         {"CNT_VAL"                     ,        0,      15,     215,    "R/W",  0,      0,      0ull,   0ull},
61099         {"CNT_ENB"                     ,        15,     1,      215,    "R/W",  0,      0,      0ull,   0ull},
61100         {"RESERVED_16_63"              ,        16,     48,     215,    "RAZ",  1,      1,      0,      0},
61101         {"CNT_VAL"                     ,        0,      15,     216,    "R/W",  0,      0,      0ull,   0ull},
61102         {"CNT_ENB"                     ,        15,     1,      216,    "R/W",  0,      0,      0ull,   0ull},
61103         {"RESERVED_16_63"              ,        16,     48,     216,    "RAZ",  1,      1,      0,      0},
61104         {"CNT_VAL"                     ,        0,      15,     217,    "R/W",  0,      0,      0ull,   0ull},
61105         {"CNT_ENB"                     ,        15,     1,      217,    "R/W",  0,      0,      0ull,   0ull},
61106         {"RESERVED_16_63"              ,        16,     48,     217,    "RAZ",  1,      1,      0,      0},
61107         {"PORT"                        ,        0,      6,      218,    "RO",   0,      1,      0ull,   0},
61108         {"RESERVED_6_63"               ,        6,      58,     218,    "RAZ",  1,      1,      0,      0},
61109         {"SKIP_SZ"                     ,        0,      6,      219,    "R/W",  0,      0,      0ull,   0ull},
61110         {"RESERVED_6_63"               ,        6,      58,     219,    "RAZ",  1,      1,      0,      0},
61111         {"BACK"                        ,        0,      4,      220,    "R/W",  0,      0,      0ull,   0ull},
61112         {"RESERVED_4_63"               ,        4,      60,     220,    "RAZ",  1,      1,      0,      0},
61113         {"BACK"                        ,        0,      4,      221,    "R/W",  0,      0,      0ull,   0ull},
61114         {"RESERVED_4_63"               ,        4,      60,     221,    "RAZ",  1,      1,      0,      0},
61115         {"PWP"                         ,        0,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61116         {"IPD_NEW"                     ,        1,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61117         {"IPD_OLD"                     ,        2,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61118         {"PRC_OFF"                     ,        3,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61119         {"PWQ0"                        ,        4,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61120         {"PWQ1"                        ,        5,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61121         {"PBM_WORD"                    ,        6,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61122         {"PBM0"                        ,        7,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61123         {"PBM1"                        ,        8,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61124         {"PBM2"                        ,        9,      1,      222,    "RO",   0,      0,      0ull,   0ull},
61125         {"PBM3"                        ,        10,     1,      222,    "RO",   0,      0,      0ull,   0ull},
61126         {"IPQ_PBE0"                    ,        11,     1,      222,    "RO",   0,      0,      0ull,   0ull},
61127         {"IPQ_PBE1"                    ,        12,     1,      222,    "RO",   0,      0,      0ull,   0ull},
61128         {"PWQ_POW"                     ,        13,     1,      222,    "RO",   0,      0,      0ull,   0ull},
61129         {"PWQ_WP1"                     ,        14,     1,      222,    "RO",   0,      0,      0ull,   0ull},
61130         {"PWQ_WQED"                    ,        15,     1,      222,    "RO",   0,      0,      0ull,   0ull},
61131         {"CSR_NCMD"                    ,        16,     1,      222,    "RO",   0,      0,      0ull,   0ull},
61132         {"CSR_MEM"                     ,        17,     1,      222,    "RO",   0,      0,      0ull,   0ull},
61133         {"RESERVED_18_63"              ,        18,     46,     222,    "RAZ",  1,      1,      0,      0},
61134         {"PRT_ENB"                     ,        0,      40,     223,    "R/W",  0,      0,      0ull,   0ull},
61135         {"RESERVED_40_63"              ,        40,     24,     223,    "RAZ",  1,      1,      0,      0},
61136         {"CLK_CNT"                     ,        0,      64,     224,    "RO",   0,      0,      0ull,   0ull},
61137         {"IPD_EN"                      ,        0,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
61138         {"OPC_MODE"                    ,        1,      2,      225,    "R/W",  0,      0,      0ull,   0ull},
61139         {"PBP_EN"                      ,        3,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
61140         {"WQE_LEND"                    ,        4,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
61141         {"PKT_LEND"                    ,        5,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
61142         {"NADDBUF"                     ,        6,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
61143         {"ADDPKT"                      ,        7,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
61144         {"RESET"                       ,        8,      1,      225,    "R/W",  0,      0,      0ull,   0ull},
61145         {"LEN_M8"                      ,        9,      1,      225,    "R/W",  0,      0,      0ull,   1ull},
61146         {"PKT_OFF"                     ,        10,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
61147         {"IPD_FULL"                    ,        11,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
61148         {"PQ_NABUF"                    ,        12,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
61149         {"PQ_APKT"                     ,        13,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
61150         {"NO_WPTR"                     ,        14,     1,      225,    "R/W",  0,      0,      0ull,   0ull},
61151         {"RESERVED_15_63"              ,        15,     49,     225,    "RAZ",  1,      1,      0,      0},
61152         {"PRC_PAR0"                    ,        0,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61153         {"PRC_PAR1"                    ,        1,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61154         {"PRC_PAR2"                    ,        2,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61155         {"PRC_PAR3"                    ,        3,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61156         {"BP_SUB"                      ,        4,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61157         {"DC_OVR"                      ,        5,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61158         {"CC_OVR"                      ,        6,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61159         {"C_COLL"                      ,        7,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61160         {"D_COLL"                      ,        8,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61161         {"BC_OVR"                      ,        9,      1,      226,    "R/W",  0,      0,      0ull,   0ull},
61162         {"PQ_ADD"                      ,        10,     1,      226,    "R/W",  0,      0,      0ull,   0ull},
61163         {"PQ_SUB"                      ,        11,     1,      226,    "R/W",  0,      0,      0ull,   0ull},
61164         {"RESERVED_12_63"              ,        12,     52,     226,    "RAZ",  1,      1,      0,      0},
61165         {"PRC_PAR0"                    ,        0,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61166         {"PRC_PAR1"                    ,        1,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61167         {"PRC_PAR2"                    ,        2,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61168         {"PRC_PAR3"                    ,        3,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61169         {"BP_SUB"                      ,        4,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61170         {"DC_OVR"                      ,        5,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61171         {"CC_OVR"                      ,        6,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61172         {"C_COLL"                      ,        7,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61173         {"D_COLL"                      ,        8,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61174         {"BC_OVR"                      ,        9,      1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61175         {"PQ_ADD"                      ,        10,     1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61176         {"PQ_SUB"                      ,        11,     1,      227,    "R/W1C",        0,      0,      0ull,   0ull},
61177         {"RESERVED_12_63"              ,        12,     52,     227,    "RAZ",  1,      1,      0,      0},
61178         {"SKIP_SZ"                     ,        0,      6,      228,    "R/W",  0,      0,      0ull,   0ull},
61179         {"RESERVED_6_63"               ,        6,      58,     228,    "RAZ",  1,      1,      0,      0},
61180         {"MB_SIZE"                     ,        0,      12,     229,    "R/W",  0,      0,      32ull,  32ull},
61181         {"RESERVED_12_63"              ,        12,     52,     229,    "RAZ",  1,      1,      0,      0},
61182         {"PTR"                         ,        0,      29,     230,    "RO",   1,      1,      0,      0},
61183         {"RESERVED_29_63"              ,        29,     35,     230,    "RAZ",  1,      1,      0,      0},
61184         {"PAGE_CNT"                    ,        0,      17,     231,    "R/W",  0,      0,      0ull,   0ull},
61185         {"BP_ENB"                      ,        17,     1,      231,    "R/W",  0,      0,      0ull,   0ull},
61186         {"RESERVED_18_63"              ,        18,     46,     231,    "RAZ",  1,      1,      0,      0},
61187         {"PAGE_CNT"                    ,        0,      17,     232,    "R/W",  0,      0,      0ull,   0ull},
61188         {"BP_ENB"                      ,        17,     1,      232,    "R/W",  0,      0,      0ull,   0ull},
61189         {"RESERVED_18_63"              ,        18,     46,     232,    "RAZ",  1,      1,      0,      0},
61190         {"CNT_VAL"                     ,        0,      25,     233,    "RO",   0,      1,      0ull,   0},
61191         {"RESERVED_25_63"              ,        25,     39,     233,    "RAZ",  1,      1,      0,      0},
61192         {"CNT_VAL"                     ,        0,      25,     234,    "RO",   0,      1,      0ull,   0},
61193         {"RESERVED_25_63"              ,        25,     39,     234,    "RAZ",  1,      1,      0,      0},
61194         {"CNT"                         ,        0,      32,     235,    "RO",   0,      1,      0ull,   0},
61195         {"WMARK"                       ,        32,     32,     235,    "R/W",  0,      1,      4294967295ull,  0},
61196         {"INTR"                        ,        0,      64,     236,    "R/W1C",        0,      0,      0ull,   0ull},
61197         {"ENB"                         ,        0,      64,     237,    "R/W",  0,      0,      0ull,   1ull},
61198         {"RADDR"                       ,        0,      3,      238,    "R/W",  0,      0,      0ull,   0ull},
61199         {"CENA"                        ,        3,      1,      238,    "R/W",  0,      0,      1ull,   1ull},
61200         {"PTR"                         ,        4,      29,     238,    "RO",   1,      1,      0,      0},
61201         {"PRADDR"                      ,        33,     3,      238,    "RO",   1,      1,      0,      0},
61202         {"MAX_PKT"                     ,        36,     3,      238,    "RO",   0,      0,      5ull,   5ull},
61203         {"RESERVED_39_63"              ,        39,     25,     238,    "RAZ",  1,      1,      0,      0},
61204         {"RADDR"                       ,        0,      7,      239,    "R/W",  0,      0,      0ull,   0ull},
61205         {"CENA"                        ,        7,      1,      239,    "R/W",  0,      0,      1ull,   1ull},
61206         {"PTR"                         ,        8,      29,     239,    "RO",   1,      1,      0,      0},
61207         {"MAX_PKT"                     ,        37,     7,      239,    "RO",   0,      0,      8ull,   8ull},
61208         {"RESERVED_44_63"              ,        44,     20,     239,    "RAZ",  1,      1,      0,      0},
61209         {"WQE_PCNT"                    ,        0,      7,      240,    "RO",   0,      0,      0ull,   0ull},
61210         {"PKT_PCNT"                    ,        7,      7,      240,    "RO",   0,      0,      0ull,   0ull},
61211         {"PFIF_CNT"                    ,        14,     3,      240,    "RO",   0,      0,      0ull,   0ull},
61212         {"WQEV_CNT"                    ,        17,     1,      240,    "RO",   0,      0,      0ull,   0ull},
61213         {"PKTV_CNT"                    ,        18,     1,      240,    "RO",   0,      0,      0ull,   0ull},
61214         {"RESERVED_19_63"              ,        19,     45,     240,    "RAZ",  1,      1,      0,      0},
61215         {"RADDR"                       ,        0,      8,      241,    "R/W",  0,      0,      0ull,   0ull},
61216         {"CENA"                        ,        8,      1,      241,    "R/W",  0,      0,      1ull,   1ull},
61217         {"PTR"                         ,        9,      29,     241,    "RO",   1,      1,      0,      0},
61218         {"PRADDR"                      ,        38,     8,      241,    "RO",   1,      1,      0,      0},
61219         {"WRADDR"                      ,        46,     8,      241,    "RO",   1,      1,      0,      0},
61220         {"MAX_CNTS"                    ,        54,     7,      241,    "RO",   0,      0,      8ull,   8ull},
61221         {"RESERVED_61_63"              ,        61,     3,      241,    "RAZ",  1,      1,      0,      0},
61222         {"PASS"                        ,        0,      32,     242,    "R/W",  0,      1,      0ull,   0},
61223         {"DROP"                        ,        32,     32,     242,    "R/W",  0,      1,      0ull,   0},
61224         {"Q0_PCNT"                     ,        0,      32,     243,    "RO",   0,      0,      0ull,   0ull},
61225         {"RESERVED_32_63"              ,        32,     32,     243,    "RAZ",  1,      1,      0,      0},
61226         {"PRT_ENB"                     ,        0,      36,     244,    "R/W",  0,      0,      0ull,   0ull},
61227         {"AVG_DLY"                     ,        36,     14,     244,    "R/W",  0,      1,      0ull,   0},
61228         {"PRB_DLY"                     ,        50,     14,     244,    "R/W",  0,      0,      0ull,   0ull},
61229         {"PRT_ENB"                     ,        0,      4,      245,    "R/W",  0,      0,      0ull,   0ull},
61230         {"RESERVED_4_63"               ,        4,      60,     245,    "RAZ",  1,      1,      0,      0},
61231         {"PRB_CON"                     ,        0,      32,     246,    "R/W",  0,      1,      0ull,   0},
61232         {"AVG_CON"                     ,        32,     8,      246,    "R/W",  0,      1,      0ull,   0},
61233         {"NEW_CON"                     ,        40,     8,      246,    "R/W",  0,      1,      0ull,   0},
61234         {"USE_PCNT"                    ,        48,     1,      246,    "R/W",  0,      0,      0ull,   0ull},
61235         {"RESERVED_49_63"              ,        49,     15,     246,    "RAZ",  1,      1,      0,      0},
61236         {"PAGE_CNT"                    ,        0,      25,     247,    "R/W",  1,      0,      0,      0ull},
61237         {"PORT"                        ,        25,     6,      247,    "R/W",  1,      0,      0,      0ull},
61238         {"RESERVED_31_63"              ,        31,     33,     247,    "RAZ",  1,      1,      0,      0},
61239         {"PORT_BIT"                    ,        0,      32,     248,    "R/W",  0,      0,      4294967295ull,  4294967295ull},
61240         {"RESERVED_32_35"              ,        32,     4,      248,    "RAZ",  1,      1,      0,      0},
61241         {"PORT_BIT2"                   ,        36,     4,      248,    "R/W",  0,      0,      15ull,  15ull},
61242         {"RESERVED_40_63"              ,        40,     24,     248,    "RAZ",  1,      1,      0,      0},
61243         {"CNT"                         ,        0,      32,     249,    "R/W",  1,      0,      0,      0ull},
61244         {"PORT_QOS"                    ,        32,     9,      249,    "R/W",  1,      0,      0,      0ull},
61245         {"RESERVED_41_63"              ,        41,     23,     249,    "RAZ",  1,      1,      0,      0},
61246         {"WQE_POOL"                    ,        0,      3,      250,    "R/W",  0,      0,      1ull,   1ull},
61247         {"RESERVED_3_63"               ,        3,      61,     250,    "RAZ",  1,      1,      0,      0},
61248         {"PTR"                         ,        0,      29,     251,    "RO",   1,      1,      0,      0},
61249         {"RESERVED_29_63"              ,        29,     35,     251,    "RAZ",  1,      1,      0,      0},
61250         {"WLB_DAT"                     ,        0,      4,      252,    "RO",   0,      0,      0ull,   0ull},
61251         {"STIN_MSK"                    ,        4,      1,      252,    "RO",   0,      0,      0ull,   0ull},
61252         {"DT"                          ,        5,      1,      252,    "RO",   0,      0,      0ull,   0ull},
61253         {"DTCNT"                       ,        6,      10,     252,    "RO",   0,      0,      0ull,   0ull},
61254         {"RESERVED_16_18"              ,        16,     3,      252,    "RAZ",  0,      0,      0ull,   0ull},
61255         {"WLB_MSK"                     ,        19,     4,      252,    "RO",   0,      0,      0ull,   0ull},
61256         {"DTBNK"                       ,        23,     1,      252,    "RO",   0,      0,      0ull,   0ull},
61257         {"RESERVED_24_63"              ,        24,     40,     252,    "RAZ",  0,      0,      0ull,   0ull},
61258         {"L2T"                         ,        0,      9,      253,    "RO",   0,      0,      0ull,   0ull},
61259         {"VAB_VWCF"                    ,        9,      1,      253,    "RO",   0,      0,      0ull,   0ull},
61260         {"ILC"                         ,        10,     1,      253,    "RO",   0,      0,      0ull,   0ull},
61261         {"RESERVED_11_11"              ,        11,     1,      253,    "RAZ",  0,      0,      0ull,   0ull},
61262         {"VWDF"                        ,        12,     4,      253,    "RO",   0,      0,      0ull,   0ull},
61263         {"PLC0"                        ,        16,     1,      253,    "RO",   0,      0,      0ull,   0ull},
61264         {"PLC1"                        ,        17,     1,      253,    "RO",   0,      0,      0ull,   0ull},
61265         {"PLC2"                        ,        18,     1,      253,    "RO",   0,      0,      0ull,   0ull},
61266         {"RESERVED_19_63"              ,        19,     45,     253,    "RAZ",  0,      0,      0ull,   0ull},
61267         {"XRDDAT"                      ,        0,      1,      254,    "RO",   0,      0,      0ull,   0ull},
61268         {"XRDMSK"                      ,        1,      1,      254,    "RO",   0,      0,      0ull,   0ull},
61269         {"RESERVED_2_2"                ,        2,      1,      254,    "RAZ",  0,      0,      0ull,   0ull},
61270         {"IPCBST"                      ,        3,      1,      254,    "RO",   0,      0,      0ull,   0ull},
61271         {"RESERVED_4_7"                ,        4,      4,      254,    "RAZ",  0,      0,      0ull,   0ull},
61272         {"RMDF"                        ,        8,      4,      254,    "RO",   0,      0,      0ull,   0ull},
61273         {"MRB"                         ,        12,     4,      254,    "RO",   0,      0,      0ull,   0ull},
61274         {"RESERVED_16_63"              ,        16,     48,     254,    "RAZ",  0,      0,      0ull,   0ull},
61275         {"LRF_ARB_MODE"                ,        0,      1,      255,    "R/W",  0,      0,      1ull,   1ull},
61276         {"RFB_ARB_MODE"                ,        1,      1,      255,    "R/W",  0,      0,      1ull,   1ull},
61277         {"RSP_ARB_MODE"                ,        2,      1,      255,    "R/W",  0,      0,      1ull,   1ull},
61278         {"MWF_CRD"                     ,        3,      4,      255,    "R/W",  0,      0,      2ull,   2ull},
61279         {"IDXALIAS"                    ,        7,      1,      255,    "R/W",  0,      0,      0ull,   1ull},
61280         {"FPEN"                        ,        8,      1,      255,    "R/W",  0,      0,      0ull,   0ull},
61281         {"FPEMPTY"                     ,        9,      1,      255,    "R/W",  0,      0,      0ull,   0ull},
61282         {"FPEXP"                       ,        10,     4,      255,    "R/W",  0,      0,      0ull,   0ull},
61283         {"RESERVED_14_17"              ,        14,     4,      255,    "RAZ",  1,      1,      0,      0},
61284         {"LBIST"                       ,        18,     1,      255,    "R/W",  0,      0,      0ull,   0ull},
61285         {"BSTRUN"                      ,        19,     1,      255,    "RO",   0,      0,      0ull,   0ull},
61286         {"RESERVED_20_63"              ,        20,     44,     255,    "RAZ",  1,      1,      0,      0},
61287         {"L2T"                         ,        0,      1,      256,    "R/W",  0,      0,      0ull,   0ull},
61288         {"L2D"                         ,        1,      1,      256,    "R/W",  0,      0,      0ull,   0ull},
61289         {"FINV"                        ,        2,      1,      256,    "R/W",  0,      0,      0ull,   0ull},
61290         {"SET"                         ,        3,      3,      256,    "R/W",  0,      0,      0ull,   0ull},
61291         {"PPNUM"                       ,        6,      2,      256,    "R/W",  0,      0,      0ull,   0ull},
61292         {"RESERVED_8_9"                ,        8,      2,      256,    "RAZ",  0,      0,      0ull,   0ull},
61293         {"LFB_DMP"                     ,        10,     1,      256,    "R/W",  0,      0,      0ull,   0ull},
61294         {"LFB_ENUM"                    ,        11,     3,      256,    "R/W",  0,      0,      0ull,   0ull},
61295         {"RESERVED_14_63"              ,        14,     50,     256,    "RAZ",  0,      0,      0ull,   0ull},
61296         {"DT_TAG"                      ,        0,      29,     257,    "RO",   0,      0,      0ull,   0ull},
61297         {"DT_VLD"                      ,        29,     1,      257,    "RO",   0,      0,      0ull,   0ull},
61298         {"RESERVED_30_30"              ,        30,     1,      257,    "RAZ",  0,      0,      0ull,   0ull},
61299         {"DTENA"                       ,        31,     1,      257,    "R/W",  0,      0,      0ull,   0ull},
61300         {"RESERVED_32_63"              ,        32,     32,     257,    "RAZ",  0,      0,      0ull,   0ull},
61301         {"PLC0RMSK"                    ,        0,      32,     258,    "R/W",  0,      0,      0ull,   0ull},
61302         {"PLC1RMSK"                    ,        32,     32,     258,    "R/W",  0,      0,      0ull,   0ull},
61303         {"PLC2RMSK"                    ,        0,      32,     259,    "R/W",  0,      0,      0ull,   0ull},
61304         {"ILCRMSK"                     ,        32,     32,     259,    "R/W",  0,      0,      0ull,   0ull},
61305         {"OOB1EN"                      ,        0,      1,      260,    "R/W",  0,      0,      0ull,   1ull},
61306         {"OOB2EN"                      ,        1,      1,      260,    "R/W",  0,      0,      0ull,   1ull},
61307         {"OOB3EN"                      ,        2,      1,      260,    "R/W",  0,      0,      0ull,   1ull},
61308         {"L2TSECEN"                    ,        3,      1,      260,    "R/W",  0,      0,      0ull,   1ull},
61309         {"L2TDEDEN"                    ,        4,      1,      260,    "R/W",  0,      0,      0ull,   1ull},
61310         {"L2DSECEN"                    ,        5,      1,      260,    "R/W",  0,      0,      0ull,   1ull},
61311         {"L2DDEDEN"                    ,        6,      1,      260,    "R/W",  0,      0,      0ull,   1ull},
61312         {"LCKENA"                      ,        7,      1,      260,    "R/W",  0,      0,      0ull,   1ull},
61313         {"LCK2ENA"                     ,        8,      1,      260,    "R/W",  0,      0,      0ull,   1ull},
61314         {"RESERVED_9_63"               ,        9,      55,     260,    "RAZ",  0,      0,      0ull,   0ull},
61315         {"OOB1"                        ,        0,      1,      261,    "R/W1C",        0,      0,      0ull,   0ull},
61316         {"OOB2"                        ,        1,      1,      261,    "R/W1C",        0,      0,      0ull,   0ull},
61317         {"OOB3"                        ,        2,      1,      261,    "R/W1C",        0,      0,      0ull,   0ull},
61318         {"L2TSEC"                      ,        3,      1,      261,    "R/W1C",        0,      0,      0ull,   0ull},
61319         {"L2TDED"                      ,        4,      1,      261,    "R/W1C",        0,      0,      0ull,   0ull},
61320         {"L2DSEC"                      ,        5,      1,      261,    "R/W1C",        0,      0,      0ull,   0ull},
61321         {"L2DDED"                      ,        6,      1,      261,    "R/W1C",        0,      0,      0ull,   0ull},
61322         {"LCK"                         ,        7,      1,      261,    "R/W1C",        0,      0,      0ull,   0ull},
61323         {"LCK2"                        ,        8,      1,      261,    "R/W1C",        0,      0,      0ull,   0ull},
61324         {"RESERVED_9_63"               ,        9,      55,     261,    "RAZ",  0,      0,      0ull,   0ull},
61325         {"LCK_ENA"                     ,        0,      1,      262,    "R/W",  0,      0,      0ull,   0ull},
61326         {"RESERVED_1_3"                ,        1,      3,      262,    "RAZ",  0,      0,      0ull,   0ull},
61327         {"LCK_BASE"                    ,        4,      27,     262,    "R/W",  0,      0,      0ull,   0ull},
61328         {"RESERVED_31_63"              ,        31,     33,     262,    "RAZ",  0,      0,      0ull,   0ull},
61329         {"LCK_OFFSET"                  ,        0,      10,     263,    "R/W",  0,      0,      0ull,   0ull},
61330         {"RESERVED_10_63"              ,        10,     54,     263,    "RAZ",  0,      0,      0ull,   0ull},
61331         {"VLD"                         ,        0,      1,      264,    "RO",   0,      0,      0ull,   0ull},
61332         {"CMD"                         ,        1,      4,      264,    "RO",   0,      0,      0ull,   0ull},
61333         {"SID"                         ,        5,      9,      264,    "RO",   0,      0,      0ull,   0ull},
61334         {"VABNUM"                      ,        14,     3,      264,    "RO",   0,      0,      0ull,   0ull},
61335         {"RESERVED_17_17"              ,        17,     1,      264,    "RAZ",  0,      0,      0ull,   0ull},
61336         {"SET"                         ,        18,     3,      264,    "RO",   0,      0,      0ull,   0ull},
61337         {"IHD"                         ,        21,     1,      264,    "RO",   0,      0,      0ull,   0ull},
61338         {"ITL"                         ,        22,     1,      264,    "RO",   0,      0,      0ull,   0ull},
61339         {"INXT"                        ,        23,     3,      264,    "RO",   0,      0,      0ull,   0ull},
61340         {"RESERVED_26_26"              ,        26,     1,      264,    "RAZ",  0,      0,      0ull,   0ull},
61341         {"VAM"                         ,        27,     1,      264,    "RO",   0,      0,      0ull,   0ull},
61342         {"STCFL"                       ,        28,     1,      264,    "RO",   0,      0,      0ull,   0ull},
61343         {"STINV"                       ,        29,     1,      264,    "RO",   0,      0,      0ull,   0ull},
61344         {"STPND"                       ,        30,     1,      264,    "RO",   0,      0,      0ull,   0ull},
61345         {"STCPND"                      ,        31,     1,      264,    "RO",   0,      0,      0ull,   0ull},
61346         {"RESERVED_32_63"              ,        32,     32,     264,    "RAZ",  0,      0,      0ull,   0ull},
61347         {"VLD"                         ,        0,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61348         {"WTPRB"                       ,        1,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61349         {"PRBRTY"                      ,        2,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61350         {"WTMFL"                       ,        3,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61351         {"WTVTM"                       ,        4,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61352         {"WTSTRSC"                     ,        5,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61353         {"WTSTRSP"                     ,        6,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61354         {"WTSTDT"                      ,        7,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61355         {"WTRDA"                       ,        8,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61356         {"WTSTM"                       ,        9,      1,      265,    "RO",   0,      0,      0ull,   0ull},
61357         {"WTWRM"                       ,        10,     1,      265,    "RO",   0,      0,      0ull,   0ull},
61358         {"WTWHF"                       ,        11,     1,      265,    "RO",   0,      0,      0ull,   0ull},
61359         {"WTWHP"                       ,        12,     1,      265,    "RO",   0,      0,      0ull,   0ull},
61360         {"WTDQ"                        ,        13,     1,      265,    "RO",   0,      0,      0ull,   0ull},
61361         {"WTDW"                        ,        14,     1,      265,    "RO",   0,      0,      0ull,   0ull},
61362         {"WTRSP"                       ,        15,     1,      265,    "RO",   0,      0,      0ull,   0ull},
61363         {"BID"                         ,        16,     2,      265,    "RO",   0,      0,      0ull,   0ull},
61364         {"DSGOING"                     ,        18,     1,      265,    "RO",   0,      0,      0ull,   0ull},
61365         {"RESERVED_19_63"              ,        19,     45,     265,    "RAZ",  0,      0,      0ull,   0ull},
61366         {"LFB_IDX"                     ,        0,      9,      266,    "RO",   0,      0,      0ull,   0ull},
61367         {"LFB_TAG"                     ,        9,      18,     266,    "RO",   0,      0,      0ull,   0ull},
61368         {"RESERVED_27_63"              ,        27,     37,     266,    "RAZ",  0,      0,      0ull,   0ull},
61369         {"LFB_HWM"                     ,        0,      3,      267,    "R/W",  0,      0,      7ull,   7ull},
61370         {"RESERVED_3_3"                ,        3,      1,      267,    "RAZ",  0,      0,      0ull,   0ull},
61371         {"STPARTDIS"                   ,        4,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
61372         {"RESERVED_5_63"               ,        5,      59,     267,    "RAZ",  0,      0,      0ull,   0ull},
61373         {"STENA"                       ,        0,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
61374         {"DWBENA"                      ,        1,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
61375         {"RESERVED_2_63"               ,        2,      62,     268,    "RAZ",  0,      0,      0ull,   0ull},
61376         {"SIZE"                        ,        0,      14,     269,    "R/W",  0,      0,      0ull,   0ull},
61377         {"RESERVED_14_19"              ,        14,     6,      269,    "RAZ",  0,      0,      0ull,   0ull},
61378         {"SADR"                        ,        20,     14,     269,    "R/W",  0,      0,      0ull,   0ull},
61379         {"RESERVED_34_35"              ,        34,     2,      269,    "RAZ",  0,      0,      0ull,   0ull},
61380         {"FSRC"                        ,        36,     1,      269,    "RO",   0,      0,      0ull,   0ull},
61381         {"FADR"                        ,        37,     27,     269,    "RO",   0,      0,      0ull,   0ull},
61382         {"SIZE"                        ,        0,      14,     270,    "R/W",  0,      0,      0ull,   0ull},
61383         {"RESERVED_14_19"              ,        14,     6,      270,    "RAZ",  0,      0,      0ull,   0ull},
61384         {"SADR"                        ,        20,     14,     270,    "R/W",  0,      0,      0ull,   0ull},
61385         {"RESERVED_34_35"              ,        34,     2,      270,    "RAZ",  0,      0,      0ull,   0ull},
61386         {"FSRC"                        ,        36,     1,      270,    "RO",   0,      0,      0ull,   0ull},
61387         {"FADR"                        ,        37,     27,     270,    "RO",   0,      0,      0ull,   0ull},
61388         {"SIZE"                        ,        0,      14,     271,    "R/W",  0,      0,      0ull,   0ull},
61389         {"RESERVED_14_19"              ,        14,     6,      271,    "RAZ",  0,      0,      0ull,   0ull},
61390         {"SADR"                        ,        20,     14,     271,    "R/W",  0,      0,      0ull,   0ull},
61391         {"RESERVED_34_35"              ,        34,     2,      271,    "RAZ",  0,      0,      0ull,   0ull},
61392         {"FSRC"                        ,        36,     1,      271,    "RO",   0,      0,      0ull,   0ull},
61393         {"FADR"                        ,        37,     27,     271,    "RO",   0,      0,      0ull,   0ull},
61394         {"PFCNT0"                      ,        0,      36,     272,    "RO",   0,      0,      0ull,   0ull},
61395         {"RESERVED_36_63"              ,        36,     28,     272,    "RAZ",  0,      0,      0ull,   0ull},
61396         {"CNT0SEL"                     ,        0,      6,      273,    "R/W",  0,      0,      0ull,   0ull},
61397         {"CNT0CLR"                     ,        6,      1,      273,    "R/W",  0,      0,      0ull,   0ull},
61398         {"CNT0ENA"                     ,        7,      1,      273,    "R/W",  0,      0,      0ull,   0ull},
61399         {"CNT1SEL"                     ,        8,      6,      273,    "R/W",  0,      0,      0ull,   0ull},
61400         {"CNT1CLR"                     ,        14,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61401         {"CNT1ENA"                     ,        15,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61402         {"CNT2SEL"                     ,        16,     6,      273,    "R/W",  0,      0,      0ull,   0ull},
61403         {"CNT2CLR"                     ,        22,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61404         {"CNT2ENA"                     ,        23,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61405         {"CNT3SEL"                     ,        24,     6,      273,    "R/W",  0,      0,      0ull,   0ull},
61406         {"CNT3CLR"                     ,        30,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61407         {"CNT3ENA"                     ,        31,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61408         {"CNT0RDCLR"                   ,        32,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61409         {"CNT1RDCLR"                   ,        33,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61410         {"CNT2RDCLR"                   ,        34,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61411         {"CNT3RDCLR"                   ,        35,     1,      273,    "R/W",  0,      0,      0ull,   0ull},
61412         {"RESERVED_36_63"              ,        36,     28,     273,    "RAZ",  0,      0,      0ull,   0ull},
61413         {"PP0GRP"                      ,        0,      2,      274,    "R/W",  0,      0,      0ull,   0ull},
61414         {"PP1GRP"                      ,        2,      2,      274,    "R/W",  0,      0,      0ull,   0ull},
61415         {"PP2GRP"                      ,        4,      2,      274,    "R/W",  0,      0,      0ull,   0ull},
61416         {"PP3GRP"                      ,        6,      2,      274,    "R/W",  0,      0,      0ull,   0ull},
61417         {"RESERVED_8_63"               ,        8,      56,     274,    "RAZ",  0,      0,      0ull,   0ull},
61418         {"UMSK0"                       ,        0,      8,      275,    "R/W",  0,      0,      0ull,   0ull},
61419         {"UMSK1"                       ,        8,      8,      275,    "R/W",  0,      0,      0ull,   0ull},
61420         {"UMSK2"                       ,        16,     8,      275,    "R/W",  0,      0,      0ull,   0ull},
61421         {"UMSK3"                       ,        24,     8,      275,    "R/W",  0,      0,      0ull,   0ull},
61422         {"RESERVED_32_63"              ,        32,     32,     275,    "RAZ",  0,      0,      0ull,   0ull},
61423         {"UMSKIOB"                     ,        0,      8,      276,    "R/W",  0,      0,      0ull,   0ull},
61424         {"RESERVED_8_63"               ,        8,      56,     276,    "RAZ",  0,      0,      0ull,   0ull},
61425         {"Q0STAT"                      ,        0,      34,     277,    "RO",   0,      0,      0ull,   0ull},
61426         {"FTL"                         ,        34,     1,      277,    "RO",   0,      0,      0ull,   0ull},
61427         {"RESERVED_35_63"              ,        35,     29,     277,    "RAZ",  0,      0,      0ull,   0ull},
61428         {"Q1STAT"                      ,        0,      34,     278,    "RO",   0,      0,      0ull,   0ull},
61429         {"RESERVED_34_63"              ,        34,     30,     278,    "RAZ",  0,      0,      0ull,   0ull},
61430         {"Q2STAT"                      ,        0,      34,     279,    "RO",   0,      0,      0ull,   0ull},
61431         {"RESERVED_34_63"              ,        34,     30,     279,    "RAZ",  0,      0,      0ull,   0ull},
61432         {"Q3STAT"                      ,        0,      34,     280,    "RO",   0,      0,      0ull,   0ull},
61433         {"RESERVED_34_63"              ,        34,     30,     280,    "RAZ",  0,      0,      0ull,   0ull},
61434         {"ECC_ENA"                     ,        0,      1,      281,    "R/W",  0,      0,      0ull,   1ull},
61435         {"SEC_INTENA"                  ,        1,      1,      281,    "R/W",  0,      0,      0ull,   1ull},
61436         {"DED_INTENA"                  ,        2,      1,      281,    "R/W",  0,      0,      0ull,   1ull},
61437         {"SEC_ERR"                     ,        3,      1,      281,    "R/W1C",        0,      0,      0ull,   0ull},
61438         {"DED_ERR"                     ,        4,      1,      281,    "R/W1C",        0,      0,      0ull,   0ull},
61439         {"BMHCLSEL"                    ,        5,      1,      281,    "R/W",  0,      0,      0ull,   0ull},
61440         {"RESERVED_6_63"               ,        6,      58,     281,    "RAZ",  0,      0,      0ull,   0ull},
61441         {"FADR"                        ,        0,      10,     282,    "RO",   0,      0,      0ull,   0ull},
61442         {"RESERVED_10_10"              ,        10,     1,      282,    "RAZ",  0,      0,      0ull,   0ull},
61443         {"FSET"                        ,        11,     3,      282,    "RO",   0,      0,      0ull,   0ull},
61444         {"FOWMSK"                      ,        14,     4,      282,    "RO",   0,      0,      0ull,   0ull},
61445         {"RESERVED_18_63"              ,        18,     46,     282,    "RAZ",  0,      0,      0ull,   0ull},
61446         {"FSYN_OW0"                    ,        0,      10,     283,    "RO",   0,      0,      0ull,   0ull},
61447         {"FSYN_OW1"                    ,        10,     10,     283,    "RO",   0,      0,      0ull,   0ull},
61448         {"RESERVED_20_63"              ,        20,     44,     283,    "RAZ",  0,      0,      0ull,   0ull},
61449         {"FSYN_OW2"                    ,        0,      10,     284,    "RO",   0,      0,      0ull,   0ull},
61450         {"FSYN_OW3"                    ,        10,     10,     284,    "RO",   0,      0,      0ull,   0ull},
61451         {"RESERVED_20_63"              ,        20,     44,     284,    "RAZ",  0,      0,      0ull,   0ull},
61452         {"Q0FUS"                       ,        0,      34,     285,    "RO",   0,      0,      0ull,   0ull},
61453         {"RESERVED_34_63"              ,        34,     30,     285,    "RAZ",  0,      0,      0ull,   0ull},
61454         {"Q1FUS"                       ,        0,      34,     286,    "RO",   0,      0,      0ull,   0ull},
61455         {"RESERVED_34_63"              ,        34,     30,     286,    "RAZ",  0,      0,      0ull,   0ull},
61456         {"Q2FUS"                       ,        0,      34,     287,    "RO",   0,      0,      0ull,   0ull},
61457         {"RESERVED_34_63"              ,        34,     30,     287,    "RAZ",  0,      0,      0ull,   0ull},
61458         {"Q3FUS"                       ,        0,      34,     288,    "RO",   0,      0,      0ull,   0ull},
61459         {"CRIP_256K"                   ,        34,     1,      288,    "RO",   0,      0,      0ull,   0ull},
61460         {"CRIP_128K"                   ,        35,     1,      288,    "RO",   0,      0,      0ull,   0ull},
61461         {"RESERVED_36_36"              ,        36,     1,      288,    "RAZ",  0,      0,      0ull,   0ull},
61462         {"EMA_CTL"                     ,        37,     3,      288,    "RO",   0,      0,      0ull,   0ull},
61463         {"RESERVED_40_63"              ,        40,     24,     288,    "RAZ",  0,      0,      0ull,   0ull},
61464         {"ECC_ENA"                     ,        0,      1,      289,    "R/W",  0,      0,      0ull,   1ull},
61465         {"SEC_INTENA"                  ,        1,      1,      289,    "R/W",  0,      0,      0ull,   1ull},
61466         {"DED_INTENA"                  ,        2,      1,      289,    "R/W",  0,      0,      0ull,   1ull},
61467         {"SEC_ERR"                     ,        3,      1,      289,    "R/W1C",        0,      0,      0ull,   0ull},
61468         {"DED_ERR"                     ,        4,      1,      289,    "R/W1C",        0,      0,      0ull,   0ull},
61469         {"FSYN"                        ,        5,      6,      289,    "RO",   0,      0,      0ull,   0ull},
61470         {"FADR"                        ,        11,     9,      289,    "RO",   0,      0,      0ull,   0ull},
61471         {"RESERVED_20_20"              ,        20,     1,      289,    "RAZ",  0,      0,      0ull,   0ull},
61472         {"FSET"                        ,        21,     3,      289,    "RO",   0,      0,      0ull,   0ull},
61473         {"LCKERR"                      ,        24,     1,      289,    "R/W1C",        0,      0,      0ull,   0ull},
61474         {"LCK_INTENA"                  ,        25,     1,      289,    "R/W",  0,      0,      0ull,   1ull},
61475         {"LCKERR2"                     ,        26,     1,      289,    "R/W1C",        0,      0,      0ull,   0ull},
61476         {"LCK_INTENA2"                 ,        27,     1,      289,    "R/W",  0,      0,      0ull,   1ull},
61477         {"RESERVED_28_63"              ,        28,     36,     289,    "RAZ",  0,      0,      0ull,   0ull},
61478         {"START"                       ,        0,      1,      290,    "R/W",  0,      0,      0ull,   0ull},
61479         {"RESERVED_1_63"               ,        1,      63,     290,    "RAZ",  1,      0,      0,      0ull},
61480         {"MRD"                         ,        0,      3,      291,    "RO",   1,      0,      0,      0ull},
61481         {"MRF"                         ,        3,      1,      291,    "RO",   1,      0,      0,      0ull},
61482         {"MWC"                         ,        4,      1,      291,    "RO",   1,      0,      0,      0ull},
61483         {"MWD"                         ,        5,      3,      291,    "RO",   1,      0,      0,      0ull},
61484         {"MWF"                         ,        8,      1,      291,    "RO",   1,      0,      0,      0ull},
61485         {"CSRE2D"                      ,        9,      1,      291,    "RO",   1,      0,      0,      0ull},
61486         {"CSRD2E"                      ,        10,     1,      291,    "RO",   1,      0,      0,      0ull},
61487         {"RESERVED_11_63"              ,        11,     53,     291,    "RAZ",  1,      0,      0,      0ull},
61488         {"PCTL_DAT"                    ,        0,      5,      292,    "R/W",  0,      1,      0ull,   0},
61489         {"RESERVED_5_11"               ,        5,      7,      292,    "RAZ",  0,      1,      0ull,   0},
61490         {"PCTL_CSR"                    ,        12,     4,      292,    "R/W",  0,      1,      15ull,  0},
61491         {"NCTL_DAT"                    ,        16,     4,      292,    "R/W",  0,      1,      0ull,   0},
61492         {"RESERVED_20_27"              ,        20,     8,      292,    "RAZ",  0,      1,      0ull,   0},
61493         {"NCTL_CSR"                    ,        28,     4,      292,    "R/W",  0,      1,      15ull,  0},
61494         {"RESERVED_32_63"              ,        32,     32,     292,    "RAZ",  0,      0,      0ull,   0ull},
61495         {"DIC"                         ,        0,      2,      293,    "R/W",  0,      0,      0ull,   0ull},
61496         {"QS_DIC"                      ,        2,      2,      293,    "R/W",  0,      0,      2ull,   2ull},
61497         {"TSKW"                        ,        4,      2,      293,    "R/W",  0,      0,      0ull,   1ull},
61498         {"SIL_LAT"                     ,        6,      2,      293,    "R/W",  0,      0,      1ull,   1ull},
61499         {"BPRCH"                       ,        8,      1,      293,    "R/W",  0,      1,      0ull,   0},
61500         {"FPRCH2"                      ,        9,      1,      293,    "R/W",  0,      0,      0ull,   1ull},
61501         {"MODE32B"                     ,        10,     1,      293,    "R/W",  0,      0,      0ull,   0ull},
61502         {"DRESET"                      ,        11,     1,      293,    "R/W",  0,      0,      0ull,   0ull},
61503         {"INORDER_MRF"                 ,        12,     1,      293,    "R/W",  0,      0,      0ull,   0ull},
61504         {"INORDER_MWF"                 ,        13,     1,      293,    "RAZ",  0,      0,      0ull,   0ull},
61505         {"R2R_SLOT"                    ,        14,     1,      293,    "R/W",  0,      0,      0ull,   0ull},
61506         {"RDIMM_ENA"                   ,        15,     1,      293,    "R/W",  0,      1,      0ull,   0},
61507         {"RESERVED_16_17"              ,        16,     2,      293,    "RAZ",  0,      0,      0ull,   0ull},
61508         {"MAX_WRITE_BATCH"             ,        18,     4,      293,    "R/W",  0,      0,      8ull,   8ull},
61509         {"XOR_BANK"                    ,        22,     1,      293,    "R/W",  0,      0,      0ull,   1ull},
61510         {"SLOW_SCF"                    ,        23,     1,      293,    "R/W",  0,      0,      0ull,   0ull},
61511         {"DDR__PCTL"                   ,        24,     4,      293,    "RO",   1,      1,      0,      0},
61512         {"DDR__NCTL"                   ,        28,     4,      293,    "RO",   1,      1,      0,      0},
61513         {"RESERVED_32_63"              ,        32,     32,     293,    "RAZ",  1,      1,      0,      0},
61514         {"RESERVED_0_7"                ,        0,      8,      294,    "RAZ",  0,      1,      0ull,   0},
61515         {"DCC_ENABLE"                  ,        8,      1,      294,    "R/W",  0,      0,      0ull,   0ull},
61516         {"SIL_MODE"                    ,        9,      1,      294,    "R/W",  0,      0,      0ull,   1ull},
61517         {"SEQUENCE"                    ,        10,     3,      294,    "R/W",  0,      0,      0ull,   0ull},
61518         {"IDLEPOWER"                   ,        13,     3,      294,    "R/W",  0,      0,      0ull,   6ull},
61519         {"FORCEWRITE"                  ,        16,     4,      294,    "R/W",  0,      0,      0ull,   0ull},
61520         {"ECC_ADR"                     ,        20,     1,      294,    "R/W",  0,      0,      0ull,   1ull},
61521         {"RESERVED_21_63"              ,        21,     43,     294,    "RAZ",  1,      1,      0,      0},
61522         {"DCLKCNT_HI"                  ,        0,      32,     295,    "RO",   0,      0,      0ull,   0ull},
61523         {"RESERVED_32_63"              ,        32,     32,     295,    "RAZ",  1,      1,      0,      0},
61524         {"DCLKCNT_LO"                  ,        0,      32,     296,    "RO",   0,      0,      0ull,   0ull},
61525         {"RESERVED_32_63"              ,        32,     32,     296,    "RAZ",  1,      1,      0,      0},
61526         {"DDR2"                        ,        0,      1,      297,    "R/W",  0,      0,      1ull,   1ull},
61527         {"RDQS"                        ,        1,      1,      297,    "R/W",  0,      0,      0ull,   0ull},
61528         {"DLL90_BYP"                   ,        2,      1,      297,    "R/W",  0,      0,      0ull,   0ull},
61529         {"DLL90_VLU"                   ,        3,      5,      297,    "R/W",  0,      1,      0ull,   0},
61530         {"QDLL_ENA"                    ,        8,      1,      297,    "R/W",  0,      0,      0ull,   0ull},
61531         {"ODT_ENA"                     ,        9,      1,      297,    "R/W",  0,      0,      0ull,   0ull},
61532         {"DDR2T"                       ,        10,     1,      297,    "R/W",  0,      1,      0ull,   0},
61533         {"CRIP_MODE"                   ,        11,     1,      297,    "R/W",  0,      0,      0ull,   0ull},
61534         {"TFAW"                        ,        12,     5,      297,    "R/W",  0,      0,      0ull,   9ull},
61535         {"DDR_EOF"                     ,        17,     4,      297,    "R/W",  0,      0,      0ull,   0ull},
61536         {"SILO_HC"                     ,        21,     1,      297,    "R/W",  0,      1,      1ull,   0},
61537         {"TWR"                         ,        22,     3,      297,    "R/W",  0,      0,      3ull,   1ull},
61538         {"BWCNT"                       ,        25,     1,      297,    "R/W",  0,      0,      0ull,   0ull},
61539         {"POCAS"                       ,        26,     1,      297,    "R/W",  0,      0,      0ull,   0ull},
61540         {"ADDLAT"                      ,        27,     3,      297,    "R/W",  0,      0,      0ull,   0ull},
61541         {"BURST8"                      ,        30,     1,      297,    "R/W",  0,      0,      0ull,   1ull},
61542         {"BANK8"                       ,        31,     1,      297,    "R/W",  0,      1,      0ull,   0},
61543         {"RESERVED_32_63"              ,        32,     32,     297,    "RAZ",  0,      0,      0ull,   0ull},
61544         {"CLK"                         ,        0,      4,      298,    "R/W",  0,      0,      0ull,   0ull},
61545         {"RESERVED_4_4"                ,        4,      1,      298,    "RAZ",  0,      0,      0ull,   0ull},
61546         {"CMD"                         ,        5,      4,      298,    "R/W",  0,      0,      0ull,   0ull},
61547         {"RESERVED_9_9"                ,        9,      1,      298,    "RAZ",  0,      0,      0ull,   0ull},
61548         {"DQ"                          ,        10,     4,      298,    "R/W",  0,      0,      0ull,   0ull},
61549         {"RESERVED_14_63"              ,        14,     50,     298,    "RAZ",  0,      0,      0ull,   0ull},
61550         {"DLL90_VLU"                   ,        0,      5,      299,    "R/W",  0,      1,      0ull,   0},
61551         {"DLL90_ENA"                   ,        5,      1,      299,    "R/W",  0,      0,      0ull,   0ull},
61552         {"DLL90_BYP"                   ,        6,      1,      299,    "R/W",  0,      0,      0ull,   0ull},
61553         {"DRESET"                      ,        7,      1,      299,    "R/W",  0,      0,      1ull,   0ull},
61554         {"RESERVED_8_63"               ,        8,      56,     299,    "RAZ",  1,      1,      0,      0},
61555         {"CS_MASK"                     ,        0,      8,      300,    "R/W",  0,      1,      0ull,   0},
61556         {"RESERVED_8_15"               ,        8,      8,      300,    "RAZ",  0,      1,      0ull,   0},
61557         {"ROW_LSB"                     ,        16,     3,      300,    "R/W",  0,      1,      3ull,   0},
61558         {"BANK8"                       ,        19,     1,      300,    "R/W",  0,      1,      0ull,   0},
61559         {"RESERVED_20_63"              ,        20,     44,     300,    "RAZ",  0,      1,      0ull,   0},
61560         {"MRDSYN0"                     ,        0,      8,      301,    "RO",   0,      0,      0ull,   0ull},
61561         {"MRDSYN1"                     ,        8,      8,      301,    "RO",   0,      0,      0ull,   0ull},
61562         {"MRDSYN2"                     ,        16,     8,      301,    "RO",   0,      0,      0ull,   0ull},
61563         {"MRDSYN3"                     ,        24,     8,      301,    "RO",   0,      0,      0ull,   0ull},
61564         {"RESERVED_32_63"              ,        32,     32,     301,    "RAZ",  1,      1,      0,      0},
61565         {"FCOL"                        ,        0,      12,     302,    "RO",   0,      0,      0ull,   0ull},
61566         {"FROW"                        ,        12,     14,     302,    "RO",   0,      0,      0ull,   0ull},
61567         {"FBANK"                       ,        26,     3,      302,    "RO",   0,      0,      0ull,   0ull},
61568         {"FBUNK"                       ,        29,     1,      302,    "RO",   0,      0,      0ull,   0ull},
61569         {"FDIMM"                       ,        30,     2,      302,    "RO",   0,      0,      0ull,   0ull},
61570         {"RESERVED_32_63"              ,        32,     32,     302,    "RAZ",  1,      1,      0,      0},
61571         {"IFBCNT_HI"                   ,        0,      32,     303,    "RO",   0,      0,      0ull,   0ull},
61572         {"RESERVED_32_63"              ,        32,     32,     303,    "RAZ",  1,      1,      0,      0},
61573         {"IFBCNT_LO"                   ,        0,      32,     304,    "RO",   0,      0,      0ull,   0ull},
61574         {"RESERVED_32_63"              ,        32,     32,     304,    "RAZ",  1,      1,      0,      0},
61575         {"INIT_START"                  ,        0,      1,      305,    "WR0",  0,      0,      0ull,   0ull},
61576         {"ECC_ENA"                     ,        1,      1,      305,    "R/W",  0,      0,      0ull,   1ull},
61577         {"ROW_LSB"                     ,        2,      3,      305,    "R/W",  0,      1,      3ull,   0},
61578         {"PBANK_LSB"                   ,        5,      4,      305,    "R/W",  0,      1,      5ull,   0},
61579         {"REF_INT"                     ,        9,      6,      305,    "R/W",  0,      0,      1ull,   2ull},
61580         {"TCL"                         ,        15,     4,      305,    "R/W",  0,      1,      3ull,   0},
61581         {"INTR_SEC_ENA"                ,        19,     1,      305,    "R/W",  0,      0,      0ull,   1ull},
61582         {"INTR_DED_ENA"                ,        20,     1,      305,    "R/W",  0,      0,      0ull,   1ull},
61583         {"SEC_ERR"                     ,        21,     4,      305,    "R/W1C",        0,      0,      0ull,   0ull},
61584         {"DED_ERR"                     ,        25,     4,      305,    "R/W1C",        0,      0,      0ull,   0ull},
61585         {"BUNK_ENA"                    ,        29,     1,      305,    "R/W",  0,      1,      0ull,   0},
61586         {"SILO_QC"                     ,        30,     1,      305,    "R/W",  0,      1,      0ull,   0},
61587         {"RESET"                       ,        31,     1,      305,    "RAZ",  1,      1,      0,      0},
61588         {"RESERVED_32_63"              ,        32,     32,     305,    "RAZ",  1,      1,      0,      0},
61589         {"TRAS"                        ,        0,      5,      306,    "R/W",  0,      0,      12ull,  12ull},
61590         {"TRCD"                        ,        5,      4,      306,    "R/W",  0,      0,      4ull,   4ull},
61591         {"TWTR"                        ,        9,      4,      306,    "R/W",  0,      0,      2ull,   2ull},
61592         {"TRP"                         ,        13,     4,      306,    "R/W",  0,      0,      5ull,   4ull},
61593         {"TRFC"                        ,        17,     5,      306,    "R/W",  0,      0,      6ull,   7ull},
61594         {"TMRD"                        ,        22,     3,      306,    "R/W",  0,      0,      2ull,   2ull},
61595         {"CASLAT"                      ,        25,     3,      306,    "R/W",  0,      0,      4ull,   4ull},
61596         {"TRRD"                        ,        28,     3,      306,    "R/W",  0,      0,      2ull,   2ull},
61597         {"RESERVED_31_63"              ,        31,     33,     306,    "RAZ",  1,      1,      0,      0},
61598         {"OPSCNT_HI"                   ,        0,      32,     307,    "RO",   0,      0,      0ull,   0ull},
61599         {"RESERVED_32_63"              ,        32,     32,     307,    "RAZ",  1,      1,      0,      0},
61600         {"OPSCNT_LO"                   ,        0,      32,     308,    "RO",   0,      0,      0ull,   0ull},
61601         {"RESERVED_32_63"              ,        32,     32,     308,    "RAZ",  1,      1,      0,      0},
61602         {"EN2"                         ,        0,      1,      309,    "R/W",  0,      1,      0ull,   0},
61603         {"EN4"                         ,        1,      1,      309,    "R/W",  0,      1,      0ull,   0},
61604         {"EN6"                         ,        2,      1,      309,    "R/W",  0,      1,      0ull,   0},
61605         {"EN8"                         ,        3,      1,      309,    "R/W",  0,      1,      1ull,   0},
61606         {"EN12"                        ,        4,      1,      309,    "R/W",  0,      1,      0ull,   0},
61607         {"EN16"                        ,        5,      1,      309,    "R/W",  0,      1,      0ull,   0},
61608         {"RESERVED_6_7"                ,        6,      2,      309,    "RAZ",  0,      1,      0ull,   0},
61609         {"CLKR"                        ,        8,      6,      309,    "R/W",  0,      1,      0ull,   0},
61610         {"CLKF"                        ,        14,     12,     309,    "R/W",  0,      1,      31ull,  0},
61611         {"RESET_N"                     ,        26,     1,      309,    "R/W",  0,      0,      0ull,   1ull},
61612         {"DIV_RESET"                   ,        27,     1,      309,    "R/W",  0,      0,      1ull,   0ull},
61613         {"FASTEN_N"                    ,        28,     1,      309,    "R/W",  0,      0,      0ull,   1ull},
61614         {"BYPASS"                      ,        29,     1,      309,    "R/W",  0,      0,      0ull,   0ull},
61615         {"RESERVED_30_63"              ,        30,     34,     309,    "RAZ",  0,      1,      0ull,   0},
61616         {"FBSLIP"                      ,        0,      1,      310,    "R/W1C",        0,      1,      0ull,   0},
61617         {"RFSLIP"                      ,        1,      1,      310,    "R/W1C",        0,      1,      0ull,   0},
61618         {"RESERVED_2_21"               ,        2,      20,     310,    "RAZ",  1,      1,      0,      0},
61619         {"DDR__PCTL"                   ,        22,     5,      310,    "RO",   1,      1,      0,      0},
61620         {"DDR__NCTL"                   ,        27,     5,      310,    "RO",   1,      1,      0,      0},
61621         {"RESERVED_32_63"              ,        32,     32,     310,    "RAZ",  1,      1,      0,      0},
61622         {"BNK"                         ,        0,      3,      311,    "R/W",  0,      0,      0ull,   0ull},
61623         {"RESERVED_3_3"                ,        3,      1,      311,    "RAZ",  0,      0,      0ull,   0ull},
61624         {"COL"                         ,        4,      12,     311,    "R/W",  0,      0,      0ull,   0ull},
61625         {"ROW"                         ,        16,     16,     311,    "R/W",  0,      0,      0ull,   0ull},
61626         {"PATTERN"                     ,        32,     8,      311,    "R/W",  0,      0,      170ull, 170ull},
61627         {"RANKMASK"                    ,        40,     4,      311,    "R/W",  0,      0,      0ull,   0ull},
61628         {"RESERVED_44_63"              ,        44,     20,     311,    "RAZ",  0,      0,      0ull,   0ull},
61629         {"BYTE"                        ,        0,      4,      312,    "R/W",  0,      0,      0ull,   0ull},
61630         {"RESERVED_4_15"               ,        4,      12,     312,    "RAZ",  0,      0,      0ull,   0ull},
61631         {"BITMASK"                     ,        16,     16,     312,    "RO",   0,      0,      0ull,   0ull},
61632         {"RESERVED_32_63"              ,        32,     32,     312,    "RAZ",  0,      0,      0ull,   0ull},
61633         {"BYTE0"                       ,        0,      4,      313,    "R/W",  0,      1,      0ull,   0},
61634         {"BYTE1"                       ,        4,      4,      313,    "R/W",  0,      1,      0ull,   0},
61635         {"BYTE2"                       ,        8,      4,      313,    "R/W",  0,      1,      0ull,   0},
61636         {"BYTE3"                       ,        12,     4,      313,    "R/W",  0,      1,      0ull,   0},
61637         {"BYTE4"                       ,        16,     4,      313,    "R/W",  0,      1,      0ull,   0},
61638         {"BYTE5"                       ,        20,     4,      313,    "R/W",  0,      1,      0ull,   0},
61639         {"BYTE6"                       ,        24,     4,      313,    "R/W",  0,      1,      0ull,   0},
61640         {"BYTE7"                       ,        28,     4,      313,    "R/W",  0,      1,      0ull,   0},
61641         {"BYTE8"                       ,        32,     4,      313,    "R/W",  0,      1,      0ull,   0},
61642         {"STATUS"                      ,        36,     2,      313,    "RO",   0,      1,      0ull,   0},
61643         {"RESERVED_38_63"              ,        38,     26,     313,    "RAZ",  1,      0,      0,      0ull},
61644         {"PCTL"                        ,        0,      5,      314,    "R/W",  0,      1,      0ull,   0},
61645         {"RESERVED_5_7"                ,        5,      3,      314,    "RAZ",  0,      1,      0ull,   0},
61646         {"NCTL"                        ,        8,      4,      314,    "R/W",  0,      1,      0ull,   0},
61647         {"RESERVED_12_15"              ,        12,     4,      314,    "RAZ",  0,      1,      0ull,   0},
61648         {"ENABLE"                      ,        16,     1,      314,    "R/W",  0,      1,      0ull,   0},
61649         {"RESERVED_17_63"              ,        17,     47,     314,    "RAZ",  0,      1,      0ull,   0},
61650         {"RODT_LO0"                    ,        0,      4,      315,    "R/W",  0,      0,      15ull,  0ull},
61651         {"RODT_LO1"                    ,        4,      4,      315,    "R/W",  0,      0,      15ull,  0ull},
61652         {"RODT_LO2"                    ,        8,      4,      315,    "R/W",  0,      0,      15ull,  0ull},
61653         {"RODT_LO3"                    ,        12,     4,      315,    "R/W",  0,      0,      15ull,  0ull},
61654         {"RODT_HI0"                    ,        16,     4,      315,    "R/W",  0,      0,      15ull,  0ull},
61655         {"RODT_HI1"                    ,        20,     4,      315,    "R/W",  0,      0,      15ull,  0ull},
61656         {"RODT_HI2"                    ,        24,     4,      315,    "R/W",  0,      0,      15ull,  0ull},
61657         {"RODT_HI3"                    ,        28,     4,      315,    "R/W",  0,      0,      15ull,  0ull},
61658         {"RESERVED_32_63"              ,        32,     32,     315,    "RAZ",  1,      1,      0,      0},
61659         {"WODT_D0_R0"                  ,        0,      8,      316,    "R/W",  0,      0,      255ull, 255ull},
61660         {"WODT_D0_R1"                  ,        8,      8,      316,    "R/W",  0,      0,      255ull, 255ull},
61661         {"WODT_D1_R0"                  ,        16,     8,      316,    "R/W",  0,      0,      255ull, 255ull},
61662         {"WODT_D1_R1"                  ,        24,     8,      316,    "R/W",  0,      0,      255ull, 255ull},
61663         {"RESERVED_32_63"              ,        32,     32,     316,    "RAZ",  0,      0,      0ull,   0ull},
61664         {"WODT_D2_R0"                  ,        0,      8,      317,    "R/W",  0,      0,      255ull, 255ull},
61665         {"WODT_D2_R1"                  ,        8,      8,      317,    "R/W",  0,      0,      255ull, 255ull},
61666         {"WODT_D3_R0"                  ,        16,     8,      317,    "R/W",  0,      0,      255ull, 255ull},
61667         {"WODT_D3_R1"                  ,        24,     8,      317,    "R/W",  0,      0,      255ull, 255ull},
61668         {"RESERVED_32_63"              ,        32,     32,     317,    "RAZ",  0,      0,      0ull,   0ull},
61669         {"NCBI"                        ,        0,      1,      318,    "RO",   0,      0,      0ull,   0ull},
61670         {"LOC"                         ,        1,      1,      318,    "RO",   0,      0,      0ull,   0ull},
61671         {"DMA"                         ,        2,      1,      318,    "RO",   0,      0,      0ull,   0ull},
61672         {"NCBO_0"                      ,        3,      1,      318,    "RO",   0,      0,      0ull,   0ull},
61673         {"RESERVED_4_63"               ,        4,      60,     318,    "RAZ",  1,      1,      0,      0},
61674         {"NCTL"                        ,        0,      5,      319,    "R/W",  0,      1,      31ull,  0},
61675         {"PCTL"                        ,        5,      5,      319,    "R/W",  0,      1,      31ull,  0},
61676         {"RESERVED_10_63"              ,        10,     54,     319,    "RAZ",  1,      1,      0,      0},
61677         {"ADR"                         ,        0,      36,     320,    "R/W",  0,      1,      0ull,   0},
61678         {"SIZE"                        ,        36,     20,     320,    "R/W",  0,      1,      0ull,   0},
61679         {"ENDIAN"                      ,        56,     1,      320,    "R/W",  0,      1,      0ull,   0},
61680         {"SWAP8"                       ,        57,     1,      320,    "R/W",  0,      1,      0ull,   0},
61681         {"SWAP16"                      ,        58,     1,      320,    "R/W",  0,      1,      0ull,   0},
61682         {"SWAP32"                      ,        59,     1,      320,    "R/W",  0,      1,      0ull,   0},
61683         {"RESERVED_60_60"              ,        60,     1,      320,    "RAZ",  1,      1,      0,      0},
61684         {"CLR"                         ,        61,     1,      320,    "R/W",  0,      1,      0ull,   0},
61685         {"RW"                          ,        62,     1,      320,    "R/W",  0,      1,      0ull,   0},
61686         {"EN"                          ,        63,     1,      320,    "R/W",  0,      1,      0ull,   0},
61687         {"DONE"                        ,        0,      1,      321,    "R/W1C",        0,      1,      0ull,   0},
61688         {"DMARQ"                       ,        1,      1,      321,    "RO",   1,      1,      0,      0},
61689         {"RESERVED_2_63"               ,        2,      62,     321,    "RAZ",  1,      1,      0,      0},
61690         {"DONE"                        ,        0,      1,      322,    "R/W",  0,      1,      0ull,   0},
61691         {"DMARQ"                       ,        1,      1,      322,    "R/W",  0,      1,      0ull,   0},
61692         {"RESERVED_2_63"               ,        2,      62,     322,    "RAZ",  1,      1,      0,      0},
61693         {"DMARQ"                       ,        0,      6,      323,    "R/W",  0,      1,      63ull,  0},
61694         {"DMACK_S"                     ,        6,      6,      323,    "R/W",  0,      1,      63ull,  0},
61695         {"OE_A"                        ,        12,     6,      323,    "R/W",  0,      1,      63ull,  0},
61696         {"OE_N"                        ,        18,     6,      323,    "R/W",  0,      1,      63ull,  0},
61697         {"WE_A"                        ,        24,     6,      323,    "R/W",  0,      1,      63ull,  0},
61698         {"WE_N"                        ,        30,     6,      323,    "R/W",  0,      1,      63ull,  0},
61699         {"DMACK_H"                     ,        36,     6,      323,    "R/W",  0,      1,      63ull,  0},
61700         {"PAUSE"                       ,        42,     6,      323,    "R/W",  0,      1,      63ull,  0},
61701         {"RESERVED_48_54"              ,        48,     7,      323,    "RAZ",  1,      1,      0,      0},
61702         {"WIDTH"                       ,        55,     1,      323,    "R/W",  0,      1,      0ull,   0},
61703         {"DDR"                         ,        56,     1,      323,    "R/W",  0,      1,      0ull,   0},
61704         {"RD_DLY"                      ,        57,     3,      323,    "R/W",  0,      1,      0ull,   0},
61705         {"TIM_MULT"                    ,        60,     2,      323,    "R/W",  0,      1,      0ull,   0},
61706         {"DMARQ_PI"                    ,        62,     1,      323,    "R/W",  0,      1,      0ull,   0},
61707         {"DMACK_PI"                    ,        63,     1,      323,    "R/W",  0,      1,      0ull,   0},
61708         {"ADR_ERR"                     ,        0,      1,      324,    "R/W1C",        0,      0,      0ull,   0ull},
61709         {"WAIT_ERR"                    ,        1,      1,      324,    "R/W1C",        0,      0,      0ull,   0ull},
61710         {"RESERVED_2_63"               ,        2,      62,     324,    "RAZ",  1,      1,      0,      0},
61711         {"ADR_INT"                     ,        0,      1,      325,    "R/W",  0,      1,      0ull,   0},
61712         {"WAIT_INT"                    ,        1,      1,      325,    "R/W",  0,      1,      0ull,   0},
61713         {"RESERVED_2_63"               ,        2,      62,     325,    "RAZ",  1,      1,      0,      0},
61714         {"RESERVED_0_2"                ,        0,      3,      326,    "RAZ",  1,      1,      0,      0},
61715         {"ADR"                         ,        3,      5,      326,    "R/W",  0,      1,      0ull,   0},
61716         {"RESERVED_8_63"               ,        8,      56,     326,    "RAZ",  1,      1,      0,      0},
61717         {"RESERVED_0_2"                ,        0,      3,      327,    "RAZ",  1,      1,      0,      0},
61718         {"BASE"                        ,        3,      25,     327,    "R/W",  0,      1,      0ull,   0},
61719         {"RESERVED_28_30"              ,        28,     3,      327,    "RAZ",  1,      1,      0,      0},
61720         {"EN"                          ,        31,     1,      327,    "R/W",  0,      1,      0ull,   0},
61721         {"RESERVED_32_63"              ,        32,     32,     327,    "RAZ",  1,      1,      0,      0},
61722         {"DATA"                        ,        0,      64,     328,    "R/W",  1,      1,      0,      0},
61723         {"BASE"                        ,        0,      16,     329,    "R/W",  0,      1,      0ull,   0},
61724         {"SIZE"                        ,        16,     12,     329,    "R/W",  0,      1,      0ull,   0},
61725         {"WIDTH"                       ,        28,     1,      329,    "R/W",  0,      1,      0ull,   0},
61726         {"ALE"                         ,        29,     1,      329,    "R/W",  0,      1,      0ull,   0},
61727         {"ORBIT"                       ,        30,     1,      329,    "R/W",  0,      1,      0ull,   0},
61728         {"EN"                          ,        31,     1,      329,    "R/W",  0,      1,      0ull,   0},
61729         {"OE_EXT"                      ,        32,     2,      329,    "R/W",  0,      1,      0ull,   0},
61730         {"WE_EXT"                      ,        34,     2,      329,    "R/W",  0,      1,      0ull,   0},
61731         {"SAM"                         ,        36,     1,      329,    "R/W",  0,      1,      0ull,   0},
61732         {"RD_DLY"                      ,        37,     3,      329,    "R/W",  0,      1,      0ull,   0},
61733         {"TIM_MULT"                    ,        40,     2,      329,    "R/W",  0,      1,      0ull,   0},
61734         {"DMACK"                       ,        42,     2,      329,    "R/W",  0,      1,      0ull,   0},
61735         {"RESERVED_44_63"              ,        44,     20,     329,    "RAZ",  1,      1,      0,      0},
61736         {"ADR"                         ,        0,      6,      330,    "R/W",  0,      1,      63ull,  0},
61737         {"CE"                          ,        6,      6,      330,    "R/W",  0,      1,      63ull,  0},
61738         {"OE"                          ,        12,     6,      330,    "R/W",  0,      1,      63ull,  0},
61739         {"WE"                          ,        18,     6,      330,    "R/W",  0,      1,      63ull,  0},
61740         {"RD_HLD"                      ,        24,     6,      330,    "R/W",  0,      1,      63ull,  0},
61741         {"WR_HLD"                      ,        30,     6,      330,    "R/W",  0,      1,      63ull,  0},
61742         {"PAUSE"                       ,        36,     6,      330,    "R/W",  0,      1,      63ull,  0},
61743         {"WAIT"                        ,        42,     6,      330,    "R/W",  0,      1,      63ull,  0},
61744         {"PAGE"                        ,        48,     6,      330,    "R/W",  0,      1,      63ull,  0},
61745         {"ALE"                         ,        54,     6,      330,    "R/W",  0,      1,      63ull,  0},
61746         {"PAGES"                       ,        60,     2,      330,    "R/W",  0,      1,      0ull,   0},
61747         {"WAITM"                       ,        62,     1,      330,    "R/W",  0,      1,      0ull,   0},
61748         {"PAGEM"                       ,        63,     1,      330,    "R/W",  0,      1,      0ull,   0},
61749         {"FIF_THR"                     ,        0,      6,      331,    "R/W",  0,      0,      26ull,  26ull},
61750         {"RESERVED_6_7"                ,        6,      2,      331,    "RAZ",  1,      1,      0,      0},
61751         {"FIF_CNT"                     ,        8,      6,      331,    "RO",   0,      1,      0ull,   0},
61752         {"RESERVED_14_15"              ,        14,     2,      331,    "RAZ",  1,      1,      0,      0},
61753         {"DMA_THR"                     ,        16,     6,      331,    "R/W",  0,      1,      0ull,   0},
61754         {"RESERVED_22_63"              ,        22,     42,     331,    "RAZ",  1,      1,      0,      0},
61755         {"DAT"                         ,        0,      64,     332,    "R/W",  1,      1,      0,      0},
61756         {"MAN_INFO"                    ,        0,      32,     333,    "RO",   1,      1,      0,      0},
61757         {"RESERVED_32_63"              ,        32,     32,     333,    "RAZ",  1,      1,      0,      0},
61758         {"MAN_INFO"                    ,        0,      32,     334,    "RO",   1,      1,      0,      0},
61759         {"RESERVED_32_63"              ,        32,     32,     334,    "RAZ",  1,      1,      0,      0},
61760         {"PP_DIS"                      ,        0,      4,      335,    "RO",   1,      1,      0,      0},
61761         {"RESERVED_4_15"               ,        4,      12,     335,    "RO",   1,      1,      0,      0},
61762         {"CHIP_ID"                     ,        16,     8,      335,    "RO",   1,      1,      0,      0},
61763         {"BIST_DIS"                    ,        24,     1,      335,    "RO",   1,      1,      0,      0},
61764         {"RST_SHT"                     ,        25,     1,      335,    "RO",   1,      1,      0,      0},
61765         {"NOCRYPTO"                    ,        26,     1,      335,    "RO",   1,      1,      0,      0},
61766         {"NOMUL"                       ,        27,     1,      335,    "RO",   1,      1,      0,      0},
61767         {"NODFA_CP2"                   ,        28,     1,      335,    "RO",   1,      1,      0,      0},
61768         {"NOKASU"                      ,        29,     1,      335,    "RO",   1,      1,      0,      0},
61769         {"RESERVED_30_31"              ,        30,     2,      335,    "RAZ",  1,      1,      0,      0},
61770         {"RAID_EN"                     ,        32,     1,      335,    "RO",   1,      1,      0,      0},
61771         {"FUS318"                      ,        33,     1,      335,    "RO",   1,      1,      0,      0},
61772         {"RESERVED_34_63"              ,        34,     30,     335,    "RAZ",  1,      1,      0,      0},
61773         {"ICACHE"                      ,        0,      24,     336,    "RO",   1,      1,      0,      0},
61774         {"NODFA_DTE"                   ,        24,     1,      336,    "RO",   1,      1,      0,      0},
61775         {"NOZIP"                       ,        25,     1,      336,    "RO",   1,      1,      0,      0},
61776         {"EFUS_IGN"                    ,        26,     1,      336,    "RO",   1,      1,      0,      0},
61777         {"EFUS_LCK"                    ,        27,     1,      336,    "RO",   1,      1,      0,      0},
61778         {"BAR2_EN"                     ,        28,     1,      336,    "RO",   1,      1,      0,      0},
61779         {"ZIP_CRIP"                    ,        29,     2,      336,    "RO",   1,      1,      0,      0},
61780         {"RESERVED_31_63"              ,        31,     33,     336,    "RAZ",  1,      1,      0,      0},
61781         {"EMA"                         ,        0,      3,      337,    "R/W",  1,      0,      0,      0ull},
61782         {"RESERVED_3_3"                ,        3,      1,      337,    "RAZ",  1,      1,      0,      0},
61783         {"EFF_EMA"                     ,        4,      3,      337,    "RO",   1,      0,      0,      0ull},
61784         {"RESERVED_7_63"               ,        7,      57,     337,    "RAZ",  1,      1,      0,      0},
61785         {"PDF"                         ,        0,      64,     338,    "RO",   1,      1,      0,      0},
61786         {"FBSLIP"                      ,        0,      1,      339,    "R/W1C",        0,      1,      0ull,   0},
61787         {"RFSLIP"                      ,        1,      1,      339,    "R/W1C",        0,      1,      0ull,   0},
61788         {"RESERVED_2_63"               ,        2,      62,     339,    "RAZ",  1,      1,      0,      0},
61789         {"PROG"                        ,        0,      1,      340,    "R/W",  1,      1,      0,      0},
61790         {"RESERVED_1_63"               ,        1,      63,     340,    "RAZ",  1,      1,      0,      0},
61791         {"SETUP"                       ,        0,      8,      341,    "R/W",  0,      1,      3ull,   0},
61792         {"SCLK_HI"                     ,        8,      12,     341,    "R/W",  0,      1,      100ull, 0},
61793         {"SCLK_LO"                     ,        20,     4,      341,    "R/W",  0,      1,      2ull,   0},
61794         {"OUT"                         ,        24,     8,      341,    "R/W",  0,      1,      3ull,   0},
61795         {"PROG_PIN"                    ,        32,     1,      341,    "RO",   0,      0,      0ull,   0ull},
61796         {"RESERVED_33_63"              ,        33,     31,     341,    "RAZ",  1,      1,      0,      0},
61797         {"ADDR"                        ,        0,      8,      342,    "R/W",  0,      0,      0ull,   0ull},
61798         {"EFUSE"                       ,        8,      1,      342,    "R/W",  0,      0,      0ull,   0ull},
61799         {"RESERVED_9_11"               ,        9,      3,      342,    "RAZ",  1,      1,      0,      0},
61800         {"PEND"                        ,        12,     1,      342,    "R/W",  0,      0,      0ull,   0ull},
61801         {"RESERVED_13_15"              ,        13,     3,      342,    "RAZ",  1,      1,      0,      0},
61802         {"DAT"                         ,        16,     8,      342,    "RO",   1,      1,      0,      0},
61803         {"RESERVED_24_63"              ,        24,     40,     342,    "RAZ",  1,      1,      0,      0},
61804         {"REPAIR0"                     ,        0,      14,     343,    "RO",   0,      0,      0ull,   0ull},
61805         {"REPAIR1"                     ,        14,     14,     343,    "RO",   0,      0,      0ull,   0ull},
61806         {"REPAIR2"                     ,        28,     14,     343,    "RO",   0,      0,      0ull,   0ull},
61807         {"RESERVED_42_63"              ,        42,     22,     343,    "RAZ",  1,      1,      0,      0},
61808         {"TOO_MANY"                    ,        0,      1,      344,    "RO",   0,      0,      0ull,   0ull},
61809         {"RESERVED_1_63"               ,        1,      63,     344,    "RAZ",  1,      1,      0,      0},
61810         {"ADDR"                        ,        0,      3,      345,    "R/W",  1,      1,      0,      0},
61811         {"RESERVED_3_63"               ,        3,      61,     345,    "RAZ",  1,      1,      0,      0},
61812         {"ST_INT"                      ,        0,      1,      346,    "R/W1C",        0,      1,      0ull,   0},
61813         {"TS_INT"                      ,        1,      1,      346,    "R/W1C",        0,      1,      0ull,   0},
61814         {"CORE_INT"                    ,        2,      1,      346,    "RO",   0,      1,      0ull,   0},
61815         {"RESERVED_3_3"                ,        3,      1,      346,    "RAZ",  1,      1,      0,      0},
61816         {"ST_EN"                       ,        4,      1,      346,    "R/W",  0,      1,      0ull,   0},
61817         {"TS_EN"                       ,        5,      1,      346,    "R/W",  0,      1,      0ull,   0},
61818         {"CORE_EN"                     ,        6,      1,      346,    "R/W",  0,      1,      0ull,   0},
61819         {"RESERVED_7_7"                ,        7,      1,      346,    "RAZ",  1,      1,      0,      0},
61820         {"SDA_OVR"                     ,        8,      1,      346,    "R/W",  0,      1,      0ull,   0},
61821         {"SCL_OVR"                     ,        9,      1,      346,    "R/W",  0,      1,      0ull,   0},
61822         {"SDA"                         ,        10,     1,      346,    "RO",   1,      1,      0,      0},
61823         {"SCL"                         ,        11,     1,      346,    "RO",   1,      1,      0,      0},
61824         {"RESERVED_12_63"              ,        12,     52,     346,    "RAZ",  1,      1,      0,      0},
61825         {"D"                           ,        0,      32,     347,    "R/W",  0,      1,      0ull,   0},
61826         {"EOP_IA"                      ,        32,     3,      347,    "R/W",  0,      1,      0ull,   0},
61827         {"IA"                          ,        35,     5,      347,    "R/W",  0,      1,      0ull,   0},
61828         {"A"                           ,        40,     10,     347,    "R/W",  0,      1,      0ull,   0},
61829         {"SCR"                         ,        50,     2,      347,    "R/W",  0,      1,      0ull,   0},
61830         {"SIZE"                        ,        52,     3,      347,    "R/W",  0,      1,      0ull,   0},
61831         {"SOVR"                        ,        55,     1,      347,    "R/W",  0,      1,      0ull,   0},
61832         {"R"                           ,        56,     1,      347,    "R/W",  0,      1,      0ull,   0},
61833         {"OP"                          ,        57,     4,      347,    "R/W",  0,      1,      0ull,   0},
61834         {"EIA"                         ,        61,     1,      347,    "R/W",  0,      1,      0ull,   0},
61835         {"SLONLY"                      ,        62,     1,      347,    "R/W",  0,      1,      0ull,   0},
61836         {"V"                           ,        63,     1,      347,    "RC/W", 0,      1,      0ull,   0},
61837         {"D"                           ,        0,      32,     348,    "R/W",  0,      1,      0ull,   0},
61838         {"IA"                          ,        32,     8,      348,    "R/W",  0,      1,      0ull,   0},
61839         {"RESERVED_40_63"              ,        40,     24,     348,    "RAZ",  1,      1,      0,      0},
61840         {"D"                           ,        0,      32,     349,    "R/W",  1,      1,      0,      0},
61841         {"RESERVED_32_61"              ,        32,     30,     349,    "RAZ",  1,      1,      0,      0},
61842         {"V"                           ,        62,     2,      349,    "RC/W", 0,      1,      0ull,   0},
61843         {"DLH"                         ,        0,      8,      350,    "R/W",  0,      1,      0ull,   0},
61844         {"RESERVED_8_63"               ,        8,      56,     350,    "RAZ",  1,      1,      0,      0},
61845         {"DLL"                         ,        0,      8,      351,    "R/W",  0,      1,      0ull,   0},
61846         {"RESERVED_8_63"               ,        8,      56,     351,    "RAZ",  1,      1,      0,      0},
61847         {"FAR"                         ,        0,      1,      352,    "R/W",  0,      1,      0ull,   0},
61848         {"RESERVED_1_63"               ,        1,      63,     352,    "RAZ",  1,      1,      0,      0},
61849         {"EN"                          ,        0,      1,      353,    "WO",   0,      1,      0ull,   0},
61850         {"RXFR"                        ,        1,      1,      353,    "WO",   0,      1,      0ull,   0},
61851         {"TXFR"                        ,        2,      1,      353,    "WO",   0,      1,      0ull,   0},
61852         {"RESERVED_3_3"                ,        3,      1,      353,    "RAZ",  0,      1,      0ull,   0},
61853         {"TXTRIG"                      ,        4,      2,      353,    "WO",   0,      1,      0ull,   0},
61854         {"RXTRIG"                      ,        6,      2,      353,    "WO",   0,      1,      0ull,   0},
61855         {"RESERVED_8_63"               ,        8,      56,     353,    "RAZ",  1,      1,      0,      0},
61856         {"HTX"                         ,        0,      1,      354,    "R/W",  0,      1,      0ull,   0},
61857         {"RESERVED_1_63"               ,        1,      63,     354,    "RAZ",  1,      1,      0,      0},
61858         {"ERBFI"                       ,        0,      1,      355,    "R/W",  0,      1,      0ull,   0},
61859         {"ETBEI"                       ,        1,      1,      355,    "R/W",  0,      1,      0ull,   0},
61860         {"ELSI"                        ,        2,      1,      355,    "R/W",  0,      1,      0ull,   0},
61861         {"EDSSI"                       ,        3,      1,      355,    "R/W",  0,      1,      0ull,   0},
61862         {"RESERVED_4_6"                ,        4,      3,      355,    "RAZ",  0,      1,      0ull,   0},
61863         {"PTIME"                       ,        7,      1,      355,    "R/W",  0,      1,      0ull,   0},
61864         {"RESERVED_8_63"               ,        8,      56,     355,    "RAZ",  1,      1,      0,      0},
61865         {"IID"                         ,        0,      4,      356,    "RO",   0,      1,      1ull,   0},
61866         {"RESERVED_4_5"                ,        4,      2,      356,    "RAZ",  0,      1,      0ull,   0},
61867         {"FEN"                         ,        6,      2,      356,    "RO",   0,      1,      0ull,   0},
61868         {"RESERVED_8_63"               ,        8,      56,     356,    "RAZ",  1,      1,      0,      0},
61869         {"CLS"                         ,        0,      2,      357,    "R/W",  0,      1,      0ull,   0},
61870         {"STOP"                        ,        2,      1,      357,    "R/W",  0,      1,      0ull,   0},
61871         {"PEN"                         ,        3,      1,      357,    "R/W",  0,      1,      0ull,   0},
61872         {"EPS"                         ,        4,      1,      357,    "R/W",  0,      1,      0ull,   0},
61873         {"RESERVED_5_5"                ,        5,      1,      357,    "RAZ",  0,      1,      0ull,   0},
61874         {"BRK"                         ,        6,      1,      357,    "R/W",  0,      1,      0ull,   0},
61875         {"DLAB"                        ,        7,      1,      357,    "R/W",  0,      1,      0ull,   0},
61876         {"RESERVED_8_63"               ,        8,      56,     357,    "RAZ",  1,      1,      0,      0},
61877         {"DR"                          ,        0,      1,      358,    "RO",   0,      1,      0ull,   0},
61878         {"OE"                          ,        1,      1,      358,    "RC",   0,      1,      0ull,   0},
61879         {"PE"                          ,        2,      1,      358,    "RC",   0,      1,      0ull,   0},
61880         {"FE"                          ,        3,      1,      358,    "RC",   0,      1,      0ull,   0},
61881         {"BI"                          ,        4,      1,      358,    "RC",   0,      1,      0ull,   0},
61882         {"THRE"                        ,        5,      1,      358,    "RO",   0,      1,      1ull,   0},
61883         {"TEMT"                        ,        6,      1,      358,    "RO",   0,      1,      1ull,   0},
61884         {"FERR"                        ,        7,      1,      358,    "RC",   0,      1,      0ull,   0},
61885         {"RESERVED_8_63"               ,        8,      56,     358,    "RAZ",  1,      1,      0,      0},
61886         {"DTR"                         ,        0,      1,      359,    "R/W",  0,      1,      0ull,   0},
61887         {"RTS"                         ,        1,      1,      359,    "R/W",  0,      1,      0ull,   0},
61888         {"OUT1"                        ,        2,      1,      359,    "R/W",  0,      1,      0ull,   0},
61889         {"OUT2"                        ,        3,      1,      359,    "R/W",  0,      1,      0ull,   0},
61890         {"LOOP"                        ,        4,      1,      359,    "R/W",  0,      1,      0ull,   0},
61891         {"AFCE"                        ,        5,      1,      359,    "R/W",  0,      1,      0ull,   0},
61892         {"RESERVED_6_63"               ,        6,      58,     359,    "RAZ",  0,      1,      0ull,   0},
61893         {"DCTS"                        ,        0,      1,      360,    "RC",   0,      1,      0ull,   0},
61894         {"DDSR"                        ,        1,      1,      360,    "RC",   0,      1,      0ull,   0},
61895         {"TERI"                        ,        2,      1,      360,    "RC",   0,      1,      0ull,   0},
61896         {"DDCD"                        ,        3,      1,      360,    "RC",   0,      1,      0ull,   0},
61897         {"CTS"                         ,        4,      1,      360,    "RO",   1,      1,      0,      0},
61898         {"DSR"                         ,        5,      1,      360,    "RO",   0,      1,      0ull,   0},
61899         {"RI"                          ,        6,      1,      360,    "RO",   0,      1,      0ull,   0},
61900         {"DCD"                         ,        7,      1,      360,    "RO",   0,      1,      0ull,   0},
61901         {"RESERVED_8_63"               ,        8,      56,     360,    "RAZ",  1,      1,      0,      0},
61902         {"RBR"                         ,        0,      8,      361,    "RO",   0,      1,      0ull,   0},
61903         {"RESERVED_8_63"               ,        8,      56,     361,    "RAZ",  1,      1,      0,      0},
61904         {"RFL"                         ,        0,      7,      362,    "RO",   0,      1,      0ull,   0},
61905         {"RESERVED_7_63"               ,        7,      57,     362,    "RAZ",  1,      1,      0,      0},
61906         {"RFWD"                        ,        0,      8,      363,    "WO",   0,      1,      0ull,   0},
61907         {"RFPE"                        ,        8,      1,      363,    "WO",   0,      1,      0ull,   0},
61908         {"RFFE"                        ,        9,      1,      363,    "WO",   0,      1,      0ull,   0},
61909         {"RESERVED_10_63"              ,        10,     54,     363,    "RAZ",  1,      1,      0,      0},
61910         {"SBCR"                        ,        0,      1,      364,    "R/W",  0,      1,      0ull,   0},
61911         {"RESERVED_1_63"               ,        1,      63,     364,    "RAZ",  1,      1,      0,      0},
61912         {"SCR"                         ,        0,      8,      365,    "R/W",  0,      1,      0ull,   0},
61913         {"RESERVED_8_63"               ,        8,      56,     365,    "RAZ",  1,      1,      0,      0},
61914         {"SFE"                         ,        0,      1,      366,    "R/W",  0,      1,      0ull,   0},
61915         {"RESERVED_1_63"               ,        1,      63,     366,    "RAZ",  1,      1,      0,      0},
61916         {"USR"                         ,        0,      1,      367,    "WO",   0,      1,      0ull,   0},
61917         {"SRFR"                        ,        1,      1,      367,    "WO",   0,      1,      0ull,   0},
61918         {"STFR"                        ,        2,      1,      367,    "WO",   0,      1,      0ull,   0},
61919         {"RESERVED_3_63"               ,        3,      61,     367,    "RAZ",  1,      1,      0,      0},
61920         {"SRT"                         ,        0,      2,      368,    "R/W",  0,      1,      0ull,   0},
61921         {"RESERVED_2_63"               ,        2,      62,     368,    "RAZ",  1,      1,      0,      0},
61922         {"SRTS"                        ,        0,      1,      369,    "R/W",  0,      1,      0ull,   0},
61923         {"RESERVED_1_63"               ,        1,      63,     369,    "RAZ",  1,      1,      0,      0},
61924         {"STT"                         ,        0,      2,      370,    "R/W",  0,      1,      0ull,   0},
61925         {"RESERVED_2_63"               ,        2,      62,     370,    "RAZ",  1,      1,      0,      0},
61926         {"TFL"                         ,        0,      7,      371,    "RO",   0,      1,      0ull,   0},
61927         {"RESERVED_7_63"               ,        7,      57,     371,    "RAZ",  1,      1,      0,      0},
61928         {"TFR"                         ,        0,      8,      372,    "RO",   0,      1,      0ull,   0},
61929         {"RESERVED_8_63"               ,        8,      56,     372,    "RAZ",  1,      1,      0,      0},
61930         {"THR"                         ,        0,      8,      373,    "WO",   0,      1,      0ull,   0},
61931         {"RESERVED_8_63"               ,        8,      56,     373,    "RAZ",  1,      1,      0,      0},
61932         {"BUSY"                        ,        0,      1,      374,    "RO",   0,      1,      0ull,   0},
61933         {"TFNF"                        ,        1,      1,      374,    "RO",   0,      1,      1ull,   0},
61934         {"TFE"                         ,        2,      1,      374,    "RO",   0,      1,      1ull,   0},
61935         {"RFNE"                        ,        3,      1,      374,    "RO",   0,      1,      0ull,   0},
61936         {"RFF"                         ,        4,      1,      374,    "RO",   0,      1,      0ull,   0},
61937         {"RESERVED_5_63"               ,        5,      59,     374,    "RAZ",  1,      1,      0,      0},
61938         {"DLH"                         ,        0,      8,      375,    "R/W",  0,      1,      0ull,   0},
61939         {"RESERVED_8_63"               ,        8,      56,     375,    "RAZ",  1,      1,      0,      0},
61940         {"DLL"                         ,        0,      8,      376,    "R/W",  0,      1,      0ull,   0},
61941         {"RESERVED_8_63"               ,        8,      56,     376,    "RAZ",  1,      1,      0,      0},
61942         {"FAR"                         ,        0,      1,      377,    "R/W",  0,      1,      0ull,   0},
61943         {"RESERVED_1_63"               ,        1,      63,     377,    "RAZ",  1,      1,      0,      0},
61944         {"EN"                          ,        0,      1,      378,    "WO",   0,      1,      0ull,   0},
61945         {"RXFR"                        ,        1,      1,      378,    "WO",   0,      1,      0ull,   0},
61946         {"TXFR"                        ,        2,      1,      378,    "WO",   0,      1,      0ull,   0},
61947         {"RESERVED_3_3"                ,        3,      1,      378,    "RAZ",  0,      1,      0ull,   0},
61948         {"TXTRIG"                      ,        4,      2,      378,    "WO",   0,      1,      0ull,   0},
61949         {"RXTRIG"                      ,        6,      2,      378,    "WO",   0,      1,      0ull,   0},
61950         {"RESERVED_8_63"               ,        8,      56,     378,    "RAZ",  1,      1,      0,      0},
61951         {"HTX"                         ,        0,      1,      379,    "R/W",  0,      1,      0ull,   0},
61952         {"RESERVED_1_63"               ,        1,      63,     379,    "RAZ",  1,      1,      0,      0},
61953         {"ERBFI"                       ,        0,      1,      380,    "R/W",  0,      1,      0ull,   0},
61954         {"ETBEI"                       ,        1,      1,      380,    "R/W",  0,      1,      0ull,   0},
61955         {"ELSI"                        ,        2,      1,      380,    "R/W",  0,      1,      0ull,   0},
61956         {"EDSSI"                       ,        3,      1,      380,    "R/W",  0,      1,      0ull,   0},
61957         {"RESERVED_4_6"                ,        4,      3,      380,    "RAZ",  0,      1,      0ull,   0},
61958         {"PTIME"                       ,        7,      1,      380,    "R/W",  0,      1,      0ull,   0},
61959         {"RESERVED_8_63"               ,        8,      56,     380,    "RAZ",  1,      1,      0,      0},
61960         {"IID"                         ,        0,      4,      381,    "RO",   0,      1,      1ull,   0},
61961         {"RESERVED_4_5"                ,        4,      2,      381,    "RAZ",  0,      1,      0ull,   0},
61962         {"FEN"                         ,        6,      2,      381,    "RO",   0,      1,      0ull,   0},
61963         {"RESERVED_8_63"               ,        8,      56,     381,    "RAZ",  1,      1,      0,      0},
61964         {"CLS"                         ,        0,      2,      382,    "R/W",  0,      1,      0ull,   0},
61965         {"STOP"                        ,        2,      1,      382,    "R/W",  0,      1,      0ull,   0},
61966         {"PEN"                         ,        3,      1,      382,    "R/W",  0,      1,      0ull,   0},
61967         {"EPS"                         ,        4,      1,      382,    "R/W",  0,      1,      0ull,   0},
61968         {"RESERVED_5_5"                ,        5,      1,      382,    "RAZ",  0,      1,      0ull,   0},
61969         {"BRK"                         ,        6,      1,      382,    "R/W",  0,      1,      0ull,   0},
61970         {"DLAB"                        ,        7,      1,      382,    "R/W",  0,      1,      0ull,   0},
61971         {"RESERVED_8_63"               ,        8,      56,     382,    "RAZ",  1,      1,      0,      0},
61972         {"DR"                          ,        0,      1,      383,    "RO",   0,      1,      0ull,   0},
61973         {"OE"                          ,        1,      1,      383,    "RC",   0,      1,      0ull,   0},
61974         {"PE"                          ,        2,      1,      383,    "RC",   0,      1,      0ull,   0},
61975         {"FE"                          ,        3,      1,      383,    "RC",   0,      1,      0ull,   0},
61976         {"BI"                          ,        4,      1,      383,    "RC",   0,      1,      0ull,   0},
61977         {"THRE"                        ,        5,      1,      383,    "RO",   0,      1,      1ull,   0},
61978         {"TEMT"                        ,        6,      1,      383,    "RO",   0,      1,      1ull,   0},
61979         {"FERR"                        ,        7,      1,      383,    "RC",   0,      1,      0ull,   0},
61980         {"RESERVED_8_63"               ,        8,      56,     383,    "RAZ",  1,      1,      0,      0},
61981         {"DTR"                         ,        0,      1,      384,    "R/W",  0,      1,      0ull,   0},
61982         {"RTS"                         ,        1,      1,      384,    "R/W",  0,      1,      0ull,   0},
61983         {"OUT1"                        ,        2,      1,      384,    "R/W",  0,      1,      0ull,   0},
61984         {"OUT2"                        ,        3,      1,      384,    "R/W",  0,      1,      0ull,   0},
61985         {"LOOP"                        ,        4,      1,      384,    "R/W",  0,      1,      0ull,   0},
61986         {"AFCE"                        ,        5,      1,      384,    "R/W",  0,      1,      0ull,   0},
61987         {"RESERVED_6_63"               ,        6,      58,     384,    "RAZ",  0,      1,      0ull,   0},
61988         {"DCTS"                        ,        0,      1,      385,    "RC",   0,      1,      0ull,   0},
61989         {"DDSR"                        ,        1,      1,      385,    "RC",   0,      1,      0ull,   0},
61990         {"TERI"                        ,        2,      1,      385,    "RC",   0,      1,      0ull,   0},
61991         {"DDCD"                        ,        3,      1,      385,    "RC",   0,      1,      0ull,   0},
61992         {"CTS"                         ,        4,      1,      385,    "RO",   1,      1,      0,      0},
61993         {"DSR"                         ,        5,      1,      385,    "RO",   0,      1,      0ull,   0},
61994         {"RI"                          ,        6,      1,      385,    "RO",   0,      1,      0ull,   0},
61995         {"DCD"                         ,        7,      1,      385,    "RO",   0,      1,      0ull,   0},
61996         {"RESERVED_8_63"               ,        8,      56,     385,    "RAZ",  1,      1,      0,      0},
61997         {"RBR"                         ,        0,      8,      386,    "RO",   0,      1,      0ull,   0},
61998         {"RESERVED_8_63"               ,        8,      56,     386,    "RAZ",  1,      1,      0,      0},
61999         {"RFL"                         ,        0,      7,      387,    "RO",   0,      1,      0ull,   0},
62000         {"RESERVED_7_63"               ,        7,      57,     387,    "RAZ",  1,      1,      0,      0},
62001         {"RFWD"                        ,        0,      8,      388,    "WO",   0,      1,      0ull,   0},
62002         {"RFPE"                        ,        8,      1,      388,    "WO",   0,      1,      0ull,   0},
62003         {"RFFE"                        ,        9,      1,      388,    "WO",   0,      1,      0ull,   0},
62004         {"RESERVED_10_63"              ,        10,     54,     388,    "RAZ",  1,      1,      0,      0},
62005         {"SBCR"                        ,        0,      1,      389,    "R/W",  0,      1,      0ull,   0},
62006         {"RESERVED_1_63"               ,        1,      63,     389,    "RAZ",  1,      1,      0,      0},
62007         {"SCR"                         ,        0,      8,      390,    "R/W",  0,      1,      0ull,   0},
62008         {"RESERVED_8_63"               ,        8,      56,     390,    "RAZ",  1,      1,      0,      0},
62009         {"SFE"                         ,        0,      1,      391,    "R/W",  0,      1,      0ull,   0},
62010         {"RESERVED_1_63"               ,        1,      63,     391,    "RAZ",  1,      1,      0,      0},
62011         {"USR"                         ,        0,      1,      392,    "WO",   0,      1,      0ull,   0},
62012         {"SRFR"                        ,        1,      1,      392,    "WO",   0,      1,      0ull,   0},
62013         {"STFR"                        ,        2,      1,      392,    "WO",   0,      1,      0ull,   0},
62014         {"RESERVED_3_63"               ,        3,      61,     392,    "RAZ",  1,      1,      0,      0},
62015         {"SRT"                         ,        0,      2,      393,    "R/W",  0,      1,      0ull,   0},
62016         {"RESERVED_2_63"               ,        2,      62,     393,    "RAZ",  1,      1,      0,      0},
62017         {"SRTS"                        ,        0,      1,      394,    "R/W",  0,      1,      0ull,   0},
62018         {"RESERVED_1_63"               ,        1,      63,     394,    "RAZ",  1,      1,      0,      0},
62019         {"STT"                         ,        0,      2,      395,    "R/W",  0,      1,      0ull,   0},
62020         {"RESERVED_2_63"               ,        2,      62,     395,    "RAZ",  1,      1,      0,      0},
62021         {"TFL"                         ,        0,      7,      396,    "RO",   0,      1,      0ull,   0},
62022         {"RESERVED_7_63"               ,        7,      57,     396,    "RAZ",  1,      1,      0,      0},
62023         {"TFR"                         ,        0,      8,      397,    "RO",   0,      1,      0ull,   0},
62024         {"RESERVED_8_63"               ,        8,      56,     397,    "RAZ",  1,      1,      0,      0},
62025         {"THR"                         ,        0,      8,      398,    "WO",   0,      1,      0ull,   0},
62026         {"RESERVED_8_63"               ,        8,      56,     398,    "RAZ",  1,      1,      0,      0},
62027         {"BUSY"                        ,        0,      1,      399,    "RO",   0,      1,      0ull,   0},
62028         {"TFNF"                        ,        1,      1,      399,    "RO",   0,      1,      1ull,   0},
62029         {"TFE"                         ,        2,      1,      399,    "RO",   0,      1,      1ull,   0},
62030         {"RFNE"                        ,        3,      1,      399,    "RO",   0,      1,      0ull,   0},
62031         {"RFF"                         ,        4,      1,      399,    "RO",   0,      1,      0ull,   0},
62032         {"RESERVED_5_63"               ,        5,      59,     399,    "RAZ",  1,      1,      0,      0},
62033         {"ORFDAT"                      ,        0,      1,      400,    "RO",   0,      0,      0ull,   0ull},
62034         {"IRFDAT"                      ,        1,      1,      400,    "RO",   0,      0,      0ull,   0ull},
62035         {"IPFDAT"                      ,        2,      1,      400,    "RO",   0,      0,      0ull,   0ull},
62036         {"MRQDAT"                      ,        3,      1,      400,    "RO",   0,      0,      0ull,   0ull},
62037         {"RESERVED_4_63"               ,        4,      60,     400,    "RAZ",  0,      0,      0ull,   0ull},
62038         {"MRQ_HWM"                     ,        0,      2,      401,    "R/W",  0,      0,      1ull,   1ull},
62039         {"NBTARB"                      ,        2,      1,      401,    "R/W",  0,      0,      0ull,   0ull},
62040         {"LENDIAN"                     ,        3,      1,      401,    "R/W",  0,      0,      0ull,   0ull},
62041         {"RESET"                       ,        4,      1,      401,    "R/W",  0,      0,      1ull,   0ull},
62042         {"EN"                          ,        5,      1,      401,    "R/W",  0,      0,      0ull,   0ull},
62043         {"BUSY"                        ,        6,      1,      401,    "RO",   0,      0,      0ull,   0ull},
62044         {"CRC_STRIP"                   ,        7,      1,      401,    "R/W",  0,      0,      0ull,   0ull},
62045         {"RESERVED_8_63"               ,        8,      56,     401,    "RAZ",  1,      1,      0,      0},
62046         {"OVFENA"                      ,        0,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
62047         {"IVFENA"                      ,        1,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
62048         {"OTHENA"                      ,        2,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
62049         {"ITHENA"                      ,        3,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
62050         {"DATA_DRPENA"                 ,        4,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
62051         {"IRUNENA"                     ,        5,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
62052         {"ORUNENA"                     ,        6,      1,      402,    "R/W",  0,      0,      0ull,   0ull},
62053         {"RESERVED_7_63"               ,        7,      57,     402,    "RAZ",  1,      1,      0,      0},
62054         {"IRCNT"                       ,        0,      20,     403,    "R/W",  0,      0,      0ull,   0ull},
62055         {"RESERVED_20_63"              ,        20,     44,     403,    "RAZ",  1,      1,      0,      0},
62056         {"IRHWM"                       ,        0,      20,     404,    "R/W",  0,      0,      0ull,   0ull},
62057         {"IBPLWM"                      ,        20,     20,     404,    "R/W",  0,      0,      0ull,   0ull},
62058         {"RESERVED_40_63"              ,        40,     24,     404,    "RAZ",  1,      1,      0,      0},
62059         {"RESERVED_0_2"                ,        0,      3,      405,    "RAZ",  1,      1,      0,      0},
62060         {"IBASE"                       ,        3,      33,     405,    "R/W",  0,      1,      0ull,   0},
62061         {"RESERVED_36_39"              ,        36,     4,      405,    "RAZ",  1,      1,      0,      0},
62062         {"ISIZE"                       ,        40,     20,     405,    "R/W",  0,      1,      0ull,   0},
62063         {"RESERVED_60_63"              ,        60,     4,      405,    "RAZ",  1,      1,      0,      0},
62064         {"IDBELL"                      ,        0,      20,     406,    "R/W",  0,      1,      0ull,   0},
62065         {"RESERVED_20_31"              ,        20,     12,     406,    "RAZ",  1,      1,      0,      0},
62066         {"ITLPTR"                      ,        32,     20,     406,    "RO",   0,      1,      0ull,   0},
62067         {"RESERVED_52_63"              ,        52,     12,     406,    "RAZ",  1,      1,      0,      0},
62068         {"ODBLOVF"                     ,        0,      1,      407,    "R/W1C",        0,      0,      0ull,   0ull},
62069         {"IDBLOVF"                     ,        1,      1,      407,    "R/W1C",        0,      0,      0ull,   0ull},
62070         {"ORTHRESH"                    ,        2,      1,      407,    "RO",   0,      0,      0ull,   0ull},
62071         {"IRTHRESH"                    ,        3,      1,      407,    "RO",   0,      0,      0ull,   0ull},
62072         {"DATA_DRP"                    ,        4,      1,      407,    "R/W1C",        0,      0,      0ull,   0ull},
62073         {"IRUN"                        ,        5,      1,      407,    "R/W1C",        0,      0,      0ull,   0ull},
62074         {"ORUN"                        ,        6,      1,      407,    "R/W1C",        0,      0,      0ull,   0ull},
62075         {"RESERVED_7_63"               ,        7,      57,     407,    "RAZ",  1,      1,      0,      0},
62076         {"ORCNT"                       ,        0,      20,     408,    "R/W",  0,      0,      0ull,   0ull},
62077         {"RESERVED_20_63"              ,        20,     44,     408,    "RAZ",  1,      1,      0,      0},
62078         {"ORHWM"                       ,        0,      20,     409,    "R/W",  0,      0,      0ull,   0ull},
62079         {"RESERVED_20_63"              ,        20,     44,     409,    "RAZ",  1,      1,      0,      0},
62080         {"RESERVED_0_2"                ,        0,      3,      410,    "RAZ",  1,      1,      0,      0},
62081         {"OBASE"                       ,        3,      33,     410,    "R/W",  0,      1,      0ull,   0},
62082         {"RESERVED_36_39"              ,        36,     4,      410,    "RAZ",  1,      1,      0,      0},
62083         {"OSIZE"                       ,        40,     20,     410,    "R/W",  0,      1,      0ull,   0},
62084         {"RESERVED_60_63"              ,        60,     4,      410,    "RAZ",  1,      1,      0,      0},
62085         {"ODBELL"                      ,        0,      20,     411,    "R/W",  0,      1,      0ull,   0},
62086         {"RESERVED_20_31"              ,        20,     12,     411,    "RAZ",  1,      1,      0,      0},
62087         {"OTLPTR"                      ,        32,     20,     411,    "RO",   0,      1,      0ull,   0},
62088         {"RESERVED_52_63"              ,        52,     12,     411,    "RAZ",  1,      1,      0,      0},
62089         {"OREMCNT"                     ,        0,      20,     412,    "RO",   0,      0,      0ull,   0ull},
62090         {"RESERVED_20_31"              ,        20,     12,     412,    "RAZ",  1,      1,      0,      0},
62091         {"IREMCNT"                     ,        32,     20,     412,    "RO",   0,      0,      0ull,   0ull},
62092         {"RESERVED_52_63"              ,        52,     12,     412,    "RAZ",  1,      1,      0,      0},
62093         {"ADDR_V"                      ,        0,      1,      413,    "R/W",  0,      1,      0ull,   0},
62094         {"END_SWP"                     ,        1,      2,      413,    "R/W",  0,      1,      0ull,   0},
62095         {"CA"                          ,        3,      1,      413,    "R/W",  0,      0,      0ull,   0ull},
62096         {"ADDR_IDX"                    ,        4,      14,     413,    "R/W",  0,      1,      0ull,   0},
62097         {"RESERVED_18_31"              ,        18,     14,     413,    "RAZ",  1,      1,      0,      0},
62098         {"NCB_CMD"                     ,        0,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62099         {"MSI"                         ,        1,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62100         {"DR3_MEM"                     ,        2,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62101         {"DIF3"                        ,        3,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62102         {"DIF2"                        ,        4,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62103         {"DIF1"                        ,        5,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62104         {"DIF0"                        ,        6,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62105         {"CSM1"                        ,        7,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62106         {"CSM0"                        ,        8,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62107         {"P2N1_P1"                     ,        9,      1,      414,    "RO",   0,      0,      0ull,   0ull},
62108         {"P2N1_P0"                     ,        10,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62109         {"P2N1_N"                      ,        11,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62110         {"P2N1_C1"                     ,        12,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62111         {"P2N1_C0"                     ,        13,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62112         {"P2N0_P1"                     ,        14,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62113         {"P2N0_P0"                     ,        15,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62114         {"P2N0_N"                      ,        16,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62115         {"P2N0_C1"                     ,        17,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62116         {"P2N0_C0"                     ,        18,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62117         {"P2N0_CO"                     ,        19,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62118         {"P2N0_NO"                     ,        20,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62119         {"P2N0_PO"                     ,        21,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62120         {"P2N1_CO"                     ,        22,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62121         {"P2N1_NO"                     ,        23,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62122         {"P2N1_PO"                     ,        24,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62123         {"CPL_P1"                      ,        25,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62124         {"CPL_P0"                      ,        26,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62125         {"N2P1_O"                      ,        27,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62126         {"N2P1_C"                      ,        28,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62127         {"N2P0_O"                      ,        29,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62128         {"N2P0_C"                      ,        30,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62129         {"DR2_MEM"                     ,        31,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62130         {"D3_PST"                      ,        32,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62131         {"D2_PST"                      ,        33,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62132         {"D1_PST"                      ,        34,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62133         {"D0_PST"                      ,        35,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62134         {"DR1_MEM"                     ,        36,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62135         {"D3_MEM"                      ,        37,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62136         {"D2_MEM"                      ,        38,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62137         {"D1_MEM"                      ,        39,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62138         {"D0_MEM"                      ,        40,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62139         {"DR0_MEM"                     ,        41,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62140         {"D3_MEM3"                     ,        42,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62141         {"D2_MEM2"                     ,        43,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62142         {"D1_MEM1"                     ,        44,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62143         {"D0_MEM0"                     ,        45,     1,      414,    "RO",   0,      0,      0ull,   0ull},
62144         {"RESERVED_46_63"              ,        46,     18,     414,    "RAZ",  1,      1,      0,      0},
62145         {"WAIT_COM"                    ,        0,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
62146         {"BAR2_CAX"                    ,        1,      1,      415,    "R/W",  0,      0,      0ull,   0ull},
62147         {"BAR2_ESX"                    ,        2,      2,      415,    "R/W",  0,      1,      0ull,   0},
62148         {"BAR2_ENB"                    ,        4,      1,      415,    "R/W",  0,      0,      0ull,   1ull},
62149         {"PTLP_RO"                     ,        5,      1,      415,    "R/W",  0,      0,      0ull,   1ull},
62150         {"RESERVED_6_6"                ,        6,      1,      415,    "RAZ",  0,      0,      0ull,   0ull},
62151         {"CTLP_RO"                     ,        7,      1,      415,    "R/W",  0,      0,      0ull,   1ull},
62152         {"INTA_MAP"                    ,        8,      2,      415,    "R/W",  0,      0,      0ull,   0ull},
62153         {"INTB_MAP"                    ,        10,     2,      415,    "R/W",  0,      0,      1ull,   1ull},
62154         {"INTC_MAP"                    ,        12,     2,      415,    "R/W",  0,      0,      2ull,   2ull},
62155         {"INTD_MAP"                    ,        14,     2,      415,    "R/W",  0,      0,      3ull,   3ull},
62156         {"INTA"                        ,        16,     1,      415,    "RO",   0,      0,      1ull,   1ull},
62157         {"INTB"                        ,        17,     1,      415,    "RO",   0,      0,      1ull,   1ull},
62158         {"INTC"                        ,        18,     1,      415,    "RO",   0,      0,      1ull,   1ull},
62159         {"INTD"                        ,        19,     1,      415,    "RO",   0,      0,      1ull,   1ull},
62160         {"WAITL_COM"                   ,        20,     1,      415,    "R/W",  0,      1,      0ull,   0},
62161         {"RESERVED_21_63"              ,        21,     43,     415,    "RAZ",  1,      1,      0,      0},
62162         {"WAIT_COM"                    ,        0,      1,      416,    "R/W",  0,      0,      0ull,   0ull},
62163         {"BAR2_CAX"                    ,        1,      1,      416,    "R/W",  0,      0,      0ull,   0ull},
62164         {"BAR2_ESX"                    ,        2,      2,      416,    "R/W",  0,      1,      0ull,   0},
62165         {"BAR2_ENB"                    ,        4,      1,      416,    "R/W",  0,      0,      0ull,   1ull},
62166         {"PTLP_RO"                     ,        5,      1,      416,    "R/W",  0,      0,      0ull,   1ull},
62167         {"RESERVED_6_6"                ,        6,      1,      416,    "RAZ",  0,      0,      0ull,   0ull},
62168         {"CTLP_RO"                     ,        7,      1,      416,    "R/W",  0,      0,      0ull,   1ull},
62169         {"INTA_MAP"                    ,        8,      2,      416,    "R/W",  0,      0,      0ull,   0ull},
62170         {"INTB_MAP"                    ,        10,     2,      416,    "R/W",  0,      0,      1ull,   1ull},
62171         {"INTC_MAP"                    ,        12,     2,      416,    "R/W",  0,      0,      2ull,   2ull},
62172         {"INTD_MAP"                    ,        14,     2,      416,    "R/W",  0,      0,      3ull,   3ull},
62173         {"INTA"                        ,        16,     1,      416,    "RO",   0,      0,      1ull,   1ull},
62174         {"INTB"                        ,        17,     1,      416,    "RO",   0,      0,      1ull,   1ull},
62175         {"INTC"                        ,        18,     1,      416,    "RO",   0,      0,      1ull,   1ull},
62176         {"INTD"                        ,        19,     1,      416,    "RO",   0,      0,      1ull,   1ull},
62177         {"WAITL_COM"                   ,        20,     1,      416,    "R/W",  0,      1,      0ull,   0},
62178         {"RESERVED_21_63"              ,        21,     43,     416,    "RAZ",  1,      1,      0,      0},
62179         {"CHIP_REV"                    ,        0,      8,      417,    "RO",   1,      1,      0,      0},
62180         {"HOST_MODE"                   ,        8,      1,      417,    "RO",   1,      1,      0,      0},
62181         {"RESERVED_9_12"               ,        9,      4,      417,    "RAZ",  0,      0,      0ull,   0ull},
62182         {"ARB"                         ,        13,     1,      417,    "R/W",  0,      0,      0ull,   1ull},
62183         {"LNK_RST"                     ,        14,     1,      417,    "R/W1C",        0,      0,      0ull,   0ull},
62184         {"RESERVED_15_15"              ,        15,     1,      417,    "RAZ",  0,      0,      0ull,   0ull},
62185         {"CFG_RTRY"                    ,        16,     16,     417,    "R/W",  0,      0,      0ull,   0ull},
62186         {"P0_NTAGS"                    ,        32,     6,      417,    "R/W",  0,      0,      32ull,  32ull},
62187         {"P1_NTAGS"                    ,        38,     6,      417,    "R/W",  0,      0,      32ull,  32ull},
62188         {"RESERVED_44_63"              ,        44,     20,     417,    "RAZ",  1,      1,      0,      0},
62189         {"C0_B0_D"                     ,        0,      1,      418,    "R/W",  0,      0,      0ull,   0ull},
62190         {"C0_WI_D"                     ,        1,      1,      418,    "R/W",  0,      0,      0ull,   0ull},
62191         {"C1_B0_D"                     ,        2,      1,      418,    "R/W",  0,      0,      0ull,   0ull},
62192         {"C1_WI_D"                     ,        3,      1,      418,    "R/W",  0,      0,      0ull,   0ull},
62193         {"C0_B1_S"                     ,        4,      3,      418,    "R/W",  0,      0,      1ull,   1ull},
62194         {"C1_B1_S"                     ,        7,      3,      418,    "R/W",  0,      0,      1ull,   1ull},
62195         {"C0_W_FLT"                    ,        10,     1,      418,    "R/W",  0,      0,      0ull,   0ull},
62196         {"C1_W_FLT"                    ,        11,     1,      418,    "R/W",  0,      0,      0ull,   0ull},
62197         {"MRRS"                        ,        12,     3,      418,    "R/W",  0,      0,      2ull,   2ull},
62198         {"MPS"                         ,        15,     1,      418,    "R/W",  0,      0,      0ull,   0ull},
62199         {"RESERVED_16_63"              ,        16,     48,     418,    "RAZ",  1,      1,      0,      0},
62200         {"P0_FCNT"                     ,        0,      6,      419,    "RO",   0,      1,      0ull,   0},
62201         {"P0_UCNT"                     ,        6,      16,     419,    "RO",   0,      1,      0ull,   0},
62202         {"P1_FCNT"                     ,        22,     6,      419,    "RO",   0,      1,      0ull,   0},
62203         {"P1_UCNT"                     ,        28,     16,     419,    "RO",   0,      1,      0ull,   0},
62204         {"RESERVED_44_63"              ,        44,     20,     419,    "RAZ",  1,      1,      0,      0},
62205         {"DATA"                        ,        0,      17,     420,    "RO",   0,      1,      0ull,   0},
62206         {"DSEL_EXT"                    ,        17,     1,      420,    "R/W",  0,      0,      1ull,   0ull},
62207         {"C_MUL"                       ,        18,     5,      420,    "RO",   1,      1,      0,      0},
62208         {"QLM1_SPD"                    ,        23,     2,      420,    "RO",   1,      1,      0,      0},
62209         {"QLM1_MODE"                   ,        25,     2,      420,    "RO",   1,      1,      0,      0},
62210         {"QLM0_REV_LANES"              ,        27,     1,      420,    "RO",   1,      1,      0,      0},
62211         {"QLM0_LINK_WIDTH"             ,        28,     1,      420,    "RO",   1,      1,      0,      0},
62212         {"RESERVED_29_63"              ,        29,     35,     420,    "RAZ",  1,      1,      0,      0},
62213         {"DBG_SEL"                     ,        0,      16,     421,    "R/W",  0,      1,      0ull,   0},
62214         {"RESERVED_16_63"              ,        16,     48,     421,    "RAZ",  1,      1,      0,      0},
62215         {"DBELL"                       ,        0,      32,     422,    "RO",   0,      0,      0ull,   0ull},
62216         {"FCNT"                        ,        32,     7,      422,    "RO",   0,      0,      0ull,   0ull},
62217         {"RESERVED_39_63"              ,        39,     25,     422,    "RAZ",  1,      1,      0,      0},
62218         {"DBELL"                       ,        0,      16,     423,    "R/W",  0,      1,      0ull,   0},
62219         {"RESERVED_16_31"              ,        16,     16,     423,    "RAZ",  1,      1,      0,      0},
62220         {"RESERVED_0_6"                ,        0,      7,      424,    "RAZ",  1,      1,      0,      0},
62221         {"SADDR"                       ,        7,      29,     424,    "R/W",  0,      1,      0ull,   0},
62222         {"RESERVED_36_63"              ,        36,     28,     424,    "RAZ",  1,      1,      0,      0},
62223         {"ADDR"                        ,        0,      36,     425,    "RO",   0,      1,      0ull,   0},
62224         {"RESERVED_36_63"              ,        36,     28,     425,    "RAZ",  1,      1,      0,      0},
62225         {"CNT"                         ,        0,      32,     426,    "R/W",  0,      1,      0ull,   0},
62226         {"TIME"                        ,        32,     32,     426,    "R/W",  0,      1,      0ull,   0},
62227         {"CNT"                         ,        0,      32,     427,    "R/W",  0,      1,      0ull,   0},
62228         {"TIME"                        ,        32,     32,     427,    "R/W",  0,      1,      0ull,   0},
62229         {"DMA0"                        ,        0,      32,     428,    "R/W",  0,      1,      0ull,   0},
62230         {"DMA1"                        ,        32,     32,     428,    "R/W",  0,      1,      0ull,   0},
62231         {"CSIZE"                       ,        0,      14,     429,    "R/W",  0,      1,      0ull,   0},
62232         {"O_MODE"                      ,        14,     1,      429,    "R/W",  0,      0,      0ull,   1ull},
62233         {"O_ES"                        ,        15,     2,      429,    "R/W",  0,      1,      0ull,   0},
62234         {"O_NS"                        ,        17,     1,      429,    "R/W",  0,      1,      0ull,   0},
62235         {"O_RO"                        ,        18,     1,      429,    "R/W",  0,      1,      0ull,   0},
62236         {"O_ADD1"                      ,        19,     1,      429,    "R/W",  0,      0,      0ull,   1ull},
62237         {"FPA_QUE"                     ,        20,     3,      429,    "R/W",  0,      1,      0ull,   0},
62238         {"DWB_ICHK"                    ,        23,     9,      429,    "R/W",  0,      1,      0ull,   0},
62239         {"DWB_DENB"                    ,        32,     1,      429,    "R/W",  0,      0,      0ull,   1ull},
62240         {"B0_LEND"                     ,        33,     1,      429,    "R/W",  0,      0,      0ull,   0ull},
62241         {"DMA0_ENB"                    ,        34,     1,      429,    "R/W",  0,      0,      0ull,   1ull},
62242         {"DMA1_ENB"                    ,        35,     1,      429,    "R/W",  0,      0,      0ull,   1ull},
62243         {"DMA2_ENB"                    ,        36,     1,      429,    "R/W",  0,      0,      0ull,   1ull},
62244         {"DMA3_ENB"                    ,        37,     1,      429,    "R/W",  0,      0,      0ull,   1ull},
62245         {"RESERVED_38_63"              ,        38,     26,     429,    "RAZ",  1,      1,      0,      0},
62246         {"RESERVED_0_4"                ,        0,      5,      430,    "RAZ",  0,      0,      0ull,   0ull},
62247         {"D3_REQST"                    ,        5,      5,      430,    "RO",   0,      1,      0ull,   0},
62248         {"D2_REQST"                    ,        10,     5,      430,    "RO",   0,      1,      0ull,   0},
62249         {"D1_REQST"                    ,        15,     5,      430,    "RO",   0,      1,      0ull,   0},
62250         {"D0_REQST"                    ,        20,     5,      430,    "RO",   0,      1,      0ull,   0},
62251         {"RESERVED_25_31"              ,        25,     7,      430,    "RAZ",  0,      0,      0ull,   0ull},
62252         {"D3_DIFST"                    ,        32,     7,      430,    "RO",   0,      1,      0ull,   0},
62253         {"D2_DIFST"                    ,        39,     7,      430,    "RO",   0,      1,      0ull,   0},
62254         {"D1_DIFST"                    ,        46,     7,      430,    "RO",   0,      1,      0ull,   0},
62255         {"D0_DIFST"                    ,        53,     7,      430,    "RO",   0,      1,      0ull,   0},
62256         {"RESERVED_60_63"              ,        60,     4,      430,    "RAZ",  0,      0,      0ull,   0ull},
62257         {"RESERVED_0_8"                ,        0,      9,      431,    "RAZ",  0,      0,      0ull,   0ull},
62258         {"D3_DFFST"                    ,        9,      9,      431,    "RO",   0,      1,      0ull,   0},
62259         {"D2_DFFST"                    ,        18,     9,      431,    "RO",   0,      1,      0ull,   0},
62260         {"D1_DFFST"                    ,        27,     9,      431,    "RO",   0,      1,      0ull,   0},
62261         {"D0_DFFST"                    ,        36,     9,      431,    "RO",   0,      1,      0ull,   0},
62262         {"RESERVED_45_63"              ,        45,     19,     431,    "RAZ",  0,      0,      0ull,   0ull},
62263         {"D3_DREST"                    ,        0,      15,     432,    "RO",   0,      1,      0ull,   0},
62264         {"D2_DREST"                    ,        15,     15,     432,    "RO",   0,      1,      0ull,   0},
62265         {"D1_DREST"                    ,        30,     15,     432,    "RO",   0,      1,      0ull,   0},
62266         {"D0_DREST"                    ,        45,     15,     432,    "RO",   0,      1,      0ull,   0},
62267         {"RESERVED_60_63"              ,        60,     4,      432,    "RAZ",  0,      0,      0ull,   0ull},
62268         {"D3_DWEST"                    ,        0,      13,     433,    "RO",   0,      1,      0ull,   0},
62269         {"D2_DWEST"                    ,        13,     13,     433,    "RO",   0,      1,      0ull,   0},
62270         {"D1_DWEST"                    ,        26,     13,     433,    "RO",   0,      1,      0ull,   0},
62271         {"D0_DWEST"                    ,        39,     13,     433,    "RO",   0,      1,      0ull,   0},
62272         {"RESERVED_52_63"              ,        52,     12,     433,    "RAZ",  0,      0,      0ull,   0ull},
62273         {"DMA0_CPL"                    ,        0,      1,      434,    "R/W",  0,      0,      0ull,   1ull},
62274         {"DMA1_CPL"                    ,        1,      1,      434,    "R/W",  0,      0,      0ull,   1ull},
62275         {"RESERVED_2_63"               ,        2,      62,     434,    "RAZ",  0,      1,      0ull,   0},
62276         {"DMA0_CPL"                    ,        0,      1,      435,    "R/W",  0,      0,      0ull,   1ull},
62277         {"DMA1_CPL"                    ,        1,      1,      435,    "R/W",  0,      0,      0ull,   1ull},
62278         {"RESERVED_2_63"               ,        2,      62,     435,    "RAZ",  0,      1,      0ull,   0},
62279         {"DMA0_CPL"                    ,        0,      1,      436,    "R/W1C",        0,      0,      0ull,   0ull},
62280         {"DMA1_CPL"                    ,        1,      1,      436,    "R/W1C",        0,      0,      0ull,   0ull},
62281         {"RESERVED_2_63"               ,        2,      62,     436,    "RAZ",  0,      0,      0ull,   0ull},
62282         {"RML_RTO"                     ,        0,      1,      437,    "R/W",  0,      0,      0ull,   1ull},
62283         {"RML_WTO"                     ,        1,      1,      437,    "R/W",  0,      0,      0ull,   1ull},
62284         {"BAR0_TO"                     ,        2,      1,      437,    "R/W",  0,      0,      0ull,   1ull},
62285         {"IOB2BIG"                     ,        3,      1,      437,    "R/W",  0,      0,      0ull,   1ull},
62286         {"DMA0DBO"                     ,        4,      1,      437,    "R/W",  0,      0,      0ull,   1ull},
62287         {"DMA1DBO"                     ,        5,      1,      437,    "R/W",  0,      0,      0ull,   1ull},
62288         {"DMA2DBO"                     ,        6,      1,      437,    "R/W",  0,      0,      0ull,   1ull},
62289         {"DMA3DBO"                     ,        7,      1,      437,    "R/W",  0,      0,      0ull,   1ull},
62290         {"RESERVED_8_8"                ,        8,      1,      437,    "RAZ",  1,      1,      0,      0},
62291         {"DMA0FI"                      ,        9,      1,      437,    "R/W",  0,      0,      0ull,   1ull},
62292         {"DMA1FI"                      ,        10,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62293         {"DCNT0"                       ,        11,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62294         {"DCNT1"                       ,        12,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62295         {"DTIME0"                      ,        13,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62296         {"DTIME1"                      ,        14,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62297         {"PSLDBOF"                     ,        15,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62298         {"PIDBOF"                      ,        16,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62299         {"PCNT"                        ,        17,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62300         {"PTIME"                       ,        18,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62301         {"C0_AERI"                     ,        19,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62302         {"CRS0_ER"                     ,        20,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62303         {"C0_SE"                       ,        21,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62304         {"CRS0_DR"                     ,        22,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62305         {"C0_WAKE"                     ,        23,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62306         {"C0_PMEI"                     ,        24,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62307         {"C0_HPINT"                    ,        25,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62308         {"C1_AERI"                     ,        26,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62309         {"CRS1_ER"                     ,        27,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62310         {"C1_SE"                       ,        28,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62311         {"CRS1_DR"                     ,        29,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62312         {"C1_WAKE"                     ,        30,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62313         {"C1_PMEI"                     ,        31,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62314         {"C1_HPINT"                    ,        32,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62315         {"C0_UP_B0"                    ,        33,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62316         {"C0_UP_B1"                    ,        34,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62317         {"C0_UP_B2"                    ,        35,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62318         {"C0_UP_WI"                    ,        36,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62319         {"C0_UP_BX"                    ,        37,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62320         {"C0_UN_B0"                    ,        38,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62321         {"C0_UN_B1"                    ,        39,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62322         {"C0_UN_B2"                    ,        40,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62323         {"C0_UN_WI"                    ,        41,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62324         {"C0_UN_BX"                    ,        42,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62325         {"C1_UP_B0"                    ,        43,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62326         {"C1_UP_B1"                    ,        44,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62327         {"C1_UP_B2"                    ,        45,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62328         {"C1_UP_WI"                    ,        46,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62329         {"C1_UP_BX"                    ,        47,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62330         {"C1_UN_B0"                    ,        48,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62331         {"C1_UN_B1"                    ,        49,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62332         {"C1_UN_B2"                    ,        50,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62333         {"C1_UN_WI"                    ,        51,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62334         {"C1_UN_BX"                    ,        52,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62335         {"C0_UN_WF"                    ,        53,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62336         {"C1_UN_WF"                    ,        54,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62337         {"C0_UP_WF"                    ,        55,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62338         {"C1_UP_WF"                    ,        56,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62339         {"C0_EXC"                      ,        57,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62340         {"C1_EXC"                      ,        58,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62341         {"C0_LDWN"                     ,        59,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62342         {"C1_LDWN"                     ,        60,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62343         {"INT_A"                       ,        61,     1,      437,    "RO",   0,      0,      1ull,   1ull},
62344         {"RESERVED_62_62"              ,        62,     1,      437,    "RAZ",  0,      1,      0ull,   0},
62345         {"MIO_INTA"                    ,        63,     1,      437,    "R/W",  0,      0,      0ull,   1ull},
62346         {"RML_RTO"                     ,        0,      1,      438,    "R/W",  0,      0,      0ull,   1ull},
62347         {"RML_WTO"                     ,        1,      1,      438,    "R/W",  0,      0,      0ull,   1ull},
62348         {"BAR0_TO"                     ,        2,      1,      438,    "R/W",  0,      0,      0ull,   1ull},
62349         {"IOB2BIG"                     ,        3,      1,      438,    "R/W",  0,      0,      0ull,   1ull},
62350         {"DMA0DBO"                     ,        4,      1,      438,    "R/W",  0,      0,      0ull,   1ull},
62351         {"DMA1DBO"                     ,        5,      1,      438,    "R/W",  0,      0,      0ull,   1ull},
62352         {"DMA2DBO"                     ,        6,      1,      438,    "R/W",  0,      0,      0ull,   1ull},
62353         {"DMA3DBO"                     ,        7,      1,      438,    "R/W",  0,      0,      0ull,   1ull},
62354         {"RESERVED_8_8"                ,        8,      1,      438,    "RAZ",  1,      1,      0,      0},
62355         {"DMA0FI"                      ,        9,      1,      438,    "R/W",  0,      0,      0ull,   1ull},
62356         {"DMA1FI"                      ,        10,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62357         {"DCNT0"                       ,        11,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62358         {"DCNT1"                       ,        12,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62359         {"DTIME0"                      ,        13,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62360         {"DTIME1"                      ,        14,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62361         {"PSLDBOF"                     ,        15,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62362         {"PIDBOF"                      ,        16,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62363         {"PCNT"                        ,        17,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62364         {"PTIME"                       ,        18,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62365         {"C0_AERI"                     ,        19,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62366         {"CRS0_ER"                     ,        20,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62367         {"C0_SE"                       ,        21,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62368         {"CRS0_DR"                     ,        22,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62369         {"C0_WAKE"                     ,        23,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62370         {"C0_PMEI"                     ,        24,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62371         {"C0_HPINT"                    ,        25,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62372         {"C1_AERI"                     ,        26,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62373         {"CRS1_ER"                     ,        27,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62374         {"C1_SE"                       ,        28,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62375         {"CRS1_DR"                     ,        29,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62376         {"C1_WAKE"                     ,        30,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62377         {"C1_PMEI"                     ,        31,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62378         {"C1_HPINT"                    ,        32,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62379         {"C0_UP_B0"                    ,        33,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62380         {"C0_UP_B1"                    ,        34,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62381         {"C0_UP_B2"                    ,        35,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62382         {"C0_UP_WI"                    ,        36,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62383         {"C0_UP_BX"                    ,        37,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62384         {"C0_UN_B0"                    ,        38,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62385         {"C0_UN_B1"                    ,        39,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62386         {"C0_UN_B2"                    ,        40,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62387         {"C0_UN_WI"                    ,        41,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62388         {"C0_UN_BX"                    ,        42,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62389         {"C1_UP_B0"                    ,        43,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62390         {"C1_UP_B1"                    ,        44,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62391         {"C1_UP_B2"                    ,        45,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62392         {"C1_UP_WI"                    ,        46,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62393         {"C1_UP_BX"                    ,        47,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62394         {"C1_UN_B0"                    ,        48,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62395         {"C1_UN_B1"                    ,        49,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62396         {"C1_UN_B2"                    ,        50,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62397         {"C1_UN_WI"                    ,        51,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62398         {"C1_UN_BX"                    ,        52,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62399         {"C0_UN_WF"                    ,        53,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62400         {"C1_UN_WF"                    ,        54,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62401         {"C0_UP_WF"                    ,        55,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62402         {"C1_UP_WF"                    ,        56,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62403         {"C0_EXC"                      ,        57,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62404         {"C1_EXC"                      ,        58,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62405         {"C0_LDWN"                     ,        59,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62406         {"C1_LDWN"                     ,        60,     1,      438,    "R/W",  0,      0,      0ull,   1ull},
62407         {"INT_A"                       ,        61,     1,      438,    "RO",   0,      0,      1ull,   1ull},
62408         {"RESERVED_62_63"              ,        62,     2,      438,    "RAZ",  0,      1,      0ull,   0},
62409         {"RML_RTO"                     ,        0,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62410         {"RML_WTO"                     ,        1,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62411         {"BAR0_TO"                     ,        2,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62412         {"IOB2BIG"                     ,        3,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62413         {"DMA0DBO"                     ,        4,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62414         {"DMA1DBO"                     ,        5,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62415         {"DMA2DBO"                     ,        6,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62416         {"DMA3DBO"                     ,        7,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62417         {"RESERVED_8_8"                ,        8,      1,      439,    "RAZ",  1,      1,      0,      0},
62418         {"DMA0FI"                      ,        9,      1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62419         {"DMA1FI"                      ,        10,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62420         {"DCNT0"                       ,        11,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62421         {"DCNT1"                       ,        12,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62422         {"DTIME0"                      ,        13,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62423         {"DTIME1"                      ,        14,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62424         {"RESERVED_15_18"              ,        15,     4,      439,    "RAZ",  0,      0,      0ull,   0ull},
62425         {"C0_AERI"                     ,        19,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62426         {"CRS0_ER"                     ,        20,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62427         {"C0_SE"                       ,        21,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62428         {"CRS0_DR"                     ,        22,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62429         {"C0_WAKE"                     ,        23,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62430         {"C0_PMEI"                     ,        24,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62431         {"C0_HPINT"                    ,        25,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62432         {"C1_AERI"                     ,        26,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62433         {"CRS1_ER"                     ,        27,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62434         {"C1_SE"                       ,        28,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62435         {"CRS1_DR"                     ,        29,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62436         {"C1_WAKE"                     ,        30,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62437         {"C1_PMEI"                     ,        31,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62438         {"C1_HPINT"                    ,        32,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62439         {"C0_UP_B0"                    ,        33,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62440         {"C0_UP_B1"                    ,        34,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62441         {"C0_UP_B2"                    ,        35,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62442         {"C0_UP_WI"                    ,        36,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62443         {"C0_UP_BX"                    ,        37,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62444         {"C0_UN_B0"                    ,        38,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62445         {"C0_UN_B1"                    ,        39,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62446         {"C0_UN_B2"                    ,        40,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62447         {"C0_UN_WI"                    ,        41,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62448         {"C0_UN_BX"                    ,        42,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62449         {"C1_UP_B0"                    ,        43,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62450         {"C1_UP_B1"                    ,        44,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62451         {"C1_UP_B2"                    ,        45,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62452         {"C1_UP_WI"                    ,        46,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62453         {"C1_UP_BX"                    ,        47,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62454         {"C1_UN_B0"                    ,        48,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62455         {"C1_UN_B1"                    ,        49,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62456         {"C1_UN_B2"                    ,        50,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62457         {"C1_UN_WI"                    ,        51,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62458         {"C1_UN_BX"                    ,        52,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62459         {"C0_UN_WF"                    ,        53,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62460         {"C1_UN_WF"                    ,        54,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62461         {"C0_UP_WF"                    ,        55,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62462         {"C1_UP_WF"                    ,        56,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62463         {"C0_EXC"                      ,        57,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62464         {"C1_EXC"                      ,        58,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62465         {"C0_LDWN"                     ,        59,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62466         {"C1_LDWN"                     ,        60,     1,      439,    "R/W1C",        0,      0,      0ull,   0ull},
62467         {"INT_A"                       ,        61,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62468         {"RESERVED_62_62"              ,        62,     1,      439,    "RAZ",  0,      0,      0ull,   0ull},
62469         {"MIO_INTA"                    ,        63,     1,      439,    "RO",   0,      0,      0ull,   0ull},
62470         {"RML_RTO"                     ,        0,      1,      440,    "RO",   0,      0,      0ull,   0ull},
62471         {"RML_WTO"                     ,        1,      1,      440,    "RO",   0,      0,      0ull,   0ull},
62472         {"BAR0_TO"                     ,        2,      1,      440,    "RO",   0,      0,      0ull,   0ull},
62473         {"IOB2BIG"                     ,        3,      1,      440,    "RO",   0,      0,      0ull,   0ull},
62474         {"DMA0DBO"                     ,        4,      1,      440,    "RO",   0,      0,      0ull,   0ull},
62475         {"DMA1DBO"                     ,        5,      1,      440,    "RO",   0,      0,      0ull,   0ull},
62476         {"DMA2DBO"                     ,        6,      1,      440,    "RO",   0,      0,      0ull,   0ull},
62477         {"DMA3DBO"                     ,        7,      1,      440,    "RO",   0,      0,      0ull,   0ull},
62478         {"RESERVED_8_8"                ,        8,      1,      440,    "RAZ",  1,      1,      0,      0},
62479         {"DMA0FI"                      ,        9,      1,      440,    "RO",   0,      0,      0ull,   0ull},
62480         {"DMA1FI"                      ,        10,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62481         {"DCNT0"                       ,        11,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62482         {"DCNT1"                       ,        12,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62483         {"DTIME0"                      ,        13,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62484         {"DTIME1"                      ,        14,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62485         {"RESERVED_15_18"              ,        15,     4,      440,    "RAZ",  0,      0,      0ull,   0ull},
62486         {"C0_AERI"                     ,        19,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62487         {"CRS0_ER"                     ,        20,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62488         {"C0_SE"                       ,        21,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62489         {"CRS0_DR"                     ,        22,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62490         {"C0_WAKE"                     ,        23,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62491         {"C0_PMEI"                     ,        24,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62492         {"C0_HPINT"                    ,        25,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62493         {"C1_AERI"                     ,        26,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62494         {"CRS1_ER"                     ,        27,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62495         {"C1_SE"                       ,        28,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62496         {"CRS1_DR"                     ,        29,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62497         {"C1_WAKE"                     ,        30,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62498         {"C1_PMEI"                     ,        31,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62499         {"C1_HPINT"                    ,        32,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62500         {"C0_UP_B0"                    ,        33,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62501         {"C0_UP_B1"                    ,        34,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62502         {"C0_UP_B2"                    ,        35,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62503         {"C0_UP_WI"                    ,        36,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62504         {"C0_UP_BX"                    ,        37,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62505         {"C0_UN_B0"                    ,        38,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62506         {"C0_UN_B1"                    ,        39,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62507         {"C0_UN_B2"                    ,        40,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62508         {"C0_UN_WI"                    ,        41,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62509         {"C0_UN_BX"                    ,        42,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62510         {"C1_UP_B0"                    ,        43,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62511         {"C1_UP_B1"                    ,        44,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62512         {"C1_UP_B2"                    ,        45,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62513         {"C1_UP_WI"                    ,        46,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62514         {"C1_UP_BX"                    ,        47,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62515         {"C1_UN_B0"                    ,        48,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62516         {"C1_UN_B1"                    ,        49,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62517         {"C1_UN_B2"                    ,        50,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62518         {"C1_UN_WI"                    ,        51,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62519         {"C1_UN_BX"                    ,        52,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62520         {"C0_UN_WF"                    ,        53,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62521         {"C1_UN_WF"                    ,        54,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62522         {"C0_UP_WF"                    ,        55,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62523         {"C1_UP_WF"                    ,        56,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62524         {"C0_EXC"                      ,        57,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62525         {"C1_EXC"                      ,        58,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62526         {"C0_LDWN"                     ,        59,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62527         {"C1_LDWN"                     ,        60,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62528         {"INT_A"                       ,        61,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62529         {"RESERVED_62_62"              ,        62,     1,      440,    "RAZ",  0,      0,      0ull,   0ull},
62530         {"MIO_INTA"                    ,        63,     1,      440,    "RO",   0,      0,      0ull,   0ull},
62531         {"DATA"                        ,        0,      64,     441,    "RO",   0,      1,      0ull,   0},
62532         {"DATA"                        ,        0,      64,     442,    "RO",   0,      1,      0ull,   0},
62533         {"TIMER"                       ,        0,      10,     443,    "R/W",  0,      0,      0ull,   50ull},
62534         {"MAX_WORD"                    ,        10,     4,      443,    "R/W",  0,      0,      0ull,   0ull},
62535         {"RESERVED_14_63"              ,        14,     50,     443,    "RAZ",  1,      1,      0,      0},
62536         {"BA"                          ,        0,      30,     444,    "R/W",  0,      1,      0ull,   0},
62537         {"ROW"                         ,        30,     1,      444,    "R/W",  0,      1,      0ull,   0},
62538         {"ROR"                         ,        31,     1,      444,    "R/W",  0,      1,      0ull,   0},
62539         {"NSW"                         ,        32,     1,      444,    "R/W",  0,      1,      0ull,   0},
62540         {"NSR"                         ,        33,     1,      444,    "R/W",  0,      1,      0ull,   0},
62541         {"ESW"                         ,        34,     2,      444,    "R/W",  0,      1,      0ull,   0},
62542         {"ESR"                         ,        36,     2,      444,    "R/W",  0,      1,      0ull,   0},
62543         {"NMERGE"                      ,        38,     1,      444,    "R/W",  0,      0,      0ull,   0ull},
62544         {"PORT"                        ,        39,     2,      444,    "R/W",  0,      1,      0ull,   0},
62545         {"ZERO"                        ,        41,     1,      444,    "R/W",  0,      0,      0ull,   0ull},
62546         {"RESERVED_42_63"              ,        42,     22,     444,    "RAZ",  1,      1,      0,      0},
62547         {"ENB"                         ,        0,      64,     445,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
62548         {"ENB"                         ,        0,      64,     446,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
62549         {"ENB"                         ,        0,      64,     447,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
62550         {"ENB"                         ,        0,      64,     448,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
62551         {"INTR"                        ,        0,      64,     449,    "R/W1C",        0,      0,      0ull,   0ull},
62552         {"INTR"                        ,        0,      64,     450,    "R/W1C",        0,      0,      0ull,   0ull},
62553         {"INTR"                        ,        0,      64,     451,    "R/W1C",        0,      0,      0ull,   0ull},
62554         {"INTR"                        ,        0,      64,     452,    "R/W1C",        0,      0,      0ull,   0ull},
62555         {"MSI_INT"                     ,        0,      8,      453,    "R/W",  0,      1,      0ull,   0},
62556         {"RD_INT"                      ,        8,      8,      453,    "RO",   0,      1,      0ull,   0},
62557         {"RESERVED_16_63"              ,        16,     48,     453,    "RAZ",  1,      1,      0,      0},
62558         {"MSI_INT"                     ,        0,      8,      454,    "R/W",  0,      1,      0ull,   0},
62559         {"CIU_INT"                     ,        8,      8,      454,    "R/W",  0,      1,      0ull,   0},
62560         {"RESERVED_16_63"              ,        16,     48,     454,    "RAZ",  1,      1,      0,      0},
62561         {"INTR"                        ,        0,      8,      455,    "R/W",  0,      1,      0ull,   0},
62562         {"RESERVED_8_63"               ,        8,      56,     455,    "RAZ",  1,      1,      0,      0},
62563         {"RESERVED_0_7"                ,        0,      8,      456,    "RAZ",  1,      1,      0,      0},
62564         {"INTR"                        ,        8,      8,      456,    "R/W",  0,      1,      0ull,   0},
62565         {"RESERVED_16_63"              ,        16,     48,     456,    "RAZ",  1,      1,      0,      0},
62566         {"RESERVED_0_15"               ,        0,      16,     457,    "RAZ",  1,      1,      0,      0},
62567         {"INTR"                        ,        16,     8,      457,    "R/W",  0,      1,      0ull,   0},
62568         {"RESERVED_24_63"              ,        24,     40,     457,    "RAZ",  1,      1,      0,      0},
62569         {"RESERVED_0_23"               ,        0,      24,     458,    "RAZ",  1,      1,      0,      0},
62570         {"INTR"                        ,        24,     8,      458,    "R/W",  0,      1,      0ull,   0},
62571         {"RESERVED_32_63"              ,        32,     32,     458,    "RAZ",  1,      1,      0,      0},
62572         {"MIO"                         ,        0,      1,      459,    "RO",   0,      0,      0ull,   0ull},
62573         {"GMX0"                        ,        1,      1,      459,    "RO",   0,      0,      0ull,   0ull},
62574         {"GMX1"                        ,        2,      1,      459,    "RO",   0,      0,      0ull,   0ull},
62575         {"NPEI"                        ,        3,      1,      459,    "RO",   0,      0,      0ull,   0ull},
62576         {"KEY"                         ,        4,      1,      459,    "RO",   0,      0,      0ull,   0ull},
62577         {"FPA"                         ,        5,      1,      459,    "RO",   0,      0,      0ull,   0ull},
62578         {"DFA"                         ,        6,      1,      459,    "RAZ",  0,      0,      0ull,   0ull},
62579         {"ZIP"                         ,        7,      1,      459,    "RO",   0,      0,      0ull,   0ull},
62580         {"RESERVED_8_8"                ,        8,      1,      459,    "RAZ",  0,      0,      0ull,   0ull},
62581         {"IPD"                         ,        9,      1,      459,    "RO",   0,      0,      0ull,   0ull},
62582         {"PKO"                         ,        10,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62583         {"TIM"                         ,        11,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62584         {"POW"                         ,        12,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62585         {"USB"                         ,        13,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62586         {"RAD"                         ,        14,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62587         {"USB1"                        ,        15,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62588         {"L2C"                         ,        16,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62589         {"LMC0"                        ,        17,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62590         {"SPX0"                        ,        18,     1,      459,    "RAZ",  0,      0,      0ull,   0ull},
62591         {"SPX1"                        ,        19,     1,      459,    "RAZ",  0,      0,      0ull,   0ull},
62592         {"PIP"                         ,        20,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62593         {"RESERVED_21_21"              ,        21,     1,      459,    "RAZ",  0,      0,      0ull,   0ull},
62594         {"ASXPCS0"                     ,        22,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62595         {"ASXPCS1"                     ,        23,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62596         {"RESERVED_24_27"              ,        24,     4,      459,    "RAZ",  0,      0,      0ull,   0ull},
62597         {"AGL"                         ,        28,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62598         {"LMC1"                        ,        29,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62599         {"IOB"                         ,        30,     1,      459,    "RO",   0,      0,      0ull,   0ull},
62600         {"RESERVED_31_63"              ,        31,     33,     459,    "RAZ",  0,      0,      0ull,   0ull},
62601         {"DATA"                        ,        0,      64,     460,    "R/W",  0,      1,      0ull,   0},
62602         {"CSR"                         ,        0,      39,     461,    "RO",   0,      1,      1ull,   0},
62603         {"ARB"                         ,        39,     1,      461,    "RO",   0,      1,      0ull,   0},
62604         {"CPL0"                        ,        40,     12,     461,    "RO",   0,      1,      1ull,   0},
62605         {"CPL1"                        ,        52,     12,     461,    "RO",   0,      1,      1ull,   0},
62606         {"NND"                         ,        0,      8,      462,    "RO",   0,      1,      1ull,   0},
62607         {"NNP0"                        ,        8,      8,      462,    "RO",   0,      1,      1ull,   0},
62608         {"CSM0"                        ,        16,     15,     462,    "RO",   0,      1,      1ull,   0},
62609         {"CSM1"                        ,        31,     15,     462,    "RO",   0,      1,      1ull,   0},
62610         {"RAC"                         ,        46,     1,      462,    "RO",   0,      1,      1ull,   0},
62611         {"NPEI"                        ,        47,     1,      462,    "RO",   0,      1,      1ull,   0},
62612         {"RESERVED_48_63"              ,        48,     16,     462,    "RAZ",  1,      1,      0,      0},
62613         {"NSM0"                        ,        0,      13,     463,    "RO",   0,      1,      1ull,   0},
62614         {"NSM1"                        ,        13,     13,     463,    "RO",   0,      1,      1ull,   0},
62615         {"PSM0"                        ,        26,     15,     463,    "RO",   0,      1,      1ull,   0},
62616         {"PSM1"                        ,        41,     15,     463,    "RO",   0,      1,      1ull,   0},
62617         {"RESERVED_56_63"              ,        56,     8,      463,    "RAZ",  1,      1,      0,      0},
62618         {"RD_ADDR"                     ,        0,      48,     464,    "R/W",  0,      1,      0ull,   0},
62619         {"IOBIT"                       ,        48,     1,      464,    "RAZ",  0,      0,      0ull,   0ull},
62620         {"LD_CMD"                      ,        49,     2,      464,    "R/W",  0,      1,      0ull,   0},
62621         {"RESERVED_51_63"              ,        51,     13,     464,    "RAZ",  1,      1,      0,      0},
62622         {"RD_DATA"                     ,        0,      64,     465,    "RO",   0,      1,      0ull,   0},
62623         {"RESERVED_0_1"                ,        0,      2,      466,    "RAZ",  1,      1,      0,      0},
62624         {"WR_ADDR"                     ,        2,      46,     466,    "R/W",  0,      1,      0ull,   0},
62625         {"IOBIT"                       ,        48,     1,      466,    "RAZ",  0,      0,      0ull,   0ull},
62626         {"RESERVED_49_63"              ,        49,     15,     466,    "RAZ",  1,      1,      0,      0},
62627         {"WR_DATA"                     ,        0,      64,     467,    "R/W",  0,      1,      0ull,   0},
62628         {"WR_MASK"                     ,        0,      8,      468,    "R/W",  0,      0,      0ull,   0ull},
62629         {"RESERVED_8_63"               ,        8,      56,     468,    "RAZ",  1,      1,      0,      0},
62630         {"TIME"                        ,        0,      32,     469,    "R/W",  0,      0,      0ull,   2097152ull},
62631         {"RESERVED_32_63"              ,        32,     32,     469,    "RAZ",  1,      1,      0,      0},
62632         {"VENDID"                      ,        0,      16,     470,    "RO/WRSL",      0,      0,      6013ull,        6013ull},
62633         {"DEVID"                       ,        16,     16,     470,    "RO/WRSL",      0,      0,      128ull, 128ull},
62634         {"ISAE"                        ,        0,      1,      471,    "R/W",  0,      0,      0ull,   0ull},
62635         {"MSAE"                        ,        1,      1,      471,    "R/W",  0,      0,      0ull,   0ull},
62636         {"ME"                          ,        2,      1,      471,    "R/W",  0,      0,      0ull,   0ull},
62637         {"SCSE"                        ,        3,      1,      471,    "RO",   0,      0,      0ull,   0ull},
62638         {"MWICE"                       ,        4,      1,      471,    "RO",   0,      0,      0ull,   0ull},
62639         {"VPS"                         ,        5,      1,      471,    "RO",   0,      0,      0ull,   0ull},
62640         {"PER"                         ,        6,      1,      471,    "R/W",  0,      0,      0ull,   0ull},
62641         {"IDS_WCC"                     ,        7,      1,      471,    "RO",   0,      0,      0ull,   0ull},
62642         {"SEE"                         ,        8,      1,      471,    "R/W",  0,      0,      0ull,   0ull},
62643         {"FBBE"                        ,        9,      1,      471,    "RO",   0,      0,      0ull,   0ull},
62644         {"I_DIS"                       ,        10,     1,      471,    "R/W",  0,      0,      0ull,   0ull},
62645         {"RESERVED_11_18"              ,        11,     8,      471,    "RAZ",  1,      1,      0,      0},
62646         {"I_STAT"                      ,        19,     1,      471,    "RO",   0,      0,      0ull,   0ull},
62647         {"CL"                          ,        20,     1,      471,    "RO",   0,      0,      1ull,   1ull},
62648         {"M66"                         ,        21,     1,      471,    "RO",   0,      0,      0ull,   0ull},
62649         {"RESERVED_22_22"              ,        22,     1,      471,    "RAZ",  1,      1,      0,      0},
62650         {"FBB"                         ,        23,     1,      471,    "RO",   0,      0,      0ull,   0ull},
62651         {"MDPE"                        ,        24,     1,      471,    "R/W1C",        0,      0,      0ull,   0ull},
62652         {"DEVT"                        ,        25,     2,      471,    "RO",   0,      0,      0ull,   0ull},
62653         {"STA"                         ,        27,     1,      471,    "R/W1C",        0,      0,      0ull,   0ull},
62654         {"RTA"                         ,        28,     1,      471,    "R/W1C",        0,      0,      0ull,   0ull},
62655         {"RMA"                         ,        29,     1,      471,    "R/W1C",        0,      0,      0ull,   0ull},
62656         {"SSE"                         ,        30,     1,      471,    "R/W1C",        0,      0,      0ull,   0ull},
62657         {"DPE"                         ,        31,     1,      471,    "R/W1C",        0,      0,      0ull,   0ull},
62658         {"RID"                         ,        0,      8,      472,    "RO/WRSL",      0,      0,      0ull,   0ull},
62659         {"PI"                          ,        8,      8,      472,    "RO/WRSL",      0,      0,      0ull,   0ull},
62660         {"SC"                          ,        16,     8,      472,    "RO/WRSL",      0,      0,      48ull,  48ull},
62661         {"BCC"                         ,        24,     8,      472,    "RO/WRSL",      0,      0,      11ull,  11ull},
62662         {"CLS"                         ,        0,      8,      473,    "R/W",  0,      0,      0ull,   0ull},
62663         {"LT"                          ,        8,      8,      473,    "RO",   0,      0,      0ull,   0ull},
62664         {"CHF"                         ,        16,     7,      473,    "RO",   0,      0,      0ull,   0ull},
62665         {"MFD"                         ,        23,     1,      473,    "RO/WRSL",      0,      0,      0ull,   0ull},
62666         {"BIST"                        ,        24,     8,      473,    "RO",   0,      0,      0ull,   0ull},
62667         {"MSPC"                        ,        0,      1,      474,    "RO/WRSL",      0,      0,      0ull,   0ull},
62668         {"TYP"                         ,        1,      2,      474,    "RO/WRSL",      0,      0,      2ull,   2ull},
62669         {"PF"                          ,        3,      1,      474,    "RO/WRSL",      0,      0,      1ull,   1ull},
62670         {"RESERVED_4_13"               ,        4,      10,     474,    "RAZ",  1,      1,      0,      0},
62671         {"LBAB"                        ,        14,     18,     474,    "R/W",  0,      0,      0ull,   0ull},
62672         {"ENB"                         ,        0,      1,      475,    "WORSL",        0,      0,      1ull,   1ull},
62673         {"LMASK"                       ,        1,      31,     475,    "WORSL",        0,      0,      8191ull,        8191ull},
62674         {"UBAB"                        ,        0,      32,     476,    "R/W",  0,      0,      0ull,   0ull},
62675         {"UMASK"                       ,        0,      32,     477,    "WORSL",        0,      0,      0ull,   0ull},
62676         {"MSPC"                        ,        0,      1,      478,    "RO/WRSL",      0,      0,      0ull,   0ull},
62677         {"TYP"                         ,        1,      2,      478,    "RO/WRSL",      0,      0,      2ull,   2ull},
62678         {"PF"                          ,        3,      1,      478,    "RO/WRSL",      0,      0,      1ull,   1ull},
62679         {"RESERVED_4_25"               ,        4,      22,     478,    "RAZ",  1,      1,      0,      0},
62680         {"LBAB"                        ,        26,     6,      478,    "R/W",  0,      0,      0ull,   0ull},
62681         {"ENB"                         ,        0,      1,      479,    "WORSL",        0,      0,      1ull,   1ull},
62682         {"LMASK"                       ,        1,      31,     479,    "WORSL",        0,      0,      33554431ull,    33554431ull},
62683         {"UBAB"                        ,        0,      32,     480,    "R/W",  0,      0,      0ull,   0ull},
62684         {"UMASK"                       ,        0,      32,     481,    "WORSL",        0,      0,      0ull,   0ull},
62685         {"MSPC"                        ,        0,      1,      482,    "RO/WRSL",      0,      0,      0ull,   0ull},
62686         {"TYP"                         ,        1,      2,      482,    "RO/WRSL",      0,      0,      2ull,   2ull},
62687         {"PF"                          ,        3,      1,      482,    "RO/WRSL",      0,      0,      1ull,   1ull},
62688         {"RESERVED_4_31"               ,        4,      28,     482,    "RAZ",  1,      1,      0,      0},
62689         {"ENB"                         ,        0,      1,      483,    "WORSL",        0,      0,      1ull,   1ull},
62690         {"LMASK"                       ,        1,      31,     483,    "WORSL",        0,      0,      2147483647ull,  2147483647ull},
62691         {"RESERVED_0_6"                ,        0,      7,      484,    "RAZ",  1,      1,      0,      0},
62692         {"UBAB"                        ,        7,      25,     484,    "R/W",  0,      0,      0ull,   0ull},
62693         {"UMASK"                       ,        0,      32,     485,    "WORSL",        0,      0,      127ull, 127ull},
62694         {"CISP"                        ,        0,      32,     486,    "RO/WRSL",      0,      0,      0ull,   0ull},
62695         {"SSVID"                       ,        0,      16,     487,    "RO/WRSL",      0,      0,      6013ull,        6013ull},
62696         {"SSID"                        ,        16,     16,     487,    "RO/WRSL",      0,      0,      1ull,   1ull},
62697         {"ER_EN"                       ,        0,      1,      488,    "R/W",  0,      0,      0ull,   0ull},
62698         {"RESERVED_1_15"               ,        1,      15,     488,    "RAZ",  1,      1,      0,      0},
62699         {"ERADDR"                      ,        16,     16,     488,    "R/W",  0,      0,      0ull,   0ull},
62700         {"ENB"                         ,        0,      1,      489,    "WORSL",        0,      0,      1ull,   1ull},
62701         {"MASK"                        ,        1,      31,     489,    "WORSL",        0,      0,      2147483647ull,  2147483647ull},
62702         {"CP"                          ,        0,      8,      490,    "RO/WRSL",      0,      0,      64ull,  64ull},
62703         {"RESERVED_8_31"               ,        8,      24,     490,    "RAZ",  1,      1,      0,      0},
62704         {"IL"                          ,        0,      8,      491,    "R/W",  0,      0,      255ull, 255ull},
62705         {"INTA"                        ,        8,      8,      491,    "RO/WRSL",      0,      0,      1ull,   1ull},
62706         {"MG"                          ,        16,     8,      491,    "RO",   0,      0,      0ull,   0ull},
62707         {"ML"                          ,        24,     8,      491,    "RO",   0,      0,      0ull,   0ull},
62708         {"PMCID"                       ,        0,      8,      492,    "RO",   0,      0,      1ull,   0ull},
62709         {"NCP"                         ,        8,      8,      492,    "RO/WRSL",      0,      0,      80ull,  0ull},
62710         {"PMSV"                        ,        16,     3,      492,    "RO/WRSL",      0,      0,      3ull,   0ull},
62711         {"PME_CLOCK"                   ,        19,     1,      492,    "RO",   0,      0,      0ull,   0ull},
62712         {"RESERVED_20_20"              ,        20,     1,      492,    "RAZ",  1,      1,      0,      0},
62713         {"DSI"                         ,        21,     1,      492,    "RO/WRSL",      0,      0,      0ull,   0ull},
62714         {"AUXC"                        ,        22,     3,      492,    "RO/WRSL",      0,      0,      0ull,   0ull},
62715         {"D1S"                         ,        25,     1,      492,    "RO/WRSL",      0,      0,      0ull,   0ull},
62716         {"D2S"                         ,        26,     1,      492,    "RO/WRSL",      0,      0,      0ull,   0ull},
62717         {"PMES"                        ,        27,     5,      492,    "RO/WRSL",      0,      0,      0ull,   0ull},
62718         {"PS"                          ,        0,      2,      493,    "R/W",  0,      0,      0ull,   0ull},
62719         {"RESERVED_2_2"                ,        2,      1,      493,    "RAZ",  1,      1,      0,      0},
62720         {"NSR"                         ,        3,      1,      493,    "RO/WRSL",      0,      0,      0ull,   0ull},
62721         {"RESERVED_4_7"                ,        4,      4,      493,    "RAZ",  1,      1,      0,      0},
62722         {"PMEENS"                      ,        8,      1,      493,    "R/W",  0,      0,      0ull,   0ull},
62723         {"PMDS"                        ,        9,      4,      493,    "RO",   0,      0,      0ull,   0ull},
62724         {"PMEDSIA"                     ,        13,     2,      493,    "RO",   0,      0,      0ull,   0ull},
62725         {"PMESS"                       ,        15,     1,      493,    "R/W1C",        0,      0,      0ull,   0ull},
62726         {"RESERVED_16_21"              ,        16,     6,      493,    "RAZ",  1,      1,      0,      0},
62727         {"BD3H"                        ,        22,     1,      493,    "RO",   0,      0,      0ull,   0ull},
62728         {"BPCCEE"                      ,        23,     1,      493,    "RO",   0,      0,      0ull,   0ull},
62729         {"PMDIA"                       ,        24,     8,      493,    "RO",   0,      0,      0ull,   0ull},
62730         {"MSICID"                      ,        0,      8,      494,    "RO",   0,      0,      5ull,   5ull},
62731         {"NCP"                         ,        8,      8,      494,    "RO/WRSL",      0,      0,      112ull, 112ull},
62732         {"MSIEN"                       ,        16,     1,      494,    "R/W",  0,      0,      0ull,   0ull},
62733         {"MMC"                         ,        17,     3,      494,    "RO/WRSL",      0,      0,      0ull,   0ull},
62734         {"MME"                         ,        20,     3,      494,    "R/W",  0,      0,      0ull,   0ull},
62735         {"M64"                         ,        23,     1,      494,    "RO/WRSL",      0,      0,      1ull,   1ull},
62736         {"RESERVED_24_31"              ,        24,     8,      494,    "RAZ",  1,      1,      0,      0},
62737         {"RESERVED_0_1"                ,        0,      2,      495,    "RAZ",  1,      1,      0,      0},
62738         {"LMSI"                        ,        2,      30,     495,    "R/W",  0,      0,      0ull,   0ull},
62739         {"UMSI"                        ,        0,      32,     496,    "R/W",  0,      0,      0ull,   0ull},
62740         {"MSIMD"                       ,        0,      16,     497,    "R/W",  0,      0,      0ull,   0ull},
62741         {"RESERVED_16_31"              ,        16,     16,     497,    "RAZ",  1,      1,      0,      0},
62742         {"PCIEID"                      ,        0,      8,      498,    "RO",   0,      0,      16ull,  16ull},
62743         {"NCP"                         ,        8,      8,      498,    "RO/WRSL",      0,      0,      0ull,   0ull},
62744         {"PCIECV"                      ,        16,     4,      498,    "RO",   0,      0,      2ull,   2ull},
62745         {"DPT"                         ,        20,     4,      498,    "RO",   0,      0,      0ull,   0ull},
62746         {"SI"                          ,        24,     1,      498,    "RO/WRSL",      0,      0,      0ull,   0ull},
62747         {"IMN"                         ,        25,     5,      498,    "RO/WRSL",      0,      0,      0ull,   0ull},
62748         {"RESERVED_30_31"              ,        30,     2,      498,    "RAZ",  1,      1,      0,      0},
62749         {"MPSS"                        ,        0,      3,      499,    "RO/WRSL",      0,      0,      1ull,   1ull},
62750         {"PFS"                         ,        3,      2,      499,    "RO/WRSL",      0,      0,      0ull,   0ull},
62751         {"ETFS"                        ,        5,      1,      499,    "RO/WRSL",      0,      0,      0ull,   0ull},
62752         {"EL0AL"                       ,        6,      3,      499,    "RO/WRSL",      0,      0,      4ull,   4ull},
62753         {"EL1AL"                       ,        9,      3,      499,    "RO/WRSL",      0,      0,      3ull,   3ull},
62754         {"RESERVED_12_14"              ,        12,     3,      499,    "RAZ",  1,      1,      0,      0},
62755         {"RBER"                        ,        15,     1,      499,    "RO/WRSL",      0,      0,      1ull,   1ull},
62756         {"RESERVED_16_17"              ,        16,     2,      499,    "RAZ",  1,      1,      0,      0},
62757         {"CSPLV"                       ,        18,     8,      499,    "RO",   0,      0,      0ull,   0ull},
62758         {"CSPLS"                       ,        26,     2,      499,    "RO",   0,      0,      0ull,   0ull},
62759         {"RESERVED_28_31"              ,        28,     4,      499,    "RAZ",  1,      1,      0,      0},
62760         {"CE_EN"                       ,        0,      1,      500,    "R/W",  0,      0,      0ull,   0ull},
62761         {"NFE_EN"                      ,        1,      1,      500,    "R/W",  0,      0,      0ull,   0ull},
62762         {"FE_EN"                       ,        2,      1,      500,    "R/W",  0,      0,      0ull,   0ull},
62763         {"UR_EN"                       ,        3,      1,      500,    "R/W",  0,      0,      0ull,   0ull},
62764         {"RO_EN"                       ,        4,      1,      500,    "R/W",  0,      0,      1ull,   1ull},
62765         {"MPS"                         ,        5,      3,      500,    "R/W",  0,      0,      0ull,   0ull},
62766         {"ETF_EN"                      ,        8,      1,      500,    "R/W",  0,      0,      0ull,   0ull},
62767         {"PF_EN"                       ,        9,      1,      500,    "R/W",  0,      0,      0ull,   0ull},
62768         {"AP_EN"                       ,        10,     1,      500,    "R/W",  0,      0,      0ull,   0ull},
62769         {"NS_EN"                       ,        11,     1,      500,    "R/W",  0,      0,      1ull,   1ull},
62770         {"MRRS"                        ,        12,     3,      500,    "R/W",  0,      0,      2ull,   2ull},
62771         {"RESERVED_15_15"              ,        15,     1,      500,    "RAZ",  1,      1,      0,      0},
62772         {"CE_D"                        ,        16,     1,      500,    "R/W1C",        0,      0,      0ull,   0ull},
62773         {"NFE_D"                       ,        17,     1,      500,    "R/W1C",        0,      0,      0ull,   0ull},
62774         {"FE_D"                        ,        18,     1,      500,    "R/W1C",        0,      0,      0ull,   0ull},
62775         {"UR_D"                        ,        19,     1,      500,    "R/W1C",        0,      0,      0ull,   0ull},
62776         {"AP_D"                        ,        20,     1,      500,    "RO",   0,      0,      0ull,   0ull},
62777         {"TP"                          ,        21,     1,      500,    "RO",   0,      0,      0ull,   0ull},
62778         {"RESERVED_22_31"              ,        22,     10,     500,    "RAZ",  1,      1,      0,      0},
62779         {"MLS"                         ,        0,      4,      501,    "RO/WRSL",      0,      0,      1ull,   1ull},
62780         {"MLW"                         ,        4,      6,      501,    "RO/WRSL",      0,      0,      8ull,   8ull},
62781         {"ASLPMS"                      ,        10,     2,      501,    "RO/WRSL",      0,      0,      3ull,   3ull},
62782         {"L0EL"                        ,        12,     3,      501,    "RO/WRSL",      0,      0,      6ull,   6ull},
62783         {"L1EL"                        ,        15,     3,      501,    "RO/WRSL",      0,      0,      6ull,   6ull},
62784         {"CPM"                         ,        18,     1,      501,    "RO/WRSL",      0,      0,      0ull,   0ull},
62785         {"SDERC"                       ,        19,     1,      501,    "RO",   0,      0,      0ull,   0ull},
62786         {"DLLARC"                      ,        20,     1,      501,    "RO",   0,      0,      0ull,   0ull},
62787         {"LBNC"                        ,        21,     1,      501,    "RO",   0,      0,      0ull,   0ull},
62788         {"RESERVED_22_23"              ,        22,     2,      501,    "RAZ",  1,      1,      0,      0},
62789         {"PNUM"                        ,        24,     8,      501,    "RO/WRSL",      0,      0,      0ull,   0ull},
62790         {"ASLPC"                       ,        0,      2,      502,    "R/W",  0,      0,      0ull,   0ull},
62791         {"RESERVED_2_2"                ,        2,      1,      502,    "RAZ",  1,      1,      0,      0},
62792         {"RCB"                         ,        3,      1,      502,    "RO",   0,      0,      0ull,   0ull},
62793         {"LD"                          ,        4,      1,      502,    "RO",   0,      0,      0ull,   0ull},
62794         {"RL"                          ,        5,      1,      502,    "RO",   0,      0,      0ull,   0ull},
62795         {"CCC"                         ,        6,      1,      502,    "R/W",  0,      0,      0ull,   0ull},
62796         {"ES"                          ,        7,      1,      502,    "R/W",  0,      0,      0ull,   0ull},
62797         {"ECPM"                        ,        8,      1,      502,    "R/W",  0,      0,      0ull,   0ull},
62798         {"HAWD"                        ,        9,      1,      502,    "R/W",  0,      0,      0ull,   0ull},
62799         {"RESERVED_10_15"              ,        10,     6,      502,    "RAZ",  1,      1,      0,      0},
62800         {"LS"                          ,        16,     4,      502,    "RO",   0,      0,      1ull,   1ull},
62801         {"NLW"                         ,        20,     6,      502,    "RO",   0,      0,      0ull,   8ull},
62802         {"RESERVED_26_26"              ,        26,     1,      502,    "RAZ",  1,      1,      0,      0},
62803         {"LT"                          ,        27,     1,      502,    "RO",   0,      0,      0ull,   0ull},
62804         {"SCC"                         ,        28,     1,      502,    "RO/WRSL",      0,      0,      1ull,   1ull},
62805         {"DLLA"                        ,        29,     1,      502,    "RO",   0,      0,      0ull,   0ull},
62806         {"RESERVED_30_31"              ,        30,     2,      502,    "RAZ",  1,      1,      0,      0},
62807         {"ABP"                         ,        0,      1,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62808         {"PCP"                         ,        1,      1,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62809         {"MRLSP"                       ,        2,      1,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62810         {"AIP"                         ,        3,      1,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62811         {"PIP"                         ,        4,      1,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62812         {"HP_S"                        ,        5,      1,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62813         {"HP_C"                        ,        6,      1,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62814         {"SP_LV"                       ,        7,      8,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62815         {"SP_LS"                       ,        15,     2,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62816         {"EMIP"                        ,        17,     1,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62817         {"NCCS"                        ,        18,     1,      503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62818         {"PS_NUM"                      ,        19,     13,     503,    "RO/WRSL",      0,      0,      0ull,   0ull},
62819         {"ABP_EN"                      ,        0,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
62820         {"PF_EN"                       ,        1,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
62821         {"MRLS_EN"                     ,        2,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
62822         {"PD_EN"                       ,        3,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
62823         {"CCINT_EN"                    ,        4,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
62824         {"HPINT_EN"                    ,        5,      1,      504,    "R/W",  0,      0,      0ull,   0ull},
62825         {"AIC"                         ,        6,      2,      504,    "R/W",  0,      0,      0ull,   0ull},
62826         {"PIC"                         ,        8,      2,      504,    "R/W",  0,      0,      0ull,   0ull},
62827         {"PCC"                         ,        10,     1,      504,    "R/W",  0,      0,      0ull,   0ull},
62828         {"EMIC"                        ,        11,     1,      504,    "R/W",  0,      0,      0ull,   0ull},
62829         {"DLLS_EN"                     ,        12,     1,      504,    "RO",   0,      0,      0ull,   0ull},
62830         {"RESERVED_13_15"              ,        13,     3,      504,    "RAZ",  1,      1,      0,      0},
62831         {"ABP_D"                       ,        16,     1,      504,    "R/W1C",        0,      0,      0ull,   0ull},
62832         {"PF_D"                        ,        17,     1,      504,    "R/W1C",        0,      0,      0ull,   0ull},
62833         {"MRLS_C"                      ,        18,     1,      504,    "R/W1C",        0,      0,      0ull,   0ull},
62834         {"PD_C"                        ,        19,     1,      504,    "R/W1C",        0,      0,      0ull,   0ull},
62835         {"CCINT_D"                     ,        20,     1,      504,    "R/W1C",        0,      0,      0ull,   0ull},
62836         {"MRLSS"                       ,        21,     1,      504,    "RO",   0,      0,      0ull,   0ull},
62837         {"PDS"                         ,        22,     1,      504,    "RO",   0,      0,      0ull,   0ull},
62838         {"EMIS"                        ,        23,     1,      504,    "RO",   0,      0,      0ull,   0ull},
62839         {"DLLS_C"                      ,        24,     1,      504,    "RO",   0,      0,      0ull,   0ull},
62840         {"RESERVED_25_31"              ,        25,     7,      504,    "RAZ",  1,      1,      0,      0},
62841         {"CTRS"                        ,        0,      4,      505,    "RO",   0,      0,      0ull,   0ull},
62842         {"CTDS"                        ,        4,      1,      505,    "RO",   0,      0,      1ull,   1ull},
62843         {"RESERVED_5_31"               ,        5,      27,     505,    "RAZ",  1,      1,      0,      0},
62844         {"CTV"                         ,        0,      4,      506,    "RO",   0,      0,      0ull,   0ull},
62845         {"CTD"                         ,        4,      1,      506,    "R/W",  0,      0,      0ull,   0ull},
62846         {"RESERVED_5_31"               ,        5,      27,     506,    "RAZ",  1,      1,      0,      0},
62847         {"RESERVED_0_31"               ,        0,      32,     507,    "RAZ",  1,      1,      0,      0},
62848         {"RESERVED_0_31"               ,        0,      32,     508,    "RAZ",  1,      1,      0,      0},
62849         {"RESERVED_0_31"               ,        0,      32,     509,    "RAZ",  1,      1,      0,      0},
62850         {"RESERVED_0_31"               ,        0,      32,     510,    "RAZ",  1,      1,      0,      0},
62851         {"PCIEEC"                      ,        0,      16,     511,    "RO",   0,      0,      1ull,   0ull},
62852         {"CV"                          ,        16,     4,      511,    "RO",   0,      0,      1ull,   0ull},
62853         {"NCO"                         ,        20,     12,     511,    "RO",   0,      0,      0ull,   0ull},
62854         {"RESERVED_0_3"                ,        0,      4,      512,    "RAZ",  1,      1,      0,      0},
62855         {"DLPES"                       ,        4,      1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62856         {"SDES"                        ,        5,      1,      512,    "RO",   0,      0,      0ull,   0ull},
62857         {"RESERVED_6_11"               ,        6,      6,      512,    "RAZ",  1,      1,      0,      0},
62858         {"PTLPS"                       ,        12,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62859         {"FCPES"                       ,        13,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62860         {"CTS"                         ,        14,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62861         {"CAS"                         ,        15,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62862         {"UCS"                         ,        16,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62863         {"ROS"                         ,        17,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62864         {"MTLPS"                       ,        18,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62865         {"ECRCES"                      ,        19,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62866         {"URES"                        ,        20,     1,      512,    "R/W1C",        0,      0,      0ull,   0ull},
62867         {"RESERVED_21_31"              ,        21,     11,     512,    "RAZ",  1,      1,      0,      0},
62868         {"RESERVED_0_3"                ,        0,      4,      513,    "RAZ",  1,      1,      0,      0},
62869         {"DLPEM"                       ,        4,      1,      513,    "R/W",  0,      0,      0ull,   0ull},
62870         {"SDEM"                        ,        5,      1,      513,    "RO",   0,      0,      0ull,   0ull},
62871         {"RESERVED_6_11"               ,        6,      6,      513,    "RAZ",  1,      1,      0,      0},
62872         {"PTLPM"                       ,        12,     1,      513,    "R/W",  0,      0,      0ull,   0ull},
62873         {"FCPEM"                       ,        13,     1,      513,    "R/W",  0,      0,      0ull,   0ull},
62874         {"CTM"                         ,        14,     1,      513,    "R/W",  0,      0,      0ull,   0ull},
62875         {"CAM"                         ,        15,     1,      513,    "R/W",  0,      0,      0ull,   0ull},
62876         {"UCM"                         ,        16,     1,      513,    "R/W",  0,      0,      0ull,   0ull},
62877         {"ROM"                         ,        17,     1,      513,    "R/W",  0,      0,      0ull,   0ull},
62878         {"MTLPM"                       ,        18,     1,      513,    "R/W",  0,      0,      0ull,   0ull},
62879         {"ECRCEM"                      ,        19,     1,      513,    "R/W",  0,      0,      0ull,   0ull},
62880         {"UREM"                        ,        20,     1,      513,    "R/W",  0,      0,      0ull,   0ull},
62881         {"RESERVED_21_31"              ,        21,     11,     513,    "RAZ",  1,      1,      0,      0},
62882         {"RESERVED_0_3"                ,        0,      4,      514,    "RAZ",  1,      1,      0,      0},
62883         {"DLPES"                       ,        4,      1,      514,    "R/W",  0,      0,      1ull,   1ull},
62884         {"SDES"                        ,        5,      1,      514,    "RO",   0,      0,      1ull,   1ull},
62885         {"RESERVED_6_11"               ,        6,      6,      514,    "RAZ",  1,      1,      0,      0},
62886         {"PTLPS"                       ,        12,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
62887         {"FCPES"                       ,        13,     1,      514,    "R/W",  0,      0,      1ull,   1ull},
62888         {"CTS"                         ,        14,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
62889         {"CAS"                         ,        15,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
62890         {"UCS"                         ,        16,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
62891         {"ROS"                         ,        17,     1,      514,    "R/W",  0,      0,      1ull,   1ull},
62892         {"MTLPS"                       ,        18,     1,      514,    "R/W",  0,      0,      1ull,   1ull},
62893         {"ECRCES"                      ,        19,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
62894         {"URES"                        ,        20,     1,      514,    "R/W",  0,      0,      0ull,   0ull},
62895         {"RESERVED_21_31"              ,        21,     11,     514,    "RAZ",  1,      1,      0,      0},
62896         {"RES"                         ,        0,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
62897         {"RESERVED_1_5"                ,        1,      5,      515,    "RAZ",  1,      1,      0,      0},
62898         {"BTLPS"                       ,        6,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
62899         {"BDLLPS"                      ,        7,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
62900         {"RNRS"                        ,        8,      1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
62901         {"RESERVED_9_11"               ,        9,      3,      515,    "RAZ",  1,      1,      0,      0},
62902         {"RTTS"                        ,        12,     1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
62903         {"ANFES"                       ,        13,     1,      515,    "R/W1C",        0,      0,      0ull,   0ull},
62904         {"RESERVED_14_31"              ,        14,     18,     515,    "RAZ",  1,      1,      0,      0},
62905         {"REM"                         ,        0,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
62906         {"RESERVED_1_5"                ,        1,      5,      516,    "RAZ",  1,      1,      0,      0},
62907         {"BTLPM"                       ,        6,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
62908         {"BDLLPM"                      ,        7,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
62909         {"RNRM"                        ,        8,      1,      516,    "R/W",  0,      0,      0ull,   0ull},
62910         {"RESERVED_9_11"               ,        9,      3,      516,    "RAZ",  1,      1,      0,      0},
62911         {"RTTM"                        ,        12,     1,      516,    "R/W",  0,      0,      0ull,   0ull},
62912         {"ANFEM"                       ,        13,     1,      516,    "R/W",  0,      0,      1ull,   1ull},
62913         {"RESERVED_14_31"              ,        14,     18,     516,    "RAZ",  1,      1,      0,      0},
62914         {"FEP"                         ,        0,      5,      517,    "RO",   0,      0,      0ull,   0ull},
62915         {"GC"                          ,        5,      1,      517,    "RO",   0,      0,      1ull,   1ull},
62916         {"GE"                          ,        6,      1,      517,    "R/W",  0,      0,      0ull,   0ull},
62917         {"CC"                          ,        7,      1,      517,    "RO",   0,      0,      1ull,   1ull},
62918         {"CE"                          ,        8,      1,      517,    "R/W",  0,      0,      0ull,   0ull},
62919         {"RESERVED_9_31"               ,        9,      23,     517,    "RAZ",  1,      1,      0,      0},
62920         {"DWORD1"                      ,        0,      32,     518,    "RO",   0,      0,      0ull,   0ull},
62921         {"DWORD2"                      ,        0,      32,     519,    "RO",   0,      0,      0ull,   0ull},
62922         {"DWORD3"                      ,        0,      32,     520,    "RO",   0,      0,      0ull,   0ull},
62923         {"DWORD4"                      ,        0,      32,     521,    "RO",   0,      0,      0ull,   0ull},
62924         {"RTLTL"                       ,        0,      16,     522,    "R/W",  0,      0,      4143ull,        4143ull},
62925         {"RTL"                         ,        16,     16,     522,    "R/W",  0,      0,      12429ull,       12429ull},
62926         {"OMR"                         ,        0,      32,     523,    "R/W",  0,      1,      4294967295ull,  0},
62927         {"LINK_NUM"                    ,        0,      8,      524,    "RO",   0,      0,      0ull,   0ull},
62928         {"RESERVED_8_14"               ,        8,      7,      524,    "RAZ",  1,      1,      0,      0},
62929         {"FORCE_LINK"                  ,        15,     1,      524,    "R/W",  0,      0,      0ull,   0ull},
62930         {"LINK_STATE"                  ,        16,     6,      524,    "R/W",  0,      0,      0ull,   0ull},
62931         {"RESERVED_22_23"              ,        22,     2,      524,    "RAZ",  1,      1,      0,      0},
62932         {"LPEC"                        ,        24,     8,      524,    "R/W",  0,      0,      7ull,   7ull},
62933         {"ACK_FREQ"                    ,        0,      8,      525,    "R/W",  0,      0,      0ull,   0ull},
62934         {"N_FTS"                       ,        8,      8,      525,    "R/W",  0,      0,      128ull, 128ull},
62935         {"N_FTS_CC"                    ,        16,     8,      525,    "R/W",  0,      0,      128ull, 128ull},
62936         {"L0EL"                        ,        24,     3,      525,    "R/W",  0,      0,      3ull,   3ull},
62937         {"L1EL"                        ,        27,     3,      525,    "R/W",  0,      0,      3ull,   3ull},
62938         {"RESERVED_30_31"              ,        30,     2,      525,    "RAZ",  1,      1,      0,      0},
62939         {"OMR"                         ,        0,      1,      526,    "R/W",  0,      0,      0ull,   0ull},
62940         {"SD"                          ,        1,      1,      526,    "R/W",  0,      0,      0ull,   0ull},
62941         {"LE"                          ,        2,      1,      526,    "R/W",  0,      0,      0ull,   0ull},
62942         {"RA"                          ,        3,      1,      526,    "R/W",  0,      0,      0ull,   0ull},
62943         {"RESERVED_4_4"                ,        4,      1,      526,    "RAZ",  1,      1,      0,      0},
62944         {"DLLLE"                       ,        5,      1,      526,    "R/W",  0,      0,      1ull,   1ull},
62945         {"RESERVED_6_6"                ,        6,      1,      526,    "RAZ",  1,      1,      0,      0},
62946         {"FLM"                         ,        7,      1,      526,    "R/W",  0,      0,      0ull,   0ull},
62947         {"RESERVED_8_15"               ,        8,      8,      526,    "RO",   0,      0,      1ull,   1ull},
62948         {"LME"                         ,        16,     6,      526,    "R/W",  0,      0,      7ull,   7ull},
62949         {"RESERVED_22_24"              ,        22,     3,      526,    "RAZ",  1,      1,      0,      0},
62950         {"ECCRC"                       ,        25,     1,      526,    "R/W",  0,      0,      0ull,   0ull},
62951         {"RESERVED_26_31"              ,        26,     6,      526,    "RAZ",  1,      1,      0,      0},
62952         {"ILST"                        ,        0,      24,     527,    "R/W",  0,      0,      0ull,   0ull},
62953         {"FCD"                         ,        24,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
62954         {"ACK_NAK"                     ,        25,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
62955         {"RESERVED_26_30"              ,        26,     5,      527,    "RAZ",  1,      1,      0,      0},
62956         {"DLLD"                        ,        31,     1,      527,    "R/W",  0,      0,      0ull,   0ull},
62957         {"NTSS"                        ,        0,      4,      528,    "R/W",  0,      0,      10ull,  10ull},
62958         {"RESERVED_4_7"                ,        4,      4,      528,    "RO",   1,      1,      0,      0},
62959         {"NSKPS"                       ,        8,      3,      528,    "R/W",  0,      0,      3ull,   3ull},
62960         {"RESERVED_11_13"              ,        11,     3,      528,    "RAZ",  1,      1,      0,      0},
62961         {"TMRT"                        ,        14,     5,      528,    "R/W",  0,      0,      8ull,   8ull},
62962         {"TMANLT"                      ,        19,     5,      528,    "R/W",  0,      0,      0ull,   0ull},
62963         {"TMFCWT"                      ,        24,     5,      528,    "R/W",  0,      0,      0ull,   0ull},
62964         {"RESERVED_29_31"              ,        29,     3,      528,    "RO",   1,      1,      0,      0},
62965         {"SKPIV"                       ,        0,      11,     529,    "R/W",  0,      0,      1280ull,        1280ull},
62966         {"RESERVED_11_14"              ,        11,     4,      529,    "RAZ",  1,      1,      0,      0},
62967         {"DFCWT"                       ,        15,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62968         {"M_FUN"                       ,        16,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62969         {"M_POIS_FILT"                 ,        17,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62970         {"M_BAR_MATCH"                 ,        18,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62971         {"M_CFG1_FILT"                 ,        19,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62972         {"M_LK_FILT"                   ,        20,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62973         {"M_CPL_TAG_ERR"               ,        21,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62974         {"M_CPL_RID_ERR"               ,        22,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62975         {"M_CPL_FUN_ERR"               ,        23,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62976         {"M_CPL_TC_ERR"                ,        24,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62977         {"M_CPL_ATTR_ERR"              ,        25,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62978         {"M_CPL_LEN_ERR"               ,        26,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62979         {"M_ECRC_FILT"                 ,        27,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62980         {"M_CPL_ECRC_FILT"             ,        28,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62981         {"MSG_CTRL"                    ,        29,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62982         {"M_IO_FILT"                   ,        30,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62983         {"M_CFG0_FILT"                 ,        31,     1,      529,    "R/W",  0,      0,      0ull,   0ull},
62984         {"M_VEND0_DRP"                 ,        0,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
62985         {"M_VEND1_DRP"                 ,        1,      1,      530,    "R/W",  0,      0,      0ull,   0ull},
62986         {"RESERVED_2_31"               ,        2,      30,     530,    "RAZ",  1,      1,      0,      0},
62987         {"DBG_INFO_L32"                ,        0,      32,     531,    "RO",   0,      0,      0ull,   0ull},
62988         {"DBG_INFO_U32"                ,        0,      32,     532,    "RO",   0,      0,      0ull,   0ull},
62989         {"TPDFCC"                      ,        0,      12,     533,    "RO",   0,      0,      0ull,   0ull},
62990         {"TPHFCC"                      ,        12,     8,      533,    "RO",   0,      0,      0ull,   0ull},
62991         {"RESERVED_20_31"              ,        20,     12,     533,    "RAZ",  1,      1,      0,      0},
62992         {"TCDFCC"                      ,        0,      12,     534,    "RO",   0,      0,      0ull,   0ull},
62993         {"TCHFCC"                      ,        12,     8,      534,    "RO",   0,      0,      0ull,   0ull},
62994         {"RESERVED_20_31"              ,        20,     12,     534,    "RAZ",  1,      1,      0,      0},
62995         {"TCDFCC"                      ,        0,      12,     535,    "RO",   0,      0,      0ull,   0ull},
62996         {"TCHFCC"                      ,        12,     8,      535,    "RO",   0,      0,      0ull,   0ull},
62997         {"RESERVED_20_31"              ,        20,     12,     535,    "RAZ",  1,      1,      0,      0},
62998         {"RTLPFCCNR"                   ,        0,      1,      536,    "RO",   0,      0,      0ull,   0ull},
62999         {"TRBNE"                       ,        1,      1,      536,    "RO",   0,      0,      0ull,   0ull},
63000         {"RQNE"                        ,        2,      1,      536,    "RO",   0,      0,      0ull,   0ull},
63001         {"RESERVED_3_31"               ,        3,      29,     536,    "RAZ",  1,      1,      0,      0},
63002         {"WRR_VC0"                     ,        0,      8,      537,    "RO",   0,      0,      15ull,  15ull},
63003         {"WRR_VC1"                     ,        8,      8,      537,    "RO",   0,      0,      0ull,   0ull},
63004         {"WRR_VC2"                     ,        16,     8,      537,    "RO",   0,      0,      0ull,   0ull},
63005         {"WRR_VC3"                     ,        24,     8,      537,    "RO",   0,      0,      0ull,   0ull},
63006         {"WRR_VC4"                     ,        0,      8,      538,    "RO",   0,      0,      0ull,   0ull},
63007         {"WRR_VC5"                     ,        8,      8,      538,    "RO",   0,      0,      0ull,   0ull},
63008         {"WRR_VC6"                     ,        16,     8,      538,    "RO",   0,      0,      0ull,   0ull},
63009         {"WRR_VC7"                     ,        24,     8,      538,    "RO",   0,      0,      0ull,   0ull},
63010         {"DATA_CREDITS"                ,        0,      12,     539,    "RO/WRSL",      0,      0,      72ull,  72ull},
63011         {"HEADER_CREDITS"              ,        12,     8,      539,    "RO/WRSL",      0,      0,      32ull,  32ull},
63012         {"RESERVED_20_20"              ,        20,     1,      539,    "RAZ",  1,      1,      0,      0},
63013         {"QUEUE_MODE"                  ,        21,     3,      539,    "RO/WRSL",      0,      0,      2ull,   2ull},
63014         {"RESERVED_24_29"              ,        24,     6,      539,    "RAZ",  1,      1,      0,      0},
63015         {"TYPE_ORDERING"               ,        30,     1,      539,    "RO/WRSL",      0,      0,      1ull,   1ull},
63016         {"RX_QUEUE_ORDER"              ,        31,     1,      539,    "RO/WRSL",      0,      0,      0ull,   0ull},
63017         {"DATA_CREDITS"                ,        0,      12,     540,    "RO/WRSL",      0,      0,      4ull,   4ull},
63018         {"HEADER_CREDITS"              ,        12,     8,      540,    "RO/WRSL",      0,      0,      8ull,   8ull},
63019         {"RESERVED_20_20"              ,        20,     1,      540,    "RAZ",  1,      1,      0,      0},
63020         {"QUEUE_MODE"                  ,        21,     3,      540,    "RO/WRSL",      0,      0,      2ull,   2ull},
63021         {"RESERVED_24_31"              ,        24,     8,      540,    "RAZ",  1,      1,      0,      0},
63022         {"DATA_CREDITS"                ,        0,      12,     541,    "RO/WRSL",      0,      0,      0ull,   0ull},
63023         {"HEADER_CREDITS"              ,        12,     8,      541,    "RO/WRSL",      0,      0,      0ull,   0ull},
63024         {"RESERVED_20_20"              ,        20,     1,      541,    "RAZ",  1,      1,      0,      0},
63025         {"QUEUE_MODE"                  ,        21,     3,      541,    "RO/WRSL",      0,      0,      2ull,   2ull},
63026         {"RESERVED_24_31"              ,        24,     8,      541,    "RAZ",  1,      1,      0,      0},
63027         {"DATA_DEPTH"                  ,        0,      14,     542,    "RO/WRSL",      0,      0,      216ull, 216ull},
63028         {"RESERVED_14_15"              ,        14,     2,      542,    "RAZ",  1,      1,      0,      0},
63029         {"HEADER_DEPTH"                ,        16,     10,     542,    "RO/WRSL",      0,      0,      38ull,  38ull},
63030         {"RESERVED_26_31"              ,        26,     6,      542,    "RAZ",  1,      1,      0,      0},
63031         {"DATA_DEPTH"                  ,        0,      14,     543,    "RO/WRSL",      0,      0,      56ull,  56ull},
63032         {"RESERVED_14_15"              ,        14,     2,      543,    "RAZ",  1,      1,      0,      0},
63033         {"HEADER_DEPTH"                ,        16,     10,     543,    "RO/WRSL",      0,      0,      14ull,  14ull},
63034         {"RESERVED_26_31"              ,        26,     6,      543,    "RAZ",  1,      1,      0,      0},
63035         {"DATA_DEPTH"                  ,        0,      14,     544,    "RO/WRSL",      0,      0,      360ull, 360ull},
63036         {"RESERVED_14_15"              ,        14,     2,      544,    "RAZ",  1,      1,      0,      0},
63037         {"HEADER_DEPTH"                ,        16,     10,     544,    "RO/WRSL",      0,      0,      70ull,  70ull},
63038         {"RESERVED_26_31"              ,        26,     6,      544,    "RAZ",  1,      1,      0,      0},
63039         {"PHY_STAT"                    ,        0,      32,     545,    "RO",   0,      0,      0ull,   0ull},
63040         {"PHY_CTRL"                    ,        0,      32,     546,    "R/W",  0,      0,      0ull,   0ull},
63041         {"VENDID"                      ,        0,      16,     547,    "R/W",  0,      0,      6013ull,        6013ull},
63042         {"DEVID"                       ,        16,     16,     547,    "R/W",  0,      0,      128ull, 128ull},
63043         {"ISAE"                        ,        0,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
63044         {"MSAE"                        ,        1,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
63045         {"ME"                          ,        2,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
63046         {"SCSE"                        ,        3,      1,      548,    "RO",   0,      0,      0ull,   0ull},
63047         {"MWICE"                       ,        4,      1,      548,    "RO",   0,      0,      0ull,   0ull},
63048         {"VPS"                         ,        5,      1,      548,    "RO",   0,      0,      0ull,   0ull},
63049         {"PER"                         ,        6,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
63050         {"IDS_WCC"                     ,        7,      1,      548,    "RO",   0,      0,      0ull,   0ull},
63051         {"SEE"                         ,        8,      1,      548,    "R/W",  0,      0,      0ull,   0ull},
63052         {"FBBE"                        ,        9,      1,      548,    "RO",   0,      0,      0ull,   0ull},
63053         {"I_DIS"                       ,        10,     1,      548,    "R/W",  0,      0,      0ull,   0ull},
63054         {"RESERVED_11_18"              ,        11,     8,      548,    "RAZ",  1,      1,      0,      0},
63055         {"I_STAT"                      ,        19,     1,      548,    "RO",   0,      0,      0ull,   0ull},
63056         {"CL"                          ,        20,     1,      548,    "RO",   0,      0,      1ull,   1ull},
63057         {"M66"                         ,        21,     1,      548,    "RO",   0,      0,      0ull,   0ull},
63058         {"RESERVED_22_22"              ,        22,     1,      548,    "RO",   1,      1,      0,      0},
63059         {"FBB"                         ,        23,     1,      548,    "RO",   0,      0,      0ull,   0ull},
63060         {"MDPE"                        ,        24,     1,      548,    "R/W1C",        0,      0,      0ull,   0ull},
63061         {"DEVT"                        ,        25,     2,      548,    "RO",   0,      0,      0ull,   0ull},
63062         {"STA"                         ,        27,     1,      548,    "R/W1C",        0,      0,      0ull,   0ull},
63063         {"RTA"                         ,        28,     1,      548,    "R/W1C",        0,      0,      0ull,   0ull},
63064         {"RMA"                         ,        29,     1,      548,    "R/W1C",        0,      0,      0ull,   0ull},
63065         {"SSE"                         ,        30,     1,      548,    "R/W1C",        0,      0,      0ull,   0ull},
63066         {"DPE"                         ,        31,     1,      548,    "R/W1C",        0,      0,      0ull,   0ull},
63067         {"RID"                         ,        0,      8,      549,    "R/W",  0,      0,      0ull,   0ull},
63068         {"PI"                          ,        8,      8,      549,    "R/W",  0,      0,      0ull,   0ull},
63069         {"SC"                          ,        16,     8,      549,    "R/W",  0,      0,      48ull,  48ull},
63070         {"BCC"                         ,        24,     8,      549,    "R/W",  0,      0,      11ull,  11ull},
63071         {"CLS"                         ,        0,      8,      550,    "R/W",  0,      0,      0ull,   0ull},
63072         {"LT"                          ,        8,      8,      550,    "RO",   0,      0,      0ull,   0ull},
63073         {"CHF"                         ,        16,     7,      550,    "RO",   0,      0,      1ull,   1ull},
63074         {"MFD"                         ,        23,     1,      550,    "R/W",  0,      0,      0ull,   0ull},
63075         {"BIST"                        ,        24,     8,      550,    "RO",   0,      0,      0ull,   0ull},
63076         {"RESERVED_0_31"               ,        0,      32,     551,    "RO",   1,      1,      0,      0},
63077         {"RESERVED_0_31"               ,        0,      32,     552,    "RO",   1,      1,      0,      0},
63078         {"PBNUM"                       ,        0,      8,      553,    "R/W",  0,      0,      0ull,   0ull},
63079         {"SBNUM"                       ,        8,      8,      553,    "R/W",  0,      0,      0ull,   0ull},
63080         {"SUBBNUM"                     ,        16,     8,      553,    "R/W",  0,      0,      0ull,   0ull},
63081         {"SLT"                         ,        24,     8,      553,    "RO",   0,      0,      0ull,   0ull},
63082         {"IO32A"                       ,        0,      1,      554,    "R/W",  0,      0,      1ull,   1ull},
63083         {"RESERVED_1_3"                ,        1,      3,      554,    "RAZ",  0,      0,      0ull,   0ull},
63084         {"LIO_BASE"                    ,        4,      4,      554,    "R/W",  0,      0,      0ull,   0ull},
63085         {"IO32B"                       ,        8,      1,      554,    "RO",   0,      0,      1ull,   1ull},
63086         {"RESERVED_9_11"               ,        9,      3,      554,    "RAZ",  0,      0,      0ull,   0ull},
63087         {"LIO_LIMI"                    ,        12,     4,      554,    "R/W",  0,      0,      0ull,   0ull},
63088         {"RESERVED_16_20"              ,        16,     5,      554,    "RAZ",  1,      1,      0,      0},
63089         {"M66"                         ,        21,     1,      554,    "RO",   0,      0,      0ull,   0ull},
63090         {"RESERVED_22_22"              ,        22,     1,      554,    "RO",   1,      1,      0,      0},
63091         {"FBB"                         ,        23,     1,      554,    "RO",   0,      0,      0ull,   0ull},
63092         {"MDPE"                        ,        24,     1,      554,    "R/W1C",        0,      0,      0ull,   0ull},
63093         {"DEVT"                        ,        25,     2,      554,    "RO",   0,      0,      0ull,   0ull},
63094         {"STA"                         ,        27,     1,      554,    "R/W1C",        0,      0,      0ull,   0ull},
63095         {"RTA"                         ,        28,     1,      554,    "R/W1C",        0,      0,      0ull,   0ull},
63096         {"RMA"                         ,        29,     1,      554,    "R/W1C",        0,      0,      0ull,   0ull},
63097         {"SSE"                         ,        30,     1,      554,    "R/W1C",        0,      0,      0ull,   0ull},
63098         {"DPE"                         ,        31,     1,      554,    "R/W1C",        0,      0,      0ull,   0ull},
63099         {"RESERVED_0_3"                ,        0,      4,      555,    "RO",   1,      1,      0,      0},
63100         {"MB_ADDR"                     ,        4,      12,     555,    "R/W",  0,      0,      0ull,   0ull},
63101         {"RESERVED_16_19"              ,        16,     4,      555,    "RO",   1,      1,      0,      0},
63102         {"ML_ADDR"                     ,        20,     12,     555,    "R/W",  0,      0,      0ull,   0ull},
63103         {"MEM64A"                      ,        0,      1,      556,    "R/W",  0,      0,      1ull,   1ull},
63104         {"RESERVED_1_3"                ,        1,      3,      556,    "RO",   1,      1,      0,      0},
63105         {"LMEM_BASE"                   ,        4,      12,     556,    "R/W",  0,      0,      0ull,   0ull},
63106         {"MEM64B"                      ,        16,     1,      556,    "RO",   0,      0,      1ull,   1ull},
63107         {"RESERVED_17_19"              ,        17,     3,      556,    "RO",   1,      1,      0,      0},
63108         {"LMEM_LIMIT"                  ,        20,     12,     556,    "R/W",  0,      0,      0ull,   0ull},
63109         {"UMEM_BASE"                   ,        0,      32,     557,    "R/W",  0,      0,      0ull,   0ull},
63110         {"UMEM_LIMIT"                  ,        0,      32,     558,    "R/W",  0,      0,      0ull,   0ull},
63111         {"UIO_BASE"                    ,        0,      16,     559,    "R/W",  0,      0,      0ull,   0ull},
63112         {"UIO_LIMIT"                   ,        16,     16,     559,    "R/W",  0,      0,      0ull,   0ull},
63113         {"CP"                          ,        0,      8,      560,    "R/W",  0,      0,      64ull,  64ull},
63114         {"RESERVED_8_31"               ,        8,      24,     560,    "RAZ",  1,      1,      0,      0},
63115         {"RESERVED_0_31"               ,        0,      32,     561,    "RAZ",  1,      1,      0,      0},
63116         {"IL"                          ,        0,      8,      562,    "R/W",  0,      0,      255ull, 255ull},
63117         {"INTA"                        ,        8,      8,      562,    "R/W",  0,      0,      1ull,   1ull},
63118         {"PERE"                        ,        16,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
63119         {"SEE"                         ,        17,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
63120         {"ISAE"                        ,        18,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
63121         {"VGAE"                        ,        19,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
63122         {"VGA16D"                      ,        20,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
63123         {"MAM"                         ,        21,     1,      562,    "RO",   0,      0,      0ull,   0ull},
63124         {"SBRST"                       ,        22,     1,      562,    "R/W",  0,      0,      0ull,   0ull},
63125         {"FBBE"                        ,        23,     1,      562,    "RO",   0,      0,      0ull,   0ull},
63126         {"PDT"                         ,        24,     1,      562,    "RO",   0,      0,      0ull,   0ull},
63127         {"SDT"                         ,        25,     1,      562,    "RO",   0,      0,      0ull,   0ull},
63128         {"DTS"                         ,        26,     1,      562,    "RO",   0,      0,      0ull,   0ull},
63129         {"DTSEES"                      ,        27,     1,      562,    "RO",   0,      0,      0ull,   0ull},
63130         {"RESERVED_28_31"              ,        28,     4,      562,    "RO",   1,      1,      0,      0},
63131         {"PMCID"                       ,        0,      8,      563,    "RO",   0,      0,      1ull,   1ull},
63132         {"NCP"                         ,        8,      8,      563,    "R/W",  0,      0,      80ull,  80ull},
63133         {"PMSV"                        ,        16,     3,      563,    "R/W",  0,      0,      3ull,   3ull},
63134         {"PME_CLOCK"                   ,        19,     1,      563,    "RO",   0,      0,      0ull,   0ull},
63135         {"RESERVED_20_20"              ,        20,     1,      563,    "RAZ",  1,      1,      0,      0},
63136         {"DSI"                         ,        21,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
63137         {"AUXC"                        ,        22,     3,      563,    "R/W",  0,      0,      0ull,   0ull},
63138         {"D1S"                         ,        25,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
63139         {"D2S"                         ,        26,     1,      563,    "R/W",  0,      0,      0ull,   0ull},
63140         {"PMES"                        ,        27,     5,      563,    "R/W",  0,      0,      0ull,   0ull},
63141         {"PS"                          ,        0,      2,      564,    "R/W",  0,      0,      0ull,   0ull},
63142         {"RESERVED_2_2"                ,        2,      1,      564,    "RAZ",  1,      1,      0,      0},
63143         {"NSR"                         ,        3,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
63144         {"RESERVED_4_7"                ,        4,      4,      564,    "RAZ",  1,      1,      0,      0},
63145         {"PMEENS"                      ,        8,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
63146         {"PMDS"                        ,        9,      4,      564,    "RO",   0,      0,      0ull,   0ull},
63147         {"PMEDSIA"                     ,        13,     2,      564,    "RO",   0,      0,      0ull,   0ull},
63148         {"PMESS"                       ,        15,     1,      564,    "R/W1C",        0,      0,      0ull,   0ull},
63149         {"RESERVED_16_21"              ,        16,     6,      564,    "RAZ",  1,      1,      0,      0},
63150         {"BD3H"                        ,        22,     1,      564,    "RO",   0,      0,      0ull,   0ull},
63151         {"BPCCEE"                      ,        23,     1,      564,    "RO",   0,      0,      0ull,   0ull},
63152         {"PMDIA"                       ,        24,     8,      564,    "RO",   0,      0,      0ull,   0ull},
63153         {"MSICID"                      ,        0,      8,      565,    "RO",   0,      0,      5ull,   5ull},
63154         {"NCP"                         ,        8,      8,      565,    "R/W",  0,      0,      112ull, 112ull},
63155         {"MSIEN"                       ,        16,     1,      565,    "R/W",  0,      0,      0ull,   0ull},
63156         {"MMC"                         ,        17,     3,      565,    "R/W",  0,      0,      0ull,   0ull},
63157         {"MME"                         ,        20,     3,      565,    "R/W",  0,      0,      0ull,   0ull},
63158         {"M64"                         ,        23,     1,      565,    "R/W",  0,      0,      1ull,   1ull},
63159         {"RESERVED_24_31"              ,        24,     8,      565,    "RAZ",  1,      1,      0,      0},
63160         {"RESERVED_0_1"                ,        0,      2,      566,    "RAZ",  1,      1,      0,      0},
63161         {"LMSI"                        ,        2,      30,     566,    "R/W",  0,      0,      0ull,   0ull},
63162         {"UMSI"                        ,        0,      32,     567,    "R/W",  0,      0,      0ull,   0ull},
63163         {"MSIMD"                       ,        0,      16,     568,    "R/W",  0,      0,      0ull,   0ull},
63164         {"RESERVED_16_31"              ,        16,     16,     568,    "RAZ",  1,      1,      0,      0},
63165         {"PCIEID"                      ,        0,      8,      569,    "RO",   0,      0,      16ull,  16ull},
63166         {"NCP"                         ,        8,      8,      569,    "R/W",  0,      0,      0ull,   0ull},
63167         {"PCIECV"                      ,        16,     4,      569,    "RO",   0,      0,      2ull,   2ull},
63168         {"DPT"                         ,        20,     4,      569,    "RO",   0,      0,      4ull,   4ull},
63169         {"SI"                          ,        24,     1,      569,    "R/W",  0,      0,      0ull,   0ull},
63170         {"IMN"                         ,        25,     5,      569,    "R/W",  0,      0,      0ull,   0ull},
63171         {"RESERVED_30_31"              ,        30,     2,      569,    "RAZ",  1,      1,      0,      0},
63172         {"MPSS"                        ,        0,      3,      570,    "R/W",  0,      0,      1ull,   1ull},
63173         {"PFS"                         ,        3,      2,      570,    "R/W",  0,      0,      0ull,   0ull},
63174         {"ETFS"                        ,        5,      1,      570,    "R/W",  0,      0,      0ull,   0ull},
63175         {"EL0AL"                       ,        6,      3,      570,    "R/W",  0,      0,      0ull,   0ull},
63176         {"EL1AL"                       ,        9,      3,      570,    "R/W",  0,      0,      0ull,   0ull},
63177         {"RESERVED_12_14"              ,        12,     3,      570,    "RAZ",  1,      1,      0,      0},
63178         {"RBER"                        ,        15,     1,      570,    "R/W",  0,      0,      1ull,   1ull},
63179         {"RESERVED_16_17"              ,        16,     2,      570,    "RAZ",  1,      1,      0,      0},
63180         {"CSPLV"                       ,        18,     8,      570,    "RO",   0,      0,      0ull,   0ull},
63181         {"CSPLS"                       ,        26,     2,      570,    "RO",   0,      0,      0ull,   0ull},
63182         {"RESERVED_28_31"              ,        28,     4,      570,    "RAZ",  1,      1,      0,      0},
63183         {"CE_EN"                       ,        0,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
63184         {"NFE_EN"                      ,        1,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
63185         {"FE_EN"                       ,        2,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
63186         {"UR_EN"                       ,        3,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
63187         {"RO_EN"                       ,        4,      1,      571,    "R/W",  0,      0,      1ull,   1ull},
63188         {"MPS"                         ,        5,      3,      571,    "R/W",  0,      0,      0ull,   0ull},
63189         {"ETF_EN"                      ,        8,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
63190         {"PF_EN"                       ,        9,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
63191         {"AP_EN"                       ,        10,     1,      571,    "R/W",  0,      0,      0ull,   0ull},
63192         {"NS_EN"                       ,        11,     1,      571,    "R/W",  0,      0,      1ull,   1ull},
63193         {"MRRS"                        ,        12,     3,      571,    "R/W",  0,      0,      2ull,   2ull},
63194         {"RESERVED_15_15"              ,        15,     1,      571,    "RAZ",  1,      1,      0,      0},
63195         {"CE_D"                        ,        16,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
63196         {"NFE_D"                       ,        17,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
63197         {"FE_D"                        ,        18,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
63198         {"UR_D"                        ,        19,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
63199         {"AP_D"                        ,        20,     1,      571,    "RO",   0,      0,      0ull,   0ull},
63200         {"TP"                          ,        21,     1,      571,    "RO",   0,      0,      0ull,   0ull},
63201         {"RESERVED_22_31"              ,        22,     10,     571,    "RAZ",  1,      1,      0,      0},
63202         {"MLS"                         ,        0,      4,      572,    "R/W",  0,      0,      1ull,   1ull},
63203         {"MLW"                         ,        4,      6,      572,    "R/W",  0,      0,      8ull,   8ull},
63204         {"ASLPMS"                      ,        10,     2,      572,    "R/W",  0,      0,      3ull,   3ull},
63205         {"L0EL"                        ,        12,     3,      572,    "R/W",  0,      0,      6ull,   6ull},
63206         {"L1EL"                        ,        15,     3,      572,    "R/W",  0,      0,      6ull,   6ull},
63207         {"CPM"                         ,        18,     1,      572,    "R/W",  0,      0,      0ull,   0ull},
63208         {"SDERC"                       ,        19,     1,      572,    "RO",   0,      0,      0ull,   0ull},
63209         {"DLLARC"                      ,        20,     1,      572,    "RO",   0,      0,      1ull,   1ull},
63210         {"LBNC"                        ,        21,     1,      572,    "RO",   0,      0,      1ull,   1ull},
63211         {"RESERVED_22_23"              ,        22,     2,      572,    "RAZ",  1,      1,      0,      0},
63212         {"PNUM"                        ,        24,     8,      572,    "R/W",  0,      0,      0ull,   0ull},
63213         {"ASLPC"                       ,        0,      2,      573,    "R/W",  0,      0,      0ull,   0ull},
63214         {"RESERVED_2_2"                ,        2,      1,      573,    "RAZ",  1,      1,      0,      0},
63215         {"RCB"                         ,        3,      1,      573,    "R/W",  0,      0,      1ull,   1ull},
63216         {"LD"                          ,        4,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
63217         {"RL"                          ,        5,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
63218         {"CCC"                         ,        6,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
63219         {"ES"                          ,        7,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
63220         {"ECPM"                        ,        8,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
63221         {"HAWD"                        ,        9,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
63222         {"LBM_INT_ENB"                 ,        10,     1,      573,    "R/W",  0,      0,      0ull,   0ull},
63223         {"LAB_INT_ENB"                 ,        11,     1,      573,    "R/W",  0,      0,      0ull,   0ull},
63224         {"RESERVED_12_15"              ,        12,     4,      573,    "RAZ",  1,      1,      0,      0},
63225         {"LS"                          ,        16,     4,      573,    "RO",   0,      0,      1ull,   1ull},
63226         {"NLW"                         ,        20,     6,      573,    "RO",   0,      0,      0ull,   0ull},
63227         {"RESERVED_26_26"              ,        26,     1,      573,    "RAZ",  1,      1,      0,      0},
63228         {"LT"                          ,        27,     1,      573,    "RO",   0,      0,      0ull,   0ull},
63229         {"SCC"                         ,        28,     1,      573,    "R/W",  0,      0,      1ull,   0ull},
63230         {"DLLA"                        ,        29,     1,      573,    "RO",   0,      0,      0ull,   1ull},
63231         {"LBM"                         ,        30,     1,      573,    "R/W1C",        0,      0,      0ull,   0ull},
63232         {"LAB"                         ,        31,     1,      573,    "R/W1C",        0,      0,      0ull,   0ull},
63233         {"ABP"                         ,        0,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
63234         {"PCP"                         ,        1,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
63235         {"MRLSP"                       ,        2,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
63236         {"AIP"                         ,        3,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
63237         {"PIP"                         ,        4,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
63238         {"HP_S"                        ,        5,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
63239         {"HP_C"                        ,        6,      1,      574,    "R/W",  0,      0,      0ull,   0ull},
63240         {"SP_LV"                       ,        7,      8,      574,    "R/W",  0,      0,      0ull,   0ull},
63241         {"SP_LS"                       ,        15,     2,      574,    "R/W",  0,      0,      0ull,   0ull},
63242         {"EMIP"                        ,        17,     1,      574,    "R/W",  0,      0,      0ull,   0ull},
63243         {"NCCS"                        ,        18,     1,      574,    "R/W",  0,      0,      0ull,   0ull},
63244         {"PS_NUM"                      ,        19,     13,     574,    "R/W",  0,      0,      0ull,   0ull},
63245         {"ABP_EN"                      ,        0,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
63246         {"PF_EN"                       ,        1,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
63247         {"MRLS_EN"                     ,        2,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
63248         {"PD_EN"                       ,        3,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
63249         {"CCINT_EN"                    ,        4,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
63250         {"HPINT_EN"                    ,        5,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
63251         {"AIC"                         ,        6,      2,      575,    "R/W",  0,      0,      3ull,   3ull},
63252         {"PIC"                         ,        8,      2,      575,    "R/W",  0,      0,      3ull,   3ull},
63253         {"PCC"                         ,        10,     1,      575,    "R/W",  0,      0,      0ull,   0ull},
63254         {"EMIC"                        ,        11,     1,      575,    "R/W",  0,      0,      0ull,   0ull},
63255         {"DLLS_EN"                     ,        12,     1,      575,    "R/W",  0,      0,      0ull,   0ull},
63256         {"RESERVED_13_15"              ,        13,     3,      575,    "RAZ",  1,      1,      0,      0},
63257         {"ABP_D"                       ,        16,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
63258         {"PF_D"                        ,        17,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
63259         {"MRLS_C"                      ,        18,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
63260         {"PD_C"                        ,        19,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
63261         {"CCINT_D"                     ,        20,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
63262         {"MRLSS"                       ,        21,     1,      575,    "RO",   0,      0,      0ull,   0ull},
63263         {"PDS"                         ,        22,     1,      575,    "RO",   0,      0,      1ull,   1ull},
63264         {"EMIS"                        ,        23,     1,      575,    "RO",   0,      0,      0ull,   0ull},
63265         {"DLLS_C"                      ,        24,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
63266         {"RESERVED_25_31"              ,        25,     7,      575,    "RAZ",  1,      1,      0,      0},
63267         {"SECEE"                       ,        0,      1,      576,    "R/W",  0,      0,      0ull,   0ull},
63268         {"SENFEE"                      ,        1,      1,      576,    "R/W",  0,      0,      0ull,   0ull},
63269         {"SEFEE"                       ,        2,      1,      576,    "R/W",  0,      0,      0ull,   0ull},
63270         {"PMEIE"                       ,        3,      1,      576,    "R/W",  0,      0,      0ull,   0ull},
63271         {"CRSSVE"                      ,        4,      1,      576,    "RO",   0,      0,      0ull,   0ull},
63272         {"RESERVED_5_15"               ,        5,      11,     576,    "RAZ",  1,      1,      0,      0},
63273         {"CRSSV"                       ,        16,     1,      576,    "RO",   0,      0,      0ull,   0ull},
63274         {"RESERVED_17_31"              ,        17,     15,     576,    "RAZ",  1,      1,      0,      0},
63275         {"PME_RID"                     ,        0,      16,     577,    "RO",   0,      0,      0ull,   0ull},
63276         {"PME_STAT"                    ,        16,     1,      577,    "R/W1C",        0,      0,      0ull,   0ull},
63277         {"PME_PEND"                    ,        17,     1,      577,    "RO",   0,      0,      0ull,   0ull},
63278         {"RESERVED_18_31"              ,        18,     14,     577,    "RAZ",  0,      0,      0ull,   0ull},
63279         {"CTRS"                        ,        0,      4,      578,    "RO",   0,      0,      0ull,   0ull},
63280         {"CTDS"                        ,        4,      1,      578,    "RO",   0,      0,      1ull,   1ull},
63281         {"RESERVED_5_31"               ,        5,      27,     578,    "RAZ",  1,      1,      0,      0},
63282         {"CTV"                         ,        0,      4,      579,    "RO",   0,      0,      0ull,   0ull},
63283         {"CTD"                         ,        4,      1,      579,    "R/W",  0,      0,      0ull,   0ull},
63284         {"RESERVED_5_31"               ,        5,      27,     579,    "RAZ",  1,      1,      0,      0},
63285         {"RESERVED_0_31"               ,        0,      32,     580,    "RAZ",  1,      1,      0,      0},
63286         {"RESERVED_0_31"               ,        0,      32,     581,    "RAZ",  1,      1,      0,      0},
63287         {"RESERVED_0_31"               ,        0,      32,     582,    "RAZ",  1,      1,      0,      0},
63288         {"RESERVED_0_31"               ,        0,      32,     583,    "RAZ",  1,      1,      0,      0},
63289         {"PCIEEC"                      ,        0,      16,     584,    "RO",   0,      0,      1ull,   1ull},
63290         {"CV"                          ,        16,     4,      584,    "RO",   0,      0,      1ull,   1ull},
63291         {"NCO"                         ,        20,     12,     584,    "RO",   0,      0,      0ull,   0ull},
63292         {"RESERVED_0_3"                ,        0,      4,      585,    "RAZ",  1,      1,      0,      0},
63293         {"DLPES"                       ,        4,      1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63294         {"SDES"                        ,        5,      1,      585,    "RO",   0,      0,      0ull,   0ull},
63295         {"RESERVED_6_11"               ,        6,      6,      585,    "RAZ",  1,      1,      0,      0},
63296         {"PTLPS"                       ,        12,     1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63297         {"FCPES"                       ,        13,     1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63298         {"CTS"                         ,        14,     1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63299         {"CAS"                         ,        15,     1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63300         {"UCS"                         ,        16,     1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63301         {"ROS"                         ,        17,     1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63302         {"MTLPS"                       ,        18,     1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63303         {"ECRCES"                      ,        19,     1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63304         {"URES"                        ,        20,     1,      585,    "R/W1C",        0,      0,      0ull,   0ull},
63305         {"RESERVED_21_31"              ,        21,     11,     585,    "RAZ",  1,      1,      0,      0},
63306         {"RESERVED_0_3"                ,        0,      4,      586,    "RAZ",  1,      1,      0,      0},
63307         {"DLPEM"                       ,        4,      1,      586,    "R/W",  0,      0,      0ull,   0ull},
63308         {"SDEM"                        ,        5,      1,      586,    "RO",   0,      0,      0ull,   0ull},
63309         {"RESERVED_6_11"               ,        6,      6,      586,    "RAZ",  1,      1,      0,      0},
63310         {"PTLPM"                       ,        12,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
63311         {"FCPEM"                       ,        13,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
63312         {"CTM"                         ,        14,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
63313         {"CAM"                         ,        15,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
63314         {"UCM"                         ,        16,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
63315         {"ROM"                         ,        17,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
63316         {"MTLPM"                       ,        18,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
63317         {"ECRCEM"                      ,        19,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
63318         {"UREM"                        ,        20,     1,      586,    "R/W",  0,      0,      0ull,   0ull},
63319         {"RESERVED_21_31"              ,        21,     11,     586,    "RAZ",  1,      1,      0,      0},
63320         {"RESERVED_0_3"                ,        0,      4,      587,    "RAZ",  1,      1,      0,      0},
63321         {"DLPES"                       ,        4,      1,      587,    "R/W",  0,      0,      1ull,   1ull},
63322         {"SDES"                        ,        5,      1,      587,    "RO",   0,      0,      1ull,   1ull},
63323         {"RESERVED_6_11"               ,        6,      6,      587,    "RAZ",  1,      1,      0,      0},
63324         {"PTLPS"                       ,        12,     1,      587,    "R/W",  0,      0,      0ull,   0ull},
63325         {"FCPES"                       ,        13,     1,      587,    "R/W",  0,      0,      1ull,   1ull},
63326         {"CTS"                         ,        14,     1,      587,    "R/W",  0,      0,      0ull,   0ull},
63327         {"CAS"                         ,        15,     1,      587,    "R/W",  0,      0,      0ull,   0ull},
63328         {"UCS"                         ,        16,     1,      587,    "R/W",  0,      0,      0ull,   0ull},
63329         {"ROS"                         ,        17,     1,      587,    "R/W",  0,      0,      1ull,   1ull},
63330         {"MTLPS"                       ,        18,     1,      587,    "R/W",  0,      0,      1ull,   1ull},
63331         {"ECRCES"                      ,        19,     1,      587,    "R/W",  0,      0,      0ull,   0ull},
63332         {"URES"                        ,        20,     1,      587,    "R/W",  0,      0,      0ull,   0ull},
63333         {"RESERVED_21_31"              ,        21,     11,     587,    "RAZ",  1,      1,      0,      0},
63334         {"RES"                         ,        0,      1,      588,    "R/W1C",        0,      0,      0ull,   0ull},
63335         {"RESERVED_1_5"                ,        1,      5,      588,    "RAZ",  1,      1,      0,      0},
63336         {"BTLPS"                       ,        6,      1,      588,    "R/W1C",        0,      0,      0ull,   0ull},
63337         {"BDLLPS"                      ,        7,      1,      588,    "R/W1C",        0,      0,      0ull,   0ull},
63338         {"RNRS"                        ,        8,      1,      588,    "R/W1C",        0,      0,      0ull,   0ull},
63339         {"RESERVED_9_11"               ,        9,      3,      588,    "RAZ",  1,      1,      0,      0},
63340         {"RTTS"                        ,        12,     1,      588,    "R/W1C",        0,      0,      0ull,   0ull},
63341         {"ANFES"                       ,        13,     1,      588,    "R/W1C",        0,      0,      0ull,   0ull},
63342         {"RESERVED_14_31"              ,        14,     18,     588,    "RAZ",  1,      1,      0,      0},
63343         {"REM"                         ,        0,      1,      589,    "R/W",  0,      0,      0ull,   0ull},
63344         {"RESERVED_1_5"                ,        1,      5,      589,    "RAZ",  1,      1,      0,      0},
63345         {"BTLPM"                       ,        6,      1,      589,    "R/W",  0,      0,      0ull,   0ull},
63346         {"BDLLPM"                      ,        7,      1,      589,    "R/W",  0,      0,      0ull,   0ull},
63347         {"RNRM"                        ,        8,      1,      589,    "R/W",  0,      0,      0ull,   0ull},
63348         {"RESERVED_9_11"               ,        9,      3,      589,    "RAZ",  1,      1,      0,      0},
63349         {"RTTM"                        ,        12,     1,      589,    "R/W",  0,      0,      0ull,   0ull},
63350         {"ANFEM"                       ,        13,     1,      589,    "R/W",  0,      0,      1ull,   1ull},
63351         {"RESERVED_14_31"              ,        14,     18,     589,    "RAZ",  1,      1,      0,      0},
63352         {"FEP"                         ,        0,      5,      590,    "RO",   0,      0,      0ull,   0ull},
63353         {"GC"                          ,        5,      1,      590,    "RO",   0,      0,      1ull,   1ull},
63354         {"GE"                          ,        6,      1,      590,    "R/W",  0,      0,      0ull,   0ull},
63355         {"CC"                          ,        7,      1,      590,    "RO",   0,      0,      1ull,   1ull},
63356         {"CE"                          ,        8,      1,      590,    "R/W",  0,      0,      0ull,   0ull},
63357         {"RESERVED_9_31"               ,        9,      23,     590,    "RAZ",  1,      1,      0,      0},
63358         {"DWORD1"                      ,        0,      32,     591,    "RO",   0,      0,      0ull,   0ull},
63359         {"DWORD2"                      ,        0,      32,     592,    "RO",   0,      0,      0ull,   0ull},
63360         {"DWORD3"                      ,        0,      32,     593,    "RO",   0,      0,      0ull,   0ull},
63361         {"DWORD4"                      ,        0,      32,     594,    "RO",   0,      0,      0ull,   0ull},
63362         {"CERE"                        ,        0,      1,      595,    "R/W",  0,      0,      0ull,   0ull},
63363         {"NFERE"                       ,        1,      1,      595,    "R/W",  0,      0,      0ull,   0ull},
63364         {"FERE"                        ,        2,      1,      595,    "R/W",  0,      0,      0ull,   0ull},
63365         {"RESERVED_3_31"               ,        3,      29,     595,    "RAZ",  1,      1,      0,      0},
63366         {"ECR"                         ,        0,      1,      596,    "R/W1C",        0,      0,      0ull,   0ull},
63367         {"MULTI_ECR"                   ,        1,      1,      596,    "R/W1C",        0,      0,      0ull,   0ull},
63368         {"EFNFR"                       ,        2,      1,      596,    "R/W1C",        0,      0,      0ull,   0ull},
63369         {"MULTI_EFNFR"                 ,        3,      1,      596,    "R/W1C",        0,      0,      0ull,   0ull},
63370         {"FUF"                         ,        4,      1,      596,    "R/W1C",        0,      0,      0ull,   0ull},
63371         {"NFEMR"                       ,        5,      1,      596,    "R/W1C",        0,      0,      0ull,   0ull},
63372         {"FEMR"                        ,        6,      1,      596,    "R/W1C",        0,      0,      0ull,   0ull},
63373         {"RESERVED_7_26"               ,        7,      20,     596,    "RAZ",  1,      1,      0,      0},
63374         {"AEIMN"                       ,        27,     5,      596,    "R/W",  0,      0,      0ull,   0ull},
63375         {"ECSI"                        ,        0,      16,     597,    "RO",   0,      0,      0ull,   0ull},
63376         {"EFNFSI"                      ,        16,     16,     597,    "RO",   0,      0,      0ull,   0ull},
63377         {"RTLTL"                       ,        0,      16,     598,    "R/W",  0,      0,      4143ull,        4143ull},
63378         {"RTL"                         ,        16,     16,     598,    "R/W",  0,      0,      12429ull,       12429ull},
63379         {"OMR"                         ,        0,      32,     599,    "R/W",  0,      1,      4294967295ull,  0},
63380         {"LINK_NUM"                    ,        0,      8,      600,    "R/W",  0,      0,      4ull,   4ull},
63381         {"RESERVED_8_14"               ,        8,      7,      600,    "RAZ",  1,      1,      0,      0},
63382         {"FORCE_LINK"                  ,        15,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
63383         {"LINK_STATE"                  ,        16,     6,      600,    "R/W",  0,      0,      0ull,   0ull},
63384         {"RESERVED_22_23"              ,        22,     2,      600,    "RAZ",  1,      1,      0,      0},
63385         {"LPEC"                        ,        24,     8,      600,    "RO",   0,      0,      7ull,   7ull},
63386         {"ACK_FREQ"                    ,        0,      8,      601,    "R/W",  0,      0,      0ull,   0ull},
63387         {"N_FTS"                       ,        8,      8,      601,    "R/W",  0,      0,      128ull, 128ull},
63388         {"N_FTS_CC"                    ,        16,     8,      601,    "R/W",  0,      0,      128ull, 128ull},
63389         {"L0EL"                        ,        24,     3,      601,    "R/W",  0,      0,      3ull,   3ull},
63390         {"L1EL"                        ,        27,     3,      601,    "R/W",  0,      0,      3ull,   3ull},
63391         {"RESERVED_30_31"              ,        30,     2,      601,    "RAZ",  1,      1,      0,      0},
63392         {"OMR"                         ,        0,      1,      602,    "R/W",  0,      0,      0ull,   0ull},
63393         {"SD"                          ,        1,      1,      602,    "R/W",  0,      0,      0ull,   0ull},
63394         {"LE"                          ,        2,      1,      602,    "R/W",  0,      0,      0ull,   0ull},
63395         {"RA"                          ,        3,      1,      602,    "R/W",  0,      0,      0ull,   0ull},
63396         {"RESERVED_4_4"                ,        4,      1,      602,    "RAZ",  1,      1,      0,      0},
63397         {"DLLLE"                       ,        5,      1,      602,    "R/W",  0,      0,      1ull,   1ull},
63398         {"RESERVED_6_6"                ,        6,      1,      602,    "RAZ",  1,      1,      0,      0},
63399         {"FLM"                         ,        7,      1,      602,    "R/W",  0,      0,      0ull,   0ull},
63400         {"RESERVED_8_15"               ,        8,      8,      602,    "RO",   0,      0,      1ull,   1ull},
63401         {"LME"                         ,        16,     6,      602,    "R/W",  0,      0,      15ull,  15ull},
63402         {"RESERVED_22_24"              ,        22,     3,      602,    "RAZ",  1,      1,      0,      0},
63403         {"ECCRC"                       ,        25,     1,      602,    "R/W",  0,      0,      0ull,   0ull},
63404         {"RESERVED_26_31"              ,        26,     6,      602,    "RAZ",  1,      1,      0,      0},
63405         {"ILST"                        ,        0,      24,     603,    "R/W",  0,      0,      0ull,   0ull},
63406         {"FCD"                         ,        24,     1,      603,    "R/W",  0,      0,      0ull,   0ull},
63407         {"ACK_NAK"                     ,        25,     1,      603,    "R/W",  0,      0,      0ull,   0ull},
63408         {"RESERVED_26_30"              ,        26,     5,      603,    "RAZ",  1,      1,      0,      0},
63409         {"DLLD"                        ,        31,     1,      603,    "R/W",  0,      0,      0ull,   0ull},
63410         {"NTSS"                        ,        0,      4,      604,    "R/W",  0,      0,      10ull,  10ull},
63411         {"RESERVED_4_7"                ,        4,      4,      604,    "RO",   1,      1,      0,      0},
63412         {"NSKPS"                       ,        8,      3,      604,    "R/W",  0,      0,      3ull,   3ull},
63413         {"RESERVED_11_13"              ,        11,     3,      604,    "RAZ",  1,      1,      0,      0},
63414         {"TMRT"                        ,        14,     5,      604,    "R/W",  0,      0,      8ull,   8ull},
63415         {"TMANLT"                      ,        19,     5,      604,    "R/W",  0,      0,      0ull,   0ull},
63416         {"TMFCWT"                      ,        24,     5,      604,    "R/W",  0,      0,      0ull,   0ull},
63417         {"RESERVED_29_31"              ,        29,     3,      604,    "RO",   1,      1,      0,      0},
63418         {"SKPIV"                       ,        0,      11,     605,    "R/W",  0,      0,      1280ull,        1280ull},
63419         {"RESERVED_11_14"              ,        11,     4,      605,    "RAZ",  1,      1,      0,      0},
63420         {"DFCWT"                       ,        15,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63421         {"M_FUN"                       ,        16,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63422         {"M_POIS_FILT"                 ,        17,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63423         {"M_BAR_MATCH"                 ,        18,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63424         {"M_CFG1_FILT"                 ,        19,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63425         {"M_LK_FILT"                   ,        20,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63426         {"M_CPL_TAG_ERR"               ,        21,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63427         {"M_CPL_RID_ERR"               ,        22,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63428         {"M_CPL_FUN_ERR"               ,        23,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63429         {"M_CPL_TC_ERR"                ,        24,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63430         {"M_CPL_ATTR_ERR"              ,        25,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63431         {"M_CPL_LEN_ERR"               ,        26,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63432         {"M_ECRC_FILT"                 ,        27,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63433         {"M_CPL_ECRC_FILT"             ,        28,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63434         {"MSG_CTRL"                    ,        29,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63435         {"M_IO_FILT"                   ,        30,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63436         {"M_CFG0_FILT"                 ,        31,     1,      605,    "R/W",  0,      0,      0ull,   0ull},
63437         {"M_VEND0_DRP"                 ,        0,      1,      606,    "R/W",  0,      0,      0ull,   0ull},
63438         {"M_VEND1_DRP"                 ,        1,      1,      606,    "R/W",  0,      0,      0ull,   0ull},
63439         {"RESERVED_2_31"               ,        2,      30,     606,    "RAZ",  1,      1,      0,      0},
63440         {"DBG_INFO_L32"                ,        0,      32,     607,    "RO",   0,      0,      0ull,   0ull},
63441         {"DBG_INFO_U32"                ,        0,      32,     608,    "RO",   0,      0,      0ull,   0ull},
63442         {"TPDFCC"                      ,        0,      12,     609,    "RO",   0,      0,      0ull,   0ull},
63443         {"TPHFCC"                      ,        12,     8,      609,    "RO",   0,      0,      0ull,   0ull},
63444         {"RESERVED_20_31"              ,        20,     12,     609,    "RAZ",  1,      1,      0,      0},
63445         {"TCDFCC"                      ,        0,      12,     610,    "RO",   0,      0,      0ull,   0ull},
63446         {"TCHFCC"                      ,        12,     8,      610,    "RO",   0,      0,      0ull,   0ull},
63447         {"RESERVED_20_31"              ,        20,     12,     610,    "RAZ",  1,      1,      0,      0},
63448         {"TCDFCC"                      ,        0,      12,     611,    "RO",   0,      0,      0ull,   0ull},
63449         {"TCHFCC"                      ,        12,     8,      611,    "RO",   0,      0,      0ull,   0ull},
63450         {"RESERVED_20_31"              ,        20,     12,     611,    "RAZ",  1,      1,      0,      0},
63451         {"RTLPFCCNR"                   ,        0,      1,      612,    "RO",   0,      0,      0ull,   0ull},
63452         {"TRBNE"                       ,        1,      1,      612,    "RO",   0,      0,      0ull,   0ull},
63453         {"RQNE"                        ,        2,      1,      612,    "RO",   0,      0,      0ull,   0ull},
63454         {"RESERVED_3_31"               ,        3,      29,     612,    "RAZ",  1,      1,      0,      0},
63455         {"WRR_VC0"                     ,        0,      8,      613,    "RO",   0,      0,      15ull,  15ull},
63456         {"WRR_VC1"                     ,        8,      8,      613,    "RO",   0,      0,      0ull,   0ull},
63457         {"WRR_VC2"                     ,        16,     8,      613,    "RO",   0,      0,      0ull,   0ull},
63458         {"WRR_VC3"                     ,        24,     8,      613,    "RO",   0,      0,      0ull,   0ull},
63459         {"WRR_VC4"                     ,        0,      8,      614,    "RO",   0,      0,      0ull,   0ull},
63460         {"WRR_VC5"                     ,        8,      8,      614,    "RO",   0,      0,      0ull,   0ull},
63461         {"WRR_VC6"                     ,        16,     8,      614,    "RO",   0,      0,      0ull,   0ull},
63462         {"WRR_VC7"                     ,        24,     8,      614,    "RO",   0,      0,      0ull,   0ull},
63463         {"DATA_CREDITS"                ,        0,      12,     615,    "R/W",  0,      0,      72ull,  72ull},
63464         {"HEADER_CREDITS"              ,        12,     8,      615,    "R/W",  0,      0,      32ull,  32ull},
63465         {"RESERVED_20_20"              ,        20,     1,      615,    "RAZ",  1,      1,      0,      0},
63466         {"QUEUE_MODE"                  ,        21,     3,      615,    "R/W",  0,      0,      2ull,   2ull},
63467         {"RESERVED_24_29"              ,        24,     6,      615,    "RAZ",  1,      1,      0,      0},
63468         {"TYPE_ORDERING"               ,        30,     1,      615,    "R/W",  0,      0,      1ull,   1ull},
63469         {"RX_QUEUE_ORDER"              ,        31,     1,      615,    "R/W",  0,      0,      0ull,   0ull},
63470         {"DATA_CREDITS"                ,        0,      12,     616,    "R/W",  0,      0,      4ull,   4ull},
63471         {"HEADER_CREDITS"              ,        12,     8,      616,    "R/W",  0,      0,      8ull,   8ull},
63472         {"RESERVED_20_20"              ,        20,     1,      616,    "RAZ",  1,      1,      0,      0},
63473         {"QUEUE_MODE"                  ,        21,     3,      616,    "R/W",  0,      0,      2ull,   2ull},
63474         {"RESERVED_24_31"              ,        24,     8,      616,    "RAZ",  1,      1,      0,      0},
63475         {"DATA_CREDITS"                ,        0,      12,     617,    "R/W",  0,      0,      128ull, 128ull},
63476         {"HEADER_CREDITS"              ,        12,     8,      617,    "R/W",  0,      0,      64ull,  64ull},
63477         {"RESERVED_20_20"              ,        20,     1,      617,    "RAZ",  1,      1,      0,      0},
63478         {"QUEUE_MODE"                  ,        21,     3,      617,    "R/W",  0,      0,      2ull,   2ull},
63479         {"RESERVED_24_31"              ,        24,     8,      617,    "RAZ",  1,      1,      0,      0},
63480         {"DATA_DEPTH"                  ,        0,      14,     618,    "R/W",  0,      0,      216ull, 216ull},
63481         {"RESERVED_14_15"              ,        14,     2,      618,    "RAZ",  1,      1,      0,      0},
63482         {"HEADER_DEPTH"                ,        16,     10,     618,    "R/W",  0,      0,      38ull,  38ull},
63483         {"RESERVED_26_31"              ,        26,     6,      618,    "RAZ",  1,      1,      0,      0},
63484         {"DATA_DEPTH"                  ,        0,      14,     619,    "R/W",  0,      0,      56ull,  56ull},
63485         {"RESERVED_14_15"              ,        14,     2,      619,    "RAZ",  1,      1,      0,      0},
63486         {"HEADER_DEPTH"                ,        16,     10,     619,    "R/W",  0,      0,      14ull,  14ull},
63487         {"RESERVED_26_31"              ,        26,     6,      619,    "RAZ",  1,      1,      0,      0},
63488         {"DATA_DEPTH"                  ,        0,      14,     620,    "R/W",  0,      0,      360ull, 360ull},
63489         {"RESERVED_14_15"              ,        14,     2,      620,    "RAZ",  1,      1,      0,      0},
63490         {"HEADER_DEPTH"                ,        16,     10,     620,    "R/W",  0,      0,      70ull,  70ull},
63491         {"RESERVED_26_31"              ,        26,     6,      620,    "RAZ",  1,      1,      0,      0},
63492         {"PHY_STAT"                    ,        0,      32,     621,    "RO",   0,      0,      0ull,   0ull},
63493         {"PHY_CTRL"                    ,        0,      32,     622,    "R/W",  0,      0,      0ull,   0ull},
63494         {"RESERVED_0_4"                ,        0,      5,      623,    "RAZ",  0,      0,      0ull,   0ull},
63495         {"FD"                          ,        5,      1,      623,    "R/W",  0,      0,      1ull,   1ull},
63496         {"HFD"                         ,        6,      1,      623,    "R/W",  0,      0,      1ull,   1ull},
63497         {"PAUSE"                       ,        7,      2,      623,    "R/W",  0,      0,      0ull,   0ull},
63498         {"RESERVED_9_11"               ,        9,      3,      623,    "RAZ",  0,      0,      0ull,   0ull},
63499         {"REM_FLT"                     ,        12,     2,      623,    "R/W",  0,      0,      0ull,   0ull},
63500         {"RESERVED_14_14"              ,        14,     1,      623,    "RAZ",  0,      0,      0ull,   0ull},
63501         {"NP"                          ,        15,     1,      623,    "RO",   0,      0,      0ull,   0ull},
63502         {"RESERVED_16_63"              ,        16,     48,     623,    "RAZ",  1,      1,      0,      0},
63503         {"RESERVED_0_11"               ,        0,      12,     624,    "RAZ",  0,      0,      0ull,   0ull},
63504         {"THOU_THD"                    ,        12,     1,      624,    "RO",   0,      0,      0ull,   0ull},
63505         {"THOU_TFD"                    ,        13,     1,      624,    "RO",   0,      0,      0ull,   0ull},
63506         {"THOU_XHD"                    ,        14,     1,      624,    "RO",   0,      0,      1ull,   1ull},
63507         {"THOU_XFD"                    ,        15,     1,      624,    "RO",   0,      0,      1ull,   1ull},
63508         {"RESERVED_16_63"              ,        16,     48,     624,    "RAZ",  1,      1,      0,      0},
63509         {"RESERVED_0_4"                ,        0,      5,      625,    "RAZ",  0,      0,      0ull,   0ull},
63510         {"FD"                          ,        5,      1,      625,    "RO",   0,      0,      0ull,   0ull},
63511         {"HFD"                         ,        6,      1,      625,    "RO",   0,      0,      0ull,   0ull},
63512         {"PAUSE"                       ,        7,      2,      625,    "RO",   0,      0,      0ull,   0ull},
63513         {"RESERVED_9_11"               ,        9,      3,      625,    "RAZ",  0,      0,      0ull,   0ull},
63514         {"REM_FLT"                     ,        12,     2,      625,    "RO",   0,      0,      0ull,   0ull},
63515         {"ACK"                         ,        14,     1,      625,    "RO",   0,      1,      0ull,   0},
63516         {"NP"                          ,        15,     1,      625,    "RO",   0,      0,      0ull,   0ull},
63517         {"RESERVED_16_63"              ,        16,     48,     625,    "RAZ",  1,      1,      0,      0},
63518         {"LINK_OK"                     ,        0,      1,      626,    "RO",   0,      0,      0ull,   0ull},
63519         {"DUP"                         ,        1,      1,      626,    "RO",   0,      0,      0ull,   0ull},
63520         {"AN_CPT"                      ,        2,      1,      626,    "RO",   0,      0,      0ull,   1ull},
63521         {"SPD"                         ,        3,      2,      626,    "RO",   0,      0,      0ull,   0ull},
63522         {"PAUSE"                       ,        5,      2,      626,    "RO",   0,      0,      0ull,   0ull},
63523         {"RESERVED_7_63"               ,        7,      57,     626,    "RAZ",  1,      1,      0,      0},
63524         {"LNKSPD_EN"                   ,        0,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63525         {"XMIT_EN"                     ,        1,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63526         {"AN_ERR_EN"                   ,        2,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63527         {"TXFIFU_EN"                   ,        3,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63528         {"TXFIFO_EN"                   ,        4,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63529         {"TXBAD_EN"                    ,        5,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63530         {"RXERR_EN"                    ,        6,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63531         {"RXBAD_EN"                    ,        7,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63532         {"RXLOCK_EN"                   ,        8,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63533         {"AN_BAD_EN"                   ,        9,      1,      627,    "R/W",  0,      0,      0ull,   1ull},
63534         {"SYNC_BAD_EN"                 ,        10,     1,      627,    "R/W",  0,      0,      0ull,   1ull},
63535         {"DUP"                         ,        11,     1,      627,    "R/W",  0,      0,      0ull,   1ull},
63536         {"RESERVED_12_63"              ,        12,     52,     627,    "RAZ",  1,      1,      0,      0},
63537         {"LNKSPD"                      ,        0,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63538         {"XMIT"                        ,        1,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63539         {"AN_ERR"                      ,        2,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63540         {"TXFIFU"                      ,        3,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63541         {"TXFIFO"                      ,        4,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63542         {"TXBAD"                       ,        5,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63543         {"RXERR"                       ,        6,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63544         {"RXBAD"                       ,        7,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63545         {"RXLOCK"                      ,        8,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63546         {"AN_BAD"                      ,        9,      1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63547         {"SYNC_BAD"                    ,        10,     1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63548         {"DUP"                         ,        11,     1,      628,    "R/W1C",        0,      0,      0ull,   0ull},
63549         {"RESERVED_12_63"              ,        12,     52,     628,    "RAZ",  1,      1,      0,      0},
63550         {"COUNT"                       ,        0,      16,     629,    "R/W",  0,      1,      1094ull,        0},
63551         {"RESERVED_16_63"              ,        16,     48,     629,    "RAZ",  1,      1,      0,      0},
63552         {"PKT_SZ"                      ,        0,      2,      630,    "R/W",  0,      0,      0ull,   0ull},
63553         {"LA_EN"                       ,        2,      1,      630,    "R/W",  0,      0,      0ull,   0ull},
63554         {"LAFIFOVFL"                   ,        3,      1,      630,    "R/W1C",        0,      0,      0ull,   0ull},
63555         {"RESERVED_4_63"               ,        4,      60,     630,    "RAZ",  1,      1,      0,      0},
63556         {"SAMP_PT"                     ,        0,      7,      631,    "R/W",  0,      1,      1ull,   0},
63557         {"AN_OVRD"                     ,        7,      1,      631,    "R/W",  0,      0,      0ull,   0ull},
63558         {"MODE"                        ,        8,      1,      631,    "R/W",  0,      0,      0ull,   0ull},
63559         {"MAC_PHY"                     ,        9,      1,      631,    "R/W",  0,      0,      0ull,   0ull},
63560         {"LOOPBCK2"                    ,        10,     1,      631,    "R/W",  0,      0,      0ull,   0ull},
63561         {"GMXENO"                      ,        11,     1,      631,    "R/W",  0,      0,      0ull,   0ull},
63562         {"SGMII"                       ,        12,     1,      631,    "RO",   1,      1,      0,      0},
63563         {"RESERVED_13_63"              ,        13,     51,     631,    "RAZ",  1,      1,      0,      0},
63564         {"RESERVED_0_4"                ,        0,      5,      632,    "RAZ",  1,      1,      0,      0},
63565         {"UNI"                         ,        5,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
63566         {"SPDMSB"                      ,        6,      1,      632,    "R/W",  0,      0,      1ull,   1ull},
63567         {"COLTST"                      ,        7,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
63568         {"DUP"                         ,        8,      1,      632,    "R/W",  0,      0,      1ull,   1ull},
63569         {"RST_AN"                      ,        9,      1,      632,    "R/W",  0,      0,      0ull,   0ull},
63570         {"RESERVED_10_10"              ,        10,     1,      632,    "RAZ",  1,      1,      0,      0},
63571         {"PWR_DN"                      ,        11,     1,      632,    "R/W",  0,      0,      1ull,   0ull},
63572         {"AN_EN"                       ,        12,     1,      632,    "R/W",  0,      0,      0ull,   0ull},
63573         {"SPDLSB"                      ,        13,     1,      632,    "R/W",  0,      0,      0ull,   0ull},
63574         {"LOOPBCK1"                    ,        14,     1,      632,    "R/W",  0,      0,      0ull,   0ull},
63575         {"RESET"                       ,        15,     1,      632,    "R/W",  0,      0,      0ull,   0ull},
63576         {"RESERVED_16_63"              ,        16,     48,     632,    "RAZ",  1,      1,      0,      0},
63577         {"EXTND"                       ,        0,      1,      633,    "RO",   0,      0,      0ull,   0ull},
63578         {"RESERVED_1_1"                ,        1,      1,      633,    "RAZ",  0,      0,      0ull,   0ull},
63579         {"LNK_ST"                      ,        2,      1,      633,    "RO",   0,      0,      0ull,   1ull},
63580         {"AN_ABIL"                     ,        3,      1,      633,    "RO",   0,      0,      1ull,   1ull},
63581         {"RM_FLT"                      ,        4,      1,      633,    "RO",   0,      0,      0ull,   0ull},
63582         {"AN_CPT"                      ,        5,      1,      633,    "RO",   0,      0,      0ull,   0ull},
63583         {"PRB_SUP"                     ,        6,      1,      633,    "RO",   0,      0,      1ull,   1ull},
63584         {"RESERVED_7_7"                ,        7,      1,      633,    "RAZ",  0,      0,      0ull,   0ull},
63585         {"EXT_ST"                      ,        8,      1,      633,    "RO",   0,      0,      1ull,   1ull},
63586         {"HUN_T2HD"                    ,        9,      1,      633,    "RO",   0,      0,      0ull,   0ull},
63587         {"HUN_T2FD"                    ,        10,     1,      633,    "RO",   0,      0,      0ull,   0ull},
63588         {"TEN_HD"                      ,        11,     1,      633,    "RO",   0,      0,      0ull,   0ull},
63589         {"TEN_FD"                      ,        12,     1,      633,    "RO",   0,      0,      0ull,   0ull},
63590         {"HUN_XHD"                     ,        13,     1,      633,    "RO",   0,      0,      0ull,   0ull},
63591         {"HUN_XFD"                     ,        14,     1,      633,    "RO",   0,      0,      0ull,   0ull},
63592         {"HUN_T4"                      ,        15,     1,      633,    "RO",   0,      0,      0ull,   0ull},
63593         {"RESERVED_16_63"              ,        16,     48,     633,    "RAZ",  1,      1,      0,      0},
63594         {"AN_ST"                       ,        0,      4,      634,    "RO",   0,      0,      0ull,   0ull},
63595         {"AN_BAD"                      ,        4,      1,      634,    "RO",   0,      0,      0ull,   0ull},
63596         {"SYNC"                        ,        5,      4,      634,    "RO",   0,      0,      0ull,   0ull},
63597         {"SYNC_BAD"                    ,        9,      1,      634,    "RO",   0,      0,      0ull,   0ull},
63598         {"RX_ST"                       ,        10,     5,      634,    "RO",   0,      0,      0ull,   0ull},
63599         {"RX_BAD"                      ,        15,     1,      634,    "RO",   0,      0,      0ull,   0ull},
63600         {"RESERVED_16_63"              ,        16,     48,     634,    "RAZ",  1,      1,      0,      0},
63601         {"BIT_LOCK"                    ,        0,      1,      635,    "RO",   0,      0,      0ull,   0ull},
63602         {"SYNC"                        ,        1,      1,      635,    "RO",   0,      0,      0ull,   0ull},
63603         {"RESERVED_2_63"               ,        2,      62,     635,    "RAZ",  1,      1,      0,      0},
63604         {"ONE"                         ,        0,      1,      636,    "RO",   0,      0,      1ull,   1ull},
63605         {"RESERVED_1_9"                ,        1,      9,      636,    "RAZ",  0,      1,      0ull,   0},
63606         {"SPEED"                       ,        10,     2,      636,    "R/W",  0,      0,      2ull,   2ull},
63607         {"DUP"                         ,        12,     1,      636,    "R/W",  0,      0,      1ull,   1ull},
63608         {"RESERVED_13_13"              ,        13,     1,      636,    "RAZ",  0,      1,      0ull,   0},
63609         {"ACK"                         ,        14,     1,      636,    "RO",   0,      0,      0ull,   0ull},
63610         {"LINK"                        ,        15,     1,      636,    "R/W",  0,      0,      0ull,   1ull},
63611         {"RESERVED_16_63"              ,        16,     48,     636,    "RAZ",  1,      1,      0,      0},
63612         {"ONE"                         ,        0,      1,      637,    "RO",   0,      0,      1ull,   1ull},
63613         {"RESERVED_1_9"                ,        1,      9,      637,    "RAZ",  0,      1,      0ull,   0},
63614         {"SPEED"                       ,        10,     2,      637,    "RO",   0,      0,      0ull,   2ull},
63615         {"DUP"                         ,        12,     1,      637,    "RO",   0,      0,      0ull,   1ull},
63616         {"RESERVED_13_14"              ,        13,     2,      637,    "RAZ",  0,      1,      0ull,   0},
63617         {"LINK"                        ,        15,     1,      637,    "RO",   0,      0,      0ull,   1ull},
63618         {"RESERVED_16_63"              ,        16,     48,     637,    "RAZ",  1,      1,      0,      0},
63619         {"ORD_ST"                      ,        0,      4,      638,    "RO",   0,      0,      0ull,   0ull},
63620         {"TX_BAD"                      ,        4,      1,      638,    "RO",   0,      0,      0ull,   0ull},
63621         {"XMIT"                        ,        5,      2,      638,    "RO",   0,      1,      0ull,   0},
63622         {"RESERVED_7_63"               ,        7,      57,     638,    "RAZ",  1,      1,      0,      0},
63623         {"TXPLRT"                      ,        0,      1,      639,    "R/W",  0,      0,      0ull,   0ull},
63624         {"RXPLRT"                      ,        1,      1,      639,    "R/W",  0,      0,      0ull,   0ull},
63625         {"AUTORXPL"                    ,        2,      1,      639,    "RO",   0,      0,      0ull,   0ull},
63626         {"RXOVRD"                      ,        3,      1,      639,    "R/W",  0,      0,      0ull,   0ull},
63627         {"RESERVED_4_63"               ,        4,      60,     639,    "RAZ",  1,      1,      0,      0},
63628         {"L0SYNC"                      ,        0,      1,      640,    "RO",   0,      0,      0ull,   1ull},
63629         {"L1SYNC"                      ,        1,      1,      640,    "RO",   0,      0,      0ull,   1ull},
63630         {"L2SYNC"                      ,        2,      1,      640,    "RO",   0,      0,      0ull,   1ull},
63631         {"L3SYNC"                      ,        3,      1,      640,    "RO",   0,      0,      0ull,   1ull},
63632         {"RESERVED_4_10"               ,        4,      7,      640,    "RAZ",  1,      1,      0,      0},
63633         {"PATTST"                      ,        11,     1,      640,    "RO",   0,      0,      0ull,   0ull},
63634         {"ALIGND"                      ,        12,     1,      640,    "RO",   0,      0,      0ull,   1ull},
63635         {"RESERVED_13_63"              ,        13,     51,     640,    "RAZ",  1,      1,      0,      0},
63636         {"BIST_STATUS"                 ,        0,      1,      641,    "RO",   0,      0,      0ull,   0ull},
63637         {"RESERVED_1_63"               ,        1,      63,     641,    "RAZ",  1,      1,      0,      0},
63638         {"BITLCK0"                     ,        0,      1,      642,    "RO",   0,      1,      0ull,   0},
63639         {"BITLCK1"                     ,        1,      1,      642,    "RO",   0,      1,      0ull,   0},
63640         {"BITLCK2"                     ,        2,      1,      642,    "RO",   0,      1,      0ull,   0},
63641         {"BITLCK3"                     ,        3,      1,      642,    "RO",   0,      1,      0ull,   0},
63642         {"RESERVED_4_63"               ,        4,      60,     642,    "RAZ",  1,      1,      0,      0},
63643         {"RESERVED_0_1"                ,        0,      2,      643,    "RAZ",  1,      1,      0,      0},
63644         {"SPD"                         ,        2,      4,      643,    "RO",   0,      0,      0ull,   0ull},
63645         {"SPDSEL0"                     ,        6,      1,      643,    "RO",   0,      0,      1ull,   1ull},
63646         {"RESERVED_7_10"               ,        7,      4,      643,    "RAZ",  1,      1,      0,      0},
63647         {"LO_PWR"                      ,        11,     1,      643,    "R/W",  0,      0,      0ull,   0ull},
63648         {"RESERVED_12_12"              ,        12,     1,      643,    "RAZ",  1,      1,      0,      0},
63649         {"SPDSEL1"                     ,        13,     1,      643,    "RO",   0,      0,      1ull,   1ull},
63650         {"LOOPBCK1"                    ,        14,     1,      643,    "R/W",  0,      0,      0ull,   0ull},
63651         {"RESET"                       ,        15,     1,      643,    "R/W",  0,      0,      1ull,   0ull},
63652         {"RESERVED_16_63"              ,        16,     48,     643,    "RAZ",  1,      1,      0,      0},
63653         {"TYPE"                        ,        0,      2,      644,    "RO",   0,      0,      1ull,   1ull},
63654         {"RESERVED_2_63"               ,        2,      62,     644,    "RAZ",  1,      1,      0,      0},
63655         {"TXFLT_EN"                    ,        0,      1,      645,    "R/W",  0,      0,      0ull,   1ull},
63656         {"RXBAD_EN"                    ,        1,      1,      645,    "R/W",  0,      0,      0ull,   1ull},
63657         {"RXSYNBAD_EN"                 ,        2,      1,      645,    "R/W",  0,      0,      0ull,   1ull},
63658         {"BITLCKLS_EN"                 ,        3,      1,      645,    "R/W",  0,      0,      0ull,   1ull},
63659         {"SYNLOS_EN"                   ,        4,      1,      645,    "R/W",  0,      0,      0ull,   1ull},
63660         {"ALGNLOS_EN"                  ,        5,      1,      645,    "R/W",  0,      0,      0ull,   1ull},
63661         {"RESERVED_6_63"               ,        6,      58,     645,    "RAZ",  1,      1,      0,      0},
63662         {"TXFLT"                       ,        0,      1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
63663         {"RXBAD"                       ,        1,      1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
63664         {"RXSYNBAD"                    ,        2,      1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
63665         {"BITLCKLS"                    ,        3,      1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
63666         {"SYNLOS"                      ,        4,      1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
63667         {"ALGNLOS"                     ,        5,      1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
63668         {"RESERVED_6_63"               ,        6,      58,     646,    "RAZ",  1,      1,      0,      0},
63669         {"PKT_SZ"                      ,        0,      2,      647,    "R/W",  0,      0,      0ull,   0ull},
63670         {"LA_EN"                       ,        2,      1,      647,    "R/W",  0,      0,      0ull,   0ull},
63671         {"LAFIFOVFL"                   ,        3,      1,      647,    "R/W1C",        0,      0,      0ull,   0ull},
63672         {"DROP_LN"                     ,        4,      2,      647,    "R/W",  0,      0,      0ull,   0ull},
63673         {"ENC_MODE"                    ,        6,      1,      647,    "R/W",  0,      0,      0ull,   0ull},
63674         {"RESERVED_7_63"               ,        7,      57,     647,    "RAZ",  1,      1,      0,      0},
63675         {"GMXENO"                      ,        0,      1,      648,    "R/W",  0,      0,      0ull,   0ull},
63676         {"XAUI"                        ,        1,      1,      648,    "RO",   1,      1,      0,      0},
63677         {"RX_SWAP"                     ,        2,      1,      648,    "R/W",  0,      1,      0ull,   0},
63678         {"TX_SWAP"                     ,        3,      1,      648,    "R/W",  0,      1,      0ull,   0},
63679         {"RESERVED_4_63"               ,        4,      60,     648,    "RAZ",  1,      1,      0,      0},
63680         {"SYNC0ST"                     ,        0,      4,      649,    "RO",   0,      1,      0ull,   0},
63681         {"SYNC1ST"                     ,        4,      4,      649,    "RO",   0,      1,      0ull,   0},
63682         {"SYNC2ST"                     ,        8,      4,      649,    "RO",   0,      1,      0ull,   0},
63683         {"SYNC3ST"                     ,        12,     4,      649,    "RO",   0,      1,      0ull,   0},
63684         {"RESERVED_16_63"              ,        16,     48,     649,    "RAZ",  1,      1,      0,      0},
63685         {"TENGB"                       ,        0,      1,      650,    "RO",   0,      0,      1ull,   1ull},
63686         {"TENPASST"                    ,        1,      1,      650,    "RO",   0,      0,      0ull,   0ull},
63687         {"RESERVED_2_63"               ,        2,      62,     650,    "RAZ",  1,      1,      0,      0},
63688         {"RESERVED_0_0"                ,        0,      1,      651,    "RAZ",  1,      1,      0,      0},
63689         {"LPABLE"                      ,        1,      1,      651,    "RO",   0,      0,      1ull,   1ull},
63690         {"RCV_LNK"                     ,        2,      1,      651,    "RO",   0,      0,      0ull,   1ull},
63691         {"RESERVED_3_6"                ,        3,      4,      651,    "RAZ",  1,      1,      0,      0},
63692         {"FLT"                         ,        7,      1,      651,    "RO",   0,      0,      0ull,   0ull},
63693         {"RESERVED_8_63"               ,        8,      56,     651,    "RAZ",  1,      1,      0,      0},
63694         {"TENGB_R"                     ,        0,      1,      652,    "RO",   0,      0,      0ull,   0ull},
63695         {"TENGB_X"                     ,        1,      1,      652,    "RO",   0,      0,      1ull,   1ull},
63696         {"TENGB_W"                     ,        2,      1,      652,    "RO",   0,      0,      0ull,   0ull},
63697         {"RESERVED_3_9"                ,        3,      7,      652,    "RAZ",  1,      1,      0,      0},
63698         {"RCVFLT"                      ,        10,     1,      652,    "RC",   0,      0,      0ull,   0ull},
63699         {"XMTFLT"                      ,        11,     1,      652,    "RC",   0,      0,      0ull,   0ull},
63700         {"RESERVED_12_13"              ,        12,     2,      652,    "RAZ",  1,      1,      0,      0},
63701         {"DEV"                         ,        14,     2,      652,    "RO",   0,      0,      2ull,   2ull},
63702         {"RESERVED_16_63"              ,        16,     48,     652,    "RAZ",  1,      1,      0,      0},
63703         {"TXPLRT"                      ,        0,      1,      653,    "R/W",  0,      0,      0ull,   0ull},
63704         {"RXPLRT"                      ,        1,      1,      653,    "R/W",  0,      0,      0ull,   0ull},
63705         {"RESERVED_2_63"               ,        2,      62,     653,    "RAZ",  1,      1,      0,      0},
63706         {"TX_ST"                       ,        0,      3,      654,    "RO",   0,      1,      0ull,   0},
63707         {"RX_ST"                       ,        3,      2,      654,    "RO",   0,      1,      0ull,   0},
63708         {"ALGN_ST"                     ,        5,      3,      654,    "RO",   0,      1,      0ull,   0},
63709         {"RXBAD"                       ,        8,      1,      654,    "RO",   0,      0,      0ull,   0ull},
63710         {"SYN0BAD"                     ,        9,      1,      654,    "RO",   0,      0,      0ull,   0ull},
63711         {"SYN1BAD"                     ,        10,     1,      654,    "RO",   0,      0,      0ull,   0ull},
63712         {"SYN2BAD"                     ,        11,     1,      654,    "RO",   0,      0,      0ull,   0ull},
63713         {"SYN3BAD"                     ,        12,     1,      654,    "RO",   0,      0,      0ull,   0ull},
63714         {"RESERVED_13_63"              ,        13,     51,     654,    "RAZ",  1,      1,      0,      0},
63715         {"SOT"                         ,        0,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63716         {"RQHDR0"                      ,        1,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63717         {"RQHDR1"                      ,        2,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63718         {"RQDATA4"                     ,        3,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63719         {"RQDATA3"                     ,        4,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63720         {"RQDATA2"                     ,        5,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63721         {"RQDATA1"                     ,        6,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63722         {"RQDATA0"                     ,        7,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63723         {"RETRY"                       ,        8,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63724         {"PTLP_OR"                     ,        9,      1,      655,    "RO",   0,      0,      0ull,   0ull},
63725         {"NTLP_OR"                     ,        10,     1,      655,    "RO",   0,      0,      0ull,   0ull},
63726         {"CTLP_OR"                     ,        11,     1,      655,    "RO",   0,      0,      0ull,   0ull},
63727         {"RESERVED_12_63"              ,        12,     52,     655,    "RAZ",  1,      1,      0,      0},
63728         {"PPF"                         ,        0,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63729         {"PEF_TC0"                     ,        1,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63730         {"PEF_TCF1"                    ,        2,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63731         {"PEF_TNF"                     ,        3,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63732         {"PEF_TPF0"                    ,        4,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63733         {"PEF_TPF1"                    ,        5,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63734         {"RSL_P2E"                     ,        6,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63735         {"PEAI_P2E"                    ,        7,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63736         {"DBG_P2E"                     ,        8,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63737         {"E2P_RSL"                     ,        9,      1,      656,    "RO",   0,      0,      0ull,   0ull},
63738         {"E2P_P"                       ,        10,     1,      656,    "RO",   0,      0,      0ull,   0ull},
63739         {"E2P_N"                       ,        11,     1,      656,    "RO",   0,      0,      0ull,   0ull},
63740         {"E2P_CPL"                     ,        12,     1,      656,    "RO",   0,      0,      0ull,   0ull},
63741         {"CTO_P2E"                     ,        13,     1,      656,    "RO",   0,      0,      0ull,   0ull},
63742         {"RESERVED_14_63"              ,        14,     50,     656,    "RAZ",  1,      1,      0,      0},
63743         {"ADDR"                        ,        0,      32,     657,    "R/W",  0,      1,      0ull,   0},
63744         {"DATA"                        ,        32,     32,     657,    "R/W",  0,      1,      0ull,   0},
63745         {"ADDR"                        ,        0,      32,     658,    "R/W",  0,      1,      0ull,   0},
63746         {"DATA"                        ,        32,     32,     658,    "R/W",  0,      1,      0ull,   0},
63747         {"TAG"                         ,        0,      32,     659,    "RO",   0,      0,      0ull,   0ull},
63748         {"RESERVED_32_63"              ,        32,     32,     659,    "RAZ",  1,      1,      0,      0},
63749         {"INV_LCRC"                    ,        0,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
63750         {"INV_ECRC"                    ,        1,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
63751         {"RESERVED_2_2"                ,        2,      1,      660,    "RAZ",  0,      0,      0ull,   0ull},
63752         {"RO_CTLP"                     ,        3,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
63753         {"LNK_ENB"                     ,        4,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
63754         {"DLY_ONE"                     ,        5,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
63755         {"NF_ECRC"                     ,        6,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
63756         {"RESERVED_7_8"                ,        7,      2,      660,    "RAZ",  0,      0,      0ull,   0ull},
63757         {"OB_P_CMD"                    ,        9,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
63758         {"PM_XPME"                     ,        10,     1,      660,    "R/W",  0,      0,      0ull,   0ull},
63759         {"PM_XTOFF"                    ,        11,     1,      660,    "R/W",  0,      0,      0ull,   0ull},
63760         {"LANE_SWP"                    ,        12,     1,      660,    "R/W",  0,      0,      0ull,   0ull},
63761         {"QLM_CFG"                     ,        13,     2,      660,    "RO",   1,      1,      0,      0},
63762         {"PBUS"                        ,        15,     8,      660,    "RO",   1,      1,      0,      0},
63763         {"DNUM"                        ,        23,     5,      660,    "RO",   1,      1,      0,      0},
63764         {"RESERVED_28_63"              ,        28,     36,     660,    "RAZ",  1,      1,      0,      0},
63765         {"PCIERST"                     ,        0,      1,      661,    "RO",   0,      0,      0ull,   0ull},
63766         {"RESERVED_1_63"               ,        1,      63,     661,    "RAZ",  1,      1,      0,      0},
63767         {"SPOISON"                     ,        0,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63768         {"RTLPMAL"                     ,        1,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63769         {"RTLPLLE"                     ,        2,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63770         {"RECRCE"                      ,        3,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63771         {"RPOISON"                     ,        4,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63772         {"RCEMRC"                      ,        5,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63773         {"RNFEMRC"                     ,        6,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63774         {"RFEMRC"                      ,        7,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63775         {"RPMERC"                      ,        8,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63776         {"RPTAMRC"                     ,        9,      1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63777         {"RUMEP"                       ,        10,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63778         {"RVDM"                        ,        11,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63779         {"ACTO"                        ,        12,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63780         {"RTE"                         ,        13,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63781         {"MRE"                         ,        14,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63782         {"RDWDLE"                      ,        15,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63783         {"RTWDLE"                      ,        16,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63784         {"DPEOOSD"                     ,        17,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63785         {"FCPVWT"                      ,        18,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63786         {"RPE"                         ,        19,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63787         {"FCUV"                        ,        20,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63788         {"RQO"                         ,        21,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63789         {"RAUC"                        ,        22,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63790         {"RACUR"                       ,        23,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63791         {"RACCA"                       ,        24,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63792         {"CAAR"                        ,        25,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63793         {"RARWDNS"                     ,        26,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63794         {"RAMTLP"                      ,        27,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63795         {"RACPP"                       ,        28,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63796         {"RAWWPP"                      ,        29,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63797         {"ECRC_E"                      ,        30,     1,      662,    "R/W1C",        0,      0,      0ull,   0ull},
63798         {"RESERVED_31_63"              ,        31,     33,     662,    "RAZ",  1,      1,      0,      0},
63799         {"SPOISON"                     ,        0,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63800         {"RTLPMAL"                     ,        1,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63801         {"RTLPLLE"                     ,        2,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63802         {"RECRCE"                      ,        3,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63803         {"RPOISON"                     ,        4,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63804         {"RCEMRC"                      ,        5,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63805         {"RNFEMRC"                     ,        6,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63806         {"RFEMRC"                      ,        7,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63807         {"RPMERC"                      ,        8,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63808         {"RPTAMRC"                     ,        9,      1,      663,    "R/W",  0,      0,      0ull,   0ull},
63809         {"RUMEP"                       ,        10,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63810         {"RVDM"                        ,        11,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63811         {"ACTO"                        ,        12,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63812         {"RTE"                         ,        13,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63813         {"MRE"                         ,        14,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63814         {"RDWDLE"                      ,        15,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63815         {"RTWDLE"                      ,        16,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63816         {"DPEOOSD"                     ,        17,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63817         {"FCPVWT"                      ,        18,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63818         {"RPE"                         ,        19,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63819         {"FCUV"                        ,        20,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63820         {"RQO"                         ,        21,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63821         {"RAUC"                        ,        22,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63822         {"RACUR"                       ,        23,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63823         {"RACCA"                       ,        24,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63824         {"CAAR"                        ,        25,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63825         {"RARWDNS"                     ,        26,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63826         {"RAMTLP"                      ,        27,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63827         {"RACPP"                       ,        28,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63828         {"RAWWPP"                      ,        29,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63829         {"ECRC_E"                      ,        30,     1,      663,    "R/W",  0,      0,      0ull,   0ull},
63830         {"RESERVED_31_63"              ,        31,     33,     663,    "RAZ",  1,      1,      0,      0},
63831         {"AUX_EN"                      ,        0,      1,      664,    "RO",   0,      0,      0ull,   0ull},
63832         {"PM_EN"                       ,        1,      1,      664,    "RO",   0,      0,      0ull,   0ull},
63833         {"PM_STAT"                     ,        2,      1,      664,    "RO",   0,      0,      0ull,   0ull},
63834         {"PM_DST"                      ,        3,      1,      664,    "RO",   0,      0,      0ull,   0ull},
63835         {"RESERVED_4_63"               ,        4,      60,     664,    "RO",   1,      1,      0,      0},
63836         {"RESERVED_0_13"               ,        0,      14,     665,    "RAZ",  1,      1,      0,      0},
63837         {"ADDR"                        ,        14,     50,     665,    "R/W",  0,      0,      0ull,   0ull},
63838         {"RESERVED_0_25"               ,        0,      26,     666,    "RAZ",  1,      1,      0,      0},
63839         {"ADDR"                        ,        26,     38,     666,    "R/W",  0,      0,      0ull,   0ull},
63840         {"RESERVED_0_38"               ,        0,      39,     667,    "RAZ",  1,      1,      0,      0},
63841         {"ADDR"                        ,        39,     25,     667,    "R/W",  0,      0,      0ull,   0ull},
63842         {"RESERVED_0_11"               ,        0,      12,     668,    "RAZ",  1,      1,      0,      0},
63843         {"ADDR"                        ,        12,     52,     668,    "R/W",  0,      1,      4503599627370495ull,    0},
63844         {"RESERVED_0_11"               ,        0,      12,     669,    "RAZ",  1,      1,      0,      0},
63845         {"ADDR"                        ,        12,     52,     669,    "R/W",  0,      1,      4503599627370495ull,    0},
63846         {"NPEI_P"                      ,        0,      5,      670,    "R/W",  0,      0,      2ull,   2ull},
63847         {"NPEI_NP"                     ,        5,      5,      670,    "R/W",  0,      0,      2ull,   2ull},
63848         {"NPEI_CPL"                    ,        10,     5,      670,    "R/W",  0,      0,      2ull,   2ull},
63849         {"PESC_P"                      ,        15,     5,      670,    "R/W",  0,      0,      2ull,   2ull},
63850         {"PESC_NP"                     ,        20,     5,      670,    "R/W",  0,      0,      2ull,   2ull},
63851         {"PESC_CPL"                    ,        25,     5,      670,    "R/W",  0,      0,      2ull,   2ull},
63852         {"PEAI_PPF"                    ,        30,     8,      670,    "R/W",  0,      0,      3ull,   3ull},
63853         {"RESERVED_38_63"              ,        38,     26,     670,    "RAZ",  1,      1,      0,      0},
63854         {"BIST"                        ,        0,      18,     671,    "RO",   0,      0,      0ull,   0ull},
63855         {"RESERVED_18_63"              ,        18,     46,     671,    "RAZ",  1,      1,      0,      0},
63856         {"DPRT"                        ,        0,      16,     672,    "R/W",  0,      0,      0ull,   0ull},
63857         {"UDP"                         ,        16,     1,      672,    "R/W",  0,      0,      0ull,   0ull},
63858         {"TCP"                         ,        17,     1,      672,    "R/W",  0,      0,      0ull,   0ull},
63859         {"RESERVED_18_63"              ,        18,     46,     672,    "RAZ",  1,      1,      0,      0},
63860         {"MAP0"                        ,        0,      4,      673,    "R/W",  0,      0,      0ull,   0ull},
63861         {"MAP1"                        ,        4,      4,      673,    "R/W",  0,      0,      0ull,   0ull},
63862         {"MAP2"                        ,        8,      4,      673,    "R/W",  0,      0,      0ull,   0ull},
63863         {"MAP3"                        ,        12,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63864         {"MAP4"                        ,        16,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63865         {"MAP5"                        ,        20,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63866         {"MAP6"                        ,        24,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63867         {"MAP7"                        ,        28,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63868         {"MAP8"                        ,        32,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63869         {"MAP9"                        ,        36,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63870         {"MAP10"                       ,        40,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63871         {"MAP11"                       ,        44,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63872         {"MAP12"                       ,        48,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63873         {"MAP13"                       ,        52,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63874         {"MAP14"                       ,        56,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63875         {"MAP15"                       ,        60,     4,      673,    "R/W",  0,      0,      0ull,   0ull},
63876         {"MAP0"                        ,        0,      4,      674,    "R/W",  0,      0,      0ull,   0ull},
63877         {"MAP1"                        ,        4,      4,      674,    "R/W",  0,      0,      0ull,   0ull},
63878         {"MAP2"                        ,        8,      4,      674,    "R/W",  0,      0,      0ull,   0ull},
63879         {"MAP3"                        ,        12,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63880         {"MAP4"                        ,        16,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63881         {"MAP5"                        ,        20,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63882         {"MAP6"                        ,        24,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63883         {"MAP7"                        ,        28,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63884         {"MAP8"                        ,        32,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63885         {"MAP9"                        ,        36,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63886         {"MAP10"                       ,        40,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63887         {"MAP11"                       ,        44,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63888         {"MAP12"                       ,        48,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63889         {"MAP13"                       ,        52,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63890         {"MAP14"                       ,        56,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63891         {"MAP15"                       ,        60,     4,      674,    "R/W",  0,      0,      0ull,   0ull},
63892         {"MINLEN"                      ,        0,      16,     675,    "R/W",  0,      0,      64ull,  64ull},
63893         {"MAXLEN"                      ,        16,     16,     675,    "R/W",  0,      0,      1536ull,        1536ull},
63894         {"RESERVED_32_63"              ,        32,     32,     675,    "RAZ",  1,      1,      0,      0},
63895         {"NIP_SHF"                     ,        0,      3,      676,    "R/W",  0,      0,      0ull,   0ull},
63896         {"RESERVED_3_7"                ,        3,      5,      676,    "RAZ",  1,      1,      0,      0},
63897         {"RAW_SHF"                     ,        8,      3,      676,    "R/W",  0,      0,      0ull,   0ull},
63898         {"RESERVED_11_15"              ,        11,     5,      676,    "RAZ",  1,      1,      0,      0},
63899         {"MAX_L2"                      ,        16,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
63900         {"IP6_UDP"                     ,        17,     1,      676,    "R/W",  0,      0,      1ull,   1ull},
63901         {"TAG_SYN"                     ,        18,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
63902         {"RESERVED_19_63"              ,        19,     45,     676,    "RAZ",  1,      1,      0,      0},
63903         {"IP_CHK"                      ,        0,      1,      677,    "R/W",  0,      0,      1ull,   1ull},
63904         {"IP_MAL"                      ,        1,      1,      677,    "R/W",  0,      0,      1ull,   1ull},
63905         {"IP_HOP"                      ,        2,      1,      677,    "R/W",  0,      0,      1ull,   1ull},
63906         {"IP4_OPTS"                    ,        3,      1,      677,    "R/W",  0,      0,      1ull,   1ull},
63907         {"IP6_EEXT"                    ,        4,      2,      677,    "R/W",  0,      0,      1ull,   3ull},
63908         {"RESERVED_6_7"                ,        6,      2,      677,    "RAZ",  1,      1,      0,      0},
63909         {"L4_MAL"                      ,        8,      1,      677,    "R/W",  0,      0,      1ull,   1ull},
63910         {"L4_PRT"                      ,        9,      1,      677,    "R/W",  0,      0,      1ull,   1ull},
63911         {"L4_CHK"                      ,        10,     1,      677,    "R/W",  0,      0,      1ull,   1ull},
63912         {"L4_LEN"                      ,        11,     1,      677,    "R/W",  0,      0,      1ull,   1ull},
63913         {"TCP_FLAG"                    ,        12,     1,      677,    "R/W",  0,      0,      1ull,   1ull},
63914         {"L2_MAL"                      ,        13,     1,      677,    "R/W",  0,      0,      1ull,   1ull},
63915         {"VS_QOS"                      ,        14,     1,      677,    "R/W",  0,      0,      0ull,   0ull},
63916         {"VS_WQE"                      ,        15,     1,      677,    "R/W",  0,      0,      0ull,   0ull},
63917         {"IGNRS"                       ,        16,     1,      677,    "R/W",  0,      0,      0ull,   0ull},
63918         {"RESERVED_17_19"              ,        17,     3,      677,    "RAZ",  0,      0,      0ull,   0ull},
63919         {"RING_EN"                     ,        20,     1,      677,    "R/W",  0,      0,      0ull,   0ull},
63920         {"RESERVED_21_23"              ,        21,     3,      677,    "RAZ",  1,      1,      0,      0},
63921         {"DSA_GRP_SID"                 ,        24,     1,      677,    "R/W",  0,      0,      0ull,   0ull},
63922         {"DSA_GRP_SCMD"                ,        25,     1,      677,    "R/W",  0,      0,      0ull,   0ull},
63923         {"DSA_GRP_TVID"                ,        26,     1,      677,    "R/W",  0,      0,      0ull,   0ull},
63924         {"RESERVED_27_63"              ,        27,     37,     677,    "RAZ",  1,      1,      0,      0},
63925         {"PRI"                         ,        0,      6,      678,    "R/W",  0,      1,      0ull,   0},
63926         {"RESERVED_6_7"                ,        6,      2,      678,    "RAZ",  1,      1,      0,      0},
63927         {"QOS"                         ,        8,      3,      678,    "R/W",  0,      1,      0ull,   0},
63928         {"RESERVED_11_11"              ,        11,     1,      678,    "RAZ",  1,      1,      0,      0},
63929         {"UP_QOS"                      ,        12,     1,      678,    "RAZ",  0,      1,      0ull,   0},
63930         {"RESERVED_13_63"              ,        13,     51,     678,    "RAZ",  1,      1,      0,      0},
63931         {"PKTDRP"                      ,        0,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
63932         {"RESERVED_1_1"                ,        1,      1,      679,    "RAZ",  1,      1,      0,      0},
63933         {"BCKPRS"                      ,        2,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
63934         {"PRTNXA"                      ,        3,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
63935         {"BADTAG"                      ,        4,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
63936         {"SKPRUNT"                     ,        5,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
63937         {"TODOOVR"                     ,        6,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
63938         {"FEPERR"                      ,        7,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
63939         {"BEPERR"                      ,        8,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
63940         {"MINERR"                      ,        9,      1,      679,    "R/W",  0,      0,      0ull,   0ull},
63941         {"MAXERR"                      ,        10,     1,      679,    "R/W",  0,      0,      0ull,   0ull},
63942         {"LENERR"                      ,        11,     1,      679,    "R/W",  0,      0,      0ull,   0ull},
63943         {"PUNYERR"                     ,        12,     1,      679,    "R/W",  0,      0,      0ull,   0ull},
63944         {"RESERVED_13_63"              ,        13,     51,     679,    "RAZ",  1,      1,      0,      0},
63945         {"PKTDRP"                      ,        0,      1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63946         {"RESERVED_1_1"                ,        1,      1,      680,    "RAZ",  1,      1,      0,      0},
63947         {"BCKPRS"                      ,        2,      1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63948         {"PRTNXA"                      ,        3,      1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63949         {"BADTAG"                      ,        4,      1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63950         {"SKPRUNT"                     ,        5,      1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63951         {"TODOOVR"                     ,        6,      1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63952         {"FEPERR"                      ,        7,      1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63953         {"BEPERR"                      ,        8,      1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63954         {"MINERR"                      ,        9,      1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63955         {"MAXERR"                      ,        10,     1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63956         {"LENERR"                      ,        11,     1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63957         {"PUNYERR"                     ,        12,     1,      680,    "R/W1C",        0,      0,      0ull,   0ull},
63958         {"RESERVED_13_63"              ,        13,     51,     680,    "RAZ",  1,      1,      0,      0},
63959         {"OFFSET"                      ,        0,      3,      681,    "R/W",  0,      0,      0ull,   0ull},
63960         {"RESERVED_3_63"               ,        3,      61,     681,    "RAZ",  1,      1,      0,      0},
63961         {"SKIP"                        ,        0,      7,      682,    "R/W",  0,      0,      0ull,   0ull},
63962         {"RESERVED_7_7"                ,        7,      1,      682,    "RAZ",  1,      1,      0,      0},
63963         {"MODE"                        ,        8,      2,      682,    "R/W",  0,      0,      0ull,   0ull},
63964         {"DSA_EN"                      ,        10,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63965         {"HIGIG_EN"                    ,        11,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63966         {"CRC_EN"                      ,        12,     1,      682,    "RO",   0,      0,      0ull,   0ull},
63967         {"RESERVED_13_15"              ,        13,     3,      682,    "RAZ",  1,      1,      0,      0},
63968         {"QOS_VLAN"                    ,        16,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63969         {"QOS_DIFF"                    ,        17,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63970         {"QOS_VOD"                     ,        18,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63971         {"QOS_VSEL"                    ,        19,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63972         {"QOS_WAT"                     ,        20,     4,      682,    "R/W",  0,      0,      0ull,   0ull},
63973         {"QOS"                         ,        24,     3,      682,    "R/W",  0,      0,      0ull,   0ull},
63974         {"HG_QOS"                      ,        27,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63975         {"GRP_WAT"                     ,        28,     4,      682,    "R/W",  0,      0,      0ull,   0ull},
63976         {"INST_HDR"                    ,        32,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63977         {"DYN_RS"                      ,        33,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63978         {"TAG_INC"                     ,        34,     2,      682,    "R/W",  0,      0,      0ull,   0ull},
63979         {"RAWDRP"                      ,        36,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63980         {"RESERVED_37_39"              ,        37,     3,      682,    "RAZ",  1,      1,      0,      0},
63981         {"QOS_WAT_47"                  ,        40,     4,      682,    "R/W",  0,      0,      0ull,   0ull},
63982         {"GRP_WAT_47"                  ,        44,     4,      682,    "R/W",  0,      0,      0ull,   0ull},
63983         {"MINERR_EN"                   ,        48,     1,      682,    "R/W",  0,      0,      1ull,   1ull},
63984         {"MAXERR_EN"                   ,        49,     1,      682,    "R/W",  0,      0,      1ull,   1ull},
63985         {"LENERR_EN"                   ,        50,     1,      682,    "R/W",  0,      0,      1ull,   1ull},
63986         {"VLAN_LEN"                    ,        51,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63987         {"PAD_LEN"                     ,        52,     1,      682,    "R/W",  0,      0,      0ull,   0ull},
63988         {"RESERVED_53_63"              ,        53,     11,     682,    "RAZ",  1,      1,      0,      0},
63989         {"GRP"                         ,        0,      4,      683,    "R/W",  0,      0,      0ull,   0ull},
63990         {"NON_TAG_TYPE"                ,        4,      2,      683,    "R/W",  0,      0,      0ull,   0ull},
63991         {"IP4_TAG_TYPE"                ,        6,      2,      683,    "R/W",  0,      0,      0ull,   0ull},
63992         {"IP6_TAG_TYPE"                ,        8,      2,      683,    "R/W",  0,      0,      0ull,   0ull},
63993         {"TCP4_TAG_TYPE"               ,        10,     2,      683,    "R/W",  0,      0,      0ull,   0ull},
63994         {"TCP6_TAG_TYPE"               ,        12,     2,      683,    "R/W",  0,      0,      0ull,   0ull},
63995         {"IP4_SRC_FLAG"                ,        14,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
63996         {"IP6_SRC_FLAG"                ,        15,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
63997         {"IP4_DST_FLAG"                ,        16,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
63998         {"IP6_DST_FLAG"                ,        17,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
63999         {"IP4_PCTL_FLAG"               ,        18,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64000         {"IP6_NXTH_FLAG"               ,        19,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64001         {"IP4_SPRT_FLAG"               ,        20,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64002         {"IP6_SPRT_FLAG"               ,        21,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64003         {"IP4_DPRT_FLAG"               ,        22,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64004         {"IP6_DPRT_FLAG"               ,        23,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64005         {"INC_PRT_FLAG"                ,        24,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64006         {"INC_VLAN"                    ,        25,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64007         {"INC_VS"                      ,        26,     2,      683,    "R/W",  0,      0,      0ull,   0ull},
64008         {"TAG_MODE"                    ,        28,     2,      683,    "R/W",  0,      0,      0ull,   0ull},
64009         {"GRPTAG_MSKIP"                ,        30,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64010         {"GRPTAG"                      ,        31,     1,      683,    "R/W",  0,      0,      0ull,   0ull},
64011         {"GRPTAGMASK"                  ,        32,     4,      683,    "R/W",  0,      0,      0ull,   0ull},
64012         {"GRPTAGBASE"                  ,        36,     4,      683,    "R/W",  0,      0,      0ull,   0ull},
64013         {"RESERVED_40_63"              ,        40,     24,     683,    "RAZ",  1,      1,      0,      0},
64014         {"QOS"                         ,        0,      3,      684,    "R/W",  0,      0,      0ull,   0ull},
64015         {"RESERVED_3_63"               ,        3,      61,     684,    "RAZ",  1,      1,      0,      0},
64016         {"QOS"                         ,        0,      3,      685,    "R/W",  0,      0,      0ull,   0ull},
64017         {"RESERVED_3_3"                ,        3,      1,      685,    "RAZ",  1,      1,      0,      0},
64018         {"QOS1"                        ,        4,      3,      685,    "R/W",  0,      0,      0ull,   0ull},
64019         {"RESERVED_7_63"               ,        7,      57,     685,    "RAZ",  1,      1,      0,      0},
64020         {"MATCH_VALUE"                 ,        0,      16,     686,    "R/W",  0,      0,      0ull,   0ull},
64021         {"MATCH_TYPE"                  ,        16,     3,      686,    "R/W",  0,      0,      0ull,   0ull},
64022         {"RESERVED_19_19"              ,        19,     1,      686,    "RAZ",  1,      1,      0,      0},
64023         {"QOS"                         ,        20,     3,      686,    "R/W",  0,      0,      0ull,   0ull},
64024         {"RESERVED_23_23"              ,        23,     1,      686,    "RAZ",  1,      1,      0,      0},
64025         {"GRP"                         ,        24,     4,      686,    "R/W",  0,      0,      0ull,   0ull},
64026         {"RESERVED_28_31"              ,        28,     4,      686,    "RAZ",  1,      1,      0,      0},
64027         {"MASK"                        ,        32,     16,     686,    "R/W",  0,      0,      0ull,   0ull},
64028         {"RESERVED_48_63"              ,        48,     16,     686,    "RAZ",  1,      1,      0,      0},
64029         {"WORD"                        ,        0,      56,     687,    "R/W",  0,      0,      0ull,   0ull},
64030         {"RESERVED_56_63"              ,        56,     8,      687,    "RAZ",  1,      1,      0,      0},
64031         {"RST"                         ,        0,      1,      688,    "R/W",  0,      0,      0ull,   0ull},
64032         {"RESERVED_1_63"               ,        1,      63,     688,    "RAZ",  1,      1,      0,      0},
64033         {"DRP_OCTS"                    ,        0,      32,     689,    "R/W",  0,      1,      0ull,   0},
64034         {"DRP_PKTS"                    ,        32,     32,     689,    "R/W",  0,      1,      0ull,   0},
64035         {"OCTS"                        ,        0,      48,     690,    "R/W",  0,      1,      0ull,   0},
64036         {"RESERVED_48_63"              ,        48,     16,     690,    "RAZ",  1,      1,      0,      0},
64037         {"RAW"                         ,        0,      32,     691,    "R/W",  0,      1,      0ull,   0},
64038         {"PKTS"                        ,        32,     32,     691,    "R/W",  0,      1,      0ull,   0},
64039         {"MCST"                        ,        0,      32,     692,    "R/W",  0,      1,      0ull,   0},
64040         {"BCST"                        ,        32,     32,     692,    "R/W",  0,      1,      0ull,   0},
64041         {"H64"                         ,        0,      32,     693,    "R/W",  0,      1,      0ull,   0},
64042         {"H65TO127"                    ,        32,     32,     693,    "R/W",  0,      1,      0ull,   0},
64043         {"H128TO255"                   ,        0,      32,     694,    "R/W",  0,      1,      0ull,   0},
64044         {"H256TO511"                   ,        32,     32,     694,    "R/W",  0,      1,      0ull,   0},
64045         {"H512TO1023"                  ,        0,      32,     695,    "R/W",  0,      1,      0ull,   0},
64046         {"H1024TO1518"                 ,        32,     32,     695,    "R/W",  0,      1,      0ull,   0},
64047         {"H1519"                       ,        0,      32,     696,    "R/W",  0,      1,      0ull,   0},
64048         {"FCS"                         ,        32,     32,     696,    "R/W",  0,      1,      0ull,   0},
64049         {"UNDERSZ"                     ,        0,      32,     697,    "R/W",  0,      1,      0ull,   0},
64050         {"FRAG"                        ,        32,     32,     697,    "R/W",  0,      1,      0ull,   0},
64051         {"OVERSZ"                      ,        0,      32,     698,    "R/W",  0,      1,      0ull,   0},
64052         {"JABBER"                      ,        32,     32,     698,    "R/W",  0,      1,      0ull,   0},
64053         {"RDCLR"                       ,        0,      1,      699,    "R/W",  0,      0,      1ull,   1ull},
64054         {"RESERVED_1_63"               ,        1,      63,     699,    "RAZ",  1,      1,      0,      0},
64055         {"ERRS"                        ,        0,      16,     700,    "R/W",  0,      1,      0ull,   0},
64056         {"RESERVED_16_63"              ,        16,     48,     700,    "RAZ",  1,      1,      0,      0},
64057         {"OCTS"                        ,        0,      48,     701,    "R/W",  0,      1,      0ull,   0},
64058         {"RESERVED_48_63"              ,        48,     16,     701,    "RAZ",  1,      1,      0,      0},
64059         {"PKTS"                        ,        0,      32,     702,    "R/W",  0,      1,      0ull,   0},
64060         {"RESERVED_32_63"              ,        32,     32,     702,    "RAZ",  1,      1,      0,      0},
64061         {"EN"                          ,        0,      8,      703,    "R/W",  0,      0,      0ull,   0ull},
64062         {"RESERVED_8_63"               ,        8,      56,     703,    "RAZ",  1,      1,      0,      0},
64063         {"MASK"                        ,        0,      16,     704,    "R/W",  0,      0,      0ull,   0ull},
64064         {"RESERVED_16_63"              ,        16,     48,     704,    "RAZ",  1,      1,      0,      0},
64065         {"SRC"                         ,        0,      16,     705,    "R/W",  0,      0,      0ull,   0ull},
64066         {"DST"                         ,        16,     16,     705,    "R/W",  0,      0,      0ull,   0ull},
64067         {"RESERVED_32_63"              ,        32,     32,     705,    "RAZ",  1,      1,      0,      0},
64068         {"ENTRY"                       ,        0,      62,     706,    "RO",   1,      1,      0,      0},
64069         {"RESERVED_62_62"              ,        62,     1,      706,    "RAZ",  1,      1,      0,      0},
64070         {"VAL"                         ,        63,     1,      706,    "RO",   1,      1,      0,      0},
64071         {"COUNT"                       ,        0,      32,     707,    "R/W1C",        1,      0,      0,      0ull},
64072         {"RESERVED_32_63"              ,        32,     32,     707,    "RAZ",  1,      1,      0,      0},
64073         {"COUNT"                       ,        0,      48,     708,    "R/W1C",        1,      0,      0,      0ull},
64074         {"RESERVED_48_63"              ,        48,     16,     708,    "RAZ",  1,      1,      0,      0},
64075         {"SIZE"                        ,        0,      16,     709,    "RO",   1,      0,      0,      0ull},
64076         {"SEGS"                        ,        16,     6,      709,    "RO",   1,      0,      0,      0ull},
64077         {"CMD"                         ,        22,     14,     709,    "RO",   1,      0,      0,      0ull},
64078         {"FAU"                         ,        36,     28,     709,    "RO",   1,      0,      0,      0ull},
64079         {"PTR"                         ,        0,      40,     710,    "RO",   1,      0,      0,      0ull},
64080         {"SIZE"                        ,        40,     16,     710,    "RO",   1,      0,      0,      0ull},
64081         {"POOL"                        ,        56,     3,      710,    "RO",   1,      0,      0,      0ull},
64082         {"BACK"                        ,        59,     4,      710,    "RO",   1,      0,      0,      0ull},
64083         {"I"                           ,        63,     1,      710,    "RO",   1,      0,      0,      0ull},
64084         {"PTRS2"                       ,        0,      17,     711,    "RO",   1,      0,      0,      0ull},
64085         {"RESERVED_17_31"              ,        17,     15,     711,    "RAZ",  1,      0,      0,      0ull},
64086         {"PTRS1"                       ,        32,     17,     711,    "RO",   1,      0,      0,      0ull},
64087         {"RESERVED_49_63"              ,        49,     15,     711,    "RAZ",  1,      0,      0,      0ull},
64088         {"MOD"                         ,        0,      3,      712,    "RO",   1,      0,      0,      0ull},
64089         {"CNT"                         ,        3,      13,     712,    "RO",   1,      0,      0,      0ull},
64090         {"CHK"                         ,        16,     1,      712,    "RO",   1,      0,      0,      0ull},
64091         {"LEN"                         ,        17,     1,      712,    "RO",   1,      0,      0,      0ull},
64092         {"SOP"                         ,        18,     1,      712,    "RO",   1,      0,      0,      0ull},
64093         {"UID"                         ,        19,     3,      712,    "RO",   1,      0,      0,      0ull},
64094         {"MAJ"                         ,        22,     1,      712,    "RO",   1,      0,      0,      0ull},
64095         {"RESERVED_23_63"              ,        23,     41,     712,    "RAZ",  1,      0,      0,      0ull},
64096         {"SIZE"                        ,        0,      16,     713,    "RO",   1,      0,      0,      0ull},
64097         {"SEGS"                        ,        16,     6,      713,    "RO",   1,      0,      0,      0ull},
64098         {"CMD"                         ,        22,     14,     713,    "RO",   1,      0,      0,      0ull},
64099         {"FAU"                         ,        36,     28,     713,    "RO",   1,      0,      0,      0ull},
64100         {"PTR"                         ,        0,      40,     714,    "RO",   1,      0,      0,      0ull},
64101         {"SIZE"                        ,        40,     16,     714,    "RO",   1,      0,      0,      0ull},
64102         {"POOL"                        ,        56,     3,      714,    "RO",   1,      0,      0,      0ull},
64103         {"BACK"                        ,        59,     4,      714,    "RO",   1,      0,      0,      0ull},
64104         {"I"                           ,        63,     1,      714,    "RO",   1,      0,      0,      0ull},
64105         {"DATA"                        ,        0,      64,     715,    "RO",   1,      0,      0,      0ull},
64106         {"PTR"                         ,        0,      40,     716,    "RO",   1,      0,      0,      0ull},
64107         {"SIZE"                        ,        40,     16,     716,    "RO",   1,      0,      0,      0ull},
64108         {"POOL"                        ,        56,     3,      716,    "RO",   1,      0,      0,      0ull},
64109         {"BACK"                        ,        59,     4,      716,    "RO",   1,      0,      0,      0ull},
64110         {"I"                           ,        63,     1,      716,    "RO",   1,      0,      0,      0ull},
64111         {"DATA"                        ,        0,      64,     717,    "RO",   1,      0,      0,      0ull},
64112         {"MAJOR"                       ,        0,      3,      718,    "RO",   1,      0,      0,      0ull},
64113         {"MINOR"                       ,        3,      2,      718,    "RO",   1,      0,      0,      0ull},
64114         {"WAIT"                        ,        5,      1,      718,    "RO",   1,      0,      0,      0ull},
64115         {"CHK_MODE"                    ,        6,      1,      718,    "RO",   1,      0,      0,      0ull},
64116         {"CHK_ONCE"                    ,        7,      1,      718,    "RO",   1,      0,      0,      0ull},
64117         {"INIT_DWRITE"                 ,        8,      1,      718,    "RO",   1,      0,      0,      0ull},
64118         {"DREAD_SOP"                   ,        9,      1,      718,    "RO",   1,      0,      0,      0ull},
64119         {"UID"                         ,        10,     2,      718,    "RO",   1,      0,      0,      0ull},
64120         {"CMND_OFF"                    ,        12,     6,      718,    "RO",   1,      0,      0,      0ull},
64121         {"CMND_SIZ"                    ,        18,     16,     718,    "RO",   1,      0,      0,      0ull},
64122         {"CMND_SEGS"                   ,        34,     6,      718,    "RO",   1,      0,      0,      0ull},
64123         {"CURR_OFF"                    ,        40,     16,     718,    "RO",   1,      0,      0,      0ull},
64124         {"CURR_SIZ"                    ,        56,     8,      718,    "RO",   1,      0,      0,      0ull},
64125         {"CURR_SIZ"                    ,        0,      8,      719,    "RO",   1,      0,      0,      0ull},
64126         {"CURR_PTR"                    ,        8,      40,     719,    "RO",   1,      0,      0,      0ull},
64127         {"NXT_INFLT"                   ,        48,     6,      719,    "RO",   1,      0,      0,      0ull},
64128         {"RESERVED_54_63"              ,        54,     10,     719,    "RAZ",  1,      0,      0,      0ull},
64129         {"QID_BASE"                    ,        0,      8,      720,    "RO",   1,      0,      0,      0ull},
64130         {"QID_OFF"                     ,        8,      4,      720,    "RO",   1,      0,      0,      0ull},
64131         {"QID_OFFMAX"                  ,        12,     4,      720,    "RO",   1,      0,      0,      0ull},
64132         {"QCB_RIDX"                    ,        16,     5,      720,    "RO",   1,      0,      0,      0ull},
64133         {"QOS"                         ,        21,     3,      720,    "RO",   1,      0,      0,      0ull},
64134         {"STATC"                       ,        24,     1,      720,    "RO",   1,      0,      0,      0ull},
64135         {"ACTIVE"                      ,        25,     1,      720,    "RO",   1,      0,      0,      0ull},
64136         {"PREEMPTED"                   ,        26,     1,      720,    "RO",   1,      0,      0,      0ull},
64137         {"PREEMPTEE"                   ,        27,     1,      720,    "RO",   1,      0,      0,      0ull},
64138         {"PREEMPTER"                   ,        28,     1,      720,    "RO",   1,      0,      0,      0ull},
64139         {"QID_OFFTHS"                  ,        29,     4,      720,    "RO",   1,      0,      0,      0ull},
64140         {"QID_OFFRES"                  ,        33,     4,      720,    "RO",   1,      0,      0,      0ull},
64141         {"RESERVED_37_63"              ,        37,     27,     720,    "RAZ",  1,      0,      0,      0ull},
64142         {"QCB_RIDX"                    ,        0,      6,      721,    "RO",   1,      0,      0,      0ull},
64143         {"QCB_WIDX"                    ,        6,      6,      721,    "RO",   1,      0,      0,      0ull},
64144         {"BUF_PTR"                     ,        12,     33,     721,    "RO",   1,      0,      0,      0ull},
64145         {"BUF_SIZ"                     ,        45,     13,     721,    "RO",   1,      0,      0,      0ull},
64146         {"TAIL"                        ,        58,     1,      721,    "RO",   1,      0,      0,      0ull},
64147         {"QOS"                         ,        59,     5,      721,    "RO",   1,      0,      0,      0ull},
64148         {"QOS"                         ,        0,      3,      722,    "RO",   1,      0,      0,      0ull},
64149         {"STATIC_Q"                    ,        3,      1,      722,    "RO",   1,      0,      0,      0ull},
64150         {"S_TAIL"                      ,        4,      1,      722,    "RO",   1,      0,      0,      0ull},
64151         {"STATIC_P"                    ,        5,      1,      722,    "RO",   1,      0,      0,      0ull},
64152         {"PREEMPTEE"                   ,        6,      1,      722,    "RO",   1,      0,      0,      0ull},
64153         {"RESERVED_7_7"                ,        7,      1,      722,    "RAZ",  1,      0,      0,      0ull},
64154         {"DOORBELL"                    ,        8,      20,     722,    "RO",   1,      0,      0,      0ull},
64155         {"PREEMPTER"                   ,        28,     1,      722,    "RO",   1,      0,      0,      0ull},
64156         {"RESERVED_29_63"              ,        29,     35,     722,    "RAZ",  1,      0,      0,      0ull},
64157         {"PTRS3"                       ,        0,      17,     723,    "RO",   1,      0,      0,      0ull},
64158         {"RESERVED_17_31"              ,        17,     15,     723,    "RAZ",  1,      0,      0,      0ull},
64159         {"PTRS0"                       ,        32,     17,     723,    "RO",   1,      0,      0,      0ull},
64160         {"RESERVED_49_63"              ,        49,     15,     723,    "RAZ",  1,      0,      0,      0ull},
64161         {"PID"                         ,        0,      6,      724,    "R/W",  1,      0,      0,      0ull},
64162         {"EID"                         ,        6,      4,      724,    "R/W",  1,      0,      0,      0ull},
64163         {"BP_PORT"                     ,        10,     6,      724,    "R/W",  1,      0,      0,      0ull},
64164         {"RESERVED_16_52"              ,        16,     37,     724,    "RAZ",  1,      0,      0,      0ull},
64165         {"QOS_MASK"                    ,        53,     8,      724,    "R/W",  1,      0,      0,      0ull},
64166         {"STATIC_P"                    ,        61,     1,      724,    "R/W",  1,      0,      0,      0ull},
64167         {"RESERVED_62_63"              ,        62,     2,      724,    "RAZ",  1,      0,      0,      0ull},
64168         {"PID"                         ,        0,      6,      725,    "R/W",  1,      0,      0,      0ull},
64169         {"EID"                         ,        6,      4,      725,    "R/W",  1,      0,      0,      0ull},
64170         {"RESERVED_10_52"              ,        10,     43,     725,    "RAZ",  1,      0,      0,      0ull},
64171         {"QOS_MASK"                    ,        53,     8,      725,    "R/W",  1,      0,      0,      0ull},
64172         {"RESERVED_61_63"              ,        61,     3,      725,    "RAZ",  1,      0,      0,      0ull},
64173         {"PID"                         ,        0,      6,      726,    "R/W",  1,      0,      0,      0ull},
64174         {"RESERVED_6_7"                ,        6,      2,      726,    "RAZ",  1,      0,      0,      0ull},
64175         {"RATE_PKT"                    ,        8,      24,     726,    "R/W",  1,      0,      0,      0ull},
64176         {"RATE_WORD"                   ,        32,     19,     726,    "R/W",  1,      0,      0,      0ull},
64177         {"RESERVED_51_63"              ,        51,     13,     726,    "RAZ",  1,      0,      0,      0ull},
64178         {"PID"                         ,        0,      6,      727,    "R/W",  1,      0,      0,      0ull},
64179         {"RESERVED_6_7"                ,        6,      2,      727,    "RAZ",  1,      0,      0,      0ull},
64180         {"RATE_LIM"                    ,        8,      24,     727,    "R/W",  1,      0,      0,      0ull},
64181         {"RESERVED_32_63"              ,        32,     32,     727,    "RAZ",  1,      0,      0,      0ull},
64182         {"QUEUE"                       ,        0,      7,      728,    "R/W",  1,      0,      0,      0ull},
64183         {"PORT"                        ,        7,      6,      728,    "WR0",  1,      0,      0,      0ull},
64184         {"INDEX"                       ,        13,     3,      728,    "WR0",  1,      0,      0,      0ull},
64185         {"TAIL"                        ,        16,     1,      728,    "R/W",  1,      0,      0,      0ull},
64186         {"BUF_PTR"                     ,        17,     36,     728,    "R/W",  1,      0,      0,      0ull},
64187         {"QOS_MASK"                    ,        53,     8,      728,    "R/W",  1,      0,      0,      0ull},
64188         {"STATIC_Q"                    ,        61,     1,      728,    "R/W",  1,      0,      0,      0ull},
64189         {"STATIC_P"                    ,        62,     1,      728,    "R/W",  1,      0,      0,      0ull},
64190         {"S_TAIL"                      ,        63,     1,      728,    "R/W",  1,      0,      0,      0ull},
64191         {"QID"                         ,        0,      7,      729,    "R/W",  1,      0,      0,      0ull},
64192         {"PID"                         ,        7,      6,      729,    "WR0",  1,      0,      0,      0ull},
64193         {"RESERVED_13_52"              ,        13,     40,     729,    "RAZ",  1,      0,      0,      0ull},
64194         {"QOS_MASK"                    ,        53,     8,      729,    "R/W",  1,      0,      0,      0ull},
64195         {"RESERVED_61_63"              ,        61,     3,      729,    "RAZ",  1,      0,      0,      0ull},
64196         {"DAT_PTR"                     ,        0,      4,      730,    "RO",   1,      0,      0,      0ull},
64197         {"DAT_DAT"                     ,        4,      2,      730,    "RO",   1,      0,      0,      0ull},
64198         {"PRT_CTL"                     ,        6,      2,      730,    "RO",   1,      0,      0,      0ull},
64199         {"PRT_QSB"                     ,        8,      3,      730,    "RO",   1,      0,      0,      0ull},
64200         {"PRT_QCB"                     ,        11,     2,      730,    "RO",   1,      0,      0,      0ull},
64201         {"NCB_INB"                     ,        13,     2,      730,    "RO",   1,      0,      0,      0ull},
64202         {"PRT_PSB"                     ,        15,     8,      730,    "RO",   1,      0,      0,      0ull},
64203         {"PRT_NXT"                     ,        23,     1,      730,    "RO",   1,      0,      0,      0ull},
64204         {"PRT_CHK"                     ,        24,     3,      730,    "RO",   1,      0,      0,      0ull},
64205         {"OUT_WIF"                     ,        27,     1,      730,    "RO",   1,      0,      0,      0ull},
64206         {"OUT_STA"                     ,        28,     1,      730,    "RO",   1,      0,      0,      0ull},
64207         {"OUT_CTL"                     ,        29,     3,      730,    "RO",   1,      0,      0,      0ull},
64208         {"OUT_DAT"                     ,        32,     1,      730,    "RO",   1,      0,      0,      0ull},
64209         {"IOB"                         ,        33,     1,      730,    "RO",   1,      0,      0,      0ull},
64210         {"CSR"                         ,        34,     1,      730,    "RO",   1,      0,      0,      0ull},
64211         {"RESERVED_35_63"              ,        35,     29,     730,    "RAZ",  1,      0,      0,      0ull},
64212         {"SIZE"                        ,        0,      13,     731,    "R/W",  0,      0,      0ull,   0ull},
64213         {"RESERVED_13_19"              ,        13,     7,      731,    "RAZ",  0,      0,      0ull,   0ull},
64214         {"POOL"                        ,        20,     3,      731,    "R/W",  0,      0,      0ull,   0ull},
64215         {"RESERVED_23_63"              ,        23,     41,     731,    "RAZ",  1,      0,      0,      0ull},
64216         {"ASSERTS"                     ,        0,      64,     732,    "RO",   0,      0,      0ull,   0ull},
64217         {"ASSERTS"                     ,        0,      64,     733,    "RO",   0,      0,      0ull,   0ull},
64218         {"ASSERTS"                     ,        0,      64,     734,    "RO",   0,      0,      0ull,   0ull},
64219         {"ASSERTS"                     ,        0,      64,     735,    "RO",   0,      0,      0ull,   0ull},
64220         {"ENGINE0"                     ,        0,      4,      736,    "R/W",  0,      0,      4ull,   4ull},
64221         {"ENGINE1"                     ,        4,      4,      736,    "R/W",  0,      0,      4ull,   4ull},
64222         {"ENGINE2"                     ,        8,      4,      736,    "R/W",  0,      0,      4ull,   4ull},
64223         {"ENGINE3"                     ,        12,     4,      736,    "R/W",  0,      0,      4ull,   4ull},
64224         {"ENGINE4"                     ,        16,     4,      736,    "R/W",  0,      0,      0ull,   0ull},
64225         {"ENGINE5"                     ,        20,     4,      736,    "R/W",  0,      0,      0ull,   0ull},
64226         {"ENGINE6"                     ,        24,     4,      736,    "R/W",  0,      0,      0ull,   0ull},
64227         {"ENGINE7"                     ,        28,     4,      736,    "R/W",  0,      0,      0ull,   0ull},
64228         {"ENGINE8"                     ,        32,     4,      736,    "R/W",  0,      0,      4ull,   4ull},
64229         {"ENGINE9"                     ,        36,     4,      736,    "R/W",  0,      0,      4ull,   4ull},
64230         {"RESERVED_40_63"              ,        40,     24,     736,    "RAZ",  1,      0,      0,      0ull},
64231         {"MASK"                        ,        0,      10,     737,    "R/W",  0,      0,      0ull,   0ull},
64232         {"RESERVED_10_63"              ,        10,     54,     737,    "RAZ",  1,      0,      0,      0ull},
64233         {"PARITY"                      ,        0,      1,      738,    "R/W1C",        0,      0,      0ull,   0ull},
64234         {"DOORBELL"                    ,        1,      1,      738,    "R/W1C",        0,      0,      0ull,   0ull},
64235         {"CURRZERO"                    ,        2,      1,      738,    "R/W1C",        0,      0,      0ull,   0ull},
64236         {"RESERVED_3_63"               ,        3,      61,     738,    "RAZ",  1,      0,      0,      0ull},
64237         {"ENA_PKO"                     ,        0,      1,      739,    "R/W",  0,      0,      0ull,   0ull},
64238         {"ENA_DWB"                     ,        1,      1,      739,    "R/W",  0,      0,      0ull,   0ull},
64239         {"STORE_BE"                    ,        2,      1,      739,    "R/W",  0,      0,      0ull,   0ull},
64240         {"RESET"                       ,        3,      1,      739,    "RAZ",  0,      0,      0ull,   0ull},
64241         {"RESERVED_4_63"               ,        4,      60,     739,    "RAZ",  1,      0,      0,      0ull},
64242         {"MODE0"                       ,        0,      3,      740,    "R/W",  0,      0,      2ull,   2ull},
64243         {"MODE1"                       ,        3,      3,      740,    "R/W",  0,      0,      0ull,   0ull},
64244         {"RESERVED_6_63"               ,        6,      58,     740,    "RAZ",  1,      0,      0,      0ull},
64245         {"PARITY"                      ,        0,      1,      741,    "R/W",  0,      0,      0ull,   0ull},
64246         {"DOORBELL"                    ,        1,      1,      741,    "R/W",  0,      0,      0ull,   0ull},
64247         {"CURRZERO"                    ,        2,      1,      741,    "R/W",  0,      0,      0ull,   0ull},
64248         {"RESERVED_3_63"               ,        3,      61,     741,    "RAZ",  1,      0,      0,      0ull},
64249         {"MODE"                        ,        0,      2,      742,    "R/W",  0,      0,      0ull,   0ull},
64250         {"RESERVED_2_63"               ,        2,      62,     742,    "RAZ",  1,      0,      0,      0ull},
64251         {"QID7"                        ,        0,      1,      743,    "R/W",  0,      0,      0ull,   0ull},
64252         {"IDX3"                        ,        1,      1,      743,    "R/W",  0,      0,      0ull,   0ull},
64253         {"RESERVED_2_63"               ,        2,      62,     743,    "RAZ",  1,      0,      0,      0ull},
64254         {"INDEX"                       ,        0,      8,      744,    "R/W",  0,      0,      0ull,   0ull},
64255         {"INC"                         ,        8,      8,      744,    "R/W",  0,      0,      0ull,   0ull},
64256         {"RESERVED_16_63"              ,        16,     48,     744,    "RAZ",  1,      0,      0,      0ull},
64257         {"ADR"                         ,        0,      1,      745,    "RO",   0,      0,      0ull,   0ull},
64258         {"PEND"                        ,        1,      1,      745,    "RO",   0,      0,      0ull,   0ull},
64259         {"NBR0"                        ,        2,      1,      745,    "RO",   0,      0,      0ull,   0ull},
64260         {"NBR1"                        ,        3,      1,      745,    "RO",   0,      0,      0ull,   0ull},
64261         {"FIDX"                        ,        4,      1,      745,    "RO",   0,      0,      0ull,   0ull},
64262         {"INDEX"                       ,        5,      1,      745,    "RO",   0,      0,      0ull,   0ull},
64263         {"NBT0"                        ,        6,      1,      745,    "RO",   0,      0,      0ull,   0ull},
64264         {"NBT1"                        ,        7,      1,      745,    "RO",   0,      0,      0ull,   0ull},
64265         {"CAM"                         ,        8,      1,      745,    "RO",   0,      0,      0ull,   0ull},
64266         {"RESERVED_9_15"               ,        9,      7,      745,    "RAZ",  1,      1,      0,      0},
64267         {"PP"                          ,        16,     4,      745,    "RO",   0,      0,      0ull,   0ull},
64268         {"RESERVED_20_63"              ,        20,     44,     745,    "RAZ",  1,      1,      0,      0},
64269         {"DS_PC"                       ,        0,      32,     746,    "R/W1C",        0,      1,      0ull,   0},
64270         {"RESERVED_32_63"              ,        32,     32,     746,    "RAZ",  1,      1,      0,      0},
64271         {"SBE"                         ,        0,      1,      747,    "R/W1C",        0,      0,      0ull,   0ull},
64272         {"DBE"                         ,        1,      1,      747,    "R/W1C",        0,      0,      0ull,   0ull},
64273         {"SBE_IE"                      ,        2,      1,      747,    "R/W",  0,      1,      0ull,   0},
64274         {"DBE_IE"                      ,        3,      1,      747,    "R/W",  0,      1,      0ull,   0},
64275         {"SYN"                         ,        4,      5,      747,    "RO",   1,      1,      0,      0},
64276         {"RESERVED_9_11"               ,        9,      3,      747,    "RAZ",  1,      1,      0,      0},
64277         {"RPE"                         ,        12,     1,      747,    "R/W1C",        0,      0,      0ull,   0ull},
64278         {"RPE_IE"                      ,        13,     1,      747,    "R/W",  0,      1,      0ull,   0},
64279         {"RESERVED_14_15"              ,        14,     2,      747,    "RAZ",  1,      1,      0,      0},
64280         {"IOP"                         ,        16,     13,     747,    "R/W1C",        0,      0,      0ull,   0ull},
64281         {"RESERVED_29_31"              ,        29,     3,      747,    "RAZ",  1,      1,      0,      0},
64282         {"IOP_IE"                      ,        32,     13,     747,    "R/W",  0,      1,      0ull,   0},
64283         {"RESERVED_45_63"              ,        45,     19,     747,    "RAZ",  1,      1,      0,      0},
64284         {"NBR_THR"                     ,        0,      5,      748,    "R/W",  0,      0,      2ull,   2ull},
64285         {"PFR_DIS"                     ,        5,      1,      748,    "R/W",  0,      0,      0ull,   0ull},
64286         {"RESERVED_6_63"               ,        6,      58,     748,    "RAZ",  1,      1,      0,      0},
64287         {"IQ_CNT"                      ,        0,      32,     749,    "RO",   0,      1,      0ull,   0},
64288         {"RESERVED_32_63"              ,        32,     32,     749,    "RAZ",  1,      1,      0,      0},
64289         {"IQ_CNT"                      ,        0,      32,     750,    "RO",   0,      1,      0ull,   0},
64290         {"RESERVED_32_63"              ,        32,     32,     750,    "RAZ",  1,      1,      0,      0},
64291         {"IQ_INT"                      ,        0,      8,      751,    "R/W1C",        0,      1,      0ull,   0},
64292         {"RESERVED_8_63"               ,        8,      56,     751,    "RAZ",  1,      1,      0,      0},
64293         {"INT_EN"                      ,        0,      8,      752,    "R/W",  0,      1,      0ull,   0},
64294         {"RESERVED_8_63"               ,        8,      56,     752,    "RAZ",  1,      1,      0,      0},
64295         {"IQ_THR"                      ,        0,      32,     753,    "R/W",  0,      1,      4294967295ull,  0},
64296         {"RESERVED_32_63"              ,        32,     32,     753,    "RAZ",  1,      1,      0,      0},
64297         {"NOS_CNT"                     ,        0,      10,     754,    "RO",   0,      1,      0ull,   0},
64298         {"RESERVED_10_63"              ,        10,     54,     754,    "RAZ",  1,      1,      0,      0},
64299         {"NW_TIM"                      ,        0,      10,     755,    "R/W",  0,      0,      0ull,   1023ull},
64300         {"RESERVED_10_63"              ,        10,     54,     755,    "RAZ",  1,      1,      0,      0},
64301         {"RST_MSK"                     ,        0,      8,      756,    "R/W",  0,      1,      0ull,   0},
64302         {"RESERVED_8_63"               ,        8,      56,     756,    "RAZ",  1,      1,      0,      0},
64303         {"GRP_MSK"                     ,        0,      16,     757,    "R/W",  0,      0,      65535ull,       65535ull},
64304         {"QOS0_PRI"                    ,        16,     4,      757,    "R/W",  0,      1,      0ull,   0},
64305         {"QOS1_PRI"                    ,        20,     4,      757,    "R/W",  0,      1,      0ull,   0},
64306         {"QOS2_PRI"                    ,        24,     4,      757,    "R/W",  0,      1,      0ull,   0},
64307         {"QOS3_PRI"                    ,        28,     4,      757,    "R/W",  0,      1,      0ull,   0},
64308         {"QOS4_PRI"                    ,        32,     4,      757,    "R/W",  0,      1,      0ull,   0},
64309         {"QOS5_PRI"                    ,        36,     4,      757,    "R/W",  0,      1,      0ull,   0},
64310         {"QOS6_PRI"                    ,        40,     4,      757,    "R/W",  0,      1,      0ull,   0},
64311         {"QOS7_PRI"                    ,        44,     4,      757,    "R/W",  0,      1,      0ull,   0},
64312         {"RESERVED_48_63"              ,        48,     16,     757,    "RAZ",  1,      1,      0,      0},
64313         {"RND"                         ,        0,      8,      758,    "R/W",  0,      1,      255ull, 0},
64314         {"RND_P1"                      ,        8,      8,      758,    "R/W",  0,      1,      255ull, 0},
64315         {"RND_P2"                      ,        16,     8,      758,    "R/W",  0,      1,      255ull, 0},
64316         {"RND_P3"                      ,        24,     8,      758,    "R/W",  0,      1,      255ull, 0},
64317         {"RESERVED_32_63"              ,        32,     32,     758,    "RAZ",  1,      1,      0,      0},
64318         {"MIN_THR"                     ,        0,      9,      759,    "R/W",  0,      1,      0ull,   0},
64319         {"RESERVED_9_11"               ,        9,      3,      759,    "RAZ",  1,      1,      0,      0},
64320         {"MAX_THR"                     ,        12,     9,      759,    "R/W",  0,      1,      511ull, 0},
64321         {"RESERVED_21_23"              ,        21,     3,      759,    "RAZ",  1,      1,      0,      0},
64322         {"FREE_CNT"                    ,        24,     10,     759,    "RO",   0,      1,      503ull, 0},
64323         {"RESERVED_34_35"              ,        34,     2,      759,    "RAZ",  1,      1,      0,      0},
64324         {"BUF_CNT"                     ,        36,     10,     759,    "RO",   0,      1,      0ull,   0},
64325         {"RESERVED_46_47"              ,        46,     2,      759,    "RAZ",  1,      1,      0,      0},
64326         {"DES_CNT"                     ,        48,     10,     759,    "RO",   0,      1,      0ull,   0},
64327         {"RESERVED_58_63"              ,        58,     6,      759,    "RAZ",  1,      1,      0,      0},
64328         {"TS_PC"                       ,        0,      32,     760,    "R/W1C",        0,      1,      0ull,   0},
64329         {"RESERVED_32_63"              ,        32,     32,     760,    "RAZ",  1,      1,      0,      0},
64330         {"WA_PC"                       ,        0,      32,     761,    "R/W1C",        0,      1,      0ull,   0},
64331         {"RESERVED_32_63"              ,        32,     32,     761,    "RAZ",  1,      1,      0,      0},
64332         {"WA_PC"                       ,        0,      32,     762,    "R/W1C",        0,      1,      0ull,   0},
64333         {"RESERVED_32_63"              ,        32,     32,     762,    "RAZ",  1,      1,      0,      0},
64334         {"WQ_INT"                      ,        0,      16,     763,    "R/W1C",        0,      1,      0ull,   0},
64335         {"IQ_DIS"                      ,        16,     16,     763,    "R/W1", 0,      1,      0ull,   0},
64336         {"RESERVED_32_63"              ,        32,     32,     763,    "RAZ",  1,      1,      0,      0},
64337         {"IQ_CNT"                      ,        0,      10,     764,    "RO",   0,      1,      0ull,   0},
64338         {"RESERVED_10_11"              ,        10,     2,      764,    "RAZ",  1,      1,      0,      0},
64339         {"DS_CNT"                      ,        12,     10,     764,    "RO",   0,      1,      0ull,   0},
64340         {"RESERVED_22_23"              ,        22,     2,      764,    "RAZ",  1,      1,      0,      0},
64341         {"TC_CNT"                      ,        24,     4,      764,    "RO",   0,      1,      0ull,   0},
64342         {"RESERVED_28_63"              ,        28,     36,     764,    "RAZ",  1,      1,      0,      0},
64343         {"RESERVED_0_7"                ,        0,      8,      765,    "RAZ",  1,      1,      0,      0},
64344         {"PC_THR"                      ,        8,      20,     765,    "R/W",  0,      1,      0ull,   0},
64345         {"RESERVED_28_31"              ,        28,     4,      765,    "RAZ",  1,      1,      0,      0},
64346         {"PC"                          ,        32,     28,     765,    "RO",   0,      1,      0ull,   0},
64347         {"RESERVED_60_63"              ,        60,     4,      765,    "RAZ",  1,      1,      0,      0},
64348         {"IQ_THR"                      ,        0,      9,      766,    "R/W",  0,      1,      0ull,   0},
64349         {"RESERVED_9_11"               ,        9,      3,      766,    "RAZ",  1,      1,      0,      0},
64350         {"DS_THR"                      ,        12,     9,      766,    "R/W",  0,      1,      0ull,   0},
64351         {"RESERVED_21_23"              ,        21,     3,      766,    "RAZ",  1,      1,      0,      0},
64352         {"TC_THR"                      ,        24,     4,      766,    "R/W",  0,      1,      0ull,   0},
64353         {"TC_EN"                       ,        28,     1,      766,    "R/W",  0,      1,      0ull,   0},
64354         {"RESERVED_29_63"              ,        29,     35,     766,    "RAZ",  1,      1,      0,      0},
64355         {"WS_PC"                       ,        0,      32,     767,    "R/W1C",        0,      1,      0ull,   0},
64356         {"RESERVED_32_63"              ,        32,     32,     767,    "RAZ",  1,      1,      0,      0},
64357         {"IWORD"                       ,        0,      64,     768,    "RO",   1,      1,      0,      0},
64358         {"P_DAT"                       ,        0,      64,     769,    "RO",   1,      1,      0,      0},
64359         {"Q_DAT"                       ,        0,      64,     770,    "RO",   1,      1,      0,      0},
64360         {"DAT"                         ,        0,      2,      771,    "RO",   1,      0,      0,      0ull},
64361         {"NCB_INB"                     ,        2,      2,      771,    "RO",   1,      0,      0,      0ull},
64362         {"NCB_OUB"                     ,        4,      1,      771,    "RO",   1,      0,      0,      0ull},
64363         {"STA"                         ,        5,      1,      771,    "RO",   1,      0,      0,      0ull},
64364         {"RESERVED_6_63"               ,        6,      58,     771,    "RAZ",  0,      0,      0ull,   0ull},
64365         {"PTR"                         ,        0,      33,     772,    "R/W",  0,      1,      0ull,   0},
64366         {"SIZE"                        ,        33,     13,     772,    "R/W",  0,      1,      0ull,   0},
64367         {"POOL"                        ,        46,     3,      772,    "R/W",  0,      1,      0ull,   0},
64368         {"DWB"                         ,        49,     9,      772,    "R/W",  0,      1,      0ull,   0},
64369         {"RESERVED_58_63"              ,        58,     6,      772,    "RAZ",  0,      0,      0ull,   0ull},
64370         {"RESET"                       ,        0,      1,      773,    "RAZ",  0,      0,      0ull,   0ull},
64371         {"STORE_LE"                    ,        1,      1,      773,    "R/W",  0,      0,      0ull,   0ull},
64372         {"MAX_READ"                    ,        2,      4,      773,    "R/W",  0,      0,      8ull,   8ull},
64373         {"RESERVED_6_63"               ,        6,      58,     773,    "RAZ",  0,      0,      0ull,   0ull},
64374         {"STATE"                       ,        0,      5,      774,    "RO",   1,      1,      0,      0},
64375         {"COMMIT"                      ,        5,      1,      774,    "RO",   1,      1,      0,      0},
64376         {"OWORDPV"                     ,        6,      1,      774,    "RO",   1,      1,      0,      0},
64377         {"OWORDQV"                     ,        7,      1,      774,    "RO",   1,      1,      0,      0},
64378         {"IWIDX"                       ,        8,      6,      774,    "RO",   1,      1,      0,      0},
64379         {"RESERVED_14_15"              ,        14,     2,      774,    "RAZ",  1,      1,      0,      0},
64380         {"IRIDX"                       ,        16,     6,      774,    "RO",   1,      1,      0,      0},
64381         {"RESERVED_22_31"              ,        22,     10,     774,    "RAZ",  1,      1,      0,      0},
64382         {"LOOP"                        ,        32,     25,     774,    "RO",   1,      1,      0,      0},
64383         {"RESERVED_57_63"              ,        57,     7,      774,    "RAZ",  1,      1,      0,      0},
64384         {"CWORD"                       ,        0,      64,     775,    "RO",   1,      1,      0,      0},
64385         {"PTR"                         ,        0,      40,     776,    "RO",   1,      1,      0,      0},
64386         {"SIZE"                        ,        40,     16,     776,    "RO",   1,      1,      0,      0},
64387         {"FLAGS"                       ,        56,     8,      776,    "RO",   1,      1,      0,      0},
64388         {"INDEX"                       ,        0,      8,      777,    "RO",   1,      1,      0,      0},
64389         {"SOD"                         ,        8,      1,      777,    "RO",   1,      1,      0,      0},
64390         {"EOD"                         ,        9,      1,      777,    "RO",   1,      1,      0,      0},
64391         {"WC"                          ,        10,     1,      777,    "RO",   1,      1,      0,      0},
64392         {"P"                           ,        11,     1,      777,    "RO",   1,      1,      0,      0},
64393         {"Q"                           ,        12,     1,      777,    "RO",   1,      1,      0,      0},
64394         {"RESERVED_13_63"              ,        13,     51,     777,    "RAZ",  0,      0,      0ull,   0ull},
64395         {"ASSERTS"                     ,        0,      15,     778,    "RO",   1,      1,      0,      0},
64396         {"RESERVED_15_63"              ,        15,     49,     778,    "RAZ",  0,      0,      0ull,   0ull},
64397         {"OWORDP"                      ,        0,      64,     779,    "RO",   1,      1,      0,      0},
64398         {"OWORDQ"                      ,        0,      64,     780,    "RO",   1,      1,      0,      0},
64399         {"RWORD"                       ,        0,      64,     781,    "RO",   1,      1,      0,      0},
64400         {"N0CREDS"                     ,        0,      4,      782,    "RO",   0,      0,      8ull,   0ull},
64401         {"N1CREDS"                     ,        4,      4,      782,    "RO",   0,      0,      8ull,   0ull},
64402         {"POWCREDS"                    ,        8,      2,      782,    "RO",   0,      0,      2ull,   0ull},
64403         {"RESERVED_10_11"              ,        10,     2,      782,    "RAZ",  0,      0,      0ull,   0ull},
64404         {"FPACREDS"                    ,        12,     2,      782,    "RO",   0,      0,      1ull,   0ull},
64405         {"WCCREDS"                     ,        14,     2,      782,    "RO",   0,      0,      0ull,   0ull},
64406         {"NIWIDX0"                     ,        16,     4,      782,    "RO",   1,      1,      0,      0},
64407         {"NIRIDX0"                     ,        20,     4,      782,    "RO",   1,      1,      0,      0},
64408         {"NIWIDX1"                     ,        24,     4,      782,    "RO",   1,      1,      0,      0},
64409         {"NIRIDX1"                     ,        28,     4,      782,    "RO",   1,      1,      0,      0},
64410         {"NIRVAL6"                     ,        32,     5,      782,    "RO",   1,      1,      0,      0},
64411         {"NIRARB6"                     ,        37,     1,      782,    "RO",   1,      1,      0,      0},
64412         {"NIRQUE6"                     ,        38,     2,      782,    "RO",   1,      1,      0,      0},
64413         {"NIROPC6"                     ,        40,     3,      782,    "RO",   1,      1,      0,      0},
64414         {"NIRVAL7"                     ,        43,     5,      782,    "RO",   1,      1,      0,      0},
64415         {"NIRQUE7"                     ,        48,     2,      782,    "RO",   1,      1,      0,      0},
64416         {"NIROPC7"                     ,        50,     3,      782,    "RO",   1,      1,      0,      0},
64417         {"RESERVED_53_63"              ,        53,     11,     782,    "RAZ",  0,      0,      0ull,   0ull},
64418         {"PTR"                         ,        0,      40,     783,    "RO",   1,      1,      0,      0},
64419         {"SIZE"                        ,        40,     16,     783,    "RO",   1,      1,      0,      0},
64420         {"CNT"                         ,        56,     8,      783,    "RO",   1,      1,      0,      0},
64421         {"CNT"                         ,        0,      15,     784,    "RO",   1,      1,      0,      0},
64422         {"RESERVED_15_63"              ,        15,     49,     784,    "RAZ",  0,      0,      0ull,   0ull},
64423         {"PTR"                         ,        0,      40,     785,    "RO",   1,      1,      0,      0},
64424         {"SIZE"                        ,        40,     16,     785,    "RO",   1,      1,      0,      0},
64425         {"FLAGS"                       ,        56,     8,      785,    "RO",   1,      1,      0,      0},
64426         {"INDEX"                       ,        0,      8,      786,    "RO",   1,      1,      0,      0},
64427         {"MUL"                         ,        8,      8,      786,    "RO",   1,      1,      0,      0},
64428         {"P"                           ,        16,     1,      786,    "RO",   1,      1,      0,      0},
64429         {"Q"                           ,        17,     1,      786,    "RO",   1,      1,      0,      0},
64430         {"INI"                         ,        18,     1,      786,    "RO",   1,      1,      0,      0},
64431         {"EOD"                         ,        19,     1,      786,    "RO",   1,      1,      0,      0},
64432         {"RESERVED_20_63"              ,        20,     44,     786,    "RAZ",  0,      0,      0ull,   0ull},
64433         {"DOORBELL"                    ,        0,      1,      787,    "R/W1C",        0,      0,      0ull,   0ull},
64434         {"RESERVED_1_63"               ,        1,      63,     787,    "RAZ",  0,      0,      0ull,   0ull},
64435         {"DOORBELL"                    ,        0,      1,      788,    "R/W",  0,      0,      0ull,   0ull},
64436         {"RESERVED_1_63"               ,        1,      63,     788,    "RAZ",  0,      0,      0ull,   0ull},
64437         {"COEFFS"                      ,        0,      8,      789,    "R/W",  0,      0,      29ull,  29ull},
64438         {"RESERVED_8_63"               ,        8,      56,     789,    "RAZ",  0,      0,      0ull,   0ull},
64439         {"INDEX"                       ,        0,      16,     790,    "R/W",  0,      0,      0ull,   0ull},
64440         {"INC"                         ,        16,     16,     790,    "R/W",  0,      0,      0ull,   0ull},
64441         {"RESERVED_32_63"              ,        32,     32,     790,    "RAZ",  0,      0,      0ull,   0ull},
64442         {"MEM"                         ,        0,      1,      791,    "RO",   0,      0,      0ull,   0ull},
64443         {"RRC"                         ,        1,      1,      791,    "RO",   0,      0,      0ull,   0ull},
64444         {"RESERVED_2_63"               ,        2,      62,     791,    "RAZ",  1,      1,      0,      0},
64445         {"ENT_EN"                      ,        0,      1,      792,    "R/W",  0,      0,      0ull,   0ull},
64446         {"RNG_EN"                      ,        1,      1,      792,    "R/W",  0,      0,      0ull,   0ull},
64447         {"RNM_RST"                     ,        2,      1,      792,    "R/W",  0,      0,      0ull,   0ull},
64448         {"RNG_RST"                     ,        3,      1,      792,    "R/W",  0,      0,      0ull,   0ull},
64449         {"EXP_ENT"                     ,        4,      1,      792,    "R/W",  0,      0,      0ull,   0ull},
64450         {"ENT_SEL"                     ,        5,      4,      792,    "R/W",  0,      0,      0ull,   0ull},
64451         {"RESERVED_9_63"               ,        9,      55,     792,    "RAZ",  1,      1,      0,      0},
64452         {"PHASE"                       ,        0,      8,      793,    "R/W",  0,      0,      100ull, 100ull},
64453         {"SAMPLE"                      ,        8,      4,      793,    "R/W",  0,      0,      2ull,   2ull},
64454         {"PREAMBLE"                    ,        12,     1,      793,    "R/W",  0,      0,      1ull,   1ull},
64455         {"CLK_IDLE"                    ,        13,     1,      793,    "R/W",  0,      0,      0ull,   0ull},
64456         {"RESERVED_14_14"              ,        14,     1,      793,    "RAZ",  1,      1,      0,      0},
64457         {"SAMPLE_MODE"                 ,        15,     1,      793,    "RAZ",  0,      0,      0ull,   0ull},
64458         {"SAMPLE_HI"                   ,        16,     5,      793,    "R/W",  0,      0,      0ull,   0ull},
64459         {"RESERVED_21_23"              ,        21,     3,      793,    "RAZ",  1,      1,      0,      0},
64460         {"MODE"                        ,        24,     1,      793,    "R/W",  0,      0,      0ull,   0ull},
64461         {"RESERVED_25_63"              ,        25,     39,     793,    "RAZ",  1,      1,      0,      0},
64462         {"REG_ADR"                     ,        0,      5,      794,    "R/W",  0,      1,      0ull,   0},
64463         {"RESERVED_5_7"                ,        5,      3,      794,    "RAZ",  1,      1,      0,      0},
64464         {"PHY_ADR"                     ,        8,      5,      794,    "R/W",  0,      1,      0ull,   0},
64465         {"RESERVED_13_15"              ,        13,     3,      794,    "RAZ",  1,      1,      0,      0},
64466         {"PHY_OP"                      ,        16,     2,      794,    "R/W",  0,      1,      0ull,   0},
64467         {"RESERVED_18_63"              ,        18,     46,     794,    "RAZ",  1,      1,      0,      0},
64468         {"EN"                          ,        0,      1,      795,    "R/W",  0,      0,      0ull,   1ull},
64469         {"RESERVED_1_63"               ,        1,      63,     795,    "RAZ",  1,      1,      0,      0},
64470         {"DAT"                         ,        0,      16,     796,    "RO",   0,      1,      0ull,   0},
64471         {"VAL"                         ,        16,     1,      796,    "RO",   0,      1,      0ull,   0},
64472         {"PENDING"                     ,        17,     1,      796,    "RO",   0,      1,      0ull,   0},
64473         {"RESERVED_18_63"              ,        18,     46,     796,    "RAZ",  1,      1,      0,      0},
64474         {"DAT"                         ,        0,      16,     797,    "R/W",  0,      1,      0ull,   0},
64475         {"VAL"                         ,        16,     1,      797,    "RO",   0,      1,      0ull,   0},
64476         {"PENDING"                     ,        17,     1,      797,    "RO",   0,      1,      0ull,   0},
64477         {"RESERVED_18_63"              ,        18,     46,     797,    "RAZ",  1,      1,      0,      0},
64478         {"INTERVAL"                    ,        0,      22,     798,    "RO",   1,      0,      0,      0ull},
64479         {"RESERVED_22_23"              ,        22,     2,      798,    "RAZ",  1,      0,      0,      0ull},
64480         {"COUNT"                       ,        24,     22,     798,    "RO",   1,      0,      0,      0ull},
64481         {"RESERVED_46_46"              ,        46,     1,      798,    "RAZ",  1,      0,      0,      0ull},
64482         {"ENA"                         ,        47,     1,      798,    "RO",   1,      0,      0,      0ull},
64483         {"RESERVED_48_63"              ,        48,     16,     798,    "RAZ",  1,      0,      0,      0ull},
64484         {"BSIZE"                       ,        0,      20,     799,    "RO",   1,      0,      0,      0ull},
64485         {"BASE"                        ,        20,     31,     799,    "RO",   1,      0,      0,      0ull},
64486         {"BUCKET"                      ,        51,     13,     799,    "RO",   1,      0,      0,      0ull},
64487         {"BUCKET"                      ,        0,      7,      800,    "RO",   1,      0,      0,      0ull},
64488         {"RESERVED_7_7"                ,        7,      1,      800,    "RAZ",  1,      0,      0,      0ull},
64489         {"CSIZE"                       ,        8,      13,     800,    "RO",   1,      0,      0,      0ull},
64490         {"CPOOL"                       ,        21,     3,      800,    "RO",   1,      0,      0,      0ull},
64491         {"RESERVED_24_63"              ,        24,     40,     800,    "RAZ",  1,      0,      0,      0ull},
64492         {"RING"                        ,        0,      4,      801,    "R/W",  0,      0,      0ull,   0ull},
64493         {"NUM_BUCKETS"                 ,        4,      20,     801,    "R/W",  0,      0,      0ull,   0ull},
64494         {"FIRST_BUCKET"                ,        24,     31,     801,    "R/W",  0,      0,      0ull,   0ull},
64495         {"RESERVED_55_63"              ,        55,     9,      801,    "RAZ",  1,      0,      0,      0ull},
64496         {"RING"                        ,        0,      4,      802,    "R/W",  0,      0,      0ull,   0ull},
64497         {"INTERVAL"                    ,        4,      22,     802,    "R/W",  0,      0,      0ull,   0ull},
64498         {"WORDS_PER_CHUNK"             ,        26,     13,     802,    "R/W",  0,      0,      0ull,   0ull},
64499         {"POOL"                        ,        39,     3,      802,    "R/W",  0,      0,      0ull,   0ull},
64500         {"ENABLE"                      ,        42,     1,      802,    "R/W",  0,      0,      0ull,   0ull},
64501         {"RESERVED_43_63"              ,        43,     21,     802,    "RAZ",  1,      0,      0,      0ull},
64502         {"CTL"                         ,        0,      1,      803,    "RO",   1,      0,      0,      0ull},
64503         {"NCB"                         ,        1,      1,      803,    "RO",   1,      0,      0,      0ull},
64504         {"STA"                         ,        2,      2,      803,    "RO",   1,      0,      0,      0ull},
64505         {"RESERVED_4_63"               ,        4,      60,     803,    "RAZ",  1,      0,      0,      0ull},
64506         {"MASK"                        ,        0,      16,     804,    "R/W1C",        0,      0,      0ull,   0ull},
64507         {"RESERVED_16_63"              ,        16,     48,     804,    "RAZ",  1,      0,      0,      0ull},
64508         {"ENABLE_TIMERS"               ,        0,      1,      805,    "R/W",  0,      0,      0ull,   0ull},
64509         {"ENABLE_DWB"                  ,        1,      1,      805,    "R/W",  0,      0,      0ull,   0ull},
64510         {"RESET"                       ,        2,      1,      805,    "RAZ",  0,      0,      0ull,   0ull},
64511         {"RESERVED_3_63"               ,        3,      61,     805,    "RAZ",  1,      0,      0,      0ull},
64512         {"MASK"                        ,        0,      16,     806,    "R/W",  0,      0,      0ull,   0ull},
64513         {"RESERVED_16_63"              ,        16,     48,     806,    "RAZ",  1,      0,      0,      0ull},
64514         {"INDEX"                       ,        0,      8,      807,    "R/W",  0,      0,      0ull,   0ull},
64515         {"INC"                         ,        8,      8,      807,    "R/W",  0,      0,      0ull,   0ull},
64516         {"RESERVED_16_63"              ,        16,     48,     807,    "RAZ",  1,      0,      0,      0ull},
64517         {"TDF0"                        ,        0,      1,      808,    "RO",   0,      0,      0ull,   0ull},
64518         {"TDF1"                        ,        1,      1,      808,    "RO",   0,      0,      0ull,   0ull},
64519         {"TCF"                         ,        2,      1,      808,    "RO",   0,      0,      0ull,   0ull},
64520         {"RESERVED_3_63"               ,        3,      61,     808,    "RAZ",  0,      0,      0ull,   0ull},
64521         {"ENA"                         ,        0,      1,      809,    "R/W",  0,      0,      0ull,   0ull},
64522         {"WRAP"                        ,        1,      1,      809,    "R/W",  0,      0,      0ull,   0ull},
64523         {"TRIG_CTL"                    ,        2,      2,      809,    "R/W",  0,      0,      0ull,   0ull},
64524         {"TIME_GRN"                    ,        4,      3,      809,    "R/W",  0,      0,      0ull,   0ull},
64525         {"FULL_THR"                    ,        7,      2,      809,    "R/W",  0,      0,      0ull,   0ull},
64526         {"CIU_TRG"                     ,        9,      1,      809,    "R/W",  0,      0,      0ull,   0ull},
64527         {"CIU_THR"                     ,        10,     1,      809,    "R/W",  0,      0,      0ull,   0ull},
64528         {"MCD0_TRG"                    ,        11,     1,      809,    "R/W",  0,      0,      0ull,   0ull},
64529         {"MCD0_THR"                    ,        12,     1,      809,    "R/W",  0,      0,      0ull,   0ull},
64530         {"MCD0_ENA"                    ,        13,     1,      809,    "R/W",  0,      0,      0ull,   0ull},
64531         {"IGNORE_O"                    ,        14,     1,      809,    "R/W",  0,      0,      0ull,   0ull},
64532         {"RESERVED_15_63"              ,        15,     49,     809,    "RAZ",  0,      0,      0ull,   0ull},
64533         {"WPTR"                        ,        0,      8,      810,    "RO",   0,      0,      0ull,   0ull},
64534         {"RPTR"                        ,        8,      8,      810,    "RO",   0,      0,      0ull,   0ull},
64535         {"CYCLES"                      ,        16,     48,     810,    "RO",   0,      0,      0ull,   0ull},
64536         {"WPTR"                        ,        0,      10,     811,    "RO",   0,      0,      0ull,   0ull},
64537         {"RESERVED_10_11"              ,        10,     2,      811,    "RAZ",  0,      0,      0ull,   0ull},
64538         {"RPTR"                        ,        12,     10,     811,    "RO",   0,      0,      0ull,   0ull},
64539         {"RESERVED_22_23"              ,        22,     2,      811,    "RAZ",  0,      0,      0ull,   0ull},
64540         {"CYCLES"                      ,        24,     40,     811,    "RO",   0,      0,      0ull,   0ull},
64541         {"ADR"                         ,        0,      36,     812,    "R/W",  0,      1,      0ull,   0},
64542         {"RESERVED_36_63"              ,        36,     28,     812,    "RAZ",  0,      0,      0ull,   0ull},
64543         {"ADR"                         ,        0,      36,     813,    "R/W",  0,      0,      0ull,   0ull},
64544         {"RESERVED_36_63"              ,        36,     28,     813,    "RAZ",  0,      0,      0ull,   0ull},
64545         {"DWB"                         ,        0,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64546         {"PL2"                         ,        1,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64547         {"PSL1"                        ,        2,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64548         {"LDD"                         ,        3,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64549         {"LDI"                         ,        4,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64550         {"LDT"                         ,        5,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64551         {"STF"                         ,        6,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64552         {"STC"                         ,        7,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64553         {"STP"                         ,        8,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64554         {"STT"                         ,        9,      1,      814,    "R/W",  0,      0,      0ull,   1ull},
64555         {"IOBLD8"                      ,        10,     1,      814,    "R/W",  0,      0,      0ull,   1ull},
64556         {"IOBLD16"                     ,        11,     1,      814,    "R/W",  0,      0,      0ull,   1ull},
64557         {"IOBLD32"                     ,        12,     1,      814,    "R/W",  0,      0,      0ull,   1ull},
64558         {"IOBLD64"                     ,        13,     1,      814,    "R/W",  0,      0,      0ull,   1ull},
64559         {"IOBST"                       ,        14,     1,      814,    "R/W",  0,      0,      0ull,   1ull},
64560         {"IOBDMA"                      ,        15,     1,      814,    "R/W",  0,      0,      0ull,   1ull},
64561         {"SAA"                         ,        16,     1,      814,    "R/W",  0,      0,      0ull,   1ull},
64562         {"RESERVED_17_63"              ,        17,     47,     814,    "RAZ",  0,      0,      0ull,   0ull},
64563         {"MIO"                         ,        0,      1,      815,    "R/W",  0,      0,      0ull,   1ull},
64564         {"ILLEGAL3"                    ,        1,      2,      815,    "R/W",  0,      0,      0ull,   3ull},
64565         {"PCI"                         ,        3,      1,      815,    "R/W",  0,      0,      0ull,   1ull},
64566         {"KEY"                         ,        4,      1,      815,    "R/W",  0,      0,      0ull,   1ull},
64567         {"FPA"                         ,        5,      1,      815,    "R/W",  0,      0,      0ull,   1ull},
64568         {"DFA"                         ,        6,      1,      815,    "R/W",  0,      0,      0ull,   1ull},
64569         {"ZIP"                         ,        7,      1,      815,    "R/W",  0,      0,      0ull,   1ull},
64570         {"RNG"                         ,        8,      1,      815,    "R/W",  0,      0,      0ull,   1ull},
64571         {"ILLEGAL2"                    ,        9,      3,      815,    "R/W",  0,      0,      0ull,   7ull},
64572         {"POW"                         ,        12,     1,      815,    "R/W",  0,      0,      0ull,   1ull},
64573         {"ILLEGAL"                     ,        13,     19,     815,    "R/W",  0,      0,      0ull,   524287ull},
64574         {"RESERVED_32_63"              ,        32,     32,     815,    "RAZ",  0,      0,      0ull,   0ull},
64575         {"PP"                          ,        0,      16,     816,    "R/W",  0,      0,      0ull,   0ull},
64576         {"PKI"                         ,        16,     1,      816,    "R/W",  0,      0,      0ull,   0ull},
64577         {"PKO"                         ,        17,     1,      816,    "R/W",  0,      0,      0ull,   0ull},
64578         {"IOBREQ"                      ,        18,     1,      816,    "R/W",  0,      0,      0ull,   0ull},
64579         {"DWB"                         ,        19,     1,      816,    "R/W",  0,      0,      0ull,   0ull},
64580         {"RESERVED_20_63"              ,        20,     44,     816,    "RAZ",  0,      0,      0ull,   0ull},
64581         {"CIU_TRG"                     ,        0,      1,      817,    "R/W1C",        0,      0,      0ull,   0ull},
64582         {"CIU_THR"                     ,        1,      1,      817,    "R/W1C",        0,      0,      0ull,   0ull},
64583         {"MCD0_TRG"                    ,        2,      1,      817,    "R/W1C",        0,      0,      0ull,   0ull},
64584         {"MCD0_THR"                    ,        3,      1,      817,    "R/W1C",        0,      0,      0ull,   0ull},
64585         {"RESERVED_4_63"               ,        4,      60,     817,    "RAZ",  0,      0,      0ull,   0ull},
64586         {"DATA"                        ,        0,      64,     818,    "RO",   0,      0,      0ull,   0ull},
64587         {"ADR"                         ,        0,      36,     819,    "R/W",  0,      1,      0ull,   0},
64588         {"RESERVED_36_63"              ,        36,     28,     819,    "RAZ",  0,      0,      0ull,   0ull},
64589         {"ADR"                         ,        0,      36,     820,    "R/W",  0,      0,      0ull,   0ull},
64590         {"RESERVED_36_63"              ,        36,     28,     820,    "RAZ",  0,      0,      0ull,   0ull},
64591         {"DWB"                         ,        0,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64592         {"PL2"                         ,        1,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64593         {"PSL1"                        ,        2,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64594         {"LDD"                         ,        3,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64595         {"LDI"                         ,        4,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64596         {"LDT"                         ,        5,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64597         {"STF"                         ,        6,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64598         {"STC"                         ,        7,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64599         {"STP"                         ,        8,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64600         {"STT"                         ,        9,      1,      821,    "R/W",  0,      0,      0ull,   1ull},
64601         {"IOBLD8"                      ,        10,     1,      821,    "R/W",  0,      0,      0ull,   1ull},
64602         {"IOBLD16"                     ,        11,     1,      821,    "R/W",  0,      0,      0ull,   1ull},
64603         {"IOBLD32"                     ,        12,     1,      821,    "R/W",  0,      0,      0ull,   1ull},
64604         {"IOBLD64"                     ,        13,     1,      821,    "R/W",  0,      0,      0ull,   1ull},
64605         {"IOBST"                       ,        14,     1,      821,    "R/W",  0,      0,      0ull,   1ull},
64606         {"IOBDMA"                      ,        15,     1,      821,    "R/W",  0,      0,      0ull,   1ull},
64607         {"SAA"                         ,        16,     1,      821,    "R/W",  0,      0,      0ull,   1ull},
64608         {"RESERVED_17_63"              ,        17,     47,     821,    "RAZ",  0,      0,      0ull,   0ull},
64609         {"MIO"                         ,        0,      1,      822,    "R/W",  0,      0,      0ull,   1ull},
64610         {"ILLEGAL3"                    ,        1,      2,      822,    "R/W",  0,      0,      0ull,   3ull},
64611         {"PCI"                         ,        3,      1,      822,    "R/W",  0,      0,      0ull,   1ull},
64612         {"KEY"                         ,        4,      1,      822,    "R/W",  0,      0,      0ull,   1ull},
64613         {"FPA"                         ,        5,      1,      822,    "R/W",  0,      0,      0ull,   1ull},
64614         {"DFA"                         ,        6,      1,      822,    "R/W",  0,      0,      0ull,   1ull},
64615         {"ZIP"                         ,        7,      1,      822,    "R/W",  0,      0,      0ull,   1ull},
64616         {"RNG"                         ,        8,      1,      822,    "R/W",  0,      0,      0ull,   1ull},
64617         {"ILLEGAL2"                    ,        9,      3,      822,    "R/W",  0,      0,      0ull,   7ull},
64618         {"POW"                         ,        12,     1,      822,    "R/W",  0,      0,      0ull,   1ull},
64619         {"ILLEGAL"                     ,        13,     19,     822,    "R/W",  0,      0,      0ull,   524287ull},
64620         {"RESERVED_32_63"              ,        32,     32,     822,    "RAZ",  0,      0,      0ull,   0ull},
64621         {"PP"                          ,        0,      16,     823,    "R/W",  0,      0,      0ull,   0ull},
64622         {"PKI"                         ,        16,     1,      823,    "R/W",  0,      0,      0ull,   0ull},
64623         {"PKO"                         ,        17,     1,      823,    "R/W",  0,      0,      0ull,   0ull},
64624         {"IOBREQ"                      ,        18,     1,      823,    "R/W",  0,      0,      0ull,   0ull},
64625         {"DWB"                         ,        19,     1,      823,    "R/W",  0,      0,      0ull,   0ull},
64626         {"RESERVED_20_63"              ,        20,     44,     823,    "RAZ",  0,      0,      0ull,   0ull},
64627         {"ADR"                         ,        0,      36,     824,    "R/W",  0,      1,      0ull,   0},
64628         {"RESERVED_36_63"              ,        36,     28,     824,    "RAZ",  0,      0,      0ull,   0ull},
64629         {"ADR"                         ,        0,      36,     825,    "R/W",  0,      0,      0ull,   0ull},
64630         {"RESERVED_36_63"              ,        36,     28,     825,    "RAZ",  0,      0,      0ull,   0ull},
64631         {"DWB"                         ,        0,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64632         {"PL2"                         ,        1,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64633         {"PSL1"                        ,        2,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64634         {"LDD"                         ,        3,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64635         {"LDI"                         ,        4,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64636         {"LDT"                         ,        5,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64637         {"STF"                         ,        6,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64638         {"STC"                         ,        7,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64639         {"STP"                         ,        8,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64640         {"STT"                         ,        9,      1,      826,    "R/W",  0,      0,      0ull,   1ull},
64641         {"IOBLD8"                      ,        10,     1,      826,    "R/W",  0,      0,      0ull,   1ull},
64642         {"IOBLD16"                     ,        11,     1,      826,    "R/W",  0,      0,      0ull,   1ull},
64643         {"IOBLD32"                     ,        12,     1,      826,    "R/W",  0,      0,      0ull,   1ull},
64644         {"IOBLD64"                     ,        13,     1,      826,    "R/W",  0,      0,      0ull,   1ull},
64645         {"IOBST"                       ,        14,     1,      826,    "R/W",  0,      0,      0ull,   1ull},
64646         {"IOBDMA"                      ,        15,     1,      826,    "R/W",  0,      0,      0ull,   1ull},
64647         {"SAA"                         ,        16,     1,      826,    "R/W",  0,      0,      0ull,   1ull},
64648         {"RESERVED_17_63"              ,        17,     47,     826,    "RAZ",  0,      0,      0ull,   0ull},
64649         {"MIO"                         ,        0,      1,      827,    "R/W",  0,      0,      0ull,   1ull},
64650         {"ILLEGAL3"                    ,        1,      2,      827,    "R/W",  0,      0,      0ull,   3ull},
64651         {"PCI"                         ,        3,      1,      827,    "R/W",  0,      0,      0ull,   1ull},
64652         {"KEY"                         ,        4,      1,      827,    "R/W",  0,      0,      0ull,   1ull},
64653         {"FPA"                         ,        5,      1,      827,    "R/W",  0,      0,      0ull,   1ull},
64654         {"DFA"                         ,        6,      1,      827,    "R/W",  0,      0,      0ull,   1ull},
64655         {"ZIP"                         ,        7,      1,      827,    "R/W",  0,      0,      0ull,   1ull},
64656         {"RNG"                         ,        8,      1,      827,    "R/W",  0,      0,      0ull,   1ull},
64657         {"ILLEGAL2"                    ,        9,      3,      827,    "R/W",  0,      0,      0ull,   7ull},
64658         {"POW"                         ,        12,     1,      827,    "R/W",  0,      0,      0ull,   1ull},
64659         {"ILLEGAL"                     ,        13,     19,     827,    "R/W",  0,      0,      0ull,   524287ull},
64660         {"RESERVED_32_63"              ,        32,     32,     827,    "RAZ",  0,      0,      0ull,   0ull},
64661         {"PP"                          ,        0,      16,     828,    "R/W",  0,      0,      0ull,   0ull},
64662         {"PKI"                         ,        16,     1,      828,    "R/W",  0,      0,      0ull,   0ull},
64663         {"PKO"                         ,        17,     1,      828,    "R/W",  0,      0,      0ull,   0ull},
64664         {"IOBREQ"                      ,        18,     1,      828,    "R/W",  0,      0,      0ull,   0ull},
64665         {"DWB"                         ,        19,     1,      828,    "R/W",  0,      0,      0ull,   0ull},
64666         {"RESERVED_20_63"              ,        20,     44,     828,    "RAZ",  0,      0,      0ull,   0ull},
64667         {"INEPINT"                     ,        0,      16,     829,    "RO",   0,      0,      0ull,   0ull},
64668         {"OUTEPINT"                    ,        16,     16,     829,    "RO",   0,      0,      0ull,   0ull},
64669         {"INEPMSK"                     ,        0,      16,     830,    "R/W",  0,      0,      0ull,   0ull},
64670         {"OUTEPMSK"                    ,        16,     16,     830,    "R/W",  0,      0,      0ull,   0ull},
64671         {"DEVSPD"                      ,        0,      2,      831,    "R/W",  0,      0,      0ull,   0ull},
64672         {"NZSTSOUTHSHK"                ,        2,      1,      831,    "R/W",  0,      0,      0ull,   0ull},
64673         {"RESERVED_3_3"                ,        3,      1,      831,    "RAZ",  1,      1,      0,      0},
64674         {"DEVADDR"                     ,        4,      7,      831,    "R/W",  0,      0,      0ull,   0ull},
64675         {"PERFRINT"                    ,        11,     2,      831,    "R/W",  0,      0,      0ull,   0ull},
64676         {"RESERVED_13_17"              ,        13,     5,      831,    "RAZ",  1,      1,      0,      0},
64677         {"EPMISCNT"                    ,        18,     5,      831,    "R/W",  0,      0,      8ull,   0ull},
64678         {"RESERVED_23_31"              ,        23,     9,      831,    "RAZ",  1,      1,      0,      0},
64679         {"RMTWKUPSIG"                  ,        0,      1,      832,    "R/W",  0,      0,      0ull,   0ull},
64680         {"SFTDISCON"                   ,        1,      1,      832,    "R/W",  0,      0,      0ull,   0ull},
64681         {"GNPINNAKSTS"                 ,        2,      1,      832,    "RO",   0,      0,      0ull,   0ull},
64682         {"GOUTNAKSTS"                  ,        3,      1,      832,    "RO",   0,      0,      0ull,   0ull},
64683         {"TSTCTL"                      ,        4,      3,      832,    "R/W",  0,      0,      0ull,   0ull},
64684         {"SGNPINNAK"                   ,        7,      1,      832,    "WO",   0,      0,      0ull,   0ull},
64685         {"CGNPINNAK"                   ,        8,      1,      832,    "WO",   0,      0,      0ull,   0ull},
64686         {"SGOUTNAK"                    ,        9,      1,      832,    "WO",   0,      0,      0ull,   0ull},
64687         {"CGOUTNAK"                    ,        10,     1,      832,    "WO",   0,      0,      0ull,   0ull},
64688         {"PWRONPRGDONE"                ,        11,     1,      832,    "R/W",  0,      0,      0ull,   0ull},
64689         {"RESERVED_12_31"              ,        12,     20,     832,    "RAZ",  1,      1,      0,      0},
64690         {"MPS"                         ,        0,      11,     833,    "R/W",  0,      0,      0ull,   0ull},
64691         {"NEXTEP"                      ,        11,     4,      833,    "R/W",  0,      0,      0ull,   0ull},
64692         {"USBACTEP"                    ,        15,     1,      833,    "R/W",  0,      0,      1ull,   0ull},
64693         {"DPID"                        ,        16,     1,      833,    "RO",   0,      0,      0ull,   0ull},
64694         {"NAKSTS"                      ,        17,     1,      833,    "RO",   0,      0,      0ull,   0ull},
64695         {"EPTYPE"                      ,        18,     2,      833,    "R/W",  0,      0,      0ull,   0ull},
64696         {"RESERVED_20_20"              ,        20,     1,      833,    "RAZ",  1,      1,      0,      0},
64697         {"STALL"                       ,        21,     1,      833,    "R/W",  0,      0,      0ull,   0ull},
64698         {"TXFNUM"                      ,        22,     4,      833,    "R/W",  0,      0,      0ull,   0ull},
64699         {"CNAK"                        ,        26,     1,      833,    "WO",   0,      0,      0ull,   0ull},
64700         {"SNAK"                        ,        27,     1,      833,    "WO",   0,      0,      0ull,   0ull},
64701         {"SETD0PID"                    ,        28,     1,      833,    "WO",   0,      0,      0ull,   0ull},
64702         {"SETD1PID"                    ,        29,     1,      833,    "WO",   0,      0,      0ull,   0ull},
64703         {"EPDIS"                       ,        30,     1,      833,    "R/W",  0,      0,      0ull,   0ull},
64704         {"EPENA"                       ,        31,     1,      833,    "R/W",  0,      0,      0ull,   0ull},
64705         {"XFERCOMPL"                   ,        0,      1,      834,    "R/W1C",        0,      0,      0ull,   0ull},
64706         {"EPDISBLD"                    ,        1,      1,      834,    "R/W1C",        0,      0,      0ull,   0ull},
64707         {"AHBERR"                      ,        2,      1,      834,    "R/W1C",        0,      0,      0ull,   0ull},
64708         {"TIMEOUT"                     ,        3,      1,      834,    "R/W1C",        0,      0,      0ull,   0ull},
64709         {"INTKNTXFEMP"                 ,        4,      1,      834,    "R/W1C",        0,      0,      0ull,   0ull},
64710         {"INTKNEPMIS"                  ,        5,      1,      834,    "R/W1C",        0,      0,      0ull,   0ull},
64711         {"INEPNAKEFF"                  ,        6,      1,      834,    "RO",   0,      0,      0ull,   0ull},
64712         {"RESERVED_7_31"               ,        7,      25,     834,    "RAZ",  1,      1,      0,      0},
64713         {"XFERCOMPLMSK"                ,        0,      1,      835,    "R/W",  0,      0,      0ull,   0ull},
64714         {"EPDISBLDMSK"                 ,        1,      1,      835,    "R/W",  0,      0,      0ull,   0ull},
64715         {"AHBERRMSK"                   ,        2,      1,      835,    "R/W",  0,      0,      0ull,   0ull},
64716         {"TIMEOUTMSK"                  ,        3,      1,      835,    "R/W",  0,      0,      0ull,   0ull},
64717         {"INTKNTXFEMPMSK"              ,        4,      1,      835,    "R/W",  0,      0,      0ull,   0ull},
64718         {"INTKNEPMISMSK"               ,        5,      1,      835,    "R/W",  0,      0,      0ull,   0ull},
64719         {"INEPNAKEFFMSK"               ,        6,      1,      835,    "R/W",  0,      0,      0ull,   0ull},
64720         {"RESERVED_7_31"               ,        7,      25,     835,    "RAZ",  1,      1,      0,      0},
64721         {"XFERSIZE"                    ,        0,      19,     836,    "R/W",  0,      0,      0ull,   0ull},
64722         {"PKTCNT"                      ,        19,     10,     836,    "R/W",  0,      0,      0ull,   0ull},
64723         {"MC"                          ,        29,     2,      836,    "R/W",  0,      0,      0ull,   0ull},
64724         {"RESERVED_31_31"              ,        31,     1,      836,    "RAZ",  1,      1,      0,      0},
64725         {"MPS"                         ,        0,      11,     837,    "R/W",  0,      0,      0ull,   0ull},
64726         {"RESERVED_11_14"              ,        11,     4,      837,    "RAZ",  0,      0,      0ull,   0ull},
64727         {"USBACTEP"                    ,        15,     1,      837,    "R/W",  0,      0,      1ull,   0ull},
64728         {"DPID"                        ,        16,     1,      837,    "RO",   0,      0,      0ull,   0ull},
64729         {"NAKSTS"                      ,        17,     1,      837,    "RO",   0,      0,      0ull,   0ull},
64730         {"EPTYPE"                      ,        18,     2,      837,    "R/W",  0,      0,      0ull,   0ull},
64731         {"SNP"                         ,        20,     1,      837,    "R/W",  0,      0,      0ull,   0ull},
64732         {"STALL"                       ,        21,     1,      837,    "R/W",  0,      0,      0ull,   0ull},
64733         {"RESERVED_22_25"              ,        22,     4,      837,    "RAZ",  1,      1,      0,      0},
64734         {"CNAK"                        ,        26,     1,      837,    "WO",   0,      0,      0ull,   0ull},
64735         {"SNAK"                        ,        27,     1,      837,    "WO",   0,      0,      0ull,   0ull},
64736         {"SETD0PID"                    ,        28,     1,      837,    "WO",   0,      0,      0ull,   0ull},
64737         {"SETD1PID"                    ,        29,     1,      837,    "WO",   0,      0,      0ull,   0ull},
64738         {"EPDIS"                       ,        30,     1,      837,    "R/W",  0,      0,      0ull,   0ull},
64739         {"EPENA"                       ,        31,     1,      837,    "R/W",  0,      0,      0ull,   0ull},
64740         {"XFERCOMPL"                   ,        0,      1,      838,    "R/W1C",        0,      0,      0ull,   0ull},
64741         {"EPDISBLD"                    ,        1,      1,      838,    "R/W1C",        0,      0,      0ull,   0ull},
64742         {"AHBERR"                      ,        2,      1,      838,    "R/W1C",        0,      0,      0ull,   0ull},
64743         {"SETUP"                       ,        3,      1,      838,    "R/W1C",        0,      0,      0ull,   0ull},
64744         {"OUTTKNEPDIS"                 ,        4,      1,      838,    "R/W1C",        0,      0,      0ull,   0ull},
64745         {"RESERVED_5_31"               ,        5,      27,     838,    "RAZ",  1,      1,      0,      0},
64746         {"XFERCOMPLMSK"                ,        0,      1,      839,    "R/W",  0,      0,      0ull,   0ull},
64747         {"EPDISBLDMSK"                 ,        1,      1,      839,    "R/W",  0,      0,      0ull,   0ull},
64748         {"AHBERRMSK"                   ,        2,      1,      839,    "R/W",  0,      0,      0ull,   0ull},
64749         {"SETUPMSK"                    ,        3,      1,      839,    "R/W",  0,      0,      0ull,   0ull},
64750         {"OUTTKNEPDISMSK"              ,        4,      1,      839,    "R/W",  0,      0,      0ull,   0ull},
64751         {"RESERVED_5_31"               ,        5,      27,     839,    "RAZ",  1,      1,      0,      0},
64752         {"XFERSIZE"                    ,        0,      19,     840,    "R/W",  0,      0,      0ull,   0ull},
64753         {"PKTCNT"                      ,        19,     10,     840,    "R/W",  0,      0,      0ull,   0ull},
64754         {"MC"                          ,        29,     2,      840,    "R/W",  0,      0,      0ull,   0ull},
64755         {"RESERVED_31_31"              ,        31,     1,      840,    "RAZ",  1,      1,      0,      0},
64756         {"DPTXFSTADDR"                 ,        0,      16,     841,    "RO",   0,      0,      0ull,   0ull},
64757         {"DPTXFSIZE"                   ,        16,     16,     841,    "RO",   0,      0,      1896ull,        1896ull},
64758         {"SUSPSTS"                     ,        0,      1,      842,    "RO",   0,      0,      0ull,   0ull},
64759         {"ENUMSPD"                     ,        1,      2,      842,    "RO",   0,      0,      0ull,   0ull},
64760         {"ERRTICERR"                   ,        3,      1,      842,    "RO",   0,      0,      0ull,   0ull},
64761         {"RESERVED_4_7"                ,        4,      4,      842,    "RAZ",  1,      1,      0,      0},
64762         {"SOFFN"                       ,        8,      14,     842,    "RO",   0,      0,      0ull,   0ull},
64763         {"RESERVED_22_31"              ,        22,     10,     842,    "RAZ",  1,      1,      0,      0},
64764         {"INTKNWPTR"                   ,        0,      5,      843,    "RO",   0,      0,      0ull,   0ull},
64765         {"RESERVED_5_6"                ,        5,      2,      843,    "RAZ",  1,      1,      0,      0},
64766         {"WRAPBIT"                     ,        7,      1,      843,    "RO",   0,      0,      0ull,   0ull},
64767         {"EPTKN"                       ,        8,      24,     843,    "RO",   0,      0,      0ull,   0ull},
64768         {"EPTKN"                       ,        0,      32,     844,    "RO",   0,      0,      0ull,   0ull},
64769         {"EPTKN"                       ,        0,      32,     845,    "RO",   0,      0,      0ull,   0ull},
64770         {"EPTKN"                       ,        0,      32,     846,    "RO",   0,      0,      0ull,   0ull},
64771         {"GLBLINTRMSK"                 ,        0,      1,      847,    "R/W",  0,      0,      0ull,   1ull},
64772         {"HBSTLEN"                     ,        1,      4,      847,    "R/W",  0,      0,      0ull,   0ull},
64773         {"DMAEN"                       ,        5,      1,      847,    "R/W",  0,      0,      0ull,   0ull},
64774         {"RESERVED_6_6"                ,        6,      1,      847,    "RAZ",  1,      1,      0,      0},
64775         {"NPTXFEMPLVL"                 ,        7,      1,      847,    "R/W",  0,      0,      0ull,   1ull},
64776         {"PTXFEMPLVL"                  ,        8,      1,      847,    "R/W",  0,      0,      0ull,   1ull},
64777         {"RESERVED_9_31"               ,        9,      23,     847,    "RAZ",  1,      1,      0,      0},
64778         {"EPDIR"                       ,        0,      32,     848,    "RO",   0,      0,      0ull,   0ull},
64779         {"OTGMODE"                     ,        0,      3,      849,    "RO",   0,      0,      2ull,   2ull},
64780         {"OTGARCH"                     ,        3,      2,      849,    "RO",   0,      0,      1ull,   1ull},
64781         {"SINGPNT"                     ,        5,      1,      849,    "RO",   0,      0,      0ull,   0ull},
64782         {"HSPHYTYPE"                   ,        6,      2,      849,    "RO",   0,      0,      1ull,   1ull},
64783         {"FSPHYTYPE"                   ,        8,      2,      849,    "RO",   0,      0,      0ull,   0ull},
64784         {"NUMDEVEPS"                   ,        10,     4,      849,    "RO",   0,      0,      4ull,   4ull},
64785         {"NUMHSTCHNL"                  ,        14,     4,      849,    "RO",   0,      0,      7ull,   7ull},
64786         {"PERIOSUPPORT"                ,        18,     1,      849,    "RO",   0,      0,      1ull,   1ull},
64787         {"DYNFIFOSIZING"               ,        19,     1,      849,    "RO",   0,      0,      1ull,   1ull},
64788         {"RESERVED_20_21"              ,        20,     2,      849,    "RAZ",  1,      1,      0,      0},
64789         {"NPTXQDEPTH"                  ,        22,     2,      849,    "RO",   0,      0,      2ull,   2ull},
64790         {"PTXQDEPTH"                   ,        24,     2,      849,    "RO",   0,      0,      2ull,   2ull},
64791         {"TKNQDEPTH"                   ,        26,     5,      849,    "RO",   0,      0,      30ull,  30ull},
64792         {"RESERVED_31_31"              ,        31,     1,      849,    "RAZ",  1,      1,      0,      0},
64793         {"XFERSIZEWIDTH"               ,        0,      4,      850,    "RO",   0,      0,      8ull,   8ull},
64794         {"PKTSIZEWIDTH"                ,        4,      3,      850,    "RO",   0,      0,      6ull,   6ull},
64795         {"OTGEN"                       ,        7,      1,      850,    "RO",   0,      0,      1ull,   1ull},
64796         {"I2C_SELECTION"               ,        8,      1,      850,    "RO",   0,      0,      0ull,   0ull},
64797         {"VENDOR_CONTROL_INTERFACE_SUPPORT",    9,      1,      850,    "RO",   0,      0,      0ull,   0ull},
64798         {"OPTFEATURE"                  ,        10,     1,      850,    "RO",   0,      0,      1ull,   1ull},
64799         {"RSTTYPE"                     ,        11,     1,      850,    "RO",   0,      0,      0ull,   0ull},
64800         {"AHBPHYSYNC"                  ,        12,     1,      850,    "RO",   0,      0,      0ull,   0ull},
64801         {"RESERVED_13_15"              ,        13,     3,      850,    "RAZ",  1,      1,      0,      0},
64802         {"DFIFODEPTH"                  ,        16,     16,     850,    "RO",   0,      0,      1824ull,        1824ull},
64803         {"NUMDEVPERIOEPS"              ,        0,      4,      851,    "RO",   0,      0,      4ull,   4ull},
64804         {"ENABLEPWROPT"                ,        4,      1,      851,    "RO",   0,      0,      0ull,   0ull},
64805         {"AHBFREQ"                     ,        5,      1,      851,    "RO",   0,      0,      1ull,   1ull},
64806         {"RESERVED_6_13"               ,        6,      8,      851,    "RAZ",  1,      1,      0,      0},
64807         {"PHYDATAWIDTH"                ,        14,     2,      851,    "RO",   0,      0,      1ull,   1ull},
64808         {"NUMCTLEPS"                   ,        16,     4,      851,    "RO",   0,      0,      4ull,   4ull},
64809         {"IDDGFLTR"                    ,        20,     1,      851,    "RO",   0,      0,      1ull,   1ull},
64810         {"VBUSVALIDFLTR"               ,        21,     1,      851,    "RO",   0,      0,      1ull,   1ull},
64811         {"AVALIDFLTR"                  ,        22,     1,      851,    "RO",   0,      0,      0ull,   0ull},
64812         {"BVALIDFLTR"                  ,        23,     1,      851,    "RO",   0,      0,      0ull,   0ull},
64813         {"SESSENDFLTR"                 ,        24,     1,      851,    "RO",   0,      0,      0ull,   0ull},
64814         {"ENDEDTRFIFO"                 ,        25,     1,      851,    "RO",   0,      0,      0ull,   0ull},
64815         {"NUMDEVMODINEND"              ,        26,     4,      851,    "RO",   0,      0,      2ull,   2ull},
64816         {"RESERVED_30_31"              ,        30,     2,      851,    "RAZ",  1,      1,      0,      0},
64817         {"RESERVED_0_0"                ,        0,      1,      852,    "RAZ",  1,      1,      0,      0},
64818         {"MODEMISMSK"                  ,        1,      1,      852,    "R/W",  0,      0,      0ull,   0ull},
64819         {"OTGINTMSK"                   ,        2,      1,      852,    "R/W",  0,      0,      0ull,   0ull},
64820         {"SOFMSK"                      ,        3,      1,      852,    "R/W",  0,      0,      0ull,   0ull},
64821         {"RXFLVLMSK"                   ,        4,      1,      852,    "R/W",  0,      0,      0ull,   0ull},
64822         {"NPTXFEMPMSK"                 ,        5,      1,      852,    "R/W",  0,      0,      0ull,   0ull},
64823         {"GINNAKEFFMSK"                ,        6,      1,      852,    "R/W",  0,      0,      0ull,   0ull},
64824         {"GOUTNAKEFFMSK"               ,        7,      1,      852,    "R/W",  0,      0,      0ull,   0ull},
64825         {"ULPICKINTMSK"                ,        8,      1,      852,    "R/W",  0,      0,      0ull,   0ull},
64826         {"I2CINT"                      ,        9,      1,      852,    "R/W",  0,      0,      0ull,   0ull},
64827         {"ERLYSUSPMSK"                 ,        10,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64828         {"USBSUSPMSK"                  ,        11,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64829         {"USBRSTMSK"                   ,        12,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64830         {"ENUMDONEMSK"                 ,        13,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64831         {"ISOOUTDROPMSK"               ,        14,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64832         {"EOPFMSK"                     ,        15,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64833         {"RESERVED_16_16"              ,        16,     1,      852,    "RAZ",  1,      1,      0,      0},
64834         {"EPMISMSK"                    ,        17,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64835         {"INEPINTMSK"                  ,        18,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64836         {"OEPINTMSK"                   ,        19,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64837         {"INCOMPISOINMSK"              ,        20,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64838         {"INCOMPLPMSK"                 ,        21,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64839         {"FETSUSPMSK"                  ,        22,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64840         {"RESERVED_23_23"              ,        23,     1,      852,    "RAZ",  1,      1,      0,      0},
64841         {"PRTINTMSK"                   ,        24,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64842         {"HCHINTMSK"                   ,        25,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64843         {"PTXFEMPMSK"                  ,        26,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64844         {"RESERVED_27_27"              ,        27,     1,      852,    "RAZ",  1,      1,      0,      0},
64845         {"CONIDSTSCHNGMSK"             ,        28,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64846         {"DISCONNINTMSK"               ,        29,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64847         {"SESSREQINTMSK"               ,        30,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64848         {"WKUPINTMSK"                  ,        31,     1,      852,    "R/W",  0,      0,      0ull,   0ull},
64849         {"CURMOD"                      ,        0,      1,      853,    "RO",   0,      0,      0ull,   0ull},
64850         {"MODEMIS"                     ,        1,      1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64851         {"OTGINT"                      ,        2,      1,      853,    "RO",   0,      0,      0ull,   0ull},
64852         {"SOF"                         ,        3,      1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64853         {"RXFLVL"                      ,        4,      1,      853,    "RO",   0,      0,      0ull,   0ull},
64854         {"NPTXFEMP"                    ,        5,      1,      853,    "RO",   0,      0,      0ull,   0ull},
64855         {"GINNAKEFF"                   ,        6,      1,      853,    "RO",   0,      0,      0ull,   0ull},
64856         {"GOUTNAKEFF"                  ,        7,      1,      853,    "RO",   0,      0,      0ull,   0ull},
64857         {"ULPICKINT"                   ,        8,      1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64858         {"I2CINT"                      ,        9,      1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64859         {"ERLYSUSP"                    ,        10,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64860         {"USBSUSP"                     ,        11,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64861         {"USBRST"                      ,        12,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64862         {"ENUMDONE"                    ,        13,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64863         {"ISOOUTDROP"                  ,        14,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64864         {"EOPF"                        ,        15,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64865         {"RESERVED_16_16"              ,        16,     1,      853,    "RAZ",  1,      1,      0,      0},
64866         {"EPMIS"                       ,        17,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64867         {"IEPINT"                      ,        18,     1,      853,    "RO",   0,      0,      0ull,   0ull},
64868         {"OEPINT"                      ,        19,     1,      853,    "RO",   0,      0,      0ull,   0ull},
64869         {"INCOMPISOIN"                 ,        20,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64870         {"INCOMPLP"                    ,        21,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64871         {"FETSUSP"                     ,        22,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64872         {"RESERVED_23_23"              ,        23,     1,      853,    "RAZ",  1,      1,      0,      0},
64873         {"PRTINT"                      ,        24,     1,      853,    "RO",   0,      0,      0ull,   0ull},
64874         {"HCHINT"                      ,        25,     1,      853,    "RO",   0,      0,      0ull,   0ull},
64875         {"PTXFEMP"                     ,        26,     1,      853,    "RO",   0,      0,      0ull,   0ull},
64876         {"RESERVED_27_27"              ,        27,     1,      853,    "RAZ",  1,      1,      0,      0},
64877         {"CONIDSTSCHNG"                ,        28,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64878         {"DISCONNINT"                  ,        29,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64879         {"SESSREQINT"                  ,        30,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64880         {"WKUPINT"                     ,        31,     1,      853,    "R/W1C",        0,      0,      0ull,   0ull},
64881         {"NPTXFSTADDR"                 ,        0,      16,     854,    "R/W",  0,      0,      1824ull,        456ull},
64882         {"NPTXFDEP"                    ,        16,     16,     854,    "R/W",  0,      0,      1824ull,        912ull},
64883         {"NPTXFSPCAVAIL"               ,        0,      16,     855,    "RO",   0,      0,      0ull,   0ull},
64884         {"NPTXQSPCAVAIL"               ,        16,     8,      855,    "RO",   0,      0,      0ull,   0ull},
64885         {"NPTXQTOP"                    ,        24,     7,      855,    "RO",   0,      0,      0ull,   0ull},
64886         {"RESERVED_31_31"              ,        31,     1,      855,    "RAZ",  1,      1,      0,      0},
64887         {"SESREQSCS"                   ,        0,      1,      856,    "R/W",  0,      0,      0ull,   0ull},
64888         {"SESREQ"                      ,        1,      1,      856,    "R/W",  0,      0,      0ull,   0ull},
64889         {"RESERVED_2_7"                ,        2,      6,      856,    "RAZ",  1,      1,      0,      0},
64890         {"HSTNEGSCS"                   ,        8,      1,      856,    "R/W",  0,      0,      0ull,   0ull},
64891         {"HNPREQ"                      ,        9,      1,      856,    "R/W",  0,      0,      0ull,   0ull},
64892         {"HSTSETHNPEN"                 ,        10,     1,      856,    "R/W",  0,      0,      0ull,   0ull},
64893         {"DEVHNPEN"                    ,        11,     1,      856,    "R/W",  0,      0,      0ull,   0ull},
64894         {"RESERVED_12_15"              ,        12,     4,      856,    "RAZ",  1,      1,      0,      0},
64895         {"CONIDSTS"                    ,        16,     1,      856,    "RO",   1,      1,      0,      0},
64896         {"DBNCTIME"                    ,        17,     1,      856,    "RO",   0,      0,      0ull,   0ull},
64897         {"ASESVLD"                     ,        18,     1,      856,    "RO",   1,      1,      0,      0},
64898         {"BSESVLD"                     ,        19,     1,      856,    "RO",   1,      1,      0,      0},
64899         {"RESERVED_20_31"              ,        20,     12,     856,    "RAZ",  1,      1,      0,      0},
64900         {"RESERVED_0_1"                ,        0,      2,      857,    "RAZ",  1,      1,      0,      0},
64901         {"SESENDDET"                   ,        2,      1,      857,    "R/W1C",        0,      0,      0ull,   0ull},
64902         {"RESERVED_3_7"                ,        3,      5,      857,    "RAZ",  1,      1,      0,      0},
64903         {"SESREQSUCSTSCHNG"            ,        8,      1,      857,    "R/W1C",        0,      0,      0ull,   0ull},
64904         {"HSTNEGSUCSTSCHNG"            ,        9,      1,      857,    "R/W1C",        0,      0,      0ull,   0ull},
64905         {"RESERVED_10_16"              ,        10,     7,      857,    "RAZ",  1,      1,      0,      0},
64906         {"HSTNEGDET"                   ,        17,     1,      857,    "R/W1C",        0,      0,      0ull,   0ull},
64907         {"ADEVTOUTCHG"                 ,        18,     1,      857,    "R/W1C",        0,      0,      0ull,   0ull},
64908         {"DBNCEDONE"                   ,        19,     1,      857,    "R/W1C",        0,      0,      0ull,   0ull},
64909         {"RESERVED_20_31"              ,        20,     12,     857,    "RAZ",  1,      1,      0,      0},
64910         {"CSFTRST"                     ,        0,      1,      858,    "R/W",  0,      0,      0ull,   0ull},
64911         {"HSFTRST"                     ,        1,      1,      858,    "R/W",  0,      0,      0ull,   0ull},
64912         {"FRMCNTRRST"                  ,        2,      1,      858,    "R/W",  0,      0,      0ull,   0ull},
64913         {"INTKNQFLSH"                  ,        3,      1,      858,    "R/W",  0,      0,      0ull,   0ull},
64914         {"RXFFLSH"                     ,        4,      1,      858,    "R/W",  0,      0,      0ull,   0ull},
64915         {"TXFFLSH"                     ,        5,      1,      858,    "R/W",  0,      0,      0ull,   0ull},
64916         {"TXFNUM"                      ,        6,      5,      858,    "R/W",  0,      0,      0ull,   0ull},
64917         {"RESERVED_11_29"              ,        11,     19,     858,    "RAZ",  1,      1,      0,      0},
64918         {"DMAREQ"                      ,        30,     1,      858,    "RO",   0,      0,      0ull,   0ull},
64919         {"AHBIDLE"                     ,        31,     1,      858,    "RO",   0,      0,      1ull,   1ull},
64920         {"RXFDEP"                      ,        0,      16,     859,    "R/W",  0,      0,      1824ull,        456ull},
64921         {"RESERVED_16_31"              ,        16,     16,     859,    "RAZ",  1,      1,      0,      0},
64922         {"EPNUM"                       ,        0,      4,      860,    "RO",   0,      0,      0ull,   0ull},
64923         {"BCNT"                        ,        4,      11,     860,    "RO",   0,      0,      0ull,   0ull},
64924         {"DPID"                        ,        15,     2,      860,    "RO",   0,      0,      0ull,   0ull},
64925         {"PKTSTS"                      ,        17,     4,      860,    "RO",   0,      0,      0ull,   0ull},
64926         {"FN"                          ,        21,     4,      860,    "RO",   0,      0,      0ull,   0ull},
64927         {"RESERVED_25_31"              ,        25,     7,      860,    "RAZ",  1,      1,      0,      0},
64928         {"CHNUM"                       ,        0,      4,      861,    "RO",   0,      0,      0ull,   0ull},
64929         {"BCNT"                        ,        4,      11,     861,    "RO",   0,      0,      0ull,   0ull},
64930         {"DPID"                        ,        15,     2,      861,    "RO",   0,      0,      0ull,   0ull},
64931         {"PKTSTS"                      ,        17,     4,      861,    "RO",   0,      0,      0ull,   0ull},
64932         {"RESERVED_21_31"              ,        21,     11,     861,    "RAZ",  1,      1,      0,      0},
64933         {"EPNUM"                       ,        0,      4,      862,    "RO",   0,      0,      0ull,   0ull},
64934         {"BCNT"                        ,        4,      11,     862,    "RO",   0,      0,      0ull,   0ull},
64935         {"DPID"                        ,        15,     2,      862,    "RO",   0,      0,      0ull,   0ull},
64936         {"PKTSTS"                      ,        17,     4,      862,    "RO",   0,      0,      0ull,   0ull},
64937         {"FN"                          ,        21,     4,      862,    "RO",   0,      0,      0ull,   0ull},
64938         {"RESERVED_25_31"              ,        25,     7,      862,    "RAZ",  1,      1,      0,      0},
64939         {"CHNUM"                       ,        0,      4,      863,    "RO",   0,      0,      0ull,   0ull},
64940         {"BCNT"                        ,        4,      11,     863,    "RO",   0,      0,      0ull,   0ull},
64941         {"DPID"                        ,        15,     2,      863,    "RO",   0,      0,      0ull,   0ull},
64942         {"PKTSTS"                      ,        17,     4,      863,    "RO",   0,      0,      0ull,   0ull},
64943         {"RESERVED_21_31"              ,        21,     11,     863,    "RAZ",  1,      1,      0,      0},
64944         {"SYNOPSYSID"                  ,        0,      32,     864,    "RO",   1,      1,      0,      0},
64945         {"TOUTCAL"                     ,        0,      3,      865,    "R/W",  0,      0,      0ull,   0ull},
64946         {"PHYIF"                       ,        3,      1,      865,    "RO",   0,      0,      1ull,   1ull},
64947         {"ULPI_UTMI_SEL"               ,        4,      1,      865,    "RO",   0,      0,      0ull,   0ull},
64948         {"FSINTF"                      ,        5,      1,      865,    "WO",   0,      0,      0ull,   0ull},
64949         {"PHYSEL"                      ,        6,      1,      865,    "WO",   0,      0,      0ull,   0ull},
64950         {"DDRSEL"                      ,        7,      1,      865,    "R/W",  0,      0,      0ull,   0ull},
64951         {"SRPCAP"                      ,        8,      1,      865,    "RO",   0,      0,      0ull,   0ull},
64952         {"HNPCAP"                      ,        9,      1,      865,    "RO",   0,      0,      0ull,   0ull},
64953         {"USBTRDTIM"                   ,        10,     4,      865,    "R/W",  0,      0,      5ull,   5ull},
64954         {"RESERVED_14_14"              ,        14,     1,      865,    "RAZ",  1,      1,      0,      0},
64955         {"PHYLPWRCLKSEL"               ,        15,     1,      865,    "R/W",  0,      0,      0ull,   0ull},
64956         {"OTGI2CSEL"                   ,        16,     1,      865,    "RO",   0,      0,      0ull,   0ull},
64957         {"RESERVED_17_31"              ,        17,     15,     865,    "RAZ",  1,      1,      0,      0},
64958         {"HAINT"                       ,        0,      16,     866,    "RO",   0,      0,      0ull,   0ull},
64959         {"RESERVED_16_31"              ,        16,     16,     866,    "RAZ",  1,      1,      0,      0},
64960         {"HAINTMSK"                    ,        0,      16,     867,    "R/W",  0,      0,      0ull,   0ull},
64961         {"RESERVED_16_31"              ,        16,     16,     867,    "RAZ",  1,      1,      0,      0},
64962         {"MPS"                         ,        0,      11,     868,    "R/W",  0,      0,      0ull,   0ull},
64963         {"EPNUM"                       ,        11,     4,      868,    "R/W",  0,      0,      0ull,   0ull},
64964         {"EPDIR"                       ,        15,     1,      868,    "R/W",  0,      0,      0ull,   0ull},
64965         {"RESERVED_16_16"              ,        16,     1,      868,    "RAZ",  1,      1,      0,      0},
64966         {"LSPDDEV"                     ,        17,     1,      868,    "R/W",  0,      0,      0ull,   0ull},
64967         {"EPTYPE"                      ,        18,     2,      868,    "R/W",  0,      0,      0ull,   0ull},
64968         {"EC"                          ,        20,     2,      868,    "R/W",  0,      0,      0ull,   0ull},
64969         {"DEVADDR"                     ,        22,     7,      868,    "R/W",  0,      0,      0ull,   0ull},
64970         {"ODDFRM"                      ,        29,     1,      868,    "R/W",  0,      0,      0ull,   0ull},
64971         {"CHDIS"                       ,        30,     1,      868,    "R/W",  0,      0,      0ull,   0ull},
64972         {"CHENA"                       ,        31,     1,      868,    "R/W",  0,      0,      0ull,   0ull},
64973         {"FSLSPCLKSEL"                 ,        0,      2,      869,    "R/W",  0,      0,      0ull,   0ull},
64974         {"FSLSSUPP"                    ,        2,      1,      869,    "R/W",  0,      0,      0ull,   0ull},
64975         {"RESERVED_3_31"               ,        3,      29,     869,    "RAZ",  1,      1,      0,      0},
64976         {"XFERCOMPL"                   ,        0,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64977         {"CHHLTD"                      ,        1,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64978         {"AHBERR"                      ,        2,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64979         {"STALL"                       ,        3,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64980         {"NAK"                         ,        4,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64981         {"ACK"                         ,        5,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64982         {"NYET"                        ,        6,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64983         {"XACTERR"                     ,        7,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64984         {"BBLERR"                      ,        8,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64985         {"FRMOVRUN"                    ,        9,      1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64986         {"DATATGLERR"                  ,        10,     1,      870,    "R/W1C",        0,      0,      0ull,   0ull},
64987         {"RESERVED_11_31"              ,        11,     21,     870,    "RAZ",  1,      1,      0,      0},
64988         {"XFERCOMPLMSK"                ,        0,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64989         {"CHHLTDMSK"                   ,        1,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64990         {"AHBERRMSK"                   ,        2,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64991         {"STALLMSK"                    ,        3,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64992         {"NAKMSK"                      ,        4,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64993         {"ACKMSK"                      ,        5,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64994         {"NYETMSK"                     ,        6,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64995         {"XACTERRMSK"                  ,        7,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64996         {"BBLERRMSK"                   ,        8,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64997         {"FRMOVRUNMSK"                 ,        9,      1,      871,    "R/W",  0,      0,      0ull,   0ull},
64998         {"DATATGLERRMSK"               ,        10,     1,      871,    "R/W",  0,      0,      0ull,   0ull},
64999         {"RESERVED_11_31"              ,        11,     21,     871,    "RAZ",  1,      1,      0,      0},
65000         {"PRTADDR"                     ,        0,      7,      872,    "R/W",  0,      0,      0ull,   0ull},
65001         {"HUBADDR"                     ,        7,      7,      872,    "R/W",  0,      0,      0ull,   0ull},
65002         {"XACTPOS"                     ,        14,     2,      872,    "R/W",  0,      0,      0ull,   0ull},
65003         {"COMPSPLT"                    ,        16,     1,      872,    "R/W",  0,      0,      0ull,   0ull},
65004         {"RESERVED_17_30"              ,        17,     14,     872,    "RAZ",  1,      1,      0,      0},
65005         {"SPLTENA"                     ,        31,     1,      872,    "R/W",  0,      0,      0ull,   0ull},
65006         {"XFERSIZE"                    ,        0,      19,     873,    "R/W",  0,      0,      0ull,   0ull},
65007         {"PKTCNT"                      ,        19,     10,     873,    "R/W",  0,      0,      0ull,   0ull},
65008         {"PID"                         ,        29,     2,      873,    "R/W",  0,      0,      0ull,   0ull},
65009         {"DOPNG"                       ,        31,     1,      873,    "R/W",  0,      0,      0ull,   0ull},
65010         {"FRINT"                       ,        0,      16,     874,    "R/W",  0,      0,      2959ull,        3750ull},
65011         {"RESERVED_16_31"              ,        16,     16,     874,    "RAZ",  1,      1,      0,      0},
65012         {"FRNUM"                       ,        0,      16,     875,    "RO",   0,      0,      16383ull,       0ull},
65013         {"FRREM"                       ,        16,     16,     875,    "RO",   0,      0,      0ull,   0ull},
65014         {"PRTCONNSTS"                  ,        0,      1,      876,    "RO",   0,      0,      0ull,   0ull},
65015         {"PRTCONNDET"                  ,        1,      1,      876,    "R/W1C",        0,      0,      0ull,   0ull},
65016         {"PRTENA"                      ,        2,      1,      876,    "R/W1C",        0,      0,      0ull,   0ull},
65017         {"PRTENCHNG"                   ,        3,      1,      876,    "R/W1C",        0,      0,      0ull,   0ull},
65018         {"PRTOVRCURRACT"               ,        4,      1,      876,    "RO",   0,      0,      0ull,   0ull},
65019         {"PRTOVRCURRCHNG"              ,        5,      1,      876,    "R/W1C",        0,      0,      0ull,   0ull},
65020         {"PRTRES"                      ,        6,      1,      876,    "R/W",  0,      0,      0ull,   0ull},
65021         {"PRTSUSP"                     ,        7,      1,      876,    "R/W",  0,      0,      0ull,   0ull},
65022         {"PRTRST"                      ,        8,      1,      876,    "R/W",  0,      0,      0ull,   0ull},
65023         {"RESERVED_9_9"                ,        9,      1,      876,    "RAZ",  1,      1,      0,      0},
65024         {"PRTLNSTS"                    ,        10,     2,      876,    "RO",   0,      0,      0ull,   0ull},
65025         {"PRTPWR"                      ,        12,     1,      876,    "R/W",  0,      0,      0ull,   0ull},
65026         {"PRTTSTCTL"                   ,        13,     4,      876,    "R/W",  0,      0,      0ull,   0ull},
65027         {"PRTSPD"                      ,        17,     2,      876,    "RO",   0,      0,      0ull,   0ull},
65028         {"RESERVED_19_31"              ,        19,     13,     876,    "RAZ",  1,      1,      0,      0},
65029         {"PTXFSTADDR"                  ,        0,      16,     877,    "R/W",  0,      0,      3648ull,        912ull},
65030         {"PTXFSIZE"                    ,        16,     16,     877,    "R/W",  0,      0,      256ull, 456ull},
65031         {"PTXFSPCAVAIL"                ,        0,      16,     878,    "RO",   0,      0,      0ull,   0ull},
65032         {"PTXQSPCAVAIL"                ,        16,     8,      878,    "RO",   0,      0,      0ull,   0ull},
65033         {"PTXQTOP"                     ,        24,     8,      878,    "RO",   0,      0,      0ull,   0ull},
65034         {"DATA"                        ,        0,      32,     879,    "R/W",  0,      0,      0ull,   0ull},
65035         {"STOPPCLK"                    ,        0,      1,      880,    "R/W",  0,      0,      0ull,   0ull},
65036         {"GATEHCLK"                    ,        1,      1,      880,    "R/W",  0,      0,      0ull,   0ull},
65037         {"PWRCLMP"                     ,        2,      1,      880,    "R/W",  0,      0,      0ull,   0ull},
65038         {"RSTPDWNMODULE"               ,        3,      1,      880,    "R/W",  0,      0,      0ull,   0ull},
65039         {"PHYSUSPENDED"                ,        4,      1,      880,    "RO",   0,      0,      0ull,   0ull},
65040         {"RESERVED_5_31"               ,        5,      27,     880,    "RAZ",  1,      1,      0,      0},
65041         {"NOF_BIS"                     ,        0,      1,      881,    "RO",   0,      0,      0ull,   0ull},
65042         {"NIF_BIS"                     ,        1,      1,      881,    "RO",   0,      0,      0ull,   0ull},
65043         {"USBC_BIS"                    ,        2,      1,      881,    "RO",   0,      0,      0ull,   0ull},
65044         {"N2UF_BIS"                    ,        3,      1,      881,    "RO",   0,      0,      0ull,   0ull},
65045         {"E2HC_BIS"                    ,        4,      1,      881,    "RO",   0,      0,      0ull,   0ull},
65046         {"U2NF_BIS"                    ,        5,      1,      881,    "RO",   0,      0,      0ull,   0ull},
65047         {"U2NC_BIS"                    ,        6,      1,      881,    "RO",   0,      0,      0ull,   0ull},
65048         {"RESERVED_7_63"               ,        7,      57,     881,    "RAZ",  1,      1,      0,      0},
65049         {"DIVIDE"                      ,        0,      3,      882,    "R/W",  0,      0,      4ull,   0ull},
65050         {"HRST"                        ,        3,      1,      882,    "R/W",  0,      0,      0ull,   1ull},
65051         {"PRST"                        ,        4,      1,      882,    "R/W",  0,      0,      0ull,   1ull},
65052         {"ENABLE"                      ,        5,      1,      882,    "R/W",  0,      0,      1ull,   1ull},
65053         {"POR"                         ,        6,      1,      882,    "R/W",  0,      0,      1ull,   0ull},
65054         {"S_BIST"                      ,        7,      1,      882,    "R/W",  0,      0,      0ull,   1ull},
65055         {"SD_MODE"                     ,        8,      2,      882,    "R/W",  0,      0,      0ull,   0ull},
65056         {"CDIV_BYP"                    ,        10,     1,      882,    "R/W",  0,      0,      0ull,   0ull},
65057         {"P_C_SEL"                     ,        11,     2,      882,    "R/W",  0,      0,      2ull,   0ull},
65058         {"P_COM_ON"                    ,        13,     1,      882,    "R/W",  0,      0,      1ull,   1ull},
65059         {"P_RTYPE"                     ,        14,     2,      882,    "R/W",  0,      0,      0ull,   0ull},
65060         {"RESERVED_16_16"              ,        16,     1,      882,    "RAZ",  1,      1,      0,      0},
65061         {"HCLK_RST"                    ,        17,     1,      882,    "R/W",  0,      0,      1ull,   1ull},
65062         {"DIVIDE2"                     ,        18,     2,      882,    "R/W",  0,      0,      0ull,   1ull},
65063         {"RESERVED_20_63"              ,        20,     44,     882,    "RAZ",  1,      1,      0,      0},
65064         {"L2C_EMOD"                    ,        0,      2,      883,    "R/W",  0,      0,      1ull,   1ull},
65065         {"INV_A2"                      ,        2,      1,      883,    "R/W",  0,      0,      0ull,   0ull},
65066         {"DMA_TEST"                    ,        3,      1,      883,    "R/W",  0,      0,      0ull,   0ull},
65067         {"DMA_STT"                     ,        4,      1,      883,    "R/W",  0,      0,      0ull,   0ull},
65068         {"DMA_0PAG"                    ,        5,      1,      883,    "R/W",  0,      0,      0ull,   0ull},
65069         {"RESERVED_6_63"               ,        6,      58,     883,    "RAZ",  1,      1,      0,      0},
65070         {"ADDR"                        ,        0,      36,     884,    "R/W",  0,      1,      0ull,   0},
65071         {"RESERVED_36_63"              ,        36,     28,     884,    "RAZ",  1,      1,      0,      0},
65072         {"ADDR"                        ,        0,      36,     885,    "R/W",  0,      1,      0ull,   0},
65073         {"RESERVED_36_63"              ,        36,     28,     885,    "RAZ",  1,      1,      0,      0},
65074         {"ADDR"                        ,        0,      36,     886,    "R/W",  0,      1,      0ull,   0},
65075         {"RESERVED_36_63"              ,        36,     28,     886,    "RAZ",  1,      1,      0,      0},
65076         {"ADDR"                        ,        0,      36,     887,    "R/W",  0,      1,      0ull,   0},
65077         {"RESERVED_36_63"              ,        36,     28,     887,    "RAZ",  1,      1,      0,      0},
65078         {"ADDR"                        ,        0,      36,     888,    "R/W",  0,      1,      0ull,   0},
65079         {"RESERVED_36_63"              ,        36,     28,     888,    "RAZ",  1,      1,      0,      0},
65080         {"ADDR"                        ,        0,      36,     889,    "R/W",  0,      1,      0ull,   0},
65081         {"RESERVED_36_63"              ,        36,     28,     889,    "RAZ",  1,      1,      0,      0},
65082         {"ADDR"                        ,        0,      36,     890,    "R/W",  0,      1,      0ull,   0},
65083         {"RESERVED_36_63"              ,        36,     28,     890,    "RAZ",  1,      1,      0,      0},
65084         {"ADDR"                        ,        0,      36,     891,    "R/W",  0,      1,      0ull,   0},
65085         {"RESERVED_36_63"              ,        36,     28,     891,    "RAZ",  1,      1,      0,      0},
65086         {"ADDR"                        ,        0,      36,     892,    "R/W",  0,      1,      0ull,   0},
65087         {"RESERVED_36_63"              ,        36,     28,     892,    "RAZ",  1,      1,      0,      0},
65088         {"ADDR"                        ,        0,      36,     893,    "R/W",  0,      1,      0ull,   0},
65089         {"RESERVED_36_63"              ,        36,     28,     893,    "RAZ",  1,      1,      0,      0},
65090         {"ADDR"                        ,        0,      36,     894,    "R/W",  0,      1,      0ull,   0},
65091         {"RESERVED_36_63"              ,        36,     28,     894,    "RAZ",  1,      1,      0,      0},
65092         {"ADDR"                        ,        0,      36,     895,    "R/W",  0,      1,      0ull,   0},
65093         {"RESERVED_36_63"              ,        36,     28,     895,    "RAZ",  1,      1,      0,      0},
65094         {"ADDR"                        ,        0,      36,     896,    "R/W",  0,      1,      0ull,   0},
65095         {"RESERVED_36_63"              ,        36,     28,     896,    "RAZ",  1,      1,      0,      0},
65096         {"ADDR"                        ,        0,      36,     897,    "R/W",  0,      1,      0ull,   0},
65097         {"RESERVED_36_63"              ,        36,     28,     897,    "RAZ",  1,      1,      0,      0},
65098         {"ADDR"                        ,        0,      36,     898,    "R/W",  0,      1,      0ull,   0},
65099         {"RESERVED_36_63"              ,        36,     28,     898,    "RAZ",  1,      1,      0,      0},
65100         {"ADDR"                        ,        0,      36,     899,    "R/W",  0,      1,      0ull,   0},
65101         {"RESERVED_36_63"              ,        36,     28,     899,    "RAZ",  1,      1,      0,      0},
65102         {"BURST"                       ,        0,      4,      900,    "R/W",  0,      0,      0ull,   0ull},
65103         {"CHANNEL"                     ,        4,      5,      900,    "R/W",  0,      0,      0ull,   0ull},
65104         {"COUNT"                       ,        9,      11,     900,    "R/W",  0,      0,      0ull,   0ull},
65105         {"F_ADDR"                      ,        20,     18,     900,    "R/W",  0,      0,      0ull,   0ull},
65106         {"REQ"                         ,        38,     1,      900,    "R/W1C",        0,      0,      0ull,   0ull},
65107         {"DONE"                        ,        39,     1,      900,    "R/W1C",        0,      0,      0ull,   0ull},
65108         {"RESERVED_40_63"              ,        40,     24,     900,    "RAZ",  1,      1,      0,      0},
65109         {"PR_PO_E"                     ,        0,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65110         {"PR_PU_F"                     ,        1,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65111         {"NR_PO_E"                     ,        2,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65112         {"NR_PU_F"                     ,        3,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65113         {"LR_PO_E"                     ,        4,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65114         {"LR_PU_F"                     ,        5,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65115         {"PT_PO_E"                     ,        6,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65116         {"PT_PU_F"                     ,        7,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65117         {"NT_PO_E"                     ,        8,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65118         {"NT_PU_F"                     ,        9,      1,      901,    "R/W",  0,      0,      0ull,   0ull},
65119         {"LT_PO_E"                     ,        10,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65120         {"LT_PU_F"                     ,        11,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65121         {"DCRED_E"                     ,        12,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65122         {"DCRED_F"                     ,        13,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65123         {"L2C_S_E"                     ,        14,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65124         {"L2C_A_F"                     ,        15,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65125         {"L2_FI_E"                     ,        16,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65126         {"L2_FI_F"                     ,        17,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65127         {"RG_FI_E"                     ,        18,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65128         {"RG_FI_F"                     ,        19,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65129         {"RQ_Q2_F"                     ,        20,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65130         {"RQ_Q2_E"                     ,        21,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65131         {"RQ_Q3_F"                     ,        22,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65132         {"RQ_Q3_E"                     ,        23,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65133         {"UOD_PE"                      ,        24,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65134         {"UOD_PF"                      ,        25,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65135         {"RESERVED_26_31"              ,        26,     6,      901,    "RAZ",  0,      0,      0ull,   0ull},
65136         {"LTL_F_PE"                    ,        32,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65137         {"LTL_F_PF"                    ,        33,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65138         {"ND4O_RPE"                    ,        34,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65139         {"ND4O_RPF"                    ,        35,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65140         {"ND4O_DPE"                    ,        36,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65141         {"ND4O_DPF"                    ,        37,     1,      901,    "R/W",  0,      0,      0ull,   0ull},
65142         {"RESERVED_38_63"              ,        38,     26,     901,    "RAZ",  1,      1,      0,      0},
65143         {"PR_PO_E"                     ,        0,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65144         {"PR_PU_F"                     ,        1,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65145         {"NR_PO_E"                     ,        2,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65146         {"NR_PU_F"                     ,        3,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65147         {"LR_PO_E"                     ,        4,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65148         {"LR_PU_F"                     ,        5,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65149         {"PT_PO_E"                     ,        6,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65150         {"PT_PU_F"                     ,        7,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65151         {"NT_PO_E"                     ,        8,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65152         {"NT_PU_F"                     ,        9,      1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65153         {"LT_PO_E"                     ,        10,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65154         {"LT_PU_F"                     ,        11,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65155         {"DCRED_E"                     ,        12,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65156         {"DCRED_F"                     ,        13,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65157         {"L2C_S_E"                     ,        14,     1,      902,    "R/W1C",        1,      0,      0,      0ull},
65158         {"L2C_A_F"                     ,        15,     1,      902,    "R/W1C",        1,      0,      0,      0ull},
65159         {"LT_FI_E"                     ,        16,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65160         {"LT_FI_F"                     ,        17,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65161         {"RG_FI_E"                     ,        18,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65162         {"RG_FI_F"                     ,        19,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65163         {"RQ_Q2_F"                     ,        20,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65164         {"RQ_Q2_E"                     ,        21,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65165         {"RQ_Q3_F"                     ,        22,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65166         {"RQ_Q3_E"                     ,        23,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65167         {"UOD_PE"                      ,        24,     1,      902,    "R/W1C",        1,      0,      0,      0ull},
65168         {"UOD_PF"                      ,        25,     1,      902,    "R/W1C",        1,      0,      0,      0ull},
65169         {"RESERVED_26_31"              ,        26,     6,      902,    "RAZ",  1,      0,      0,      0ull},
65170         {"LTL_F_PE"                    ,        32,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65171         {"LTL_F_PF"                    ,        33,     1,      902,    "R/W1C",        0,      0,      0ull,   0ull},
65172         {"ND4O_RPE"                    ,        34,     1,      902,    "R/W1C",        1,      0,      0,      0ull},
65173         {"ND4O_RPF"                    ,        35,     1,      902,    "R/W1C",        1,      0,      0,      0ull},
65174         {"ND4O_DPE"                    ,        36,     1,      902,    "R/W1C",        1,      0,      0,      0ull},
65175         {"ND4O_DPF"                    ,        37,     1,      902,    "R/W1C",        1,      0,      0,      0ull},
65176         {"RESERVED_38_63"              ,        38,     26,     902,    "RAZ",  1,      1,      0,      0},
65177         {"ATE_RESET"                   ,        0,      1,      903,    "R/W",  0,      0,      0ull,   0ull},
65178         {"TDATA_IN"                    ,        1,      8,      903,    "R/W",  0,      0,      0ull,   0ull},
65179         {"TADDR_IN"                    ,        9,      4,      903,    "R/W",  0,      0,      0ull,   0ull},
65180         {"TDATA_SEL"                   ,        13,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65181         {"BIST_ENB"                    ,        14,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65182         {"VTEST_ENB"                   ,        15,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65183         {"LOOP_ENB"                    ,        16,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65184         {"TX_BS_EN"                    ,        17,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65185         {"TX_BS_ENH"                   ,        18,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65186         {"RESERVED_19_22"              ,        19,     4,      903,    "RAZ",  0,      0,      0ull,   0ull},
65187         {"HST_MODE"                    ,        23,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65188         {"DM_PULLD"                    ,        24,     1,      903,    "R/W",  0,      0,      1ull,   1ull},
65189         {"DP_PULLD"                    ,        25,     1,      903,    "R/W",  0,      0,      1ull,   1ull},
65190         {"TCLK"                        ,        26,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65191         {"USBP_BIST"                   ,        27,     1,      903,    "R/W",  0,      0,      1ull,   1ull},
65192         {"USBC_END"                    ,        28,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65193         {"DMA_BMODE"                   ,        29,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65194         {"TXPREEMPHASISTUNE"           ,        30,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65195         {"RESERVED_31_31"              ,        31,     1,      903,    "RAZ",  0,      0,      0ull,   0ull},
65196         {"TDATA_OUT"                   ,        32,     4,      903,    "RO",   1,      1,      0,      0},
65197         {"BIST_ERR"                    ,        36,     1,      903,    "RO",   0,      0,      0ull,   0ull},
65198         {"BIST_DONE"                   ,        37,     1,      903,    "RO",   0,      0,      0ull,   0ull},
65199         {"HSBIST"                      ,        38,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65200         {"FSBIST"                      ,        39,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65201         {"LSBIST"                      ,        40,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65202         {"DRVVBUS"                     ,        41,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65203         {"PORTRESET"                   ,        42,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65204         {"OTGDISABLE"                  ,        43,     1,      903,    "R/W",  0,      0,      1ull,   1ull},
65205         {"OTGTUNE"                     ,        44,     3,      903,    "R/W",  0,      0,      2ull,   2ull},
65206         {"COMPDISTUNE"                 ,        47,     3,      903,    "R/W",  0,      0,      2ull,   2ull},
65207         {"SQRXTUNE"                    ,        50,     3,      903,    "R/W",  0,      0,      3ull,   3ull},
65208         {"TXHSXVTUNE"                  ,        53,     2,      903,    "R/W",  0,      0,      0ull,   0ull},
65209         {"TXFSLSTUNE"                  ,        55,     4,      903,    "R/W",  0,      0,      3ull,   3ull},
65210         {"TXVREFTUNE"                  ,        59,     4,      903,    "R/W",  0,      0,      7ull,   7ull},
65211         {"TXRISETUNE"                  ,        63,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
65212         {NULL,0,0,0,0,0,0,0,0}
65213 };
65214 static const CVMX_CSR_DB_TYPE cvmx_csr_db_cn52xx[] = {
65215          /* name                       ,        ---------------type,    bits,   off,    #field, fld of */
65216         {"cvmx_agl_gmx_bad_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     0,      14,     0},
65217         {"cvmx_agl_gmx_bist"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1,      2,      14},
65218         {"cvmx_agl_gmx_drv_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2,      12,     16},
65219         {"cvmx_agl_gmx_inf_mode"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     3,      3,      28},
65220         {"cvmx_agl_gmx_prt#_cfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     4,      7,      31},
65221         {"cvmx_agl_gmx_rx#_adr_cam0"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     6,      1,      38},
65222         {"cvmx_agl_gmx_rx#_adr_cam1"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     8,      1,      39},
65223         {"cvmx_agl_gmx_rx#_adr_cam2"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     10,     1,      40},
65224         {"cvmx_agl_gmx_rx#_adr_cam3"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     12,     1,      41},
65225         {"cvmx_agl_gmx_rx#_adr_cam4"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     14,     1,      42},
65226         {"cvmx_agl_gmx_rx#_adr_cam5"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     16,     1,      43},
65227         {"cvmx_agl_gmx_rx#_adr_cam_en" ,        CVMX_CSR_DB_TYPE_RSL,   64,     18,     2,      44},
65228         {"cvmx_agl_gmx_rx#_adr_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     20,     4,      46},
65229         {"cvmx_agl_gmx_rx#_decision"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     22,     2,      50},
65230         {"cvmx_agl_gmx_rx#_frm_chk"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     24,     10,     52},
65231         {"cvmx_agl_gmx_rx#_frm_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     26,     11,     62},
65232         {"cvmx_agl_gmx_rx#_frm_max"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     28,     2,      73},
65233         {"cvmx_agl_gmx_rx#_frm_min"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     30,     2,      75},
65234         {"cvmx_agl_gmx_rx#_ifg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     32,     2,      77},
65235         {"cvmx_agl_gmx_rx#_int_en"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     34,     19,     79},
65236         {"cvmx_agl_gmx_rx#_int_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     36,     19,     98},
65237         {"cvmx_agl_gmx_rx#_jabber"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     38,     2,      117},
65238         {"cvmx_agl_gmx_rx#_pause_drop_time",    CVMX_CSR_DB_TYPE_RSL,   64,     40,     2,      119},
65239         {"cvmx_agl_gmx_rx#_stats_ctl"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     42,     2,      121},
65240         {"cvmx_agl_gmx_rx#_stats_octs" ,        CVMX_CSR_DB_TYPE_RSL,   64,     44,     2,      123},
65241         {"cvmx_agl_gmx_rx#_stats_octs_ctl",     CVMX_CSR_DB_TYPE_RSL,   64,     46,     2,      125},
65242         {"cvmx_agl_gmx_rx#_stats_octs_dmac",    CVMX_CSR_DB_TYPE_RSL,   64,     48,     2,      127},
65243         {"cvmx_agl_gmx_rx#_stats_octs_drp",     CVMX_CSR_DB_TYPE_RSL,   64,     50,     2,      129},
65244         {"cvmx_agl_gmx_rx#_stats_pkts" ,        CVMX_CSR_DB_TYPE_RSL,   64,     52,     2,      131},
65245         {"cvmx_agl_gmx_rx#_stats_pkts_bad",     CVMX_CSR_DB_TYPE_RSL,   64,     54,     2,      133},
65246         {"cvmx_agl_gmx_rx#_stats_pkts_ctl",     CVMX_CSR_DB_TYPE_RSL,   64,     56,     2,      135},
65247         {"cvmx_agl_gmx_rx#_stats_pkts_dmac",    CVMX_CSR_DB_TYPE_RSL,   64,     58,     2,      137},
65248         {"cvmx_agl_gmx_rx#_stats_pkts_drp",     CVMX_CSR_DB_TYPE_RSL,   64,     60,     2,      139},
65249         {"cvmx_agl_gmx_rx#_udd_skp"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     62,     4,      141},
65250         {"cvmx_agl_gmx_rx_bp_drop#"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     64,     2,      145},
65251         {"cvmx_agl_gmx_rx_bp_off#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     66,     2,      147},
65252         {"cvmx_agl_gmx_rx_bp_on#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     68,     2,      149},
65253         {"cvmx_agl_gmx_rx_prt_info"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     70,     4,      151},
65254         {"cvmx_agl_gmx_rx_tx_status"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     71,     4,      155},
65255         {"cvmx_agl_gmx_smac#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     72,     2,      159},
65256         {"cvmx_agl_gmx_stat_bp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     74,     3,      161},
65257         {"cvmx_agl_gmx_tx#_append"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     75,     5,      164},
65258         {"cvmx_agl_gmx_tx#_ctl"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     77,     3,      169},
65259         {"cvmx_agl_gmx_tx#_min_pkt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     79,     2,      172},
65260         {"cvmx_agl_gmx_tx#_pause_pkt_interval", CVMX_CSR_DB_TYPE_RSL,   64,     81,     2,      174},
65261         {"cvmx_agl_gmx_tx#_pause_pkt_time",     CVMX_CSR_DB_TYPE_RSL,   64,     83,     2,      176},
65262         {"cvmx_agl_gmx_tx#_pause_togo" ,        CVMX_CSR_DB_TYPE_RSL,   64,     85,     2,      178},
65263         {"cvmx_agl_gmx_tx#_pause_zero" ,        CVMX_CSR_DB_TYPE_RSL,   64,     87,     2,      180},
65264         {"cvmx_agl_gmx_tx#_soft_pause" ,        CVMX_CSR_DB_TYPE_RSL,   64,     89,     2,      182},
65265         {"cvmx_agl_gmx_tx#_stat0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     91,     2,      184},
65266         {"cvmx_agl_gmx_tx#_stat1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     93,     2,      186},
65267         {"cvmx_agl_gmx_tx#_stat2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     95,     2,      188},
65268         {"cvmx_agl_gmx_tx#_stat3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     97,     2,      190},
65269         {"cvmx_agl_gmx_tx#_stat4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     99,     2,      192},
65270         {"cvmx_agl_gmx_tx#_stat5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     101,    2,      194},
65271         {"cvmx_agl_gmx_tx#_stat6"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     103,    2,      196},
65272         {"cvmx_agl_gmx_tx#_stat7"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     105,    2,      198},
65273         {"cvmx_agl_gmx_tx#_stat8"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     107,    2,      200},
65274         {"cvmx_agl_gmx_tx#_stat9"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     109,    2,      202},
65275         {"cvmx_agl_gmx_tx#_stats_ctl"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     111,    2,      204},
65276         {"cvmx_agl_gmx_tx#_thresh"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     113,    2,      206},
65277         {"cvmx_agl_gmx_tx_bp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     115,    2,      208},
65278         {"cvmx_agl_gmx_tx_col_attempt" ,        CVMX_CSR_DB_TYPE_RSL,   64,     116,    2,      210},
65279         {"cvmx_agl_gmx_tx_ifg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     117,    3,      212},
65280         {"cvmx_agl_gmx_tx_int_en"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     118,    10,     215},
65281         {"cvmx_agl_gmx_tx_int_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     119,    10,     225},
65282         {"cvmx_agl_gmx_tx_jam"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     120,    2,      235},
65283         {"cvmx_agl_gmx_tx_lfsr"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     121,    2,      237},
65284         {"cvmx_agl_gmx_tx_ovr_bp"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     122,    6,      239},
65285         {"cvmx_agl_gmx_tx_pause_pkt_dmac",      CVMX_CSR_DB_TYPE_RSL,   64,     123,    2,      245},
65286         {"cvmx_agl_gmx_tx_pause_pkt_type",      CVMX_CSR_DB_TYPE_RSL,   64,     124,    2,      247},
65287         {"cvmx_ciu_bist"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     125,    2,      249},
65288         {"cvmx_ciu_dint"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     126,    2,      251},
65289         {"cvmx_ciu_fuse"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     127,    2,      253},
65290         {"cvmx_ciu_gstop"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     128,    2,      255},
65291         {"cvmx_ciu_int#_en0"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     129,    22,     257},
65292         {"cvmx_ciu_int#_en0_w1c"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     138,    22,     279},
65293         {"cvmx_ciu_int#_en0_w1s"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     147,    22,     301},
65294         {"cvmx_ciu_int#_en1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     156,    7,      323},
65295         {"cvmx_ciu_int#_en1_w1c"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     165,    7,      330},
65296         {"cvmx_ciu_int#_en1_w1s"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     174,    7,      337},
65297         {"cvmx_ciu_int#_en4_0"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     183,    22,     344},
65298         {"cvmx_ciu_int#_en4_0_w1c"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     187,    22,     366},
65299         {"cvmx_ciu_int#_en4_0_w1s"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     191,    22,     388},
65300         {"cvmx_ciu_int#_en4_1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     195,    7,      410},
65301         {"cvmx_ciu_int#_en4_1_w1c"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     199,    7,      417},
65302         {"cvmx_ciu_int#_en4_1_w1s"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     203,    7,      424},
65303         {"cvmx_ciu_int#_sum0"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     207,    22,     431},
65304         {"cvmx_ciu_int#_sum4"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     216,    22,     453},
65305         {"cvmx_ciu_int_sum1"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     220,    7,      475},
65306         {"cvmx_ciu_mbox_clr#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     221,    2,      482},
65307         {"cvmx_ciu_mbox_set#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     225,    2,      484},
65308         {"cvmx_ciu_nmi"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     229,    2,      486},
65309         {"cvmx_ciu_pci_inta"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     230,    2,      488},
65310         {"cvmx_ciu_pp_dbg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     231,    2,      490},
65311         {"cvmx_ciu_pp_poke#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     232,    1,      492},
65312         {"cvmx_ciu_pp_rst"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     236,    3,      493},
65313         {"cvmx_ciu_qlm_dcok"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     237,    2,      496},
65314         {"cvmx_ciu_qlm_jtgc"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     238,    6,      498},
65315         {"cvmx_ciu_qlm_jtgd"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     239,    8,      504},
65316         {"cvmx_ciu_soft_bist"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     240,    2,      512},
65317         {"cvmx_ciu_soft_prst"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     241,    2,      514},
65318         {"cvmx_ciu_soft_prst1"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     242,    2,      516},
65319         {"cvmx_ciu_soft_rst"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     243,    2,      518},
65320         {"cvmx_ciu_tim#"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     244,    3,      520},
65321         {"cvmx_ciu_wdog#"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     248,    7,      523},
65322         {"cvmx_fpa_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     252,    6,      530},
65323         {"cvmx_fpa_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     253,    7,      536},
65324         {"cvmx_fpa_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     254,    29,     543},
65325         {"cvmx_fpa_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     255,    29,     572},
65326         {"cvmx_fpa_que#_available"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     256,    2,      601},
65327         {"cvmx_fpa_que#_page_index"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     264,    2,      603},
65328         {"cvmx_fpa_que_act"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     272,    3,      605},
65329         {"cvmx_fpa_que_exp"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     273,    3,      608},
65330         {"cvmx_fpa_wart_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     274,    2,      611},
65331         {"cvmx_fpa_wart_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     275,    2,      613},
65332         {"cvmx_gmx#_bad_reg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     276,    7,      615},
65333         {"cvmx_gmx#_bist"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     277,    2,      622},
65334         {"cvmx_gmx#_clk_en"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     278,    2,      624},
65335         {"cvmx_gmx#_hg2_control"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     279,    5,      626},
65336         {"cvmx_gmx#_inf_mode"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     280,    7,      631},
65337         {"cvmx_gmx#_nxa_adr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     281,    2,      638},
65338         {"cvmx_gmx#_prt#_cbfc_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     282,    8,      640},
65339         {"cvmx_gmx#_prt#_cfg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     283,    10,     648},
65340         {"cvmx_gmx#_rx#_adr_cam0"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     287,    1,      658},
65341         {"cvmx_gmx#_rx#_adr_cam1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     291,    1,      659},
65342         {"cvmx_gmx#_rx#_adr_cam2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     295,    1,      660},
65343         {"cvmx_gmx#_rx#_adr_cam3"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     299,    1,      661},
65344         {"cvmx_gmx#_rx#_adr_cam4"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     303,    1,      662},
65345         {"cvmx_gmx#_rx#_adr_cam5"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     307,    1,      663},
65346         {"cvmx_gmx#_rx#_adr_cam_en"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     311,    2,      664},
65347         {"cvmx_gmx#_rx#_adr_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     315,    4,      666},
65348         {"cvmx_gmx#_rx#_decision"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     319,    2,      670},
65349         {"cvmx_gmx#_rx#_frm_chk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     323,    9,      672},
65350         {"cvmx_gmx#_rx#_frm_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     327,    11,     681},
65351         {"cvmx_gmx#_rx#_ifg"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     331,    2,      692},
65352         {"cvmx_gmx#_rx#_int_en"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     335,    27,     694},
65353         {"cvmx_gmx#_rx#_int_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     339,    27,     721},
65354         {"cvmx_gmx#_rx#_jabber"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     343,    2,      748},
65355         {"cvmx_gmx#_rx#_pause_drop_time",       CVMX_CSR_DB_TYPE_RSL,   64,     347,    2,      750},
65356         {"cvmx_gmx#_rx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     351,    2,      752},
65357         {"cvmx_gmx#_rx#_stats_octs"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     355,    2,      754},
65358         {"cvmx_gmx#_rx#_stats_octs_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     359,    2,      756},
65359         {"cvmx_gmx#_rx#_stats_octs_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     363,    2,      758},
65360         {"cvmx_gmx#_rx#_stats_octs_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     367,    2,      760},
65361         {"cvmx_gmx#_rx#_stats_pkts"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     371,    2,      762},
65362         {"cvmx_gmx#_rx#_stats_pkts_bad",        CVMX_CSR_DB_TYPE_RSL,   64,     375,    2,      764},
65363         {"cvmx_gmx#_rx#_stats_pkts_ctl",        CVMX_CSR_DB_TYPE_RSL,   64,     379,    2,      766},
65364         {"cvmx_gmx#_rx#_stats_pkts_dmac",       CVMX_CSR_DB_TYPE_RSL,   64,     383,    2,      768},
65365         {"cvmx_gmx#_rx#_stats_pkts_drp",        CVMX_CSR_DB_TYPE_RSL,   64,     387,    2,      770},
65366         {"cvmx_gmx#_rx#_udd_skp"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     391,    4,      772},
65367         {"cvmx_gmx#_rx_bp_drop#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     395,    2,      776},
65368         {"cvmx_gmx#_rx_bp_off#"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     399,    2,      778},
65369         {"cvmx_gmx#_rx_bp_on#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     403,    2,      780},
65370         {"cvmx_gmx#_rx_hg2_status"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     407,    4,      782},
65371         {"cvmx_gmx#_rx_prt_info"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     408,    4,      786},
65372         {"cvmx_gmx#_rx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     409,    2,      790},
65373         {"cvmx_gmx#_rx_xaui_bad_col"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     410,    5,      792},
65374         {"cvmx_gmx#_rx_xaui_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     411,    2,      797},
65375         {"cvmx_gmx#_smac#"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     412,    2,      799},
65376         {"cvmx_gmx#_stat_bp"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     416,    3,      801},
65377         {"cvmx_gmx#_tx#_append"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     417,    5,      804},
65378         {"cvmx_gmx#_tx#_burst"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     421,    2,      809},
65379         {"cvmx_gmx#_tx#_cbfc_xoff"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     425,    2,      811},
65380         {"cvmx_gmx#_tx#_cbfc_xon"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     426,    2,      813},
65381         {"cvmx_gmx#_tx#_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     427,    3,      815},
65382         {"cvmx_gmx#_tx#_min_pkt"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     431,    2,      818},
65383         {"cvmx_gmx#_tx#_pause_pkt_interval",    CVMX_CSR_DB_TYPE_RSL,   64,     435,    2,      820},
65384         {"cvmx_gmx#_tx#_pause_pkt_time",        CVMX_CSR_DB_TYPE_RSL,   64,     439,    2,      822},
65385         {"cvmx_gmx#_tx#_pause_togo"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     443,    3,      824},
65386         {"cvmx_gmx#_tx#_pause_zero"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     447,    2,      827},
65387         {"cvmx_gmx#_tx#_sgmii_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     451,    2,      829},
65388         {"cvmx_gmx#_tx#_slot"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     455,    2,      831},
65389         {"cvmx_gmx#_tx#_soft_pause"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     459,    2,      833},
65390         {"cvmx_gmx#_tx#_stat0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     463,    2,      835},
65391         {"cvmx_gmx#_tx#_stat1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     467,    2,      837},
65392         {"cvmx_gmx#_tx#_stat2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     471,    2,      839},
65393         {"cvmx_gmx#_tx#_stat3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     475,    2,      841},
65394         {"cvmx_gmx#_tx#_stat4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     479,    2,      843},
65395         {"cvmx_gmx#_tx#_stat5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     483,    2,      845},
65396         {"cvmx_gmx#_tx#_stat6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     487,    2,      847},
65397         {"cvmx_gmx#_tx#_stat7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     491,    2,      849},
65398         {"cvmx_gmx#_tx#_stat8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     495,    2,      851},
65399         {"cvmx_gmx#_tx#_stat9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     499,    2,      853},
65400         {"cvmx_gmx#_tx#_stats_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     503,    2,      855},
65401         {"cvmx_gmx#_tx#_thresh"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     507,    2,      857},
65402         {"cvmx_gmx#_tx_bp"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     511,    2,      859},
65403         {"cvmx_gmx#_tx_col_attempt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     512,    2,      861},
65404         {"cvmx_gmx#_tx_corrupt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     513,    2,      863},
65405         {"cvmx_gmx#_tx_hg2_reg1"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     514,    2,      865},
65406         {"cvmx_gmx#_tx_hg2_reg2"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     515,    2,      867},
65407         {"cvmx_gmx#_tx_ifg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     516,    3,      869},
65408         {"cvmx_gmx#_tx_int_en"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     517,    8,      872},
65409         {"cvmx_gmx#_tx_int_reg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     518,    8,      880},
65410         {"cvmx_gmx#_tx_jam"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     519,    2,      888},
65411         {"cvmx_gmx#_tx_lfsr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     520,    2,      890},
65412         {"cvmx_gmx#_tx_ovr_bp"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     521,    6,      892},
65413         {"cvmx_gmx#_tx_pause_pkt_dmac" ,        CVMX_CSR_DB_TYPE_RSL,   64,     522,    2,      898},
65414         {"cvmx_gmx#_tx_pause_pkt_type" ,        CVMX_CSR_DB_TYPE_RSL,   64,     523,    2,      900},
65415         {"cvmx_gmx#_tx_prts"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     524,    2,      902},
65416         {"cvmx_gmx#_tx_xaui_ctl"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     525,    9,      904},
65417         {"cvmx_gmx#_xaui_ext_loopback" ,        CVMX_CSR_DB_TYPE_RSL,   64,     526,    3,      913},
65418         {"cvmx_gpio_bit_cfg#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     527,    9,      916},
65419         {"cvmx_gpio_clk_gen#"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     543,    2,      925},
65420         {"cvmx_gpio_int_clr"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     547,    2,      927},
65421         {"cvmx_gpio_rx_dat"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     548,    2,      929},
65422         {"cvmx_gpio_tx_clr"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     549,    2,      931},
65423         {"cvmx_gpio_tx_set"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     550,    2,      933},
65424         {"cvmx_iob_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     551,    19,     935},
65425         {"cvmx_iob_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     552,    7,      954},
65426         {"cvmx_iob_dwb_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     553,    3,      961},
65427         {"cvmx_iob_fau_timeout"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     554,    3,      964},
65428         {"cvmx_iob_i2c_pri_cnt"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     555,    3,      967},
65429         {"cvmx_iob_inb_control_match"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     556,    5,      970},
65430         {"cvmx_iob_inb_control_match_enb",      CVMX_CSR_DB_TYPE_RSL,   64,     557,    5,      975},
65431         {"cvmx_iob_inb_data_match"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     558,    1,      980},
65432         {"cvmx_iob_inb_data_match_enb" ,        CVMX_CSR_DB_TYPE_RSL,   64,     559,    1,      981},
65433         {"cvmx_iob_int_enb"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     560,    7,      982},
65434         {"cvmx_iob_int_sum"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     561,    7,      989},
65435         {"cvmx_iob_n2c_l2c_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     562,    3,      996},
65436         {"cvmx_iob_n2c_rsp_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     563,    3,      999},
65437         {"cvmx_iob_outb_com_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     564,    3,      1002},
65438         {"cvmx_iob_outb_control_match" ,        CVMX_CSR_DB_TYPE_RSL,   64,     565,    5,      1005},
65439         {"cvmx_iob_outb_control_match_enb",     CVMX_CSR_DB_TYPE_RSL,   64,     566,    5,      1010},
65440         {"cvmx_iob_outb_data_match"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     567,    1,      1015},
65441         {"cvmx_iob_outb_data_match_enb",        CVMX_CSR_DB_TYPE_RSL,   64,     568,    1,      1016},
65442         {"cvmx_iob_outb_fpa_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     569,    3,      1017},
65443         {"cvmx_iob_outb_req_pri_cnt"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     570,    3,      1020},
65444         {"cvmx_iob_p2c_req_pri_cnt"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     571,    3,      1023},
65445         {"cvmx_iob_pkt_err"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     572,    2,      1026},
65446         {"cvmx_iob_to_cmb_credits"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     573,    4,      1028},
65447         {"cvmx_ipd_1st_mbuff_skip"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     574,    2,      1032},
65448         {"cvmx_ipd_1st_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     575,    2,      1034},
65449         {"cvmx_ipd_2nd_next_ptr_back"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     576,    2,      1036},
65450         {"cvmx_ipd_bist_status"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     577,    19,     1038},
65451         {"cvmx_ipd_bp_prt_red_end"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     578,    2,      1057},
65452         {"cvmx_ipd_clk_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     579,    1,      1059},
65453         {"cvmx_ipd_ctl_status"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     580,    15,     1060},
65454         {"cvmx_ipd_int_enb"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     581,    13,     1075},
65455         {"cvmx_ipd_int_sum"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     582,    13,     1088},
65456         {"cvmx_ipd_not_1st_mbuff_skip" ,        CVMX_CSR_DB_TYPE_NCB,   64,     583,    2,      1101},
65457         {"cvmx_ipd_packet_mbuff_size"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     584,    2,      1103},
65458         {"cvmx_ipd_pkt_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     585,    2,      1105},
65459         {"cvmx_ipd_port#_bp_page_cnt"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     586,    3,      1107},
65460         {"cvmx_ipd_port#_bp_page_cnt2" ,        CVMX_CSR_DB_TYPE_NCB,   64,     594,    3,      1110},
65461         {"cvmx_ipd_port_bp_counters2_pair#",    CVMX_CSR_DB_TYPE_NCB,   64,     598,    2,      1113},
65462         {"cvmx_ipd_port_bp_counters_pair#",     CVMX_CSR_DB_TYPE_NCB,   64,     602,    2,      1115},
65463         {"cvmx_ipd_port_qos_#_cnt"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     610,    2,      1117},
65464         {"cvmx_ipd_port_qos_int#"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     706,    1,      1119},
65465         {"cvmx_ipd_port_qos_int_enb#"  ,        CVMX_CSR_DB_TYPE_NCB,   64,     708,    1,      1120},
65466         {"cvmx_ipd_prc_hold_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     710,    6,      1121},
65467         {"cvmx_ipd_prc_port_ptr_fifo_ctl",      CVMX_CSR_DB_TYPE_NCB,   64,     711,    5,      1127},
65468         {"cvmx_ipd_ptr_count"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     712,    6,      1132},
65469         {"cvmx_ipd_pwp_ptr_fifo_ctl"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     713,    7,      1138},
65470         {"cvmx_ipd_qos#_red_marks"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     714,    2,      1145},
65471         {"cvmx_ipd_que0_free_page_cnt" ,        CVMX_CSR_DB_TYPE_NCB,   64,     722,    2,      1147},
65472         {"cvmx_ipd_red_port_enable"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     723,    3,      1149},
65473         {"cvmx_ipd_red_port_enable2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     724,    2,      1152},
65474         {"cvmx_ipd_red_que#_param"     ,        CVMX_CSR_DB_TYPE_NCB,   64,     725,    5,      1154},
65475         {"cvmx_ipd_sub_port_bp_page_cnt",       CVMX_CSR_DB_TYPE_NCB,   64,     733,    3,      1159},
65476         {"cvmx_ipd_sub_port_fcs"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     734,    4,      1162},
65477         {"cvmx_ipd_sub_port_qos_cnt"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     735,    3,      1166},
65478         {"cvmx_ipd_wqe_fpa_queue"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     736,    2,      1169},
65479         {"cvmx_ipd_wqe_ptr_valid"      ,        CVMX_CSR_DB_TYPE_NCB,   64,     737,    2,      1171},
65480         {"cvmx_l2c_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     738,    8,      1173},
65481         {"cvmx_l2c_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     739,    9,      1181},
65482         {"cvmx_l2c_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     740,    8,      1190},
65483         {"cvmx_l2c_cfg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     741,    12,     1198},
65484         {"cvmx_l2c_dbg"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     742,    9,      1210},
65485         {"cvmx_l2c_dut"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     743,    5,      1219},
65486         {"cvmx_l2c_grpwrr0"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     744,    2,      1224},
65487         {"cvmx_l2c_grpwrr1"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     745,    2,      1226},
65488         {"cvmx_l2c_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     746,    10,     1228},
65489         {"cvmx_l2c_int_stat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     747,    10,     1238},
65490         {"cvmx_l2c_lckbase"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     748,    4,      1248},
65491         {"cvmx_l2c_lckoff"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     749,    2,      1252},
65492         {"cvmx_l2c_lfb0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     750,    16,     1254},
65493         {"cvmx_l2c_lfb1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     751,    19,     1270},
65494         {"cvmx_l2c_lfb2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     752,    3,      1289},
65495         {"cvmx_l2c_lfb3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     753,    4,      1292},
65496         {"cvmx_l2c_oob"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     754,    3,      1296},
65497         {"cvmx_l2c_oob1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     755,    6,      1299},
65498         {"cvmx_l2c_oob2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     756,    6,      1305},
65499         {"cvmx_l2c_oob3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     757,    6,      1311},
65500         {"cvmx_l2c_pfc#"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     758,    2,      1317},
65501         {"cvmx_l2c_pfctl"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     762,    17,     1319},
65502         {"cvmx_l2c_ppgrp"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     763,    5,      1336},
65503         {"cvmx_l2c_spar0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     764,    5,      1341},
65504         {"cvmx_l2c_spar4"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     765,    2,      1346},
65505         {"cvmx_l2d_bst0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     766,    3,      1348},
65506         {"cvmx_l2d_bst1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     767,    2,      1351},
65507         {"cvmx_l2d_bst2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     768,    2,      1353},
65508         {"cvmx_l2d_bst3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     769,    2,      1355},
65509         {"cvmx_l2d_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     770,    7,      1357},
65510         {"cvmx_l2d_fadr"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     771,    5,      1364},
65511         {"cvmx_l2d_fsyn0"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     772,    3,      1369},
65512         {"cvmx_l2d_fsyn1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     773,    3,      1372},
65513         {"cvmx_l2d_fus0"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     774,    2,      1375},
65514         {"cvmx_l2d_fus1"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     775,    2,      1377},
65515         {"cvmx_l2d_fus2"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     776,    2,      1379},
65516         {"cvmx_l2d_fus3"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     777,    6,      1381},
65517         {"cvmx_l2t_err"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     778,    14,     1387},
65518         {"cvmx_lmc#_bist_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     779,    2,      1401},
65519         {"cvmx_lmc#_bist_result"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     780,    8,      1403},
65520         {"cvmx_lmc#_comp_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     781,    7,      1411},
65521         {"cvmx_lmc#_ctl"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     782,    19,     1418},
65522         {"cvmx_lmc#_ctl1"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     783,    8,      1437},
65523         {"cvmx_lmc#_dclk_cnt_hi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     784,    2,      1445},
65524         {"cvmx_lmc#_dclk_cnt_lo"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     785,    2,      1447},
65525         {"cvmx_lmc#_ddr2_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     786,    18,     1449},
65526         {"cvmx_lmc#_delay_cfg"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     787,    6,      1467},
65527         {"cvmx_lmc#_dll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     788,    5,      1473},
65528         {"cvmx_lmc#_dual_memcfg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     789,    5,      1478},
65529         {"cvmx_lmc#_ecc_synd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     790,    5,      1483},
65530         {"cvmx_lmc#_fadr"              ,        CVMX_CSR_DB_TYPE_RSL,   64,     791,    6,      1488},
65531         {"cvmx_lmc#_ifb_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     792,    2,      1494},
65532         {"cvmx_lmc#_ifb_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     793,    2,      1496},
65533         {"cvmx_lmc#_mem_cfg0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     794,    14,     1498},
65534         {"cvmx_lmc#_mem_cfg1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     795,    9,      1512},
65535         {"cvmx_lmc#_nxm"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     796,    2,      1521},
65536         {"cvmx_lmc#_ops_cnt_hi"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     797,    2,      1523},
65537         {"cvmx_lmc#_ops_cnt_lo"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     798,    2,      1525},
65538         {"cvmx_lmc#_pll_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     799,    14,     1527},
65539         {"cvmx_lmc#_pll_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     800,    6,      1541},
65540         {"cvmx_lmc#_read_level_ctl"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     801,    7,      1547},
65541         {"cvmx_lmc#_read_level_dbg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     802,    4,      1554},
65542         {"cvmx_lmc#_read_level_rank#"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     803,    11,     1558},
65543         {"cvmx_lmc#_rodt_comp_ctl"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     807,    6,      1569},
65544         {"cvmx_lmc#_rodt_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     808,    9,      1575},
65545         {"cvmx_lmc#_wodt_ctl0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     809,    5,      1584},
65546         {"cvmx_lmc#_wodt_ctl1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     810,    5,      1589},
65547         {"cvmx_mio_boot_bist_stat"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     811,    6,      1594},
65548         {"cvmx_mio_boot_comp"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     812,    3,      1600},
65549         {"cvmx_mio_boot_dma_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     813,    10,     1603},
65550         {"cvmx_mio_boot_dma_int#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     815,    3,      1613},
65551         {"cvmx_mio_boot_dma_int_en#"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     817,    3,      1616},
65552         {"cvmx_mio_boot_dma_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     819,    15,     1619},
65553         {"cvmx_mio_boot_err"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     821,    3,      1634},
65554         {"cvmx_mio_boot_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     822,    3,      1637},
65555         {"cvmx_mio_boot_loc_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     823,    3,      1640},
65556         {"cvmx_mio_boot_loc_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     824,    5,      1643},
65557         {"cvmx_mio_boot_loc_dat"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     826,    1,      1648},
65558         {"cvmx_mio_boot_pin_defs"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     827,    9,      1649},
65559         {"cvmx_mio_boot_reg_cfg#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     828,    13,     1658},
65560         {"cvmx_mio_boot_reg_tim#"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     836,    13,     1671},
65561         {"cvmx_mio_boot_thr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     844,    6,      1684},
65562         {"cvmx_mio_fus_bnk_dat#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     845,    1,      1690},
65563         {"cvmx_mio_fus_dat0"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     849,    2,      1691},
65564         {"cvmx_mio_fus_dat1"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     850,    2,      1693},
65565         {"cvmx_mio_fus_dat2"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     851,    13,     1695},
65566         {"cvmx_mio_fus_dat3"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     852,    8,      1708},
65567         {"cvmx_mio_fus_ema"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     853,    4,      1716},
65568         {"cvmx_mio_fus_pdf"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     854,    1,      1720},
65569         {"cvmx_mio_fus_pll"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     855,    3,      1721},
65570         {"cvmx_mio_fus_prog"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     856,    2,      1724},
65571         {"cvmx_mio_fus_prog_times"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     857,    6,      1726},
65572         {"cvmx_mio_fus_rcmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     858,    7,      1732},
65573         {"cvmx_mio_fus_spr_repair_res" ,        CVMX_CSR_DB_TYPE_RSL,   64,     859,    4,      1739},
65574         {"cvmx_mio_fus_spr_repair_sum" ,        CVMX_CSR_DB_TYPE_RSL,   64,     860,    2,      1743},
65575         {"cvmx_mio_fus_wadr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     861,    2,      1745},
65576         {"cvmx_mio_ndf_dma_cfg"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     862,    10,     1747},
65577         {"cvmx_mio_ndf_dma_int"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     863,    2,      1757},
65578         {"cvmx_mio_ndf_dma_int_en"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     864,    2,      1759},
65579         {"cvmx_mio_tws#_int"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     865,    13,     1761},
65580         {"cvmx_mio_tws#_sw_twsi"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     867,    12,     1774},
65581         {"cvmx_mio_tws#_sw_twsi_ext"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     869,    3,      1786},
65582         {"cvmx_mio_tws#_twsi_sw"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     871,    3,      1789},
65583         {"cvmx_mio_uart#_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     873,    2,      1792},
65584         {"cvmx_mio_uart#_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     875,    2,      1794},
65585         {"cvmx_mio_uart#_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     877,    2,      1796},
65586         {"cvmx_mio_uart#_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     879,    7,      1798},
65587         {"cvmx_mio_uart#_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     881,    2,      1805},
65588         {"cvmx_mio_uart#_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     883,    7,      1807},
65589         {"cvmx_mio_uart#_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     885,    4,      1814},
65590         {"cvmx_mio_uart#_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     887,    8,      1818},
65591         {"cvmx_mio_uart#_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     889,    9,      1826},
65592         {"cvmx_mio_uart#_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     891,    7,      1835},
65593         {"cvmx_mio_uart#_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     893,    9,      1842},
65594         {"cvmx_mio_uart#_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     895,    2,      1851},
65595         {"cvmx_mio_uart#_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     897,    2,      1853},
65596         {"cvmx_mio_uart#_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     899,    4,      1855},
65597         {"cvmx_mio_uart#_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     901,    2,      1859},
65598         {"cvmx_mio_uart#_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     903,    2,      1861},
65599         {"cvmx_mio_uart#_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     905,    2,      1863},
65600         {"cvmx_mio_uart#_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     907,    4,      1865},
65601         {"cvmx_mio_uart#_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     909,    2,      1869},
65602         {"cvmx_mio_uart#_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     911,    2,      1871},
65603         {"cvmx_mio_uart#_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     913,    2,      1873},
65604         {"cvmx_mio_uart#_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     915,    2,      1875},
65605         {"cvmx_mio_uart#_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     917,    2,      1877},
65606         {"cvmx_mio_uart#_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     919,    2,      1879},
65607         {"cvmx_mio_uart#_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     921,    6,      1881},
65608         {"cvmx_mio_uart2_dlh"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     923,    2,      1887},
65609         {"cvmx_mio_uart2_dll"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     924,    2,      1889},
65610         {"cvmx_mio_uart2_far"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     925,    2,      1891},
65611         {"cvmx_mio_uart2_fcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     926,    7,      1893},
65612         {"cvmx_mio_uart2_htx"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     927,    2,      1900},
65613         {"cvmx_mio_uart2_ier"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     928,    7,      1902},
65614         {"cvmx_mio_uart2_iir"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     929,    4,      1909},
65615         {"cvmx_mio_uart2_lcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     930,    8,      1913},
65616         {"cvmx_mio_uart2_lsr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     931,    9,      1921},
65617         {"cvmx_mio_uart2_mcr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     932,    7,      1930},
65618         {"cvmx_mio_uart2_msr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     933,    9,      1937},
65619         {"cvmx_mio_uart2_rbr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     934,    2,      1946},
65620         {"cvmx_mio_uart2_rfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     935,    2,      1948},
65621         {"cvmx_mio_uart2_rfw"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     936,    4,      1950},
65622         {"cvmx_mio_uart2_sbcr"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     937,    2,      1954},
65623         {"cvmx_mio_uart2_scr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     938,    2,      1956},
65624         {"cvmx_mio_uart2_sfe"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     939,    2,      1958},
65625         {"cvmx_mio_uart2_srr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     940,    4,      1960},
65626         {"cvmx_mio_uart2_srt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     941,    2,      1964},
65627         {"cvmx_mio_uart2_srts"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     942,    2,      1966},
65628         {"cvmx_mio_uart2_stt"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     943,    2,      1968},
65629         {"cvmx_mio_uart2_tfl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     944,    2,      1970},
65630         {"cvmx_mio_uart2_tfr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     945,    2,      1972},
65631         {"cvmx_mio_uart2_thr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     946,    2,      1974},
65632         {"cvmx_mio_uart2_usr"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     947,    6,      1976},
65633         {"cvmx_mix#_bist"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     948,    5,      1982},
65634         {"cvmx_mix#_ctl"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     950,    8,      1987},
65635         {"cvmx_mix#_intena"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     952,    8,      1995},
65636         {"cvmx_mix#_ircnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     954,    2,      2003},
65637         {"cvmx_mix#_irhwm"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     956,    3,      2005},
65638         {"cvmx_mix#_iring1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     958,    5,      2008},
65639         {"cvmx_mix#_iring2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     960,    4,      2013},
65640         {"cvmx_mix#_isr"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     962,    8,      2017},
65641         {"cvmx_mix#_orcnt"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     964,    2,      2025},
65642         {"cvmx_mix#_orhwm"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     966,    2,      2027},
65643         {"cvmx_mix#_oring1"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     968,    5,      2029},
65644         {"cvmx_mix#_oring2"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     970,    4,      2034},
65645         {"cvmx_mix#_remcnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     972,    4,      2038},
65646         {"cvmx_ndf_bt_pg_info"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     974,    4,      2042},
65647         {"cvmx_ndf_cmd"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     975,    1,      2046},
65648         {"cvmx_ndf_drbell"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     976,    2,      2047},
65649         {"cvmx_ndf_ecc_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     977,    3,      2049},
65650         {"cvmx_ndf_int"                ,        CVMX_CSR_DB_TYPE_NCB,   64,     978,    8,      2052},
65651         {"cvmx_ndf_int_en"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     979,    8,      2060},
65652         {"cvmx_ndf_misc"               ,        CVMX_CSR_DB_TYPE_NCB,   64,     980,    11,     2068},
65653         {"cvmx_ndf_st_reg"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     981,    8,      2079},
65654         {"cvmx_npei_bar1_index#"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     982,    5,      2087},
65655         {"cvmx_npei_bist_status"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1014,   58,     2092},
65656         {"cvmx_npei_bist_status2"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1015,   15,     2150},
65657         {"cvmx_npei_ctl_port0"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1016,   17,     2165},
65658         {"cvmx_npei_ctl_port1"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1017,   17,     2182},
65659         {"cvmx_npei_ctl_status"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1018,   10,     2199},
65660         {"cvmx_npei_ctl_status2"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1019,   11,     2209},
65661         {"cvmx_npei_data_out_cnt"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1020,   5,      2220},
65662         {"cvmx_npei_dbg_data"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1021,   8,      2225},
65663         {"cvmx_npei_dbg_select"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1022,   2,      2233},
65664         {"cvmx_npei_dma#_counts"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1023,   3,      2235},
65665         {"cvmx_npei_dma#_dbell"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     1028,   2,      2238},
65666         {"cvmx_npei_dma#_ibuff_saddr"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1033,   4,      2240},
65667         {"cvmx_npei_dma#_naddr"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1038,   2,      2244},
65668         {"cvmx_npei_dma0_int_level"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1043,   2,      2246},
65669         {"cvmx_npei_dma1_int_level"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1044,   2,      2248},
65670         {"cvmx_npei_dma_cnts"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1045,   2,      2250},
65671         {"cvmx_npei_dma_control"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1046,   17,     2252},
65672         {"cvmx_npei_dma_pcie_req_num"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1047,   15,     2269},
65673         {"cvmx_npei_dma_state1"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1048,   6,      2284},
65674         {"cvmx_npei_dma_state2"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1049,   6,      2290},
65675         {"cvmx_npei_int_a_enb"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1050,   11,     2296},
65676         {"cvmx_npei_int_a_enb2"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1051,   11,     2307},
65677         {"cvmx_npei_int_a_sum"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1052,   11,     2318},
65678         {"cvmx_npei_int_enb"           ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1053,   64,     2329},
65679         {"cvmx_npei_int_enb2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1054,   63,     2393},
65680         {"cvmx_npei_int_info"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1055,   3,      2456},
65681         {"cvmx_npei_int_sum"           ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1056,   64,     2459},
65682         {"cvmx_npei_int_sum2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1057,   61,     2523},
65683         {"cvmx_npei_last_win_rdata0"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1058,   1,      2584},
65684         {"cvmx_npei_last_win_rdata1"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1059,   1,      2585},
65685         {"cvmx_npei_mem_access_ctl"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1060,   3,      2586},
65686         {"cvmx_npei_mem_access_subid#" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1061,   11,     2589},
65687         {"cvmx_npei_msi_enb0"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1077,   1,      2600},
65688         {"cvmx_npei_msi_enb1"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1078,   1,      2601},
65689         {"cvmx_npei_msi_enb2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1079,   1,      2602},
65690         {"cvmx_npei_msi_enb3"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1080,   1,      2603},
65691         {"cvmx_npei_msi_rcv0"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1081,   1,      2604},
65692         {"cvmx_npei_msi_rcv1"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1082,   1,      2605},
65693         {"cvmx_npei_msi_rcv2"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1083,   1,      2606},
65694         {"cvmx_npei_msi_rcv3"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1084,   1,      2607},
65695         {"cvmx_npei_msi_rd_map"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1085,   3,      2608},
65696         {"cvmx_npei_msi_w1c_enb0"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1086,   1,      2611},
65697         {"cvmx_npei_msi_w1c_enb1"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1087,   1,      2612},
65698         {"cvmx_npei_msi_w1c_enb2"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1088,   1,      2613},
65699         {"cvmx_npei_msi_w1c_enb3"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1089,   1,      2614},
65700         {"cvmx_npei_msi_w1s_enb0"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1090,   1,      2615},
65701         {"cvmx_npei_msi_w1s_enb1"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1091,   1,      2616},
65702         {"cvmx_npei_msi_w1s_enb2"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1092,   1,      2617},
65703         {"cvmx_npei_msi_w1s_enb3"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1093,   1,      2618},
65704         {"cvmx_npei_msi_wr_map"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1094,   3,      2619},
65705         {"cvmx_npei_pcie_credit_cnt"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1095,   7,      2622},
65706         {"cvmx_npei_pcie_msi_rcv"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1096,   2,      2629},
65707         {"cvmx_npei_pcie_msi_rcv_b1"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1097,   3,      2631},
65708         {"cvmx_npei_pcie_msi_rcv_b2"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1098,   3,      2634},
65709         {"cvmx_npei_pcie_msi_rcv_b3"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1099,   3,      2637},
65710         {"cvmx_npei_pkt#_cnts"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1100,   3,      2640},
65711         {"cvmx_npei_pkt#_in_bp"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1132,   2,      2643},
65712         {"cvmx_npei_pkt#_instr_baddr"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1164,   2,      2645},
65713         {"cvmx_npei_pkt#_instr_baoff_dbell",    CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1196,   2,      2647},
65714         {"cvmx_npei_pkt#_instr_fifo_rsize",     CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1228,   5,      2649},
65715         {"cvmx_npei_pkt#_instr_header" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1260,   13,     2654},
65716         {"cvmx_npei_pkt#_slist_baddr"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1292,   2,      2667},
65717         {"cvmx_npei_pkt#_slist_baoff_dbell",    CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1324,   2,      2669},
65718         {"cvmx_npei_pkt#_slist_fifo_rsize",     CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1356,   2,      2671},
65719         {"cvmx_npei_pkt_cnt_int"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1388,   2,      2673},
65720         {"cvmx_npei_pkt_cnt_int_enb"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1389,   2,      2675},
65721         {"cvmx_npei_pkt_data_out_es"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1390,   1,      2677},
65722         {"cvmx_npei_pkt_data_out_ns"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1391,   2,      2678},
65723         {"cvmx_npei_pkt_data_out_ror"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1392,   2,      2680},
65724         {"cvmx_npei_pkt_dpaddr"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1393,   2,      2682},
65725         {"cvmx_npei_pkt_in_bp"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1394,   2,      2684},
65726         {"cvmx_npei_pkt_in_done#_cnts" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1395,   2,      2686},
65727         {"cvmx_npei_pkt_in_instr_counts",       CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1427,   2,      2688},
65728         {"cvmx_npei_pkt_in_pcie_port"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1428,   1,      2690},
65729         {"cvmx_npei_pkt_input_control" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1429,   10,     2691},
65730         {"cvmx_npei_pkt_instr_enb"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1430,   2,      2701},
65731         {"cvmx_npei_pkt_instr_rd_size" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1431,   1,      2703},
65732         {"cvmx_npei_pkt_instr_size"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1432,   2,      2704},
65733         {"cvmx_npei_pkt_int_levels"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1433,   3,      2706},
65734         {"cvmx_npei_pkt_iptr"          ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1434,   2,      2709},
65735         {"cvmx_npei_pkt_out_bmode"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1435,   2,      2711},
65736         {"cvmx_npei_pkt_out_enb"       ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1436,   2,      2713},
65737         {"cvmx_npei_pkt_output_wmark"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1437,   2,      2715},
65738         {"cvmx_npei_pkt_pcie_port"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1438,   1,      2717},
65739         {"cvmx_npei_pkt_port_in_rst"   ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1439,   2,      2718},
65740         {"cvmx_npei_pkt_slist_es"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1440,   1,      2720},
65741         {"cvmx_npei_pkt_slist_id_size" ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1441,   3,      2721},
65742         {"cvmx_npei_pkt_slist_ns"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1442,   2,      2724},
65743         {"cvmx_npei_pkt_slist_ror"     ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1443,   2,      2726},
65744         {"cvmx_npei_pkt_time_int"      ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1444,   2,      2728},
65745         {"cvmx_npei_pkt_time_int_enb"  ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1445,   2,      2730},
65746         {"cvmx_npei_rsl_int_blocks"    ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1446,   29,     2732},
65747         {"cvmx_npei_scratch_1"         ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1447,   1,      2761},
65748         {"cvmx_npei_state1"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1448,   4,      2762},
65749         {"cvmx_npei_state2"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1449,   7,      2766},
65750         {"cvmx_npei_state3"            ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1450,   5,      2773},
65751         {"cvmx_npei_win_rd_addr"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1451,   4,      2778},
65752         {"cvmx_npei_win_rd_data"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1452,   1,      2782},
65753         {"cvmx_npei_win_wr_addr"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1453,   4,      2783},
65754         {"cvmx_npei_win_wr_data"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1454,   1,      2787},
65755         {"cvmx_npei_win_wr_mask"       ,        CVMX_CSR_DB_TYPE_PEXP,  64,     1455,   2,      2788},
65756         {"cvmx_npei_window_ctl"        ,        CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     1456,   2,      2790},
65757         {"cvmx_pcieep_cfg000"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1457,   2,      2792},
65758         {"cvmx_pcieep_cfg001"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1458,   24,     2794},
65759         {"cvmx_pcieep_cfg002"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1459,   4,      2818},
65760         {"cvmx_pcieep_cfg003"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1460,   5,      2822},
65761         {"cvmx_pcieep_cfg004"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1461,   5,      2827},
65762         {"cvmx_pcieep_cfg004_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1462,   2,      2832},
65763         {"cvmx_pcieep_cfg005"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1463,   1,      2834},
65764         {"cvmx_pcieep_cfg005_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1464,   1,      2835},
65765         {"cvmx_pcieep_cfg006"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1465,   5,      2836},
65766         {"cvmx_pcieep_cfg006_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1466,   2,      2841},
65767         {"cvmx_pcieep_cfg007"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1467,   1,      2843},
65768         {"cvmx_pcieep_cfg007_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1468,   1,      2844},
65769         {"cvmx_pcieep_cfg008"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1469,   4,      2845},
65770         {"cvmx_pcieep_cfg008_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1470,   2,      2849},
65771         {"cvmx_pcieep_cfg009"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1471,   2,      2851},
65772         {"cvmx_pcieep_cfg009_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1472,   1,      2853},
65773         {"cvmx_pcieep_cfg010"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1473,   1,      2854},
65774         {"cvmx_pcieep_cfg011"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1474,   2,      2855},
65775         {"cvmx_pcieep_cfg012"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1475,   3,      2857},
65776         {"cvmx_pcieep_cfg012_mask"     ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1476,   2,      2860},
65777         {"cvmx_pcieep_cfg013"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1477,   2,      2862},
65778         {"cvmx_pcieep_cfg015"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1478,   4,      2864},
65779         {"cvmx_pcieep_cfg016"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1479,   10,     2868},
65780         {"cvmx_pcieep_cfg017"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1480,   12,     2878},
65781         {"cvmx_pcieep_cfg020"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1481,   7,      2890},
65782         {"cvmx_pcieep_cfg021"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1482,   2,      2897},
65783         {"cvmx_pcieep_cfg022"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1483,   1,      2899},
65784         {"cvmx_pcieep_cfg023"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1484,   2,      2900},
65785         {"cvmx_pcieep_cfg028"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1485,   7,      2902},
65786         {"cvmx_pcieep_cfg029"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1486,   11,     2909},
65787         {"cvmx_pcieep_cfg030"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1487,   19,     2920},
65788         {"cvmx_pcieep_cfg031"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1488,   11,     2939},
65789         {"cvmx_pcieep_cfg032"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1489,   17,     2950},
65790         {"cvmx_pcieep_cfg033"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1490,   12,     2967},
65791         {"cvmx_pcieep_cfg034"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1491,   22,     2979},
65792         {"cvmx_pcieep_cfg037"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1492,   3,      3001},
65793         {"cvmx_pcieep_cfg038"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1493,   3,      3004},
65794         {"cvmx_pcieep_cfg039"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1494,   1,      3007},
65795         {"cvmx_pcieep_cfg040"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1495,   1,      3008},
65796         {"cvmx_pcieep_cfg041"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1496,   1,      3009},
65797         {"cvmx_pcieep_cfg042"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1497,   1,      3010},
65798         {"cvmx_pcieep_cfg064"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1498,   3,      3011},
65799         {"cvmx_pcieep_cfg065"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1499,   14,     3014},
65800         {"cvmx_pcieep_cfg066"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1500,   14,     3028},
65801         {"cvmx_pcieep_cfg067"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1501,   14,     3042},
65802         {"cvmx_pcieep_cfg068"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1502,   9,      3056},
65803         {"cvmx_pcieep_cfg069"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1503,   9,      3065},
65804         {"cvmx_pcieep_cfg070"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1504,   6,      3074},
65805         {"cvmx_pcieep_cfg071"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1505,   1,      3080},
65806         {"cvmx_pcieep_cfg072"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1506,   1,      3081},
65807         {"cvmx_pcieep_cfg073"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1507,   1,      3082},
65808         {"cvmx_pcieep_cfg074"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1508,   1,      3083},
65809         {"cvmx_pcieep_cfg448"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1509,   2,      3084},
65810         {"cvmx_pcieep_cfg449"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1510,   1,      3086},
65811         {"cvmx_pcieep_cfg450"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1511,   6,      3087},
65812         {"cvmx_pcieep_cfg451"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1512,   6,      3093},
65813         {"cvmx_pcieep_cfg452"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1513,   13,     3099},
65814         {"cvmx_pcieep_cfg453"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1514,   5,      3112},
65815         {"cvmx_pcieep_cfg454"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1515,   8,      3117},
65816         {"cvmx_pcieep_cfg455"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1516,   19,     3125},
65817         {"cvmx_pcieep_cfg456"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1517,   3,      3144},
65818         {"cvmx_pcieep_cfg458"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1518,   1,      3147},
65819         {"cvmx_pcieep_cfg459"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1519,   1,      3148},
65820         {"cvmx_pcieep_cfg460"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1520,   3,      3149},
65821         {"cvmx_pcieep_cfg461"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1521,   3,      3152},
65822         {"cvmx_pcieep_cfg462"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1522,   3,      3155},
65823         {"cvmx_pcieep_cfg463"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1523,   4,      3158},
65824         {"cvmx_pcieep_cfg464"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1524,   4,      3162},
65825         {"cvmx_pcieep_cfg465"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1525,   4,      3166},
65826         {"cvmx_pcieep_cfg466"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1526,   7,      3170},
65827         {"cvmx_pcieep_cfg467"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1527,   5,      3177},
65828         {"cvmx_pcieep_cfg468"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1528,   5,      3182},
65829         {"cvmx_pcieep_cfg490"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1529,   4,      3187},
65830         {"cvmx_pcieep_cfg491"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1530,   4,      3191},
65831         {"cvmx_pcieep_cfg492"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1531,   4,      3195},
65832         {"cvmx_pcieep_cfg516"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1532,   1,      3199},
65833         {"cvmx_pcieep_cfg517"          ,        CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     1533,   1,      3200},
65834         {"cvmx_pcierc#_cfg000"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1534,   2,      3201},
65835         {"cvmx_pcierc#_cfg001"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1536,   24,     3203},
65836         {"cvmx_pcierc#_cfg002"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1538,   4,      3227},
65837         {"cvmx_pcierc#_cfg003"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1540,   5,      3231},
65838         {"cvmx_pcierc#_cfg004"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1542,   1,      3236},
65839         {"cvmx_pcierc#_cfg005"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1544,   1,      3237},
65840         {"cvmx_pcierc#_cfg006"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1546,   4,      3238},
65841         {"cvmx_pcierc#_cfg007"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1548,   17,     3242},
65842         {"cvmx_pcierc#_cfg008"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1550,   4,      3259},
65843         {"cvmx_pcierc#_cfg009"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1552,   6,      3263},
65844         {"cvmx_pcierc#_cfg010"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1554,   1,      3269},
65845         {"cvmx_pcierc#_cfg011"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1556,   1,      3270},
65846         {"cvmx_pcierc#_cfg012"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1558,   2,      3271},
65847         {"cvmx_pcierc#_cfg013"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1560,   2,      3273},
65848         {"cvmx_pcierc#_cfg014"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1562,   1,      3275},
65849         {"cvmx_pcierc#_cfg015"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1564,   15,     3276},
65850         {"cvmx_pcierc#_cfg016"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1566,   10,     3291},
65851         {"cvmx_pcierc#_cfg017"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1568,   12,     3301},
65852         {"cvmx_pcierc#_cfg020"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1570,   7,      3313},
65853         {"cvmx_pcierc#_cfg021"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1572,   2,      3320},
65854         {"cvmx_pcierc#_cfg022"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1574,   1,      3322},
65855         {"cvmx_pcierc#_cfg023"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1576,   2,      3323},
65856         {"cvmx_pcierc#_cfg028"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1578,   7,      3325},
65857         {"cvmx_pcierc#_cfg029"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1580,   11,     3332},
65858         {"cvmx_pcierc#_cfg030"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1582,   19,     3343},
65859         {"cvmx_pcierc#_cfg031"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1584,   11,     3362},
65860         {"cvmx_pcierc#_cfg032"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1586,   20,     3373},
65861         {"cvmx_pcierc#_cfg033"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1588,   12,     3393},
65862         {"cvmx_pcierc#_cfg034"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1590,   22,     3405},
65863         {"cvmx_pcierc#_cfg035"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1592,   8,      3427},
65864         {"cvmx_pcierc#_cfg036"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1594,   4,      3435},
65865         {"cvmx_pcierc#_cfg037"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1596,   3,      3439},
65866         {"cvmx_pcierc#_cfg038"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1598,   3,      3442},
65867         {"cvmx_pcierc#_cfg039"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1600,   1,      3445},
65868         {"cvmx_pcierc#_cfg040"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1602,   1,      3446},
65869         {"cvmx_pcierc#_cfg041"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1604,   1,      3447},
65870         {"cvmx_pcierc#_cfg042"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1606,   1,      3448},
65871         {"cvmx_pcierc#_cfg064"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1608,   3,      3449},
65872         {"cvmx_pcierc#_cfg065"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1610,   14,     3452},
65873         {"cvmx_pcierc#_cfg066"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1612,   14,     3466},
65874         {"cvmx_pcierc#_cfg067"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1614,   14,     3480},
65875         {"cvmx_pcierc#_cfg068"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1616,   9,      3494},
65876         {"cvmx_pcierc#_cfg069"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1618,   9,      3503},
65877         {"cvmx_pcierc#_cfg070"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1620,   6,      3512},
65878         {"cvmx_pcierc#_cfg071"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1622,   1,      3518},
65879         {"cvmx_pcierc#_cfg072"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1624,   1,      3519},
65880         {"cvmx_pcierc#_cfg073"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1626,   1,      3520},
65881         {"cvmx_pcierc#_cfg074"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1628,   1,      3521},
65882         {"cvmx_pcierc#_cfg075"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1630,   4,      3522},
65883         {"cvmx_pcierc#_cfg076"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1632,   9,      3526},
65884         {"cvmx_pcierc#_cfg077"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1634,   2,      3535},
65885         {"cvmx_pcierc#_cfg448"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1636,   2,      3537},
65886         {"cvmx_pcierc#_cfg449"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1638,   1,      3539},
65887         {"cvmx_pcierc#_cfg450"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1640,   6,      3540},
65888         {"cvmx_pcierc#_cfg451"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1642,   6,      3546},
65889         {"cvmx_pcierc#_cfg452"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1644,   13,     3552},
65890         {"cvmx_pcierc#_cfg453"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1646,   5,      3565},
65891         {"cvmx_pcierc#_cfg454"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1648,   8,      3570},
65892         {"cvmx_pcierc#_cfg455"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1650,   19,     3578},
65893         {"cvmx_pcierc#_cfg456"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1652,   3,      3597},
65894         {"cvmx_pcierc#_cfg458"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1654,   1,      3600},
65895         {"cvmx_pcierc#_cfg459"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1656,   1,      3601},
65896         {"cvmx_pcierc#_cfg460"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1658,   3,      3602},
65897         {"cvmx_pcierc#_cfg461"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1660,   3,      3605},
65898         {"cvmx_pcierc#_cfg462"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1662,   3,      3608},
65899         {"cvmx_pcierc#_cfg463"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1664,   4,      3611},
65900         {"cvmx_pcierc#_cfg464"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1666,   4,      3615},
65901         {"cvmx_pcierc#_cfg465"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1668,   4,      3619},
65902         {"cvmx_pcierc#_cfg466"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1670,   7,      3623},
65903         {"cvmx_pcierc#_cfg467"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1672,   5,      3630},
65904         {"cvmx_pcierc#_cfg468"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1674,   5,      3635},
65905         {"cvmx_pcierc#_cfg490"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1676,   4,      3640},
65906         {"cvmx_pcierc#_cfg491"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1678,   4,      3644},
65907         {"cvmx_pcierc#_cfg492"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1680,   4,      3648},
65908         {"cvmx_pcierc#_cfg516"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1682,   1,      3652},
65909         {"cvmx_pcierc#_cfg517"         ,        CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     1684,   1,      3653},
65910         {"cvmx_pcs#_an#_adv_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1686,   9,      3654},
65911         {"cvmx_pcs#_an#_ext_st_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1690,   6,      3663},
65912         {"cvmx_pcs#_an#_lp_abil_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1694,   9,      3669},
65913         {"cvmx_pcs#_an#_results_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1698,   6,      3678},
65914         {"cvmx_pcs#_int#_en_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1702,   13,     3684},
65915         {"cvmx_pcs#_int#_reg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1706,   13,     3697},
65916         {"cvmx_pcs#_link#_timer_count_reg",     CVMX_CSR_DB_TYPE_RSL,   64,     1710,   2,      3710},
65917         {"cvmx_pcs#_log_anl#_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1714,   4,      3712},
65918         {"cvmx_pcs#_misc#_ctl_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1718,   8,      3716},
65919         {"cvmx_pcs#_mr#_control_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1722,   13,     3724},
65920         {"cvmx_pcs#_mr#_status_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1726,   17,     3737},
65921         {"cvmx_pcs#_rx#_states_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1730,   7,      3754},
65922         {"cvmx_pcs#_rx#_sync_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1734,   3,      3761},
65923         {"cvmx_pcs#_sgm#_an_adv_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1738,   8,      3764},
65924         {"cvmx_pcs#_sgm#_lp_adv_reg"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1742,   7,      3772},
65925         {"cvmx_pcs#_tx#_states_reg"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1746,   4,      3779},
65926         {"cvmx_pcs#_tx_rx#_polarity_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     1750,   5,      3783},
65927         {"cvmx_pcsx#_10gbx_status_reg" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1754,   8,      3788},
65928         {"cvmx_pcsx#_bist_status_reg"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     1756,   2,      3796},
65929         {"cvmx_pcsx#_bit_lock_status_reg",      CVMX_CSR_DB_TYPE_RSL,   64,     1758,   5,      3798},
65930         {"cvmx_pcsx#_control1_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1760,   10,     3803},
65931         {"cvmx_pcsx#_control2_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1762,   2,      3813},
65932         {"cvmx_pcsx#_int_en_reg"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1764,   7,      3815},
65933         {"cvmx_pcsx#_int_reg"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1766,   7,      3822},
65934         {"cvmx_pcsx#_log_anl_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1768,   6,      3829},
65935         {"cvmx_pcsx#_misc_ctl_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1770,   5,      3835},
65936         {"cvmx_pcsx#_rx_sync_states_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     1772,   5,      3840},
65937         {"cvmx_pcsx#_spd_abil_reg"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1774,   3,      3845},
65938         {"cvmx_pcsx#_status1_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1776,   6,      3848},
65939         {"cvmx_pcsx#_status2_reg"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1778,   9,      3854},
65940         {"cvmx_pcsx#_tx_rx_polarity_reg",       CVMX_CSR_DB_TYPE_RSL,   64,     1780,   5,      3863},
65941         {"cvmx_pcsx#_tx_rx_states_reg" ,        CVMX_CSR_DB_TYPE_RSL,   64,     1782,   10,     3868},
65942         {"cvmx_pesc#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1784,   14,     3878},
65943         {"cvmx_pesc#_bist_status2"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1786,   15,     3892},
65944         {"cvmx_pesc#_cfg_rd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1788,   2,      3907},
65945         {"cvmx_pesc#_cfg_wr"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1790,   2,      3909},
65946         {"cvmx_pesc#_cpl_lut_valid"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     1792,   2,      3911},
65947         {"cvmx_pesc#_ctl_status"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1794,   16,     3913},
65948         {"cvmx_pesc#_ctl_status2"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1796,   3,      3929},
65949         {"cvmx_pesc#_dbg_info"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1798,   32,     3932},
65950         {"cvmx_pesc#_dbg_info_en"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1800,   32,     3964},
65951         {"cvmx_pesc#_diag_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1802,   5,      3996},
65952         {"cvmx_pesc#_p2n_bar0_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1804,   2,      4001},
65953         {"cvmx_pesc#_p2n_bar1_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1806,   2,      4003},
65954         {"cvmx_pesc#_p2n_bar2_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1808,   2,      4005},
65955         {"cvmx_pesc#_p2p_bar#_end"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     1810,   2,      4007},
65956         {"cvmx_pesc#_p2p_bar#_start"   ,        CVMX_CSR_DB_TYPE_RSL,   64,     1818,   2,      4009},
65957         {"cvmx_pesc#_tlp_credits"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     1826,   8,      4011},
65958         {"cvmx_pip_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1828,   2,      4019},
65959         {"cvmx_pip_dec_ipsec#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1829,   4,      4021},
65960         {"cvmx_pip_dsa_src_grp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1833,   16,     4025},
65961         {"cvmx_pip_dsa_vid_grp"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     1834,   16,     4041},
65962         {"cvmx_pip_frm_len_chk#"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     1835,   3,      4057},
65963         {"cvmx_pip_gbl_cfg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1837,   8,      4060},
65964         {"cvmx_pip_gbl_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1838,   22,     4068},
65965         {"cvmx_pip_hg_pri_qos"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1839,   6,      4090},
65966         {"cvmx_pip_int_en"             ,        CVMX_CSR_DB_TYPE_RSL,   64,     1840,   14,     4096},
65967         {"cvmx_pip_int_reg"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1841,   14,     4110},
65968         {"cvmx_pip_ip_offset"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1842,   2,      4124},
65969         {"cvmx_pip_prt_cfg#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1843,   28,     4126},
65970         {"cvmx_pip_prt_tag#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1855,   25,     4154},
65971         {"cvmx_pip_qos_diff#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1867,   2,      4179},
65972         {"cvmx_pip_qos_vlan#"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     1931,   4,      4181},
65973         {"cvmx_pip_qos_watch#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1939,   9,      4185},
65974         {"cvmx_pip_raw_word"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     1947,   2,      4194},
65975         {"cvmx_pip_sft_rst"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     1948,   2,      4196},
65976         {"cvmx_pip_stat0_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1949,   2,      4198},
65977         {"cvmx_pip_stat1_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1961,   2,      4200},
65978         {"cvmx_pip_stat2_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1973,   2,      4202},
65979         {"cvmx_pip_stat3_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1985,   2,      4204},
65980         {"cvmx_pip_stat4_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     1997,   2,      4206},
65981         {"cvmx_pip_stat5_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2009,   2,      4208},
65982         {"cvmx_pip_stat6_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2021,   2,      4210},
65983         {"cvmx_pip_stat7_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2033,   2,      4212},
65984         {"cvmx_pip_stat8_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2045,   2,      4214},
65985         {"cvmx_pip_stat9_prt#"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2057,   2,      4216},
65986         {"cvmx_pip_stat_ctl"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2069,   2,      4218},
65987         {"cvmx_pip_stat_inb_errs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2070,   2,      4220},
65988         {"cvmx_pip_stat_inb_octs#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2082,   2,      4222},
65989         {"cvmx_pip_stat_inb_pkts#"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2094,   2,      4224},
65990         {"cvmx_pip_tag_inc#"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2106,   2,      4226},
65991         {"cvmx_pip_tag_mask"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2170,   2,      4228},
65992         {"cvmx_pip_tag_secret"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2171,   3,      4230},
65993         {"cvmx_pip_todo_entry"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2172,   3,      4233},
65994         {"cvmx_pko_mem_count0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2173,   2,      4236},
65995         {"cvmx_pko_mem_count1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2174,   2,      4238},
65996         {"cvmx_pko_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2175,   4,      4240},
65997         {"cvmx_pko_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2176,   5,      4244},
65998         {"cvmx_pko_mem_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2177,   4,      4249},
65999         {"cvmx_pko_mem_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2178,   8,      4253},
66000         {"cvmx_pko_mem_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2179,   4,      4261},
66001         {"cvmx_pko_mem_debug13"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2180,   5,      4265},
66002         {"cvmx_pko_mem_debug14"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2181,   1,      4270},
66003         {"cvmx_pko_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2182,   5,      4271},
66004         {"cvmx_pko_mem_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2183,   1,      4276},
66005         {"cvmx_pko_mem_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2184,   13,     4277},
66006         {"cvmx_pko_mem_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2185,   4,      4290},
66007         {"cvmx_pko_mem_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2186,   13,     4294},
66008         {"cvmx_pko_mem_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2187,   6,      4307},
66009         {"cvmx_pko_mem_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2188,   9,      4313},
66010         {"cvmx_pko_mem_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2189,   4,      4322},
66011         {"cvmx_pko_mem_port_ptrs"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2190,   7,      4326},
66012         {"cvmx_pko_mem_port_qos"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2191,   5,      4333},
66013         {"cvmx_pko_mem_port_rate0"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2192,   5,      4338},
66014         {"cvmx_pko_mem_port_rate1"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2193,   4,      4343},
66015         {"cvmx_pko_mem_queue_ptrs"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2194,   9,      4347},
66016         {"cvmx_pko_mem_queue_qos"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2195,   5,      4356},
66017         {"cvmx_pko_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2196,   16,     4361},
66018         {"cvmx_pko_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2197,   4,      4377},
66019         {"cvmx_pko_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2198,   1,      4381},
66020         {"cvmx_pko_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2199,   1,      4382},
66021         {"cvmx_pko_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2200,   1,      4383},
66022         {"cvmx_pko_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2201,   1,      4384},
66023         {"cvmx_pko_reg_engine_inflight",        CVMX_CSR_DB_TYPE_RSL,   64,     2202,   11,     4385},
66024         {"cvmx_pko_reg_engine_thresh"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2203,   2,      4396},
66025         {"cvmx_pko_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2204,   4,      4398},
66026         {"cvmx_pko_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2205,   5,      4402},
66027         {"cvmx_pko_reg_gmx_port_mode"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2206,   3,      4407},
66028         {"cvmx_pko_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2207,   4,      4410},
66029         {"cvmx_pko_reg_queue_mode"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2208,   2,      4414},
66030         {"cvmx_pko_reg_queue_ptrs1"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2209,   3,      4416},
66031         {"cvmx_pko_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2210,   3,      4419},
66032         {"cvmx_pow_bist_stat"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2211,   12,     4422},
66033         {"cvmx_pow_ds_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2212,   2,      4434},
66034         {"cvmx_pow_ecc_err"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2213,   13,     4436},
66035         {"cvmx_pow_int_ctl"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2214,   3,      4449},
66036         {"cvmx_pow_iq_cnt#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2215,   2,      4452},
66037         {"cvmx_pow_iq_com_cnt"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2223,   2,      4454},
66038         {"cvmx_pow_iq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2224,   2,      4456},
66039         {"cvmx_pow_iq_int_en"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2225,   2,      4458},
66040         {"cvmx_pow_iq_thr#"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2226,   2,      4460},
66041         {"cvmx_pow_nos_cnt"            ,        CVMX_CSR_DB_TYPE_NCB,   64,     2234,   2,      4462},
66042         {"cvmx_pow_nw_tim"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2235,   2,      4464},
66043         {"cvmx_pow_pf_rst_msk"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2236,   2,      4466},
66044         {"cvmx_pow_pp_grp_msk#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2237,   10,     4468},
66045         {"cvmx_pow_qos_rnd#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2241,   5,      4478},
66046         {"cvmx_pow_qos_thr#"           ,        CVMX_CSR_DB_TYPE_NCB,   64,     2249,   10,     4483},
66047         {"cvmx_pow_ts_pc"              ,        CVMX_CSR_DB_TYPE_NCB,   64,     2257,   2,      4493},
66048         {"cvmx_pow_wa_com_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2258,   2,      4495},
66049         {"cvmx_pow_wa_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2259,   2,      4497},
66050         {"cvmx_pow_wq_int"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2267,   3,      4499},
66051         {"cvmx_pow_wq_int_cnt#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2268,   6,      4502},
66052         {"cvmx_pow_wq_int_pc"          ,        CVMX_CSR_DB_TYPE_NCB,   64,     2284,   5,      4508},
66053         {"cvmx_pow_wq_int_thr#"        ,        CVMX_CSR_DB_TYPE_NCB,   64,     2285,   7,      4513},
66054         {"cvmx_pow_ws_pc#"             ,        CVMX_CSR_DB_TYPE_NCB,   64,     2301,   2,      4520},
66055         {"cvmx_rad_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2317,   1,      4522},
66056         {"cvmx_rad_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2318,   1,      4523},
66057         {"cvmx_rad_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2319,   1,      4524},
66058         {"cvmx_rad_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2320,   5,      4525},
66059         {"cvmx_rad_reg_cmd_buf"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2321,   5,      4530},
66060         {"cvmx_rad_reg_ctl"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2322,   4,      4535},
66061         {"cvmx_rad_reg_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2323,   10,     4539},
66062         {"cvmx_rad_reg_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2324,   1,      4549},
66063         {"cvmx_rad_reg_debug10"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2325,   3,      4550},
66064         {"cvmx_rad_reg_debug11"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2326,   7,      4553},
66065         {"cvmx_rad_reg_debug12"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2327,   2,      4560},
66066         {"cvmx_rad_reg_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2328,   1,      4562},
66067         {"cvmx_rad_reg_debug3"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2329,   1,      4563},
66068         {"cvmx_rad_reg_debug4"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2330,   1,      4564},
66069         {"cvmx_rad_reg_debug5"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2331,   18,     4565},
66070         {"cvmx_rad_reg_debug6"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2332,   3,      4583},
66071         {"cvmx_rad_reg_debug7"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2333,   2,      4586},
66072         {"cvmx_rad_reg_debug8"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2334,   3,      4588},
66073         {"cvmx_rad_reg_debug9"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2335,   7,      4591},
66074         {"cvmx_rad_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2336,   2,      4598},
66075         {"cvmx_rad_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2337,   2,      4600},
66076         {"cvmx_rad_reg_polynomial"     ,        CVMX_CSR_DB_TYPE_RSL,   64,     2338,   2,      4602},
66077         {"cvmx_rad_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2339,   3,      4604},
66078         {"cvmx_rnm_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2340,   3,      4607},
66079         {"cvmx_rnm_ctl_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2341,   7,      4610},
66080         {"cvmx_smi#_clk"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2342,   10,     4617},
66081         {"cvmx_smi#_cmd"               ,        CVMX_CSR_DB_TYPE_RSL,   64,     2344,   6,      4627},
66082         {"cvmx_smi#_en"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2346,   2,      4633},
66083         {"cvmx_smi#_rd_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2348,   4,      4635},
66084         {"cvmx_smi#_wr_dat"            ,        CVMX_CSR_DB_TYPE_RSL,   64,     2350,   4,      4639},
66085         {"cvmx_tim_mem_debug0"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2352,   6,      4643},
66086         {"cvmx_tim_mem_debug1"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2353,   3,      4649},
66087         {"cvmx_tim_mem_debug2"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2354,   5,      4652},
66088         {"cvmx_tim_mem_ring0"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2355,   4,      4657},
66089         {"cvmx_tim_mem_ring1"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2356,   6,      4661},
66090         {"cvmx_tim_reg_bist_result"    ,        CVMX_CSR_DB_TYPE_RSL,   64,     2357,   4,      4667},
66091         {"cvmx_tim_reg_error"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2358,   2,      4671},
66092         {"cvmx_tim_reg_flags"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2359,   4,      4673},
66093         {"cvmx_tim_reg_int_mask"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2360,   2,      4677},
66094         {"cvmx_tim_reg_read_idx"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2361,   3,      4679},
66095         {"cvmx_tra_bist_status"        ,        CVMX_CSR_DB_TYPE_RSL,   64,     2362,   4,      4682},
66096         {"cvmx_tra_ctl"                ,        CVMX_CSR_DB_TYPE_RSL,   64,     2363,   12,     4686},
66097         {"cvmx_tra_cycles_since"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2364,   3,      4698},
66098         {"cvmx_tra_cycles_since1"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2365,   5,      4701},
66099         {"cvmx_tra_filt_adr_adr"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2366,   2,      4706},
66100         {"cvmx_tra_filt_adr_msk"       ,        CVMX_CSR_DB_TYPE_RSL,   64,     2367,   2,      4708},
66101         {"cvmx_tra_filt_cmd"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2368,   18,     4710},
66102         {"cvmx_tra_filt_did"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2369,   12,     4728},
66103         {"cvmx_tra_filt_sid"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2370,   6,      4740},
66104         {"cvmx_tra_int_status"         ,        CVMX_CSR_DB_TYPE_RSL,   64,     2371,   5,      4746},
66105         {"cvmx_tra_read_dat"           ,        CVMX_CSR_DB_TYPE_RSL,   64,     2372,   1,      4751},
66106         {"cvmx_tra_trig0_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2373,   2,      4752},
66107         {"cvmx_tra_trig0_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2374,   2,      4754},
66108         {"cvmx_tra_trig0_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2375,   18,     4756},
66109         {"cvmx_tra_trig0_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2376,   12,     4774},
66110         {"cvmx_tra_trig0_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2377,   6,      4786},
66111         {"cvmx_tra_trig1_adr_adr"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2378,   2,      4792},
66112         {"cvmx_tra_trig1_adr_msk"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2379,   2,      4794},
66113         {"cvmx_tra_trig1_cmd"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2380,   18,     4796},
66114         {"cvmx_tra_trig1_did"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2381,   12,     4814},
66115         {"cvmx_tra_trig1_sid"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2382,   6,      4826},
66116         {"cvmx_usbc#_daint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     2383,   2,      4832},
66117         {"cvmx_usbc#_daintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2385,   2,      4834},
66118         {"cvmx_usbc#_dcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2387,   8,      4836},
66119         {"cvmx_usbc#_dctl"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2389,   11,     4844},
66120         {"cvmx_usbc#_diepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2391,   15,     4855},
66121         {"cvmx_usbc#_diepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2401,   8,      4870},
66122         {"cvmx_usbc#_diepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2411,   8,      4878},
66123         {"cvmx_usbc#_dieptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2413,   4,      4886},
66124         {"cvmx_usbc#_doepctl#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2423,   15,     4890},
66125         {"cvmx_usbc#_doepint#"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2433,   6,      4905},
66126         {"cvmx_usbc#_doepmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2443,   6,      4911},
66127         {"cvmx_usbc#_doeptsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2445,   4,      4917},
66128         {"cvmx_usbc#_dptxfsiz#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2455,   2,      4921},
66129         {"cvmx_usbc#_dsts"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2463,   6,      4923},
66130         {"cvmx_usbc#_dtknqr1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2465,   4,      4929},
66131         {"cvmx_usbc#_dtknqr2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2467,   1,      4933},
66132         {"cvmx_usbc#_dtknqr3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2469,   1,      4934},
66133         {"cvmx_usbc#_dtknqr4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2471,   1,      4935},
66134         {"cvmx_usbc#_gahbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2473,   7,      4936},
66135         {"cvmx_usbc#_ghwcfg1"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2475,   1,      4943},
66136         {"cvmx_usbc#_ghwcfg2"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2477,   14,     4944},
66137         {"cvmx_usbc#_ghwcfg3"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2479,   10,     4958},
66138         {"cvmx_usbc#_ghwcfg4"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2481,   14,     4968},
66139         {"cvmx_usbc#_gintmsk"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2483,   32,     4982},
66140         {"cvmx_usbc#_gintsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2485,   32,     5014},
66141         {"cvmx_usbc#_gnptxfsiz"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2487,   2,      5046},
66142         {"cvmx_usbc#_gnptxsts"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2489,   4,      5048},
66143         {"cvmx_usbc#_gotgctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2491,   13,     5052},
66144         {"cvmx_usbc#_gotgint"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2493,   10,     5065},
66145         {"cvmx_usbc#_grstctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2495,   10,     5075},
66146         {"cvmx_usbc#_grxfsiz"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2497,   2,      5085},
66147         {"cvmx_usbc#_grxstspd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2499,   6,      5087},
66148         {"cvmx_usbc#_grxstsph"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2501,   5,      5093},
66149         {"cvmx_usbc#_grxstsrd"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2503,   6,      5098},
66150         {"cvmx_usbc#_grxstsrh"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2505,   5,      5104},
66151         {"cvmx_usbc#_gsnpsid"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2507,   1,      5109},
66152         {"cvmx_usbc#_gusbcfg"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2509,   13,     5110},
66153         {"cvmx_usbc#_haint"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     2511,   2,      5123},
66154         {"cvmx_usbc#_haintmsk"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2513,   2,      5125},
66155         {"cvmx_usbc#_hcchar#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2515,   11,     5127},
66156         {"cvmx_usbc#_hcfg"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2531,   3,      5138},
66157         {"cvmx_usbc#_hcint#"           ,        CVMX_CSR_DB_TYPE_NCB,   32,     2533,   12,     5141},
66158         {"cvmx_usbc#_hcintmsk#"        ,        CVMX_CSR_DB_TYPE_NCB,   32,     2549,   12,     5153},
66159         {"cvmx_usbc#_hcsplt#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2565,   6,      5165},
66160         {"cvmx_usbc#_hctsiz#"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2581,   4,      5171},
66161         {"cvmx_usbc#_hfir"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2597,   2,      5175},
66162         {"cvmx_usbc#_hfnum"            ,        CVMX_CSR_DB_TYPE_NCB,   32,     2599,   2,      5177},
66163         {"cvmx_usbc#_hprt"             ,        CVMX_CSR_DB_TYPE_NCB,   32,     2601,   15,     5179},
66164         {"cvmx_usbc#_hptxfsiz"         ,        CVMX_CSR_DB_TYPE_NCB,   32,     2603,   2,      5194},
66165         {"cvmx_usbc#_hptxsts"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2605,   3,      5196},
66166         {"cvmx_usbc#_nptxdfifo#"       ,        CVMX_CSR_DB_TYPE_NCB,   32,     2607,   1,      5199},
66167         {"cvmx_usbc#_pcgcctl"          ,        CVMX_CSR_DB_TYPE_NCB,   32,     2623,   6,      5200},
66168         {"cvmx_usbn#_bist_status"      ,        CVMX_CSR_DB_TYPE_RSL,   64,     2625,   8,      5206},
66169         {"cvmx_usbn#_clk_ctl"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2627,   15,     5214},
66170         {"cvmx_usbn#_ctl_status"       ,        CVMX_CSR_DB_TYPE_NCB,   64,     2629,   6,      5229},
66171         {"cvmx_usbn#_dma0_inb_chn0"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2631,   2,      5235},
66172         {"cvmx_usbn#_dma0_inb_chn1"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2633,   2,      5237},
66173         {"cvmx_usbn#_dma0_inb_chn2"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2635,   2,      5239},
66174         {"cvmx_usbn#_dma0_inb_chn3"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2637,   2,      5241},
66175         {"cvmx_usbn#_dma0_inb_chn4"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2639,   2,      5243},
66176         {"cvmx_usbn#_dma0_inb_chn5"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2641,   2,      5245},
66177         {"cvmx_usbn#_dma0_inb_chn6"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2643,   2,      5247},
66178         {"cvmx_usbn#_dma0_inb_chn7"    ,        CVMX_CSR_DB_TYPE_NCB,   64,     2645,   2,      5249},
66179         {"cvmx_usbn#_dma0_outb_chn0"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2647,   2,      5251},
66180         {"cvmx_usbn#_dma0_outb_chn1"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2649,   2,      5253},
66181         {"cvmx_usbn#_dma0_outb_chn2"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2651,   2,      5255},
66182         {"cvmx_usbn#_dma0_outb_chn3"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2653,   2,      5257},
66183         {"cvmx_usbn#_dma0_outb_chn4"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2655,   2,      5259},
66184         {"cvmx_usbn#_dma0_outb_chn5"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2657,   2,      5261},
66185         {"cvmx_usbn#_dma0_outb_chn6"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2659,   2,      5263},
66186         {"cvmx_usbn#_dma0_outb_chn7"   ,        CVMX_CSR_DB_TYPE_NCB,   64,     2661,   2,      5265},
66187         {"cvmx_usbn#_dma_test"         ,        CVMX_CSR_DB_TYPE_NCB,   64,     2663,   7,      5267},
66188         {"cvmx_usbn#_int_enb"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2665,   34,     5274},
66189         {"cvmx_usbn#_int_sum"          ,        CVMX_CSR_DB_TYPE_RSL,   64,     2667,   34,     5308},
66190         {"cvmx_usbn#_usbp_ctl_status"  ,        CVMX_CSR_DB_TYPE_RSL,   64,     2669,   35,     5342},
66191         {NULL,0,0,0,0,0}
66192 };
66193 static const CVMX_CSR_DB_ADDRESS_TYPE cvmx_csr_db_addresses_cn52xx[] = {
66194         /* name                        ,        --------------address,  ---------------type,    bits,   csr offset */
66195         {"AGL_GMX_BAD_REG"             ,           0x11800E0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     0},
66196         {"AGL_GMX_BIST"                ,           0x11800E0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     1},
66197         {"AGL_GMX_DRV_CTL"             ,           0x11800E00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     2},
66198         {"AGL_GMX_INF_MODE"            ,           0x11800E00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     3},
66199         {"AGL_GMX_PRT0_CFG"            ,           0x11800E0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
66200         {"AGL_GMX_PRT1_CFG"            ,           0x11800E0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     4},
66201         {"AGL_GMX_RX0_ADR_CAM0"        ,           0x11800E0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
66202         {"AGL_GMX_RX1_ADR_CAM0"        ,           0x11800E0000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     5},
66203         {"AGL_GMX_RX0_ADR_CAM1"        ,           0x11800E0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
66204         {"AGL_GMX_RX1_ADR_CAM1"        ,           0x11800E0000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     6},
66205         {"AGL_GMX_RX0_ADR_CAM2"        ,           0x11800E0000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
66206         {"AGL_GMX_RX1_ADR_CAM2"        ,           0x11800E0000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     7},
66207         {"AGL_GMX_RX0_ADR_CAM3"        ,           0x11800E0000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
66208         {"AGL_GMX_RX1_ADR_CAM3"        ,           0x11800E0000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     8},
66209         {"AGL_GMX_RX0_ADR_CAM4"        ,           0x11800E00001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
66210         {"AGL_GMX_RX1_ADR_CAM4"        ,           0x11800E00009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     9},
66211         {"AGL_GMX_RX0_ADR_CAM5"        ,           0x11800E00001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
66212         {"AGL_GMX_RX1_ADR_CAM5"        ,           0x11800E00009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     10},
66213         {"AGL_GMX_RX0_ADR_CAM_EN"      ,           0x11800E0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
66214         {"AGL_GMX_RX1_ADR_CAM_EN"      ,           0x11800E0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     11},
66215         {"AGL_GMX_RX0_ADR_CTL"         ,           0x11800E0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
66216         {"AGL_GMX_RX1_ADR_CTL"         ,           0x11800E0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     12},
66217         {"AGL_GMX_RX0_DECISION"        ,           0x11800E0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
66218         {"AGL_GMX_RX1_DECISION"        ,           0x11800E0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     13},
66219         {"AGL_GMX_RX0_FRM_CHK"         ,           0x11800E0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
66220         {"AGL_GMX_RX1_FRM_CHK"         ,           0x11800E0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     14},
66221         {"AGL_GMX_RX0_FRM_CTL"         ,           0x11800E0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
66222         {"AGL_GMX_RX1_FRM_CTL"         ,           0x11800E0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     15},
66223         {"AGL_GMX_RX0_FRM_MAX"         ,           0x11800E0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
66224         {"AGL_GMX_RX1_FRM_MAX"         ,           0x11800E0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     16},
66225         {"AGL_GMX_RX0_FRM_MIN"         ,           0x11800E0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
66226         {"AGL_GMX_RX1_FRM_MIN"         ,           0x11800E0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     17},
66227         {"AGL_GMX_RX0_IFG"             ,           0x11800E0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
66228         {"AGL_GMX_RX1_IFG"             ,           0x11800E0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     18},
66229         {"AGL_GMX_RX0_INT_EN"          ,           0x11800E0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
66230         {"AGL_GMX_RX1_INT_EN"          ,           0x11800E0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     19},
66231         {"AGL_GMX_RX0_INT_REG"         ,           0x11800E0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
66232         {"AGL_GMX_RX1_INT_REG"         ,           0x11800E0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     20},
66233         {"AGL_GMX_RX0_JABBER"          ,           0x11800E0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
66234         {"AGL_GMX_RX1_JABBER"          ,           0x11800E0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     21},
66235         {"AGL_GMX_RX0_PAUSE_DROP_TIME" ,           0x11800E0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
66236         {"AGL_GMX_RX1_PAUSE_DROP_TIME" ,           0x11800E0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     22},
66237         {"AGL_GMX_RX0_STATS_CTL"       ,           0x11800E0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     23},
66238         {"AGL_GMX_RX1_STATS_CTL"       ,           0x11800E0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     23},
66239         {"AGL_GMX_RX0_STATS_OCTS"      ,           0x11800E0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     24},
66240         {"AGL_GMX_RX1_STATS_OCTS"      ,           0x11800E0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     24},
66241         {"AGL_GMX_RX0_STATS_OCTS_CTL"  ,           0x11800E0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     25},
66242         {"AGL_GMX_RX1_STATS_OCTS_CTL"  ,           0x11800E0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     25},
66243         {"AGL_GMX_RX0_STATS_OCTS_DMAC" ,           0x11800E00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     26},
66244         {"AGL_GMX_RX1_STATS_OCTS_DMAC" ,           0x11800E00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     26},
66245         {"AGL_GMX_RX0_STATS_OCTS_DRP"  ,           0x11800E00000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     27},
66246         {"AGL_GMX_RX1_STATS_OCTS_DRP"  ,           0x11800E00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     27},
66247         {"AGL_GMX_RX0_STATS_PKTS"      ,           0x11800E0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     28},
66248         {"AGL_GMX_RX1_STATS_PKTS"      ,           0x11800E0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     28},
66249         {"AGL_GMX_RX0_STATS_PKTS_BAD"  ,           0x11800E00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     29},
66250         {"AGL_GMX_RX1_STATS_PKTS_BAD"  ,           0x11800E00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     29},
66251         {"AGL_GMX_RX0_STATS_PKTS_CTL"  ,           0x11800E0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     30},
66252         {"AGL_GMX_RX1_STATS_PKTS_CTL"  ,           0x11800E0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     30},
66253         {"AGL_GMX_RX0_STATS_PKTS_DMAC" ,           0x11800E00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     31},
66254         {"AGL_GMX_RX1_STATS_PKTS_DMAC" ,           0x11800E00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     31},
66255         {"AGL_GMX_RX0_STATS_PKTS_DRP"  ,           0x11800E00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     32},
66256         {"AGL_GMX_RX1_STATS_PKTS_DRP"  ,           0x11800E00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     32},
66257         {"AGL_GMX_RX0_UDD_SKP"         ,           0x11800E0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     33},
66258         {"AGL_GMX_RX1_UDD_SKP"         ,           0x11800E0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     33},
66259         {"AGL_GMX_RX_BP_DROP0"         ,           0x11800E0000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     34},
66260         {"AGL_GMX_RX_BP_DROP1"         ,           0x11800E0000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     34},
66261         {"AGL_GMX_RX_BP_OFF0"          ,           0x11800E0000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     35},
66262         {"AGL_GMX_RX_BP_OFF1"          ,           0x11800E0000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     35},
66263         {"AGL_GMX_RX_BP_ON0"           ,           0x11800E0000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     36},
66264         {"AGL_GMX_RX_BP_ON1"           ,           0x11800E0000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     36},
66265         {"AGL_GMX_RX_PRT_INFO"         ,           0x11800E00004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     37},
66266         {"AGL_GMX_RX_TX_STATUS"        ,           0x11800E00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     38},
66267         {"AGL_GMX_SMAC0"               ,           0x11800E0000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     39},
66268         {"AGL_GMX_SMAC1"               ,           0x11800E0000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     39},
66269         {"AGL_GMX_STAT_BP"             ,           0x11800E0000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     40},
66270         {"AGL_GMX_TX0_APPEND"          ,           0x11800E0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
66271         {"AGL_GMX_TX1_APPEND"          ,           0x11800E0000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     41},
66272         {"AGL_GMX_TX0_CTL"             ,           0x11800E0000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     42},
66273         {"AGL_GMX_TX1_CTL"             ,           0x11800E0000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     42},
66274         {"AGL_GMX_TX0_MIN_PKT"         ,           0x11800E0000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     43},
66275         {"AGL_GMX_TX1_MIN_PKT"         ,           0x11800E0000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     43},
66276         {"AGL_GMX_TX0_PAUSE_PKT_INTERVAL",         0x11800E0000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
66277         {"AGL_GMX_TX1_PAUSE_PKT_INTERVAL",         0x11800E0000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     44},
66278         {"AGL_GMX_TX0_PAUSE_PKT_TIME"  ,           0x11800E0000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     45},
66279         {"AGL_GMX_TX1_PAUSE_PKT_TIME"  ,           0x11800E0000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     45},
66280         {"AGL_GMX_TX0_PAUSE_TOGO"      ,           0x11800E0000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
66281         {"AGL_GMX_TX1_PAUSE_TOGO"      ,           0x11800E0000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     46},
66282         {"AGL_GMX_TX0_PAUSE_ZERO"      ,           0x11800E0000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
66283         {"AGL_GMX_TX1_PAUSE_ZERO"      ,           0x11800E0000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     47},
66284         {"AGL_GMX_TX0_SOFT_PAUSE"      ,           0x11800E0000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
66285         {"AGL_GMX_TX1_SOFT_PAUSE"      ,           0x11800E0000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     48},
66286         {"AGL_GMX_TX0_STAT0"           ,           0x11800E0000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
66287         {"AGL_GMX_TX1_STAT0"           ,           0x11800E0000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     49},
66288         {"AGL_GMX_TX0_STAT1"           ,           0x11800E0000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
66289         {"AGL_GMX_TX1_STAT1"           ,           0x11800E0000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     50},
66290         {"AGL_GMX_TX0_STAT2"           ,           0x11800E0000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
66291         {"AGL_GMX_TX1_STAT2"           ,           0x11800E0000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     51},
66292         {"AGL_GMX_TX0_STAT3"           ,           0x11800E0000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
66293         {"AGL_GMX_TX1_STAT3"           ,           0x11800E0000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     52},
66294         {"AGL_GMX_TX0_STAT4"           ,           0x11800E00002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
66295         {"AGL_GMX_TX1_STAT4"           ,           0x11800E0000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     53},
66296         {"AGL_GMX_TX0_STAT5"           ,           0x11800E00002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
66297         {"AGL_GMX_TX1_STAT5"           ,           0x11800E0000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     54},
66298         {"AGL_GMX_TX0_STAT6"           ,           0x11800E00002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
66299         {"AGL_GMX_TX1_STAT6"           ,           0x11800E0000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     55},
66300         {"AGL_GMX_TX0_STAT7"           ,           0x11800E00002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
66301         {"AGL_GMX_TX1_STAT7"           ,           0x11800E0000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     56},
66302         {"AGL_GMX_TX0_STAT8"           ,           0x11800E00002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
66303         {"AGL_GMX_TX1_STAT8"           ,           0x11800E0000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     57},
66304         {"AGL_GMX_TX0_STAT9"           ,           0x11800E00002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
66305         {"AGL_GMX_TX1_STAT9"           ,           0x11800E0000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     58},
66306         {"AGL_GMX_TX0_STATS_CTL"       ,           0x11800E0000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
66307         {"AGL_GMX_TX1_STATS_CTL"       ,           0x11800E0000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     59},
66308         {"AGL_GMX_TX0_THRESH"          ,           0x11800E0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
66309         {"AGL_GMX_TX1_THRESH"          ,           0x11800E0000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     60},
66310         {"AGL_GMX_TX_BP"               ,           0x11800E00004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     61},
66311         {"AGL_GMX_TX_COL_ATTEMPT"      ,           0x11800E0000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     62},
66312         {"AGL_GMX_TX_IFG"              ,           0x11800E0000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     63},
66313         {"AGL_GMX_TX_INT_EN"           ,           0x11800E0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     64},
66314         {"AGL_GMX_TX_INT_REG"          ,           0x11800E0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     65},
66315         {"AGL_GMX_TX_JAM"              ,           0x11800E0000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     66},
66316         {"AGL_GMX_TX_LFSR"             ,           0x11800E00004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     67},
66317         {"AGL_GMX_TX_OVR_BP"           ,           0x11800E00004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     68},
66318         {"AGL_GMX_TX_PAUSE_PKT_DMAC"   ,           0x11800E00004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     69},
66319         {"AGL_GMX_TX_PAUSE_PKT_TYPE"   ,           0x11800E00004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     70},
66320         {"CIU_BIST"                    ,           0x1070000000730ull,  CVMX_CSR_DB_TYPE_NCB,   64,     71},
66321         {"CIU_DINT"                    ,           0x1070000000720ull,  CVMX_CSR_DB_TYPE_NCB,   64,     72},
66322         {"CIU_FUSE"                    ,           0x1070000000728ull,  CVMX_CSR_DB_TYPE_NCB,   64,     73},
66323         {"CIU_GSTOP"                   ,           0x1070000000710ull,  CVMX_CSR_DB_TYPE_NCB,   64,     74},
66324         {"CIU_INT0_EN0"                ,           0x1070000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
66325         {"CIU_INT1_EN0"                ,           0x1070000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
66326         {"CIU_INT2_EN0"                ,           0x1070000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
66327         {"CIU_INT3_EN0"                ,           0x1070000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
66328         {"CIU_INT4_EN0"                ,           0x1070000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
66329         {"CIU_INT5_EN0"                ,           0x1070000000250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
66330         {"CIU_INT6_EN0"                ,           0x1070000000260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
66331         {"CIU_INT7_EN0"                ,           0x1070000000270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
66332         {"CIU_INT32_EN0"               ,           0x1070000000400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     75},
66333         {"CIU_INT0_EN0_W1C"            ,           0x1070000002200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
66334         {"CIU_INT1_EN0_W1C"            ,           0x1070000002210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
66335         {"CIU_INT2_EN0_W1C"            ,           0x1070000002220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
66336         {"CIU_INT3_EN0_W1C"            ,           0x1070000002230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
66337         {"CIU_INT4_EN0_W1C"            ,           0x1070000002240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
66338         {"CIU_INT5_EN0_W1C"            ,           0x1070000002250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
66339         {"CIU_INT6_EN0_W1C"            ,           0x1070000002260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
66340         {"CIU_INT7_EN0_W1C"            ,           0x1070000002270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
66341         {"CIU_INT32_EN0_W1C"           ,           0x1070000002400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     76},
66342         {"CIU_INT0_EN0_W1S"            ,           0x1070000006200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
66343         {"CIU_INT1_EN0_W1S"            ,           0x1070000006210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
66344         {"CIU_INT2_EN0_W1S"            ,           0x1070000006220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
66345         {"CIU_INT3_EN0_W1S"            ,           0x1070000006230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
66346         {"CIU_INT4_EN0_W1S"            ,           0x1070000006240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
66347         {"CIU_INT5_EN0_W1S"            ,           0x1070000006250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
66348         {"CIU_INT6_EN0_W1S"            ,           0x1070000006260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
66349         {"CIU_INT7_EN0_W1S"            ,           0x1070000006270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
66350         {"CIU_INT32_EN0_W1S"           ,           0x1070000006400ull,  CVMX_CSR_DB_TYPE_NCB,   64,     77},
66351         {"CIU_INT0_EN1"                ,           0x1070000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
66352         {"CIU_INT1_EN1"                ,           0x1070000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
66353         {"CIU_INT2_EN1"                ,           0x1070000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
66354         {"CIU_INT3_EN1"                ,           0x1070000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
66355         {"CIU_INT4_EN1"                ,           0x1070000000248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
66356         {"CIU_INT5_EN1"                ,           0x1070000000258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
66357         {"CIU_INT6_EN1"                ,           0x1070000000268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
66358         {"CIU_INT7_EN1"                ,           0x1070000000278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
66359         {"CIU_INT32_EN1"               ,           0x1070000000408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     78},
66360         {"CIU_INT0_EN1_W1C"            ,           0x1070000002208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
66361         {"CIU_INT1_EN1_W1C"            ,           0x1070000002218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
66362         {"CIU_INT2_EN1_W1C"            ,           0x1070000002228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
66363         {"CIU_INT3_EN1_W1C"            ,           0x1070000002238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
66364         {"CIU_INT4_EN1_W1C"            ,           0x1070000002248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
66365         {"CIU_INT5_EN1_W1C"            ,           0x1070000002258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
66366         {"CIU_INT6_EN1_W1C"            ,           0x1070000002268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
66367         {"CIU_INT7_EN1_W1C"            ,           0x1070000002278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
66368         {"CIU_INT32_EN1_W1C"           ,           0x1070000002408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     79},
66369         {"CIU_INT0_EN1_W1S"            ,           0x1070000006208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
66370         {"CIU_INT1_EN1_W1S"            ,           0x1070000006218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
66371         {"CIU_INT2_EN1_W1S"            ,           0x1070000006228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
66372         {"CIU_INT3_EN1_W1S"            ,           0x1070000006238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
66373         {"CIU_INT4_EN1_W1S"            ,           0x1070000006248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
66374         {"CIU_INT5_EN1_W1S"            ,           0x1070000006258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
66375         {"CIU_INT6_EN1_W1S"            ,           0x1070000006268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
66376         {"CIU_INT7_EN1_W1S"            ,           0x1070000006278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
66377         {"CIU_INT32_EN1_W1S"           ,           0x1070000006408ull,  CVMX_CSR_DB_TYPE_NCB,   64,     80},
66378         {"CIU_INT0_EN4_0"              ,           0x1070000000C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
66379         {"CIU_INT1_EN4_0"              ,           0x1070000000C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
66380         {"CIU_INT2_EN4_0"              ,           0x1070000000CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
66381         {"CIU_INT3_EN4_0"              ,           0x1070000000CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     81},
66382         {"CIU_INT0_EN4_0_W1C"          ,           0x1070000002C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
66383         {"CIU_INT1_EN4_0_W1C"          ,           0x1070000002C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
66384         {"CIU_INT2_EN4_0_W1C"          ,           0x1070000002CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
66385         {"CIU_INT3_EN4_0_W1C"          ,           0x1070000002CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     82},
66386         {"CIU_INT0_EN4_0_W1S"          ,           0x1070000006C80ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
66387         {"CIU_INT1_EN4_0_W1S"          ,           0x1070000006C90ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
66388         {"CIU_INT2_EN4_0_W1S"          ,           0x1070000006CA0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
66389         {"CIU_INT3_EN4_0_W1S"          ,           0x1070000006CB0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     83},
66390         {"CIU_INT0_EN4_1"              ,           0x1070000000C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
66391         {"CIU_INT1_EN4_1"              ,           0x1070000000C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
66392         {"CIU_INT2_EN4_1"              ,           0x1070000000CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
66393         {"CIU_INT3_EN4_1"              ,           0x1070000000CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     84},
66394         {"CIU_INT0_EN4_1_W1C"          ,           0x1070000002C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
66395         {"CIU_INT1_EN4_1_W1C"          ,           0x1070000002C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
66396         {"CIU_INT2_EN4_1_W1C"          ,           0x1070000002CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
66397         {"CIU_INT3_EN4_1_W1C"          ,           0x1070000002CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     85},
66398         {"CIU_INT0_EN4_1_W1S"          ,           0x1070000006C88ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
66399         {"CIU_INT1_EN4_1_W1S"          ,           0x1070000006C98ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
66400         {"CIU_INT2_EN4_1_W1S"          ,           0x1070000006CA8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
66401         {"CIU_INT3_EN4_1_W1S"          ,           0x1070000006CB8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     86},
66402         {"CIU_INT0_SUM0"               ,           0x1070000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
66403         {"CIU_INT1_SUM0"               ,           0x1070000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
66404         {"CIU_INT2_SUM0"               ,           0x1070000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
66405         {"CIU_INT3_SUM0"               ,           0x1070000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
66406         {"CIU_INT4_SUM0"               ,           0x1070000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
66407         {"CIU_INT5_SUM0"               ,           0x1070000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
66408         {"CIU_INT6_SUM0"               ,           0x1070000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
66409         {"CIU_INT7_SUM0"               ,           0x1070000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
66410         {"CIU_INT32_SUM0"              ,           0x1070000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     87},
66411         {"CIU_INT0_SUM4"               ,           0x1070000000C00ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
66412         {"CIU_INT1_SUM4"               ,           0x1070000000C08ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
66413         {"CIU_INT2_SUM4"               ,           0x1070000000C10ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
66414         {"CIU_INT3_SUM4"               ,           0x1070000000C18ull,  CVMX_CSR_DB_TYPE_NCB,   64,     88},
66415         {"CIU_INT_SUM1"                ,           0x1070000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     89},
66416         {"CIU_MBOX_CLR0"               ,           0x1070000000680ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
66417         {"CIU_MBOX_CLR1"               ,           0x1070000000688ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
66418         {"CIU_MBOX_CLR2"               ,           0x1070000000690ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
66419         {"CIU_MBOX_CLR3"               ,           0x1070000000698ull,  CVMX_CSR_DB_TYPE_NCB,   64,     90},
66420         {"CIU_MBOX_SET0"               ,           0x1070000000600ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
66421         {"CIU_MBOX_SET1"               ,           0x1070000000608ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
66422         {"CIU_MBOX_SET2"               ,           0x1070000000610ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
66423         {"CIU_MBOX_SET3"               ,           0x1070000000618ull,  CVMX_CSR_DB_TYPE_NCB,   64,     91},
66424         {"CIU_NMI"                     ,           0x1070000000718ull,  CVMX_CSR_DB_TYPE_NCB,   64,     92},
66425         {"CIU_PCI_INTA"                ,           0x1070000000750ull,  CVMX_CSR_DB_TYPE_NCB,   64,     93},
66426         {"CIU_PP_DBG"                  ,           0x1070000000708ull,  CVMX_CSR_DB_TYPE_NCB,   64,     94},
66427         {"CIU_PP_POKE0"                ,           0x1070000000580ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
66428         {"CIU_PP_POKE1"                ,           0x1070000000588ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
66429         {"CIU_PP_POKE2"                ,           0x1070000000590ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
66430         {"CIU_PP_POKE3"                ,           0x1070000000598ull,  CVMX_CSR_DB_TYPE_NCB,   64,     95},
66431         {"CIU_PP_RST"                  ,           0x1070000000700ull,  CVMX_CSR_DB_TYPE_NCB,   64,     96},
66432         {"CIU_QLM_DCOK"                ,           0x1070000000760ull,  CVMX_CSR_DB_TYPE_NCB,   64,     97},
66433         {"CIU_QLM_JTGC"                ,           0x1070000000768ull,  CVMX_CSR_DB_TYPE_NCB,   64,     98},
66434         {"CIU_QLM_JTGD"                ,           0x1070000000770ull,  CVMX_CSR_DB_TYPE_NCB,   64,     99},
66435         {"CIU_SOFT_BIST"               ,           0x1070000000738ull,  CVMX_CSR_DB_TYPE_NCB,   64,     100},
66436         {"CIU_SOFT_PRST"               ,           0x1070000000748ull,  CVMX_CSR_DB_TYPE_NCB,   64,     101},
66437         {"CIU_SOFT_PRST1"              ,           0x1070000000758ull,  CVMX_CSR_DB_TYPE_NCB,   64,     102},
66438         {"CIU_SOFT_RST"                ,           0x1070000000740ull,  CVMX_CSR_DB_TYPE_NCB,   64,     103},
66439         {"CIU_TIM0"                    ,           0x1070000000480ull,  CVMX_CSR_DB_TYPE_NCB,   64,     104},
66440         {"CIU_TIM1"                    ,           0x1070000000488ull,  CVMX_CSR_DB_TYPE_NCB,   64,     104},
66441         {"CIU_TIM2"                    ,           0x1070000000490ull,  CVMX_CSR_DB_TYPE_NCB,   64,     104},
66442         {"CIU_TIM3"                    ,           0x1070000000498ull,  CVMX_CSR_DB_TYPE_NCB,   64,     104},
66443         {"CIU_WDOG0"                   ,           0x1070000000500ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
66444         {"CIU_WDOG1"                   ,           0x1070000000508ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
66445         {"CIU_WDOG2"                   ,           0x1070000000510ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
66446         {"CIU_WDOG3"                   ,           0x1070000000518ull,  CVMX_CSR_DB_TYPE_NCB,   64,     105},
66447         {"FPA_BIST_STATUS"             ,           0x11800280000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     106},
66448         {"FPA_CTL_STATUS"              ,           0x1180028000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     107},
66449         {"FPA_INT_ENB"                 ,           0x1180028000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     108},
66450         {"FPA_INT_SUM"                 ,           0x1180028000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     109},
66451         {"FPA_QUE0_AVAILABLE"          ,           0x1180028000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
66452         {"FPA_QUE1_AVAILABLE"          ,           0x11800280000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
66453         {"FPA_QUE2_AVAILABLE"          ,           0x11800280000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
66454         {"FPA_QUE3_AVAILABLE"          ,           0x11800280000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
66455         {"FPA_QUE4_AVAILABLE"          ,           0x11800280000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
66456         {"FPA_QUE5_AVAILABLE"          ,           0x11800280000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
66457         {"FPA_QUE6_AVAILABLE"          ,           0x11800280000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
66458         {"FPA_QUE7_AVAILABLE"          ,           0x11800280000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     110},
66459         {"FPA_QUE0_PAGE_INDEX"         ,           0x11800280000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
66460         {"FPA_QUE1_PAGE_INDEX"         ,           0x11800280000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
66461         {"FPA_QUE2_PAGE_INDEX"         ,           0x1180028000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
66462         {"FPA_QUE3_PAGE_INDEX"         ,           0x1180028000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
66463         {"FPA_QUE4_PAGE_INDEX"         ,           0x1180028000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
66464         {"FPA_QUE5_PAGE_INDEX"         ,           0x1180028000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
66465         {"FPA_QUE6_PAGE_INDEX"         ,           0x1180028000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
66466         {"FPA_QUE7_PAGE_INDEX"         ,           0x1180028000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     111},
66467         {"FPA_QUE_ACT"                 ,           0x1180028000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     112},
66468         {"FPA_QUE_EXP"                 ,           0x1180028000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     113},
66469         {"FPA_WART_CTL"                ,           0x11800280000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     114},
66470         {"FPA_WART_STATUS"             ,           0x11800280000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     115},
66471         {"GMX0_BAD_REG"                ,           0x1180008000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     116},
66472         {"GMX0_BIST"                   ,           0x1180008000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     117},
66473         {"GMX0_CLK_EN"                 ,           0x11800080007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     118},
66474         {"GMX0_HG2_CONTROL"            ,           0x1180008000550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     119},
66475         {"GMX0_INF_MODE"               ,           0x11800080007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     120},
66476         {"GMX0_NXA_ADR"                ,           0x1180008000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     121},
66477         {"GMX0_PRT000_CBFC_CTL"        ,           0x1180008000580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     122},
66478         {"GMX0_PRT000_CFG"             ,           0x1180008000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
66479         {"GMX0_PRT001_CFG"             ,           0x1180008000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
66480         {"GMX0_PRT002_CFG"             ,           0x1180008001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
66481         {"GMX0_PRT003_CFG"             ,           0x1180008001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     123},
66482         {"GMX0_RX000_ADR_CAM0"         ,           0x1180008000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
66483         {"GMX0_RX001_ADR_CAM0"         ,           0x1180008000980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
66484         {"GMX0_RX002_ADR_CAM0"         ,           0x1180008001180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
66485         {"GMX0_RX003_ADR_CAM0"         ,           0x1180008001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     124},
66486         {"GMX0_RX000_ADR_CAM1"         ,           0x1180008000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
66487         {"GMX0_RX001_ADR_CAM1"         ,           0x1180008000988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
66488         {"GMX0_RX002_ADR_CAM1"         ,           0x1180008001188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
66489         {"GMX0_RX003_ADR_CAM1"         ,           0x1180008001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     125},
66490         {"GMX0_RX000_ADR_CAM2"         ,           0x1180008000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
66491         {"GMX0_RX001_ADR_CAM2"         ,           0x1180008000990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
66492         {"GMX0_RX002_ADR_CAM2"         ,           0x1180008001190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
66493         {"GMX0_RX003_ADR_CAM2"         ,           0x1180008001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     126},
66494         {"GMX0_RX000_ADR_CAM3"         ,           0x1180008000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
66495         {"GMX0_RX001_ADR_CAM3"         ,           0x1180008000998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
66496         {"GMX0_RX002_ADR_CAM3"         ,           0x1180008001198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
66497         {"GMX0_RX003_ADR_CAM3"         ,           0x1180008001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     127},
66498         {"GMX0_RX000_ADR_CAM4"         ,           0x11800080001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
66499         {"GMX0_RX001_ADR_CAM4"         ,           0x11800080009A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
66500         {"GMX0_RX002_ADR_CAM4"         ,           0x11800080011A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
66501         {"GMX0_RX003_ADR_CAM4"         ,           0x11800080019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     128},
66502         {"GMX0_RX000_ADR_CAM5"         ,           0x11800080001A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
66503         {"GMX0_RX001_ADR_CAM5"         ,           0x11800080009A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
66504         {"GMX0_RX002_ADR_CAM5"         ,           0x11800080011A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
66505         {"GMX0_RX003_ADR_CAM5"         ,           0x11800080019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     129},
66506         {"GMX0_RX000_ADR_CAM_EN"       ,           0x1180008000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
66507         {"GMX0_RX001_ADR_CAM_EN"       ,           0x1180008000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
66508         {"GMX0_RX002_ADR_CAM_EN"       ,           0x1180008001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
66509         {"GMX0_RX003_ADR_CAM_EN"       ,           0x1180008001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     130},
66510         {"GMX0_RX000_ADR_CTL"          ,           0x1180008000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
66511         {"GMX0_RX001_ADR_CTL"          ,           0x1180008000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
66512         {"GMX0_RX002_ADR_CTL"          ,           0x1180008001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
66513         {"GMX0_RX003_ADR_CTL"          ,           0x1180008001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     131},
66514         {"GMX0_RX000_DECISION"         ,           0x1180008000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
66515         {"GMX0_RX001_DECISION"         ,           0x1180008000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
66516         {"GMX0_RX002_DECISION"         ,           0x1180008001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
66517         {"GMX0_RX003_DECISION"         ,           0x1180008001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     132},
66518         {"GMX0_RX000_FRM_CHK"          ,           0x1180008000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
66519         {"GMX0_RX001_FRM_CHK"          ,           0x1180008000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
66520         {"GMX0_RX002_FRM_CHK"          ,           0x1180008001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
66521         {"GMX0_RX003_FRM_CHK"          ,           0x1180008001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     133},
66522         {"GMX0_RX000_FRM_CTL"          ,           0x1180008000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
66523         {"GMX0_RX001_FRM_CTL"          ,           0x1180008000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
66524         {"GMX0_RX002_FRM_CTL"          ,           0x1180008001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
66525         {"GMX0_RX003_FRM_CTL"          ,           0x1180008001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     134},
66526         {"GMX0_RX000_IFG"              ,           0x1180008000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
66527         {"GMX0_RX001_IFG"              ,           0x1180008000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
66528         {"GMX0_RX002_IFG"              ,           0x1180008001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
66529         {"GMX0_RX003_IFG"              ,           0x1180008001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     135},
66530         {"GMX0_RX000_INT_EN"           ,           0x1180008000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
66531         {"GMX0_RX001_INT_EN"           ,           0x1180008000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
66532         {"GMX0_RX002_INT_EN"           ,           0x1180008001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
66533         {"GMX0_RX003_INT_EN"           ,           0x1180008001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     136},
66534         {"GMX0_RX000_INT_REG"          ,           0x1180008000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
66535         {"GMX0_RX001_INT_REG"          ,           0x1180008000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
66536         {"GMX0_RX002_INT_REG"          ,           0x1180008001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
66537         {"GMX0_RX003_INT_REG"          ,           0x1180008001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     137},
66538         {"GMX0_RX000_JABBER"           ,           0x1180008000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
66539         {"GMX0_RX001_JABBER"           ,           0x1180008000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
66540         {"GMX0_RX002_JABBER"           ,           0x1180008001038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
66541         {"GMX0_RX003_JABBER"           ,           0x1180008001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     138},
66542         {"GMX0_RX000_PAUSE_DROP_TIME"  ,           0x1180008000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
66543         {"GMX0_RX001_PAUSE_DROP_TIME"  ,           0x1180008000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
66544         {"GMX0_RX002_PAUSE_DROP_TIME"  ,           0x1180008001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
66545         {"GMX0_RX003_PAUSE_DROP_TIME"  ,           0x1180008001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     139},
66546         {"GMX0_RX000_STATS_CTL"        ,           0x1180008000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
66547         {"GMX0_RX001_STATS_CTL"        ,           0x1180008000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
66548         {"GMX0_RX002_STATS_CTL"        ,           0x1180008001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
66549         {"GMX0_RX003_STATS_CTL"        ,           0x1180008001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     140},
66550         {"GMX0_RX000_STATS_OCTS"       ,           0x1180008000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
66551         {"GMX0_RX001_STATS_OCTS"       ,           0x1180008000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
66552         {"GMX0_RX002_STATS_OCTS"       ,           0x1180008001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
66553         {"GMX0_RX003_STATS_OCTS"       ,           0x1180008001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     141},
66554         {"GMX0_RX000_STATS_OCTS_CTL"   ,           0x1180008000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
66555         {"GMX0_RX001_STATS_OCTS_CTL"   ,           0x1180008000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
66556         {"GMX0_RX002_STATS_OCTS_CTL"   ,           0x1180008001098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
66557         {"GMX0_RX003_STATS_OCTS_CTL"   ,           0x1180008001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     142},
66558         {"GMX0_RX000_STATS_OCTS_DMAC"  ,           0x11800080000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
66559         {"GMX0_RX001_STATS_OCTS_DMAC"  ,           0x11800080008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
66560         {"GMX0_RX002_STATS_OCTS_DMAC"  ,           0x11800080010A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
66561         {"GMX0_RX003_STATS_OCTS_DMAC"  ,           0x11800080018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     143},
66562         {"GMX0_RX000_STATS_OCTS_DRP"   ,           0x11800080000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
66563         {"GMX0_RX001_STATS_OCTS_DRP"   ,           0x11800080008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
66564         {"GMX0_RX002_STATS_OCTS_DRP"   ,           0x11800080010B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
66565         {"GMX0_RX003_STATS_OCTS_DRP"   ,           0x11800080018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     144},
66566         {"GMX0_RX000_STATS_PKTS"       ,           0x1180008000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
66567         {"GMX0_RX001_STATS_PKTS"       ,           0x1180008000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
66568         {"GMX0_RX002_STATS_PKTS"       ,           0x1180008001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
66569         {"GMX0_RX003_STATS_PKTS"       ,           0x1180008001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     145},
66570         {"GMX0_RX000_STATS_PKTS_BAD"   ,           0x11800080000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
66571         {"GMX0_RX001_STATS_PKTS_BAD"   ,           0x11800080008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
66572         {"GMX0_RX002_STATS_PKTS_BAD"   ,           0x11800080010C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
66573         {"GMX0_RX003_STATS_PKTS_BAD"   ,           0x11800080018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     146},
66574         {"GMX0_RX000_STATS_PKTS_CTL"   ,           0x1180008000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
66575         {"GMX0_RX001_STATS_PKTS_CTL"   ,           0x1180008000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
66576         {"GMX0_RX002_STATS_PKTS_CTL"   ,           0x1180008001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
66577         {"GMX0_RX003_STATS_PKTS_CTL"   ,           0x1180008001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     147},
66578         {"GMX0_RX000_STATS_PKTS_DMAC"  ,           0x11800080000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
66579         {"GMX0_RX001_STATS_PKTS_DMAC"  ,           0x11800080008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
66580         {"GMX0_RX002_STATS_PKTS_DMAC"  ,           0x11800080010A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
66581         {"GMX0_RX003_STATS_PKTS_DMAC"  ,           0x11800080018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     148},
66582         {"GMX0_RX000_STATS_PKTS_DRP"   ,           0x11800080000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
66583         {"GMX0_RX001_STATS_PKTS_DRP"   ,           0x11800080008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
66584         {"GMX0_RX002_STATS_PKTS_DRP"   ,           0x11800080010B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
66585         {"GMX0_RX003_STATS_PKTS_DRP"   ,           0x11800080018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     149},
66586         {"GMX0_RX000_UDD_SKP"          ,           0x1180008000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
66587         {"GMX0_RX001_UDD_SKP"          ,           0x1180008000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
66588         {"GMX0_RX002_UDD_SKP"          ,           0x1180008001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
66589         {"GMX0_RX003_UDD_SKP"          ,           0x1180008001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     150},
66590         {"GMX0_RX_BP_DROP000"          ,           0x1180008000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
66591         {"GMX0_RX_BP_DROP001"          ,           0x1180008000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
66592         {"GMX0_RX_BP_DROP002"          ,           0x1180008000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
66593         {"GMX0_RX_BP_DROP003"          ,           0x1180008000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     151},
66594         {"GMX0_RX_BP_OFF000"           ,           0x1180008000460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
66595         {"GMX0_RX_BP_OFF001"           ,           0x1180008000468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
66596         {"GMX0_RX_BP_OFF002"           ,           0x1180008000470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
66597         {"GMX0_RX_BP_OFF003"           ,           0x1180008000478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     152},
66598         {"GMX0_RX_BP_ON000"            ,           0x1180008000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
66599         {"GMX0_RX_BP_ON001"            ,           0x1180008000448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
66600         {"GMX0_RX_BP_ON002"            ,           0x1180008000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
66601         {"GMX0_RX_BP_ON003"            ,           0x1180008000458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     153},
66602         {"GMX0_RX_HG2_STATUS"          ,           0x1180008000548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     154},
66603         {"GMX0_RX_PRT_INFO"            ,           0x11800080004E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     155},
66604         {"GMX0_RX_PRTS"                ,           0x1180008000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     156},
66605         {"GMX0_RX_XAUI_BAD_COL"        ,           0x1180008000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     157},
66606         {"GMX0_RX_XAUI_CTL"            ,           0x1180008000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     158},
66607         {"GMX0_SMAC000"                ,           0x1180008000230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
66608         {"GMX0_SMAC001"                ,           0x1180008000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
66609         {"GMX0_SMAC002"                ,           0x1180008001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
66610         {"GMX0_SMAC003"                ,           0x1180008001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     159},
66611         {"GMX0_STAT_BP"                ,           0x1180008000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     160},
66612         {"GMX0_TX000_APPEND"           ,           0x1180008000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
66613         {"GMX0_TX001_APPEND"           ,           0x1180008000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
66614         {"GMX0_TX002_APPEND"           ,           0x1180008001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
66615         {"GMX0_TX003_APPEND"           ,           0x1180008001A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     161},
66616         {"GMX0_TX000_BURST"            ,           0x1180008000228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
66617         {"GMX0_TX001_BURST"            ,           0x1180008000A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
66618         {"GMX0_TX002_BURST"            ,           0x1180008001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
66619         {"GMX0_TX003_BURST"            ,           0x1180008001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     162},
66620         {"GMX0_TX000_CBFC_XOFF"        ,           0x11800080005A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     163},
66621         {"GMX0_TX000_CBFC_XON"         ,           0x11800080005C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     164},
66622         {"GMX0_TX000_CTL"              ,           0x1180008000270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
66623         {"GMX0_TX001_CTL"              ,           0x1180008000A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
66624         {"GMX0_TX002_CTL"              ,           0x1180008001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
66625         {"GMX0_TX003_CTL"              ,           0x1180008001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     165},
66626         {"GMX0_TX000_MIN_PKT"          ,           0x1180008000240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
66627         {"GMX0_TX001_MIN_PKT"          ,           0x1180008000A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
66628         {"GMX0_TX002_MIN_PKT"          ,           0x1180008001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
66629         {"GMX0_TX003_MIN_PKT"          ,           0x1180008001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     166},
66630         {"GMX0_TX000_PAUSE_PKT_INTERVAL",          0x1180008000248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
66631         {"GMX0_TX001_PAUSE_PKT_INTERVAL",          0x1180008000A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
66632         {"GMX0_TX002_PAUSE_PKT_INTERVAL",          0x1180008001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
66633         {"GMX0_TX003_PAUSE_PKT_INTERVAL",          0x1180008001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     167},
66634         {"GMX0_TX000_PAUSE_PKT_TIME"   ,           0x1180008000238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
66635         {"GMX0_TX001_PAUSE_PKT_TIME"   ,           0x1180008000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
66636         {"GMX0_TX002_PAUSE_PKT_TIME"   ,           0x1180008001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
66637         {"GMX0_TX003_PAUSE_PKT_TIME"   ,           0x1180008001A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     168},
66638         {"GMX0_TX000_PAUSE_TOGO"       ,           0x1180008000258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
66639         {"GMX0_TX001_PAUSE_TOGO"       ,           0x1180008000A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
66640         {"GMX0_TX002_PAUSE_TOGO"       ,           0x1180008001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
66641         {"GMX0_TX003_PAUSE_TOGO"       ,           0x1180008001A58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     169},
66642         {"GMX0_TX000_PAUSE_ZERO"       ,           0x1180008000260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
66643         {"GMX0_TX001_PAUSE_ZERO"       ,           0x1180008000A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
66644         {"GMX0_TX002_PAUSE_ZERO"       ,           0x1180008001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
66645         {"GMX0_TX003_PAUSE_ZERO"       ,           0x1180008001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     170},
66646         {"GMX0_TX000_SGMII_CTL"        ,           0x1180008000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
66647         {"GMX0_TX001_SGMII_CTL"        ,           0x1180008000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
66648         {"GMX0_TX002_SGMII_CTL"        ,           0x1180008001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
66649         {"GMX0_TX003_SGMII_CTL"        ,           0x1180008001B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     171},
66650         {"GMX0_TX000_SLOT"             ,           0x1180008000220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
66651         {"GMX0_TX001_SLOT"             ,           0x1180008000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
66652         {"GMX0_TX002_SLOT"             ,           0x1180008001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
66653         {"GMX0_TX003_SLOT"             ,           0x1180008001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     172},
66654         {"GMX0_TX000_SOFT_PAUSE"       ,           0x1180008000250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
66655         {"GMX0_TX001_SOFT_PAUSE"       ,           0x1180008000A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
66656         {"GMX0_TX002_SOFT_PAUSE"       ,           0x1180008001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
66657         {"GMX0_TX003_SOFT_PAUSE"       ,           0x1180008001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     173},
66658         {"GMX0_TX000_STAT0"            ,           0x1180008000280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
66659         {"GMX0_TX001_STAT0"            ,           0x1180008000A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
66660         {"GMX0_TX002_STAT0"            ,           0x1180008001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
66661         {"GMX0_TX003_STAT0"            ,           0x1180008001A80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     174},
66662         {"GMX0_TX000_STAT1"            ,           0x1180008000288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
66663         {"GMX0_TX001_STAT1"            ,           0x1180008000A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
66664         {"GMX0_TX002_STAT1"            ,           0x1180008001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
66665         {"GMX0_TX003_STAT1"            ,           0x1180008001A88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     175},
66666         {"GMX0_TX000_STAT2"            ,           0x1180008000290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
66667         {"GMX0_TX001_STAT2"            ,           0x1180008000A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
66668         {"GMX0_TX002_STAT2"            ,           0x1180008001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
66669         {"GMX0_TX003_STAT2"            ,           0x1180008001A90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     176},
66670         {"GMX0_TX000_STAT3"            ,           0x1180008000298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
66671         {"GMX0_TX001_STAT3"            ,           0x1180008000A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
66672         {"GMX0_TX002_STAT3"            ,           0x1180008001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
66673         {"GMX0_TX003_STAT3"            ,           0x1180008001A98ull,  CVMX_CSR_DB_TYPE_RSL,   64,     177},
66674         {"GMX0_TX000_STAT4"            ,           0x11800080002A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
66675         {"GMX0_TX001_STAT4"            ,           0x1180008000AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
66676         {"GMX0_TX002_STAT4"            ,           0x11800080012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
66677         {"GMX0_TX003_STAT4"            ,           0x1180008001AA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     178},
66678         {"GMX0_TX000_STAT5"            ,           0x11800080002A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
66679         {"GMX0_TX001_STAT5"            ,           0x1180008000AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
66680         {"GMX0_TX002_STAT5"            ,           0x11800080012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
66681         {"GMX0_TX003_STAT5"            ,           0x1180008001AA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     179},
66682         {"GMX0_TX000_STAT6"            ,           0x11800080002B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
66683         {"GMX0_TX001_STAT6"            ,           0x1180008000AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
66684         {"GMX0_TX002_STAT6"            ,           0x11800080012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
66685         {"GMX0_TX003_STAT6"            ,           0x1180008001AB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     180},
66686         {"GMX0_TX000_STAT7"            ,           0x11800080002B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
66687         {"GMX0_TX001_STAT7"            ,           0x1180008000AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
66688         {"GMX0_TX002_STAT7"            ,           0x11800080012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
66689         {"GMX0_TX003_STAT7"            ,           0x1180008001AB8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     181},
66690         {"GMX0_TX000_STAT8"            ,           0x11800080002C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
66691         {"GMX0_TX001_STAT8"            ,           0x1180008000AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
66692         {"GMX0_TX002_STAT8"            ,           0x11800080012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
66693         {"GMX0_TX003_STAT8"            ,           0x1180008001AC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     182},
66694         {"GMX0_TX000_STAT9"            ,           0x11800080002C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
66695         {"GMX0_TX001_STAT9"            ,           0x1180008000AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
66696         {"GMX0_TX002_STAT9"            ,           0x11800080012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
66697         {"GMX0_TX003_STAT9"            ,           0x1180008001AC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     183},
66698         {"GMX0_TX000_STATS_CTL"        ,           0x1180008000268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
66699         {"GMX0_TX001_STATS_CTL"        ,           0x1180008000A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
66700         {"GMX0_TX002_STATS_CTL"        ,           0x1180008001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
66701         {"GMX0_TX003_STATS_CTL"        ,           0x1180008001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     184},
66702         {"GMX0_TX000_THRESH"           ,           0x1180008000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
66703         {"GMX0_TX001_THRESH"           ,           0x1180008000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
66704         {"GMX0_TX002_THRESH"           ,           0x1180008001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
66705         {"GMX0_TX003_THRESH"           ,           0x1180008001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     185},
66706         {"GMX0_TX_BP"                  ,           0x11800080004D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     186},
66707         {"GMX0_TX_COL_ATTEMPT"         ,           0x1180008000498ull,  CVMX_CSR_DB_TYPE_RSL,   64,     187},
66708         {"GMX0_TX_CORRUPT"             ,           0x11800080004D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     188},
66709         {"GMX0_TX_HG2_REG1"            ,           0x1180008000558ull,  CVMX_CSR_DB_TYPE_RSL,   64,     189},
66710         {"GMX0_TX_HG2_REG2"            ,           0x1180008000560ull,  CVMX_CSR_DB_TYPE_RSL,   64,     190},
66711         {"GMX0_TX_IFG"                 ,           0x1180008000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     191},
66712         {"GMX0_TX_INT_EN"              ,           0x1180008000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     192},
66713         {"GMX0_TX_INT_REG"             ,           0x1180008000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     193},
66714         {"GMX0_TX_JAM"                 ,           0x1180008000490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     194},
66715         {"GMX0_TX_LFSR"                ,           0x11800080004F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     195},
66716         {"GMX0_TX_OVR_BP"              ,           0x11800080004C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     196},
66717         {"GMX0_TX_PAUSE_PKT_DMAC"      ,           0x11800080004A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     197},
66718         {"GMX0_TX_PAUSE_PKT_TYPE"      ,           0x11800080004A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     198},
66719         {"GMX0_TX_PRTS"                ,           0x1180008000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     199},
66720         {"GMX0_TX_XAUI_CTL"            ,           0x1180008000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     200},
66721         {"GMX0_XAUI_EXT_LOOPBACK"      ,           0x1180008000540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     201},
66722         {"GPIO_BIT_CFG0"               ,           0x1070000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66723         {"GPIO_BIT_CFG1"               ,           0x1070000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66724         {"GPIO_BIT_CFG2"               ,           0x1070000000810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66725         {"GPIO_BIT_CFG3"               ,           0x1070000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66726         {"GPIO_BIT_CFG4"               ,           0x1070000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66727         {"GPIO_BIT_CFG5"               ,           0x1070000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66728         {"GPIO_BIT_CFG6"               ,           0x1070000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66729         {"GPIO_BIT_CFG7"               ,           0x1070000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66730         {"GPIO_BIT_CFG8"               ,           0x1070000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66731         {"GPIO_BIT_CFG9"               ,           0x1070000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66732         {"GPIO_BIT_CFG10"              ,           0x1070000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66733         {"GPIO_BIT_CFG11"              ,           0x1070000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66734         {"GPIO_BIT_CFG12"              ,           0x1070000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66735         {"GPIO_BIT_CFG13"              ,           0x1070000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66736         {"GPIO_BIT_CFG14"              ,           0x1070000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66737         {"GPIO_BIT_CFG15"              ,           0x1070000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     202},
66738         {"GPIO_CLK_GEN0"               ,           0x10700000008C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     203},
66739         {"GPIO_CLK_GEN1"               ,           0x10700000008C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     203},
66740         {"GPIO_CLK_GEN2"               ,           0x10700000008D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     203},
66741         {"GPIO_CLK_GEN3"               ,           0x10700000008D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     203},
66742         {"GPIO_INT_CLR"                ,           0x1070000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     204},
66743         {"GPIO_RX_DAT"                 ,           0x1070000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     205},
66744         {"GPIO_TX_CLR"                 ,           0x1070000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     206},
66745         {"GPIO_TX_SET"                 ,           0x1070000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     207},
66746         {"IOB_BIST_STATUS"             ,           0x11800F00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     208},
66747         {"IOB_CTL_STATUS"              ,           0x11800F0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     209},
66748         {"IOB_DWB_PRI_CNT"             ,           0x11800F0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     210},
66749         {"IOB_FAU_TIMEOUT"             ,           0x11800F0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     211},
66750         {"IOB_I2C_PRI_CNT"             ,           0x11800F0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     212},
66751         {"IOB_INB_CONTROL_MATCH"       ,           0x11800F0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     213},
66752         {"IOB_INB_CONTROL_MATCH_ENB"   ,           0x11800F0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     214},
66753         {"IOB_INB_DATA_MATCH"          ,           0x11800F0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     215},
66754         {"IOB_INB_DATA_MATCH_ENB"      ,           0x11800F0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     216},
66755         {"IOB_INT_ENB"                 ,           0x11800F0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     217},
66756         {"IOB_INT_SUM"                 ,           0x11800F0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     218},
66757         {"IOB_N2C_L2C_PRI_CNT"         ,           0x11800F0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     219},
66758         {"IOB_N2C_RSP_PRI_CNT"         ,           0x11800F0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     220},
66759         {"IOB_OUTB_COM_PRI_CNT"        ,           0x11800F0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     221},
66760         {"IOB_OUTB_CONTROL_MATCH"      ,           0x11800F0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     222},
66761         {"IOB_OUTB_CONTROL_MATCH_ENB"  ,           0x11800F00000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     223},
66762         {"IOB_OUTB_DATA_MATCH"         ,           0x11800F0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     224},
66763         {"IOB_OUTB_DATA_MATCH_ENB"     ,           0x11800F00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     225},
66764         {"IOB_OUTB_FPA_PRI_CNT"        ,           0x11800F0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     226},
66765         {"IOB_OUTB_REQ_PRI_CNT"        ,           0x11800F0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     227},
66766         {"IOB_P2C_REQ_PRI_CNT"         ,           0x11800F0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     228},
66767         {"IOB_PKT_ERR"                 ,           0x11800F0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     229},
66768         {"IOB_TO_CMB_CREDITS"          ,           0x11800F00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     230},
66769         {"IPD_1ST_MBUFF_SKIP"          ,           0x14F0000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     231},
66770         {"IPD_1ST_NEXT_PTR_BACK"       ,           0x14F0000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     232},
66771         {"IPD_2ND_NEXT_PTR_BACK"       ,           0x14F0000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     233},
66772         {"IPD_BIST_STATUS"             ,           0x14F00000007F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     234},
66773         {"IPD_BP_PRT_RED_END"          ,           0x14F0000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     235},
66774         {"IPD_CLK_COUNT"               ,           0x14F0000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     236},
66775         {"IPD_CTL_STATUS"              ,           0x14F0000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     237},
66776         {"IPD_INT_ENB"                 ,           0x14F0000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     238},
66777         {"IPD_INT_SUM"                 ,           0x14F0000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     239},
66778         {"IPD_NOT_1ST_MBUFF_SKIP"      ,           0x14F0000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     240},
66779         {"IPD_PACKET_MBUFF_SIZE"       ,           0x14F0000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     241},
66780         {"IPD_PKT_PTR_VALID"           ,           0x14F0000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     242},
66781         {"IPD_PORT0_BP_PAGE_CNT"       ,           0x14F0000000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
66782         {"IPD_PORT1_BP_PAGE_CNT"       ,           0x14F0000000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
66783         {"IPD_PORT2_BP_PAGE_CNT"       ,           0x14F0000000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
66784         {"IPD_PORT3_BP_PAGE_CNT"       ,           0x14F0000000040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
66785         {"IPD_PORT32_BP_PAGE_CNT"      ,           0x14F0000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
66786         {"IPD_PORT33_BP_PAGE_CNT"      ,           0x14F0000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
66787         {"IPD_PORT34_BP_PAGE_CNT"      ,           0x14F0000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
66788         {"IPD_PORT35_BP_PAGE_CNT"      ,           0x14F0000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     243},
66789         {"IPD_PORT36_BP_PAGE_CNT2"     ,           0x14F0000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     244},
66790         {"IPD_PORT37_BP_PAGE_CNT2"     ,           0x14F0000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     244},
66791         {"IPD_PORT38_BP_PAGE_CNT2"     ,           0x14F0000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     244},
66792         {"IPD_PORT39_BP_PAGE_CNT2"     ,           0x14F0000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     244},
66793         {"IPD_PORT_BP_COUNTERS2_PAIR36",           0x14F0000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     245},
66794         {"IPD_PORT_BP_COUNTERS2_PAIR37",           0x14F0000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     245},
66795         {"IPD_PORT_BP_COUNTERS2_PAIR38",           0x14F0000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     245},
66796         {"IPD_PORT_BP_COUNTERS2_PAIR39",           0x14F00000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     245},
66797         {"IPD_PORT_BP_COUNTERS_PAIR0"  ,           0x14F00000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
66798         {"IPD_PORT_BP_COUNTERS_PAIR1"  ,           0x14F00000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
66799         {"IPD_PORT_BP_COUNTERS_PAIR2"  ,           0x14F00000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
66800         {"IPD_PORT_BP_COUNTERS_PAIR3"  ,           0x14F00000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
66801         {"IPD_PORT_BP_COUNTERS_PAIR32" ,           0x14F00000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
66802         {"IPD_PORT_BP_COUNTERS_PAIR33" ,           0x14F00000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
66803         {"IPD_PORT_BP_COUNTERS_PAIR34" ,           0x14F00000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
66804         {"IPD_PORT_BP_COUNTERS_PAIR35" ,           0x14F00000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     246},
66805         {"IPD_PORT_QOS_0_CNT"          ,           0x14F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66806         {"IPD_PORT_QOS_1_CNT"          ,           0x14F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66807         {"IPD_PORT_QOS_2_CNT"          ,           0x14F0000000898ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66808         {"IPD_PORT_QOS_3_CNT"          ,           0x14F00000008A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66809         {"IPD_PORT_QOS_4_CNT"          ,           0x14F00000008A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66810         {"IPD_PORT_QOS_5_CNT"          ,           0x14F00000008B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66811         {"IPD_PORT_QOS_6_CNT"          ,           0x14F00000008B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66812         {"IPD_PORT_QOS_7_CNT"          ,           0x14F00000008C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66813         {"IPD_PORT_QOS_8_CNT"          ,           0x14F00000008C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66814         {"IPD_PORT_QOS_9_CNT"          ,           0x14F00000008D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66815         {"IPD_PORT_QOS_10_CNT"         ,           0x14F00000008D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66816         {"IPD_PORT_QOS_11_CNT"         ,           0x14F00000008E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66817         {"IPD_PORT_QOS_12_CNT"         ,           0x14F00000008E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66818         {"IPD_PORT_QOS_13_CNT"         ,           0x14F00000008F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66819         {"IPD_PORT_QOS_14_CNT"         ,           0x14F00000008F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66820         {"IPD_PORT_QOS_15_CNT"         ,           0x14F0000000900ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66821         {"IPD_PORT_QOS_16_CNT"         ,           0x14F0000000908ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66822         {"IPD_PORT_QOS_17_CNT"         ,           0x14F0000000910ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66823         {"IPD_PORT_QOS_18_CNT"         ,           0x14F0000000918ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66824         {"IPD_PORT_QOS_19_CNT"         ,           0x14F0000000920ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66825         {"IPD_PORT_QOS_20_CNT"         ,           0x14F0000000928ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66826         {"IPD_PORT_QOS_21_CNT"         ,           0x14F0000000930ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66827         {"IPD_PORT_QOS_22_CNT"         ,           0x14F0000000938ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66828         {"IPD_PORT_QOS_23_CNT"         ,           0x14F0000000940ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66829         {"IPD_PORT_QOS_24_CNT"         ,           0x14F0000000948ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66830         {"IPD_PORT_QOS_25_CNT"         ,           0x14F0000000950ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66831         {"IPD_PORT_QOS_26_CNT"         ,           0x14F0000000958ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66832         {"IPD_PORT_QOS_27_CNT"         ,           0x14F0000000960ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66833         {"IPD_PORT_QOS_28_CNT"         ,           0x14F0000000968ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66834         {"IPD_PORT_QOS_29_CNT"         ,           0x14F0000000970ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66835         {"IPD_PORT_QOS_30_CNT"         ,           0x14F0000000978ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66836         {"IPD_PORT_QOS_31_CNT"         ,           0x14F0000000980ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66837         {"IPD_PORT_QOS_256_CNT"        ,           0x14F0000001088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66838         {"IPD_PORT_QOS_257_CNT"        ,           0x14F0000001090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66839         {"IPD_PORT_QOS_258_CNT"        ,           0x14F0000001098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66840         {"IPD_PORT_QOS_259_CNT"        ,           0x14F00000010A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66841         {"IPD_PORT_QOS_260_CNT"        ,           0x14F00000010A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66842         {"IPD_PORT_QOS_261_CNT"        ,           0x14F00000010B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66843         {"IPD_PORT_QOS_262_CNT"        ,           0x14F00000010B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66844         {"IPD_PORT_QOS_263_CNT"        ,           0x14F00000010C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66845         {"IPD_PORT_QOS_264_CNT"        ,           0x14F00000010C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66846         {"IPD_PORT_QOS_265_CNT"        ,           0x14F00000010D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66847         {"IPD_PORT_QOS_266_CNT"        ,           0x14F00000010D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66848         {"IPD_PORT_QOS_267_CNT"        ,           0x14F00000010E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66849         {"IPD_PORT_QOS_268_CNT"        ,           0x14F00000010E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66850         {"IPD_PORT_QOS_269_CNT"        ,           0x14F00000010F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66851         {"IPD_PORT_QOS_270_CNT"        ,           0x14F00000010F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66852         {"IPD_PORT_QOS_271_CNT"        ,           0x14F0000001100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66853         {"IPD_PORT_QOS_272_CNT"        ,           0x14F0000001108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66854         {"IPD_PORT_QOS_273_CNT"        ,           0x14F0000001110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66855         {"IPD_PORT_QOS_274_CNT"        ,           0x14F0000001118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66856         {"IPD_PORT_QOS_275_CNT"        ,           0x14F0000001120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66857         {"IPD_PORT_QOS_276_CNT"        ,           0x14F0000001128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66858         {"IPD_PORT_QOS_277_CNT"        ,           0x14F0000001130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66859         {"IPD_PORT_QOS_278_CNT"        ,           0x14F0000001138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66860         {"IPD_PORT_QOS_279_CNT"        ,           0x14F0000001140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66861         {"IPD_PORT_QOS_280_CNT"        ,           0x14F0000001148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66862         {"IPD_PORT_QOS_281_CNT"        ,           0x14F0000001150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66863         {"IPD_PORT_QOS_282_CNT"        ,           0x14F0000001158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66864         {"IPD_PORT_QOS_283_CNT"        ,           0x14F0000001160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66865         {"IPD_PORT_QOS_284_CNT"        ,           0x14F0000001168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66866         {"IPD_PORT_QOS_285_CNT"        ,           0x14F0000001170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66867         {"IPD_PORT_QOS_286_CNT"        ,           0x14F0000001178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66868         {"IPD_PORT_QOS_287_CNT"        ,           0x14F0000001180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66869         {"IPD_PORT_QOS_288_CNT"        ,           0x14F0000001188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66870         {"IPD_PORT_QOS_289_CNT"        ,           0x14F0000001190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66871         {"IPD_PORT_QOS_290_CNT"        ,           0x14F0000001198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66872         {"IPD_PORT_QOS_291_CNT"        ,           0x14F00000011A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66873         {"IPD_PORT_QOS_292_CNT"        ,           0x14F00000011A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66874         {"IPD_PORT_QOS_293_CNT"        ,           0x14F00000011B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66875         {"IPD_PORT_QOS_294_CNT"        ,           0x14F00000011B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66876         {"IPD_PORT_QOS_295_CNT"        ,           0x14F00000011C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66877         {"IPD_PORT_QOS_296_CNT"        ,           0x14F00000011C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66878         {"IPD_PORT_QOS_297_CNT"        ,           0x14F00000011D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66879         {"IPD_PORT_QOS_298_CNT"        ,           0x14F00000011D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66880         {"IPD_PORT_QOS_299_CNT"        ,           0x14F00000011E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66881         {"IPD_PORT_QOS_300_CNT"        ,           0x14F00000011E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66882         {"IPD_PORT_QOS_301_CNT"        ,           0x14F00000011F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66883         {"IPD_PORT_QOS_302_CNT"        ,           0x14F00000011F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66884         {"IPD_PORT_QOS_303_CNT"        ,           0x14F0000001200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66885         {"IPD_PORT_QOS_304_CNT"        ,           0x14F0000001208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66886         {"IPD_PORT_QOS_305_CNT"        ,           0x14F0000001210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66887         {"IPD_PORT_QOS_306_CNT"        ,           0x14F0000001218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66888         {"IPD_PORT_QOS_307_CNT"        ,           0x14F0000001220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66889         {"IPD_PORT_QOS_308_CNT"        ,           0x14F0000001228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66890         {"IPD_PORT_QOS_309_CNT"        ,           0x14F0000001230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66891         {"IPD_PORT_QOS_310_CNT"        ,           0x14F0000001238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66892         {"IPD_PORT_QOS_311_CNT"        ,           0x14F0000001240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66893         {"IPD_PORT_QOS_312_CNT"        ,           0x14F0000001248ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66894         {"IPD_PORT_QOS_313_CNT"        ,           0x14F0000001250ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66895         {"IPD_PORT_QOS_314_CNT"        ,           0x14F0000001258ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66896         {"IPD_PORT_QOS_315_CNT"        ,           0x14F0000001260ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66897         {"IPD_PORT_QOS_316_CNT"        ,           0x14F0000001268ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66898         {"IPD_PORT_QOS_317_CNT"        ,           0x14F0000001270ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66899         {"IPD_PORT_QOS_318_CNT"        ,           0x14F0000001278ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66900         {"IPD_PORT_QOS_319_CNT"        ,           0x14F0000001280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     247},
66901         {"IPD_PORT_QOS_INT0"           ,           0x14F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     248},
66902         {"IPD_PORT_QOS_INT4"           ,           0x14F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     248},
66903         {"IPD_PORT_QOS_INT_ENB0"       ,           0x14F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
66904         {"IPD_PORT_QOS_INT_ENB4"       ,           0x14F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     249},
66905         {"IPD_PRC_HOLD_PTR_FIFO_CTL"   ,           0x14F0000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     250},
66906         {"IPD_PRC_PORT_PTR_FIFO_CTL"   ,           0x14F0000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     251},
66907         {"IPD_PTR_COUNT"               ,           0x14F0000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     252},
66908         {"IPD_PWP_PTR_FIFO_CTL"        ,           0x14F0000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     253},
66909         {"IPD_QOS0_RED_MARKS"          ,           0x14F0000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     254},
66910         {"IPD_QOS1_RED_MARKS"          ,           0x14F0000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     254},
66911         {"IPD_QOS2_RED_MARKS"          ,           0x14F0000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     254},
66912         {"IPD_QOS3_RED_MARKS"          ,           0x14F0000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     254},
66913         {"IPD_QOS4_RED_MARKS"          ,           0x14F0000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     254},
66914         {"IPD_QOS5_RED_MARKS"          ,           0x14F00000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     254},
66915         {"IPD_QOS6_RED_MARKS"          ,           0x14F00000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     254},
66916         {"IPD_QOS7_RED_MARKS"          ,           0x14F00000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     254},
66917         {"IPD_QUE0_FREE_PAGE_CNT"      ,           0x14F0000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     255},
66918         {"IPD_RED_PORT_ENABLE"         ,           0x14F00000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     256},
66919         {"IPD_RED_PORT_ENABLE2"        ,           0x14F00000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     257},
66920         {"IPD_RED_QUE0_PARAM"          ,           0x14F00000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     258},
66921         {"IPD_RED_QUE1_PARAM"          ,           0x14F00000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     258},
66922         {"IPD_RED_QUE2_PARAM"          ,           0x14F00000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     258},
66923         {"IPD_RED_QUE3_PARAM"          ,           0x14F00000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     258},
66924         {"IPD_RED_QUE4_PARAM"          ,           0x14F0000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     258},
66925         {"IPD_RED_QUE5_PARAM"          ,           0x14F0000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     258},
66926         {"IPD_RED_QUE6_PARAM"          ,           0x14F0000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     258},
66927         {"IPD_RED_QUE7_PARAM"          ,           0x14F0000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     258},
66928         {"IPD_SUB_PORT_BP_PAGE_CNT"    ,           0x14F0000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     259},
66929         {"IPD_SUB_PORT_FCS"            ,           0x14F0000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     260},
66930         {"IPD_SUB_PORT_QOS_CNT"        ,           0x14F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     261},
66931         {"IPD_WQE_FPA_QUEUE"           ,           0x14F0000000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     262},
66932         {"IPD_WQE_PTR_VALID"           ,           0x14F0000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     263},
66933         {"L2C_BST0"                    ,           0x11800800007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     264},
66934         {"L2C_BST1"                    ,           0x11800800007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     265},
66935         {"L2C_BST2"                    ,           0x11800800007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     266},
66936         {"L2C_CFG"                     ,           0x1180080000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     267},
66937         {"L2C_DBG"                     ,           0x1180080000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     268},
66938         {"L2C_DUT"                     ,           0x1180080000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     269},
66939         {"L2C_GRPWRR0"                 ,           0x11800800000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     270},
66940         {"L2C_GRPWRR1"                 ,           0x11800800000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     271},
66941         {"L2C_INT_EN"                  ,           0x1180080000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     272},
66942         {"L2C_INT_STAT"                ,           0x11800800000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     273},
66943         {"L2C_LCKBASE"                 ,           0x1180080000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     274},
66944         {"L2C_LCKOFF"                  ,           0x1180080000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     275},
66945         {"L2C_LFB0"                    ,           0x1180080000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     276},
66946         {"L2C_LFB1"                    ,           0x1180080000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     277},
66947         {"L2C_LFB2"                    ,           0x1180080000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     278},
66948         {"L2C_LFB3"                    ,           0x11800800000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     279},
66949         {"L2C_OOB"                     ,           0x11800800000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     280},
66950         {"L2C_OOB1"                    ,           0x11800800000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     281},
66951         {"L2C_OOB2"                    ,           0x11800800000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     282},
66952         {"L2C_OOB3"                    ,           0x11800800000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     283},
66953         {"L2C_PFC0"                    ,           0x1180080000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
66954         {"L2C_PFC1"                    ,           0x11800800000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
66955         {"L2C_PFC2"                    ,           0x11800800000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
66956         {"L2C_PFC3"                    ,           0x11800800000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     284},
66957         {"L2C_PFCTL"                   ,           0x1180080000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     285},
66958         {"L2C_PPGRP"                   ,           0x11800800000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     286},
66959         {"L2C_SPAR0"                   ,           0x1180080000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     287},
66960         {"L2C_SPAR4"                   ,           0x1180080000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     288},
66961         {"L2D_BST0"                    ,           0x1180080000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     289},
66962         {"L2D_BST1"                    ,           0x1180080000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     290},
66963         {"L2D_BST2"                    ,           0x1180080000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     291},
66964         {"L2D_BST3"                    ,           0x1180080000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     292},
66965         {"L2D_ERR"                     ,           0x1180080000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     293},
66966         {"L2D_FADR"                    ,           0x1180080000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     294},
66967         {"L2D_FSYN0"                   ,           0x1180080000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     295},
66968         {"L2D_FSYN1"                   ,           0x1180080000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     296},
66969         {"L2D_FUS0"                    ,           0x11800800007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     297},
66970         {"L2D_FUS1"                    ,           0x11800800007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     298},
66971         {"L2D_FUS2"                    ,           0x11800800007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     299},
66972         {"L2D_FUS3"                    ,           0x11800800007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     300},
66973         {"L2T_ERR"                     ,           0x1180080000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     301},
66974         {"LMC0_BIST_CTL"               ,           0x11800880000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     302},
66975         {"LMC0_BIST_RESULT"            ,           0x11800880000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     303},
66976         {"LMC0_COMP_CTL"               ,           0x1180088000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     304},
66977         {"LMC0_CTL"                    ,           0x1180088000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     305},
66978         {"LMC0_CTL1"                   ,           0x1180088000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     306},
66979         {"LMC0_DCLK_CNT_HI"            ,           0x1180088000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     307},
66980         {"LMC0_DCLK_CNT_LO"            ,           0x1180088000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     308},
66981         {"LMC0_DDR2_CTL"               ,           0x1180088000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     309},
66982         {"LMC0_DELAY_CFG"              ,           0x1180088000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     310},
66983         {"LMC0_DLL_CTL"                ,           0x11800880000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     311},
66984         {"LMC0_DUAL_MEMCFG"            ,           0x1180088000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     312},
66985         {"LMC0_ECC_SYND"               ,           0x1180088000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     313},
66986         {"LMC0_FADR"                   ,           0x1180088000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     314},
66987         {"LMC0_IFB_CNT_HI"             ,           0x1180088000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     315},
66988         {"LMC0_IFB_CNT_LO"             ,           0x1180088000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     316},
66989         {"LMC0_MEM_CFG0"               ,           0x1180088000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     317},
66990         {"LMC0_MEM_CFG1"               ,           0x1180088000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     318},
66991         {"LMC0_NXM"                    ,           0x11800880000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     319},
66992         {"LMC0_OPS_CNT_HI"             ,           0x1180088000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     320},
66993         {"LMC0_OPS_CNT_LO"             ,           0x1180088000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     321},
66994         {"LMC0_PLL_CTL"                ,           0x11800880000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     322},
66995         {"LMC0_PLL_STATUS"             ,           0x11800880000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     323},
66996         {"LMC0_READ_LEVEL_CTL"         ,           0x1180088000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     324},
66997         {"LMC0_READ_LEVEL_DBG"         ,           0x1180088000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     325},
66998         {"LMC0_READ_LEVEL_RANK000"     ,           0x1180088000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
66999         {"LMC0_READ_LEVEL_RANK001"     ,           0x1180088000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
67000         {"LMC0_READ_LEVEL_RANK002"     ,           0x1180088000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
67001         {"LMC0_READ_LEVEL_RANK003"     ,           0x1180088000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     326},
67002         {"LMC0_RODT_COMP_CTL"          ,           0x11800880000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     327},
67003         {"LMC0_RODT_CTL"               ,           0x1180088000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     328},
67004         {"LMC0_WODT_CTL0"              ,           0x1180088000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     329},
67005         {"LMC0_WODT_CTL1"              ,           0x1180088000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     330},
67006         {"MIO_BOOT_BIST_STAT"          ,           0x11800000000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     331},
67007         {"MIO_BOOT_COMP"               ,           0x11800000000B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     332},
67008         {"MIO_BOOT_DMA_CFG0"           ,           0x1180000000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
67009         {"MIO_BOOT_DMA_CFG1"           ,           0x1180000000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     333},
67010         {"MIO_BOOT_DMA_INT0"           ,           0x1180000000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
67011         {"MIO_BOOT_DMA_INT1"           ,           0x1180000000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     334},
67012         {"MIO_BOOT_DMA_INT_EN0"        ,           0x1180000000150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     335},
67013         {"MIO_BOOT_DMA_INT_EN1"        ,           0x1180000000158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     335},
67014         {"MIO_BOOT_DMA_TIM0"           ,           0x1180000000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     336},
67015         {"MIO_BOOT_DMA_TIM1"           ,           0x1180000000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     336},
67016         {"MIO_BOOT_ERR"                ,           0x11800000000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     337},
67017         {"MIO_BOOT_INT"                ,           0x11800000000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     338},
67018         {"MIO_BOOT_LOC_ADR"            ,           0x1180000000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     339},
67019         {"MIO_BOOT_LOC_CFG0"           ,           0x1180000000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
67020         {"MIO_BOOT_LOC_CFG1"           ,           0x1180000000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     340},
67021         {"MIO_BOOT_LOC_DAT"            ,           0x1180000000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     341},
67022         {"MIO_BOOT_PIN_DEFS"           ,           0x11800000000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     342},
67023         {"MIO_BOOT_REG_CFG0"           ,           0x1180000000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
67024         {"MIO_BOOT_REG_CFG1"           ,           0x1180000000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
67025         {"MIO_BOOT_REG_CFG2"           ,           0x1180000000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
67026         {"MIO_BOOT_REG_CFG3"           ,           0x1180000000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
67027         {"MIO_BOOT_REG_CFG4"           ,           0x1180000000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
67028         {"MIO_BOOT_REG_CFG5"           ,           0x1180000000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
67029         {"MIO_BOOT_REG_CFG6"           ,           0x1180000000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
67030         {"MIO_BOOT_REG_CFG7"           ,           0x1180000000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     343},
67031         {"MIO_BOOT_REG_TIM0"           ,           0x1180000000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
67032         {"MIO_BOOT_REG_TIM1"           ,           0x1180000000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
67033         {"MIO_BOOT_REG_TIM2"           ,           0x1180000000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
67034         {"MIO_BOOT_REG_TIM3"           ,           0x1180000000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
67035         {"MIO_BOOT_REG_TIM4"           ,           0x1180000000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
67036         {"MIO_BOOT_REG_TIM5"           ,           0x1180000000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
67037         {"MIO_BOOT_REG_TIM6"           ,           0x1180000000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
67038         {"MIO_BOOT_REG_TIM7"           ,           0x1180000000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     344},
67039         {"MIO_BOOT_THR"                ,           0x11800000000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     345},
67040         {"MIO_FUS_BNK_DAT0"            ,           0x1180000001520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     346},
67041         {"MIO_FUS_BNK_DAT1"            ,           0x1180000001528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     346},
67042         {"MIO_FUS_BNK_DAT2"            ,           0x1180000001530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     346},
67043         {"MIO_FUS_BNK_DAT3"            ,           0x1180000001538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     346},
67044         {"MIO_FUS_DAT0"                ,           0x1180000001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     347},
67045         {"MIO_FUS_DAT1"                ,           0x1180000001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     348},
67046         {"MIO_FUS_DAT2"                ,           0x1180000001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     349},
67047         {"MIO_FUS_DAT3"                ,           0x1180000001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     350},
67048         {"MIO_FUS_EMA"                 ,           0x1180000001550ull,  CVMX_CSR_DB_TYPE_RSL,   64,     351},
67049         {"MIO_FUS_PDF"                 ,           0x1180000001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     352},
67050         {"MIO_FUS_PLL"                 ,           0x1180000001580ull,  CVMX_CSR_DB_TYPE_RSL,   64,     353},
67051         {"MIO_FUS_PROG"                ,           0x1180000001510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     354},
67052         {"MIO_FUS_PROG_TIMES"          ,           0x1180000001518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     355},
67053         {"MIO_FUS_RCMD"                ,           0x1180000001500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     356},
67054         {"MIO_FUS_SPR_REPAIR_RES"      ,           0x1180000001548ull,  CVMX_CSR_DB_TYPE_RSL,   64,     357},
67055         {"MIO_FUS_SPR_REPAIR_SUM"      ,           0x1180000001540ull,  CVMX_CSR_DB_TYPE_RSL,   64,     358},
67056         {"MIO_FUS_WADR"                ,           0x1180000001508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     359},
67057         {"MIO_NDF_DMA_CFG"             ,           0x1180000000168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     360},
67058         {"MIO_NDF_DMA_INT"             ,           0x1180000000170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     361},
67059         {"MIO_NDF_DMA_INT_EN"          ,           0x1180000000178ull,  CVMX_CSR_DB_TYPE_RSL,   64,     362},
67060         {"MIO_TWS0_INT"                ,           0x1180000001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     363},
67061         {"MIO_TWS1_INT"                ,           0x1180000001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     363},
67062         {"MIO_TWS0_SW_TWSI"            ,           0x1180000001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     364},
67063         {"MIO_TWS1_SW_TWSI"            ,           0x1180000001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     364},
67064         {"MIO_TWS0_SW_TWSI_EXT"        ,           0x1180000001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     365},
67065         {"MIO_TWS1_SW_TWSI_EXT"        ,           0x1180000001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     365},
67066         {"MIO_TWS0_TWSI_SW"            ,           0x1180000001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
67067         {"MIO_TWS1_TWSI_SW"            ,           0x1180000001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     366},
67068         {"MIO_UART0_DLH"               ,           0x1180000000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
67069         {"MIO_UART1_DLH"               ,           0x1180000000C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     367},
67070         {"MIO_UART0_DLL"               ,           0x1180000000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     368},
67071         {"MIO_UART1_DLL"               ,           0x1180000000C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     368},
67072         {"MIO_UART0_FAR"               ,           0x1180000000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
67073         {"MIO_UART1_FAR"               ,           0x1180000000D20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     369},
67074         {"MIO_UART0_FCR"               ,           0x1180000000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     370},
67075         {"MIO_UART1_FCR"               ,           0x1180000000C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     370},
67076         {"MIO_UART0_HTX"               ,           0x1180000000B08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     371},
67077         {"MIO_UART1_HTX"               ,           0x1180000000F08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     371},
67078         {"MIO_UART0_IER"               ,           0x1180000000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     372},
67079         {"MIO_UART1_IER"               ,           0x1180000000C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     372},
67080         {"MIO_UART0_IIR"               ,           0x1180000000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     373},
67081         {"MIO_UART1_IIR"               ,           0x1180000000C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     373},
67082         {"MIO_UART0_LCR"               ,           0x1180000000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     374},
67083         {"MIO_UART1_LCR"               ,           0x1180000000C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     374},
67084         {"MIO_UART0_LSR"               ,           0x1180000000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     375},
67085         {"MIO_UART1_LSR"               ,           0x1180000000C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     375},
67086         {"MIO_UART0_MCR"               ,           0x1180000000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     376},
67087         {"MIO_UART1_MCR"               ,           0x1180000000C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     376},
67088         {"MIO_UART0_MSR"               ,           0x1180000000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     377},
67089         {"MIO_UART1_MSR"               ,           0x1180000000C30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     377},
67090         {"MIO_UART0_RBR"               ,           0x1180000000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     378},
67091         {"MIO_UART1_RBR"               ,           0x1180000000C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     378},
67092         {"MIO_UART0_RFL"               ,           0x1180000000A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     379},
67093         {"MIO_UART1_RFL"               ,           0x1180000000E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     379},
67094         {"MIO_UART0_RFW"               ,           0x1180000000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     380},
67095         {"MIO_UART1_RFW"               ,           0x1180000000D30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     380},
67096         {"MIO_UART0_SBCR"              ,           0x1180000000A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     381},
67097         {"MIO_UART1_SBCR"              ,           0x1180000000E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     381},
67098         {"MIO_UART0_SCR"               ,           0x1180000000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     382},
67099         {"MIO_UART1_SCR"               ,           0x1180000000C38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     382},
67100         {"MIO_UART0_SFE"               ,           0x1180000000A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     383},
67101         {"MIO_UART1_SFE"               ,           0x1180000000E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     383},
67102         {"MIO_UART0_SRR"               ,           0x1180000000A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     384},
67103         {"MIO_UART1_SRR"               ,           0x1180000000E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     384},
67104         {"MIO_UART0_SRT"               ,           0x1180000000A38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     385},
67105         {"MIO_UART1_SRT"               ,           0x1180000000E38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     385},
67106         {"MIO_UART0_SRTS"              ,           0x1180000000A18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     386},
67107         {"MIO_UART1_SRTS"              ,           0x1180000000E18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     386},
67108         {"MIO_UART0_STT"               ,           0x1180000000B00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     387},
67109         {"MIO_UART1_STT"               ,           0x1180000000F00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     387},
67110         {"MIO_UART0_TFL"               ,           0x1180000000A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     388},
67111         {"MIO_UART1_TFL"               ,           0x1180000000E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     388},
67112         {"MIO_UART0_TFR"               ,           0x1180000000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     389},
67113         {"MIO_UART1_TFR"               ,           0x1180000000D28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     389},
67114         {"MIO_UART0_THR"               ,           0x1180000000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     390},
67115         {"MIO_UART1_THR"               ,           0x1180000000C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     390},
67116         {"MIO_UART0_USR"               ,           0x1180000000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     391},
67117         {"MIO_UART1_USR"               ,           0x1180000000D38ull,  CVMX_CSR_DB_TYPE_RSL,   64,     391},
67118         {"MIO_UART2_DLH"               ,           0x1180000000488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     392},
67119         {"MIO_UART2_DLL"               ,           0x1180000000480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     393},
67120         {"MIO_UART2_FAR"               ,           0x1180000000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     394},
67121         {"MIO_UART2_FCR"               ,           0x1180000000450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     395},
67122         {"MIO_UART2_HTX"               ,           0x1180000000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     396},
67123         {"MIO_UART2_IER"               ,           0x1180000000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     397},
67124         {"MIO_UART2_IIR"               ,           0x1180000000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     398},
67125         {"MIO_UART2_LCR"               ,           0x1180000000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     399},
67126         {"MIO_UART2_LSR"               ,           0x1180000000428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     400},
67127         {"MIO_UART2_MCR"               ,           0x1180000000420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     401},
67128         {"MIO_UART2_MSR"               ,           0x1180000000430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     402},
67129         {"MIO_UART2_RBR"               ,           0x1180000000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     403},
67130         {"MIO_UART2_RFL"               ,           0x1180000000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     404},
67131         {"MIO_UART2_RFW"               ,           0x1180000000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     405},
67132         {"MIO_UART2_SBCR"              ,           0x1180000000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     406},
67133         {"MIO_UART2_SCR"               ,           0x1180000000438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     407},
67134         {"MIO_UART2_SFE"               ,           0x1180000000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     408},
67135         {"MIO_UART2_SRR"               ,           0x1180000000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     409},
67136         {"MIO_UART2_SRT"               ,           0x1180000000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     410},
67137         {"MIO_UART2_SRTS"              ,           0x1180000000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     411},
67138         {"MIO_UART2_STT"               ,           0x1180000000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     412},
67139         {"MIO_UART2_TFL"               ,           0x1180000000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     413},
67140         {"MIO_UART2_TFR"               ,           0x1180000000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     414},
67141         {"MIO_UART2_THR"               ,           0x1180000000440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     415},
67142         {"MIO_UART2_USR"               ,           0x1180000000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     416},
67143         {"MIX0_BIST"                   ,           0x1070000100078ull,  CVMX_CSR_DB_TYPE_NCB,   64,     417},
67144         {"MIX1_BIST"                   ,           0x1070000100878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     417},
67145         {"MIX0_CTL"                    ,           0x1070000100020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     418},
67146         {"MIX1_CTL"                    ,           0x1070000100820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     418},
67147         {"MIX0_INTENA"                 ,           0x1070000100050ull,  CVMX_CSR_DB_TYPE_NCB,   64,     419},
67148         {"MIX1_INTENA"                 ,           0x1070000100850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     419},
67149         {"MIX0_IRCNT"                  ,           0x1070000100030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     420},
67150         {"MIX1_IRCNT"                  ,           0x1070000100830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     420},
67151         {"MIX0_IRHWM"                  ,           0x1070000100028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     421},
67152         {"MIX1_IRHWM"                  ,           0x1070000100828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     421},
67153         {"MIX0_IRING1"                 ,           0x1070000100010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     422},
67154         {"MIX1_IRING1"                 ,           0x1070000100810ull,  CVMX_CSR_DB_TYPE_NCB,   64,     422},
67155         {"MIX0_IRING2"                 ,           0x1070000100018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     423},
67156         {"MIX1_IRING2"                 ,           0x1070000100818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     423},
67157         {"MIX0_ISR"                    ,           0x1070000100048ull,  CVMX_CSR_DB_TYPE_NCB,   64,     424},
67158         {"MIX1_ISR"                    ,           0x1070000100848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     424},
67159         {"MIX0_ORCNT"                  ,           0x1070000100040ull,  CVMX_CSR_DB_TYPE_NCB,   64,     425},
67160         {"MIX1_ORCNT"                  ,           0x1070000100840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     425},
67161         {"MIX0_ORHWM"                  ,           0x1070000100038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     426},
67162         {"MIX1_ORHWM"                  ,           0x1070000100838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     426},
67163         {"MIX0_ORING1"                 ,           0x1070000100000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     427},
67164         {"MIX1_ORING1"                 ,           0x1070000100800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     427},
67165         {"MIX0_ORING2"                 ,           0x1070000100008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     428},
67166         {"MIX1_ORING2"                 ,           0x1070000100808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     428},
67167         {"MIX0_REMCNT"                 ,           0x1070000100058ull,  CVMX_CSR_DB_TYPE_NCB,   64,     429},
67168         {"MIX1_REMCNT"                 ,           0x1070000100858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     429},
67169         {"NDF_BT_PG_INFO"              ,           0x1070001000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     430},
67170         {"NDF_CMD"                     ,           0x1070001000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     431},
67171         {"NDF_DRBELL"                  ,           0x1070001000030ull,  CVMX_CSR_DB_TYPE_NCB,   64,     432},
67172         {"NDF_ECC_CNT"                 ,           0x1070001000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     433},
67173         {"NDF_INT"                     ,           0x1070001000020ull,  CVMX_CSR_DB_TYPE_NCB,   64,     434},
67174         {"NDF_INT_EN"                  ,           0x1070001000028ull,  CVMX_CSR_DB_TYPE_NCB,   64,     435},
67175         {"NDF_MISC"                    ,           0x1070001000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     436},
67176         {"NDF_ST_REG"                  ,           0x1070001000038ull,  CVMX_CSR_DB_TYPE_NCB,   64,     437},
67177         {"NPEI_BAR1_INDEX0"            ,           0x11F0000008000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67178         {"NPEI_BAR1_INDEX1"            ,           0x11F0000008010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67179         {"NPEI_BAR1_INDEX2"            ,           0x11F0000008020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67180         {"NPEI_BAR1_INDEX3"            ,           0x11F0000008030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67181         {"NPEI_BAR1_INDEX4"            ,           0x11F0000008040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67182         {"NPEI_BAR1_INDEX5"            ,           0x11F0000008050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67183         {"NPEI_BAR1_INDEX6"            ,           0x11F0000008060ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67184         {"NPEI_BAR1_INDEX7"            ,           0x11F0000008070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67185         {"NPEI_BAR1_INDEX8"            ,           0x11F0000008080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67186         {"NPEI_BAR1_INDEX9"            ,           0x11F0000008090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67187         {"NPEI_BAR1_INDEX10"           ,           0x11F00000080A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67188         {"NPEI_BAR1_INDEX11"           ,           0x11F00000080B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67189         {"NPEI_BAR1_INDEX12"           ,           0x11F00000080C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67190         {"NPEI_BAR1_INDEX13"           ,           0x11F00000080D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67191         {"NPEI_BAR1_INDEX14"           ,           0x11F00000080E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67192         {"NPEI_BAR1_INDEX15"           ,           0x11F00000080F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67193         {"NPEI_BAR1_INDEX16"           ,           0x11F0000008100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67194         {"NPEI_BAR1_INDEX17"           ,           0x11F0000008110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67195         {"NPEI_BAR1_INDEX18"           ,           0x11F0000008120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67196         {"NPEI_BAR1_INDEX19"           ,           0x11F0000008130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67197         {"NPEI_BAR1_INDEX20"           ,           0x11F0000008140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67198         {"NPEI_BAR1_INDEX21"           ,           0x11F0000008150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67199         {"NPEI_BAR1_INDEX22"           ,           0x11F0000008160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67200         {"NPEI_BAR1_INDEX23"           ,           0x11F0000008170ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67201         {"NPEI_BAR1_INDEX24"           ,           0x11F0000008180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67202         {"NPEI_BAR1_INDEX25"           ,           0x11F0000008190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67203         {"NPEI_BAR1_INDEX26"           ,           0x11F00000081A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67204         {"NPEI_BAR1_INDEX27"           ,           0x11F00000081B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67205         {"NPEI_BAR1_INDEX28"           ,           0x11F00000081C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67206         {"NPEI_BAR1_INDEX29"           ,           0x11F00000081D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67207         {"NPEI_BAR1_INDEX30"           ,           0x11F00000081E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67208         {"NPEI_BAR1_INDEX31"           ,           0x11F00000081F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     438},
67209         {"NPEI_BIST_STATUS"            ,           0x11F0000008580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     439},
67210         {"NPEI_BIST_STATUS2"           ,           0x11F0000008680ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     440},
67211         {"NPEI_CTL_PORT0"              ,           0x11F0000008250ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     441},
67212         {"NPEI_CTL_PORT1"              ,           0x11F0000008260ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     442},
67213         {"NPEI_CTL_STATUS"             ,           0x11F0000008570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     443},
67214         {"NPEI_CTL_STATUS2"            ,           0x11F000000BC00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     444},
67215         {"NPEI_DATA_OUT_CNT"           ,           0x11F00000085F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     445},
67216         {"NPEI_DBG_DATA"               ,           0x11F0000008510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     446},
67217         {"NPEI_DBG_SELECT"             ,           0x11F0000008500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     447},
67218         {"NPEI_DMA0_COUNTS"            ,           0x11F0000008450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     448},
67219         {"NPEI_DMA1_COUNTS"            ,           0x11F0000008460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     448},
67220         {"NPEI_DMA2_COUNTS"            ,           0x11F0000008470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     448},
67221         {"NPEI_DMA3_COUNTS"            ,           0x11F0000008480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     448},
67222         {"NPEI_DMA4_COUNTS"            ,           0x11F0000008490ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     448},
67223         {"NPEI_DMA0_DBELL"             ,           0x11F00000083B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     449},
67224         {"NPEI_DMA1_DBELL"             ,           0x11F00000083C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     449},
67225         {"NPEI_DMA2_DBELL"             ,           0x11F00000083D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     449},
67226         {"NPEI_DMA3_DBELL"             ,           0x11F00000083E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     449},
67227         {"NPEI_DMA4_DBELL"             ,           0x11F00000083F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      32,     449},
67228         {"NPEI_DMA0_IBUFF_SADDR"       ,           0x11F0000008400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     450},
67229         {"NPEI_DMA1_IBUFF_SADDR"       ,           0x11F0000008410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     450},
67230         {"NPEI_DMA2_IBUFF_SADDR"       ,           0x11F0000008420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     450},
67231         {"NPEI_DMA3_IBUFF_SADDR"       ,           0x11F0000008430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     450},
67232         {"NPEI_DMA4_IBUFF_SADDR"       ,           0x11F0000008440ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     450},
67233         {"NPEI_DMA0_NADDR"             ,           0x11F00000084A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     451},
67234         {"NPEI_DMA1_NADDR"             ,           0x11F00000084B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     451},
67235         {"NPEI_DMA2_NADDR"             ,           0x11F00000084C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     451},
67236         {"NPEI_DMA3_NADDR"             ,           0x11F00000084D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     451},
67237         {"NPEI_DMA4_NADDR"             ,           0x11F00000084E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     451},
67238         {"NPEI_DMA0_INT_LEVEL"         ,           0x11F00000085C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     452},
67239         {"NPEI_DMA1_INT_LEVEL"         ,           0x11F00000085D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     453},
67240         {"NPEI_DMA_CNTS"               ,           0x11F00000085E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     454},
67241         {"NPEI_DMA_CONTROL"            ,           0x11F00000083A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     455},
67242         {"NPEI_DMA_PCIE_REQ_NUM"       ,           0x11F00000085B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     456},
67243         {"NPEI_DMA_STATE1"             ,           0x11F00000086C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     457},
67244         {"NPEI_DMA_STATE2"             ,           0x11F00000086D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     458},
67245         {"NPEI_INT_A_ENB"              ,           0x11F0000008560ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     459},
67246         {"NPEI_INT_A_ENB2"             ,           0x11F000000BCE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     460},
67247         {"NPEI_INT_A_SUM"              ,           0x11F0000008550ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     461},
67248         {"NPEI_INT_ENB"                ,           0x11F0000008540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     462},
67249         {"NPEI_INT_ENB2"               ,           0x11F000000BCD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     463},
67250         {"NPEI_INT_INFO"               ,           0x11F0000008590ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     464},
67251         {"NPEI_INT_SUM"                ,           0x11F0000008530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     465},
67252         {"NPEI_INT_SUM2"               ,           0x11F000000BCC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     466},
67253         {"NPEI_LAST_WIN_RDATA0"        ,           0x11F0000008600ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     467},
67254         {"NPEI_LAST_WIN_RDATA1"        ,           0x11F0000008610ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     468},
67255         {"NPEI_MEM_ACCESS_CTL"         ,           0x11F00000084F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     469},
67256         {"NPEI_MEM_ACCESS_SUBID12"     ,           0x11F0000008280ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67257         {"NPEI_MEM_ACCESS_SUBID13"     ,           0x11F0000008290ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67258         {"NPEI_MEM_ACCESS_SUBID14"     ,           0x11F00000082A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67259         {"NPEI_MEM_ACCESS_SUBID15"     ,           0x11F00000082B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67260         {"NPEI_MEM_ACCESS_SUBID16"     ,           0x11F00000082C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67261         {"NPEI_MEM_ACCESS_SUBID17"     ,           0x11F00000082D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67262         {"NPEI_MEM_ACCESS_SUBID18"     ,           0x11F00000082E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67263         {"NPEI_MEM_ACCESS_SUBID19"     ,           0x11F00000082F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67264         {"NPEI_MEM_ACCESS_SUBID20"     ,           0x11F0000008300ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67265         {"NPEI_MEM_ACCESS_SUBID21"     ,           0x11F0000008310ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67266         {"NPEI_MEM_ACCESS_SUBID22"     ,           0x11F0000008320ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67267         {"NPEI_MEM_ACCESS_SUBID23"     ,           0x11F0000008330ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67268         {"NPEI_MEM_ACCESS_SUBID24"     ,           0x11F0000008340ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67269         {"NPEI_MEM_ACCESS_SUBID25"     ,           0x11F0000008350ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67270         {"NPEI_MEM_ACCESS_SUBID26"     ,           0x11F0000008360ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67271         {"NPEI_MEM_ACCESS_SUBID27"     ,           0x11F0000008370ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     470},
67272         {"NPEI_MSI_ENB0"               ,           0x11F000000BC50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     471},
67273         {"NPEI_MSI_ENB1"               ,           0x11F000000BC60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     472},
67274         {"NPEI_MSI_ENB2"               ,           0x11F000000BC70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     473},
67275         {"NPEI_MSI_ENB3"               ,           0x11F000000BC80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     474},
67276         {"NPEI_MSI_RCV0"               ,           0x11F000000BC10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     475},
67277         {"NPEI_MSI_RCV1"               ,           0x11F000000BC20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     476},
67278         {"NPEI_MSI_RCV2"               ,           0x11F000000BC30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     477},
67279         {"NPEI_MSI_RCV3"               ,           0x11F000000BC40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     478},
67280         {"NPEI_MSI_RD_MAP"             ,           0x11F000000BCA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     479},
67281         {"NPEI_MSI_W1C_ENB0"           ,           0x11F000000BCF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     480},
67282         {"NPEI_MSI_W1C_ENB1"           ,           0x11F000000BD00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     481},
67283         {"NPEI_MSI_W1C_ENB2"           ,           0x11F000000BD10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     482},
67284         {"NPEI_MSI_W1C_ENB3"           ,           0x11F000000BD20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     483},
67285         {"NPEI_MSI_W1S_ENB0"           ,           0x11F000000BD30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     484},
67286         {"NPEI_MSI_W1S_ENB1"           ,           0x11F000000BD40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     485},
67287         {"NPEI_MSI_W1S_ENB2"           ,           0x11F000000BD50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     486},
67288         {"NPEI_MSI_W1S_ENB3"           ,           0x11F000000BD60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     487},
67289         {"NPEI_MSI_WR_MAP"             ,           0x11F000000BC90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     488},
67290         {"NPEI_PCIE_CREDIT_CNT"        ,           0x11F000000BD70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     489},
67291         {"NPEI_PCIE_MSI_RCV"           ,           0x11F000000BCB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     490},
67292         {"NPEI_PCIE_MSI_RCV_B1"        ,           0x11F0000008650ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     491},
67293         {"NPEI_PCIE_MSI_RCV_B2"        ,           0x11F0000008660ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     492},
67294         {"NPEI_PCIE_MSI_RCV_B3"        ,           0x11F0000008670ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     493},
67295         {"NPEI_PKT0_CNTS"              ,           0x11F000000A400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67296         {"NPEI_PKT1_CNTS"              ,           0x11F000000A410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67297         {"NPEI_PKT2_CNTS"              ,           0x11F000000A420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67298         {"NPEI_PKT3_CNTS"              ,           0x11F000000A430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67299         {"NPEI_PKT4_CNTS"              ,           0x11F000000A440ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67300         {"NPEI_PKT5_CNTS"              ,           0x11F000000A450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67301         {"NPEI_PKT6_CNTS"              ,           0x11F000000A460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67302         {"NPEI_PKT7_CNTS"              ,           0x11F000000A470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67303         {"NPEI_PKT8_CNTS"              ,           0x11F000000A480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67304         {"NPEI_PKT9_CNTS"              ,           0x11F000000A490ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67305         {"NPEI_PKT10_CNTS"             ,           0x11F000000A4A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67306         {"NPEI_PKT11_CNTS"             ,           0x11F000000A4B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67307         {"NPEI_PKT12_CNTS"             ,           0x11F000000A4C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67308         {"NPEI_PKT13_CNTS"             ,           0x11F000000A4D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67309         {"NPEI_PKT14_CNTS"             ,           0x11F000000A4E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67310         {"NPEI_PKT15_CNTS"             ,           0x11F000000A4F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67311         {"NPEI_PKT16_CNTS"             ,           0x11F000000A500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67312         {"NPEI_PKT17_CNTS"             ,           0x11F000000A510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67313         {"NPEI_PKT18_CNTS"             ,           0x11F000000A520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67314         {"NPEI_PKT19_CNTS"             ,           0x11F000000A530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67315         {"NPEI_PKT20_CNTS"             ,           0x11F000000A540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67316         {"NPEI_PKT21_CNTS"             ,           0x11F000000A550ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67317         {"NPEI_PKT22_CNTS"             ,           0x11F000000A560ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67318         {"NPEI_PKT23_CNTS"             ,           0x11F000000A570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67319         {"NPEI_PKT24_CNTS"             ,           0x11F000000A580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67320         {"NPEI_PKT25_CNTS"             ,           0x11F000000A590ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67321         {"NPEI_PKT26_CNTS"             ,           0x11F000000A5A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67322         {"NPEI_PKT27_CNTS"             ,           0x11F000000A5B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67323         {"NPEI_PKT28_CNTS"             ,           0x11F000000A5C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67324         {"NPEI_PKT29_CNTS"             ,           0x11F000000A5D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67325         {"NPEI_PKT30_CNTS"             ,           0x11F000000A5E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67326         {"NPEI_PKT31_CNTS"             ,           0x11F000000A5F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     494},
67327         {"NPEI_PKT0_IN_BP"             ,           0x11F000000B800ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67328         {"NPEI_PKT1_IN_BP"             ,           0x11F000000B810ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67329         {"NPEI_PKT2_IN_BP"             ,           0x11F000000B820ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67330         {"NPEI_PKT3_IN_BP"             ,           0x11F000000B830ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67331         {"NPEI_PKT4_IN_BP"             ,           0x11F000000B840ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67332         {"NPEI_PKT5_IN_BP"             ,           0x11F000000B850ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67333         {"NPEI_PKT6_IN_BP"             ,           0x11F000000B860ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67334         {"NPEI_PKT7_IN_BP"             ,           0x11F000000B870ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67335         {"NPEI_PKT8_IN_BP"             ,           0x11F000000B880ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67336         {"NPEI_PKT9_IN_BP"             ,           0x11F000000B890ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67337         {"NPEI_PKT10_IN_BP"            ,           0x11F000000B8A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67338         {"NPEI_PKT11_IN_BP"            ,           0x11F000000B8B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67339         {"NPEI_PKT12_IN_BP"            ,           0x11F000000B8C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67340         {"NPEI_PKT13_IN_BP"            ,           0x11F000000B8D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67341         {"NPEI_PKT14_IN_BP"            ,           0x11F000000B8E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67342         {"NPEI_PKT15_IN_BP"            ,           0x11F000000B8F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67343         {"NPEI_PKT16_IN_BP"            ,           0x11F000000B900ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67344         {"NPEI_PKT17_IN_BP"            ,           0x11F000000B910ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67345         {"NPEI_PKT18_IN_BP"            ,           0x11F000000B920ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67346         {"NPEI_PKT19_IN_BP"            ,           0x11F000000B930ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67347         {"NPEI_PKT20_IN_BP"            ,           0x11F000000B940ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67348         {"NPEI_PKT21_IN_BP"            ,           0x11F000000B950ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67349         {"NPEI_PKT22_IN_BP"            ,           0x11F000000B960ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67350         {"NPEI_PKT23_IN_BP"            ,           0x11F000000B970ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67351         {"NPEI_PKT24_IN_BP"            ,           0x11F000000B980ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67352         {"NPEI_PKT25_IN_BP"            ,           0x11F000000B990ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67353         {"NPEI_PKT26_IN_BP"            ,           0x11F000000B9A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67354         {"NPEI_PKT27_IN_BP"            ,           0x11F000000B9B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67355         {"NPEI_PKT28_IN_BP"            ,           0x11F000000B9C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67356         {"NPEI_PKT29_IN_BP"            ,           0x11F000000B9D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67357         {"NPEI_PKT30_IN_BP"            ,           0x11F000000B9E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67358         {"NPEI_PKT31_IN_BP"            ,           0x11F000000B9F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     495},
67359         {"NPEI_PKT0_INSTR_BADDR"       ,           0x11F000000A800ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67360         {"NPEI_PKT1_INSTR_BADDR"       ,           0x11F000000A810ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67361         {"NPEI_PKT2_INSTR_BADDR"       ,           0x11F000000A820ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67362         {"NPEI_PKT3_INSTR_BADDR"       ,           0x11F000000A830ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67363         {"NPEI_PKT4_INSTR_BADDR"       ,           0x11F000000A840ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67364         {"NPEI_PKT5_INSTR_BADDR"       ,           0x11F000000A850ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67365         {"NPEI_PKT6_INSTR_BADDR"       ,           0x11F000000A860ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67366         {"NPEI_PKT7_INSTR_BADDR"       ,           0x11F000000A870ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67367         {"NPEI_PKT8_INSTR_BADDR"       ,           0x11F000000A880ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67368         {"NPEI_PKT9_INSTR_BADDR"       ,           0x11F000000A890ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67369         {"NPEI_PKT10_INSTR_BADDR"      ,           0x11F000000A8A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67370         {"NPEI_PKT11_INSTR_BADDR"      ,           0x11F000000A8B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67371         {"NPEI_PKT12_INSTR_BADDR"      ,           0x11F000000A8C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67372         {"NPEI_PKT13_INSTR_BADDR"      ,           0x11F000000A8D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67373         {"NPEI_PKT14_INSTR_BADDR"      ,           0x11F000000A8E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67374         {"NPEI_PKT15_INSTR_BADDR"      ,           0x11F000000A8F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67375         {"NPEI_PKT16_INSTR_BADDR"      ,           0x11F000000A900ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67376         {"NPEI_PKT17_INSTR_BADDR"      ,           0x11F000000A910ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67377         {"NPEI_PKT18_INSTR_BADDR"      ,           0x11F000000A920ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67378         {"NPEI_PKT19_INSTR_BADDR"      ,           0x11F000000A930ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67379         {"NPEI_PKT20_INSTR_BADDR"      ,           0x11F000000A940ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67380         {"NPEI_PKT21_INSTR_BADDR"      ,           0x11F000000A950ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67381         {"NPEI_PKT22_INSTR_BADDR"      ,           0x11F000000A960ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67382         {"NPEI_PKT23_INSTR_BADDR"      ,           0x11F000000A970ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67383         {"NPEI_PKT24_INSTR_BADDR"      ,           0x11F000000A980ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67384         {"NPEI_PKT25_INSTR_BADDR"      ,           0x11F000000A990ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67385         {"NPEI_PKT26_INSTR_BADDR"      ,           0x11F000000A9A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67386         {"NPEI_PKT27_INSTR_BADDR"      ,           0x11F000000A9B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67387         {"NPEI_PKT28_INSTR_BADDR"      ,           0x11F000000A9C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67388         {"NPEI_PKT29_INSTR_BADDR"      ,           0x11F000000A9D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67389         {"NPEI_PKT30_INSTR_BADDR"      ,           0x11F000000A9E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67390         {"NPEI_PKT31_INSTR_BADDR"      ,           0x11F000000A9F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     496},
67391         {"NPEI_PKT0_INSTR_BAOFF_DBELL" ,           0x11F000000AC00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67392         {"NPEI_PKT1_INSTR_BAOFF_DBELL" ,           0x11F000000AC10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67393         {"NPEI_PKT2_INSTR_BAOFF_DBELL" ,           0x11F000000AC20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67394         {"NPEI_PKT3_INSTR_BAOFF_DBELL" ,           0x11F000000AC30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67395         {"NPEI_PKT4_INSTR_BAOFF_DBELL" ,           0x11F000000AC40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67396         {"NPEI_PKT5_INSTR_BAOFF_DBELL" ,           0x11F000000AC50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67397         {"NPEI_PKT6_INSTR_BAOFF_DBELL" ,           0x11F000000AC60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67398         {"NPEI_PKT7_INSTR_BAOFF_DBELL" ,           0x11F000000AC70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67399         {"NPEI_PKT8_INSTR_BAOFF_DBELL" ,           0x11F000000AC80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67400         {"NPEI_PKT9_INSTR_BAOFF_DBELL" ,           0x11F000000AC90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67401         {"NPEI_PKT10_INSTR_BAOFF_DBELL",           0x11F000000ACA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67402         {"NPEI_PKT11_INSTR_BAOFF_DBELL",           0x11F000000ACB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67403         {"NPEI_PKT12_INSTR_BAOFF_DBELL",           0x11F000000ACC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67404         {"NPEI_PKT13_INSTR_BAOFF_DBELL",           0x11F000000ACD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67405         {"NPEI_PKT14_INSTR_BAOFF_DBELL",           0x11F000000ACE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67406         {"NPEI_PKT15_INSTR_BAOFF_DBELL",           0x11F000000ACF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67407         {"NPEI_PKT16_INSTR_BAOFF_DBELL",           0x11F000000AD00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67408         {"NPEI_PKT17_INSTR_BAOFF_DBELL",           0x11F000000AD10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67409         {"NPEI_PKT18_INSTR_BAOFF_DBELL",           0x11F000000AD20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67410         {"NPEI_PKT19_INSTR_BAOFF_DBELL",           0x11F000000AD30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67411         {"NPEI_PKT20_INSTR_BAOFF_DBELL",           0x11F000000AD40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67412         {"NPEI_PKT21_INSTR_BAOFF_DBELL",           0x11F000000AD50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67413         {"NPEI_PKT22_INSTR_BAOFF_DBELL",           0x11F000000AD60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67414         {"NPEI_PKT23_INSTR_BAOFF_DBELL",           0x11F000000AD70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67415         {"NPEI_PKT24_INSTR_BAOFF_DBELL",           0x11F000000AD80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67416         {"NPEI_PKT25_INSTR_BAOFF_DBELL",           0x11F000000AD90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67417         {"NPEI_PKT26_INSTR_BAOFF_DBELL",           0x11F000000ADA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67418         {"NPEI_PKT27_INSTR_BAOFF_DBELL",           0x11F000000ADB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67419         {"NPEI_PKT28_INSTR_BAOFF_DBELL",           0x11F000000ADC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67420         {"NPEI_PKT29_INSTR_BAOFF_DBELL",           0x11F000000ADD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67421         {"NPEI_PKT30_INSTR_BAOFF_DBELL",           0x11F000000ADE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67422         {"NPEI_PKT31_INSTR_BAOFF_DBELL",           0x11F000000ADF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     497},
67423         {"NPEI_PKT0_INSTR_FIFO_RSIZE"  ,           0x11F000000B000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67424         {"NPEI_PKT1_INSTR_FIFO_RSIZE"  ,           0x11F000000B010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67425         {"NPEI_PKT2_INSTR_FIFO_RSIZE"  ,           0x11F000000B020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67426         {"NPEI_PKT3_INSTR_FIFO_RSIZE"  ,           0x11F000000B030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67427         {"NPEI_PKT4_INSTR_FIFO_RSIZE"  ,           0x11F000000B040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67428         {"NPEI_PKT5_INSTR_FIFO_RSIZE"  ,           0x11F000000B050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67429         {"NPEI_PKT6_INSTR_FIFO_RSIZE"  ,           0x11F000000B060ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67430         {"NPEI_PKT7_INSTR_FIFO_RSIZE"  ,           0x11F000000B070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67431         {"NPEI_PKT8_INSTR_FIFO_RSIZE"  ,           0x11F000000B080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67432         {"NPEI_PKT9_INSTR_FIFO_RSIZE"  ,           0x11F000000B090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67433         {"NPEI_PKT10_INSTR_FIFO_RSIZE" ,           0x11F000000B0A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67434         {"NPEI_PKT11_INSTR_FIFO_RSIZE" ,           0x11F000000B0B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67435         {"NPEI_PKT12_INSTR_FIFO_RSIZE" ,           0x11F000000B0C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67436         {"NPEI_PKT13_INSTR_FIFO_RSIZE" ,           0x11F000000B0D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67437         {"NPEI_PKT14_INSTR_FIFO_RSIZE" ,           0x11F000000B0E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67438         {"NPEI_PKT15_INSTR_FIFO_RSIZE" ,           0x11F000000B0F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67439         {"NPEI_PKT16_INSTR_FIFO_RSIZE" ,           0x11F000000B100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67440         {"NPEI_PKT17_INSTR_FIFO_RSIZE" ,           0x11F000000B110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67441         {"NPEI_PKT18_INSTR_FIFO_RSIZE" ,           0x11F000000B120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67442         {"NPEI_PKT19_INSTR_FIFO_RSIZE" ,           0x11F000000B130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67443         {"NPEI_PKT20_INSTR_FIFO_RSIZE" ,           0x11F000000B140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67444         {"NPEI_PKT21_INSTR_FIFO_RSIZE" ,           0x11F000000B150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67445         {"NPEI_PKT22_INSTR_FIFO_RSIZE" ,           0x11F000000B160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67446         {"NPEI_PKT23_INSTR_FIFO_RSIZE" ,           0x11F000000B170ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67447         {"NPEI_PKT24_INSTR_FIFO_RSIZE" ,           0x11F000000B180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67448         {"NPEI_PKT25_INSTR_FIFO_RSIZE" ,           0x11F000000B190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67449         {"NPEI_PKT26_INSTR_FIFO_RSIZE" ,           0x11F000000B1A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67450         {"NPEI_PKT27_INSTR_FIFO_RSIZE" ,           0x11F000000B1B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67451         {"NPEI_PKT28_INSTR_FIFO_RSIZE" ,           0x11F000000B1C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67452         {"NPEI_PKT29_INSTR_FIFO_RSIZE" ,           0x11F000000B1D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67453         {"NPEI_PKT30_INSTR_FIFO_RSIZE" ,           0x11F000000B1E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67454         {"NPEI_PKT31_INSTR_FIFO_RSIZE" ,           0x11F000000B1F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     498},
67455         {"NPEI_PKT0_INSTR_HEADER"      ,           0x11F000000B400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67456         {"NPEI_PKT1_INSTR_HEADER"      ,           0x11F000000B410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67457         {"NPEI_PKT2_INSTR_HEADER"      ,           0x11F000000B420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67458         {"NPEI_PKT3_INSTR_HEADER"      ,           0x11F000000B430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67459         {"NPEI_PKT4_INSTR_HEADER"      ,           0x11F000000B440ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67460         {"NPEI_PKT5_INSTR_HEADER"      ,           0x11F000000B450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67461         {"NPEI_PKT6_INSTR_HEADER"      ,           0x11F000000B460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67462         {"NPEI_PKT7_INSTR_HEADER"      ,           0x11F000000B470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67463         {"NPEI_PKT8_INSTR_HEADER"      ,           0x11F000000B480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67464         {"NPEI_PKT9_INSTR_HEADER"      ,           0x11F000000B490ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67465         {"NPEI_PKT10_INSTR_HEADER"     ,           0x11F000000B4A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67466         {"NPEI_PKT11_INSTR_HEADER"     ,           0x11F000000B4B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67467         {"NPEI_PKT12_INSTR_HEADER"     ,           0x11F000000B4C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67468         {"NPEI_PKT13_INSTR_HEADER"     ,           0x11F000000B4D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67469         {"NPEI_PKT14_INSTR_HEADER"     ,           0x11F000000B4E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67470         {"NPEI_PKT15_INSTR_HEADER"     ,           0x11F000000B4F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67471         {"NPEI_PKT16_INSTR_HEADER"     ,           0x11F000000B500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67472         {"NPEI_PKT17_INSTR_HEADER"     ,           0x11F000000B510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67473         {"NPEI_PKT18_INSTR_HEADER"     ,           0x11F000000B520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67474         {"NPEI_PKT19_INSTR_HEADER"     ,           0x11F000000B530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67475         {"NPEI_PKT20_INSTR_HEADER"     ,           0x11F000000B540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67476         {"NPEI_PKT21_INSTR_HEADER"     ,           0x11F000000B550ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67477         {"NPEI_PKT22_INSTR_HEADER"     ,           0x11F000000B560ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67478         {"NPEI_PKT23_INSTR_HEADER"     ,           0x11F000000B570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67479         {"NPEI_PKT24_INSTR_HEADER"     ,           0x11F000000B580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67480         {"NPEI_PKT25_INSTR_HEADER"     ,           0x11F000000B590ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67481         {"NPEI_PKT26_INSTR_HEADER"     ,           0x11F000000B5A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67482         {"NPEI_PKT27_INSTR_HEADER"     ,           0x11F000000B5B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67483         {"NPEI_PKT28_INSTR_HEADER"     ,           0x11F000000B5C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67484         {"NPEI_PKT29_INSTR_HEADER"     ,           0x11F000000B5D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67485         {"NPEI_PKT30_INSTR_HEADER"     ,           0x11F000000B5E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67486         {"NPEI_PKT31_INSTR_HEADER"     ,           0x11F000000B5F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     499},
67487         {"NPEI_PKT0_SLIST_BADDR"       ,           0x11F0000009400ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67488         {"NPEI_PKT1_SLIST_BADDR"       ,           0x11F0000009410ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67489         {"NPEI_PKT2_SLIST_BADDR"       ,           0x11F0000009420ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67490         {"NPEI_PKT3_SLIST_BADDR"       ,           0x11F0000009430ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67491         {"NPEI_PKT4_SLIST_BADDR"       ,           0x11F0000009440ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67492         {"NPEI_PKT5_SLIST_BADDR"       ,           0x11F0000009450ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67493         {"NPEI_PKT6_SLIST_BADDR"       ,           0x11F0000009460ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67494         {"NPEI_PKT7_SLIST_BADDR"       ,           0x11F0000009470ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67495         {"NPEI_PKT8_SLIST_BADDR"       ,           0x11F0000009480ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67496         {"NPEI_PKT9_SLIST_BADDR"       ,           0x11F0000009490ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67497         {"NPEI_PKT10_SLIST_BADDR"      ,           0x11F00000094A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67498         {"NPEI_PKT11_SLIST_BADDR"      ,           0x11F00000094B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67499         {"NPEI_PKT12_SLIST_BADDR"      ,           0x11F00000094C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67500         {"NPEI_PKT13_SLIST_BADDR"      ,           0x11F00000094D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67501         {"NPEI_PKT14_SLIST_BADDR"      ,           0x11F00000094E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67502         {"NPEI_PKT15_SLIST_BADDR"      ,           0x11F00000094F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67503         {"NPEI_PKT16_SLIST_BADDR"      ,           0x11F0000009500ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67504         {"NPEI_PKT17_SLIST_BADDR"      ,           0x11F0000009510ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67505         {"NPEI_PKT18_SLIST_BADDR"      ,           0x11F0000009520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67506         {"NPEI_PKT19_SLIST_BADDR"      ,           0x11F0000009530ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67507         {"NPEI_PKT20_SLIST_BADDR"      ,           0x11F0000009540ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67508         {"NPEI_PKT21_SLIST_BADDR"      ,           0x11F0000009550ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67509         {"NPEI_PKT22_SLIST_BADDR"      ,           0x11F0000009560ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67510         {"NPEI_PKT23_SLIST_BADDR"      ,           0x11F0000009570ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67511         {"NPEI_PKT24_SLIST_BADDR"      ,           0x11F0000009580ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67512         {"NPEI_PKT25_SLIST_BADDR"      ,           0x11F0000009590ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67513         {"NPEI_PKT26_SLIST_BADDR"      ,           0x11F00000095A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67514         {"NPEI_PKT27_SLIST_BADDR"      ,           0x11F00000095B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67515         {"NPEI_PKT28_SLIST_BADDR"      ,           0x11F00000095C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67516         {"NPEI_PKT29_SLIST_BADDR"      ,           0x11F00000095D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67517         {"NPEI_PKT30_SLIST_BADDR"      ,           0x11F00000095E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67518         {"NPEI_PKT31_SLIST_BADDR"      ,           0x11F00000095F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     500},
67519         {"NPEI_PKT0_SLIST_BAOFF_DBELL" ,           0x11F0000009800ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67520         {"NPEI_PKT1_SLIST_BAOFF_DBELL" ,           0x11F0000009810ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67521         {"NPEI_PKT2_SLIST_BAOFF_DBELL" ,           0x11F0000009820ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67522         {"NPEI_PKT3_SLIST_BAOFF_DBELL" ,           0x11F0000009830ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67523         {"NPEI_PKT4_SLIST_BAOFF_DBELL" ,           0x11F0000009840ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67524         {"NPEI_PKT5_SLIST_BAOFF_DBELL" ,           0x11F0000009850ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67525         {"NPEI_PKT6_SLIST_BAOFF_DBELL" ,           0x11F0000009860ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67526         {"NPEI_PKT7_SLIST_BAOFF_DBELL" ,           0x11F0000009870ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67527         {"NPEI_PKT8_SLIST_BAOFF_DBELL" ,           0x11F0000009880ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67528         {"NPEI_PKT9_SLIST_BAOFF_DBELL" ,           0x11F0000009890ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67529         {"NPEI_PKT10_SLIST_BAOFF_DBELL",           0x11F00000098A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67530         {"NPEI_PKT11_SLIST_BAOFF_DBELL",           0x11F00000098B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67531         {"NPEI_PKT12_SLIST_BAOFF_DBELL",           0x11F00000098C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67532         {"NPEI_PKT13_SLIST_BAOFF_DBELL",           0x11F00000098D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67533         {"NPEI_PKT14_SLIST_BAOFF_DBELL",           0x11F00000098E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67534         {"NPEI_PKT15_SLIST_BAOFF_DBELL",           0x11F00000098F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67535         {"NPEI_PKT16_SLIST_BAOFF_DBELL",           0x11F0000009900ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67536         {"NPEI_PKT17_SLIST_BAOFF_DBELL",           0x11F0000009910ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67537         {"NPEI_PKT18_SLIST_BAOFF_DBELL",           0x11F0000009920ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67538         {"NPEI_PKT19_SLIST_BAOFF_DBELL",           0x11F0000009930ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67539         {"NPEI_PKT20_SLIST_BAOFF_DBELL",           0x11F0000009940ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67540         {"NPEI_PKT21_SLIST_BAOFF_DBELL",           0x11F0000009950ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67541         {"NPEI_PKT22_SLIST_BAOFF_DBELL",           0x11F0000009960ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67542         {"NPEI_PKT23_SLIST_BAOFF_DBELL",           0x11F0000009970ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67543         {"NPEI_PKT24_SLIST_BAOFF_DBELL",           0x11F0000009980ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67544         {"NPEI_PKT25_SLIST_BAOFF_DBELL",           0x11F0000009990ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67545         {"NPEI_PKT26_SLIST_BAOFF_DBELL",           0x11F00000099A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67546         {"NPEI_PKT27_SLIST_BAOFF_DBELL",           0x11F00000099B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67547         {"NPEI_PKT28_SLIST_BAOFF_DBELL",           0x11F00000099C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67548         {"NPEI_PKT29_SLIST_BAOFF_DBELL",           0x11F00000099D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67549         {"NPEI_PKT30_SLIST_BAOFF_DBELL",           0x11F00000099E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67550         {"NPEI_PKT31_SLIST_BAOFF_DBELL",           0x11F00000099F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     501},
67551         {"NPEI_PKT0_SLIST_FIFO_RSIZE"  ,           0x11F0000009C00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67552         {"NPEI_PKT1_SLIST_FIFO_RSIZE"  ,           0x11F0000009C10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67553         {"NPEI_PKT2_SLIST_FIFO_RSIZE"  ,           0x11F0000009C20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67554         {"NPEI_PKT3_SLIST_FIFO_RSIZE"  ,           0x11F0000009C30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67555         {"NPEI_PKT4_SLIST_FIFO_RSIZE"  ,           0x11F0000009C40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67556         {"NPEI_PKT5_SLIST_FIFO_RSIZE"  ,           0x11F0000009C50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67557         {"NPEI_PKT6_SLIST_FIFO_RSIZE"  ,           0x11F0000009C60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67558         {"NPEI_PKT7_SLIST_FIFO_RSIZE"  ,           0x11F0000009C70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67559         {"NPEI_PKT8_SLIST_FIFO_RSIZE"  ,           0x11F0000009C80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67560         {"NPEI_PKT9_SLIST_FIFO_RSIZE"  ,           0x11F0000009C90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67561         {"NPEI_PKT10_SLIST_FIFO_RSIZE" ,           0x11F0000009CA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67562         {"NPEI_PKT11_SLIST_FIFO_RSIZE" ,           0x11F0000009CB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67563         {"NPEI_PKT12_SLIST_FIFO_RSIZE" ,           0x11F0000009CC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67564         {"NPEI_PKT13_SLIST_FIFO_RSIZE" ,           0x11F0000009CD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67565         {"NPEI_PKT14_SLIST_FIFO_RSIZE" ,           0x11F0000009CE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67566         {"NPEI_PKT15_SLIST_FIFO_RSIZE" ,           0x11F0000009CF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67567         {"NPEI_PKT16_SLIST_FIFO_RSIZE" ,           0x11F0000009D00ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67568         {"NPEI_PKT17_SLIST_FIFO_RSIZE" ,           0x11F0000009D10ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67569         {"NPEI_PKT18_SLIST_FIFO_RSIZE" ,           0x11F0000009D20ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67570         {"NPEI_PKT19_SLIST_FIFO_RSIZE" ,           0x11F0000009D30ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67571         {"NPEI_PKT20_SLIST_FIFO_RSIZE" ,           0x11F0000009D40ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67572         {"NPEI_PKT21_SLIST_FIFO_RSIZE" ,           0x11F0000009D50ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67573         {"NPEI_PKT22_SLIST_FIFO_RSIZE" ,           0x11F0000009D60ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67574         {"NPEI_PKT23_SLIST_FIFO_RSIZE" ,           0x11F0000009D70ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67575         {"NPEI_PKT24_SLIST_FIFO_RSIZE" ,           0x11F0000009D80ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67576         {"NPEI_PKT25_SLIST_FIFO_RSIZE" ,           0x11F0000009D90ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67577         {"NPEI_PKT26_SLIST_FIFO_RSIZE" ,           0x11F0000009DA0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67578         {"NPEI_PKT27_SLIST_FIFO_RSIZE" ,           0x11F0000009DB0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67579         {"NPEI_PKT28_SLIST_FIFO_RSIZE" ,           0x11F0000009DC0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67580         {"NPEI_PKT29_SLIST_FIFO_RSIZE" ,           0x11F0000009DD0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67581         {"NPEI_PKT30_SLIST_FIFO_RSIZE" ,           0x11F0000009DE0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67582         {"NPEI_PKT31_SLIST_FIFO_RSIZE" ,           0x11F0000009DF0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     502},
67583         {"NPEI_PKT_CNT_INT"            ,           0x11F0000009110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     503},
67584         {"NPEI_PKT_CNT_INT_ENB"        ,           0x11F0000009130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     504},
67585         {"NPEI_PKT_DATA_OUT_ES"        ,           0x11F00000090B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     505},
67586         {"NPEI_PKT_DATA_OUT_NS"        ,           0x11F00000090A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     506},
67587         {"NPEI_PKT_DATA_OUT_ROR"       ,           0x11F0000009090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     507},
67588         {"NPEI_PKT_DPADDR"             ,           0x11F0000009080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     508},
67589         {"NPEI_PKT_IN_BP"              ,           0x11F00000086B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     509},
67590         {"NPEI_PKT_IN_DONE0_CNTS"      ,           0x11F000000A000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67591         {"NPEI_PKT_IN_DONE1_CNTS"      ,           0x11F000000A010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67592         {"NPEI_PKT_IN_DONE2_CNTS"      ,           0x11F000000A020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67593         {"NPEI_PKT_IN_DONE3_CNTS"      ,           0x11F000000A030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67594         {"NPEI_PKT_IN_DONE4_CNTS"      ,           0x11F000000A040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67595         {"NPEI_PKT_IN_DONE5_CNTS"      ,           0x11F000000A050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67596         {"NPEI_PKT_IN_DONE6_CNTS"      ,           0x11F000000A060ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67597         {"NPEI_PKT_IN_DONE7_CNTS"      ,           0x11F000000A070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67598         {"NPEI_PKT_IN_DONE8_CNTS"      ,           0x11F000000A080ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67599         {"NPEI_PKT_IN_DONE9_CNTS"      ,           0x11F000000A090ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67600         {"NPEI_PKT_IN_DONE10_CNTS"     ,           0x11F000000A0A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67601         {"NPEI_PKT_IN_DONE11_CNTS"     ,           0x11F000000A0B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67602         {"NPEI_PKT_IN_DONE12_CNTS"     ,           0x11F000000A0C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67603         {"NPEI_PKT_IN_DONE13_CNTS"     ,           0x11F000000A0D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67604         {"NPEI_PKT_IN_DONE14_CNTS"     ,           0x11F000000A0E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67605         {"NPEI_PKT_IN_DONE15_CNTS"     ,           0x11F000000A0F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67606         {"NPEI_PKT_IN_DONE16_CNTS"     ,           0x11F000000A100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67607         {"NPEI_PKT_IN_DONE17_CNTS"     ,           0x11F000000A110ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67608         {"NPEI_PKT_IN_DONE18_CNTS"     ,           0x11F000000A120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67609         {"NPEI_PKT_IN_DONE19_CNTS"     ,           0x11F000000A130ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67610         {"NPEI_PKT_IN_DONE20_CNTS"     ,           0x11F000000A140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67611         {"NPEI_PKT_IN_DONE21_CNTS"     ,           0x11F000000A150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67612         {"NPEI_PKT_IN_DONE22_CNTS"     ,           0x11F000000A160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67613         {"NPEI_PKT_IN_DONE23_CNTS"     ,           0x11F000000A170ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67614         {"NPEI_PKT_IN_DONE24_CNTS"     ,           0x11F000000A180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67615         {"NPEI_PKT_IN_DONE25_CNTS"     ,           0x11F000000A190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67616         {"NPEI_PKT_IN_DONE26_CNTS"     ,           0x11F000000A1A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67617         {"NPEI_PKT_IN_DONE27_CNTS"     ,           0x11F000000A1B0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67618         {"NPEI_PKT_IN_DONE28_CNTS"     ,           0x11F000000A1C0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67619         {"NPEI_PKT_IN_DONE29_CNTS"     ,           0x11F000000A1D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67620         {"NPEI_PKT_IN_DONE30_CNTS"     ,           0x11F000000A1E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67621         {"NPEI_PKT_IN_DONE31_CNTS"     ,           0x11F000000A1F0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     510},
67622         {"NPEI_PKT_IN_INSTR_COUNTS"    ,           0x11F00000086A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     511},
67623         {"NPEI_PKT_IN_PCIE_PORT"       ,           0x11F00000091A0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     512},
67624         {"NPEI_PKT_INPUT_CONTROL"      ,           0x11F0000009150ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     513},
67625         {"NPEI_PKT_INSTR_ENB"          ,           0x11F0000009000ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     514},
67626         {"NPEI_PKT_INSTR_RD_SIZE"      ,           0x11F0000009190ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     515},
67627         {"NPEI_PKT_INSTR_SIZE"         ,           0x11F0000009020ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     516},
67628         {"NPEI_PKT_INT_LEVELS"         ,           0x11F0000009100ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     517},
67629         {"NPEI_PKT_IPTR"               ,           0x11F0000009070ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     518},
67630         {"NPEI_PKT_OUT_BMODE"          ,           0x11F00000090D0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     519},
67631         {"NPEI_PKT_OUT_ENB"            ,           0x11F0000009010ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     520},
67632         {"NPEI_PKT_OUTPUT_WMARK"       ,           0x11F0000009160ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     521},
67633         {"NPEI_PKT_PCIE_PORT"          ,           0x11F00000090E0ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     522},
67634         {"NPEI_PKT_PORT_IN_RST"        ,           0x11F0000008690ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     523},
67635         {"NPEI_PKT_SLIST_ES"           ,           0x11F0000009050ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     524},
67636         {"NPEI_PKT_SLIST_ID_SIZE"      ,           0x11F0000009180ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     525},
67637         {"NPEI_PKT_SLIST_NS"           ,           0x11F0000009040ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     526},
67638         {"NPEI_PKT_SLIST_ROR"          ,           0x11F0000009030ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     527},
67639         {"NPEI_PKT_TIME_INT"           ,           0x11F0000009120ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     528},
67640         {"NPEI_PKT_TIME_INT_ENB"       ,           0x11F0000009140ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     529},
67641         {"NPEI_RSL_INT_BLOCKS"         ,           0x11F0000008520ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     530},
67642         {"NPEI_SCRATCH_1"              ,           0x11F0000008270ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     531},
67643         {"NPEI_STATE1"                 ,           0x11F0000008620ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     532},
67644         {"NPEI_STATE2"                 ,           0x11F0000008630ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     533},
67645         {"NPEI_STATE3"                 ,           0x11F0000008640ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     534},
67646         {"NPEI_WIN_RD_ADDR"            ,                     0x210ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     535},
67647         {"NPEI_WIN_RD_DATA"            ,                     0x240ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     536},
67648         {"NPEI_WIN_WR_ADDR"            ,                     0x200ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     537},
67649         {"NPEI_WIN_WR_DATA"            ,                     0x220ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     538},
67650         {"NPEI_WIN_WR_MASK"            ,                     0x230ull,  CVMX_CSR_DB_TYPE_PEXP,  64,     539},
67651         {"NPEI_WINDOW_CTL"             ,           0x11F0000008380ull,  CVMX_CSR_DB_TYPE_PEXP_NCB,      64,     540},
67652         {"PCIEEP_CFG000"               ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     541},
67653         {"PCIEEP_CFG001"               ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     542},
67654         {"PCIEEP_CFG002"               ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     543},
67655         {"PCIEEP_CFG003"               ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     544},
67656         {"PCIEEP_CFG004"               ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     545},
67657         {"PCIEEP_CFG004_MASK"          ,                0x80000010ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     546},
67658         {"PCIEEP_CFG005"               ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     547},
67659         {"PCIEEP_CFG005_MASK"          ,                0x80000014ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     548},
67660         {"PCIEEP_CFG006"               ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     549},
67661         {"PCIEEP_CFG006_MASK"          ,                0x80000018ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     550},
67662         {"PCIEEP_CFG007"               ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     551},
67663         {"PCIEEP_CFG007_MASK"          ,                0x8000001Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     552},
67664         {"PCIEEP_CFG008"               ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     553},
67665         {"PCIEEP_CFG008_MASK"          ,                0x80000020ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     554},
67666         {"PCIEEP_CFG009"               ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     555},
67667         {"PCIEEP_CFG009_MASK"          ,                0x80000024ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     556},
67668         {"PCIEEP_CFG010"               ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     557},
67669         {"PCIEEP_CFG011"               ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     558},
67670         {"PCIEEP_CFG012"               ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     559},
67671         {"PCIEEP_CFG012_MASK"          ,                0x80000030ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     560},
67672         {"PCIEEP_CFG013"               ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     561},
67673         {"PCIEEP_CFG015"               ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     562},
67674         {"PCIEEP_CFG016"               ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     563},
67675         {"PCIEEP_CFG017"               ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     564},
67676         {"PCIEEP_CFG020"               ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     565},
67677         {"PCIEEP_CFG021"               ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     566},
67678         {"PCIEEP_CFG022"               ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     567},
67679         {"PCIEEP_CFG023"               ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     568},
67680         {"PCIEEP_CFG028"               ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     569},
67681         {"PCIEEP_CFG029"               ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     570},
67682         {"PCIEEP_CFG030"               ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     571},
67683         {"PCIEEP_CFG031"               ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     572},
67684         {"PCIEEP_CFG032"               ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     573},
67685         {"PCIEEP_CFG033"               ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     574},
67686         {"PCIEEP_CFG034"               ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     575},
67687         {"PCIEEP_CFG037"               ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     576},
67688         {"PCIEEP_CFG038"               ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     577},
67689         {"PCIEEP_CFG039"               ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     578},
67690         {"PCIEEP_CFG040"               ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     579},
67691         {"PCIEEP_CFG041"               ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     580},
67692         {"PCIEEP_CFG042"               ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     581},
67693         {"PCIEEP_CFG064"               ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     582},
67694         {"PCIEEP_CFG065"               ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     583},
67695         {"PCIEEP_CFG066"               ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     584},
67696         {"PCIEEP_CFG067"               ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     585},
67697         {"PCIEEP_CFG068"               ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     586},
67698         {"PCIEEP_CFG069"               ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     587},
67699         {"PCIEEP_CFG070"               ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     588},
67700         {"PCIEEP_CFG071"               ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     589},
67701         {"PCIEEP_CFG072"               ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     590},
67702         {"PCIEEP_CFG073"               ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     591},
67703         {"PCIEEP_CFG074"               ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     592},
67704         {"PCIEEP_CFG448"               ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     593},
67705         {"PCIEEP_CFG449"               ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     594},
67706         {"PCIEEP_CFG450"               ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     595},
67707         {"PCIEEP_CFG451"               ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     596},
67708         {"PCIEEP_CFG452"               ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     597},
67709         {"PCIEEP_CFG453"               ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     598},
67710         {"PCIEEP_CFG454"               ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     599},
67711         {"PCIEEP_CFG455"               ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     600},
67712         {"PCIEEP_CFG456"               ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     601},
67713         {"PCIEEP_CFG458"               ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     602},
67714         {"PCIEEP_CFG459"               ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     603},
67715         {"PCIEEP_CFG460"               ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     604},
67716         {"PCIEEP_CFG461"               ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     605},
67717         {"PCIEEP_CFG462"               ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     606},
67718         {"PCIEEP_CFG463"               ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     607},
67719         {"PCIEEP_CFG464"               ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     608},
67720         {"PCIEEP_CFG465"               ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     609},
67721         {"PCIEEP_CFG466"               ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     610},
67722         {"PCIEEP_CFG467"               ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     611},
67723         {"PCIEEP_CFG468"               ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     612},
67724         {"PCIEEP_CFG490"               ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     613},
67725         {"PCIEEP_CFG491"               ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     614},
67726         {"PCIEEP_CFG492"               ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     615},
67727         {"PCIEEP_CFG516"               ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     616},
67728         {"PCIEEP_CFG517"               ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGEP,   32,     617},
67729         {"PCIERC0_CFG000"              ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     618},
67730         {"PCIERC1_CFG000"              ,                       0x0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     618},
67731         {"PCIERC0_CFG001"              ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     619},
67732         {"PCIERC1_CFG001"              ,                       0x4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     619},
67733         {"PCIERC0_CFG002"              ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     620},
67734         {"PCIERC1_CFG002"              ,                       0x8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     620},
67735         {"PCIERC0_CFG003"              ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     621},
67736         {"PCIERC1_CFG003"              ,                       0xCull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     621},
67737         {"PCIERC0_CFG004"              ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     622},
67738         {"PCIERC1_CFG004"              ,                      0x10ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     622},
67739         {"PCIERC0_CFG005"              ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     623},
67740         {"PCIERC1_CFG005"              ,                      0x14ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     623},
67741         {"PCIERC0_CFG006"              ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     624},
67742         {"PCIERC1_CFG006"              ,                      0x18ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     624},
67743         {"PCIERC0_CFG007"              ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     625},
67744         {"PCIERC1_CFG007"              ,                      0x1Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     625},
67745         {"PCIERC0_CFG008"              ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     626},
67746         {"PCIERC1_CFG008"              ,                      0x20ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     626},
67747         {"PCIERC0_CFG009"              ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     627},
67748         {"PCIERC1_CFG009"              ,                      0x24ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     627},
67749         {"PCIERC0_CFG010"              ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     628},
67750         {"PCIERC1_CFG010"              ,                      0x28ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     628},
67751         {"PCIERC0_CFG011"              ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     629},
67752         {"PCIERC1_CFG011"              ,                      0x2Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     629},
67753         {"PCIERC0_CFG012"              ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     630},
67754         {"PCIERC1_CFG012"              ,                      0x30ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     630},
67755         {"PCIERC0_CFG013"              ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     631},
67756         {"PCIERC1_CFG013"              ,                      0x34ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     631},
67757         {"PCIERC0_CFG014"              ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     632},
67758         {"PCIERC1_CFG014"              ,                      0x38ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     632},
67759         {"PCIERC0_CFG015"              ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     633},
67760         {"PCIERC1_CFG015"              ,                      0x3Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     633},
67761         {"PCIERC0_CFG016"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     634},
67762         {"PCIERC1_CFG016"              ,                      0x40ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     634},
67763         {"PCIERC0_CFG017"              ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     635},
67764         {"PCIERC1_CFG017"              ,                      0x44ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     635},
67765         {"PCIERC0_CFG020"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     636},
67766         {"PCIERC1_CFG020"              ,                      0x50ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     636},
67767         {"PCIERC0_CFG021"              ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     637},
67768         {"PCIERC1_CFG021"              ,                      0x54ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     637},
67769         {"PCIERC0_CFG022"              ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     638},
67770         {"PCIERC1_CFG022"              ,                      0x58ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     638},
67771         {"PCIERC0_CFG023"              ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     639},
67772         {"PCIERC1_CFG023"              ,                      0x5Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     639},
67773         {"PCIERC0_CFG028"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     640},
67774         {"PCIERC1_CFG028"              ,                      0x70ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     640},
67775         {"PCIERC0_CFG029"              ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     641},
67776         {"PCIERC1_CFG029"              ,                      0x74ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     641},
67777         {"PCIERC0_CFG030"              ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     642},
67778         {"PCIERC1_CFG030"              ,                      0x78ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     642},
67779         {"PCIERC0_CFG031"              ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     643},
67780         {"PCIERC1_CFG031"              ,                      0x7Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     643},
67781         {"PCIERC0_CFG032"              ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     644},
67782         {"PCIERC1_CFG032"              ,                      0x80ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     644},
67783         {"PCIERC0_CFG033"              ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     645},
67784         {"PCIERC1_CFG033"              ,                      0x84ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     645},
67785         {"PCIERC0_CFG034"              ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     646},
67786         {"PCIERC1_CFG034"              ,                      0x88ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     646},
67787         {"PCIERC0_CFG035"              ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     647},
67788         {"PCIERC1_CFG035"              ,                      0x8Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     647},
67789         {"PCIERC0_CFG036"              ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     648},
67790         {"PCIERC1_CFG036"              ,                      0x90ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     648},
67791         {"PCIERC0_CFG037"              ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     649},
67792         {"PCIERC1_CFG037"              ,                      0x94ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     649},
67793         {"PCIERC0_CFG038"              ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     650},
67794         {"PCIERC1_CFG038"              ,                      0x98ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     650},
67795         {"PCIERC0_CFG039"              ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     651},
67796         {"PCIERC1_CFG039"              ,                      0x9Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     651},
67797         {"PCIERC0_CFG040"              ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     652},
67798         {"PCIERC1_CFG040"              ,                      0xA0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     652},
67799         {"PCIERC0_CFG041"              ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     653},
67800         {"PCIERC1_CFG041"              ,                      0xA4ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     653},
67801         {"PCIERC0_CFG042"              ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     654},
67802         {"PCIERC1_CFG042"              ,                      0xA8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     654},
67803         {"PCIERC0_CFG064"              ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     655},
67804         {"PCIERC1_CFG064"              ,                     0x100ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     655},
67805         {"PCIERC0_CFG065"              ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     656},
67806         {"PCIERC1_CFG065"              ,                     0x104ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     656},
67807         {"PCIERC0_CFG066"              ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     657},
67808         {"PCIERC1_CFG066"              ,                     0x108ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     657},
67809         {"PCIERC0_CFG067"              ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     658},
67810         {"PCIERC1_CFG067"              ,                     0x10Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     658},
67811         {"PCIERC0_CFG068"              ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     659},
67812         {"PCIERC1_CFG068"              ,                     0x110ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     659},
67813         {"PCIERC0_CFG069"              ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     660},
67814         {"PCIERC1_CFG069"              ,                     0x114ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     660},
67815         {"PCIERC0_CFG070"              ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     661},
67816         {"PCIERC1_CFG070"              ,                     0x118ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     661},
67817         {"PCIERC0_CFG071"              ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     662},
67818         {"PCIERC1_CFG071"              ,                     0x11Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     662},
67819         {"PCIERC0_CFG072"              ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     663},
67820         {"PCIERC1_CFG072"              ,                     0x120ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     663},
67821         {"PCIERC0_CFG073"              ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     664},
67822         {"PCIERC1_CFG073"              ,                     0x124ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     664},
67823         {"PCIERC0_CFG074"              ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     665},
67824         {"PCIERC1_CFG074"              ,                     0x128ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     665},
67825         {"PCIERC0_CFG075"              ,                     0x12Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     666},
67826         {"PCIERC1_CFG075"              ,                     0x12Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     666},
67827         {"PCIERC0_CFG076"              ,                     0x130ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     667},
67828         {"PCIERC1_CFG076"              ,                     0x130ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     667},
67829         {"PCIERC0_CFG077"              ,                     0x134ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     668},
67830         {"PCIERC1_CFG077"              ,                     0x134ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     668},
67831         {"PCIERC0_CFG448"              ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     669},
67832         {"PCIERC1_CFG448"              ,                     0x700ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     669},
67833         {"PCIERC0_CFG449"              ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     670},
67834         {"PCIERC1_CFG449"              ,                     0x704ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     670},
67835         {"PCIERC0_CFG450"              ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     671},
67836         {"PCIERC1_CFG450"              ,                     0x708ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     671},
67837         {"PCIERC0_CFG451"              ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     672},
67838         {"PCIERC1_CFG451"              ,                     0x70Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     672},
67839         {"PCIERC0_CFG452"              ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     673},
67840         {"PCIERC1_CFG452"              ,                     0x710ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     673},
67841         {"PCIERC0_CFG453"              ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     674},
67842         {"PCIERC1_CFG453"              ,                     0x714ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     674},
67843         {"PCIERC0_CFG454"              ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     675},
67844         {"PCIERC1_CFG454"              ,                     0x718ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     675},
67845         {"PCIERC0_CFG455"              ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     676},
67846         {"PCIERC1_CFG455"              ,                     0x71Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     676},
67847         {"PCIERC0_CFG456"              ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     677},
67848         {"PCIERC1_CFG456"              ,                     0x720ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     677},
67849         {"PCIERC0_CFG458"              ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     678},
67850         {"PCIERC1_CFG458"              ,                     0x728ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     678},
67851         {"PCIERC0_CFG459"              ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     679},
67852         {"PCIERC1_CFG459"              ,                     0x72Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     679},
67853         {"PCIERC0_CFG460"              ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     680},
67854         {"PCIERC1_CFG460"              ,                     0x730ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     680},
67855         {"PCIERC0_CFG461"              ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     681},
67856         {"PCIERC1_CFG461"              ,                     0x734ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     681},
67857         {"PCIERC0_CFG462"              ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     682},
67858         {"PCIERC1_CFG462"              ,                     0x738ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     682},
67859         {"PCIERC0_CFG463"              ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     683},
67860         {"PCIERC1_CFG463"              ,                     0x73Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     683},
67861         {"PCIERC0_CFG464"              ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     684},
67862         {"PCIERC1_CFG464"              ,                     0x740ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     684},
67863         {"PCIERC0_CFG465"              ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     685},
67864         {"PCIERC1_CFG465"              ,                     0x744ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     685},
67865         {"PCIERC0_CFG466"              ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     686},
67866         {"PCIERC1_CFG466"              ,                     0x748ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     686},
67867         {"PCIERC0_CFG467"              ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     687},
67868         {"PCIERC1_CFG467"              ,                     0x74Cull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     687},
67869         {"PCIERC0_CFG468"              ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     688},
67870         {"PCIERC1_CFG468"              ,                     0x750ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     688},
67871         {"PCIERC0_CFG490"              ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     689},
67872         {"PCIERC1_CFG490"              ,                     0x7A8ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     689},
67873         {"PCIERC0_CFG491"              ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     690},
67874         {"PCIERC1_CFG491"              ,                     0x7ACull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     690},
67875         {"PCIERC0_CFG492"              ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     691},
67876         {"PCIERC1_CFG492"              ,                     0x7B0ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     691},
67877         {"PCIERC0_CFG516"              ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     692},
67878         {"PCIERC1_CFG516"              ,                     0x810ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     692},
67879         {"PCIERC0_CFG517"              ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     693},
67880         {"PCIERC1_CFG517"              ,                     0x814ull,  CVMX_CSR_DB_TYPE_PCICONFIGRC,   32,     693},
67881         {"PCS0_AN000_ADV_REG"          ,           0x11800B0001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
67882         {"PCS0_AN001_ADV_REG"          ,           0x11800B0001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
67883         {"PCS0_AN002_ADV_REG"          ,           0x11800B0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
67884         {"PCS0_AN003_ADV_REG"          ,           0x11800B0001C10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     694},
67885         {"PCS0_AN000_EXT_ST_REG"       ,           0x11800B0001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
67886         {"PCS0_AN001_EXT_ST_REG"       ,           0x11800B0001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
67887         {"PCS0_AN002_EXT_ST_REG"       ,           0x11800B0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
67888         {"PCS0_AN003_EXT_ST_REG"       ,           0x11800B0001C28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     695},
67889         {"PCS0_AN000_LP_ABIL_REG"      ,           0x11800B0001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
67890         {"PCS0_AN001_LP_ABIL_REG"      ,           0x11800B0001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
67891         {"PCS0_AN002_LP_ABIL_REG"      ,           0x11800B0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
67892         {"PCS0_AN003_LP_ABIL_REG"      ,           0x11800B0001C18ull,  CVMX_CSR_DB_TYPE_RSL,   64,     696},
67893         {"PCS0_AN000_RESULTS_REG"      ,           0x11800B0001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
67894         {"PCS0_AN001_RESULTS_REG"      ,           0x11800B0001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
67895         {"PCS0_AN002_RESULTS_REG"      ,           0x11800B0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
67896         {"PCS0_AN003_RESULTS_REG"      ,           0x11800B0001C20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     697},
67897         {"PCS0_INT000_EN_REG"          ,           0x11800B0001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
67898         {"PCS0_INT001_EN_REG"          ,           0x11800B0001488ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
67899         {"PCS0_INT002_EN_REG"          ,           0x11800B0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
67900         {"PCS0_INT003_EN_REG"          ,           0x11800B0001C88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     698},
67901         {"PCS0_INT000_REG"             ,           0x11800B0001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     699},
67902         {"PCS0_INT001_REG"             ,           0x11800B0001480ull,  CVMX_CSR_DB_TYPE_RSL,   64,     699},
67903         {"PCS0_INT002_REG"             ,           0x11800B0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     699},
67904         {"PCS0_INT003_REG"             ,           0x11800B0001C80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     699},
67905         {"PCS0_LINK000_TIMER_COUNT_REG",           0x11800B0001040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
67906         {"PCS0_LINK001_TIMER_COUNT_REG",           0x11800B0001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
67907         {"PCS0_LINK002_TIMER_COUNT_REG",           0x11800B0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
67908         {"PCS0_LINK003_TIMER_COUNT_REG",           0x11800B0001C40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     700},
67909         {"PCS0_LOG_ANL000_REG"         ,           0x11800B0001090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
67910         {"PCS0_LOG_ANL001_REG"         ,           0x11800B0001490ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
67911         {"PCS0_LOG_ANL002_REG"         ,           0x11800B0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
67912         {"PCS0_LOG_ANL003_REG"         ,           0x11800B0001C90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     701},
67913         {"PCS0_MISC000_CTL_REG"        ,           0x11800B0001078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
67914         {"PCS0_MISC001_CTL_REG"        ,           0x11800B0001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
67915         {"PCS0_MISC002_CTL_REG"        ,           0x11800B0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
67916         {"PCS0_MISC003_CTL_REG"        ,           0x11800B0001C78ull,  CVMX_CSR_DB_TYPE_RSL,   64,     702},
67917         {"PCS0_MR000_CONTROL_REG"      ,           0x11800B0001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
67918         {"PCS0_MR001_CONTROL_REG"      ,           0x11800B0001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
67919         {"PCS0_MR002_CONTROL_REG"      ,           0x11800B0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
67920         {"PCS0_MR003_CONTROL_REG"      ,           0x11800B0001C00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     703},
67921         {"PCS0_MR000_STATUS_REG"       ,           0x11800B0001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     704},
67922         {"PCS0_MR001_STATUS_REG"       ,           0x11800B0001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     704},
67923         {"PCS0_MR002_STATUS_REG"       ,           0x11800B0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     704},
67924         {"PCS0_MR003_STATUS_REG"       ,           0x11800B0001C08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     704},
67925         {"PCS0_RX000_STATES_REG"       ,           0x11800B0001058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     705},
67926         {"PCS0_RX001_STATES_REG"       ,           0x11800B0001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     705},
67927         {"PCS0_RX002_STATES_REG"       ,           0x11800B0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     705},
67928         {"PCS0_RX003_STATES_REG"       ,           0x11800B0001C58ull,  CVMX_CSR_DB_TYPE_RSL,   64,     705},
67929         {"PCS0_RX000_SYNC_REG"         ,           0x11800B0001050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     706},
67930         {"PCS0_RX001_SYNC_REG"         ,           0x11800B0001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     706},
67931         {"PCS0_RX002_SYNC_REG"         ,           0x11800B0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     706},
67932         {"PCS0_RX003_SYNC_REG"         ,           0x11800B0001C50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     706},
67933         {"PCS0_SGM000_AN_ADV_REG"      ,           0x11800B0001068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     707},
67934         {"PCS0_SGM001_AN_ADV_REG"      ,           0x11800B0001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     707},
67935         {"PCS0_SGM002_AN_ADV_REG"      ,           0x11800B0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     707},
67936         {"PCS0_SGM003_AN_ADV_REG"      ,           0x11800B0001C68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     707},
67937         {"PCS0_SGM000_LP_ADV_REG"      ,           0x11800B0001070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     708},
67938         {"PCS0_SGM001_LP_ADV_REG"      ,           0x11800B0001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     708},
67939         {"PCS0_SGM002_LP_ADV_REG"      ,           0x11800B0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     708},
67940         {"PCS0_SGM003_LP_ADV_REG"      ,           0x11800B0001C70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     708},
67941         {"PCS0_TX000_STATES_REG"       ,           0x11800B0001060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     709},
67942         {"PCS0_TX001_STATES_REG"       ,           0x11800B0001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     709},
67943         {"PCS0_TX002_STATES_REG"       ,           0x11800B0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     709},
67944         {"PCS0_TX003_STATES_REG"       ,           0x11800B0001C60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     709},
67945         {"PCS0_TX_RX000_POLARITY_REG"  ,           0x11800B0001048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     710},
67946         {"PCS0_TX_RX001_POLARITY_REG"  ,           0x11800B0001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     710},
67947         {"PCS0_TX_RX002_POLARITY_REG"  ,           0x11800B0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     710},
67948         {"PCS0_TX_RX003_POLARITY_REG"  ,           0x11800B0001C48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     710},
67949         {"PCSX0_10GBX_STATUS_REG"      ,           0x11800B0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     711},
67950         {"PCSX1_10GBX_STATUS_REG"      ,           0x11800B8000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     711},
67951         {"PCSX0_BIST_STATUS_REG"       ,           0x11800B0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     712},
67952         {"PCSX1_BIST_STATUS_REG"       ,           0x11800B8000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     712},
67953         {"PCSX0_BIT_LOCK_STATUS_REG"   ,           0x11800B0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     713},
67954         {"PCSX1_BIT_LOCK_STATUS_REG"   ,           0x11800B8000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     713},
67955         {"PCSX0_CONTROL1_REG"          ,           0x11800B0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     714},
67956         {"PCSX1_CONTROL1_REG"          ,           0x11800B8000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     714},
67957         {"PCSX0_CONTROL2_REG"          ,           0x11800B0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     715},
67958         {"PCSX1_CONTROL2_REG"          ,           0x11800B8000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     715},
67959         {"PCSX0_INT_EN_REG"            ,           0x11800B0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     716},
67960         {"PCSX1_INT_EN_REG"            ,           0x11800B8000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     716},
67961         {"PCSX0_INT_REG"               ,           0x11800B0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     717},
67962         {"PCSX1_INT_REG"               ,           0x11800B8000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     717},
67963         {"PCSX0_LOG_ANL_REG"           ,           0x11800B0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     718},
67964         {"PCSX1_LOG_ANL_REG"           ,           0x11800B8000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     718},
67965         {"PCSX0_MISC_CTL_REG"          ,           0x11800B0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     719},
67966         {"PCSX1_MISC_CTL_REG"          ,           0x11800B8000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     719},
67967         {"PCSX0_RX_SYNC_STATES_REG"    ,           0x11800B0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     720},
67968         {"PCSX1_RX_SYNC_STATES_REG"    ,           0x11800B8000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     720},
67969         {"PCSX0_SPD_ABIL_REG"          ,           0x11800B0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     721},
67970         {"PCSX1_SPD_ABIL_REG"          ,           0x11800B8000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     721},
67971         {"PCSX0_STATUS1_REG"           ,           0x11800B0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     722},
67972         {"PCSX1_STATUS1_REG"           ,           0x11800B8000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     722},
67973         {"PCSX0_STATUS2_REG"           ,           0x11800B0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     723},
67974         {"PCSX1_STATUS2_REG"           ,           0x11800B8000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     723},
67975         {"PCSX0_TX_RX_POLARITY_REG"    ,           0x11800B0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
67976         {"PCSX1_TX_RX_POLARITY_REG"    ,           0x11800B8000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     724},
67977         {"PCSX0_TX_RX_STATES_REG"      ,           0x11800B0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
67978         {"PCSX1_TX_RX_STATES_REG"      ,           0x11800B8000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     725},
67979         {"PESC0_BIST_STATUS"           ,           0x11800C8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     726},
67980         {"PESC1_BIST_STATUS"           ,           0x11800D0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     726},
67981         {"PESC0_BIST_STATUS2"          ,           0x11800C8000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     727},
67982         {"PESC1_BIST_STATUS2"          ,           0x11800D0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     727},
67983         {"PESC0_CFG_RD"                ,           0x11800C8000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     728},
67984         {"PESC1_CFG_RD"                ,           0x11800D0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     728},
67985         {"PESC0_CFG_WR"                ,           0x11800C8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     729},
67986         {"PESC1_CFG_WR"                ,           0x11800D0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     729},
67987         {"PESC0_CPL_LUT_VALID"         ,           0x11800C8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     730},
67988         {"PESC1_CPL_LUT_VALID"         ,           0x11800D0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     730},
67989         {"PESC0_CTL_STATUS"            ,           0x11800C8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     731},
67990         {"PESC1_CTL_STATUS"            ,           0x11800D0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     731},
67991         {"PESC0_CTL_STATUS2"           ,           0x11800C8000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     732},
67992         {"PESC1_CTL_STATUS2"           ,           0x11800D0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     732},
67993         {"PESC0_DBG_INFO"              ,           0x11800C8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     733},
67994         {"PESC1_DBG_INFO"              ,           0x11800D0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     733},
67995         {"PESC0_DBG_INFO_EN"           ,           0x11800C80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     734},
67996         {"PESC1_DBG_INFO_EN"           ,           0x11800D00000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     734},
67997         {"PESC0_DIAG_STATUS"           ,           0x11800C8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     735},
67998         {"PESC1_DIAG_STATUS"           ,           0x11800D0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     735},
67999         {"PESC0_P2N_BAR0_START"        ,           0x11800C8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     736},
68000         {"PESC1_P2N_BAR0_START"        ,           0x11800D0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     736},
68001         {"PESC0_P2N_BAR1_START"        ,           0x11800C8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     737},
68002         {"PESC1_P2N_BAR1_START"        ,           0x11800D0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     737},
68003         {"PESC0_P2N_BAR2_START"        ,           0x11800C8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     738},
68004         {"PESC1_P2N_BAR2_START"        ,           0x11800D0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     738},
68005         {"PESC0_P2P_BAR000_END"        ,           0x11800C8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
68006         {"PESC0_P2P_BAR001_END"        ,           0x11800C8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
68007         {"PESC0_P2P_BAR002_END"        ,           0x11800C8000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
68008         {"PESC0_P2P_BAR003_END"        ,           0x11800C8000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
68009         {"PESC1_P2P_BAR000_END"        ,           0x11800D0000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
68010         {"PESC1_P2P_BAR001_END"        ,           0x11800D0000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
68011         {"PESC1_P2P_BAR002_END"        ,           0x11800D0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
68012         {"PESC1_P2P_BAR003_END"        ,           0x11800D0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     739},
68013         {"PESC0_P2P_BAR000_START"      ,           0x11800C8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
68014         {"PESC0_P2P_BAR001_START"      ,           0x11800C8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
68015         {"PESC0_P2P_BAR002_START"      ,           0x11800C8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
68016         {"PESC0_P2P_BAR003_START"      ,           0x11800C8000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
68017         {"PESC1_P2P_BAR000_START"      ,           0x11800D0000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
68018         {"PESC1_P2P_BAR001_START"      ,           0x11800D0000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
68019         {"PESC1_P2P_BAR002_START"      ,           0x11800D0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
68020         {"PESC1_P2P_BAR003_START"      ,           0x11800D0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     740},
68021         {"PESC0_TLP_CREDITS"           ,           0x11800C8000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
68022         {"PESC1_TLP_CREDITS"           ,           0x11800D0000038ull,  CVMX_CSR_DB_TYPE_RSL,   64,     741},
68023         {"PIP_BIST_STATUS"             ,           0x11800A0000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     742},
68024         {"PIP_DEC_IPSEC0"              ,           0x11800A0000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
68025         {"PIP_DEC_IPSEC1"              ,           0x11800A0000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
68026         {"PIP_DEC_IPSEC2"              ,           0x11800A0000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
68027         {"PIP_DEC_IPSEC3"              ,           0x11800A0000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     743},
68028         {"PIP_DSA_SRC_GRP"             ,           0x11800A0000190ull,  CVMX_CSR_DB_TYPE_RSL,   64,     744},
68029         {"PIP_DSA_VID_GRP"             ,           0x11800A0000198ull,  CVMX_CSR_DB_TYPE_RSL,   64,     745},
68030         {"PIP_FRM_LEN_CHK0"            ,           0x11800A0000180ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
68031         {"PIP_FRM_LEN_CHK1"            ,           0x11800A0000188ull,  CVMX_CSR_DB_TYPE_RSL,   64,     746},
68032         {"PIP_GBL_CFG"                 ,           0x11800A0000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     747},
68033         {"PIP_GBL_CTL"                 ,           0x11800A0000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     748},
68034         {"PIP_HG_PRI_QOS"              ,           0x11800A00001A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     749},
68035         {"PIP_INT_EN"                  ,           0x11800A0000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     750},
68036         {"PIP_INT_REG"                 ,           0x11800A0000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     751},
68037         {"PIP_IP_OFFSET"               ,           0x11800A0000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     752},
68038         {"PIP_PRT_CFG0"                ,           0x11800A0000200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68039         {"PIP_PRT_CFG1"                ,           0x11800A0000208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68040         {"PIP_PRT_CFG2"                ,           0x11800A0000210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68041         {"PIP_PRT_CFG3"                ,           0x11800A0000218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68042         {"PIP_PRT_CFG32"               ,           0x11800A0000300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68043         {"PIP_PRT_CFG33"               ,           0x11800A0000308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68044         {"PIP_PRT_CFG34"               ,           0x11800A0000310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68045         {"PIP_PRT_CFG35"               ,           0x11800A0000318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68046         {"PIP_PRT_CFG36"               ,           0x11800A0000320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68047         {"PIP_PRT_CFG37"               ,           0x11800A0000328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68048         {"PIP_PRT_CFG38"               ,           0x11800A0000330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68049         {"PIP_PRT_CFG39"               ,           0x11800A0000338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     753},
68050         {"PIP_PRT_TAG0"                ,           0x11800A0000400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68051         {"PIP_PRT_TAG1"                ,           0x11800A0000408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68052         {"PIP_PRT_TAG2"                ,           0x11800A0000410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68053         {"PIP_PRT_TAG3"                ,           0x11800A0000418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68054         {"PIP_PRT_TAG32"               ,           0x11800A0000500ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68055         {"PIP_PRT_TAG33"               ,           0x11800A0000508ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68056         {"PIP_PRT_TAG34"               ,           0x11800A0000510ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68057         {"PIP_PRT_TAG35"               ,           0x11800A0000518ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68058         {"PIP_PRT_TAG36"               ,           0x11800A0000520ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68059         {"PIP_PRT_TAG37"               ,           0x11800A0000528ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68060         {"PIP_PRT_TAG38"               ,           0x11800A0000530ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68061         {"PIP_PRT_TAG39"               ,           0x11800A0000538ull,  CVMX_CSR_DB_TYPE_RSL,   64,     754},
68062         {"PIP_QOS_DIFF0"               ,           0x11800A0000600ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68063         {"PIP_QOS_DIFF1"               ,           0x11800A0000608ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68064         {"PIP_QOS_DIFF2"               ,           0x11800A0000610ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68065         {"PIP_QOS_DIFF3"               ,           0x11800A0000618ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68066         {"PIP_QOS_DIFF4"               ,           0x11800A0000620ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68067         {"PIP_QOS_DIFF5"               ,           0x11800A0000628ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68068         {"PIP_QOS_DIFF6"               ,           0x11800A0000630ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68069         {"PIP_QOS_DIFF7"               ,           0x11800A0000638ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68070         {"PIP_QOS_DIFF8"               ,           0x11800A0000640ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68071         {"PIP_QOS_DIFF9"               ,           0x11800A0000648ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68072         {"PIP_QOS_DIFF10"              ,           0x11800A0000650ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68073         {"PIP_QOS_DIFF11"              ,           0x11800A0000658ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68074         {"PIP_QOS_DIFF12"              ,           0x11800A0000660ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68075         {"PIP_QOS_DIFF13"              ,           0x11800A0000668ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68076         {"PIP_QOS_DIFF14"              ,           0x11800A0000670ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68077         {"PIP_QOS_DIFF15"              ,           0x11800A0000678ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68078         {"PIP_QOS_DIFF16"              ,           0x11800A0000680ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68079         {"PIP_QOS_DIFF17"              ,           0x11800A0000688ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68080         {"PIP_QOS_DIFF18"              ,           0x11800A0000690ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68081         {"PIP_QOS_DIFF19"              ,           0x11800A0000698ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68082         {"PIP_QOS_DIFF20"              ,           0x11800A00006A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68083         {"PIP_QOS_DIFF21"              ,           0x11800A00006A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68084         {"PIP_QOS_DIFF22"              ,           0x11800A00006B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68085         {"PIP_QOS_DIFF23"              ,           0x11800A00006B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68086         {"PIP_QOS_DIFF24"              ,           0x11800A00006C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68087         {"PIP_QOS_DIFF25"              ,           0x11800A00006C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68088         {"PIP_QOS_DIFF26"              ,           0x11800A00006D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68089         {"PIP_QOS_DIFF27"              ,           0x11800A00006D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68090         {"PIP_QOS_DIFF28"              ,           0x11800A00006E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68091         {"PIP_QOS_DIFF29"              ,           0x11800A00006E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68092         {"PIP_QOS_DIFF30"              ,           0x11800A00006F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68093         {"PIP_QOS_DIFF31"              ,           0x11800A00006F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68094         {"PIP_QOS_DIFF32"              ,           0x11800A0000700ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68095         {"PIP_QOS_DIFF33"              ,           0x11800A0000708ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68096         {"PIP_QOS_DIFF34"              ,           0x11800A0000710ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68097         {"PIP_QOS_DIFF35"              ,           0x11800A0000718ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68098         {"PIP_QOS_DIFF36"              ,           0x11800A0000720ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68099         {"PIP_QOS_DIFF37"              ,           0x11800A0000728ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68100         {"PIP_QOS_DIFF38"              ,           0x11800A0000730ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68101         {"PIP_QOS_DIFF39"              ,           0x11800A0000738ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68102         {"PIP_QOS_DIFF40"              ,           0x11800A0000740ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68103         {"PIP_QOS_DIFF41"              ,           0x11800A0000748ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68104         {"PIP_QOS_DIFF42"              ,           0x11800A0000750ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68105         {"PIP_QOS_DIFF43"              ,           0x11800A0000758ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68106         {"PIP_QOS_DIFF44"              ,           0x11800A0000760ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68107         {"PIP_QOS_DIFF45"              ,           0x11800A0000768ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68108         {"PIP_QOS_DIFF46"              ,           0x11800A0000770ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68109         {"PIP_QOS_DIFF47"              ,           0x11800A0000778ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68110         {"PIP_QOS_DIFF48"              ,           0x11800A0000780ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68111         {"PIP_QOS_DIFF49"              ,           0x11800A0000788ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68112         {"PIP_QOS_DIFF50"              ,           0x11800A0000790ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68113         {"PIP_QOS_DIFF51"              ,           0x11800A0000798ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68114         {"PIP_QOS_DIFF52"              ,           0x11800A00007A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68115         {"PIP_QOS_DIFF53"              ,           0x11800A00007A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68116         {"PIP_QOS_DIFF54"              ,           0x11800A00007B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68117         {"PIP_QOS_DIFF55"              ,           0x11800A00007B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68118         {"PIP_QOS_DIFF56"              ,           0x11800A00007C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68119         {"PIP_QOS_DIFF57"              ,           0x11800A00007C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68120         {"PIP_QOS_DIFF58"              ,           0x11800A00007D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68121         {"PIP_QOS_DIFF59"              ,           0x11800A00007D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68122         {"PIP_QOS_DIFF60"              ,           0x11800A00007E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68123         {"PIP_QOS_DIFF61"              ,           0x11800A00007E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68124         {"PIP_QOS_DIFF62"              ,           0x11800A00007F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68125         {"PIP_QOS_DIFF63"              ,           0x11800A00007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     755},
68126         {"PIP_QOS_VLAN0"               ,           0x11800A00000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     756},
68127         {"PIP_QOS_VLAN1"               ,           0x11800A00000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     756},
68128         {"PIP_QOS_VLAN2"               ,           0x11800A00000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     756},
68129         {"PIP_QOS_VLAN3"               ,           0x11800A00000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     756},
68130         {"PIP_QOS_VLAN4"               ,           0x11800A00000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     756},
68131         {"PIP_QOS_VLAN5"               ,           0x11800A00000E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     756},
68132         {"PIP_QOS_VLAN6"               ,           0x11800A00000F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     756},
68133         {"PIP_QOS_VLAN7"               ,           0x11800A00000F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     756},
68134         {"PIP_QOS_WATCH0"              ,           0x11800A0000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
68135         {"PIP_QOS_WATCH1"              ,           0x11800A0000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
68136         {"PIP_QOS_WATCH2"              ,           0x11800A0000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
68137         {"PIP_QOS_WATCH3"              ,           0x11800A0000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
68138         {"PIP_QOS_WATCH4"              ,           0x11800A0000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
68139         {"PIP_QOS_WATCH5"              ,           0x11800A0000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
68140         {"PIP_QOS_WATCH6"              ,           0x11800A0000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
68141         {"PIP_QOS_WATCH7"              ,           0x11800A0000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     757},
68142         {"PIP_RAW_WORD"                ,           0x11800A00000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     758},
68143         {"PIP_SFT_RST"                 ,           0x11800A0000030ull,  CVMX_CSR_DB_TYPE_RSL,   64,     759},
68144         {"PIP_STAT0_PRT0"              ,           0x11800A0000800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68145         {"PIP_STAT0_PRT1"              ,           0x11800A0000850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68146         {"PIP_STAT0_PRT2"              ,           0x11800A00008A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68147         {"PIP_STAT0_PRT3"              ,           0x11800A00008F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68148         {"PIP_STAT0_PRT32"             ,           0x11800A0001200ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68149         {"PIP_STAT0_PRT33"             ,           0x11800A0001250ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68150         {"PIP_STAT0_PRT34"             ,           0x11800A00012A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68151         {"PIP_STAT0_PRT35"             ,           0x11800A00012F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68152         {"PIP_STAT0_PRT36"             ,           0x11800A0001340ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68153         {"PIP_STAT0_PRT37"             ,           0x11800A0001390ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68154         {"PIP_STAT0_PRT38"             ,           0x11800A00013E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68155         {"PIP_STAT0_PRT39"             ,           0x11800A0001430ull,  CVMX_CSR_DB_TYPE_RSL,   64,     760},
68156         {"PIP_STAT1_PRT0"              ,           0x11800A0000808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68157         {"PIP_STAT1_PRT1"              ,           0x11800A0000858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68158         {"PIP_STAT1_PRT2"              ,           0x11800A00008A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68159         {"PIP_STAT1_PRT3"              ,           0x11800A00008F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68160         {"PIP_STAT1_PRT32"             ,           0x11800A0001208ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68161         {"PIP_STAT1_PRT33"             ,           0x11800A0001258ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68162         {"PIP_STAT1_PRT34"             ,           0x11800A00012A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68163         {"PIP_STAT1_PRT35"             ,           0x11800A00012F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68164         {"PIP_STAT1_PRT36"             ,           0x11800A0001348ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68165         {"PIP_STAT1_PRT37"             ,           0x11800A0001398ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68166         {"PIP_STAT1_PRT38"             ,           0x11800A00013E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68167         {"PIP_STAT1_PRT39"             ,           0x11800A0001438ull,  CVMX_CSR_DB_TYPE_RSL,   64,     761},
68168         {"PIP_STAT2_PRT0"              ,           0x11800A0000810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68169         {"PIP_STAT2_PRT1"              ,           0x11800A0000860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68170         {"PIP_STAT2_PRT2"              ,           0x11800A00008B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68171         {"PIP_STAT2_PRT3"              ,           0x11800A0000900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68172         {"PIP_STAT2_PRT32"             ,           0x11800A0001210ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68173         {"PIP_STAT2_PRT33"             ,           0x11800A0001260ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68174         {"PIP_STAT2_PRT34"             ,           0x11800A00012B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68175         {"PIP_STAT2_PRT35"             ,           0x11800A0001300ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68176         {"PIP_STAT2_PRT36"             ,           0x11800A0001350ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68177         {"PIP_STAT2_PRT37"             ,           0x11800A00013A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68178         {"PIP_STAT2_PRT38"             ,           0x11800A00013F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68179         {"PIP_STAT2_PRT39"             ,           0x11800A0001440ull,  CVMX_CSR_DB_TYPE_RSL,   64,     762},
68180         {"PIP_STAT3_PRT0"              ,           0x11800A0000818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68181         {"PIP_STAT3_PRT1"              ,           0x11800A0000868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68182         {"PIP_STAT3_PRT2"              ,           0x11800A00008B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68183         {"PIP_STAT3_PRT3"              ,           0x11800A0000908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68184         {"PIP_STAT3_PRT32"             ,           0x11800A0001218ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68185         {"PIP_STAT3_PRT33"             ,           0x11800A0001268ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68186         {"PIP_STAT3_PRT34"             ,           0x11800A00012B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68187         {"PIP_STAT3_PRT35"             ,           0x11800A0001308ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68188         {"PIP_STAT3_PRT36"             ,           0x11800A0001358ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68189         {"PIP_STAT3_PRT37"             ,           0x11800A00013A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68190         {"PIP_STAT3_PRT38"             ,           0x11800A00013F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68191         {"PIP_STAT3_PRT39"             ,           0x11800A0001448ull,  CVMX_CSR_DB_TYPE_RSL,   64,     763},
68192         {"PIP_STAT4_PRT0"              ,           0x11800A0000820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68193         {"PIP_STAT4_PRT1"              ,           0x11800A0000870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68194         {"PIP_STAT4_PRT2"              ,           0x11800A00008C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68195         {"PIP_STAT4_PRT3"              ,           0x11800A0000910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68196         {"PIP_STAT4_PRT32"             ,           0x11800A0001220ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68197         {"PIP_STAT4_PRT33"             ,           0x11800A0001270ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68198         {"PIP_STAT4_PRT34"             ,           0x11800A00012C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68199         {"PIP_STAT4_PRT35"             ,           0x11800A0001310ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68200         {"PIP_STAT4_PRT36"             ,           0x11800A0001360ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68201         {"PIP_STAT4_PRT37"             ,           0x11800A00013B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68202         {"PIP_STAT4_PRT38"             ,           0x11800A0001400ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68203         {"PIP_STAT4_PRT39"             ,           0x11800A0001450ull,  CVMX_CSR_DB_TYPE_RSL,   64,     764},
68204         {"PIP_STAT5_PRT0"              ,           0x11800A0000828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68205         {"PIP_STAT5_PRT1"              ,           0x11800A0000878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68206         {"PIP_STAT5_PRT2"              ,           0x11800A00008C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68207         {"PIP_STAT5_PRT3"              ,           0x11800A0000918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68208         {"PIP_STAT5_PRT32"             ,           0x11800A0001228ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68209         {"PIP_STAT5_PRT33"             ,           0x11800A0001278ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68210         {"PIP_STAT5_PRT34"             ,           0x11800A00012C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68211         {"PIP_STAT5_PRT35"             ,           0x11800A0001318ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68212         {"PIP_STAT5_PRT36"             ,           0x11800A0001368ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68213         {"PIP_STAT5_PRT37"             ,           0x11800A00013B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68214         {"PIP_STAT5_PRT38"             ,           0x11800A0001408ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68215         {"PIP_STAT5_PRT39"             ,           0x11800A0001458ull,  CVMX_CSR_DB_TYPE_RSL,   64,     765},
68216         {"PIP_STAT6_PRT0"              ,           0x11800A0000830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68217         {"PIP_STAT6_PRT1"              ,           0x11800A0000880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68218         {"PIP_STAT6_PRT2"              ,           0x11800A00008D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68219         {"PIP_STAT6_PRT3"              ,           0x11800A0000920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68220         {"PIP_STAT6_PRT32"             ,           0x11800A0001230ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68221         {"PIP_STAT6_PRT33"             ,           0x11800A0001280ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68222         {"PIP_STAT6_PRT34"             ,           0x11800A00012D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68223         {"PIP_STAT6_PRT35"             ,           0x11800A0001320ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68224         {"PIP_STAT6_PRT36"             ,           0x11800A0001370ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68225         {"PIP_STAT6_PRT37"             ,           0x11800A00013C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68226         {"PIP_STAT6_PRT38"             ,           0x11800A0001410ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68227         {"PIP_STAT6_PRT39"             ,           0x11800A0001460ull,  CVMX_CSR_DB_TYPE_RSL,   64,     766},
68228         {"PIP_STAT7_PRT0"              ,           0x11800A0000838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68229         {"PIP_STAT7_PRT1"              ,           0x11800A0000888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68230         {"PIP_STAT7_PRT2"              ,           0x11800A00008D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68231         {"PIP_STAT7_PRT3"              ,           0x11800A0000928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68232         {"PIP_STAT7_PRT32"             ,           0x11800A0001238ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68233         {"PIP_STAT7_PRT33"             ,           0x11800A0001288ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68234         {"PIP_STAT7_PRT34"             ,           0x11800A00012D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68235         {"PIP_STAT7_PRT35"             ,           0x11800A0001328ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68236         {"PIP_STAT7_PRT36"             ,           0x11800A0001378ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68237         {"PIP_STAT7_PRT37"             ,           0x11800A00013C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68238         {"PIP_STAT7_PRT38"             ,           0x11800A0001418ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68239         {"PIP_STAT7_PRT39"             ,           0x11800A0001468ull,  CVMX_CSR_DB_TYPE_RSL,   64,     767},
68240         {"PIP_STAT8_PRT0"              ,           0x11800A0000840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68241         {"PIP_STAT8_PRT1"              ,           0x11800A0000890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68242         {"PIP_STAT8_PRT2"              ,           0x11800A00008E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68243         {"PIP_STAT8_PRT3"              ,           0x11800A0000930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68244         {"PIP_STAT8_PRT32"             ,           0x11800A0001240ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68245         {"PIP_STAT8_PRT33"             ,           0x11800A0001290ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68246         {"PIP_STAT8_PRT34"             ,           0x11800A00012E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68247         {"PIP_STAT8_PRT35"             ,           0x11800A0001330ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68248         {"PIP_STAT8_PRT36"             ,           0x11800A0001380ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68249         {"PIP_STAT8_PRT37"             ,           0x11800A00013D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68250         {"PIP_STAT8_PRT38"             ,           0x11800A0001420ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68251         {"PIP_STAT8_PRT39"             ,           0x11800A0001470ull,  CVMX_CSR_DB_TYPE_RSL,   64,     768},
68252         {"PIP_STAT9_PRT0"              ,           0x11800A0000848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68253         {"PIP_STAT9_PRT1"              ,           0x11800A0000898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68254         {"PIP_STAT9_PRT2"              ,           0x11800A00008E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68255         {"PIP_STAT9_PRT3"              ,           0x11800A0000938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68256         {"PIP_STAT9_PRT32"             ,           0x11800A0001248ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68257         {"PIP_STAT9_PRT33"             ,           0x11800A0001298ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68258         {"PIP_STAT9_PRT34"             ,           0x11800A00012E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68259         {"PIP_STAT9_PRT35"             ,           0x11800A0001338ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68260         {"PIP_STAT9_PRT36"             ,           0x11800A0001388ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68261         {"PIP_STAT9_PRT37"             ,           0x11800A00013D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68262         {"PIP_STAT9_PRT38"             ,           0x11800A0001428ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68263         {"PIP_STAT9_PRT39"             ,           0x11800A0001478ull,  CVMX_CSR_DB_TYPE_RSL,   64,     769},
68264         {"PIP_STAT_CTL"                ,           0x11800A0000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     770},
68265         {"PIP_STAT_INB_ERRS0"          ,           0x11800A0001A10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68266         {"PIP_STAT_INB_ERRS1"          ,           0x11800A0001A30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68267         {"PIP_STAT_INB_ERRS2"          ,           0x11800A0001A50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68268         {"PIP_STAT_INB_ERRS3"          ,           0x11800A0001A70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68269         {"PIP_STAT_INB_ERRS32"         ,           0x11800A0001E10ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68270         {"PIP_STAT_INB_ERRS33"         ,           0x11800A0001E30ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68271         {"PIP_STAT_INB_ERRS34"         ,           0x11800A0001E50ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68272         {"PIP_STAT_INB_ERRS35"         ,           0x11800A0001E70ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68273         {"PIP_STAT_INB_ERRS36"         ,           0x11800A0001E90ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68274         {"PIP_STAT_INB_ERRS37"         ,           0x11800A0001EB0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68275         {"PIP_STAT_INB_ERRS38"         ,           0x11800A0001ED0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68276         {"PIP_STAT_INB_ERRS39"         ,           0x11800A0001EF0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     771},
68277         {"PIP_STAT_INB_OCTS0"          ,           0x11800A0001A08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68278         {"PIP_STAT_INB_OCTS1"          ,           0x11800A0001A28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68279         {"PIP_STAT_INB_OCTS2"          ,           0x11800A0001A48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68280         {"PIP_STAT_INB_OCTS3"          ,           0x11800A0001A68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68281         {"PIP_STAT_INB_OCTS32"         ,           0x11800A0001E08ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68282         {"PIP_STAT_INB_OCTS33"         ,           0x11800A0001E28ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68283         {"PIP_STAT_INB_OCTS34"         ,           0x11800A0001E48ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68284         {"PIP_STAT_INB_OCTS35"         ,           0x11800A0001E68ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68285         {"PIP_STAT_INB_OCTS36"         ,           0x11800A0001E88ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68286         {"PIP_STAT_INB_OCTS37"         ,           0x11800A0001EA8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68287         {"PIP_STAT_INB_OCTS38"         ,           0x11800A0001EC8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68288         {"PIP_STAT_INB_OCTS39"         ,           0x11800A0001EE8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     772},
68289         {"PIP_STAT_INB_PKTS0"          ,           0x11800A0001A00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68290         {"PIP_STAT_INB_PKTS1"          ,           0x11800A0001A20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68291         {"PIP_STAT_INB_PKTS2"          ,           0x11800A0001A40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68292         {"PIP_STAT_INB_PKTS3"          ,           0x11800A0001A60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68293         {"PIP_STAT_INB_PKTS32"         ,           0x11800A0001E00ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68294         {"PIP_STAT_INB_PKTS33"         ,           0x11800A0001E20ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68295         {"PIP_STAT_INB_PKTS34"         ,           0x11800A0001E40ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68296         {"PIP_STAT_INB_PKTS35"         ,           0x11800A0001E60ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68297         {"PIP_STAT_INB_PKTS36"         ,           0x11800A0001E80ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68298         {"PIP_STAT_INB_PKTS37"         ,           0x11800A0001EA0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68299         {"PIP_STAT_INB_PKTS38"         ,           0x11800A0001EC0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68300         {"PIP_STAT_INB_PKTS39"         ,           0x11800A0001EE0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     773},
68301         {"PIP_TAG_INC0"                ,           0x11800A0001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68302         {"PIP_TAG_INC1"                ,           0x11800A0001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68303         {"PIP_TAG_INC2"                ,           0x11800A0001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68304         {"PIP_TAG_INC3"                ,           0x11800A0001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68305         {"PIP_TAG_INC4"                ,           0x11800A0001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68306         {"PIP_TAG_INC5"                ,           0x11800A0001828ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68307         {"PIP_TAG_INC6"                ,           0x11800A0001830ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68308         {"PIP_TAG_INC7"                ,           0x11800A0001838ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68309         {"PIP_TAG_INC8"                ,           0x11800A0001840ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68310         {"PIP_TAG_INC9"                ,           0x11800A0001848ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68311         {"PIP_TAG_INC10"               ,           0x11800A0001850ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68312         {"PIP_TAG_INC11"               ,           0x11800A0001858ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68313         {"PIP_TAG_INC12"               ,           0x11800A0001860ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68314         {"PIP_TAG_INC13"               ,           0x11800A0001868ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68315         {"PIP_TAG_INC14"               ,           0x11800A0001870ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68316         {"PIP_TAG_INC15"               ,           0x11800A0001878ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68317         {"PIP_TAG_INC16"               ,           0x11800A0001880ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68318         {"PIP_TAG_INC17"               ,           0x11800A0001888ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68319         {"PIP_TAG_INC18"               ,           0x11800A0001890ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68320         {"PIP_TAG_INC19"               ,           0x11800A0001898ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68321         {"PIP_TAG_INC20"               ,           0x11800A00018A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68322         {"PIP_TAG_INC21"               ,           0x11800A00018A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68323         {"PIP_TAG_INC22"               ,           0x11800A00018B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68324         {"PIP_TAG_INC23"               ,           0x11800A00018B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68325         {"PIP_TAG_INC24"               ,           0x11800A00018C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68326         {"PIP_TAG_INC25"               ,           0x11800A00018C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68327         {"PIP_TAG_INC26"               ,           0x11800A00018D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68328         {"PIP_TAG_INC27"               ,           0x11800A00018D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68329         {"PIP_TAG_INC28"               ,           0x11800A00018E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68330         {"PIP_TAG_INC29"               ,           0x11800A00018E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68331         {"PIP_TAG_INC30"               ,           0x11800A00018F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68332         {"PIP_TAG_INC31"               ,           0x11800A00018F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68333         {"PIP_TAG_INC32"               ,           0x11800A0001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68334         {"PIP_TAG_INC33"               ,           0x11800A0001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68335         {"PIP_TAG_INC34"               ,           0x11800A0001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68336         {"PIP_TAG_INC35"               ,           0x11800A0001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68337         {"PIP_TAG_INC36"               ,           0x11800A0001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68338         {"PIP_TAG_INC37"               ,           0x11800A0001928ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68339         {"PIP_TAG_INC38"               ,           0x11800A0001930ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68340         {"PIP_TAG_INC39"               ,           0x11800A0001938ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68341         {"PIP_TAG_INC40"               ,           0x11800A0001940ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68342         {"PIP_TAG_INC41"               ,           0x11800A0001948ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68343         {"PIP_TAG_INC42"               ,           0x11800A0001950ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68344         {"PIP_TAG_INC43"               ,           0x11800A0001958ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68345         {"PIP_TAG_INC44"               ,           0x11800A0001960ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68346         {"PIP_TAG_INC45"               ,           0x11800A0001968ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68347         {"PIP_TAG_INC46"               ,           0x11800A0001970ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68348         {"PIP_TAG_INC47"               ,           0x11800A0001978ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68349         {"PIP_TAG_INC48"               ,           0x11800A0001980ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68350         {"PIP_TAG_INC49"               ,           0x11800A0001988ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68351         {"PIP_TAG_INC50"               ,           0x11800A0001990ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68352         {"PIP_TAG_INC51"               ,           0x11800A0001998ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68353         {"PIP_TAG_INC52"               ,           0x11800A00019A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68354         {"PIP_TAG_INC53"               ,           0x11800A00019A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68355         {"PIP_TAG_INC54"               ,           0x11800A00019B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68356         {"PIP_TAG_INC55"               ,           0x11800A00019B8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68357         {"PIP_TAG_INC56"               ,           0x11800A00019C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68358         {"PIP_TAG_INC57"               ,           0x11800A00019C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68359         {"PIP_TAG_INC58"               ,           0x11800A00019D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68360         {"PIP_TAG_INC59"               ,           0x11800A00019D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68361         {"PIP_TAG_INC60"               ,           0x11800A00019E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68362         {"PIP_TAG_INC61"               ,           0x11800A00019E8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68363         {"PIP_TAG_INC62"               ,           0x11800A00019F0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68364         {"PIP_TAG_INC63"               ,           0x11800A00019F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     774},
68365         {"PIP_TAG_MASK"                ,           0x11800A0000070ull,  CVMX_CSR_DB_TYPE_RSL,   64,     775},
68366         {"PIP_TAG_SECRET"              ,           0x11800A0000068ull,  CVMX_CSR_DB_TYPE_RSL,   64,     776},
68367         {"PIP_TODO_ENTRY"              ,           0x11800A0000078ull,  CVMX_CSR_DB_TYPE_RSL,   64,     777},
68368         {"PKO_MEM_COUNT0"              ,           0x1180050001080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     778},
68369         {"PKO_MEM_COUNT1"              ,           0x1180050001088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     779},
68370         {"PKO_MEM_DEBUG0"              ,           0x1180050001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     780},
68371         {"PKO_MEM_DEBUG1"              ,           0x1180050001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     781},
68372         {"PKO_MEM_DEBUG10"             ,           0x1180050001150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     782},
68373         {"PKO_MEM_DEBUG11"             ,           0x1180050001158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     783},
68374         {"PKO_MEM_DEBUG12"             ,           0x1180050001160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     784},
68375         {"PKO_MEM_DEBUG13"             ,           0x1180050001168ull,  CVMX_CSR_DB_TYPE_RSL,   64,     785},
68376         {"PKO_MEM_DEBUG14"             ,           0x1180050001170ull,  CVMX_CSR_DB_TYPE_RSL,   64,     786},
68377         {"PKO_MEM_DEBUG2"              ,           0x1180050001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     787},
68378         {"PKO_MEM_DEBUG3"              ,           0x1180050001118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     788},
68379         {"PKO_MEM_DEBUG4"              ,           0x1180050001120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     789},
68380         {"PKO_MEM_DEBUG5"              ,           0x1180050001128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     790},
68381         {"PKO_MEM_DEBUG6"              ,           0x1180050001130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     791},
68382         {"PKO_MEM_DEBUG7"              ,           0x1180050001138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     792},
68383         {"PKO_MEM_DEBUG8"              ,           0x1180050001140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     793},
68384         {"PKO_MEM_DEBUG9"              ,           0x1180050001148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     794},
68385         {"PKO_MEM_PORT_PTRS"           ,           0x1180050001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     795},
68386         {"PKO_MEM_PORT_QOS"            ,           0x1180050001018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     796},
68387         {"PKO_MEM_PORT_RATE0"          ,           0x1180050001020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     797},
68388         {"PKO_MEM_PORT_RATE1"          ,           0x1180050001028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     798},
68389         {"PKO_MEM_QUEUE_PTRS"          ,           0x1180050001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     799},
68390         {"PKO_MEM_QUEUE_QOS"           ,           0x1180050001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     800},
68391         {"PKO_REG_BIST_RESULT"         ,           0x1180050000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     801},
68392         {"PKO_REG_CMD_BUF"             ,           0x1180050000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     802},
68393         {"PKO_REG_DEBUG0"              ,           0x1180050000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     803},
68394         {"PKO_REG_DEBUG1"              ,           0x11800500000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     804},
68395         {"PKO_REG_DEBUG2"              ,           0x11800500000A8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     805},
68396         {"PKO_REG_DEBUG3"              ,           0x11800500000B0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     806},
68397         {"PKO_REG_ENGINE_INFLIGHT"     ,           0x1180050000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     807},
68398         {"PKO_REG_ENGINE_THRESH"       ,           0x1180050000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     808},
68399         {"PKO_REG_ERROR"               ,           0x1180050000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     809},
68400         {"PKO_REG_FLAGS"               ,           0x1180050000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     810},
68401         {"PKO_REG_GMX_PORT_MODE"       ,           0x1180050000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     811},
68402         {"PKO_REG_INT_MASK"            ,           0x1180050000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     812},
68403         {"PKO_REG_QUEUE_MODE"          ,           0x1180050000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     813},
68404         {"PKO_REG_QUEUE_PTRS1"         ,           0x1180050000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     814},
68405         {"PKO_REG_READ_IDX"            ,           0x1180050000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     815},
68406         {"POW_BIST_STAT"               ,           0x16700000003F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     816},
68407         {"POW_DS_PC"                   ,           0x1670000000398ull,  CVMX_CSR_DB_TYPE_NCB,   64,     817},
68408         {"POW_ECC_ERR"                 ,           0x1670000000218ull,  CVMX_CSR_DB_TYPE_NCB,   64,     818},
68409         {"POW_INT_CTL"                 ,           0x1670000000220ull,  CVMX_CSR_DB_TYPE_NCB,   64,     819},
68410         {"POW_IQ_CNT0"                 ,           0x1670000000340ull,  CVMX_CSR_DB_TYPE_NCB,   64,     820},
68411         {"POW_IQ_CNT1"                 ,           0x1670000000348ull,  CVMX_CSR_DB_TYPE_NCB,   64,     820},
68412         {"POW_IQ_CNT2"                 ,           0x1670000000350ull,  CVMX_CSR_DB_TYPE_NCB,   64,     820},
68413         {"POW_IQ_CNT3"                 ,           0x1670000000358ull,  CVMX_CSR_DB_TYPE_NCB,   64,     820},
68414         {"POW_IQ_CNT4"                 ,           0x1670000000360ull,  CVMX_CSR_DB_TYPE_NCB,   64,     820},
68415         {"POW_IQ_CNT5"                 ,           0x1670000000368ull,  CVMX_CSR_DB_TYPE_NCB,   64,     820},
68416         {"POW_IQ_CNT6"                 ,           0x1670000000370ull,  CVMX_CSR_DB_TYPE_NCB,   64,     820},
68417         {"POW_IQ_CNT7"                 ,           0x1670000000378ull,  CVMX_CSR_DB_TYPE_NCB,   64,     820},
68418         {"POW_IQ_COM_CNT"              ,           0x1670000000388ull,  CVMX_CSR_DB_TYPE_NCB,   64,     821},
68419         {"POW_IQ_INT"                  ,           0x1670000000238ull,  CVMX_CSR_DB_TYPE_NCB,   64,     822},
68420         {"POW_IQ_INT_EN"               ,           0x1670000000240ull,  CVMX_CSR_DB_TYPE_NCB,   64,     823},
68421         {"POW_IQ_THR0"                 ,           0x16700000003A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
68422         {"POW_IQ_THR1"                 ,           0x16700000003A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
68423         {"POW_IQ_THR2"                 ,           0x16700000003B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
68424         {"POW_IQ_THR3"                 ,           0x16700000003B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
68425         {"POW_IQ_THR4"                 ,           0x16700000003C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
68426         {"POW_IQ_THR5"                 ,           0x16700000003C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
68427         {"POW_IQ_THR6"                 ,           0x16700000003D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
68428         {"POW_IQ_THR7"                 ,           0x16700000003D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     824},
68429         {"POW_NOS_CNT"                 ,           0x1670000000228ull,  CVMX_CSR_DB_TYPE_NCB,   64,     825},
68430         {"POW_NW_TIM"                  ,           0x1670000000210ull,  CVMX_CSR_DB_TYPE_NCB,   64,     826},
68431         {"POW_PF_RST_MSK"              ,           0x1670000000230ull,  CVMX_CSR_DB_TYPE_NCB,   64,     827},
68432         {"POW_PP_GRP_MSK0"             ,           0x1670000000000ull,  CVMX_CSR_DB_TYPE_NCB,   64,     828},
68433         {"POW_PP_GRP_MSK1"             ,           0x1670000000008ull,  CVMX_CSR_DB_TYPE_NCB,   64,     828},
68434         {"POW_PP_GRP_MSK2"             ,           0x1670000000010ull,  CVMX_CSR_DB_TYPE_NCB,   64,     828},
68435         {"POW_PP_GRP_MSK3"             ,           0x1670000000018ull,  CVMX_CSR_DB_TYPE_NCB,   64,     828},
68436         {"POW_QOS_RND0"                ,           0x16700000001C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     829},
68437         {"POW_QOS_RND1"                ,           0x16700000001C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     829},
68438         {"POW_QOS_RND2"                ,           0x16700000001D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     829},
68439         {"POW_QOS_RND3"                ,           0x16700000001D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     829},
68440         {"POW_QOS_RND4"                ,           0x16700000001E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     829},
68441         {"POW_QOS_RND5"                ,           0x16700000001E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     829},
68442         {"POW_QOS_RND6"                ,           0x16700000001F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     829},
68443         {"POW_QOS_RND7"                ,           0x16700000001F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     829},
68444         {"POW_QOS_THR0"                ,           0x1670000000180ull,  CVMX_CSR_DB_TYPE_NCB,   64,     830},
68445         {"POW_QOS_THR1"                ,           0x1670000000188ull,  CVMX_CSR_DB_TYPE_NCB,   64,     830},
68446         {"POW_QOS_THR2"                ,           0x1670000000190ull,  CVMX_CSR_DB_TYPE_NCB,   64,     830},
68447         {"POW_QOS_THR3"                ,           0x1670000000198ull,  CVMX_CSR_DB_TYPE_NCB,   64,     830},
68448         {"POW_QOS_THR4"                ,           0x16700000001A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     830},
68449         {"POW_QOS_THR5"                ,           0x16700000001A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     830},
68450         {"POW_QOS_THR6"                ,           0x16700000001B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     830},
68451         {"POW_QOS_THR7"                ,           0x16700000001B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     830},
68452         {"POW_TS_PC"                   ,           0x1670000000390ull,  CVMX_CSR_DB_TYPE_NCB,   64,     831},
68453         {"POW_WA_COM_PC"               ,           0x1670000000380ull,  CVMX_CSR_DB_TYPE_NCB,   64,     832},
68454         {"POW_WA_PC0"                  ,           0x1670000000300ull,  CVMX_CSR_DB_TYPE_NCB,   64,     833},
68455         {"POW_WA_PC1"                  ,           0x1670000000308ull,  CVMX_CSR_DB_TYPE_NCB,   64,     833},
68456         {"POW_WA_PC2"                  ,           0x1670000000310ull,  CVMX_CSR_DB_TYPE_NCB,   64,     833},
68457         {"POW_WA_PC3"                  ,           0x1670000000318ull,  CVMX_CSR_DB_TYPE_NCB,   64,     833},
68458         {"POW_WA_PC4"                  ,           0x1670000000320ull,  CVMX_CSR_DB_TYPE_NCB,   64,     833},
68459         {"POW_WA_PC5"                  ,           0x1670000000328ull,  CVMX_CSR_DB_TYPE_NCB,   64,     833},
68460         {"POW_WA_PC6"                  ,           0x1670000000330ull,  CVMX_CSR_DB_TYPE_NCB,   64,     833},
68461         {"POW_WA_PC7"                  ,           0x1670000000338ull,  CVMX_CSR_DB_TYPE_NCB,   64,     833},
68462         {"POW_WQ_INT"                  ,           0x1670000000200ull,  CVMX_CSR_DB_TYPE_NCB,   64,     834},
68463         {"POW_WQ_INT_CNT0"             ,           0x1670000000100ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68464         {"POW_WQ_INT_CNT1"             ,           0x1670000000108ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68465         {"POW_WQ_INT_CNT2"             ,           0x1670000000110ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68466         {"POW_WQ_INT_CNT3"             ,           0x1670000000118ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68467         {"POW_WQ_INT_CNT4"             ,           0x1670000000120ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68468         {"POW_WQ_INT_CNT5"             ,           0x1670000000128ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68469         {"POW_WQ_INT_CNT6"             ,           0x1670000000130ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68470         {"POW_WQ_INT_CNT7"             ,           0x1670000000138ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68471         {"POW_WQ_INT_CNT8"             ,           0x1670000000140ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68472         {"POW_WQ_INT_CNT9"             ,           0x1670000000148ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68473         {"POW_WQ_INT_CNT10"            ,           0x1670000000150ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68474         {"POW_WQ_INT_CNT11"            ,           0x1670000000158ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68475         {"POW_WQ_INT_CNT12"            ,           0x1670000000160ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68476         {"POW_WQ_INT_CNT13"            ,           0x1670000000168ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68477         {"POW_WQ_INT_CNT14"            ,           0x1670000000170ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68478         {"POW_WQ_INT_CNT15"            ,           0x1670000000178ull,  CVMX_CSR_DB_TYPE_NCB,   64,     835},
68479         {"POW_WQ_INT_PC"               ,           0x1670000000208ull,  CVMX_CSR_DB_TYPE_NCB,   64,     836},
68480         {"POW_WQ_INT_THR0"             ,           0x1670000000080ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68481         {"POW_WQ_INT_THR1"             ,           0x1670000000088ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68482         {"POW_WQ_INT_THR2"             ,           0x1670000000090ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68483         {"POW_WQ_INT_THR3"             ,           0x1670000000098ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68484         {"POW_WQ_INT_THR4"             ,           0x16700000000A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68485         {"POW_WQ_INT_THR5"             ,           0x16700000000A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68486         {"POW_WQ_INT_THR6"             ,           0x16700000000B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68487         {"POW_WQ_INT_THR7"             ,           0x16700000000B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68488         {"POW_WQ_INT_THR8"             ,           0x16700000000C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68489         {"POW_WQ_INT_THR9"             ,           0x16700000000C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68490         {"POW_WQ_INT_THR10"            ,           0x16700000000D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68491         {"POW_WQ_INT_THR11"            ,           0x16700000000D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68492         {"POW_WQ_INT_THR12"            ,           0x16700000000E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68493         {"POW_WQ_INT_THR13"            ,           0x16700000000E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68494         {"POW_WQ_INT_THR14"            ,           0x16700000000F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68495         {"POW_WQ_INT_THR15"            ,           0x16700000000F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     837},
68496         {"POW_WS_PC0"                  ,           0x1670000000280ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68497         {"POW_WS_PC1"                  ,           0x1670000000288ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68498         {"POW_WS_PC2"                  ,           0x1670000000290ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68499         {"POW_WS_PC3"                  ,           0x1670000000298ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68500         {"POW_WS_PC4"                  ,           0x16700000002A0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68501         {"POW_WS_PC5"                  ,           0x16700000002A8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68502         {"POW_WS_PC6"                  ,           0x16700000002B0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68503         {"POW_WS_PC7"                  ,           0x16700000002B8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68504         {"POW_WS_PC8"                  ,           0x16700000002C0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68505         {"POW_WS_PC9"                  ,           0x16700000002C8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68506         {"POW_WS_PC10"                 ,           0x16700000002D0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68507         {"POW_WS_PC11"                 ,           0x16700000002D8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68508         {"POW_WS_PC12"                 ,           0x16700000002E0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68509         {"POW_WS_PC13"                 ,           0x16700000002E8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68510         {"POW_WS_PC14"                 ,           0x16700000002F0ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68511         {"POW_WS_PC15"                 ,           0x16700000002F8ull,  CVMX_CSR_DB_TYPE_NCB,   64,     838},
68512         {"RAD_MEM_DEBUG0"              ,           0x1180070001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     839},
68513         {"RAD_MEM_DEBUG1"              ,           0x1180070001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     840},
68514         {"RAD_MEM_DEBUG2"              ,           0x1180070001010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     841},
68515         {"RAD_REG_BIST_RESULT"         ,           0x1180070000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     842},
68516         {"RAD_REG_CMD_BUF"             ,           0x1180070000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     843},
68517         {"RAD_REG_CTL"                 ,           0x1180070000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     844},
68518         {"RAD_REG_DEBUG0"              ,           0x1180070000100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     845},
68519         {"RAD_REG_DEBUG1"              ,           0x1180070000108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     846},
68520         {"RAD_REG_DEBUG10"             ,           0x1180070000150ull,  CVMX_CSR_DB_TYPE_RSL,   64,     847},
68521         {"RAD_REG_DEBUG11"             ,           0x1180070000158ull,  CVMX_CSR_DB_TYPE_RSL,   64,     848},
68522         {"RAD_REG_DEBUG12"             ,           0x1180070000160ull,  CVMX_CSR_DB_TYPE_RSL,   64,     849},
68523         {"RAD_REG_DEBUG2"              ,           0x1180070000110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     850},
68524         {"RAD_REG_DEBUG3"              ,           0x1180070000118ull,  CVMX_CSR_DB_TYPE_RSL,   64,     851},
68525         {"RAD_REG_DEBUG4"              ,           0x1180070000120ull,  CVMX_CSR_DB_TYPE_RSL,   64,     852},
68526         {"RAD_REG_DEBUG5"              ,           0x1180070000128ull,  CVMX_CSR_DB_TYPE_RSL,   64,     853},
68527         {"RAD_REG_DEBUG6"              ,           0x1180070000130ull,  CVMX_CSR_DB_TYPE_RSL,   64,     854},
68528         {"RAD_REG_DEBUG7"              ,           0x1180070000138ull,  CVMX_CSR_DB_TYPE_RSL,   64,     855},
68529         {"RAD_REG_DEBUG8"              ,           0x1180070000140ull,  CVMX_CSR_DB_TYPE_RSL,   64,     856},
68530         {"RAD_REG_DEBUG9"              ,           0x1180070000148ull,  CVMX_CSR_DB_TYPE_RSL,   64,     857},
68531         {"RAD_REG_ERROR"               ,           0x1180070000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     858},
68532         {"RAD_REG_INT_MASK"            ,           0x1180070000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     859},
68533         {"RAD_REG_POLYNOMIAL"          ,           0x1180070000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     860},
68534         {"RAD_REG_READ_IDX"            ,           0x1180070000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     861},
68535         {"RNM_BIST_STATUS"             ,           0x1180040000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     862},
68536         {"RNM_CTL_STATUS"              ,           0x1180040000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     863},
68537         {"SMI0_CLK"                    ,           0x1180000001818ull,  CVMX_CSR_DB_TYPE_RSL,   64,     864},
68538         {"SMI1_CLK"                    ,           0x1180000001918ull,  CVMX_CSR_DB_TYPE_RSL,   64,     864},
68539         {"SMI0_CMD"                    ,           0x1180000001800ull,  CVMX_CSR_DB_TYPE_RSL,   64,     865},
68540         {"SMI1_CMD"                    ,           0x1180000001900ull,  CVMX_CSR_DB_TYPE_RSL,   64,     865},
68541         {"SMI0_EN"                     ,           0x1180000001820ull,  CVMX_CSR_DB_TYPE_RSL,   64,     866},
68542         {"SMI1_EN"                     ,           0x1180000001920ull,  CVMX_CSR_DB_TYPE_RSL,   64,     866},
68543         {"SMI0_RD_DAT"                 ,           0x1180000001810ull,  CVMX_CSR_DB_TYPE_RSL,   64,     867},
68544         {"SMI1_RD_DAT"                 ,           0x1180000001910ull,  CVMX_CSR_DB_TYPE_RSL,   64,     867},
68545         {"SMI0_WR_DAT"                 ,           0x1180000001808ull,  CVMX_CSR_DB_TYPE_RSL,   64,     868},
68546         {"SMI1_WR_DAT"                 ,           0x1180000001908ull,  CVMX_CSR_DB_TYPE_RSL,   64,     868},
68547         {"TIM_MEM_DEBUG0"              ,           0x1180058001100ull,  CVMX_CSR_DB_TYPE_RSL,   64,     869},
68548         {"TIM_MEM_DEBUG1"              ,           0x1180058001108ull,  CVMX_CSR_DB_TYPE_RSL,   64,     870},
68549         {"TIM_MEM_DEBUG2"              ,           0x1180058001110ull,  CVMX_CSR_DB_TYPE_RSL,   64,     871},
68550         {"TIM_MEM_RING0"               ,           0x1180058001000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     872},
68551         {"TIM_MEM_RING1"               ,           0x1180058001008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     873},
68552         {"TIM_REG_BIST_RESULT"         ,           0x1180058000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     874},
68553         {"TIM_REG_ERROR"               ,           0x1180058000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     875},
68554         {"TIM_REG_FLAGS"               ,           0x1180058000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     876},
68555         {"TIM_REG_INT_MASK"            ,           0x1180058000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     877},
68556         {"TIM_REG_READ_IDX"            ,           0x1180058000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     878},
68557         {"TRA_BIST_STATUS"             ,           0x11800A8000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     879},
68558         {"TRA_CTL"                     ,           0x11800A8000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     880},
68559         {"TRA_CYCLES_SINCE"            ,           0x11800A8000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     881},
68560         {"TRA_CYCLES_SINCE1"           ,           0x11800A8000028ull,  CVMX_CSR_DB_TYPE_RSL,   64,     882},
68561         {"TRA_FILT_ADR_ADR"            ,           0x11800A8000058ull,  CVMX_CSR_DB_TYPE_RSL,   64,     883},
68562         {"TRA_FILT_ADR_MSK"            ,           0x11800A8000060ull,  CVMX_CSR_DB_TYPE_RSL,   64,     884},
68563         {"TRA_FILT_CMD"                ,           0x11800A8000040ull,  CVMX_CSR_DB_TYPE_RSL,   64,     885},
68564         {"TRA_FILT_DID"                ,           0x11800A8000050ull,  CVMX_CSR_DB_TYPE_RSL,   64,     886},
68565         {"TRA_FILT_SID"                ,           0x11800A8000048ull,  CVMX_CSR_DB_TYPE_RSL,   64,     887},
68566         {"TRA_INT_STATUS"              ,           0x11800A8000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     888},
68567         {"TRA_READ_DAT"                ,           0x11800A8000020ull,  CVMX_CSR_DB_TYPE_RSL,   64,     889},
68568         {"TRA_TRIG0_ADR_ADR"           ,           0x11800A8000098ull,  CVMX_CSR_DB_TYPE_RSL,   64,     890},
68569         {"TRA_TRIG0_ADR_MSK"           ,           0x11800A80000A0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     891},
68570         {"TRA_TRIG0_CMD"               ,           0x11800A8000080ull,  CVMX_CSR_DB_TYPE_RSL,   64,     892},
68571         {"TRA_TRIG0_DID"               ,           0x11800A8000090ull,  CVMX_CSR_DB_TYPE_RSL,   64,     893},
68572         {"TRA_TRIG0_SID"               ,           0x11800A8000088ull,  CVMX_CSR_DB_TYPE_RSL,   64,     894},
68573         {"TRA_TRIG1_ADR_ADR"           ,           0x11800A80000D8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     895},
68574         {"TRA_TRIG1_ADR_MSK"           ,           0x11800A80000E0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     896},
68575         {"TRA_TRIG1_CMD"               ,           0x11800A80000C0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     897},
68576         {"TRA_TRIG1_DID"               ,           0x11800A80000D0ull,  CVMX_CSR_DB_TYPE_RSL,   64,     898},
68577         {"TRA_TRIG1_SID"               ,           0x11800A80000C8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     899},
68578         {"USBC0_DAINT"                 ,           0x16F0010000818ull,  CVMX_CSR_DB_TYPE_NCB,   32,     900},
68579         {"USBC1_DAINT"                 ,           0x17F0010000818ull,  CVMX_CSR_DB_TYPE_NCB,   32,     900},
68580         {"USBC0_DAINTMSK"              ,           0x16F001000081Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     901},
68581         {"USBC1_DAINTMSK"              ,           0x17F001000081Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     901},
68582         {"USBC0_DCFG"                  ,           0x16F0010000800ull,  CVMX_CSR_DB_TYPE_NCB,   32,     902},
68583         {"USBC1_DCFG"                  ,           0x17F0010000800ull,  CVMX_CSR_DB_TYPE_NCB,   32,     902},
68584         {"USBC0_DCTL"                  ,           0x16F0010000804ull,  CVMX_CSR_DB_TYPE_NCB,   32,     903},
68585         {"USBC1_DCTL"                  ,           0x17F0010000804ull,  CVMX_CSR_DB_TYPE_NCB,   32,     903},
68586         {"USBC0_DIEPCTL000"            ,           0x16F0010000900ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68587         {"USBC0_DIEPCTL001"            ,           0x16F0010000920ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68588         {"USBC0_DIEPCTL002"            ,           0x16F0010000940ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68589         {"USBC0_DIEPCTL003"            ,           0x16F0010000960ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68590         {"USBC0_DIEPCTL004"            ,           0x16F0010000980ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68591         {"USBC1_DIEPCTL000"            ,           0x17F0010000900ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68592         {"USBC1_DIEPCTL001"            ,           0x17F0010000920ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68593         {"USBC1_DIEPCTL002"            ,           0x17F0010000940ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68594         {"USBC1_DIEPCTL003"            ,           0x17F0010000960ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68595         {"USBC1_DIEPCTL004"            ,           0x17F0010000980ull,  CVMX_CSR_DB_TYPE_NCB,   32,     904},
68596         {"USBC0_DIEPINT000"            ,           0x16F0010000908ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68597         {"USBC0_DIEPINT001"            ,           0x16F0010000928ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68598         {"USBC0_DIEPINT002"            ,           0x16F0010000948ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68599         {"USBC0_DIEPINT003"            ,           0x16F0010000968ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68600         {"USBC0_DIEPINT004"            ,           0x16F0010000988ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68601         {"USBC1_DIEPINT000"            ,           0x17F0010000908ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68602         {"USBC1_DIEPINT001"            ,           0x17F0010000928ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68603         {"USBC1_DIEPINT002"            ,           0x17F0010000948ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68604         {"USBC1_DIEPINT003"            ,           0x17F0010000968ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68605         {"USBC1_DIEPINT004"            ,           0x17F0010000988ull,  CVMX_CSR_DB_TYPE_NCB,   32,     905},
68606         {"USBC0_DIEPMSK"               ,           0x16F0010000810ull,  CVMX_CSR_DB_TYPE_NCB,   32,     906},
68607         {"USBC1_DIEPMSK"               ,           0x17F0010000810ull,  CVMX_CSR_DB_TYPE_NCB,   32,     906},
68608         {"USBC0_DIEPTSIZ000"           ,           0x16F0010000910ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68609         {"USBC0_DIEPTSIZ001"           ,           0x16F0010000930ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68610         {"USBC0_DIEPTSIZ002"           ,           0x16F0010000950ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68611         {"USBC0_DIEPTSIZ003"           ,           0x16F0010000970ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68612         {"USBC0_DIEPTSIZ004"           ,           0x16F0010000990ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68613         {"USBC1_DIEPTSIZ000"           ,           0x17F0010000910ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68614         {"USBC1_DIEPTSIZ001"           ,           0x17F0010000930ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68615         {"USBC1_DIEPTSIZ002"           ,           0x17F0010000950ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68616         {"USBC1_DIEPTSIZ003"           ,           0x17F0010000970ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68617         {"USBC1_DIEPTSIZ004"           ,           0x17F0010000990ull,  CVMX_CSR_DB_TYPE_NCB,   32,     907},
68618         {"USBC0_DOEPCTL000"            ,           0x16F0010000B00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68619         {"USBC0_DOEPCTL001"            ,           0x16F0010000B20ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68620         {"USBC0_DOEPCTL002"            ,           0x16F0010000B40ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68621         {"USBC0_DOEPCTL003"            ,           0x16F0010000B60ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68622         {"USBC0_DOEPCTL004"            ,           0x16F0010000B80ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68623         {"USBC1_DOEPCTL000"            ,           0x17F0010000B00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68624         {"USBC1_DOEPCTL001"            ,           0x17F0010000B20ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68625         {"USBC1_DOEPCTL002"            ,           0x17F0010000B40ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68626         {"USBC1_DOEPCTL003"            ,           0x17F0010000B60ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68627         {"USBC1_DOEPCTL004"            ,           0x17F0010000B80ull,  CVMX_CSR_DB_TYPE_NCB,   32,     908},
68628         {"USBC0_DOEPINT000"            ,           0x16F0010000B08ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68629         {"USBC0_DOEPINT001"            ,           0x16F0010000B28ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68630         {"USBC0_DOEPINT002"            ,           0x16F0010000B48ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68631         {"USBC0_DOEPINT003"            ,           0x16F0010000B68ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68632         {"USBC0_DOEPINT004"            ,           0x16F0010000B88ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68633         {"USBC1_DOEPINT000"            ,           0x17F0010000B08ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68634         {"USBC1_DOEPINT001"            ,           0x17F0010000B28ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68635         {"USBC1_DOEPINT002"            ,           0x17F0010000B48ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68636         {"USBC1_DOEPINT003"            ,           0x17F0010000B68ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68637         {"USBC1_DOEPINT004"            ,           0x17F0010000B88ull,  CVMX_CSR_DB_TYPE_NCB,   32,     909},
68638         {"USBC0_DOEPMSK"               ,           0x16F0010000814ull,  CVMX_CSR_DB_TYPE_NCB,   32,     910},
68639         {"USBC1_DOEPMSK"               ,           0x17F0010000814ull,  CVMX_CSR_DB_TYPE_NCB,   32,     910},
68640         {"USBC0_DOEPTSIZ000"           ,           0x16F0010000B10ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68641         {"USBC0_DOEPTSIZ001"           ,           0x16F0010000B30ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68642         {"USBC0_DOEPTSIZ002"           ,           0x16F0010000B50ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68643         {"USBC0_DOEPTSIZ003"           ,           0x16F0010000B70ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68644         {"USBC0_DOEPTSIZ004"           ,           0x16F0010000B90ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68645         {"USBC1_DOEPTSIZ000"           ,           0x17F0010000B10ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68646         {"USBC1_DOEPTSIZ001"           ,           0x17F0010000B30ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68647         {"USBC1_DOEPTSIZ002"           ,           0x17F0010000B50ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68648         {"USBC1_DOEPTSIZ003"           ,           0x17F0010000B70ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68649         {"USBC1_DOEPTSIZ004"           ,           0x17F0010000B90ull,  CVMX_CSR_DB_TYPE_NCB,   32,     911},
68650         {"USBC0_DPTXFSIZ001"           ,           0x16F0010000104ull,  CVMX_CSR_DB_TYPE_NCB,   32,     912},
68651         {"USBC0_DPTXFSIZ002"           ,           0x16F0010000108ull,  CVMX_CSR_DB_TYPE_NCB,   32,     912},
68652         {"USBC0_DPTXFSIZ003"           ,           0x16F001000010Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     912},
68653         {"USBC0_DPTXFSIZ004"           ,           0x16F0010000110ull,  CVMX_CSR_DB_TYPE_NCB,   32,     912},
68654         {"USBC1_DPTXFSIZ001"           ,           0x17F0010000104ull,  CVMX_CSR_DB_TYPE_NCB,   32,     912},
68655         {"USBC1_DPTXFSIZ002"           ,           0x17F0010000108ull,  CVMX_CSR_DB_TYPE_NCB,   32,     912},
68656         {"USBC1_DPTXFSIZ003"           ,           0x17F001000010Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     912},
68657         {"USBC1_DPTXFSIZ004"           ,           0x17F0010000110ull,  CVMX_CSR_DB_TYPE_NCB,   32,     912},
68658         {"USBC0_DSTS"                  ,           0x16F0010000808ull,  CVMX_CSR_DB_TYPE_NCB,   32,     913},
68659         {"USBC1_DSTS"                  ,           0x17F0010000808ull,  CVMX_CSR_DB_TYPE_NCB,   32,     913},
68660         {"USBC0_DTKNQR1"               ,           0x16F0010000820ull,  CVMX_CSR_DB_TYPE_NCB,   32,     914},
68661         {"USBC1_DTKNQR1"               ,           0x17F0010000820ull,  CVMX_CSR_DB_TYPE_NCB,   32,     914},
68662         {"USBC0_DTKNQR2"               ,           0x16F0010000824ull,  CVMX_CSR_DB_TYPE_NCB,   32,     915},
68663         {"USBC1_DTKNQR2"               ,           0x17F0010000824ull,  CVMX_CSR_DB_TYPE_NCB,   32,     915},
68664         {"USBC0_DTKNQR3"               ,           0x16F0010000830ull,  CVMX_CSR_DB_TYPE_NCB,   32,     916},
68665         {"USBC1_DTKNQR3"               ,           0x17F0010000830ull,  CVMX_CSR_DB_TYPE_NCB,   32,     916},
68666         {"USBC0_DTKNQR4"               ,           0x16F0010000834ull,  CVMX_CSR_DB_TYPE_NCB,   32,     917},
68667         {"USBC1_DTKNQR4"               ,           0x17F0010000834ull,  CVMX_CSR_DB_TYPE_NCB,   32,     917},
68668         {"USBC0_GAHBCFG"               ,           0x16F0010000008ull,  CVMX_CSR_DB_TYPE_NCB,   32,     918},
68669         {"USBC1_GAHBCFG"               ,           0x17F0010000008ull,  CVMX_CSR_DB_TYPE_NCB,   32,     918},
68670         {"USBC0_GHWCFG1"               ,           0x16F0010000044ull,  CVMX_CSR_DB_TYPE_NCB,   32,     919},
68671         {"USBC1_GHWCFG1"               ,           0x17F0010000044ull,  CVMX_CSR_DB_TYPE_NCB,   32,     919},
68672         {"USBC0_GHWCFG2"               ,           0x16F0010000048ull,  CVMX_CSR_DB_TYPE_NCB,   32,     920},
68673         {"USBC1_GHWCFG2"               ,           0x17F0010000048ull,  CVMX_CSR_DB_TYPE_NCB,   32,     920},
68674         {"USBC0_GHWCFG3"               ,           0x16F001000004Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     921},
68675         {"USBC1_GHWCFG3"               ,           0x17F001000004Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     921},
68676         {"USBC0_GHWCFG4"               ,           0x16F0010000050ull,  CVMX_CSR_DB_TYPE_NCB,   32,     922},
68677         {"USBC1_GHWCFG4"               ,           0x17F0010000050ull,  CVMX_CSR_DB_TYPE_NCB,   32,     922},
68678         {"USBC0_GINTMSK"               ,           0x16F0010000018ull,  CVMX_CSR_DB_TYPE_NCB,   32,     923},
68679         {"USBC1_GINTMSK"               ,           0x17F0010000018ull,  CVMX_CSR_DB_TYPE_NCB,   32,     923},
68680         {"USBC0_GINTSTS"               ,           0x16F0010000014ull,  CVMX_CSR_DB_TYPE_NCB,   32,     924},
68681         {"USBC1_GINTSTS"               ,           0x17F0010000014ull,  CVMX_CSR_DB_TYPE_NCB,   32,     924},
68682         {"USBC0_GNPTXFSIZ"             ,           0x16F0010000028ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
68683         {"USBC1_GNPTXFSIZ"             ,           0x17F0010000028ull,  CVMX_CSR_DB_TYPE_NCB,   32,     925},
68684         {"USBC0_GNPTXSTS"              ,           0x16F001000002Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     926},
68685         {"USBC1_GNPTXSTS"              ,           0x17F001000002Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     926},
68686         {"USBC0_GOTGCTL"               ,           0x16F0010000000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
68687         {"USBC1_GOTGCTL"               ,           0x17F0010000000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     927},
68688         {"USBC0_GOTGINT"               ,           0x16F0010000004ull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
68689         {"USBC1_GOTGINT"               ,           0x17F0010000004ull,  CVMX_CSR_DB_TYPE_NCB,   32,     928},
68690         {"USBC0_GRSTCTL"               ,           0x16F0010000010ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
68691         {"USBC1_GRSTCTL"               ,           0x17F0010000010ull,  CVMX_CSR_DB_TYPE_NCB,   32,     929},
68692         {"USBC0_GRXFSIZ"               ,           0x16F0010000024ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
68693         {"USBC1_GRXFSIZ"               ,           0x17F0010000024ull,  CVMX_CSR_DB_TYPE_NCB,   32,     930},
68694         {"USBC0_GRXSTSPD"              ,           0x16F0010040020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     931},
68695         {"USBC1_GRXSTSPD"              ,           0x17F0010040020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     931},
68696         {"USBC0_GRXSTSPH"              ,           0x16F0010000020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     932},
68697         {"USBC1_GRXSTSPH"              ,           0x17F0010000020ull,  CVMX_CSR_DB_TYPE_NCB,   32,     932},
68698         {"USBC0_GRXSTSRD"              ,           0x16F001004001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     933},
68699         {"USBC1_GRXSTSRD"              ,           0x17F001004001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     933},
68700         {"USBC0_GRXSTSRH"              ,           0x16F001000001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     934},
68701         {"USBC1_GRXSTSRH"              ,           0x17F001000001Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     934},
68702         {"USBC0_GSNPSID"               ,           0x16F0010000040ull,  CVMX_CSR_DB_TYPE_NCB,   32,     935},
68703         {"USBC1_GSNPSID"               ,           0x17F0010000040ull,  CVMX_CSR_DB_TYPE_NCB,   32,     935},
68704         {"USBC0_GUSBCFG"               ,           0x16F001000000Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
68705         {"USBC1_GUSBCFG"               ,           0x17F001000000Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     936},
68706         {"USBC0_HAINT"                 ,           0x16F0010000414ull,  CVMX_CSR_DB_TYPE_NCB,   32,     937},
68707         {"USBC1_HAINT"                 ,           0x17F0010000414ull,  CVMX_CSR_DB_TYPE_NCB,   32,     937},
68708         {"USBC0_HAINTMSK"              ,           0x16F0010000418ull,  CVMX_CSR_DB_TYPE_NCB,   32,     938},
68709         {"USBC1_HAINTMSK"              ,           0x17F0010000418ull,  CVMX_CSR_DB_TYPE_NCB,   32,     938},
68710         {"USBC0_HCCHAR000"             ,           0x16F0010000500ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68711         {"USBC0_HCCHAR001"             ,           0x16F0010000520ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68712         {"USBC0_HCCHAR002"             ,           0x16F0010000540ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68713         {"USBC0_HCCHAR003"             ,           0x16F0010000560ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68714         {"USBC0_HCCHAR004"             ,           0x16F0010000580ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68715         {"USBC0_HCCHAR005"             ,           0x16F00100005A0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68716         {"USBC0_HCCHAR006"             ,           0x16F00100005C0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68717         {"USBC0_HCCHAR007"             ,           0x16F00100005E0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68718         {"USBC1_HCCHAR000"             ,           0x17F0010000500ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68719         {"USBC1_HCCHAR001"             ,           0x17F0010000520ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68720         {"USBC1_HCCHAR002"             ,           0x17F0010000540ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68721         {"USBC1_HCCHAR003"             ,           0x17F0010000560ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68722         {"USBC1_HCCHAR004"             ,           0x17F0010000580ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68723         {"USBC1_HCCHAR005"             ,           0x17F00100005A0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68724         {"USBC1_HCCHAR006"             ,           0x17F00100005C0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68725         {"USBC1_HCCHAR007"             ,           0x17F00100005E0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     939},
68726         {"USBC0_HCFG"                  ,           0x16F0010000400ull,  CVMX_CSR_DB_TYPE_NCB,   32,     940},
68727         {"USBC1_HCFG"                  ,           0x17F0010000400ull,  CVMX_CSR_DB_TYPE_NCB,   32,     940},
68728         {"USBC0_HCINT000"              ,           0x16F0010000508ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68729         {"USBC0_HCINT001"              ,           0x16F0010000528ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68730         {"USBC0_HCINT002"              ,           0x16F0010000548ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68731         {"USBC0_HCINT003"              ,           0x16F0010000568ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68732         {"USBC0_HCINT004"              ,           0x16F0010000588ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68733         {"USBC0_HCINT005"              ,           0x16F00100005A8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68734         {"USBC0_HCINT006"              ,           0x16F00100005C8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68735         {"USBC0_HCINT007"              ,           0x16F00100005E8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68736         {"USBC1_HCINT000"              ,           0x17F0010000508ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68737         {"USBC1_HCINT001"              ,           0x17F0010000528ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68738         {"USBC1_HCINT002"              ,           0x17F0010000548ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68739         {"USBC1_HCINT003"              ,           0x17F0010000568ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68740         {"USBC1_HCINT004"              ,           0x17F0010000588ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68741         {"USBC1_HCINT005"              ,           0x17F00100005A8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68742         {"USBC1_HCINT006"              ,           0x17F00100005C8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68743         {"USBC1_HCINT007"              ,           0x17F00100005E8ull,  CVMX_CSR_DB_TYPE_NCB,   32,     941},
68744         {"USBC0_HCINTMSK000"           ,           0x16F001000050Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68745         {"USBC0_HCINTMSK001"           ,           0x16F001000052Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68746         {"USBC0_HCINTMSK002"           ,           0x16F001000054Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68747         {"USBC0_HCINTMSK003"           ,           0x16F001000056Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68748         {"USBC0_HCINTMSK004"           ,           0x16F001000058Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68749         {"USBC0_HCINTMSK005"           ,           0x16F00100005ACull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68750         {"USBC0_HCINTMSK006"           ,           0x16F00100005CCull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68751         {"USBC0_HCINTMSK007"           ,           0x16F00100005ECull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68752         {"USBC1_HCINTMSK000"           ,           0x17F001000050Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68753         {"USBC1_HCINTMSK001"           ,           0x17F001000052Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68754         {"USBC1_HCINTMSK002"           ,           0x17F001000054Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68755         {"USBC1_HCINTMSK003"           ,           0x17F001000056Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68756         {"USBC1_HCINTMSK004"           ,           0x17F001000058Cull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68757         {"USBC1_HCINTMSK005"           ,           0x17F00100005ACull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68758         {"USBC1_HCINTMSK006"           ,           0x17F00100005CCull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68759         {"USBC1_HCINTMSK007"           ,           0x17F00100005ECull,  CVMX_CSR_DB_TYPE_NCB,   32,     942},
68760         {"USBC0_HCSPLT000"             ,           0x16F0010000504ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68761         {"USBC0_HCSPLT001"             ,           0x16F0010000524ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68762         {"USBC0_HCSPLT002"             ,           0x16F0010000544ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68763         {"USBC0_HCSPLT003"             ,           0x16F0010000564ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68764         {"USBC0_HCSPLT004"             ,           0x16F0010000584ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68765         {"USBC0_HCSPLT005"             ,           0x16F00100005A4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68766         {"USBC0_HCSPLT006"             ,           0x16F00100005C4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68767         {"USBC0_HCSPLT007"             ,           0x16F00100005E4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68768         {"USBC1_HCSPLT000"             ,           0x17F0010000504ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68769         {"USBC1_HCSPLT001"             ,           0x17F0010000524ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68770         {"USBC1_HCSPLT002"             ,           0x17F0010000544ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68771         {"USBC1_HCSPLT003"             ,           0x17F0010000564ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68772         {"USBC1_HCSPLT004"             ,           0x17F0010000584ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68773         {"USBC1_HCSPLT005"             ,           0x17F00100005A4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68774         {"USBC1_HCSPLT006"             ,           0x17F00100005C4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68775         {"USBC1_HCSPLT007"             ,           0x17F00100005E4ull,  CVMX_CSR_DB_TYPE_NCB,   32,     943},
68776         {"USBC0_HCTSIZ000"             ,           0x16F0010000510ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68777         {"USBC0_HCTSIZ001"             ,           0x16F0010000530ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68778         {"USBC0_HCTSIZ002"             ,           0x16F0010000550ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68779         {"USBC0_HCTSIZ003"             ,           0x16F0010000570ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68780         {"USBC0_HCTSIZ004"             ,           0x16F0010000590ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68781         {"USBC0_HCTSIZ005"             ,           0x16F00100005B0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68782         {"USBC0_HCTSIZ006"             ,           0x16F00100005D0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68783         {"USBC0_HCTSIZ007"             ,           0x16F00100005F0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68784         {"USBC1_HCTSIZ000"             ,           0x17F0010000510ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68785         {"USBC1_HCTSIZ001"             ,           0x17F0010000530ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68786         {"USBC1_HCTSIZ002"             ,           0x17F0010000550ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68787         {"USBC1_HCTSIZ003"             ,           0x17F0010000570ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68788         {"USBC1_HCTSIZ004"             ,           0x17F0010000590ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68789         {"USBC1_HCTSIZ005"             ,           0x17F00100005B0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68790         {"USBC1_HCTSIZ006"             ,           0x17F00100005D0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68791         {"USBC1_HCTSIZ007"             ,           0x17F00100005F0ull,  CVMX_CSR_DB_TYPE_NCB,   32,     944},
68792         {"USBC0_HFIR"                  ,           0x16F0010000404ull,  CVMX_CSR_DB_TYPE_NCB,   32,     945},
68793         {"USBC1_HFIR"                  ,           0x17F0010000404ull,  CVMX_CSR_DB_TYPE_NCB,   32,     945},
68794         {"USBC0_HFNUM"                 ,           0x16F0010000408ull,  CVMX_CSR_DB_TYPE_NCB,   32,     946},
68795         {"USBC1_HFNUM"                 ,           0x17F0010000408ull,  CVMX_CSR_DB_TYPE_NCB,   32,     946},
68796         {"USBC0_HPRT"                  ,           0x16F0010000440ull,  CVMX_CSR_DB_TYPE_NCB,   32,     947},
68797         {"USBC1_HPRT"                  ,           0x17F0010000440ull,  CVMX_CSR_DB_TYPE_NCB,   32,     947},
68798         {"USBC0_HPTXFSIZ"              ,           0x16F0010000100ull,  CVMX_CSR_DB_TYPE_NCB,   32,     948},
68799         {"USBC1_HPTXFSIZ"              ,           0x17F0010000100ull,  CVMX_CSR_DB_TYPE_NCB,   32,     948},
68800         {"USBC0_HPTXSTS"               ,           0x16F0010000410ull,  CVMX_CSR_DB_TYPE_NCB,   32,     949},
68801         {"USBC1_HPTXSTS"               ,           0x17F0010000410ull,  CVMX_CSR_DB_TYPE_NCB,   32,     949},
68802         {"USBC0_NPTXDFIFO000"          ,           0x16F0010001000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68803         {"USBC0_NPTXDFIFO001"          ,           0x16F0010002000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68804         {"USBC0_NPTXDFIFO002"          ,           0x16F0010003000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68805         {"USBC0_NPTXDFIFO003"          ,           0x16F0010004000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68806         {"USBC0_NPTXDFIFO004"          ,           0x16F0010005000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68807         {"USBC0_NPTXDFIFO005"          ,           0x16F0010006000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68808         {"USBC0_NPTXDFIFO006"          ,           0x16F0010007000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68809         {"USBC0_NPTXDFIFO007"          ,           0x16F0010008000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68810         {"USBC1_NPTXDFIFO000"          ,           0x17F0010001000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68811         {"USBC1_NPTXDFIFO001"          ,           0x17F0010002000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68812         {"USBC1_NPTXDFIFO002"          ,           0x17F0010003000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68813         {"USBC1_NPTXDFIFO003"          ,           0x17F0010004000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68814         {"USBC1_NPTXDFIFO004"          ,           0x17F0010005000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68815         {"USBC1_NPTXDFIFO005"          ,           0x17F0010006000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68816         {"USBC1_NPTXDFIFO006"          ,           0x17F0010007000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68817         {"USBC1_NPTXDFIFO007"          ,           0x17F0010008000ull,  CVMX_CSR_DB_TYPE_NCB,   32,     950},
68818         {"USBC0_PCGCCTL"               ,           0x16F0010000E00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     951},
68819         {"USBC1_PCGCCTL"               ,           0x17F0010000E00ull,  CVMX_CSR_DB_TYPE_NCB,   32,     951},
68820         {"USBN0_BIST_STATUS"           ,           0x11800680007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     952},
68821         {"USBN1_BIST_STATUS"           ,           0x11800780007F8ull,  CVMX_CSR_DB_TYPE_RSL,   64,     952},
68822         {"USBN0_CLK_CTL"               ,           0x1180068000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     953},
68823         {"USBN1_CLK_CTL"               ,           0x1180078000010ull,  CVMX_CSR_DB_TYPE_RSL,   64,     953},
68824         {"USBN0_CTL_STATUS"            ,           0x16F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     954},
68825         {"USBN1_CTL_STATUS"            ,           0x17F0000000800ull,  CVMX_CSR_DB_TYPE_NCB,   64,     954},
68826         {"USBN0_DMA0_INB_CHN0"         ,           0x16F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     955},
68827         {"USBN1_DMA0_INB_CHN0"         ,           0x17F0000000818ull,  CVMX_CSR_DB_TYPE_NCB,   64,     955},
68828         {"USBN0_DMA0_INB_CHN1"         ,           0x16F0000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     956},
68829         {"USBN1_DMA0_INB_CHN1"         ,           0x17F0000000820ull,  CVMX_CSR_DB_TYPE_NCB,   64,     956},
68830         {"USBN0_DMA0_INB_CHN2"         ,           0x16F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     957},
68831         {"USBN1_DMA0_INB_CHN2"         ,           0x17F0000000828ull,  CVMX_CSR_DB_TYPE_NCB,   64,     957},
68832         {"USBN0_DMA0_INB_CHN3"         ,           0x16F0000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     958},
68833         {"USBN1_DMA0_INB_CHN3"         ,           0x17F0000000830ull,  CVMX_CSR_DB_TYPE_NCB,   64,     958},
68834         {"USBN0_DMA0_INB_CHN4"         ,           0x16F0000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     959},
68835         {"USBN1_DMA0_INB_CHN4"         ,           0x17F0000000838ull,  CVMX_CSR_DB_TYPE_NCB,   64,     959},
68836         {"USBN0_DMA0_INB_CHN5"         ,           0x16F0000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     960},
68837         {"USBN1_DMA0_INB_CHN5"         ,           0x17F0000000840ull,  CVMX_CSR_DB_TYPE_NCB,   64,     960},
68838         {"USBN0_DMA0_INB_CHN6"         ,           0x16F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     961},
68839         {"USBN1_DMA0_INB_CHN6"         ,           0x17F0000000848ull,  CVMX_CSR_DB_TYPE_NCB,   64,     961},
68840         {"USBN0_DMA0_INB_CHN7"         ,           0x16F0000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     962},
68841         {"USBN1_DMA0_INB_CHN7"         ,           0x17F0000000850ull,  CVMX_CSR_DB_TYPE_NCB,   64,     962},
68842         {"USBN0_DMA0_OUTB_CHN0"        ,           0x16F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     963},
68843         {"USBN1_DMA0_OUTB_CHN0"        ,           0x17F0000000858ull,  CVMX_CSR_DB_TYPE_NCB,   64,     963},
68844         {"USBN0_DMA0_OUTB_CHN1"        ,           0x16F0000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     964},
68845         {"USBN1_DMA0_OUTB_CHN1"        ,           0x17F0000000860ull,  CVMX_CSR_DB_TYPE_NCB,   64,     964},
68846         {"USBN0_DMA0_OUTB_CHN2"        ,           0x16F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     965},
68847         {"USBN1_DMA0_OUTB_CHN2"        ,           0x17F0000000868ull,  CVMX_CSR_DB_TYPE_NCB,   64,     965},
68848         {"USBN0_DMA0_OUTB_CHN3"        ,           0x16F0000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     966},
68849         {"USBN1_DMA0_OUTB_CHN3"        ,           0x17F0000000870ull,  CVMX_CSR_DB_TYPE_NCB,   64,     966},
68850         {"USBN0_DMA0_OUTB_CHN4"        ,           0x16F0000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     967},
68851         {"USBN1_DMA0_OUTB_CHN4"        ,           0x17F0000000878ull,  CVMX_CSR_DB_TYPE_NCB,   64,     967},
68852         {"USBN0_DMA0_OUTB_CHN5"        ,           0x16F0000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     968},
68853         {"USBN1_DMA0_OUTB_CHN5"        ,           0x17F0000000880ull,  CVMX_CSR_DB_TYPE_NCB,   64,     968},
68854         {"USBN0_DMA0_OUTB_CHN6"        ,           0x16F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     969},
68855         {"USBN1_DMA0_OUTB_CHN6"        ,           0x17F0000000888ull,  CVMX_CSR_DB_TYPE_NCB,   64,     969},
68856         {"USBN0_DMA0_OUTB_CHN7"        ,           0x16F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     970},
68857         {"USBN1_DMA0_OUTB_CHN7"        ,           0x17F0000000890ull,  CVMX_CSR_DB_TYPE_NCB,   64,     970},
68858         {"USBN0_DMA_TEST"              ,           0x16F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     971},
68859         {"USBN1_DMA_TEST"              ,           0x17F0000000808ull,  CVMX_CSR_DB_TYPE_NCB,   64,     971},
68860         {"USBN0_INT_ENB"               ,           0x1180068000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     972},
68861         {"USBN1_INT_ENB"               ,           0x1180078000008ull,  CVMX_CSR_DB_TYPE_RSL,   64,     972},
68862         {"USBN0_INT_SUM"               ,           0x1180068000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     973},
68863         {"USBN1_INT_SUM"               ,           0x1180078000000ull,  CVMX_CSR_DB_TYPE_RSL,   64,     973},
68864         {"USBN0_USBP_CTL_STATUS"       ,           0x1180068000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     974},
68865         {"USBN1_USBP_CTL_STATUS"       ,           0x1180078000018ull,  CVMX_CSR_DB_TYPE_RSL,   64,     974},
68866         {NULL,0,0,0,0}
68867 };
68868 static const CVMX_CSR_DB_FIELD_TYPE cvmx_csr_db_fields_cn52xx[] = {
68869         /* name                        ,        bit,    width,  csr,    type,   rst un, typ un, reset,  typical */
68870         {"RESERVED_0_1"                ,        0,      2,      0,      "RAZ",  0,      0,      0ull,   0ull},
68871         {"OUT_OVR"                     ,        2,      2,      0,      "R/W1C",        0,      0,      0ull,   0ull},
68872         {"RESERVED_4_21"               ,        4,      18,     0,      "RAZ",  0,      0,      0ull,   0ull},
68873         {"LOSTSTAT"                    ,        22,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
68874         {"RESERVED_23_25"              ,        23,     3,      0,      "RAZ",  1,      1,      0,      0},
68875         {"STATOVR"                     ,        26,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
68876         {"RESERVED_27_31"              ,        27,     5,      0,      "RAZ",  1,      1,      0,      0},
68877         {"OVRFLW"                      ,        32,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
68878         {"TXPOP"                       ,        33,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
68879         {"TXPSH"                       ,        34,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
68880         {"OVRFLW1"                     ,        35,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
68881         {"TXPOP1"                      ,        36,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
68882         {"TXPSH1"                      ,        37,     1,      0,      "R/W1C",        0,      0,      0ull,   0ull},
68883         {"RESERVED_38_63"              ,        38,     26,     0,      "RAZ",  1,      1,      0,      0},
68884         {"STATUS"                      ,        0,      10,     1,      "RO",   0,      0,      0ull,   0ull},
68885         {"RESERVED_10_63"              ,        10,     54,     1,      "RAZ",  1,      1,      0,      0},
68886         {"NCTL"                        ,        0,      5,      2,      "R/W",  0,      1,      16ull,  0},
68887         {"RESERVED_5_7"                ,        5,      3,      2,      "RAZ",  1,      1,      0,      0},
68888         {"PCTL"                        ,        8,      5,      2,      "R/W",  0,      1,      16ull,  0},
68889         {"RESERVED_13_15"              ,        13,     3,      2,      "RAZ",  1,      1,      0,      0},
68890         {"BYP_EN"                      ,        16,     1,      2,      "R/W",  0,      0,      0ull,   0ull},
68891         {"RESERVED_17_31"              ,        17,     15,     2,      "RAZ",  1,      1,      0,      0},
68892         {"NCTL1"                       ,        32,     5,      2,      "R/W",  0,      1,      16ull,  0},
68893         {"RESERVED_37_39"              ,        37,     3,      2,      "RAZ",  1,      1,      0,      0},
68894         {"PCTL1"                       ,        40,     5,      2,      "R/W",  0,      1,      16ull,  0},
68895         {"RESERVED_45_47"              ,        45,     3,      2,      "RAZ",  1,      1,      0,      0},
68896         {"BYP_EN1"                     ,        48,     1,      2,      "R/W",  0,      0,      0ull,   0ull},
68897         {"RESERVED_49_63"              ,        49,     15,     2,      "RAZ",  1,      1,      0,      0},
68898         {"RESERVED_0_0"                ,        0,      1,      3,      "RAZ",  1,      1,      0,      0},
68899         {"EN"                          ,        1,      1,      3,      "R/W",  0,      0,      0ull,   1ull},
68900         {"RESERVED_2_63"               ,        2,      62,     3,      "RAZ",  1,      1,      0,      0},
68901         {"EN"                          ,        0,      1,      4,      "R/W",  0,      1,      0ull,   0},
68902         {"SPEED"                       ,        1,      1,      4,      "RO",   0,      0,      0ull,   0ull},
68903         {"DUPLEX"                      ,        2,      1,      4,      "R/W",  0,      1,      1ull,   0},
68904         {"SLOTTIME"                    ,        3,      1,      4,      "RO",   0,      0,      0ull,   0ull},
68905         {"RX_EN"                       ,        4,      1,      4,      "R/W",  0,      1,      0ull,   0},
68906         {"TX_EN"                       ,        5,      1,      4,      "R/W",  0,      1,      0ull,   0},
68907         {"RESERVED_6_63"               ,        6,      58,     4,      "RAZ",  1,      1,      0,      0},
68908         {"ADR"                         ,        0,      64,     5,      "R/W",  0,      1,      0ull,   0},
68909         {"ADR"                         ,        0,      64,     6,      "R/W",  0,      1,      0ull,   0},
68910         {"ADR"                         ,        0,      64,     7,      "R/W",  0,      1,      0ull,   0},
68911         {"ADR"                         ,        0,      64,     8,      "R/W",  0,      1,      0ull,   0},
68912         {"ADR"                         ,        0,      64,     9,      "R/W",  0,      1,      0ull,   0},
68913         {"ADR"                         ,        0,      64,     10,     "R/W",  0,      1,      0ull,   0},
68914         {"EN"                          ,        0,      8,      11,     "R/W",  0,      1,      0ull,   0},
68915         {"RESERVED_8_63"               ,        8,      56,     11,     "RAZ",  1,      1,      0,      0},
68916         {"BCST"                        ,        0,      1,      12,     "R/W",  0,      1,      1ull,   0},
68917         {"MCST"                        ,        1,      2,      12,     "R/W",  0,      1,      0ull,   0},
68918         {"CAM_MODE"                    ,        3,      1,      12,     "R/W",  0,      1,      0ull,   0},
68919         {"RESERVED_4_63"               ,        4,      60,     12,     "RAZ",  1,      1,      0,      0},
68920         {"CNT"                         ,        0,      5,      13,     "R/W",  0,      0,      24ull,  24ull},
68921         {"RESERVED_5_63"               ,        5,      59,     13,     "RAZ",  1,      1,      0,      0},
68922         {"MINERR"                      ,        0,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
68923         {"RESERVED_1_1"                ,        1,      1,      14,     "RAZ",  0,      0,      0ull,   0ull},
68924         {"MAXERR"                      ,        2,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
68925         {"JABBER"                      ,        3,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
68926         {"FCSERR"                      ,        4,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
68927         {"ALNERR"                      ,        5,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
68928         {"LENERR"                      ,        6,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
68929         {"RCVERR"                      ,        7,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
68930         {"SKPERR"                      ,        8,      1,      14,     "R/W",  0,      0,      1ull,   1ull},
68931         {"RESERVED_9_63"               ,        9,      55,     14,     "RAZ",  1,      1,      0,      0},
68932         {"PRE_CHK"                     ,        0,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
68933         {"PRE_STRP"                    ,        1,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
68934         {"CTL_DRP"                     ,        2,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
68935         {"CTL_BCK"                     ,        3,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
68936         {"CTL_MCST"                    ,        4,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
68937         {"CTL_SMAC"                    ,        5,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
68938         {"PRE_FREE"                    ,        6,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
68939         {"VLAN_LEN"                    ,        7,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
68940         {"PAD_LEN"                     ,        8,      1,      15,     "R/W",  0,      0,      0ull,   0ull},
68941         {"PRE_ALIGN"                   ,        9,      1,      15,     "R/W",  0,      0,      1ull,   1ull},
68942         {"RESERVED_10_63"              ,        10,     54,     15,     "RAZ",  1,      1,      0,      0},
68943         {"LEN"                         ,        0,      16,     16,     "R/W",  0,      0,      1536ull,        1536ull},
68944         {"RESERVED_16_63"              ,        16,     48,     16,     "RAZ",  1,      1,      0,      0},
68945         {"LEN"                         ,        0,      16,     17,     "R/W",  0,      0,      64ull,  64ull},
68946         {"RESERVED_16_63"              ,        16,     48,     17,     "RAZ",  1,      1,      0,      0},
68947         {"IFG"                         ,        0,      4,      18,     "R/W",  0,      0,      12ull,  12ull},
68948         {"RESERVED_4_63"               ,        4,      60,     18,     "RAZ",  1,      1,      0,      0},
68949         {"MINERR"                      ,        0,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
68950         {"RESERVED_1_1"                ,        1,      1,      19,     "RAZ",  1,      1,      0,      0},
68951         {"MAXERR"                      ,        2,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
68952         {"JABBER"                      ,        3,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
68953         {"FCSERR"                      ,        4,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
68954         {"ALNERR"                      ,        5,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
68955         {"LENERR"                      ,        6,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
68956         {"RCVERR"                      ,        7,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
68957         {"SKPERR"                      ,        8,      1,      19,     "R/W",  0,      0,      0ull,   0ull},
68958         {"RESERVED_9_9"                ,        9,      1,      19,     "RAZ",  1,      1,      0,      0},
68959         {"OVRERR"                      ,        10,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
68960         {"PCTERR"                      ,        11,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
68961         {"RSVERR"                      ,        12,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
68962         {"FALERR"                      ,        13,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
68963         {"COLDET"                      ,        14,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
68964         {"IFGERR"                      ,        15,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
68965         {"RESERVED_16_18"              ,        16,     3,      19,     "RAZ",  1,      1,      0,      0},
68966         {"PAUSE_DRP"                   ,        19,     1,      19,     "R/W",  0,      0,      0ull,   0ull},
68967         {"RESERVED_20_63"              ,        20,     44,     19,     "RAZ",  1,      1,      0,      0},
68968         {"MINERR"                      ,        0,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68969         {"RESERVED_1_1"                ,        1,      1,      20,     "RAZ",  0,      0,      0ull,   0ull},
68970         {"MAXERR"                      ,        2,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68971         {"JABBER"                      ,        3,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68972         {"FCSERR"                      ,        4,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68973         {"ALNERR"                      ,        5,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68974         {"LENERR"                      ,        6,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68975         {"RCVERR"                      ,        7,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68976         {"SKPERR"                      ,        8,      1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68977         {"RESERVED_9_9"                ,        9,      1,      20,     "RAZ",  0,      0,      0ull,   0ull},
68978         {"OVRERR"                      ,        10,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68979         {"PCTERR"                      ,        11,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68980         {"RSVERR"                      ,        12,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68981         {"FALERR"                      ,        13,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68982         {"COLDET"                      ,        14,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68983         {"IFGERR"                      ,        15,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68984         {"RESERVED_16_18"              ,        16,     3,      20,     "RAZ",  0,      0,      0ull,   0ull},
68985         {"PAUSE_DRP"                   ,        19,     1,      20,     "R/W1C",        0,      0,      0ull,   0ull},
68986         {"RESERVED_20_63"              ,        20,     44,     20,     "RAZ",  1,      1,      0,      0},
68987         {"CNT"                         ,        0,      16,     21,     "R/W",  0,      0,      10240ull,       10240ull},
68988         {"RESERVED_16_63"              ,        16,     48,     21,     "RAZ",  1,      1,      0,      0},
68989         {"STATUS"                      ,        0,      16,     22,     "R/W1C",        0,      1,      0ull,   0},
68990         {"RESERVED_16_63"              ,        16,     48,     22,     "RAZ",  1,      1,      0,      0},
68991         {"RD_CLR"                      ,        0,      1,      23,     "R/W",  0,      0,      0ull,   0ull},
68992         {"RESERVED_1_63"               ,        1,      63,     23,     "RAZ",  1,      1,      0,      0},
68993         {"CNT"                         ,        0,      48,     24,     "RC/W", 0,      1,      0ull,   0},
68994         {"RESERVED_48_63"              ,        48,     16,     24,     "RAZ",  1,      1,      0,      0},
68995         {"CNT"                         ,        0,      48,     25,     "RC/W", 0,      1,      0ull,   0},
68996         {"RESERVED_48_63"              ,        48,     16,     25,     "RAZ",  1,      1,      0,      0},
68997         {"CNT"                         ,        0,      48,     26,     "RC/W", 0,      1,      0ull,   0},
68998         {"RESERVED_48_63"              ,        48,     16,     26,     "RAZ",  1,      1,      0,      0},
68999         {"CNT"                         ,        0,      48,     27,     "RC/W", 0,      1,      0ull,   0},
69000         {"RESERVED_48_63"              ,        48,     16,     27,     "RAZ",  1,      1,      0,      0},
69001         {"CNT"                         ,        0,      32,     28,     "RC/W", 0,      1,      0ull,   0},
69002         {"RESERVED_32_63"              ,        32,     32,     28,     "RAZ",  1,      1,      0,      0},
69003         {"CNT"                         ,        0,      32,     29,     "RC/W", 0,      1,      0ull,   0},
69004         {"RESERVED_32_63"              ,        32,     32,     29,     "RAZ",  1,      1,      0,      0},
69005         {"CNT"                         ,        0,      32,     30,     "RC/W", 0,      1,      0ull,   0},
69006         {"RESERVED_32_63"              ,        32,     32,     30,     "RAZ",  1,      1,      0,      0},
69007         {"CNT"                         ,        0,      32,     31,     "RC/W", 0,      1,      0ull,   0},
69008         {"RESERVED_32_63"              ,        32,     32,     31,     "RAZ",  1,      1,      0,      0},
69009         {"CNT"                         ,        0,      32,     32,     "RC/W", 0,      1,      0ull,   0},
69010         {"RESERVED_32_63"              ,        32,     32,     32,     "RAZ",  1,      1,      0,      0},
69011         {"LEN"                         ,        0,      7,      33,     "R/W",  0,      0,      0ull,   0ull},
69012         {"RESERVED_7_7"                ,        7,      1,      33,     "RAZ",  1,      1,      0,      0},
69013         {"FCSSEL"                      ,        8,      1,      33,     "R/W",  0,      0,      0ull,   0ull},
69014         {"RESERVED_9_63"               ,        9,      55,     33,     "RAZ",  1,      1,      0,      0},
69015         {"MARK"                        ,        0,      6,      34,     "R/W",  0,      0,      2ull,   2ull},
69016         {"RESERVED_6_63"               ,        6,      58,     34,     "RAZ",  1,      1,      0,      0},
69017         {"MARK"                        ,        0,      6,      35,     "R/W",  0,      0,      16ull,  16ull},
69018         {"RESERVED_6_63"               ,        6,      58,     35,     "RAZ",  1,      1,      0,      0},
69019         {"MARK"                        ,        0,      9,      36,     "R/W",  0,      0,      32ull,  32ull},
69020         {"RESERVED_9_63"               ,        9,      55,     36,     "RAZ",  1,      1,      0,      0},
69021         {"COMMIT"                      ,        0,      2,      37,     "RO",   0,      0,      0ull,   0ull},
69022         {"RESERVED_2_15"               ,        2,      14,     37,     "RAZ",  1,      1,      0,      0},
69023         {"DROP"                        ,        16,     2,      37,     "RO",   0,      0,      0ull,   0ull},
69024         {"RESERVED_18_63"              ,        18,     46,     37,     "RAZ",  1,      1,      0,      0},
69025         {"RX"                          ,        0,      2,      38,     "RC",   0,      0,      0ull,   0ull},
69026         {"RESERVED_2_3"                ,        2,      2,      38,     "RAZ",  1,      1,      0,      0},
69027         {"TX"                          ,        4,      2,      38,     "RC",   0,      0,      0ull,   0ull},
69028         {"RESERVED_6_63"               ,        6,      58,     38,     "RAZ",  1,      1,      0,      0},
69029         {"SMAC"                        ,        0,      48,     39,     "R/W",  0,      1,      0ull,   0},
69030         {"RESERVED_48_63"              ,        48,     16,     39,     "RAZ",  1,      1,      0,      0},
69031         {"CNT"                         ,        0,      16,     40,     "R/W1C",        0,      0,      0ull,   0ull},
69032         {"BP"                          ,        16,     1,      40,     "RO",   0,      0,      0ull,   0ull},
69033         {"RESERVED_17_63"              ,        17,     47,     40,     "RAZ",  1,      1,      0,      0},
69034         {"PREAMBLE"                    ,        0,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
69035         {"PAD"                         ,        1,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
69036         {"FCS"                         ,        2,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
69037         {"FORCE_FCS"                   ,        3,      1,      41,     "R/W",  0,      0,      1ull,   1ull},
69038         {"RESERVED_4_63"               ,        4,      60,     41,     "RAZ",  1,      1,      0,      0},
69039         {"XSCOL_EN"                    ,        0,      1,      42,     "R/W",  0,      0,      1ull,   1ull},
69040         {"XSDEF_EN"                    ,        1,      1,      42,     "R/W",  0,      0,      1ull,   1ull},
69041         {"RESERVED_2_63"               ,        2,      62,     42,     "RAZ",  1,      1,      0,      0},
69042         {"MIN_SIZE"                    ,        0,      8,      43,     "R/W",  0,      0,      59ull,  59ull},
69043         {"RESERVED_8_63"               ,        8,      56,     43,     "RAZ",  1,      1,      0,      0},
69044         {"INTERVAL"                    ,        0,      16,     44,     "R/W",  0,      1,      16ull,  0},
69045         {"RESERVED_16_63"              ,        16,     48,     44,     "RAZ",  1,      1,      0,      0},
69046         {"TIME"                        ,        0,      16,     45,     "R/W",  0,      1,      96ull,  0},
69047         {"RESERVED_16_63"              ,        16,     48,     45,     "RAZ",  1,      1,      0,      0},
69048         {"TIME"                        ,        0,      16,     46,     "RO",   1,      1,      0,      0},
69049         {"RESERVED_16_63"              ,        16,     48,     46,     "RAZ",  1,      1,      0,      0},
69050         {"SEND"                        ,        0,      1,      47,     "R/W",  0,      0,      1ull,   1ull},
69051         {"RESERVED_1_63"               ,        1,      63,     47,     "RAZ",  1,      1,      0,      0},
69052         {"TIME"                        ,        0,      16,     48,     "R/W",  0,      1,      0ull,   0},
69053         {"RESERVED_16_63"              ,        16,     48,     48,     "RAZ",  1,      1,      0,      0},
69054         {"XSCOL"                       ,        0,      32,     49,     "RC/W", 0,      1,      0ull,   0},
69055         {"XSDEF"                       ,        32,     32,     49,     "RC/W", 0,      1,      0ull,   0},
69056         {"MCOL"                        ,        0,      32,     50,     "RC/W", 0,      1,      0ull,   0},
69057         {"SCOL"                        ,        32,     32,     50,     "RC/W", 0,      1,      0ull,   0},
69058         {"OCTS"                        ,        0,      48,     51,     "RC/W", 0,      1,      0ull,   0},
69059         {"RESERVED_48_63"              ,        48,     16,     51,     "RAZ",  1,      1,      0,      0},
69060         {"PKTS"                        ,        0,      32,     52,     "RC/W", 0,      1,      0ull,   0},
69061         {"RESERVED_32_63"              ,        32,     32,     52,     "RAZ",  1,      1,      0,      0},
69062         {"HIST0"                       ,        0,      32,     53,     "RC/W", 0,      1,      0ull,   0},
69063         {"HIST1"                       ,        32,     32,     53,     "RC/W", 0,      1,      0ull,   0},
69064         {"HIST2"                       ,        0,      32,     54,     "RC/W", 0,      1,      0ull,   0},
69065         {"HIST3"                       ,        32,     32,     54,     "RC/W", 0,      1,      0ull,   0},
69066         {"HIST4"                       ,        0,      32,     55,     "RC/W", 0,      1,      0ull,   0},
69067         {"HIST5"                       ,        32,     32,     55,     "RC/W", 0,      1,      0ull,   0},
69068         {"HIST6"                       ,        0,      32,     56,     "RC/W", 0,      1,      0ull,   0},
69069         {"HIST7"                       ,        32,     32,     56,     "RC/W", 0,      1,      0ull,   0},
69070         {"BCST"                        ,        0,      32,     57,     "RC/W", 0,      1,      0ull,   0},
69071         {"MCST"                        ,        32,     32,     57,     "RC/W", 0,      1,      0ull,   0},
69072         {"CTL"                         ,        0,      32,     58,     "RC/W", 0,      1,      0ull,   0},
69073         {"UNDFLW"                      ,        32,     32,     58,     "RC/W", 0,      1,      0ull,   0},
69074         {"RD_CLR"                      ,        0,      1,      59,     "R/W",  0,      0,      0ull,   0ull},
69075         {"RESERVED_1_63"               ,        1,      63,     59,     "RAZ",  1,      1,      0,      0},
69076         {"CNT"                         ,        0,      6,      60,     "R/W",  0,      0,      16ull,  16ull},
69077         {"RESERVED_6_63"               ,        6,      58,     60,     "RAZ",  1,      1,      0,      0},
69078         {"BP"                          ,        0,      2,      61,     "RO",   0,      0,      0ull,   0ull},
69079         {"RESERVED_2_63"               ,        2,      62,     61,     "RAZ",  1,      1,      0,      0},
69080         {"LIMIT"                       ,        0,      5,      62,     "R/W",  0,      0,      16ull,  16ull},
69081         {"RESERVED_5_63"               ,        5,      59,     62,     "RAZ",  1,      1,      0,      0},
69082         {"IFG1"                        ,        0,      4,      63,     "R/W",  0,      1,      8ull,   0},
69083         {"IFG2"                        ,        4,      4,      63,     "R/W",  0,      1,      4ull,   0},
69084         {"RESERVED_8_63"               ,        8,      56,     63,     "RAZ",  1,      1,      0,      0},
69085         {"PKO_NXA"                     ,        0,      1,      64,     "R/W",  0,      0,      0ull,   0ull},
69086         {"RESERVED_1_1"                ,        1,      1,      64,     "RAZ",  1,      1,      0,      0},
69087         {"UNDFLW"                      ,        2,      2,      64,     "R/W",  0,      0,      0ull,   0ull},
69088         {"RESERVED_4_7"                ,        4,      4,      64,     "RAZ",  1,      1,      0,      0},
69089         {"XSCOL"                       ,        8,      2,      64,     "R/W",  0,      0,      0ull,   0ull},
69090         {"RESERVED_10_11"              ,        10,     2,      64,     "RAZ",  1,      1,      0,      0},
69091         {"XSDEF"                       ,        12,     2,      64,     "R/W",  0,      0,      0ull,   0ull},
69092         {"RESERVED_14_15"              ,        14,     2,      64,     "RAZ",  1,      1,      0,      0},
69093         {"LATE_COL"                    ,        16,     2,      64,     "R/W",  0,      0,      0ull,   0ull},
69094         {"RESERVED_18_63"              ,        18,     46,     64,     "RAZ",  1,      1,      0,      0},
69095         {"PKO_NXA"                     ,        0,      1,      65,     "R/W1C",        0,      0,      0ull,   0ull},
69096         {"RESERVED_1_1"                ,        1,      1,      65,     "RAZ",  1,      1,      0,      0},
69097         {"UNDFLW"                      ,        2,      2,      65,     "R/W1C",        0,      0,      0ull,   0ull},
69098         {"RESERVED_4_7"                ,        4,      4,      65,     "RAZ",  1,      1,      0,      0},
69099         {"XSCOL"                       ,        8,      2,      65,     "R/W1C",        0,      0,      0ull,   0ull},
69100         {"RESERVED_10_11"              ,        10,     2,      65,     "RAZ",  1,      1,      0,      0},
69101         {"XSDEF"                       ,        12,     2,      65,     "R/W1C",        0,      0,      0ull,   0ull},
69102         {"RESERVED_14_15"              ,        14,     2,      65,     "RAZ",  1,      1,      0,      0},
69103         {"LATE_COL"                    ,        16,     2,      65,     "R/W1C",        0,      0,      0ull,   0ull},
69104         {"RESERVED_18_63"              ,        18,     46,     65,     "RAZ",  1,      1,      0,      0},
69105         {"JAM"                         ,        0,      8,      66,     "R/W",  0,      1,      238ull, 0},
69106         {"RESERVED_8_63"               ,        8,      56,     66,     "RAZ",  1,      1,      0,      0},
69107         {"LFSR"                        ,        0,      16,     67,     "R/W",  0,      1,      65535ull,       0},
69108         {"RESERVED_16_63"              ,        16,     48,     67,     "RAZ",  1,      1,      0,      0},
69109         {"IGN_FULL"                    ,        0,      2,      68,     "R/W",  0,      0,      0ull,   0ull},
69110         {"RESERVED_2_3"                ,        2,      2,      68,     "RAZ",  1,      1,      0,      0},
69111         {"BP"                          ,        4,      2,      68,     "R/W",  0,      0,      0ull,   0ull},
69112         {"RESERVED_6_7"                ,        6,      2,      68,     "RAZ",  1,      1,      0,      0},
69113         {"EN"                          ,        8,      2,      68,     "R/W",  0,      0,      0ull,   0ull},
69114         {"RESERVED_10_63"              ,        10,     54,     68,     "RAZ",  1,      1,      0,      0},
69115         {"DMAC"                        ,        0,      48,     69,     "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
69116         {"RESERVED_48_63"              ,        48,     16,     69,     "RAZ",  1,      1,      0,      0},
69117         {"TYPE"                        ,        0,      16,     70,     "R/W",  0,      0,      34824ull,       34824ull},
69118         {"RESERVED_16_63"              ,        16,     48,     70,     "RAZ",  1,      1,      0,      0},
69119         {"BIST"                        ,        0,      3,      71,     "RO",   0,      0,      0ull,   0ull},
69120         {"RESERVED_3_63"               ,        3,      61,     71,     "RAZ",  1,      1,      0,      0},
69121         {"DINT"                        ,        0,      4,      72,     "WO",   0,      0,      0ull,   0ull},
69122         {"RESERVED_4_63"               ,        4,      60,     72,     "RAZ",  1,      1,      0,      0},
69123         {"FUSE"                        ,        0,      4,      73,     "RO",   1,      1,      0,      0},
69124         {"RESERVED_4_63"               ,        4,      60,     73,     "RAZ",  1,      1,      0,      0},
69125         {"GSTOP"                       ,        0,      1,      74,     "R/W",  0,      0,      0ull,   0ull},
69126         {"RESERVED_1_63"               ,        1,      63,     74,     "RAZ",  1,      1,      0,      0},
69127         {"WORKQ"                       ,        0,      16,     75,     "R/W",  0,      0,      0ull,   0ull},
69128         {"GPIO"                        ,        16,     16,     75,     "R/W",  0,      0,      0ull,   0ull},
69129         {"MBOX"                        ,        32,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
69130         {"UART"                        ,        34,     2,      75,     "R/W",  0,      0,      0ull,   0ull},
69131         {"PCI_INT"                     ,        36,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
69132         {"PCI_MSI"                     ,        40,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
69133         {"RESERVED_44_44"              ,        44,     1,      75,     "RAZ",  1,      1,      0,      0},
69134         {"TWSI"                        ,        45,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69135         {"RML"                         ,        46,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69136         {"TRACE"                       ,        47,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69137         {"GMX_DRP"                     ,        48,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69138         {"RESERVED_49_49"              ,        49,     1,      75,     "RAZ",  0,      0,      0ull,   0ull},
69139         {"IPD_DRP"                     ,        50,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69140         {"RESERVED_51_51"              ,        51,     1,      75,     "RAZ",  0,      0,      0ull,   0ull},
69141         {"TIMER"                       ,        52,     4,      75,     "R/W",  0,      0,      0ull,   0ull},
69142         {"USB"                         ,        56,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69143         {"RESERVED_57_58"              ,        57,     2,      75,     "RAZ",  0,      0,      0ull,   0ull},
69144         {"TWSI2"                       ,        59,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69145         {"POWIQ"                       ,        60,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69146         {"IPDPPTHR"                    ,        61,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69147         {"MII"                         ,        62,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69148         {"BOOTDMA"                     ,        63,     1,      75,     "R/W",  0,      0,      0ull,   0ull},
69149         {"WORKQ"                       ,        0,      16,     76,     "R/W1C",        0,      0,      0ull,   0ull},
69150         {"GPIO"                        ,        16,     16,     76,     "R/W1C",        0,      0,      0ull,   0ull},
69151         {"MBOX"                        ,        32,     2,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69152         {"UART"                        ,        34,     2,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69153         {"PCI_INT"                     ,        36,     4,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69154         {"PCI_MSI"                     ,        40,     4,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69155         {"RESERVED_44_44"              ,        44,     1,      76,     "RAZ",  1,      1,      0,      0},
69156         {"TWSI"                        ,        45,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69157         {"RML"                         ,        46,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69158         {"TRACE"                       ,        47,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69159         {"GMX_DRP"                     ,        48,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69160         {"RESERVED_49_49"              ,        49,     1,      76,     "RAZ",  0,      0,      0ull,   0ull},
69161         {"IPD_DRP"                     ,        50,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69162         {"RESERVED_51_51"              ,        51,     1,      76,     "RAZ",  0,      0,      0ull,   0ull},
69163         {"TIMER"                       ,        52,     4,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69164         {"USB"                         ,        56,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69165         {"RESERVED_57_58"              ,        57,     2,      76,     "RAZ",  0,      0,      0ull,   0ull},
69166         {"TWSI2"                       ,        59,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69167         {"POWIQ"                       ,        60,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69168         {"IPDPPTHR"                    ,        61,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69169         {"MII"                         ,        62,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69170         {"BOOTDMA"                     ,        63,     1,      76,     "R/W1C",        0,      0,      0ull,   0ull},
69171         {"WORKQ"                       ,        0,      16,     77,     "R/W1", 0,      0,      0ull,   0ull},
69172         {"GPIO"                        ,        16,     16,     77,     "R/W1", 0,      0,      0ull,   0ull},
69173         {"MBOX"                        ,        32,     2,      77,     "R/W1", 0,      0,      0ull,   0ull},
69174         {"UART"                        ,        34,     2,      77,     "R/W1", 0,      0,      0ull,   0ull},
69175         {"PCI_INT"                     ,        36,     4,      77,     "R/W1", 0,      0,      0ull,   0ull},
69176         {"PCI_MSI"                     ,        40,     4,      77,     "R/W1", 0,      0,      0ull,   0ull},
69177         {"RESERVED_44_44"              ,        44,     1,      77,     "RAZ",  1,      1,      0,      0},
69178         {"TWSI"                        ,        45,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69179         {"RML"                         ,        46,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69180         {"TRACE"                       ,        47,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69181         {"GMX_DRP"                     ,        48,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69182         {"RESERVED_49_49"              ,        49,     1,      77,     "RAZ",  0,      0,      0ull,   0ull},
69183         {"IPD_DRP"                     ,        50,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69184         {"RESERVED_51_51"              ,        51,     1,      77,     "RAZ",  0,      0,      0ull,   0ull},
69185         {"TIMER"                       ,        52,     4,      77,     "R/W1", 0,      0,      0ull,   0ull},
69186         {"USB"                         ,        56,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69187         {"RESERVED_57_58"              ,        57,     2,      77,     "RAZ",  0,      0,      0ull,   0ull},
69188         {"TWSI2"                       ,        59,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69189         {"POWIQ"                       ,        60,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69190         {"IPDPPTHR"                    ,        61,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69191         {"MII"                         ,        62,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69192         {"BOOTDMA"                     ,        63,     1,      77,     "R/W1", 0,      0,      0ull,   0ull},
69193         {"WDOG"                        ,        0,      4,      78,     "R/W",  0,      0,      0ull,   0ull},
69194         {"RESERVED_4_15"               ,        4,      12,     78,     "RAZ",  1,      1,      0,      0},
69195         {"UART2"                       ,        16,     1,      78,     "R/W",  0,      0,      0ull,   0ull},
69196         {"USB1"                        ,        17,     1,      78,     "R/W",  0,      0,      0ull,   0ull},
69197         {"MII1"                        ,        18,     1,      78,     "R/W",  0,      0,      0ull,   0ull},
69198         {"NAND"                        ,        19,     1,      78,     "R/W",  0,      0,      0ull,   0ull},
69199         {"RESERVED_20_63"              ,        20,     44,     78,     "RAZ",  1,      1,      0,      0},
69200         {"WDOG"                        ,        0,      4,      79,     "R/W1C",        0,      0,      0ull,   0ull},
69201         {"RESERVED_4_15"               ,        4,      12,     79,     "RAZ",  1,      1,      0,      0},
69202         {"UART2"                       ,        16,     1,      79,     "R/W1C",        0,      0,      0ull,   0ull},
69203         {"USB1"                        ,        17,     1,      79,     "R/W1C",        0,      0,      0ull,   0ull},
69204         {"MII1"                        ,        18,     1,      79,     "R/W1C",        0,      0,      0ull,   0ull},
69205         {"NAND"                        ,        19,     1,      79,     "R/W1C",        0,      0,      0ull,   0ull},
69206         {"RESERVED_20_63"              ,        20,     44,     79,     "RAZ",  1,      1,      0,      0},
69207         {"WDOG"                        ,        0,      4,      80,     "R/W1", 0,      0,      0ull,   0ull},
69208         {"RESERVED_4_15"               ,        4,      12,     80,     "RAZ",  1,      1,      0,      0},
69209         {"UART2"                       ,        16,     1,      80,     "R/W1", 0,      0,      0ull,   0ull},
69210         {"USB1"                        ,        17,     1,      80,     "R/W1", 0,      0,      0ull,   0ull},
69211         {"MII1"                        ,        18,     1,      80,     "R/W1", 0,      0,      0ull,   0ull},
69212         {"NAND"                        ,        19,     1,      80,     "R/W1", 0,      0,      0ull,   0ull},
69213         {"RESERVED_20_63"              ,        20,     44,     80,     "RAZ",  1,      1,      0,      0},
69214         {"WORKQ"                       ,        0,      16,     81,     "R/W",  0,      0,      0ull,   0ull},
69215         {"GPIO"                        ,        16,     16,     81,     "R/W",  0,      0,      0ull,   0ull},
69216         {"MBOX"                        ,        32,     2,      81,     "R/W",  0,      0,      0ull,   0ull},
69217         {"UART"                        ,        34,     2,      81,     "R/W",  0,      0,      0ull,   0ull},
69218         {"PCI_INT"                     ,        36,     4,      81,     "R/W",  0,      0,      0ull,   0ull},
69219         {"PCI_MSI"                     ,        40,     4,      81,     "R/W",  0,      0,      0ull,   0ull},
69220         {"RESERVED_44_44"              ,        44,     1,      81,     "RAZ",  1,      1,      0,      0},
69221         {"TWSI"                        ,        45,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69222         {"RML"                         ,        46,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69223         {"TRACE"                       ,        47,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69224         {"GMX_DRP"                     ,        48,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69225         {"RESERVED_49_49"              ,        49,     1,      81,     "RAZ",  0,      0,      0ull,   0ull},
69226         {"IPD_DRP"                     ,        50,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69227         {"RESERVED_51_51"              ,        51,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69228         {"TIMER"                       ,        52,     4,      81,     "R/W",  0,      0,      0ull,   0ull},
69229         {"USB"                         ,        56,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69230         {"RESERVED_57_58"              ,        57,     2,      81,     "R/W",  0,      0,      0ull,   0ull},
69231         {"TWSI2"                       ,        59,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69232         {"POWIQ"                       ,        60,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69233         {"IPDPPTHR"                    ,        61,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69234         {"MII"                         ,        62,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69235         {"BOOTDMA"                     ,        63,     1,      81,     "R/W",  0,      0,      0ull,   0ull},
69236         {"WORKQ"                       ,        0,      16,     82,     "R/W1C",        0,      0,      0ull,   0ull},
69237         {"GPIO"                        ,        16,     16,     82,     "R/W1C",        0,      0,      0ull,   0ull},
69238         {"MBOX"                        ,        32,     2,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69239         {"UART"                        ,        34,     2,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69240         {"PCI_INT"                     ,        36,     4,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69241         {"PCI_MSI"                     ,        40,     4,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69242         {"RESERVED_44_44"              ,        44,     1,      82,     "RAZ",  1,      1,      0,      0},
69243         {"TWSI"                        ,        45,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69244         {"RML"                         ,        46,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69245         {"TRACE"                       ,        47,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69246         {"GMX_DRP"                     ,        48,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69247         {"RESERVED_49_49"              ,        49,     1,      82,     "RAZ",  0,      0,      0ull,   0ull},
69248         {"IPD_DRP"                     ,        50,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69249         {"RESERVED_51_51"              ,        51,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69250         {"TIMER"                       ,        52,     4,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69251         {"USB"                         ,        56,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69252         {"RESERVED_57_58"              ,        57,     2,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69253         {"TWSI2"                       ,        59,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69254         {"POWIQ"                       ,        60,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69255         {"IPDPPTHR"                    ,        61,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69256         {"MII"                         ,        62,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69257         {"BOOTDMA"                     ,        63,     1,      82,     "R/W1C",        0,      0,      0ull,   0ull},
69258         {"WORKQ"                       ,        0,      16,     83,     "R/W1", 0,      0,      0ull,   0ull},
69259         {"GPIO"                        ,        16,     16,     83,     "R/W1", 0,      0,      0ull,   0ull},
69260         {"MBOX"                        ,        32,     2,      83,     "R/W1", 0,      0,      0ull,   0ull},
69261         {"UART"                        ,        34,     2,      83,     "R/W1", 0,      0,      0ull,   0ull},
69262         {"PCI_INT"                     ,        36,     4,      83,     "R/W1", 0,      0,      0ull,   0ull},
69263         {"PCI_MSI"                     ,        40,     4,      83,     "R/W1", 0,      0,      0ull,   0ull},
69264         {"RESERVED_44_44"              ,        44,     1,      83,     "RAZ",  1,      1,      0,      0},
69265         {"TWSI"                        ,        45,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69266         {"RML"                         ,        46,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69267         {"TRACE"                       ,        47,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69268         {"GMX_DRP"                     ,        48,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69269         {"RESERVED_49_49"              ,        49,     1,      83,     "RAZ",  0,      0,      0ull,   0ull},
69270         {"IPD_DRP"                     ,        50,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69271         {"RESERVED_51_51"              ,        51,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69272         {"TIMER"                       ,        52,     4,      83,     "R/W1", 0,      0,      0ull,   0ull},
69273         {"USB"                         ,        56,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69274         {"RESERVED_57_58"              ,        57,     2,      83,     "R/W1", 0,      0,      0ull,   0ull},
69275         {"TWSI2"                       ,        59,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69276         {"POWIQ"                       ,        60,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69277         {"IPDPPTHR"                    ,        61,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69278         {"MII"                         ,        62,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69279         {"BOOTDMA"                     ,        63,     1,      83,     "R/W1", 0,      0,      0ull,   0ull},
69280         {"WDOG"                        ,        0,      4,      84,     "R/W",  0,      0,      0ull,   0ull},
69281         {"RESERVED_4_15"               ,        4,      12,     84,     "RAZ",  1,      1,      0,      0},
69282         {"UART2"                       ,        16,     1,      84,     "R/W",  0,      0,      0ull,   0ull},
69283         {"USB1"                        ,        17,     1,      84,     "R/W",  0,      0,      0ull,   0ull},
69284         {"MII1"                        ,        18,     1,      84,     "R/W",  0,      0,      0ull,   0ull},
69285         {"NAND"                        ,        19,     1,      84,     "R/W",  0,      0,      0ull,   0ull},
69286         {"RESERVED_20_63"              ,        20,     44,     84,     "RAZ",  1,      1,      0,      0},
69287         {"WDOG"                        ,        0,      4,      85,     "R/W1C",        0,      0,      0ull,   0ull},
69288         {"RESERVED_4_15"               ,        4,      12,     85,     "RAZ",  1,      1,      0,      0},
69289         {"UART2"                       ,        16,     1,      85,     "R/W1C",        0,      0,      0ull,   0ull},
69290         {"USB1"                        ,        17,     1,      85,     "R/W1C",        0,      0,      0ull,   0ull},
69291         {"MII1"                        ,        18,     1,      85,     "R/W1C",        0,      0,      0ull,   0ull},
69292         {"NAND"                        ,        19,     1,      85,     "R/W1C",        0,      0,      0ull,   0ull},
69293         {"RESERVED_20_63"              ,        20,     44,     85,     "RAZ",  1,      1,      0,      0},
69294         {"WDOG"                        ,        0,      4,      86,     "R/W1", 0,      0,      0ull,   0ull},
69295         {"RESERVED_4_15"               ,        4,      12,     86,     "RAZ",  1,      1,      0,      0},
69296         {"UART2"                       ,        16,     1,      86,     "R/W1", 0,      0,      0ull,   0ull},
69297         {"USB1"                        ,        17,     1,      86,     "R/W1", 0,      0,      0ull,   0ull},
69298         {"MII1"                        ,        18,     1,      86,     "R/W1", 0,      0,      0ull,   0ull},
69299         {"NAND"                        ,        19,     1,      86,     "R/W1", 0,      0,      0ull,   0ull},
69300         {"RESERVED_20_63"              ,        20,     44,     86,     "RAZ",  1,      1,      0,      0},
69301         {"WORKQ"                       ,        0,      16,     87,     "RO",   0,      0,      0ull,   0ull},
69302         {"GPIO"                        ,        16,     16,     87,     "RO",   0,      0,      0ull,   0ull},
69303         {"MBOX"                        ,        32,     2,      87,     "RO",   0,      0,      0ull,   0ull},
69304         {"UART"                        ,        34,     2,      87,     "RO",   0,      0,      0ull,   0ull},
69305         {"PCI_INT"                     ,        36,     4,      87,     "RO",   0,      0,      0ull,   0ull},
69306         {"PCI_MSI"                     ,        40,     4,      87,     "RO",   0,      0,      0ull,   0ull},
69307         {"WDOG_SUM"                    ,        44,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69308         {"TWSI"                        ,        45,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69309         {"RML"                         ,        46,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69310         {"TRACE"                       ,        47,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69311         {"GMX_DRP"                     ,        48,     1,      87,     "R/W1C",        0,      0,      0ull,   0ull},
69312         {"RESERVED_49_49"              ,        49,     1,      87,     "RAZ",  1,      1,      0,      0},
69313         {"IPD_DRP"                     ,        50,     1,      87,     "R/W1C",        0,      0,      0ull,   0ull},
69314         {"RESERVED_51_51"              ,        51,     1,      87,     "RAZ",  0,      0,      0ull,   0ull},
69315         {"TIMER"                       ,        52,     4,      87,     "R/W1C",        0,      0,      0ull,   0ull},
69316         {"USB"                         ,        56,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69317         {"RESERVED_57_58"              ,        57,     2,      87,     "RAZ",  0,      0,      0ull,   0ull},
69318         {"TWSI2"                       ,        59,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69319         {"POWIQ"                       ,        60,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69320         {"IPDPPTHR"                    ,        61,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69321         {"MII"                         ,        62,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69322         {"BOOTDMA"                     ,        63,     1,      87,     "RO",   0,      0,      0ull,   0ull},
69323         {"WORKQ"                       ,        0,      16,     88,     "RO",   0,      0,      0ull,   0ull},
69324         {"GPIO"                        ,        16,     16,     88,     "RO",   0,      0,      0ull,   0ull},
69325         {"MBOX"                        ,        32,     2,      88,     "RO",   0,      0,      0ull,   0ull},
69326         {"UART"                        ,        34,     2,      88,     "RO",   0,      0,      0ull,   0ull},
69327         {"PCI_INT"                     ,        36,     4,      88,     "RO",   0,      0,      0ull,   0ull},
69328         {"PCI_MSI"                     ,        40,     4,      88,     "RO",   0,      0,      0ull,   0ull},
69329         {"WDOG_SUM"                    ,        44,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69330         {"TWSI"                        ,        45,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69331         {"RML"                         ,        46,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69332         {"TRACE"                       ,        47,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69333         {"GMX_DRP"                     ,        48,     1,      88,     "R/W1C",        0,      0,      0ull,   0ull},
69334         {"RESERVED_49_49"              ,        49,     1,      88,     "RAZ",  0,      0,      0ull,   0ull},
69335         {"IPD_DRP"                     ,        50,     1,      88,     "R/W1C",        0,      0,      0ull,   0ull},
69336         {"RESERVED_51_51"              ,        51,     1,      88,     "RAZ",  0,      0,      0ull,   0ull},
69337         {"TIMER"                       ,        52,     4,      88,     "R/W1C",        0,      0,      0ull,   0ull},
69338         {"USB"                         ,        56,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69339         {"RESERVED_57_58"              ,        57,     2,      88,     "RAZ",  0,      0,      0ull,   0ull},
69340         {"TWSI2"                       ,        59,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69341         {"POWIQ"                       ,        60,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69342         {"IPDPPTHR"                    ,        61,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69343         {"MII"                         ,        62,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69344         {"BOOTDMA"                     ,        63,     1,      88,     "RO",   0,      0,      0ull,   0ull},
69345         {"WDOG"                        ,        0,      4,      89,     "RO",   0,      0,      0ull,   0ull},
69346         {"RESERVED_4_15"               ,        4,      12,     89,     "RAZ",  1,      1,      0,      0},
69347         {"UART2"                       ,        16,     1,      89,     "RO",   0,      0,      0ull,   0ull},
69348         {"USB1"                        ,        17,     1,      89,     "RO",   0,      0,      0ull,   0ull},
69349         {"MII1"                        ,        18,     1,      89,     "RO",   0,      0,      0ull,   0ull},
69350         {"NAND"                        ,        19,     1,      89,     "RO",   0,      0,      0ull,   0ull},
69351         {"RESERVED_20_63"              ,        20,     44,     89,     "RAZ",  1,      1,      0,      0},
69352         {"BITS"                        ,        0,      32,     90,     "R/W1C",        0,      0,      0ull,   0ull},
69353         {"RESERVED_32_63"              ,        32,     32,     90,     "RAZ",  1,      1,      0,      0},
69354         {"BITS"                        ,        0,      32,     91,     "R/W1", 0,      0,      0ull,   0ull},
69355         {"RESERVED_32_63"              ,        32,     32,     91,     "RAZ",  1,      1,      0,      0},
69356         {"NMI"                         ,        0,      4,      92,     "WO",   0,      0,      0ull,   0ull},
69357         {"RESERVED_4_63"               ,        4,      60,     92,     "RAZ",  1,      1,      0,      0},
69358         {"INTR"                        ,        0,      2,      93,     "R/W",  0,      0,      0ull,   0ull},
69359         {"RESERVED_2_63"               ,        2,      62,     93,     "RAZ",  1,      1,      0,      0},
69360         {"PPDBG"                       ,        0,      4,      94,     "RO",   0,      0,      0ull,   0ull},
69361         {"RESERVED_4_63"               ,        4,      60,     94,     "RAZ",  1,      1,      0,      0},
69362         {"POKE"                        ,        0,      64,     95,     "RAZ",  1,      1,      0,      0},
69363         {"RST0"                        ,        0,      1,      96,     "R/W",  1,      1,      0,      0},
69364         {"RST"                         ,        1,      3,      96,     "R/W",  0,      0,      32767ull,       0ull},
69365         {"RESERVED_4_63"               ,        4,      60,     96,     "RAZ",  1,      1,      0,      0},
69366         {"QLM_DCOK"                    ,        0,      2,      97,     "R/W",  0,      0,      1ull,   1ull},
69367         {"RESERVED_2_63"               ,        2,      62,     97,     "RAZ",  1,      1,      0,      0},
69368         {"BYPASS"                      ,        0,      2,      98,     "R/W",  0,      1,      0ull,   0},
69369         {"RESERVED_2_3"                ,        2,      2,      98,     "RAZ",  1,      1,      0,      0},
69370         {"MUX_SEL"                     ,        4,      1,      98,     "R/W",  0,      1,      0ull,   0},
69371         {"RESERVED_5_7"                ,        5,      3,      98,     "RAZ",  1,      1,      0,      0},
69372         {"CLK_DIV"                     ,        8,      3,      98,     "R/W",  0,      1,      0ull,   0},
69373         {"RESERVED_11_63"              ,        11,     53,     98,     "RAZ",  1,      1,      0,      0},
69374         {"SHFT_REG"                    ,        0,      32,     99,     "R/W",  0,      1,      0ull,   0},
69375         {"SHFT_CNT"                    ,        32,     5,      99,     "R/W",  0,      1,      0ull,   0},
69376         {"RESERVED_37_39"              ,        37,     3,      99,     "RAZ",  1,      1,      0,      0},
69377         {"SELECT"                      ,        40,     2,      99,     "R/W",  0,      1,      0ull,   0},
69378         {"RESERVED_42_60"              ,        42,     19,     99,     "RAZ",  1,      1,      0,      0},
69379         {"UPDATE"                      ,        61,     1,      99,     "R/W",  0,      1,      0ull,   0},
69380         {"SHIFT"                       ,        62,     1,      99,     "R/W",  0,      1,      0ull,   0},
69381         {"CAPTURE"                     ,        63,     1,      99,     "R/W",  0,      1,      0ull,   0},
69382         {"SOFT_BIST"                   ,        0,      1,      100,    "R/W",  0,      0,      0ull,   0ull},
69383         {"RESERVED_1_63"               ,        1,      63,     100,    "RAZ",  1,      1,      0,      0},
69384         {"SOFT_PRST"                   ,        0,      1,      101,    "R/W",  0,      0,      1ull,   0ull},
69385         {"RESERVED_1_63"               ,        1,      63,     101,    "RAZ",  1,      1,      0,      0},
69386         {"SOFT_PRST"                   ,        0,      1,      102,    "R/W",  0,      0,      1ull,   0ull},
69387         {"RESERVED_1_63"               ,        1,      63,     102,    "RAZ",  1,      1,      0,      0},
69388         {"SOFT_RST"                    ,        0,      1,      103,    "WO",   0,      0,      0ull,   0ull},
69389         {"RESERVED_1_63"               ,        1,      63,     103,    "RAZ",  1,      1,      0,      0},
69390         {"LEN"                         ,        0,      36,     104,    "R/W",  0,      0,      0ull,   0ull},
69391         {"ONE_SHOT"                    ,        36,     1,      104,    "R/W",  0,      0,      0ull,   0ull},
69392         {"RESERVED_37_63"              ,        37,     27,     104,    "RAZ",  1,      1,      0,      0},
69393         {"MODE"                        ,        0,      2,      105,    "R/W",  0,      0,      0ull,   0ull},
69394         {"STATE"                       ,        2,      2,      105,    "RO",   0,      0,      0ull,   0ull},
69395         {"LEN"                         ,        4,      16,     105,    "R/W",  0,      0,      0ull,   0ull},
69396         {"CNT"                         ,        20,     24,     105,    "RO",   0,      0,      0ull,   0ull},
69397         {"DSTOP"                       ,        44,     1,      105,    "R/W",  0,      0,      0ull,   0ull},
69398         {"GSTOPEN"                     ,        45,     1,      105,    "R/W",  0,      0,      0ull,   0ull},
69399         {"RESERVED_46_63"              ,        46,     18,     105,    "RAZ",  1,      1,      0,      0},
69400         {"FDR"                         ,        0,      1,      106,    "RO",   0,      0,      0ull,   0ull},
69401         {"FFR"                         ,        1,      1,      106,    "RO",   0,      0,      0ull,   0ull},
69402         {"FPF1"                        ,        2,      1,      106,    "RO",   0,      0,      0ull,   0ull},
69403         {"FPF0"                        ,        3,      1,      106,    "RO",   0,      0,      0ull,   0ull},
69404         {"FRD"                         ,        4,      1,      106,    "RO",   0,      0,      0ull,   0ull},
69405         {"RESERVED_5_63"               ,        5,      59,     106,    "RAZ",  1,      1,      0,      0},
69406         {"MEM0_ERR"                    ,        0,      7,      107,    "R/W",  0,      0,      0ull,   0ull},
69407         {"MEM1_ERR"                    ,        7,      7,      107,    "R/W",  0,      0,      0ull,   0ull},
69408         {"ENB"                         ,        14,     1,      107,    "R/W",  0,      0,      0ull,   0ull},
69409         {"USE_STT"                     ,        15,     1,      107,    "R/W",  0,      0,      0ull,   0ull},
69410         {"USE_LDT"                     ,        16,     1,      107,    "R/W",  0,      0,      0ull,   0ull},
69411         {"RESET"                       ,        17,     1,      107,    "R/W",  0,      0,      0ull,   0ull},
69412         {"RESERVED_18_63"              ,        18,     46,     107,    "RAZ",  1,      1,      0,      0},
69413         {"FED0_SBE"                    ,        0,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69414         {"FED0_DBE"                    ,        1,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69415         {"FED1_SBE"                    ,        2,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69416         {"FED1_DBE"                    ,        3,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69417         {"Q0_UND"                      ,        4,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69418         {"Q0_COFF"                     ,        5,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69419         {"Q0_PERR"                     ,        6,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69420         {"Q1_UND"                      ,        7,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69421         {"Q1_COFF"                     ,        8,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69422         {"Q1_PERR"                     ,        9,      1,      108,    "R/W",  0,      0,      0ull,   0ull},
69423         {"Q2_UND"                      ,        10,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69424         {"Q2_COFF"                     ,        11,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69425         {"Q2_PERR"                     ,        12,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69426         {"Q3_UND"                      ,        13,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69427         {"Q3_COFF"                     ,        14,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69428         {"Q3_PERR"                     ,        15,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69429         {"Q4_UND"                      ,        16,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69430         {"Q4_COFF"                     ,        17,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69431         {"Q4_PERR"                     ,        18,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69432         {"Q5_UND"                      ,        19,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69433         {"Q5_COFF"                     ,        20,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69434         {"Q5_PERR"                     ,        21,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69435         {"Q6_UND"                      ,        22,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69436         {"Q6_COFF"                     ,        23,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69437         {"Q6_PERR"                     ,        24,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69438         {"Q7_UND"                      ,        25,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69439         {"Q7_COFF"                     ,        26,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69440         {"Q7_PERR"                     ,        27,     1,      108,    "R/W",  0,      0,      0ull,   0ull},
69441         {"RESERVED_28_63"              ,        28,     36,     108,    "RAZ",  1,      1,      0,      0},
69442         {"FED0_SBE"                    ,        0,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69443         {"FED0_DBE"                    ,        1,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69444         {"FED1_SBE"                    ,        2,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69445         {"FED1_DBE"                    ,        3,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69446         {"Q0_UND"                      ,        4,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69447         {"Q0_COFF"                     ,        5,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69448         {"Q0_PERR"                     ,        6,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69449         {"Q1_UND"                      ,        7,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69450         {"Q1_COFF"                     ,        8,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69451         {"Q1_PERR"                     ,        9,      1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69452         {"Q2_UND"                      ,        10,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69453         {"Q2_COFF"                     ,        11,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69454         {"Q2_PERR"                     ,        12,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69455         {"Q3_UND"                      ,        13,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69456         {"Q3_COFF"                     ,        14,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69457         {"Q3_PERR"                     ,        15,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69458         {"Q4_UND"                      ,        16,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69459         {"Q4_COFF"                     ,        17,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69460         {"Q4_PERR"                     ,        18,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69461         {"Q5_UND"                      ,        19,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69462         {"Q5_COFF"                     ,        20,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69463         {"Q5_PERR"                     ,        21,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69464         {"Q6_UND"                      ,        22,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69465         {"Q6_COFF"                     ,        23,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69466         {"Q6_PERR"                     ,        24,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69467         {"Q7_UND"                      ,        25,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69468         {"Q7_COFF"                     ,        26,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69469         {"Q7_PERR"                     ,        27,     1,      109,    "R/W1C",        0,      0,      0ull,   0ull},
69470         {"RESERVED_28_63"              ,        28,     36,     109,    "RAZ",  1,      1,      0,      0},
69471         {"QUE_SIZ"                     ,        0,      29,     110,    "RO",   0,      0,      0ull,   0ull},
69472         {"RESERVED_29_63"              ,        29,     35,     110,    "RAZ",  1,      1,      0,      0},
69473         {"PG_NUM"                      ,        0,      25,     111,    "RO",   0,      1,      0ull,   0},
69474         {"RESERVED_25_63"              ,        25,     39,     111,    "RAZ",  1,      1,      0,      0},
69475         {"ACT_INDX"                    ,        0,      26,     112,    "RO",   0,      1,      0ull,   0},
69476         {"ACT_QUE"                     ,        26,     3,      112,    "RO",   0,      1,      0ull,   0},
69477         {"RESERVED_29_63"              ,        29,     35,     112,    "RAZ",  0,      0,      0ull,   7ull},
69478         {"EXP_INDX"                    ,        0,      26,     113,    "RO",   0,      1,      0ull,   0},
69479         {"EXP_QUE"                     ,        26,     3,      113,    "RO",   0,      1,      0ull,   0},
69480         {"RESERVED_29_63"              ,        29,     35,     113,    "RAZ",  0,      0,      0ull,   7ull},
69481         {"CTL"                         ,        0,      16,     114,    "R/W",  1,      0,      0,      0ull},
69482         {"RESERVED_16_63"              ,        16,     48,     114,    "RAZ",  1,      1,      0,      0},
69483         {"STATUS"                      ,        0,      32,     115,    "RO",   0,      0,      0ull,   0ull},
69484         {"RESERVED_32_63"              ,        32,     32,     115,    "RAZ",  1,      1,      0,      0},
69485         {"RESERVED_0_1"                ,        0,      2,      116,    "RAZ",  1,      1,      0,      0},
69486         {"OUT_OVR"                     ,        2,      4,      116,    "R/W1C",        0,      0,      0ull,   0ull},
69487         {"RESERVED_6_21"               ,        6,      16,     116,    "RAZ",  1,      1,      0,      0},
69488         {"LOSTSTAT"                    ,        22,     4,      116,    "R/W1C",        0,      0,      0ull,   0ull},
69489         {"STATOVR"                     ,        26,     1,      116,    "R/W1C",        0,      0,      0ull,   0ull},
69490         {"INB_NXA"                     ,        27,     4,      116,    "R/W1C",        0,      0,      0ull,   0ull},
69491         {"RESERVED_31_63"              ,        31,     33,     116,    "RAZ",  1,      1,      0,      0},
69492         {"STATUS"                      ,        0,      16,     117,    "RO",   0,      0,      0ull,   0ull},
69493         {"RESERVED_16_63"              ,        16,     48,     117,    "RAZ",  1,      1,      0,      0},
69494         {"CLK_EN"                      ,        0,      1,      118,    "R/W",  0,      0,      0ull,   0ull},
69495         {"RESERVED_1_63"               ,        1,      63,     118,    "RAZ",  1,      1,      0,      0},
69496         {"LOGL_EN"                     ,        0,      16,     119,    "R/W",  0,      1,      65535ull,       0},
69497         {"PHYS_EN"                     ,        16,     1,      119,    "R/W",  0,      1,      1ull,   0},
69498         {"HG2RX_EN"                    ,        17,     1,      119,    "R/W",  0,      0,      0ull,   0ull},
69499         {"HG2TX_EN"                    ,        18,     1,      119,    "R/W",  0,      0,      0ull,   0ull},
69500         {"RESERVED_19_63"              ,        19,     45,     119,    "RAZ",  1,      1,      0,      0},
69501         {"TYPE"                        ,        0,      1,      120,    "RO",   0,      1,      0ull,   0},
69502         {"EN"                          ,        1,      1,      120,    "R/W",  0,      1,      0ull,   0},
69503         {"RESERVED_2_3"                ,        2,      2,      120,    "RAZ",  1,      1,      0,      0},
69504         {"MODE"                        ,        4,      2,      120,    "RO",   0,      1,      0ull,   0},
69505         {"RESERVED_6_7"                ,        6,      2,      120,    "RAZ",  1,      1,      0,      0},
69506         {"SPEED"                       ,        8,      2,      120,    "RO",   1,      1,      0,      0},
69507         {"RESERVED_10_63"              ,        10,     54,     120,    "RAZ",  1,      1,      0,      0},
69508         {"PRT"                         ,        0,      6,      121,    "RO",   0,      1,      0ull,   0},
69509         {"RESERVED_6_63"               ,        6,      58,     121,    "RAZ",  1,      1,      0,      0},
69510         {"RX_EN"                       ,        0,      1,      122,    "R/W",  0,      0,      0ull,   0ull},
69511         {"TX_EN"                       ,        1,      1,      122,    "R/W",  0,      0,      0ull,   0ull},
69512         {"DRP_EN"                      ,        2,      1,      122,    "R/W",  0,      0,      0ull,   0ull},
69513         {"BCK_EN"                      ,        3,      1,      122,    "R/W",  0,      0,      0ull,   0ull},
69514         {"RESERVED_4_15"               ,        4,      12,     122,    "RAZ",  1,      1,      0,      0},
69515         {"PHYS_BP"                     ,        16,     16,     122,    "R/W",  0,      1,      65535ull,       0},
69516         {"LOGL_EN"                     ,        32,     16,     122,    "R/W",  0,      0,      255ull, 255ull},
69517         {"PHYS_EN"                     ,        48,     16,     122,    "R/W",  0,      0,      255ull, 255ull},
69518         {"EN"                          ,        0,      1,      123,    "R/W",  0,      1,      0ull,   0},
69519         {"SPEED"                       ,        1,      1,      123,    "R/W",  0,      1,      1ull,   0},
69520         {"DUPLEX"                      ,        2,      1,      123,    "R/W",  0,      1,      1ull,   0},
69521         {"SLOTTIME"                    ,        3,      1,      123,    "R/W",  0,      1,      1ull,   0},
69522         {"RESERVED_4_7"                ,        4,      4,      123,    "RAZ",  1,      1,      0,      0},
69523         {"SPEED_MSB"                   ,        8,      1,      123,    "R/W",  0,      1,      0ull,   0},
69524         {"RESERVED_9_11"               ,        9,      3,      123,    "RAZ",  1,      1,      0,      0},
69525         {"RX_IDLE"                     ,        12,     1,      123,    "RO",   0,      1,      1ull,   0},
69526         {"TX_IDLE"                     ,        13,     1,      123,    "RO",   0,      1,      1ull,   0},
69527         {"RESERVED_14_63"              ,        14,     50,     123,    "RAZ",  1,      1,      0,      0},
69528         {"ADR"                         ,        0,      64,     124,    "R/W",  0,      1,      0ull,   0},
69529         {"ADR"                         ,        0,      64,     125,    "R/W",  0,      1,      0ull,   0},
69530         {"ADR"                         ,        0,      64,     126,    "R/W",  0,      1,      0ull,   0},
69531         {"ADR"                         ,        0,      64,     127,    "R/W",  0,      1,      0ull,   0},
69532         {"ADR"                         ,        0,      64,     128,    "R/W",  0,      1,      0ull,   0},
69533         {"ADR"                         ,        0,      64,     129,    "R/W",  0,      1,      0ull,   0},
69534         {"EN"                          ,        0,      8,      130,    "R/W",  0,      1,      0ull,   0},
69535         {"RESERVED_8_63"               ,        8,      56,     130,    "RAZ",  1,      1,      0,      0},
69536         {"BCST"                        ,        0,      1,      131,    "R/W",  0,      1,      1ull,   0},
69537         {"MCST"                        ,        1,      2,      131,    "R/W",  0,      1,      0ull,   0},
69538         {"CAM_MODE"                    ,        3,      1,      131,    "R/W",  0,      1,      0ull,   0},
69539         {"RESERVED_4_63"               ,        4,      60,     131,    "RAZ",  1,      1,      0,      0},
69540         {"CNT"                         ,        0,      5,      132,    "R/W",  0,      0,      24ull,  24ull},
69541         {"RESERVED_5_63"               ,        5,      59,     132,    "RAZ",  1,      1,      0,      0},
69542         {"RESERVED_0_0"                ,        0,      1,      133,    "RAZ",  1,      1,      0,      0},
69543         {"CAREXT"                      ,        1,      1,      133,    "R/W",  0,      0,      1ull,   1ull},
69544         {"RESERVED_2_2"                ,        2,      1,      133,    "RAZ",  1,      1,      0,      0},
69545         {"JABBER"                      ,        3,      1,      133,    "R/W",  0,      0,      1ull,   1ull},
69546         {"FCSERR"                      ,        4,      1,      133,    "R/W",  0,      0,      1ull,   1ull},
69547         {"RESERVED_5_6"                ,        5,      2,      133,    "RAZ",  1,      1,      0,      0},
69548         {"RCVERR"                      ,        7,      1,      133,    "R/W",  0,      0,      1ull,   1ull},
69549         {"SKPERR"                      ,        8,      1,      133,    "R/W",  0,      0,      1ull,   1ull},
69550         {"RESERVED_9_63"               ,        9,      55,     133,    "RAZ",  1,      1,      0,      0},
69551         {"PRE_CHK"                     ,        0,      1,      134,    "R/W",  0,      0,      1ull,   1ull},
69552         {"PRE_STRP"                    ,        1,      1,      134,    "R/W",  0,      0,      1ull,   1ull},
69553         {"CTL_DRP"                     ,        2,      1,      134,    "R/W",  0,      0,      1ull,   1ull},
69554         {"CTL_BCK"                     ,        3,      1,      134,    "R/W",  0,      0,      1ull,   1ull},
69555         {"CTL_MCST"                    ,        4,      1,      134,    "R/W",  0,      0,      1ull,   1ull},
69556         {"CTL_SMAC"                    ,        5,      1,      134,    "R/W",  0,      0,      0ull,   0ull},
69557         {"PRE_FREE"                    ,        6,      1,      134,    "RO",   0,      0,      1ull,   1ull},
69558         {"RESERVED_7_8"                ,        7,      2,      134,    "RAZ",  1,      1,      0,      0},
69559         {"PRE_ALIGN"                   ,        9,      1,      134,    "R/W",  0,      0,      0ull,   0ull},
69560         {"NULL_DIS"                    ,        10,     1,      134,    "R/W",  0,      0,      0ull,   0ull},
69561         {"RESERVED_11_63"              ,        11,     53,     134,    "RAZ",  1,      1,      0,      0},
69562         {"IFG"                         ,        0,      4,      135,    "R/W",  0,      0,      8ull,   8ull},
69563         {"RESERVED_4_63"               ,        4,      60,     135,    "RAZ",  1,      1,      0,      0},
69564         {"RESERVED_0_0"                ,        0,      1,      136,    "RAZ",  1,      1,      0,      0},
69565         {"CAREXT"                      ,        1,      1,      136,    "R/W",  0,      0,      0ull,   0ull},
69566         {"RESERVED_2_2"                ,        2,      1,      136,    "RAZ",  1,      1,      0,      0},
69567         {"JABBER"                      ,        3,      1,      136,    "R/W",  0,      0,      0ull,   0ull},
69568         {"FCSERR"                      ,        4,      1,      136,    "R/W",  0,      0,      0ull,   0ull},
69569         {"RESERVED_5_6"                ,        5,      2,      136,    "RAZ",  1,      1,      0,      0},
69570         {"RCVERR"                      ,        7,      1,      136,    "R/W",  0,      0,      0ull,   0ull},
69571         {"SKPERR"                      ,        8,      1,      136,    "R/W",  0,      0,      0ull,   0ull},
69572         {"RESERVED_9_9"                ,        9,      1,      136,    "RAZ",  1,      1,      0,      0},
69573         {"OVRERR"                      ,        10,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69574         {"PCTERR"                      ,        11,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69575         {"RSVERR"                      ,        12,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69576         {"FALERR"                      ,        13,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69577         {"COLDET"                      ,        14,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69578         {"IFGERR"                      ,        15,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69579         {"RESERVED_16_18"              ,        16,     3,      136,    "RAZ",  1,      1,      0,      0},
69580         {"PAUSE_DRP"                   ,        19,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69581         {"LOC_FAULT"                   ,        20,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69582         {"REM_FAULT"                   ,        21,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69583         {"BAD_SEQ"                     ,        22,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69584         {"BAD_TERM"                    ,        23,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69585         {"UNSOP"                       ,        24,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69586         {"UNEOP"                       ,        25,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69587         {"UNDAT"                       ,        26,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69588         {"HG2FLD"                      ,        27,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69589         {"HG2CC"                       ,        28,     1,      136,    "R/W",  0,      0,      0ull,   0ull},
69590         {"RESERVED_29_63"              ,        29,     35,     136,    "RAZ",  1,      1,      0,      0},
69591         {"RESERVED_0_0"                ,        0,      1,      137,    "RAZ",  1,      1,      0,      0},
69592         {"CAREXT"                      ,        1,      1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69593         {"RESERVED_2_2"                ,        2,      1,      137,    "RAZ",  1,      1,      0,      0},
69594         {"JABBER"                      ,        3,      1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69595         {"FCSERR"                      ,        4,      1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69596         {"RESERVED_5_6"                ,        5,      2,      137,    "RAZ",  1,      1,      0,      0},
69597         {"RCVERR"                      ,        7,      1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69598         {"SKPERR"                      ,        8,      1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69599         {"RESERVED_9_9"                ,        9,      1,      137,    "RAZ",  1,      1,      0,      0},
69600         {"OVRERR"                      ,        10,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69601         {"PCTERR"                      ,        11,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69602         {"RSVERR"                      ,        12,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69603         {"FALERR"                      ,        13,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69604         {"COLDET"                      ,        14,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69605         {"IFGERR"                      ,        15,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69606         {"RESERVED_16_18"              ,        16,     3,      137,    "RAZ",  1,      1,      0,      0},
69607         {"PAUSE_DRP"                   ,        19,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69608         {"LOC_FAULT"                   ,        20,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69609         {"REM_FAULT"                   ,        21,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69610         {"BAD_SEQ"                     ,        22,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69611         {"BAD_TERM"                    ,        23,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69612         {"UNSOP"                       ,        24,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69613         {"UNEOP"                       ,        25,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69614         {"UNDAT"                       ,        26,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69615         {"HG2FLD"                      ,        27,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69616         {"HG2CC"                       ,        28,     1,      137,    "R/W1C",        0,      0,      0ull,   0ull},
69617         {"RESERVED_29_63"              ,        29,     35,     137,    "RAZ",  1,      1,      0,      0},
69618         {"CNT"                         ,        0,      16,     138,    "R/W",  0,      0,      10240ull,       10240ull},
69619         {"RESERVED_16_63"              ,        16,     48,     138,    "RAZ",  1,      1,      0,      0},
69620         {"STATUS"                      ,        0,      16,     139,    "R/W1C",        0,      1,      0ull,   0},
69621         {"RESERVED_16_63"              ,        16,     48,     139,    "RAZ",  1,      1,      0,      0},
69622         {"RD_CLR"                      ,        0,      1,      140,    "R/W",  0,      0,      0ull,   0ull},
69623         {"RESERVED_1_63"               ,        1,      63,     140,    "RAZ",  1,      1,      0,      0},
69624         {"CNT"                         ,        0,      48,     141,    "RC/W", 0,      1,      0ull,   0},
69625         {"RESERVED_48_63"              ,        48,     16,     141,    "RAZ",  1,      1,      0,      0},
69626         {"CNT"                         ,        0,      48,     142,    "RC/W", 0,      1,      0ull,   0},
69627         {"RESERVED_48_63"              ,        48,     16,     142,    "RAZ",  1,      1,      0,      0},
69628         {"CNT"                         ,        0,      48,     143,    "RC/W", 0,      1,      0ull,   0},
69629         {"RESERVED_48_63"              ,        48,     16,     143,    "RAZ",  1,      1,      0,      0},
69630         {"CNT"                         ,        0,      48,     144,    "RC/W", 0,      1,      0ull,   0},
69631         {"RESERVED_48_63"              ,        48,     16,     144,    "RAZ",  1,      1,      0,      0},
69632         {"CNT"                         ,        0,      32,     145,    "RC/W", 0,      1,      0ull,   0},
69633         {"RESERVED_32_63"              ,        32,     32,     145,    "RAZ",  1,      1,      0,      0},
69634         {"CNT"                         ,        0,      32,     146,    "RC/W", 0,      1,      0ull,   0},
69635         {"RESERVED_32_63"              ,        32,     32,     146,    "RAZ",  1,      1,      0,      0},
69636         {"CNT"                         ,        0,      32,     147,    "RC/W", 0,      1,      0ull,   0},
69637         {"RESERVED_32_63"              ,        32,     32,     147,    "RAZ",  1,      1,      0,      0},
69638         {"CNT"                         ,        0,      32,     148,    "RC/W", 0,      1,      0ull,   0},
69639         {"RESERVED_32_63"              ,        32,     32,     148,    "RAZ",  1,      1,      0,      0},
69640         {"CNT"                         ,        0,      32,     149,    "RC/W", 0,      1,      0ull,   0},
69641         {"RESERVED_32_63"              ,        32,     32,     149,    "RAZ",  1,      1,      0,      0},
69642         {"LEN"                         ,        0,      7,      150,    "R/W",  0,      0,      0ull,   0ull},
69643         {"RESERVED_7_7"                ,        7,      1,      150,    "RAZ",  1,      1,      0,      0},
69644         {"FCSSEL"                      ,        8,      1,      150,    "R/W",  0,      0,      0ull,   0ull},
69645         {"RESERVED_9_63"               ,        9,      55,     150,    "RAZ",  1,      1,      0,      0},
69646         {"MARK"                        ,        0,      6,      151,    "R/W",  0,      0,      2ull,   2ull},
69647         {"RESERVED_6_63"               ,        6,      58,     151,    "RAZ",  1,      1,      0,      0},
69648         {"MARK"                        ,        0,      6,      152,    "R/W",  0,      0,      16ull,  16ull},
69649         {"RESERVED_6_63"               ,        6,      58,     152,    "RAZ",  1,      1,      0,      0},
69650         {"MARK"                        ,        0,      9,      153,    "R/W",  0,      0,      64ull,  64ull},
69651         {"RESERVED_9_63"               ,        9,      55,     153,    "RAZ",  1,      1,      0,      0},
69652         {"LGTIM2GO"                    ,        0,      16,     154,    "RO",   0,      1,      0ull,   0},
69653         {"XOF"                         ,        16,     16,     154,    "RO",   0,      0,      0ull,   0ull},
69654         {"PHTIM2GO"                    ,        32,     16,     154,    "RO",   0,      1,      0ull,   0},
69655         {"RESERVED_48_63"              ,        48,     16,     154,    "RAZ",  1,      1,      0,      0},
69656         {"COMMIT"                      ,        0,      4,      155,    "RO",   0,      0,      0ull,   0ull},
69657         {"RESERVED_4_15"               ,        4,      12,     155,    "RAZ",  1,      1,      0,      0},
69658         {"DROP"                        ,        16,     4,      155,    "RO",   0,      0,      0ull,   0ull},
69659         {"RESERVED_20_63"              ,        20,     44,     155,    "RAZ",  1,      1,      0,      0},
69660         {"PRTS"                        ,        0,      3,      156,    "R/W",  0,      0,      4ull,   4ull},
69661         {"RESERVED_3_63"               ,        3,      61,     156,    "RAZ",  1,      1,      0,      0},
69662         {"LANE_RXD"                    ,        0,      32,     157,    "RO",   0,      1,      0ull,   0},
69663         {"LANE_RXC"                    ,        32,     4,      157,    "RO",   0,      1,      0ull,   0},
69664         {"STATE"                       ,        36,     3,      157,    "RO",   0,      1,      0ull,   0},
69665         {"VAL"                         ,        39,     1,      157,    "R/W1C",        0,      1,      0ull,   0},
69666         {"RESERVED_40_63"              ,        40,     24,     157,    "RAZ",  1,      1,      0,      0},
69667         {"STATUS"                      ,        0,      2,      158,    "RO",   0,      0,      0ull,   0ull},
69668         {"RESERVED_2_63"               ,        2,      62,     158,    "RAZ",  1,      1,      0,      0},
69669         {"SMAC"                        ,        0,      48,     159,    "R/W",  0,      1,      0ull,   0},
69670         {"RESERVED_48_63"              ,        48,     16,     159,    "RAZ",  1,      1,      0,      0},
69671         {"CNT"                         ,        0,      16,     160,    "R/W1C",        0,      0,      0ull,   0ull},
69672         {"BP"                          ,        16,     1,      160,    "RO",   0,      0,      0ull,   0ull},
69673         {"RESERVED_17_63"              ,        17,     47,     160,    "RAZ",  1,      1,      0,      0},
69674         {"PREAMBLE"                    ,        0,      1,      161,    "R/W",  0,      0,      1ull,   1ull},
69675         {"PAD"                         ,        1,      1,      161,    "R/W",  0,      0,      1ull,   1ull},
69676         {"FCS"                         ,        2,      1,      161,    "R/W",  0,      0,      1ull,   1ull},
69677         {"FORCE_FCS"                   ,        3,      1,      161,    "R/W",  0,      0,      1ull,   1ull},
69678         {"RESERVED_4_63"               ,        4,      60,     161,    "RAZ",  1,      1,      0,      0},
69679         {"BURST"                       ,        0,      16,     162,    "R/W",  0,      0,      8192ull,        8192ull},
69680         {"RESERVED_16_63"              ,        16,     48,     162,    "RAZ",  1,      1,      0,      0},
69681         {"XOFF"                        ,        0,      16,     163,    "R/W1", 0,      0,      0ull,   0ull},
69682         {"RESERVED_16_63"              ,        16,     48,     163,    "RAZ",  1,      1,      0,      0},
69683         {"XON"                         ,        0,      16,     164,    "R/W1C",        0,      0,      0ull,   0ull},
69684         {"RESERVED_16_63"              ,        16,     48,     164,    "RAZ",  1,      1,      0,      0},
69685         {"XSCOL_EN"                    ,        0,      1,      165,    "R/W",  0,      0,      1ull,   1ull},
69686         {"XSDEF_EN"                    ,        1,      1,      165,    "R/W",  0,      0,      1ull,   1ull},
69687         {"RESERVED_2_63"               ,        2,      62,     165,    "RAZ",  1,      1,      0,      0},
69688         {"MIN_SIZE"                    ,        0,      8,      166,    "R/W",  0,      0,      59ull,  59ull},
69689         {"RESERVED_8_63"               ,        8,      56,     166,    "RAZ",  1,      1,      0,      0},
69690         {"INTERVAL"                    ,        0,      16,     167,    "R/W",  0,      1,      16ull,  0},
69691         {"RESERVED_16_63"              ,        16,     48,     167,    "RAZ",  1,      1,      0,      0},
69692         {"TIME"                        ,        0,      16,     168,    "R/W",  0,      1,      96ull,  0},
69693         {"RESERVED_16_63"              ,        16,     48,     168,    "RAZ",  1,      1,      0,      0},
69694         {"TIME"                        ,        0,      16,     169,    "RO",   1,      1,      0,      0},
69695         {"MSG_TIME"                    ,        16,     16,     169,    "RO",   1,      1,      0,      0},
69696         {"RESERVED_32_63"              ,        32,     32,     169,    "RAZ",  1,      1,      0,      0},
69697         {"SEND"                        ,        0,      1,      170,    "R/W",  0,      0,      1ull,   1ull},
69698         {"RESERVED_1_63"               ,        1,      63,     170,    "RAZ",  1,      1,      0,      0},
69699         {"ALIGN"                       ,        0,      1,      171,    "R/W",  0,      0,      1ull,   1ull},
69700         {"RESERVED_1_63"               ,        1,      63,     171,    "RAZ",  1,      1,      0,      0},
69701         {"SLOT"                        ,        0,      10,     172,    "R/W",  0,      0,      512ull, 512ull},
69702         {"RESERVED_10_63"              ,        10,     54,     172,    "RAZ",  1,      1,      0,      0},
69703         {"TIME"                        ,        0,      16,     173,    "R/W",  0,      1,      0ull,   0},
69704         {"RESERVED_16_63"              ,        16,     48,     173,    "RAZ",  1,      1,      0,      0},
69705         {"XSCOL"                       ,        0,      32,     174,    "RC/W", 0,      1,      0ull,   0},
69706         {"XSDEF"                       ,        32,     32,     174,    "RC/W", 0,      1,      0ull,   0},
69707         {"MCOL"                        ,        0,      32,     175,    "RC/W", 0,      1,      0ull,   0},
69708         {"SCOL"                        ,        32,     32,     175,    "RC/W", 0,      1,      0ull,   0},
69709         {"OCTS"                        ,        0,      48,     176,    "RC/W", 0,      1,      0ull,   0},
69710         {"RESERVED_48_63"              ,        48,     16,     176,    "RAZ",  1,      1,      0,      0},
69711         {"PKTS"                        ,        0,      32,     177,    "RC/W", 0,      1,      0ull,   0},
69712         {"RESERVED_32_63"              ,        32,     32,     177,    "RAZ",  1,      1,      0,      0},
69713         {"HIST0"                       ,        0,      32,     178,    "RC/W", 0,      1,      0ull,   0},
69714         {"HIST1"                       ,        32,     32,     178,    "RC/W", 0,      1,      0ull,   0},
69715         {"HIST2"                       ,        0,      32,     179,    "RC/W", 0,      1,      0ull,   0},
69716         {"HIST3"                       ,        32,     32,     179,    "RC/W", 0,      1,      0ull,   0},
69717         {"HIST4"                       ,        0,      32,     180,    "RC/W", 0,      1,      0ull,   0},
69718         {"HIST5"                       ,        32,     32,     180,    "RC/W", 0,      1,      0ull,   0},
69719         {"HIST6"                       ,        0,      32,     181,    "RC/W", 0,      1,      0ull,   0},
69720         {"HIST7"                       ,        32,     32,     181,    "RC/W", 0,      1,      0ull,   0},
69721         {"BCST"                        ,        0,      32,     182,    "RC/W", 0,      1,      0ull,   0},
69722         {"MCST"                        ,        32,     32,     182,    "RC/W", 0,      1,      0ull,   0},
69723         {"CTL"                         ,        0,      32,     183,    "RC/W", 0,      1,      0ull,   0},
69724         {"UNDFLW"                      ,        32,     32,     183,    "RC/W", 0,      1,      0ull,   0},
69725         {"RD_CLR"                      ,        0,      1,      184,    "R/W",  0,      0,      0ull,   0ull},
69726         {"RESERVED_1_63"               ,        1,      63,     184,    "RAZ",  1,      1,      0,      0},
69727         {"CNT"                         ,        0,      9,      185,    "R/W",  0,      0,      32ull,  32ull},
69728         {"RESERVED_9_63"               ,        9,      55,     185,    "RAZ",  1,      1,      0,      0},
69729         {"BP"                          ,        0,      4,      186,    "RO",   0,      0,      0ull,   0ull},
69730         {"RESERVED_4_63"               ,        4,      60,     186,    "RAZ",  1,      1,      0,      0},
69731         {"LIMIT"                       ,        0,      5,      187,    "R/W",  0,      0,      16ull,  16ull},
69732         {"RESERVED_5_63"               ,        5,      59,     187,    "RAZ",  1,      1,      0,      0},
69733         {"CORRUPT"                     ,        0,      4,      188,    "R/W",  0,      0,      15ull,  15ull},
69734         {"RESERVED_4_63"               ,        4,      60,     188,    "RAZ",  1,      1,      0,      0},
69735         {"TX_XOF"                      ,        0,      16,     189,    "R/W1", 0,      1,      0ull,   0},
69736         {"RESERVED_16_63"              ,        16,     48,     189,    "RAZ",  1,      1,      0,      0},
69737         {"TX_XON"                      ,        0,      16,     190,    "R/W1C",        0,      1,      0ull,   0},
69738         {"RESERVED_16_63"              ,        16,     48,     190,    "RAZ",  1,      1,      0,      0},
69739         {"IFG1"                        ,        0,      4,      191,    "R/W",  0,      1,      8ull,   0},
69740         {"IFG2"                        ,        4,      4,      191,    "R/W",  0,      1,      4ull,   0},
69741         {"RESERVED_8_63"               ,        8,      56,     191,    "RAZ",  1,      1,      0,      0},
69742         {"PKO_NXA"                     ,        0,      1,      192,    "R/W",  0,      0,      0ull,   0ull},
69743         {"RESERVED_1_1"                ,        1,      1,      192,    "RAZ",  0,      0,      0ull,   0ull},
69744         {"UNDFLW"                      ,        2,      4,      192,    "R/W",  0,      0,      0ull,   0ull},
69745         {"RESERVED_6_7"                ,        6,      2,      192,    "RAZ",  0,      0,      0ull,   0ull},
69746         {"XSCOL"                       ,        8,      4,      192,    "R/W",  0,      0,      0ull,   0ull},
69747         {"XSDEF"                       ,        12,     4,      192,    "R/W",  0,      0,      0ull,   0ull},
69748         {"LATE_COL"                    ,        16,     4,      192,    "R/W",  0,      0,      0ull,   0ull},
69749         {"RESERVED_20_63"              ,        20,     44,     192,    "RAZ",  1,      1,      0,      0},
69750         {"PKO_NXA"                     ,        0,      1,      193,    "R/W1C",        0,      0,      0ull,   0ull},
69751         {"RESERVED_1_1"                ,        1,      1,      193,    "RAZ",  0,      0,      0ull,   0ull},
69752         {"UNDFLW"                      ,        2,      4,      193,    "R/W1C",        0,      0,      0ull,   0ull},
69753         {"RESERVED_6_7"                ,        6,      2,      193,    "RAZ",  0,      0,      0ull,   0ull},
69754         {"XSCOL"                       ,        8,      4,      193,    "R/W1C",        0,      0,      0ull,   0ull},
69755         {"XSDEF"                       ,        12,     4,      193,    "R/W1C",        0,      0,      0ull,   0ull},
69756         {"LATE_COL"                    ,        16,     4,      193,    "R/W1C",        0,      0,      0ull,   0ull},
69757         {"RESERVED_20_63"              ,        20,     44,     193,    "RAZ",  1,      1,      0,      0},
69758         {"JAM"                         ,        0,      8,      194,    "R/W",  0,      1,      238ull, 0},
69759         {"RESERVED_8_63"               ,        8,      56,     194,    "RAZ",  1,      1,      0,      0},
69760         {"LFSR"                        ,        0,      16,     195,    "R/W",  0,      1,      65535ull,       0},
69761         {"RESERVED_16_63"              ,        16,     48,     195,    "RAZ",  1,      1,      0,      0},
69762         {"IGN_FULL"                    ,        0,      4,      196,    "R/W",  0,      0,      0ull,   0ull},
69763         {"BP"                          ,        4,      4,      196,    "R/W",  0,      0,      0ull,   0ull},
69764         {"EN"                          ,        8,      4,      196,    "R/W",  0,      0,      0ull,   0ull},
69765         {"RESERVED_12_31"              ,        12,     20,     196,    "RAZ",  1,      1,      0,      0},
69766         {"TX_PRT_BP"                   ,        32,     16,     196,    "R/W",  0,      0,      0ull,   0ull},
69767         {"RESERVED_48_63"              ,        48,     16,     196,    "RAZ",  1,      1,      0,      0},
69768         {"DMAC"                        ,        0,      48,     197,    "R/W",  0,      0,      1652522221569ull,       1652522221569ull},
69769         {"RESERVED_48_63"              ,        48,     16,     197,    "RAZ",  1,      1,      0,      0},
69770         {"TYPE"                        ,        0,      16,     198,    "R/W",  0,      0,      34824ull,       34824ull},
69771         {"RESERVED_16_63"              ,        16,     48,     198,    "RAZ",  1,      1,      0,      0},
69772         {"PRTS"                        ,        0,      5,      199,    "R/W",  0,      1,      4ull,   0},
69773         {"RESERVED_5_63"               ,        5,      59,     199,    "RAZ",  1,      1,      0,      0},
69774         {"DIC_EN"                      ,        0,      1,      200,    "R/W",  0,      0,      0ull,   1ull},
69775         {"UNI_EN"                      ,        1,      1,      200,    "R/W",  0,      0,      0ull,   0ull},
69776         {"RESERVED_2_3"                ,        2,      2,      200,    "RAZ",  1,      1,      0,      0},
69777         {"LS"                          ,        4,      2,      200,    "R/W",  0,      0,      0ull,   0ull},
69778         {"LS_BYP"                      ,        6,      1,      200,    "R/W",  0,      0,      0ull,   0ull},
69779         {"RESERVED_7_7"                ,        7,      1,      200,    "RAZ",  1,      1,      0,      0},
69780         {"HG_EN"                       ,        8,      1,      200,    "R/W",  0,      0,      0ull,   0ull},
69781         {"HG_PAUSE_HGI"                ,        9,      2,      200,    "R/W",  0,      0,      2ull,   2ull},
69782         {"RESERVED_11_63"              ,        11,     53,     200,    "RAZ",  1,      1,      0,      0},
69783         {"THRESH"                      ,        0,      4,      201,    "R/W",  0,      0,      6ull,   6ull},
69784         {"EN"                          ,        4,      1,      201,    "R/W",  0,      0,      0ull,   0ull},
69785         {"RESERVED_5_63"               ,        5,      59,     201,    "RAZ",  1,      1,      0,      0},
69786         {"TX_OE"                       ,        0,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
69787         {"RX_XOR"                      ,        1,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
69788         {"INT_EN"                      ,        2,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
69789         {"INT_TYPE"                    ,        3,      1,      202,    "R/W",  0,      0,      0ull,   0ull},
69790         {"FIL_CNT"                     ,        4,      4,      202,    "R/W",  0,      0,      0ull,   0ull},
69791         {"FIL_SEL"                     ,        8,      4,      202,    "R/W",  0,      0,      0ull,   0ull},
69792         {"CLK_SEL"                     ,        12,     2,      202,    "R/W",  0,      0,      0ull,   0ull},
69793         {"CLK_GEN"                     ,        14,     1,      202,    "R/W",  0,      0,      0ull,   0ull},
69794         {"RESERVED_15_63"              ,        15,     49,     202,    "RAZ",  1,      1,      0,      0},
69795         {"N"                           ,        0,      32,     203,    "R/W",  0,      1,      0ull,   0},
69796         {"RESERVED_32_63"              ,        32,     32,     203,    "RAZ",  1,      1,      0,      0},
69797         {"TYPE"                        ,        0,      16,     204,    "R/W1C",        0,      0,      0ull,   0ull},
69798         {"RESERVED_16_63"              ,        16,     48,     204,    "RAZ",  1,      1,      0,      0},
69799         {"DAT"                         ,        0,      16,     205,    "RO",   0,      0,      0ull,   0ull},
69800         {"RESERVED_16_63"              ,        16,     48,     205,    "RAZ",  1,      1,      0,      0},
69801         {"CLR"                         ,        0,      16,     206,    "R/W1C",        0,      0,      0ull,   0ull},
69802         {"RESERVED_16_63"              ,        16,     48,     206,    "RAZ",  1,      1,      0,      0},
69803         {"SET"                         ,        0,      16,     207,    "R/W1", 0,      0,      0ull,   0ull},
69804         {"RESERVED_16_63"              ,        16,     48,     207,    "RAZ",  1,      1,      0,      0},
69805         {"ICD"                         ,        0,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69806         {"IBD"                         ,        1,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69807         {"ICRP1"                       ,        2,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69808         {"ICRP0"                       ,        3,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69809         {"ICRN1"                       ,        4,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69810         {"ICRN0"                       ,        5,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69811         {"IBRQ1"                       ,        6,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69812         {"IBRQ0"                       ,        7,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69813         {"ICNRT"                       ,        8,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69814         {"IBR1"                        ,        9,      1,      208,    "RO",   0,      0,      0ull,   0ull},
69815         {"IBR0"                        ,        10,     1,      208,    "RO",   0,      0,      0ull,   0ull},
69816         {"IBDR1"                       ,        11,     1,      208,    "RO",   0,      0,      0ull,   0ull},
69817         {"IBDR0"                       ,        12,     1,      208,    "RO",   0,      0,      0ull,   0ull},
69818         {"ICNR0"                       ,        13,     1,      208,    "RO",   0,      0,      0ull,   0ull},
69819         {"ICNR1"                       ,        14,     1,      208,    "RO",   0,      0,      0ull,   0ull},
69820         {"ICR1"                        ,        15,     1,      208,    "RO",   0,      0,      0ull,   0ull},
69821         {"ICR0"                        ,        16,     1,      208,    "RO",   0,      0,      0ull,   0ull},
69822         {"ICNRCB"                      ,        17,     1,      208,    "RO",   0,      0,      0ull,   0ull},
69823         {"RESERVED_18_63"              ,        18,     46,     208,    "RAZ",  1,      1,      0,      0},
69824         {"FAU_END"                     ,        0,      1,      209,    "R/W",  0,      0,      0ull,   0ull},
69825         {"DWB_ENB"                     ,        1,      1,      209,    "R/W",  0,      0,      1ull,   1ull},
69826         {"PKO_ENB"                     ,        2,      1,      209,    "R/W",  0,      0,      0ull,   0ull},
69827         {"INB_MAT"                     ,        3,      1,      209,    "R/W1C",        0,      0,      0ull,   0ull},
69828         {"OUTB_MAT"                    ,        4,      1,      209,    "R/W1C",        0,      0,      0ull,   0ull},
69829         {"RR_MODE"                     ,        5,      1,      209,    "R/W",  0,      0,      0ull,   0ull},
69830         {"RESERVED_6_63"               ,        6,      58,     209,    "RAZ",  1,      1,      0,      0},
69831         {"CNT_VAL"                     ,        0,      15,     210,    "R/W",  0,      0,      0ull,   0ull},
69832         {"CNT_ENB"                     ,        15,     1,      210,    "R/W",  0,      0,      0ull,   0ull},
69833         {"RESERVED_16_63"              ,        16,     48,     210,    "RAZ",  1,      1,      0,      0},
69834         {"TOUT_VAL"                    ,        0,      12,     211,    "R/W",  0,      0,      4ull,   4ull},
69835         {"TOUT_ENB"                    ,        12,     1,      211,    "R/W",  0,      0,      1ull,   0ull},
69836         {"RESERVED_13_63"              ,        13,     51,     211,    "RAZ",  1,      1,      0,      0},
69837         {"CNT_VAL"                     ,        0,      15,     212,    "R/W",  0,      0,      0ull,   0ull},
69838         {"CNT_ENB"                     ,        15,     1,      212,    "R/W",  0,      0,      0ull,   0ull},
69839         {"RESERVED_16_63"              ,        16,     48,     212,    "RAZ",  1,      1,      0,      0},
69840         {"SRC"                         ,        0,      8,      213,    "R/W",  0,      1,      0ull,   0},
69841         {"DST"                         ,        8,      9,      213,    "R/W",  0,      1,      0ull,   0},
69842         {"OPC"                         ,        17,     4,      213,    "R/W",  0,      1,      0ull,   0},
69843         {"MASK"                        ,        21,     8,      213,    "R/W",  0,      1,      0ull,   0},
69844         {"RESERVED_29_63"              ,        29,     35,     213,    "RAZ",  1,      1,      0,      0},
69845         {"SRC"                         ,        0,      8,      214,    "R/W",  0,      1,      0ull,   0},
69846         {"DST"                         ,        8,      9,      214,    "R/W",  0,      1,      0ull,   0},
69847         {"OPC"                         ,        17,     4,      214,    "R/W",  0,      1,      0ull,   0},
69848         {"MASK"                        ,        21,     8,      214,    "R/W",  0,      1,      0ull,   0},
69849         {"RESERVED_29_63"              ,        29,     35,     214,    "RAZ",  1,      1,      0,      0},
69850         {"DATA"                        ,        0,      64,     215,    "R/W",  0,      1,      0ull,   0},
69851         {"DATA"                        ,        0,      64,     216,    "R/W",  0,      1,      0ull,   0},
69852         {"NP_SOP"                      ,        0,      1,      217,    "R/W",  0,      0,      0ull,   0ull},
69853         {"NP_EOP"                      ,        1,      1,      217,    "R/W",  0,      0,      0ull,   0ull},
69854         {"P_SOP"                       ,        2,      1,      217,    "R/W",  0,      0,      0ull,   0ull},
69855         {"P_EOP"                       ,        3,      1,      217,    "R/W",  0,      0,      0ull,   0ull},
69856         {"NP_DAT"                      ,        4,      1,      217,    "R/W",  0,      0,      0ull,   0ull},
69857         {"P_DAT"                       ,        5,      1,      217,    "R/W",  0,      0,      0ull,   0ull},
69858         {"RESERVED_6_63"               ,        6,      58,     217,    "RAZ",  1,      1,      0,      0},
69859         {"NP_SOP"                      ,        0,      1,      218,    "R/W1C",        0,      0,      0ull,   0ull},
69860         {"NP_EOP"                      ,        1,      1,      218,    "R/W1C",        0,      0,      0ull,   0ull},
69861         {"P_SOP"                       ,        2,      1,      218,    "R/W1C",        0,      0,      0ull,   0ull},
69862         {"P_EOP"                       ,        3,      1,      218,    "R/W1C",        0,      0,      0ull,   0ull},
69863         {"NP_DAT"                      ,        4,      1,      218,    "R/W1C",        0,      0,      0ull,   0ull},
69864         {"P_DAT"                       ,        5,      1,      218,    "R/W1C",        0,      0,      0ull,   0ull},
69865         {"RESERVED_6_63"               ,        6,      58,     218,    "RAZ",  1,      1,      0,      0},
69866         {"CNT_VAL"                     ,        0,      15,     219,    "R/W",  0,      0,      0ull,   0ull},
69867         {"CNT_ENB"                     ,        15,     1,      219,    "R/W",  0,      0,      0ull,   0ull},
69868         {"RESERVED_16_63"              ,        16,     48,     219,    "RAZ",  1,      1,      0,      0},
69869         {"CNT_VAL"                     ,        0,      15,     220,    "R/W",  0,      0,      0ull,   0ull},
69870         {"CNT_ENB"                     ,        15,     1,      220,    "R/W",  0,      0,      0ull,   0ull},
69871         {"RESERVED_16_63"              ,        16,     48,     220,    "RAZ",  1,      1,      0,      0},
69872         {"CNT_VAL"                     ,        0,      15,     221,    "R/W",  0,      0,      0ull,   0ull},
69873         {"CNT_ENB"                     ,        15,     1,      221,    "R/W",  0,      0,      0ull,   0ull},
69874         {"RESERVED_16_63"              ,        16,     48,     221,    "RAZ",  1,      1,      0,      0},
69875         {"SRC"                         ,        0,      9,      222,    "R/W",  0,      1,      0ull,   0},
69876         {"DST"                         ,        9,      8,      222,    "R/W",  0,      1,      0ull,   0},
69877         {"EOT"                         ,        17,     1,      222,    "R/W",  0,      1,      0ull,   0},
69878         {"MASK"                        ,        18,     8,      222,    "R/W",  0,      1,      0ull,   0},
69879         {"RESERVED_26_63"              ,        26,     38,     222,    "RAZ",  1,      1,      0,      0},
69880         {"SRC"                         ,        0,      9,      223,    "R/W",  0,      1,      0ull,   0},
69881         {"DST"                         ,        9,      8,      223,    "R/W",  0,      1,      0ull,   0},
69882         {"EOT"                         ,        17,     1,      223,    "R/W",  0,      1,      0ull,   0},
69883         {"MASK"                        ,        18,     8,      223,    "R/W",  0,      1,      0ull,   0},
69884         {"RESERVED_26_63"              ,        26,     38,     223,    "RAZ",  1,      1,      0,      0},
69885         {"DATA"                        ,        0,      64,     224,    "R/W",  0,      1,      0ull,   0},
69886         {"DATA"                        ,        0,      64,     225,    "R/W",  0,      1,      0ull,   0},
69887         {"CNT_VAL"                     ,        0,      15,     226,    "R/W",  0,      0,      0ull,   0ull},
69888         {"CNT_ENB"                     ,        15,     1,      226,    "R/W",  0,      0,      0ull,   0ull},
69889         {"RESERVED_16_63"              ,        16,     48,     226,    "RAZ",  1,      1,      0,      0},
69890         {"CNT_VAL"                     ,        0,      15,     227,    "R/W",  0,      0,      0ull,   0ull},
69891         {"CNT_ENB"                     ,        15,     1,      227,    "R/W",  0,      0,      0ull,   0ull},
69892         {"RESERVED_16_63"              ,        16,     48,     227,    "RAZ",  1,      1,      0,      0},
69893         {"CNT_VAL"                     ,        0,      15,     228,    "R/W",  0,      0,      0ull,   0ull},
69894         {"CNT_ENB"                     ,        15,     1,      228,    "R/W",  0,      0,      0ull,   0ull},
69895         {"RESERVED_16_63"              ,        16,     48,     228,    "RAZ",  1,      1,      0,      0},
69896         {"PORT"                        ,        0,      6,      229,    "RO",   0,      1,      0ull,   0},
69897         {"RESERVED_6_63"               ,        6,      58,     229,    "RAZ",  1,      1,      0,      0},
69898         {"NCB_WR"                      ,        0,      3,      230,    "R/W",  0,      1,      0ull,   0},
69899         {"NCB_RD"                      ,        3,      3,      230,    "R/W",  0,      1,      0ull,   0},
69900         {"PKO_RD"                      ,        6,      3,      230,    "R/W",  0,      1,      0ull,   0},
69901         {"RESERVED_9_63"               ,        9,      55,     230,    "RAZ",  1,      1,      0,      0},
69902         {"SKIP_SZ"                     ,        0,      6,      231,    "R/W",  0,      0,      0ull,   0ull},
69903         {"RESERVED_6_63"               ,        6,      58,     231,    "RAZ",  1,      1,      0,      0},
69904         {"BACK"                        ,        0,      4,      232,    "R/W",  0,      0,      0ull,   0ull},
69905         {"RESERVED_4_63"               ,        4,      60,     232,    "RAZ",  1,      1,      0,      0},
69906         {"BACK"                        ,        0,      4,      233,    "R/W",  0,      0,      0ull,   0ull},
69907         {"RESERVED_4_63"               ,        4,      60,     233,    "RAZ",  1,      1,      0,      0},
69908         {"PWP"                         ,        0,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69909         {"IPD_NEW"                     ,        1,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69910         {"IPD_OLD"                     ,        2,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69911         {"PRC_OFF"                     ,        3,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69912         {"PWQ0"                        ,        4,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69913         {"PWQ1"                        ,        5,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69914         {"PBM_WORD"                    ,        6,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69915         {"PBM0"                        ,        7,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69916         {"PBM1"                        ,        8,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69917         {"PBM2"                        ,        9,      1,      234,    "RO",   0,      0,      0ull,   0ull},
69918         {"PBM3"                        ,        10,     1,      234,    "RO",   0,      0,      0ull,   0ull},
69919         {"IPQ_PBE0"                    ,        11,     1,      234,    "RO",   0,      0,      0ull,   0ull},
69920         {"IPQ_PBE1"                    ,        12,     1,      234,    "RO",   0,      0,      0ull,   0ull},
69921         {"PWQ_POW"                     ,        13,     1,      234,    "RO",   0,      0,      0ull,   0ull},
69922         {"PWQ_WP1"                     ,        14,     1,      234,    "RO",   0,      0,      0ull,   0ull},
69923         {"PWQ_WQED"                    ,        15,     1,      234,    "RO",   0,      0,      0ull,   0ull},
69924         {"CSR_NCMD"                    ,        16,     1,      234,    "RO",   0,      0,      0ull,   0ull},
69925         {"CSR_MEM"                     ,        17,     1,      234,    "RO",   0,      0,      0ull,   0ull},
69926         {"RESERVED_18_63"              ,        18,     46,     234,    "RAZ",  1,      1,      0,      0},
69927         {"PRT_ENB"                     ,        0,      40,     235,    "R/W",  0,      0,      0ull,   0ull},
69928         {"RESERVED_40_63"              ,        40,     24,     235,    "RAZ",  1,      1,      0,      0},
69929         {"CLK_CNT"                     ,        0,      64,     236,    "RO",   0,      0,      0ull,   0ull},
69930         {"IPD_EN"                      ,        0,      1,      237,    "R/W",  0,      0,      0ull,   0ull},
69931         {"OPC_MODE"                    ,        1,      2,      237,    "R/W",  0,      0,      0ull,   0ull},
69932         {"PBP_EN"                      ,        3,      1,      237,    "R/W",  0,      0,      0ull,   0ull},
69933         {"WQE_LEND"                    ,        4,      1,      237,    "R/W",  0,      0,      0ull,   0ull},
69934         {"PKT_LEND"                    ,        5,      1,      237,    "R/W",  0,      0,      0ull,   0ull},
69935         {"NADDBUF"                     ,        6,      1,      237,    "R/W",  0,      0,      0ull,   0ull},
69936         {"ADDPKT"                      ,        7,      1,      237,    "R/W",  0,      0,      0ull,   0ull},
69937         {"RESET"                       ,        8,      1,      237,    "R/W",  0,      0,      0ull,   0ull},
69938         {"LEN_M8"                      ,        9,      1,      237,    "R/W",  0,      0,      0ull,   1ull},
69939         {"PKT_OFF"                     ,        10,     1,      237,    "R/W",  0,      0,      0ull,   0ull},
69940         {"IPD_FULL"                    ,        11,     1,      237,    "R/W",  0,      0,      0ull,   0ull},
69941         {"PQ_NABUF"                    ,        12,     1,      237,    "R/W",  0,      0,      0ull,   0ull},
69942         {"PQ_APKT"                     ,        13,     1,      237,    "R/W",  0,      0,      0ull,   0ull},
69943         {"NO_WPTR"                     ,        14,     1,      237,    "R/W",  0,      0,      0ull,   0ull},
69944         {"RESERVED_15_63"              ,        15,     49,     237,    "RAZ",  1,      1,      0,      0},
69945         {"PRC_PAR0"                    ,        0,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69946         {"PRC_PAR1"                    ,        1,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69947         {"PRC_PAR2"                    ,        2,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69948         {"PRC_PAR3"                    ,        3,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69949         {"BP_SUB"                      ,        4,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69950         {"DC_OVR"                      ,        5,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69951         {"CC_OVR"                      ,        6,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69952         {"C_COLL"                      ,        7,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69953         {"D_COLL"                      ,        8,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69954         {"BC_OVR"                      ,        9,      1,      238,    "R/W",  0,      0,      0ull,   0ull},
69955         {"PQ_ADD"                      ,        10,     1,      238,    "R/W",  0,      0,      0ull,   0ull},
69956         {"PQ_SUB"                      ,        11,     1,      238,    "R/W",  0,      0,      0ull,   0ull},
69957         {"RESERVED_12_63"              ,        12,     52,     238,    "RAZ",  1,      1,      0,      0},
69958         {"PRC_PAR0"                    ,        0,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69959         {"PRC_PAR1"                    ,        1,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69960         {"PRC_PAR2"                    ,        2,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69961         {"PRC_PAR3"                    ,        3,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69962         {"BP_SUB"                      ,        4,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69963         {"DC_OVR"                      ,        5,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69964         {"CC_OVR"                      ,        6,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69965         {"C_COLL"                      ,        7,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69966         {"D_COLL"                      ,        8,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69967         {"BC_OVR"                      ,        9,      1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69968         {"PQ_ADD"                      ,        10,     1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69969         {"PQ_SUB"                      ,        11,     1,      239,    "R/W1C",        0,      0,      0ull,   0ull},
69970         {"RESERVED_12_63"              ,        12,     52,     239,    "RAZ",  1,      1,      0,      0},
69971         {"SKIP_SZ"                     ,        0,      6,      240,    "R/W",  0,      0,      0ull,   0ull},
69972         {"RESERVED_6_63"               ,        6,      58,     240,    "RAZ",  1,      1,      0,      0},
69973         {"MB_SIZE"                     ,        0,      12,     241,    "R/W",  0,      0,      32ull,  32ull},
69974         {"RESERVED_12_63"              ,        12,     52,     241,    "RAZ",  1,      1,      0,      0},
69975         {"PTR"                         ,        0,      29,     242,    "RO",   1,      1,      0,      0},
69976         {"RESERVED_29_63"              ,        29,     35,     242,    "RAZ",  1,      1,      0,      0},
69977         {"PAGE_CNT"                    ,        0,      17,     243,    "R/W",  0,      0,      0ull,   0ull},
69978         {"BP_ENB"                      ,        17,     1,      243,    "R/W",  0,      0,      0ull,   0ull},
69979         {"RESERVED_18_63"              ,        18,     46,     243,    "RAZ",  1,      1,      0,      0},
69980         {"PAGE_CNT"                    ,        0,      17,     244,    "R/W",  0,      0,      0ull,   0ull},
69981         {"BP_ENB"                      ,        17,     1,      244,    "R/W",  0,      0,      0ull,   0ull},
69982         {"RESERVED_18_63"              ,        18,     46,     244,    "RAZ",  1,      1,      0,      0},
69983         {"CNT_VAL"                     ,        0,      25,     245,    "RO",   0,      1,      0ull,   0},
69984         {"RESERVED_25_63"              ,        25,     39,     245,    "RAZ",  1,      1,      0,      0},
69985         {"CNT_VAL"                     ,        0,      25,     246,    "RO",   0,      1,      0ull,   0},
69986         {"RESERVED_25_63"              ,        25,     39,     246,    "RAZ",  1,      1,      0,      0},
69987         {"CNT"                         ,        0,      32,     247,    "RO",   0,      1,      0ull,   0},
69988         {"WMARK"                       ,        32,     32,     247,    "R/W",  0,      1,      4294967295ull,  0},
69989         {"INTR"                        ,        0,      64,     248,    "R/W1C",        0,      0,      0ull,   0ull},
69990         {"ENB"                         ,        0,      64,     249,    "R/W",  0,      0,      0ull,   1ull},
69991         {"RADDR"                       ,        0,      3,      250,    "R/W",  0,      0,      0ull,   0ull},
69992         {"CENA"                        ,        3,      1,      250,    "R/W",  0,      0,      1ull,   1ull},
69993         {"PTR"                         ,        4,      29,     250,    "RO",   1,      1,      0,      0},
69994         {"PRADDR"                      ,        33,     3,      250,    "RO",   1,      1,      0,      0},
69995         {"MAX_PKT"                     ,        36,     3,      250,    "RO",   0,      0,      5ull,   5ull},
69996         {"RESERVED_39_63"              ,        39,     25,     250,    "RAZ",  1,      1,      0,      0},
69997         {"RADDR"                       ,        0,      7,      251,    "R/W",  0,      0,      0ull,   0ull},
69998         {"CENA"                        ,        7,      1,      251,    "R/W",  0,      0,      1ull,   1ull},
69999         {"PTR"                         ,        8,      29,     251,    "RO",   1,      1,      0,      0},
70000         {"MAX_PKT"                     ,        37,     7,      251,    "RO",   0,      0,      12ull,  12ull},
70001         {"RESERVED_44_63"              ,        44,     20,     251,    "RAZ",  1,      1,      0,      0},
70002         {"WQE_PCNT"                    ,        0,      7,      252,    "RO",   0,      0,      0ull,   0ull},
70003         {"PKT_PCNT"                    ,        7,      7,      252,    "RO",   0,      0,      0ull,   0ull},
70004         {"PFIF_CNT"                    ,        14,     3,      252,    "RO",   0,      0,      0ull,   0ull},
70005         {"WQEV_CNT"                    ,        17,     1,      252,    "RO",   0,      0,      0ull,   0ull},
70006         {"PKTV_CNT"                    ,        18,     1,      252,    "RO",   0,      0,      0ull,   0ull},
70007         {"RESERVED_19_63"              ,        19,     45,     252,    "RAZ",  1,      1,      0,      0},
70008         {"RADDR"                       ,        0,      8,      253,    "R/W",  0,      0,      0ull,   0ull},
70009         {"CENA"                        ,        8,      1,      253,    "R/W",  0,      0,      1ull,   1ull},
70010         {"PTR"                         ,        9,      29,     253,    "RO",   1,      1,      0,      0},
70011         {"PRADDR"                      ,        38,     8,      253,    "RO",   1,      1,      0,      0},
70012         {"WRADDR"                      ,        46,     8,      253,    "RO",   1,      1,      0,      0},
70013         {"MAX_CNTS"                    ,        54,     7,      253,    "RO",   0,      0,      8ull,   8ull},
70014         {"RESERVED_61_63"              ,        61,     3,      253,    "RAZ",  1,      1,      0,      0},
70015         {"PASS"                        ,        0,      32,     254,    "R/W",  0,      1,      0ull,   0},
70016         {"DROP"                        ,        32,     32,     254,    "R/W",  0,      1,      0ull,   0},
70017         {"Q0_PCNT"                     ,        0,      32,     255,    "RO",   0,      0,      0ull,   0ull},
70018         {"RESERVED_32_63"              ,        32,     32,     255,    "RAZ",  1,      1,      0,      0},
70019         {"PRT_ENB"                     ,        0,      36,     256,    "R/W",  0,      0,      0ull,   0ull},
70020         {"AVG_DLY"                     ,        36,     14,     256,    "R/W",  0,      1,      0ull,   0},
70021         {"PRB_DLY"                     ,        50,     14,     256,    "R/W",  0,      0,      0ull,   0ull},
70022         {"PRT_ENB"                     ,        0,      4,      257,    "R/W",  0,      0,      0ull,   0ull},
70023         {"RESERVED_4_63"               ,        4,      60,     257,    "RAZ",  1,      1,      0,      0},
70024         {"PRB_CON"                     ,        0,      32,     258,    "R/W",  0,      1,      0ull,   0},
70025         {"AVG_CON"                     ,        32,     8,      258,    "R/W",  0,      1,      0ull,   0},
70026         {"NEW_CON"                     ,        40,     8,      258,    "R/W",  0,      1,      0ull,   0},
70027         {"USE_PCNT"                    ,        48,     1,      258,    "R/W",  0,      0,      0ull,   0ull},
70028         {"RESERVED_49_63"              ,        49,     15,     258,    "RAZ",  1,      1,      0,      0},
70029         {"PAGE_CNT"                    ,        0,      25,     259,    "R/W",  1,      0,      0,      0ull},
70030         {"PORT"                        ,        25,     6,      259,    "R/W",  1,      0,      0,      0ull},
70031         {"RESERVED_31_63"              ,        31,     33,     259,    "RAZ",  1,      1,      0,      0},
70032         {"PORT_BIT"                    ,        0,      32,     260,    "R/W",  0,      0,      4294967295ull,  4294967295ull},
70033         {"RESERVED_32_35"              ,        32,     4,      260,    "RAZ",  1,      1,      0,      0},
70034         {"PORT_BIT2"                   ,        36,     4,      260,    "R/W",  0,      0,      15ull,  15ull},
70035         {"RESERVED_40_63"              ,        40,     24,     260,    "RAZ",  1,      1,      0,      0},
70036         {"CNT"                         ,        0,      32,     261,    "R/W",  1,      0,      0,      0ull},
70037         {"PORT_QOS"                    ,        32,     9,      261,    "R/W",  1,      0,      0,      0ull},
70038         {"RESERVED_41_63"              ,        41,     23,     261,    "RAZ",  1,      1,      0,      0},
70039         {"WQE_POOL"                    ,        0,      3,      262,    "R/W",  0,      0,      1ull,   1ull},
70040         {"RESERVED_3_63"               ,        3,      61,     262,    "RAZ",  1,      1,      0,      0},
70041         {"PTR"                         ,        0,      29,     263,    "RO",   1,      1,      0,      0},
70042         {"RESERVED_29_63"              ,        29,     35,     263,    "RAZ",  1,      1,      0,      0},
70043         {"WLB_DAT"                     ,        0,      4,      264,    "RO",   0,      0,      0ull,   0ull},
70044         {"STIN_MSK"                    ,        4,      1,      264,    "RO",   0,      0,      0ull,   0ull},
70045         {"DT"                          ,        5,      1,      264,    "RO",   0,      0,      0ull,   0ull},
70046         {"DTCNT"                       ,        6,      10,     264,    "RO",   0,      0,      0ull,   0ull},
70047         {"RESERVED_16_18"              ,        16,     3,      264,    "RAZ",  0,      0,      0ull,   0ull},
70048         {"WLB_MSK"                     ,        19,     4,      264,    "RO",   0,      0,      0ull,   0ull},
70049         {"DTBNK"                       ,        23,     1,      264,    "RO",   0,      0,      0ull,   0ull},
70050         {"RESERVED_24_63"              ,        24,     40,     264,    "RAZ",  0,      0,      0ull,   0ull},
70051         {"L2T"                         ,        0,      9,      265,    "RO",   0,      0,      0ull,   0ull},
70052         {"VAB_VWCF"                    ,        9,      1,      265,    "RO",   0,      0,      0ull,   0ull},
70053         {"ILC"                         ,        10,     1,      265,    "RO",   0,      0,      0ull,   0ull},
70054         {"RESERVED_11_11"              ,        11,     1,      265,    "RAZ",  0,      0,      0ull,   0ull},
70055         {"VWDF"                        ,        12,     4,      265,    "RO",   0,      0,      0ull,   0ull},
70056         {"PLC0"                        ,        16,     1,      265,    "RO",   0,      0,      0ull,   0ull},
70057         {"PLC1"                        ,        17,     1,      265,    "RO",   0,      0,      0ull,   0ull},
70058         {"PLC2"                        ,        18,     1,      265,    "RO",   0,      0,      0ull,   0ull},
70059         {"RESERVED_19_63"              ,        19,     45,     265,    "RAZ",  0,      0,      0ull,   0ull},
70060         {"XRDDAT"                      ,        0,      1,      266,    "RO",   0,      0,      0ull,   0ull},
70061         {"XRDMSK"                      ,        1,      1,      266,    "RO",   0,      0,      0ull,   0ull},
70062         {"RESERVED_2_2"                ,        2,      1,      266,    "RAZ",  0,      0,      0ull,   0ull},
70063         {"IPCBST"                      ,        3,      1,      266,    "RO",   0,      0,      0ull,   0ull},
70064         {"RESERVED_4_7"                ,        4,      4,      266,    "RAZ",  0,      0,      0ull,   0ull},
70065         {"RMDF"                        ,        8,      4,      266,    "RO",   0,      0,      0ull,   0ull},
70066         {"MRB"                         ,        12,     4,      266,    "RO",   0,      0,      0ull,   0ull},
70067         {"RESERVED_16_63"              ,        16,     48,     266,    "RAZ",  0,      0,      0ull,   0ull},
70068         {"LRF_ARB_MODE"                ,        0,      1,      267,    "R/W",  0,      0,      1ull,   1ull},
70069         {"RFB_ARB_MODE"                ,        1,      1,      267,    "R/W",  0,      0,      1ull,   1ull},
70070         {"RSP_ARB_MODE"                ,        2,      1,      267,    "R/W",  0,      0,      1ull,   1ull},
70071         {"MWF_CRD"                     ,        3,      4,      267,    "R/W",  0,      0,      2ull,   2ull},
70072         {"IDXALIAS"                    ,        7,      1,      267,    "R/W",  0,      0,      0ull,   1ull},
70073         {"FPEN"                        ,        8,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
70074         {"FPEMPTY"                     ,        9,      1,      267,    "R/W",  0,      0,      0ull,   0ull},
70075         {"FPEXP"                       ,        10,     4,      267,    "R/W",  0,      0,      0ull,   0ull},
70076         {"RESERVED_14_17"              ,        14,     4,      267,    "RAZ",  1,      1,      0,      0},
70077         {"LBIST"                       ,        18,     1,      267,    "R/W",  0,      0,      0ull,   0ull},
70078         {"BSTRUN"                      ,        19,     1,      267,    "RO",   0,      0,      0ull,   0ull},
70079         {"RESERVED_20_63"              ,        20,     44,     267,    "RAZ",  1,      1,      0,      0},
70080         {"L2T"                         ,        0,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
70081         {"L2D"                         ,        1,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
70082         {"FINV"                        ,        2,      1,      268,    "R/W",  0,      0,      0ull,   0ull},
70083         {"SET"                         ,        3,      3,      268,    "R/W",  0,      0,      0ull,   0ull},
70084         {"PPNUM"                       ,        6,      2,      268,    "R/W",  0,      0,      0ull,   0ull},
70085         {"RESERVED_8_9"                ,        8,      2,      268,    "RAZ",  0,      0,      0ull,   0ull},
70086         {"LFB_DMP"                     ,        10,     1,      268,    "R/W",  0,      0,      0ull,   0ull},
70087         {"LFB_ENUM"                    ,        11,     3,      268,    "R/W",  0,      0,      0ull,   0ull},
70088         {"RESERVED_14_63"              ,        14,     50,     268,    "RAZ",  0,      0,      0ull,   0ull},
70089         {"DT_TAG"                      ,        0,      29,     269,    "RO",   0,      0,      0ull,   0ull},
70090         {"DT_VLD"                      ,        29,     1,      269,    "RO",   0,      0,      0ull,   0ull},
70091         {"RESERVED_30_30"              ,        30,     1,      269,    "RAZ",  0,      0,      0ull,   0ull},
70092         {"DTENA"                       ,        31,     1,      269,    "R/W",  0,      0,      0ull,   0ull},
70093         {"RESERVED_32_63"              ,        32,     32,     269,    "RAZ",  0,      0,      0ull,   0ull},
70094         {"PLC0RMSK"                    ,        0,      32,     270,    "R/W",  0,      0,      0ull,   0ull},
70095         {"PLC1RMSK"                    ,        32,     32,     270,    "R/W",  0,      0,      0ull,   0ull},
70096         {"PLC2RMSK"                    ,        0,      32,     271,    "R/W",  0,      0,      0ull,   0ull},
70097         {"ILCRMSK"                     ,        32,     32,     271,    "R/W",  0,      0,      0ull,   0ull},
70098         {"OOB1EN"                      ,        0,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
70099         {"OOB2EN"                      ,        1,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
70100         {"OOB3EN"                      ,        2,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
70101         {"L2TSECEN"                    ,        3,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
70102         {"L2TDEDEN"                    ,        4,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
70103         {"L2DSECEN"                    ,        5,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
70104         {"L2DDEDEN"                    ,        6,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
70105         {"LCKENA"                      ,        7,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
70106         {"LCK2ENA"                     ,        8,      1,      272,    "R/W",  0,      0,      0ull,   1ull},
70107         {"RESERVED_9_63"               ,        9,      55,     272,    "RAZ",  0,      0,      0ull,   0ull},
70108         {"OOB1"                        ,        0,      1,      273,    "R/W1C",        0,      0,      0ull,   0ull},
70109         {"OOB2"                        ,        1,      1,      273,    "R/W1C",        0,      0,      0ull,   0ull},
70110         {"OOB3"                        ,        2,      1,      273,    "R/W1C",        0,      0,      0ull,   0ull},
70111         {"L2TSEC"                      ,        3,      1,      273,    "R/W1C",        0,      0,      0ull,   0ull},
70112         {"L2TDED"                      ,        4,      1,      273,    "R/W1C",        0,      0,      0ull,   0ull},
70113         {"L2DSEC"                      ,        5,      1,      273,    "R/W1C",        0,      0,      0ull,   0ull},
70114         {"L2DDED"                      ,        6,      1,      273,    "R/W1C",        0,      0,      0ull,   0ull},
70115         {"LCK"                         ,        7,      1,      273,    "R/W1C",        0,      0,      0ull,   0ull},
70116         {"LCK2"                        ,        8,      1,      273,    "R/W1C",        0,      0,      0ull,   0ull},
70117         {"RESERVED_9_63"               ,        9,      55,     273,    "RAZ",  0,      0,      0ull,   0ull},
70118         {"LCK_ENA"                     ,        0,      1,      274,    "R/W",  0,      0,      0ull,   0ull},
70119         {"RESERVED_1_3"                ,        1,      3,      274,    "RAZ",  0,      0,      0ull,   0ull},
70120         {"LCK_BASE"                    ,        4,      27,     274,    "R/W",  0,      0,      0ull,   0ull},
70121         {"RESERVED_31_63"              ,        31,     33,     274,    "RAZ",  0,      0,      0ull,   0ull},
70122         {"LCK_OFFSET"                  ,        0,      10,     275,    "R/W",  0,      0,      0ull,   0ull},
70123         {"RESERVED_10_63"              ,        10,     54,     275,    "RAZ",  0,      0,      0ull,   0ull},
70124         {"VLD"                         ,        0,      1,      276,    "RO",   0,      0,      0ull,   0ull},
70125         {"CMD"                         ,        1,      4,      276,    "RO",   0,      0,      0ull,   0ull},
70126         {"SID"                         ,        5,      9,      276,    "RO",   0,      0,      0ull,   0ull},
70127         {"VABNUM"                      ,        14,     3,      276,    "RO",   0,      0,      0ull,   0ull},
70128         {"RESERVED_17_17"              ,        17,     1,      276,    "RAZ",  0,      0,      0ull,   0ull},
70129         {"SET"                         ,        18,     3,      276,    "RO",   0,      0,      0ull,   0ull},
70130         {"IHD"                         ,        21,     1,      276,    "RO",   0,      0,      0ull,   0ull},
70131         {"ITL"                         ,        22,     1,      276,    "RO",   0,      0,      0ull,   0ull},
70132         {"INXT"                        ,        23,     3,      276,    "RO",   0,      0,      0ull,   0ull},
70133         {"RESERVED_26_26"              ,        26,     1,      276,    "RAZ",  0,      0,      0ull,   0ull},
70134         {"VAM"                         ,        27,     1,      276,    "RO",   0,      0,      0ull,   0ull},
70135         {"STCFL"                       ,        28,     1,      276,    "RO",   0,      0,      0ull,   0ull},
70136         {"STINV"                       ,        29,     1,      276,    "RO",   0,      0,      0ull,   0ull},
70137         {"STPND"                       ,        30,     1,      276,    "RO",   0,      0,      0ull,   0ull},
70138         {"STCPND"                      ,        31,     1,      276,    "RO",   0,      0,      0ull,   0ull},
70139         {"RESERVED_32_63"              ,        32,     32,     276,    "RAZ",  0,      0,      0ull,   0ull},
70140         {"VLD"                         ,        0,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70141         {"WTPRB"                       ,        1,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70142         {"PRBRTY"                      ,        2,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70143         {"WTMFL"                       ,        3,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70144         {"WTVTM"                       ,        4,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70145         {"WTSTRSC"                     ,        5,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70146         {"WTSTRSP"                     ,        6,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70147         {"WTSTDT"                      ,        7,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70148         {"WTRDA"                       ,        8,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70149         {"WTSTM"                       ,        9,      1,      277,    "RO",   0,      0,      0ull,   0ull},
70150         {"WTWRM"                       ,        10,     1,      277,    "RO",   0,      0,      0ull,   0ull},
70151         {"WTWHF"                       ,        11,     1,      277,    "RO",   0,      0,      0ull,   0ull},
70152         {"WTWHP"                       ,        12,     1,      277,    "RO",   0,      0,      0ull,   0ull},
70153         {"WTDQ"                        ,        13,     1,      277,    "RO",   0,      0,      0ull,   0ull},
70154         {"WTDW"                        ,        14,     1,      277,    "RO",   0,      0,      0ull,   0ull},
70155         {"WTRSP"                       ,        15,     1,      277,    "RO",   0,      0,      0ull,   0ull},
70156         {"BID"                         ,        16,     2,      277,    "RO",   0,      0,      0ull,   0ull},
70157         {"DSGOING"                     ,        18,     1,      277,    "RO",   0,      0,      0ull,   0ull},
70158         {"RESERVED_19_63"              ,        19,     45,     277,    "RAZ",  0,      0,      0ull,   0ull},
70159         {"LFB_IDX"                     ,        0,      9,      278,    "RO",   0,      0,      0ull,   0ull},
70160         {"LFB_TAG"                     ,        9,      18,     278,    "RO",   0,      0,      0ull,   0ull},
70161         {"RESERVED_27_63"              ,        27,     37,     278,    "RAZ",  0,      0,      0ull,   0ull},
70162         {"LFB_HWM"                     ,        0,      3,      279,    "R/W",  0,      0,      7ull,   7ull},
70163         {"RESERVED_3_3"                ,        3,      1,      279,    "RAZ",  0,      0,      0ull,   0ull},
70164         {"STPARTDIS"                   ,        4,      1,      279,    "R/W",  0,      0,      0ull,   0ull},
70165         {"RESERVED_5_63"               ,        5,      59,     279,    "RAZ",  0,      0,      0ull,   0ull},
70166         {"STENA"                       ,        0,      1,      280,    "R/W",  0,      0,      0ull,   0ull},
70167         {"DWBENA"                      ,        1,      1,      280,    "R/W",  0,      0,      0ull,   0ull},
70168         {"RESERVED_2_63"               ,        2,      62,     280,    "RAZ",  0,      0,      0ull,   0ull},
70169         {"SIZE"                        ,        0,      14,     281,    "R/W",  0,      0,      0ull,   0ull},
70170         {"RESERVED_14_19"              ,        14,     6,      281,    "RAZ",  0,      0,      0ull,   0ull},
70171         {"SADR"                        ,        20,     14,     281,    "R/W",  0,      0,      0ull,   0ull},
70172         {"RESERVED_34_35"              ,        34,     2,      281,    "RAZ",  0,      0,      0ull,   0ull},
70173         {"FSRC"                        ,        36,     1,      281,    "RO",   0,      0,      0ull,   0ull},
70174         {"FADR"                        ,        37,     27,     281,    "RO",   0,      0,      0ull,   0ull},
70175         {"SIZE"                        ,        0,      14,     282,    "R/W",  0,      0,      0ull,   0ull},
70176         {"RESERVED_14_19"              ,        14,     6,      282,    "RAZ",  0,      0,      0ull,   0ull},
70177         {"SADR"                        ,        20,     14,     282,    "R/W",  0,      0,      0ull,   0ull},
70178         {"RESERVED_34_35"              ,        34,     2,      282,    "RAZ",  0,      0,      0ull,   0ull},
70179         {"FSRC"                        ,        36,     1,      282,    "RO",   0,      0,      0ull,   0ull},
70180         {"FADR"                        ,        37,     27,     282,    "RO",   0,      0,      0ull,   0ull},
70181         {"SIZE"                        ,        0,      14,     283,    "R/W",  0,      0,      0ull,   0ull},
70182         {"RESERVED_14_19"              ,        14,     6,      283,    "RAZ",  0,      0,      0ull,   0ull},
70183         {"SADR"                        ,        20,     14,     283,    "R/W",  0,      0,      0ull,   0ull},
70184         {"RESERVED_34_35"              ,        34,     2,      283,    "RAZ",  0,      0,      0ull,   0ull},
70185         {"FSRC"                        ,        36,     1,      283,    "RO",   0,      0,      0ull,   0ull},
70186         {"FADR"                        ,        37,     27,     283,    "RO",   0,      0,      0ull,   0ull},
70187         {"PFCNT0"                      ,        0,      36,     284,    "RO",   0,      0,      0ull,   0ull},
70188         {"RESERVED_36_63"              ,        36,     28,     284,    "RAZ",  0,      0,      0ull,   0ull},
70189         {"CNT0SEL"                     ,        0,      6,      285,    "R/W",  0,      0,      0ull,   0ull},
70190         {"CNT0CLR"                     ,        6,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
70191         {"CNT0ENA"                     ,        7,      1,      285,    "R/W",  0,      0,      0ull,   0ull},
70192         {"CNT1SEL"                     ,        8,      6,      285,    "R/W",  0,      0,      0ull,   0ull},
70193         {"CNT1CLR"                     ,        14,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70194         {"CNT1ENA"                     ,        15,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70195         {"CNT2SEL"                     ,        16,     6,      285,    "R/W",  0,      0,      0ull,   0ull},
70196         {"CNT2CLR"                     ,        22,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70197         {"CNT2ENA"                     ,        23,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70198         {"CNT3SEL"                     ,        24,     6,      285,    "R/W",  0,      0,      0ull,   0ull},
70199         {"CNT3CLR"                     ,        30,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70200         {"CNT3ENA"                     ,        31,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70201         {"CNT0RDCLR"                   ,        32,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70202         {"CNT1RDCLR"                   ,        33,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70203         {"CNT2RDCLR"                   ,        34,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70204         {"CNT3RDCLR"                   ,        35,     1,      285,    "R/W",  0,      0,      0ull,   0ull},
70205         {"RESERVED_36_63"              ,        36,     28,     285,    "RAZ",  0,      0,      0ull,   0ull},
70206         {"PP0GRP"                      ,        0,      2,      286,    "R/W",  0,      0,      0ull,   0ull},
70207         {"PP1GRP"                      ,        2,      2,      286,    "R/W",  0,      0,      0ull,   0ull},
70208         {"PP2GRP"                      ,        4,      2,      286,    "R/W",  0,      0,      0ull,   0ull},
70209         {"PP3GRP"                      ,        6,      2,      286,    "R/W",  0,      0,      0ull,   0ull},
70210         {"RESERVED_8_63"               ,        8,      56,     286,    "RAZ",  0,      0,      0ull,   0ull},
70211         {"UMSK0"                       ,        0,      8,      287,    "R/W",  0,      0,      0ull,   0ull},
70212         {"UMSK1"                       ,        8,      8,      287,    "R/W",  0,      0,      0ull,   0ull},
70213         {"UMSK2"                       ,        16,     8,      287,    "R/W",  0,      0,      0ull,   0ull},
70214         {"UMSK3"                       ,        24,     8,      287,    "R/W",  0,      0,      0ull,   0ull},
70215         {"RESERVED_32_63"              ,        32,     32,     287,    "RAZ",  0,      0,      0ull,   0ull},
70216         {"UMSKIOB"                     ,        0,      8,      288,    "R/W",  0,      0,      0ull,   0ull},
70217         {"RESERVED_8_63"               ,        8,      56,     288,    "RAZ",  0,      0,      0ull,   0ull},
70218         {"Q0STAT"                      ,        0,      34,     289,    "RO",   0,      0,      0ull,   0ull},
70219         {"FTL"                         ,        34,     1,      289,    "RO",   0,      0,      0ull,   0ull},
70220         {"RESERVED_35_63"              ,        35,     29,     289,    "RAZ",  0,      0,      0ull,   0ull},
70221         {"Q1STAT"                      ,        0,      34,     290,    "RO",   0,      0,      0ull,   0ull},
70222         {"RESERVED_34_63"              ,        34,     30,     290,    "RAZ",  0,      0,      0ull,   0ull},
70223         {"Q2STAT"                      ,        0,      34,     291,    "RO",   0,      0,      0ull,   0ull},
70224         {"RESERVED_34_63"              ,        34,     30,     291,    "RAZ",  0,      0,      0ull,   0ull},
70225         {"Q3STAT"                      ,        0,      34,     292,    "RO",   0,      0,      0ull,   0ull},
70226         {"RESERVED_34_63"              ,        34,     30,     292,    "RAZ",  0,      0,      0ull,   0ull},
70227         {"ECC_ENA"                     ,        0,      1,      293,    "R/W",  0,      0,      0ull,   1ull},
70228         {"SEC_INTENA"                  ,        1,      1,      293,    "R/W",  0,      0,      0ull,   1ull},
70229         {"DED_INTENA"                  ,        2,      1,      293,    "R/W",  0,      0,      0ull,   1ull},
70230         {"SEC_ERR"                     ,        3,      1,      293,    "R/W1C",        0,      0,      0ull,   0ull},
70231         {"DED_ERR"                     ,        4,      1,      293,    "R/W1C",        0,      0,      0ull,   0ull},
70232         {"BMHCLSEL"                    ,        5,      1,      293,    "R/W",  0,      0,      0ull,   0ull},
70233         {"RESERVED_6_63"               ,        6,      58,     293,    "RAZ",  0,      0,      0ull,   0ull},
70234         {"FADR"                        ,        0,      10,     294,    "RO",   0,      0,      0ull,   0ull},
70235         {"RESERVED_10_10"              ,        10,     1,      294,    "RAZ",  0,      0,      0ull,   0ull},
70236         {"FSET"                        ,        11,     3,      294,    "RO",   0,      0,      0ull,   0ull},
70237         {"FOWMSK"                      ,        14,     4,      294,    "RO",   0,      0,      0ull,   0ull},
70238         {"RESERVED_18_63"              ,        18,     46,     294,    "RAZ",  0,      0,      0ull,   0ull},
70239         {"FSYN_OW0"                    ,        0,      10,     295,    "RO",   0,      0,      0ull,   0ull},
70240         {"FSYN_OW1"                    ,        10,     10,     295,    "RO",   0,      0,      0ull,   0ull},
70241         {"RESERVED_20_63"              ,        20,     44,     295,    "RAZ",  0,      0,      0ull,   0ull},
70242         {"FSYN_OW2"                    ,        0,      10,     296,    "RO",   0,      0,      0ull,   0ull},
70243         {"FSYN_OW3"                    ,        10,     10,     296,    "RO",   0,      0,      0ull,   0ull},
70244         {"RESERVED_20_63"              ,        20,     44,     296,    "RAZ",  0,      0,      0ull,   0ull},
70245         {"Q0FUS"                       ,        0,      34,     297,    "RO",   0,      0,      0ull,   0ull},
70246         {"RESERVED_34_63"              ,        34,     30,     297,    "RAZ",  0,      0,      0ull,   0ull},
70247         {"Q1FUS"                       ,        0,      34,     298,    "RO",   0,      0,      0ull,   0ull},
70248         {"RESERVED_34_63"              ,        34,     30,     298,    "RAZ",  0,      0,      0ull,   0ull},
70249         {"Q2FUS"                       ,        0,      34,     299,    "RO",   0,      0,      0ull,   0ull},
70250         {"RESERVED_34_63"              ,        34,     30,     299,    "RAZ",  0,      0,      0ull,   0ull},
70251         {"Q3FUS"                       ,        0,      34,     300,    "RO",   0,      0,      0ull,   0ull},
70252         {"CRIP_256K"                   ,        34,     1,      300,    "RO",   0,      0,      0ull,   0ull},
70253         {"CRIP_128K"                   ,        35,     1,      300,    "RO",   0,      0,      0ull,   0ull},
70254         {"RESERVED_36_36"              ,        36,     1,      300,    "RAZ",  0,      0,      0ull,   0ull},
70255         {"EMA_CTL"                     ,        37,     3,      300,    "RO",   0,      0,      0ull,   0ull},
70256         {"RESERVED_40_63"              ,        40,     24,     300,    "RAZ",  0,      0,      0ull,   0ull},
70257         {"ECC_ENA"                     ,        0,      1,      301,    "R/W",  0,      0,      0ull,   1ull},
70258         {"SEC_INTENA"                  ,        1,      1,      301,    "R/W",  0,      0,      0ull,   1ull},
70259         {"DED_INTENA"                  ,        2,      1,      301,    "R/W",  0,      0,      0ull,   1ull},
70260         {"SEC_ERR"                     ,        3,      1,      301,    "R/W1C",        0,      0,      0ull,   0ull},
70261         {"DED_ERR"                     ,        4,      1,      301,    "R/W1C",        0,      0,      0ull,   0ull},
70262         {"FSYN"                        ,        5,      6,      301,    "RO",   0,      0,      0ull,   0ull},
70263         {"FADR"                        ,        11,     9,      301,    "RO",   0,      0,      0ull,   0ull},
70264         {"RESERVED_20_20"              ,        20,     1,      301,    "RAZ",  0,      0,      0ull,   0ull},
70265         {"FSET"                        ,        21,     3,      301,    "RO",   0,      0,      0ull,   0ull},
70266         {"LCKERR"                      ,        24,     1,      301,    "R/W1C",        0,      0,      0ull,   0ull},
70267         {"LCK_INTENA"                  ,        25,     1,      301,    "R/W",  0,      0,      0ull,   1ull},
70268         {"LCKERR2"                     ,        26,     1,      301,    "R/W1C",        0,      0,      0ull,   0ull},
70269         {"LCK_INTENA2"                 ,        27,     1,      301,    "R/W",  0,      0,      0ull,   1ull},
70270         {"RESERVED_28_63"              ,        28,     36,     301,    "RAZ",  0,      0,      0ull,   0ull},
70271         {"START"                       ,        0,      1,      302,    "R/W",  0,      0,      0ull,   0ull},
70272         {"RESERVED_1_63"               ,        1,      63,     302,    "RAZ",  1,      0,      0,      0ull},
70273         {"MRD"                         ,        0,      3,      303,    "RO",   1,      0,      0,      0ull},
70274         {"MRF"                         ,        3,      1,      303,    "RO",   1,      0,      0,      0ull},
70275         {"MWC"                         ,        4,      1,      303,    "RO",   1,      0,      0,      0ull},
70276         {"MWD"                         ,        5,      3,      303,    "RO",   1,      0,      0,      0ull},
70277         {"MWF"                         ,        8,      1,      303,    "RO",   1,      0,      0,      0ull},
70278         {"CSRE2D"                      ,        9,      1,      303,    "RO",   1,      0,      0,      0ull},
70279         {"CSRD2E"                      ,        10,     1,      303,    "RO",   1,      0,      0,      0ull},
70280         {"RESERVED_11_63"              ,        11,     53,     303,    "RAZ",  1,      0,      0,      0ull},
70281         {"PCTL_DAT"                    ,        0,      5,      304,    "R/W",  0,      1,      0ull,   0},
70282         {"RESERVED_5_11"               ,        5,      7,      304,    "RAZ",  0,      1,      0ull,   0},
70283         {"PCTL_CSR"                    ,        12,     4,      304,    "R/W",  0,      1,      15ull,  0},
70284         {"NCTL_DAT"                    ,        16,     4,      304,    "R/W",  0,      1,      0ull,   0},
70285         {"RESERVED_20_27"              ,        20,     8,      304,    "RAZ",  0,      1,      0ull,   0},
70286         {"NCTL_CSR"                    ,        28,     4,      304,    "R/W",  0,      1,      15ull,  0},
70287         {"RESERVED_32_63"              ,        32,     32,     304,    "RAZ",  0,      0,      0ull,   0ull},
70288         {"DIC"                         ,        0,      2,      305,    "R/W",  0,      0,      0ull,   0ull},
70289         {"QS_DIC"                      ,        2,      2,      305,    "R/W",  0,      0,      2ull,   2ull},
70290         {"TSKW"                        ,        4,      2,      305,    "R/W",  0,      0,      0ull,   1ull},
70291         {"SIL_LAT"                     ,        6,      2,      305,    "R/W",  0,      0,      1ull,   1ull},
70292         {"BPRCH"                       ,        8,      1,      305,    "R/W",  0,      1,      0ull,   0},
70293         {"FPRCH2"                      ,        9,      1,      305,    "R/W",  0,      0,      0ull,   1ull},
70294         {"MODE32B"                     ,        10,     1,      305,    "R/W",  0,      0,      0ull,   0ull},
70295         {"DRESET"                      ,        11,     1,      305,    "R/W",  0,      0,      0ull,   0ull},
70296         {"INORDER_MRF"                 ,        12,     1,      305,    "R/W",  0,      0,      0ull,   0ull},
70297         {"INORDER_MWF"                 ,        13,     1,      305,    "RAZ",  0,      0,      0ull,   0ull},
70298         {"R2R_SLOT"                    ,        14,     1,      305,    "R/W",  0,      0,      0ull,   0ull},
70299         {"RDIMM_ENA"                   ,        15,     1,      305,    "R/W",  0,      1,      0ull,   0},
70300         {"RESERVED_16_17"              ,        16,     2,      305,    "RAZ",  0,      0,      0ull,   0ull},
70301         {"MAX_WRITE_BATCH"             ,        18,     4,      305,    "R/W",  0,      0,      8ull,   8ull},
70302         {"XOR_BANK"                    ,        22,     1,      305,    "R/W",  0,      0,      0ull,   1ull},
70303         {"SLOW_SCF"                    ,        23,     1,      305,    "R/W",  0,      0,      0ull,   0ull},
70304         {"DDR__PCTL"                   ,        24,     4,      305,    "RO",   1,      1,      0,      0},
70305         {"DDR__NCTL"                   ,        28,     4,      305,    "RO",   1,      1,      0,      0},
70306         {"RESERVED_32_63"              ,        32,     32,     305,    "RAZ",  1,      1,      0,      0},
70307         {"RESERVED_0_7"                ,        0,      8,      306,    "RAZ",  0,      1,      0ull,   0},
70308         {"DCC_ENABLE"                  ,        8,      1,      306,    "R/W",  0,      0,      0ull,   0ull},
70309         {"SIL_MODE"                    ,        9,      1,      306,    "R/W",  0,      0,      0ull,   1ull},
70310         {"SEQUENCE"                    ,        10,     3,      306,    "R/W",  0,      0,      0ull,   0ull},
70311         {"IDLEPOWER"                   ,        13,     3,      306,    "R/W",  0,      0,      0ull,   6ull},
70312         {"FORCEWRITE"                  ,        16,     4,      306,    "R/W",  0,      0,      0ull,   0ull},
70313         {"ECC_ADR"                     ,        20,     1,      306,    "R/W",  0,      0,      0ull,   1ull},
70314         {"RESERVED_21_63"              ,        21,     43,     306,    "RAZ",  1,      1,      0,      0},
70315         {"DCLKCNT_HI"                  ,        0,      32,     307,    "RO",   0,      0,      0ull,   0ull},
70316         {"RESERVED_32_63"              ,        32,     32,     307,    "RAZ",  1,      1,      0,      0},
70317         {"DCLKCNT_LO"                  ,        0,      32,     308,    "RO",   0,      0,      0ull,   0ull},
70318         {"RESERVED_32_63"              ,        32,     32,     308,    "RAZ",  1,      1,      0,      0},
70319         {"DDR2"                        ,        0,      1,      309,    "R/W",  0,      0,      1ull,   1ull},
70320         {"RDQS"                        ,        1,      1,      309,    "R/W",  0,      0,      0ull,   0ull},
70321         {"DLL90_BYP"                   ,        2,      1,      309,    "R/W",  0,      0,      0ull,   0ull},
70322         {"DLL90_VLU"                   ,        3,      5,      309,    "R/W",  0,      1,      0ull,   0},
70323         {"QDLL_ENA"                    ,        8,      1,      309,    "R/W",  0,      0,      0ull,   0ull},
70324         {"ODT_ENA"                     ,        9,      1,      309,    "R/W",  0,      0,      0ull,   0ull},
70325         {"DDR2T"                       ,        10,     1,      309,    "R/W",  0,      1,      0ull,   0},
70326         {"CRIP_MODE"                   ,        11,     1,      309,    "R/W",  0,      0,      0ull,   0ull},
70327         {"TFAW"                        ,        12,     5,      309,    "R/W",  0,      0,      0ull,   9ull},
70328         {"DDR_EOF"                     ,        17,     4,      309,    "R/W",  0,      0,      0ull,   0ull},
70329         {"SILO_HC"                     ,        21,     1,      309,    "R/W",  0,      1,      1ull,   0},
70330         {"TWR"                         ,        22,     3,      309,    "R/W",  0,      0,      3ull,   1ull},
70331         {"BWCNT"                       ,        25,     1,      309,    "R/W",  0,      0,      0ull,   0ull},
70332         {"POCAS"                       ,        26,     1,      309,    "R/W",  0,      0,      0ull,   0ull},
70333         {"ADDLAT"                      ,        27,     3,      309,    "R/W",  0,      0,      0ull,   0ull},
70334         {"BURST8"                      ,        30,     1,      309,    "R/W",  0,      0,      0ull,   1ull},
70335         {"BANK8"                       ,        31,     1,      309,    "R/W",  0,      1,      0ull,   0},
70336         {"RESERVED_32_63"              ,        32,     32,     309,    "RAZ",  0,      0,      0ull,   0ull},
70337         {"CLK"                         ,        0,      4,      310,    "R/W",  0,      0,      0ull,   0ull},
70338         {"RESERVED_4_4"                ,        4,      1,      310,    "RAZ",  0,      0,      0ull,   0ull},
70339         {"CMD"                         ,        5,      4,      310,    "R/W",  0,      0,      0ull,   0ull},
70340         {"RESERVED_9_9"                ,        9,      1,      310,    "RAZ",  0,      0,      0ull,   0ull},
70341         {"DQ"                          ,        10,     4,      310,    "R/W",  0,      0,      0ull,   0ull},
70342         {"RESERVED_14_63"              ,        14,     50,     310,    "RAZ",  0,      0,      0ull,   0ull},
70343         {"DLL90_VLU"                   ,        0,      5,      311,    "R/W",  0,      1,      0ull,   0},
70344         {"DLL90_ENA"                   ,        5,      1,      311,    "R/W",  0,      0,      0ull,   0ull},
70345         {"DLL90_BYP"                   ,        6,      1,      311,    "R/W",  0,      0,      0ull,   0ull},
70346         {"DRESET"                      ,        7,      1,      311,    "R/W",  0,      0,      1ull,   0ull},
70347         {"RESERVED_8_63"               ,        8,      56,     311,    "RAZ",  1,      1,      0,      0},
70348         {"CS_MASK"                     ,        0,      8,      312,    "R/W",  0,      1,      0ull,   0},
70349         {"RESERVED_8_15"               ,        8,      8,      312,    "RAZ",  0,      1,      0ull,   0},
70350         {"ROW_LSB"                     ,        16,     3,      312,    "R/W",  0,      1,      3ull,   0},
70351         {"BANK8"                       ,        19,     1,      312,    "R/W",  0,      1,      0ull,   0},
70352         {"RESERVED_20_63"              ,        20,     44,     312,    "RAZ",  0,      1,      0ull,   0},
70353         {"MRDSYN0"                     ,        0,      8,      313,    "RO",   0,      0,      0ull,   0ull},
70354         {"MRDSYN1"                     ,        8,      8,      313,    "RO",   0,      0,      0ull,   0ull},
70355         {"MRDSYN2"                     ,        16,     8,      313,    "RO",   0,      0,      0ull,   0ull},
70356         {"MRDSYN3"                     ,        24,     8,      313,    "RO",   0,      0,      0ull,   0ull},
70357         {"RESERVED_32_63"              ,        32,     32,     313,    "RAZ",  1,      1,      0,      0},
70358         {"FCOL"                        ,        0,      12,     314,    "RO",   0,      0,      0ull,   0ull},
70359         {"FROW"                        ,        12,     14,     314,    "RO",   0,      0,      0ull,   0ull},
70360         {"FBANK"                       ,        26,     3,      314,    "RO",   0,      0,      0ull,   0ull},
70361         {"FBUNK"                       ,        29,     1,      314,    "RO",   0,      0,      0ull,   0ull},
70362         {"FDIMM"                       ,        30,     2,      314,    "RO",   0,      0,      0ull,   0ull},
70363         {"RESERVED_32_63"              ,        32,     32,     314,    "RAZ",  1,      1,      0,      0},
70364         {"IFBCNT_HI"                   ,        0,      32,     315,    "RO",   0,      0,      0ull,   0ull},
70365         {"RESERVED_32_63"              ,        32,     32,     315,    "RAZ",  1,      1,      0,      0},
70366         {"IFBCNT_LO"                   ,        0,      32,     316,    "RO",   0,      0,      0ull,   0ull},
70367         {"RESERVED_32_63"              ,        32,     32,     316,    "RAZ",  1,      1,      0,      0},
70368         {"INIT_START"                  ,        0,      1,      317,    "WR0",  0,      0,      0ull,   0ull},
70369         {"ECC_ENA"                     ,        1,      1,      317,    "R/W",  0,      0,      0ull,   1ull},
70370         {"ROW_LSB"                     ,        2,      3,      317,    "R/W",  0,      1,      3ull,   0},
70371         {"PBANK_LSB"                   ,        5,      4,      317,    "R/W",  0,      1,      5ull,   0},
70372         {"REF_INT"                     ,        9,      6,      317,    "R/W",  0,      0,      1ull,   2ull},
70373         {"TCL"                         ,        15,     4,      317,    "R/W",  0,      1,      3ull,   0},
70374         {"INTR_SEC_ENA"                ,        19,     1,      317,    "R/W",  0,      0,      0ull,   1ull},
70375         {"INTR_DED_ENA"                ,        20,     1,      317,    "R/W",  0,      0,      0ull,   1ull},
70376         {"SEC_ERR"                     ,        21,     4,      317,    "R/W1C",        0,      0,      0ull,   0ull},
70377         {"DED_ERR"                     ,        25,     4,      317,    "R/W1C",        0,      0,      0ull,   0ull},
70378         {"BUNK_ENA"                    ,        29,     1,      317,    "R/W",  0,      1,      0ull,   0},
70379         {"SILO_QC"                     ,        30,     1,      317,    "R/W",  0,      1,      0ull,   0},
70380         {"RESET"                       ,        31,     1,      317,    "RAZ",  1,      1,      0,      0},
70381         {"RESERVED_32_63"              ,        32,     32,     317,    "RAZ",  1,      1,      0,      0},
70382         {"TRAS"                        ,        0,      5,      318,    "R/W",  0,      0,      12ull,  12ull},
70383         {"TRCD"                        ,        5,      4,      318,    "R/W",  0,      0,      4ull,   4ull},
70384         {"TWTR"                        ,        9,      4,      318,    "R/W",  0,      0,      2ull,   2ull},
70385         {"TRP"                         ,        13,     4,      318,    "R/W",  0,      0,      5ull,   4ull},
70386         {"TRFC"                        ,        17,     5,      318,    "R/W",  0,      0,      6ull,   7ull},
70387         {"TMRD"                        ,        22,     3,      318,    "R/W",  0,      0,      2ull,   2ull},
70388         {"CASLAT"                      ,        25,     3,      318,    "R/W",  0,      0,      4ull,   4ull},
70389         {"TRRD"                        ,        28,     3,      318,    "R/W",  0,      0,      2ull,   2ull},
70390         {"RESERVED_31_63"              ,        31,     33,     318,    "RAZ",  1,      1,      0,      0},
70391         {"CS_MASK"                     ,        0,      8,      319,    "R/W",  0,      1,      0ull,   0},
70392         {"RESERVED_8_63"               ,        8,      56,     319,    "RAZ",  1,      1,      0,      0},
70393         {"OPSCNT_HI"                   ,        0,      32,     320,    "RO",   0,      0,      0ull,   0ull},
70394         {"RESERVED_32_63"              ,        32,     32,     320,    "RAZ",  1,      1,      0,      0},
70395         {"OPSCNT_LO"                   ,        0,      32,     321,    "RO",   0,      0,      0ull,   0ull},
70396         {"RESERVED_32_63"              ,        32,     32,     321,    "RAZ",  1,      1,      0,      0},
70397         {"EN2"                         ,        0,      1,      322,    "R/W",  0,      1,      0ull,   0},
70398         {"EN4"                         ,        1,      1,      322,    "R/W",  0,      1,      0ull,   0},
70399         {"EN6"                         ,        2,      1,      322,    "R/W",  0,      1,      0ull,   0},
70400         {"EN8"                         ,        3,      1,      322,    "R/W",  0,      1,      1ull,   0},
70401         {"EN12"                        ,        4,      1,      322,    "R/W",  0,      1,      0ull,   0},
70402         {"EN16"                        ,        5,      1,      322,    "R/W",  0,      1,      0ull,   0},
70403         {"RESERVED_6_7"                ,        6,      2,      322,    "RAZ",  0,      1,      0ull,   0},
70404         {"CLKR"                        ,        8,      6,      322,    "R/W",  0,      1,      0ull,   0},
70405         {"CLKF"                        ,        14,     12,     322,    "R/W",  0,      1,      31ull,  0},
70406         {"RESET_N"                     ,        26,     1,      322,    "R/W",  0,      0,      0ull,   1ull},
70407         {"DIV_RESET"                   ,        27,     1,      322,    "R/W",  0,      0,      1ull,   0ull},
70408         {"FASTEN_N"                    ,        28,     1,      322,    "R/W",  0,      0,      0ull,   1ull},
70409         {"BYPASS"                      ,        29,     1,      322,    "R/W",  0,      0,      0ull,   0ull},
70410         {"RESERVED_30_63"              ,        30,     34,     322,    "RAZ",  0,      1,      0ull,   0},
70411         {"FBSLIP"                      ,        0,      1,      323,    "R/W1C",        0,      1,      0ull,   0},
70412         {"RFSLIP"                      ,        1,      1,      323,    "R/W1C",        0,      1,      0ull,   0},
70413         {"RESERVED_2_21"               ,        2,      20,     323,    "RAZ",  1,      1,      0,      0},
70414         {"DDR__PCTL"                   ,        22,     5,      323,    "RO",   1,      1,      0,      0},
70415         {"DDR__NCTL"                   ,        27,     5,      323,    "RO",   1,      1,      0,      0},
70416         {"RESERVED_32_63"              ,        32,     32,     323,    "RAZ",  1,      1,      0,      0},
70417         {"BNK"                         ,        0,      3,      324,    "R/W",  0,      0,      0ull,   0ull},
70418         {"RESERVED_3_3"                ,        3,      1,      324,    "RAZ",  0,      0,      0ull,   0ull},
70419         {"COL"                         ,        4,      12,     324,    "R/W",  0,      0,      0ull,   0ull},
70420         {"ROW"                         ,        16,     16,     324,    "R/W",  0,      0,      0ull,   0ull},
70421         {"PATTERN"                     ,        32,     8,      324,    "R/W",  0,      0,      170ull, 170ull},
70422         {"RANKMASK"                    ,        40,     4,      324,    "R/W",  0,      0,      0ull,   0ull},
70423         {"RESERVED_44_63"              ,        44,     20,     324,    "RAZ",  0,      0,      0ull,   0ull},
70424         {"BYTE"                        ,        0,      4,      325,    "R/W",  0,      0,      0ull,   0ull},
70425         {"RESERVED_4_15"               ,        4,      12,     325,    "RAZ",  0,      0,      0ull,   0ull},
70426         {"BITMASK"                     ,        16,     16,     325,    "RO",   0,      0,      0ull,   0ull},
70427         {"RESERVED_32_63"              ,        32,     32,     325,    "RAZ",  0,      0,      0ull,   0ull},
70428         {"BYTE0"                       ,        0,      4,      326,    "R/W",  0,      1,      0ull,   0},
70429         {"BYTE1"                       ,        4,      4,      326,    "R/W",  0,      1,      0ull,   0},
70430         {"BYTE2"                       ,        8,      4,      326,    "R/W",  0,      1,      0ull,   0},
70431         {"BYTE3"                       ,        12,     4,      326,    "R/W",  0,      1,      0ull,   0},
70432         {"BYTE4"                       ,        16,     4,      326,    "R/W",  0,      1,      0ull,   0},
70433         {"BYTE5"                       ,        20,     4,      326,    "R/W",  0,      1,      0ull,   0},
70434         {"BYTE6"                       ,        24,     4,      326,    "R/W",  0,      1,      0ull,   0},
70435         {"BYTE7"                       ,        28,     4,      326,    "R/W",  0,      1,      0ull,   0},
70436         {"BYTE8"                       ,        32,     4,      326,    "R/W",  0,      1,      0ull,   0},
70437         {"STATUS"                      ,        36,     2,      326,    "RO",   0,      1,      0ull,   0},
70438         {"RESERVED_38_63"              ,        38,     26,     326,    "RAZ",  1,      0,      0,      0ull},
70439         {"PCTL"                        ,        0,      5,      327,    "R/W",  0,      1,      0ull,   0},
70440         {"RESERVED_5_7"                ,        5,      3,      327,    "RAZ",  0,      1,      0ull,   0},
70441         {"NCTL"                        ,        8,      4,      327,    "R/W",  0,      1,      0ull,   0},
70442         {"RESERVED_12_15"              ,        12,     4,      327,    "RAZ",  0,      1,      0ull,   0},
70443         {"ENABLE"                      ,        16,     1,      327,    "R/W",  0,      1,      0ull,   0},
70444         {"RESERVED_17_63"              ,        17,     47,     327,    "RAZ",  0,      1,      0ull,   0},
70445         {"RODT_LO0"                    ,        0,      4,      328,    "R/W",  0,      0,      15ull,  15ull},
70446         {"RODT_LO1"                    ,        4,      4,      328,    "R/W",  0,      0,      15ull,  15ull},
70447         {"RODT_LO2"                    ,        8,      4,      328,    "R/W",  0,      0,      15ull,  15ull},
70448         {"RODT_LO3"                    ,        12,     4,      328,    "R/W",  0,      0,      15ull,  15ull},
70449         {"RODT_HI0"                    ,        16,     4,      328,    "R/W",  0,      0,      15ull,  15ull},
70450         {"RODT_HI1"                    ,        20,     4,      328,    "R/W",  0,      0,      15ull,  15ull},
70451         {"RODT_HI2"                    ,        24,     4,      328,    "R/W",  0,      0,      15ull,  15ull},
70452         {"RODT_HI3"                    ,        28,     4,      328,    "R/W",  0,      0,      15ull,  15ull},
70453         {"RESERVED_32_63"              ,        32,     32,     328,    "RAZ",  1,      1,      0,      0},
70454         {"WODT_D0_R0"                  ,        0,      8,      329,    "R/W",  0,      0,      255ull, 255ull},
70455         {"WODT_D0_R1"                  ,        8,      8,      329,    "R/W",  0,      0,      255ull, 255ull},
70456         {"WODT_D1_R0"                  ,        16,     8,      329,    "R/W",  0,      0,      255ull, 255ull},
70457         {"WODT_D1_R1"                  ,        24,     8,      329,    "R/W",  0,      0,      255ull, 255ull},
70458         {"RESERVED_32_63"              ,        32,     32,     329,    "RAZ",  0,      0,      0ull,   0ull},
70459         {"WODT_D2_R0"                  ,        0,      8,      330,    "R/W",  0,      0,      255ull, 255ull},
70460         {"WODT_D2_R1"                  ,        8,      8,      330,    "R/W",  0,      0,      255ull, 255ull},
70461         {"WODT_D3_R0"                  ,        16,     8,      330,    "R/W",  0,      0,      255ull, 255ull},
70462         {"WODT_D3_R1"                  ,        24,     8,      330,    "R/W",  0,      0,      255ull, 255ull},
70463         {"RESERVED_32_63"              ,        32,     32,     330,    "RAZ",  0,      0,      0ull,   0ull},
70464         {"NCBI"                        ,        0,      1,      331,    "RO",   0,      0,      0ull,   0ull},
70465         {"LOC"                         ,        1,      1,      331,    "RO",   0,      0,      0ull,   0ull},
70466         {"DMA"                         ,        2,      1,      331,    "RO",   0,      0,      0ull,   0ull},
70467         {"NCBO_0"                      ,        3,      1,      331,    "RO",   0,      0,      0ull,   0ull},
70468         {"NDF"                         ,        4,      2,      331,    "RO",   0,      0,      0ull,   0ull},
70469         {"RESERVED_6_63"               ,        6,      58,     331,    "RAZ",  1,      1,      0,      0},
70470         {"NCTL"                        ,        0,      5,      332,    "R/W",  1,      1,      0,      0},
70471         {"PCTL"                        ,        5,      5,      332,    "R/W",  1,      1,      0,      0},
70472         {"RESERVED_10_63"              ,        10,     54,     332,    "RAZ",  1,      1,      0,      0},
70473         {"ADR"                         ,        0,      36,     333,    "R/W",  0,      1,      0ull,   0},
70474         {"SIZE"                        ,        36,     20,     333,    "R/W",  0,      1,      0ull,   0},
70475         {"ENDIAN"                      ,        56,     1,      333,    "R/W",  0,      1,      0ull,   0},
70476         {"SWAP8"                       ,        57,     1,      333,    "R/W",  0,      1,      0ull,   0},
70477         {"SWAP16"                      ,        58,     1,      333,    "R/W",  0,      1,      0ull,   0},
70478         {"SWAP32"                      ,        59,     1,      333,    "R/W",  0,      1,      0ull,   0},
70479         {"RESERVED_60_60"              ,        60,     1,      333,    "RAZ",  1,      1,      0,      0},
70480         {"CLR"                         ,        61,     1,      333,    "R/W",  0,      1,      0ull,   0},
70481         {"RW"                          ,        62,     1,      333,    "R/W",  0,      1,      0ull,   0},
70482         {"EN"                          ,        63,     1,      333,    "R/W",  0,      1,      0ull,   0},
70483         {"DONE"                        ,        0,      1,      334,    "R/W1C",        0,      1,      0ull,   0},
70484         {"DMARQ"                       ,        1,      1,      334,    "RO",   1,      1,      0,      0},
70485         {"RESERVED_2_63"               ,        2,      62,     334,    "RAZ",  1,      1,      0,      0},
70486         {"DONE"                        ,        0,      1,      335,    "R/W",  0,      1,      0ull,   0},
70487         {"DMARQ"                       ,        1,      1,      335,    "R/W",  0,      1,      0ull,   0},
70488         {"RESERVED_2_63"               ,        2,      62,     335,    "RAZ",  1,      1,      0,      0},
70489         {"DMARQ"                       ,        0,      6,      336,    "R/W",  0,      1,      63ull,  0},
70490         {"DMACK_S"                     ,        6,      6,      336,    "R/W",  0,      1,      63ull,  0},
70491         {"OE_A"                        ,        12,     6,      336,    "R/W",  0,      1,      63ull,  0},
70492         {"OE_N"                        ,        18,     6,      336,    "R/W",  0,      1,      63ull,  0},
70493         {"WE_A"                        ,        24,     6,      336,    "R/W",  0,      1,      63ull,  0},
70494         {"WE_N"                        ,        30,     6,      336,    "R/W",  0,      1,      63ull,  0},
70495         {"DMACK_H"                     ,        36,     6,      336,    "R/W",  0,      1,      63ull,  0},
70496         {"PAUSE"                       ,        42,     6,      336,    "R/W",  0,      1,      63ull,  0},
70497         {"RESERVED_48_54"              ,        48,     7,      336,    "RAZ",  1,      1,      0,      0},
70498         {"WIDTH"                       ,        55,     1,      336,    "R/W",  0,      1,      0ull,   0},
70499         {"DDR"                         ,        56,     1,      336,    "R/W",  0,      1,      0ull,   0},
70500         {"RD_DLY"                      ,        57,     3,      336,    "R/W",  0,      1,      0ull,   0},
70501         {"TIM_MULT"                    ,        60,     2,      336,    "R/W",  0,      1,      0ull,   0},
70502         {"DMARQ_PI"                    ,        62,     1,      336,    "R/W",  0,      1,      0ull,   0},
70503         {"DMACK_PI"                    ,        63,     1,      336,    "R/W",  0,      1,      0ull,   0},
70504         {"ADR_ERR"                     ,        0,      1,      337,    "R/W1C",        0,      0,      0ull,   0ull},
70505         {"WAIT_ERR"                    ,        1,      1,      337,    "R/W1C",        0,      0,      0ull,   0ull},
70506         {"RESERVED_2_63"               ,        2,      62,     337,    "RAZ",  1,      1,      0,      0},
70507         {"ADR_INT"                     ,        0,      1,      338,    "R/W",  0,      1,      0ull,   0},
70508         {"WAIT_INT"                    ,        1,      1,      338,    "R/W",  0,      1,      0ull,   0},
70509         {"RESERVED_2_63"               ,        2,      62,     338,    "RAZ",  1,      1,      0,      0},
70510         {"RESERVED_0_2"                ,        0,      3,      339,    "RAZ",  1,      1,      0,      0},
70511         {"ADR"                         ,        3,      5,      339,    "R/W",  0,      1,      0ull,   0},
70512         {"RESERVED_8_63"               ,        8,      56,     339,    "RAZ",  1,      1,      0,      0},
70513         {"RESERVED_0_2"                ,        0,      3,      340,    "RAZ",  1,      1,      0,      0},
70514         {"BASE"                        ,        3,      25,     340,    "R/W",  0,      1,      0ull,   0},
70515         {"RESERVED_28_30"              ,        28,     3,      340,    "RAZ",  1,      1,      0,      0},
70516         {"EN"                          ,        31,     1,      340,    "R/W",  0,      1,      0ull,   0},
70517         {"RESERVED_32_63"              ,        32,     32,     340,    "RAZ",  1,      1,      0,      0},
70518         {"DATA"                        ,        0,      64,     341,    "R/W",  1,      1,      0,      0},
70519         {"RESERVED_0_7"                ,        0,      8,      342,    "RAZ",  1,      1,      0,      0},
70520         {"NAND"                        ,        8,      1,      342,    "RO",   1,      1,      0,      0},
70521         {"TERM"                        ,        9,      2,      342,    "RO",   1,      1,      0,      0},
70522         {"DMACK_P0"                    ,        11,     1,      342,    "RO",   1,      1,      0,      0},
70523         {"DMACK_P1"                    ,        12,     1,      342,    "RO",   1,      1,      0,      0},
70524         {"RESERVED_13_13"              ,        13,     1,      342,    "RAZ",  1,      1,      0,      0},
70525         {"WIDTH"                       ,        14,     1,      342,    "RO",   1,      1,      0,      0},
70526         {"ALE"                         ,        15,     1,      342,    "RO",   1,      1,      0,      0},
70527         {"RESERVED_16_63"              ,        16,     48,     342,    "RAZ",  1,      1,      0,      0},
70528         {"BASE"                        ,        0,      16,     343,    "R/W",  0,      1,      0ull,   0},
70529         {"SIZE"                        ,        16,     12,     343,    "R/W",  0,      1,      0ull,   0},
70530         {"WIDTH"                       ,        28,     1,      343,    "R/W",  0,      1,      0ull,   0},
70531         {"ALE"                         ,        29,     1,      343,    "R/W",  0,      1,      0ull,   0},
70532         {"ORBIT"                       ,        30,     1,      343,    "R/W",  0,      1,      0ull,   0},
70533         {"EN"                          ,        31,     1,      343,    "R/W",  0,      1,      0ull,   0},
70534         {"OE_EXT"                      ,        32,     2,      343,    "R/W",  0,      1,      0ull,   0},
70535         {"WE_EXT"                      ,        34,     2,      343,    "R/W",  0,      1,      0ull,   0},
70536         {"SAM"                         ,        36,     1,      343,    "R/W",  0,      1,      0ull,   0},
70537         {"RD_DLY"                      ,        37,     3,      343,    "R/W",  0,      1,      0ull,   0},
70538         {"TIM_MULT"                    ,        40,     2,      343,    "R/W",  0,      1,      0ull,   0},
70539         {"DMACK"                       ,        42,     2,      343,    "R/W",  0,      1,      0ull,   0},
70540         {"RESERVED_44_63"              ,        44,     20,     343,    "RAZ",  1,      1,      0,      0},
70541         {"ADR"                         ,        0,      6,      344,    "R/W",  0,      1,      63ull,  0},
70542         {"CE"                          ,        6,      6,      344,    "R/W",  0,      1,      63ull,  0},
70543         {"OE"                          ,        12,     6,      344,    "R/W",  0,      1,      63ull,  0},
70544         {"WE"                          ,        18,     6,      344,    "R/W",  0,      1,      63ull,  0},
70545         {"RD_HLD"                      ,        24,     6,      344,    "R/W",  0,      1,      63ull,  0},
70546         {"WR_HLD"                      ,        30,     6,      344,    "R/W",  0,      1,      63ull,  0},
70547         {"PAUSE"                       ,        36,     6,      344,    "R/W",  0,      1,      63ull,  0},
70548         {"WAIT"                        ,        42,     6,      344,    "R/W",  0,      1,      63ull,  0},
70549         {"PAGE"                        ,        48,     6,      344,    "R/W",  0,      1,      63ull,  0},
70550         {"ALE"                         ,        54,     6,      344,    "R/W",  0,      1,      63ull,  0},
70551         {"PAGES"                       ,        60,     2,      344,    "R/W",  0,      1,      0ull,   0},
70552         {"WAITM"                       ,        62,     1,      344,    "R/W",  0,      1,      0ull,   0},
70553         {"PAGEM"                       ,        63,     1,      344,    "R/W",  0,      1,      0ull,   0},
70554         {"FIF_THR"                     ,        0,      6,      345,    "R/W",  0,      0,      25ull,  25ull},
70555         {"RESERVED_6_7"                ,        6,      2,      345,    "RAZ",  1,      1,      0,      0},
70556         {"FIF_CNT"                     ,        8,      6,      345,    "RO",   0,      1,      0ull,   0},
70557         {"RESERVED_14_15"              ,        14,     2,      345,    "RAZ",  1,      1,      0,      0},
70558         {"DMA_THR"                     ,        16,     6,      345,    "R/W",  0,      1,      0ull,   0},
70559         {"RESERVED_22_63"              ,        22,     42,     345,    "RAZ",  1,      1,      0,      0},
70560         {"DAT"                         ,        0,      64,     346,    "R/W",  1,      1,      0,      0},
70561         {"MAN_INFO"                    ,        0,      32,     347,    "RO",   1,      1,      0,      0},
70562         {"RESERVED_32_63"              ,        32,     32,     347,    "RAZ",  1,      1,      0,      0},
70563         {"MAN_INFO"                    ,        0,      32,     348,    "RO",   1,      1,      0,      0},
70564         {"RESERVED_32_63"              ,        32,     32,     348,    "RAZ",  1,      1,      0,      0},
70565         {"PP_DIS"                      ,        0,      4,      349,    "RO",   1,      1,      0,      0},
70566         {"RESERVED_4_15"               ,        4,      12,     349,    "RO",   1,      1,      0,      0},
70567         {"CHIP_ID"                     ,        16,     8,      349,    "RO",   1,      1,      0,      0},
70568         {"BIST_DIS"                    ,        24,     1,      349,    "RO",   1,      1,      0,      0},
70569         {"RST_SHT"                     ,        25,     1,      349,    "RO",   1,      1,      0,      0},
70570         {"NOCRYPTO"                    ,        26,     1,      349,    "RO",   1,      1,      0,      0},
70571         {"NOMUL"                       ,        27,     1,      349,    "RO",   1,      1,      0,      0},
70572         {"NODFA_CP2"                   ,        28,     1,      349,    "RO",   1,      1,      0,      0},
70573         {"NOKASU"                      ,        29,     1,      349,    "RO",   1,      1,      0,      0},
70574         {"RESERVED_30_31"              ,        30,     2,      349,    "RAZ",  1,      1,      0,      0},
70575         {"RAID_EN"                     ,        32,     1,      349,    "RO",   1,      1,      0,      0},
70576         {"FUS318"                      ,        33,     1,      349,    "RO",   1,      1,      0,      0},
70577         {"RESERVED_34_63"              ,        34,     30,     349,    "RAZ",  1,      1,      0,      0},
70578         {"ICACHE"                      ,        0,      24,     350,    "RO",   1,      1,      0,      0},
70579         {"NODFA_DTE"                   ,        24,     1,      350,    "RO",   1,      1,      0,      0},
70580         {"NOZIP"                       ,        25,     1,      350,    "RO",   1,      1,      0,      0},
70581         {"EFUS_IGN"                    ,        26,     1,      350,    "RO",   1,      1,      0,      0},
70582         {"EFUS_LCK"                    ,        27,     1,      350,    "RO",   1,      1,      0,      0},
70583         {"BAR2_EN"                     ,        28,     1,      350,    "RO",   1,      1,      0,      0},
70584         {"ZIP_CRIP"                    ,        29,     2,      350,    "RO",   1,      1,      0,      0},
70585         {"RESERVED_31_63"              ,        31,     33,     350,    "RAZ",  1,      1,      0,      0},
70586         {"EMA"                         ,        0,      3,      351,    "R/W",  1,      0,      0,      0ull},
70587         {"RESERVED_3_3"                ,        3,      1,      351,    "RAZ",  1,      1,      0,      0},
70588         {"EFF_EMA"                     ,        4,      3,      351,    "RO",   1,      0,      0,      0ull},
70589         {"RESERVED_7_63"               ,        7,      57,     351,    "RAZ",  1,      1,      0,      0},
70590         {"PDF"                         ,        0,      64,     352,    "RO",   1,      1,      0,      0},
70591         {"FBSLIP"                      ,        0,      1,      353,    "R/W1C",        0,      1,      0ull,   0},
70592         {"RFSLIP"                      ,        1,      1,      353,    "R/W1C",        0,      1,      0ull,   0},
70593         {"RESERVED_2_63"               ,        2,      62,     353,    "RAZ",  1,      1,      0,      0},
70594         {"PROG"                        ,        0,      1,      354,    "R/W",  1,      1,      0,      0},
70595         {"RESERVED_1_63"               ,        1,      63,     354,    "RAZ",  1,      1,      0,      0},
70596         {"SETUP"                       ,        0,      8,      355,    "R/W",  0,      1,      3ull,   0},
70597         {"SCLK_HI"                     ,        8,      12,     355,    "R/W",  0,      1,      100ull, 0},
70598         {"SCLK_LO"                     ,        20,     4,      355,    "R/W",  0,      1,      2ull,   0},
70599         {"OUT"                         ,        24,     8,      355,    "R/W",  0,      1,      3ull,   0},
70600         {"PROG_PIN"                    ,        32,     1,      355,    "RO",   0,      0,      0ull,   0ull},
70601         {"RESERVED_33_63"              ,        33,     31,     355,    "RAZ",  1,      1,      0,      0},
70602         {"ADDR"                        ,        0,      8,      356,    "R/W",  0,      0,      0ull,   0ull},
70603         {"EFUSE"                       ,        8,      1,      356,    "R/W",  0,      0,      0ull,   0ull},
70604         {"RESERVED_9_11"               ,        9,      3,      356,    "RAZ",  1,      1,      0,      0},
70605         {"PEND"                        ,        12,     1,      356,    "R/W",  0,      0,      0ull,   0ull},
70606         {"RESERVED_13_15"              ,        13,     3,      356,    "RAZ",  1,      1,      0,      0},
70607         {"DAT"                         ,        16,     8,      356,    "RO",   1,      1,      0,      0},
70608         {"RESERVED_24_63"              ,        24,     40,     356,    "RAZ",  1,      1,      0,      0},
70609         {"REPAIR0"                     ,        0,      14,     357,    "RO",   0,      0,      0ull,   0ull},
70610         {"REPAIR1"                     ,        14,     14,     357,    "RO",   0,      0,      0ull,   0ull},
70611         {"REPAIR2"                     ,        28,     14,     357,    "RO",   0,      0,      0ull,   0ull},
70612         {"RESERVED_42_63"              ,        42,     22,     357,    "RAZ",  1,      1,      0,      0},
70613         {"TOO_MANY"                    ,        0,      1,      358,    "RO",   0,      0,      0ull,   0ull},
70614         {"RESERVED_1_63"               ,        1,      63,     358,    "RAZ",  1,      1,      0,      0},
70615         {"ADDR"                        ,        0,      3,      359,    "R/W",  1,      1,      0,      0},
70616         {"RESERVED_3_63"               ,        3,      61,     359,    "RAZ",  1,      1,      0,      0},
70617         {"ADR"                         ,        0,      36,     360,    "R/W",  0,      1,      0ull,   0},
70618         {"SIZE"                        ,        36,     20,     360,    "R/W",  0,      1,      0ull,   0},
70619         {"ENDIAN"                      ,        56,     1,      360,    "R/W",  0,      1,      0ull,   0},
70620         {"SWAP8"                       ,        57,     1,      360,    "R/W",  0,      1,      0ull,   0},
70621         {"SWAP16"                      ,        58,     1,      360,    "R/W",  0,      1,      0ull,   0},
70622         {"SWAP32"                      ,        59,     1,      360,    "R/W",  0,      1,      0ull,   0},
70623         {"RESERVED_60_60"              ,        60,     1,      360,    "RAZ",  1,      1,      0,      0},
70624         {"CLR"                         ,        61,     1,      360,    "R/W",  0,      1,      0ull,   0},
70625         {"RW"                          ,        62,     1,      360,    "R/W",  0,      1,      0ull,   0},
70626         {"EN"                          ,        63,     1,      360,    "R/W",  0,      1,      0ull,   0},
70627         {"DONE"                        ,        0,      1,      361,    "R/W1C",        0,      1,      0ull,   0},
70628         {"RESERVED_1_63"               ,        1,      63,     361,    "RAZ",  1,      1,      0,      0},
70629         {"DONE"                        ,        0,      1,      362,    "R/W",  0,      1,      0ull,   0},
70630         {"RESERVED_1_63"               ,        1,      63,     362,    "RAZ",  1,      1,      0,      0},
70631         {"ST_INT"                      ,        0,      1,      363,    "R/W1C",        0,      1,      0ull,   0},
70632         {"TS_INT"                      ,        1,      1,      363,    "R/W1C",        0,      1,      0ull,   0},
70633         {"CORE_INT"                    ,        2,      1,      363,    "RO",   0,      1,      0ull,   0},
70634         {"RESERVED_3_3"                ,        3,      1,      363,    "RAZ",  1,      1,      0,      0},
70635         {"ST_EN"                       ,        4,      1,      363,    "R/W",  0,      1,      0ull,   0},
70636         {"TS_EN"                       ,        5,      1,      363,    "R/W",  0,      1,      0ull,   0},
70637         {"CORE_EN"                     ,        6,      1,      363,    "R/W",  0,      1,      0ull,   0},
70638         {"RESERVED_7_7"                ,        7,      1,      363,    "RAZ",  1,      1,      0,      0},
70639         {"SDA_OVR"                     ,        8,      1,      363,    "R/W",  0,      1,      0ull,   0},
70640         {"SCL_OVR"                     ,        9,      1,      363,    "R/W",  0,      1,      0ull,   0},
70641         {"SDA"                         ,        10,     1,      363,    "RO",   1,      1,      0,      0},
70642         {"SCL"                         ,        11,     1,      363,    "RO",   1,      1,      0,      0},
70643         {"RESERVED_12_63"              ,        12,     52,     363,    "RAZ",  1,      1,      0,      0},
70644         {"D"                           ,        0,      32,     364,    "R/W",  0,      1,      0ull,   0},
70645         {"EOP_IA"                      ,        32,     3,      364,    "R/W",  0,      1,      0ull,   0},
70646         {"IA"                          ,        35,     5,      364,    "R/W",  0,      1,      0ull,   0},
70647         {"A"                           ,        40,     10,     364,    "R/W",  0,      1,      0ull,   0},
70648         {"SCR"                         ,        50,     2,      364,    "R/W",  0,      1,      0ull,   0},
70649         {"SIZE"                        ,        52,     3,      364,    "R/W",  0,      1,      0ull,   0},
70650         {"SOVR"                        ,        55,     1,      364,    "R/W",  0,      1,      0ull,   0},
70651         {"R"                           ,        56,     1,      364,    "R/W",  0,      1,      0ull,   0},
70652         {"OP"                          ,        57,     4,      364,    "R/W",  0,      1,      0ull,   0},
70653         {"EIA"                         ,        61,     1,      364,    "R/W",  0,      1,      0ull,   0},
70654         {"SLONLY"                      ,        62,     1,      364,    "R/W",  0,      1,      0ull,   0},
70655         {"V"                           ,        63,     1,      364,    "RC/W", 0,      1,      0ull,   0},
70656         {"D"                           ,        0,      32,     365,    "R/W",  0,      1,      0ull,   0},
70657         {"IA"                          ,        32,     8,      365,    "R/W",  0,      1,      0ull,   0},
70658         {"RESERVED_40_63"              ,        40,     24,     365,    "RAZ",  1,      1,      0,      0},
70659         {"D"                           ,        0,      32,     366,    "R/W",  1,      1,      0,      0},
70660         {"RESERVED_32_61"              ,        32,     30,     366,    "RAZ",  1,      1,      0,      0},
70661         {"V"                           ,        62,     2,      366,    "RC/W", 0,      1,      0ull,   0},
70662         {"DLH"                         ,        0,      8,      367,    "R/W",  0,      1,      0ull,   0},
70663         {"RESERVED_8_63"               ,        8,      56,     367,    "RAZ",  1,      1,      0,      0},
70664         {"DLL"                         ,        0,      8,      368,    "R/W",  0,      1,      0ull,   0},
70665         {"RESERVED_8_63"               ,        8,      56,     368,    "RAZ",  1,      1,      0,      0},
70666         {"FAR"                         ,        0,      1,      369,    "R/W",  0,      1,      0ull,   0},
70667         {"RESERVED_1_63"               ,        1,      63,     369,    "RAZ",  1,      1,      0,      0},
70668         {"EN"                          ,        0,      1,      370,    "WO",   0,      1,      0ull,   0},
70669         {"RXFR"                        ,        1,      1,      370,    "WO",   0,      1,      0ull,   0},
70670         {"TXFR"                        ,        2,      1,      370,    "WO",   0,      1,      0ull,   0},
70671         {"RESERVED_3_3"                ,        3,      1,      370,    "RAZ",  0,      1,      0ull,   0},
70672         {"TXTRIG"                      ,        4,      2,      370,    "WO",   0,      1,      0ull,   0},
70673         {"RXTRIG"                      ,        6,      2,      370,    "WO",   0,      1,      0ull,   0},
70674         {"RESERVED_8_63"               ,        8,      56,     370,    "RAZ",  1,      1,      0,      0},
70675         {"HTX"                         ,        0,      1,      371,    "R/W",  0,      1,      0ull,   0},
70676         {"RESERVED_1_63"               ,        1,      63,     371,    "RAZ",  1,      1,      0,      0},
70677         {"ERBFI"                       ,        0,      1,      372,    "R/W",  0,      1,      0ull,   0},
70678         {"ETBEI"                       ,        1,      1,      372,    "R/W",  0,      1,      0ull,   0},
70679         {"ELSI"                        ,        2,      1,      372,    "R/W",  0,      1,      0ull,   0},
70680         {"EDSSI"                       ,        3,      1,      372,    "R/W",  0,      1,      0ull,   0},
70681         {"RESERVED_4_6"                ,        4,      3,      372,    "RAZ",  0,      1,      0ull,   0},
70682         {"PTIME"                       ,        7,      1,      372,    "R/W",  0,      1,      0ull,   0},
70683         {"RESERVED_8_63"               ,        8,      56,     372,    "RAZ",  1,      1,      0,      0},
70684         {"IID"                         ,        0,      4,      373,    "RO",   0,      1,      1ull,   0},
70685         {"RESERVED_4_5"                ,        4,      2,      373,    "RAZ",  0,      1,      0ull,   0},
70686         {"FEN"                         ,        6,      2,      373,    "RO",   0,      1,      0ull,   0},
70687         {"RESERVED_8_63"               ,        8,      56,     373,    "RAZ",  1,      1,      0,      0},
70688         {"CLS"                         ,        0,      2,      374,    "R/W",  0,      1,      0ull,   0},
70689         {"STOP"                        ,        2,      1,      374,    "R/W",  0,      1,      0ull,   0},
70690         {"PEN"                         ,        3,      1,      374,    "R/W",  0,      1,      0ull,   0},
70691         {"EPS"                         ,        4,      1,      374,    "R/W",  0,      1,      0ull,   0},
70692         {"RESERVED_5_5"                ,        5,      1,      374,    "RAZ",  0,      1,      0ull,   0},
70693         {"BRK"                         ,        6,      1,      374,    "R/W",  0,      1,      0ull,   0},
70694         {"DLAB"                        ,        7,      1,      374,    "R/W",  0,      1,      0ull,   0},
70695         {"RESERVED_8_63"               ,        8,      56,     374,    "RAZ",  1,      1,      0,      0},
70696         {"DR"                          ,        0,      1,      375,    "RO",   0,      1,      0ull,   0},
70697         {"OE"                          ,        1,      1,      375,    "RC",   0,      1,      0ull,   0},
70698         {"PE"                          ,        2,      1,      375,    "RC",   0,      1,      0ull,   0},
70699         {"FE"                          ,        3,      1,      375,    "RC",   0,      1,      0ull,   0},
70700         {"BI"                          ,        4,      1,      375,    "RC",   0,      1,      0ull,   0},
70701         {"THRE"                        ,        5,      1,      375,    "RO",   0,      1,      1ull,   0},
70702         {"TEMT"                        ,        6,      1,      375,    "RO",   0,      1,      1ull,   0},
70703         {"FERR"                        ,        7,      1,      375,    "RC",   0,      1,      0ull,   0},
70704         {"RESERVED_8_63"               ,        8,      56,     375,    "RAZ",  1,      1,      0,      0},
70705         {"DTR"                         ,        0,      1,      376,    "R/W",  0,      1,      0ull,   0},
70706         {"RTS"                         ,        1,      1,      376,    "R/W",  0,      1,      0ull,   0},
70707         {"OUT1"                        ,        2,      1,      376,    "R/W",  0,      1,      0ull,   0},
70708         {"OUT2"                        ,        3,      1,      376,    "R/W",  0,      1,      0ull,   0},
70709         {"LOOP"                        ,        4,      1,      376,    "R/W",  0,      1,      0ull,   0},
70710         {"AFCE"                        ,        5,      1,      376,    "R/W",  0,      1,      0ull,   0},
70711         {"RESERVED_6_63"               ,        6,      58,     376,    "RAZ",  0,      1,      0ull,   0},
70712         {"DCTS"                        ,        0,      1,      377,    "RC",   0,      1,      0ull,   0},
70713         {"DDSR"                        ,        1,      1,      377,    "RC",   0,      1,      0ull,   0},
70714         {"TERI"                        ,        2,      1,      377,    "RC",   0,      1,      0ull,   0},
70715         {"DDCD"                        ,        3,      1,      377,    "RC",   0,      1,      0ull,   0},
70716         {"CTS"                         ,        4,      1,      377,    "RO",   1,      1,      0,      0},
70717         {"DSR"                         ,        5,      1,      377,    "RO",   0,      1,      0ull,   0},
70718         {"RI"                          ,        6,      1,      377,    "RO",   0,      1,      0ull,   0},
70719         {"DCD"                         ,        7,      1,      377,    "RO",   0,      1,      0ull,   0},
70720         {"RESERVED_8_63"               ,        8,      56,     377,    "RAZ",  1,      1,      0,      0},
70721         {"RBR"                         ,        0,      8,      378,    "RO",   0,      1,      0ull,   0},
70722         {"RESERVED_8_63"               ,        8,      56,     378,    "RAZ",  1,      1,      0,      0},
70723         {"RFL"                         ,        0,      7,      379,    "RO",   0,      1,      0ull,   0},
70724         {"RESERVED_7_63"               ,        7,      57,     379,    "RAZ",  1,      1,      0,      0},
70725         {"RFWD"                        ,        0,      8,      380,    "WO",   0,      1,      0ull,   0},
70726         {"RFPE"                        ,        8,      1,      380,    "WO",   0,      1,      0ull,   0},
70727         {"RFFE"                        ,        9,      1,      380,    "WO",   0,      1,      0ull,   0},
70728         {"RESERVED_10_63"              ,        10,     54,     380,    "RAZ",  1,      1,      0,      0},
70729         {"SBCR"                        ,        0,      1,      381,    "R/W",  0,      1,      0ull,   0},
70730         {"RESERVED_1_63"               ,        1,      63,     381,    "RAZ",  1,      1,      0,      0},
70731         {"SCR"                         ,        0,      8,      382,    "R/W",  0,      1,      0ull,   0},
70732         {"RESERVED_8_63"               ,        8,      56,     382,    "RAZ",  1,      1,      0,      0},
70733         {"SFE"                         ,        0,      1,      383,    "R/W",  0,      1,      0ull,   0},
70734         {"RESERVED_1_63"               ,        1,      63,     383,    "RAZ",  1,      1,      0,      0},
70735         {"USR"                         ,        0,      1,      384,    "WO",   0,      1,      0ull,   0},
70736         {"SRFR"                        ,        1,      1,      384,    "WO",   0,      1,      0ull,   0},
70737         {"STFR"                        ,        2,      1,      384,    "WO",   0,      1,      0ull,   0},
70738         {"RESERVED_3_63"               ,        3,      61,     384,    "RAZ",  1,      1,      0,      0},
70739         {"SRT"                         ,        0,      2,      385,    "R/W",  0,      1,      0ull,   0},
70740         {"RESERVED_2_63"               ,        2,      62,     385,    "RAZ",  1,      1,      0,      0},
70741         {"SRTS"                        ,        0,      1,      386,    "R/W",  0,      1,      0ull,   0},
70742         {"RESERVED_1_63"               ,        1,      63,     386,    "RAZ",  1,      1,      0,      0},
70743         {"STT"                         ,        0,      2,      387,    "R/W",  0,      1,      0ull,   0},
70744         {"RESERVED_2_63"               ,        2,      62,     387,    "RAZ",  1,      1,      0,      0},
70745         {"TFL"                         ,        0,      7,      388,    "RO",   0,      1,      0ull,   0},
70746         {"RESERVED_7_63"               ,        7,      57,     388,    "RAZ",  1,      1,      0,      0},
70747         {"TFR"                         ,        0,      8,      389,    "RO",   0,      1,      0ull,   0},
70748         {"RESERVED_8_63"               ,        8,      56,     389,    "RAZ",  1,      1,      0,      0},
70749         {"THR"                         ,        0,      8,      390,    "WO",   0,      1,      0ull,   0},
70750         {"RESERVED_8_63"               ,        8,      56,     390,    "RAZ",  1,      1,      0,      0},
70751         {"BUSY"                        ,        0,      1,      391,    "RO",   0,      1,      0ull,   0},
70752         {"TFNF"                        ,        1,      1,      391,    "RO",   0,      1,      1ull,   0},
70753         {"TFE"                         ,        2,      1,      391,    "RO",   0,      1,      1ull,   0},
70754         {"RFNE"                        ,        3,      1,      391,    "RO",   0,      1,      0ull,   0},
70755         {"RFF"                         ,        4,      1,      391,    "RO",   0,      1,      0ull,   0},
70756         {"RESERVED_5_63"               ,        5,      59,     391,    "RAZ",  1,      1,      0,      0},
70757         {"DLH"                         ,        0,      8,      392,    "R/W",  0,      1,      0ull,   0},
70758         {"RESERVED_8_63"               ,        8,      56,     392,    "RAZ",  1,      1,      0,      0},
70759         {"DLL"                         ,        0,      8,      393,    "R/W",  0,      1,      0ull,   0},
70760         {"RESERVED_8_63"               ,        8,      56,     393,    "RAZ",  1,      1,      0,      0},
70761         {"FAR"                         ,        0,      1,      394,    "R/W",  0,      1,      0ull,   0},
70762         {"RESERVED_1_63"               ,        1,      63,     394,    "RAZ",  1,      1,      0,      0},
70763         {"EN"                          ,        0,      1,      395,    "WO",   0,      1,      0ull,   0},
70764         {"RXFR"                        ,        1,      1,      395,    "WO",   0,      1,      0ull,   0},
70765         {"TXFR"                        ,        2,      1,      395,    "WO",   0,      1,      0ull,   0},
70766         {"RESERVED_3_3"                ,        3,      1,      395,    "RAZ",  0,      1,      0ull,   0},
70767         {"TXTRIG"                      ,        4,      2,      395,    "WO",   0,      1,      0ull,   0},
70768         {"RXTRIG"                      ,        6,      2,      395,    "WO",   0,      1,      0ull,   0},
70769         {"RESERVED_8_63"               ,        8,      56,     395,    "RAZ",  1,      1,      0,      0},
70770         {"HTX"                         ,        0,      1,      396,    "R/W",  0,      1,      0ull,   0},
70771         {"RESERVED_1_63"               ,        1,      63,     396,    "RAZ",  1,      1,      0,      0},
70772         {"ERBFI"                       ,        0,      1,      397,    "R/W",  0,      1,      0ull,   0},
70773         {"ETBEI"                       ,        1,      1,      397,    "R/W",  0,      1,      0ull,   0},
70774         {"ELSI"                        ,        2,      1,      397,    "R/W",  0,      1,      0ull,   0},
70775         {"EDSSI"                       ,        3,      1,      397,    "R/W",  0,      1,      0ull,   0},
70776         {"RESERVED_4_6"                ,        4,      3,      397,    "RAZ",  0,      1,      0ull,   0},
70777         {"PTIME"                       ,        7,      1,      397,    "R/W",  0,      1,      0ull,   0},
70778         {"RESERVED_8_63"               ,        8,      56,     397,    "RAZ",  1,      1,      0,      0},
70779         {"IID"                         ,        0,      4,      398,    "RO",   0,      1,      1ull,   0},
70780         {"RESERVED_4_5"                ,        4,      2,      398,    "RAZ",  0,      1,      0ull,   0},
70781         {"FEN"                         ,        6,      2,      398,    "RO",   0,      1,      0ull,   0},
70782         {"RESERVED_8_63"               ,        8,      56,     398,    "RAZ",  1,      1,      0,      0},
70783         {"CLS"                         ,        0,      2,      399,    "R/W",  0,      1,      0ull,   0},
70784         {"STOP"                        ,        2,      1,      399,    "R/W",  0,      1,      0ull,   0},
70785         {"PEN"                         ,        3,      1,      399,    "R/W",  0,      1,      0ull,   0},
70786         {"EPS"                         ,        4,      1,      399,    "R/W",  0,      1,      0ull,   0},
70787         {"RESERVED_5_5"                ,        5,      1,      399,    "RAZ",  0,      1,      0ull,   0},
70788         {"BRK"                         ,        6,      1,      399,    "R/W",  0,      1,      0ull,   0},
70789         {"DLAB"                        ,        7,      1,      399,    "R/W",  0,      1,      0ull,   0},
70790         {"RESERVED_8_63"               ,        8,      56,     399,    "RAZ",  1,      1,      0,      0},
70791         {"DR"                          ,        0,      1,      400,    "RO",   0,      1,      0ull,   0},
70792         {"OE"                          ,        1,      1,      400,    "RC",   0,      1,      0ull,   0},
70793         {"PE"                          ,        2,      1,      400,    "RC",   0,      1,      0ull,   0},
70794         {"FE"                          ,        3,      1,      400,    "RC",   0,      1,      0ull,   0},
70795         {"BI"                          ,        4,      1,      400,    "RC",   0,      1,      0ull,   0},
70796         {"THRE"                        ,        5,      1,      400,    "RO",   0,      1,      1ull,   0},
70797         {"TEMT"                        ,        6,      1,      400,    "RO",   0,      1,      1ull,   0},
70798         {"FERR"                        ,        7,      1,      400,    "RC",   0,      1,      0ull,   0},
70799         {"RESERVED_8_63"               ,        8,      56,     400,    "RAZ",  1,      1,      0,      0},
70800         {"DTR"                         ,        0,      1,      401,    "R/W",  0,      1,      0ull,   0},
70801         {"RTS"                         ,        1,      1,      401,    "R/W",  0,      1,      0ull,   0},
70802         {"OUT1"                        ,        2,      1,      401,    "R/W",  0,      1,      0ull,   0},
70803         {"OUT2"                        ,        3,      1,      401,    "R/W",  0,      1,      0ull,   0},
70804         {"LOOP"                        ,        4,      1,      401,    "R/W",  0,      1,      0ull,   0},
70805         {"AFCE"                        ,        5,      1,      401,    "R/W",  0,      1,      0ull,   0},
70806         {"RESERVED_6_63"               ,        6,      58,     401,    "RAZ",  0,      1,      0ull,   0},
70807         {"DCTS"                        ,        0,      1,      402,    "RC",   0,      1,      0ull,   0},
70808         {"DDSR"                        ,        1,      1,      402,    "RC",   0,      1,      0ull,   0},
70809         {"TERI"                        ,        2,      1,      402,    "RC",   0,      1,      0ull,   0},
70810         {"DDCD"                        ,        3,      1,      402,    "RC",   0,      1,      0ull,   0},
70811         {"CTS"                         ,        4,      1,      402,    "RO",   1,      1,      0,      0},
70812         {"DSR"                         ,        5,      1,      402,    "RO",   0,      1,      0ull,   0},
70813         {"RI"                          ,        6,      1,      402,    "RO",   0,      1,      0ull,   0},
70814         {"DCD"                         ,        7,      1,      402,    "RO",   0,      1,      0ull,   0},
70815         {"RESERVED_8_63"               ,        8,      56,     402,    "RAZ",  1,      1,      0,      0},
70816         {"RBR"                         ,        0,      8,      403,    "RO",   0,      1,      0ull,   0},
70817         {"RESERVED_8_63"               ,        8,      56,     403,    "RAZ",  1,      1,      0,      0},
70818         {"RFL"                         ,        0,      7,      404,    "RO",   0,      1,      0ull,   0},
70819         {"RESERVED_7_63"               ,        7,      57,     404,    "RAZ",  1,      1,      0,      0},
70820         {"RFWD"                        ,        0,      8,      405,    "WO",   0,      1,      0ull,   0},
70821         {"RFPE"                        ,        8,      1,      405,    "WO",   0,      1,      0ull,   0},
70822         {"RFFE"                        ,        9,      1,      405,    "WO",   0,      1,      0ull,   0},
70823         {"RESERVED_10_63"              ,        10,     54,     405,    "RAZ",  1,      1,      0,      0},
70824         {"SBCR"                        ,        0,      1,      406,    "R/W",  0,      1,      0ull,   0},
70825         {"RESERVED_1_63"               ,        1,      63,     406,    "RAZ",  1,      1,      0,      0},
70826         {"SCR"                         ,        0,      8,      407,    "R/W",  0,      1,      0ull,   0},
70827         {"RESERVED_8_63"               ,        8,      56,     407,    "RAZ",  1,      1,      0,      0},
70828         {"SFE"                         ,        0,      1,      408,    "R/W",  0,      1,      0ull,   0},
70829         {"RESERVED_1_63"               ,        1,      63,     408,    "RAZ",  1,      1,      0,      0},
70830         {"USR"                         ,        0,      1,      409,    "WO",   0,      1,      0ull,   0},
70831         {"SRFR"                        ,        1,      1,      409,    "WO",   0,      1,      0ull,   0},
70832         {"STFR"                        ,        2,      1,      409,    "WO",   0,      1,      0ull,   0},
70833         {"RESERVED_3_63"               ,        3,      61,     409,    "RAZ",  1,      1,      0,      0},
70834         {"SRT"                         ,        0,      2,      410,    "R/W",  0,      1,      0ull,   0},
70835         {"RESERVED_2_63"               ,        2,      62,     410,    "RAZ",  1,      1,      0,      0},
70836         {"SRTS"                        ,        0,      1,      411,    "R/W",  0,      1,      0ull,   0},
70837         {"RESERVED_1_63"               ,        1,      63,     411,    "RAZ",  1,      1,      0,      0},
70838         {"STT"                         ,        0,      2,      412,    "R/W",  0,      1,      0ull,   0},
70839         {"RESERVED_2_63"               ,        2,      62,     412,    "RAZ",  1,      1,      0,      0},
70840         {"TFL"                         ,        0,      7,      413,    "RO",   0,      1,      0ull,   0},
70841         {"RESERVED_7_63"               ,        7,      57,     413,    "RAZ",  1,      1,      0,      0},
70842         {"TFR"                         ,        0,      8,      414,    "RO",   0,      1,      0ull,   0},
70843         {"RESERVED_8_63"               ,        8,      56,     414,    "RAZ",  1,      1,      0,      0},
70844         {"THR"                         ,        0,      8,      415,    "WO",   0,      1,      0ull,   0},
70845         {"RESERVED_8_63"               ,        8,      56,     415,    "RAZ",  1,      1,      0,      0},
70846         {"BUSY"                        ,        0,      1,      416,    "RO",   0,      1,      0ull,   0},
70847         {"TFNF"                        ,        1,      1,      416,    "RO",   0,      1,      1ull,   0},
70848         {"TFE"                         ,        2,      1,      416,    "RO",   0,      1,      1ull,   0},
70849         {"RFNE"                        ,        3,      1,      416,    "RO",   0,      1,      0ull,   0},
70850         {"RFF"                         ,        4,      1,      416,    "RO",   0,      1,      0ull,   0},
70851         {"RESERVED_5_63"               ,        5,      59,     416,    "RAZ",  1,      1,      0,      0},
70852         {"ORFDAT"                      ,        0,      1,      417,    "RO",   0,      0,      0ull,   0ull},
70853         {"IRFDAT"                      ,        1,      1,      417,    "RO",   0,      0,      0ull,   0ull},
70854         {"IPFDAT"                      ,        2,      1,      417,    "RO",   0,      0,      0ull,   0ull},
70855         {"MRQDAT"                      ,        3,      1,      417,    "RO",   0,      0,      0ull,   0ull},
70856         {"RESERVED_4_63"               ,        4,      60,     417,    "RAZ",  0,      0,      0ull,   0ull},
70857         {"MRQ_HWM"                     ,        0,      2,      418,    "R/W",  0,      0,      1ull,   1ull},
70858         {"NBTARB"                      ,        2,      1,      418,    "R/W",  0,      0,      0ull,   0ull},
70859         {"LENDIAN"                     ,        3,      1,      418,    "R/W",  0,      0,      0ull,   0ull},
70860         {"RESET"                       ,        4,      1,      418,    "R/W",  0,      0,      1ull,   0ull},
70861         {"EN"                          ,        5,      1,      418,    "R/W",  0,      0,      0ull,   0ull},
70862         {"BUSY"                        ,        6,      1,      418,    "RO",   0,      0,      0ull,   0ull},
70863         {"CRC_STRIP"                   ,        7,      1,      418,    "R/W",  0,      0,      0ull,   0ull},
70864         {"RESERVED_8_63"               ,        8,      56,     418,    "RAZ",  1,      1,      0,      0},
70865         {"OVFENA"                      ,        0,      1,      419,    "R/W",  0,      0,      0ull,   0ull},
70866         {"IVFENA"                      ,        1,      1,      419,    "R/W",  0,      0,      0ull,   0ull},
70867         {"OTHENA"                      ,        2,      1,      419,    "R/W",  0,      0,      0ull,   0ull},
70868         {"ITHENA"                      ,        3,      1,      419,    "R/W",  0,      0,      0ull,   0ull},
70869         {"DATA_DRPENA"                 ,        4,      1,      419,    "R/W",  0,      0,      0ull,   0ull},
70870         {"IRUNENA"                     ,        5,      1,      419,    "R/W",  0,      0,      0ull,   0ull},
70871         {"ORUNENA"                     ,        6,      1,      419,    "R/W",  0,      0,      0ull,   0ull},
70872         {"RESERVED_7_63"               ,        7,      57,     419,    "RAZ",  1,      1,      0,      0},
70873         {"IRCNT"                       ,        0,      20,     420,    "R/W",  0,      0,      0ull,   0ull},
70874         {"RESERVED_20_63"              ,        20,     44,     420,    "RAZ",  1,      1,      0,      0},
70875         {"IRHWM"                       ,        0,      20,     421,    "R/W",  0,      0,      0ull,   0ull},
70876         {"IBPLWM"                      ,        20,     20,     421,    "R/W",  0,      0,      0ull,   0ull},
70877         {"RESERVED_40_63"              ,        40,     24,     421,    "RAZ",  1,      1,      0,      0},
70878         {"RESERVED_0_2"                ,        0,      3,      422,    "RAZ",  1,      1,      0,      0},
70879         {"IBASE"                       ,        3,      33,     422,    "R/W",  0,      1,      0ull,   0},
70880         {"RESERVED_36_39"              ,        36,     4,      422,    "RAZ",  1,      1,      0,      0},
70881         {"ISIZE"                       ,        40,     20,     422,    "R/W",  0,      1,      0ull,   0},
70882         {"RESERVED_60_63"              ,        60,     4,      422,    "RAZ",  1,      1,      0,      0},
70883         {"IDBELL"                      ,        0,      20,     423,    "R/W",  0,      1,      0ull,   0},
70884         {"RESERVED_20_31"              ,        20,     12,     423,    "RAZ",  1,      1,      0,      0},
70885         {"ITLPTR"                      ,        32,     20,     423,    "RO",   0,      1,      0ull,   0},
70886         {"RESERVED_52_63"              ,        52,     12,     423,    "RAZ",  1,      1,      0,      0},
70887         {"ODBLOVF"                     ,        0,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
70888         {"IDBLOVF"                     ,        1,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
70889         {"ORTHRESH"                    ,        2,      1,      424,    "RO",   0,      0,      0ull,   0ull},
70890         {"IRTHRESH"                    ,        3,      1,      424,    "RO",   0,      0,      0ull,   0ull},
70891         {"DATA_DRP"                    ,        4,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
70892         {"IRUN"                        ,        5,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
70893         {"ORUN"                        ,        6,      1,      424,    "R/W1C",        0,      0,      0ull,   0ull},
70894         {"RESERVED_7_63"               ,        7,      57,     424,    "RAZ",  1,      1,      0,      0},
70895         {"ORCNT"                       ,        0,      20,     425,    "R/W",  0,      0,      0ull,   0ull},
70896         {"RESERVED_20_63"              ,        20,     44,     425,    "RAZ",  1,      1,      0,      0},
70897         {"ORHWM"                       ,        0,      20,     426,    "R/W",  0,      0,      0ull,   0ull},
70898         {"RESERVED_20_63"              ,        20,     44,     426,    "RAZ",  1,      1,      0,      0},
70899         {"RESERVED_0_2"                ,        0,      3,      427,    "RAZ",  1,      1,      0,      0},
70900         {"OBASE"                       ,        3,      33,     427,    "R/W",  0,      1,      0ull,   0},
70901         {"RESERVED_36_39"              ,        36,     4,      427,    "RAZ",  1,      1,      0,      0},
70902         {"OSIZE"                       ,        40,     20,     427,    "R/W",  0,      1,      0ull,   0},
70903         {"RESERVED_60_63"              ,        60,     4,      427,    "RAZ",  1,      1,      0,      0},
70904         {"ODBELL"                      ,        0,      20,     428,    "R/W",  0,      1,      0ull,   0},
70905         {"RESERVED_20_31"              ,        20,     12,     428,    "RAZ",  1,      1,      0,      0},
70906         {"OTLPTR"                      ,        32,     20,     428,    "RO",   0,      1,      0ull,   0},
70907         {"RESERVED_52_63"              ,        52,     12,     428,    "RAZ",  1,      1,      0,      0},
70908         {"OREMCNT"                     ,        0,      20,     429,    "RO",   0,      0,      0ull,   0ull},
70909         {"RESERVED_20_31"              ,        20,     12,     429,    "RAZ",  1,      1,      0,      0},
70910         {"IREMCNT"                     ,        32,     20,     429,    "RO",   0,      0,      0ull,   0ull},
70911         {"RESERVED_52_63"              ,        52,     12,     429,    "RAZ",  1,      1,      0,      0},
70912         {"SIZE"                        ,        0,      3,      430,    "R/W",  0,      1,      0ull,   0},
70913         {"ADR_CYC"                     ,        3,      4,      430,    "R/W",  0,      1,      8ull,   0},
70914         {"T_MULT"                      ,        7,      4,      430,    "R/W",  0,      1,      9ull,   0},
70915         {"RESERVED_11_63"              ,        11,     53,     430,    "RAZ",  1,      1,      0,      0},
70916         {"NF_CMD"                      ,        0,      64,     431,    "R/W",  0,      1,      0ull,   0},
70917         {"CNT"                         ,        0,      8,      432,    "R/W",  0,      1,      0ull,   0},
70918         {"RESERVED_8_63"               ,        8,      56,     432,    "RAZ",  1,      1,      0,      0},
70919         {"ECC_ERR"                     ,        0,      8,      433,    "RO",   0,      1,      0ull,   0},
70920         {"XOR_ECC"                     ,        8,      24,     433,    "RO",   0,      1,      0ull,   0},
70921         {"RESERVED_32_63"              ,        32,     32,     433,    "RAZ",  1,      1,      0,      0},
70922         {"EMPTY"                       ,        0,      1,      434,    "R/W1C",        0,      1,      0ull,   0},
70923         {"FULL"                        ,        1,      1,      434,    "R/W1C",        0,      1,      0ull,   0},
70924         {"WDOG"                        ,        2,      1,      434,    "R/W1C",        0,      1,      0ull,   0},
70925         {"SM_BAD"                      ,        3,      1,      434,    "R/W1C",        0,      1,      0ull,   0},
70926         {"ECC_1BIT"                    ,        4,      1,      434,    "R/W1C",        0,      1,      0ull,   0},
70927         {"ECC_MULT"                    ,        5,      1,      434,    "R/W1C",        0,      1,      0ull,   0},
70928         {"OVRF"                        ,        6,      1,      434,    "R/W1C",        0,      1,      0ull,   0},
70929         {"RESERVED_7_63"               ,        7,      57,     434,    "RAZ",  1,      1,      0,      0},
70930         {"EMPTY"                       ,        0,      1,      435,    "R/W",  0,      1,      0ull,   0},
70931         {"FULL"                        ,        1,      1,      435,    "R/W",  0,      1,      0ull,   0},
70932         {"WDOG"                        ,        2,      1,      435,    "R/W",  0,      1,      0ull,   0},
70933         {"SM_BAD"                      ,        3,      1,      435,    "R/W",  0,      1,      0ull,   0},
70934         {"ECC_1BIT"                    ,        4,      1,      435,    "R/W",  0,      1,      0ull,   0},
70935         {"ECC_MULT"                    ,        5,      1,      435,    "R/W",  0,      1,      0ull,   0},
70936         {"OVRF"                        ,        6,      1,      435,    "R/W",  0,      1,      0ull,   0},
70937         {"RESERVED_7_63"               ,        7,      57,     435,    "RAZ",  1,      1,      0,      0},
70938         {"RST_FF"                      ,        0,      1,      436,    "R/W",  0,      0,      0ull,   0ull},
70939         {"EX_DIS"                      ,        1,      1,      436,    "R/W",  0,      0,      0ull,   0ull},
70940         {"BT_DIS"                      ,        2,      1,      436,    "R/W",  0,      0,      0ull,   1ull},
70941         {"BT_DMA"                      ,        3,      1,      436,    "R/W",  0,      1,      0ull,   0},
70942         {"RD_CMD"                      ,        4,      1,      436,    "R/W",  0,      0,      0ull,   0ull},
70943         {"RD_VAL"                      ,        5,      1,      436,    "RO",   0,      1,      0ull,   0},
70944         {"RD_DONE"                     ,        6,      1,      436,    "R/W1C",        0,      0,      0ull,   0ull},
70945         {"FR_BYT"                      ,        7,      11,     436,    "RO",   0,      1,      0ull,   0},
70946         {"WAIT_CNT"                    ,        18,     6,      436,    "R/W",  0,      1,      20ull,  0},
70947         {"NBR_HWM"                     ,        24,     3,      436,    "R/W",  0,      0,      3ull,   3ull},
70948         {"RESERVED_27_63"              ,        27,     37,     436,    "RAZ",  1,      1,      0,      0},
70949         {"MAIN_SM"                     ,        0,      3,      437,    "RO",   0,      1,      0ull,   0},
70950         {"MAIN_BAD"                    ,        3,      1,      437,    "RO",   0,      1,      0ull,   0},
70951         {"RD_FF"                       ,        4,      2,      437,    "RO",   0,      1,      0ull,   0},
70952         {"RD_FF_BAD"                   ,        6,      1,      437,    "RO",   0,      1,      0ull,   0},
70953         {"BT_SM"                       ,        7,      4,      437,    "RO",   0,      1,      0ull,   0},
70954         {"EXE_SM"                      ,        11,     4,      437,    "RO",   0,      1,      0ull,   0},
70955         {"EXE_IDLE"                    ,        15,     1,      437,    "RO",   0,      1,      1ull,   0},
70956         {"RESERVED_16_63"              ,        16,     48,     437,    "RAZ",  1,      1,      0,      0},
70957         {"ADDR_V"                      ,        0,      1,      438,    "R/W",  0,      1,      0ull,   0},
70958         {"END_SWP"                     ,        1,      2,      438,    "R/W",  0,      1,      0ull,   0},
70959         {"CA"                          ,        3,      1,      438,    "R/W",  0,      0,      0ull,   0ull},
70960         {"ADDR_IDX"                    ,        4,      14,     438,    "R/W",  0,      1,      0ull,   0},
70961         {"RESERVED_18_31"              ,        18,     14,     438,    "RAZ",  1,      1,      0,      0},
70962         {"NCB_CMD"                     ,        0,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70963         {"MSI"                         ,        1,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70964         {"DIF4"                        ,        2,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70965         {"DIF3"                        ,        3,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70966         {"DIF2"                        ,        4,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70967         {"DIF1"                        ,        5,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70968         {"DIF0"                        ,        6,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70969         {"CSM1"                        ,        7,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70970         {"CSM0"                        ,        8,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70971         {"P2N1_P1"                     ,        9,      1,      439,    "RO",   0,      0,      0ull,   0ull},
70972         {"P2N1_P0"                     ,        10,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70973         {"P2N1_N"                      ,        11,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70974         {"P2N1_C1"                     ,        12,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70975         {"P2N1_C0"                     ,        13,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70976         {"P2N0_P1"                     ,        14,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70977         {"P2N0_P0"                     ,        15,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70978         {"P2N0_N"                      ,        16,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70979         {"P2N0_C1"                     ,        17,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70980         {"P2N0_C0"                     ,        18,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70981         {"P2N0_CO"                     ,        19,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70982         {"P2N0_NO"                     ,        20,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70983         {"P2N0_PO"                     ,        21,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70984         {"P2N1_CO"                     ,        22,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70985         {"P2N1_NO"                     ,        23,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70986         {"P2N1_PO"                     ,        24,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70987         {"CPL_P1"                      ,        25,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70988         {"CPL_P0"                      ,        26,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70989         {"N2P1_O"                      ,        27,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70990         {"N2P1_C"                      ,        28,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70991         {"N2P0_O"                      ,        29,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70992         {"N2P0_C"                      ,        30,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70993         {"D4_PST"                      ,        31,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70994         {"D3_PST"                      ,        32,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70995         {"D2_PST"                      ,        33,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70996         {"D1_PST"                      ,        34,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70997         {"D0_PST"                      ,        35,     1,      439,    "RO",   0,      0,      0ull,   0ull},
70998         {"RESERVED_36_39"              ,        36,     4,      439,    "RAZ",  1,      1,      0,      0},
70999         {"DS_MEM"                      ,        40,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71000         {"D4_MEM"                      ,        41,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71001         {"D3_MEM"                      ,        42,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71002         {"D2_MEM"                      ,        43,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71003         {"D1_MEM"                      ,        44,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71004         {"D0_MEM"                      ,        45,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71005         {"PKT_POP1"                    ,        46,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71006         {"PKT_POP0"                    ,        47,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71007         {"RESERVED_48_49"              ,        48,     2,      439,    "RAZ",  1,      1,      0,      0},
71008         {"PKT_POF"                     ,        50,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71009         {"PKT_PFM"                     ,        51,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71010         {"PKT_IMEM"                    ,        52,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71011         {"PCSR_SL"                     ,        53,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71012         {"PCSR_ID"                     ,        54,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71013         {"PCSR_CNT"                    ,        55,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71014         {"PCSR_IM"                     ,        56,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71015         {"PCSR_INT"                    ,        57,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71016         {"PKT_PIF"                     ,        58,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71017         {"PCR_GIM"                     ,        59,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71018         {"RESERVED_60_62"              ,        60,     3,      439,    "RAZ",  1,      1,      0,      0},
71019         {"PKT_RDF"                     ,        63,     1,      439,    "RO",   0,      0,      0ull,   0ull},
71020         {"PKT_BLK"                     ,        0,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71021         {"PKT_GL"                      ,        1,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71022         {"PKT_GD"                      ,        2,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71023         {"PSC_P1"                      ,        3,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71024         {"PSC_P0"                      ,        4,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71025         {"PKT_RD"                      ,        5,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71026         {"NWE_WR1"                     ,        6,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71027         {"NWE_WR0"                     ,        7,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71028         {"NWE_ST"                      ,        8,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71029         {"NRD_ST"                      ,        9,      1,      440,    "RO",   0,      0,      0ull,   0ull},
71030         {"PRD_ERR"                     ,        10,     1,      440,    "RO",   0,      0,      0ull,   0ull},
71031         {"PRD_ST1"                     ,        11,     1,      440,    "RO",   0,      0,      0ull,   0ull},
71032         {"PRD_ST0"                     ,        12,     1,      440,    "RO",   0,      0,      0ull,   0ull},
71033         {"PRD_TAG"                     ,        13,     1,      440,    "RO",   0,      0,      0ull,   0ull},
71034         {"RESERVED_14_63"              ,        14,     50,     440,    "RAZ",  1,      1,      0,      0},
71035         {"WAIT_COM"                    ,        0,      1,      441,    "R/W",  0,      0,      0ull,   0ull},
71036         {"BAR2_CAX"                    ,        1,      1,      441,    "R/W",  0,      0,      0ull,   0ull},
71037         {"BAR2_ESX"                    ,        2,      2,      441,    "R/W",  0,      1,      0ull,   0},
71038         {"BAR2_ENB"                    ,        4,      1,      441,    "R/W",  0,      0,      0ull,   1ull},
71039         {"PTLP_RO"                     ,        5,      1,      441,    "R/W",  0,      0,      0ull,   1ull},
71040         {"RESERVED_6_6"                ,        6,      1,      441,    "RAZ",  0,      0,      0ull,   0ull},
71041         {"CTLP_RO"                     ,        7,      1,      441,    "R/W",  0,      0,      0ull,   1ull},
71042         {"INTA_MAP"                    ,        8,      2,      441,    "R/W",  0,      0,      0ull,   0ull},
71043         {"INTB_MAP"                    ,        10,     2,      441,    "R/W",  0,      0,      1ull,   1ull},
71044         {"INTC_MAP"                    ,        12,     2,      441,    "R/W",  0,      0,      2ull,   2ull},
71045         {"INTD_MAP"                    ,        14,     2,      441,    "R/W",  0,      0,      3ull,   3ull},
71046         {"INTA"                        ,        16,     1,      441,    "RO",   0,      0,      1ull,   1ull},
71047         {"INTB"                        ,        17,     1,      441,    "RO",   0,      0,      1ull,   1ull},
71048         {"INTC"                        ,        18,     1,      441,    "RO",   0,      0,      1ull,   1ull},
71049         {"INTD"                        ,        19,     1,      441,    "RO",   0,      0,      1ull,   1ull},
71050         {"WAITL_COM"                   ,        20,     1,      441,    "R/W",  0,      1,      0ull,   0},
71051         {"RESERVED_21_63"              ,        21,     43,     441,    "RAZ",  1,      1,      0,      0},
71052         {"WAIT_COM"                    ,        0,      1,      442,    "R/W",  0,      0,      0ull,   0ull},
71053         {"BAR2_CAX"                    ,        1,      1,      442,    "R/W",  0,      0,      0ull,   0ull},
71054         {"BAR2_ESX"                    ,        2,      2,      442,    "R/W",  0,      1,      0ull,   0},
71055         {"BAR2_ENB"                    ,        4,      1,      442,    "R/W",  0,      0,      0ull,   1ull},
71056         {"PTLP_RO"                     ,        5,      1,      442,    "R/W",  0,      0,      0ull,   1ull},
71057         {"RESERVED_6_6"                ,        6,      1,      442,    "RAZ",  0,      0,      0ull,   0ull},
71058         {"CTLP_RO"                     ,        7,      1,      442,    "R/W",  0,      0,      0ull,   1ull},
71059         {"INTA_MAP"                    ,        8,      2,      442,    "R/W",  0,      0,      0ull,   0ull},
71060         {"INTB_MAP"                    ,        10,     2,      442,    "R/W",  0,      0,      1ull,   1ull},
71061         {"INTC_MAP"                    ,        12,     2,      442,    "R/W",  0,      0,      2ull,   2ull},
71062         {"INTD_MAP"                    ,        14,     2,      442,    "R/W",  0,      0,      3ull,   3ull},
71063         {"INTA"                        ,        16,     1,      442,    "RO",   0,      0,      1ull,   1ull},
71064         {"INTB"                        ,        17,     1,      442,    "RO",   0,      0,      1ull,   1ull},
71065         {"INTC"                        ,        18,     1,      442,    "RO",   0,      0,      1ull,   1ull},
71066         {"INTD"                        ,        19,     1,      442,    "RO",   0,      0,      1ull,   1ull},
71067         {"WAITL_COM"                   ,        20,     1,      442,    "R/W",  0,      1,      0ull,   0},
71068         {"RESERVED_21_63"              ,        21,     43,     442,    "RAZ",  1,      1,      0,      0},
71069         {"CHIP_REV"                    ,        0,      8,      443,    "RO",   1,      1,      0,      0},
71070         {"HOST_MODE"                   ,        8,      1,      443,    "RO",   1,      1,      0,      0},
71071         {"PKT_BP"                      ,        9,      4,      443,    "R/W",  0,      0,      15ull,  15ull},
71072         {"ARB"                         ,        13,     1,      443,    "R/W",  0,      0,      0ull,   1ull},
71073         {"LNK_RST"                     ,        14,     1,      443,    "R/W1C",        0,      0,      0ull,   0ull},
71074         {"RING_EN"                     ,        15,     1,      443,    "R/W",  0,      0,      0ull,   0ull},
71075         {"CFG_RTRY"                    ,        16,     16,     443,    "R/W",  0,      0,      0ull,   32ull},
71076         {"P0_NTAGS"                    ,        32,     6,      443,    "R/W",  0,      0,      32ull,  32ull},
71077         {"P1_NTAGS"                    ,        38,     6,      443,    "R/W",  0,      0,      32ull,  32ull},
71078         {"RESERVED_44_63"              ,        44,     20,     443,    "RAZ",  1,      1,      0,      0},
71079         {"C0_B0_D"                     ,        0,      1,      444,    "R/W",  0,      0,      0ull,   0ull},
71080         {"C0_WI_D"                     ,        1,      1,      444,    "R/W",  0,      0,      0ull,   0ull},
71081         {"C1_B0_D"                     ,        2,      1,      444,    "R/W",  0,      0,      0ull,   0ull},
71082         {"C1_WI_D"                     ,        3,      1,      444,    "R/W",  0,      0,      0ull,   0ull},
71083         {"C0_B1_S"                     ,        4,      3,      444,    "R/W",  0,      0,      1ull,   1ull},
71084         {"C1_B1_S"                     ,        7,      3,      444,    "R/W",  0,      0,      1ull,   1ull},
71085         {"C0_W_FLT"                    ,        10,     1,      444,    "R/W",  0,      0,      0ull,   0ull},
71086         {"C1_W_FLT"                    ,        11,     1,      444,    "R/W",  0,      0,      0ull,   0ull},
71087         {"MRRS"                        ,        12,     3,      444,    "R/W",  0,      0,      2ull,   2ull},
71088         {"MPS"                         ,        15,     1,      444,    "R/W",  0,      0,      0ull,   0ull},
71089         {"RESERVED_16_63"              ,        16,     48,     444,    "RAZ",  1,      1,      0,      0},
71090         {"P0_FCNT"                     ,        0,      6,      445,    "RO",   0,      1,      0ull,   0},
71091         {"P0_UCNT"                     ,        6,      16,     445,    "RO",   0,      1,      0ull,   0},
71092         {"P1_FCNT"                     ,        22,     6,      445,    "RO",   0,      1,      0ull,   0},
71093         {"P1_UCNT"                     ,        28,     16,     445,    "RO",   0,      1,      0ull,   0},
71094         {"RESERVED_44_63"              ,        44,     20,     445,    "RAZ",  1,      1,      0,      0},
71095         {"DATA"                        ,        0,      17,     446,    "RO",   0,      1,      0ull,   0},
71096         {"DSEL_EXT"                    ,        17,     1,      446,    "R/W",  0,      0,      1ull,   0ull},
71097         {"C_MUL"                       ,        18,     5,      446,    "RO",   1,      1,      0,      0},
71098         {"QLM1_SPD"                    ,        23,     2,      446,    "RO",   1,      1,      0,      0},
71099         {"QLM1_MODE"                   ,        25,     2,      446,    "RO",   1,      1,      0,      0},
71100         {"QLM0_REV_LANES"              ,        27,     1,      446,    "RO",   1,      1,      0,      0},
71101         {"QLM0_LINK_WIDTH"             ,        28,     1,      446,    "RO",   1,      1,      0,      0},
71102         {"RESERVED_29_63"              ,        29,     35,     446,    "RAZ",  1,      1,      0,      0},
71103         {"DBG_SEL"                     ,        0,      16,     447,    "R/W",  0,      1,      0ull,   0},
71104         {"RESERVED_16_63"              ,        16,     48,     447,    "RAZ",  1,      1,      0,      0},
71105         {"DBELL"                       ,        0,      32,     448,    "RO",   0,      0,      0ull,   0ull},
71106         {"FCNT"                        ,        32,     7,      448,    "RO",   0,      0,      0ull,   0ull},
71107         {"RESERVED_39_63"              ,        39,     25,     448,    "RAZ",  1,      1,      0,      0},
71108         {"DBELL"                       ,        0,      16,     449,    "R/W",  0,      1,      0ull,   0},
71109         {"RESERVED_16_31"              ,        16,     16,     449,    "RAZ",  1,      1,      0,      0},
71110         {"RESERVED_0_6"                ,        0,      7,      450,    "RAZ",  1,      1,      0,      0},
71111         {"SADDR"                       ,        7,      29,     450,    "R/W",  0,      1,      0ull,   0},
71112         {"IDLE"                        ,        36,     1,      450,    "RO",   0,      1,      1ull,   0},
71113         {"RESERVED_37_63"              ,        37,     27,     450,    "RAZ",  1,      1,      0,      0},
71114         {"ADDR"                        ,        0,      36,     451,    "RO",   0,      1,      0ull,   0},
71115         {"RESERVED_36_63"              ,        36,     28,     451,    "RAZ",  1,      1,      0,      0},
71116         {"CNT"                         ,        0,      32,     452,    "R/W",  0,      1,      0ull,   0},
71117         {"TIME"                        ,        32,     32,     452,    "R/W",  0,      1,      0ull,   0},
71118         {"CNT"                         ,        0,      32,     453,    "R/W",  0,      1,      0ull,   0},
71119         {"TIME"                        ,        32,     32,     453,    "R/W",  0,      1,      0ull,   0},
71120         {"DMA0"                        ,        0,      32,     454,    "R/W",  0,      1,      0ull,   0},
71121         {"DMA1"                        ,        32,     32,     454,    "R/W",  0,      1,      0ull,   0},
71122         {"CSIZE"                       ,        0,      14,     455,    "R/W",  0,      1,      0ull,   0},
71123         {"O_MODE"                      ,        14,     1,      455,    "R/W",  0,      0,      0ull,   1ull},
71124         {"O_ES"                        ,        15,     2,      455,    "R/W",  0,      1,      0ull,   0},
71125         {"O_NS"                        ,        17,     1,      455,    "R/W",  0,      1,      0ull,   0},
71126         {"O_RO"                        ,        18,     1,      455,    "R/W",  0,      1,      0ull,   0},
71127         {"O_ADD1"                      ,        19,     1,      455,    "R/W",  0,      0,      0ull,   1ull},
71128         {"FPA_QUE"                     ,        20,     3,      455,    "R/W",  0,      1,      0ull,   0},
71129         {"DWB_ICHK"                    ,        23,     9,      455,    "R/W",  0,      1,      0ull,   0},
71130         {"DWB_DENB"                    ,        32,     1,      455,    "R/W",  0,      0,      0ull,   1ull},
71131         {"B0_LEND"                     ,        33,     1,      455,    "R/W",  0,      0,      0ull,   0ull},
71132         {"DMA0_ENB"                    ,        34,     1,      455,    "R/W",  0,      0,      0ull,   1ull},
71133         {"DMA1_ENB"                    ,        35,     1,      455,    "R/W",  0,      0,      0ull,   1ull},
71134         {"DMA2_ENB"                    ,        36,     1,      455,    "R/W",  0,      0,      0ull,   1ull},
71135         {"DMA3_ENB"                    ,        37,     1,      455,    "R/W",  0,      0,      0ull,   1ull},
71136         {"DMA4_ENB"                    ,        38,     1,      455,    "R/W",  0,      0,      0ull,   1ull},
71137         {"P_32B_M"                     ,        39,     1,      455,    "R/W",  0,      0,      0ull,   0ull},
71138         {"RESERVED_40_63"              ,        40,     24,     455,    "RAZ",  1,      1,      0,      0},
71139         {"DMA_CNT"                     ,        0,      5,      456,    "R/W",  0,      1,      16ull,  0},
71140         {"RESERVED_5_7"                ,        5,      3,      456,    "RAZ",  1,      1,      0,      0},
71141         {"DMA0_CNT"                    ,        8,      5,      456,    "R/W",  0,      1,      16ull,  0},
71142         {"RESERVED_13_15"              ,        13,     3,      456,    "RAZ",  1,      1,      0,      0},
71143         {"DMA1_CNT"                    ,        16,     5,      456,    "R/W",  0,      1,      16ull,  0},
71144         {"RESERVED_21_23"              ,        21,     3,      456,    "RAZ",  1,      1,      0,      0},
71145         {"DMA2_CNT"                    ,        24,     5,      456,    "R/W",  0,      1,      16ull,  0},
71146         {"RESERVED_29_31"              ,        29,     3,      456,    "RAZ",  1,      1,      0,      0},
71147         {"DMA3_CNT"                    ,        32,     5,      456,    "R/W",  0,      1,      16ull,  0},
71148         {"RESERVED_37_39"              ,        37,     3,      456,    "RAZ",  1,      1,      0,      0},
71149         {"DMA4_CNT"                    ,        40,     5,      456,    "R/W",  0,      1,      16ull,  0},
71150         {"RESERVED_45_47"              ,        45,     3,      456,    "RAZ",  1,      1,      0,      0},
71151         {"PKT_CNT"                     ,        48,     5,      456,    "R/W",  0,      1,      16ull,  0},
71152         {"RESERVED_53_62"              ,        53,     10,     456,    "RAZ",  1,      1,      0,      0},
71153         {"DMA_ARB"                     ,        63,     1,      456,    "R/W",  0,      1,      1ull,   0},
71154         {"D0_DWE"                      ,        0,      8,      457,    "RO",   0,      1,      1ull,   0},
71155         {"D1_DWE"                      ,        8,      8,      457,    "RO",   0,      1,      1ull,   0},
71156         {"D2_DWE"                      ,        16,     8,      457,    "RO",   0,      1,      1ull,   0},
71157         {"D3_DWE"                      ,        24,     8,      457,    "RO",   0,      1,      1ull,   0},
71158         {"D4_DWE"                      ,        32,     8,      457,    "RO",   0,      1,      1ull,   0},
71159         {"RESERVED_40_63"              ,        40,     24,     457,    "RAZ",  1,      1,      0,      0},
71160         {"PRD"                         ,        0,      10,     458,    "RO",   0,      1,      1ull,   0},
71161         {"RESERVED_10_15"              ,        10,     6,      458,    "RAZ",  1,      1,      0,      0},
71162         {"NDRE"                        ,        16,     5,      458,    "RO",   0,      1,      1ull,   0},
71163         {"RESERVED_21_23"              ,        21,     3,      458,    "RAZ",  1,      1,      0,      0},
71164         {"NDWE"                        ,        24,     4,      458,    "RO",   0,      1,      1ull,   0},
71165         {"RESERVED_28_63"              ,        28,     36,     458,    "RAZ",  1,      1,      0,      0},
71166         {"DMA0_CPL"                    ,        0,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71167         {"DMA1_CPL"                    ,        1,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71168         {"PINS_ERR"                    ,        2,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71169         {"POP_ERR"                     ,        3,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71170         {"PDI_ERR"                     ,        4,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71171         {"PGL_ERR"                     ,        5,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71172         {"P0_RDLK"                     ,        6,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71173         {"P1_RDLK"                     ,        7,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71174         {"PIN_BP"                      ,        8,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71175         {"POUT_ERR"                    ,        9,      1,      459,    "R/W",  0,      0,      0ull,   1ull},
71176         {"RESERVED_10_63"              ,        10,     54,     459,    "RAZ",  0,      1,      0ull,   0},
71177         {"DMA0_CPL"                    ,        0,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71178         {"DMA1_CPL"                    ,        1,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71179         {"PINS_ERR"                    ,        2,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71180         {"POP_ERR"                     ,        3,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71181         {"PDI_ERR"                     ,        4,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71182         {"PGL_ERR"                     ,        5,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71183         {"P0_RDLK"                     ,        6,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71184         {"P1_RDLK"                     ,        7,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71185         {"PIN_BP"                      ,        8,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71186         {"POUT_ERR"                    ,        9,      1,      460,    "R/W",  0,      0,      0ull,   1ull},
71187         {"RESERVED_10_63"              ,        10,     54,     460,    "RAZ",  0,      1,      0ull,   0},
71188         {"DMA0_CPL"                    ,        0,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71189         {"DMA1_CPL"                    ,        1,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71190         {"PINS_ERR"                    ,        2,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71191         {"POP_ERR"                     ,        3,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71192         {"PDI_ERR"                     ,        4,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71193         {"PGL_ERR"                     ,        5,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71194         {"P0_RDLK"                     ,        6,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71195         {"P1_RDLK"                     ,        7,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71196         {"PIN_BP"                      ,        8,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71197         {"POUT_ERR"                    ,        9,      1,      461,    "R/W1C",        0,      0,      0ull,   0ull},
71198         {"RESERVED_10_63"              ,        10,     54,     461,    "RAZ",  0,      0,      0ull,   0ull},
71199         {"RML_RTO"                     ,        0,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71200         {"RML_WTO"                     ,        1,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71201         {"BAR0_TO"                     ,        2,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71202         {"IOB2BIG"                     ,        3,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71203         {"DMA0DBO"                     ,        4,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71204         {"DMA1DBO"                     ,        5,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71205         {"DMA2DBO"                     ,        6,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71206         {"DMA3DBO"                     ,        7,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71207         {"DMA4DBO"                     ,        8,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71208         {"DMA0FI"                      ,        9,      1,      462,    "R/W",  0,      0,      0ull,   1ull},
71209         {"DMA1FI"                      ,        10,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71210         {"DCNT0"                       ,        11,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71211         {"DCNT1"                       ,        12,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71212         {"DTIME0"                      ,        13,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71213         {"DTIME1"                      ,        14,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71214         {"PSLDBOF"                     ,        15,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71215         {"PIDBOF"                      ,        16,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71216         {"PCNT"                        ,        17,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71217         {"PTIME"                       ,        18,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71218         {"C0_AERI"                     ,        19,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71219         {"CRS0_ER"                     ,        20,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71220         {"C0_SE"                       ,        21,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71221         {"CRS0_DR"                     ,        22,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71222         {"C0_WAKE"                     ,        23,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71223         {"C0_PMEI"                     ,        24,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71224         {"C0_HPINT"                    ,        25,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71225         {"C1_AERI"                     ,        26,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71226         {"CRS1_ER"                     ,        27,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71227         {"C1_SE"                       ,        28,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71228         {"CRS1_DR"                     ,        29,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71229         {"C1_WAKE"                     ,        30,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71230         {"C1_PMEI"                     ,        31,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71231         {"C1_HPINT"                    ,        32,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71232         {"C0_UP_B0"                    ,        33,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71233         {"C0_UP_B1"                    ,        34,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71234         {"C0_UP_B2"                    ,        35,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71235         {"C0_UP_WI"                    ,        36,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71236         {"C0_UP_BX"                    ,        37,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71237         {"C0_UN_B0"                    ,        38,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71238         {"C0_UN_B1"                    ,        39,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71239         {"C0_UN_B2"                    ,        40,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71240         {"C0_UN_WI"                    ,        41,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71241         {"C0_UN_BX"                    ,        42,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71242         {"C1_UP_B0"                    ,        43,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71243         {"C1_UP_B1"                    ,        44,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71244         {"C1_UP_B2"                    ,        45,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71245         {"C1_UP_WI"                    ,        46,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71246         {"C1_UP_BX"                    ,        47,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71247         {"C1_UN_B0"                    ,        48,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71248         {"C1_UN_B1"                    ,        49,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71249         {"C1_UN_B2"                    ,        50,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71250         {"C1_UN_WI"                    ,        51,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71251         {"C1_UN_BX"                    ,        52,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71252         {"C0_UN_WF"                    ,        53,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71253         {"C1_UN_WF"                    ,        54,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71254         {"C0_UP_WF"                    ,        55,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71255         {"C1_UP_WF"                    ,        56,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71256         {"C0_EXC"                      ,        57,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71257         {"C1_EXC"                      ,        58,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71258         {"C0_LDWN"                     ,        59,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71259         {"C1_LDWN"                     ,        60,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71260         {"INT_A"                       ,        61,     1,      462,    "RO",   0,      0,      1ull,   1ull},
71261         {"RESERVED_62_62"              ,        62,     1,      462,    "RAZ",  0,      1,      0ull,   0},
71262         {"MIO_INTA"                    ,        63,     1,      462,    "R/W",  0,      0,      0ull,   1ull},
71263         {"RML_RTO"                     ,        0,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71264         {"RML_WTO"                     ,        1,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71265         {"BAR0_TO"                     ,        2,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71266         {"IOB2BIG"                     ,        3,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71267         {"DMA0DBO"                     ,        4,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71268         {"DMA1DBO"                     ,        5,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71269         {"DMA2DBO"                     ,        6,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71270         {"DMA3DBO"                     ,        7,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71271         {"DMA4DBO"                     ,        8,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71272         {"DMA0FI"                      ,        9,      1,      463,    "R/W",  0,      0,      0ull,   1ull},
71273         {"DMA1FI"                      ,        10,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71274         {"DCNT0"                       ,        11,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71275         {"DCNT1"                       ,        12,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71276         {"DTIME0"                      ,        13,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71277         {"DTIME1"                      ,        14,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71278         {"PSLDBOF"                     ,        15,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71279         {"PIDBOF"                      ,        16,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71280         {"PCNT"                        ,        17,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71281         {"PTIME"                       ,        18,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71282         {"C0_AERI"                     ,        19,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71283         {"CRS0_ER"                     ,        20,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71284         {"C0_SE"                       ,        21,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71285         {"CRS0_DR"                     ,        22,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71286         {"C0_WAKE"                     ,        23,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71287         {"C0_PMEI"                     ,        24,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71288         {"C0_HPINT"                    ,        25,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71289         {"C1_AERI"                     ,        26,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71290         {"CRS1_ER"                     ,        27,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71291         {"C1_SE"                       ,        28,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71292         {"CRS1_DR"                     ,        29,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71293         {"C1_WAKE"                     ,        30,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71294         {"C1_PMEI"                     ,        31,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71295         {"C1_HPINT"                    ,        32,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71296         {"C0_UP_B0"                    ,        33,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71297         {"C0_UP_B1"                    ,        34,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71298         {"C0_UP_B2"                    ,        35,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71299         {"C0_UP_WI"                    ,        36,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71300         {"C0_UP_BX"                    ,        37,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71301         {"C0_UN_B0"                    ,        38,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71302         {"C0_UN_B1"                    ,        39,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71303         {"C0_UN_B2"                    ,        40,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71304         {"C0_UN_WI"                    ,        41,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71305         {"C0_UN_BX"                    ,        42,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71306         {"C1_UP_B0"                    ,        43,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71307         {"C1_UP_B1"                    ,        44,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71308         {"C1_UP_B2"                    ,        45,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71309         {"C1_UP_WI"                    ,        46,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71310         {"C1_UP_BX"                    ,        47,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71311         {"C1_UN_B0"                    ,        48,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71312         {"C1_UN_B1"                    ,        49,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71313         {"C1_UN_B2"                    ,        50,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71314         {"C1_UN_WI"                    ,        51,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71315         {"C1_UN_BX"                    ,        52,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71316         {"C0_UN_WF"                    ,        53,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71317         {"C1_UN_WF"                    ,        54,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71318         {"C0_UP_WF"                    ,        55,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71319         {"C1_UP_WF"                    ,        56,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71320         {"C0_EXC"                      ,        57,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71321         {"C1_EXC"                      ,        58,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71322         {"C0_LDWN"                     ,        59,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71323         {"C1_LDWN"                     ,        60,     1,      463,    "R/W",  0,      0,      0ull,   1ull},
71324         {"INT_A"                       ,        61,     1,      463,    "RO",   0,      0,      1ull,   1ull},
71325         {"RESERVED_62_63"              ,        62,     2,      463,    "RAZ",  0,      1,      0ull,   0},
71326         {"PSLDBOF"                     ,        0,      6,      464,    "RO",   0,      1,      0ull,   0},
71327         {"PIDBOF"                      ,        6,      6,      464,    "RO",   0,      1,      0ull,   0},
71328         {"RESERVED_12_63"              ,        12,     52,     464,    "RAZ",  1,      1,      0,      0},
71329         {"RML_RTO"                     ,        0,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71330         {"RML_WTO"                     ,        1,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71331         {"BAR0_TO"                     ,        2,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71332         {"IOB2BIG"                     ,        3,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71333         {"DMA0DBO"                     ,        4,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71334         {"DMA1DBO"                     ,        5,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71335         {"DMA2DBO"                     ,        6,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71336         {"DMA3DBO"                     ,        7,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71337         {"DMA4DBO"                     ,        8,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71338         {"DMA0FI"                      ,        9,      1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71339         {"DMA1FI"                      ,        10,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71340         {"DCNT0"                       ,        11,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71341         {"DCNT1"                       ,        12,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71342         {"DTIME0"                      ,        13,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71343         {"DTIME1"                      ,        14,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71344         {"PSLDBOF"                     ,        15,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71345         {"PIDBOF"                      ,        16,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71346         {"PCNT"                        ,        17,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71347         {"PTIME"                       ,        18,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71348         {"C0_AERI"                     ,        19,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71349         {"CRS0_ER"                     ,        20,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71350         {"C0_SE"                       ,        21,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71351         {"CRS0_DR"                     ,        22,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71352         {"C0_WAKE"                     ,        23,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71353         {"C0_PMEI"                     ,        24,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71354         {"C0_HPINT"                    ,        25,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71355         {"C1_AERI"                     ,        26,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71356         {"CRS1_ER"                     ,        27,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71357         {"C1_SE"                       ,        28,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71358         {"CRS1_DR"                     ,        29,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71359         {"C1_WAKE"                     ,        30,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71360         {"C1_PMEI"                     ,        31,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71361         {"C1_HPINT"                    ,        32,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71362         {"C0_UP_B0"                    ,        33,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71363         {"C0_UP_B1"                    ,        34,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71364         {"C0_UP_B2"                    ,        35,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71365         {"C0_UP_WI"                    ,        36,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71366         {"C0_UP_BX"                    ,        37,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71367         {"C0_UN_B0"                    ,        38,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71368         {"C0_UN_B1"                    ,        39,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71369         {"C0_UN_B2"                    ,        40,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71370         {"C0_UN_WI"                    ,        41,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71371         {"C0_UN_BX"                    ,        42,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71372         {"C1_UP_B0"                    ,        43,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71373         {"C1_UP_B1"                    ,        44,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71374         {"C1_UP_B2"                    ,        45,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71375         {"C1_UP_WI"                    ,        46,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71376         {"C1_UP_BX"                    ,        47,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71377         {"C1_UN_B0"                    ,        48,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71378         {"C1_UN_B1"                    ,        49,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71379         {"C1_UN_B2"                    ,        50,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71380         {"C1_UN_WI"                    ,        51,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71381         {"C1_UN_BX"                    ,        52,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71382         {"C0_UN_WF"                    ,        53,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71383         {"C1_UN_WF"                    ,        54,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71384         {"C0_UP_WF"                    ,        55,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71385         {"C1_UP_WF"                    ,        56,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71386         {"C0_EXC"                      ,        57,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71387         {"C1_EXC"                      ,        58,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71388         {"C0_LDWN"                     ,        59,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71389         {"C1_LDWN"                     ,        60,     1,      465,    "R/W1C",        0,      0,      0ull,   0ull},
71390         {"INT_A"                       ,        61,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71391         {"RESERVED_62_62"              ,        62,     1,      465,    "RAZ",  0,      0,      0ull,   0ull},
71392         {"MIO_INTA"                    ,        63,     1,      465,    "RO",   0,      0,      0ull,   0ull},
71393         {"RML_RTO"                     ,        0,      1,      466,    "RO",   0,      0,      0ull,   0ull},
71394         {"RML_WTO"                     ,        1,      1,      466,    "RO",   0,      0,      0ull,   0ull},
71395         {"BAR0_TO"                     ,        2,      1,      466,    "RO",   0,      0,      0ull,   0ull},
71396         {"IOB2BIG"                     ,        3,      1,      466,    "RO",   0,      0,      0ull,   0ull},
71397         {"DMA0DBO"                     ,        4,      1,      466,    "RO",   0,      0,      0ull,   0ull},
71398         {"DMA1DBO"                     ,        5,      1,      466,    "RO",   0,      0,      0ull,   0ull},
71399         {"DMA2DBO"                     ,        6,      1,      466,    "RO",   0,      0,      0ull,   0ull},
71400         {"DMA3DBO"                     ,        7,      1,      466,    "RO",   0,      0,      0ull,   0ull},
71401         {"RESERVED_8_8"                ,        8,      1,      466,    "RAZ",  1,      1,      0,      0},
71402         {"DMA0FI"                      ,        9,      1,      466,    "RO",   0,      0,      0ull,   0ull},
71403         {"DMA1FI"                      ,        10,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71404         {"DCNT0"                       ,        11,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71405         {"DCNT1"                       ,        12,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71406         {"DTIME0"                      ,        13,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71407         {"DTIME1"                      ,        14,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71408         {"RESERVED_15_18"              ,        15,     4,      466,    "RAZ",  0,      0,      0ull,   0ull},
71409         {"C0_AERI"                     ,        19,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71410         {"CRS0_ER"                     ,        20,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71411         {"C0_SE"                       ,        21,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71412         {"CRS0_DR"                     ,        22,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71413         {"C0_WAKE"                     ,        23,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71414         {"C0_PMEI"                     ,        24,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71415         {"C0_HPINT"                    ,        25,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71416         {"C1_AERI"                     ,        26,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71417         {"CRS1_ER"                     ,        27,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71418         {"C1_SE"                       ,        28,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71419         {"CRS1_DR"                     ,        29,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71420         {"C1_WAKE"                     ,        30,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71421         {"C1_PMEI"                     ,        31,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71422         {"C1_HPINT"                    ,        32,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71423         {"C0_UP_B0"                    ,        33,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71424         {"C0_UP_B1"                    ,        34,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71425         {"C0_UP_B2"                    ,        35,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71426         {"C0_UP_WI"                    ,        36,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71427         {"C0_UP_BX"                    ,        37,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71428         {"C0_UN_B0"                    ,        38,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71429         {"C0_UN_B1"                    ,        39,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71430         {"C0_UN_B2"                    ,        40,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71431         {"C0_UN_WI"                    ,        41,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71432         {"C0_UN_BX"                    ,        42,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71433         {"C1_UP_B0"                    ,        43,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71434         {"C1_UP_B1"                    ,        44,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71435         {"C1_UP_B2"                    ,        45,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71436         {"C1_UP_WI"                    ,        46,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71437         {"C1_UP_BX"                    ,        47,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71438         {"C1_UN_B0"                    ,        48,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71439         {"C1_UN_B1"                    ,        49,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71440         {"C1_UN_B2"                    ,        50,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71441         {"C1_UN_WI"                    ,        51,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71442         {"C1_UN_BX"                    ,        52,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71443         {"C0_UN_WF"                    ,        53,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71444         {"C1_UN_WF"                    ,        54,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71445         {"C0_UP_WF"                    ,        55,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71446         {"C1_UP_WF"                    ,        56,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71447         {"C0_EXC"                      ,        57,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71448         {"C1_EXC"                      ,        58,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71449         {"C0_LDWN"                     ,        59,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71450         {"C1_LDWN"                     ,        60,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71451         {"INT_A"                       ,        61,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71452         {"RESERVED_62_62"              ,        62,     1,      466,    "RAZ",  0,      0,      0ull,   0ull},
71453         {"MIO_INTA"                    ,        63,     1,      466,    "RO",   0,      0,      0ull,   0ull},
71454         {"DATA"                        ,        0,      64,     467,    "RO",   0,      1,      0ull,   0},
71455         {"DATA"                        ,        0,      64,     468,    "RO",   0,      1,      0ull,   0},
71456         {"TIMER"                       ,        0,      10,     469,    "R/W",  0,      0,      0ull,   50ull},
71457         {"MAX_WORD"                    ,        10,     4,      469,    "R/W",  0,      0,      0ull,   0ull},
71458         {"RESERVED_14_63"              ,        14,     50,     469,    "RAZ",  1,      1,      0,      0},
71459         {"BA"                          ,        0,      30,     470,    "R/W",  0,      1,      0ull,   0},
71460         {"ROW"                         ,        30,     1,      470,    "R/W",  0,      1,      0ull,   0},
71461         {"ROR"                         ,        31,     1,      470,    "R/W",  0,      1,      0ull,   0},
71462         {"NSW"                         ,        32,     1,      470,    "R/W",  0,      1,      0ull,   0},
71463         {"NSR"                         ,        33,     1,      470,    "R/W",  0,      1,      0ull,   0},
71464         {"ESW"                         ,        34,     2,      470,    "R/W",  0,      1,      0ull,   0},
71465         {"ESR"                         ,        36,     2,      470,    "R/W",  0,      1,      0ull,   0},
71466         {"NMERGE"                      ,        38,     1,      470,    "R/W",  0,      0,      0ull,   0ull},
71467         {"PORT"                        ,        39,     2,      470,    "R/W",  0,      1,      0ull,   0},
71468         {"ZERO"                        ,        41,     1,      470,    "R/W",  0,      0,      0ull,   0ull},
71469         {"RESERVED_42_63"              ,        42,     22,     470,    "RAZ",  1,      1,      0,      0},
71470         {"ENB"                         ,        0,      64,     471,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
71471         {"ENB"                         ,        0,      64,     472,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
71472         {"ENB"                         ,        0,      64,     473,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
71473         {"ENB"                         ,        0,      64,     474,    "R/W",  0,      0,      0ull,   18446744073709551615ull},
71474         {"INTR"                        ,        0,      64,     475,    "R/W1C",        0,      0,      0ull,   0ull},
71475         {"INTR"                        ,        0,      64,     476,    "R/W1C",        0,      0,      0ull,   0ull},
71476         {"INTR"                        ,        0,      64,     477,    "R/W1C",        0,      0,      0ull,   0ull},
71477         {"INTR"                        ,        0,      64,     478,    "R/W1C",        0,      0,      0ull,   0ull},
71478         {"MSI_INT"                     ,        0,      8,      479,    "R/W",  0,      1,      0ull,   0},
71479         {"RD_INT"                      ,        8,      8,      479,    "RO",   0,      1,      0ull,   0},
71480         {"RESERVED_16_63"              ,        16,     48,     479,    "RAZ",  1,      1,      0,      0},
71481         {"CLR"                         ,        0,      64,     480,    "R/W",  0,      0,      0ull,   0ull},
71482         {"CLR"                         ,        0,      64,     481,    "R/W",  0,      0,      0ull,   0ull},
71483         {"CLR"                         ,        0,      64,     482,    "R/W",  0,      0,      0ull,   0ull},
71484         {"CLR"                         ,        0,      64,     483,    "R/W",  0,      0,      0ull,   0ull},
71485         {"SET"                         ,        0,      64,     484,    "R/W",  0,      0,      0ull,   0ull},
71486         {"SET"                         ,        0,      64,     485,    "R/W",  0,      0,      0ull,   0ull},
71487         {"SET"                         ,        0,      64,     486,    "R/W",  0,      0,      0ull,   0ull},
71488         {"SET"                         ,        0,      64,     487,    "R/W",  0,      0,      0ull,   0ull},
71489         {"MSI_INT"                     ,        0,      8,      488,    "R/W",  0,      1,      0ull,   0},
71490         {"CIU_INT"                     ,        8,      8,      488,    "R/W",  0,      1,      0ull,   0},
71491         {"RESERVED_16_63"              ,        16,     48,     488,    "RAZ",  1,      1,      0,      0},
71492         {"P0_PCNT"                     ,        0,      8,      489,    "R/W",  0,      0,      128ull, 128ull},
71493         {"P0_NCNT"                     ,        8,      8,      489,    "R/W",  0,      0,      16ull,  16ull},
71494         {"P0_CCNT"                     ,        16,     8,      489,    "R/W",  0,      0,      128ull, 128ull},
71495         {"P1_PCNT"                     ,        24,     8,      489,    "R/W",  0,      0,      128ull, 128ull},
71496         {"P1_NCNT"                     ,        32,     8,      489,    "R/W",  0,      0,      16ull,  16ull},
71497         {"P1_CCNT"                     ,        40,     8,      489,    "R/W",  0,      0,      128ull, 128ull},
71498         {"RESERVED_48_63"              ,        48,     16,     489,    "RAZ",  1,      1,      0,      0},
71499         {"INTR"                        ,        0,      8,      490,    "R/W",  0,      1,      0ull,   0},
71500         {"RESERVED_8_63"               ,        8,      56,     490,    "RAZ",  1,      1,      0,      0},
71501         {"RESERVED_0_7"                ,        0,      8,      491,    "RAZ",  1,      1,      0,      0},
71502         {"INTR"                        ,        8,      8,      491,    "R/W",  0,      1,      0ull,   0},
71503         {"RESERVED_16_63"              ,        16,     48,     491,    "RAZ",  1,      1,      0,      0},
71504         {"RESERVED_0_15"               ,        0,      16,     492,    "RAZ",  1,      1,      0,      0},
71505         {"INTR"                        ,        16,     8,      492,    "R/W",  0,      1,      0ull,   0},
71506         {"RESERVED_24_63"              ,        24,     40,     492,    "RAZ",  1,      1,      0,      0},
71507         {"RESERVED_0_23"               ,        0,      24,     493,    "RAZ",  1,      1,      0,      0},
71508         {"INTR"                        ,        24,     8,      493,    "R/W",  0,      1,      0ull,   0},
71509         {"RESERVED_32_63"              ,        32,     32,     493,    "RAZ",  1,      1,      0,      0},
71510         {"CNT"                         ,        0,      32,     494,    "R/W",  0,      0,      0ull,   0ull},
71511         {"TIMER"                       ,        32,     22,     494,    "RO",   0,      0,      0ull,   0ull},
71512         {"RESERVED_54_63"              ,        54,     10,     494,    "RAZ",  1,      1,      0,      0},
71513         {"CNT"                         ,        0,      32,     495,    "R/W",  0,      0,      0ull,   0ull},
71514         {"WMARK"                       ,        32,     32,     495,    "R/W",  0,      1,      4294967295ull,  0},
71515         {"RESERVED_0_2"                ,        0,      3,      496,    "RAZ",  1,      1,      0,      0},
71516         {"ADDR"                        ,        3,      61,     496,    "R/W",  0,      1,      0ull,   0},
71517         {"DBELL"                       ,        0,      32,     497,    "R/W",  0,      0,      0ull,   0ull},
71518         {"AOFF"                        ,        32,     32,     497,    "RO",   0,      1,      0ull,   0},
71519         {"RSIZE"                       ,        0,      32,     498,    "R/W",  0,      1,      0ull,   0},
71520         {"FCNT"                        ,        32,     5,      498,    "RO",   0,      1,      0ull,   0},
71521         {"WRP"                         ,        37,     9,      498,    "RO",   0,      1,      0ull,   0},
71522         {"RRP"                         ,        46,     9,      498,    "RO",   0,      1,      0ull,   0},
71523         {"MAX"                         ,        55,     9,      498,    "RO",   0,      1,      16ull,  0},
71524         {"RESERVED_0_5"                ,        0,      6,      499,    "RAZ",  0,      1,      0ull,   0},
71525         {"SKP_LEN"                     ,        6,      7,      499,    "R/W",  0,      1,      0ull,   0},
71526         {"RESERVED_13_13"              ,        13,     1,      499,    "RAZ",  0,      1,      0ull,   0},
71527         {"PAR_MODE"                    ,        14,     2,      499,    "R/W",  0,      1,      0ull,   0},
71528         {"RESERVED_16_20"              ,        16,     5,      499,    "RAZ",  0,      1,      0ull,   0},
71529         {"USE_IHDR"                    ,        21,     1,      499,    "R/W",  0,      1,      0ull,   0},
71530         {"RESERVED_22_27"              ,        22,     6,      499,    "R/W",  0,      1,      0ull,   0},
71531         {"RSKP_LEN"                    ,        28,     7,      499,    "R/W",  0,      1,      0ull,   0},
71532         {"RESERVED_35_35"              ,        35,     1,      499,    "RAZ",  0,      1,      0ull,   0},
71533         {"RPARMODE"                    ,        36,     2,      499,    "R/W",  0,      1,      0ull,   0},
71534         {"RESERVED_38_42"              ,        38,     5,      499,    "RAZ",  0,      1,      0ull,   0},
71535         {"PBP"                         ,        43,     1,      499,    "R/W",  0,      1,      0ull,   0},
71536         {"RESERVED_44_63"              ,        44,     20,     499,    "RAZ",  1,      1,      0,      0},
71537         {"RESERVED_0_3"                ,        0,      4,      500,    "RAZ",  1,      1,      0,      0},
71538         {"ADDR"                        ,        4,      60,     500,    "R/W",  0,      1,      0ull,   0},
71539         {"DBELL"                       ,        0,      32,     501,    "R/W",  0,      0,      0ull,   0ull},
71540         {"AOFF"                        ,        32,     32,     501,    "RO",   0,      1,      0ull,   0},
71541         {"RSIZE"                       ,        0,      32,     502,    "R/W",  0,      1,      0ull,   0},
71542         {"RESERVED_32_63"              ,        32,     32,     502,    "RAZ",  0,      1,      0ull,   0},
71543         {"PORT"                        ,        0,      32,     503,    "R/W1C",        0,      1,      0ull,   0},
71544         {"RESERVED_32_63"              ,        32,     32,     503,    "RAZ",  1,      1,      0,      0},
71545         {"PORT"                        ,        0,      32,     504,    "R/W",  0,      1,      0ull,   0},
71546         {"RESERVED_32_63"              ,        32,     32,     504,    "RAZ",  1,      1,      0,      0},
71547         {"ES"                          ,        0,      64,     505,    "R/W",  0,      1,      0ull,   0},
71548         {"NSR"                         ,        0,      32,     506,    "R/W",  0,      1,      0ull,   0},
71549         {"RESERVED_32_63"              ,        32,     32,     506,    "RAZ",  1,      1,      0,      0},
71550         {"ROR"                         ,        0,      32,     507,    "R/W",  0,      1,      0ull,   0},
71551         {"RESERVED_32_63"              ,        32,     32,     507,    "RAZ",  1,      1,      0,      0},
71552         {"DPTR"                        ,        0,      32,     508,    "R/W",  0,      0,      0ull,   4294967295ull},
71553         {"RESERVED_32_63"              ,        32,     32,     508,    "RAZ",  1,      1,      0,      0},
71554         {"BP"                          ,        0,      32,     509,    "RO",   0,      1,      0ull,   0},
71555         {"RESERVED_32_63"              ,        32,     32,     509,    "RAZ",  1,      1,      0,      0},
71556         {"CNT"                         ,        0,      32,     510,    "RO",   0,      1,      0ull,   0},
71557         {"RESERVED_32_63"              ,        32,     32,     510,    "RAZ",  0,      1,      0ull,   0},
71558         {"RD_CNT"                      ,        0,      32,     511,    "RO",   0,      1,      0ull,   0},
71559         {"WR_CNT"                      ,        32,     32,     511,    "RO",   0,      1,      0ull,   0},
71560         {"PP"                          ,        0,      64,     512,    "R/W",  0,      1,      0ull,   0},
71561         {"ROR"                         ,        0,      1,      513,    "R/W",  0,      1,      0ull,   0},
71562         {"ESR"                         ,        1,      2,      513,    "R/W",  0,      1,      0ull,   0},
71563         {"NSR"                         ,        3,      1,      513,    "R/W",  0,      1,      0ull,   0},
71564         {"USE_CSR"                     ,        4,      1,      513,    "R/W",  0,      0,      0ull,   1ull},
71565         {"D_ROR"                       ,        5,      1,      513,    "R/W",  0,      1,      0ull,   0},
71566         {"D_ESR"                       ,        6,      2,      513,    "R/W",  0,      1,      0ull,   0},
71567         {"D_NSR"                       ,        8,      1,      513,    "R/W",  0,      1,      0ull,   0},
71568         {"PBP_DHI"                     ,        9,      13,     513,    "R/W",  0,      0,      0ull,   0ull},
71569         {"PKT_RR"                      ,        22,     1,      513,    "R/W",  0,      0,      0ull,   1ull},
71570         {"RESERVED_23_63"              ,        23,     41,     513,    "RAZ",  1,      1,      0,      0},
71571         {"ENB"                         ,        0,      32,     514,    "R/W",  0,      1,      0ull,   0},
71572         {"RESERVED_32_63"              ,        32,     32,     514,    "RAZ",  1,      1,      0,      0},
71573         {"RDSIZE"                      ,        0,      64,     515,    "R/W",  0,      1,      0ull,   0},
71574         {"IS_64B"                      ,        0,      32,     516,    "R/W",  0,      1,      0ull,   0},
71575         {"RESERVED_32_63"              ,        32,     32,     516,    "RAZ",  1,      1,      0,      0},
71576         {"CNT"                         ,        0,      32,     517,    "R/W",  0,      1,      0ull,   0},
71577         {"TIME"                        ,        32,     22,     517,    "R/W",  0,      1,      0ull,   0},
71578         {"RESERVED_54_63"              ,        54,     10,     517,    "RAZ",  1,      1,      0,      0},
71579         {"IPTR"                        ,        0,      32,     518,    "R/W",  0,      1,      0ull,   0},
71580         {"RESERVED_32_63"              ,        32,     32,     518,    "RAZ",  1,      1,      0,      0},
71581         {"BMODE"                       ,        0,      32,     519,    "R/W",  0,      1,      0ull,   0},
71582         {"RESERVED_32_63"              ,        32,     32,     519,    "RAZ",  1,      1,      0,      0},
71583         {"ENB"                         ,        0,      32,     520,    "R/W",  0,      1,      0ull,   0},
71584         {"RESERVED_32_63"              ,        32,     32,     520,    "RAZ",  1,      1,      0,      0},
71585         {"WMARK"                       ,        0,      32,     521,    "R/W",  0,      0,      0ull,   14ull},
71586         {"RESERVED_32_63"              ,        32,     32,     521,    "RAZ",  1,      1,      0,      0},
71587         {"PP"                          ,        0,      64,     522,    "R/W",  0,      1,      0ull,   0},
71588         {"OUT_RST"                     ,        0,      32,     523,    "RO",   0,      1,      0ull,   0},
71589         {"IN_RST"                      ,        32,     32,     523,    "RO",   0,      1,      0ull,   0},
71590         {"ES"                          ,        0,      64,     524,    "R/W",  0,      1,      0ull,   0},
71591         {"BSIZE"                       ,        0,      16,     525,    "R/W",  0,      1,      0ull,   0},
71592         {"ISIZE"                       ,        16,     7,      525,    "R/W",  0,      1,      0ull,   0},
71593         {"RESERVED_23_63"              ,        23,     41,     525,    "RAZ",  1,      1,      0,      0},
71594         {"NSR"                         ,        0,      32,     526,    "R/W",  0,      1,      0ull,   0},
71595         {"RESERVED_32_63"              ,        32,     32,     526,    "RAZ",  1,      1,      0,      0},
71596         {"ROR"                         ,        0,      32,     527,    "R/W",  0,      1,      0ull,   0},
71597         {"RESERVED_32_63"              ,        32,     32,     527,    "RAZ",  1,      1,      0,      0},
71598         {"PORT"                        ,        0,      32,     528,    "R/W1C",        0,      1,      0ull,   0},
71599         {"RESERVED_32_63"              ,        32,     32,     528,    "RAZ",  1,      1,      0,      0},
71600         {"PORT"                        ,        0,      32,     529,    "R/W",  0,      1,      0ull,   0},
71601         {"RESERVED_32_63"              ,        32,     32,     529,    "RAZ",  1,      1,      0,      0},
71602         {"MIO"                         ,        0,      1,      530,    "RO",   0,      0,      0ull,   0ull},
71603         {"GMX0"                        ,        1,      1,      530,    "RO",   0,      0,      0ull,   0ull},
71604         {"GMX1"                        ,        2,      1,      530,    "RO",   0,      0,      0ull,   0ull},
71605         {"NPEI"                        ,        3,      1,      530,    "RO",   0,      0,      0ull,   0ull},
71606         {"KEY"                         ,        4,      1,      530,    "RO",   0,      0,      0ull,   0ull},
71607         {"FPA"                         ,        5,      1,      530,    "RO",   0,      0,      0ull,   0ull},
71608         {"DFA"                         ,        6,      1,      530,    "RAZ",  0,      0,      0ull,   0ull},
71609         {"ZIP"                         ,        7,      1,      530,    "RO",   0,      0,      0ull,   0ull},
71610         {"RESERVED_8_8"                ,        8,      1,      530,    "RAZ",  0,      0,      0ull,   0ull},
71611         {"IPD"                         ,        9,      1,      530,    "RO",   0,      0,      0ull,   0ull},
71612         {"PKO"                         ,        10,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71613         {"TIM"                         ,        11,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71614         {"POW"                         ,        12,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71615         {"USB"                         ,        13,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71616         {"RAD"                         ,        14,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71617         {"USB1"                        ,        15,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71618         {"L2C"                         ,        16,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71619         {"LMC0"                        ,        17,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71620         {"SPX0"                        ,        18,     1,      530,    "RAZ",  0,      0,      0ull,   0ull},
71621         {"SPX1"                        ,        19,     1,      530,    "RAZ",  0,      0,      0ull,   0ull},
71622         {"PIP"                         ,        20,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71623         {"RESERVED_21_21"              ,        21,     1,      530,    "RAZ",  0,      0,      0ull,   0ull},
71624         {"ASXPCS0"                     ,        22,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71625         {"ASXPCS1"                     ,        23,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71626         {"RESERVED_24_27"              ,        24,     4,      530,    "RAZ",  0,      0,      0ull,   0ull},
71627         {"AGL"                         ,        28,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71628         {"LMC1"                        ,        29,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71629         {"IOB"                         ,        30,     1,      530,    "RO",   0,      0,      0ull,   0ull},
71630         {"RESERVED_31_63"              ,        31,     33,     530,    "RAZ",  0,      0,      0ull,   0ull},
71631         {"DATA"                        ,        0,      64,     531,    "R/W",  0,      1,      0ull,   0},
71632         {"CSR"                         ,        0,      39,     532,    "RO",   0,      1,      1ull,   0},
71633         {"ARB"                         ,        39,     1,      532,    "RO",   0,      1,      0ull,   0},
71634         {"CPL0"                        ,        40,     12,     532,    "RO",   0,      1,      1ull,   0},
71635         {"CPL1"                        ,        52,     12,     532,    "RO",   0,      1,      1ull,   0},
71636         {"NND"                         ,        0,      8,      533,    "RO",   0,      1,      1ull,   0},
71637         {"NNP0"                        ,        8,      8,      533,    "RO",   0,      1,      1ull,   0},
71638         {"CSM0"                        ,        16,     15,     533,    "RO",   0,      1,      1ull,   0},
71639         {"CSM1"                        ,        31,     15,     533,    "RO",   0,      1,      1ull,   0},
71640         {"RAC"                         ,        46,     1,      533,    "RO",   0,      1,      1ull,   0},
71641         {"NPEI"                        ,        47,     1,      533,    "RO",   0,      1,      1ull,   0},
71642         {"RESERVED_48_63"              ,        48,     16,     533,    "RAZ",  1,      1,      0,      0},
71643         {"NSM0"                        ,        0,      13,     534,    "RO",   0,      1,      1ull,   0},
71644         {"NSM1"                        ,        13,     13,     534,    "RO",   0,      1,      1ull,   0},
71645         {"PSM0"                        ,        26,     15,     534,    "RO",   0,      1,      1ull,   0},
71646         {"PSM1"                        ,        41,     15,     534,    "RO",   0,      1,      1ull,   0},
71647         {"RESERVED_56_63"              ,        56,     8,      534,    "RAZ",  1,      1,      0,      0},
71648         {"RD_ADDR"                     ,        0,      48,     535,    "R/W",  0,      1,      0ull,   0},
71649         {"IOBIT"                       ,        48,     1,      535,    "RAZ",  0,      0,      0ull,   0ull},
71650         {"LD_CMD"                      ,        49,     2,      535,    "R/W",  0,      1,      0ull,   0},
71651         {"RESERVED_51_63"              ,        51,     13,     535,    "RAZ",  1,      1,      0,      0},
71652         {"RD_DATA"                     ,        0,      64,     536,    "RO",   0,      1,      0ull,   0},
71653         {"RESERVED_0_1"                ,        0,      2,      537,    "RAZ",  1,      1,      0,      0},
71654         {"WR_ADDR"                     ,        2,      46,     537,    "R/W",  0,      1,      0ull,   0},
71655         {"IOBIT"                       ,        48,     1,      537,    "RAZ",  0,      0,      0ull,   0ull},
71656         {"RESERVED_49_63"              ,        49,     15,     537,    "RAZ",  1,      1,      0,      0},
71657         {"WR_DATA"                     ,        0,      64,     538,    "R/W",  0,      1,      0ull,   0},
71658         {"WR_MASK"                     ,        0,      8,      539,    "R/W",  0,      0,      0ull,   0ull},
71659         {"RESERVED_8_63"               ,        8,      56,     539,    "RAZ",  1,      1,      0,      0},
71660         {"TIME"                        ,        0,      32,     540,    "R/W",  0,      0,      0ull,   2097152ull},
71661         {"RESERVED_32_63"              ,        32,     32,     540,    "RAZ",  1,      1,      0,      0},
71662         {"VENDID"                      ,        0,      16,     541,    "RO/WRSL",      0,      0,      6013ull,        6013ull},
71663         {"DEVID"                       ,        16,     16,     541,    "RO/WRSL",      0,      0,      128ull, 128ull},
71664         {"ISAE"                        ,        0,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
71665         {"MSAE"                        ,        1,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
71666         {"ME"                          ,        2,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
71667         {"SCSE"                        ,        3,      1,      542,    "RO",   0,      0,      0ull,   0ull},
71668         {"MWICE"                       ,        4,      1,      542,    "RO",   0,      0,      0ull,   0ull},
71669         {"VPS"                         ,        5,      1,      542,    "RO",   0,      0,      0ull,   0ull},
71670         {"PER"                         ,        6,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
71671         {"IDS_WCC"                     ,        7,      1,      542,    "RO",   0,      0,      0ull,   0ull},
71672         {"SEE"                         ,        8,      1,      542,    "R/W",  0,      0,      0ull,   0ull},
71673         {"FBBE"                        ,        9,      1,      542,    "RO",   0,      0,      0ull,   0ull},
71674         {"I_DIS"                       ,        10,     1,      542,    "R/W",  0,      0,      0ull,   0ull},
71675         {"RESERVED_11_18"              ,        11,     8,      542,    "RAZ",  1,      1,      0,      0},
71676         {"I_STAT"                      ,        19,     1,      542,    "RO",   0,      0,      0ull,   0ull},
71677         {"CL"                          ,        20,     1,      542,    "RO",   0,      0,      1ull,   1ull},
71678         {"M66"                         ,        21,     1,      542,    "RO",   0,      0,      0ull,   0ull},
71679         {"RESERVED_22_22"              ,        22,     1,      542,    "RAZ",  1,      1,      0,      0},
71680         {"FBB"                         ,        23,     1,      542,    "RO",   0,      0,      0ull,   0ull},
71681         {"MDPE"                        ,        24,     1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
71682         {"DEVT"                        ,        25,     2,      542,    "RO",   0,      0,      0ull,   0ull},
71683         {"STA"                         ,        27,     1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
71684         {"RTA"                         ,        28,     1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
71685         {"RMA"                         ,        29,     1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
71686         {"SSE"                         ,        30,     1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
71687         {"DPE"                         ,        31,     1,      542,    "R/W1C",        0,      0,      0ull,   0ull},
71688         {"RID"                         ,        0,      8,      543,    "RO/WRSL",      0,      0,      8ull,   8ull},
71689         {"PI"                          ,        8,      8,      543,    "RO/WRSL",      0,      0,      0ull,   0ull},
71690         {"SC"                          ,        16,     8,      543,    "RO/WRSL",      0,      0,      48ull,  48ull},
71691         {"BCC"                         ,        24,     8,      543,    "RO/WRSL",      0,      0,      11ull,  11ull},
71692         {"CLS"                         ,        0,      8,      544,    "R/W",  0,      0,      0ull,   0ull},
71693         {"LT"                          ,        8,      8,      544,    "RO",   0,      0,      0ull,   0ull},
71694         {"CHF"                         ,        16,     7,      544,    "RO",   0,      0,      0ull,   0ull},
71695         {"MFD"                         ,        23,     1,      544,    "RO/WRSL",      0,      0,      0ull,   0ull},
71696         {"BIST"                        ,        24,     8,      544,    "RO",   0,      0,      0ull,   0ull},
71697         {"MSPC"                        ,        0,      1,      545,    "RO/WRSL",      0,      0,      0ull,   0ull},
71698         {"TYP"                         ,        1,      2,      545,    "RO/WRSL",      0,      0,      2ull,   2ull},
71699         {"PF"                          ,        3,      1,      545,    "RO/WRSL",      0,      0,      1ull,   1ull},
71700         {"RESERVED_4_13"               ,        4,      10,     545,    "RAZ",  1,      1,      0,      0},
71701         {"LBAB"                        ,        14,     18,     545,    "R/W",  0,      0,      0ull,   0ull},
71702         {"ENB"                         ,        0,      1,      546,    "WORSL",        0,      0,      1ull,   1ull},
71703         {"LMASK"                       ,        1,      31,     546,    "WORSL",        0,      0,      8191ull,        8191ull},
71704         {"UBAB"                        ,        0,      32,     547,    "R/W",  0,      0,      0ull,   0ull},
71705         {"UMASK"                       ,        0,      32,     548,    "WORSL",        0,      0,      0ull,   0ull},
71706         {"MSPC"                        ,        0,      1,      549,    "RO/WRSL",      0,      0,      0ull,   0ull},
71707         {"TYP"                         ,        1,      2,      549,    "RO/WRSL",      0,      0,      2ull,   2ull},
71708         {"PF"                          ,        3,      1,      549,    "RO/WRSL",      0,      0,      1ull,   1ull},
71709         {"RESERVED_4_25"               ,        4,      22,     549,    "RAZ",  1,      1,      0,      0},
71710         {"LBAB"                        ,        26,     6,      549,    "R/W",  0,      0,      0ull,   0ull},
71711         {"ENB"                         ,        0,      1,      550,    "WORSL",        0,      0,      1ull,   1ull},
71712         {"LMASK"                       ,        1,      31,     550,    "WORSL",        0,      0,      33554431ull,    33554431ull},
71713         {"UBAB"                        ,        0,      32,     551,    "R/W",  0,      0,      0ull,   0ull},
71714         {"UMASK"                       ,        0,      32,     552,    "WORSL",        0,      0,      0ull,   0ull},
71715         {"MSPC"                        ,        0,      1,      553,    "RO/WRSL",      0,      0,      0ull,   0ull},
71716         {"TYP"                         ,        1,      2,      553,    "RO/WRSL",      0,      0,      2ull,   2ull},
71717         {"PF"                          ,        3,      1,      553,    "RO/WRSL",      0,      0,      1ull,   1ull},
71718         {"RESERVED_4_31"               ,        4,      28,     553,    "RAZ",  1,      1,      0,      0},
71719         {"ENB"                         ,        0,      1,      554,    "WORSL",        0,      0,      1ull,   1ull},
71720         {"LMASK"                       ,        1,      31,     554,    "WORSL",        0,      0,      2147483647ull,  2147483647ull},
71721         {"RESERVED_0_6"                ,        0,      7,      555,    "RAZ",  1,      1,      0,      0},
71722         {"UBAB"                        ,        7,      25,     555,    "R/W",  0,      0,      0ull,   0ull},
71723         {"UMASK"                       ,        0,      32,     556,    "WORSL",        0,      0,      127ull, 127ull},
71724         {"CISP"                        ,        0,      32,     557,    "RO/WRSL",      0,      0,      0ull,   0ull},
71725         {"SSVID"                       ,        0,      16,     558,    "RO/WRSL",      0,      0,      6013ull,        6013ull},
71726         {"SSID"                        ,        16,     16,     558,    "RO/WRSL",      0,      0,      1ull,   1ull},
71727         {"ER_EN"                       ,        0,      1,      559,    "R/W",  0,      0,      0ull,   0ull},
71728         {"RESERVED_1_15"               ,        1,      15,     559,    "RAZ",  1,      1,      0,      0},
71729         {"ERADDR"                      ,        16,     16,     559,    "R/W",  0,      0,      0ull,   0ull},
71730         {"ENB"                         ,        0,      1,      560,    "WORSL",        0,      0,      1ull,   1ull},
71731         {"MASK"                        ,        1,      31,     560,    "WORSL",        0,      0,      2147483647ull,  2147483647ull},
71732         {"CP"                          ,        0,      8,      561,    "RO/WRSL",      0,      0,      64ull,  64ull},
71733         {"RESERVED_8_31"               ,        8,      24,     561,    "RAZ",  1,      1,      0,      0},
71734         {"IL"                          ,        0,      8,      562,    "R/W",  0,      0,      255ull, 255ull},
71735         {"INTA"                        ,        8,      8,      562,    "RO/WRSL",      0,      0,      1ull,   1ull},
71736         {"MG"                          ,        16,     8,      562,    "RO",   0,      0,      0ull,   0ull},
71737         {"ML"                          ,        24,     8,      562,    "RO",   0,      0,      0ull,   0ull},
71738         {"PMCID"                       ,        0,      8,      563,    "RO",   0,      0,      1ull,   0ull},
71739         {"NCP"                         ,        8,      8,      563,    "RO/WRSL",      0,      0,      80ull,  0ull},
71740         {"PMSV"                        ,        16,     3,      563,    "RO/WRSL",      0,      0,      3ull,   0ull},
71741         {"PME_CLOCK"                   ,        19,     1,      563,    "RO",   0,      0,      0ull,   0ull},
71742         {"RESERVED_20_20"              ,        20,     1,      563,    "RAZ",  1,      1,      0,      0},
71743         {"DSI"                         ,        21,     1,      563,    "RO/WRSL",      0,      0,      0ull,   0ull},
71744         {"AUXC"                        ,        22,     3,      563,    "RO/WRSL",      0,      0,      0ull,   0ull},
71745         {"D1S"                         ,        25,     1,      563,    "RO/WRSL",      0,      0,      0ull,   0ull},
71746         {"D2S"                         ,        26,     1,      563,    "RO/WRSL",      0,      0,      0ull,   0ull},
71747         {"PMES"                        ,        27,     5,      563,    "RO/WRSL",      0,      0,      0ull,   0ull},
71748         {"PS"                          ,        0,      2,      564,    "R/W",  0,      0,      0ull,   0ull},
71749         {"RESERVED_2_2"                ,        2,      1,      564,    "RAZ",  1,      1,      0,      0},
71750         {"NSR"                         ,        3,      1,      564,    "RO/WRSL",      0,      0,      0ull,   0ull},
71751         {"RESERVED_4_7"                ,        4,      4,      564,    "RAZ",  1,      1,      0,      0},
71752         {"PMEENS"                      ,        8,      1,      564,    "R/W",  0,      0,      0ull,   0ull},
71753         {"PMDS"                        ,        9,      4,      564,    "RO",   0,      0,      0ull,   0ull},
71754         {"PMEDSIA"                     ,        13,     2,      564,    "RO",   0,      0,      0ull,   0ull},
71755         {"PMESS"                       ,        15,     1,      564,    "R/W1C",        0,      0,      0ull,   0ull},
71756         {"RESERVED_16_21"              ,        16,     6,      564,    "RAZ",  1,      1,      0,      0},
71757         {"BD3H"                        ,        22,     1,      564,    "RO",   0,      0,      0ull,   0ull},
71758         {"BPCCEE"                      ,        23,     1,      564,    "RO",   0,      0,      0ull,   0ull},
71759         {"PMDIA"                       ,        24,     8,      564,    "RO",   0,      0,      0ull,   0ull},
71760         {"MSICID"                      ,        0,      8,      565,    "RO",   0,      0,      5ull,   5ull},
71761         {"NCP"                         ,        8,      8,      565,    "RO/WRSL",      0,      0,      112ull, 112ull},
71762         {"MSIEN"                       ,        16,     1,      565,    "R/W",  0,      0,      0ull,   0ull},
71763         {"MMC"                         ,        17,     3,      565,    "RO/WRSL",      0,      0,      0ull,   0ull},
71764         {"MME"                         ,        20,     3,      565,    "R/W",  0,      0,      0ull,   0ull},
71765         {"M64"                         ,        23,     1,      565,    "RO/WRSL",      0,      0,      1ull,   1ull},
71766         {"RESERVED_24_31"              ,        24,     8,      565,    "RAZ",  1,      1,      0,      0},
71767         {"RESERVED_0_1"                ,        0,      2,      566,    "RAZ",  1,      1,      0,      0},
71768         {"LMSI"                        ,        2,      30,     566,    "R/W",  0,      0,      0ull,   0ull},
71769         {"UMSI"                        ,        0,      32,     567,    "R/W",  0,      0,      0ull,   0ull},
71770         {"MSIMD"                       ,        0,      16,     568,    "R/W",  0,      0,      0ull,   0ull},
71771         {"RESERVED_16_31"              ,        16,     16,     568,    "RAZ",  1,      1,      0,      0},
71772         {"PCIEID"                      ,        0,      8,      569,    "RO",   0,      0,      16ull,  16ull},
71773         {"NCP"                         ,        8,      8,      569,    "RO/WRSL",      0,      0,      0ull,   0ull},
71774         {"PCIECV"                      ,        16,     4,      569,    "RO",   0,      0,      2ull,   2ull},
71775         {"DPT"                         ,        20,     4,      569,    "RO",   0,      0,      0ull,   0ull},
71776         {"SI"                          ,        24,     1,      569,    "RO/WRSL",      0,      0,      0ull,   0ull},
71777         {"IMN"                         ,        25,     5,      569,    "RO/WRSL",      0,      0,      0ull,   0ull},
71778         {"RESERVED_30_31"              ,        30,     2,      569,    "RAZ",  1,      1,      0,      0},
71779         {"MPSS"                        ,        0,      3,      570,    "RO/WRSL",      0,      0,      1ull,   1ull},
71780         {"PFS"                         ,        3,      2,      570,    "RO/WRSL",      0,      0,      0ull,   0ull},
71781         {"ETFS"                        ,        5,      1,      570,    "RO/WRSL",      0,      0,      0ull,   0ull},
71782         {"EL0AL"                       ,        6,      3,      570,    "RO/WRSL",      0,      0,      4ull,   4ull},
71783         {"EL1AL"                       ,        9,      3,      570,    "RO/WRSL",      0,      0,      3ull,   3ull},
71784         {"RESERVED_12_14"              ,        12,     3,      570,    "RAZ",  1,      1,      0,      0},
71785         {"RBER"                        ,        15,     1,      570,    "RO/WRSL",      0,      0,      1ull,   1ull},
71786         {"RESERVED_16_17"              ,        16,     2,      570,    "RAZ",  1,      1,      0,      0},
71787         {"CSPLV"                       ,        18,     8,      570,    "RO",   0,      0,      0ull,   0ull},
71788         {"CSPLS"                       ,        26,     2,      570,    "RO",   0,      0,      0ull,   0ull},
71789         {"RESERVED_28_31"              ,        28,     4,      570,    "RAZ",  1,      1,      0,      0},
71790         {"CE_EN"                       ,        0,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
71791         {"NFE_EN"                      ,        1,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
71792         {"FE_EN"                       ,        2,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
71793         {"UR_EN"                       ,        3,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
71794         {"RO_EN"                       ,        4,      1,      571,    "R/W",  0,      0,      1ull,   1ull},
71795         {"MPS"                         ,        5,      3,      571,    "R/W",  0,      0,      0ull,   0ull},
71796         {"ETF_EN"                      ,        8,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
71797         {"PF_EN"                       ,        9,      1,      571,    "R/W",  0,      0,      0ull,   0ull},
71798         {"AP_EN"                       ,        10,     1,      571,    "R/W",  0,      0,      0ull,   0ull},
71799         {"NS_EN"                       ,        11,     1,      571,    "R/W",  0,      0,      1ull,   1ull},
71800         {"MRRS"                        ,        12,     3,      571,    "R/W",  0,      0,      2ull,   2ull},
71801         {"RESERVED_15_15"              ,        15,     1,      571,    "RAZ",  1,      1,      0,      0},
71802         {"CE_D"                        ,        16,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
71803         {"NFE_D"                       ,        17,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
71804         {"FE_D"                        ,        18,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
71805         {"UR_D"                        ,        19,     1,      571,    "R/W1C",        0,      0,      0ull,   0ull},
71806         {"AP_D"                        ,        20,     1,      571,    "RO",   0,      0,      0ull,   0ull},
71807         {"TP"                          ,        21,     1,      571,    "RO",   0,      0,      0ull,   0ull},
71808         {"RESERVED_22_31"              ,        22,     10,     571,    "RAZ",  1,      1,      0,      0},
71809         {"MLS"                         ,        0,      4,      572,    "RO/WRSL",      0,      0,      1ull,   1ull},
71810         {"MLW"                         ,        4,      6,      572,    "RO/WRSL",      0,      0,      8ull,   8ull},
71811         {"ASLPMS"                      ,        10,     2,      572,    "RO/WRSL",      0,      0,      3ull,   3ull},
71812         {"L0EL"                        ,        12,     3,      572,    "RO/WRSL",      0,      0,      6ull,   6ull},
71813         {"L1EL"                        ,        15,     3,      572,    "RO/WRSL",      0,      0,      6ull,   6ull},
71814         {"CPM"                         ,        18,     1,      572,    "RO/WRSL",      0,      0,      0ull,   0ull},
71815         {"SDERC"                       ,        19,     1,      572,    "RO",   0,      0,      0ull,   0ull},
71816         {"DLLARC"                      ,        20,     1,      572,    "RO",   0,      0,      0ull,   0ull},
71817         {"LBNC"                        ,        21,     1,      572,    "RO",   0,      0,      0ull,   0ull},
71818         {"RESERVED_22_23"              ,        22,     2,      572,    "RAZ",  1,      1,      0,      0},
71819         {"PNUM"                        ,        24,     8,      572,    "RO/WRSL",      0,      0,      0ull,   0ull},
71820         {"ASLPC"                       ,        0,      2,      573,    "R/W",  0,      0,      0ull,   0ull},
71821         {"RESERVED_2_2"                ,        2,      1,      573,    "RAZ",  1,      1,      0,      0},
71822         {"RCB"                         ,        3,      1,      573,    "RO",   0,      0,      0ull,   0ull},
71823         {"LD"                          ,        4,      1,      573,    "RO",   0,      0,      0ull,   0ull},
71824         {"RL"                          ,        5,      1,      573,    "RO",   0,      0,      0ull,   0ull},
71825         {"CCC"                         ,        6,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
71826         {"ES"                          ,        7,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
71827         {"ECPM"                        ,        8,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
71828         {"HAWD"                        ,        9,      1,      573,    "R/W",  0,      0,      0ull,   0ull},
71829         {"RESERVED_10_15"              ,        10,     6,      573,    "RAZ",  1,      1,      0,      0},
71830         {"LS"                          ,        16,     4,      573,    "RO",   0,      0,      1ull,   1ull},
71831         {"NLW"                         ,        20,     6,      573,    "RO",   0,      0,      0ull,   8ull},
71832         {"RESERVED_26_26"              ,        26,     1,      573,    "RAZ",  1,      1,      0,      0},
71833         {"LT"                          ,        27,     1,      573,    "RO",   0,      0,      0ull,   0ull},
71834         {"SCC"                         ,        28,     1,      573,    "RO/WRSL",      0,      0,      1ull,   1ull},
71835         {"DLLA"                        ,        29,     1,      573,    "RO",   0,      0,      0ull,   0ull},
71836         {"RESERVED_30_31"              ,        30,     2,      573,    "RAZ",  1,      1,      0,      0},
71837         {"ABP"                         ,        0,      1,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71838         {"PCP"                         ,        1,      1,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71839         {"MRLSP"                       ,        2,      1,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71840         {"AIP"                         ,        3,      1,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71841         {"PIP"                         ,        4,      1,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71842         {"HP_S"                        ,        5,      1,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71843         {"HP_C"                        ,        6,      1,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71844         {"SP_LV"                       ,        7,      8,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71845         {"SP_LS"                       ,        15,     2,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71846         {"EMIP"                        ,        17,     1,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71847         {"NCCS"                        ,        18,     1,      574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71848         {"PS_NUM"                      ,        19,     13,     574,    "RO/WRSL",      0,      0,      0ull,   0ull},
71849         {"ABP_EN"                      ,        0,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
71850         {"PF_EN"                       ,        1,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
71851         {"MRLS_EN"                     ,        2,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
71852         {"PD_EN"                       ,        3,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
71853         {"CCINT_EN"                    ,        4,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
71854         {"HPINT_EN"                    ,        5,      1,      575,    "R/W",  0,      0,      0ull,   0ull},
71855         {"AIC"                         ,        6,      2,      575,    "R/W",  0,      0,      0ull,   0ull},
71856         {"PIC"                         ,        8,      2,      575,    "R/W",  0,      0,      0ull,   0ull},
71857         {"PCC"                         ,        10,     1,      575,    "R/W",  0,      0,      0ull,   0ull},
71858         {"EMIC"                        ,        11,     1,      575,    "R/W",  0,      0,      0ull,   0ull},
71859         {"DLLS_EN"                     ,        12,     1,      575,    "RO",   0,      0,      0ull,   0ull},
71860         {"RESERVED_13_15"              ,        13,     3,      575,    "RAZ",  1,      1,      0,      0},
71861         {"ABP_D"                       ,        16,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
71862         {"PF_D"                        ,        17,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
71863         {"MRLS_C"                      ,        18,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
71864         {"PD_C"                        ,        19,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
71865         {"CCINT_D"                     ,        20,     1,      575,    "R/W1C",        0,      0,      0ull,   0ull},
71866         {"MRLSS"                       ,        21,     1,      575,    "RO",   0,      0,      0ull,   0ull},
71867         {"PDS"                         ,        22,     1,      575,    "RO",   0,      0,      0ull,   0ull},
71868         {"EMIS"                        ,        23,     1,      575,    "RO",   0,      0,      0ull,   0ull},
71869         {"DLLS_C"                      ,        24,     1,      575,    "RO",   0,      0,      0ull,   0ull},
71870         {"RESERVED_25_31"              ,        25,     7,      575,    "RAZ",  1,      1,      0,      0},
71871         {"CTRS"                        ,        0,      4,      576,    "RO",   0,      0,      0ull,   0ull},
71872         {"CTDS"                        ,        4,      1,      576,    "RO",   0,      0,      1ull,   1ull},
71873         {"RESERVED_5_31"               ,        5,      27,     576,    "RAZ",  1,      1,      0,      0},
71874         {"CTV"                         ,        0,      4,      577,    "RO",   0,      0,      0ull,   0ull},
71875         {"CTD"                         ,        4,      1,      577,    "R/W",  0,      0,      0ull,   0ull},
71876         {"RESERVED_5_31"               ,        5,      27,     577,    "RAZ",  1,      1,      0,      0},
71877         {"RESERVED_0_31"               ,        0,      32,     578,    "RAZ",  1,      1,      0,      0},
71878         {"RESERVED_0_31"               ,        0,      32,     579,    "RAZ",  1,      1,      0,      0},
71879         {"RESERVED_0_31"               ,        0,      32,     580,    "RAZ",  1,      1,      0,      0},
71880         {"RESERVED_0_31"               ,        0,      32,     581,    "RAZ",  1,      1,      0,      0},
71881         {"PCIEEC"                      ,        0,      16,     582,    "RO",   0,      0,      1ull,   0ull},
71882         {"CV"                          ,        16,     4,      582,    "RO",   0,      0,      1ull,   0ull},
71883         {"NCO"                         ,        20,     12,     582,    "RO",   0,      0,      0ull,   0ull},
71884         {"RESERVED_0_3"                ,        0,      4,      583,    "RAZ",  1,      1,      0,      0},
71885         {"DLPES"                       ,        4,      1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71886         {"SDES"                        ,        5,      1,      583,    "RO",   0,      0,      0ull,   0ull},
71887         {"RESERVED_6_11"               ,        6,      6,      583,    "RAZ",  1,      1,      0,      0},
71888         {"PTLPS"                       ,        12,     1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71889         {"FCPES"                       ,        13,     1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71890         {"CTS"                         ,        14,     1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71891         {"CAS"                         ,        15,     1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71892         {"UCS"                         ,        16,     1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71893         {"ROS"                         ,        17,     1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71894         {"MTLPS"                       ,        18,     1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71895         {"ECRCES"                      ,        19,     1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71896         {"URES"                        ,        20,     1,      583,    "R/W1C",        0,      0,      0ull,   0ull},
71897         {"RESERVED_21_31"              ,        21,     11,     583,    "RAZ",  1,      1,      0,      0},
71898         {"RESERVED_0_3"                ,        0,      4,      584,    "RAZ",  1,      1,      0,      0},
71899         {"DLPEM"                       ,        4,      1,      584,    "R/W",  0,      0,      0ull,   0ull},
71900         {"SDEM"                        ,        5,      1,      584,    "RO",   0,      0,      0ull,   0ull},
71901         {"RESERVED_6_11"               ,        6,      6,      584,    "RAZ",  1,      1,      0,      0},
71902         {"PTLPM"                       ,        12,     1,      584,    "R/W",  0,      0,      0ull,   0ull},
71903         {"FCPEM"                       ,        13,     1,      584,    "R/W",  0,      0,      0ull,   0ull},
71904         {"CTM"                         ,        14,     1,      584,    "R/W",  0,      0,      0ull,   0ull},
71905         {"CAM"                         ,        15,     1,      584,    "R/W",  0,      0,      0ull,   0ull},
71906         {"UCM"                         ,        16,     1,      584,    "R/W",  0,      0,      0ull,   0ull},
71907         {"ROM"                         ,        17,     1,      584,    "R/W",  0,      0,      0ull,   0ull},
71908         {"MTLPM"                       ,        18,     1,      584,    "R/W",  0,      0,      0ull,   0ull},
71909         {"ECRCEM"                      ,        19,     1,      584,    "R/W",  0,      0,      0ull,   0ull},
71910         {"UREM"                        ,        20,     1,      584,    "R/W",  0,      0,      0ull,   0ull},
71911         {"RESERVED_21_31"              ,        21,     11,     584,    "RAZ",  1,      1,      0,      0},
71912         {"RESERVED_0_3"                ,        0,      4,      585,    "RAZ",  1,      1,      0,      0},
71913         {"DLPES"                       ,        4,      1,      585,    "R/W",  0,      0,      1ull,   1ull},
71914         {"SDES"                        ,        5,      1,      585,    "RO",   0,      0,      1ull,   1ull},
71915         {"RESERVED_6_11"               ,        6,      6,      585,    "RAZ",  1,      1,      0,      0},
71916         {"PTLPS"                       ,        12,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
71917         {"FCPES"                       ,        13,     1,      585,    "R/W",  0,      0,      1ull,   1ull},
71918         {"CTS"                         ,        14,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
71919         {"CAS"                         ,        15,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
71920         {"UCS"                         ,        16,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
71921         {"ROS"                         ,        17,     1,      585,    "R/W",  0,      0,      1ull,   1ull},
71922         {"MTLPS"                       ,        18,     1,      585,    "R/W",  0,      0,      1ull,   1ull},
71923         {"ECRCES"                      ,        19,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
71924         {"URES"                        ,        20,     1,      585,    "R/W",  0,      0,      0ull,   0ull},
71925         {"RESERVED_21_31"              ,        21,     11,     585,    "RAZ",  1,      1,      0,      0},
71926         {"RES"                         ,        0,      1,      586,    "R/W1C",        0,      0,      0ull,   0ull},
71927         {"RESERVED_1_5"                ,        1,      5,      586,    "RAZ",  1,      1,      0,      0},
71928         {"BTLPS"                       ,        6,      1,      586,    "R/W1C",        0,      0,      0ull,   0ull},
71929         {"BDLLPS"                      ,        7,      1,      586,    "R/W1C",        0,      0,      0ull,   0ull},
71930         {"RNRS"                        ,        8,      1,      586,    "R/W1C",        0,      0,      0ull,   0ull},
71931         {"RESERVED_9_11"               ,        9,      3,      586,    "RAZ",  1,      1,      0,      0},
71932         {"RTTS"                        ,        12,     1,      586,    "R/W1C",        0,      0,      0ull,   0ull},
71933         {"ANFES"                       ,        13,     1,      586,    "R/W1C",        0,      0,      0ull,   0ull},
71934         {"RESERVED_14_31"              ,        14,     18,     586,    "RAZ",  1,      1,      0,      0},
71935         {"REM"                         ,        0,      1,      587,    "R/W",  0,      0,      0ull,   0ull},
71936         {"RESERVED_1_5"                ,        1,      5,      587,    "RAZ",  1,      1,      0,      0},
71937         {"BTLPM"                       ,        6,      1,      587,    "R/W",  0,      0,      0ull,   0ull},
71938         {"BDLLPM"                      ,        7,      1,      587,    "R/W",  0,      0,      0ull,   0ull},
71939         {"RNRM"                        ,        8,      1,      587,    "R/W",  0,      0,      0ull,   0ull},
71940         {"RESERVED_9_11"               ,        9,      3,      587,    "RAZ",  1,      1,      0,      0},
71941         {"RTTM"                        ,        12,     1,      587,    "R/W",  0,      0,      0ull,   0ull},
71942         {"ANFEM"                       ,        13,     1,      587,    "R/W",  0,      0,      1ull,   1ull},
71943         {"RESERVED_14_31"              ,        14,     18,     587,    "RAZ",  1,      1,      0,      0},
71944         {"FEP"                         ,        0,      5,      588,    "RO",   0,      0,      0ull,   0ull},
71945         {"GC"                          ,        5,      1,      588,    "RO",   0,      0,      1ull,   1ull},
71946         {"GE"                          ,        6,      1,      588,    "R/W",  0,      0,      0ull,   0ull},
71947         {"CC"                          ,        7,      1,      588,    "RO",   0,      0,      1ull,   1ull},
71948         {"CE"                          ,        8,      1,      588,    "R/W",  0,      0,      0ull,   0ull},
71949         {"RESERVED_9_31"               ,        9,      23,     588,    "RAZ",  1,      1,      0,      0},
71950         {"DWORD1"                      ,        0,      32,     589,    "RO",   0,      0,      0ull,   0ull},
71951         {"DWORD2"                      ,        0,      32,     590,    "RO",   0,      0,      0ull,   0ull},
71952         {"DWORD3"                      ,        0,      32,     591,    "RO",   0,      0,      0ull,   0ull},
71953         {"DWORD4"                      ,        0,      32,     592,    "RO",   0,      0,      0ull,   0ull},
71954         {"RTLTL"                       ,        0,      16,     593,    "R/W",  0,      0,      4143ull,        4143ull},
71955         {"RTL"                         ,        16,     16,     593,    "R/W",  0,      0,      12429ull,       12429ull},
71956         {"OMR"                         ,        0,      32,     594,    "R/W",  0,      1,      4294967295ull,  0},
71957         {"LINK_NUM"                    ,        0,      8,      595,    "RO",   0,      0,      0ull,   0ull},
71958         {"RESERVED_8_14"               ,        8,      7,      595,    "RAZ",  1,      1,      0,      0},
71959         {"FORCE_LINK"                  ,        15,     1,      595,    "R/W",  0,      0,      0ull,   0ull},
71960         {"LINK_STATE"                  ,        16,     6,      595,    "R/W",  0,      0,      0ull,   0ull},
71961         {"RESERVED_22_23"              ,        22,     2,      595,    "RAZ",  1,      1,      0,      0},
71962         {"LPEC"                        ,        24,     8,      595,    "R/W",  0,      0,      7ull,   7ull},
71963         {"ACK_FREQ"                    ,        0,      8,      596,    "R/W",  0,      0,      0ull,   0ull},
71964         {"N_FTS"                       ,        8,      8,      596,    "R/W",  0,      0,      128ull, 128ull},
71965         {"N_FTS_CC"                    ,        16,     8,      596,    "R/W",  0,      0,      128ull, 128ull},
71966         {"L0EL"                        ,        24,     3,      596,    "R/W",  0,      0,      3ull,   3ull},
71967         {"L1EL"                        ,        27,     3,      596,    "R/W",  0,      0,      3ull,   3ull},
71968         {"RESERVED_30_31"              ,        30,     2,      596,    "RAZ",  1,      1,      0,      0},
71969         {"OMR"                         ,        0,      1,      597,    "R/W",  0,      0,      0ull,   0ull},
71970         {"SD"                          ,        1,      1,      597,    "R/W",  0,      0,      0ull,   0ull},
71971         {"LE"                          ,        2,      1,      597,    "R/W",  0,      0,      0ull,   0ull},
71972         {"RA"                          ,        3,      1,      597,    "R/W",  0,      0,      0ull,   0ull},
71973         {"RESERVED_4_4"                ,        4,      1,      597,    "RAZ",  1,      1,      0,      0},
71974         {"DLLLE"                       ,        5,      1,      597,    "R/W",  0,      0,      1ull,   1ull},
71975         {"RESERVED_6_6"                ,        6,      1,      597,    "RAZ",  1,      1,      0,      0},
71976         {"FLM"                         ,        7,      1,      597,    "R/W",  0,      0,      0ull,   0ull},
71977         {"RESERVED_8_15"               ,        8,      8,      597,    "RO",   0,      0,      1ull,   1ull},
71978         {"LME"                         ,        16,     6,      597,    "R/W",  0,      0,      7ull,   7ull},
71979         {"RESERVED_22_24"              ,        22,     3,      597,    "RAZ",  1,      1,      0,      0},
71980         {"ECCRC"                       ,        25,     1,      597,    "R/W",  0,      0,      0ull,   0ull},
71981         {"RESERVED_26_31"              ,        26,     6,      597,    "RAZ",  1,      1,      0,      0},
71982         {"ILST"                        ,        0,      24,     598,    "R/W",  0,      0,      0ull,   0ull},
71983         {"FCD"                         ,        24,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
71984         {"ACK_NAK"                     ,        25,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
71985         {"RESERVED_26_30"              ,        26,     5,      598,    "RAZ",  1,      1,      0,      0},
71986         {"DLLD"                        ,        31,     1,      598,    "R/W",  0,      0,      0ull,   0ull},
71987         {"NTSS"                        ,        0,      4,      599,    "R/W",  0,      0,      10ull,  10ull},
71988         {"RESERVED_4_7"                ,        4,      4,      599,    "RO",   1,      1,      0,      0},
71989         {"NSKPS"                       ,        8,      3,      599,    "R/W",  0,      0,      3ull,   3ull},
71990         {"RESERVED_11_13"              ,        11,     3,      599,    "RAZ",  1,      1,      0,      0},
71991         {"TMRT"                        ,        14,     5,      599,    "R/W",  0,      0,      8ull,   8ull},
71992         {"TMANLT"                      ,        19,     5,      599,    "R/W",  0,      0,      0ull,   0ull},
71993         {"TMFCWT"                      ,        24,     5,      599,    "R/W",  0,      0,      0ull,   0ull},
71994         {"RESERVED_29_31"              ,        29,     3,      599,    "RO",   1,      1,      0,      0},
71995         {"SKPIV"                       ,        0,      11,     600,    "R/W",  0,      0,      1280ull,        1280ull},
71996         {"RESERVED_11_14"              ,        11,     4,      600,    "RAZ",  1,      1,      0,      0},
71997         {"DFCWT"                       ,        15,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
71998         {"M_FUN"                       ,        16,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
71999         {"M_POIS_FILT"                 ,        17,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72000         {"M_BAR_MATCH"                 ,        18,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72001         {"M_CFG1_FILT"                 ,        19,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72002         {"M_LK_FILT"                   ,        20,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72003         {"M_CPL_TAG_ERR"               ,        21,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72004         {"M_CPL_RID_ERR"               ,        22,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72005         {"M_CPL_FUN_ERR"               ,        23,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72006         {"M_CPL_TC_ERR"                ,        24,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72007         {"M_CPL_ATTR_ERR"              ,        25,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72008         {"M_CPL_LEN_ERR"               ,        26,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72009         {"M_ECRC_FILT"                 ,        27,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72010         {"M_CPL_ECRC_FILT"             ,        28,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72011         {"MSG_CTRL"                    ,        29,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72012         {"M_IO_FILT"                   ,        30,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72013         {"M_CFG0_FILT"                 ,        31,     1,      600,    "R/W",  0,      0,      0ull,   0ull},
72014         {"M_VEND0_DRP"                 ,        0,      1,      601,    "R/W",  0,      0,      0ull,   0ull},
72015         {"M_VEND1_DRP"                 ,        1,      1,      601,    "R/W",  0,      0,      0ull,   0ull},
72016         {"RESERVED_2_31"               ,        2,      30,     601,    "RAZ",  1,      1,      0,      0},
72017         {"DBG_INFO_L32"                ,        0,      32,     602,    "RO",   0,      0,      0ull,   0ull},
72018         {"DBG_INFO_U32"                ,        0,      32,     603,    "RO",   0,      0,      0ull,   0ull},
72019         {"TPDFCC"                      ,        0,      12,     604,    "RO",   0,      0,      0ull,   0ull},
72020         {"TPHFCC"                      ,        12,     8,      604,    "RO",   0,      0,      0ull,   0ull},
72021         {"RESERVED_20_31"              ,        20,     12,     604,    "RAZ",  1,      1,      0,      0},
72022         {"TCDFCC"                      ,        0,      12,     605,    "RO",   0,      0,      0ull,   0ull},
72023         {"TCHFCC"                      ,        12,     8,      605,    "RO",   0,      0,      0ull,   0ull},
72024         {"RESERVED_20_31"              ,        20,     12,     605,    "RAZ",  1,      1,      0,      0},
72025         {"TCDFCC"                      ,        0,      12,     606,    "RO",   0,      0,      0ull,   0ull},
72026         {"TCHFCC"                      ,        12,     8,      606,    "RO",   0,      0,      0ull,   0ull},
72027         {"RESERVED_20_31"              ,        20,     12,     606,    "RAZ",  1,      1,      0,      0},
72028         {"RTLPFCCNR"                   ,        0,      1,      607,    "RO",   0,      0,      0ull,   0ull},
72029         {"TRBNE"                       ,        1,      1,      607,    "RO",   0,      0,      0ull,   0ull},
72030         {"RQNE"                        ,        2,      1,      607,    "RO",   0,      0,      0ull,   0ull},
72031         {"RESERVED_3_31"               ,        3,      29,     607,    "RAZ",  1,      1,      0,      0},
72032         {"WRR_VC0"                     ,        0,      8,      608,    "RO",   0,      0,      15ull,  15ull},
72033         {"WRR_VC1"                     ,        8,      8,      608,    "RO",   0,      0,      0ull,   0ull},
72034         {"WRR_VC2"                     ,        16,     8,      608,    "RO",   0,      0,      0ull,   0ull},
72035         {"WRR_VC3"                     ,        24,     8,      608,    "RO",   0,      0,      0ull,   0ull},
72036         {"WRR_VC4"                     ,        0,      8,      609,    "RO",   0,      0,      0ull,   0ull},
72037         {"WRR_VC5"                     ,        8,      8,      609,    "RO",   0,      0,      0ull,   0ull},
72038         {"WRR_VC6"                     ,        16,     8,      609,    "RO",   0,      0,      0ull,   0ull},
72039         {"WRR_VC7"                     ,        24,     8,      609,    "RO",   0,      0,      0ull,   0ull},
72040         {"DATA_CREDITS"                ,        0,      12,     610,    "RO/WRSL",      0,      0,      128ull, 128ull},
72041         {"HEADER_CREDITS"              ,        12,     8,      610,    "RO/WRSL",      0,      0,      35ull,  35ull},
72042         {"RESERVED_20_20"              ,        20,     1,      610,    "RAZ",  1,      1,      0,      0},
72043         {"QUEUE_MODE"                  ,        21,     3,      610,    "RO/WRSL",      0,      0,      2ull,   2ull},
72044         {"RESERVED_24_29"              ,        24,     6,      610,    "RAZ",  1,      1,      0,      0},
72045         {"TYPE_ORDERING"               ,        30,     1,      610,    "RO/WRSL",      0,      0,      1ull,   1ull},
72046         {"RX_QUEUE_ORDER"              ,        31,     1,      610,    "RO/WRSL",      0,      0,      0ull,   0ull},
72047         {"DATA_CREDITS"                ,        0,      12,     611,    "RO/WRSL",      0,      0,      4ull,   4ull},
72048         {"HEADER_CREDITS"              ,        12,     8,      611,    "RO/WRSL",      0,      0,      8ull,   8ull},
72049         {"RESERVED_20_20"              ,        20,     1,      611,    "RAZ",  1,      1,      0,      0},
72050         {"QUEUE_MODE"                  ,        21,     3,      611,    "RO/WRSL",      0,      0,      2ull,   2ull},
72051         {"RESERVED_24_31"              ,        24,     8,      611,    "RAZ",  1,      1,      0,      0},
72052         {"DATA_CREDITS"                ,        0,      12,     612,    "RO/WRSL",      0,      0,      0ull,   0ull},
72053         {"HEADER_CREDITS"              ,        12,     8,      612,    "RO/WRSL",      0,      0,      0ull,   0ull},
72054         {"RESERVED_20_20"              ,        20,     1,      612,    "RAZ",  1,      1,      0,      0},
72055         {"QUEUE_MODE"                  ,        21,     3,      612,    "RO/WRSL",      0,      0,      2ull,   2ull},
72056         {"RESERVED_24_31"              ,        24,     8,      612,    "RAZ",  1,      1,      0,      0},
72057         {"DATA_DEPTH"                  ,        0,      14,     613,    "RO/WRSL",      0,      0,      331ull, 331ull},
72058         {"RESERVED_14_15"              ,        14,     2,      613,    "RAZ",  1,      1,      0,      0},
72059         {"HEADER_DEPTH"                ,        16,     10,     613,    "RO/WRSL",      0,      0,      41ull,  41ull},
72060         {"RESERVED_26_31"              ,        26,     6,      613,    "RAZ",  1,      1,      0,      0},
72061         {"DATA_DEPTH"                  ,        0,      14,     614,    "RO/WRSL",      0,      0,      56ull,  56ull},
72062         {"RESERVED_14_15"              ,        14,     2,      614,    "RAZ",  1,      1,      0,      0},
72063         {"HEADER_DEPTH"                ,        16,     10,     614,    "RO/WRSL",      0,      0,      14ull,  14ull},
72064         {"RESERVED_26_31"              ,        26,     6,      614,    "RAZ",  1,      1,      0,      0},
72065         {"DATA_DEPTH"                  ,        0,      14,     615,    "RO/WRSL",      0,      0,      360ull, 360ull},
72066         {"RESERVED_14_15"              ,        14,     2,      615,    "RAZ",  1,      1,      0,      0},
72067         {"HEADER_DEPTH"                ,        16,     10,     615,    "RO/WRSL",      0,      0,      70ull,  70ull},
72068         {"RESERVED_26_31"              ,        26,     6,      615,    "RAZ",  1,      1,      0,      0},
72069         {"PHY_STAT"                    ,        0,      32,     616,    "RO",   0,      0,      0ull,   0ull},
72070         {"PHY_CTRL"                    ,        0,      32,     617,    "R/W",  0,      0,      0ull,   0ull},
72071         {"VENDID"                      ,        0,      16,     618,    "R/W",  0,      0,      6013ull,        6013ull},
72072         {"DEVID"                       ,        16,     16,     618,    "R/W",  0,      0,      128ull, 128ull},
72073         {"ISAE"                        ,        0,      1,      619,    "R/W",  0,      0,      0ull,   0ull},
72074         {"MSAE"                        ,        1,      1,      619,    "R/W",  0,      0,      0ull,   0ull},
72075         {"ME"                          ,        2,      1,      619,    "R/W",  0,      0,      0ull,   0ull},
72076         {"SCSE"                        ,        3,      1,      619,    "RO",   0,      0,      0ull,   0ull},
72077         {"MWICE"                       ,        4,      1,      619,    "RO",   0,      0,      0ull,   0ull},
72078         {"VPS"                         ,        5,      1,      619,    "RO",   0,      0,      0ull,   0ull},
72079         {"PER"                         ,        6,      1,      619,    "R/W",  0,      0,      0ull,   0ull},
72080         {"IDS_WCC"                     ,        7,      1,      619,    "RO",   0,      0,      0ull,   0ull},
72081         {"SEE"                         ,        8,      1,      619,    "R/W",  0,      0,      0ull,   0ull},
72082         {"FBBE"                        ,        9,      1,      619,    "RO",   0,      0,      0ull,   0ull},
72083         {"I_DIS"                       ,        10,     1,      619,    "R/W",  0,      0,      0ull,   0ull},
72084         {"RESERVED_11_18"              ,        11,     8,      619,    "RAZ",  1,      1,      0,      0},
72085         {"I_STAT"                      ,        19,     1,      619,    "RO",   0,      0,      0ull,   0ull},
72086         {"CL"                          ,        20,     1,      619,    "RO",   0,      0,      1ull,   1ull},
72087         {"M66"                         ,        21,     1,      619,    "RO",   0,      0,      0ull,   0ull},
72088         {"RESERVED_22_22"              ,        22,     1,      619,    "RO",   1,      1,      0,      0},
72089         {"FBB"                         ,        23,     1,      619,    "RO",   0,      0,      0ull,   0ull},
72090         {"MDPE"                        ,        24,     1,      619,    "R/W1C",        0,      0,      0ull,   0ull},
72091         {"DEVT"                        ,        25,     2,      619,    "RO",   0,      0,      0ull,   0ull},
72092         {"STA"                         ,        27,     1,      619,    "R/W1C",        0,      0,      0ull,   0ull},
72093         {"RTA"                         ,        28,     1,      619,    "R/W1C",        0,      0,      0ull,   0ull},
72094         {"RMA"                         ,        29,     1,      619,    "R/W1C",        0,      0,      0ull,   0ull},
72095         {"SSE"                         ,        30,     1,      619,    "R/W1C",        0,      0,      0ull,   0ull},
72096         {"DPE"                         ,        31,     1,      619,    "R/W1C",        0,      0,      0ull,   0ull},
72097         {"RID"                         ,        0,      8,      620,    "R/W",  0,      0,      8ull,   8ull},
72098         {"PI"                          ,        8,      8,      620,    "R/W",  0,      0,      0ull,   0ull},
72099         {"SC"                          ,        16,     8,      620,    "R/W",  0,      0,      48ull,  48ull},
72100         {"BCC"                         ,        24,     8,      620,    "R/W",  0,      0,      11ull,  11ull},
72101         {"CLS"                         ,        0,      8,      621,    "R/W",  0,      0,      0ull,   0ull},
72102         {"LT"                          ,        8,      8,      621,    "RO",   0,      0,      0ull,   0ull},
72103         {"CHF"                         ,        16,     7,      621,    "RO",   0,      0,      1ull,   1ull},
72104         {"MFD"                         ,        23,     1,      621,    "R/W",  0,      0,      0ull,   0ull},
72105         {"BIST"                        ,        24,     8,      621,    "RO",   0,      0,      0ull,   0ull},
72106         {"RESERVED_0_31"               ,        0,      32,     622,    "RO",   1,      1,      0,      0},
72107         {"RESERVED_0_31"               ,        0,      32,     623,    "RO",   1,      1,      0,      0},
72108         {"PBNUM"                       ,        0,      8,      624,    "R/W",  0,      0,      0ull,   0ull},
72109         {"SBNUM"                       ,        8,      8,      624,    "R/W",  0,      0,      0ull,   0ull},
72110         {"SUBBNUM"                     ,        16,     8,      624,    "R/W",  0,      0,      0ull,   0ull},
72111         {"SLT"                         ,        24,     8,      624,    "RO",   0,      0,      0ull,   0ull},
72112         {"IO32A"                       ,        0,      1,      625,    "R/W",  0,      0,      1ull,   1ull},
72113         {"RESERVED_1_3"                ,        1,      3,      625,    "RAZ",  0,      0,      0ull,   0ull},
72114         {"LIO_BASE"                    ,        4,      4,      625,    "R/W",  0,      0,      0ull,   0ull},
72115         {"IO32B"                       ,        8,      1,      625,    "RO",   0,      0,      1ull,   1ull},
72116         {"RESERVED_9_11"               ,        9,      3,      625,    "RAZ",  0,      0,      0ull,   0ull},
72117         {"LIO_LIMI"                    ,        12,     4,      625,    "R/W",  0,      0,      0ull,   0ull},
72118         {"RESERVED_16_20"              ,        16,     5,      625,    "RAZ",  1,      1,      0,      0},
72119         {"M66"                         ,        21,     1,      625,    "RO",   0,      0,      0ull,   0ull},
72120         {"RESERVED_22_22"              ,        22,     1,      625,    "RO",   1,      1,      0,      0},
72121         {"FBB"                         ,        23,     1,      625,    "RO",   0,      0,      0ull,   0ull},
72122         {"MDPE"                        ,        24,     1,      625,    "R/W1C",        0,      0,      0ull,   0ull},
72123         {"DEVT"                        ,        25,     2,      625,    "RO",   0,      0,      0ull,   0ull},
72124         {"STA"                         ,        27,     1,      625,    "R/W1C",        0,      0,      0ull,   0ull},
72125         {"RTA"                         ,        28,     1,      625,    "R/W1C",        0,      0,      0ull,   0ull},
72126         {"RMA"                         ,        29,     1,      625,    "R/W1C",        0,      0,      0ull,   0ull},
72127         {"SSE"                         ,        30,     1,      625,    "R/W1C",        0,      0,      0ull,   0ull},
72128         {"DPE"                         ,        31,     1,      625,    "R/W1C",        0,      0,      0ull,   0ull},
72129         {"RESERVED_0_3"                ,        0,      4,      626,    "RO",   1,      1,      0,      0},
72130         {"MB_ADDR"                     ,        4,      12,     626,    "R/W",  0,      0,      0ull,   0ull},
72131         {"RESERVED_16_19"              ,        16,     4,      626,    "RO",   1,      1,      0,      0},
72132         {"ML_ADDR"                     ,        20,     12,     626,    "R/W",  0,      0,      0ull,   0ull},
72133         {"MEM64A"                      ,        0,      1,      627,    "R/W",  0,      0,      1ull,   1ull},
72134         {"RESERVED_1_3"                ,        1,      3,      627,    "RO",   1,      1,      0,      0},
72135         {"LMEM_BASE"                   ,        4,      12,     627,    "R/W",  0,      0,      0ull,   0ull},
72136         {"MEM64B"                      ,        16,     1,      627,    "RO",   0,      0,      1ull,   1ull},
72137         {"RESERVED_17_19"              ,        17,     3,      627,    "RO",   1,      1,      0,      0},
72138         {"LMEM_LIMIT"                  ,        20,     12,     627,    "R/W",  0,      0,      0ull,   0ull},
72139         {"UMEM_BASE"                   ,        0,      32,     628,    "R/W",  0,      0,      0ull,   0ull},
72140         {"UMEM_LIMIT"                  ,        0,      32,     629,    "R/W",  0,      0,      0ull,   0ull},
72141         {"UIO_BASE"                    ,        0,      16,     630,    "R/W",  0,      0,      0ull,   0ull},
72142         {"UIO_LIMIT"                   ,        16,     16,     630,    "R/W",  0,      0,      0ull,   0ull},
72143         {"CP"                          ,        0,      8,      631,    "R/W",  0,      0,      64ull,  64ull},
72144         {"RESERVED_8_31"               ,        8,      24,     631,    "RAZ",  1,      1,      0,      0},
72145         {"RESERVED_0_31"               ,        0,      32,     632,    "RAZ",  1,      1,      0,      0},
72146         {"IL"                          ,        0,      8,      633,    "R/W",  0,      0,      255ull, 255ull},
72147         {"INTA"                        ,        8,      8,      633,    "R/W",  0,      0,      1ull,   1ull},
72148         {"PERE"                        ,        16,     1,      633,    "R/W",  0,      0,      0ull,   0ull},
72149         {"SEE"                         ,        17,     1,      633,    "R/W",  0,      0,      0ull,   0ull},
72150         {"ISAE"                        ,        18,     1,      633,    "R/W",  0,      0,      0ull,   0ull},
72151         {"VGAE"                        ,        19,     1,      633,    "R/W",  0,      0,      0ull,   0ull},
72152         {"VGA16D"                      ,        20,     1,      633,    "R/W",  0,      0,      0ull,   0ull},
72153         {"MAM"                         ,        21,     1,      633,    "RO",   0,      0,      0ull,   0ull},
72154         {"SBRST"                       ,        22,     1,      633,    "R/W",  0,      0,      0ull,   0ull},
72155         {"FBBE"                        ,        23,     1,      633,    "RO",   0,      0,      0ull,   0ull},
72156         {"PDT"                         ,        24,     1,      633,    "RO",   0,      0,      0ull,   0ull},
72157         {"SDT"                         ,        25,     1,      633,    "RO",   0,      0,      0ull,   0ull},
72158         {"DTS"                         ,        26,     1,      633,    "RO",   0,      0,      0ull,   0ull},
72159         {"DTSEES"                      ,        27,     1,      633,    "RO",   0,      0,      0ull,   0ull},
72160         {"RESERVED_28_31"              ,        28,     4,      633,    "RO",   1,      1,      0,      0},
72161         {"PMCID"                       ,        0,      8,      634,    "RO",   0,      0,      1ull,   1ull},
72162         {"NCP"                         ,        8,      8,      634,    "R/W",  0,      0,      80ull,  80ull},
72163         {"PMSV"                        ,        16,     3,      634,    "R/W",  0,      0,      3ull,   3ull},
72164         {"PME_CLOCK"                   ,        19,     1,      634,    "RO",   0,      0,      0ull,   0ull},
72165         {"RESERVED_20_20"              ,        20,     1,      634,    "RAZ",  1,      1,      0,      0},
72166         {"DSI"                         ,        21,     1,      634,    "R/W",  0,      0,      0ull,   0ull},
72167         {"AUXC"                        ,        22,     3,      634,    "R/W",  0,      0,      0ull,   0ull},
72168         {"D1S"                         ,        25,     1,      634,    "R/W",  0,      0,      0ull,   0ull},
72169         {"D2S"                         ,        26,     1,      634,    "R/W",  0,      0,      0ull,   0ull},
72170         {"PMES"                        ,        27,     5,      634,    "R/W",  0,      0,      0ull,   0ull},
72171         {"PS"                          ,        0,      2,      635,    "R/W",  0,      0,      0ull,   0ull},
72172         {"RESERVED_2_2"                ,        2,      1,      635,    "RAZ",  1,      1,      0,      0},
72173         {"NSR"                         ,        3,      1,      635,    "R/W",  0,      0,      0ull,   0ull},
72174         {"RESERVED_4_7"                ,        4,      4,      635,    "RAZ",  1,      1,      0,      0},
72175         {"PMEENS"                      ,        8,      1,      635,    "R/W",  0,      0,      0ull,   0ull},
72176         {"PMDS"                        ,        9,      4,      635,    "RO",   0,      0,      0ull,   0ull},
72177         {"PMEDSIA"                     ,        13,     2,      635,    "RO",   0,      0,      0ull,   0ull},
72178         {"PMESS"                       ,        15,     1,      635,    "R/W1C",        0,      0,      0ull,   0ull},
72179         {"RESERVED_16_21"              ,        16,     6,      635,    "RAZ",  1,      1,      0,      0},
72180         {"BD3H"                        ,        22,     1,      635,    "RO",   0,      0,      0ull,   0ull},
72181         {"BPCCEE"                      ,        23,     1,      635,    "RO",   0,      0,      0ull,   0ull},
72182         {"PMDIA"                       ,        24,     8,      635,    "RO",   0,      0,      0ull,   0ull},
72183         {"MSICID"                      ,        0,      8,      636,    "RO",   0,      0,      5ull,   5ull},
72184         {"NCP"                         ,        8,      8,      636,    "R/W",  0,      0,      112ull, 112ull},
72185         {"MSIEN"                       ,        16,     1,      636,    "R/W",  0,      0,      0ull,   0ull},
72186         {"MMC"                         ,        17,     3,      636,    "R/W",  0,      0,      0ull,   0ull},
72187         {"MME"                         ,        20,     3,      636,    "R/W",  0,      0,      0ull,   0ull},
72188         {"M64"                         ,        23,     1,      636,    "R/W",  0,      0,      1ull,   1ull},
72189         {"RESERVED_24_31"              ,        24,     8,      636,    "RAZ",  1,      1,      0,      0},
72190         {"RESERVED_0_1"                ,        0,      2,      637,    "RAZ",  1,      1,      0,      0},
72191         {"LMSI"                        ,        2,      30,     637,    "R/W",  0,      0,      0ull,   0ull},
72192         {"UMSI"                        ,        0,      32,     638,    "R/W",  0,      0,      0ull,   0ull},
72193         {"MSIMD"                       ,        0,      16,     639,    "R/W",  0,      0,      0ull,   0ull},
72194         {"RESERVED_16_31"              ,        16,     16,     639,    "RAZ",  1,      1,      0,      0},
72195         {"PCIEID"                      ,        0,      8,      640,    "RO",   0,      0,      16ull,  16ull},
72196         {"NCP"                         ,        8,      8,      640,    "R/W",  0,      0,      0ull,   0ull},
72197         {"PCIECV"                      ,        16,     4,      640,    "RO",   0,      0,      2ull,   2ull},
72198         {"DPT"                         ,        20,     4,      640,    "RO",   0,      0,      4ull,   4ull},
72199         {"SI"                          ,        24,     1,      640,    "R/W",  0,      0,      0ull,   0ull},
72200         {"IMN"                         ,        25,     5,      640,    "R/W",  0,      0,      0ull,   0ull},
72201         {"RESERVED_30_31"              ,        30,     2,      640,    "RAZ",  1,      1,      0,      0},
72202         {"MPSS"                        ,        0,      3,      641,    "R/W",  0,      0,      1ull,   1ull},
72203         {"PFS"                         ,        3,      2,      641,    "R/W",  0,      0,      0ull,   0ull},
72204         {"ETFS"                        ,        5,      1,      641,    "R/W",  0,      0,      0ull,   0ull},
72205         {"EL0AL"                       ,        6,      3,      641,    "R/W",  0,      0,      0ull,   0ull},
72206         {"EL1AL"                       ,        9,      3,      641,    "R/W",  0,      0,      0ull,   0ull},
72207         {"RESERVED_12_14"              ,        12,     3,      641,    "RAZ",  1,      1,      0,      0},
72208         {"RBER"                        ,        15,     1,      641,    "R/W",  0,      0,      1ull,   1ull},
72209         {"RESERVED_16_17"              ,        16,     2,      641,    "RAZ",  1,      1,      0,      0},
72210         {"CSPLV"                       ,        18,     8,      641,    "RO",   0,      0,      0ull,   0ull},
72211         {"CSPLS"                       ,        26,     2,      641,    "RO",   0,      0,      0ull,   0ull},
72212         {"RESERVED_28_31"              ,        28,     4,      641,    "RAZ",  1,      1,      0,      0},
72213         {"CE_EN"                       ,        0,      1,      642,    "R/W",  0,      0,      0ull,   0ull},
72214         {"NFE_EN"                      ,        1,      1,      642,    "R/W",  0,      0,      0ull,   0ull},
72215         {"FE_EN"                       ,        2,      1,      642,    "R/W",  0,      0,      0ull,   0ull},
72216         {"UR_EN"                       ,        3,      1,      642,    "R/W",  0,      0,      0ull,   0ull},
72217         {"RO_EN"                       ,        4,      1,      642,    "R/W",  0,      0,      1ull,   1ull},
72218         {"MPS"                         ,        5,      3,      642,    "R/W",  0,      0,      0ull,   0ull},
72219         {"ETF_EN"                      ,        8,      1,      642,    "R/W",  0,      0,      0ull,   0ull},
72220         {"PF_EN"                       ,        9,      1,      642,    "R/W",  0,      0,      0ull,   0ull},
72221         {"AP_EN"                       ,        10,     1,      642,    "R/W",  0,      0,      0ull,   0ull},
72222         {"NS_EN"                       ,        11,     1,      642,    "R/W",  0,      0,      1ull,   1ull},
72223         {"MRRS"                        ,        12,     3,      642,    "R/W",  0,      0,      2ull,   2ull},
72224         {"RESERVED_15_15"              ,        15,     1,      642,    "RAZ",  1,      1,      0,      0},
72225         {"CE_D"                        ,        16,     1,      642,    "R/W1C",        0,      0,      0ull,   0ull},
72226         {"NFE_D"                       ,        17,     1,      642,    "R/W1C",        0,      0,      0ull,   0ull},
72227         {"FE_D"                        ,        18,     1,      642,    "R/W1C",        0,      0,      0ull,   0ull},
72228         {"UR_D"                        ,        19,     1,      642,    "R/W1C",        0,      0,      0ull,   0ull},
72229         {"AP_D"                        ,        20,     1,      642,    "RO",   0,      0,      0ull,   0ull},
72230         {"TP"                          ,        21,     1,      642,    "RO",   0,      0,      0ull,   0ull},
72231         {"RESERVED_22_31"              ,        22,     10,     642,    "RAZ",  1,      1,      0,      0},
72232         {"MLS"                         ,        0,      4,      643,    "R/W",  0,      0,      1ull,   1ull},
72233         {"MLW"                         ,        4,      6,      643,    "R/W",  0,      0,      8ull,   8ull},
72234         {"ASLPMS"                      ,        10,     2,      643,    "R/W",  0,      0,      3ull,   3ull},
72235         {"L0EL"                        ,        12,     3,      643,    "R/W",  0,      0,      6ull,   6ull},
72236         {"L1EL"                        ,        15,     3,      643,    "R/W",  0,      0,      6ull,   6ull},
72237         {"CPM"                         ,        18,     1,      643,    "R/W",  0,      0,      0ull,   0ull},
72238         {"SDERC"                       ,        19,     1,      643,    "RO",   0,      0,      0ull,   0ull},
72239         {"DLLARC"                      ,        20,     1,      643,    "RO",   0,      0,      1ull,   1ull},
72240         {"LBNC"                        ,        21,     1,      643,    "RO",   0,      0,      1ull,   1ull},
72241         {"RESERVED_22_23"              ,        22,     2,      643,    "RAZ",  1,      1,      0,      0},
72242         {"PNUM"                        ,        24,     8,      643,    "R/W",  0,      0,      0ull,   0ull},
72243         {"ASLPC"                       ,        0,      2,      644,    "R/W",  0,      0,      0ull,   0ull},
72244         {"RESERVED_2_2"                ,        2,      1,      644,    "RAZ",  1,      1,      0,      0},
72245         {"RCB"                         ,        3,      1,      644,    "R/W",  0,      0,      1ull,   1ull},
72246         {"LD"                          ,        4,      1,      644,    "R/W",  0,      0,      0ull,   0ull},
72247         {"RL"                          ,        5,      1,      644,    "R/W",  0,      0,      0ull,   0ull},
72248         {"CCC"                         ,        6,      1,      644,    "R/W",  0,      0,      0ull,   0ull},
72249         {"ES"                          ,        7,      1,      644,    "R/W",  0,      0,      0ull,   0ull},
72250         {"ECPM"                        ,        8,      1,      644,    "R/W",  0,      0,      0ull,   0ull},
72251         {"HAWD"                        ,        9,      1,      644,    "R/W",  0,      0,      0ull,   0ull},
72252         {"LBM_INT_ENB"                 ,        10,     1,      644,    "R/W",  0,      0,      0ull,   0ull},
72253         {"LAB_INT_ENB"                 ,        11,     1,      644,    "R/W",  0,      0,      0ull,   0ull},
72254         {"RESERVED_12_15"              ,        12,     4,      644,    "RAZ",  1,      1,      0,      0},
72255         {"LS"                          ,        16,     4,      644,    "RO",   0,      0,      1ull,   1ull},
72256         {"NLW"                         ,        20,     6,      644,    "RO",   0,      0,      0ull,   0ull},
72257         {"RESERVED_26_26"              ,        26,     1,      644,    "RAZ",  1,      1,      0,      0},
72258         {"LT"                          ,        27,     1,      644,    "RO",   0,      0,      0ull,   0ull},
72259         {"SCC"                         ,        28,     1,      644,    "R/W",  0,      0,      1ull,   0ull},
72260         {"DLLA"                        ,        29,     1,      644,    "RO",   0,      0,      0ull,   1ull},
72261         {"LBM"                         ,        30,     1,      644,    "R/W1C",        0,      0,      0ull,   0ull},
72262         {"LAB"                         ,        31,     1,      644,    "R/W1C",        0,      0,      0ull,   0ull},
72263         {"ABP"                         ,        0,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
72264         {"PCP"                         ,        1,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
72265         {"MRLSP"                       ,        2,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
72266         {"AIP"                         ,        3,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
72267         {"PIP"                         ,        4,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
72268         {"HP_S"                        ,        5,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
72269         {"HP_C"                        ,        6,      1,      645,    "R/W",  0,      0,      0ull,   0ull},
72270         {"SP_LV"                       ,        7,      8,      645,    "R/W",  0,      0,      0ull,   0ull},
72271         {"SP_LS"                       ,        15,     2,      645,    "R/W",  0,      0,      0ull,   0ull},
72272         {"EMIP"                        ,        17,     1,      645,    "R/W",  0,      0,      0ull,   0ull},
72273         {"NCCS"                        ,        18,     1,      645,    "R/W",  0,      0,      0ull,   0ull},
72274         {"PS_NUM"                      ,        19,     13,     645,    "R/W",  0,      0,      0ull,   0ull},
72275         {"ABP_EN"                      ,        0,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
72276         {"PF_EN"                       ,        1,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
72277         {"MRLS_EN"                     ,        2,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
72278         {"PD_EN"                       ,        3,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
72279         {"CCINT_EN"                    ,        4,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
72280         {"HPINT_EN"                    ,        5,      1,      646,    "R/W",  0,      0,      0ull,   0ull},
72281         {"AIC"                         ,        6,      2,      646,    "R/W",  0,      0,      3ull,   3ull},
72282         {"PIC"                         ,        8,      2,      646,    "R/W",  0,      0,      3ull,   3ull},
72283         {"PCC"                         ,        10,     1,      646,    "R/W",  0,      0,      0ull,   0ull},
72284         {"EMIC"                        ,        11,     1,      646,    "R/W",  0,      0,      0ull,   0ull},
72285         {"DLLS_EN"                     ,        12,     1,      646,    "R/W",  0,      0,      0ull,   0ull},
72286         {"RESERVED_13_15"              ,        13,     3,      646,    "RAZ",  1,      1,      0,      0},
72287         {"ABP_D"                       ,        16,     1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
72288         {"PF_D"                        ,        17,     1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
72289         {"MRLS_C"                      ,        18,     1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
72290         {"PD_C"                        ,        19,     1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
72291         {"CCINT_D"                     ,        20,     1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
72292         {"MRLSS"                       ,        21,     1,      646,    "RO",   0,      0,      0ull,   0ull},
72293         {"PDS"                         ,        22,     1,      646,    "RO",   0,      0,      1ull,   1ull},
72294         {"EMIS"                        ,        23,     1,      646,    "RO",   0,      0,      0ull,   0ull},
72295         {"DLLS_C"                      ,        24,     1,      646,    "R/W1C",        0,      0,      0ull,   0ull},
72296         {"RESERVED_25_31"              ,        25,     7,      646,    "RAZ",  1,      1,      0,      0},
72297         {"SECEE"                       ,        0,      1,      647,    "R/W",  0,      0,      0ull,   0ull},
72298         {"SENFEE"                      ,        1,      1,      647,    "R/W",  0,      0,      0ull,   0ull},
72299         {"SEFEE"                       ,        2,      1,      647,    "R/W",  0,      0,      0ull,   0ull},
72300         {"PMEIE"                       ,        3,      1,      647,    "R/W",  0,      0,      0ull,   0ull},
72301         {"CRSSVE"                      ,        4,      1,      647,    "RO",   0,      0,      0ull,   0ull},
72302         {"RESERVED_5_15"               ,        5,      11,     647,    "RAZ",  1,      1,      0,      0},
72303         {"CRSSV"                       ,        16,     1,      647,    "RO",   0,      0,      0ull,   0ull},
72304         {"RESERVED_17_31"              ,        17,     15,     647,    "RAZ",  1,      1,      0,      0},
72305         {"PME_RID"                     ,        0,      16,     648,    "RO",   0,      0,      0ull,   0ull},
72306         {"PME_STAT"                    ,        16,     1,      648,    "R/W1C",        0,      0,      0ull,   0ull},
72307         {"PME_PEND"                    ,        17,     1,      648,    "RO",   0,      0,      0ull,   0ull},
72308         {"RESERVED_18_31"              ,        18,     14,     648,    "RAZ",  0,      0,      0ull,   0ull},
72309         {"CTRS"                        ,        0,      4,      649,    "RO",   0,      0,      0ull,   0ull},
72310         {"CTDS"                        ,        4,      1,      649,    "RO",   0,      0,      1ull,   1ull},
72311         {"RESERVED_5_31"               ,        5,      27,     649,    "RAZ",  1,      1,      0,      0},
72312         {"CTV"                         ,        0,      4,      650,    "RO",   0,      0,      0ull,   0ull},
72313         {"CTD"                         ,        4,      1,      650,    "R/W",  0,      0,      0ull,   0ull},
72314         {"RESERVED_5_31"               ,        5,      27,     650,    "RAZ",  1,      1,      0,      0},
72315         {"RESERVED_0_31"               ,        0,      32,     651,    "RAZ",  1,      1,      0,      0},
72316         {"RESERVED_0_31"               ,        0,      32,     652,    "RAZ",  1,      1,      0,      0},
72317         {"RESERVED_0_31"               ,        0,      32,     653,    "RAZ",  1,      1,      0,      0},
72318         {"RESERVED_0_31"               ,        0,      32,     654,    "RAZ",  1,      1,      0,      0},
72319         {"PCIEEC"                      ,        0,      16,     655,    "RO",   0,      0,      1ull,   1ull},
72320         {"CV"                          ,        16,     4,      655,    "RO",   0,      0,      1ull,   1ull},
72321         {"NCO"                         ,        20,     12,     655,    "RO",   0,      0,      0ull,   0ull},
72322         {"RESERVED_0_3"                ,        0,      4,      656,    "RAZ",  1,      1,      0,      0},
72323         {"DLPES"                       ,        4,      1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72324         {"SDES"                        ,        5,      1,      656,    "RO",   0,      0,      0ull,   0ull},
72325         {"RESERVED_6_11"               ,        6,      6,      656,    "RAZ",  1,      1,      0,      0},
72326         {"PTLPS"                       ,        12,     1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72327         {"FCPES"                       ,        13,     1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72328         {"CTS"                         ,        14,     1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72329         {"CAS"                         ,        15,     1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72330         {"UCS"                         ,        16,     1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72331         {"ROS"                         ,        17,     1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72332         {"MTLPS"                       ,        18,     1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72333         {"ECRCES"                      ,        19,     1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72334         {"URES"                        ,        20,     1,      656,    "R/W1C",        0,      0,      0ull,   0ull},
72335         {"RESERVED_21_31"              ,        21,     11,     656,    "RAZ",  1,      1,      0,      0},
72336         {"RESERVED_0_3"                ,        0,      4,      657,    "RAZ",  1,      1,      0,      0},
72337         {"DLPEM"                       ,        4,      1,      657,    "R/W",  0,      0,      0ull,   0ull},
72338         {"SDEM"                        ,        5,      1,      657,    "RO",   0,      0,      0ull,   0ull},
72339         {"RESERVED_6_11"               ,        6,      6,      657,    "RAZ",  1,      1,      0,      0},
72340         {"PTLPM"                       ,        12,     1,      657,    "R/W",  0,      0,      0ull,   0ull},
72341         {"FCPEM"                       ,        13,     1,      657,    "R/W",  0,      0,      0ull,   0ull},
72342         {"CTM"                         ,        14,     1,      657,    "R/W",  0,      0,      0ull,   0ull},
72343         {"CAM"                         ,        15,     1,      657,    "R/W",  0,      0,      0ull,   0ull},
72344         {"UCM"                         ,        16,     1,      657,    "R/W",  0,      0,      0ull,   0ull},
72345         {"ROM"                         ,        17,     1,      657,    "R/W",  0,      0,      0ull,   0ull},
72346         {"MTLPM"                       ,        18,     1,      657,    "R/W",  0,      0,      0ull,   0ull},
72347         {"ECRCEM"                      ,        19,     1,      657,    "R/W",  0,      0,      0ull,   0ull},
72348         {"UREM"                        ,        20,     1,      657,    "R/W",  0,      0,      0ull,   0ull},
72349         {"RESERVED_21_31"              ,        21,     11,     657,    "RAZ",  1,      1,      0,      0},
72350         {"RESERVED_0_3"                ,        0,      4,      658,    "RAZ",  1,      1,      0,      0},
72351         {"DLPES"                       ,        4,      1,      658,    "R/W",  0,      0,      1ull,   1ull},
72352         {"SDES"                        ,        5,      1,      658,    "RO",   0,      0,      1ull,   1ull},
72353         {"RESERVED_6_11"               ,        6,      6,      658,    "RAZ",  1,      1,      0,      0},
72354         {"PTLPS"                       ,        12,     1,      658,    "R/W",  0,      0,      0ull,   0ull},
72355         {"FCPES"                       ,        13,     1,      658,    "R/W",  0,      0,      1ull,   1ull},
72356         {"CTS"                         ,        14,     1,      658,    "R/W",  0,      0,      0ull,   0ull},
72357         {"CAS"                         ,        15,     1,      658,    "R/W",  0,      0,      0ull,   0ull},
72358         {"UCS"                         ,        16,     1,      658,    "R/W",  0,      0,      0ull,   0ull},
72359         {"ROS"                         ,        17,     1,      658,    "R/W",  0,      0,      1ull,   1ull},
72360         {"MTLPS"                       ,        18,     1,      658,    "R/W",  0,      0,      1ull,   1ull},
72361         {"ECRCES"                      ,        19,     1,      658,    "R/W",  0,      0,      0ull,   0ull},
72362         {"URES"                        ,        20,     1,      658,    "R/W",  0,      0,      0ull,   0ull},
72363         {"RESERVED_21_31"              ,        21,     11,     658,    "RAZ",  1,      1,      0,      0},
72364         {"RES"                         ,        0,      1,      659,    "R/W1C",        0,      0,      0ull,   0ull},
72365         {"RESERVED_1_5"                ,        1,      5,      659,    "RAZ",  1,      1,      0,      0},
72366         {"BTLPS"                       ,        6,      1,      659,    "R/W1C",        0,      0,      0ull,   0ull},
72367         {"BDLLPS"                      ,        7,      1,      659,    "R/W1C",        0,      0,      0ull,   0ull},
72368         {"RNRS"                        ,        8,      1,      659,    "R/W1C",        0,      0,      0ull,   0ull},
72369         {"RESERVED_9_11"               ,        9,      3,      659,    "RAZ",  1,      1,      0,      0},
72370         {"RTTS"                        ,        12,     1,      659,    "R/W1C",        0,      0,      0ull,   0ull},
72371         {"ANFES"                       ,        13,     1,      659,    "R/W1C",        0,      0,      0ull,   0ull},
72372         {"RESERVED_14_31"              ,        14,     18,     659,    "RAZ",  1,      1,      0,      0},
72373         {"REM"                         ,        0,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
72374         {"RESERVED_1_5"                ,        1,      5,      660,    "RAZ",  1,      1,      0,      0},
72375         {"BTLPM"                       ,        6,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
72376         {"BDLLPM"                      ,        7,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
72377         {"RNRM"                        ,        8,      1,      660,    "R/W",  0,      0,      0ull,   0ull},
72378         {"RESERVED_9_11"               ,        9,      3,      660,    "RAZ",  1,      1,      0,      0},
72379         {"RTTM"                        ,        12,     1,      660,    "R/W",  0,      0,      0ull,   0ull},
72380         {"ANFEM"                       ,        13,     1,      660,    "R/W",  0,      0,      1ull,   1ull},
72381         {"RESERVED_14_31"              ,        14,     18,     660,    "RAZ",  1,      1,      0,      0},
72382         {"FEP"                         ,        0,      5,      661,    "RO",   0,      0,      0ull,   0ull},
72383         {"GC"                          ,        5,      1,      661,    "RO",   0,      0,      1ull,   1ull},
72384         {"GE"                          ,        6,      1,      661,    "R/W",  0,      0,      0ull,   0ull},
72385         {"CC"                          ,        7,      1,      661,    "RO",   0,      0,      1ull,   1ull},
72386         {"CE"                          ,        8,      1,      661,    "R/W",  0,      0,      0ull,   0ull},
72387         {"RESERVED_9_31"               ,        9,      23,     661,    "RAZ",  1,      1,      0,      0},
72388         {"DWORD1"                      ,        0,      32,     662,    "RO",   0,      0,      0ull,   0ull},
72389         {"DWORD2"                      ,        0,      32,     663,    "RO",   0,      0,      0ull,   0ull},
72390         {"DWORD3"                      ,        0,      32,     664,    "RO",   0,      0,      0ull,   0ull},
72391         {"DWORD4"                      ,        0,      32,     665,    "RO",   0,      0,      0ull,   0ull},
72392         {"CERE"                        ,        0,      1,      666,    "R/W",  0,      0,      0ull,   0ull},
72393         {"NFERE"                       ,        1,      1,      666,    "R/W",  0,      0,      0ull,   0ull},
72394         {"FERE"                        ,        2,      1,      666,    "R/W",  0,      0,      0ull,   0ull},
72395         {"RESERVED_3_31"               ,        3,      29,     666,    "RAZ",  1,      1,      0,      0},
72396         {"ECR"                         ,        0,      1,      667,    "R/W1C",        0,      0,      0ull,   0ull},
72397         {"MULTI_ECR"                   ,        1,      1,      667,    "R/W1C",        0,      0,      0ull,   0ull},
72398         {"EFNFR"                       ,        2,      1,      667,    "R/W1C",        0,      0,      0ull,   0ull},
72399         {"MULTI_EFNFR"                 ,        3,      1,      667,    "R/W1C",        0,      0,      0ull,   0ull},
72400         {"FUF"                         ,        4,      1,      667,    "R/W1C",        0,      0,      0ull,   0ull},
72401         {"NFEMR"                       ,        5,      1,      667,    "R/W1C",        0,      0,      0ull,   0ull},
72402         {"FEMR"                        ,        6,      1,      667,    "R/W1C",        0,      0,      0ull,   0ull},
72403         {"RESERVED_7_26"               ,        7,      20,     667,    "RAZ",  1,      1,      0,      0},
72404         {"AEIMN"                       ,        27,     5,      667,    "R/W",  0,      0,      0ull,   0ull},
72405         {"ECSI"                        ,        0,      16,     668,    "RO",   0,      0,      0ull,   0ull},
72406         {"EFNFSI"                      ,        16,     16,     668,    "RO",   0,      0,      0ull,   0ull},
72407         {"RTLTL"                       ,        0,      16,     669,    "R/W",  0,      0,      4143ull,        4143ull},
72408         {"RTL"                         ,        16,     16,     669,    "R/W",  0,      0,      12429ull,       12429ull},
72409         {"OMR"                         ,        0,      32,     670,    "R/W",  0,      1,      4294967295ull,  0},
72410         {"LINK_NUM"                    ,        0,      8,      671,    "R/W",  0,      0,      4ull,   4ull},
72411         {"RESERVED_8_14"               ,        8,      7,      671,    "RAZ",  1,      1,      0,      0},
72412         {"FORCE_LINK"                  ,        15,     1,      671,    "R/W",  0,      0,      0ull,   0ull},
72413         {"LINK_STATE"                  ,        16,     6,      671,    "R/W",  0,      0,      0ull,   0ull},
72414         {"RESERVED_22_23"              ,        22,     2,      671,    "RAZ",  1,      1,      0,      0},
72415         {"LPEC"                        ,        24,     8,      671,    "RO",   0,      0,      7ull,   7ull},
72416         {"ACK_FREQ"                    ,        0,      8,      672,    "R/W",  0,      0,      0ull,   0ull},
72417         {"N_FTS"                       ,        8,      8,      672,    "R/W",  0,      0,      128ull, 128ull},
72418         {"N_FTS_CC"                    ,        16,     8,      672,    "R/W",  0,      0,      128ull, 128ull},
72419         {"L0EL"                        ,        24,     3,      672,    "R/W",  0,      0,      3ull,   3ull},
72420         {"L1EL"                        ,        27,     3,      672,    "R/W",  0,      0,      3ull,   3ull},
72421         {"RESERVED_30_31"              ,        30,     2,      672,    "RAZ",  1,      1,      0,      0},
72422         {"OMR"                         ,        0,      1,      673,    "R/W",  0,      0,      0ull,   0ull},
72423         {"SD"                          ,        1,      1,      673,    "R/W",  0,      0,      0ull,   0ull},
72424         {"LE"                          ,        2,      1,      673,    "R/W",  0,      0,      0ull,   0ull},
72425         {"RA"                          ,        3,      1,      673,    "R/W",  0,      0,      0ull,   0ull},
72426         {"RESERVED_4_4"                ,        4,      1,      673,    "RAZ",  1,      1,      0,      0},
72427         {"DLLLE"                       ,        5,      1,      673,    "R/W",  0,      0,      1ull,   1ull},
72428         {"RESERVED_6_6"                ,        6,      1,      673,    "RAZ",  1,      1,      0,      0},
72429         {"FLM"                         ,        7,      1,      673,    "R/W",  0,      0,      0ull,   0ull},
72430         {"RESERVED_8_15"               ,        8,      8,      673,    "RO",   0,      0,      1ull,   1ull},
72431         {"LME"                         ,        16,     6,      673,    "R/W",  0,      0,      15ull,  15ull},
72432         {"RESERVED_22_24"              ,        22,     3,      673,    "RAZ",  1,      1,      0,      0},
72433         {"ECCRC"                       ,        25,     1,      673,    "R/W",  0,      0,      0ull,   0ull},
72434         {"RESERVED_26_31"              ,        26,     6,      673,    "RAZ",  1,      1,      0,      0},
72435         {"ILST"                        ,        0,      24,     674,    "R/W",  0,      0,      0ull,   0ull},
72436         {"FCD"                         ,        24,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
72437         {"ACK_NAK"                     ,        25,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
72438         {"RESERVED_26_30"              ,        26,     5,      674,    "RAZ",  1,      1,      0,      0},
72439         {"DLLD"                        ,        31,     1,      674,    "R/W",  0,      0,      0ull,   0ull},
72440         {"NTSS"                        ,        0,      4,      675,    "R/W",  0,      0,      10ull,  10ull},
72441         {"RESERVED_4_7"                ,        4,      4,      675,    "RO",   1,      1,      0,      0},
72442         {"NSKPS"                       ,        8,      3,      675,    "R/W",  0,      0,      3ull,   3ull},
72443         {"RESERVED_11_13"              ,        11,     3,      675,    "RAZ",  1,      1,      0,      0},
72444         {"TMRT"                        ,        14,     5,      675,    "R/W",  0,      0,      8ull,   8ull},
72445         {"TMANLT"                      ,        19,     5,      675,    "R/W",  0,      0,      0ull,   0ull},
72446         {"TMFCWT"                      ,        24,     5,      675,    "R/W",  0,      0,      0ull,   0ull},
72447         {"RESERVED_29_31"              ,        29,     3,      675,    "RO",   1,      1,      0,      0},
72448         {"SKPIV"                       ,        0,      11,     676,    "R/W",  0,      0,      1280ull,        1280ull},
72449         {"RESERVED_11_14"              ,        11,     4,      676,    "RAZ",  1,      1,      0,      0},
72450         {"DFCWT"                       ,        15,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72451         {"M_FUN"                       ,        16,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72452         {"M_POIS_FILT"                 ,        17,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72453         {"M_BAR_MATCH"                 ,        18,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72454         {"M_CFG1_FILT"                 ,        19,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72455         {"M_LK_FILT"                   ,        20,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72456         {"M_CPL_TAG_ERR"               ,        21,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72457         {"M_CPL_RID_ERR"               ,        22,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72458         {"M_CPL_FUN_ERR"               ,        23,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72459         {"M_CPL_TC_ERR"                ,        24,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72460         {"M_CPL_ATTR_ERR"              ,        25,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72461         {"M_CPL_LEN_ERR"               ,        26,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72462         {"M_ECRC_FILT"                 ,        27,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72463         {"M_CPL_ECRC_FILT"             ,        28,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72464         {"MSG_CTRL"                    ,        29,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72465         {"M_IO_FILT"                   ,        30,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72466         {"M_CFG0_FILT"                 ,        31,     1,      676,    "R/W",  0,      0,      0ull,   0ull},
72467         {"M_VEND0_DRP"                 ,        0,      1,      677,    "R/W",  0,      0,      0ull,   0ull},
72468         {"M_VEND1_DRP"                 ,        1,      1,      677,    "R/W",  0,      0,      0ull,   0ull},
72469         {"RESERVED_2_31"               ,        2,      30,     677,    "RAZ",  1,      1,      0,      0},
72470         {"DBG_INFO_L32"                ,        0,      32,     678,    "RO",   0,      0,      0ull,   0ull},
72471         {"DBG_INFO_U32"                ,        0,      32,     679,    "RO",   0,      0,      0ull,   0ull},
72472         {"TPDFCC"                      ,        0,      12,     680,    "RO",   0,      0,      0ull,   0ull},
72473         {"TPHFCC"                      ,        12,     8,      680,    "RO",   0,      0,      0ull,   0ull},
72474         {"RESERVED_20_31"              ,        20,     12,     680,    "RAZ",  1,      1,      0,      0},
72475         {"TCDFCC"                      ,        0,      12,     681,    "RO",   0,      0,      0ull,   0ull},
72476         {"TCHFCC"                      ,        12,     8,      681,    "RO",   0,      0,      0ull,   0ull},
72477         {"RESERVED_20_31"              ,        20,     12,     681,    "RAZ",  1,      1,      0,      0},
72478         {"TCDFCC"                      ,        0,      12,     682,    "RO",   0,      0,      0ull,   0ull},
72479         {"TCHFCC"                      ,        12,     8,      682,    "RO",   0,      0,      0ull,   0ull},
72480         {"RESERVED_20_31"              ,        20,     12,     682,    "RAZ",  1,      1,      0,      0},
72481         {"RTLPFCCNR"                   ,        0,      1,      683,    "RO",   0,      0,      0ull,   0ull},
72482         {"TRBNE"                       ,        1,      1,      683,    "RO",   0,      0,      0ull,   0ull},
72483         {"RQNE"                        ,        2,      1,      683,    "RO",   0,      0,      0ull,   0ull},
72484         {"RESERVED_3_31"               ,        3,      29,     683,    "RAZ",  1,      1,      0,      0},
72485         {"WRR_VC0"                     ,        0,      8,      684,    "RO",   0,      0,      15ull,  15ull},
72486         {"WRR_VC1"                     ,        8,      8,      684,    "RO",   0,      0,      0ull,   0ull},
72487         {"WRR_VC2"                     ,        16,     8,      684,    "RO",   0,      0,      0ull,   0ull},
72488         {"WRR_VC3"                     ,        24,     8,      684,    "RO",   0,      0,      0ull,   0ull},
72489         {"WRR_VC4"                     ,        0,      8,      685,    "RO",   0,      0,      0ull,   0ull},
72490         {"WRR_VC5"                     ,        8,      8,      685,    "RO",   0,      0,      0ull,   0ull},
72491         {"WRR_VC6"                     ,        16,     8,      685,    "RO",   0,      0,      0ull,   0ull},
72492         {"WRR_VC7"                     ,        24,     8,      685,    "RO",   0,      0,      0ull,   0ull},
72493         {"DATA_CREDITS"                ,        0,      12,     686,    "R/W",  0,      0,      128ull, 128ull},
72494         {"HEADER_CREDITS"              ,        12,     8,      686,    "R/W",  0,      0,      35ull,  35ull},
72495         {"RESERVED_20_20"              ,        20,     1,      686,    "RAZ",  1,      1,      0,      0},
72496         {"QUEUE_MODE"                  ,        21,     3,      686,    "R/W",  0,      0,      2ull,   2ull},
72497         {"RESERVED_24_29"              ,        24,     6,      686,    "RAZ",  1,      1,      0,      0},
72498         {"TYPE_ORDERING"               ,        30,     1,      686,    "R/W",  0,      0,      1ull,   1ull},
72499         {"RX_QUEUE_ORDER"              ,        31,     1,      686,    "R/W",  0,      0,      0ull,   0ull},
72500         {"DATA_CREDITS"                ,        0,      12,     687,    "R/W",  0,      0,      4ull,   4ull},
72501         {"HEADER_CREDITS"              ,        12,     8,      687,    "R/W",  0,      0,      8ull,   8ull},
72502         {"RESERVED_20_20"              ,        20,     1,      687,    "RAZ",  1,      1,      0,      0},
72503         {"QUEUE_MODE"                  ,        21,     3,      687,    "R/W",  0,      0,      2ull,   2ull},
72504         {"RESERVED_24_31"              ,        24,     8,      687,    "RAZ",  1,      1,      0,      0},
72505         {"DATA_CREDITS"                ,        0,      12,     688,    "R/W",  0,      0,      128ull, 128ull},
72506         {"HEADER_CREDITS"              ,        12,     8,      688,    "R/W",  0,      0,      64ull,  64ull},
72507         {"RESERVED_20_20"              ,        20,     1,      688,    "RAZ",  1,      1,      0,      0},
72508         {"QUEUE_MODE"                  ,        21,     3,      688,    "R/W",  0,      0,      2ull,   2ull},
72509         {"RESERVED_24_31"              ,        24,     8,      688,    "RAZ",  1,      1,      0,      0},
72510         {"DATA_DEPTH"                  ,        0,      14,     689,    "R/W",  0,      0,      331ull, 331ull},
72511         {"RESERVED_14_15"              ,        14,     2,      689,    "RAZ",  1,      1,      0,      0},
72512         {"HEADER_DEPTH"                ,        16,     10,     689,    "R/W",  0,      0,      41ull,  41ull},
72513         {"RESERVED_26_31"              ,        26,     6,      689,    "RAZ",  1,      1,      0,      0},
72514         {"DATA_DEPTH"                  ,        0,      14,     690,    "R/W",  0,      0,      56ull,  56ull},
72515         {"RESERVED_14_15"              ,        14,     2,      690,    "RAZ",  1,      1,      0,      0},
72516         {"HEADER_DEPTH"                ,        16,     10,     690,    "R/W",  0,      0,      14ull,  14ull},
72517         {"RESERVED_26_31"              ,        26,     6,      690,    "RAZ",  1,      1,      0,      0},
72518         {"DATA_DEPTH"                  ,        0,      14,     691,    "R/W",  0,      0,      360ull, 360ull},
72519         {"RESERVED_14_15"              ,        14,     2,      691,    "RAZ",  1,      1,      0,      0},
72520         {"HEADER_DEPTH"                ,        16,     10,     691,    "R/W",  0,      0,      70ull,  70ull},
72521         {"RESERVED_26_31"              ,        26,     6,      691,    "RAZ",  1,      1,      0,      0},
72522         {"PHY_STAT"                    ,        0,      32,     692,    "RO",   0,      0,      0ull,   0ull},
72523         {"PHY_CTRL"                    ,        0,      32,     693,    "R/W",  0,      0,      0ull,   0ull},
72524         {"RESERVED_0_4"                ,        0,      5,      694,    "RAZ",  0,      0,      0ull,   0ull},
72525         {"FD"                          ,        5,      1,      694,    "R/W",  0,      0,      1ull,   1ull},
72526         {"HFD"                         ,        6,      1,      694,    "R/W",  0,      0,      1ull,   1ull},
72527         {"PAUSE"                       ,        7,      2,      694,    "R/W",  0,      0,      0ull,   0ull},
72528         {"RESERVED_9_11"               ,        9,      3,      694,    "RAZ",  0,      0,      0ull,   0ull},
72529         {"REM_FLT"                     ,        12,     2,      694,    "R/W",  0,      0,      0ull,   0ull},
72530         {"RESERVED_14_14"              ,        14,     1,      694,    "RAZ",  0,      0,      0ull,   0ull},
72531         {"NP"                          ,        15,     1,      694,    "RO",   0,      0,      0ull,   0ull},
72532         {"RESERVED_16_63"              ,        16,     48,     694,    "RAZ",  1,      1,      0,      0},
72533         {"RESERVED_0_11"               ,        0,      12,     695,    "RAZ",  0,      0,      0ull,   0ull},
72534         {"THOU_THD"                    ,        12,     1,      695,    "RO",   0,      0,      0ull,   0ull},
72535         {"THOU_TFD"                    ,        13,     1,      695,    "RO",   0,      0,      0ull,   0ull},
72536         {"THOU_XHD"                    ,        14,     1,      695,    "RO",   0,      0,      1ull,   1ull},
72537         {"THOU_XFD"                    ,        15,     1,      695,    "RO",   0,      0,      1ull,   1ull},
72538         {"RESERVED_16_63"              ,        16,     48,     695,    "RAZ",  1,      1,      0,      0},
72539         {"RESERVED_0_4"                ,        0,      5,      696,    "RAZ",  0,      0,      0ull,   0ull},
72540         {"FD"                          ,        5,      1,      696,    "RO",   0,      0,      0ull,   0ull},
72541         {"HFD"                         ,        6,      1,      696,    "RO",   0,      0,      0ull,   0ull},
72542         {"PAUSE"                       ,        7,      2,      696,    "RO",   0,      0,      0ull,   0ull},
72543         {"RESERVED_9_11"               ,        9,      3,      696,    "RAZ",  0,      0,      0ull,   0ull},
72544         {"REM_FLT"                     ,        12,     2,      696,    "RO",   0,      0,      0ull,   0ull},
72545         {"ACK"                         ,        14,     1,      696,    "RO",   0,      1,      0ull,   0},
72546         {"NP"                          ,        15,     1,      696,    "RO",   0,      0,      0ull,   0ull},
72547         {"RESERVED_16_63"              ,        16,     48,     696,    "RAZ",  1,      1,      0,      0},
72548         {"LINK_OK"                     ,        0,      1,      697,    "RO",   0,      0,      0ull,   0ull},
72549         {"DUP"                         ,        1,      1,      697,    "RO",   0,      0,      0ull,   0ull},
72550         {"AN_CPT"                      ,        2,      1,      697,    "RO",   0,      0,      0ull,   1ull},
72551         {"SPD"                         ,        3,      2,      697,    "RO",   0,      0,      0ull,   0ull},
72552         {"PAUSE"                       ,        5,      2,      697,    "RO",   0,      0,      0ull,   0ull},
72553         {"RESERVED_7_63"               ,        7,      57,     697,    "RAZ",  1,      1,      0,      0},
72554         {"LNKSPD_EN"                   ,        0,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72555         {"XMIT_EN"                     ,        1,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72556         {"AN_ERR_EN"                   ,        2,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72557         {"TXFIFU_EN"                   ,        3,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72558         {"TXFIFO_EN"                   ,        4,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72559         {"TXBAD_EN"                    ,        5,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72560         {"RXERR_EN"                    ,        6,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72561         {"RXBAD_EN"                    ,        7,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72562         {"RXLOCK_EN"                   ,        8,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72563         {"AN_BAD_EN"                   ,        9,      1,      698,    "R/W",  0,      0,      0ull,   1ull},
72564         {"SYNC_BAD_EN"                 ,        10,     1,      698,    "R/W",  0,      0,      0ull,   1ull},
72565         {"DUP"                         ,        11,     1,      698,    "R/W",  0,      0,      0ull,   1ull},
72566         {"RESERVED_12_63"              ,        12,     52,     698,    "RAZ",  1,      1,      0,      0},
72567         {"LNKSPD"                      ,        0,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72568         {"XMIT"                        ,        1,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72569         {"AN_ERR"                      ,        2,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72570         {"TXFIFU"                      ,        3,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72571         {"TXFIFO"                      ,        4,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72572         {"TXBAD"                       ,        5,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72573         {"RXERR"                       ,        6,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72574         {"RXBAD"                       ,        7,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72575         {"RXLOCK"                      ,        8,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72576         {"AN_BAD"                      ,        9,      1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72577         {"SYNC_BAD"                    ,        10,     1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72578         {"DUP"                         ,        11,     1,      699,    "R/W1C",        0,      0,      0ull,   0ull},
72579         {"RESERVED_12_63"              ,        12,     52,     699,    "RAZ",  1,      1,      0,      0},
72580         {"COUNT"                       ,        0,      16,     700,    "R/W",  0,      1,      1094ull,        0},
72581         {"RESERVED_16_63"              ,        16,     48,     700,    "RAZ",  1,      1,      0,      0},
72582         {"PKT_SZ"                      ,        0,      2,      701,    "R/W",  0,      0,      0ull,   0ull},
72583         {"LA_EN"                       ,        2,      1,      701,    "R/W",  0,      0,      0ull,   0ull},
72584         {"LAFIFOVFL"                   ,        3,      1,      701,    "R/W1C",        0,      0,      0ull,   0ull},
72585         {"RESERVED_4_63"               ,        4,      60,     701,    "RAZ",  1,      1,      0,      0},
72586         {"SAMP_PT"                     ,        0,      7,      702,    "R/W",  0,      1,      1ull,   0},
72587         {"AN_OVRD"                     ,        7,      1,      702,    "R/W",  0,      0,      0ull,   0ull},
72588         {"MODE"                        ,        8,      1,      702,    "R/W",  0,      0,      0ull,   0ull},
72589         {"MAC_PHY"                     ,        9,      1,      702,    "R/W",  0,      0,      0ull,   0ull},
72590         {"LOOPBCK2"                    ,        10,     1,      702,    "R/W",  0,      0,      0ull,   0ull},
72591         {"GMXENO"                      ,        11,     1,      702,    "R/W",  0,      0,      0ull,   0ull},
72592         {"SGMII"                       ,        12,     1,      702,    "RO",   1,      1,      0,      0},
72593         {"RESERVED_13_63"              ,        13,     51,     702,    "RAZ",  1,      1,      0,      0},
72594         {"RESERVED_0_4"                ,        0,      5,      703,    "RAZ",  1,      1,      0,      0},
72595         {"UNI"                         ,        5,      1,      703,    "R/W",  0,      0,      0ull,   0ull},
72596         {"SPDMSB"                      ,        6,      1,      703,    "R/W",  0,      0,      1ull,   1ull},
72597         {"COLTST"                      ,        7,      1,      703,    "R/W",  0,      0,      0ull,   0ull},
72598         {"DUP"                         ,        8,      1,      703,    "R/W",  0,      0,      1ull,   1ull},
72599         {"RST_AN"                      ,        9,      1,      703,    "R/W",  0,      0,      0ull,   0ull},
72600         {"RESERVED_10_10"              ,        10,     1,      703,    "RAZ",  1,      1,      0,      0},
72601         {"PWR_DN"                      ,        11,     1,      703,    "R/W",  0,      0,      1ull,   0ull},
72602         {"AN_EN"                       ,        12,     1,      703,    "R/W",  0,      0,      0ull,   0ull},
72603         {"SPDLSB"                      ,        13,     1,      703,    "R/W",  0,      0,      0ull,   0ull},
72604         {"LOOPBCK1"                    ,        14,     1,      703,    "R/W",  0,      0,      0ull,   0ull},
72605         {"RESET"                       ,        15,     1,      703,    "R/W",  0,      0,      0ull,   0ull},
72606         {"RESERVED_16_63"              ,        16,     48,     703,    "RAZ",  1,      1,      0,      0},
72607         {"EXTND"                       ,        0,      1,      704,    "RO",   0,      0,      0ull,   0ull},
72608         {"RESERVED_1_1"                ,        1,      1,      704,    "RAZ",  0,      0,      0ull,   0ull},
72609         {"LNK_ST"                      ,        2,      1,      704,    "RO",   0,      0,      0ull,   1ull},
72610         {"AN_ABIL"                     ,        3,      1,      704,    "RO",   0,      0,      1ull,   1ull},
72611         {"RM_FLT"                      ,        4,      1,      704,    "RO",   0,      0,      0ull,   0ull},
72612         {"AN_CPT"                      ,        5,      1,      704,    "RO",   0,      0,      0ull,   0ull},
72613         {"PRB_SUP"                     ,        6,      1,      704,    "RO",   0,      0,      1ull,   1ull},
72614         {"RESERVED_7_7"                ,        7,      1,      704,    "RAZ",  0,      0,      0ull,   0ull},
72615         {"EXT_ST"                      ,        8,      1,      704,    "RO",   0,      0,      1ull,   1ull},
72616         {"HUN_T2HD"                    ,        9,      1,      704,    "RO",   0,      0,      0ull,   0ull},
72617         {"HUN_T2FD"                    ,        10,     1,      704,    "RO",   0,      0,      0ull,   0ull},
72618         {"TEN_HD"                      ,        11,     1,      704,    "RO",   0,      0,      0ull,   0ull},
72619         {"TEN_FD"                      ,        12,     1,      704,    "RO",   0,      0,      0ull,   0ull},
72620         {"HUN_XHD"                     ,        13,     1,      704,    "RO",   0,      0,      0ull,   0ull},
72621         {"HUN_XFD"                     ,        14,     1,      704,    "RO",   0,      0,      0ull,   0ull},
72622         {"HUN_T4"                      ,        15,     1,      704,    "RO",   0,      0,      0ull,   0ull},
72623         {"RESERVED_16_63"              ,        16,     48,     704,    "RAZ",  1,      1,      0,      0},
72624         {"AN_ST"                       ,        0,      4,      705,    "RO",   0,      0,      0ull,   0ull},
72625         {"AN_BAD"                      ,        4,      1,      705,    "RO",   0,      0,      0ull,   0ull},
72626         {"SYNC"                        ,        5,      4,      705,    "RO",   0,      0,      0ull,   0ull},
72627         {"SYNC_BAD"                    ,        9,      1,      705,    "RO",   0,      0,      0ull,   0ull},
72628         {"RX_ST"                       ,        10,     5,      705,    "RO",   0,      0,      0ull,   0ull},
72629         {"RX_BAD"                      ,        15,     1,      705,    "RO",   0,      0,      0ull,   0ull},
72630         {"RESERVED_16_63"              ,        16,     48,     705,    "RAZ",  1,      1,      0,      0},
72631         {"BIT_LOCK"                    ,        0,      1,      706,    "RO",   0,      0,      0ull,   0ull},
72632         {"SYNC"                        ,        1,      1,      706,    "RO",   0,      0,      0ull,   0ull},
72633         {"RESERVED_2_63"               ,        2,      62,     706,    "RAZ",  1,      1,      0,      0},
72634         {"ONE"                         ,        0,      1,      707,    "RO",   0,      0,      1ull,   1ull},
72635         {"RESERVED_1_9"                ,        1,      9,      707,    "RAZ",  0,      1,      0ull,   0},
72636         {"SPEED"                       ,        10,     2,      707,    "R/W",  0,      0,      2ull,   2ull},
72637         {"DUP"                         ,        12,     1,      707,    "R/W",  0,      0,      1ull,   1ull},
72638         {"RESERVED_13_13"              ,        13,     1,      707,    "RAZ",  0,      1,      0ull,   0},
72639         {"ACK"                         ,        14,     1,      707,    "RO",   0,      0,      0ull,   0ull},
72640         {"LINK"                        ,        15,     1,      707,    "R/W",  0,      0,      0ull,   1ull},
72641         {"RESERVED_16_63"              ,        16,     48,     707,    "RAZ",  1,      1,      0,      0},
72642         {"ONE"                         ,        0,      1,      708,    "RO",   0,      0,      1ull,   1ull},
72643         {"RESERVED_1_9"                ,        1,      9,      708,    "RAZ",  0,      1,      0ull,   0},
72644         {"SPEED"                       ,        10,     2,      708,    "RO",   0,      0,      0ull,   2ull},
72645         {"DUP"                         ,        12,     1,      708,    "RO",   0,      0,      0ull,   1ull},
72646         {"RESERVED_13_14"              ,        13,     2,      708,    "RAZ",  0,      1,      0ull,   0},
72647         {"LINK"                        ,        15,     1,      708,    "RO",   0,      0,      0ull,   1ull},
72648         {"RESERVED_16_63"              ,        16,     48,     708,    "RAZ",  1,      1,      0,      0},
72649         {"ORD_ST"                      ,        0,      4,      709,    "RO",   0,      0,      0ull,   0ull},
72650         {"TX_BAD"                      ,        4,      1,      709,    "RO",   0,      0,      0ull,   0ull},
72651         {"XMIT"                        ,        5,      2,      709,    "RO",   0,      1,      0ull,   0},
72652         {"RESERVED_7_63"               ,        7,      57,     709,    "RAZ",  1,      1,      0,      0},
72653         {"TXPLRT"                      ,        0,      1,      710,    "R/W",  0,      0,      0ull,   0ull},
72654         {"RXPLRT"                      ,        1,      1,      710,    "R/W",  0,      0,      0ull,   0ull},
72655         {"AUTORXPL"                    ,        2,      1,      710,    "RO",   0,      0,      0ull,   0ull},
72656         {"RXOVRD"                      ,        3,      1,      710,    "R/W",  0,      0,      0ull,   0ull},
72657         {"RESERVED_4_63"               ,        4,      60,     710,    "RAZ",  1,      1,      0,      0},
72658         {"L0SYNC"                      ,        0,      1,      711,    "RO",   0,      0,      0ull,   1ull},
72659         {"L1SYNC"                      ,        1,      1,      711,    "RO",   0,      0,      0ull,   1ull},
72660         {"L2SYNC"                      ,        2,      1,      711,    "RO",   0,      0,      0ull,   1ull},
72661         {"L3SYNC"                      ,        3,      1,      711,    "RO",   0,      0,      0ull,   1ull},
72662         {"RESERVED_4_10"               ,        4,      7,      711,    "RAZ",  1,      1,      0,      0},
72663         {"PATTST"                      ,        11,     1,      711,    "RO",   0,      0,      0ull,   0ull},
72664         {"ALIGND"                      ,        12,     1,      711,    "RO",   0,      0,      0ull,   1ull},
72665         {"RESERVED_13_63"              ,        13,     51,     711,    "RAZ",  1,      1,      0,      0},
72666         {"BIST_STATUS"                 ,        0,      1,      712,    "RO",   0,      0,      0ull,   0ull},
72667         {"RESERVED_1_63"               ,        1,      63,     712,    "RAZ",  1,      1,      0,      0},
72668         {"BITLCK0"                     ,        0,      1,      713,    "RO",   0,      1,      0ull,   0},
72669         {"BITLCK1"                     ,        1,      1,      713,    "RO",   0,      1,      0ull,   0},
72670         {"BITLCK2"                     ,        2,      1,      713,    "RO",   0,      1,      0ull,   0},
72671         {"BITLCK3"                     ,        3,      1,      713,    "RO",   0,      1,      0ull,   0},
72672         {"RESERVED_4_63"               ,        4,      60,     713,    "RAZ",  1,      1,      0,      0},
72673         {"RESERVED_0_1"                ,        0,      2,      714,    "RAZ",  1,      1,      0,      0},
72674         {"SPD"                         ,        2,      4,      714,    "RO",   0,      0,      0ull,   0ull},
72675         {"SPDSEL0"                     ,        6,      1,      714,    "RO",   0,      0,      1ull,   1ull},
72676         {"RESERVED_7_10"               ,        7,      4,      714,    "RAZ",  1,      1,      0,      0},
72677         {"LO_PWR"                      ,        11,     1,      714,    "R/W",  0,      0,      0ull,   0ull},
72678         {"RESERVED_12_12"              ,        12,     1,      714,    "RAZ",  1,      1,      0,      0},
72679         {"SPDSEL1"                     ,        13,     1,      714,    "RO",   0,      0,      1ull,   1ull},
72680         {"LOOPBCK1"                    ,        14,     1,      714,    "R/W",  0,      0,      0ull,   0ull},
72681         {"RESET"                       ,        15,     1,      714,    "R/W",  0,      0,      1ull,   0ull},
72682         {"RESERVED_16_63"              ,        16,     48,     714,    "RAZ",  1,      1,      0,      0},
72683         {"TYPE"                        ,        0,      2,      715,    "RO",   0,      0,      1ull,   1ull},
72684         {"RESERVED_2_63"               ,        2,      62,     715,    "RAZ",  1,      1,      0,      0},
72685         {"TXFLT_EN"                    ,        0,      1,      716,    "R/W",  0,      0,      0ull,   1ull},
72686         {"RXBAD_EN"                    ,        1,      1,      716,    "R/W",  0,      0,      0ull,   1ull},
72687         {"RXSYNBAD_EN"                 ,        2,      1,      716,    "R/W",  0,      0,      0ull,   1ull},
72688         {"BITLCKLS_EN"                 ,        3,      1,      716,    "R/W",  0,      0,      0ull,   1ull},
72689         {"SYNLOS_EN"                   ,        4,      1,      716,    "R/W",  0,      0,      0ull,   1ull},
72690         {"ALGNLOS_EN"                  ,        5,      1,      716,    "R/W",  0,      0,      0ull,   1ull},
72691         {"RESERVED_6_63"               ,        6,      58,     716,    "RAZ",  1,      1,      0,      0},
72692         {"TXFLT"                       ,        0,      1,      717,    "R/W1C",        0,      0,      0ull,   0ull},
72693         {"RXBAD"                       ,        1,      1,      717,    "R/W1C",        0,      0,      0ull,   0ull},
72694         {"RXSYNBAD"                    ,        2,      1,      717,    "R/W1C",        0,      0,      0ull,   0ull},
72695         {"BITLCKLS"                    ,        3,      1,      717,    "R/W1C",        0,      0,      0ull,   0ull},
72696         {"SYNLOS"                      ,        4,      1,      717,    "R/W1C",        0,      0,      0ull,   0ull},
72697         {"ALGNLOS"                     ,        5,      1,      717,    "R/W1C",        0,      0,      0ull,   0ull},
72698         {"RESERVED_6_63"               ,        6,      58,     717,    "RAZ",  1,      1,      0,      0},
72699         {"PKT_SZ"                      ,        0,      2,      718,    "R/W",  0,      0,      0ull,   0ull},
72700         {"LA_EN"                       ,        2,      1,      718,    "R/W",  0,      0,      0ull,   0ull},
72701         {"LAFIFOVFL"                   ,        3,      1,      718,    "R/W1C",        0,      0,      0ull,   0ull},
72702         {"DROP_LN"                     ,        4,      2,      718,    "R/W",  0,      0,      0ull,   0ull},
72703         {"ENC_MODE"                    ,        6,      1,      718,    "R/W",  0,      0,      0ull,   0ull},
72704         {"RESERVED_7_63"               ,        7,      57,     718,    "RAZ",  1,      1,      0,      0},
72705         {"GMXENO"                      ,        0,      1,      719,    "R/W",  0,      0,      0ull,   0ull},
72706         {"XAUI"                        ,        1,      1,      719,    "RO",   1,      1,      0,      0},
72707         {"RX_SWAP"                     ,        2,      1,      719,    "R/W",  0,      1,      0ull,   0},
72708         {"TX_SWAP"                     ,        3,      1,      719,    "R/W",  0,      1,      0ull,   0},
72709         {"RESERVED_4_63"               ,        4,      60,     719,    "RAZ",  1,      1,      0,      0},
72710         {"SYNC0ST"                     ,        0,      4,      720,    "RO",   0,      1,      0ull,   0},
72711         {"SYNC1ST"                     ,        4,      4,      720,    "RO",   0,      1,      0ull,   0},
72712         {"SYNC2ST"                     ,        8,      4,      720,    "RO",   0,      1,      0ull,   0},
72713         {"SYNC3ST"                     ,        12,     4,      720,    "RO",   0,      1,      0ull,   0},
72714         {"RESERVED_16_63"              ,        16,     48,     720,    "RAZ",  1,      1,      0,      0},
72715         {"TENGB"                       ,        0,      1,      721,    "RO",   0,      0,      1ull,   1ull},
72716         {"TENPASST"                    ,        1,      1,      721,    "RO",   0,      0,      0ull,   0ull},
72717         {"RESERVED_2_63"               ,        2,      62,     721,    "RAZ",  1,      1,      0,      0},
72718         {"RESERVED_0_0"                ,        0,      1,      722,    "RAZ",  1,      1,      0,      0},
72719         {"LPABLE"                      ,        1,      1,      722,    "RO",   0,      0,      1ull,   1ull},
72720         {"RCV_LNK"                     ,        2,      1,      722,    "RO",   0,      0,      0ull,   1ull},
72721         {"RESERVED_3_6"                ,        3,      4,      722,    "RAZ",  1,      1,      0,      0},
72722         {"FLT"                         ,        7,      1,      722,    "RO",   0,      0,      0ull,   0ull},
72723         {"RESERVED_8_63"               ,        8,      56,     722,    "RAZ",  1,      1,      0,      0},
72724         {"TENGB_R"                     ,        0,      1,      723,    "RO",   0,      0,      0ull,   0ull},
72725         {"TENGB_X"                     ,        1,      1,      723,    "RO",   0,      0,      1ull,   1ull},
72726         {"TENGB_W"                     ,        2,      1,      723,    "RO",   0,      0,      0ull,   0ull},
72727         {"RESERVED_3_9"                ,        3,      7,      723,    "RAZ",  1,      1,      0,      0},
72728         {"RCVFLT"                      ,        10,     1,      723,    "RC",   0,      0,      0ull,   0ull},
72729         {"XMTFLT"                      ,        11,     1,      723,    "RC",   0,      0,      0ull,   0ull},
72730         {"RESERVED_12_13"              ,        12,     2,      723,    "RAZ",  1,      1,      0,      0},
72731         {"DEV"                         ,        14,     2,      723,    "RO",   0,      0,      2ull,   2ull},
72732         {"RESERVED_16_63"              ,        16,     48,     723,    "RAZ",  1,      1,      0,      0},
72733         {"TXPLRT"                      ,        0,      1,      724,    "R/W",  0,      0,      0ull,   0ull},
72734         {"RXPLRT"                      ,        1,      1,      724,    "R/W",  0,      0,      0ull,   0ull},
72735         {"XOR_TXPLRT"                  ,        2,      4,      724,    "R/W",  0,      0,      0ull,   0ull},
72736         {"XOR_RXPLRT"                  ,        6,      4,      724,    "R/W",  0,      0,      0ull,   0ull},
72737         {"RESERVED_10_63"              ,        10,     54,     724,    "RAZ",  1,      1,      0,      0},
72738         {"TX_ST"                       ,        0,      3,      725,    "RO",   0,      1,      0ull,   0},
72739         {"RX_ST"                       ,        3,      2,      725,    "RO",   0,      1,      0ull,   0},
72740         {"ALGN_ST"                     ,        5,      3,      725,    "RO",   0,      1,      0ull,   0},
72741         {"RXBAD"                       ,        8,      1,      725,    "RO",   0,      0,      0ull,   0ull},
72742         {"SYN0BAD"                     ,        9,      1,      725,    "RO",   0,      0,      0ull,   0ull},
72743         {"SYN1BAD"                     ,        10,     1,      725,    "RO",   0,      0,      0ull,   0ull},
72744         {"SYN2BAD"                     ,        11,     1,      725,    "RO",   0,      0,      0ull,   0ull},
72745         {"SYN3BAD"                     ,        12,     1,      725,    "RO",   0,      0,      0ull,   0ull},
72746         {"TERM_ERR"                    ,        13,     1,      725,    "R/W1C",        0,      0,      0ull,   0ull},
72747         {"RESERVED_14_63"              ,        14,     50,     725,    "RAZ",  1,      1,      0,      0},
72748         {"SOT"                         ,        0,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72749         {"RQHDR0"                      ,        1,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72750         {"RQHDR1"                      ,        2,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72751         {"RQDATA4"                     ,        3,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72752         {"RQDATA3"                     ,        4,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72753         {"RQDATA2"                     ,        5,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72754         {"RQDATA1"                     ,        6,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72755         {"RQDATA0"                     ,        7,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72756         {"RETRY"                       ,        8,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72757         {"PTLP_OR"                     ,        9,      1,      726,    "RO",   0,      0,      0ull,   0ull},
72758         {"NTLP_OR"                     ,        10,     1,      726,    "RO",   0,      0,      0ull,   0ull},
72759         {"CTLP_OR"                     ,        11,     1,      726,    "RO",   0,      0,      0ull,   0ull},
72760         {"RQDATA5"                     ,        12,     1,      726,    "RO",   0,      0,      0ull,   0ull},
72761         {"RESERVED_13_63"              ,        13,     51,     726,    "RAZ",  1,      1,      0,      0},
72762         {"PPF"                         ,        0,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72763         {"PEF_TC0"                     ,        1,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72764         {"PEF_TCF1"                    ,        2,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72765         {"PEF_TNF"                     ,        3,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72766         {"PEF_TPF0"                    ,        4,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72767         {"PEF_TPF1"                    ,        5,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72768         {"RSL_P2E"                     ,        6,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72769         {"PEAI_P2E"                    ,        7,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72770         {"DBG_P2E"                     ,        8,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72771         {"E2P_RSL"                     ,        9,      1,      727,    "RO",   0,      0,      0ull,   0ull},
72772         {"E2P_P"                       ,        10,     1,      727,    "RO",   0,      0,      0ull,   0ull},
72773         {"E2P_N"                       ,        11,     1,      727,    "RO",   0,      0,      0ull,   0ull},
72774         {"E2P_CPL"                     ,        12,     1,      727,    "RO",   0,      0,      0ull,   0ull},
72775         {"CTO_P2E"                     ,        13,     1,      727,    "RO",   0,      0,      0ull,   0ull},
72776         {"RESERVED_14_63"              ,        14,     50,     727,    "RAZ",  1,      1,      0,      0},
72777         {"ADDR"                        ,        0,      32,     728,    "R/W",  0,      1,      0ull,   0},
72778         {"DATA"                        ,        32,     32,     728,    "R/W",  0,      1,      0ull,   0},
72779         {"ADDR"                        ,        0,      32,     729,    "R/W",  0,      1,      0ull,   0},
72780         {"DATA"                        ,        32,     32,     729,    "R/W",  0,      1,      0ull,   0},
72781         {"TAG"                         ,        0,      32,     730,    "RO",   0,      0,      0ull,   0ull},
72782         {"RESERVED_32_63"              ,        32,     32,     730,    "RAZ",  1,      1,      0,      0},
72783         {"INV_LCRC"                    ,        0,      1,      731,    "R/W",  0,      0,      0ull,   0ull},
72784         {"INV_ECRC"                    ,        1,      1,      731,    "R/W",  0,      0,      0ull,   0ull},
72785         {"RESERVED_2_2"                ,        2,      1,      731,    "RAZ",  0,      0,      0ull,   0ull},
72786         {"RO_CTLP"                     ,        3,      1,      731,    "R/W",  0,      0,      0ull,   0ull},
72787         {"LNK_ENB"                     ,        4,      1,      731,    "R/W",  0,      0,      0ull,   0ull},
72788         {"DLY_ONE"                     ,        5,      1,      731,    "R/W",  0,      0,      0ull,   0ull},
72789         {"NF_ECRC"                     ,        6,      1,      731,    "R/W",  0,      0,      0ull,   0ull},
72790         {"RESERVED_7_8"                ,        7,      2,      731,    "RAZ",  0,      0,      0ull,   0ull},
72791         {"OB_P_CMD"                    ,        9,      1,      731,    "R/W",  0,      0,      0ull,   0ull},
72792         {"PM_XPME"                     ,        10,     1,      731,    "R/W",  0,      0,      0ull,   0ull},
72793         {"PM_XTOFF"                    ,        11,     1,      731,    "R/W",  0,      0,      0ull,   0ull},
72794         {"LANE_SWP"                    ,        12,     1,      731,    "R/W",  0,      0,      0ull,   0ull},
72795         {"QLM_CFG"                     ,        13,     2,      731,    "RO",   1,      1,      0,      0},
72796         {"PBUS"                        ,        15,     8,      731,    "RO",   1,      1,      0,      0},
72797         {"DNUM"                        ,        23,     5,      731,    "RO",   1,      1,      0,      0},
72798         {"RESERVED_28_63"              ,        28,     36,     731,    "RAZ",  1,      1,      0,      0},
72799         {"PCIERST"                     ,        0,      1,      732,    "RO",   0,      0,      0ull,   0ull},
72800         {"PCLK_RUN"                    ,        1,      1,      732,    "R/W1C",        0,      0,      0ull,   1ull},
72801         {"RESERVED_2_63"               ,        2,      62,     732,    "RAZ",  1,      1,      0,      0},
72802         {"SPOISON"                     ,        0,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72803         {"RTLPMAL"                     ,        1,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72804         {"RTLPLLE"                     ,        2,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72805         {"RECRCE"                      ,        3,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72806         {"RPOISON"                     ,        4,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72807         {"RCEMRC"                      ,        5,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72808         {"RNFEMRC"                     ,        6,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72809         {"RFEMRC"                      ,        7,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72810         {"RPMERC"                      ,        8,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72811         {"RPTAMRC"                     ,        9,      1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72812         {"RUMEP"                       ,        10,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72813         {"RVDM"                        ,        11,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72814         {"ACTO"                        ,        12,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72815         {"RTE"                         ,        13,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72816         {"MRE"                         ,        14,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72817         {"RDWDLE"                      ,        15,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72818         {"RTWDLE"                      ,        16,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72819         {"DPEOOSD"                     ,        17,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72820         {"FCPVWT"                      ,        18,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72821         {"RPE"                         ,        19,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72822         {"FCUV"                        ,        20,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72823         {"RQO"                         ,        21,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72824         {"RAUC"                        ,        22,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72825         {"RACUR"                       ,        23,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72826         {"RACCA"                       ,        24,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72827         {"CAAR"                        ,        25,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72828         {"RARWDNS"                     ,        26,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72829         {"RAMTLP"                      ,        27,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72830         {"RACPP"                       ,        28,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72831         {"RAWWPP"                      ,        29,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72832         {"ECRC_E"                      ,        30,     1,      733,    "R/W1C",        0,      0,      0ull,   0ull},
72833         {"RESERVED_31_63"              ,        31,     33,     733,    "RAZ",  1,      1,      0,      0},
72834         {"SPOISON"                     ,        0,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72835         {"RTLPMAL"                     ,        1,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72836         {"RTLPLLE"                     ,        2,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72837         {"RECRCE"                      ,        3,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72838         {"RPOISON"                     ,        4,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72839         {"RCEMRC"                      ,        5,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72840         {"RNFEMRC"                     ,        6,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72841         {"RFEMRC"                      ,        7,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72842         {"RPMERC"                      ,        8,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72843         {"RPTAMRC"                     ,        9,      1,      734,    "R/W",  0,      0,      0ull,   0ull},
72844         {"RUMEP"                       ,        10,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72845         {"RVDM"                        ,        11,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72846         {"ACTO"                        ,        12,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72847         {"RTE"                         ,        13,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72848         {"MRE"                         ,        14,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72849         {"RDWDLE"                      ,        15,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72850         {"RTWDLE"                      ,        16,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72851         {"DPEOOSD"                     ,        17,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72852         {"FCPVWT"                      ,        18,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72853         {"RPE"                         ,        19,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72854         {"FCUV"                        ,        20,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72855         {"RQO"                         ,        21,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72856         {"RAUC"                        ,        22,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72857         {"RACUR"                       ,        23,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72858         {"RACCA"                       ,        24,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72859         {"CAAR"                        ,        25,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72860         {"RARWDNS"                     ,        26,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72861         {"RAMTLP"                      ,        27,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72862         {"RACPP"                       ,        28,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72863         {"RAWWPP"                      ,        29,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72864         {"ECRC_E"                      ,        30,     1,      734,    "R/W",  0,      0,      0ull,   0ull},
72865         {"RESERVED_31_63"              ,        31,     33,     734,    "RAZ",  1,      1,      0,      0},
72866         {"AUX_EN"                      ,        0,      1,      735,    "RO",   0,      0,      0ull,   0ull},
72867         {"PM_EN"                       ,        1,      1,      735,    "RO",   0,      0,      0ull,   0ull},
72868         {"PM_STAT"                     ,        2,      1,      735,    "RO",   0,      0,      0ull,   0ull},
72869         {"PM_DST"                      ,        3,      1,      735,    "RO",   0,      0,      0ull,   0ull},
72870         {"RESERVED_4_63"               ,        4,      60,     735,    "RO",   1,      1,      0,      0},
72871         {"RESERVED_0_13"               ,        0,      14,     736,    "RAZ",  1,      1,      0,      0},
72872         {"ADDR"                        ,        14,     50,     736,    "R/W",  0,      0,      0ull,   0ull},
72873         {"RESERVED_0_25"               ,        0,      26,     737,    "RAZ",  1,      1,      0,      0},
72874         {"ADDR"                        ,        26,     38,     737,    "R/W",  0,      0,      0ull,   0ull},
72875         {"RESERVED_0_38"               ,        0,      39,     738,    "RAZ",  1,      1,      0,      0},
72876         {"ADDR"                        ,        39,     25,     738,    "R/W",  0,      0,      0ull,   0ull},
72877         {"RESERVED_0_11"               ,        0,      12,     739,    "RAZ",  1,      1,      0,      0},
72878         {"ADDR"                        ,        12,     52,     739,    "R/W",  0,      1,      4503599627370495ull,    0},
72879         {"RESERVED_0_11"               ,        0,      12,     740,    "RAZ",  1,      1,      0,      0},
72880         {"ADDR"                        ,        12,     52,     740,    "R/W",  0,      1,      4503599627370495ull,    0},
72881         {"NPEI_P"                      ,        0,      8,      741,    "R/W",  0,      0,      128ull, 128ull},
72882         {"NPEI_NP"                     ,        8,      8,      741,    "R/W",  0,      0,      16ull,  16ull},
72883         {"NPEI_CPL"                    ,        16,     8,      741,    "R/W",  0,      0,      128ull, 128ull},
72884         {"PESC_P"                      ,        24,     8,      741,    "R/W",  0,      0,      128ull, 128ull},
72885         {"PESC_NP"                     ,        32,     8,      741,    "R/W",  0,      0,      16ull,  16ull},
72886         {"PESC_CPL"                    ,        40,     8,      741,    "R/W",  0,      0,      128ull, 128ull},
72887         {"PEAI_PPF"                    ,        48,     8,      741,    "R/W",  0,      0,      128ull, 128ull},
72888         {"RESERVED_56_63"              ,        56,     8,      741,    "RAZ",  1,      1,      0,      0},
72889         {"BIST"                        ,        0,      18,     742,    "RO",   0,      0,      0ull,   0ull},
72890         {"RESERVED_18_63"              ,        18,     46,     742,    "RAZ",  1,      1,      0,      0},
72891         {"DPRT"                        ,        0,      16,     743,    "R/W",  0,      0,      0ull,   0ull},
72892         {"UDP"                         ,        16,     1,      743,    "R/W",  0,      0,      0ull,   0ull},
72893         {"TCP"                         ,        17,     1,      743,    "R/W",  0,      0,      0ull,   0ull},
72894         {"RESERVED_18_63"              ,        18,     46,     743,    "RAZ",  1,      1,      0,      0},
72895         {"MAP0"                        ,        0,      4,      744,    "R/W",  0,      0,      0ull,   0ull},
72896         {"MAP1"                        ,        4,      4,      744,    "R/W",  0,      0,      0ull,   0ull},
72897         {"MAP2"                        ,        8,      4,      744,    "R/W",  0,      0,      0ull,   0ull},
72898         {"MAP3"                        ,        12,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72899         {"MAP4"                        ,        16,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72900         {"MAP5"                        ,        20,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72901         {"MAP6"                        ,        24,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72902         {"MAP7"                        ,        28,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72903         {"MAP8"                        ,        32,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72904         {"MAP9"                        ,        36,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72905         {"MAP10"                       ,        40,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72906         {"MAP11"                       ,        44,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72907         {"MAP12"                       ,        48,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72908         {"MAP13"                       ,        52,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72909         {"MAP14"                       ,        56,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72910         {"MAP15"                       ,        60,     4,      744,    "R/W",  0,      0,      0ull,   0ull},
72911         {"MAP0"                        ,        0,      4,      745,    "R/W",  0,      0,      0ull,   0ull},
72912         {"MAP1"                        ,        4,      4,      745,    "R/W",  0,      0,      0ull,   0ull},
72913         {"MAP2"                        ,        8,      4,      745,    "R/W",  0,      0,      0ull,   0ull},
72914         {"MAP3"                        ,        12,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72915         {"MAP4"                        ,        16,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72916         {"MAP5"                        ,        20,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72917         {"MAP6"                        ,        24,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72918         {"MAP7"                        ,        28,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72919         {"MAP8"                        ,        32,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72920         {"MAP9"                        ,        36,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72921         {"MAP10"                       ,        40,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72922         {"MAP11"                       ,        44,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72923         {"MAP12"                       ,        48,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72924         {"MAP13"                       ,        52,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72925         {"MAP14"                       ,        56,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72926         {"MAP15"                       ,        60,     4,      745,    "R/W",  0,      0,      0ull,   0ull},
72927         {"MINLEN"                      ,        0,      16,     746,    "R/W",  0,      0,      64ull,  64ull},
72928         {"MAXLEN"                      ,        16,     16,     746,    "R/W",  0,      0,      1536ull,        1536ull},
72929         {"RESERVED_32_63"              ,        32,     32,     746,    "RAZ",  1,      1,      0,      0},
72930         {"NIP_SHF"                     ,        0,      3,      747,    "R/W",  0,      0,      0ull,   0ull},
72931         {"RESERVED_3_7"                ,        3,      5,      747,    "RAZ",  1,      1,      0,      0},
72932         {"RAW_SHF"                     ,        8,      3,      747,    "R/W",  0,      0,      0ull,   0ull},
72933         {"RESERVED_11_15"              ,        11,     5,      747,    "RAZ",  1,      1,      0,      0},
72934         {"MAX_L2"                      ,        16,     1,      747,    "R/W",  0,      0,      0ull,   0ull},
72935         {"IP6_UDP"                     ,        17,     1,      747,    "R/W",  0,      0,      1ull,   1ull},
72936         {"TAG_SYN"                     ,        18,     1,      747,    "R/W",  0,      0,      0ull,   0ull},
72937         {"RESERVED_19_63"              ,        19,     45,     747,    "RAZ",  1,      1,      0,      0},
72938         {"IP_CHK"                      ,        0,      1,      748,    "R/W",  0,      0,      1ull,   1ull},
72939         {"IP_MAL"                      ,        1,      1,      748,    "R/W",  0,      0,      1ull,   1ull},
72940         {"IP_HOP"                      ,        2,      1,      748,    "R/W",  0,      0,      1ull,   1ull},
72941         {"IP4_OPTS"                    ,        3,      1,      748,    "R/W",  0,      0,      1ull,   1ull},
72942         {"IP6_EEXT"                    ,        4,      2,      748,    "R/W",  0,      0,      1ull,   3ull},
72943         {"RESERVED_6_7"                ,        6,      2,      748,    "RAZ",  1,      1,      0,      0},
72944         {"L4_MAL"                      ,        8,      1,      748,    "R/W",  0,      0,      1ull,   1ull},
72945         {"L4_PRT"                      ,        9,      1,      748,    "R/W",  0,      0,      1ull,   1ull},
72946         {"L4_CHK"                      ,        10,     1,      748,    "R/W",  0,      0,      1ull,   1ull},
72947         {"L4_LEN"                      ,        11,     1,      748,    "R/W",  0,      0,      1ull,   1ull},
72948         {"TCP_FLAG"                    ,        12,     1,      748,    "R/W",  0,      0,      1ull,   1ull},
72949         {"L2_MAL"                      ,        13,     1,      748,    "R/W",  0,      0,      1ull,   1ull},
72950         {"VS_QOS"                      ,        14,     1,      748,    "R/W",  0,      0,      0ull,   0ull},
72951         {"VS_WQE"                      ,        15,     1,      748,    "R/W",  0,      0,      0ull,   0ull},
72952         {"IGNRS"                       ,        16,     1,      748,    "R/W",  0,      0,      0ull,   0ull},
72953         {"RESERVED_17_19"              ,        17,     3,      748,    "RAZ",  0,      0,      0ull,   0ull},
72954         {"RING_EN"                     ,        20,     1,      748,    "R/W",  0,      0,      0ull,   0ull},
72955         {"RESERVED_21_23"              ,        21,     3,      748,    "RAZ",  1,      1,      0,      0},
72956         {"DSA_GRP_SID"                 ,        24,     1,      748,    "R/W",  0,      0,      0ull,   0ull},
72957         {"DSA_GRP_SCMD"                ,        25,     1,      748,    "R/W",  0,      0,      0ull,   0ull},
72958         {"DSA_GRP_TVID"                ,        26,     1,      748,    "R/W",  0,      0,      0ull,   0ull},
72959         {"RESERVED_27_63"              ,        27,     37,     748,    "RAZ",  1,      1,      0,      0},
72960         {"PRI"                         ,        0,      6,      749,    "R/W",  0,      1,      0ull,   0},
72961         {"RESERVED_6_7"                ,        6,      2,      749,    "RAZ",  1,      1,      0,      0},
72962         {"QOS"                         ,        8,      3,      749,    "R/W",  0,      1,      0ull,   0},
72963         {"RESERVED_11_11"              ,        11,     1,      749,    "RAZ",  1,      1,      0,      0},
72964         {"UP_QOS"                      ,        12,     1,      749,    "RAZ",  0,      1,      0ull,   0},
72965         {"RESERVED_13_63"              ,        13,     51,     749,    "RAZ",  1,      1,      0,      0},
72966         {"PKTDRP"                      ,        0,      1,      750,    "R/W",  0,      0,      0ull,   0ull},
72967         {"RESERVED_1_1"                ,        1,      1,      750,    "RAZ",  1,      1,      0,      0},
72968         {"BCKPRS"                      ,        2,      1,      750,    "R/W",  0,      0,      0ull,   0ull},
72969         {"PRTNXA"                      ,        3,      1,      750,    "R/W",  0,      0,      0ull,   0ull},
72970         {"BADTAG"                      ,        4,      1,      750,    "R/W",  0,      0,      0ull,   0ull},
72971         {"SKPRUNT"                     ,        5,      1,      750,    "R/W",  0,      0,      0ull,   0ull},
72972         {"TODOOVR"                     ,        6,      1,      750,    "R/W",  0,      0,      0ull,   0ull},
72973         {"FEPERR"                      ,        7,      1,      750,    "R/W",  0,      0,      0ull,   0ull},
72974         {"BEPERR"                      ,        8,      1,      750,    "R/W",  0,      0,      0ull,   0ull},
72975         {"MINERR"                      ,        9,      1,      750,    "R/W",  0,      0,      0ull,   0ull},
72976         {"MAXERR"                      ,        10,     1,      750,    "R/W",  0,      0,      0ull,   0ull},
72977         {"LENERR"                      ,        11,     1,      750,    "R/W",  0,      0,      0ull,   0ull},
72978         {"PUNYERR"                     ,        12,     1,      750,    "R/W",  0,      0,      0ull,   0ull},
72979         {"RESERVED_13_63"              ,        13,     51,     750,    "RAZ",  1,      1,      0,      0},
72980         {"PKTDRP"                      ,        0,      1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72981         {"RESERVED_1_1"                ,        1,      1,      751,    "RAZ",  1,      1,      0,      0},
72982         {"BCKPRS"                      ,        2,      1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72983         {"PRTNXA"                      ,        3,      1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72984         {"BADTAG"                      ,        4,      1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72985         {"SKPRUNT"                     ,        5,      1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72986         {"TODOOVR"                     ,        6,      1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72987         {"FEPERR"                      ,        7,      1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72988         {"BEPERR"                      ,        8,      1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72989         {"MINERR"                      ,        9,      1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72990         {"MAXERR"                      ,        10,     1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72991         {"LENERR"                      ,        11,     1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72992         {"PUNYERR"                     ,        12,     1,      751,    "R/W1C",        0,      0,      0ull,   0ull},
72993         {"RESERVED_13_63"              ,        13,     51,     751,    "RAZ",  1,      1,      0,      0},
72994         {"OFFSET"                      ,        0,      3,      752,    "R/W",  0,      0,      0ull,   0ull},
72995         {"RESERVED_3_63"               ,        3,      61,     752,    "RAZ",  1,      1,      0,      0},
72996         {"SKIP"                        ,        0,      7,      753,    "R/W",  0,      0,      0ull,   0ull},
72997         {"RESERVED_7_7"                ,        7,      1,      753,    "RAZ",  1,      1,      0,      0},
72998         {"MODE"                        ,        8,      2,      753,    "R/W",  0,      0,      0ull,   0ull},
72999         {"DSA_EN"                      ,        10,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73000         {"HIGIG_EN"                    ,        11,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73001         {"CRC_EN"                      ,        12,     1,      753,    "RO",   0,      0,      0ull,   0ull},
73002         {"RESERVED_13_15"              ,        13,     3,      753,    "RAZ",  1,      1,      0,      0},
73003         {"QOS_VLAN"                    ,        16,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73004         {"QOS_DIFF"                    ,        17,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73005         {"QOS_VOD"                     ,        18,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73006         {"QOS_VSEL"                    ,        19,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73007         {"QOS_WAT"                     ,        20,     4,      753,    "R/W",  0,      0,      0ull,   0ull},
73008         {"QOS"                         ,        24,     3,      753,    "R/W",  0,      0,      0ull,   0ull},
73009         {"HG_QOS"                      ,        27,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73010         {"GRP_WAT"                     ,        28,     4,      753,    "R/W",  0,      0,      0ull,   0ull},
73011         {"INST_HDR"                    ,        32,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73012         {"DYN_RS"                      ,        33,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73013         {"TAG_INC"                     ,        34,     2,      753,    "R/W",  0,      0,      0ull,   0ull},
73014         {"RAWDRP"                      ,        36,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73015         {"RESERVED_37_39"              ,        37,     3,      753,    "RAZ",  1,      1,      0,      0},
73016         {"QOS_WAT_47"                  ,        40,     4,      753,    "R/W",  0,      0,      0ull,   0ull},
73017         {"GRP_WAT_47"                  ,        44,     4,      753,    "R/W",  0,      0,      0ull,   0ull},
73018         {"MINERR_EN"                   ,        48,     1,      753,    "R/W",  0,      0,      1ull,   1ull},
73019         {"MAXERR_EN"                   ,        49,     1,      753,    "R/W",  0,      0,      1ull,   1ull},
73020         {"LENERR_EN"                   ,        50,     1,      753,    "R/W",  0,      0,      1ull,   1ull},
73021         {"VLAN_LEN"                    ,        51,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73022         {"PAD_LEN"                     ,        52,     1,      753,    "R/W",  0,      0,      0ull,   0ull},
73023         {"RESERVED_53_63"              ,        53,     11,     753,    "RAZ",  1,      1,      0,      0},
73024         {"GRP"                         ,        0,      4,      754,    "R/W",  0,      0,      0ull,   0ull},
73025         {"NON_TAG_TYPE"                ,        4,      2,      754,    "R/W",  0,      0,      0ull,   0ull},
73026         {"IP4_TAG_TYPE"                ,        6,      2,      754,    "R/W",  0,      0,      0ull,   0ull},
73027         {"IP6_TAG_TYPE"                ,        8,      2,      754,    "R/W",  0,      0,      0ull,   0ull},
73028         {"TCP4_TAG_TYPE"               ,        10,     2,      754,    "R/W",  0,      0,      0ull,   0ull},
73029         {"TCP6_TAG_TYPE"               ,        12,     2,      754,    "R/W",  0,      0,      0ull,   0ull},
73030         {"IP4_SRC_FLAG"                ,        14,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73031         {"IP6_SRC_FLAG"                ,        15,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73032         {"IP4_DST_FLAG"                ,        16,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73033         {"IP6_DST_FLAG"                ,        17,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73034         {"IP4_PCTL_FLAG"               ,        18,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73035         {"IP6_NXTH_FLAG"               ,        19,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73036         {"IP4_SPRT_FLAG"               ,        20,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73037         {"IP6_SPRT_FLAG"               ,        21,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73038         {"IP4_DPRT_FLAG"               ,        22,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73039         {"IP6_DPRT_FLAG"               ,        23,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73040         {"INC_PRT_FLAG"                ,        24,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73041         {"INC_VLAN"                    ,        25,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73042         {"INC_VS"                      ,        26,     2,      754,    "R/W",  0,      0,      0ull,   0ull},
73043         {"TAG_MODE"                    ,        28,     2,      754,    "R/W",  0,      0,      0ull,   0ull},
73044         {"GRPTAG_MSKIP"                ,        30,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73045         {"GRPTAG"                      ,        31,     1,      754,    "R/W",  0,      0,      0ull,   0ull},
73046         {"GRPTAGMASK"                  ,        32,     4,      754,    "R/W",  0,      0,      0ull,   0ull},
73047         {"GRPTAGBASE"                  ,        36,     4,      754,    "R/W",  0,      0,      0ull,   0ull},
73048         {"RESERVED_40_63"              ,        40,     24,     754,    "RAZ",  1,      1,      0,      0},
73049         {"QOS"                         ,        0,      3,      755,    "R/W",  0,      0,      0ull,   0ull},
73050         {"RESERVED_3_63"               ,        3,      61,     755,    "RAZ",  1,      1,      0,      0},
73051         {"QOS"                         ,        0,      3,      756,    "R/W",  0,      0,      0ull,   0ull},
73052         {"RESERVED_3_3"                ,        3,      1,      756,    "RAZ",  1,      1,      0,      0},
73053         {"QOS1"                        ,        4,      3,      756,    "R/W",  0,      0,      0ull,   0ull},
73054         {"RESERVED_7_63"               ,        7,      57,     756,    "RAZ",  1,      1,      0,      0},
73055         {"MATCH_VALUE"                 ,        0,      16,     757,    "R/W",  0,      0,      0ull,   0ull},
73056         {"MATCH_TYPE"                  ,        16,     3,      757,    "R/W",  0,      0,      0ull,   0ull},
73057         {"RESERVED_19_19"              ,        19,     1,      757,    "RAZ",  1,      1,      0,      0},
73058         {"QOS"                         ,        20,     3,      757,    "R/W",  0,      0,      0ull,   0ull},
73059         {"RESERVED_23_23"              ,        23,     1,      757,    "RAZ",  1,      1,      0,      0},
73060         {"GRP"                         ,        24,     4,      757,    "R/W",  0,      0,      0ull,   0ull},
73061         {"RESERVED_28_31"              ,        28,     4,      757,    "RAZ",  1,      1,      0,      0},
73062         {"MASK"                        ,        32,     16,     757,    "R/W",  0,      0,      0ull,   0ull},
73063         {"RESERVED_48_63"              ,        48,     16,     757,    "RAZ",  1,      1,      0,      0},
73064         {"WORD"                        ,        0,      56,     758,    "R/W",  0,      0,      0ull,   0ull},
73065         {"RESERVED_56_63"              ,        56,     8,      758,    "RAZ",  1,      1,      0,      0},
73066         {"RST"                         ,        0,      1,      759,    "R/W",  0,      0,      0ull,   0ull},
73067         {"RESERVED_1_63"               ,        1,      63,     759,    "RAZ",  1,      1,      0,      0},
73068         {"DRP_OCTS"                    ,        0,      32,     760,    "R/W",  0,      1,      0ull,   0},
73069         {"DRP_PKTS"                    ,        32,     32,     760,    "R/W",  0,      1,      0ull,   0},
73070         {"OCTS"                        ,        0,      48,     761,    "R/W",  0,      1,      0ull,   0},
73071         {"RESERVED_48_63"              ,        48,     16,     761,    "RAZ",  1,      1,      0,      0},
73072         {"RAW"                         ,        0,      32,     762,    "R/W",  0,      1,      0ull,   0},
73073         {"PKTS"                        ,        32,     32,     762,    "R/W",  0,      1,      0ull,   0},
73074         {"MCST"                        ,        0,      32,     763,    "R/W",  0,      1,      0ull,   0},
73075         {"BCST"                        ,        32,     32,     763,    "R/W",  0,      1,      0ull,   0},
73076         {"H64"                         ,        0,      32,     764,    "R/W",  0,      1,      0ull,   0},
73077         {"H65TO127"                    ,        32,     32,     764,    "R/W",  0,      1,      0ull,   0},
73078         {"H128TO255"                   ,        0,      32,     765,    "R/W",  0,      1,      0ull,   0},
73079         {"H256TO511"                   ,        32,     32,     765,    "R/W",  0,      1,      0ull,   0},
73080         {"H512TO1023"                  ,        0,      32,     766,    "R/W",  0,      1,      0ull,   0},
73081         {"H1024TO1518"                 ,        32,     32,     766,    "R/W",  0,      1,      0ull,   0},
73082         {"H1519"                       ,        0,      32,     767,    "R/W",  0,      1,      0ull,   0},
73083         {"FCS"                         ,        32,     32,     767,    "R/W",  0,      1,      0ull,   0},
73084         {"UNDERSZ"                     ,        0,      32,     768,    "R/W",  0,      1,      0ull,   0},
73085         {"FRAG"                        ,        32,     32,     768,    "R/W",  0,      1,      0ull,   0},
73086         {"OVERSZ"                      ,        0,      32,     769,    "R/W",  0,      1,      0ull,   0},
73087         {"JABBER"                      ,        32,     32,     769,    "R/W",  0,      1,      0ull,   0},
73088         {"RDCLR"                       ,        0,      1,      770,    "R/W",  0,      0,      1ull,   1ull},
73089         {"RESERVED_1_63"               ,        1,      63,     770,    "RAZ",  1,      1,      0,      0},
73090         {"ERRS"                        ,        0,      16,     771,    "R/W",  0,      1,      0ull,   0},
73091         {"RESERVED_16_63"              ,        16,     48,     771,    "RAZ",  1,      1,      0,      0},
73092         {"OCTS"                        ,        0,      48,     772,    "R/W",  0,      1,      0ull,   0},
73093         {"RESERVED_48_63"              ,        48,     16,     772,    "RAZ",  1,      1,      0,      0},
73094         {"PKTS"                        ,        0,      32,     773,    "R/W",  0,      1,      0ull,   0},
73095         {"RESERVED_32_63"              ,        32,     32,     773,    "RAZ",  1,      1,      0,      0},
73096         {"EN"                          ,        0,      8,      774,    "R/W",  0,      0,      0ull,   0ull},
73097         {"RESERVED_8_63"               ,        8,      56,     774,    "RAZ",  1,      1,      0,      0},
73098         {"MASK"                        ,        0,      16,     775,    "R/W",  0,      0,      0ull,   0ull},
73099         {"RESERVED_16_63"              ,        16,     48,     775,    "RAZ",  1,      1,      0,      0},
73100         {"SRC"                         ,        0,      16,     776,    "R/W",  0,      0,      0ull,   0ull},
73101         {"DST"                         ,        16,     16,     776,    "R/W",  0,      0,      0ull,   0ull},
73102         {"RESERVED_32_63"              ,        32,     32,     776,    "RAZ",  1,      1,      0,      0},
73103         {"ENTRY"                       ,        0,      62,     777,    "RO",   1,      1,      0,      0},
73104         {"RESERVED_62_62"              ,        62,     1,      777,    "RAZ",  1,      1,      0,      0},
73105         {"VAL"                         ,        63,     1,      777,    "RO",   1,      1,      0,      0},
73106         {"COUNT"                       ,        0,      32,     778,    "R/W1C",        1,      0,      0,      0ull},
73107         {"RESERVED_32_63"              ,        32,     32,     778,    "RAZ",  1,      1,      0,      0},
73108         {"COUNT"                       ,        0,      48,     779,    "R/W1C",        1,      0,      0,      0ull},
73109         {"RESERVED_48_63"              ,        48,     16,     779,    "RAZ",  1,      1,      0,      0},
73110         {"SIZE"                        ,        0,      16,     780,    "RO",   1,      0,      0,      0ull},
73111         {"SEGS"                        ,        16,     6,      780,    "RO",   1,      0,      0,      0ull},
73112         {"CMD"                         ,        22,     14,     780,    "RO",   1,      0,      0,      0ull},
73113         {"FAU"                         ,        36,     28,     780,    "RO",   1,      0,      0,      0ull},
73114         {"PTR"                         ,        0,      40,     781,    "RO",   1,      0,      0,      0ull},
73115         {"SIZE"                        ,        40,     16,     781,    "RO",   1,      0,      0,      0ull},
73116         {"POOL"                        ,        56,     3,      781,    "RO",   1,      0,      0,      0ull},
73117         {"BACK"                        ,        59,     4,      781,    "RO",   1,      0,      0,      0ull},
73118         {"I"                           ,        63,     1,      781,    "RO",   1,      0,      0,      0ull},
73119         {"PTRS2"                       ,        0,      17,     782,    "RO",   1,      0,      0,      0ull},
73120         {"RESERVED_17_31"              ,        17,     15,     782,    "RAZ",  1,      0,      0,      0ull},
73121         {"PTRS1"                       ,        32,     17,     782,    "RO",   1,      0,      0,      0ull},
73122         {"RESERVED_49_63"              ,        49,     15,     782,    "RAZ",  1,      0,      0,      0ull},
73123         {"MOD"                         ,        0,      3,      783,    "RO",   1,      0,      0,      0ull},
73124         {"CNT"                         ,        3,      13,     783,    "RO",   1,      0,      0,      0ull},
73125         {"CHK"                         ,        16,     1,      783,    "RO",   1,      0,      0,      0ull},
73126         {"LEN"                         ,        17,     1,      783,    "RO",   1,      0,      0,      0ull},
73127         {"SOP"                         ,        18,     1,      783,    "RO",   1,      0,      0,      0ull},
73128         {"UID"                         ,        19,     3,      783,    "RO",   1,      0,      0,      0ull},
73129         {"MAJ"                         ,        22,     1,      783,    "RO",   1,      0,      0,      0ull},
73130         {"RESERVED_23_63"              ,        23,     41,     783,    "RAZ",  1,      0,      0,      0ull},
73131         {"SIZE"                        ,        0,      16,     784,    "RO",   1,      0,      0,      0ull},
73132         {"SEGS"                        ,        16,     6,      784,    "RO",   1,      0,      0,      0ull},
73133         {"CMD"                         ,        22,     14,     784,    "RO",   1,      0,      0,      0ull},
73134         {"FAU"                         ,        36,     28,     784,    "RO",   1,      0,      0,      0ull},
73135         {"PTR"                         ,        0,      40,     785,    "RO",   1,      0,      0,      0ull},
73136         {"SIZE"                        ,        40,     16,     785,    "RO",   1,      0,      0,      0ull},
73137         {"POOL"                        ,        56,     3,      785,    "RO",   1,      0,      0,      0ull},
73138         {"BACK"                        ,        59,     4,      785,    "RO",   1,      0,      0,      0ull},
73139         {"I"                           ,        63,     1,      785,    "RO",   1,      0,      0,      0ull},
73140         {"DATA"                        ,        0,      64,     786,    "RO",   1,      0,      0,      0ull},
73141         {"PTR"                         ,        0,      40,     787,    "RO",   1,      0,      0,      0ull},
73142         {"SIZE"                        ,        40,     16,     787,    "RO",   1,      0,      0,      0ull},
73143         {"POOL"                        ,        56,     3,      787,    "RO",   1,      0,      0,      0ull},
73144         {"BACK"                        ,        59,     4,      787,    "RO",   1,      0,      0,      0ull},
73145         {"I"                           ,        63,     1,      787,    "RO",   1,      0,      0,      0ull},
73146         {"DATA"                        ,        0,      64,     788,    "RO",   1,      0,      0,      0ull},
73147         {"MAJOR"                       ,        0,      3,      789,    "RO",   1,      0,      0,      0ull},
73148         {"MINOR"                       ,        3,      2,      789,    "RO",   1,      0,      0,      0ull},
73149         {"WAIT"                        ,        5,      1,      789,    "RO",   1,      0,      0,      0ull},
73150         {"CHK_MODE"                    ,        6,      1,      789,    "RO",   1,      0,      0,      0ull},
73151         {"CHK_ONCE"                    ,        7,      1,      789,    "RO",   1,      0,      0,      0ull},
73152         {"INIT_DWRITE"                 ,        8,      1,      789,    "RO",   1,      0,      0,      0ull},
73153         {"DREAD_SOP"                   ,        9,      1,      789,    "RO",   1,      0,      0,      0ull},
73154         {"UID"                         ,        10,     2,      789,    "RO",   1,      0,      0,      0ull},
73155         {"CMND_OFF"                    ,        12,     6,      789,    "RO",   1,      0,      0,      0ull},
73156         {"CMND_SIZ"                    ,        18,     16,     789,    "RO",   1,      0,      0,      0ull},
73157         {"CMND_SEGS"                   ,        34,     6,      789,    "RO",   1,      0,      0,      0ull},
73158         {"CURR_OFF"                    ,        40,     16,     789,    "RO",   1,      0,      0,      0ull},
73159         {"CURR_SIZ"                    ,        56,     8,      789,    "RO",   1,      0,      0,      0ull},
73160         {"CURR_SIZ"                    ,        0,      8,      790,    "RO",   1,      0,      0,      0ull},
73161         {"CURR_PTR"                    ,        8,      40,     790,    "RO",   1,      0,      0,      0ull},
73162         {"NXT_INFLT"                   ,        48,     6,      790,    "RO",   1,      0,      0,      0ull},
73163         {"RESERVED_54_63"              ,        54,     10,     790,    "RAZ",  1,      0,      0,      0ull},
73164         {"QID_BASE"                    ,        0,      8,      791,    "RO",   1,      0,      0,      0ull},
73165         {"QID_OFF"                     ,        8,      4,      791,    "RO",   1,      0,      0,      0ull},
73166         {"QID_OFFMAX"                  ,        12,     4,      791,    "RO",   1,      0,      0,      0ull},
73167         {"QCB_RIDX"                    ,        16,     5,      791,    "RO",   1,      0,      0,      0ull},
73168         {"QOS"                         ,        21,     3,      791,    "RO",   1,      0,      0,      0ull},
73169         {"STATC"                       ,        24,     1,      791,    "RO",   1,      0,      0,      0ull},
73170         {"ACTIVE"                      ,        25,     1,      791,    "RO",   1,      0,      0,      0ull},
73171         {"PREEMPTED"                   ,        26,     1,      791,    "RO",   1,      0,      0,      0ull},
73172         {"PREEMPTEE"                   ,        27,     1,      791,    "RO",   1,      0,      0,      0ull},
73173         {"PREEMPTER"                   ,        28,     1,      791,    "RO",   1,      0,      0,      0ull},
73174         {"QID_OFFTHS"                  ,        29,     4,      791,    "RO",   1,      0,      0,      0ull},
73175         {"QID_OFFRES"                  ,        33,     4,      791,    "RO",   1,      0,      0,      0ull},
73176         {"RESERVED_37_63"              ,        37,     27,     791,    "RAZ",  1,      0,      0,      0ull},
73177         {"QCB_RIDX"                    ,        0,      6,      792,    "RO",   1,      0,      0,      0ull},
73178         {"QCB_WIDX"                    ,        6,      6,      792,    "RO",   1,      0,      0,      0ull},
73179         {"BUF_PTR"                     ,        12,     33,     792,    "RO",   1,      0,      0,      0ull},
73180         {"BUF_SIZ"                     ,        45,     13,     792,    "RO",   1,      0,      0,      0ull},
73181         {"TAIL"                        ,        58,     1,      792,    "RO",   1,      0,      0,      0ull},
73182         {"QOS"                         ,        59,     5,      792,    "RO",   1,      0,      0,      0ull},
73183         {"QOS"                         ,        0,      3,      793,    "RO",   1,      0,      0,      0ull},
73184         {"STATIC_Q"                    ,        3,      1,      793,    "RO",   1,      0,      0,      0ull},
73185         {"S_TAIL"                      ,        4,      1,      793,    "RO",   1,      0,      0,      0ull},
73186         {"STATIC_P"                    ,        5,      1,      793,    "RO",   1,      0,      0,      0ull},
73187         {"PREEMPTEE"                   ,        6,      1,      793,    "RO",   1,      0,      0,      0ull},
73188         {"RESERVED_7_7"                ,        7,      1,      793,    "RAZ",  1,      0,      0,      0ull},
73189         {"DOORBELL"                    ,        8,      20,     793,    "RO",   1,      0,      0,      0ull},
73190         {"PREEMPTER"                   ,        28,     1,      793,    "RO",   1,      0,      0,      0ull},
73191         {"RESERVED_29_63"              ,        29,     35,     793,    "RAZ",  1,      0,      0,      0ull},
73192         {"PTRS3"                       ,        0,      17,     794,    "RO",   1,      0,      0,      0ull},
73193         {"RESERVED_17_31"              ,        17,     15,     794,    "RAZ",  1,      0,      0,      0ull},
73194         {"PTRS0"                       ,        32,     17,     794,    "RO",   1,      0,      0,      0ull},
73195         {"RESERVED_49_63"              ,        49,     15,     794,    "RAZ",  1,      0,      0,      0ull},
73196         {"PID"                         ,        0,      6,      795,    "R/W",  1,      0,      0,      0ull},
73197         {"EID"                         ,        6,      4,      795,    "R/W",  1,      0,      0,      0ull},
73198         {"BP_PORT"                     ,        10,     6,      795,    "R/W",  1,      0,      0,      0ull},
73199         {"RESERVED_16_52"              ,        16,     37,     795,    "RAZ",  1,      0,      0,      0ull},
73200         {"QOS_MASK"                    ,        53,     8,      795,    "R/W",  1,      0,      0,      0ull},
73201         {"STATIC_P"                    ,        61,     1,      795,    "R/W",  1,      0,      0,      0ull},
73202         {"RESERVED_62_63"              ,        62,     2,      795,    "RAZ",  1,      0,      0,      0ull},
73203         {"PID"                         ,        0,      6,      796,    "R/W",  1,      0,      0,      0ull},
73204         {"EID"                         ,        6,      4,      796,    "R/W",  1,      0,      0,      0ull},
73205         {"RESERVED_10_52"              ,        10,     43,     796,    "RAZ",  1,      0,      0,      0ull},
73206         {"QOS_MASK"                    ,        53,     8,      796,    "R/W",  1,      0,      0,      0ull},
73207         {"RESERVED_61_63"              ,        61,     3,      796,    "RAZ",  1,      0,      0,      0ull},
73208         {"PID"                         ,        0,      6,      797,    "R/W",  1,      0,      0,      0ull},
73209         {"RESERVED_6_7"                ,        6,      2,      797,    "RAZ",  1,      0,      0,      0ull},
73210         {"RATE_PKT"                    ,        8,      24,     797,    "R/W",  1,      0,      0,      0ull},
73211         {"RATE_WORD"                   ,        32,     19,     797,    "R/W",  1,      0,      0,      0ull},
73212         {"RESERVED_51_63"              ,        51,     13,     797,    "RAZ",  1,      0,      0,      0ull},
73213         {"PID"                         ,        0,      6,      798,    "R/W",  1,      0,      0,      0ull},
73214         {"RESERVED_6_7"                ,        6,      2,      798,    "RAZ",  1,      0,      0,      0ull},
73215         {"RATE_LIM"                    ,        8,      24,     798,    "R/W",  1,      0,      0,      0ull},
73216         {"RESERVED_32_63"              ,        32,     32,     798,    "RAZ",  1,      0,      0,      0ull},
73217         {"QUEUE"                       ,        0,      7,      799,    "R/W",  1,      0,      0,      0ull},
73218         {"PORT"                        ,        7,      6,      799,    "WR0",  1,      0,      0,      0ull},
73219         {"INDEX"                       ,        13,     3,      799,    "WR0",  1,      0,      0,      0ull},
73220         {"TAIL"                        ,        16,     1,      799,    "R/W",  1,      0,      0,      0ull},
73221         {"BUF_PTR"                     ,        17,     36,     799,    "R/W",  1,      0,      0,      0ull},
73222         {"QOS_MASK"                    ,        53,     8,      799,    "R/W",  1,      0,      0,      0ull},
73223         {"STATIC_Q"                    ,        61,     1,      799,    "R/W",  1,      0,      0,      0ull},
73224         {"STATIC_P"                    ,        62,     1,      799,    "R/W",  1,      0,      0,      0ull},
73225         {"S_TAIL"                      ,        63,     1,      799,    "R/W",  1,      0,      0,      0ull},
73226         {"QID"                         ,        0,      7,      800,    "R/W",  1,      0,      0,      0ull},
73227         {"PID"                         ,        7,      6,      800,    "WR0",  1,      0,      0,      0ull},
73228         {"RESERVED_13_52"              ,        13,     40,     800,    "RAZ",  1,      0,      0,      0ull},
73229         {"QOS_MASK"                    ,        53,     8,      800,    "R/W",  1,      0,      0,      0ull},
73230         {"RESERVED_61_63"              ,        61,     3,      800,    "RAZ",  1,      0,      0,      0ull},
73231         {"DAT_PTR"                     ,        0,      4,      801,    "RO",   1,      0,      0,      0ull},
73232         {"DAT_DAT"                     ,        4,      2,      801,    "RO",   1,      0,      0,      0ull},
73233         {"PRT_CTL"                     ,        6,      2,      801,    "RO",   1,      0,      0,      0ull},
73234         {"PRT_QSB"                     ,        8,      3,      801,    "RO",   1,      0,      0,      0ull},
73235         {"PRT_QCB"                     ,        11,     2,      801,    "RO",   1,      0,      0,      0ull},
73236         {"NCB_INB"                     ,        13,     2,      801,    "RO",   1,      0,      0,      0ull},
73237         {"PRT_PSB"                     ,        15,     8,      801,    "RO",   1,      0,      0,      0ull},
73238         {"PRT_NXT"                     ,        23,     1,      801,    "RO",   1,      0,      0,      0ull},
73239         {"PRT_CHK"                     ,        24,     3,      801,    "RO",   1,      0,      0,      0ull},
73240         {"OUT_WIF"                     ,        27,     1,      801,    "RO",   1,      0,      0,      0ull},
73241         {"OUT_STA"                     ,        28,     1,      801,    "RO",   1,      0,      0,      0ull},
73242         {"OUT_CTL"                     ,        29,     3,      801,    "RO",   1,      0,      0,      0ull},
73243         {"OUT_DAT"                     ,        32,     1,      801,    "RO",   1,      0,      0,      0ull},
73244         {"IOB"                         ,        33,     1,      801,    "RO",   1,      0,      0,      0ull},
73245         {"CSR"                         ,        34,     1,      801,    "RO",   1,      0,      0,      0ull},
73246         {"RESERVED_35_63"              ,        35,     29,     801,    "RAZ",  1,      0,      0,      0ull},
73247         {"SIZE"                        ,        0,      13,     802,    "R/W",  0,      0,      0ull,   0ull},
73248         {"RESERVED_13_19"              ,        13,     7,      802,    "RAZ",  0,      0,      0ull,   0ull},
73249         {"POOL"                        ,        20,     3,      802,    "R/W",  0,      0,      0ull,   0ull},
73250         {"RESERVED_23_63"              ,        23,     41,     802,    "RAZ",  1,      0,      0,      0ull},
73251         {"ASSERTS"                     ,        0,      64,     803,    "RO",   0,      0,      0ull,   0ull},
73252         {"ASSERTS"                     ,        0,      64,     804,    "RO",   0,      0,      0ull,   0ull},
73253         {"ASSERTS"                     ,        0,      64,     805,    "RO",   0,      0,      0ull,   0ull},
73254         {"ASSERTS"                     ,        0,      64,     806,    "RO",   0,      0,      0ull,   0ull},
73255         {"ENGINE0"                     ,        0,      4,      807,    "R/W",  0,      0,      4ull,   4ull},
73256         {"ENGINE1"                     ,        4,      4,      807,    "R/W",  0,      0,      4ull,   4ull},
73257         {"ENGINE2"                     ,        8,      4,      807,    "R/W",  0,      0,      4ull,   4ull},
73258         {"ENGINE3"                     ,        12,     4,      807,    "R/W",  0,      0,      4ull,   4ull},
73259         {"ENGINE4"                     ,        16,     4,      807,    "R/W",  0,      0,      0ull,   0ull},
73260         {"ENGINE5"                     ,        20,     4,      807,    "R/W",  0,      0,      0ull,   0ull},
73261         {"ENGINE6"                     ,        24,     4,      807,    "R/W",  0,      0,      0ull,   0ull},
73262         {"ENGINE7"                     ,        28,     4,      807,    "R/W",  0,      0,      0ull,   0ull},
73263         {"ENGINE8"                     ,        32,     4,      807,    "R/W",  0,      0,      4ull,   4ull},
73264         {"ENGINE9"                     ,        36,     4,      807,    "R/W",  0,      0,      4ull,   4ull},
73265         {"RESERVED_40_63"              ,        40,     24,     807,    "RAZ",  1,      0,      0,      0ull},
73266         {"MASK"                        ,        0,      10,     808,    "R/W",  0,      0,      0ull,   0ull},
73267         {"RESERVED_10_63"              ,        10,     54,     808,    "RAZ",  1,      0,      0,      0ull},
73268         {"PARITY"                      ,        0,      1,      809,    "R/W1C",        0,      0,      0ull,   0ull},
73269         {"DOORBELL"                    ,        1,      1,      809,    "R/W1C",        0,      0,      0ull,   0ull},
73270         {"CURRZERO"                    ,        2,      1,      809,    "R/W1C",        0,      0,      0ull,   0ull},
73271         {"RESERVED_3_63"               ,        3,      61,     809,    "RAZ",  1,      0,      0,      0ull},
73272         {"ENA_PKO"                     ,        0,      1,      810,    "R/W",  0,      0,      0ull,   0ull},
73273         {"ENA_DWB"                     ,        1,      1,      810,    "R/W",  0,      0,      0ull,   0ull},
73274         {"STORE_BE"                    ,        2,      1,      810,    "R/W",  0,      0,      0ull,   0ull},
73275         {"RESET"                       ,        3,      1,      810,    "RAZ",  0,      0,      0ull,   0ull},
73276         {"RESERVED_4_63"               ,        4,      60,     810,    "RAZ",  1,      0,      0,      0ull},
73277         {"MODE0"                       ,        0,      3,      811,    "R/W",  0,      0,      2ull,   2ull},
73278         {"MODE1"                       ,        3,      3,      811,    "R/W",  0,      0,      0ull,   0ull},
73279         {"RESERVED_6_63"               ,        6,      58,     811,    "RAZ",  1,      0,      0,      0ull},
73280         {"PARITY"                      ,        0,      1,      812,    "R/W",  0,      0,      0ull,   0ull},
73281         {"DOORBELL"                    ,        1,      1,      812,    "R/W",  0,      0,      0ull,   0ull},
73282         {"CURRZERO"                    ,        2,      1,      812,    "R/W",  0,      0,      0ull,   0ull},
73283         {"RESERVED_3_63"               ,        3,      61,     812,    "RAZ",  1,      0,      0,      0ull},
73284         {"MODE"                        ,        0,      2,      813,    "R/W",  0,      0,      0ull,   0ull},
73285         {"RESERVED_2_63"               ,        2,      62,     813,    "RAZ",  1,      0,      0,      0ull},
73286         {"QID7"                        ,        0,      1,      814,    "R/W",  0,      0,      0ull,   0ull},
73287         {"IDX3"                        ,        1,      1,      814,    "R/W",  0,      0,      0ull,   0ull},
73288         {"RESERVED_2_63"               ,        2,      62,     814,    "RAZ",  1,      0,      0,      0ull},
73289         {"INDEX"                       ,        0,      8,      815,    "R/W",  0,      0,      0ull,   0ull},
73290         {"INC"                         ,        8,      8,      815,    "R/W",  0,      0,      0ull,   0ull},
73291         {"RESERVED_16_63"              ,        16,     48,     815,    "RAZ",  1,      0,      0,      0ull},
73292         {"ADR"                         ,        0,      1,      816,    "RO",   0,      0,      0ull,   0ull},
73293         {"PEND"                        ,        1,      1,      816,    "RO",   0,      0,      0ull,   0ull},
73294         {"NBR0"                        ,        2,      1,      816,    "RO",   0,      0,      0ull,   0ull},
73295         {"NBR1"                        ,        3,      1,      816,    "RO",   0,      0,      0ull,   0ull},
73296         {"FIDX"                        ,        4,      1,      816,    "RO",   0,      0,      0ull,   0ull},
73297         {"INDEX"                       ,        5,      1,      816,    "RO",   0,      0,      0ull,   0ull},
73298         {"NBT0"                        ,        6,      1,      816,    "RO",   0,      0,      0ull,   0ull},
73299         {"NBT1"                        ,        7,      1,      816,    "RO",   0,      0,      0ull,   0ull},
73300         {"CAM"                         ,        8,      1,      816,    "RO",   0,      0,      0ull,   0ull},
73301         {"RESERVED_9_15"               ,        9,      7,      816,    "RAZ",  1,      1,      0,      0},
73302         {"PP"                          ,        16,     4,      816,    "RO",   0,      0,      0ull,   0ull},
73303         {"RESERVED_20_63"              ,        20,     44,     816,    "RAZ",  1,      1,      0,      0},
73304         {"DS_PC"                       ,        0,      32,     817,    "R/W1C",        0,      1,      0ull,   0},
73305         {"RESERVED_32_63"              ,        32,     32,     817,    "RAZ",  1,      1,      0,      0},
73306         {"SBE"                         ,        0,      1,      818,    "R/W1C",        0,      0,      0ull,   0ull},
73307         {"DBE"                         ,        1,      1,      818,    "R/W1C",        0,      0,      0ull,   0ull},
73308         {"SBE_IE"                      ,        2,      1,      818,    "R/W",  0,      1,      0ull,   0},
73309         {"DBE_IE"                      ,        3,      1,      818,    "R/W",  0,      1,      0ull,   0},
73310         {"SYN"                         ,        4,      5,      818,    "RO",   1,      1,      0,      0},
73311         {"RESERVED_9_11"               ,        9,      3,      818,    "RAZ",  1,      1,      0,      0},
73312         {"RPE"                         ,        12,     1,      818,    "R/W1C",        0,      0,      0ull,   0ull},
73313         {"RPE_IE"                      ,        13,     1,      818,    "R/W",  0,      1,      0ull,   0},
73314         {"RESERVED_14_15"              ,        14,     2,      818,    "RAZ",  1,      1,      0,      0},
73315         {"IOP"                         ,        16,     13,     818,    "R/W1C",        0,      0,      0ull,   0ull},
73316         {"RESERVED_29_31"              ,        29,     3,      818,    "RAZ",  1,      1,      0,      0},
73317         {"IOP_IE"                      ,        32,     13,     818,    "R/W",  0,      1,      0ull,   0},
73318         {"RESERVED_45_63"              ,        45,     19,     818,    "RAZ",  1,      1,      0,      0},
73319         {"NBR_THR"                     ,        0,      5,      819,    "R/W",  0,      0,      2ull,   2ull},
73320         {"PFR_DIS"                     ,        5,      1,      819,    "R/W",  0,      0,      0ull,   0ull},
73321         {"RESERVED_6_63"               ,        6,      58,     819,    "RAZ",  1,      1,      0,      0},
73322         {"IQ_CNT"                      ,        0,      32,     820,    "RO",   0,      1,      0ull,   0},
73323         {"RESERVED_32_63"              ,        32,     32,     820,    "RAZ",  1,      1,      0,      0},
73324         {"IQ_CNT"                      ,        0,      32,     821,    "RO",   0,      1,      0ull,   0},
73325         {"RESERVED_32_63"              ,        32,     32,     821,    "RAZ",  1,      1,      0,      0},
73326         {"IQ_INT"                      ,        0,      8,      822,    "R/W1C",        0,      1,      0ull,   0},
73327         {"RESERVED_8_63"               ,        8,      56,     822,    "RAZ",  1,      1,      0,      0},
73328         {"INT_EN"                      ,        0,      8,      823,    "R/W",  0,      1,      0ull,   0},
73329         {"RESERVED_8_63"               ,        8,      56,     823,    "RAZ",  1,      1,      0,      0},
73330         {"IQ_THR"                      ,        0,      32,     824,    "R/W",  0,      1,      4294967295ull,  0},
73331         {"RESERVED_32_63"              ,        32,     32,     824,    "RAZ",  1,      1,      0,      0},
73332         {"NOS_CNT"                     ,        0,      10,     825,    "RO",   0,      1,      0ull,   0},
73333         {"RESERVED_10_63"              ,        10,     54,     825,    "RAZ",  1,      1,      0,      0},
73334         {"NW_TIM"                      ,        0,      10,     826,    "R/W",  0,      0,      0ull,   1023ull},
73335         {"RESERVED_10_63"              ,        10,     54,     826,    "RAZ",  1,      1,      0,      0},
73336         {"RST_MSK"                     ,        0,      8,      827,    "R/W",  0,      1,      0ull,   0},
73337         {"RESERVED_8_63"               ,        8,      56,     827,    "RAZ",  1,      1,      0,      0},
73338         {"GRP_MSK"                     ,        0,      16,     828,    "R/W",  0,      0,      65535ull,       65535ull},
73339         {"QOS0_PRI"                    ,        16,     4,      828,    "R/W",  0,      1,      0ull,   0},
73340         {"QOS1_PRI"                    ,        20,     4,      828,    "R/W",  0,      1,      0ull,   0},
73341         {"QOS2_PRI"                    ,        24,     4,      828,    "R/W",  0,      1,      0ull,   0},
73342         {"QOS3_PRI"                    ,        28,     4,      828,    "R/W",  0,      1,      0ull,   0},
73343         {"QOS4_PRI"                    ,        32,     4,      828,    "R/W",  0,      1,      0ull,   0},
73344         {"QOS5_PRI"                    ,        36,     4,      828,    "R/W",  0,      1,      0ull,   0},
73345         {"QOS6_PRI"                    ,        40,     4,      828,    "R/W",  0,      1,      0ull,   0},
73346         {"QOS7_PRI"                    ,        44,     4,      828,    "R/W",  0,      1,      0ull,   0},
73347         {"RESERVED_48_63"              ,        48,     16,     828,    "RAZ",  1,      1,      0,      0},
73348         {"RND"                         ,        0,      8,      829,    "R/W",  0,      1,      255ull, 0},
73349         {"RND_P1"                      ,        8,      8,      829,    "R/W",  0,      1,      255ull, 0},
73350         {"RND_P2"                      ,        16,     8,      829,    "R/W",  0,      1,      255ull, 0},
73351         {"RND_P3"                      ,        24,     8,      829,    "R/W",  0,      1,      255ull, 0},
73352         {"RESERVED_32_63"              ,        32,     32,     829,    "RAZ",  1,      1,      0,      0},
73353         {"MIN_THR"                     ,        0,      9,      830,    "R/W",  0,      1,      0ull,   0},
73354         {"RESERVED_9_11"               ,        9,      3,      830,    "RAZ",  1,      1,      0,      0},
73355         {"MAX_THR"                     ,        12,     9,      830,    "R/W",  0,      1,      511ull, 0},
73356         {"RESERVED_21_23"              ,        21,     3,      830,    "RAZ",  1,      1,      0,      0},
73357         {"FREE_CNT"                    ,        24,     10,     830,    "RO",   0,      1,      503ull, 0},
73358         {"RESERVED_34_35"              ,        34,     2,      830,    "RAZ",  1,      1,      0,      0},
73359         {"BUF_CNT"                     ,        36,     10,     830,    "RO",   0,      1,      0ull,   0},
73360         {"RESERVED_46_47"              ,        46,     2,      830,    "RAZ",  1,      1,      0,      0},
73361         {"DES_CNT"                     ,        48,     10,     830,    "RO",   0,      1,      0ull,   0},
73362         {"RESERVED_58_63"              ,        58,     6,      830,    "RAZ",  1,      1,      0,      0},
73363         {"TS_PC"                       ,        0,      32,     831,    "R/W1C",        0,      1,      0ull,   0},
73364         {"RESERVED_32_63"              ,        32,     32,     831,    "RAZ",  1,      1,      0,      0},
73365         {"WA_PC"                       ,        0,      32,     832,    "R/W1C",        0,      1,      0ull,   0},
73366         {"RESERVED_32_63"              ,        32,     32,     832,    "RAZ",  1,      1,      0,      0},
73367         {"WA_PC"                       ,        0,      32,     833,    "R/W1C",        0,      1,      0ull,   0},
73368         {"RESERVED_32_63"              ,        32,     32,     833,    "RAZ",  1,      1,      0,      0},
73369         {"WQ_INT"                      ,        0,      16,     834,    "R/W1C",        0,      1,      0ull,   0},
73370         {"IQ_DIS"                      ,        16,     16,     834,    "R/W1", 0,      1,      0ull,   0},
73371         {"RESERVED_32_63"              ,        32,     32,     834,    "RAZ",  1,      1,      0,      0},
73372         {"IQ_CNT"                      ,        0,      10,     835,    "RO",   0,      1,      0ull,   0},
73373         {"RESERVED_10_11"              ,        10,     2,      835,    "RAZ",  1,      1,      0,      0},
73374         {"DS_CNT"                      ,        12,     10,     835,    "RO",   0,      1,      0ull,   0},
73375         {"RESERVED_22_23"              ,        22,     2,      835,    "RAZ",  1,      1,      0,      0},
73376         {"TC_CNT"                      ,        24,     4,      835,    "RO",   0,      1,      0ull,   0},
73377         {"RESERVED_28_63"              ,        28,     36,     835,    "RAZ",  1,      1,      0,      0},
73378         {"RESERVED_0_7"                ,        0,      8,      836,    "RAZ",  1,      1,      0,      0},
73379         {"PC_THR"                      ,        8,      20,     836,    "R/W",  0,      1,      0ull,   0},
73380         {"RESERVED_28_31"              ,        28,     4,      836,    "RAZ",  1,      1,      0,      0},
73381         {"PC"                          ,        32,     28,     836,    "RO",   0,      1,      0ull,   0},
73382         {"RESERVED_60_63"              ,        60,     4,      836,    "RAZ",  1,      1,      0,      0},
73383         {"IQ_THR"                      ,        0,      9,      837,    "R/W",  0,      1,      0ull,   0},
73384         {"RESERVED_9_11"               ,        9,      3,      837,    "RAZ",  1,      1,      0,      0},
73385         {"DS_THR"                      ,        12,     9,      837,    "R/W",  0,      1,      0ull,   0},
73386         {"RESERVED_21_23"              ,        21,     3,      837,    "RAZ",  1,      1,      0,      0},
73387         {"TC_THR"                      ,        24,     4,      837,    "R/W",  0,      1,      0ull,   0},
73388         {"TC_EN"                       ,        28,     1,      837,    "R/W",  0,      1,      0ull,   0},
73389         {"RESERVED_29_63"              ,        29,     35,     837,    "RAZ",  1,      1,      0,      0},
73390         {"WS_PC"                       ,        0,      32,     838,    "R/W1C",        0,      1,      0ull,   0},
73391         {"RESERVED_32_63"              ,        32,     32,     838,    "RAZ",  1,      1,      0,      0},
73392         {"IWORD"                       ,        0,      64,     839,    "RO",   1,      1,      0,      0},
73393         {"P_DAT"                       ,        0,      64,     840,    "RO",   1,      1,      0,      0},
73394         {"Q_DAT"                       ,        0,      64,     841,    "RO",   1,      1,      0,      0},
73395         {"DAT"                         ,        0,      2,      842,    "RO",   1,      0,      0,      0ull},
73396         {"NCB_INB"                     ,        2,      2,      842,    "RO",   1,      0,      0,      0ull},
73397         {"NCB_OUB"                     ,        4,      1,      842,    "RO",   1,      0,      0,      0ull},
73398         {"STA"                         ,        5,      1,      842,    "RO",   1,      0,      0,      0ull},
73399         {"RESERVED_6_63"               ,        6,      58,     842,    "RAZ",  0,      0,      0ull,   0ull},
73400         {"PTR"                         ,        0,      33,     843,    "R/W",  0,      1,      0ull,   0},
73401         {"SIZE"                        ,        33,     13,     843,    "R/W",  0,      1,      0ull,   0},
73402         {"POOL"                        ,        46,     3,      843,    "R/W",  0,      1,      0ull,   0},
73403         {"DWB"                         ,        49,     9,      843,    "R/W",  0,      1,      0ull,   0},
73404         {"RESERVED_58_63"              ,        58,     6,      843,    "RAZ",  0,      0,      0ull,   0ull},
73405         {"RESET"                       ,        0,      1,      844,    "RAZ",  0,      0,      0ull,   0ull},
73406         {"STORE_LE"                    ,        1,      1,      844,    "R/W",  0,      0,      0ull,   0ull},
73407         {"MAX_READ"                    ,        2,      4,      844,    "R/W",  0,      0,      8ull,   8ull},
73408         {"RESERVED_6_63"               ,        6,      58,     844,    "RAZ",  0,      0,      0ull,   0ull},
73409         {"STATE"                       ,        0,      5,      845,    "RO",   1,      1,      0,      0},
73410         {"COMMIT"                      ,        5,      1,      845,    "RO",   1,      1,      0,      0},
73411         {"OWORDPV"                     ,        6,      1,      845,    "RO",   1,      1,      0,      0},
73412         {"OWORDQV"                     ,        7,      1,      845,    "RO",   1,      1,      0,      0},
73413         {"IWIDX"                       ,        8,      6,      845,    "RO",   1,      1,      0,      0},
73414         {"RESERVED_14_15"              ,        14,     2,      845,    "RAZ",  1,      1,      0,      0},
73415         {"IRIDX"                       ,        16,     6,      845,    "RO",   1,      1,      0,      0},
73416         {"RESERVED_22_31"              ,        22,     10,     845,    "RAZ",  1,      1,      0,      0},
73417         {"LOOP"                        ,        32,     25,     845,    "RO",   1,      1,      0,      0},
73418         {"RESERVED_57_63"              ,        57,     7,      845,    "RAZ",  1,      1,      0,      0},
73419         {"CWORD"                       ,        0,      64,     846,    "RO",   1,      1,      0,      0},
73420         {"PTR"                         ,        0,      40,     847,    "RO",   1,      1,      0,      0},
73421         {"SIZE"                        ,        40,     16,     847,    "RO",   1,      1,      0,      0},
73422         {"FLAGS"                       ,        56,     8,      847,    "RO",   1,      1,      0,      0},
73423         {"INDEX"                       ,        0,      8,      848,    "RO",   1,      1,      0,      0},
73424         {"SOD"                         ,        8,      1,      848,    "RO",   1,      1,      0,      0},
73425         {"EOD"                         ,        9,      1,      848,    "RO",   1,      1,      0,      0},
73426         {"WC"                          ,        10,     1,      848,    "RO",   1,      1,      0,      0},
73427         {"P"                           ,        11,     1,      848,    "RO",   1,      1,      0,      0},
73428         {"Q"                           ,        12,     1,      848,    "RO",   1,      1,      0,      0},
73429         {"RESERVED_13_63"              ,        13,     51,     848,    "RAZ",  0,      0,      0ull,   0ull},
73430         {"ASSERTS"                     ,        0,      15,     849,    "RO",   1,      1,      0,      0},
73431         {"RESERVED_15_63"              ,        15,     49,     849,    "RAZ",  0,      0,      0ull,   0ull},
73432         {"OWORDP"                      ,        0,      64,     850,    "RO",   1,      1,      0,      0},
73433         {"OWORDQ"                      ,        0,      64,     851,    "RO",   1,      1,      0,      0},
73434         {"RWORD"                       ,        0,      64,     852,    "RO",   1,      1,      0,      0},
73435         {"N0CREDS"                     ,        0,      4,      853,    "RO",   0,      0,      8ull,   0ull},
73436         {"N1CREDS"                     ,        4,      4,      853,    "RO",   0,      0,      8ull,   0ull},
73437         {"POWCREDS"                    ,        8,      2,      853,    "RO",   0,      0,      2ull,   0ull},
73438         {"RESERVED_10_11"              ,        10,     2,      853,    "RAZ",  0,      0,      0ull,   0ull},
73439         {"FPACREDS"                    ,        12,     2,      853,    "RO",   0,      0,      1ull,   0ull},
73440         {"WCCREDS"                     ,        14,     2,      853,    "RO",   0,      0,      0ull,   0ull},
73441         {"NIWIDX0"                     ,        16,     4,      853,    "RO",   1,      1,      0,      0},
73442         {"NIRIDX0"                     ,        20,     4,      853,    "RO",   1,      1,      0,      0},
73443         {"NIWIDX1"                     ,        24,     4,      853,    "RO",   1,      1,      0,      0},
73444         {"NIRIDX1"                     ,        28,     4,      853,    "RO",   1,      1,      0,      0},
73445         {"NIRVAL6"                     ,        32,     5,      853,    "RO",   1,      1,      0,      0},
73446         {"NIRARB6"                     ,        37,     1,      853,    "RO",   1,      1,      0,      0},
73447         {"NIRQUE6"                     ,        38,     2,      853,    "RO",   1,      1,      0,      0},
73448         {"NIROPC6"                     ,        40,     3,      853,    "RO",   1,      1,      0,      0},
73449         {"NIRVAL7"                     ,        43,     5,      853,    "RO",   1,      1,      0,      0},
73450         {"NIRQUE7"                     ,        48,     2,      853,    "RO",   1,      1,      0,      0},
73451         {"NIROPC7"                     ,        50,     3,      853,    "RO",   1,      1,      0,      0},
73452         {"RESERVED_53_63"              ,        53,     11,     853,    "RAZ",  0,      0,      0ull,   0ull},
73453         {"PTR"                         ,        0,      40,     854,    "RO",   1,      1,      0,      0},
73454         {"SIZE"                        ,        40,     16,     854,    "RO",   1,      1,      0,      0},
73455         {"CNT"                         ,        56,     8,      854,    "RO",   1,      1,      0,      0},
73456         {"CNT"                         ,        0,      15,     855,    "RO",   1,      1,      0,      0},
73457         {"RESERVED_15_63"              ,        15,     49,     855,    "RAZ",  0,      0,      0ull,   0ull},
73458         {"PTR"                         ,        0,      40,     856,    "RO",   1,      1,      0,      0},
73459         {"SIZE"                        ,        40,     16,     856,    "RO",   1,      1,      0,      0},
73460         {"FLAGS"                       ,        56,     8,      856,    "RO",   1,      1,      0,      0},
73461         {"INDEX"                       ,        0,      8,      857,    "RO",   1,      1,      0,      0},
73462         {"MUL"                         ,        8,      8,      857,    "RO",   1,      1,      0,      0},
73463         {"P"                           ,        16,     1,      857,    "RO",   1,      1,      0,      0},
73464         {"Q"                           ,        17,     1,      857,    "RO",   1,      1,      0,      0},
73465         {"INI"                         ,        18,     1,      857,    "RO",   1,      1,      0,      0},
73466         {"EOD"                         ,        19,     1,      857,    "RO",   1,      1,      0,      0},
73467         {"RESERVED_20_63"              ,        20,     44,     857,    "RAZ",  0,      0,      0ull,   0ull},
73468         {"DOORBELL"                    ,        0,      1,      858,    "R/W1C",        0,      0,      0ull,   0ull},
73469         {"RESERVED_1_63"               ,        1,      63,     858,    "RAZ",  0,      0,      0ull,   0ull},
73470         {"DOORBELL"                    ,        0,      1,      859,    "R/W",  0,      0,      0ull,   0ull},
73471         {"RESERVED_1_63"               ,        1,      63,     859,    "RAZ",  0,      0,      0ull,   0ull},
73472         {"COEFFS"                      ,        0,      8,      860,    "R/W",  0,      0,      29ull,  29ull},
73473         {"RESERVED_8_63"               ,        8,      56,     860,    "RAZ",  0,      0,      0ull,   0ull},
73474         {"INDEX"                       ,        0,      16,     861,    "R/W",  0,      0,      0ull,   0ull},
73475         {"INC"                         ,        16,     16,     861,    "R/W",  0,      0,      0ull,   0ull},
73476         {"RESERVED_32_63"              ,        32,     32,     861,    "RAZ",  0,      0,      0ull,   0ull},
73477         {"MEM"                         ,        0,      1,      862,    "RO",   0,      0,      0ull,   0ull},
73478         {"RRC"                         ,        1,      1,      862,    "RO",   0,      0,      0ull,   0ull},
73479         {"RESERVED_2_63"               ,        2,      62,     862,    "RAZ",  1,      1,      0,      0},
73480         {"ENT_EN"                      ,        0,      1,      863,    "R/W",  0,      0,      0ull,   0ull},
73481         {"RNG_EN"                      ,        1,      1,      863,    "R/W",  0,      0,      0ull,   0ull},
73482         {"RNM_RST"                     ,        2,      1,      863,    "R/W",  0,      0,      0ull,   0ull},
73483         {"RNG_RST"                     ,        3,      1,      863,    "R/W",  0,      0,      0ull,   0ull},
73484         {"EXP_ENT"                     ,        4,      1,      863,    "R/W",  0,      0,      0ull,   0ull},
73485         {"ENT_SEL"                     ,        5,      4,      863,    "R/W",  0,      0,      0ull,   0ull},
73486         {"RESERVED_9_63"               ,        9,      55,     863,    "RAZ",  1,      1,      0,      0},
73487         {"PHASE"                       ,        0,      8,      864,    "R/W",  0,      0,      100ull, 100ull},
73488         {"SAMPLE"                      ,        8,      4,      864,    "R/W",  0,      0,      2ull,   2ull},
73489         {"PREAMBLE"                    ,        12,     1,      864,    "R/W",  0,      0,      1ull,   1ull},
73490         {"CLK_IDLE"                    ,        13,     1,      864,    "R/W",  0,      0,      0ull,   0ull},
73491         {"RESERVED_14_14"              ,        14,     1,      864,    "RAZ",  1,      1,      0,      0},
73492         {"SAMPLE_MODE"                 ,        15,     1,      864,    "R/W",  0,      0,      0ull,   0ull},
73493         {"SAMPLE_HI"                   ,        16,     5,      864,    "R/W",  0,      0,      0ull,   0ull},
73494         {"RESERVED_21_23"              ,        21,     3,      864,    "RAZ",  1,      1,      0,      0},
73495         {"MODE"                        ,        24,     1,      864,    "R/W",  0,      0,      0ull,   0ull},
73496         {"RESERVED_25_63"              ,        25,     39,     864,    "RAZ",  1,      1,      0,      0},
73497         {"REG_ADR"                     ,        0,      5,      865,    "R/W",  0,      1,      0ull,   0},
73498         {"RESERVED_5_7"                ,        5,      3,      865,    "RAZ",  1,      1,      0,      0},
73499         {"PHY_ADR"                     ,        8,      5,      865,    "R/W",  0,      1,      0ull,   0},
73500         {"RESERVED_13_15"              ,        13,     3,      865,    "RAZ",  1,      1,      0,      0},
73501         {"PHY_OP"                      ,        16,     2,      865,    "R/W",  0,      1,      0ull,   0},
73502         {"RESERVED_18_63"              ,        18,     46,     865,    "RAZ",  1,      1,      0,      0},
73503         {"EN"                          ,        0,      1,      866,    "R/W",  0,      0,      0ull,   1ull},
73504         {"RESERVED_1_63"               ,        1,      63,     866,    "RAZ",  1,      1,      0,      0},
73505         {"DAT"                         ,        0,      16,     867,    "RO",   0,      1,      0ull,   0},
73506         {"VAL"                         ,        16,     1,      867,    "RO",   0,      1,      0ull,   0},
73507         {"PENDING"                     ,        17,     1,      867,    "RO",   0,      1,      0ull,   0},
73508         {"RESERVED_18_63"              ,        18,     46,     867,    "RAZ",  1,      1,      0,      0},
73509         {"DAT"                         ,        0,      16,     868,    "R/W",  0,      1,      0ull,   0},
73510         {"VAL"                         ,        16,     1,      868,    "RO",   0,      1,      0ull,   0},
73511         {"PENDING"                     ,        17,     1,      868,    "RO",   0,      1,      0ull,   0},
73512         {"RESERVED_18_63"              ,        18,     46,     868,    "RAZ",  1,      1,      0,      0},
73513         {"INTERVAL"                    ,        0,      22,     869,    "RO",   1,      0,      0,      0ull},
73514         {"RESERVED_22_23"              ,        22,     2,      869,    "RAZ",  1,      0,      0,      0ull},
73515         {"COUNT"                       ,        24,     22,     869,    "RO",   1,      0,      0,      0ull},
73516         {"RESERVED_46_46"              ,        46,     1,      869,    "RAZ",  1,      0,      0,      0ull},
73517         {"ENA"                         ,        47,     1,      869,    "RO",   1,      0,      0,      0ull},
73518         {"RESERVED_48_63"              ,        48,     16,     869,    "RAZ",  1,      0,      0,      0ull},
73519         {"BSIZE"                       ,        0,      20,     870,    "RO",   1,      0,      0,      0ull},
73520         {"BASE"                        ,        20,     31,     870,    "RO",   1,      0,      0,      0ull},
73521         {"BUCKET"                      ,        51,     13,     870,    "RO",   1,      0,      0,      0ull},
73522         {"BUCKET"                      ,        0,      7,      871,    "RO",   1,      0,      0,      0ull},
73523         {"RESERVED_7_7"                ,        7,      1,      871,    "RAZ",  1,      0,      0,      0ull},
73524         {"CSIZE"                       ,        8,      13,     871,    "RO",   1,      0,      0,      0ull},
73525         {"CPOOL"                       ,        21,     3,      871,    "RO",   1,      0,      0,      0ull},
73526         {"RESERVED_24_63"              ,        24,     40,     871,    "RAZ",  1,      0,      0,      0ull},
73527         {"RING"                        ,        0,      4,      872,    "R/W",  0,      0,      0ull,   0ull},
73528         {"NUM_BUCKETS"                 ,        4,      20,     872,    "R/W",  0,      0,      0ull,   0ull},
73529         {"FIRST_BUCKET"                ,        24,     31,     872,    "R/W",  0,      0,      0ull,   0ull},
73530         {"RESERVED_55_63"              ,        55,     9,      872,    "RAZ",  1,      0,      0,      0ull},
73531         {"RING"                        ,        0,      4,      873,    "R/W",  0,      0,      0ull,   0ull},
73532         {"INTERVAL"                    ,        4,      22,     873,    "R/W",  0,      0,      0ull,   0ull},
73533         {"WORDS_PER_CHUNK"             ,        26,     13,     873,    "R/W",  0,      0,      0ull,   0ull},
73534         {"POOL"                        ,        39,     3,      873,    "R/W",  0,      0,      0ull,   0ull},
73535         {"ENABLE"                      ,        42,     1,      873,    "R/W",  0,      0,      0ull,   0ull},
73536         {"RESERVED_43_63"              ,        43,     21,     873,    "RAZ",  1,      0,      0,      0ull},
73537         {"CTL"                         ,        0,      1,      874,    "RO",   1,      0,      0,      0ull},
73538         {"NCB"                         ,        1,      1,      874,    "RO",   1,      0,      0,      0ull},
73539         {"STA"                         ,        2,      2,      874,    "RO",   1,      0,      0,      0ull},
73540         {"RESERVED_4_63"               ,        4,      60,     874,    "RAZ",  1,      0,      0,      0ull},
73541         {"MASK"                        ,        0,      16,     875,    "R/W1C",        0,      0,      0ull,   0ull},
73542         {"RESERVED_16_63"              ,        16,     48,     875,    "RAZ",  1,      0,      0,      0ull},
73543         {"ENABLE_TIMERS"               ,        0,      1,      876,    "R/W",  0,      0,      0ull,   0ull},
73544         {"ENABLE_DWB"                  ,        1,      1,      876,    "R/W",  0,      0,      0ull,   0ull},
73545         {"RESET"                       ,        2,      1,      876,    "RAZ",  0,      0,      0ull,   0ull},
73546         {"RESERVED_3_63"               ,        3,      61,     876,    "RAZ",  1,      0,      0,      0ull},
73547         {"MASK"                        ,        0,      16,     877,    "R/W",  0,      0,      0ull,   0ull},
73548         {"RESERVED_16_63"              ,        16,     48,     877,    "RAZ",  1,      0,      0,      0ull},
73549         {"INDEX"                       ,        0,      8,      878,    "R/W",  0,      0,      0ull,   0ull},
73550         {"INC"                         ,        8,      8,      878,    "R/W",  0,      0,      0ull,   0ull},
73551         {"RESERVED_16_63"              ,        16,     48,     878,    "RAZ",  1,      0,      0,      0ull},
73552         {"TDF0"                        ,        0,      1,      879,    "RO",   0,      0,      0ull,   0ull},
73553         {"TDF1"                        ,        1,      1,      879,    "RO",   0,      0,      0ull,   0ull},
73554         {"TCF"                         ,        2,      1,      879,    "RO",   0,      0,      0ull,   0ull},
73555         {"RESERVED_3_63"               ,        3,      61,     879,    "RAZ",  0,      0,      0ull,   0ull},
73556         {"ENA"                         ,        0,      1,      880,    "R/W",  0,      0,      0ull,   0ull},
73557         {"WRAP"                        ,        1,      1,      880,    "R/W",  0,      0,      0ull,   0ull},
73558         {"TRIG_CTL"                    ,        2,      2,      880,    "R/W",  0,      0,      0ull,   0ull},
73559         {"TIME_GRN"                    ,        4,      3,      880,    "R/W",  0,      0,      0ull,   0ull},
73560         {"FULL_THR"                    ,        7,      2,      880,    "R/W",  0,      0,      0ull,   0ull},
73561         {"CIU_TRG"                     ,        9,      1,      880,    "R/W",  0,      0,      0ull,   0ull},
73562         {"CIU_THR"                     ,        10,     1,      880,    "R/W",  0,      0,      0ull,   0ull},
73563         {"MCD0_TRG"                    ,        11,     1,      880,    "R/W",  0,      0,      0ull,   0ull},
73564         {"MCD0_THR"                    ,        12,     1,      880,    "R/W",  0,      0,      0ull,   0ull},
73565         {"MCD0_ENA"                    ,        13,     1,      880,    "R/W",  0,      0,      0ull,   0ull},
73566         {"IGNORE_O"                    ,        14,     1,      880,    "R/W",  0,      0,      0ull,   0ull},
73567         {"RESERVED_15_63"              ,        15,     49,     880,    "RAZ",  0,      0,      0ull,   0ull},
73568         {"WPTR"                        ,        0,      8,      881,    "RO",   0,      0,      0ull,   0ull},
73569         {"RPTR"                        ,        8,      8,      881,    "RO",   0,      0,      0ull,   0ull},
73570         {"CYCLES"                      ,        16,     48,     881,    "RO",   0,      0,      0ull,   0ull},
73571         {"WPTR"                        ,        0,      10,     882,    "RO",   0,      0,      0ull,   0ull},
73572         {"RESERVED_10_11"              ,        10,     2,      882,    "RAZ",  0,      0,      0ull,   0ull},
73573         {"RPTR"                        ,        12,     10,     882,    "RO",   0,      0,      0ull,   0ull},
73574         {"RESERVED_22_23"              ,        22,     2,      882,    "RAZ",  0,      0,      0ull,   0ull},
73575         {"CYCLES"                      ,        24,     40,     882,    "RO",   0,      0,      0ull,   0ull},
73576         {"ADR"                         ,        0,      36,     883,    "R/W",  0,      1,      0ull,   0},
73577         {"RESERVED_36_63"              ,        36,     28,     883,    "RAZ",  0,      0,      0ull,   0ull},
73578         {"ADR"                         ,        0,      36,     884,    "R/W",  0,      0,      0ull,   0ull},
73579         {"RESERVED_36_63"              ,        36,     28,     884,    "RAZ",  0,      0,      0ull,   0ull},
73580         {"DWB"                         ,        0,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73581         {"PL2"                         ,        1,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73582         {"PSL1"                        ,        2,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73583         {"LDD"                         ,        3,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73584         {"LDI"                         ,        4,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73585         {"LDT"                         ,        5,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73586         {"STF"                         ,        6,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73587         {"STC"                         ,        7,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73588         {"STP"                         ,        8,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73589         {"STT"                         ,        9,      1,      885,    "R/W",  0,      0,      0ull,   1ull},
73590         {"IOBLD8"                      ,        10,     1,      885,    "R/W",  0,      0,      0ull,   1ull},
73591         {"IOBLD16"                     ,        11,     1,      885,    "R/W",  0,      0,      0ull,   1ull},
73592         {"IOBLD32"                     ,        12,     1,      885,    "R/W",  0,      0,      0ull,   1ull},
73593         {"IOBLD64"                     ,        13,     1,      885,    "R/W",  0,      0,      0ull,   1ull},
73594         {"IOBST"                       ,        14,     1,      885,    "R/W",  0,      0,      0ull,   1ull},
73595         {"IOBDMA"                      ,        15,     1,      885,    "R/W",  0,      0,      0ull,   1ull},
73596         {"SAA"                         ,        16,     1,      885,    "R/W",  0,      0,      0ull,   1ull},
73597         {"RESERVED_17_63"              ,        17,     47,     885,    "RAZ",  0,      0,      0ull,   0ull},
73598         {"MIO"                         ,        0,      1,      886,    "R/W",  0,      0,      0ull,   1ull},
73599         {"ILLEGAL3"                    ,        1,      2,      886,    "R/W",  0,      0,      0ull,   3ull},
73600         {"PCI"                         ,        3,      1,      886,    "R/W",  0,      0,      0ull,   1ull},
73601         {"KEY"                         ,        4,      1,      886,    "R/W",  0,      0,      0ull,   1ull},
73602         {"FPA"                         ,        5,      1,      886,    "R/W",  0,      0,      0ull,   1ull},
73603         {"DFA"                         ,        6,      1,      886,    "R/W",  0,      0,      0ull,   1ull},
73604         {"ZIP"                         ,        7,      1,      886,    "R/W",  0,      0,      0ull,   1ull},
73605         {"RNG"                         ,        8,      1,      886,    "R/W",  0,      0,      0ull,   1ull},
73606         {"ILLEGAL2"                    ,        9,      3,      886,    "R/W",  0,      0,      0ull,   7ull},
73607         {"POW"                         ,        12,     1,      886,    "R/W",  0,      0,      0ull,   1ull},
73608         {"ILLEGAL"                     ,        13,     19,     886,    "R/W",  0,      0,      0ull,   524287ull},
73609         {"RESERVED_32_63"              ,        32,     32,     886,    "RAZ",  0,      0,      0ull,   0ull},
73610         {"PP"                          ,        0,      16,     887,    "R/W",  0,      0,      0ull,   0ull},
73611         {"PKI"                         ,        16,     1,      887,    "R/W",  0,      0,      0ull,   0ull},
73612         {"PKO"                         ,        17,     1,      887,    "R/W",  0,      0,      0ull,   0ull},
73613         {"IOBREQ"                      ,        18,     1,      887,    "R/W",  0,      0,      0ull,   0ull},
73614         {"DWB"                         ,        19,     1,      887,    "R/W",  0,      0,      0ull,   0ull},
73615         {"RESERVED_20_63"              ,        20,     44,     887,    "RAZ",  0,      0,      0ull,   0ull},
73616         {"CIU_TRG"                     ,        0,      1,      888,    "R/W1C",        0,      0,      0ull,   0ull},
73617         {"CIU_THR"                     ,        1,      1,      888,    "R/W1C",        0,      0,      0ull,   0ull},
73618         {"MCD0_TRG"                    ,        2,      1,      888,    "R/W1C",        0,      0,      0ull,   0ull},
73619         {"MCD0_THR"                    ,        3,      1,      888,    "R/W1C",        0,      0,      0ull,   0ull},
73620         {"RESERVED_4_63"               ,        4,      60,     888,    "RAZ",  0,      0,      0ull,   0ull},
73621         {"DATA"                        ,        0,      64,     889,    "RO",   0,      0,      0ull,   0ull},
73622         {"ADR"                         ,        0,      36,     890,    "R/W",  0,      1,      0ull,   0},
73623         {"RESERVED_36_63"              ,        36,     28,     890,    "RAZ",  0,      0,      0ull,   0ull},
73624         {"ADR"                         ,        0,      36,     891,    "R/W",  0,      0,      0ull,   0ull},
73625         {"RESERVED_36_63"              ,        36,     28,     891,    "RAZ",  0,      0,      0ull,   0ull},
73626         {"DWB"                         ,        0,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73627         {"PL2"                         ,        1,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73628         {"PSL1"                        ,        2,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73629         {"LDD"                         ,        3,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73630         {"LDI"                         ,        4,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73631         {"LDT"                         ,        5,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73632         {"STF"                         ,        6,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73633         {"STC"                         ,        7,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73634         {"STP"                         ,        8,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73635         {"STT"                         ,        9,      1,      892,    "R/W",  0,      0,      0ull,   1ull},
73636         {"IOBLD8"                      ,        10,     1,      892,    "R/W",  0,      0,      0ull,   1ull},
73637         {"IOBLD16"                     ,        11,     1,      892,    "R/W",  0,      0,      0ull,   1ull},
73638         {"IOBLD32"                     ,        12,     1,      892,    "R/W",  0,      0,      0ull,   1ull},
73639         {"IOBLD64"                     ,        13,     1,      892,    "R/W",  0,      0,      0ull,   1ull},
73640         {"IOBST"                       ,        14,     1,      892,    "R/W",  0,      0,      0ull,   1ull},
73641         {"IOBDMA"                      ,        15,     1,      892,    "R/W",  0,      0,      0ull,   1ull},
73642         {"SAA"                         ,        16,     1,      892,    "R/W",  0,      0,      0ull,   1ull},
73643         {"RESERVED_17_63"              ,        17,     47,     892,    "RAZ",  0,      0,      0ull,   0ull},
73644         {"MIO"                         ,        0,      1,      893,    "R/W",  0,      0,      0ull,   1ull},
73645         {"ILLEGAL3"                    ,        1,      2,      893,    "R/W",  0,      0,      0ull,   3ull},
73646         {"PCI"                         ,        3,      1,      893,    "R/W",  0,      0,      0ull,   1ull},
73647         {"KEY"                         ,        4,      1,      893,    "R/W",  0,      0,      0ull,   1ull},
73648         {"FPA"                         ,        5,      1,      893,    "R/W",  0,      0,      0ull,   1ull},
73649         {"DFA"                         ,        6,      1,      893,    "R/W",  0,      0,      0ull,   1ull},
73650         {"ZIP"                         ,        7,      1,      893,    "R/W",  0,      0,      0ull,   1ull},
73651         {"RNG"                         ,        8,      1,      893,    "R/W",  0,      0,      0ull,   1ull},
73652         {"ILLEGAL2"                    ,        9,      3,      893,    "R/W",  0,      0,      0ull,   7ull},
73653         {"POW"                         ,        12,     1,      893,    "R/W",  0,      0,      0ull,   1ull},
73654         {"ILLEGAL"                     ,        13,     19,     893,    "R/W",  0,      0,      0ull,   524287ull},
73655         {"RESERVED_32_63"              ,        32,     32,     893,    "RAZ",  0,      0,      0ull,   0ull},
73656         {"PP"                          ,        0,      16,     894,    "R/W",  0,      0,      0ull,   0ull},
73657         {"PKI"                         ,        16,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
73658         {"PKO"                         ,        17,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
73659         {"IOBREQ"                      ,        18,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
73660         {"DWB"                         ,        19,     1,      894,    "R/W",  0,      0,      0ull,   0ull},
73661         {"RESERVED_20_63"              ,        20,     44,     894,    "RAZ",  0,      0,      0ull,   0ull},
73662         {"ADR"                         ,        0,      36,     895,    "R/W",  0,      1,      0ull,   0},
73663         {"RESERVED_36_63"              ,        36,     28,     895,    "RAZ",  0,      0,      0ull,   0ull},
73664         {"ADR"                         ,        0,      36,     896,    "R/W",  0,      0,      0ull,   0ull},
73665         {"RESERVED_36_63"              ,        36,     28,     896,    "RAZ",  0,      0,      0ull,   0ull},
73666         {"DWB"                         ,        0,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73667         {"PL2"                         ,        1,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73668         {"PSL1"                        ,        2,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73669         {"LDD"                         ,        3,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73670         {"LDI"                         ,        4,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73671         {"LDT"                         ,        5,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73672         {"STF"                         ,        6,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73673         {"STC"                         ,        7,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73674         {"STP"                         ,        8,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73675         {"STT"                         ,        9,      1,      897,    "R/W",  0,      0,      0ull,   1ull},
73676         {"IOBLD8"                      ,        10,     1,      897,    "R/W",  0,      0,      0ull,   1ull},
73677         {"IOBLD16"                     ,        11,     1,      897,    "R/W",  0,      0,      0ull,   1ull},
73678         {"IOBLD32"                     ,        12,     1,      897,    "R/W",  0,      0,      0ull,   1ull},
73679         {"IOBLD64"                     ,        13,     1,      897,    "R/W",  0,      0,      0ull,   1ull},
73680         {"IOBST"                       ,        14,     1,      897,    "R/W",  0,      0,      0ull,   1ull},
73681         {"IOBDMA"                      ,        15,     1,      897,    "R/W",  0,      0,      0ull,   1ull},
73682         {"SAA"                         ,        16,     1,      897,    "R/W",  0,      0,      0ull,   1ull},
73683         {"RESERVED_17_63"              ,        17,     47,     897,    "RAZ",  0,      0,      0ull,   0ull},
73684         {"MIO"                         ,        0,      1,      898,    "R/W",  0,      0,      0ull,   1ull},
73685         {"ILLEGAL3"                    ,        1,      2,      898,    "R/W",  0,      0,      0ull,   3ull},
73686         {"PCI"                         ,        3,      1,      898,    "R/W",  0,      0,      0ull,   1ull},
73687         {"KEY"                         ,        4,      1,      898,    "R/W",  0,      0,      0ull,   1ull},
73688         {"FPA"                         ,        5,      1,      898,    "R/W",  0,      0,      0ull,   1ull},
73689         {"DFA"                         ,        6,      1,      898,    "R/W",  0,      0,      0ull,   1ull},
73690         {"ZIP"                         ,        7,      1,      898,    "R/W",  0,      0,      0ull,   1ull},
73691         {"RNG"                         ,        8,      1,      898,    "R/W",  0,      0,      0ull,   1ull},
73692         {"ILLEGAL2"                    ,        9,      3,      898,    "R/W",  0,      0,      0ull,   7ull},
73693         {"POW"                         ,        12,     1,      898,    "R/W",  0,      0,      0ull,   1ull},
73694         {"ILLEGAL"                     ,        13,     19,     898,    "R/W",  0,      0,      0ull,   524287ull},
73695         {"RESERVED_32_63"              ,        32,     32,     898,    "RAZ",  0,      0,      0ull,   0ull},
73696         {"PP"                          ,        0,      16,     899,    "R/W",  0,      0,      0ull,   0ull},
73697         {"PKI"                         ,        16,     1,      899,    "R/W",  0,      0,      0ull,   0ull},
73698         {"PKO"                         ,        17,     1,      899,    "R/W",  0,      0,      0ull,   0ull},
73699         {"IOBREQ"                      ,        18,     1,      899,    "R/W",  0,      0,      0ull,   0ull},
73700         {"DWB"                         ,        19,     1,      899,    "R/W",  0,      0,      0ull,   0ull},
73701         {"RESERVED_20_63"              ,        20,     44,     899,    "RAZ",  0,      0,      0ull,   0ull},
73702         {"INEPINT"                     ,        0,      16,     900,    "RO",   0,      0,      0ull,   0ull},
73703         {"OUTEPINT"                    ,        16,     16,     900,    "RO",   0,      0,      0ull,   0ull},
73704         {"INEPMSK"                     ,        0,      16,     901,    "R/W",  0,      0,      0ull,   0ull},
73705         {"OUTEPMSK"                    ,        16,     16,     901,    "R/W",  0,      0,      0ull,   0ull},
73706         {"DEVSPD"                      ,        0,      2,      902,    "R/W",  0,      0,      0ull,   0ull},
73707         {"NZSTSOUTHSHK"                ,        2,      1,      902,    "R/W",  0,      0,      0ull,   0ull},
73708         {"RESERVED_3_3"                ,        3,      1,      902,    "RAZ",  1,      1,      0,      0},
73709         {"DEVADDR"                     ,        4,      7,      902,    "R/W",  0,      0,      0ull,   0ull},
73710         {"PERFRINT"                    ,        11,     2,      902,    "R/W",  0,      0,      0ull,   0ull},
73711         {"RESERVED_13_17"              ,        13,     5,      902,    "RAZ",  1,      1,      0,      0},
73712         {"EPMISCNT"                    ,        18,     5,      902,    "R/W",  0,      0,      8ull,   0ull},
73713         {"RESERVED_23_31"              ,        23,     9,      902,    "RAZ",  1,      1,      0,      0},
73714         {"RMTWKUPSIG"                  ,        0,      1,      903,    "R/W",  0,      0,      0ull,   0ull},
73715         {"SFTDISCON"                   ,        1,      1,      903,    "R/W",  0,      0,      0ull,   0ull},
73716         {"GNPINNAKSTS"                 ,        2,      1,      903,    "RO",   0,      0,      0ull,   0ull},
73717         {"GOUTNAKSTS"                  ,        3,      1,      903,    "RO",   0,      0,      0ull,   0ull},
73718         {"TSTCTL"                      ,        4,      3,      903,    "R/W",  0,      0,      0ull,   0ull},
73719         {"SGNPINNAK"                   ,        7,      1,      903,    "WO",   0,      0,      0ull,   0ull},
73720         {"CGNPINNAK"                   ,        8,      1,      903,    "WO",   0,      0,      0ull,   0ull},
73721         {"SGOUTNAK"                    ,        9,      1,      903,    "WO",   0,      0,      0ull,   0ull},
73722         {"CGOUTNAK"                    ,        10,     1,      903,    "WO",   0,      0,      0ull,   0ull},
73723         {"PWRONPRGDONE"                ,        11,     1,      903,    "R/W",  0,      0,      0ull,   0ull},
73724         {"RESERVED_12_31"              ,        12,     20,     903,    "RAZ",  1,      1,      0,      0},
73725         {"MPS"                         ,        0,      11,     904,    "R/W",  0,      0,      0ull,   0ull},
73726         {"NEXTEP"                      ,        11,     4,      904,    "R/W",  0,      0,      0ull,   0ull},
73727         {"USBACTEP"                    ,        15,     1,      904,    "R/W",  0,      0,      1ull,   0ull},
73728         {"DPID"                        ,        16,     1,      904,    "RO",   0,      0,      0ull,   0ull},
73729         {"NAKSTS"                      ,        17,     1,      904,    "RO",   0,      0,      0ull,   0ull},
73730         {"EPTYPE"                      ,        18,     2,      904,    "R/W",  0,      0,      0ull,   0ull},
73731         {"RESERVED_20_20"              ,        20,     1,      904,    "RAZ",  1,      1,      0,      0},
73732         {"STALL"                       ,        21,     1,      904,    "R/W",  0,      0,      0ull,   0ull},
73733         {"TXFNUM"                      ,        22,     4,      904,    "R/W",  0,      0,      0ull,   0ull},
73734         {"CNAK"                        ,        26,     1,      904,    "WO",   0,      0,      0ull,   0ull},
73735         {"SNAK"                        ,        27,     1,      904,    "WO",   0,      0,      0ull,   0ull},
73736         {"SETD0PID"                    ,        28,     1,      904,    "WO",   0,      0,      0ull,   0ull},
73737         {"SETD1PID"                    ,        29,     1,      904,    "WO",   0,      0,      0ull,   0ull},
73738         {"EPDIS"                       ,        30,     1,      904,    "R/W",  0,      0,      0ull,   0ull},
73739         {"EPENA"                       ,        31,     1,      904,    "R/W",  0,      0,      0ull,   0ull},
73740         {"XFERCOMPL"                   ,        0,      1,      905,    "R/W1C",        0,      0,      0ull,   0ull},
73741         {"EPDISBLD"                    ,        1,      1,      905,    "R/W1C",        0,      0,      0ull,   0ull},
73742         {"AHBERR"                      ,        2,      1,      905,    "R/W1C",        0,      0,      0ull,   0ull},
73743         {"TIMEOUT"                     ,        3,      1,      905,    "R/W1C",        0,      0,      0ull,   0ull},
73744         {"INTKNTXFEMP"                 ,        4,      1,      905,    "R/W1C",        0,      0,      0ull,   0ull},
73745         {"INTKNEPMIS"                  ,        5,      1,      905,    "R/W1C",        0,      0,      0ull,   0ull},
73746         {"INEPNAKEFF"                  ,        6,      1,      905,    "RO",   0,      0,      0ull,   0ull},
73747         {"RESERVED_7_31"               ,        7,      25,     905,    "RAZ",  1,      1,      0,      0},
73748         {"XFERCOMPLMSK"                ,        0,      1,      906,    "R/W",  0,      0,      0ull,   0ull},
73749         {"EPDISBLDMSK"                 ,        1,      1,      906,    "R/W",  0,      0,      0ull,   0ull},
73750         {"AHBERRMSK"                   ,        2,      1,      906,    "R/W",  0,      0,      0ull,   0ull},
73751         {"TIMEOUTMSK"                  ,        3,      1,      906,    "R/W",  0,      0,      0ull,   0ull},
73752         {"INTKNTXFEMPMSK"              ,        4,      1,      906,    "R/W",  0,      0,      0ull,   0ull},
73753         {"INTKNEPMISMSK"               ,        5,      1,      906,    "R/W",  0,      0,      0ull,   0ull},
73754         {"INEPNAKEFFMSK"               ,        6,      1,      906,    "R/W",  0,      0,      0ull,   0ull},
73755         {"RESERVED_7_31"               ,        7,      25,     906,    "RAZ",  1,      1,      0,      0},
73756         {"XFERSIZE"                    ,        0,      19,     907,    "R/W",  0,      0,      0ull,   0ull},
73757         {"PKTCNT"                      ,        19,     10,     907,    "R/W",  0,      0,      0ull,   0ull},
73758         {"MC"                          ,        29,     2,      907,    "R/W",  0,      0,      0ull,   0ull},
73759         {"RESERVED_31_31"              ,        31,     1,      907,    "RAZ",  1,      1,      0,      0},
73760         {"MPS"                         ,        0,      11,     908,    "R/W",  0,      0,      0ull,   0ull},
73761         {"RESERVED_11_14"              ,        11,     4,      908,    "RAZ",  0,      0,      0ull,   0ull},
73762         {"USBACTEP"                    ,        15,     1,      908,    "R/W",  0,      0,      1ull,   0ull},
73763         {"DPID"                        ,        16,     1,      908,    "RO",   0,      0,      0ull,   0ull},
73764         {"NAKSTS"                      ,        17,     1,      908,    "RO",   0,      0,      0ull,   0ull},
73765         {"EPTYPE"                      ,        18,     2,      908,    "R/W",  0,      0,      0ull,   0ull},
73766         {"SNP"                         ,        20,     1,      908,    "R/W",  0,      0,      0ull,   0ull},
73767         {"STALL"                       ,        21,     1,      908,    "R/W",  0,      0,      0ull,   0ull},
73768         {"RESERVED_22_25"              ,        22,     4,      908,    "RAZ",  1,      1,      0,      0},
73769         {"CNAK"                        ,        26,     1,      908,    "WO",   0,      0,      0ull,   0ull},
73770         {"SNAK"                        ,        27,     1,      908,    "WO",   0,      0,      0ull,   0ull},
73771         {"SETD0PID"                    ,        28,     1,      908,    "WO",   0,      0,      0ull,   0ull},
73772         {"SETD1PID"                    ,        29,     1,      908,    "WO",   0,      0,      0ull,   0ull},
73773         {"EPDIS"                       ,        30,     1,      908,    "R/W",  0,      0,      0ull,   0ull},
73774         {"EPENA"                       ,        31,     1,      908,    "R/W",  0,      0,      0ull,   0ull},
73775         {"XFERCOMPL"                   ,        0,      1,      909,    "R/W1C",        0,      0,      0ull,   0ull},
73776         {"EPDISBLD"                    ,        1,      1,      909,    "R/W1C",        0,      0,      0ull,   0ull},
73777         {"AHBERR"                      ,        2,      1,      909,    "R/W1C",        0,      0,      0ull,   0ull},
73778         {"SETUP"                       ,        3,      1,      909,    "R/W1C",        0,      0,      0ull,   0ull},
73779         {"OUTTKNEPDIS"                 ,        4,      1,      909,    "R/W1C",        0,      0,      0ull,   0ull},
73780         {"RESERVED_5_31"               ,        5,      27,     909,    "RAZ",  1,      1,      0,      0},
73781         {"XFERCOMPLMSK"                ,        0,      1,      910,    "R/W",  0,      0,      0ull,   0ull},
73782         {"EPDISBLDMSK"                 ,        1,      1,      910,    "R/W",  0,      0,      0ull,   0ull},
73783         {"AHBERRMSK"                   ,        2,      1,      910,    "R/W",  0,      0,      0ull,   0ull},
73784         {"SETUPMSK"                    ,        3,      1,      910,    "R/W",  0,      0,      0ull,   0ull},
73785         {"OUTTKNEPDISMSK"              ,        4,      1,      910,    "R/W",  0,      0,      0ull,   0ull},
73786         {"RESERVED_5_31"               ,        5,      27,     910,    "RAZ",  1,      1,      0,      0},
73787         {"XFERSIZE"                    ,        0,      19,     911,    "R/W",  0,      0,      0ull,   0ull},
73788         {"PKTCNT"                      ,        19,     10,     911,    "R/W",  0,      0,      0ull,   0ull},
73789         {"MC"                          ,        29,     2,      911,    "R/W",  0,      0,      0ull,   0ull},
73790         {"RESERVED_31_31"              ,        31,     1,      911,    "RAZ",  1,      1,      0,      0},
73791         {"DPTXFSTADDR"                 ,        0,      16,     912,    "RO",   0,      0,      0ull,   0ull},
73792         {"DPTXFSIZE"                   ,        16,     16,     912,    "RO",   0,      0,      1896ull,        1896ull},
73793         {"SUSPSTS"                     ,        0,      1,      913,    "RO",   0,      0,      0ull,   0ull},
73794         {"ENUMSPD"                     ,        1,      2,      913,    "RO",   0,      0,      0ull,   0ull},
73795         {"ERRTICERR"                   ,        3,      1,      913,    "RO",   0,      0,      0ull,   0ull},
73796         {"RESERVED_4_7"                ,        4,      4,      913,    "RAZ",  1,      1,      0,      0},
73797         {"SOFFN"                       ,        8,      14,     913,    "RO",   0,      0,      0ull,   0ull},
73798         {"RESERVED_22_31"              ,        22,     10,     913,    "RAZ",  1,      1,      0,      0},
73799         {"INTKNWPTR"                   ,        0,      5,      914,    "RO",   0,      0,      0ull,   0ull},
73800         {"RESERVED_5_6"                ,        5,      2,      914,    "RAZ",  1,      1,      0,      0},
73801         {"WRAPBIT"                     ,        7,      1,      914,    "RO",   0,      0,      0ull,   0ull},
73802         {"EPTKN"                       ,        8,      24,     914,    "RO",   0,      0,      0ull,   0ull},
73803         {"EPTKN"                       ,        0,      32,     915,    "RO",   0,      0,      0ull,   0ull},
73804         {"EPTKN"                       ,        0,      32,     916,    "RO",   0,      0,      0ull,   0ull},
73805         {"EPTKN"                       ,        0,      32,     917,    "RO",   0,      0,      0ull,   0ull},
73806         {"GLBLINTRMSK"                 ,        0,      1,      918,    "R/W",  0,      0,      0ull,   1ull},
73807         {"HBSTLEN"                     ,        1,      4,      918,    "R/W",  0,      0,      0ull,   0ull},
73808         {"DMAEN"                       ,        5,      1,      918,    "R/W",  0,      0,      0ull,   0ull},
73809         {"RESERVED_6_6"                ,        6,      1,      918,    "RAZ",  1,      1,      0,      0},
73810         {"NPTXFEMPLVL"                 ,        7,      1,      918,    "R/W",  0,      0,      0ull,   1ull},
73811         {"PTXFEMPLVL"                  ,        8,      1,      918,    "R/W",  0,      0,      0ull,   1ull},
73812         {"RESERVED_9_31"               ,        9,      23,     918,    "RAZ",  1,      1,      0,      0},
73813         {"EPDIR"                       ,        0,      32,     919,    "RO",   0,      0,      0ull,   0ull},
73814         {"OTGMODE"                     ,        0,      3,      920,    "RO",   0,      0,      2ull,   2ull},
73815         {"OTGARCH"                     ,        3,      2,      920,    "RO",   0,      0,      1ull,   1ull},
73816         {"SINGPNT"                     ,        5,      1,      920,    "RO",   0,      0,      0ull,   0ull},
73817         {"HSPHYTYPE"                   ,        6,      2,      920,    "RO",   0,      0,      1ull,   1ull},
73818         {"FSPHYTYPE"                   ,        8,      2,      920,    "RO",   0,      0,      0ull,   0ull},
73819         {"NUMDEVEPS"                   ,        10,     4,      920,    "RO",   0,      0,      4ull,   4ull},
73820         {"NUMHSTCHNL"                  ,        14,     4,      920,    "RO",   0,      0,      7ull,   7ull},
73821         {"PERIOSUPPORT"                ,        18,     1,      920,    "RO",   0,      0,      1ull,   1ull},
73822         {"DYNFIFOSIZING"               ,        19,     1,      920,    "RO",   0,      0,      1ull,   1ull},
73823         {"RESERVED_20_21"              ,        20,     2,      920,    "RAZ",  1,      1,      0,      0},
73824         {"NPTXQDEPTH"                  ,        22,     2,      920,    "RO",   0,      0,      2ull,   2ull},
73825         {"PTXQDEPTH"                   ,        24,     2,      920,    "RO",   0,      0,      2ull,   2ull},
73826         {"TKNQDEPTH"                   ,        26,     5,      920,    "RO",   0,      0,      30ull,  30ull},
73827         {"RESERVED_31_31"              ,        31,     1,      920,    "RAZ",  1,      1,      0,      0},
73828         {"XFERSIZEWIDTH"               ,        0,      4,      921,    "RO",   0,      0,      8ull,   8ull},
73829         {"PKTSIZEWIDTH"                ,        4,      3,      921,    "RO",   0,      0,      6ull,   6ull},
73830         {"OTGEN"                       ,        7,      1,      921,    "RO",   0,      0,      1ull,   1ull},
73831         {"I2C_SELECTION"               ,        8,      1,      921,    "RO",   0,      0,      0ull,   0ull},
73832         {"VENDOR_CONTROL_INTERFACE_SUPPORT",    9,      1,      921,    "RO",   0,      0,      0ull,   0ull},
73833         {"OPTFEATURE"                  ,        10,     1,      921,    "RO",   0,      0,      1ull,   1ull},
73834         {"RSTTYPE"                     ,        11,     1,      921,    "RO",   0,      0,      0ull,   0ull},
73835         {"AHBPHYSYNC"                  ,        12,     1,      921,    "RO",   0,      0,      0ull,   0ull},
73836         {"RESERVED_13_15"              ,        13,     3,      921,    "RAZ",  1,      1,      0,      0},
73837         {"DFIFODEPTH"                  ,        16,     16,     921,    "RO",   0,      0,      1824ull,        1824ull},
73838         {"NUMDEVPERIOEPS"              ,        0,      4,      922,    "RO",   0,      0,      4ull,   4ull},
73839         {"ENABLEPWROPT"                ,        4,      1,      922,    "RO",   0,      0,      0ull,   0ull},
73840         {"AHBFREQ"                     ,        5,      1,      922,    "RO",   0,      0,      1ull,   1ull},
73841         {"RESERVED_6_13"               ,        6,      8,      922,    "RAZ",  1,      1,      0,      0},
73842         {"PHYDATAWIDTH"                ,        14,     2,      922,    "RO",   0,      0,      1ull,   1ull},
73843         {"NUMCTLEPS"                   ,        16,     4,      922,    "RO",   0,      0,      4ull,   4ull},
73844         {"IDDGFLTR"                    ,        20,     1,      922,    "RO",   0,      0,      1ull,   1ull},
73845         {"VBUSVALIDFLTR"               ,        21,     1,      922,    "RO",   0,      0,      1ull,   1ull},
73846         {"AVALIDFLTR"                  ,        22,     1,      922,    "RO",   0,      0,      0ull,   0ull},
73847         {"BVALIDFLTR"                  ,        23,     1,      922,    "RO",   0,      0,      0ull,   0ull},
73848         {"SESSENDFLTR"                 ,        24,     1,      922,    "RO",   0,      0,      0ull,   0ull},
73849         {"ENDEDTRFIFO"                 ,        25,     1,      922,    "RO",   0,      0,      0ull,   0ull},
73850         {"NUMDEVMODINEND"              ,        26,     4,      922,    "RO",   0,      0,      2ull,   2ull},
73851         {"RESERVED_30_31"              ,        30,     2,      922,    "RAZ",  1,      1,      0,      0},
73852         {"RESERVED_0_0"                ,        0,      1,      923,    "RAZ",  1,      1,      0,      0},
73853         {"MODEMISMSK"                  ,        1,      1,      923,    "R/W",  0,      0,      0ull,   0ull},
73854         {"OTGINTMSK"                   ,        2,      1,      923,    "R/W",  0,      0,      0ull,   0ull},
73855         {"SOFMSK"                      ,        3,      1,      923,    "R/W",  0,      0,      0ull,   0ull},
73856         {"RXFLVLMSK"                   ,        4,      1,      923,    "R/W",  0,      0,      0ull,   0ull},
73857         {"NPTXFEMPMSK"                 ,        5,      1,      923,    "R/W",  0,      0,      0ull,   0ull},
73858         {"GINNAKEFFMSK"                ,        6,      1,      923,    "R/W",  0,      0,      0ull,   0ull},
73859         {"GOUTNAKEFFMSK"               ,        7,      1,      923,    "R/W",  0,      0,      0ull,   0ull},
73860         {"ULPICKINTMSK"                ,        8,      1,      923,    "R/W",  0,      0,      0ull,   0ull},
73861         {"I2CINT"                      ,        9,      1,      923,    "R/W",  0,      0,      0ull,   0ull},
73862         {"ERLYSUSPMSK"                 ,        10,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73863         {"USBSUSPMSK"                  ,        11,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73864         {"USBRSTMSK"                   ,        12,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73865         {"ENUMDONEMSK"                 ,        13,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73866         {"ISOOUTDROPMSK"               ,        14,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73867         {"EOPFMSK"                     ,        15,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73868         {"RESERVED_16_16"              ,        16,     1,      923,    "RAZ",  1,      1,      0,      0},
73869         {"EPMISMSK"                    ,        17,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73870         {"INEPINTMSK"                  ,        18,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73871         {"OEPINTMSK"                   ,        19,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73872         {"INCOMPISOINMSK"              ,        20,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73873         {"INCOMPLPMSK"                 ,        21,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73874         {"FETSUSPMSK"                  ,        22,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73875         {"RESERVED_23_23"              ,        23,     1,      923,    "RAZ",  1,      1,      0,      0},
73876         {"PRTINTMSK"                   ,        24,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73877         {"HCHINTMSK"                   ,        25,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73878         {"PTXFEMPMSK"                  ,        26,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73879         {"RESERVED_27_27"              ,        27,     1,      923,    "RAZ",  1,      1,      0,      0},
73880         {"CONIDSTSCHNGMSK"             ,        28,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73881         {"DISCONNINTMSK"               ,        29,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73882         {"SESSREQINTMSK"               ,        30,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73883         {"WKUPINTMSK"                  ,        31,     1,      923,    "R/W",  0,      0,      0ull,   0ull},
73884         {"CURMOD"                      ,        0,      1,      924,    "RO",   0,      0,      0ull,   0ull},
73885         {"MODEMIS"                     ,        1,      1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73886         {"OTGINT"                      ,        2,      1,      924,    "RO",   0,      0,      0ull,   0ull},
73887         {"SOF"                         ,        3,      1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73888         {"RXFLVL"                      ,        4,      1,      924,    "RO",   0,      0,      0ull,   0ull},
73889         {"NPTXFEMP"                    ,        5,      1,      924,    "RO",   0,      0,      0ull,   0ull},
73890         {"GINNAKEFF"                   ,        6,      1,      924,    "RO",   0,      0,      0ull,   0ull},
73891         {"GOUTNAKEFF"                  ,        7,      1,      924,    "RO",   0,      0,      0ull,   0ull},
73892         {"ULPICKINT"                   ,        8,      1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73893         {"I2CINT"                      ,        9,      1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73894         {"ERLYSUSP"                    ,        10,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73895         {"USBSUSP"                     ,        11,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73896         {"USBRST"                      ,        12,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73897         {"ENUMDONE"                    ,        13,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73898         {"ISOOUTDROP"                  ,        14,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73899         {"EOPF"                        ,        15,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73900         {"RESERVED_16_16"              ,        16,     1,      924,    "RAZ",  1,      1,      0,      0},
73901         {"EPMIS"                       ,        17,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73902         {"IEPINT"                      ,        18,     1,      924,    "RO",   0,      0,      0ull,   0ull},
73903         {"OEPINT"                      ,        19,     1,      924,    "RO",   0,      0,      0ull,   0ull},
73904         {"INCOMPISOIN"                 ,        20,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73905         {"INCOMPLP"                    ,        21,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73906         {"FETSUSP"                     ,        22,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73907         {"RESERVED_23_23"              ,        23,     1,      924,    "RAZ",  1,      1,      0,      0},
73908         {"PRTINT"                      ,        24,     1,      924,    "RO",   0,      0,      0ull,   0ull},
73909         {"HCHINT"                      ,        25,     1,      924,    "RO",   0,      0,      0ull,   0ull},
73910         {"PTXFEMP"                     ,        26,     1,      924,    "RO",   0,      0,      0ull,   0ull},
73911         {"RESERVED_27_27"              ,        27,     1,      924,    "RAZ",  1,      1,      0,      0},
73912         {"CONIDSTSCHNG"                ,        28,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73913         {"DISCONNINT"                  ,        29,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73914         {"SESSREQINT"                  ,        30,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73915         {"WKUPINT"                     ,        31,     1,      924,    "R/W1C",        0,      0,      0ull,   0ull},
73916         {"NPTXFSTADDR"                 ,        0,      16,     925,    "R/W",  0,      0,      1824ull,        456ull},
73917         {"NPTXFDEP"                    ,        16,     16,     925,    "R/W",  0,      0,      1824ull,        912ull},
73918         {"NPTXFSPCAVAIL"               ,        0,      16,     926,    "RO",   0,      0,      0ull,   0ull},
73919         {"NPTXQSPCAVAIL"               ,        16,     8,      926,    "RO",   0,      0,      0ull,   0ull},
73920         {"NPTXQTOP"                    ,        24,     7,      926,    "RO",   0,      0,      0ull,   0ull},
73921         {"RESERVED_31_31"              ,        31,     1,      926,    "RAZ",  1,      1,      0,      0},
73922         {"SESREQSCS"                   ,        0,      1,      927,    "R/W",  0,      0,      0ull,   0ull},
73923         {"SESREQ"                      ,        1,      1,      927,    "R/W",  0,      0,      0ull,   0ull},
73924         {"RESERVED_2_7"                ,        2,      6,      927,    "RAZ",  1,      1,      0,      0},
73925         {"HSTNEGSCS"                   ,        8,      1,      927,    "R/W",  0,      0,      0ull,   0ull},
73926         {"HNPREQ"                      ,        9,      1,      927,    "R/W",  0,      0,      0ull,   0ull},
73927         {"HSTSETHNPEN"                 ,        10,     1,      927,    "R/W",  0,      0,      0ull,   0ull},
73928         {"DEVHNPEN"                    ,        11,     1,      927,    "R/W",  0,      0,      0ull,   0ull},
73929         {"RESERVED_12_15"              ,        12,     4,      927,    "RAZ",  1,      1,      0,      0},
73930         {"CONIDSTS"                    ,        16,     1,      927,    "RO",   1,      1,      0,      0},
73931         {"DBNCTIME"                    ,        17,     1,      927,    "RO",   0,      0,      0ull,   0ull},
73932         {"ASESVLD"                     ,        18,     1,      927,    "RO",   1,      1,      0,      0},
73933         {"BSESVLD"                     ,        19,     1,      927,    "RO",   1,      1,      0,      0},
73934         {"RESERVED_20_31"              ,        20,     12,     927,    "RAZ",  1,      1,      0,      0},
73935         {"RESERVED_0_1"                ,        0,      2,      928,    "RAZ",  1,      1,      0,      0},
73936         {"SESENDDET"                   ,        2,      1,      928,    "R/W1C",        0,      0,      0ull,   0ull},
73937         {"RESERVED_3_7"                ,        3,      5,      928,    "RAZ",  1,      1,      0,      0},
73938         {"SESREQSUCSTSCHNG"            ,        8,      1,      928,    "R/W1C",        0,      0,      0ull,   0ull},
73939         {"HSTNEGSUCSTSCHNG"            ,        9,      1,      928,    "R/W1C",        0,      0,      0ull,   0ull},
73940         {"RESERVED_10_16"              ,        10,     7,      928,    "RAZ",  1,      1,      0,      0},
73941         {"HSTNEGDET"                   ,        17,     1,      928,    "R/W1C",        0,      0,      0ull,   0ull},
73942         {"ADEVTOUTCHG"                 ,        18,     1,      928,    "R/W1C",        0,      0,      0ull,   0ull},
73943         {"DBNCEDONE"                   ,        19,     1,      928,    "R/W1C",        0,      0,      0ull,   0ull},
73944         {"RESERVED_20_31"              ,        20,     12,     928,    "RAZ",  1,      1,      0,      0},
73945         {"CSFTRST"                     ,        0,      1,      929,    "R/W",  0,      0,      0ull,   0ull},
73946         {"HSFTRST"                     ,        1,      1,      929,    "R/W",  0,      0,      0ull,   0ull},
73947         {"FRMCNTRRST"                  ,        2,      1,      929,    "R/W",  0,      0,      0ull,   0ull},
73948         {"INTKNQFLSH"                  ,        3,      1,      929,    "R/W",  0,      0,      0ull,   0ull},
73949         {"RXFFLSH"                     ,        4,      1,      929,    "R/W",  0,      0,      0ull,   0ull},
73950         {"TXFFLSH"                     ,        5,      1,      929,    "R/W",  0,      0,      0ull,   0ull},
73951         {"TXFNUM"                      ,        6,      5,      929,    "R/W",  0,      0,      0ull,   0ull},
73952         {"RESERVED_11_29"              ,        11,     19,     929,    "RAZ",  1,      1,      0,      0},
73953         {"DMAREQ"                      ,        30,     1,      929,    "RO",   0,      0,      0ull,   0ull},
73954         {"AHBIDLE"                     ,        31,     1,      929,    "RO",   0,      0,      1ull,   1ull},
73955         {"RXFDEP"                      ,        0,      16,     930,    "R/W",  0,      0,      1824ull,        456ull},
73956         {"RESERVED_16_31"              ,        16,     16,     930,    "RAZ",  1,      1,      0,      0},
73957         {"EPNUM"                       ,        0,      4,      931,    "RO",   0,      0,      0ull,   0ull},
73958         {"BCNT"                        ,        4,      11,     931,    "RO",   0,      0,      0ull,   0ull},
73959         {"DPID"                        ,        15,     2,      931,    "RO",   0,      0,      0ull,   0ull},
73960         {"PKTSTS"                      ,        17,     4,      931,    "RO",   0,      0,      0ull,   0ull},
73961         {"FN"                          ,        21,     4,      931,    "RO",   0,      0,      0ull,   0ull},
73962         {"RESERVED_25_31"              ,        25,     7,      931,    "RAZ",  1,      1,      0,      0},
73963         {"CHNUM"                       ,        0,      4,      932,    "RO",   0,      0,      0ull,   0ull},
73964         {"BCNT"                        ,        4,      11,     932,    "RO",   0,      0,      0ull,   0ull},
73965         {"DPID"                        ,        15,     2,      932,    "RO",   0,      0,      0ull,   0ull},
73966         {"PKTSTS"                      ,        17,     4,      932,    "RO",   0,      0,      0ull,   0ull},
73967         {"RESERVED_21_31"              ,        21,     11,     932,    "RAZ",  1,      1,      0,      0},
73968         {"EPNUM"                       ,        0,      4,      933,    "RO",   0,      0,      0ull,   0ull},
73969         {"BCNT"                        ,        4,      11,     933,    "RO",   0,      0,      0ull,   0ull},
73970         {"DPID"                        ,        15,     2,      933,    "RO",   0,      0,      0ull,   0ull},
73971         {"PKTSTS"                      ,        17,     4,      933,    "RO",   0,      0,      0ull,   0ull},
73972         {"FN"                          ,        21,     4,      933,    "RO",   0,      0,      0ull,   0ull},
73973         {"RESERVED_25_31"              ,        25,     7,      933,    "RAZ",  1,      1,      0,      0},
73974         {"CHNUM"                       ,        0,      4,      934,    "RO",   0,      0,      0ull,   0ull},
73975         {"BCNT"                        ,        4,      11,     934,    "RO",   0,      0,      0ull,   0ull},
73976         {"DPID"                        ,        15,     2,      934,    "RO",   0,      0,      0ull,   0ull},
73977         {"PKTSTS"                      ,        17,     4,      934,    "RO",   0,      0,      0ull,   0ull},
73978         {"RESERVED_21_31"              ,        21,     11,     934,    "RAZ",  1,      1,      0,      0},
73979         {"SYNOPSYSID"                  ,        0,      32,     935,    "RO",   1,      1,      0,      0},
73980         {"TOUTCAL"                     ,        0,      3,      936,    "R/W",  0,      0,      0ull,   0ull},
73981         {"PHYIF"                       ,        3,      1,      936,    "RO",   0,      0,      1ull,   1ull},
73982         {"ULPI_UTMI_SEL"               ,        4,      1,      936,    "RO",   0,      0,      0ull,   0ull},
73983         {"FSINTF"                      ,        5,      1,      936,    "WO",   0,      0,      0ull,   0ull},
73984         {"PHYSEL"                      ,        6,      1,      936,    "WO",   0,      0,      0ull,   0ull},
73985         {"DDRSEL"                      ,        7,      1,      936,    "R/W",  0,      0,      0ull,   0ull},
73986         {"SRPCAP"                      ,        8,      1,      936,    "RO",   0,      0,      0ull,   0ull},
73987         {"HNPCAP"                      ,        9,      1,      936,    "RO",   0,      0,      0ull,   0ull},
73988         {"USBTRDTIM"                   ,        10,     4,      936,    "R/W",  0,      0,      5ull,   5ull},
73989         {"RESERVED_14_14"              ,        14,     1,      936,    "RAZ",  1,      1,      0,      0},
73990         {"PHYLPWRCLKSEL"               ,        15,     1,      936,    "R/W",  0,      0,      0ull,   0ull},
73991         {"OTGI2CSEL"                   ,        16,     1,      936,    "RO",   0,      0,      0ull,   0ull},
73992         {"RESERVED_17_31"              ,        17,     15,     936,    "RAZ",  1,      1,      0,      0},
73993         {"HAINT"                       ,        0,      16,     937,    "RO",   0,      0,      0ull,   0ull},
73994         {"RESERVED_16_31"              ,        16,     16,     937,    "RAZ",  1,      1,      0,      0},
73995         {"HAINTMSK"                    ,        0,      16,     938,    "R/W",  0,      0,      0ull,   0ull},
73996         {"RESERVED_16_31"              ,        16,     16,     938,    "RAZ",  1,      1,      0,      0},
73997         {"MPS"                         ,        0,      11,     939,    "R/W",  0,      0,      0ull,   0ull},
73998         {"EPNUM"                       ,        11,     4,      939,    "R/W",  0,      0,      0ull,   0ull},
73999         {"EPDIR"                       ,        15,     1,      939,    "R/W",  0,      0,      0ull,   0ull},
74000         {"RESERVED_16_16"              ,        16,     1,      939,    "RAZ",  1,      1,      0,      0},
74001         {"LSPDDEV"                     ,        17,     1,      939,    "R/W",  0,      0,      0ull,   0ull},
74002         {"EPTYPE"                      ,        18,     2,      939,    "R/W",  0,      0,      0ull,   0ull},
74003         {"EC"                          ,        20,     2,      939,    "R/W",  0,      0,      0ull,   0ull},
74004         {"DEVADDR"                     ,        22,     7,      939,    "R/W",  0,      0,      0ull,   0ull},
74005         {"ODDFRM"                      ,        29,     1,      939,    "R/W",  0,      0,      0ull,   0ull},
74006         {"CHDIS"                       ,        30,     1,      939,    "R/W",  0,      0,      0ull,   0ull},
74007         {"CHENA"                       ,        31,     1,      939,    "R/W",  0,      0,      0ull,   0ull},
74008         {"FSLSPCLKSEL"                 ,        0,      2,      940,    "R/W",  0,      0,      0ull,   0ull},
74009         {"FSLSSUPP"                    ,        2,      1,      940,    "R/W",  0,      0,      0ull,   0ull},
74010         {"RESERVED_3_31"               ,        3,      29,     940,    "RAZ",  1,      1,      0,      0},
74011         {"XFERCOMPL"                   ,        0,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74012         {"CHHLTD"                      ,        1,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74013         {"AHBERR"                      ,        2,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74014         {"STALL"                       ,        3,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74015         {"NAK"                         ,        4,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74016         {"ACK"                         ,        5,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74017         {"NYET"                        ,        6,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74018         {"XACTERR"                     ,        7,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74019         {"BBLERR"                      ,        8,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74020         {"FRMOVRUN"                    ,        9,      1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74021         {"DATATGLERR"                  ,        10,     1,      941,    "R/W1C",        0,      0,      0ull,   0ull},
74022         {"RESERVED_11_31"              ,        11,     21,     941,    "RAZ",  1,      1,      0,      0},
74023         {"XFERCOMPLMSK"                ,        0,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74024         {"CHHLTDMSK"                   ,        1,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74025         {"AHBERRMSK"                   ,        2,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74026         {"STALLMSK"                    ,        3,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74027         {"NAKMSK"                      ,        4,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74028         {"ACKMSK"                      ,        5,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74029         {"NYETMSK"                     ,        6,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74030         {"XACTERRMSK"                  ,        7,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74031         {"BBLERRMSK"                   ,        8,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74032         {"FRMOVRUNMSK"                 ,        9,      1,      942,    "R/W",  0,      0,      0ull,   0ull},
74033         {"DATATGLERRMSK"               ,        10,     1,      942,    "R/W",  0,      0,      0ull,   0ull},
74034         {"RESERVED_11_31"              ,        11,     21,     942,    "RAZ",  1,      1,      0,      0},
74035         {"PRTADDR"                     ,        0,      7,      943,    "R/W",  0,      0,      0ull,   0ull},
74036         {"HUBADDR"                     ,        7,      7,      943,    "R/W",  0,      0,      0ull,   0ull},
74037         {"XACTPOS"                     ,        14,     2,      943,    "R/W",  0,      0,      0ull,   0ull},
74038         {"COMPSPLT"                    ,        16,     1,      943,    "R/W",  0,      0,      0ull,   0ull},
74039         {"RESERVED_17_30"              ,        17,     14,     943,    "RAZ",  1,      1,      0,      0},
74040         {"SPLTENA"                     ,        31,     1,      943,    "R/W",  0,      0,      0ull,   0ull},
74041         {"XFERSIZE"                    ,        0,      19,     944,    "R/W",  0,      0,      0ull,   0ull},
74042         {"PKTCNT"                      ,        19,     10,     944,    "R/W",  0,      0,      0ull,   0ull},
74043         {"PID"                         ,        29,     2,      944,    "R/W",  0,      0,      0ull,   0ull},
74044         {"DOPNG"                       ,        31,     1,      944,    "R/W",  0,      0,      0ull,   0ull},
74045         {"FRINT"                       ,        0,      16,     945,    "R/W",  0,      0,      2959ull,        3750ull},
74046         {"RESERVED_16_31"              ,        16,     16,     945,    "RAZ",  1,      1,      0,      0},
74047         {"FRNUM"                       ,        0,      16,     946,    "RO",   0,      0,      16383ull,       0ull},
74048         {"FRREM"                       ,        16,     16,     946,    "RO",   0,      0,      0ull,   0ull},
74049         {"PRTCONNSTS"                  ,        0,      1,      947,    "RO",   0,      0,      0ull,   0ull},
74050         {"PRTCONNDET"                  ,        1,      1,      947,    "R/W1C",        0,      0,      0ull,   0ull},
74051         {"PRTENA"                      ,        2,      1,      947,    "R/W1C",        0,      0,      0ull,   0ull},
74052         {"PRTENCHNG"                   ,        3,      1,      947,    "R/W1C",        0,      0,      0ull,   0ull},
74053         {"PRTOVRCURRACT"               ,        4,      1,      947,    "RO",   0,      0,      0ull,   0ull},
74054         {"PRTOVRCURRCHNG"              ,        5,      1,      947,    "R/W1C",        0,      0,      0ull,   0ull},
74055         {"PRTRES"                      ,        6,      1,      947,    "R/W",  0,      0,      0ull,   0ull},
74056         {"PRTSUSP"                     ,        7,      1,      947,    "R/W",  0,      0,      0ull,   0ull},
74057         {"PRTRST"                      ,        8,      1,      947,    "R/W",  0,      0,      0ull,   0ull},
74058         {"RESERVED_9_9"                ,        9,      1,      947,    "RAZ",  1,      1,      0,      0},
74059         {"PRTLNSTS"                    ,        10,     2,      947,    "RO",   0,      0,      0ull,   0ull},
74060         {"PRTPWR"                      ,        12,     1,      947,    "R/W",  0,      0,      0ull,   0ull},
74061         {"PRTTSTCTL"                   ,        13,     4,      947,    "R/W",  0,      0,      0ull,   0ull},
74062         {"PRTSPD"                      ,        17,     2,      947,    "RO",   0,      0,      0ull,   0ull},
74063         {"RESERVED_19_31"              ,        19,     13,     947,    "RAZ",  1,      1,      0,      0},
74064         {"PTXFSTADDR"                  ,        0,      16,     948,    "R/W",  0,      0,      3648ull,        912ull},
74065         {"PTXFSIZE"                    ,        16,     16,     948,    "R/W",  0,      0,      256ull, 456ull},
74066         {"PTXFSPCAVAIL"                ,        0,      16,     949,    "RO",   0,      0,      0ull,   0ull},
74067         {"PTXQSPCAVAIL"                ,        16,     8,      949,    "RO",   0,      0,      0ull,   0ull},
74068         {"PTXQTOP"                     ,        24,     8,      949,    "RO",   0,      0,      0ull,   0ull},
74069         {"DATA"                        ,        0,      32,     950,    "R/W",  0,      0,      0ull,   0ull},
74070         {"STOPPCLK"                    ,        0,      1,      951,    "R/W",  0,      0,      0ull,   0ull},
74071         {"GATEHCLK"                    ,        1,      1,      951,    "R/W",  0,      0,      0ull,   0ull},
74072         {"PWRCLMP"                     ,        2,      1,      951,    "R/W",  0,      0,      0ull,   0ull},
74073         {"RSTPDWNMODULE"               ,        3,      1,      951,    "R/W",  0,      0,      0ull,   0ull},
74074         {"PHYSUSPENDED"                ,        4,      1,      951,    "RO",   0,      0,      0ull,   0ull},
74075         {"RESERVED_5_31"               ,        5,      27,     951,    "RAZ",  1,      1,      0,      0},
74076         {"NOF_BIS"                     ,        0,      1,      952,    "RO",   0,      0,      0ull,   0ull},
74077         {"NIF_BIS"                     ,        1,      1,      952,    "RO",   0,      0,      0ull,   0ull},
74078         {"USBC_BIS"                    ,        2,      1,      952,    "RO",   0,      0,      0ull,   0ull},
74079         {"N2UF_BIS"                    ,        3,      1,      952,    "RO",   0,      0,      0ull,   0ull},
74080         {"E2HC_BIS"                    ,        4,      1,      952,    "RO",   0,      0,      0ull,   0ull},
74081         {"U2NF_BIS"                    ,        5,      1,      952,    "RO",   0,      0,      0ull,   0ull},
74082         {"U2NC_BIS"                    ,        6,      1,      952,    "RO",   0,      0,      0ull,   0ull},
74083         {"RESERVED_7_63"               ,        7,      57,     952,    "RAZ",  1,      1,      0,      0},
74084         {"DIVIDE"                      ,        0,      3,      953,    "R/W",  0,      0,      4ull,   0ull},
74085         {"HRST"                        ,        3,      1,      953,    "R/W",  0,      0,      0ull,   1ull},
74086         {"PRST"                        ,        4,      1,      953,    "R/W",  0,      0,      0ull,   1ull},
74087         {"ENABLE"                      ,        5,      1,      953,    "R/W",  0,      0,      1ull,   1ull},
74088         {"POR"                         ,        6,      1,      953,    "R/W",  0,      0,      1ull,   0ull},
74089         {"S_BIST"                      ,        7,      1,      953,    "R/W",  0,      0,      0ull,   1ull},
74090         {"SD_MODE"                     ,        8,      2,      953,    "R/W",  0,      0,      0ull,   0ull},
74091         {"CDIV_BYP"                    ,        10,     1,      953,    "R/W",  0,      0,      0ull,   0ull},
74092         {"P_C_SEL"                     ,        11,     2,      953,    "R/W",  0,      0,      2ull,   0ull},
74093         {"P_COM_ON"                    ,        13,     1,      953,    "R/W",  0,      0,      1ull,   1ull},
74094         {"P_RTYPE"                     ,        14,     2,      953,    "R/W",  0,      0,      0ull,   0ull},
74095         {"RESERVED_16_16"              ,        16,     1,      953,    "RAZ",  1,      1,      0,      0},
74096         {"HCLK_RST"                    ,        17,     1,      953,    "R/W",  0,      0,      1ull,   1ull},
74097         {"DIVIDE2"                     ,        18,     2,      953,    "R/W",  0,      0,      0ull,   1ull},
74098         {"RESERVED_20_63"              ,        20,     44,     953,    "RAZ",  1,      1,      0,      0},
74099         {"L2C_EMOD"                    ,        0,      2,      954,    "R/W",  0,      0,      1ull,   1ull},
74100         {"INV_A2"                      ,        2,      1,      954,    "R/W",  0,      0,      0ull,   0ull},
74101         {"DMA_TEST"                    ,        3,      1,      954,    "R/W",  0,      0,      0ull,   0ull},
74102         {"DMA_STT"                     ,        4,      1,      954,    "R/W",  0,      0,      0ull,   0ull},
74103         {"DMA_0PAG"                    ,        5,      1,      954,    "R/W",  0,      0,      0ull,   0ull},
74104         {"RESERVED_6_63"               ,        6,      58,     954,    "RAZ",  1,      1,      0,      0},
74105         {"ADDR"                        ,        0,      36,     955,    "R/W",  0,      1,      0ull,   0},
74106         {"RESERVED_36_63"              ,        36,     28,     955,    "RAZ",  1,      1,      0,      0},
74107         {"ADDR"                        ,        0,      36,     956,    "R/W",  0,      1,      0ull,   0},
74108         {"RESERVED_36_63"              ,        36,     28,     956,    "RAZ",  1,      1,      0,      0},
74109         {"ADDR"                        ,        0,      36,     957,    "R/W",  0,      1,      0ull,   0},
74110         {"RESERVED_36_63"              ,        36,     28,     957,    "RAZ",  1,      1,      0,      0},
74111         {"ADDR"                        ,        0,      36,     958,    "R/W",  0,      1,      0ull,   0},
74112         {"RESERVED_36_63"              ,        36,     28,     958,    "RAZ",  1,      1,      0,      0},
74113         {"ADDR"                        ,        0,      36,     959,    "R/W",  0,      1,      0ull,   0},
74114         {"RESERVED_36_63"              ,        36,     28,     959,    "RAZ",  1,      1,      0,      0},
74115         {"ADDR"                        ,        0,      36,     960,    "R/W",  0,      1,      0ull,   0},
74116         {"RESERVED_36_63"              ,        36,     28,     960,    "RAZ",  1,      1,      0,      0},
74117         {"ADDR"                        ,        0,      36,     961,    "R/W",  0,      1,      0ull,   0},
74118         {"RESERVED_36_63"              ,        36,     28,     961,    "RAZ",  1,      1,      0,      0},
74119         {"ADDR"                        ,        0,      36,     962,    "R/W",  0,      1,      0ull,   0},
74120         {"RESERVED_36_63"              ,        36,     28,     962,    "RAZ",  1,      1,      0,      0},
74121         {"ADDR"                        ,        0,      36,     963,    "R/W",  0,      1,      0ull,   0},
74122         {"RESERVED_36_63"              ,        36,     28,     963,    "RAZ",  1,      1,      0,      0},
74123         {"ADDR"                        ,        0,      36,     964,    "R/W",  0,      1,      0ull,   0},
74124         {"RESERVED_36_63"              ,        36,     28,     964,    "RAZ",  1,      1,      0,      0},
74125         {"ADDR"                        ,        0,      36,     965,    "R/W",  0,      1,      0ull,   0},
74126         {"RESERVED_36_63"              ,        36,     28,     965,    "RAZ",  1,      1,      0,      0},
74127         {"ADDR"                        ,        0,      36,     966,    "R/W",  0,      1,      0ull,   0},
74128         {"RESERVED_36_63"              ,        36,     28,     966,    "RAZ",  1,      1,      0,      0},
74129         {"ADDR"                        ,        0,      36,     967,    "R/W",  0,      1,      0ull,   0},
74130         {"RESERVED_36_63"              ,        36,     28,     967,    "RAZ",  1,      1,      0,      0},
74131         {"ADDR"                        ,        0,      36,     968,    "R/W",  0,      1,      0ull,   0},
74132         {"RESERVED_36_63"              ,        36,     28,     968,    "RAZ",  1,      1,      0,      0},
74133         {"ADDR"                        ,        0,      36,     969,    "R/W",  0,      1,      0ull,   0},
74134         {"RESERVED_36_63"              ,        36,     28,     969,    "RAZ",  1,      1,      0,      0},
74135         {"ADDR"                        ,        0,      36,     970,    "R/W",  0,      1,      0ull,   0},
74136         {"RESERVED_36_63"              ,        36,     28,     970,    "RAZ",  1,      1,      0,      0},
74137         {"BURST"                       ,        0,      4,      971,    "R/W",  0,      0,      0ull,   0ull},
74138         {"CHANNEL"                     ,        4,      5,      971,    "R/W",  0,      0,      0ull,   0ull},
74139         {"COUNT"                       ,        9,      11,     971,    "R/W",  0,      0,      0ull,   0ull},
74140         {"F_ADDR"                      ,        20,     18,     971,    "R/W",  0,      0,      0ull,   0ull},
74141         {"REQ"                         ,        38,     1,      971,    "R/W1C",        0,      0,      0ull,   0ull},
74142         {"DONE"                        ,        39,     1,      971,    "R/W1C",        0,      0,      0ull,   0ull},
74143         {"RESERVED_40_63"              ,        40,     24,     971,    "RAZ",  1,      1,      0,      0},
74144         {"PR_PO_E"                     ,        0,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74145         {"PR_PU_F"                     ,        1,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74146         {"NR_PO_E"                     ,        2,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74147         {"NR_PU_F"                     ,        3,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74148         {"LR_PO_E"                     ,        4,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74149         {"LR_PU_F"                     ,        5,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74150         {"PT_PO_E"                     ,        6,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74151         {"PT_PU_F"                     ,        7,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74152         {"NT_PO_E"                     ,        8,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74153         {"NT_PU_F"                     ,        9,      1,      972,    "R/W",  0,      0,      0ull,   0ull},
74154         {"LT_PO_E"                     ,        10,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74155         {"LT_PU_F"                     ,        11,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74156         {"DCRED_E"                     ,        12,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74157         {"DCRED_F"                     ,        13,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74158         {"L2C_S_E"                     ,        14,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74159         {"L2C_A_F"                     ,        15,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74160         {"L2_FI_E"                     ,        16,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74161         {"L2_FI_F"                     ,        17,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74162         {"RG_FI_E"                     ,        18,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74163         {"RG_FI_F"                     ,        19,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74164         {"RQ_Q2_F"                     ,        20,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74165         {"RQ_Q2_E"                     ,        21,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74166         {"RQ_Q3_F"                     ,        22,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74167         {"RQ_Q3_E"                     ,        23,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74168         {"UOD_PE"                      ,        24,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74169         {"UOD_PF"                      ,        25,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74170         {"RESERVED_26_31"              ,        26,     6,      972,    "RAZ",  0,      0,      0ull,   0ull},
74171         {"LTL_F_PE"                    ,        32,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74172         {"LTL_F_PF"                    ,        33,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74173         {"ND4O_RPE"                    ,        34,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74174         {"ND4O_RPF"                    ,        35,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74175         {"ND4O_DPE"                    ,        36,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74176         {"ND4O_DPF"                    ,        37,     1,      972,    "R/W",  0,      0,      0ull,   0ull},
74177         {"RESERVED_38_63"              ,        38,     26,     972,    "RAZ",  1,      1,      0,      0},
74178         {"PR_PO_E"                     ,        0,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74179         {"PR_PU_F"                     ,        1,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74180         {"NR_PO_E"                     ,        2,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74181         {"NR_PU_F"                     ,        3,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74182         {"LR_PO_E"                     ,        4,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74183         {"LR_PU_F"                     ,        5,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74184         {"PT_PO_E"                     ,        6,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74185         {"PT_PU_F"                     ,        7,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74186         {"NT_PO_E"                     ,        8,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74187         {"NT_PU_F"                     ,        9,      1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74188         {"LT_PO_E"                     ,        10,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74189         {"LT_PU_F"                     ,        11,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74190         {"DCRED_E"                     ,        12,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74191         {"DCRED_F"                     ,        13,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74192         {"L2C_S_E"                     ,        14,     1,      973,    "R/W1C",        1,      0,      0,      0ull},
74193         {"L2C_A_F"                     ,        15,     1,      973,    "R/W1C",        1,      0,      0,      0ull},
74194         {"LT_FI_E"                     ,        16,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74195         {"LT_FI_F"                     ,        17,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74196         {"RG_FI_E"                     ,        18,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74197         {"RG_FI_F"                     ,        19,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74198         {"RQ_Q2_F"                     ,        20,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74199         {"RQ_Q2_E"                     ,        21,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74200         {"RQ_Q3_F"                     ,        22,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74201         {"RQ_Q3_E"                     ,        23,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74202         {"UOD_PE"                      ,        24,     1,      973,    "R/W1C",        1,      0,      0,      0ull},
74203         {"UOD_PF"                      ,        25,     1,      973,    "R/W1C",        1,      0,      0,      0ull},
74204         {"RESERVED_26_31"              ,        26,     6,      973,    "RAZ",  1,      0,      0,      0ull},
74205         {"LTL_F_PE"                    ,        32,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74206         {"LTL_F_PF"                    ,        33,     1,      973,    "R/W1C",        0,      0,      0ull,   0ull},
74207         {"ND4O_RPE"                    ,        34,     1,      973,    "R/W1C",        1,      0,      0,      0ull},
74208         {"ND4O_RPF"                    ,        35,     1,      973,    "R/W1C",        1,      0,      0,      0ull},
74209         {"ND4O_DPE"                    ,        36,     1,      973,    "R/W1C",        1,      0,      0,      0ull},
74210         {"ND4O_DPF"                    ,        37,     1,      973,    "R/W1C",        1,      0,      0,      0ull},
74211         {"RESERVED_38_63"              ,        38,     26,     973,    "RAZ",  1,      1,      0,      0},
74212         {"ATE_RESET"                   ,        0,      1,      974,    "R/W",  0,      0,      0ull,   0ull},
74213         {"TDATA_IN"                    ,        1,      8,      974,    "R/W",  0,      0,      0ull,   0ull},
74214         {"TADDR_IN"                    ,        9,      4,      974,    "R/W",  0,      0,      0ull,   0ull},
74215         {"TDATA_SEL"                   ,        13,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74216         {"BIST_ENB"                    ,        14,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74217         {"VTEST_ENB"                   ,        15,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74218         {"LOOP_ENB"                    ,        16,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74219         {"TX_BS_EN"                    ,        17,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74220         {"TX_BS_ENH"                   ,        18,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74221         {"RESERVED_19_22"              ,        19,     4,      974,    "RAZ",  0,      0,      0ull,   0ull},
74222         {"HST_MODE"                    ,        23,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74223         {"DM_PULLD"                    ,        24,     1,      974,    "R/W",  0,      0,      1ull,   1ull},
74224         {"DP_PULLD"                    ,        25,     1,      974,    "R/W",  0,      0,      1ull,   1ull},
74225         {"TCLK"                        ,        26,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74226         {"USBP_BIST"                   ,        27,     1,      974,    "R/W",  0,      0,      1ull,   1ull},
74227         {"USBC_END"                    ,        28,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74228         {"DMA_BMODE"                   ,        29,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74229         {"TXPREEMPHASISTUNE"           ,        30,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74230         {"SIDDQ"                       ,        31,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74231         {"TDATA_OUT"                   ,        32,     4,      974,    "RO",   1,      1,      0,      0},
74232         {"BIST_ERR"                    ,        36,     1,      974,    "RO",   0,      0,      0ull,   0ull},
74233         {"BIST_DONE"                   ,        37,     1,      974,    "RO",   0,      0,      0ull,   0ull},
74234         {"HSBIST"                      ,        38,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74235         {"FSBIST"                      ,        39,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74236         {"LSBIST"                      ,        40,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74237         {"DRVVBUS"                     ,        41,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74238         {"PORTRESET"                   ,        42,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74239         {"OTGDISABLE"                  ,        43,     1,      974,    "R/W",  0,      0,      1ull,   1ull},
74240         {"OTGTUNE"                     ,        44,     3,      974,    "R/W",  0,      0,      2ull,   2ull},
74241         {"COMPDISTUNE"                 ,        47,     3,      974,    "R/W",  0,      0,      2ull,   2ull},
74242         {"SQRXTUNE"                    ,        50,     3,      974,    "R/W",  0,      0,      3ull,   3ull},
74243         {"TXHSXVTUNE"                  ,        53,     2,      974,    "R/W",  0,      0,      0ull,   0ull},
74244         {"TXFSLSTUNE"                  ,        55,     4,      974,    "R/W",  0,      0,      3ull,   3ull},
74245         {"TXVREFTUNE"                  ,        59,     4,      974,    "R/W",  0,      0,      7ull,   7ull},
74246         {"TXRISETUNE"                  ,        63,     1,      974,    "R/W",  0,      0,      0ull,   0ull},
74247         {NULL,0,0,0,0,0,0,0,0}
74248 };
74249
74250
74251 const CVMX_CSR_DB_TYPE *cvmx_csr_db[] = {
74252         cvmx_csr_db_cn38xxp2,
74253         cvmx_csr_db_cn31xx,
74254         cvmx_csr_db_cn30xx,
74255         cvmx_csr_db_cn38xx,
74256         cvmx_csr_db_cn58xxp1,
74257         cvmx_csr_db_cn58xx,
74258         cvmx_csr_db_cn56xxp1,
74259         cvmx_csr_db_cn56xx,
74260         cvmx_csr_db_cn50xx,
74261         cvmx_csr_db_cn52xxp1,
74262         cvmx_csr_db_cn52xx,
74263         NULL
74264 };
74265 const CVMX_CSR_DB_ADDRESS_TYPE *cvmx_csr_db_addresses[] = {
74266         cvmx_csr_db_addresses_cn38xxp2,
74267         cvmx_csr_db_addresses_cn31xx,
74268         cvmx_csr_db_addresses_cn30xx,
74269         cvmx_csr_db_addresses_cn38xx,
74270         cvmx_csr_db_addresses_cn58xxp1,
74271         cvmx_csr_db_addresses_cn58xx,
74272         cvmx_csr_db_addresses_cn56xxp1,
74273         cvmx_csr_db_addresses_cn56xx,
74274         cvmx_csr_db_addresses_cn50xx,
74275         cvmx_csr_db_addresses_cn52xxp1,
74276         cvmx_csr_db_addresses_cn52xx,
74277         NULL
74278 };
74279 const CVMX_CSR_DB_FIELD_TYPE *cvmx_csr_db_fields[] = {
74280         cvmx_csr_db_fields_cn38xxp2,
74281         cvmx_csr_db_fields_cn31xx,
74282         cvmx_csr_db_fields_cn30xx,
74283         cvmx_csr_db_fields_cn38xx,
74284         cvmx_csr_db_fields_cn58xxp1,
74285         cvmx_csr_db_fields_cn58xx,
74286         cvmx_csr_db_fields_cn56xxp1,
74287         cvmx_csr_db_fields_cn56xx,
74288         cvmx_csr_db_fields_cn50xx,
74289         cvmx_csr_db_fields_cn52xxp1,
74290         cvmx_csr_db_fields_cn52xx,
74291         NULL
74292 };