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47 * Functions and typedefs for using Octeon in HiGig/HiGig+/HiGig2 mode over
50 * <hr>$Revision: 41586 $<hr>
53 #ifndef __CVMX_HIGIG_H__
54 #define __CVMX_HIGIG_H__
68 uint32_t start : 8; /**< 8-bits of Preamble indicating start of frame */
69 uint32_t dst_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
70 DST_MODID (bits 4:0 are in Byte 7 and bit 5 is in Byte 9). ). For HGI field
71 value of b'01' this field should be b'1'. For all other values of HGI it is don't
73 uint32_t src_modid_6 : 1; /**< This field is valid only if the HGI field is a b'10' and it represents Bit 6 of
74 SRC_MODID (bits 4:0 are in Byte 4 and bit 5 is in Byte 9). For HGI field
75 value of b'01' this field should be b'0'. For all other values of HGI it is don't
77 uint32_t hdr_ext_len : 3; /**< This field is valid only if the HGI field is a b'10' and it indicates the extension
78 to the standard 12-bytes of XGS HiGig header. Each unit represents 4
79 bytes, giving a total of 16 additional extension bytes. Value of b'101', b'110'
80 and b'111' are reserved. For HGI field value of b'01' this field should be
81 b'01'. For all other values of HGI it is don't care. */
82 uint32_t cng_high : 1; /**< Congestion Bit High flag */
83 uint32_t hgi : 2; /**< HiGig interface format indicator
85 01 = Pure preamble - IEEE standard framing of 10GE
86 10 = XGS header - framing based on XGS family definition In this
87 format, the default length of the header is 12 bytes and additional
88 bytes are indicated by the HDR_EXT_LEN field
90 uint32_t vid_high : 8; /**< 8-bits of the VLAN tag information */
91 uint32_t vid_low : 8; /**< 8 bits LSB of the VLAN tag information */
99 uint32_t opcode : 3; /**< XGS HiGig op-code, indicating the type of packet
100 000 = Control frames used for CPU to CPU communications
101 001 = Unicast packet with destination resolved; The packet can be
102 either Layer 2 unicast packet or L3 unicast packet that was
103 routed in the ingress chip.
104 010 = Broadcast or unknown Unicast packet or unknown multicast,
105 destined to all members of the VLAN
106 011 = L2 Multicast packet, destined to all ports of the group indicated
107 in the L2MC_INDEX which is overlayed on DST_PORT/DST_MODID fields
108 100 = IP Multicast packet, destined to all ports of the group indicated
109 in the IPMC_INDEX which is overlayed on DST_PORT/DST_MODID fields
113 uint32_t src_modid_low : 5; /**< Bits 4:0 of Module ID of the source module on which the packet ingress (bit
114 5 is in Byte 9 and bit 6 Is in Byte 1) */
115 uint32_t src_port_tgid : 6; /**< If the MSB of this field is set, then it indicates the LAG the packet ingressed
116 on, else it represents the physical port the packet ingressed on. */
117 uint32_t pfm : 2; /**< Three Port Filtering Modes (0, 1, 2) used in handling registed/unregistered
118 multicast (unknown L2 multicast and IPMC) packets. This field is used
119 when OPCODE is 011 or 100 Semantics of PFM bits are as follows;
120 For registered L2 multicast packets:
121 PFM= 0 Flood to VLAN
122 PFM= 1 or 2 Send to group members in the L2MC table
123 For unregistered L2 multicast packets:
124 PFM= 0 or 1 Flood to VLAN
125 PFM= 2 Drop the packet */
126 uint32_t priority : 3; /**< This is the internal priority of the packet. This internal priority will go through
127 COS_SEL mapping registers to map to the actual MMU queues. */
128 uint32_t dst_port : 5; /**< Port number of destination port on which the packet needs to egress. */
129 uint32_t dst_modid_low : 5; /**< Bits [4-: 0] of Module ID of the destination port on which the packet needs to egress. */
130 uint32_t cng_low : 1; /**< Semantics of CNG_HIGH and CNG_LOW are as follows: The following
131 encodings are to make it backward compatible:
132 {CNG_HIGH, CNG_LOW] - COLOR
133 [0, 0] Packet is green
134 [0, 1] Packet is red
135 [1, 1] Packet is yellow
136 [1, 0] Undefined */
137 uint32_t header_type : 2; /**< Indicates the format of the next 4 bytes of the XGS HiGig header
138 00 = Overlay 1 (default)
139 01 = Overlay 2 (Classification Tag)
149 uint32_t mirror : 1; /**< Mirror: XGS3 mode: a mirror copy packet. XGS1/2 mode: Indicates that the
150 packet was switched and only needs to be mirrored. */
151 uint32_t mirror_done : 1; /**< Mirroring Done: XGS1/2 mode: Indicates that the packet was mirrored and
152 may still need to be switched. */
153 uint32_t mirror_only : 1; /**< Mirror Only: XGS 1/2 mode: Indicates that the packet was switched and only
154 needs to be mirrored. */
155 uint32_t ingress_tagged : 1; /**< Ingress Tagged: Indicates whether the packet was tagged when it originally
156 ingressed the system. */
157 uint32_t dst_tgid : 3; /**< Destination Trunk Group ID: Trunk group ID of the destination port. The
158 DO_NOT_LEARN bit is overlaid on the second bit of this field. */
159 uint32_t dst_t : 1; /**< Destination Trunk: Indicates that the destination port is a member of a trunk
161 uint32_t vc_label_16_19 : 4; /**< VC Label: Bits 19:16 of VC label: HiGig+ added field */
162 uint32_t label_present : 1; /**< Label Present: Indicates that header contains a 20-bit VC label: HiGig+
164 uint32_t l3 : 1; /**< L3: Indicates that the packet is L3 switched */
165 uint32_t dst_modid_5 : 1; /**< Destination Module ID: Bit 5 of Dst_ModID (bits 4:0 are in byte 7 and bit 6
167 uint32_t src_modid_5 : 1; /**< Source Module ID: Bit 5 of Src_ModID (bits 4:0 are in byte 4 and bit 6 is in
169 uint32_t vc_label_0_15 : 16;/**< VC Label: Bits 15:0 of VC label: HiGig+ added field */
173 uint32_t classification : 16; /**< Classification tag information from the HiGig device FFP */
174 uint32_t reserved_0_15 : 16;
178 } cvmx_higig_header_t;
182 * Initialize the HiGig aspects of a XAUI interface. This function
183 * should be called before the cvmx-helper generic init.
185 * @param interface Interface to initialize HiGig on (0-1)
186 * @param enable_higig2
187 * Non zero to enable HiGig2 support. Zero to support HiGig
190 * @return Zero on success, negative on failure
192 static inline int cvmx_higig_initialize(int interface, int enable_higig2)
194 cvmx_pip_prt_cfgx_t pip_prt_cfg;
195 cvmx_gmxx_rxx_udd_skp_t gmx_rx_udd_skp;
196 cvmx_gmxx_txx_min_pkt_t gmx_tx_min_pkt;
197 cvmx_gmxx_txx_append_t gmx_tx_append;
198 cvmx_gmxx_tx_ifg_t gmx_tx_ifg;
199 cvmx_gmxx_tx_ovr_bp_t gmx_tx_ovr_bp;
200 cvmx_gmxx_rxx_frm_ctl_t gmx_rx_frm_ctl;
201 cvmx_gmxx_tx_xaui_ctl_t gmx_tx_xaui_ctl;
203 int header_size = (enable_higig2) ? 16 : 12;
205 /* Setup PIP to handle HiGig */
206 pip_prt_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(interface*16));
207 pip_prt_cfg.s.dsa_en = 0;
208 pip_prt_cfg.s.higig_en = 1;
209 pip_prt_cfg.s.hg_qos = 1;
210 pip_prt_cfg.s.skip = header_size;
211 cvmx_write_csr(CVMX_PIP_PRT_CFGX(interface*16), pip_prt_cfg.u64);
213 /* Setup some sample QoS defaults. These can be changed later */
216 cvmx_pip_hg_pri_qos_t pip_hg_pri_qos;
217 pip_hg_pri_qos.u64 = 0;
218 pip_hg_pri_qos.s.up_qos = 1;
219 pip_hg_pri_qos.s.pri = i;
220 pip_hg_pri_qos.s.qos = i&7;
221 cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64);
224 /* Setup GMX RX to treat the HiGig header as user data to ignore */
225 gmx_rx_udd_skp.u64 = cvmx_read_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface));
226 gmx_rx_udd_skp.s.len = header_size;
227 gmx_rx_udd_skp.s.fcssel = 0;
228 cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64);
230 /* Disable GMX preamble checking */
231 gmx_rx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface));
232 gmx_rx_frm_ctl.s.pre_chk = 0;
233 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64);
235 /* Setup GMX TX to pad properly min sized packets */
236 gmx_tx_min_pkt.u64 = cvmx_read_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface));
237 gmx_tx_min_pkt.s.min_size = 59 + header_size;
238 cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64);
240 /* Setup GMX TX to not add a preamble */
241 gmx_tx_append.u64 = cvmx_read_csr(CVMX_GMXX_TXX_APPEND(0, interface));
242 gmx_tx_append.s.preamble = 0;
243 cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64);
245 /* Reduce the inter frame gap to 8 bytes */
246 gmx_tx_ifg.u64 = cvmx_read_csr(CVMX_GMXX_TX_IFG(interface));
247 gmx_tx_ifg.s.ifg1 = 4;
248 gmx_tx_ifg.s.ifg2 = 4;
249 cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64);
251 /* Disable GMX backpressure */
252 gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
253 gmx_tx_ovr_bp.s.bp = 0;
254 gmx_tx_ovr_bp.s.en = 0xf;
255 gmx_tx_ovr_bp.s.ign_full = 0xf;
256 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
260 /* Enable HiGig2 support and forwarding of virtual port backpressure
262 cvmx_gmxx_hg2_control_t gmx_hg2_control;
263 gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
264 gmx_hg2_control.s.hg2rx_en = 1;
265 gmx_hg2_control.s.hg2tx_en = 1;
266 gmx_hg2_control.s.logl_en = 0xffff;
267 gmx_hg2_control.s.phys_en = 1;
268 cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64);
272 gmx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
273 gmx_tx_xaui_ctl.s.hg_en = 1;
274 cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmx_tx_xaui_ctl.u64);
283 #endif // __CVMX_HIGIG_H__