1 /***********************license start***************
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
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7 * modification, are permitted provided that the following conditions are
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37 ***********************license end**************************************/
47 * Interface to the on chip key memory. Key memory is
48 * 8k on chip that is inaccessible from off chip. It can
49 * also be cleared using an external hardware pin.
51 * <hr>$Revision: 41586 $<hr>
55 #ifndef __CVMX_KEY_H__
56 #define __CVMX_KEY_H__
62 #define CVMX_KEY_MEM_SIZE 8192 /* Size in bytes */
66 * Read from KEY memory
68 * @param address Address (byte) in key memory to read
69 * 0 <= address < CVMX_KEY_MEM_SIZE
70 * @return Value from key memory
72 static inline uint64_t cvmx_key_read(uint64_t address)
77 ptr.sio.mem_region = CVMX_IO_SEG;
79 ptr.sio.did = CVMX_OCT_DID_KEY_RW;
80 ptr.sio.offset = address;
82 return cvmx_read_csr(ptr.u64);
89 * @param address Address (byte) in key memory to write
90 * 0 <= address < CVMX_KEY_MEM_SIZE
91 * @param value Value to write to key memory
93 static inline void cvmx_key_write(uint64_t address, uint64_t value)
98 ptr.sio.mem_region = CVMX_IO_SEG;
100 ptr.sio.did = CVMX_OCT_DID_KEY_RW;
101 ptr.sio.offset = address;
103 cvmx_write_io(ptr.u64, value);
107 /* CSR typedefs have been moved to cvmx-csr-*.h */
113 #endif /* __CVMX_KEY_H__ */