sys/mips/atheros/ar71xx_chip.c

   1 /*-
   2  * Copyright (c) 2010 Adrian Chadd
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include <sys/param.h>
  31 #include <machine/cpuregs.h>
  32
  33 #include <mips/sentry5/s5reg.h>
  34
  35 #include "opt_ddb.h"
  36
  37 #include <sys/param.h>
  38 #include <sys/conf.h>
  39 #include <sys/kernel.h>
  40 #include <sys/systm.h>
  41 #include <sys/bus.h>
  42 #include <sys/cons.h>
  43 #include <sys/kdb.h>
  44 #include <sys/reboot.h>
  45
  46 #include <vm/vm.h>
  47 #include <vm/vm_page.h>
  48
  49 #include <net/ethernet.h>
  50
  51 #include <machine/clock.h>
  52 #include <machine/cpu.h>
  53 #include <machine/hwfunc.h>
  54 #include <machine/md_var.h>
  55 #include <machine/trap.h>
  56 #include <machine/vmparam.h>
  57
  58 #include <mips/atheros/ar71xxreg.h>
  59
  60 #include <mips/atheros/ar71xx_chip.h>
  61
  62 #include <mips/atheros/ar71xx_cpudef.h>
  63
  64 /* XXX these should replace the current definitions in ar71xxreg.h */
  65 /* XXX perhaps an ar71xx_chip.h header file? */
  66 #define AR71XX_PLL_REG_CPU_CONFIG       AR71XX_PLL_CPU_BASE + 0x00
  67 #define AR71XX_PLL_REG_SEC_CONFIG       AR71XX_PLL_CPU_BASE + 0x04
  68 #define AR71XX_PLL_REG_ETH0_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x10
  69 #define AR71XX_PLL_REG_ETH1_INT_CLOCK   AR71XX_PLL_CPU_BASE + 0x14
  70
  71 #define AR71XX_PLL_DIV_SHIFT            3
  72 #define AR71XX_PLL_DIV_MASK             0x1f
  73 #define AR71XX_CPU_DIV_SHIFT            16
  74 #define AR71XX_CPU_DIV_MASK             0x3
  75 #define AR71XX_DDR_DIV_SHIFT            18
  76 #define AR71XX_DDR_DIV_MASK             0x3
  77 #define AR71XX_AHB_DIV_SHIFT            20
  78 #define AR71XX_AHB_DIV_MASK             0x7
  79
  80 /* XXX these shouldn't be in here - this file is a per-chip file */
  81 /* XXX these should be in the top-level ar71xx type, not ar71xx -chip */
  82 uint32_t u_ar71xx_cpu_freq;
  83 uint32_t u_ar71xx_ahb_freq;
  84 uint32_t u_ar71xx_ddr_freq;
  85
  86 static void
  87 ar71xx_chip_detect_mem_size(void)
  88 {
  89 }
  90
  91 static void
  92 ar71xx_chip_detect_sys_frequency(void)
  93 {
  94         uint32_t pll;
  95         uint32_t freq;
  96         uint32_t div;
  97
  98         pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG);
  99
 100         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 101         freq = div * AR71XX_BASE_FREQ;
 102
 103         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 104         u_ar71xx_cpu_freq = freq / div;
 105
 106         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 107         u_ar71xx_ddr_freq = freq / div;
 108
 109         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 110         u_ar71xx_ahb_freq = u_ar71xx_cpu_freq / div;
 111 }
 112
 113 /*
 114  * This does not lock the CPU whilst doing the work!
 115  */
 116 static void
 117 ar71xx_chip_device_stop(uint32_t mask)
 118 {
 119         uint32_t reg;
 120
 121         reg = ATH_READ_REG(AR71XX_RST_RESET);
 122         ATH_WRITE_REG(AR71XX_RST_RESET, reg | mask);
 123 }
 124
 125 static void
 126 ar71xx_chip_device_start(uint32_t mask)
 127 {
 128         uint32_t reg;
 129
 130         reg = ATH_READ_REG(AR71XX_RST_RESET);
 131         ATH_WRITE_REG(AR71XX_RST_RESET, reg & ~mask);
 132 }
 133
 134 static int
 135 ar71xx_chip_device_stopped(uint32_t mask)
 136 {
 137         uint32_t reg;
 138
 139         reg = ATH_READ_REG(AR71XX_RST_RESET);
 140         return ((reg & mask) == mask);
 141 }
 142
 143 /* Speed is either 10, 100 or 1000 */
 144 static void
 145 ar71xx_chip_set_pll_ge0(int speed)
 146 {
 147         uint32_t pll;
 148
 149         switch(speed) {
 150                 case 10:
 151                         pll = PLL_ETH_INT_CLK_10;
 152                         break;
 153                 case 100:
 154                         pll = PLL_ETH_INT_CLK_100;
 155                         break;
 156                 case 1000:
 157                         pll = PLL_ETH_INT_CLK_1000;
 158                         break;
 159                 default:
 160                         printf("ar71xx_chip_set_pll_ge0: invalid speed %d\n", speed);
 161                         return;
 162         }
 163
 164         ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT0_CLK, pll, AR71XX_PLL_ETH0_SHIFT);
 165 }
 166
 167 static void
 168 ar71xx_chip_set_pll_ge1(int speed)
 169 {
 170         uint32_t pll;
 171
 172         switch(speed) {
 173                 case 10:
 174                         pll = PLL_ETH_INT_CLK_10;
 175                         break;
 176                 case 100:
 177                         pll = PLL_ETH_INT_CLK_100;
 178                         break;
 179                 case 1000:
 180                         pll = PLL_ETH_INT_CLK_1000;
 181                         break;
 182                 default:
 183                         printf("ar71xx_chip_set_pll_ge1: invalid speed %d\n", speed);
 184                         return;
 185         }
 186
 187         ar71xx_write_pll(AR71XX_PLL_SEC_CONFIG, AR71XX_PLL_ETH_INT1_CLK, pll, AR71XX_PLL_ETH1_SHIFT);
 188 }
 189
 190 static void
 191 ar71xx_chip_ddr_flush_ge0(void)
 192 {
 193         ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE0);
 194 }
 195
 196 static void
 197 ar71xx_chip_ddr_flush_ge1(void)
 198 {
 199         ar71xx_ddr_flush(AR71XX_WB_FLUSH_GE1);
 200 }
 201
 202 static uint32_t
 203 ar71xx_chip_get_eth_pll(unsigned int mac, int speed)
 204 {
 205         return 0;
 206 }
 207
 208 static void
 209 ar71xx_chip_init_usb_peripheral(void)
 210 {
 211         ar71xx_device_stop(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
 212         DELAY(1000);
 213
 214         ar71xx_device_start(RST_RESET_USB_OHCI_DLL | RST_RESET_USB_HOST | RST_RESET_USB_PHY);
 215         DELAY(1000);
 216
 217         ATH_WRITE_REG(AR71XX_USB_CTRL_CONFIG,
 218             USB_CTRL_CONFIG_OHCI_DES_SWAP | USB_CTRL_CONFIG_OHCI_BUF_SWAP |
 219             USB_CTRL_CONFIG_EHCI_DES_SWAP | USB_CTRL_CONFIG_EHCI_BUF_SWAP);
 220
 221         ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
 222             (32 << USB_CTRL_FLADJ_HOST_SHIFT) | (3 << USB_CTRL_FLADJ_A5_SHIFT));
 223
 224         DELAY(1000);
 225 }
 226
 227 struct ar71xx_cpu_def ar71xx_chip_def = {
 228         &ar71xx_chip_detect_mem_size,
 229         &ar71xx_chip_detect_sys_frequency,
 230         &ar71xx_chip_device_stop,
 231         &ar71xx_chip_device_start,
 232         &ar71xx_chip_device_stopped,
 233         &ar71xx_chip_set_pll_ge0,
 234         &ar71xx_chip_set_pll_ge1,
 235         &ar71xx_chip_ddr_flush_ge0,
 236         &ar71xx_chip_ddr_flush_ge1,
 237         &ar71xx_chip_get_eth_pll,
 238         NULL,
 239         &ar71xx_chip_init_usb_peripheral,
 240 };