2 * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <machine/bus.h>
36 #include <dev/uart/uart.h>
37 #include <dev/uart/uart_cpu.h>
38 #include <dev/uart/uart_bus.h>
40 #include <mips/atheros/ar933x_uart.h>
45 * Default system clock is 25MHz; see ar933x_chip.c for how
46 * the startup process determines whether it's 25MHz or 40MHz.
48 #define DEFAULT_RCLK (25 * 1000 * 1000)
50 #define ar933x_getreg(bas, reg) \
51 bus_space_read_4((bas)->bst, (bas)->bsh, reg)
52 #define ar933x_setreg(bas, reg, value) \
53 bus_space_write_4((bas)->bst, (bas)->bsh, reg, value)
58 ar933x_drain(struct uart_bas *bas, int what)
62 if (what & UART_DRAIN_TRANSMITTER) {
65 /* Loop over until the TX FIFO shows entirely clear */
67 if ((ar933x_getreg(bas, AR933X_UART_CS_REG)
68 & AR933X_UART_CS_TX_BUSY) == 0)
76 if (what & UART_DRAIN_RECEIVER) {
80 /* XXX duplicated from ar933x_getc() */
81 /* XXX TODO: refactor! */
83 /* If there's nothing to read, stop! */
84 if ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
85 AR933X_UART_DATA_RX_CSR) == 0) {
89 /* Read the top of the RX FIFO */
90 (void) ar933x_getreg(bas, AR933X_UART_DATA_REG);
92 /* Remove that entry from said RX FIFO */
93 ar933x_setreg(bas, AR933X_UART_DATA_REG,
94 AR933X_UART_DATA_RX_CSR);
107 * Calculate the baud from the given chip configuration parameters.
110 ar933x_uart_get_baud(unsigned int clk, unsigned int scale,
116 div = (2 << 16) * (scale + 1);
126 * Calculate the scale/step with the lowest possible deviation from
127 * the target baudrate.
130 ar933x_uart_get_scale_step(struct uart_bas *bas, unsigned int baud,
131 unsigned int *scale, unsigned int *step)
142 for (tscale = 0; tscale < AR933X_UART_MAX_SCALE; tscale++) {
146 tstep = baud * (tscale + 1);
150 if (tstep > AR933X_UART_MAX_STEP)
153 diff = abs(ar933x_uart_get_baud(clk, tscale, tstep) - baud);
154 if (diff < min_diff) {
163 ar933x_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
166 /* UART always 8 bits */
168 /* UART always 1 stop bit */
170 /* UART parity is controllable by bits 0:1, ignore for now */
172 /* Set baudrate if required. */
174 uint32_t clock_scale, clock_step;
176 /* Find the best fit for the given baud rate */
177 ar933x_uart_get_scale_step(bas, baudrate, &clock_scale,
181 * Program the clock register in its entirety - no need
182 * for Read-Modify-Write.
184 ar933x_setreg(bas, AR933X_UART_CLOCK_REG,
185 ((clock_scale & AR933X_UART_CLOCK_SCALE_M)
186 << AR933X_UART_CLOCK_SCALE_S) |
187 (clock_step & AR933X_UART_CLOCK_STEP_M));
196 * Low-level UART interface.
198 static int ar933x_probe(struct uart_bas *bas);
199 static void ar933x_init(struct uart_bas *bas, int, int, int, int);
200 static void ar933x_term(struct uart_bas *bas);
201 static void ar933x_putc(struct uart_bas *bas, int);
202 static int ar933x_rxready(struct uart_bas *bas);
203 static int ar933x_getc(struct uart_bas *bas, struct mtx *);
205 static struct uart_ops uart_ar933x_ops = {
206 .probe = ar933x_probe,
210 .rxready = ar933x_rxready,
215 ar933x_probe(struct uart_bas *bas)
218 /* We always know this will be here */
223 ar933x_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
228 /* Setup default parameters */
229 ar933x_param(bas, baudrate, databits, stopbits, parity);
231 /* XXX Force enable UART in case it was disabled */
233 /* Disable all interrupts */
234 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
236 /* Disable the host interrupt */
237 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
238 reg &= ~AR933X_UART_CS_HOST_INT_EN;
239 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
243 /* XXX Set RTS/DTR? */
247 * Detach from console.
250 ar933x_term(struct uart_bas *bas)
257 ar933x_putc(struct uart_bas *bas, int c)
263 /* Wait for space in the TX FIFO */
264 while ( ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
265 AR933X_UART_DATA_TX_CSR) == 0) && --limit)
268 /* Write the actual byte */
269 ar933x_setreg(bas, AR933X_UART_DATA_REG,
270 (c & 0xff) | AR933X_UART_DATA_TX_CSR);
274 ar933x_rxready(struct uart_bas *bas)
277 /* Wait for a character to come ready */
278 return (!!(ar933x_getreg(bas, AR933X_UART_DATA_REG)
279 & AR933X_UART_DATA_RX_CSR));
283 ar933x_getc(struct uart_bas *bas, struct mtx *hwmtx)
289 /* Wait for a character to come ready */
290 while ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
291 AR933X_UART_DATA_RX_CSR) == 0) {
297 /* Read the top of the RX FIFO */
298 c = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
300 /* Remove that entry from said RX FIFO */
301 ar933x_setreg(bas, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
309 * High-level UART interface.
311 struct ar933x_softc {
312 struct uart_softc base;
317 static int ar933x_bus_attach(struct uart_softc *);
318 static int ar933x_bus_detach(struct uart_softc *);
319 static int ar933x_bus_flush(struct uart_softc *, int);
320 static int ar933x_bus_getsig(struct uart_softc *);
321 static int ar933x_bus_ioctl(struct uart_softc *, int, intptr_t);
322 static int ar933x_bus_ipend(struct uart_softc *);
323 static int ar933x_bus_param(struct uart_softc *, int, int, int, int);
324 static int ar933x_bus_probe(struct uart_softc *);
325 static int ar933x_bus_receive(struct uart_softc *);
326 static int ar933x_bus_setsig(struct uart_softc *, int);
327 static int ar933x_bus_transmit(struct uart_softc *);
329 static kobj_method_t ar933x_methods[] = {
330 KOBJMETHOD(uart_attach, ar933x_bus_attach),
331 KOBJMETHOD(uart_detach, ar933x_bus_detach),
332 KOBJMETHOD(uart_flush, ar933x_bus_flush),
333 KOBJMETHOD(uart_getsig, ar933x_bus_getsig),
334 KOBJMETHOD(uart_ioctl, ar933x_bus_ioctl),
335 KOBJMETHOD(uart_ipend, ar933x_bus_ipend),
336 KOBJMETHOD(uart_param, ar933x_bus_param),
337 KOBJMETHOD(uart_probe, ar933x_bus_probe),
338 KOBJMETHOD(uart_receive, ar933x_bus_receive),
339 KOBJMETHOD(uart_setsig, ar933x_bus_setsig),
340 KOBJMETHOD(uart_transmit, ar933x_bus_transmit),
344 struct uart_class uart_ar933x_class = {
347 sizeof(struct ar933x_softc),
348 .uc_ops = &uart_ar933x_ops,
350 .uc_rclk = DEFAULT_RCLK
353 #define SIGCHG(c, i, s, d) \
355 i |= (i & s) ? s : s | d; \
357 i = (i & s) ? (i & ~s) | d : i; \
361 ar933x_bus_attach(struct uart_softc *sc)
363 struct ar933x_softc *u = (struct ar933x_softc *)sc;
364 struct uart_bas *bas = &sc->sc_bas;
367 /* XXX TODO: flush transmitter */
370 * Setup initial interrupt notifications.
372 * XXX for now, just RX FIFO valid.
373 * Later on (when they're handled), also handle
374 * RX errors/overflow.
376 u->u_ier = AR933X_UART_INT_RX_VALID;
378 /* Enable RX interrupts to kick-start things */
379 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
381 /* Enable the host interrupt now */
382 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
383 reg |= AR933X_UART_CS_HOST_INT_EN;
384 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
390 ar933x_bus_detach(struct uart_softc *sc)
392 struct uart_bas *bas = &sc->sc_bas;
395 /* Disable all interrupts */
396 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, 0x00000000);
398 /* Disable the host interrupt */
399 reg = ar933x_getreg(bas, AR933X_UART_CS_REG);
400 reg &= ~AR933X_UART_CS_HOST_INT_EN;
401 ar933x_setreg(bas, AR933X_UART_CS_REG, reg);
408 ar933x_bus_flush(struct uart_softc *sc, int what)
410 struct uart_bas *bas;
413 uart_lock(sc->sc_hwmtx);
414 ar933x_drain(bas, what);
415 uart_unlock(sc->sc_hwmtx);
421 ar933x_bus_getsig(struct uart_softc *sc)
423 uint32_t sig = sc->sc_hwsig;
426 * For now, let's just return that DSR/DCD/CTS is asserted.
428 * XXX TODO: actually verify whether this is correct!
430 SIGCHG(1, sig, SER_DSR, SER_DDSR);
431 SIGCHG(1, sig, SER_CTS, SER_DCTS);
432 SIGCHG(1, sig, SER_DCD, SER_DDCD);
433 SIGCHG(1, sig, SER_RI, SER_DRI);
435 sc->sc_hwsig = sig & ~SER_MASK_DELTA;
441 ar933x_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
444 struct uart_bas *bas;
445 int baudrate, divisor, error;
450 uart_lock(sc->sc_hwmtx);
452 case UART_IOCTL_BREAK:
453 lcr = uart_getreg(bas, REG_LCR);
458 uart_setreg(bas, REG_LCR, lcr);
461 case UART_IOCTL_IFLOW:
462 lcr = uart_getreg(bas, REG_LCR);
464 uart_setreg(bas, REG_LCR, 0xbf);
466 efr = uart_getreg(bas, REG_EFR);
471 uart_setreg(bas, REG_EFR, efr);
473 uart_setreg(bas, REG_LCR, lcr);
476 case UART_IOCTL_OFLOW:
477 lcr = uart_getreg(bas, REG_LCR);
479 uart_setreg(bas, REG_LCR, 0xbf);
481 efr = uart_getreg(bas, REG_EFR);
486 uart_setreg(bas, REG_EFR, efr);
488 uart_setreg(bas, REG_LCR, lcr);
491 case UART_IOCTL_BAUD:
492 lcr = uart_getreg(bas, REG_LCR);
493 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
495 divisor = uart_getreg(bas, REG_DLL) |
496 (uart_getreg(bas, REG_DLH) << 8);
498 uart_setreg(bas, REG_LCR, lcr);
500 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
502 *(int*)data = baudrate;
510 uart_unlock(sc->sc_hwmtx);
517 * Bus interrupt handler.
519 * For now, system interrupts are disabled.
520 * So this is just called from a callout in uart_core.c
521 * to poll various state.
524 ar933x_bus_ipend(struct uart_softc *sc)
526 struct ar933x_softc *u = (struct ar933x_softc *)sc;
527 struct uart_bas *bas = &sc->sc_bas;
531 uart_lock(sc->sc_hwmtx);
534 * Fetch/ACK the ISR status.
536 isr = ar933x_getreg(bas, AR933X_UART_INT_REG);
537 ar933x_setreg(bas, AR933X_UART_INT_REG, isr);
541 * RX ready - notify upper layer.
543 if (isr & AR933X_UART_INT_RX_VALID) {
544 ipend |= SER_INT_RXREADY;
548 * If we get this interrupt, we should disable
549 * it from the interrupt mask and inform the uart
550 * driver appropriately.
552 * We can't keep setting SER_INT_TXIDLE or SER_INT_SIGCHG
553 * all the time or IO stops working. So we will always
554 * clear this interrupt if we get it, then we only signal
555 * the upper layer if we were doing active TX in the
558 * Also, the name is misleading. This actually means
559 * "the FIFO is almost empty." So if we just write some
560 * more data to the FIFO without checking whether it can
561 * take said data, we'll overflow the thing.
563 * Unfortunately the FreeBSD uart device has no concept of
564 * partial UART writes - it expects that the whole buffer
565 * is written to the hardware. Thus for now, ar933x_bus_transmit()
566 * will wait for the FIFO to finish draining before it pushes
567 * more frames into it.
569 if (isr & AR933X_UART_INT_TX_EMPTY) {
571 * Update u_ier to disable TX notifications; update hardware
573 u->u_ier &= ~AR933X_UART_INT_TX_EMPTY;
574 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
579 * Only signal TX idle if we're not busy transmitting.
582 if (isr & AR933X_UART_INT_TX_EMPTY) {
583 ipend |= SER_INT_TXIDLE;
585 ipend |= SER_INT_SIGCHG;
589 uart_unlock(sc->sc_hwmtx);
594 ar933x_bus_param(struct uart_softc *sc, int baudrate, int databits,
595 int stopbits, int parity)
597 struct uart_bas *bas;
601 uart_lock(sc->sc_hwmtx);
602 error = ar933x_param(bas, baudrate, databits, stopbits, parity);
603 uart_unlock(sc->sc_hwmtx);
608 ar933x_bus_probe(struct uart_softc *sc)
610 struct uart_bas *bas;
615 error = ar933x_probe(bas);
620 ar933x_drain(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
622 /* XXX TODO: actually find out what the FIFO depth is! */
623 sc->sc_rxfifosz = 16;
624 sc->sc_txfifosz = 16;
630 ar933x_bus_receive(struct uart_softc *sc)
632 struct uart_bas *bas = &sc->sc_bas;
635 uart_lock(sc->sc_hwmtx);
637 /* Loop over until we are full, or no data is available */
638 while (ar933x_rxready(bas)) {
639 if (uart_rx_full(sc)) {
640 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
644 /* Read the top of the RX FIFO */
645 xc = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
647 /* Remove that entry from said RX FIFO */
648 ar933x_setreg(bas, AR933X_UART_DATA_REG,
649 AR933X_UART_DATA_RX_CSR);
652 /* XXX frame, parity error */
657 * XXX TODO: Discard everything left in the Rx FIFO?
658 * XXX only if we've hit an overrun condition?
661 uart_unlock(sc->sc_hwmtx);
667 ar933x_bus_setsig(struct uart_softc *sc, int sig)
670 struct ar933x_softc *ns8250 = (struct ar933x_softc*)sc;
671 struct uart_bas *bas;
678 if (sig & SER_DDTR) {
679 SIGCHG(sig & SER_DTR, new, SER_DTR,
682 if (sig & SER_DRTS) {
683 SIGCHG(sig & SER_RTS, new, SER_RTS,
686 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
687 uart_lock(sc->sc_hwmtx);
688 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
690 ns8250->mcr |= MCR_DTR;
692 ns8250->mcr |= MCR_RTS;
693 uart_setreg(bas, REG_MCR, ns8250->mcr);
695 uart_unlock(sc->sc_hwmtx);
701 * Write the current transmit buffer to the TX FIFO.
703 * Unfortunately the FreeBSD uart device has no concept of
704 * partial UART writes - it expects that the whole buffer
705 * is written to the hardware. Thus for now, this will wait for
706 * the FIFO to finish draining before it pushes more frames into it.
708 * If non-blocking operation is truely needed here, either
709 * the FreeBSD uart device will need to handle partial writes
710 * in xxx_bus_transmit(), or we'll need to do TX FIFO buffering
714 ar933x_bus_transmit(struct uart_softc *sc)
716 struct uart_bas *bas = &sc->sc_bas;
717 struct ar933x_softc *u = (struct ar933x_softc *)sc;
720 uart_lock(sc->sc_hwmtx);
722 /* Wait for the FIFO to be clear - see above */
723 while (ar933x_getreg(bas, AR933X_UART_CS_REG) &
724 AR933X_UART_CS_TX_BUSY)
730 for (i = 0; i < sc->sc_txdatasz; i++) {
731 /* Write the TX data */
732 ar933x_setreg(bas, AR933X_UART_DATA_REG,
733 (sc->sc_txbuf[i] & 0xff) | AR933X_UART_DATA_TX_CSR);
738 * Now that we're transmitting, get interrupt notification
739 * when the FIFO is (almost) empty - see above.
741 u->u_ier |= AR933X_UART_INT_TX_EMPTY;
742 ar933x_setreg(bas, AR933X_UART_INT_EN_REG, u->u_ier);
746 * Inform the upper layer that we are presently transmitting
747 * data to the hardware; this will be cleared when the
748 * TXIDLE interrupt occurs.
751 uart_unlock(sc->sc_hwmtx);