2 * Copyright (c) 2009 Advanced Computing Technologies LLC
3 * Written by: John H. Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Support for x86 machine check architecture.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/malloc.h>
47 #include <sys/mutex.h>
49 #include <sys/sched.h>
51 #include <sys/sysctl.h>
52 #include <sys/systm.h>
53 #include <sys/taskqueue.h>
54 #include <machine/intr_machdep.h>
55 #include <machine/apicvar.h>
56 #include <machine/cputypes.h>
57 #include <machine/mca.h>
58 #include <machine/md_var.h>
59 #include <machine/specialreg.h>
61 /* Modes for mca_scan() */
70 * State maintained for each monitored MCx bank to control the
71 * corrected machine check interrupt threshold.
80 struct mca_record rec;
82 STAILQ_ENTRY(mca_internal) link;
85 static MALLOC_DEFINE(M_MCA, "MCA", "Machine Check Architecture");
87 static int mca_count; /* Number of records stored. */
89 SYSCTL_NODE(_hw, OID_AUTO, mca, CTLFLAG_RD, NULL, "Machine Check Architecture");
91 static int mca_enabled = 1;
92 TUNABLE_INT("hw.mca.enabled", &mca_enabled);
93 SYSCTL_INT(_hw_mca, OID_AUTO, enabled, CTLFLAG_RDTUN, &mca_enabled, 0,
94 "Administrative toggle for machine check support");
96 static int amd10h_L1TP = 1;
97 TUNABLE_INT("hw.mca.amd10h_L1TP", &amd10h_L1TP);
98 SYSCTL_INT(_hw_mca, OID_AUTO, amd10h_L1TP, CTLFLAG_RDTUN, &amd10h_L1TP, 0,
99 "Administrative toggle for logging of level one TLB parity (L1TP) errors");
101 int workaround_erratum383;
102 SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RD, &workaround_erratum383, 0,
103 "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?");
105 static STAILQ_HEAD(, mca_internal) mca_records;
106 static struct callout mca_timer;
107 static int mca_ticks = 3600; /* Check hourly by default. */
108 static struct task mca_task;
109 static struct mtx mca_lock;
112 static struct cmc_state **cmc_state; /* Indexed by cpuid, bank */
113 static int cmc_banks;
114 static int cmc_throttle = 60; /* Time in seconds to throttle CMCI. */
118 sysctl_positive_int(SYSCTL_HANDLER_ARGS)
122 value = *(int *)arg1;
123 error = sysctl_handle_int(oidp, &value, 0, req);
124 if (error || req->newptr == NULL)
128 *(int *)arg1 = value;
133 sysctl_mca_records(SYSCTL_HANDLER_ARGS)
135 int *name = (int *)arg1;
136 u_int namelen = arg2;
137 struct mca_record record;
138 struct mca_internal *rec;
144 if (name[0] < 0 || name[0] >= mca_count)
147 mtx_lock_spin(&mca_lock);
148 if (name[0] >= mca_count) {
149 mtx_unlock_spin(&mca_lock);
153 STAILQ_FOREACH(rec, &mca_records, link) {
160 mtx_unlock_spin(&mca_lock);
161 return (SYSCTL_OUT(req, &record, sizeof(record)));
165 mca_error_ttype(uint16_t mca_error)
168 switch ((mca_error & 0x000c) >> 2) {
180 mca_error_level(uint16_t mca_error)
183 switch (mca_error & 0x0003) {
197 mca_error_request(uint16_t mca_error)
200 switch ((mca_error & 0x00f0) >> 4) {
224 mca_error_mmtype(uint16_t mca_error)
227 switch ((mca_error & 0x70) >> 4) {
242 /* Dump details about a single machine check. */
243 static void __nonnull(1)
244 mca_log(const struct mca_record *rec)
248 printf("MCA: Bank %d, Status 0x%016llx\n", rec->mr_bank,
249 (long long)rec->mr_status);
250 printf("MCA: Global Cap 0x%016llx, Status 0x%016llx\n",
251 (long long)rec->mr_mcg_cap, (long long)rec->mr_mcg_status);
252 printf("MCA: Vendor \"%s\", ID 0x%x, APIC ID %d\n", cpu_vendor,
253 rec->mr_cpu_id, rec->mr_apic_id);
254 printf("MCA: CPU %d ", rec->mr_cpu);
255 if (rec->mr_status & MC_STATUS_UC)
259 if (rec->mr_mcg_cap & MCG_CAP_CMCI_P)
260 printf("(%lld) ", ((long long)rec->mr_status &
261 MC_STATUS_COR_COUNT) >> 38);
263 if (rec->mr_status & MC_STATUS_PCC)
265 if (rec->mr_status & MC_STATUS_OVER)
267 mca_error = rec->mr_status & MC_STATUS_MCA_ERROR;
269 /* Simple error codes. */
274 printf("unclassified error");
277 printf("ucode ROM parity error");
280 printf("external error");
286 printf("internal parity error");
289 printf("internal timer error");
292 if ((mca_error & 0xfc00) == 0x0400) {
293 printf("internal error %x", mca_error & 0x03ff);
297 /* Compound error codes. */
299 /* Memory hierarchy error. */
300 if ((mca_error & 0xeffc) == 0x000c) {
301 printf("%s memory error", mca_error_level(mca_error));
306 if ((mca_error & 0xeff0) == 0x0010) {
307 printf("%sTLB %s error", mca_error_ttype(mca_error),
308 mca_error_level(mca_error));
312 /* Memory controller error. */
313 if ((mca_error & 0xef80) == 0x0080) {
314 printf("%s channel ", mca_error_mmtype(mca_error));
315 if ((mca_error & 0x000f) != 0x000f)
316 printf("%d", mca_error & 0x000f);
319 printf(" memory error");
324 if ((mca_error & 0xef00) == 0x0100) {
325 printf("%sCACHE %s %s error",
326 mca_error_ttype(mca_error),
327 mca_error_level(mca_error),
328 mca_error_request(mca_error));
332 /* Bus and/or Interconnect error. */
333 if ((mca_error & 0xe800) == 0x0800) {
334 printf("BUS%s ", mca_error_level(mca_error));
335 switch ((mca_error & 0x0600) >> 9) {
349 printf(" %s ", mca_error_request(mca_error));
350 switch ((mca_error & 0x000c) >> 2) {
364 if (mca_error & 0x0100)
365 printf(" timed out");
369 printf("unknown error %x", mca_error);
373 if (rec->mr_status & MC_STATUS_ADDRV)
374 printf("MCA: Address 0x%llx\n", (long long)rec->mr_addr);
375 if (rec->mr_status & MC_STATUS_MISCV)
376 printf("MCA: Misc 0x%llx\n", (long long)rec->mr_misc);
379 static int __nonnull(2)
380 mca_check_status(int bank, struct mca_record *rec)
385 status = rdmsr(MSR_MC_STATUS(bank));
386 if (!(status & MC_STATUS_VAL))
389 /* Save exception information. */
390 rec->mr_status = status;
393 if (status & MC_STATUS_ADDRV)
394 rec->mr_addr = rdmsr(MSR_MC_ADDR(bank));
396 if (status & MC_STATUS_MISCV)
397 rec->mr_misc = rdmsr(MSR_MC_MISC(bank));
398 rec->mr_tsc = rdtsc();
399 rec->mr_apic_id = PCPU_GET(apic_id);
400 rec->mr_mcg_cap = rdmsr(MSR_MCG_CAP);
401 rec->mr_mcg_status = rdmsr(MSR_MCG_STATUS);
402 rec->mr_cpu_id = cpu_id;
403 rec->mr_cpu_vendor_id = cpu_vendor_id;
404 rec->mr_cpu = PCPU_GET(cpuid);
407 * Clear machine check. Don't do this for uncorrectable
408 * errors so that the BIOS can see them.
410 if (!(rec->mr_status & (MC_STATUS_PCC | MC_STATUS_UC))) {
411 wrmsr(MSR_MC_STATUS(bank), 0);
417 static void __nonnull(1)
418 mca_record_entry(const struct mca_record *record)
420 struct mca_internal *rec;
422 rec = malloc(sizeof(*rec), M_MCA, M_NOWAIT);
424 printf("MCA: Unable to allocate space for an event.\n");
431 mtx_lock_spin(&mca_lock);
432 STAILQ_INSERT_TAIL(&mca_records, rec, link);
434 mtx_unlock_spin(&mca_lock);
439 * Update the interrupt threshold for a CMCI. The strategy is to use
440 * a low trigger that interrupts as soon as the first event occurs.
441 * However, if a steady stream of events arrive, the threshold is
442 * increased until the interrupts are throttled to once every
443 * cmc_throttle seconds or the periodic scan. If a periodic scan
444 * finds that the threshold is too high, it is lowered.
447 cmci_update(enum scan_mode mode, int bank, int valid, struct mca_record *rec)
449 struct cmc_state *cc;
454 /* Fetch the current limit for this bank. */
455 cc = &cmc_state[PCPU_GET(cpuid)][bank];
456 ctl = rdmsr(MSR_MC_CTL2(bank));
457 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38;
458 delta = (u_int)(ticks - cc->last_intr);
461 * If an interrupt was received less than cmc_throttle seconds
462 * since the previous interrupt and the count from the current
463 * event is greater than or equal to the current threshold,
464 * double the threshold up to the max.
466 if (mode == CMCI && valid) {
467 limit = ctl & MC_CTL2_THRESHOLD;
468 if (delta < cmc_throttle && count >= limit &&
469 limit < cc->max_threshold) {
470 limit = min(limit << 1, cc->max_threshold);
471 ctl &= ~MC_CTL2_THRESHOLD;
473 wrmsr(MSR_MC_CTL2(bank), limit);
475 cc->last_intr = ticks;
480 * When the banks are polled, check to see if the threshold
486 /* If a CMCI occured recently, do nothing for now. */
487 if (delta < cmc_throttle)
491 * Compute a new limit based on the average rate of events per
492 * cmc_throttle seconds since the last interrupt.
495 count = (rec->mr_status & MC_STATUS_COR_COUNT) >> 38;
496 limit = count * cmc_throttle / delta;
499 else if (limit > cc->max_threshold)
500 limit = cc->max_threshold;
503 if ((ctl & MC_CTL2_THRESHOLD) != limit) {
504 ctl &= ~MC_CTL2_THRESHOLD;
506 wrmsr(MSR_MC_CTL2(bank), limit);
512 * This scans all the machine check banks of the current CPU to see if
513 * there are any machine checks. Any non-recoverable errors are
514 * reported immediately via mca_log(). The current thread must be
515 * pinned when this is called. The 'mode' parameter indicates if we
516 * are being called from the MC exception handler, the CMCI handler,
517 * or the periodic poller. In the MC exception case this function
518 * returns true if the system is restartable. Otherwise, it returns a
519 * count of the number of valid MC records found.
522 mca_scan(enum scan_mode mode)
524 struct mca_record rec;
525 uint64_t mcg_cap, ucmask;
526 int count, i, recoverable, valid;
530 ucmask = MC_STATUS_UC | MC_STATUS_PCC;
532 /* When handling a MCE#, treat the OVER flag as non-restartable. */
534 ucmask |= MC_STATUS_OVER;
535 mcg_cap = rdmsr(MSR_MCG_CAP);
536 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
539 * For a CMCI, only check banks this CPU is
542 if (mode == CMCI && !(PCPU_GET(cmci_mask) & 1 << i))
546 valid = mca_check_status(i, &rec);
549 if (rec.mr_status & ucmask) {
553 mca_record_entry(&rec);
558 * If this is a bank this CPU monitors via CMCI,
559 * update the threshold.
561 if (PCPU_GET(cmci_mask) & (1 << i))
562 cmci_update(mode, i, valid, &rec);
565 return (mode == MCE ? recoverable : count);
569 * Scan the machine check banks on all CPUs by binding to each CPU in
570 * turn. If any of the CPUs contained new machine check records, log
571 * them to the console.
574 mca_scan_cpus(void *context, int pending)
576 struct mca_internal *mca;
583 for (cpu = 0; cpu <= mp_maxid; cpu++) {
588 count += mca_scan(POLLED);
594 mtx_lock_spin(&mca_lock);
595 STAILQ_FOREACH(mca, &mca_records, link) {
598 mtx_unlock_spin(&mca_lock);
600 mtx_lock_spin(&mca_lock);
603 mtx_unlock_spin(&mca_lock);
608 mca_periodic_scan(void *arg)
611 taskqueue_enqueue(taskqueue_thread, &mca_task);
612 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan, NULL);
616 sysctl_mca_scan(SYSCTL_HANDLER_ARGS)
621 error = sysctl_handle_int(oidp, &i, 0, req);
625 taskqueue_enqueue(taskqueue_thread, &mca_task);
630 mca_startup(void *dummy)
633 if (!mca_enabled || !(cpu_feature & CPUID_MCA))
636 callout_reset(&mca_timer, mca_ticks * hz, mca_periodic_scan,
639 SYSINIT(mca_startup, SI_SUB_SMP, SI_ORDER_ANY, mca_startup, NULL);
643 cmci_setup(uint64_t mcg_cap)
647 cmc_state = malloc((mp_maxid + 1) * sizeof(struct cmc_state **),
649 cmc_banks = mcg_cap & MCG_CAP_COUNT;
650 for (i = 0; i <= mp_maxid; i++)
651 cmc_state[i] = malloc(sizeof(struct cmc_state) * cmc_banks,
652 M_MCA, M_WAITOK | M_ZERO);
653 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
654 "cmc_throttle", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE,
655 &cmc_throttle, 0, sysctl_positive_int, "I",
656 "Interval in seconds to throttle corrected MC interrupts");
661 mca_setup(uint64_t mcg_cap)
665 * On AMD Family 10h processors, unless logging of level one TLB
666 * parity (L1TP) errors is disabled, enable the recommended workaround
669 if (cpu_vendor_id == CPU_VENDOR_AMD &&
670 CPUID_TO_FAMILY(cpu_id) == 0x10 && amd10h_L1TP)
671 workaround_erratum383 = 1;
673 mtx_init(&mca_lock, "mca", NULL, MTX_SPIN);
674 STAILQ_INIT(&mca_records);
675 TASK_INIT(&mca_task, 0x8000, mca_scan_cpus, NULL);
676 callout_init(&mca_timer, CALLOUT_MPSAFE);
677 SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
678 "count", CTLFLAG_RD, &mca_count, 0, "Record count");
679 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
680 "interval", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, &mca_ticks,
681 0, sysctl_positive_int, "I",
682 "Periodic interval in seconds to scan for machine checks");
683 SYSCTL_ADD_NODE(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
684 "records", CTLFLAG_RD, sysctl_mca_records, "Machine check records");
685 SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_mca), OID_AUTO,
686 "force_scan", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0,
687 sysctl_mca_scan, "I", "Force an immediate scan for machine checks");
689 if (mcg_cap & MCG_CAP_CMCI_P)
696 * See if we should monitor CMCI for this bank. If CMCI_EN is already
697 * set in MC_CTL2, then another CPU is responsible for this bank, so
698 * ignore it. If CMCI_EN returns zero after being set, then this bank
699 * does not support CMCI_EN. If this CPU sets CMCI_EN, then it should
700 * now monitor this bank.
705 struct cmc_state *cc;
708 KASSERT(i < cmc_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
710 ctl = rdmsr(MSR_MC_CTL2(i));
711 if (ctl & MC_CTL2_CMCI_EN)
712 /* Already monitored by another CPU. */
715 /* Set the threshold to one event for now. */
716 ctl &= ~MC_CTL2_THRESHOLD;
717 ctl |= MC_CTL2_CMCI_EN | 1;
718 wrmsr(MSR_MC_CTL2(i), ctl);
719 ctl = rdmsr(MSR_MC_CTL2(i));
720 if (!(ctl & MC_CTL2_CMCI_EN))
721 /* This bank does not support CMCI. */
724 cc = &cmc_state[PCPU_GET(cpuid)][i];
726 /* Determine maximum threshold. */
727 ctl &= ~MC_CTL2_THRESHOLD;
729 wrmsr(MSR_MC_CTL2(i), ctl);
730 ctl = rdmsr(MSR_MC_CTL2(i));
731 cc->max_threshold = ctl & MC_CTL2_THRESHOLD;
733 /* Start off with a threshold of 1. */
734 ctl &= ~MC_CTL2_THRESHOLD;
736 wrmsr(MSR_MC_CTL2(i), ctl);
738 /* Mark this bank as monitored. */
739 PCPU_SET(cmci_mask, PCPU_GET(cmci_mask) | 1 << i);
743 * For resume, reset the threshold for any banks we monitor back to
744 * one and throw away the timestamp of the last interrupt.
749 struct cmc_state *cc;
752 KASSERT(i < cmc_banks, ("CPU %d has more MC banks", PCPU_GET(cpuid)));
754 /* Ignore banks not monitored by this CPU. */
755 if (!(PCPU_GET(cmci_mask) & 1 << i))
758 cc = &cmc_state[PCPU_GET(cpuid)][i];
759 cc->last_intr = -ticks;
760 ctl = rdmsr(MSR_MC_CTL2(i));
761 ctl &= ~MC_CTL2_THRESHOLD;
762 ctl |= MC_CTL2_CMCI_EN | 1;
763 wrmsr(MSR_MC_CTL2(i), ctl);
768 * Initializes per-CPU machine check registers and enables corrected
769 * machine check interrupts.
778 /* MCE is required. */
779 if (!mca_enabled || !(cpu_feature & CPUID_MCE))
782 if (cpu_feature & CPUID_MCA) {
784 PCPU_SET(cmci_mask, 0);
786 mcg_cap = rdmsr(MSR_MCG_CAP);
787 if (mcg_cap & MCG_CAP_CTL_P)
788 /* Enable MCA features. */
789 wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE);
790 if (PCPU_GET(cpuid) == 0 && boot)
794 * Disable logging of level one TLB parity (L1TP) errors by
795 * the data cache as an alternative workaround for AMD Family
796 * 10h Erratum 383. Unlike the recommended workaround, there
797 * is no performance penalty to this workaround. However,
798 * L1TP errors will go unreported.
800 if (cpu_vendor_id == CPU_VENDOR_AMD &&
801 CPUID_TO_FAMILY(cpu_id) == 0x10 && !amd10h_L1TP) {
802 mask = rdmsr(MSR_MC0_CTL_MASK);
803 if ((mask & (1UL << 5)) == 0)
804 wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5));
806 for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
807 /* By default enable logging of all errors. */
808 ctl = 0xffffffffffffffffUL;
811 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
813 * For P6 models before Nehalem MC0_CTL is
814 * always enabled and reserved.
816 if (i == 0 && CPUID_TO_FAMILY(cpu_id) == 0x6
817 && CPUID_TO_MODEL(cpu_id) < 0x1a)
819 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
820 /* BKDG for Family 10h: unset GartTblWkEn. */
821 if (i == 4 && CPUID_TO_FAMILY(cpu_id) >= 0xf)
826 wrmsr(MSR_MC_CTL(i), ctl);
829 if (mcg_cap & MCG_CAP_CMCI_P) {
837 /* Clear all errors. */
838 wrmsr(MSR_MC_STATUS(i), 0);
842 if (PCPU_GET(cmci_mask) != 0 && boot)
847 load_cr4(rcr4() | CR4_MCE);
850 /* Must be executed on each CPU during boot. */
858 /* Must be executed on each CPU during resume. */
867 * The machine check registers for the BSP cannot be initialized until
868 * the local APIC is initialized. This happens at SI_SUB_CPU,
872 mca_init_bsp(void *arg __unused)
877 SYSINIT(mca_init_bsp, SI_SUB_CPU, SI_ORDER_ANY, mca_init_bsp, NULL);
879 /* Called when a machine check exception fires. */
886 if (!(cpu_feature & CPUID_MCA)) {
888 * Just print the values of the old Pentium registers
891 printf("MC Type: 0x%jx Address: 0x%jx\n",
892 (uintmax_t)rdmsr(MSR_P5_MC_TYPE),
893 (uintmax_t)rdmsr(MSR_P5_MC_ADDR));
897 /* Scan the banks and check for any non-recoverable errors. */
898 recoverable = mca_scan(MCE);
899 mcg_status = rdmsr(MSR_MCG_STATUS);
900 if (!(mcg_status & MCG_STATUS_RIPV))
904 wrmsr(MSR_MCG_STATUS, mcg_status & ~MCG_STATUS_MCIP);
905 return (recoverable);
909 /* Called for a CMCI (correctable machine check interrupt). */
913 struct mca_internal *mca;
917 * Serialize MCA bank scanning to prevent collisions from
920 count = mca_scan(CMCI);
922 /* If we found anything, log them to the console. */
924 mtx_lock_spin(&mca_lock);
925 STAILQ_FOREACH(mca, &mca_records, link) {
928 mtx_unlock_spin(&mca_lock);
930 mtx_lock_spin(&mca_lock);
933 mtx_unlock_spin(&mca_lock);