2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
39 #include <machine/bus.h>
41 #include <arm/at91/at91_spireg.h>
42 #include <arm/at91/at91_pdcreg.h>
44 #include <dev/spibus/spi.h>
45 #include "spibus_if.h"
49 device_t dev; /* Myself */
50 void *intrhand; /* Interrupt handle */
51 struct resource *irq_res; /* IRQ resource */
52 struct resource *mem_res; /* Memory resource */
53 bus_dma_tag_t dmatag; /* bus dma tag for mbufs */
54 bus_dmamap_t map[4]; /* Maps for the transaction */
58 static inline uint32_t
59 RD4(struct at91_spi_softc *sc, bus_size_t off)
61 return bus_read_4(sc->mem_res, off);
65 WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val)
67 bus_write_4(sc->mem_res, off, val);
70 /* bus entry points */
71 static int at91_spi_probe(device_t dev);
72 static int at91_spi_attach(device_t dev);
73 static int at91_spi_detach(device_t dev);
76 static int at91_spi_activate(device_t dev);
77 static void at91_spi_deactivate(device_t dev);
78 static void at91_spi_intr(void *arg);
81 at91_spi_probe(device_t dev)
83 device_set_desc(dev, "SPI");
88 at91_spi_attach(device_t dev)
90 struct at91_spi_softc *sc = device_get_softc(dev);
94 err = at91_spi_activate(dev);
99 * Allocate DMA tags and maps
101 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
102 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2058, 1,
103 2048, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag);
106 for (i = 0; i < 4; i++) {
107 err = bus_dmamap_create(sc->dmatag, 0, &sc->map[i]);
113 WR4(sc, SPI_CR, SPI_CR_SWRST);
114 WR4(sc, SPI_IDR, 0xffffffff);
116 WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS |
119 WR4(sc, SPI_CSR0, SPI_CSR_CPOL | (4 << 16) | (2 << 8));
120 WR4(sc, SPI_CR, SPI_CR_SPIEN);
122 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS);
123 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS);
124 WR4(sc, PDC_RNPR, 0);
125 WR4(sc, PDC_RNCR, 0);
126 WR4(sc, PDC_TNPR, 0);
127 WR4(sc, PDC_TNCR, 0);
135 device_add_child(dev, "spibus", -1);
136 bus_generic_attach(dev);
139 at91_spi_deactivate(dev);
144 at91_spi_detach(device_t dev)
146 return (EBUSY); /* XXX */
150 at91_spi_activate(device_t dev)
152 struct at91_spi_softc *sc;
153 int rid, err = ENOMEM;
155 sc = device_get_softc(dev);
157 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
159 if (sc->mem_res == NULL)
162 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
164 if (sc->irq_res == NULL)
166 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
167 NULL, at91_spi_intr, sc, &sc->intrhand);
172 at91_spi_deactivate(dev);
177 at91_spi_deactivate(device_t dev)
179 struct at91_spi_softc *sc;
181 sc = device_get_softc(dev);
183 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
185 bus_generic_detach(sc->dev);
187 bus_release_resource(dev, SYS_RES_IOPORT,
188 rman_get_rid(sc->mem_res), sc->mem_res);
191 bus_release_resource(dev, SYS_RES_IRQ,
192 rman_get_rid(sc->irq_res), sc->irq_res);
198 at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
202 *(bus_addr_t *)arg = segs[0].ds_addr;
206 at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
208 struct at91_spi_softc *sc;
209 int i, j, rxdone, err, mode[4];
212 sc = device_get_softc(dev);
213 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
215 if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_cmd,
216 cmd->tx_cmd_sz, at91_getaddr, &addr, 0) != 0)
218 WR4(sc, PDC_TPR, addr);
219 WR4(sc, PDC_TCR, cmd->tx_cmd_sz);
220 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE);
221 mode[i++] = BUS_DMASYNC_POSTWRITE;
222 if (cmd->tx_data_sz > 0) {
223 if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_data,
224 cmd->tx_data_sz, at91_getaddr, &addr, 0) != 0)
226 WR4(sc, PDC_TNPR, addr);
227 WR4(sc, PDC_TNCR, cmd->tx_data_sz);
228 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE);
229 mode[i++] = BUS_DMASYNC_POSTWRITE;
231 if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_cmd,
232 cmd->tx_cmd_sz, at91_getaddr, &addr, 0) != 0)
234 WR4(sc, PDC_RPR, addr);
235 WR4(sc, PDC_RCR, cmd->tx_cmd_sz);
236 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD);
237 mode[i++] = BUS_DMASYNC_POSTREAD;
238 if (cmd->rx_data_sz > 0) {
239 if (bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_data,
240 cmd->tx_data_sz, at91_getaddr, &addr, 0) != 0)
242 WR4(sc, PDC_RNPR, addr);
243 WR4(sc, PDC_RNCR, cmd->rx_data_sz);
244 bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD);
245 mode[i++] = BUS_DMASYNC_POSTREAD;
247 WR4(sc, SPI_IER, SPI_SR_ENDRX);
248 WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN);
252 err = tsleep(&sc->rxdone, PCATCH | PZERO, "spi", hz);
253 } while (rxdone == sc->rxdone && err != EINTR);
254 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
256 for (j = 0; j < i; j++)
257 bus_dmamap_sync(sc->dmatag, sc->map[j], mode[j]);
259 for (j = 0; j < i; j++)
260 bus_dmamap_unload(sc->dmatag, sc->map[j]);
263 for (j = 0; j < i; j++)
264 bus_dmamap_unload(sc->dmatag, sc->map[j]);
269 at91_spi_intr(void *arg)
271 struct at91_spi_softc *sc = (struct at91_spi_softc*)arg;
274 sr = RD4(sc, SPI_SR) & RD4(sc, SPI_IMR);
275 if (sr & SPI_SR_ENDRX) {
277 WR4(sc, SPI_IDR, SPI_SR_ENDRX);
280 if (sr & ~SPI_SR_ENDRX) {
281 device_printf(sc->dev, "Unexpected ISR %#x\n", sr);
282 WR4(sc, SPI_IDR, sr & ~SPI_SR_ENDRX);
286 static devclass_t at91_spi_devclass;
288 static device_method_t at91_spi_methods[] = {
289 /* Device interface */
290 DEVMETHOD(device_probe, at91_spi_probe),
291 DEVMETHOD(device_attach, at91_spi_attach),
292 DEVMETHOD(device_detach, at91_spi_detach),
294 /* spibus interface */
295 DEVMETHOD(spibus_transfer, at91_spi_transfer),
299 static driver_t at91_spi_driver = {
302 sizeof(struct at91_spi_softc),
305 DRIVER_MODULE(at91_spi, atmelarm, at91_spi_driver, at91_spi_devclass, 0, 0);