1 /***********************license start***************
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37 ***********************license end**************************************/
47 * General Purpose IO interface.
49 * <hr>$Revision: 41586 $<hr>
52 #ifndef __CVMX_GPIO_H__
53 #define __CVMX_GPIO_H__
59 /* CSR typedefs have been moved to cvmx-csr-*.h */
62 * Clear the interrupt rising edge detector for the supplied
63 * pins in the mask. Chips which have more than 16 GPIO pins
64 * can't use them for interrupts.
66 * @param clear_mask Mask of pins to clear
68 static inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask)
70 cvmx_gpio_int_clr_t gpio_int_clr;
72 gpio_int_clr.s.type = clear_mask;
73 cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64);
80 * @return Status of the GPIO pins
82 static inline uint32_t cvmx_gpio_read(void)
84 cvmx_gpio_rx_dat_t gpio_rx_dat;
85 gpio_rx_dat.u64 = cvmx_read_csr(CVMX_GPIO_RX_DAT);
86 return gpio_rx_dat.s.dat;
93 * @param clear_mask Bit mask to indicate which bits to drive to '0'.
95 static inline void cvmx_gpio_clear(uint32_t clear_mask)
97 cvmx_gpio_tx_clr_t gpio_tx_clr;
99 gpio_tx_clr.s.clr = clear_mask;
100 cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64);
107 * @param set_mask Bit mask to indicate which bits to drive to '1'.
109 static inline void cvmx_gpio_set(uint32_t set_mask)
111 cvmx_gpio_tx_set_t gpio_tx_set;
113 gpio_tx_set.s.set = set_mask;
114 cvmx_write_csr(CVMX_GPIO_TX_SET, gpio_tx_set.u64);