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37 ***********************license end**************************************/
47 * Small helper utilities.
49 * <hr>$Revision: 42493 $<hr>
52 #include "cvmx-bootmem.h"
60 #include "cvmx-sysinfo.h"
61 #include "cvmx-helper.h"
62 #include "cvmx-helper-util.h"
63 #include "cvmx-version.h"
65 #ifdef CVMX_ENABLE_HELPER_FUNCTIONS
68 * Get the version of the CVMX libraries.
70 * @return Version string. Note this buffer is allocated statically
71 * and will be shared by all callers.
73 const char *cvmx_helper_get_version(void)
75 return OCTEON_SDK_VERSION_STRING;
80 * Convert a interface mode into a human readable string
82 * @param mode Mode to convert
86 const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode)
90 case CVMX_HELPER_INTERFACE_MODE_DISABLED: return "DISABLED";
91 case CVMX_HELPER_INTERFACE_MODE_RGMII: return "RGMII";
92 case CVMX_HELPER_INTERFACE_MODE_GMII: return "GMII";
93 case CVMX_HELPER_INTERFACE_MODE_SPI: return "SPI";
94 case CVMX_HELPER_INTERFACE_MODE_PCIE: return "PCIE";
95 case CVMX_HELPER_INTERFACE_MODE_XAUI: return "XAUI";
96 case CVMX_HELPER_INTERFACE_MODE_SGMII: return "SGMII";
97 case CVMX_HELPER_INTERFACE_MODE_PICMG: return "PICMG";
98 case CVMX_HELPER_INTERFACE_MODE_NPI: return "NPI";
99 case CVMX_HELPER_INTERFACE_MODE_LOOP: return "LOOP";
106 * Debug routine to dump the packet structure to the console
108 * @param work Work queue entry containing the packet to dump
111 int cvmx_helper_dump_packet(cvmx_wqe_t *work)
114 uint64_t remaining_bytes;
115 cvmx_buf_ptr_t buffer_ptr;
116 uint64_t start_of_buffer;
117 uint8_t * data_address;
118 uint8_t * end_of_data;
120 cvmx_dprintf("Packet Length: %u\n", work->len);
121 cvmx_dprintf(" Input Port: %u\n", work->ipprt);
122 cvmx_dprintf(" QoS: %u\n", work->qos);
123 cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs);
125 if (work->word2.s.bufs == 0)
127 cvmx_ipd_wqe_fpa_queue_t wqe_pool;
128 wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE);
130 buffer_ptr.s.pool = wqe_pool.s.wqe_pool;
131 buffer_ptr.s.size = 128;
132 buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data);
133 if (cvmx_likely(!work->word2.s.not_IP))
135 cvmx_pip_ip_offset_t pip_ip_offset;
136 pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET);
137 buffer_ptr.s.addr += (pip_ip_offset.s.offset<<3) - work->word2.s.ip_offset;
138 buffer_ptr.s.addr += (work->word2.s.is_v6^1)<<2;
142 /* WARNING: This code assume that the packet is not RAW. If it was,
143 we would use PIP_GBL_CFG[RAW_SHF] instead of
144 PIP_GBL_CFG[NIP_SHF] */
145 cvmx_pip_gbl_cfg_t pip_gbl_cfg;
146 pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG);
147 buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf;
151 buffer_ptr = work->packet_ptr;
152 remaining_bytes = work->len;
154 while (remaining_bytes)
156 start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
157 cvmx_dprintf(" Buffer Start:%llx\n", (unsigned long long)start_of_buffer);
158 cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i);
159 cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back);
160 cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool);
161 cvmx_dprintf(" Buffer Data: %llx\n", (unsigned long long)buffer_ptr.s.addr);
162 cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size);
164 cvmx_dprintf("\t\t");
165 data_address = (uint8_t *)cvmx_phys_to_ptr(buffer_ptr.s.addr);
166 end_of_data = data_address + buffer_ptr.s.size;
168 while (data_address < end_of_data)
170 if (remaining_bytes == 0)
174 cvmx_dprintf("%02x", (unsigned int)*data_address);
176 if (remaining_bytes && (count == 7))
178 cvmx_dprintf("\n\t\t");
187 buffer_ptr = *(cvmx_buf_ptr_t*)cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
194 * Setup Random Early Drop on a specific input queue
196 * @param queue Input queue to setup RED on (0-7)
198 * Packets will begin slowly dropping when there are less than
199 * this many packet buffers free in FPA 0.
201 * All incomming packets will be dropped when there are less
202 * than this many free packet buffers in FPA 0.
203 * @return Zero on success. Negative on failure
205 int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
207 cvmx_ipd_qos_red_marks_t red_marks;
208 cvmx_ipd_red_quex_param_t red_param;
210 /* Set RED to begin dropping packets when there are pass_thresh buffers
211 left. It will linearly drop more packets until reaching drop_thresh
214 red_marks.s.drop = drop_thresh;
215 red_marks.s.pass = pass_thresh;
216 cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64);
218 /* Use the actual queue 0 counter, not the average */
220 red_param.s.prb_con = (255ul<<24) / (red_marks.s.pass - red_marks.s.drop);
221 red_param.s.avg_con = 1;
222 red_param.s.new_con = 255;
223 red_param.s.use_pcnt = 1;
224 cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64);
230 * Setup Random Early Drop to automatically begin dropping packets.
233 * Packets will begin slowly dropping when there are less than
234 * this many packet buffers free in FPA 0.
236 * All incomming packets will be dropped when there are less
237 * than this many free packet buffers in FPA 0.
238 * @return Zero on success. Negative on failure
240 int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
242 cvmx_ipd_portx_bp_page_cnt_t page_cnt;
243 cvmx_ipd_bp_prt_red_end_t ipd_bp_prt_red_end;
244 cvmx_ipd_red_port_enable_t red_port_enable;
249 /* Disable backpressure based on queued buffers. It needs SW support */
251 page_cnt.s.bp_enb = 0;
252 page_cnt.s.page_cnt = 100;
253 for (interface=0; interface<2; interface++)
255 for (port=cvmx_helper_get_first_ipd_port(interface); port<cvmx_helper_get_last_ipd_port(interface); port++)
256 cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), page_cnt.u64);
259 for (queue=0; queue<8; queue++)
260 cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
262 /* Shutoff the dropping based on the per port page count. SW isn't
263 decrementing it right now */
264 ipd_bp_prt_red_end.u64 = 0;
265 ipd_bp_prt_red_end.s.prt_enb = 0;
266 cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);
268 red_port_enable.u64 = 0;
269 red_port_enable.s.prt_enb = 0xfffffffffull;
270 red_port_enable.s.avg_dly = 10000;
271 red_port_enable.s.prb_dly = 10000;
272 cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
280 * Setup the common GMX settings that determine the number of
281 * ports. These setting apply to almost all configurations of all
284 * @param interface Interface to configure
285 * @param num_ports Number of ports on the interface
287 * @return Zero on success, negative on failure
289 int __cvmx_helper_setup_gmx(int interface, int num_ports)
291 cvmx_gmxx_tx_prts_t gmx_tx_prts;
292 cvmx_gmxx_rx_prts_t gmx_rx_prts;
293 cvmx_pko_reg_gmx_port_mode_t pko_mode;
294 cvmx_gmxx_txx_thresh_t gmx_tx_thresh;
297 /* Tell GMX the number of TX ports on this interface */
298 gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));
299 gmx_tx_prts.s.prts = num_ports;
300 cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);
302 /* Tell GMX the number of RX ports on this interface. This only
303 ** applies to *GMII and XAUI ports */
304 if (cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_RGMII
305 || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_SGMII
306 || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_GMII
307 || cvmx_helper_interface_get_mode(interface) == CVMX_HELPER_INTERFACE_MODE_XAUI)
311 cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal num_ports\n");
315 gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface));
316 gmx_rx_prts.s.prts = num_ports;
317 cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);
320 /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */
321 if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) && !OCTEON_IS_MODEL(OCTEON_CN50XX))
323 /* Tell PKO the number of ports on this interface */
324 pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);
328 pko_mode.s.mode0 = 4;
329 else if (num_ports == 2)
330 pko_mode.s.mode0 = 3;
331 else if (num_ports <= 4)
332 pko_mode.s.mode0 = 2;
333 else if (num_ports <= 8)
334 pko_mode.s.mode0 = 1;
336 pko_mode.s.mode0 = 0;
341 pko_mode.s.mode1 = 4;
342 else if (num_ports == 2)
343 pko_mode.s.mode1 = 3;
344 else if (num_ports <= 4)
345 pko_mode.s.mode1 = 2;
346 else if (num_ports <= 8)
347 pko_mode.s.mode1 = 1;
349 pko_mode.s.mode1 = 0;
351 cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);
354 /* Set GMX to buffer as much data as possible before starting transmit.
355 This reduces the chances that we have a TX under run due to memory
356 contention. Any packet that fits entirely in the GMX FIFO can never
357 have an under run regardless of memory load */
358 gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface));
359 if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
361 /* These chips have a fixed max threshold of 0x40 */
362 gmx_tx_thresh.s.cnt = 0x40;
366 /* Choose the max value for the number of ports */
368 gmx_tx_thresh.s.cnt = 0x100 / 1;
369 else if (num_ports == 2)
370 gmx_tx_thresh.s.cnt = 0x100 / 2;
372 gmx_tx_thresh.s.cnt = 0x100 / 4;
374 /* SPI and XAUI can have lots of ports but the GMX hardware only ever has
378 for (index=0; index<num_ports; index++)
379 cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), gmx_tx_thresh.u64);
386 * Returns the IPD/PKO port number for a port on teh given
389 * @param interface Interface to use
390 * @param port Port on the interface
392 * @return IPD/PKO port number
394 int cvmx_helper_get_ipd_port(int interface, int port)
399 case 1: return port + 16;
400 case 2: return port + 32;
401 case 3: return port + 36;
406 #endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
410 * Returns the interface number for an IPD/PKO port number.
412 * @param ipd_port IPD/PKO port number
414 * @return Interface number
416 int cvmx_helper_get_interface_num(int ipd_port)
420 else if (ipd_port < 32)
422 else if (ipd_port < 36)
424 else if (ipd_port < 40)
427 cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD port number\n");
434 * Returns the interface index number for an IPD/PKO port
437 * @param ipd_port IPD/PKO port number
439 * @return Interface index number
441 int cvmx_helper_get_interface_index_num(int ipd_port)
444 return ipd_port & 15;
445 else if (ipd_port < 36)
447 else if (ipd_port < 40)
450 cvmx_dprintf("cvmx_helper_get_interface_index_num: Illegal IPD port number\n");
456 * Initialize the internal QLM JTAG logic to allow programming
457 * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
458 * These functions should only be used at the direction of Cavium
459 * Networks. Programming incorrect values into the JTAG chain
460 * can cause chip damage.
462 void cvmx_helper_qlm_jtag_init(void)
464 cvmx_ciu_qlm_jtgc_t jtgc;
466 int divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
467 divisor = (divisor-1)>>2;
468 /* Convert the divisor into a power of 2 shift */
469 CVMX_CLZ(clock_div, divisor);
470 clock_div = 32 - clock_div;
472 /* Clock divider for QLM JTAG operations. eclk is divided by 2^(CLK_DIV + 2) */
474 jtgc.s.clk_div = clock_div;
476 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
480 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
481 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
486 * Write up to 32bits into the QLM jtag chain. Bits are shifted
487 * into the MSB and out the LSB, so you should shift in the low
488 * order bits followed by the high order bits. The JTAG chain is
489 * 4 * 268 bits long, or 1072.
491 * @param qlm QLM to shift value into
492 * @param bits Number of bits to shift in (1-32).
493 * @param data Data to shift in. Bit 0 enters the chain first, followed by
496 * @return The low order bits of the JTAG chain that shifted out of the
499 uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
501 cvmx_ciu_qlm_jtgd_t jtgd;
504 jtgd.s.shft_cnt = bits-1;
505 jtgd.s.shft_reg = data;
506 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
507 jtgd.s.select = 1 << qlm;
508 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
511 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
512 } while (jtgd.s.shift);
513 return jtgd.s.shft_reg >> (32-bits);
518 * Shift long sequences of zeros into the QLM JTAG chain. It is
519 * common to need to shift more than 32 bits of zeros into the
520 * chain. This function is a convience wrapper around
521 * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
524 * @param qlm QLM to shift zeros into
527 void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
534 cvmx_helper_qlm_jtag_shift(qlm, n, 0);
541 * Program the QLM JTAG chain into all lanes of the QLM. You must
542 * have already shifted in 268*4, or 1072 bits into the JTAG
543 * chain. Updating invalid values can possibly cause chip damage.
545 * @param qlm QLM to program
547 void cvmx_helper_qlm_jtag_update(int qlm)
549 cvmx_ciu_qlm_jtgd_t jtgd;
551 /* Update the new data */
554 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
555 jtgd.s.select = 1 << qlm;
556 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
559 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
560 } while (jtgd.s.update);