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47 * Interface to the Mips interrupts.
49 * <hr>$Revision: 42203 $<hr>
51 #ifndef __CVMX_INTERRUPT_H__
52 #define __CVMX_INTERRUPT_H__
59 * Enumeration of Interrupt numbers
63 /* 0 - 7 represent the 8 MIPS standard interrupt sources */
73 /* 8 - 71 represent the sources in CIU_INTX_EN0 */
84 CVMX_IRQ_WORKQ10 = 18,
85 CVMX_IRQ_WORKQ11 = 19,
86 CVMX_IRQ_WORKQ12 = 20,
87 CVMX_IRQ_WORKQ13 = 21,
88 CVMX_IRQ_WORKQ14 = 22,
89 CVMX_IRQ_WORKQ15 = 23,
100 CVMX_IRQ_GPIO10 = 34,
101 CVMX_IRQ_GPIO11 = 35,
102 CVMX_IRQ_GPIO12 = 36,
103 CVMX_IRQ_GPIO13 = 37,
104 CVMX_IRQ_GPIO14 = 38,
105 CVMX_IRQ_GPIO15 = 39,
110 CVMX_IRQ_PCI_INT0 = 44,
111 CVMX_IRQ_PCI_INT1 = 45,
112 CVMX_IRQ_PCI_INT2 = 46,
113 CVMX_IRQ_PCI_INT3 = 47,
114 CVMX_IRQ_PCI_MSI0 = 48,
115 CVMX_IRQ_PCI_MSI1 = 49,
116 CVMX_IRQ_PCI_MSI2 = 50,
117 CVMX_IRQ_PCI_MSI3 = 51,
118 CVMX_IRQ_RESERVED44 = 52,
122 CVMX_IRQ_GMX_DRP0 = 56,
123 CVMX_IRQ_GMX_DRP1 = 57,
124 CVMX_IRQ_IPD_DRP = 58,
125 CVMX_IRQ_KEY_ZERO = 59,
126 CVMX_IRQ_TIMER0 = 60,
127 CVMX_IRQ_TIMER1 = 61,
128 CVMX_IRQ_TIMER2 = 62,
129 CVMX_IRQ_TIMER3 = 63,
130 CVMX_IRQ_USB = 64, /* Doesn't apply on CN38XX or CN58XX */
133 CVMX_IRQ_TWSI2 = 67, /* Added in CN56XX */
134 CVMX_IRQ_POWIQ = 68, /* Added in CN56XX */
135 CVMX_IRQ_IPDPPTHR = 69, /* Added in CN56XX */
136 CVMX_IRQ_MII = 70, /* Added in CN56XX */
137 CVMX_IRQ_BOOTDMA = 71, /* Added in CN56XX */
139 /* 72 - 135 represent the sources in CIU_INTX_EN1 */
156 /* numbers 88 - 135 are reserved */
160 * Function prototype for the exception handler
162 typedef void (*cvmx_interrupt_exception_t)(uint64_t registers[32]);
165 * Function prototype for interrupt handlers
167 typedef void (*cvmx_interrupt_func_t)(int irq_number, uint64_t registers[32], void *user_arg);
170 * Register an interrupt handler for the specified interrupt number.
172 * @param irq_number Interrupt number to register for (0-135)
173 * @param func Function to call on interrupt.
174 * @param user_arg User data to pass to the interrupt handler
176 void cvmx_interrupt_register(cvmx_irq_t irq_number, cvmx_interrupt_func_t func, void *user_arg);
179 * Set the exception handler for all non interrupt sources.
181 * @param handler New exception handler
182 * @return Old exception handler
184 cvmx_interrupt_exception_t cvmx_interrupt_set_exception(cvmx_interrupt_exception_t handler);
187 * Masks a given interrupt number.
188 * EN0 sources are masked on IP2
189 * EN1 sources are masked on IP3
191 * @param irq_number interrupt number to mask (0-135)
193 static inline void cvmx_interrupt_mask_irq(int irq_number)
198 asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
199 mask &= ~(1<< (8 + irq_number));
200 asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
202 else if (irq_number < 8 + 64)
204 int ciu_bit = (irq_number - 8) & 63;
205 int ciu_offset = cvmx_get_core_num() * 2;
206 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
207 mask &= ~(1ull << ciu_bit);
208 cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
212 int ciu_bit = (irq_number - 8) & 63;
213 int ciu_offset = cvmx_get_core_num() * 2 + 1;
214 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
215 mask &= ~(1ull << ciu_bit);
216 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
222 * Unmasks a given interrupt number
223 * EN0 sources are unmasked on IP2
224 * EN1 sources are unmasked on IP3
226 * @param irq_number interrupt number to unmask (0-135)
228 static inline void cvmx_interrupt_unmask_irq(int irq_number)
233 asm volatile ("mfc0 %0,$12,0" : "=r" (mask));
234 mask |= (1<< (8 + irq_number));
235 asm volatile ("mtc0 %0,$12,0" : : "r" (mask));
237 else if (irq_number < 8 + 64)
239 int ciu_bit = (irq_number - 8) & 63;
240 int ciu_offset = cvmx_get_core_num() * 2;
241 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
242 mask |= (1ull << ciu_bit);
243 cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
247 int ciu_bit = (irq_number - 8) & 63;
248 int ciu_offset = cvmx_get_core_num() * 2 + 1;
249 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
250 mask |= (1ull << ciu_bit);
251 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
256 /* Disable interrupts by clearing bit 0 of the COP0 status register,
257 ** and return the previous contents of the status register.
258 ** Note: this is only used to track interrupt status. */
259 static inline uint32_t cvmx_interrupt_disable_save(void)
264 : [flags]"=r" (flags));
268 /* Restore the contents of the cop0 status register. Used with
269 ** cvmx_interrupt_disable_save to allow recursive interrupt disabling */
270 static inline void cvmx_interrupt_restore(uint32_t flags)
272 /* If flags value indicates interrupts should be enabled, then enable them */
282 * Utility function to decode Octeon's RSL_INT_BLOCKS interrupts
283 * into error messages.
285 extern void cvmx_interrupt_rsl_decode(void);
288 * Utility function to enable all RSL error interupts
290 extern void cvmx_interrupt_rsl_enable(void);
293 * Utility function to do interrupt safe printf
295 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
296 #define cvmx_safe_printf printk
297 #elif defined(CVMX_BUILD_FOR_LINUX_USER)
298 #define cvmx_safe_printf printf
300 extern void cvmx_safe_printf(const char* format, ... ) __attribute__ ((format(printf, 1, 2)));