sys/contrib/octeon-sdk/cvmx-ipd.h

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  43
  44 /**
  45  * @file
  46  *
  47  * Interface to the hardware Input Packet Data unit.
  48  *
  49  * <hr>$Revision: 41586 $<hr>
  50  */
  51
  52
  53 #ifndef __CVMX_IPD_H__
  54 #define __CVMX_IPD_H__
  55
  56 #ifndef CVMX_DONT_INCLUDE_CONFIG
  57 #include "executive-config.h"
  58 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
  59 #include "cvmx-config.h"
  60 #endif
  61 #endif
  62
  63 #ifdef  __cplusplus
  64 extern "C" {
  65 #endif
  66
  67 #ifndef CVMX_ENABLE_LEN_M8_FIX
  68 #define CVMX_ENABLE_LEN_M8_FIX 0
  69 #endif
  70
  71 /* CSR typedefs have been moved to cvmx-csr-*.h */
  72
  73 typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
  74 typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
  75
  76
  77 /**
  78  * Configure IPD
  79  *
  80  * @param mbuff_size Packets buffer size in 8 byte words
  81  * @param first_mbuff_skip
  82  *                   Number of 8 byte words to skip in the first buffer
  83  * @param not_first_mbuff_skip
  84  *                   Number of 8 byte words to skip in each following buffer
  85  * @param first_back Must be same as first_mbuff_skip / 128
  86  * @param second_back
  87  *                   Must be same as not_first_mbuff_skip / 128
  88  * @param wqe_fpa_pool
  89  *                   FPA pool to get work entries from
  90  * @param cache_mode
  91  * @param back_pres_enable_flag
  92  *                   Enable or disable port back pressure
  93  */
  94 static inline void cvmx_ipd_config(uint64_t mbuff_size,
  95                                    uint64_t first_mbuff_skip,
  96                                    uint64_t not_first_mbuff_skip,
  97                                    uint64_t first_back,
  98                                    uint64_t second_back,
  99                                    uint64_t wqe_fpa_pool,
 100                                    cvmx_ipd_mode_t cache_mode,
 101                                    uint64_t back_pres_enable_flag
 102                                   )
 103 {
 104     cvmx_ipd_mbuff_first_skip_t first_skip;
 105     cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
 106     cvmx_ipd_mbuff_size_t size;
 107     cvmx_ipd_first_next_ptr_back_t first_back_struct;
 108     cvmx_ipd_second_next_ptr_back_t second_back_struct;
 109     cvmx_ipd_wqe_fpa_pool_t wqe_pool;
 110     cvmx_ipd_ctl_status_t ipd_ctl_reg;
 111
 112     first_skip.u64 = 0;
 113     first_skip.s.skip_sz = first_mbuff_skip;
 114     cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
 115
 116     not_first_skip.u64 = 0;
 117     not_first_skip.s.skip_sz = not_first_mbuff_skip;
 118     cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
 119
 120     size.u64 = 0;
 121     size.s.mb_size = mbuff_size;
 122     cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
 123
 124     first_back_struct.u64 = 0;
 125     first_back_struct.s.back = first_back;
 126     cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
 127
 128     second_back_struct.u64 = 0;
 129     second_back_struct.s.back = second_back;
 130     cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK,second_back_struct.u64);
 131
 132     wqe_pool.u64 = 0;
 133     wqe_pool.s.wqe_pool = wqe_fpa_pool;
 134     cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
 135
 136     ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
 137     ipd_ctl_reg.s.opc_mode = cache_mode;
 138     ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
 139     cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
 140
 141     /* Note: the example RED code that used to be here has been moved to
 142         cvmx_helper_setup_red */
 143 }
 144
 145
 146 /**
 147  * Enable IPD
 148  */
 149 static inline void cvmx_ipd_enable(void)
 150 {
 151     cvmx_ipd_ctl_status_t ipd_reg;
 152     ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
 153     if (ipd_reg.s.ipd_en)
 154     {
 155         cvmx_dprintf("Warning: Enabling IPD when IPD already enabled.\n");
 156     }
 157     ipd_reg.s.ipd_en = TRUE;
 158     #if  CVMX_ENABLE_LEN_M8_FIX
 159     if(!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
 160         ipd_reg.s.len_m8 = TRUE;
 161     }
 162     #endif
 163     cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
 164 }
 165
 166
 167 /**
 168  * Disable IPD
 169  */
 170 static inline void cvmx_ipd_disable(void)
 171 {
 172     cvmx_ipd_ctl_status_t ipd_reg;
 173     ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
 174     ipd_reg.s.ipd_en = FALSE;
 175     cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
 176 }
 177
 178 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
 179 /**
 180  * Supportive function for cvmx_fpa_shutdown_pool.
 181  */
 182 static inline void cvmx_ipd_free_ptr(void)
 183 {
 184     /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
 185     if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1) && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
 186         int no_wptr = 0;
 187         cvmx_ipd_ptr_count_t ipd_ptr_count;
 188         ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
 189
 190         /* Handle Work Queue Entry in cn56xx and cn52xx */
 191         if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
 192             cvmx_ipd_ctl_status_t ipd_ctl_status;
 193             ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
 194             if (ipd_ctl_status.s.no_wptr)
 195                 no_wptr = 1;
 196         }
 197
 198         /* Free the prefetched WQE */
 199         if (ipd_ptr_count.s.wqev_cnt) {
 200             cvmx_ipd_wqe_ptr_valid_t ipd_wqe_ptr_valid;
 201             ipd_wqe_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
 202             if (no_wptr)
 203                 cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
 204             else
 205                 cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_wqe_ptr_valid.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
 206         }
 207
 208         /* Free all WQE in the fifo */
 209         if (ipd_ptr_count.s.wqe_pcnt) {
 210             int i;
 211             cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
 212             ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
 213             for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
 214                 ipd_pwp_ptr_fifo_ctl.s.cena = 0;
 215                 ipd_pwp_ptr_fifo_ctl.s.raddr = ipd_pwp_ptr_fifo_ctl.s.max_cnts + (ipd_pwp_ptr_fifo_ctl.s.wraddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
 216                 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
 217                 ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
 218                 if (no_wptr)
 219                     cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
 220                 else
 221                     cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_WQE_POOL, 0);
 222             }
 223             ipd_pwp_ptr_fifo_ctl.s.cena = 1;
 224             cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
 225         }
 226
 227         /* Free the prefetched packet */
 228         if (ipd_ptr_count.s.pktv_cnt) {
 229             cvmx_ipd_pkt_ptr_valid_t ipd_pkt_ptr_valid;
 230             ipd_pkt_ptr_valid.u64 = cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
 231             cvmx_fpa_free(cvmx_phys_to_ptr(ipd_pkt_ptr_valid.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
 232         }
 233
 234         /* Free the per port prefetched packets */
 235         if (1) {
 236             int i;
 237             cvmx_ipd_prc_port_ptr_fifo_ctl_t ipd_prc_port_ptr_fifo_ctl;
 238             ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
 239
 240             for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; i++) {
 241                 ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
 242                 ipd_prc_port_ptr_fifo_ctl.s.raddr = i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
 243                 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
 244                 ipd_prc_port_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
 245                 cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_port_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
 246             }
 247             ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
 248             cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64);
 249         }
 250
 251         /* Free all packets in the holding fifo */
 252         if (ipd_ptr_count.s.pfif_cnt) {
 253             int i;
 254             cvmx_ipd_prc_hold_ptr_fifo_ctl_t ipd_prc_hold_ptr_fifo_ctl;
 255
 256             ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
 257
 258             for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
 259                 ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
 260                 ipd_prc_hold_ptr_fifo_ctl.s.raddr = (ipd_prc_hold_ptr_fifo_ctl.s.praddr + i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
 261                 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
 262                 ipd_prc_hold_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
 263                 cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_prc_hold_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
 264             }
 265             ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
 266             cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64);
 267         }
 268
 269         /* Free all packets in the fifo */
 270         if (ipd_ptr_count.s.pkt_pcnt) {
 271             int i;
 272             cvmx_ipd_pwp_ptr_fifo_ctl_t ipd_pwp_ptr_fifo_ctl;
 273             ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
 274
 275             for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
 276                 ipd_pwp_ptr_fifo_ctl.s.cena = 0;
 277                 ipd_pwp_ptr_fifo_ctl.s.raddr = (ipd_pwp_ptr_fifo_ctl.s.praddr+i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
 278                 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
 279                 ipd_pwp_ptr_fifo_ctl.u64 = cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
 280                 cvmx_fpa_free(cvmx_phys_to_ptr((uint64_t)ipd_pwp_ptr_fifo_ctl.s.ptr<<7), CVMX_FPA_PACKET_POOL, 0);
 281             }
 282             ipd_pwp_ptr_fifo_ctl.s.cena = 1;
 283             cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64);
 284         }
 285
 286         /* Reset the IPD to get all buffers out of it */
 287         {
 288             cvmx_ipd_ctl_status_t ipd_ctl_status;
 289             ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
 290             ipd_ctl_status.s.reset = 1;
 291             cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
 292         }
 293
 294         /* Reset the PIP */
 295         {
 296             cvmx_pip_sft_rst_t pip_sft_rst;
 297             pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
 298             pip_sft_rst.s.rst = 1;
 299             cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
 300         }
 301     }
 302 }
 303 #endif
 304
 305 #ifdef  __cplusplus
 306 }
 307 #endif
 308
 309 #endif  /*  __CVMX_IPD_H__ */