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47 * Interface to PCIe as a host(RC) or target(EP)
49 * <hr>$Revision: 41586 $<hr>
52 #ifndef __CVMX_PCIE_H__
53 #define __CVMX_PCIE_H__
64 uint64_t upper : 2; /* Normally 2 for XKPHYS */
65 uint64_t reserved_49_61 : 13; /* Must be zero */
66 uint64_t io : 1; /* 1 for IO space access */
67 uint64_t did : 5; /* PCIe DID = 3 */
68 uint64_t subdid : 3; /* PCIe SubDID = 1 */
69 uint64_t reserved_36_39 : 4; /* Must be zero */
70 uint64_t es : 2; /* Endian swap = 1 */
71 uint64_t port : 2; /* PCIe port 0,1 */
72 uint64_t reserved_29_31 : 3; /* Must be zero */
73 uint64_t ty : 1; /* Selects the type of the configuration request (0 = type 0, 1 = type 1). */
74 uint64_t bus : 8; /* Target bus number sent in the ID in the request. */
75 uint64_t dev : 5; /* Target device number sent in the ID in the request. Note that Dev must be
76 zero for type 0 configuration requests. */
77 uint64_t func : 3; /* Target function number sent in the ID in the request. */
78 uint64_t reg : 12; /* Selects a register in the configuration space of the target. */
82 uint64_t upper : 2; /* Normally 2 for XKPHYS */
83 uint64_t reserved_49_61 : 13; /* Must be zero */
84 uint64_t io : 1; /* 1 for IO space access */
85 uint64_t did : 5; /* PCIe DID = 3 */
86 uint64_t subdid : 3; /* PCIe SubDID = 2 */
87 uint64_t reserved_36_39 : 4; /* Must be zero */
88 uint64_t es : 2; /* Endian swap = 1 */
89 uint64_t port : 2; /* PCIe port 0,1 */
90 uint64_t address : 32; /* PCIe IO address */
94 uint64_t upper : 2; /* Normally 2 for XKPHYS */
95 uint64_t reserved_49_61 : 13; /* Must be zero */
96 uint64_t io : 1; /* 1 for IO space access */
97 uint64_t did : 5; /* PCIe DID = 3 */
98 uint64_t subdid : 3; /* PCIe SubDID = 3-6 */
99 uint64_t reserved_36_39 : 4; /* Must be zero */
100 uint64_t address : 36; /* PCIe Mem address */
102 } cvmx_pcie_address_t;
106 * Return the Core virtual base address for PCIe IO access. IOs are
107 * read/written as an offset from this address.
109 * @param pcie_port PCIe port the IO is for
111 * @return 64bit Octeon IO base address for read/write
113 uint64_t cvmx_pcie_get_io_base_address(int pcie_port);
116 * Size of the IO address region returned at address
117 * cvmx_pcie_get_io_base_address()
119 * @param pcie_port PCIe port the IO is for
121 * @return Size of the IO window
123 uint64_t cvmx_pcie_get_io_size(int pcie_port);
126 * Return the Core virtual base address for PCIe MEM access. Memory is
127 * read/written as an offset from this address.
129 * @param pcie_port PCIe port the IO is for
131 * @return 64bit Octeon IO base address for read/write
133 uint64_t cvmx_pcie_get_mem_base_address(int pcie_port);
136 * Size of the Mem address region returned at address
137 * cvmx_pcie_get_mem_base_address()
139 * @param pcie_port PCIe port the IO is for
141 * @return Size of the Mem window
143 uint64_t cvmx_pcie_get_mem_size(int pcie_port);
146 * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
148 * @param pcie_port PCIe port to initialize
150 * @return Zero on success
152 int cvmx_pcie_rc_initialize(int pcie_port);
155 * Shutdown a PCIe port and put it in reset
157 * @param pcie_port PCIe port to shutdown
159 * @return Zero on success
161 int cvmx_pcie_rc_shutdown(int pcie_port);
164 * Read 8bits from a Device's config space
166 * @param pcie_port PCIe port the device is on
168 * @param dev Device ID
169 * @param fn Device sub function
170 * @param reg Register to access
172 * @return Result of the read
174 uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg);
177 * Read 16bits from a Device's config space
179 * @param pcie_port PCIe port the device is on
181 * @param dev Device ID
182 * @param fn Device sub function
183 * @param reg Register to access
185 * @return Result of the read
187 uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg);
190 * Read 32bits from a Device's config space
192 * @param pcie_port PCIe port the device is on
194 * @param dev Device ID
195 * @param fn Device sub function
196 * @param reg Register to access
198 * @return Result of the read
200 uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg);
203 * Write 8bits to a Device's config space
205 * @param pcie_port PCIe port the device is on
207 * @param dev Device ID
208 * @param fn Device sub function
209 * @param reg Register to access
210 * @param val Value to write
212 void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, uint8_t val);
215 * Write 16bits to a Device's config space
217 * @param pcie_port PCIe port the device is on
219 * @param dev Device ID
220 * @param fn Device sub function
221 * @param reg Register to access
222 * @param val Value to write
224 void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, uint16_t val);
227 * Write 32bits to a Device's config space
229 * @param pcie_port PCIe port the device is on
231 * @param dev Device ID
232 * @param fn Device sub function
233 * @param reg Register to access
234 * @param val Value to write
236 void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, uint32_t val);
239 * Read a PCIe config space register indirectly. This is used for
240 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
242 * @param pcie_port PCIe port to read from
243 * @param cfg_offset Address to read
247 uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset);
250 * Write a PCIe config space register indirectly. This is used for
251 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
253 * @param pcie_port PCIe port to write to
254 * @param cfg_offset Address to write
255 * @param val Value to write
257 void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val);
260 * Write a 32bit value to the Octeon NPEI register space
262 * @param address Address to write to
263 * @param val Value to write
265 static inline void cvmx_pcie_npei_write32(uint64_t address, uint32_t val)
267 cvmx_write64_uint32(address ^ 4, val);
268 cvmx_read64_uint32(address ^ 4);
272 * Read a 32bit value from the Octeon NPEI register space
274 * @param address Address to read
277 static inline uint32_t cvmx_pcie_npei_read32(uint64_t address)
279 return cvmx_read64_uint32(address ^ 4);
283 * Initialize a PCIe port for use in target(EP) mode.
285 * @return Zero on success
287 int cvmx_pcie_ep_initialize(void);
290 * Wait for posted PCIe read/writes to reach the other side of
291 * the internal PCIe switch. This will insure that core
292 * read/writes are posted before anything after this function
293 * is called. This may be necessary when writing to memory that
294 * will later be read using the DMA/PKT engines.
296 * @param pcie_port PCIe port to wait for
298 void cvmx_pcie_wait_for_pending(int pcie_port);