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47 * Support library for the hardware work queue timers.
49 * <hr>$Revision: 42180 $<hr>
51 #include "executive-config.h"
52 #include "cvmx-config.h"
54 #include "cvmx-sysinfo.h"
56 #include "cvmx-bootmem.h"
58 /* CSR typedefs have been moved to cvmx-csr-*.h */
61 * Global structure holding the state of all timers.
63 CVMX_SHARED cvmx_tim_t cvmx_tim;
66 #ifdef CVMX_ENABLE_TIMER_FUNCTIONS
68 * Setup a timer for use. Must be called before the timer
71 * @param tick Time between each bucket in microseconds. This must not be
72 * smaller than 1024/(clock frequency in MHz).
73 * @param max_ticks The maximum number of ticks the timer must be able
74 * to schedule in the future. There are guaranteed to be enough
75 * timer buckets such that:
76 * number of buckets >= max_ticks.
77 * @return Zero on success. Negative on error. Failures are possible
78 * if the number of buckets needed is too large or memory
79 * allocation fails for creating the buckets.
81 int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
83 cvmx_tim_mem_ring0_t config_ring0;
84 cvmx_tim_mem_ring1_t config_ring1;
87 #if !(defined(__KERNEL__) && defined(linux))
88 cvmx_sysinfo_t *sys_info_ptr = cvmx_sysinfo_get();
89 uint64_t cpu_clock_hz = sys_info_ptr->cpu_clock_hz;
91 uint64_t cpu_clock_hz = octeon_get_clock_rate();
94 uint64_t hw_tick_ns_allowed;
95 uint64_t tick_ns = 1000 * tick;
99 /* for the simulator */
100 if (cpu_clock_hz == 0)
101 cpu_clock_hz = 333000000;
103 hw_tick_ns = 1024 * 1000000000ull / cpu_clock_hz;
105 * Doulbe the minmal allowed tick to 2* HW tick. tick between
106 * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval
107 * to zero, or 1024 cycles. This is not enough time for the timer unit
108 * to fetch the bucket data, Resulting in timer ring error interrupt
109 * be always generated. Avoid such setting in software
111 hw_tick_ns_allowed = hw_tick_ns *2;
113 /* Make sure the timers are stopped */
116 /* Reinitialize out timer state */
117 memset(&cvmx_tim, 0, sizeof(cvmx_tim));
120 if ((tick_ns < (hw_tick_ns_allowed)) || (tick_ns > 4194304 * hw_tick_ns))
122 cvmx_dprintf("init: tick wrong size. Requested tick %lu(ns) is smaller than"
123 " the minimal ticks allowed by hardware %lu(ns)\n",
124 tick_ns, hw_tick_ns_allowed);
130 if (tick_ns < (hw_tick_ns << i))
134 cvmx_tim.max_ticks = (uint32_t)max_ticks;
135 cvmx_tim.bucket_shift = (uint32_t)(i - 1 + 10);
136 cvmx_tim.tick_cycles = tick * cpu_clock_hz / 1000000;
138 temp = (max_ticks * cvmx_tim.tick_cycles) >> cvmx_tim.bucket_shift;
140 /* round up to nearest power of 2 */
142 temp = temp | (temp >> 1);
143 temp = temp | (temp >> 2);
144 temp = temp | (temp >> 4);
145 temp = temp | (temp >> 8);
146 temp = temp | (temp >> 16);
147 cvmx_tim.num_buckets = temp + 1;
149 /* ensure input params fall into permitted ranges */
150 if ((cvmx_tim.num_buckets < 3) || cvmx_tim.num_buckets > 1048576)
152 cvmx_dprintf("init: num_buckets out of range\n");
156 /* Allocate the timer buckets from hardware addressable memory */
157 cvmx_tim.bucket = cvmx_bootmem_alloc(CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets
158 * sizeof(cvmx_tim_bucket_entry_t), CVMX_CACHE_LINE_SIZE);
159 if (cvmx_tim.bucket == NULL)
161 cvmx_dprintf("init: allocation problem\n");
164 memset(cvmx_tim.bucket, 0, CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets * sizeof(cvmx_tim_bucket_entry_t));
166 cvmx_tim.start_time = 0;
168 /* Loop through all timers */
169 for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
171 cvmx_tim_bucket_entry_t *bucket = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets;
172 /* Tell the hardware where about the bucket array */
173 config_ring0.u64 = 0;
174 config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5;
175 config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1;
176 config_ring0.s.ring = timer_id;
177 cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64);
179 /* Tell the hardware the size of each chunk block in pointers */
180 config_ring1.u64 = 0;
181 config_ring1.s.enable = 1;
182 config_ring1.s.pool = CVMX_FPA_TIMER_POOL;
183 config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8;
184 config_ring1.s.interval = (1 << (cvmx_tim.bucket_shift - 10)) - 1;
185 config_ring1.s.ring = timer_id;
186 cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64);
194 * Start the hardware timer processing
196 void cvmx_tim_start(void)
198 cvmx_tim_control_t control;
201 control.s.enable_dwb = 1;
202 control.s.enable_timers = 1;
204 /* Remember when we started the timers */
205 cvmx_tim.start_time = cvmx_get_cycle();
206 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
211 * Stop the hardware timer processing. Timers stay configured.
213 void cvmx_tim_stop(void)
215 cvmx_tim_control_t control;
217 control.s.enable_dwb = 0;
218 control.s.enable_timers = 0;
219 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
224 * Stop the timer. After this the timer must be setup again
227 #ifdef CVMX_ENABLE_TIMER_FUNCTIONS
228 void cvmx_tim_shutdown(void)
232 uint64_t entries_per_chunk;
234 /* Make sure the timers are stopped */
237 entries_per_chunk = CVMX_FPA_TIMER_POOL_SIZE/8 - 1;
239 /* Now walk all buckets freeing the chunks */
240 for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
242 for (bucket=0; bucket<cvmx_tim.num_buckets; bucket++)
245 uint64_t next_chunk_addr;
246 cvmx_tim_bucket_entry_t *bucket_ptr = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets + bucket;
247 CVMX_PREFETCH128(CAST64(bucket_ptr)); /* prefetch the next cacheline for future buckets */
249 /* Each bucket contains a list of chunks */
250 chunk_addr = bucket_ptr->first_chunk_addr;
251 while (bucket_ptr->num_entries)
254 cvmx_dprintf("Freeing Timer Chunk 0x%llx\n", CAST64(chunk_addr));
256 /* Read next chunk pointer from end of the current chunk */
257 next_chunk_addr = cvmx_read_csr(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, chunk_addr + CVMX_FPA_TIMER_POOL_SIZE - 8));
259 cvmx_fpa_free(cvmx_phys_to_ptr(chunk_addr), CVMX_FPA_TIMER_POOL, 0);
260 chunk_addr = next_chunk_addr;
261 if (bucket_ptr->num_entries > entries_per_chunk)
262 bucket_ptr->num_entries -= entries_per_chunk;
264 bucket_ptr->num_entries = 0;