2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
52 #include <cam/cam_ccb.h>
53 #include <cam/cam_sim.h>
54 #include <cam/cam_xpt_sim.h>
55 #include <cam/cam_debug.h>
57 /* local prototypes */
58 static int ahci_setup_interrupt(device_t dev);
59 static void ahci_intr(void *data);
60 static void ahci_intr_one(void *data);
61 static int ahci_suspend(device_t dev);
62 static int ahci_resume(device_t dev);
63 static int ahci_ch_init(device_t dev);
64 static int ahci_ch_deinit(device_t dev);
65 static int ahci_ch_suspend(device_t dev);
66 static int ahci_ch_resume(device_t dev);
67 static void ahci_ch_pm(void *arg);
68 static void ahci_ch_intr_locked(void *data);
69 static void ahci_ch_intr(void *data);
70 static int ahci_ctlr_reset(device_t dev);
71 static int ahci_ctlr_setup(device_t dev);
72 static void ahci_begin_transaction(device_t dev, union ccb *ccb);
73 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
74 static void ahci_execute_transaction(struct ahci_slot *slot);
75 static void ahci_timeout(struct ahci_slot *slot);
76 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
77 static int ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
78 static void ahci_dmainit(device_t dev);
79 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
80 static void ahci_dmafini(device_t dev);
81 static void ahci_slotsalloc(device_t dev);
82 static void ahci_slotsfree(device_t dev);
83 static void ahci_reset(device_t dev);
84 static void ahci_start(device_t dev, int fbs);
85 static void ahci_stop(device_t dev);
86 static void ahci_clo(device_t dev);
87 static void ahci_start_fr(device_t dev);
88 static void ahci_stop_fr(device_t dev);
90 static int ahci_sata_connect(struct ahci_channel *ch);
91 static int ahci_sata_phy_reset(device_t dev);
92 static int ahci_wait_ready(device_t dev, int t);
94 static void ahci_issue_read_log(device_t dev);
95 static void ahci_process_read_log(device_t dev, union ccb *ccb);
97 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
98 static void ahcipoll(struct cam_sim *sim);
100 MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
107 #define AHCI_Q_NOFORCE 1
108 #define AHCI_Q_NOPMP 2
109 #define AHCI_Q_NONCQ 4
111 #define AHCI_Q_2CH 16
112 #define AHCI_Q_4CH 32
113 #define AHCI_Q_EDGEIS 64
114 #define AHCI_Q_SATA2 128
115 #define AHCI_Q_NOBSYRES 256
116 #define AHCI_Q_NOAA 512
118 {0x43801002, 0x00, "ATI IXP600", 0},
119 {0x43901002, 0x00, "ATI IXP700", 0},
120 {0x43911002, 0x00, "ATI IXP700", 0},
121 {0x43921002, 0x00, "ATI IXP700", 0},
122 {0x43931002, 0x00, "ATI IXP700", 0},
123 {0x43941002, 0x00, "ATI IXP800", 0},
124 {0x43951002, 0x00, "ATI IXP800", 0},
125 {0x26528086, 0x00, "Intel ICH6", AHCI_Q_NOFORCE},
126 {0x26538086, 0x00, "Intel ICH6M", AHCI_Q_NOFORCE},
127 {0x26818086, 0x00, "Intel ESB2", 0},
128 {0x26828086, 0x00, "Intel ESB2", 0},
129 {0x26838086, 0x00, "Intel ESB2", 0},
130 {0x27c18086, 0x00, "Intel ICH7", 0},
131 {0x27c38086, 0x00, "Intel ICH7", 0},
132 {0x27c58086, 0x00, "Intel ICH7M", 0},
133 {0x27c68086, 0x00, "Intel ICH7M", 0},
134 {0x28218086, 0x00, "Intel ICH8", 0},
135 {0x28228086, 0x00, "Intel ICH8", 0},
136 {0x28248086, 0x00, "Intel ICH8", 0},
137 {0x28298086, 0x00, "Intel ICH8M", 0},
138 {0x282a8086, 0x00, "Intel ICH8M", 0},
139 {0x29228086, 0x00, "Intel ICH9", 0},
140 {0x29238086, 0x00, "Intel ICH9", 0},
141 {0x29248086, 0x00, "Intel ICH9", 0},
142 {0x29258086, 0x00, "Intel ICH9", 0},
143 {0x29278086, 0x00, "Intel ICH9", 0},
144 {0x29298086, 0x00, "Intel ICH9M", 0},
145 {0x292a8086, 0x00, "Intel ICH9M", 0},
146 {0x292b8086, 0x00, "Intel ICH9M", 0},
147 {0x292c8086, 0x00, "Intel ICH9M", 0},
148 {0x292f8086, 0x00, "Intel ICH9M", 0},
149 {0x294d8086, 0x00, "Intel ICH9", 0},
150 {0x294e8086, 0x00, "Intel ICH9M", 0},
151 {0x3a058086, 0x00, "Intel ICH10", 0},
152 {0x3a228086, 0x00, "Intel ICH10", 0},
153 {0x3a258086, 0x00, "Intel ICH10", 0},
154 {0x3b228086, 0x00, "Intel 5 Series/3400 Series", 0},
155 {0x3b238086, 0x00, "Intel 5 Series/3400 Series", 0},
156 {0x3b258086, 0x00, "Intel 5 Series/3400 Series", 0},
157 {0x3b298086, 0x00, "Intel 5 Series/3400 Series", 0},
158 {0x3b2c8086, 0x00, "Intel 5 Series/3400 Series", 0},
159 {0x3b2f8086, 0x00, "Intel 5 Series/3400 Series", 0},
160 {0x1c028086, 0x00, "Intel Cougar Point", 0},
161 {0x1c038086, 0x00, "Intel Cougar Point", 0},
162 {0x1c048086, 0x00, "Intel Cougar Point", 0},
163 {0x1c058086, 0x00, "Intel Cougar Point", 0},
164 {0x2361197b, 0x00, "JMicron JMB361", AHCI_Q_NOFORCE},
165 {0x2363197b, 0x00, "JMicron JMB363", AHCI_Q_NOFORCE},
166 {0x2365197b, 0x00, "JMicron JMB365", AHCI_Q_NOFORCE},
167 {0x2366197b, 0x00, "JMicron JMB366", AHCI_Q_NOFORCE},
168 {0x2368197b, 0x00, "JMicron JMB368", AHCI_Q_NOFORCE},
169 {0x611111ab, 0x00, "Marvell 88SX6111", AHCI_Q_NOFORCE|AHCI_Q_1CH|AHCI_Q_EDGEIS},
170 {0x612111ab, 0x00, "Marvell 88SX6121", AHCI_Q_NOFORCE|AHCI_Q_2CH|AHCI_Q_EDGEIS},
171 {0x614111ab, 0x00, "Marvell 88SX6141", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS},
172 {0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS},
173 {0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES},
174 {0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES},
175 {0x06201103, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
176 {0x06201b4b, 0x00, "HighPoint RocketRAID 620", AHCI_Q_NOBSYRES},
177 {0x06221103, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
178 {0x06221b4b, 0x00, "HighPoint RocketRAID 622", AHCI_Q_NOBSYRES},
179 {0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
180 {0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
181 {0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
182 {0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
183 {0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
184 {0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
185 {0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
186 {0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
187 {0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
188 {0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
189 {0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
190 {0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
191 {0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
192 {0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
193 {0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
194 {0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
195 {0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
196 {0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
197 {0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
198 {0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
199 {0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
200 {0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
201 {0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
202 {0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
203 {0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
204 {0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
205 {0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
206 {0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
207 {0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
208 {0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
209 {0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
210 {0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
211 {0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
212 {0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
213 {0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
214 {0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
215 {0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
216 {0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
217 {0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
218 {0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
219 {0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
220 {0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
221 {0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
222 {0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
223 {0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
224 {0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
225 {0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
226 {0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
227 {0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
228 {0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
229 {0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
230 {0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
231 {0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
232 {0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
233 {0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
234 {0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
235 {0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
236 {0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
237 {0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
238 {0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
239 {0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
240 {0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
241 {0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
242 {0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
243 {0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
244 {0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
245 {0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
246 {0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
247 {0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
248 {0x33491106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
249 {0x62871106, 0x00, "VIA VT8251", AHCI_Q_NOPMP|AHCI_Q_NONCQ},
250 {0x11841039, 0x00, "SiS 966", 0},
251 {0x11851039, 0x00, "SiS 968", 0},
252 {0x01861039, 0x00, "SiS 968", 0},
253 {0x00000000, 0x00, NULL, 0}
257 ahci_probe(device_t dev)
261 uint32_t devid = pci_get_devid(dev);
262 uint8_t revid = pci_get_revid(dev);
264 /* Is this a possible AHCI candidate? */
265 if (pci_get_class(dev) == PCIC_STORAGE &&
266 pci_get_subclass(dev) == PCIS_STORAGE_SATA &&
267 pci_get_progif(dev) == PCIP_STORAGE_SATA_AHCI_1_0)
269 /* Is this a known AHCI chip? */
270 for (i = 0; ahci_ids[i].id != 0; i++) {
271 if (ahci_ids[i].id == devid &&
272 ahci_ids[i].rev <= revid &&
273 (valid || !(ahci_ids[i].quirks & AHCI_Q_NOFORCE))) {
274 /* Do not attach JMicrons with single PCI function. */
275 if (pci_get_vendor(dev) == 0x197b &&
276 (pci_read_config(dev, 0xdf, 1) & 0x40) == 0)
278 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
280 device_set_desc_copy(dev, buf);
281 return (BUS_PROBE_VENDOR);
286 device_set_desc_copy(dev, "AHCI SATA controller");
287 return (BUS_PROBE_VENDOR);
291 ahci_ata_probe(device_t dev)
295 uint32_t devid = pci_get_devid(dev);
296 uint8_t revid = pci_get_revid(dev);
298 if ((intptr_t)device_get_ivars(dev) >= 0)
300 /* Is this a known AHCI chip? */
301 for (i = 0; ahci_ids[i].id != 0; i++) {
302 if (ahci_ids[i].id == devid &&
303 ahci_ids[i].rev <= revid) {
304 snprintf(buf, sizeof(buf), "%s AHCI SATA controller",
306 device_set_desc_copy(dev, buf);
307 return (BUS_PROBE_VENDOR);
310 device_set_desc_copy(dev, "AHCI SATA controller");
311 return (BUS_PROBE_VENDOR);
315 ahci_attach(device_t dev)
317 struct ahci_controller *ctlr = device_get_softc(dev);
319 int error, unit, speed, i;
320 uint32_t devid = pci_get_devid(dev);
321 uint8_t revid = pci_get_revid(dev);
326 while (ahci_ids[i].id != 0 &&
327 (ahci_ids[i].id != devid ||
328 ahci_ids[i].rev > revid))
330 ctlr->quirks = ahci_ids[i].quirks;
331 resource_int_value(device_get_name(dev),
332 device_get_unit(dev), "ccc", &ctlr->ccc);
333 /* if we have a memory BAR(5) we are likely on an AHCI part */
334 ctlr->r_rid = PCIR_BAR(5);
335 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
336 &ctlr->r_rid, RF_ACTIVE)))
338 /* Setup our own memory management for channels. */
339 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
340 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
341 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
342 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
343 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
344 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
347 if ((error = rman_manage_region(&ctlr->sc_iomem,
348 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
349 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
350 rman_fini(&ctlr->sc_iomem);
353 pci_enable_busmaster(dev);
354 /* Reset controller */
355 if ((error = ahci_ctlr_reset(dev)) != 0) {
356 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
357 rman_fini(&ctlr->sc_iomem);
360 /* Get the HW capabilities */
361 version = ATA_INL(ctlr->r_mem, AHCI_VS);
362 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
363 if (version >= 0x00010020)
364 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
365 if (ctlr->caps & AHCI_CAP_EMS)
366 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
367 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
368 if (ctlr->quirks & AHCI_Q_1CH) {
369 ctlr->caps &= ~AHCI_CAP_NPMASK;
370 ctlr->ichannels &= 0x01;
372 if (ctlr->quirks & AHCI_Q_2CH) {
373 ctlr->caps &= ~AHCI_CAP_NPMASK;
375 ctlr->ichannels &= 0x03;
377 if (ctlr->quirks & AHCI_Q_4CH) {
378 ctlr->caps &= ~AHCI_CAP_NPMASK;
380 ctlr->ichannels &= 0x0f;
382 ctlr->channels = MAX(flsl(ctlr->ichannels),
383 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
384 if (ctlr->quirks & AHCI_Q_NOPMP)
385 ctlr->caps &= ~AHCI_CAP_SPM;
386 if (ctlr->quirks & AHCI_Q_NONCQ)
387 ctlr->caps &= ~AHCI_CAP_SNCQ;
388 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
390 ahci_ctlr_setup(dev);
391 /* Setup interrupts. */
392 if (ahci_setup_interrupt(dev)) {
393 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
394 rman_fini(&ctlr->sc_iomem);
397 /* Announce HW capabilities. */
398 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
400 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
401 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
402 ((version >> 4) & 0xf0) + (version & 0x0f),
403 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
404 ((speed == 1) ? "1.5":((speed == 2) ? "3":
405 ((speed == 3) ? "6":"?"))),
406 (ctlr->caps & AHCI_CAP_SPM) ?
407 "supported" : "not supported",
408 (ctlr->caps & AHCI_CAP_FBSS) ?
411 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
412 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
413 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
414 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
415 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
416 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
417 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
418 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
419 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
420 ((speed == 1) ? "1.5":((speed == 2) ? "3":
421 ((speed == 3) ? "6":"?"))));
422 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
423 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
424 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
425 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
426 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
427 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
428 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
429 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
430 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
431 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
432 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
433 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
435 if (bootverbose && version >= 0x00010020) {
436 device_printf(dev, "Caps2:%s%s%s\n",
437 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
438 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
439 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
441 if (bootverbose && (ctlr->caps & AHCI_CAP_EMS)) {
442 device_printf(dev, "EM Caps:%s%s%s%s%s%s%s%s\n",
443 (ctlr->capsem & AHCI_EM_PM) ? " PM":"",
444 (ctlr->capsem & AHCI_EM_ALHD) ? " ALHD":"",
445 (ctlr->capsem & AHCI_EM_XMT) ? " XMT":"",
446 (ctlr->capsem & AHCI_EM_SMB) ? " SMB":"",
447 (ctlr->capsem & AHCI_EM_SGPIO) ? " SGPIO":"",
448 (ctlr->capsem & AHCI_EM_SES2) ? " SES-2":"",
449 (ctlr->capsem & AHCI_EM_SAFTE) ? " SAF-TE":"",
450 (ctlr->capsem & AHCI_EM_LED) ? " LED":"");
452 /* Attach all channels on this controller */
453 for (unit = 0; unit < ctlr->channels; unit++) {
454 if ((ctlr->ichannels & (1 << unit)) == 0)
456 child = device_add_child(dev, "ahcich", -1);
458 device_printf(dev, "failed to add channel device\n");
460 device_set_ivars(child, (void *)(intptr_t)unit);
462 bus_generic_attach(dev);
467 ahci_detach(device_t dev)
469 struct ahci_controller *ctlr = device_get_softc(dev);
473 /* Detach & delete all children */
474 if (!device_get_children(dev, &children, &nchildren)) {
475 for (i = 0; i < nchildren; i++)
476 device_delete_child(dev, children[i]);
477 free(children, M_TEMP);
479 /* Free interrupts. */
480 for (i = 0; i < ctlr->numirqs; i++) {
481 if (ctlr->irqs[i].r_irq) {
482 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
483 ctlr->irqs[i].handle);
484 bus_release_resource(dev, SYS_RES_IRQ,
485 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
488 pci_release_msi(dev);
490 rman_fini(&ctlr->sc_iomem);
492 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
497 ahci_ctlr_reset(device_t dev)
499 struct ahci_controller *ctlr = device_get_softc(dev);
502 if (pci_read_config(dev, 0x00, 4) == 0x28298086 &&
503 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
504 pci_write_config(dev, 0x92, 0x01, 1);
505 /* Enable AHCI mode */
506 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
507 /* Reset AHCI controller */
508 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
509 for (timeout = 1000; timeout > 0; timeout--) {
511 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
515 device_printf(dev, "AHCI controller reset failure\n");
518 /* Reenable AHCI mode */
519 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
524 ahci_ctlr_setup(device_t dev)
526 struct ahci_controller *ctlr = device_get_softc(dev);
527 /* Clear interrupts */
528 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
531 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
532 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
533 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
534 (4 << AHCI_CCCC_CC_SHIFT) |
536 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
537 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
540 "CCC with %dms/4cmd enabled on vector %d\n",
541 ctlr->ccc, ctlr->cccv);
544 /* Enable AHCI interrupts */
545 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
546 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
551 ahci_suspend(device_t dev)
553 struct ahci_controller *ctlr = device_get_softc(dev);
555 bus_generic_suspend(dev);
556 /* Disable interupts, so the state change(s) doesn't trigger */
557 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
558 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
563 ahci_resume(device_t dev)
567 if ((res = ahci_ctlr_reset(dev)) != 0)
569 ahci_ctlr_setup(dev);
570 return (bus_generic_resume(dev));
574 ahci_setup_interrupt(device_t dev)
576 struct ahci_controller *ctlr = device_get_softc(dev);
580 resource_int_value(device_get_name(dev),
581 device_get_unit(dev), "msi", &msi);
585 msi = min(1, pci_msi_count(dev));
587 msi = pci_msi_count(dev);
588 /* Allocate MSI if needed/present. */
589 if (msi && pci_alloc_msi(dev, &msi) == 0) {
595 /* Check for single MSI vector fallback. */
596 if (ctlr->numirqs > 1 &&
597 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
598 device_printf(dev, "Falling back to one MSI\n");
601 /* Allocate all IRQs. */
602 for (i = 0; i < ctlr->numirqs; i++) {
603 ctlr->irqs[i].ctlr = ctlr;
604 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0);
605 if (ctlr->numirqs == 1 || i >= ctlr->channels ||
606 (ctlr->ccc && i == ctlr->cccv))
607 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
608 else if (i == ctlr->numirqs - 1)
609 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
611 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
612 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
613 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
614 device_printf(dev, "unable to map interrupt\n");
617 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
618 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr,
619 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
620 /* SOS XXX release r_irq */
621 device_printf(dev, "unable to setup interrupt\n");
629 * Common case interrupt handler.
632 ahci_intr(void *data)
634 struct ahci_controller_irq *irq = data;
635 struct ahci_controller *ctlr = irq->ctlr;
636 u_int32_t is, ise = 0;
640 if (irq->mode == AHCI_IRQ_MODE_ALL) {
643 is = ctlr->ichannels;
645 is = ATA_INL(ctlr->r_mem, AHCI_IS);
646 } else { /* AHCI_IRQ_MODE_AFTER */
647 unit = irq->r_irq_rid - 1;
648 is = ATA_INL(ctlr->r_mem, AHCI_IS);
650 /* CCC interrupt is edge triggered. */
652 ise = 1 << ctlr->cccv;
653 /* Some controllers have edge triggered IS. */
654 if (ctlr->quirks & AHCI_Q_EDGEIS)
657 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
658 for (; unit < ctlr->channels; unit++) {
659 if ((is & (1 << unit)) != 0 &&
660 (arg = ctlr->interrupt[unit].argument)) {
661 ctlr->interrupt[unit].function(arg);
664 /* AHCI declares level triggered IS. */
665 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
666 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
670 * Simplified interrupt handler for multivector MSI mode.
673 ahci_intr_one(void *data)
675 struct ahci_controller_irq *irq = data;
676 struct ahci_controller *ctlr = irq->ctlr;
680 unit = irq->r_irq_rid - 1;
681 /* Some controllers have edge triggered IS. */
682 if (ctlr->quirks & AHCI_Q_EDGEIS)
683 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
684 if ((arg = ctlr->interrupt[unit].argument))
685 ctlr->interrupt[unit].function(arg);
686 /* AHCI declares level triggered IS. */
687 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
688 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
691 static struct resource *
692 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
693 u_long start, u_long end, u_long count, u_int flags)
695 struct ahci_controller *ctlr = device_get_softc(dev);
696 int unit = ((struct ahci_channel *)device_get_softc(child))->unit;
697 struct resource *res = NULL;
698 int offset = AHCI_OFFSET + (unit << 7);
703 st = rman_get_start(ctlr->r_mem);
704 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
705 st + offset + 127, 128, RF_ACTIVE, child);
707 bus_space_handle_t bsh;
709 bsh = rman_get_bushandle(ctlr->r_mem);
710 bst = rman_get_bustag(ctlr->r_mem);
711 bus_space_subregion(bst, bsh, offset, 128, &bsh);
712 rman_set_bushandle(res, bsh);
713 rman_set_bustag(res, bst);
717 if (*rid == ATA_IRQ_RID)
718 res = ctlr->irqs[0].r_irq;
725 ahci_release_resource(device_t dev, device_t child, int type, int rid,
731 rman_release_resource(r);
734 if (rid != ATA_IRQ_RID)
742 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
743 int flags, driver_filter_t *filter, driver_intr_t *function,
744 void *argument, void **cookiep)
746 struct ahci_controller *ctlr = device_get_softc(dev);
747 int unit = (intptr_t)device_get_ivars(child);
749 if (filter != NULL) {
750 printf("ahci.c: we cannot use a filter here\n");
753 ctlr->interrupt[unit].function = function;
754 ctlr->interrupt[unit].argument = argument;
759 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
762 struct ahci_controller *ctlr = device_get_softc(dev);
763 int unit = (intptr_t)device_get_ivars(child);
765 ctlr->interrupt[unit].function = NULL;
766 ctlr->interrupt[unit].argument = NULL;
771 ahci_print_child(device_t dev, device_t child)
775 retval = bus_print_child_header(dev, child);
776 retval += printf(" at channel %d",
777 (int)(intptr_t)device_get_ivars(child));
778 retval += bus_print_child_footer(dev, child);
784 ahci_child_location_str(device_t dev, device_t child, char *buf,
788 snprintf(buf, buflen, "channel=%d",
789 (int)(intptr_t)device_get_ivars(child));
793 devclass_t ahci_devclass;
794 static device_method_t ahci_methods[] = {
795 DEVMETHOD(device_probe, ahci_probe),
796 DEVMETHOD(device_attach, ahci_attach),
797 DEVMETHOD(device_detach, ahci_detach),
798 DEVMETHOD(device_suspend, ahci_suspend),
799 DEVMETHOD(device_resume, ahci_resume),
800 DEVMETHOD(bus_print_child, ahci_print_child),
801 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
802 DEVMETHOD(bus_release_resource, ahci_release_resource),
803 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
804 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
805 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
808 static driver_t ahci_driver = {
811 sizeof(struct ahci_controller)
813 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0);
814 static device_method_t ahci_ata_methods[] = {
815 DEVMETHOD(device_probe, ahci_ata_probe),
816 DEVMETHOD(device_attach, ahci_attach),
817 DEVMETHOD(device_detach, ahci_detach),
818 DEVMETHOD(device_suspend, ahci_suspend),
819 DEVMETHOD(device_resume, ahci_resume),
820 DEVMETHOD(bus_print_child, ahci_print_child),
821 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
822 DEVMETHOD(bus_release_resource, ahci_release_resource),
823 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
824 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
825 DEVMETHOD(bus_child_location_str, ahci_child_location_str),
828 static driver_t ahci_ata_driver = {
831 sizeof(struct ahci_controller)
833 DRIVER_MODULE(ahci, atapci, ahci_ata_driver, ahci_devclass, 0, 0);
834 MODULE_VERSION(ahci, 1);
835 MODULE_DEPEND(ahci, cam, 1, 1, 1);
838 ahci_ch_probe(device_t dev)
841 device_set_desc_copy(dev, "AHCI channel");
846 ahci_ch_attach(device_t dev)
848 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
849 struct ahci_channel *ch = device_get_softc(dev);
850 struct cam_devq *devq;
851 int rid, error, i, sata_rev = 0;
855 ch->unit = (intptr_t)device_get_ivars(dev);
856 ch->caps = ctlr->caps;
857 ch->caps2 = ctlr->caps2;
858 ch->quirks = ctlr->quirks;
859 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
860 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
861 resource_int_value(device_get_name(dev),
862 device_get_unit(dev), "pm_level", &ch->pm_level);
863 if (ch->pm_level > 3)
864 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
865 /* Limit speed for my onboard JMicron external port.
866 * It is not eSATA really. */
867 if (pci_get_devid(ctlr->dev) == 0x2363197b &&
868 pci_get_subvendor(ctlr->dev) == 0x1043 &&
869 pci_get_subdevice(ctlr->dev) == 0x81e4 &&
872 if (ch->quirks & AHCI_Q_SATA2)
874 resource_int_value(device_get_name(dev),
875 device_get_unit(dev), "sata_rev", &sata_rev);
876 for (i = 0; i < 16; i++) {
877 ch->user[i].revision = sata_rev;
878 ch->user[i].mode = 0;
879 ch->user[i].bytecount = 8192;
880 ch->user[i].tags = ch->numslots;
881 ch->user[i].caps = 0;
882 ch->curr[i] = ch->user[i];
884 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
885 CTS_SATA_CAPS_H_APST |
886 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
888 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA;
891 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
895 ahci_slotsalloc(dev);
899 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
900 &rid, RF_SHAREABLE | RF_ACTIVE))) {
901 device_printf(dev, "Unable to map interrupt\n");
905 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
906 ahci_ch_intr_locked, dev, &ch->ih))) {
907 device_printf(dev, "Unable to setup interrupt\n");
911 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
912 version = ATA_INL(ctlr->r_mem, AHCI_VS);
913 if (version < 0x00010020 && (ctlr->caps & AHCI_CAP_FBSS))
914 ch->chcaps |= AHCI_P_CMD_FBSCP;
916 device_printf(dev, "Caps:%s%s%s%s%s\n",
917 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
918 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
919 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
920 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
921 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"");
923 /* Create the device queue for our SIM. */
924 devq = cam_simq_alloc(ch->numslots);
926 device_printf(dev, "Unable to allocate simq\n");
930 /* Construct SIM entry */
931 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
932 device_get_unit(dev), &ch->mtx,
933 min(2, ch->numslots),
934 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
936 if (ch->sim == NULL) {
938 device_printf(dev, "unable to allocate sim\n");
942 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
943 device_printf(dev, "unable to register xpt bus\n");
947 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
948 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
949 device_printf(dev, "unable to create path\n");
953 if (ch->pm_level > 3) {
954 callout_reset(&ch->pm_timer,
955 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
958 mtx_unlock(&ch->mtx);
962 xpt_bus_deregister(cam_sim_path(ch->sim));
964 cam_sim_free(ch->sim, /*free_devq*/TRUE);
966 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
968 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
969 mtx_unlock(&ch->mtx);
970 mtx_destroy(&ch->mtx);
975 ahci_ch_detach(device_t dev)
977 struct ahci_channel *ch = device_get_softc(dev);
980 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
981 xpt_free_path(ch->path);
982 xpt_bus_deregister(cam_sim_path(ch->sim));
983 cam_sim_free(ch->sim, /*free_devq*/TRUE);
984 mtx_unlock(&ch->mtx);
986 if (ch->pm_level > 3)
987 callout_drain(&ch->pm_timer);
988 bus_teardown_intr(dev, ch->r_irq, ch->ih);
989 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
995 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
996 mtx_destroy(&ch->mtx);
1001 ahci_ch_init(device_t dev)
1003 struct ahci_channel *ch = device_get_softc(dev);
1006 /* Disable port interrupts */
1007 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1008 /* Setup work areas */
1009 work = ch->dma.work_bus + AHCI_CL_OFFSET;
1010 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
1011 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
1012 work = ch->dma.rfis_bus;
1013 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
1014 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
1015 /* Activate the channel and power/spin up device */
1016 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
1017 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
1018 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
1019 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1026 ahci_ch_deinit(device_t dev)
1028 struct ahci_channel *ch = device_get_softc(dev);
1030 /* Disable port interrupts. */
1031 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1032 /* Reset command register. */
1035 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1036 /* Allow everything, including partial and slumber modes. */
1037 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1038 /* Request slumber mode transition and give some time to get there. */
1039 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1042 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1047 ahci_ch_suspend(device_t dev)
1049 struct ahci_channel *ch = device_get_softc(dev);
1052 xpt_freeze_simq(ch->sim, 1);
1054 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1055 ahci_ch_deinit(dev);
1056 mtx_unlock(&ch->mtx);
1061 ahci_ch_resume(device_t dev)
1063 struct ahci_channel *ch = device_get_softc(dev);
1068 xpt_release_simq(ch->sim, TRUE);
1069 mtx_unlock(&ch->mtx);
1073 devclass_t ahcich_devclass;
1074 static device_method_t ahcich_methods[] = {
1075 DEVMETHOD(device_probe, ahci_ch_probe),
1076 DEVMETHOD(device_attach, ahci_ch_attach),
1077 DEVMETHOD(device_detach, ahci_ch_detach),
1078 DEVMETHOD(device_suspend, ahci_ch_suspend),
1079 DEVMETHOD(device_resume, ahci_ch_resume),
1082 static driver_t ahcich_driver = {
1085 sizeof(struct ahci_channel)
1087 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, 0, 0);
1089 struct ahci_dc_cb_args {
1095 ahci_dmainit(device_t dev)
1097 struct ahci_channel *ch = device_get_softc(dev);
1098 struct ahci_dc_cb_args dcba;
1101 if (ch->caps & AHCI_CAP_64BIT)
1102 ch->dma.max_address = BUS_SPACE_MAXADDR;
1104 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT;
1106 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1107 ch->dma.max_address, BUS_SPACE_MAXADDR,
1108 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1109 0, NULL, NULL, &ch->dma.work_tag))
1111 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0,
1114 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1115 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1116 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1119 ch->dma.work_bus = dcba.maddr;
1120 /* FIS receive area. */
1121 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1125 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1126 ch->dma.max_address, BUS_SPACE_MAXADDR,
1127 NULL, NULL, rfsize, 1, rfsize,
1128 0, NULL, NULL, &ch->dma.rfis_tag))
1130 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1133 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1134 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
1135 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1138 ch->dma.rfis_bus = dcba.maddr;
1140 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1141 ch->dma.max_address, BUS_SPACE_MAXADDR,
1143 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
1144 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1145 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
1151 device_printf(dev, "WARNING - DMA initialization failed\n");
1156 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1158 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1160 if (!(dcba->error = error))
1161 dcba->maddr = segs[0].ds_addr;
1165 ahci_dmafini(device_t dev)
1167 struct ahci_channel *ch = device_get_softc(dev);
1169 if (ch->dma.data_tag) {
1170 bus_dma_tag_destroy(ch->dma.data_tag);
1171 ch->dma.data_tag = NULL;
1173 if (ch->dma.rfis_bus) {
1174 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1175 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1176 ch->dma.rfis_bus = 0;
1177 ch->dma.rfis_map = NULL;
1178 ch->dma.rfis = NULL;
1180 if (ch->dma.work_bus) {
1181 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1182 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1183 ch->dma.work_bus = 0;
1184 ch->dma.work_map = NULL;
1185 ch->dma.work = NULL;
1187 if (ch->dma.work_tag) {
1188 bus_dma_tag_destroy(ch->dma.work_tag);
1189 ch->dma.work_tag = NULL;
1194 ahci_slotsalloc(device_t dev)
1196 struct ahci_channel *ch = device_get_softc(dev);
1199 /* Alloc and setup command/dma slots */
1200 bzero(ch->slot, sizeof(ch->slot));
1201 for (i = 0; i < ch->numslots; i++) {
1202 struct ahci_slot *slot = &ch->slot[i];
1206 slot->state = AHCI_SLOT_EMPTY;
1208 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1210 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1211 device_printf(ch->dev, "FAILURE - create data_map\n");
1216 ahci_slotsfree(device_t dev)
1218 struct ahci_channel *ch = device_get_softc(dev);
1221 /* Free all dma slots */
1222 for (i = 0; i < ch->numslots; i++) {
1223 struct ahci_slot *slot = &ch->slot[i];
1225 callout_drain(&slot->timeout);
1226 if (slot->dma.data_map) {
1227 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1228 slot->dma.data_map = NULL;
1234 ahci_phy_check_events(device_t dev, u_int32_t serr)
1236 struct ahci_channel *ch = device_get_softc(dev);
1238 if ((serr & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
1239 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1243 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
1244 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
1245 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) {
1246 device_printf(dev, "CONNECT requested\n");
1248 device_printf(dev, "DISCONNECT requested\n");
1251 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1253 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1254 cam_sim_path(ch->sim),
1255 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1264 ahci_notify_events(device_t dev, u_int32_t status)
1266 struct ahci_channel *ch = device_get_softc(dev);
1267 struct cam_path *dpath;
1270 if (ch->caps & AHCI_CAP_SSNTF)
1271 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1273 device_printf(dev, "SNTF 0x%04x\n", status);
1274 for (i = 0; i < 16; i++) {
1275 if ((status & (1 << i)) == 0)
1277 if (xpt_create_path(&dpath, NULL,
1278 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1279 xpt_async(AC_SCSI_AEN, dpath, NULL);
1280 xpt_free_path(dpath);
1286 ahci_ch_intr_locked(void *data)
1288 device_t dev = (device_t)data;
1289 struct ahci_channel *ch = device_get_softc(dev);
1293 mtx_unlock(&ch->mtx);
1297 ahci_ch_pm(void *arg)
1299 device_t dev = (device_t)arg;
1300 struct ahci_channel *ch = device_get_softc(dev);
1303 if (ch->numrslots != 0)
1305 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1306 if (ch->pm_level == 4)
1307 work |= AHCI_P_CMD_PARTIAL;
1309 work |= AHCI_P_CMD_SLUMBER;
1310 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1314 ahci_ch_intr(void *data)
1316 device_t dev = (device_t)data;
1317 struct ahci_channel *ch = device_get_softc(dev);
1318 uint32_t istatus, sstatus, cstatus, serr = 0, sntf = 0, ok, err;
1319 enum ahci_err_type et;
1322 /* Read and clear interrupt statuses. */
1323 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1326 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1327 /* Read command statuses. */
1328 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1329 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI);
1330 if (istatus & AHCI_P_IX_SDB) {
1331 if (ch->caps & AHCI_CAP_SSNTF)
1332 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1333 else if (ch->fbs_enabled) {
1334 u_int8_t *fis = ch->dma.rfis + 0x58;
1336 for (i = 0; i < 16; i++) {
1337 if (fis[1] & 0x80) {
1344 u_int8_t *fis = ch->dma.rfis + 0x58;
1347 sntf = (1 << (fis[1] & 0x0f));
1350 /* Process PHY events */
1351 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1352 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1353 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1355 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1356 ahci_phy_check_events(dev, serr);
1359 /* Process command errors */
1360 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1361 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1362 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1363 >> AHCI_P_CMD_CCS_SHIFT;
1364 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1365 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1366 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1368 if (ch->fbs_enabled) {
1369 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1370 if (fbs & AHCI_P_FBS_SDE) {
1371 port = (fbs & AHCI_P_FBS_DWE)
1372 >> AHCI_P_FBS_DWE_SHIFT;
1374 for (i = 0; i < 16; i++) {
1375 if (ch->numrslotspd[i] == 0)
1379 else if (port != i) {
1386 err = ch->rslots & (cstatus | sstatus);
1392 /* Complete all successfull commands. */
1393 ok = ch->rslots & ~(cstatus | sstatus);
1394 for (i = 0; i < ch->numslots; i++) {
1396 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1398 /* On error, complete the rest of commands with error statuses. */
1401 union ccb *fccb = ch->frozen;
1403 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1404 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1405 xpt_freeze_devq(fccb->ccb_h.path, 1);
1406 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1410 for (i = 0; i < ch->numslots; i++) {
1411 /* XXX: reqests in loading state. */
1412 if (((err >> i) & 1) == 0)
1415 ch->slot[i].ccb->ccb_h.target_id != port)
1417 if (istatus & AHCI_P_IX_TFE) {
1419 /* Task File Error */
1420 if (ch->numtslotspd[
1421 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1422 /* Untagged operation. */
1426 et = AHCI_ERR_INNOCENT;
1428 /* Tagged operation. */
1435 } else if (istatus & AHCI_P_IX_IF) {
1436 if (ch->numtslots == 0 && i != ccs && port != -2)
1437 et = AHCI_ERR_INNOCENT;
1441 et = AHCI_ERR_INVALID;
1442 ahci_end_transaction(&ch->slot[i], et);
1445 * We can't reinit port if there are some other
1446 * commands active, use resume to complete them.
1448 if (ch->rslots != 0)
1449 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1451 /* Process NOTIFY events */
1453 ahci_notify_events(dev, sntf);
1456 /* Must be called with channel locked. */
1458 ahci_check_collision(device_t dev, union ccb *ccb)
1460 struct ahci_channel *ch = device_get_softc(dev);
1461 int t = ccb->ccb_h.target_id;
1463 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1464 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1465 /* Tagged command while we have no supported tag free. */
1466 if (((~ch->oslots) & (0xffffffff >> (32 -
1467 ch->curr[t].tags))) == 0)
1469 /* If we have FBS */
1470 if (ch->fbs_enabled) {
1471 /* Tagged command while untagged are active. */
1472 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1475 /* Tagged command while untagged are active. */
1476 if (ch->numrslots != 0 && ch->numtslots == 0)
1478 /* Tagged command while tagged to other target is active. */
1479 if (ch->numtslots != 0 &&
1480 ch->taggedtarget != ccb->ccb_h.target_id)
1484 /* If we have FBS */
1485 if (ch->fbs_enabled) {
1486 /* Untagged command while tagged are active. */
1487 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1490 /* Untagged command while tagged are active. */
1491 if (ch->numrslots != 0 && ch->numtslots != 0)
1495 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1496 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1497 /* Atomic command while anything active. */
1498 if (ch->numrslots != 0)
1501 /* We have some atomic command running. */
1502 if (ch->aslots != 0)
1507 /* Must be called with channel locked. */
1509 ahci_begin_transaction(device_t dev, union ccb *ccb)
1511 struct ahci_channel *ch = device_get_softc(dev);
1512 struct ahci_slot *slot;
1515 /* Choose empty slot. */
1516 tags = ch->numslots;
1517 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1518 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1519 tags = ch->curr[ccb->ccb_h.target_id].tags;
1524 if (ch->slot[tag].state == AHCI_SLOT_EMPTY)
1529 /* Occupy chosen slot. */
1530 slot = &ch->slot[tag];
1532 /* Stop PM timer. */
1533 if (ch->numrslots == 0 && ch->pm_level > 3)
1534 callout_stop(&ch->pm_timer);
1535 /* Update channel stats. */
1536 ch->oslots |= (1 << slot->slot);
1538 ch->numrslotspd[ccb->ccb_h.target_id]++;
1539 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1540 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1542 ch->numtslotspd[ccb->ccb_h.target_id]++;
1543 ch->taggedtarget = ccb->ccb_h.target_id;
1545 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1546 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1547 ch->aslots |= (1 << slot->slot);
1548 slot->dma.nsegs = 0;
1549 /* If request moves data, setup and load SG list */
1550 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1554 slot->state = AHCI_SLOT_LOADING;
1555 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1556 buf = ccb->ataio.data_ptr;
1557 size = ccb->ataio.dxfer_len;
1559 buf = ccb->csio.data_ptr;
1560 size = ccb->csio.dxfer_len;
1562 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map,
1563 buf, size, ahci_dmasetprd, slot, 0);
1565 ahci_execute_transaction(slot);
1568 /* Locked by busdma engine. */
1570 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1572 struct ahci_slot *slot = arg;
1573 struct ahci_channel *ch = device_get_softc(slot->dev);
1574 struct ahci_cmd_tab *ctp;
1575 struct ahci_dma_prd *prd;
1579 device_printf(slot->dev, "DMA load error\n");
1580 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1583 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1584 /* Get a piece of the workspace for this request */
1585 ctp = (struct ahci_cmd_tab *)
1586 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1587 /* Fill S/G table */
1588 prd = &ctp->prd_tab[0];
1589 for (i = 0; i < nsegs; i++) {
1590 prd[i].dba = htole64(segs[i].ds_addr);
1591 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1593 slot->dma.nsegs = nsegs;
1594 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1595 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1596 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1597 ahci_execute_transaction(slot);
1600 /* Must be called with channel locked. */
1602 ahci_execute_transaction(struct ahci_slot *slot)
1604 device_t dev = slot->dev;
1605 struct ahci_channel *ch = device_get_softc(dev);
1606 struct ahci_cmd_tab *ctp;
1607 struct ahci_cmd_list *clp;
1608 union ccb *ccb = slot->ccb;
1609 int port = ccb->ccb_h.target_id & 0x0f;
1611 uint8_t *fis = ch->dma.rfis + 0x40;
1614 /* Get a piece of the workspace for this request */
1615 ctp = (struct ahci_cmd_tab *)
1616 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1617 /* Setup the FIS for this request */
1618 if (!(fis_size = ahci_setup_fis(dev, ctp, ccb, slot->slot))) {
1619 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1620 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1623 /* Setup the command list entry */
1624 clp = (struct ahci_cmd_list *)
1625 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1626 clp->cmd_flags = htole16(
1627 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1628 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1629 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1630 (fis_size / sizeof(u_int32_t)) |
1632 clp->prd_length = htole16(slot->dma.nsegs);
1633 /* Special handling for Soft Reset command. */
1634 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1635 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1636 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1637 /* Kick controller into sane state */
1641 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1643 /* Prepare FIS receive area for check. */
1644 for (i = 0; i < 20; i++)
1649 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1650 (AHCI_CT_SIZE * slot->slot));
1651 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1652 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1653 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1654 BUS_DMASYNC_PREREAD);
1655 /* Set ACTIVE bit for NCQ commands. */
1656 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1657 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1658 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1660 /* If FBS is enabled, set PMP port. */
1661 if (ch->fbs_enabled) {
1662 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1663 (port << AHCI_P_FBS_DEV_SHIFT));
1665 /* Issue command to the controller. */
1666 slot->state = AHCI_SLOT_RUNNING;
1667 ch->rslots |= (1 << slot->slot);
1668 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1669 /* Device reset commands doesn't interrupt. Poll them. */
1670 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1671 (ccb->ataio.cmd.command == ATA_DEVICE_RESET ||
1672 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) {
1673 int count, timeout = ccb->ccb_h.timeout;
1674 enum ahci_err_type et = AHCI_ERR_NONE;
1676 for (count = 0; count < timeout; count++) {
1678 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1680 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) {
1681 device_printf(ch->dev,
1682 "Poll error on slot %d, TFD: %04x\n",
1683 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1687 /* Workaround for ATI SB600/SB700 chipsets. */
1688 if (ccb->ccb_h.target_id == 15 &&
1689 pci_get_vendor(device_get_parent(dev)) == 0x1002 &&
1690 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1691 et = AHCI_ERR_TIMEOUT;
1695 if (timeout && (count >= timeout)) {
1696 device_printf(ch->dev,
1697 "Poll timeout on slot %d\n", slot->slot);
1698 device_printf(dev, "is %08x cs %08x ss %08x "
1699 "rs %08x tfd %02x serr %08x\n",
1700 ATA_INL(ch->r_mem, AHCI_P_IS),
1701 ATA_INL(ch->r_mem, AHCI_P_CI),
1702 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1703 ATA_INL(ch->r_mem, AHCI_P_TFD),
1704 ATA_INL(ch->r_mem, AHCI_P_SERR));
1705 et = AHCI_ERR_TIMEOUT;
1707 /* Marvell controllers do not wait for readyness. */
1708 if ((ch->quirks & AHCI_Q_NOBSYRES) &&
1709 (ccb->ccb_h.func_code == XPT_ATA_IO) &&
1710 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1711 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1712 while ((val = fis[2]) & (ATA_S_BUSY | ATA_S_DRQ)) {
1714 if (count++ >= timeout) {
1715 device_printf(dev, "device is not "
1716 "ready after soft-reset: "
1717 "tfd = %08x\n", val);
1718 et = AHCI_ERR_TIMEOUT;
1723 ahci_end_transaction(slot, et);
1724 /* Kick controller into sane state and enable FBS. */
1725 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1726 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1727 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1729 ahci_start(ch->dev, 1);
1733 /* Start command execution timeout */
1734 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 2000,
1735 (timeout_t*)ahci_timeout, slot);
1739 /* Must be called with channel locked. */
1741 ahci_process_timeout(device_t dev)
1743 struct ahci_channel *ch = device_get_softc(dev);
1746 mtx_assert(&ch->mtx, MA_OWNED);
1747 /* Handle the rest of commands. */
1748 for (i = 0; i < ch->numslots; i++) {
1749 /* Do we have a running request on slot? */
1750 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1752 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1756 /* Must be called with channel locked. */
1758 ahci_rearm_timeout(device_t dev)
1760 struct ahci_channel *ch = device_get_softc(dev);
1763 mtx_assert(&ch->mtx, MA_OWNED);
1764 for (i = 0; i < ch->numslots; i++) {
1765 struct ahci_slot *slot = &ch->slot[i];
1767 /* Do we have a running request on slot? */
1768 if (slot->state < AHCI_SLOT_RUNNING)
1770 if ((ch->toslots & (1 << i)) == 0)
1772 callout_reset(&slot->timeout,
1773 (int)slot->ccb->ccb_h.timeout * hz / 2000,
1774 (timeout_t*)ahci_timeout, slot);
1778 /* Locked by callout mechanism. */
1780 ahci_timeout(struct ahci_slot *slot)
1782 device_t dev = slot->dev;
1783 struct ahci_channel *ch = device_get_softc(dev);
1788 /* Check for stale timeout. */
1789 if (slot->state < AHCI_SLOT_RUNNING)
1792 /* Check if slot was not being executed last time we checked. */
1793 if (slot->state < AHCI_SLOT_EXECUTING) {
1794 /* Check if slot started executing. */
1795 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1796 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1797 >> AHCI_P_CMD_CCS_SHIFT;
1798 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1800 slot->state = AHCI_SLOT_EXECUTING;
1802 callout_reset(&slot->timeout,
1803 (int)slot->ccb->ccb_h.timeout * hz / 2000,
1804 (timeout_t*)ahci_timeout, slot);
1808 device_printf(dev, "Timeout on slot %d\n", slot->slot);
1809 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n",
1810 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1811 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1812 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR));
1814 /* Handle frozen command. */
1816 union ccb *fccb = ch->frozen;
1818 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1819 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1820 xpt_freeze_devq(fccb->ccb_h.path, 1);
1821 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1825 if (!ch->fbs_enabled) {
1826 /* Without FBS we know real timeout source. */
1828 /* Handle command with timeout. */
1829 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1830 /* Handle the rest of commands. */
1831 for (i = 0; i < ch->numslots; i++) {
1832 /* Do we have a running request on slot? */
1833 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1835 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1838 /* With FBS we wait for other commands timeout and pray. */
1839 if (ch->toslots == 0)
1840 xpt_freeze_simq(ch->sim, 1);
1841 ch->toslots |= (1 << slot->slot);
1842 if ((ch->rslots & ~ch->toslots) == 0)
1843 ahci_process_timeout(dev);
1845 device_printf(dev, " ... waiting for slots %08x\n",
1846 ch->rslots & ~ch->toslots);
1850 /* Must be called with channel locked. */
1852 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1854 device_t dev = slot->dev;
1855 struct ahci_channel *ch = device_get_softc(dev);
1856 union ccb *ccb = slot->ccb;
1857 struct ahci_cmd_list *clp;
1860 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1861 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1862 clp = (struct ahci_cmd_list *)
1863 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1864 /* Read result registers to the result struct
1865 * May be incorrect if several commands finished same time,
1866 * so read only when sure or have to.
1868 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1869 struct ata_res *res = &ccb->ataio.res;
1871 if ((et == AHCI_ERR_TFE) ||
1872 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1873 u_int8_t *fis = ch->dma.rfis + 0x40;
1875 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1876 BUS_DMASYNC_POSTREAD);
1877 if (ch->fbs_enabled) {
1878 fis += ccb->ccb_h.target_id * 256;
1879 res->status = fis[2];
1880 res->error = fis[3];
1882 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1885 res->error = tfd >> 8;
1887 res->lba_low = fis[4];
1888 res->lba_mid = fis[5];
1889 res->lba_high = fis[6];
1890 res->device = fis[7];
1891 res->lba_low_exp = fis[8];
1892 res->lba_mid_exp = fis[9];
1893 res->lba_high_exp = fis[10];
1894 res->sector_count = fis[12];
1895 res->sector_count_exp = fis[13];
1897 bzero(res, sizeof(*res));
1898 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
1899 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1901 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
1904 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1906 ccb->csio.dxfer_len - le32toh(clp->bytecount);
1909 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1910 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1911 (ccb->ccb_h.flags & CAM_DIR_IN) ?
1912 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1913 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1915 if (et != AHCI_ERR_NONE)
1916 ch->eslots |= (1 << slot->slot);
1917 /* In case of error, freeze device for proper recovery. */
1918 if ((et != AHCI_ERR_NONE) && (!ch->readlog) &&
1919 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1920 xpt_freeze_devq(ccb->ccb_h.path, 1);
1921 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1923 /* Set proper result status. */
1924 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1927 ccb->ccb_h.status |= CAM_REQ_CMP;
1928 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1929 ccb->csio.scsi_status = SCSI_STATUS_OK;
1931 case AHCI_ERR_INVALID:
1933 ccb->ccb_h.status |= CAM_REQ_INVALID;
1935 case AHCI_ERR_INNOCENT:
1936 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1940 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1941 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1942 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1944 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1950 xpt_freeze_simq(ch->sim, 1);
1951 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1952 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1954 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1956 case AHCI_ERR_TIMEOUT:
1958 xpt_freeze_simq(ch->sim, 1);
1959 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1960 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1962 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1966 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1969 ch->oslots &= ~(1 << slot->slot);
1970 ch->rslots &= ~(1 << slot->slot);
1971 ch->aslots &= ~(1 << slot->slot);
1972 slot->state = AHCI_SLOT_EMPTY;
1974 /* Update channel stats. */
1976 ch->numrslotspd[ccb->ccb_h.target_id]--;
1977 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1978 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1980 ch->numtslotspd[ccb->ccb_h.target_id]--;
1982 /* Cancel timeout state if request completed normally. */
1983 if (et != AHCI_ERR_TIMEOUT) {
1984 lastto = (ch->toslots == (1 << slot->slot));
1985 ch->toslots &= ~(1 << slot->slot);
1987 xpt_release_simq(ch->sim, TRUE);
1989 /* If it was first request of reset sequence and there is no error,
1990 * proceed to second request. */
1991 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1992 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1993 (ccb->ataio.cmd.control & ATA_A_RESET) &&
1994 et == AHCI_ERR_NONE) {
1995 ccb->ataio.cmd.control &= ~ATA_A_RESET;
1996 ahci_begin_transaction(dev, ccb);
1999 /* If it was our READ LOG command - process it. */
2001 ahci_process_read_log(dev, ccb);
2002 /* If it was NCQ command error, put result on hold. */
2003 } else if (et == AHCI_ERR_NCQ) {
2004 ch->hold[slot->slot] = ccb;
2008 /* Unfreeze frozen command. */
2009 if (ch->frozen && !ahci_check_collision(dev, ch->frozen)) {
2010 union ccb *fccb = ch->frozen;
2012 ahci_begin_transaction(dev, fccb);
2013 xpt_release_simq(ch->sim, TRUE);
2015 /* If we have no other active commands, ... */
2016 if (ch->rslots == 0) {
2017 /* if there was fatal error - reset port. */
2018 if (ch->toslots != 0 || ch->fatalerr) {
2021 /* if we have slots in error, we can reinit port. */
2022 if (ch->eslots != 0) {
2026 /* if there commands on hold, we can do READ LOG. */
2027 if (!ch->readlog && ch->numhslots)
2028 ahci_issue_read_log(dev);
2030 /* If all the rest of commands are in timeout - give them chance. */
2031 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2032 et != AHCI_ERR_TIMEOUT)
2033 ahci_rearm_timeout(dev);
2034 /* Start PM timer. */
2035 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2036 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2037 callout_schedule(&ch->pm_timer,
2038 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2043 ahci_issue_read_log(device_t dev)
2045 struct ahci_channel *ch = device_get_softc(dev);
2047 struct ccb_ataio *ataio;
2051 /* Find some holden command. */
2052 for (i = 0; i < ch->numslots; i++) {
2056 ccb = xpt_alloc_ccb_nowait();
2058 device_printf(dev, "Unable allocate READ LOG command");
2061 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2062 ccb->ccb_h.func_code = XPT_ATA_IO;
2063 ccb->ccb_h.flags = CAM_DIR_IN;
2064 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2065 ataio = &ccb->ataio;
2066 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2067 if (ataio->data_ptr == NULL) {
2069 device_printf(dev, "Unable allocate memory for READ LOG command");
2072 ataio->dxfer_len = 512;
2073 bzero(&ataio->cmd, sizeof(ataio->cmd));
2074 ataio->cmd.flags = CAM_ATAIO_48BIT;
2075 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2076 ataio->cmd.sector_count = 1;
2077 ataio->cmd.sector_count_exp = 0;
2078 ataio->cmd.lba_low = 0x10;
2079 ataio->cmd.lba_mid = 0;
2080 ataio->cmd.lba_mid_exp = 0;
2081 /* Freeze SIM while doing READ LOG EXT. */
2082 xpt_freeze_simq(ch->sim, 1);
2083 ahci_begin_transaction(dev, ccb);
2087 ahci_process_read_log(device_t dev, union ccb *ccb)
2089 struct ahci_channel *ch = device_get_softc(dev);
2091 struct ata_res *res;
2096 data = ccb->ataio.data_ptr;
2097 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2098 (data[0] & 0x80) == 0) {
2099 for (i = 0; i < ch->numslots; i++) {
2102 if ((data[0] & 0x1F) == i) {
2103 res = &ch->hold[i]->ataio.res;
2104 res->status = data[2];
2105 res->error = data[3];
2106 res->lba_low = data[4];
2107 res->lba_mid = data[5];
2108 res->lba_high = data[6];
2109 res->device = data[7];
2110 res->lba_low_exp = data[8];
2111 res->lba_mid_exp = data[9];
2112 res->lba_high_exp = data[10];
2113 res->sector_count = data[12];
2114 res->sector_count_exp = data[13];
2116 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2117 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2119 xpt_done(ch->hold[i]);
2124 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2125 device_printf(dev, "Error while READ LOG EXT\n");
2126 else if ((data[0] & 0x80) == 0) {
2127 device_printf(dev, "Non-queued command error in READ LOG EXT\n");
2129 for (i = 0; i < ch->numslots; i++) {
2132 xpt_done(ch->hold[i]);
2137 free(ccb->ataio.data_ptr, M_AHCI);
2139 xpt_release_simq(ch->sim, TRUE);
2143 ahci_start(device_t dev, int fbs)
2145 struct ahci_channel *ch = device_get_softc(dev);
2148 /* Clear SATA error register */
2149 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2150 /* Clear any interrupts pending on this channel */
2151 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2152 /* Configure FIS-based switching if supported. */
2153 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2154 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2155 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2156 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2158 /* Start operations on this channel */
2159 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2160 cmd &= ~AHCI_P_CMD_PMA;
2161 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2162 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2166 ahci_stop(device_t dev)
2168 struct ahci_channel *ch = device_get_softc(dev);
2172 /* Kill all activity on this channel */
2173 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2174 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2175 /* Wait for activity stop. */
2179 if (timeout++ > 1000) {
2180 device_printf(dev, "stopping AHCI engine failed\n");
2183 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2188 ahci_clo(device_t dev)
2190 struct ahci_channel *ch = device_get_softc(dev);
2194 /* Issue Command List Override if supported */
2195 if (ch->caps & AHCI_CAP_SCLO) {
2196 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2197 cmd |= AHCI_P_CMD_CLO;
2198 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2202 if (timeout++ > 1000) {
2203 device_printf(dev, "executing CLO failed\n");
2206 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2211 ahci_stop_fr(device_t dev)
2213 struct ahci_channel *ch = device_get_softc(dev);
2217 /* Kill all FIS reception on this channel */
2218 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2219 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2220 /* Wait for FIS reception stop. */
2224 if (timeout++ > 1000) {
2225 device_printf(dev, "stopping AHCI FR engine failed\n");
2228 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2232 ahci_start_fr(device_t dev)
2234 struct ahci_channel *ch = device_get_softc(dev);
2237 /* Start FIS reception on this channel */
2238 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2239 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2243 ahci_wait_ready(device_t dev, int t)
2245 struct ahci_channel *ch = device_get_softc(dev);
2249 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2250 (ATA_S_BUSY | ATA_S_DRQ)) {
2252 if (timeout++ > t) {
2253 device_printf(dev, "device is not ready (timeout %dms) "
2254 "tfd = %08x\n", t, val);
2259 device_printf(dev, "ready wait time=%dms\n", timeout);
2264 ahci_reset(device_t dev)
2266 struct ahci_channel *ch = device_get_softc(dev);
2267 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
2270 xpt_freeze_simq(ch->sim, 1);
2272 device_printf(dev, "AHCI reset...\n");
2273 /* Requeue freezed command. */
2275 union ccb *fccb = ch->frozen;
2277 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2278 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2279 xpt_freeze_devq(fccb->ccb_h.path, 1);
2280 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2284 /* Kill the engine and requeue all running commands. */
2286 for (i = 0; i < ch->numslots; i++) {
2287 /* Do we have a running request on slot? */
2288 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2290 /* XXX; Commands in loading state. */
2291 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2293 for (i = 0; i < ch->numslots; i++) {
2296 xpt_done(ch->hold[i]);
2300 if (ch->toslots != 0)
2301 xpt_release_simq(ch->sim, TRUE);
2305 /* Tell the XPT about the event */
2306 xpt_async(AC_BUS_RESET, ch->path, NULL);
2307 /* Disable port interrupts */
2308 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2309 /* Reset and reconnect PHY, */
2310 if (!ahci_sata_phy_reset(dev)) {
2313 "AHCI reset done: phy reset found no device\n");
2315 /* Enable wanted port interrupts */
2316 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2317 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC));
2318 xpt_release_simq(ch->sim, TRUE);
2321 /* Wait for clearing busy status. */
2322 if (ahci_wait_ready(dev, 15000))
2326 /* Enable wanted port interrupts */
2327 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2328 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2329 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2330 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) |
2331 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2332 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2334 device_printf(dev, "AHCI reset done: device found\n");
2335 xpt_release_simq(ch->sim, TRUE);
2339 ahci_setup_fis(device_t dev, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2341 struct ahci_channel *ch = device_get_softc(dev);
2342 u_int8_t *fis = &ctp->cfis[0];
2344 bzero(ctp->cfis, 64);
2345 fis[0] = 0x27; /* host to device */
2346 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2347 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2349 fis[2] = ATA_PACKET_CMD;
2350 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2351 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2354 fis[5] = ccb->csio.dxfer_len;
2355 fis[6] = ccb->csio.dxfer_len >> 8;
2358 fis[15] = ATA_A_4BIT;
2359 bzero(ctp->acmd, 32);
2360 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2361 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2362 ctp->acmd, ccb->csio.cdb_len);
2363 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2365 fis[2] = ccb->ataio.cmd.command;
2366 fis[3] = ccb->ataio.cmd.features;
2367 fis[4] = ccb->ataio.cmd.lba_low;
2368 fis[5] = ccb->ataio.cmd.lba_mid;
2369 fis[6] = ccb->ataio.cmd.lba_high;
2370 fis[7] = ccb->ataio.cmd.device;
2371 fis[8] = ccb->ataio.cmd.lba_low_exp;
2372 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2373 fis[10] = ccb->ataio.cmd.lba_high_exp;
2374 fis[11] = ccb->ataio.cmd.features_exp;
2375 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2379 fis[12] = ccb->ataio.cmd.sector_count;
2380 fis[13] = ccb->ataio.cmd.sector_count_exp;
2382 fis[15] = ATA_A_4BIT;
2384 fis[15] = ccb->ataio.cmd.control;
2390 ahci_sata_connect(struct ahci_channel *ch)
2395 /* Wait up to 100ms for "connect well" */
2396 for (timeout = 0; timeout < 100 ; timeout++) {
2397 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2398 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2399 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2400 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2402 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2404 device_printf(ch->dev, "SATA offline status=%08x\n",
2411 if (timeout >= 100) {
2413 device_printf(ch->dev, "SATA connect timeout status=%08x\n",
2419 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n",
2422 /* Clear SATA error register */
2423 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2428 ahci_sata_phy_reset(device_t dev)
2430 struct ahci_channel *ch = device_get_softc(dev);
2434 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2436 val = ATA_SC_SPD_SPEED_GEN1;
2437 else if (sata_rev == 2)
2438 val = ATA_SC_SPD_SPEED_GEN2;
2439 else if (sata_rev == 3)
2440 val = ATA_SC_SPD_SPEED_GEN3;
2443 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2444 ATA_SC_DET_RESET | val |
2445 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2447 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2448 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2449 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2451 if (!ahci_sata_connect(ch)) {
2452 if (ch->pm_level > 0)
2453 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2460 ahci_check_ids(device_t dev, union ccb *ccb)
2462 struct ahci_channel *ch = device_get_softc(dev);
2464 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2465 ccb->ccb_h.status = CAM_TID_INVALID;
2469 if (ccb->ccb_h.target_lun != 0) {
2470 ccb->ccb_h.status = CAM_LUN_INVALID;
2478 ahciaction(struct cam_sim *sim, union ccb *ccb)
2481 struct ahci_channel *ch;
2483 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2484 ccb->ccb_h.func_code));
2486 ch = (struct ahci_channel *)cam_sim_softc(sim);
2488 switch (ccb->ccb_h.func_code) {
2489 /* Common cases first */
2490 case XPT_ATA_IO: /* Execute the requested I/O operation */
2492 if (ahci_check_ids(dev, ccb))
2494 if (ch->devices == 0 ||
2495 (ch->pm_present == 0 &&
2496 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2497 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2500 /* Check for command collision. */
2501 if (ahci_check_collision(dev, ccb)) {
2502 /* Freeze command. */
2504 /* We have only one frozen slot, so freeze simq also. */
2505 xpt_freeze_simq(ch->sim, 1);
2508 ahci_begin_transaction(dev, ccb);
2510 case XPT_EN_LUN: /* Enable LUN as a target */
2511 case XPT_TARGET_IO: /* Execute target I/O request */
2512 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
2513 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
2514 case XPT_ABORT: /* Abort the specified CCB */
2516 ccb->ccb_h.status = CAM_REQ_INVALID;
2518 case XPT_SET_TRAN_SETTINGS:
2520 struct ccb_trans_settings *cts = &ccb->cts;
2521 struct ahci_device *d;
2523 if (ahci_check_ids(dev, ccb))
2525 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2526 d = &ch->curr[ccb->ccb_h.target_id];
2528 d = &ch->user[ccb->ccb_h.target_id];
2529 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2530 d->revision = cts->xport_specific.sata.revision;
2531 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2532 d->mode = cts->xport_specific.sata.mode;
2533 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2534 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2535 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2536 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2537 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2538 ch->pm_present = cts->xport_specific.sata.pm_present;
2539 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2540 d->atapi = cts->xport_specific.sata.atapi;
2541 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2542 d->caps = cts->xport_specific.sata.caps;
2543 ccb->ccb_h.status = CAM_REQ_CMP;
2546 case XPT_GET_TRAN_SETTINGS:
2547 /* Get default/user set transfer settings for the target */
2549 struct ccb_trans_settings *cts = &ccb->cts;
2550 struct ahci_device *d;
2553 if (ahci_check_ids(dev, ccb))
2555 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2556 d = &ch->curr[ccb->ccb_h.target_id];
2558 d = &ch->user[ccb->ccb_h.target_id];
2559 cts->protocol = PROTO_ATA;
2560 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2561 cts->transport = XPORT_SATA;
2562 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2563 cts->proto_specific.valid = 0;
2564 cts->xport_specific.sata.valid = 0;
2565 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2566 (ccb->ccb_h.target_id == 15 ||
2567 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2568 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2569 if (status & 0x0f0) {
2570 cts->xport_specific.sata.revision =
2571 (status & 0x0f0) >> 4;
2572 cts->xport_specific.sata.valid |=
2573 CTS_SATA_VALID_REVISION;
2575 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2577 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2578 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2579 if (ch->caps2 & AHCI_CAP2_APST)
2580 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2582 if ((ch->caps & AHCI_CAP_SNCQ) &&
2583 (ch->quirks & AHCI_Q_NOAA) == 0)
2584 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2585 cts->xport_specific.sata.caps &=
2586 ch->user[ccb->ccb_h.target_id].caps;
2587 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2589 cts->xport_specific.sata.revision = d->revision;
2590 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2591 cts->xport_specific.sata.caps = d->caps;
2592 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2594 cts->xport_specific.sata.mode = d->mode;
2595 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2596 cts->xport_specific.sata.bytecount = d->bytecount;
2597 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2598 cts->xport_specific.sata.pm_present = ch->pm_present;
2599 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2600 cts->xport_specific.sata.tags = d->tags;
2601 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2602 cts->xport_specific.sata.atapi = d->atapi;
2603 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2604 ccb->ccb_h.status = CAM_REQ_CMP;
2607 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2608 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2610 ccb->ccb_h.status = CAM_REQ_CMP;
2612 case XPT_TERM_IO: /* Terminate the I/O process */
2614 ccb->ccb_h.status = CAM_REQ_INVALID;
2616 case XPT_PATH_INQ: /* Path routing inquiry */
2618 struct ccb_pathinq *cpi = &ccb->cpi;
2620 cpi->version_num = 1; /* XXX??? */
2621 cpi->hba_inquiry = PI_SDTR_ABLE;
2622 if (ch->caps & AHCI_CAP_SNCQ)
2623 cpi->hba_inquiry |= PI_TAG_ABLE;
2624 if (ch->caps & AHCI_CAP_SPM)
2625 cpi->hba_inquiry |= PI_SATAPM;
2626 cpi->target_sprt = 0;
2627 cpi->hba_misc = PIM_SEQSCAN;
2628 cpi->hba_eng_cnt = 0;
2629 if (ch->caps & AHCI_CAP_SPM)
2630 cpi->max_target = 15;
2632 cpi->max_target = 0;
2634 cpi->initiator_id = 0;
2635 cpi->bus_id = cam_sim_bus(sim);
2636 cpi->base_transfer_speed = 150000;
2637 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2638 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2639 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2640 cpi->unit_number = cam_sim_unit(sim);
2641 cpi->transport = XPORT_SATA;
2642 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2643 cpi->protocol = PROTO_ATA;
2644 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2645 cpi->maxio = MAXPHYS;
2646 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2647 if (pci_get_devid(device_get_parent(dev)) == 0x43801002)
2648 cpi->maxio = min(cpi->maxio, 128 * 512);
2649 cpi->ccb_h.status = CAM_REQ_CMP;
2653 ccb->ccb_h.status = CAM_REQ_INVALID;
2660 ahcipoll(struct cam_sim *sim)
2662 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2664 ahci_ch_intr(ch->dev);