2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/sysctl.h>
48 #include <sys/malloc.h>
50 #include <sys/mutex.h>
51 #include <sys/kernel.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/errno.h>
55 #include <sys/callout.h>
57 #include <sys/endian.h>
58 #include <sys/kthread.h>
59 #include <sys/taskqueue.h>
62 #include <machine/bus.h>
65 #include <net/if_dl.h>
66 #include <net/if_media.h>
67 #include <net/if_types.h>
68 #include <net/if_arp.h>
69 #include <net/ethernet.h>
70 #include <net/if_llc.h>
72 #include <net80211/ieee80211_var.h>
73 #include <net80211/ieee80211_regdomain.h>
74 #ifdef IEEE80211_SUPPORT_SUPERG
75 #include <net80211/ieee80211_superg.h>
77 #ifdef IEEE80211_SUPPORT_TDMA
78 #include <net80211/ieee80211_tdma.h>
84 #include <netinet/in.h>
85 #include <netinet/if_ether.h>
88 #include <dev/ath/if_athvar.h>
89 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
92 #include <dev/ath/ath_tx99/ath_tx99.h>
96 * ATH_BCBUF determines the number of vap's that can transmit
97 * beacons and also (currently) the number of vap's that can
98 * have unique mac addresses/bssid. When staggering beacons
99 * 4 is probably a good max as otherwise the beacons become
100 * very closely spaced and there is limited time for cab q traffic
101 * to go out. You can burst beacons instead but that is not good
102 * for stations in power save and at some point you really want
103 * another radio (and channel).
105 * The limit on the number of mac addresses is tied to our use of
106 * the U/L bit and tracking addresses in a byte; it would be
107 * worthwhile to allow more for applications like proxy sta.
109 CTASSERT(ATH_BCBUF <= 8);
111 /* unaligned little endian access */
112 #define LE_READ_2(p) \
114 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
115 #define LE_READ_4(p) \
117 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
118 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
120 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
121 const char name[IFNAMSIZ], int unit, int opmode,
122 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
123 const uint8_t mac[IEEE80211_ADDR_LEN]);
124 static void ath_vap_delete(struct ieee80211vap *);
125 static void ath_init(void *);
126 static void ath_stop_locked(struct ifnet *);
127 static void ath_stop(struct ifnet *);
128 static void ath_start(struct ifnet *);
129 static int ath_reset(struct ifnet *);
130 static int ath_reset_vap(struct ieee80211vap *, u_long);
131 static int ath_media_change(struct ifnet *);
132 static void ath_watchdog(void *);
133 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
134 static void ath_fatal_proc(void *, int);
135 static void ath_bmiss_vap(struct ieee80211vap *);
136 static void ath_bmiss_proc(void *, int);
137 static int ath_keyset(struct ath_softc *, const struct ieee80211_key *,
138 struct ieee80211_node *);
139 static int ath_key_alloc(struct ieee80211vap *,
140 struct ieee80211_key *,
141 ieee80211_keyix *, ieee80211_keyix *);
142 static int ath_key_delete(struct ieee80211vap *,
143 const struct ieee80211_key *);
144 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *,
145 const u_int8_t mac[IEEE80211_ADDR_LEN]);
146 static void ath_key_update_begin(struct ieee80211vap *);
147 static void ath_key_update_end(struct ieee80211vap *);
148 static void ath_update_mcast(struct ifnet *);
149 static void ath_update_promisc(struct ifnet *);
150 static void ath_mode_init(struct ath_softc *);
151 static void ath_setslottime(struct ath_softc *);
152 static void ath_updateslot(struct ifnet *);
153 static int ath_beaconq_setup(struct ath_hal *);
154 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
155 static void ath_beacon_update(struct ieee80211vap *, int item);
156 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
157 static void ath_beacon_proc(void *, int);
158 static struct ath_buf *ath_beacon_generate(struct ath_softc *,
159 struct ieee80211vap *);
160 static void ath_bstuck_proc(void *, int);
161 static void ath_beacon_return(struct ath_softc *, struct ath_buf *);
162 static void ath_beacon_free(struct ath_softc *);
163 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *);
164 static void ath_descdma_cleanup(struct ath_softc *sc,
165 struct ath_descdma *, ath_bufhead *);
166 static int ath_desc_alloc(struct ath_softc *);
167 static void ath_desc_free(struct ath_softc *);
168 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
169 const uint8_t [IEEE80211_ADDR_LEN]);
170 static void ath_node_free(struct ieee80211_node *);
171 static void ath_node_getsignal(const struct ieee80211_node *,
173 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
174 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
175 int subtype, int rssi, int nf);
176 static void ath_setdefantenna(struct ath_softc *, u_int);
177 static void ath_rx_proc(void *, int);
178 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
179 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
180 static int ath_tx_setup(struct ath_softc *, int, int);
181 static int ath_wme_update(struct ieee80211com *);
182 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
183 static void ath_tx_cleanup(struct ath_softc *);
184 static void ath_freetx(struct mbuf *);
185 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
186 struct ath_buf *, struct mbuf *);
187 static void ath_tx_proc_q0(void *, int);
188 static void ath_tx_proc_q0123(void *, int);
189 static void ath_tx_proc(void *, int);
190 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *);
191 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
192 static void ath_draintxq(struct ath_softc *);
193 static void ath_stoprecv(struct ath_softc *);
194 static int ath_startrecv(struct ath_softc *);
195 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
196 static void ath_scan_start(struct ieee80211com *);
197 static void ath_scan_end(struct ieee80211com *);
198 static void ath_set_channel(struct ieee80211com *);
199 static void ath_calibrate(void *);
200 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
201 static void ath_setup_stationkey(struct ieee80211_node *);
202 static void ath_newassoc(struct ieee80211_node *, int);
203 static int ath_setregdomain(struct ieee80211com *,
204 struct ieee80211_regdomain *, int,
205 struct ieee80211_channel []);
206 static void ath_getradiocaps(struct ieee80211com *, int, int *,
207 struct ieee80211_channel []);
208 static int ath_getchannels(struct ath_softc *);
209 static void ath_led_event(struct ath_softc *, int);
211 static int ath_rate_setup(struct ath_softc *, u_int mode);
212 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
214 static void ath_sysctlattach(struct ath_softc *);
215 static int ath_raw_xmit(struct ieee80211_node *,
216 struct mbuf *, const struct ieee80211_bpf_params *);
217 static void ath_announce(struct ath_softc *);
219 #ifdef IEEE80211_SUPPORT_TDMA
220 static void ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt,
222 static void ath_tdma_bintvalsetup(struct ath_softc *sc,
223 const struct ieee80211_tdma_state *tdma);
224 static void ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap);
225 static void ath_tdma_update(struct ieee80211_node *ni,
226 const struct ieee80211_tdma_param *tdma, int);
227 static void ath_tdma_beacon_send(struct ath_softc *sc,
228 struct ieee80211vap *vap);
231 ath_hal_setcca(struct ath_hal *ah, int ena)
234 * NB: fill me in; this is not provided by default because disabling
235 * CCA in most locales violates regulatory.
240 ath_hal_getcca(struct ath_hal *ah)
243 if (ath_hal_getcapability(ah, HAL_CAP_DIAG, 0, &diag) != HAL_OK)
245 return ((diag & 0x500000) == 0);
248 #define TDMA_EP_MULTIPLIER (1<<10) /* pow2 to optimize out * and / */
249 #define TDMA_LPF_LEN 6
250 #define TDMA_DUMMY_MARKER 0x127
251 #define TDMA_EP_MUL(x, mul) ((x) * (mul))
252 #define TDMA_IN(x) (TDMA_EP_MUL((x), TDMA_EP_MULTIPLIER))
253 #define TDMA_LPF(x, y, len) \
254 ((x != TDMA_DUMMY_MARKER) ? (((x) * ((len)-1) + (y)) / (len)) : (y))
255 #define TDMA_SAMPLE(x, y) do { \
256 x = TDMA_LPF((x), TDMA_IN(y), TDMA_LPF_LEN); \
258 #define TDMA_EP_RND(x,mul) \
259 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
260 #define TDMA_AVG(x) TDMA_EP_RND(x, TDMA_EP_MULTIPLIER)
261 #endif /* IEEE80211_SUPPORT_TDMA */
263 SYSCTL_DECL(_hw_ath);
265 /* XXX validate sysctl values */
266 static int ath_longcalinterval = 30; /* long cals every 30 secs */
267 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
268 0, "long chip calibration interval (secs)");
269 static int ath_shortcalinterval = 100; /* short cals every 100 ms */
270 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
271 0, "short chip calibration interval (msecs)");
272 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
273 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
274 0, "reset chip calibration results (secs)");
276 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
277 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf,
278 0, "rx buffers allocated");
279 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
280 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
281 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf,
282 0, "tx buffers allocated");
283 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
285 static int ath_bstuck_threshold = 4; /* max missed beacons */
286 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
287 0, "max missed beacon xmits before chip reset");
291 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
292 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
293 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
294 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
295 ATH_DEBUG_RATE = 0x00000010, /* rate control */
296 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
297 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
298 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
299 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
300 ATH_DEBUG_INTR = 0x00001000, /* ISR */
301 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
302 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
303 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
304 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
305 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
306 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
307 ATH_DEBUG_NODE = 0x00080000, /* node management */
308 ATH_DEBUG_LED = 0x00100000, /* led management */
309 ATH_DEBUG_FF = 0x00200000, /* fast frames */
310 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */
311 ATH_DEBUG_TDMA = 0x00800000, /* TDMA processing */
312 ATH_DEBUG_TDMA_TIMER = 0x01000000, /* TDMA timer processing */
313 ATH_DEBUG_REGDOMAIN = 0x02000000, /* regulatory processing */
314 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
315 ATH_DEBUG_ANY = 0xffffffff
317 static int ath_debug = 0;
318 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
319 0, "control debugging printfs");
320 TUNABLE_INT("hw.ath.debug", &ath_debug);
322 #define IFF_DUMPPKTS(sc, m) \
323 ((sc->sc_debug & (m)) || \
324 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
325 #define DPRINTF(sc, m, fmt, ...) do { \
326 if (sc->sc_debug & (m)) \
327 printf(fmt, __VA_ARGS__); \
329 #define KEYPRINTF(sc, ix, hk, mac) do { \
330 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
331 ath_keyprint(sc, __func__, ix, hk, mac); \
333 static void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf,
335 static void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf,
336 u_int qnum, u_int ix, int done);
338 #define IFF_DUMPPKTS(sc, m) \
339 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
340 #define DPRINTF(sc, m, fmt, ...) do { \
343 #define KEYPRINTF(sc, k, ix, mac) do { \
348 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
351 ath_attach(u_int16_t devid, struct ath_softc *sc)
354 struct ieee80211com *ic;
355 struct ath_hal *ah = NULL;
359 uint8_t macaddr[IEEE80211_ADDR_LEN];
361 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
363 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
365 device_printf(sc->sc_dev, "can not if_alloc()\n");
371 /* set these up early for if_printf use */
372 if_initname(ifp, device_get_name(sc->sc_dev),
373 device_get_unit(sc->sc_dev));
375 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
377 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
383 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
385 sc->sc_debug = ath_debug;
389 * Check if the MAC has multi-rate retry support.
390 * We do this by trying to setup a fake extended
391 * descriptor. MAC's that don't have support will
392 * return false w/o doing anything. MAC's that do
393 * support it will return true w/o doing anything.
395 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
398 * Check if the device has hardware counters for PHY
399 * errors. If so we need to enable the MIB interrupt
400 * so we can act on stat triggers.
402 if (ath_hal_hwphycounters(ah))
406 * Get the hardware key cache size.
408 sc->sc_keymax = ath_hal_keycachesize(ah);
409 if (sc->sc_keymax > ATH_KEYMAX) {
410 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
411 ATH_KEYMAX, sc->sc_keymax);
412 sc->sc_keymax = ATH_KEYMAX;
415 * Reset the key cache since some parts do not
416 * reset the contents on initial power up.
418 for (i = 0; i < sc->sc_keymax; i++)
419 ath_hal_keyreset(ah, i);
422 * Collect the default channel list.
424 error = ath_getchannels(sc);
429 * Setup rate tables for all potential media types.
431 ath_rate_setup(sc, IEEE80211_MODE_11A);
432 ath_rate_setup(sc, IEEE80211_MODE_11B);
433 ath_rate_setup(sc, IEEE80211_MODE_11G);
434 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
435 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
436 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
437 ath_rate_setup(sc, IEEE80211_MODE_11NA);
438 ath_rate_setup(sc, IEEE80211_MODE_11NG);
439 ath_rate_setup(sc, IEEE80211_MODE_HALF);
440 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
442 /* NB: setup here so ath_rate_update is happy */
443 ath_setcurmode(sc, IEEE80211_MODE_11A);
446 * Allocate tx+rx descriptors and populate the lists.
448 error = ath_desc_alloc(sc);
450 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
453 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
454 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
456 ATH_TXBUF_LOCK_INIT(sc);
458 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
459 taskqueue_thread_enqueue, &sc->sc_tq);
460 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
461 "%s taskq", ifp->if_xname);
463 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc);
464 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
465 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
468 * Allocate hardware transmit queues: one queue for
469 * beacon frames and one data queue for each QoS
470 * priority. Note that the hal handles reseting
471 * these queues at the needed time.
475 sc->sc_bhalq = ath_beaconq_setup(ah);
476 if (sc->sc_bhalq == (u_int) -1) {
477 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
481 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
482 if (sc->sc_cabq == NULL) {
483 if_printf(ifp, "unable to setup CAB xmit queue!\n");
487 /* NB: insure BK queue is the lowest priority h/w queue */
488 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
489 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
490 ieee80211_wme_acnames[WME_AC_BK]);
494 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
495 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
496 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
498 * Not enough hardware tx queues to properly do WME;
499 * just punt and assign them all to the same h/w queue.
500 * We could do a better job of this if, for example,
501 * we allocate queues when we switch from station to
504 if (sc->sc_ac2q[WME_AC_VI] != NULL)
505 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
506 if (sc->sc_ac2q[WME_AC_BE] != NULL)
507 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
508 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
509 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
510 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
514 * Special case certain configurations. Note the
515 * CAB queue is handled by these specially so don't
516 * include them when checking the txq setup mask.
518 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
520 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
523 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
526 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
531 * Setup rate control. Some rate control modules
532 * call back to change the anntena state so expose
533 * the necessary entry points.
534 * XXX maybe belongs in struct ath_ratectrl?
536 sc->sc_setdefantenna = ath_setdefantenna;
537 sc->sc_rc = ath_rate_attach(sc);
538 if (sc->sc_rc == NULL) {
545 sc->sc_ledon = 0; /* low true */
546 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
547 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
549 * Auto-enable soft led processing for IBM cards and for
550 * 5211 minipci cards. Users can also manually enable/disable
551 * support with a sysctl.
553 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
554 if (sc->sc_softled) {
555 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin,
556 HAL_GPIO_MUX_MAC_NETWORK_LED);
557 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
561 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
562 ifp->if_start = ath_start;
563 ifp->if_ioctl = ath_ioctl;
564 ifp->if_init = ath_init;
565 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
566 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
567 IFQ_SET_READY(&ifp->if_snd);
570 /* XXX not right but it's not used anywhere important */
571 ic->ic_phytype = IEEE80211_T_OFDM;
572 ic->ic_opmode = IEEE80211_M_STA;
574 IEEE80211_C_STA /* station mode */
575 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
576 | IEEE80211_C_HOSTAP /* hostap mode */
577 | IEEE80211_C_MONITOR /* monitor mode */
578 | IEEE80211_C_AHDEMO /* adhoc demo mode */
579 | IEEE80211_C_WDS /* 4-address traffic works */
580 | IEEE80211_C_MBSS /* mesh point link mode */
581 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
582 | IEEE80211_C_SHSLOT /* short slot time supported */
583 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
584 | IEEE80211_C_BGSCAN /* capable of bg scanning */
585 | IEEE80211_C_TXFRAG /* handle tx frags */
588 * Query the hal to figure out h/w crypto support.
590 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
591 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
592 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
593 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
594 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
595 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
596 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
597 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
598 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
599 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
601 * Check if h/w does the MIC and/or whether the
602 * separate key cache entries are required to
603 * handle both tx+rx MIC keys.
605 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
606 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
608 * If the h/w supports storing tx+rx MIC keys
609 * in one cache slot automatically enable use.
611 if (ath_hal_hastkipsplit(ah) ||
612 !ath_hal_settkipsplit(ah, AH_FALSE))
615 * If the h/w can do TKIP MIC together with WME then
616 * we use it; otherwise we force the MIC to be done
617 * in software by the net80211 layer.
619 if (ath_hal_haswmetkipmic(ah))
620 sc->sc_wmetkipmic = 1;
622 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
624 * Check for multicast key search support.
626 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
627 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
628 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
630 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
632 * Mark key cache slots associated with global keys
633 * as in use. If we knew TKIP was not to be used we
634 * could leave the +32, +64, and +32+64 slots free.
636 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
637 setbit(sc->sc_keymap, i);
638 setbit(sc->sc_keymap, i+64);
639 if (sc->sc_splitmic) {
640 setbit(sc->sc_keymap, i+32);
641 setbit(sc->sc_keymap, i+32+64);
645 * TPC support can be done either with a global cap or
646 * per-packet support. The latter is not available on
647 * all parts. We're a bit pedantic here as all parts
648 * support a global cap.
650 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
651 ic->ic_caps |= IEEE80211_C_TXPMGT;
654 * Mark WME capability only if we have sufficient
655 * hardware queues to do proper priority scheduling.
657 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
658 ic->ic_caps |= IEEE80211_C_WME;
660 * Check for misc other capabilities.
662 if (ath_hal_hasbursting(ah))
663 ic->ic_caps |= IEEE80211_C_BURST;
664 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
665 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
666 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
667 if (ath_hal_hasfastframes(ah))
668 ic->ic_caps |= IEEE80211_C_FF;
669 wmodes = ath_hal_getwirelessmodes(ah);
670 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
671 ic->ic_caps |= IEEE80211_C_TURBOP;
672 #ifdef IEEE80211_SUPPORT_TDMA
673 if (ath_hal_macversion(ah) > 0x78) {
674 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
675 ic->ic_tdma_update = ath_tdma_update;
679 * Indicate we need the 802.11 header padded to a
680 * 32-bit boundary for 4-address and QoS frames.
682 ic->ic_flags |= IEEE80211_F_DATAPAD;
685 * Query the hal about antenna support.
687 sc->sc_defant = ath_hal_getdefantenna(ah);
690 * Not all chips have the VEOL support we want to
691 * use with IBSS beacons; check here for it.
693 sc->sc_hasveol = ath_hal_hasveol(ah);
695 /* get mac address from hardware */
696 ath_hal_getmac(ah, macaddr);
698 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
700 /* NB: used to size node table key mapping array */
701 ic->ic_max_keyix = sc->sc_keymax;
702 /* call MI attach routine. */
703 ieee80211_ifattach(ic, macaddr);
704 ic->ic_setregdomain = ath_setregdomain;
705 ic->ic_getradiocaps = ath_getradiocaps;
706 sc->sc_opmode = HAL_M_STA;
708 /* override default methods */
709 ic->ic_newassoc = ath_newassoc;
710 ic->ic_updateslot = ath_updateslot;
711 ic->ic_wme.wme_update = ath_wme_update;
712 ic->ic_vap_create = ath_vap_create;
713 ic->ic_vap_delete = ath_vap_delete;
714 ic->ic_raw_xmit = ath_raw_xmit;
715 ic->ic_update_mcast = ath_update_mcast;
716 ic->ic_update_promisc = ath_update_promisc;
717 ic->ic_node_alloc = ath_node_alloc;
718 sc->sc_node_free = ic->ic_node_free;
719 ic->ic_node_free = ath_node_free;
720 ic->ic_node_getsignal = ath_node_getsignal;
721 ic->ic_scan_start = ath_scan_start;
722 ic->ic_scan_end = ath_scan_end;
723 ic->ic_set_channel = ath_set_channel;
725 ieee80211_radiotap_attach(ic,
726 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
727 ATH_TX_RADIOTAP_PRESENT,
728 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
729 ATH_RX_RADIOTAP_PRESENT);
732 * Setup dynamic sysctl's now that country code and
733 * regdomain are available from the hal.
735 ath_sysctlattach(sc);
738 ieee80211_announce(ic);
754 ath_detach(struct ath_softc *sc)
756 struct ifnet *ifp = sc->sc_ifp;
758 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
759 __func__, ifp->if_flags);
762 * NB: the order of these is important:
763 * o stop the chip so no more interrupts will fire
764 * o call the 802.11 layer before detaching the hal to
765 * insure callbacks into the driver to delete global
766 * key cache entries can be handled
767 * o free the taskqueue which drains any pending tasks
768 * o reclaim the tx queue data structures after calling
769 * the 802.11 layer as we'll get called back to reclaim
770 * node state and potentially want to use them
771 * o to cleanup the tx queues the hal is called, so detach
773 * Other than that, it's straightforward...
776 ieee80211_ifdetach(ifp->if_l2com);
777 taskqueue_free(sc->sc_tq);
779 if (sc->sc_tx99 != NULL)
780 sc->sc_tx99->detach(sc->sc_tx99);
782 ath_rate_detach(sc->sc_rc);
785 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
792 * MAC address handling for multiple BSS on the same radio.
793 * The first vap uses the MAC address from the EEPROM. For
794 * subsequent vap's we set the U/L bit (bit 1) in the MAC
795 * address and use the next six bits as an index.
798 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
802 if (clone && sc->sc_hasbmask) {
803 /* NB: we only do this if h/w supports multiple bssid */
804 for (i = 0; i < 8; i++)
805 if ((sc->sc_bssidmask & (1<<i)) == 0)
808 mac[0] |= (i << 2)|0x2;
811 sc->sc_bssidmask |= 1<<i;
812 sc->sc_hwbssidmask[0] &= ~mac[0];
818 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
823 if (i != 0 || --sc->sc_nbssid0 == 0) {
824 sc->sc_bssidmask &= ~(1<<i);
825 /* recalculate bssid mask from remaining addresses */
827 for (i = 1; i < 8; i++)
828 if (sc->sc_bssidmask & (1<<i))
829 mask &= ~((i<<2)|0x2);
830 sc->sc_hwbssidmask[0] |= mask;
835 * Assign a beacon xmit slot. We try to space out
836 * assignments so when beacons are staggered the
837 * traffic coming out of the cab q has maximal time
838 * to go out before the next beacon is scheduled.
841 assign_bslot(struct ath_softc *sc)
846 for (slot = 0; slot < ATH_BCBUF; slot++)
847 if (sc->sc_bslot[slot] == NULL) {
848 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
849 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
852 /* NB: keep looking for a double slot */
857 static struct ieee80211vap *
858 ath_vap_create(struct ieee80211com *ic,
859 const char name[IFNAMSIZ], int unit, int opmode, int flags,
860 const uint8_t bssid[IEEE80211_ADDR_LEN],
861 const uint8_t mac0[IEEE80211_ADDR_LEN])
863 struct ath_softc *sc = ic->ic_ifp->if_softc;
865 struct ieee80211vap *vap;
866 uint8_t mac[IEEE80211_ADDR_LEN];
867 int ic_opmode, needbeacon, error;
869 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
870 M_80211_VAP, M_WAITOK | M_ZERO);
872 IEEE80211_ADDR_COPY(mac, mac0);
875 ic_opmode = opmode; /* default to opmode of new vap */
877 case IEEE80211_M_STA:
878 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
879 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
884 * With multiple vaps we must fall back
885 * to s/w beacon miss handling.
887 flags |= IEEE80211_CLONE_NOBEACONS;
889 if (flags & IEEE80211_CLONE_NOBEACONS) {
891 * Station mode w/o beacons are implemented w/ AP mode.
893 ic_opmode = IEEE80211_M_HOSTAP;
896 case IEEE80211_M_IBSS:
897 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
898 device_printf(sc->sc_dev,
899 "only 1 ibss vap supported\n");
904 case IEEE80211_M_AHDEMO:
905 #ifdef IEEE80211_SUPPORT_TDMA
906 if (flags & IEEE80211_CLONE_TDMA) {
907 if (sc->sc_nvaps != 0) {
908 device_printf(sc->sc_dev,
909 "only 1 tdma vap supported\n");
913 flags |= IEEE80211_CLONE_NOBEACONS;
917 case IEEE80211_M_MONITOR:
918 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
920 * Adopt existing mode. Adding a monitor or ahdemo
921 * vap to an existing configuration is of dubious
922 * value but should be ok.
924 /* XXX not right for monitor mode */
925 ic_opmode = ic->ic_opmode;
928 case IEEE80211_M_HOSTAP:
929 case IEEE80211_M_MBSS:
932 case IEEE80211_M_WDS:
933 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
934 device_printf(sc->sc_dev,
935 "wds not supported in sta mode\n");
939 * Silently remove any request for a unique
940 * bssid; WDS vap's always share the local
943 flags &= ~IEEE80211_CLONE_BSSID;
944 if (sc->sc_nvaps == 0)
945 ic_opmode = IEEE80211_M_HOSTAP;
947 ic_opmode = ic->ic_opmode;
950 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
954 * Check that a beacon buffer is available; the code below assumes it.
956 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) {
957 device_printf(sc->sc_dev, "no beacon buffer available\n");
962 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
963 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
964 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
968 /* XXX can't hold mutex across if_alloc */
970 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
974 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
979 /* h/w crypto support */
980 vap->iv_key_alloc = ath_key_alloc;
981 vap->iv_key_delete = ath_key_delete;
982 vap->iv_key_set = ath_key_set;
983 vap->iv_key_update_begin = ath_key_update_begin;
984 vap->iv_key_update_end = ath_key_update_end;
986 /* override various methods */
987 avp->av_recv_mgmt = vap->iv_recv_mgmt;
988 vap->iv_recv_mgmt = ath_recv_mgmt;
989 vap->iv_reset = ath_reset_vap;
990 vap->iv_update_beacon = ath_beacon_update;
991 avp->av_newstate = vap->iv_newstate;
992 vap->iv_newstate = ath_newstate;
993 avp->av_bmiss = vap->iv_bmiss;
994 vap->iv_bmiss = ath_bmiss_vap;
999 * Allocate beacon state and setup the q for buffered
1000 * multicast frames. We know a beacon buffer is
1001 * available because we checked above.
1003 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf);
1004 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list);
1005 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1007 * Assign the vap to a beacon xmit slot. As above
1008 * this cannot fail to find a free one.
1010 avp->av_bslot = assign_bslot(sc);
1011 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1012 ("beacon slot %u not empty", avp->av_bslot));
1013 sc->sc_bslot[avp->av_bslot] = vap;
1016 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1018 * Multple vaps are to transmit beacons and we
1019 * have h/w support for TSF adjusting; enable
1020 * use of staggered beacons.
1022 sc->sc_stagbeacons = 1;
1024 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1027 ic->ic_opmode = ic_opmode;
1028 if (opmode != IEEE80211_M_WDS) {
1030 if (opmode == IEEE80211_M_STA)
1032 if (opmode == IEEE80211_M_MBSS)
1035 switch (ic_opmode) {
1036 case IEEE80211_M_IBSS:
1037 sc->sc_opmode = HAL_M_IBSS;
1039 case IEEE80211_M_STA:
1040 sc->sc_opmode = HAL_M_STA;
1042 case IEEE80211_M_AHDEMO:
1043 #ifdef IEEE80211_SUPPORT_TDMA
1044 if (vap->iv_caps & IEEE80211_C_TDMA) {
1046 /* NB: disable tsf adjust */
1047 sc->sc_stagbeacons = 0;
1050 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1055 case IEEE80211_M_HOSTAP:
1056 case IEEE80211_M_MBSS:
1057 sc->sc_opmode = HAL_M_HOSTAP;
1059 case IEEE80211_M_MONITOR:
1060 sc->sc_opmode = HAL_M_MONITOR;
1063 /* XXX should not happen */
1066 if (sc->sc_hastsfadd) {
1068 * Configure whether or not TSF adjust should be done.
1070 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1072 if (flags & IEEE80211_CLONE_NOBEACONS) {
1074 * Enable s/w beacon miss handling.
1080 /* complete setup */
1081 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1084 reclaim_address(sc, mac);
1085 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1087 free(avp, M_80211_VAP);
1093 ath_vap_delete(struct ieee80211vap *vap)
1095 struct ieee80211com *ic = vap->iv_ic;
1096 struct ifnet *ifp = ic->ic_ifp;
1097 struct ath_softc *sc = ifp->if_softc;
1098 struct ath_hal *ah = sc->sc_ah;
1099 struct ath_vap *avp = ATH_VAP(vap);
1101 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1103 * Quiesce the hardware while we remove the vap. In
1104 * particular we need to reclaim all references to
1105 * the vap state by any frames pending on the tx queues.
1107 ath_hal_intrset(ah, 0); /* disable interrupts */
1108 ath_draintxq(sc); /* stop xmit side */
1109 ath_stoprecv(sc); /* stop recv side */
1112 ieee80211_vap_detach(vap);
1115 * Reclaim beacon state. Note this must be done before
1116 * the vap instance is reclaimed as we may have a reference
1117 * to it in the buffer for the beacon frame.
1119 if (avp->av_bcbuf != NULL) {
1120 if (avp->av_bslot != -1) {
1121 sc->sc_bslot[avp->av_bslot] = NULL;
1124 ath_beacon_return(sc, avp->av_bcbuf);
1125 avp->av_bcbuf = NULL;
1126 if (sc->sc_nbcnvaps == 0) {
1127 sc->sc_stagbeacons = 0;
1128 if (sc->sc_hastsfadd)
1129 ath_hal_settsfadjust(sc->sc_ah, 0);
1132 * Reclaim any pending mcast frames for the vap.
1134 ath_tx_draintxq(sc, &avp->av_mcastq);
1135 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq);
1138 * Update bookkeeping.
1140 if (vap->iv_opmode == IEEE80211_M_STA) {
1142 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1144 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1145 vap->iv_opmode == IEEE80211_M_MBSS) {
1146 reclaim_address(sc, vap->iv_myaddr);
1147 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1148 if (vap->iv_opmode == IEEE80211_M_MBSS)
1151 if (vap->iv_opmode != IEEE80211_M_WDS)
1153 #ifdef IEEE80211_SUPPORT_TDMA
1154 /* TDMA operation ceases when the last vap is destroyed */
1155 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1161 free(avp, M_80211_VAP);
1163 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1165 * Restart rx+tx machines if still running (RUNNING will
1166 * be reset if we just destroyed the last vap).
1168 if (ath_startrecv(sc) != 0)
1169 if_printf(ifp, "%s: unable to restart recv logic\n",
1171 if (sc->sc_beacons) { /* restart beacons */
1172 #ifdef IEEE80211_SUPPORT_TDMA
1174 ath_tdma_config(sc, NULL);
1177 ath_beacon_config(sc, NULL);
1179 ath_hal_intrset(ah, sc->sc_imask);
1184 ath_suspend(struct ath_softc *sc)
1186 struct ifnet *ifp = sc->sc_ifp;
1187 struct ieee80211com *ic = ifp->if_l2com;
1189 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1190 __func__, ifp->if_flags);
1192 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1193 if (ic->ic_opmode == IEEE80211_M_STA)
1196 ieee80211_suspend_all(ic);
1198 * NB: don't worry about putting the chip in low power
1199 * mode; pci will power off our socket on suspend and
1200 * cardbus detaches the device.
1205 * Reset the key cache since some parts do not reset the
1206 * contents on resume. First we clear all entries, then
1207 * re-load keys that the 802.11 layer assumes are setup
1211 ath_reset_keycache(struct ath_softc *sc)
1213 struct ifnet *ifp = sc->sc_ifp;
1214 struct ieee80211com *ic = ifp->if_l2com;
1215 struct ath_hal *ah = sc->sc_ah;
1218 for (i = 0; i < sc->sc_keymax; i++)
1219 ath_hal_keyreset(ah, i);
1220 ieee80211_crypto_reload_keys(ic);
1224 ath_resume(struct ath_softc *sc)
1226 struct ifnet *ifp = sc->sc_ifp;
1227 struct ieee80211com *ic = ifp->if_l2com;
1228 struct ath_hal *ah = sc->sc_ah;
1231 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1232 __func__, ifp->if_flags);
1235 * Must reset the chip before we reload the
1236 * keycache as we were powered down on suspend.
1238 ath_hal_reset(ah, sc->sc_opmode,
1239 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1241 ath_reset_keycache(sc);
1242 if (sc->sc_resume_up) {
1243 if (ic->ic_opmode == IEEE80211_M_STA) {
1246 * Program the beacon registers using the last rx'd
1247 * beacon frame and enable sync on the next beacon
1248 * we see. This should handle the case where we
1249 * wakeup and find the same AP and also the case where
1250 * we wakeup and need to roam. For the latter we
1251 * should get bmiss events that trigger a roam.
1253 ath_beacon_config(sc, NULL);
1254 sc->sc_syncbeacon = 1;
1256 ieee80211_resume_all(ic);
1258 if (sc->sc_softled) {
1259 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin,
1260 HAL_GPIO_MUX_MAC_NETWORK_LED);
1261 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
1266 ath_shutdown(struct ath_softc *sc)
1268 struct ifnet *ifp = sc->sc_ifp;
1270 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1271 __func__, ifp->if_flags);
1274 /* NB: no point powering down chip as we're about to reboot */
1278 * Interrupt handler. Most of the actual processing is deferred.
1283 struct ath_softc *sc = arg;
1284 struct ifnet *ifp = sc->sc_ifp;
1285 struct ath_hal *ah = sc->sc_ah;
1288 if (sc->sc_invalid) {
1290 * The hardware is not ready/present, don't touch anything.
1291 * Note this can happen early on if the IRQ is shared.
1293 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
1296 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
1298 if ((ifp->if_flags & IFF_UP) == 0 ||
1299 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1302 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1303 __func__, ifp->if_flags);
1304 ath_hal_getisr(ah, &status); /* clear ISR */
1305 ath_hal_intrset(ah, 0); /* disable further intr's */
1309 * Figure out the reason(s) for the interrupt. Note
1310 * that the hal returns a pseudo-ISR that may include
1311 * bits we haven't explicitly enabled so we mask the
1312 * value to insure we only process bits we requested.
1314 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
1315 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
1316 status &= sc->sc_imask; /* discard unasked for bits */
1317 if (status & HAL_INT_FATAL) {
1318 sc->sc_stats.ast_hardware++;
1319 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1320 ath_fatal_proc(sc, 0);
1322 if (status & HAL_INT_SWBA) {
1324 * Software beacon alert--time to send a beacon.
1325 * Handle beacon transmission directly; deferring
1326 * this is too slow to meet timing constraints
1329 #ifdef IEEE80211_SUPPORT_TDMA
1331 if (sc->sc_tdmaswba == 0) {
1332 struct ieee80211com *ic = ifp->if_l2com;
1333 struct ieee80211vap *vap =
1334 TAILQ_FIRST(&ic->ic_vaps);
1335 ath_tdma_beacon_send(sc, vap);
1337 vap->iv_tdma->tdma_bintval;
1343 ath_beacon_proc(sc, 0);
1344 #ifdef IEEE80211_SUPPORT_SUPERG
1346 * Schedule the rx taskq in case there's no
1347 * traffic so any frames held on the staging
1348 * queue are aged and potentially flushed.
1350 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1354 if (status & HAL_INT_RXEOL) {
1356 * NB: the hardware should re-read the link when
1357 * RXE bit is written, but it doesn't work at
1358 * least on older hardware revs.
1360 sc->sc_stats.ast_rxeol++;
1361 sc->sc_rxlink = NULL;
1363 if (status & HAL_INT_TXURN) {
1364 sc->sc_stats.ast_txurn++;
1365 /* bump tx trigger level */
1366 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1368 if (status & HAL_INT_RX)
1369 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1370 if (status & HAL_INT_TX)
1371 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
1372 if (status & HAL_INT_BMISS) {
1373 sc->sc_stats.ast_bmiss++;
1374 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
1376 if (status & HAL_INT_MIB) {
1377 sc->sc_stats.ast_mib++;
1379 * Disable interrupts until we service the MIB
1380 * interrupt; otherwise it will continue to fire.
1382 ath_hal_intrset(ah, 0);
1384 * Let the hal handle the event. We assume it will
1385 * clear whatever condition caused the interrupt.
1387 ath_hal_mibevent(ah, &sc->sc_halstats);
1388 ath_hal_intrset(ah, sc->sc_imask);
1390 if (status & HAL_INT_RXORN) {
1391 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
1392 sc->sc_stats.ast_rxorn++;
1398 ath_fatal_proc(void *arg, int pending)
1400 struct ath_softc *sc = arg;
1401 struct ifnet *ifp = sc->sc_ifp;
1406 if_printf(ifp, "hardware error; resetting\n");
1408 * Fatal errors are unrecoverable. Typically these
1409 * are caused by DMA errors. Collect h/w state from
1410 * the hal so we can diagnose what's going on.
1412 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
1413 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
1415 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
1416 state[0], state[1] , state[2], state[3],
1417 state[4], state[5]);
1423 ath_bmiss_vap(struct ieee80211vap *vap)
1426 * Workaround phantom bmiss interrupts by sanity-checking
1427 * the time of our last rx'd frame. If it is within the
1428 * beacon miss interval then ignore the interrupt. If it's
1429 * truly a bmiss we'll get another interrupt soon and that'll
1430 * be dispatched up for processing. Note this applies only
1431 * for h/w beacon miss events.
1433 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
1434 struct ifnet *ifp = vap->iv_ic->ic_ifp;
1435 struct ath_softc *sc = ifp->if_softc;
1436 u_int64_t lastrx = sc->sc_lastrx;
1437 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
1438 u_int bmisstimeout =
1439 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
1441 DPRINTF(sc, ATH_DEBUG_BEACON,
1442 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
1443 __func__, (unsigned long long) tsf,
1444 (unsigned long long)(tsf - lastrx),
1445 (unsigned long long) lastrx, bmisstimeout);
1447 if (tsf - lastrx <= bmisstimeout) {
1448 sc->sc_stats.ast_bmiss_phantom++;
1452 ATH_VAP(vap)->av_bmiss(vap);
1456 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
1461 if (!ath_hal_getdiagstate(ah, 32, &mask, sizeof(&mask), &sp, &rsize))
1463 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
1464 *hangs = *(uint32_t *)sp;
1469 ath_bmiss_proc(void *arg, int pending)
1471 struct ath_softc *sc = arg;
1472 struct ifnet *ifp = sc->sc_ifp;
1475 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
1477 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
1478 if_printf(ifp, "bb hang detected (0x%x), reseting\n", hangs);
1481 ieee80211_beacon_miss(ifp->if_l2com);
1485 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
1486 * calcs together with WME. If necessary disable the crypto
1487 * hardware and mark the 802.11 state so keys will be setup
1488 * with the MIC work done in software.
1491 ath_settkipmic(struct ath_softc *sc)
1493 struct ifnet *ifp = sc->sc_ifp;
1494 struct ieee80211com *ic = ifp->if_l2com;
1496 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
1497 if (ic->ic_flags & IEEE80211_F_WME) {
1498 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
1499 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
1501 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
1502 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
1510 struct ath_softc *sc = (struct ath_softc *) arg;
1511 struct ifnet *ifp = sc->sc_ifp;
1512 struct ieee80211com *ic = ifp->if_l2com;
1513 struct ath_hal *ah = sc->sc_ah;
1516 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1517 __func__, ifp->if_flags);
1521 * Stop anything previously setup. This is safe
1522 * whether this is the first time through or not.
1524 ath_stop_locked(ifp);
1527 * The basic interface to setting the hardware in a good
1528 * state is ``reset''. On return the hardware is known to
1529 * be powered up and with interrupts disabled. This must
1530 * be followed by initialization of the appropriate bits
1531 * and then setup of the interrupt mask.
1534 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
1535 if_printf(ifp, "unable to reset hardware; hal status %u\n",
1540 ath_chan_change(sc, ic->ic_curchan);
1543 * Likewise this is set during reset so update
1544 * state cached in the driver.
1546 sc->sc_diversity = ath_hal_getdiversity(ah);
1547 sc->sc_lastlongcal = 0;
1548 sc->sc_resetcal = 1;
1549 sc->sc_lastcalreset = 0;
1552 * Setup the hardware after reset: the key cache
1553 * is filled as needed and the receive engine is
1554 * set going. Frame transmit is handled entirely
1555 * in the frame output path; there's nothing to do
1556 * here except setup the interrupt mask.
1558 if (ath_startrecv(sc) != 0) {
1559 if_printf(ifp, "unable to start recv logic\n");
1565 * Enable interrupts.
1567 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1568 | HAL_INT_RXEOL | HAL_INT_RXORN
1569 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1571 * Enable MIB interrupts when there are hardware phy counters.
1572 * Note we only do this (at the moment) for station mode.
1574 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
1575 sc->sc_imask |= HAL_INT_MIB;
1577 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1578 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
1579 ath_hal_intrset(ah, sc->sc_imask);
1583 #ifdef ATH_TX99_DIAG
1584 if (sc->sc_tx99 != NULL)
1585 sc->sc_tx99->start(sc->sc_tx99);
1588 ieee80211_start_all(ic); /* start all vap's */
1592 ath_stop_locked(struct ifnet *ifp)
1594 struct ath_softc *sc = ifp->if_softc;
1595 struct ath_hal *ah = sc->sc_ah;
1597 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
1598 __func__, sc->sc_invalid, ifp->if_flags);
1600 ATH_LOCK_ASSERT(sc);
1601 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1603 * Shutdown the hardware and driver:
1604 * reset 802.11 state machine
1606 * disable interrupts
1607 * turn off the radio
1608 * clear transmit machinery
1609 * clear receive machinery
1610 * drain and release tx queues
1611 * reclaim beacon resources
1612 * power down hardware
1614 * Note that some of this work is not possible if the
1615 * hardware is gone (invalid).
1617 #ifdef ATH_TX99_DIAG
1618 if (sc->sc_tx99 != NULL)
1619 sc->sc_tx99->stop(sc->sc_tx99);
1621 callout_stop(&sc->sc_wd_ch);
1622 sc->sc_wd_timer = 0;
1623 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1624 if (!sc->sc_invalid) {
1625 if (sc->sc_softled) {
1626 callout_stop(&sc->sc_ledtimer);
1627 ath_hal_gpioset(ah, sc->sc_ledpin,
1629 sc->sc_blinking = 0;
1631 ath_hal_intrset(ah, 0);
1634 if (!sc->sc_invalid) {
1636 ath_hal_phydisable(ah);
1638 sc->sc_rxlink = NULL;
1639 ath_beacon_free(sc); /* XXX not needed */
1644 ath_stop(struct ifnet *ifp)
1646 struct ath_softc *sc = ifp->if_softc;
1649 ath_stop_locked(ifp);
1654 * Reset the hardware w/o losing operational state. This is
1655 * basically a more efficient way of doing ath_stop, ath_init,
1656 * followed by state transitions to the current 802.11
1657 * operational state. Used to recover from various errors and
1658 * to reset or reload hardware state.
1661 ath_reset(struct ifnet *ifp)
1663 struct ath_softc *sc = ifp->if_softc;
1664 struct ieee80211com *ic = ifp->if_l2com;
1665 struct ath_hal *ah = sc->sc_ah;
1668 ath_hal_intrset(ah, 0); /* disable interrupts */
1669 ath_draintxq(sc); /* stop xmit side */
1670 ath_stoprecv(sc); /* stop recv side */
1671 ath_settkipmic(sc); /* configure TKIP MIC handling */
1672 /* NB: indicate channel change so we do a full reset */
1673 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
1674 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1676 sc->sc_diversity = ath_hal_getdiversity(ah);
1677 if (ath_startrecv(sc) != 0) /* restart recv */
1678 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1680 * We may be doing a reset in response to an ioctl
1681 * that changes the channel so update any state that
1682 * might change as a result.
1684 ath_chan_change(sc, ic->ic_curchan);
1685 if (sc->sc_beacons) { /* restart beacons */
1686 #ifdef IEEE80211_SUPPORT_TDMA
1688 ath_tdma_config(sc, NULL);
1691 ath_beacon_config(sc, NULL);
1693 ath_hal_intrset(ah, sc->sc_imask);
1695 ath_start(ifp); /* restart xmit */
1700 ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
1702 struct ieee80211com *ic = vap->iv_ic;
1703 struct ifnet *ifp = ic->ic_ifp;
1704 struct ath_softc *sc = ifp->if_softc;
1705 struct ath_hal *ah = sc->sc_ah;
1708 case IEEE80211_IOC_TXPOWER:
1710 * If per-packet TPC is enabled, then we have nothing
1711 * to do; otherwise we need to force the global limit.
1712 * All this can happen directly; no need to reset.
1714 if (!ath_hal_gettpc(ah))
1715 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
1718 return ath_reset(ifp);
1721 static struct ath_buf *
1722 _ath_getbuf_locked(struct ath_softc *sc)
1726 ATH_TXBUF_LOCK_ASSERT(sc);
1728 bf = STAILQ_FIRST(&sc->sc_txbuf);
1729 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0)
1730 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1734 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
1735 STAILQ_FIRST(&sc->sc_txbuf) == NULL ?
1736 "out of xmit buffers" : "xmit buffer busy");
1741 static struct ath_buf *
1742 ath_getbuf(struct ath_softc *sc)
1747 bf = _ath_getbuf_locked(sc);
1749 struct ifnet *ifp = sc->sc_ifp;
1751 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
1752 sc->sc_stats.ast_tx_qstop++;
1753 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1755 ATH_TXBUF_UNLOCK(sc);
1760 * Cleanup driver resources when we run out of buffers
1761 * while processing fragments; return the tx buffers
1762 * allocated and drop node references.
1765 ath_txfrag_cleanup(struct ath_softc *sc,
1766 ath_bufhead *frags, struct ieee80211_node *ni)
1768 struct ath_buf *bf, *next;
1770 ATH_TXBUF_LOCK_ASSERT(sc);
1772 STAILQ_FOREACH_SAFE(bf, frags, bf_list, next) {
1773 /* NB: bf assumed clean */
1774 STAILQ_REMOVE_HEAD(frags, bf_list);
1775 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1776 ieee80211_node_decref(ni);
1781 * Setup xmit of a fragmented frame. Allocate a buffer
1782 * for each frag and bump the node reference count to
1783 * reflect the held reference to be setup by ath_tx_start.
1786 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags,
1787 struct mbuf *m0, struct ieee80211_node *ni)
1793 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) {
1794 bf = _ath_getbuf_locked(sc);
1795 if (bf == NULL) { /* out of buffers, cleanup */
1796 ath_txfrag_cleanup(sc, frags, ni);
1799 ieee80211_node_incref(ni);
1800 STAILQ_INSERT_TAIL(frags, bf, bf_list);
1802 ATH_TXBUF_UNLOCK(sc);
1804 return !STAILQ_EMPTY(frags);
1808 ath_start(struct ifnet *ifp)
1810 struct ath_softc *sc = ifp->if_softc;
1811 struct ieee80211_node *ni;
1813 struct mbuf *m, *next;
1816 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
1820 * Grab a TX buffer and associated resources.
1822 bf = ath_getbuf(sc);
1826 IFQ_DEQUEUE(&ifp->if_snd, m);
1829 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1830 ATH_TXBUF_UNLOCK(sc);
1833 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1835 * Check for fragmentation. If this frame
1836 * has been broken up verify we have enough
1837 * buffers to send all the fragments so all
1840 STAILQ_INIT(&frags);
1841 if ((m->m_flags & M_FRAG) &&
1842 !ath_txfrag_setup(sc, &frags, m, ni)) {
1843 DPRINTF(sc, ATH_DEBUG_XMIT,
1844 "%s: out of txfrag buffers\n", __func__);
1845 sc->sc_stats.ast_tx_nofrag++;
1853 * Pass the frame to the h/w for transmission.
1854 * Fragmented frames have each frag chained together
1855 * with m_nextpkt. We know there are sufficient ath_buf's
1856 * to send all the frags because of work done by
1857 * ath_txfrag_setup. We leave m_nextpkt set while
1858 * calling ath_tx_start so it can use it to extend the
1859 * the tx duration to cover the subsequent frag and
1860 * so it can reclaim all the mbufs in case of an error;
1861 * ath_tx_start clears m_nextpkt once it commits to
1862 * handing the frame to the hardware.
1864 next = m->m_nextpkt;
1865 if (ath_tx_start(sc, ni, bf, m)) {
1872 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
1873 ath_txfrag_cleanup(sc, &frags, ni);
1874 ATH_TXBUF_UNLOCK(sc);
1876 ieee80211_free_node(ni);
1881 * Beware of state changing between frags.
1882 * XXX check sta power-save state?
1884 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
1885 DPRINTF(sc, ATH_DEBUG_XMIT,
1886 "%s: flush fragmented packet, state %s\n",
1888 ieee80211_state_name[ni->ni_vap->iv_state]);
1893 bf = STAILQ_FIRST(&frags);
1894 KASSERT(bf != NULL, ("no buf for txfrag"));
1895 STAILQ_REMOVE_HEAD(&frags, bf_list);
1899 sc->sc_wd_timer = 5;
1904 ath_media_change(struct ifnet *ifp)
1906 int error = ieee80211_media_change(ifp);
1907 /* NB: only the fixed rate can change and that doesn't need a reset */
1908 return (error == ENETRESET ? 0 : error);
1913 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix,
1914 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1916 static const char *ciphers[] = {
1926 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1927 for (i = 0, n = hk->kv_len; i < n; i++)
1928 printf("%02x", hk->kv_val[i]);
1929 printf(" mac %s", ether_sprintf(mac));
1930 if (hk->kv_type == HAL_CIPHER_TKIP) {
1931 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic");
1932 for (i = 0; i < sizeof(hk->kv_mic); i++)
1933 printf("%02x", hk->kv_mic[i]);
1934 if (!sc->sc_splitmic) {
1936 for (i = 0; i < sizeof(hk->kv_txmic); i++)
1937 printf("%02x", hk->kv_txmic[i]);
1945 * Set a TKIP key into the hardware. This handles the
1946 * potential distribution of key state to multiple key
1947 * cache slots for TKIP.
1950 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1951 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1953 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1954 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN];
1955 struct ath_hal *ah = sc->sc_ah;
1957 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1958 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1959 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1960 if (sc->sc_splitmic) {
1962 * TX key goes at first index, RX key at the rx index.
1963 * The hal handles the MIC keys at index+64.
1965 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1966 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1967 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1970 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1971 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1972 /* XXX delete tx key on failure? */
1973 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1976 * Room for both TX+RX MIC keys in one key cache
1977 * slot, just set key at the first index; the hal
1978 * will handle the rest.
1980 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1981 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
1982 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1983 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1985 } else if (k->wk_flags & IEEE80211_KEY_XMIT) {
1986 if (sc->sc_splitmic) {
1988 * NB: must pass MIC key in expected location when
1989 * the keycache only holds one MIC key per entry.
1991 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_txmic));
1993 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
1994 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1995 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1996 } else if (k->wk_flags & IEEE80211_KEY_RECV) {
1997 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1998 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1999 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
2002 #undef IEEE80211_KEY_XR
2006 * Set a net80211 key into the hardware. This handles the
2007 * potential distribution of key state to multiple key
2008 * cache slots for TKIP with hardware MIC support.
2011 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
2012 struct ieee80211_node *bss)
2014 #define N(a) (sizeof(a)/sizeof(a[0]))
2015 static const u_int8_t ciphermap[] = {
2016 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
2017 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
2018 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
2019 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
2020 (u_int8_t) -1, /* 4 is not allocated */
2021 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
2022 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
2024 struct ath_hal *ah = sc->sc_ah;
2025 const struct ieee80211_cipher *cip = k->wk_cipher;
2026 u_int8_t gmac[IEEE80211_ADDR_LEN];
2027 const u_int8_t *mac;
2030 memset(&hk, 0, sizeof(hk));
2032 * Software crypto uses a "clear key" so non-crypto
2033 * state kept in the key cache are maintained and
2034 * so that rx frames have an entry to match.
2036 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
2037 KASSERT(cip->ic_cipher < N(ciphermap),
2038 ("invalid cipher type %u", cip->ic_cipher));
2039 hk.kv_type = ciphermap[cip->ic_cipher];
2040 hk.kv_len = k->wk_keylen;
2041 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
2043 hk.kv_type = HAL_CIPHER_CLR;
2045 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
2047 * Group keys on hardware that supports multicast frame
2048 * key search use a MAC that is the sender's address with
2049 * the high bit set instead of the app-specified address.
2051 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
2055 mac = k->wk_macaddr;
2057 if (hk.kv_type == HAL_CIPHER_TKIP &&
2058 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2059 return ath_keyset_tkip(sc, k, &hk, mac);
2061 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
2062 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
2068 * Allocate tx/rx key slots for TKIP. We allocate two slots for
2069 * each key, one for decrypt/encrypt and the other for the MIC.
2072 key_alloc_2pair(struct ath_softc *sc,
2073 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2075 #define N(a) (sizeof(a)/sizeof(a[0]))
2078 KASSERT(sc->sc_splitmic, ("key cache !split"));
2079 /* XXX could optimize */
2080 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
2081 u_int8_t b = sc->sc_keymap[i];
2084 * One or more slots in this byte are free.
2092 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
2093 if (isset(sc->sc_keymap, keyix+32) ||
2094 isset(sc->sc_keymap, keyix+64) ||
2095 isset(sc->sc_keymap, keyix+32+64)) {
2096 /* full pair unavailable */
2098 if (keyix == (i+1)*NBBY) {
2099 /* no slots were appropriate, advance */
2104 setbit(sc->sc_keymap, keyix);
2105 setbit(sc->sc_keymap, keyix+64);
2106 setbit(sc->sc_keymap, keyix+32);
2107 setbit(sc->sc_keymap, keyix+32+64);
2108 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2109 "%s: key pair %u,%u %u,%u\n",
2110 __func__, keyix, keyix+64,
2111 keyix+32, keyix+32+64);
2113 *rxkeyix = keyix+32;
2117 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
2123 * Allocate tx/rx key slots for TKIP. We allocate two slots for
2124 * each key, one for decrypt/encrypt and the other for the MIC.
2127 key_alloc_pair(struct ath_softc *sc,
2128 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2130 #define N(a) (sizeof(a)/sizeof(a[0]))
2133 KASSERT(!sc->sc_splitmic, ("key cache split"));
2134 /* XXX could optimize */
2135 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
2136 u_int8_t b = sc->sc_keymap[i];
2139 * One or more slots in this byte are free.
2147 if (isset(sc->sc_keymap, keyix+64)) {
2148 /* full pair unavailable */
2150 if (keyix == (i+1)*NBBY) {
2151 /* no slots were appropriate, advance */
2156 setbit(sc->sc_keymap, keyix);
2157 setbit(sc->sc_keymap, keyix+64);
2158 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2159 "%s: key pair %u,%u\n",
2160 __func__, keyix, keyix+64);
2161 *txkeyix = *rxkeyix = keyix;
2165 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
2171 * Allocate a single key cache slot.
2174 key_alloc_single(struct ath_softc *sc,
2175 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2177 #define N(a) (sizeof(a)/sizeof(a[0]))
2180 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
2181 for (i = 0; i < N(sc->sc_keymap); i++) {
2182 u_int8_t b = sc->sc_keymap[i];
2185 * One or more slots are free.
2190 setbit(sc->sc_keymap, keyix);
2191 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
2193 *txkeyix = *rxkeyix = keyix;
2197 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
2203 * Allocate one or more key cache slots for a uniacst key. The
2204 * key itself is needed only to identify the cipher. For hardware
2205 * TKIP with split cipher+MIC keys we allocate two key cache slot
2206 * pairs so that we can setup separate TX and RX MIC keys. Note
2207 * that the MIC key for a TKIP key at slot i is assumed by the
2208 * hardware to be at slot i+64. This limits TKIP keys to the first
2212 ath_key_alloc(struct ieee80211vap *vap, struct ieee80211_key *k,
2213 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
2215 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2218 * Group key allocation must be handled specially for
2219 * parts that do not support multicast key cache search
2220 * functionality. For those parts the key id must match
2221 * the h/w key index so lookups find the right key. On
2222 * parts w/ the key search facility we install the sender's
2223 * mac address (with the high bit set) and let the hardware
2224 * find the key w/o using the key id. This is preferred as
2225 * it permits us to support multiple users for adhoc and/or
2226 * multi-station operation.
2228 if (k->wk_keyix != IEEE80211_KEYIX_NONE) {
2230 * Only global keys should have key index assigned.
2232 if (!(&vap->iv_nw_keys[0] <= k &&
2233 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) {
2234 /* should not happen */
2235 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2236 "%s: bogus group key\n", __func__);
2239 if (vap->iv_opmode != IEEE80211_M_HOSTAP ||
2240 !(k->wk_flags & IEEE80211_KEY_GROUP) ||
2243 * XXX we pre-allocate the global keys so
2244 * have no way to check if they've already
2247 *keyix = *rxkeyix = k - vap->iv_nw_keys;
2251 * Group key and device supports multicast key search.
2253 k->wk_keyix = IEEE80211_KEYIX_NONE;
2257 * We allocate two pair for TKIP when using the h/w to do
2258 * the MIC. For everything else, including software crypto,
2259 * we allocate a single entry. Note that s/w crypto requires
2260 * a pass-through slot on the 5211 and 5212. The 5210 does
2261 * not support pass-through cache entries and we map all
2262 * those requests to slot 0.
2264 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
2265 return key_alloc_single(sc, keyix, rxkeyix);
2266 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
2267 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2268 if (sc->sc_splitmic)
2269 return key_alloc_2pair(sc, keyix, rxkeyix);
2271 return key_alloc_pair(sc, keyix, rxkeyix);
2273 return key_alloc_single(sc, keyix, rxkeyix);
2278 * Delete an entry in the key cache allocated by ath_key_alloc.
2281 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k)
2283 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2284 struct ath_hal *ah = sc->sc_ah;
2285 const struct ieee80211_cipher *cip = k->wk_cipher;
2286 u_int keyix = k->wk_keyix;
2288 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
2290 ath_hal_keyreset(ah, keyix);
2292 * Handle split tx/rx keying required for TKIP with h/w MIC.
2294 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
2295 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
2296 ath_hal_keyreset(ah, keyix+32); /* RX key */
2297 if (keyix >= IEEE80211_WEP_NKID) {
2299 * Don't touch keymap entries for global keys so
2300 * they are never considered for dynamic allocation.
2302 clrbit(sc->sc_keymap, keyix);
2303 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
2304 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2305 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
2306 if (sc->sc_splitmic) {
2307 /* +32 for RX key, +32+64 for RX key MIC */
2308 clrbit(sc->sc_keymap, keyix+32);
2309 clrbit(sc->sc_keymap, keyix+32+64);
2317 * Set the key cache contents for the specified key. Key cache
2318 * slot(s) must already have been allocated by ath_key_alloc.
2321 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k,
2322 const u_int8_t mac[IEEE80211_ADDR_LEN])
2324 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2326 return ath_keyset(sc, k, vap->iv_bss);
2330 * Block/unblock tx+rx processing while a key change is done.
2331 * We assume the caller serializes key management operations
2332 * so we only need to worry about synchronization with other
2333 * uses that originate in the driver.
2336 ath_key_update_begin(struct ieee80211vap *vap)
2338 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2339 struct ath_softc *sc = ifp->if_softc;
2341 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2342 taskqueue_block(sc->sc_tq);
2343 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
2347 ath_key_update_end(struct ieee80211vap *vap)
2349 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2350 struct ath_softc *sc = ifp->if_softc;
2352 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2353 IF_UNLOCK(&ifp->if_snd);
2354 taskqueue_unblock(sc->sc_tq);
2358 * Calculate the receive filter according to the
2359 * operating mode and state:
2361 * o always accept unicast, broadcast, and multicast traffic
2362 * o accept PHY error frames when hardware doesn't have MIB support
2363 * to count and we need them for ANI (sta mode only until recently)
2364 * and we are not scanning (ANI is disabled)
2365 * NB: older hal's add rx filter bits out of sight and we need to
2366 * blindly preserve them
2367 * o probe request frames are accepted only when operating in
2368 * hostap, adhoc, mesh, or monitor modes
2369 * o enable promiscuous mode
2370 * - when in monitor mode
2371 * - if interface marked PROMISC (assumes bridge setting is filtered)
2373 * - when operating in station mode for collecting rssi data when
2374 * the station is otherwise quiet, or
2375 * - when operating in adhoc mode so the 802.11 layer creates
2376 * node table entries for peers,
2378 * - when doing s/w beacon miss (e.g. for ap+sta)
2379 * - when operating in ap mode in 11g to detect overlapping bss that
2380 * require protection
2381 * - when operating in mesh mode to detect neighbors
2382 * o accept control frames:
2383 * - when in monitor mode
2384 * XXX BAR frames for 11n
2385 * XXX HT protection for 11n
2388 ath_calcrxfilter(struct ath_softc *sc)
2390 struct ifnet *ifp = sc->sc_ifp;
2391 struct ieee80211com *ic = ifp->if_l2com;
2394 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
2395 if (!sc->sc_needmib && !sc->sc_scanning)
2396 rfilt |= HAL_RX_FILTER_PHYERR;
2397 if (ic->ic_opmode != IEEE80211_M_STA)
2398 rfilt |= HAL_RX_FILTER_PROBEREQ;
2399 /* XXX ic->ic_monvaps != 0? */
2400 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC))
2401 rfilt |= HAL_RX_FILTER_PROM;
2402 if (ic->ic_opmode == IEEE80211_M_STA ||
2403 ic->ic_opmode == IEEE80211_M_IBSS ||
2404 sc->sc_swbmiss || sc->sc_scanning)
2405 rfilt |= HAL_RX_FILTER_BEACON;
2407 * NB: We don't recalculate the rx filter when
2408 * ic_protmode changes; otherwise we could do
2409 * this only when ic_protmode != NONE.
2411 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
2412 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
2413 rfilt |= HAL_RX_FILTER_BEACON;
2414 if (sc->sc_nmeshvaps) {
2415 rfilt |= HAL_RX_FILTER_BEACON;
2416 if (sc->sc_hasbmatch)
2417 rfilt |= HAL_RX_FILTER_BSSID;
2419 rfilt |= HAL_RX_FILTER_PROM;
2421 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2422 rfilt |= HAL_RX_FILTER_CONTROL;
2423 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n",
2424 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags);
2429 ath_update_promisc(struct ifnet *ifp)
2431 struct ath_softc *sc = ifp->if_softc;
2434 /* configure rx filter */
2435 rfilt = ath_calcrxfilter(sc);
2436 ath_hal_setrxfilter(sc->sc_ah, rfilt);
2438 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
2442 ath_update_mcast(struct ifnet *ifp)
2444 struct ath_softc *sc = ifp->if_softc;
2447 /* calculate and install multicast filter */
2448 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2449 struct ifmultiaddr *ifma;
2451 * Merge multicast addresses to form the hardware filter.
2453 mfilt[0] = mfilt[1] = 0;
2454 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
2455 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2460 /* calculate XOR of eight 6bit values */
2461 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
2462 val = LE_READ_4(dl + 0);
2463 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2464 val = LE_READ_4(dl + 3);
2465 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2467 mfilt[pos / 32] |= (1 << (pos % 32));
2469 if_maddr_runlock(ifp);
2471 mfilt[0] = mfilt[1] = ~0;
2472 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
2473 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
2474 __func__, mfilt[0], mfilt[1]);
2478 ath_mode_init(struct ath_softc *sc)
2480 struct ifnet *ifp = sc->sc_ifp;
2481 struct ath_hal *ah = sc->sc_ah;
2484 /* configure rx filter */
2485 rfilt = ath_calcrxfilter(sc);
2486 ath_hal_setrxfilter(ah, rfilt);
2488 /* configure operational mode */
2489 ath_hal_setopmode(ah);
2491 /* handle any link-level address change */
2492 ath_hal_setmac(ah, IF_LLADDR(ifp));
2494 /* calculate and install multicast filter */
2495 ath_update_mcast(ifp);
2499 * Set the slot time based on the current setting.
2502 ath_setslottime(struct ath_softc *sc)
2504 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2505 struct ath_hal *ah = sc->sc_ah;
2508 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
2510 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
2512 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
2513 /* honor short/long slot time only in 11g */
2514 /* XXX shouldn't honor on pure g or turbo g channel */
2515 if (ic->ic_flags & IEEE80211_F_SHSLOT)
2516 usec = HAL_SLOT_TIME_9;
2518 usec = HAL_SLOT_TIME_20;
2520 usec = HAL_SLOT_TIME_9;
2522 DPRINTF(sc, ATH_DEBUG_RESET,
2523 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
2524 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
2525 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
2527 ath_hal_setslottime(ah, usec);
2528 sc->sc_updateslot = OK;
2532 * Callback from the 802.11 layer to update the
2533 * slot time based on the current setting.
2536 ath_updateslot(struct ifnet *ifp)
2538 struct ath_softc *sc = ifp->if_softc;
2539 struct ieee80211com *ic = ifp->if_l2com;
2542 * When not coordinating the BSS, change the hardware
2543 * immediately. For other operation we defer the change
2544 * until beacon updates have propagated to the stations.
2546 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
2547 ic->ic_opmode == IEEE80211_M_MBSS)
2548 sc->sc_updateslot = UPDATE;
2550 ath_setslottime(sc);
2554 * Setup a h/w transmit queue for beacons.
2557 ath_beaconq_setup(struct ath_hal *ah)
2561 memset(&qi, 0, sizeof(qi));
2562 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2563 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2564 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2565 /* NB: for dynamic turbo, don't enable any other interrupts */
2566 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
2567 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
2571 * Setup the transmit queue parameters for the beacon queue.
2574 ath_beaconq_config(struct ath_softc *sc)
2576 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
2577 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2578 struct ath_hal *ah = sc->sc_ah;
2581 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
2582 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
2583 ic->ic_opmode == IEEE80211_M_MBSS) {
2585 * Always burst out beacon and CAB traffic.
2587 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
2588 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
2589 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
2591 struct wmeParams *wmep =
2592 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
2594 * Adhoc mode; important thing is to use 2x cwmin.
2596 qi.tqi_aifs = wmep->wmep_aifsn;
2597 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
2598 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
2601 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
2602 device_printf(sc->sc_dev, "unable to update parameters for "
2603 "beacon hardware queue!\n");
2606 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
2609 #undef ATH_EXPONENT_TO_VALUE
2613 * Allocate and setup an initial beacon frame.
2616 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
2618 struct ieee80211vap *vap = ni->ni_vap;
2619 struct ath_vap *avp = ATH_VAP(vap);
2625 if (bf->bf_m != NULL) {
2626 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2630 if (bf->bf_node != NULL) {
2631 ieee80211_free_node(bf->bf_node);
2636 * NB: the beacon data buffer must be 32-bit aligned;
2637 * we assume the mbuf routines will return us something
2638 * with this alignment (perhaps should assert).
2640 m = ieee80211_beacon_alloc(ni, &avp->av_boff);
2642 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__);
2643 sc->sc_stats.ast_be_nombuf++;
2646 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2647 bf->bf_segs, &bf->bf_nseg,
2650 device_printf(sc->sc_dev,
2651 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n",
2658 * Calculate a TSF adjustment factor required for staggered
2659 * beacons. Note that we assume the format of the beacon
2660 * frame leaves the tstamp field immediately following the
2663 if (sc->sc_stagbeacons && avp->av_bslot > 0) {
2665 struct ieee80211_frame *wh;
2668 * The beacon interval is in TU's; the TSF is in usecs.
2669 * We figure out how many TU's to add to align the timestamp
2670 * then convert to TSF units and handle byte swapping before
2671 * inserting it in the frame. The hardware will then add this
2672 * each time a beacon frame is sent. Note that we align vap's
2673 * 1..N and leave vap 0 untouched. This means vap 0 has a
2674 * timestamp in one beacon interval while the others get a
2675 * timstamp aligned to the next interval.
2677 tsfadjust = ni->ni_intval *
2678 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF;
2679 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */
2681 DPRINTF(sc, ATH_DEBUG_BEACON,
2682 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n",
2683 __func__, sc->sc_stagbeacons ? "stagger" : "burst",
2684 avp->av_bslot, ni->ni_intval,
2685 (long long unsigned) le64toh(tsfadjust));
2687 wh = mtod(m, struct ieee80211_frame *);
2688 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
2691 bf->bf_node = ieee80211_ref_node(ni);
2697 * Setup the beacon frame for transmit.
2700 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
2702 #define USE_SHPREAMBLE(_ic) \
2703 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
2704 == IEEE80211_F_SHPREAMBLE)
2705 struct ieee80211_node *ni = bf->bf_node;
2706 struct ieee80211com *ic = ni->ni_ic;
2707 struct mbuf *m = bf->bf_m;
2708 struct ath_hal *ah = sc->sc_ah;
2709 struct ath_desc *ds;
2711 const HAL_RATE_TABLE *rt;
2714 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
2715 __func__, m, m->m_len);
2717 /* setup descriptors */
2720 flags = HAL_TXDESC_NOACK;
2721 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
2722 ds->ds_link = bf->bf_daddr; /* self-linked */
2723 flags |= HAL_TXDESC_VEOL;
2725 * Let hardware handle antenna switching.
2727 antenna = sc->sc_txantenna;
2731 * Switch antenna every 4 beacons.
2732 * XXX assumes two antenna
2734 if (sc->sc_txantenna != 0)
2735 antenna = sc->sc_txantenna;
2736 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0)
2737 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1);
2739 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
2742 KASSERT(bf->bf_nseg == 1,
2743 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
2744 ds->ds_data = bf->bf_segs[0].ds_addr;
2746 * Calculate rate code.
2747 * XXX everything at min xmit rate
2750 rt = sc->sc_currates;
2751 rate = rt->info[rix].rateCode;
2752 if (USE_SHPREAMBLE(ic))
2753 rate |= rt->info[rix].shortPreamble;
2754 ath_hal_setuptxdesc(ah, ds
2755 , m->m_len + IEEE80211_CRC_LEN /* frame length */
2756 , sizeof(struct ieee80211_frame)/* header length */
2757 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
2758 , ni->ni_txpower /* txpower XXX */
2759 , rate, 1 /* series 0 rate/tries */
2760 , HAL_TXKEYIX_INVALID /* no encryption */
2761 , antenna /* antenna mode */
2762 , flags /* no ack, veol for beacons */
2763 , 0 /* rts/cts rate */
2764 , 0 /* rts/cts duration */
2766 /* NB: beacon's BufLen must be a multiple of 4 bytes */
2767 ath_hal_filltxdesc(ah, ds
2768 , roundup(m->m_len, 4) /* buffer length */
2769 , AH_TRUE /* first segment */
2770 , AH_TRUE /* last segment */
2771 , ds /* first descriptor */
2776 #undef USE_SHPREAMBLE
2780 ath_beacon_update(struct ieee80211vap *vap, int item)
2782 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff;
2784 setbit(bo->bo_flags, item);
2788 * Append the contents of src to dst; both queues
2789 * are assumed to be locked.
2792 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
2794 STAILQ_CONCAT(&dst->axq_q, &src->axq_q);
2795 dst->axq_link = src->axq_link;
2796 src->axq_link = NULL;
2797 dst->axq_depth += src->axq_depth;
2802 * Transmit a beacon frame at SWBA. Dynamic updates to the
2803 * frame contents are done as needed and the slot time is
2804 * also adjusted based on current state.
2807 ath_beacon_proc(void *arg, int pending)
2809 struct ath_softc *sc = arg;
2810 struct ath_hal *ah = sc->sc_ah;
2811 struct ieee80211vap *vap;
2816 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
2819 * Check if the previous beacon has gone out. If
2820 * not don't try to post another, skip this period
2821 * and wait for the next. Missed beacons indicate
2822 * a problem and should not occur. If we miss too
2823 * many consecutive beacons reset the device.
2825 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
2826 sc->sc_bmisscount++;
2827 DPRINTF(sc, ATH_DEBUG_BEACON,
2828 "%s: missed %u consecutive beacons\n",
2829 __func__, sc->sc_bmisscount);
2830 if (sc->sc_bmisscount >= ath_bstuck_threshold)
2831 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
2834 if (sc->sc_bmisscount != 0) {
2835 DPRINTF(sc, ATH_DEBUG_BEACON,
2836 "%s: resume beacon xmit after %u misses\n",
2837 __func__, sc->sc_bmisscount);
2838 sc->sc_bmisscount = 0;
2841 if (sc->sc_stagbeacons) { /* staggered beacons */
2842 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2845 tsftu = ath_hal_gettsf32(ah) >> 10;
2847 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval;
2848 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF];
2850 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
2851 bf = ath_beacon_generate(sc, vap);
2853 bfaddr = bf->bf_daddr;
2855 } else { /* burst'd beacons */
2856 uint32_t *bflink = &bfaddr;
2858 for (slot = 0; slot < ATH_BCBUF; slot++) {
2859 vap = sc->sc_bslot[slot];
2860 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
2861 bf = ath_beacon_generate(sc, vap);
2863 *bflink = bf->bf_daddr;
2864 bflink = &bf->bf_desc->ds_link;
2868 *bflink = 0; /* terminate list */
2872 * Handle slot time change when a non-ERP station joins/leaves
2873 * an 11g network. The 802.11 layer notifies us via callback,
2874 * we mark updateslot, then wait one beacon before effecting
2875 * the change. This gives associated stations at least one
2876 * beacon interval to note the state change.
2879 if (sc->sc_updateslot == UPDATE) {
2880 sc->sc_updateslot = COMMIT; /* commit next beacon */
2881 sc->sc_slotupdate = slot;
2882 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
2883 ath_setslottime(sc); /* commit change to h/w */
2886 * Check recent per-antenna transmit statistics and flip
2887 * the default antenna if noticeably more frames went out
2888 * on the non-default antenna.
2889 * XXX assumes 2 anntenae
2891 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) {
2892 otherant = sc->sc_defant & 1 ? 2 : 1;
2893 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
2894 ath_setdefantenna(sc, otherant);
2895 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
2900 * Stop any current dma and put the new frame on the queue.
2901 * This should never fail since we check above that no frames
2902 * are still pending on the queue.
2904 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2905 DPRINTF(sc, ATH_DEBUG_ANY,
2906 "%s: beacon queue %u did not stop?\n",
2907 __func__, sc->sc_bhalq);
2909 /* NB: cabq traffic should already be queued and primed */
2910 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);
2911 ath_hal_txstart(ah, sc->sc_bhalq);
2913 sc->sc_stats.ast_be_xmit++;
2917 static struct ath_buf *
2918 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
2920 struct ath_vap *avp = ATH_VAP(vap);
2921 struct ath_txq *cabq = sc->sc_cabq;
2926 KASSERT(vap->iv_state >= IEEE80211_S_RUN,
2927 ("not running, state %d", vap->iv_state));
2928 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
2931 * Update dynamic beacon contents. If this returns
2932 * non-zero then we need to remap the memory because
2933 * the beacon frame changed size (probably because
2934 * of the TIM bitmap).
2938 nmcastq = avp->av_mcastq.axq_depth;
2939 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) {
2940 /* XXX too conservative? */
2941 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2942 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2943 bf->bf_segs, &bf->bf_nseg,
2946 if_printf(vap->iv_ifp,
2947 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
2952 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) {
2953 DPRINTF(sc, ATH_DEBUG_BEACON,
2954 "%s: cabq did not drain, mcastq %u cabq %u\n",
2955 __func__, nmcastq, cabq->axq_depth);
2956 sc->sc_stats.ast_cabq_busy++;
2957 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
2959 * CABQ traffic from a previous vap is still pending.
2960 * We must drain the q before this beacon frame goes
2961 * out as otherwise this vap's stations will get cab
2962 * frames from a different vap.
2963 * XXX could be slow causing us to miss DBA
2965 ath_tx_draintxq(sc, cabq);
2968 ath_beacon_setup(sc, bf);
2969 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2972 * Enable the CAB queue before the beacon queue to
2973 * insure cab frames are triggered by this beacon.
2975 if (avp->av_boff.bo_tim[4] & 1) {
2976 struct ath_hal *ah = sc->sc_ah;
2978 /* NB: only at DTIM */
2980 ATH_TXQ_LOCK(&avp->av_mcastq);
2982 struct ath_buf *bfm;
2985 * Move frames from the s/w mcast q to the h/w cab q.
2988 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q);
2989 if (cabq->axq_link != NULL) {
2990 *cabq->axq_link = bfm->bf_daddr;
2992 ath_hal_puttxbuf(ah, cabq->axq_qnum,
2994 ath_txqmove(cabq, &avp->av_mcastq);
2996 sc->sc_stats.ast_cabq_xmit += nmcastq;
2998 /* NB: gated by beacon so safe to start here */
2999 ath_hal_txstart(ah, cabq->axq_qnum);
3000 ATH_TXQ_UNLOCK(cabq);
3001 ATH_TXQ_UNLOCK(&avp->av_mcastq);
3007 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap)
3009 struct ath_vap *avp = ATH_VAP(vap);
3010 struct ath_hal *ah = sc->sc_ah;
3015 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
3018 * Update dynamic beacon contents. If this returns
3019 * non-zero then we need to remap the memory because
3020 * the beacon frame changed size (probably because
3021 * of the TIM bitmap).
3025 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) {
3026 /* XXX too conservative? */
3027 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3028 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
3029 bf->bf_segs, &bf->bf_nseg,
3032 if_printf(vap->iv_ifp,
3033 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
3038 ath_beacon_setup(sc, bf);
3039 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3041 /* NB: caller is known to have already stopped tx dma */
3042 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
3043 ath_hal_txstart(ah, sc->sc_bhalq);
3047 * Reset the hardware after detecting beacons have stopped.
3050 ath_bstuck_proc(void *arg, int pending)
3052 struct ath_softc *sc = arg;
3053 struct ifnet *ifp = sc->sc_ifp;
3055 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3057 sc->sc_stats.ast_bstuck++;
3062 * Reclaim beacon resources and return buffer to the pool.
3065 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf)
3068 if (bf->bf_m != NULL) {
3069 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3073 if (bf->bf_node != NULL) {
3074 ieee80211_free_node(bf->bf_node);
3077 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list);
3081 * Reclaim beacon resources.
3084 ath_beacon_free(struct ath_softc *sc)
3088 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
3089 if (bf->bf_m != NULL) {
3090 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3094 if (bf->bf_node != NULL) {
3095 ieee80211_free_node(bf->bf_node);
3102 * Configure the beacon and sleep timers.
3104 * When operating as an AP this resets the TSF and sets
3105 * up the hardware to notify us when we need to issue beacons.
3107 * When operating in station mode this sets up the beacon
3108 * timers according to the timestamp of the last received
3109 * beacon and the current TSF, configures PCF and DTIM
3110 * handling, programs the sleep registers so the hardware
3111 * will wakeup in time to receive beacons, and configures
3112 * the beacon miss handling so we'll receive a BMISS
3113 * interrupt when we stop seeing beacons from the AP
3114 * we've associated with.
3117 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap)
3119 #define TSF_TO_TU(_h,_l) \
3120 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
3122 struct ath_hal *ah = sc->sc_ah;
3123 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3124 struct ieee80211_node *ni;
3125 u_int32_t nexttbtt, intval, tsftu;
3129 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
3132 /* extract tstamp from last beacon and convert to TU */
3133 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
3134 LE_READ_4(ni->ni_tstamp.data));
3135 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3136 ic->ic_opmode == IEEE80211_M_MBSS) {
3138 * For multi-bss ap/mesh support beacons are either staggered
3139 * evenly over N slots or burst together. For the former
3140 * arrange for the SWBA to be delivered for each slot.
3141 * Slots that are not occupied will generate nothing.
3143 /* NB: the beacon interval is kept internally in TU's */
3144 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3145 if (sc->sc_stagbeacons)
3146 intval /= ATH_BCBUF;
3148 /* NB: the beacon interval is kept internally in TU's */
3149 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3151 if (nexttbtt == 0) /* e.g. for ap mode */
3153 else if (intval) /* NB: can be 0 for monitor mode */
3154 nexttbtt = roundup(nexttbtt, intval);
3155 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
3156 __func__, nexttbtt, intval, ni->ni_intval);
3157 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) {
3158 HAL_BEACON_STATE bs;
3159 int dtimperiod, dtimcount;
3160 int cfpperiod, cfpcount;
3163 * Setup dtim and cfp parameters according to
3164 * last beacon we received (which may be none).
3166 dtimperiod = ni->ni_dtim_period;
3167 if (dtimperiod <= 0) /* NB: 0 if not known */
3169 dtimcount = ni->ni_dtim_count;
3170 if (dtimcount >= dtimperiod) /* NB: sanity check */
3171 dtimcount = 0; /* XXX? */
3172 cfpperiod = 1; /* NB: no PCF support yet */
3175 * Pull nexttbtt forward to reflect the current
3176 * TSF and calculate dtim+cfp state for the result.
3178 tsf = ath_hal_gettsf64(ah);
3179 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3182 if (--dtimcount < 0) {
3183 dtimcount = dtimperiod - 1;
3185 cfpcount = cfpperiod - 1;
3187 } while (nexttbtt < tsftu);
3188 memset(&bs, 0, sizeof(bs));
3189 bs.bs_intval = intval;
3190 bs.bs_nexttbtt = nexttbtt;
3191 bs.bs_dtimperiod = dtimperiod*intval;
3192 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
3193 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
3194 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
3195 bs.bs_cfpmaxduration = 0;
3198 * The 802.11 layer records the offset to the DTIM
3199 * bitmap while receiving beacons; use it here to
3200 * enable h/w detection of our AID being marked in
3201 * the bitmap vector (to indicate frames for us are
3202 * pending at the AP).
3203 * XXX do DTIM handling in s/w to WAR old h/w bugs
3204 * XXX enable based on h/w rev for newer chips
3206 bs.bs_timoffset = ni->ni_timoff;
3209 * Calculate the number of consecutive beacons to miss
3210 * before taking a BMISS interrupt.
3211 * Note that we clamp the result to at most 10 beacons.
3213 bs.bs_bmissthreshold = vap->iv_bmissthreshold;
3214 if (bs.bs_bmissthreshold > 10)
3215 bs.bs_bmissthreshold = 10;
3216 else if (bs.bs_bmissthreshold <= 0)
3217 bs.bs_bmissthreshold = 1;
3220 * Calculate sleep duration. The configuration is
3221 * given in ms. We insure a multiple of the beacon
3222 * period is used. Also, if the sleep duration is
3223 * greater than the DTIM period then it makes senses
3224 * to make it a multiple of that.
3226 * XXX fixed at 100ms
3228 bs.bs_sleepduration =
3229 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
3230 if (bs.bs_sleepduration > bs.bs_dtimperiod)
3231 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
3233 DPRINTF(sc, ATH_DEBUG_BEACON,
3234 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
3241 , bs.bs_bmissthreshold
3242 , bs.bs_sleepduration
3244 , bs.bs_cfpmaxduration
3248 ath_hal_intrset(ah, 0);
3249 ath_hal_beacontimers(ah, &bs);
3250 sc->sc_imask |= HAL_INT_BMISS;
3251 ath_hal_intrset(ah, sc->sc_imask);
3253 ath_hal_intrset(ah, 0);
3254 if (nexttbtt == intval)
3255 intval |= HAL_BEACON_RESET_TSF;
3256 if (ic->ic_opmode == IEEE80211_M_IBSS) {
3258 * In IBSS mode enable the beacon timers but only
3259 * enable SWBA interrupts if we need to manually
3260 * prepare beacon frames. Otherwise we use a
3261 * self-linked tx descriptor and let the hardware
3264 intval |= HAL_BEACON_ENA;
3265 if (!sc->sc_hasveol)
3266 sc->sc_imask |= HAL_INT_SWBA;
3267 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
3269 * Pull nexttbtt forward to reflect
3272 tsf = ath_hal_gettsf64(ah);
3273 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3276 } while (nexttbtt < tsftu);
3278 ath_beaconq_config(sc);
3279 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3280 ic->ic_opmode == IEEE80211_M_MBSS) {
3282 * In AP/mesh mode we enable the beacon timers
3283 * and SWBA interrupts to prepare beacon frames.
3285 intval |= HAL_BEACON_ENA;
3286 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
3287 ath_beaconq_config(sc);
3289 ath_hal_beaconinit(ah, nexttbtt, intval);
3290 sc->sc_bmisscount = 0;
3291 ath_hal_intrset(ah, sc->sc_imask);
3293 * When using a self-linked beacon descriptor in
3294 * ibss mode load it once here.
3296 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
3297 ath_beacon_start_adhoc(sc, vap);
3299 sc->sc_syncbeacon = 0;
3305 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3307 bus_addr_t *paddr = (bus_addr_t*) arg;
3308 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3309 *paddr = segs->ds_addr;
3313 ath_descdma_setup(struct ath_softc *sc,
3314 struct ath_descdma *dd, ath_bufhead *head,
3315 const char *name, int nbuf, int ndesc)
3317 #define DS2PHYS(_dd, _ds) \
3318 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3319 struct ifnet *ifp = sc->sc_ifp;
3320 struct ath_desc *ds;
3322 int i, bsize, error;
3324 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
3325 __func__, name, nbuf, ndesc);
3328 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
3331 * Setup DMA descriptor area.
3333 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3334 PAGE_SIZE, 0, /* alignment, bounds */
3335 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3336 BUS_SPACE_MAXADDR, /* highaddr */
3337 NULL, NULL, /* filter, filterarg */
3338 dd->dd_desc_len, /* maxsize */
3340 dd->dd_desc_len, /* maxsegsize */
3341 BUS_DMA_ALLOCNOW, /* flags */
3342 NULL, /* lockfunc */
3346 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3350 /* allocate descriptors */
3351 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
3353 if_printf(ifp, "unable to create dmamap for %s descriptors, "
3354 "error %u\n", dd->dd_name, error);
3358 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3359 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3362 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3363 "error %u\n", nbuf * ndesc, dd->dd_name, error);
3367 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3368 dd->dd_desc, dd->dd_desc_len,
3369 ath_load_cb, &dd->dd_desc_paddr,
3372 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3373 dd->dd_name, error);
3378 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3379 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
3380 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
3382 /* allocate rx buffers */
3383 bsize = sizeof(struct ath_buf) * nbuf;
3384 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3386 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3387 dd->dd_name, bsize);
3393 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
3395 bf->bf_daddr = DS2PHYS(dd, ds);
3396 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3399 if_printf(ifp, "unable to create dmamap for %s "
3400 "buffer %u, error %u\n", dd->dd_name, i, error);
3401 ath_descdma_cleanup(sc, dd, head);
3404 STAILQ_INSERT_TAIL(head, bf, bf_list);
3408 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3410 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3412 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3414 bus_dma_tag_destroy(dd->dd_dmat);
3415 memset(dd, 0, sizeof(*dd));
3421 ath_descdma_cleanup(struct ath_softc *sc,
3422 struct ath_descdma *dd, ath_bufhead *head)
3425 struct ieee80211_node *ni;
3427 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3428 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3429 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3430 bus_dma_tag_destroy(dd->dd_dmat);
3432 STAILQ_FOREACH(bf, head, bf_list) {
3437 if (bf->bf_dmamap != NULL) {
3438 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
3439 bf->bf_dmamap = NULL;
3445 * Reclaim node reference.
3447 ieee80211_free_node(ni);
3452 free(dd->dd_bufptr, M_ATHDEV);
3453 memset(dd, 0, sizeof(*dd));
3457 ath_desc_alloc(struct ath_softc *sc)
3461 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
3462 "rx", ath_rxbuf, 1);
3466 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3467 "tx", ath_txbuf, ATH_TXDESC);
3469 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3473 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3474 "beacon", ATH_BCBUF, 1);
3476 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3477 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3484 ath_desc_free(struct ath_softc *sc)
3487 if (sc->sc_bdma.dd_desc_len != 0)
3488 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3489 if (sc->sc_txdma.dd_desc_len != 0)
3490 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3491 if (sc->sc_rxdma.dd_desc_len != 0)
3492 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3495 static struct ieee80211_node *
3496 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3498 struct ieee80211com *ic = vap->iv_ic;
3499 struct ath_softc *sc = ic->ic_ifp->if_softc;
3500 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3501 struct ath_node *an;
3503 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3508 ath_rate_node_init(sc, an);
3510 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
3511 return &an->an_node;
3515 ath_node_free(struct ieee80211_node *ni)
3517 struct ieee80211com *ic = ni->ni_ic;
3518 struct ath_softc *sc = ic->ic_ifp->if_softc;
3520 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
3522 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3523 sc->sc_node_free(ni);
3527 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3529 struct ieee80211com *ic = ni->ni_ic;
3530 struct ath_softc *sc = ic->ic_ifp->if_softc;
3531 struct ath_hal *ah = sc->sc_ah;
3533 *rssi = ic->ic_node_getrssi(ni);
3534 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3535 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3537 *noise = -95; /* nominally correct */
3541 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
3543 struct ath_hal *ah = sc->sc_ah;
3546 struct ath_desc *ds;
3551 * NB: by assigning a page to the rx dma buffer we
3552 * implicitly satisfy the Atheros requirement that
3553 * this buffer be cache-line-aligned and sized to be
3554 * multiple of the cache line size. Not doing this
3555 * causes weird stuff to happen (for the 5210 at least).
3557 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3559 DPRINTF(sc, ATH_DEBUG_ANY,
3560 "%s: no mbuf/cluster\n", __func__);
3561 sc->sc_stats.ast_rx_nombuf++;
3564 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
3566 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
3568 bf->bf_segs, &bf->bf_nseg,
3571 DPRINTF(sc, ATH_DEBUG_ANY,
3572 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
3574 sc->sc_stats.ast_rx_busdma++;
3578 KASSERT(bf->bf_nseg == 1,
3579 ("multi-segment packet; nseg %u", bf->bf_nseg));
3582 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
3585 * Setup descriptors. For receive we always terminate
3586 * the descriptor list with a self-linked entry so we'll
3587 * not get overrun under high load (as can happen with a
3588 * 5212 when ANI processing enables PHY error frames).
3590 * To insure the last descriptor is self-linked we create
3591 * each descriptor as self-linked and add it to the end. As
3592 * each additional descriptor is added the previous self-linked
3593 * entry is ``fixed'' naturally. This should be safe even
3594 * if DMA is happening. When processing RX interrupts we
3595 * never remove/process the last, self-linked, entry on the
3596 * descriptor list. This insures the hardware always has
3597 * someplace to write a new frame.
3600 ds->ds_link = bf->bf_daddr; /* link to self */
3601 ds->ds_data = bf->bf_segs[0].ds_addr;
3602 ath_hal_setuprxdesc(ah, ds
3603 , m->m_len /* buffer size */
3607 if (sc->sc_rxlink != NULL)
3608 *sc->sc_rxlink = bf->bf_daddr;
3609 sc->sc_rxlink = &ds->ds_link;
3614 * Extend 15-bit time stamp from rx descriptor to
3615 * a full 64-bit TSF using the specified TSF.
3617 static __inline u_int64_t
3618 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf)
3620 if ((tsf & 0x7fff) < rstamp)
3622 return ((tsf &~ 0x7fff) | rstamp);
3626 * Intercept management frames to collect beacon rssi data
3627 * and to do ibss merges.
3630 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
3631 int subtype, int rssi, int nf)
3633 struct ieee80211vap *vap = ni->ni_vap;
3634 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
3637 * Call up first so subsequent work can use information
3638 * potentially stored in the node (e.g. for ibss merge).
3640 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf);
3642 case IEEE80211_FC0_SUBTYPE_BEACON:
3643 /* update rssi statistics for use by the hal */
3644 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
3645 if (sc->sc_syncbeacon &&
3646 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) {
3648 * Resync beacon timers using the tsf of the beacon
3649 * frame we just received.
3651 ath_beacon_config(sc, vap);
3654 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3655 if (vap->iv_opmode == IEEE80211_M_IBSS &&
3656 vap->iv_state == IEEE80211_S_RUN) {
3657 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
3658 u_int64_t tsf = ath_extend_tsf(rstamp,
3659 ath_hal_gettsf64(sc->sc_ah));
3661 * Handle ibss merge as needed; check the tsf on the
3662 * frame before attempting the merge. The 802.11 spec
3663 * says the station should change it's bssid to match
3664 * the oldest station with the same ssid, where oldest
3665 * is determined by the tsf. Note that hardware
3666 * reconfiguration happens through callback to
3667 * ath_newstate as the state machine will go from
3668 * RUN -> RUN when this happens.
3670 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
3671 DPRINTF(sc, ATH_DEBUG_STATE,
3672 "ibss merge, rstamp %u tsf %ju "
3673 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
3674 (uintmax_t)ni->ni_tstamp.tsf);
3675 (void) ieee80211_ibss_merge(ni);
3683 * Set the default antenna.
3686 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3688 struct ath_hal *ah = sc->sc_ah;
3690 /* XXX block beacon interrupts */
3691 ath_hal_setdefantenna(ah, antenna);
3692 if (sc->sc_defant != antenna)
3693 sc->sc_stats.ast_ant_defswitch++;
3694 sc->sc_defant = antenna;
3695 sc->sc_rxotherant = 0;
3699 ath_rx_tap(struct ifnet *ifp, struct mbuf *m,
3700 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
3702 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
3703 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
3704 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
3705 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
3706 struct ath_softc *sc = ifp->if_softc;
3707 const HAL_RATE_TABLE *rt;
3710 rt = sc->sc_currates;
3711 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3712 rix = rt->rateCodeToIndex[rs->rs_rate];
3713 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
3714 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
3715 #ifdef AH_SUPPORT_AR5416
3716 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
3717 if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
3718 struct ieee80211com *ic = ifp->if_l2com;
3720 if ((rs->rs_flags & HAL_RX_2040) == 0)
3721 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
3722 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
3723 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
3725 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
3726 if ((rs->rs_flags & HAL_RX_GI) == 0)
3727 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
3730 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf));
3731 if (rs->rs_status & HAL_RXERR_CRC)
3732 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
3733 /* XXX propagate other error flags from descriptor */
3734 sc->sc_rx_th.wr_antnoise = nf;
3735 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
3736 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
3744 ath_handle_micerror(struct ieee80211com *ic,
3745 struct ieee80211_frame *wh, int keyix)
3747 struct ieee80211_node *ni;
3749 /* XXX recheck MIC to deal w/ chips that lie */
3750 /* XXX discard MIC errors on !data frames */
3751 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
3753 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
3754 ieee80211_free_node(ni);
3759 ath_rx_proc(void *arg, int npending)
3761 #define PA2DESC(_sc, _pa) \
3762 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
3763 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
3764 struct ath_softc *sc = arg;
3766 struct ifnet *ifp = sc->sc_ifp;
3767 struct ieee80211com *ic = ifp->if_l2com;
3768 struct ath_hal *ah = sc->sc_ah;
3769 struct ath_desc *ds;
3770 struct ath_rx_status *rs;
3772 struct ieee80211_node *ni;
3773 int len, type, ngood;
3779 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
3781 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
3782 sc->sc_stats.ast_rx_noise = nf;
3783 tsf = ath_hal_gettsf64(ah);
3785 bf = STAILQ_FIRST(&sc->sc_rxbuf);
3786 if (bf == NULL) { /* NB: shouldn't happen */
3787 if_printf(ifp, "%s: no buffer!\n", __func__);
3791 if (m == NULL) { /* NB: shouldn't happen */
3793 * If mbuf allocation failed previously there
3794 * will be no mbuf; try again to re-populate it.
3796 /* XXX make debug msg */
3797 if_printf(ifp, "%s: no mbuf!\n", __func__);
3798 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3802 if (ds->ds_link == bf->bf_daddr) {
3803 /* NB: never process the self-linked entry at the end */
3806 /* XXX sync descriptor memory */
3808 * Must provide the virtual address of the current
3809 * descriptor, the physical address, and the virtual
3810 * address of the next descriptor in the h/w chain.
3811 * This allows the HAL to look ahead to see if the
3812 * hardware is done with a descriptor by checking the
3813 * done bit in the following descriptor and the address
3814 * of the current descriptor the DMA engine is working
3815 * on. All this is necessary because of our use of
3816 * a self-linked list to avoid rx overruns.
3818 rs = &bf->bf_status.ds_rxstat;
3819 status = ath_hal_rxprocdesc(ah, ds,
3820 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
3822 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
3823 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
3825 if (status == HAL_EINPROGRESS)
3827 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3828 if (rs->rs_status != 0) {
3829 if (rs->rs_status & HAL_RXERR_CRC)
3830 sc->sc_stats.ast_rx_crcerr++;
3831 if (rs->rs_status & HAL_RXERR_FIFO)
3832 sc->sc_stats.ast_rx_fifoerr++;
3833 if (rs->rs_status & HAL_RXERR_PHY) {
3834 sc->sc_stats.ast_rx_phyerr++;
3835 phyerr = rs->rs_phyerr & 0x1f;
3836 sc->sc_stats.ast_rx_phy[phyerr]++;
3837 goto rx_error; /* NB: don't count in ierrors */
3839 if (rs->rs_status & HAL_RXERR_DECRYPT) {
3841 * Decrypt error. If the error occurred
3842 * because there was no hardware key, then
3843 * let the frame through so the upper layers
3844 * can process it. This is necessary for 5210
3845 * parts which have no way to setup a ``clear''
3848 * XXX do key cache faulting
3850 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
3852 sc->sc_stats.ast_rx_badcrypt++;
3854 if (rs->rs_status & HAL_RXERR_MIC) {
3855 sc->sc_stats.ast_rx_badmic++;
3857 * Do minimal work required to hand off
3858 * the 802.11 header for notification.
3860 /* XXX frag's and qos frames */
3861 len = rs->rs_datalen;
3862 if (len >= sizeof (struct ieee80211_frame)) {
3863 bus_dmamap_sync(sc->sc_dmat,
3865 BUS_DMASYNC_POSTREAD);
3866 ath_handle_micerror(ic,
3867 mtod(m, struct ieee80211_frame *),
3869 rs->rs_keyix-32 : rs->rs_keyix);
3875 * Cleanup any pending partial frame.
3877 if (sc->sc_rxpending != NULL) {
3878 m_freem(sc->sc_rxpending);
3879 sc->sc_rxpending = NULL;
3882 * When a tap is present pass error frames
3883 * that have been requested. By default we
3884 * pass decrypt+mic errors but others may be
3885 * interesting (e.g. crc).
3887 if (ieee80211_radiotap_active(ic) &&
3888 (rs->rs_status & sc->sc_monpass)) {
3889 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3890 BUS_DMASYNC_POSTREAD);
3891 /* NB: bpf needs the mbuf length setup */
3892 len = rs->rs_datalen;
3893 m->m_pkthdr.len = m->m_len = len;
3894 ath_rx_tap(ifp, m, rs, tsf, nf);
3895 ieee80211_radiotap_rx_all(ic, m);
3897 /* XXX pass MIC errors up for s/w reclaculation */
3902 * Sync and unmap the frame. At this point we're
3903 * committed to passing the mbuf somewhere so clear
3904 * bf_m; this means a new mbuf must be allocated
3905 * when the rx descriptor is setup again to receive
3908 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3909 BUS_DMASYNC_POSTREAD);
3910 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3913 len = rs->rs_datalen;
3918 * Frame spans multiple descriptors; save
3919 * it for the next completed descriptor, it
3920 * will be used to construct a jumbogram.
3922 if (sc->sc_rxpending != NULL) {
3923 /* NB: max frame size is currently 2 clusters */
3924 sc->sc_stats.ast_rx_toobig++;
3925 m_freem(sc->sc_rxpending);
3927 m->m_pkthdr.rcvif = ifp;
3928 m->m_pkthdr.len = len;
3929 sc->sc_rxpending = m;
3931 } else if (sc->sc_rxpending != NULL) {
3933 * This is the second part of a jumbogram,
3934 * chain it to the first mbuf, adjust the
3935 * frame length, and clear the rxpending state.
3937 sc->sc_rxpending->m_next = m;
3938 sc->sc_rxpending->m_pkthdr.len += len;
3939 m = sc->sc_rxpending;
3940 sc->sc_rxpending = NULL;
3943 * Normal single-descriptor receive; setup
3944 * the rcvif and packet length.
3946 m->m_pkthdr.rcvif = ifp;
3947 m->m_pkthdr.len = len;
3951 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
3954 * Populate the rx status block. When there are bpf
3955 * listeners we do the additional work to provide
3956 * complete status. Otherwise we fill in only the
3957 * material required by ieee80211_input. Note that
3958 * noise setting is filled in above.
3960 if (ieee80211_radiotap_active(ic))
3961 ath_rx_tap(ifp, m, rs, tsf, nf);
3964 * From this point on we assume the frame is at least
3965 * as large as ieee80211_frame_min; verify that.
3967 if (len < IEEE80211_MIN_LEN) {
3968 if (!ieee80211_radiotap_active(ic)) {
3969 DPRINTF(sc, ATH_DEBUG_RECV,
3970 "%s: short packet %d\n", __func__, len);
3971 sc->sc_stats.ast_rx_tooshort++;
3973 /* NB: in particular this captures ack's */
3974 ieee80211_radiotap_rx_all(ic, m);
3980 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
3981 const HAL_RATE_TABLE *rt = sc->sc_currates;
3982 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
3984 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
3985 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
3988 m_adj(m, -IEEE80211_CRC_LEN);
3991 * Locate the node for sender, track state, and then
3992 * pass the (referenced) node up to the 802.11 layer
3995 ni = ieee80211_find_rxnode_withkey(ic,
3996 mtod(m, const struct ieee80211_frame_min *),
3997 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
3998 IEEE80211_KEYIX_NONE : rs->rs_keyix);
4001 * Sending station is known, dispatch directly.
4004 type = ieee80211_input(ni, m, rs->rs_rssi, nf);
4005 ieee80211_free_node(ni);
4007 * Arrange to update the last rx timestamp only for
4008 * frames from our ap when operating in station mode.
4009 * This assumes the rx key is always setup when
4012 if (ic->ic_opmode == IEEE80211_M_STA &&
4013 rs->rs_keyix != HAL_RXKEYIX_INVALID)
4016 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf);
4019 * Track rx rssi and do any rx antenna management.
4021 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
4022 if (sc->sc_diversity) {
4024 * When using fast diversity, change the default rx
4025 * antenna if diversity chooses the other antenna 3
4028 if (sc->sc_defant != rs->rs_antenna) {
4029 if (++sc->sc_rxotherant >= 3)
4030 ath_setdefantenna(sc, rs->rs_antenna);
4032 sc->sc_rxotherant = 0;
4034 if (sc->sc_softled) {
4036 * Blink for any data frame. Otherwise do a
4037 * heartbeat-style blink when idle. The latter
4038 * is mainly for station mode where we depend on
4039 * periodic beacon frames to trigger the poll event.
4041 if (type == IEEE80211_FC0_TYPE_DATA) {
4042 const HAL_RATE_TABLE *rt = sc->sc_currates;
4044 rt->rateCodeToIndex[rs->rs_rate]);
4045 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
4046 ath_led_event(sc, 0);
4049 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
4050 } while (ath_rxbuf_init(sc, bf) == 0);
4052 /* rx signal state monitoring */
4053 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
4055 sc->sc_lastrx = tsf;
4057 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
4058 #ifdef IEEE80211_SUPPORT_SUPERG
4059 ieee80211_ff_age_all(ic, 100);
4061 if (!IFQ_IS_EMPTY(&ifp->if_snd))
4068 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
4070 txq->axq_qnum = qnum;
4073 txq->axq_intrcnt = 0;
4074 txq->axq_link = NULL;
4075 STAILQ_INIT(&txq->axq_q);
4076 ATH_TXQ_LOCK_INIT(sc, txq);
4080 * Setup a h/w transmit queue.
4082 static struct ath_txq *
4083 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
4085 #define N(a) (sizeof(a)/sizeof(a[0]))
4086 struct ath_hal *ah = sc->sc_ah;
4090 memset(&qi, 0, sizeof(qi));
4091 qi.tqi_subtype = subtype;
4092 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
4093 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
4094 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
4096 * Enable interrupts only for EOL and DESC conditions.
4097 * We mark tx descriptors to receive a DESC interrupt
4098 * when a tx queue gets deep; otherwise waiting for the
4099 * EOL to reap descriptors. Note that this is done to
4100 * reduce interrupt load and this only defers reaping
4101 * descriptors, never transmitting frames. Aside from
4102 * reducing interrupts this also permits more concurrency.
4103 * The only potential downside is if the tx queue backs
4104 * up in which case the top half of the kernel may backup
4105 * due to a lack of tx descriptors.
4107 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
4108 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4111 * NB: don't print a message, this happens
4112 * normally on parts with too few tx queues
4116 if (qnum >= N(sc->sc_txq)) {
4117 device_printf(sc->sc_dev,
4118 "hal qnum %u out of range, max %zu!\n",
4119 qnum, N(sc->sc_txq));
4120 ath_hal_releasetxqueue(ah, qnum);
4123 if (!ATH_TXQ_SETUP(sc, qnum)) {
4124 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4125 sc->sc_txqsetup |= 1<<qnum;
4127 return &sc->sc_txq[qnum];
4132 * Setup a hardware data transmit queue for the specified
4133 * access control. The hal may not support all requested
4134 * queues in which case it will return a reference to a
4135 * previously setup queue. We record the mapping from ac's
4136 * to h/w queues for use by ath_tx_start and also track
4137 * the set of h/w queues being used to optimize work in the
4138 * transmit interrupt handler and related routines.
4141 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4143 #define N(a) (sizeof(a)/sizeof(a[0]))
4144 struct ath_txq *txq;
4146 if (ac >= N(sc->sc_ac2q)) {
4147 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4148 ac, N(sc->sc_ac2q));
4151 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4154 sc->sc_ac2q[ac] = txq;
4162 * Update WME parameters for a transmit queue.
4165 ath_txq_update(struct ath_softc *sc, int ac)
4167 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
4168 #define ATH_TXOP_TO_US(v) (v<<5)
4169 struct ifnet *ifp = sc->sc_ifp;
4170 struct ieee80211com *ic = ifp->if_l2com;
4171 struct ath_txq *txq = sc->sc_ac2q[ac];
4172 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
4173 struct ath_hal *ah = sc->sc_ah;
4176 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
4177 #ifdef IEEE80211_SUPPORT_TDMA
4180 * AIFS is zero so there's no pre-transmit wait. The
4181 * burst time defines the slot duration and is configured
4182 * through net80211. The QCU is setup to not do post-xmit
4183 * back off, lockout all lower-priority QCU's, and fire
4184 * off the DMA beacon alert timer which is setup based
4185 * on the slot configuration.
4187 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4188 | HAL_TXQ_TXERRINT_ENABLE
4189 | HAL_TXQ_TXURNINT_ENABLE
4190 | HAL_TXQ_TXEOLINT_ENABLE
4192 | HAL_TXQ_BACKOFF_DISABLE
4193 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
4197 qi.tqi_readyTime = sc->sc_tdmaslotlen;
4198 qi.tqi_burstTime = qi.tqi_readyTime;
4201 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4202 | HAL_TXQ_TXERRINT_ENABLE
4203 | HAL_TXQ_TXDESCINT_ENABLE
4204 | HAL_TXQ_TXURNINT_ENABLE
4206 qi.tqi_aifs = wmep->wmep_aifsn;
4207 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
4208 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
4209 qi.tqi_readyTime = 0;
4210 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
4211 #ifdef IEEE80211_SUPPORT_TDMA
4215 DPRINTF(sc, ATH_DEBUG_RESET,
4216 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
4217 __func__, txq->axq_qnum, qi.tqi_qflags,
4218 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
4220 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
4221 if_printf(ifp, "unable to update hardware queue "
4222 "parameters for %s traffic!\n",
4223 ieee80211_wme_acnames[ac]);
4226 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
4229 #undef ATH_TXOP_TO_US
4230 #undef ATH_EXPONENT_TO_VALUE
4234 * Callback from the 802.11 layer to update WME parameters.
4237 ath_wme_update(struct ieee80211com *ic)
4239 struct ath_softc *sc = ic->ic_ifp->if_softc;
4241 return !ath_txq_update(sc, WME_AC_BE) ||
4242 !ath_txq_update(sc, WME_AC_BK) ||
4243 !ath_txq_update(sc, WME_AC_VI) ||
4244 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4248 * Reclaim resources for a setup queue.
4251 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4254 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4255 ATH_TXQ_LOCK_DESTROY(txq);
4256 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4260 * Reclaim all tx queue resources.
4263 ath_tx_cleanup(struct ath_softc *sc)
4267 ATH_TXBUF_LOCK_DESTROY(sc);
4268 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4269 if (ATH_TXQ_SETUP(sc, i))
4270 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4274 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
4275 * using the current rates in sc_rixmap.
4278 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
4280 int rix = sc->sc_rixmap[rate];
4281 /* NB: return lowest rix for invalid rate */
4282 return (rix == 0xff ? 0 : rix);
4286 * Reclaim mbuf resources. For fragmented frames we
4287 * need to claim each frag chained with m_nextpkt.
4290 ath_freetx(struct mbuf *m)
4295 next = m->m_nextpkt;
4296 m->m_nextpkt = NULL;
4298 } while ((m = next) != NULL);
4302 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0)
4308 * Load the DMA map so any coalescing is done. This
4309 * also calculates the number of descriptors we need.
4311 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
4312 bf->bf_segs, &bf->bf_nseg,
4314 if (error == EFBIG) {
4315 /* XXX packet requires too many descriptors */
4316 bf->bf_nseg = ATH_TXDESC+1;
4317 } else if (error != 0) {
4318 sc->sc_stats.ast_tx_busdma++;
4323 * Discard null packets and check for packets that
4324 * require too many TX descriptors. We try to convert
4325 * the latter to a cluster.
4327 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
4328 sc->sc_stats.ast_tx_linear++;
4329 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC);
4332 sc->sc_stats.ast_tx_nombuf++;
4336 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
4337 bf->bf_segs, &bf->bf_nseg,
4340 sc->sc_stats.ast_tx_busdma++;
4344 KASSERT(bf->bf_nseg <= ATH_TXDESC,
4345 ("too many segments after defrag; nseg %u", bf->bf_nseg));
4346 } else if (bf->bf_nseg == 0) { /* null packet, discard */
4347 sc->sc_stats.ast_tx_nodata++;
4351 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n",
4352 __func__, m0, m0->m_pkthdr.len);
4353 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
4360 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf)
4362 struct ath_hal *ah = sc->sc_ah;
4363 struct ath_desc *ds, *ds0;
4367 * Fillin the remainder of the descriptor info.
4369 ds0 = ds = bf->bf_desc;
4370 for (i = 0; i < bf->bf_nseg; i++, ds++) {
4371 ds->ds_data = bf->bf_segs[i].ds_addr;
4372 if (i == bf->bf_nseg - 1)
4375 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
4376 ath_hal_filltxdesc(ah, ds
4377 , bf->bf_segs[i].ds_len /* segment length */
4378 , i == 0 /* first segment */
4379 , i == bf->bf_nseg - 1 /* last segment */
4380 , ds0 /* first descriptor */
4382 DPRINTF(sc, ATH_DEBUG_XMIT,
4383 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
4384 __func__, i, ds->ds_link, ds->ds_data,
4385 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
4388 * Insert the frame on the outbound list and pass it on
4389 * to the hardware. Multicast frames buffered for power
4390 * save stations and transmit from the CAB queue are stored
4391 * on a s/w only queue and loaded on to the CAB queue in
4392 * the SWBA handler since frames only go out on DTIM and
4393 * to avoid possible races.
4396 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
4397 ("busy status 0x%x", bf->bf_flags));
4398 if (txq->axq_qnum != ATH_TXQ_SWQ) {
4399 #ifdef IEEE80211_SUPPORT_TDMA
4402 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4403 qbusy = ath_hal_txqenabled(ah, txq->axq_qnum);
4404 if (txq->axq_link == NULL) {
4406 * Be careful writing the address to TXDP. If
4407 * the tx q is enabled then this write will be
4408 * ignored. Normally this is not an issue but
4409 * when tdma is in use and the q is beacon gated
4410 * this race can occur. If the q is busy then
4411 * defer the work to later--either when another
4412 * packet comes along or when we prepare a beacon
4416 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
4417 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
4418 DPRINTF(sc, ATH_DEBUG_XMIT,
4419 "%s: TXDP[%u] = %p (%p) depth %d\n",
4420 __func__, txq->axq_qnum,
4421 (caddr_t)bf->bf_daddr, bf->bf_desc,
4424 txq->axq_flags |= ATH_TXQ_PUTPENDING;
4425 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
4426 "%s: Q%u busy, defer enable\n", __func__,
4430 *txq->axq_link = bf->bf_daddr;
4431 DPRINTF(sc, ATH_DEBUG_XMIT,
4432 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
4433 txq->axq_qnum, txq->axq_link,
4434 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
4435 if ((txq->axq_flags & ATH_TXQ_PUTPENDING) && !qbusy) {
4437 * The q was busy when we previously tried
4438 * to write the address of the first buffer
4439 * in the chain. Since it's not busy now
4440 * handle this chore. We are certain the
4441 * buffer at the front is the right one since
4442 * axq_link is NULL only when the buffer list
4445 ath_hal_puttxbuf(ah, txq->axq_qnum,
4446 STAILQ_FIRST(&txq->axq_q)->bf_daddr);
4447 txq->axq_flags &= ~ATH_TXQ_PUTPENDING;
4448 DPRINTF(sc, ATH_DEBUG_TDMA | ATH_DEBUG_XMIT,
4449 "%s: Q%u restarted\n", __func__,
4454 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4455 if (txq->axq_link == NULL) {
4456 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
4457 DPRINTF(sc, ATH_DEBUG_XMIT,
4458 "%s: TXDP[%u] = %p (%p) depth %d\n",
4459 __func__, txq->axq_qnum,
4460 (caddr_t)bf->bf_daddr, bf->bf_desc,
4463 *txq->axq_link = bf->bf_daddr;
4464 DPRINTF(sc, ATH_DEBUG_XMIT,
4465 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
4466 txq->axq_qnum, txq->axq_link,
4467 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
4469 #endif /* IEEE80211_SUPPORT_TDMA */
4470 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
4471 ath_hal_txstart(ah, txq->axq_qnum);
4473 if (txq->axq_link != NULL) {
4474 struct ath_buf *last = ATH_TXQ_LAST(txq);
4475 struct ieee80211_frame *wh;
4477 /* mark previous frame */
4478 wh = mtod(last->bf_m, struct ieee80211_frame *);
4479 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
4480 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap,
4481 BUS_DMASYNC_PREWRITE);
4483 /* link descriptor */
4484 *txq->axq_link = bf->bf_daddr;
4486 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4487 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
4489 ATH_TXQ_UNLOCK(txq);
4493 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf,
4496 struct ieee80211vap *vap = ni->ni_vap;
4497 struct ath_vap *avp = ATH_VAP(vap);
4498 struct ath_hal *ah = sc->sc_ah;
4499 struct ifnet *ifp = sc->sc_ifp;
4500 struct ieee80211com *ic = ifp->if_l2com;
4501 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
4502 int error, iswep, ismcast, isfrag, ismrr;
4503 int keyix, hdrlen, pktlen, try0;
4504 u_int8_t rix, txrate, ctsrate;
4505 u_int8_t cix = 0xff; /* NB: silence compiler */
4506 struct ath_desc *ds;
4507 struct ath_txq *txq;
4508 struct ieee80211_frame *wh;
4509 u_int subtype, flags, ctsduration;
4511 const HAL_RATE_TABLE *rt;
4512 HAL_BOOL shortPreamble;
4513 struct ath_node *an;
4516 wh = mtod(m0, struct ieee80211_frame *);
4517 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
4518 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
4519 isfrag = m0->m_flags & M_FRAG;
4520 hdrlen = ieee80211_anyhdrsize(wh);
4522 * Packet length must not include any
4523 * pad bytes; deduct them here.
4525 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
4528 const struct ieee80211_cipher *cip;
4529 struct ieee80211_key *k;
4532 * Construct the 802.11 header+trailer for an encrypted
4533 * frame. The only reason this can fail is because of an
4534 * unknown or unsupported cipher/key type.
4536 k = ieee80211_crypto_encap(ni, m0);
4539 * This can happen when the key is yanked after the
4540 * frame was queued. Just discard the frame; the
4541 * 802.11 layer counts failures and provides
4542 * debugging/diagnostics.
4548 * Adjust the packet + header lengths for the crypto
4549 * additions and calculate the h/w key index. When
4550 * a s/w mic is done the frame will have had any mic
4551 * added to it prior to entry so m0->m_pkthdr.len will
4552 * account for it. Otherwise we need to add it to the
4556 hdrlen += cip->ic_header;
4557 pktlen += cip->ic_header + cip->ic_trailer;
4558 /* NB: frags always have any TKIP MIC done in s/w */
4559 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag)
4560 pktlen += cip->ic_miclen;
4561 keyix = k->wk_keyix;
4563 /* packet header may have moved, reset our local pointer */
4564 wh = mtod(m0, struct ieee80211_frame *);
4565 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
4567 * Use station key cache slot, if assigned.
4569 keyix = ni->ni_ucastkey.wk_keyix;
4570 if (keyix == IEEE80211_KEYIX_NONE)
4571 keyix = HAL_TXKEYIX_INVALID;
4573 keyix = HAL_TXKEYIX_INVALID;
4575 pktlen += IEEE80211_CRC_LEN;
4578 * Load the DMA map so any coalescing is done. This
4579 * also calculates the number of descriptors we need.
4581 error = ath_tx_dmasetup(sc, bf, m0);
4584 bf->bf_node = ni; /* NB: held reference */
4585 m0 = bf->bf_m; /* NB: may have changed */
4586 wh = mtod(m0, struct ieee80211_frame *);
4588 /* setup descriptors */
4590 rt = sc->sc_currates;
4591 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
4594 * NB: the 802.11 layer marks whether or not we should
4595 * use short preamble based on the current mode and
4596 * negotiated parameters.
4598 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
4599 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
4600 shortPreamble = AH_TRUE;
4601 sc->sc_stats.ast_tx_shortpre++;
4603 shortPreamble = AH_FALSE;
4607 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
4608 ismrr = 0; /* default no multi-rate retry*/
4609 pri = M_WME_GETAC(m0); /* honor classification */
4610 /* XXX use txparams instead of fixed values */
4612 * Calculate Atheros packet type from IEEE80211 packet header,
4613 * setup for rate calculations, and select h/w transmit queue.
4615 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
4616 case IEEE80211_FC0_TYPE_MGT:
4617 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4618 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
4619 atype = HAL_PKT_TYPE_BEACON;
4620 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
4621 atype = HAL_PKT_TYPE_PROBE_RESP;
4622 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
4623 atype = HAL_PKT_TYPE_ATIM;
4625 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
4626 rix = an->an_mgmtrix;
4627 txrate = rt->info[rix].rateCode;
4629 txrate |= rt->info[rix].shortPreamble;
4630 try0 = ATH_TXMGTTRY;
4631 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
4633 case IEEE80211_FC0_TYPE_CTL:
4634 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
4635 rix = an->an_mgmtrix;
4636 txrate = rt->info[rix].rateCode;
4638 txrate |= rt->info[rix].shortPreamble;
4639 try0 = ATH_TXMGTTRY;
4640 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
4642 case IEEE80211_FC0_TYPE_DATA:
4643 atype = HAL_PKT_TYPE_NORMAL; /* default */
4645 * Data frames: multicast frames go out at a fixed rate,
4646 * EAPOL frames use the mgmt frame rate; otherwise consult
4647 * the rate control module for the rate to use.
4650 rix = an->an_mcastrix;
4651 txrate = rt->info[rix].rateCode;
4653 txrate |= rt->info[rix].shortPreamble;
4655 } else if (m0->m_flags & M_EAPOL) {
4656 /* XXX? maybe always use long preamble? */
4657 rix = an->an_mgmtrix;
4658 txrate = rt->info[rix].rateCode;
4660 txrate |= rt->info[rix].shortPreamble;
4661 try0 = ATH_TXMAXTRY; /* XXX?too many? */
4663 ath_rate_findrate(sc, an, shortPreamble, pktlen,
4664 &rix, &try0, &txrate);
4665 sc->sc_txrix = rix; /* for LED blinking */
4666 sc->sc_lastdatarix = rix; /* for fast frames */
4667 if (try0 != ATH_TXMAXTRY)
4670 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
4671 flags |= HAL_TXDESC_NOACK;
4674 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
4675 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
4680 txq = sc->sc_ac2q[pri];
4683 * When servicing one or more stations in power-save mode
4684 * (or) if there is some mcast data waiting on the mcast
4685 * queue (to prevent out of order delivery) multicast
4686 * frames must be buffered until after the beacon.
4688 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth))
4689 txq = &avp->av_mcastq;
4692 * Calculate miscellaneous flags.
4695 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
4696 } else if (pktlen > vap->iv_rtsthreshold &&
4697 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) {
4698 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
4699 cix = rt->info[rix].controlRate;
4700 sc->sc_stats.ast_tx_rts++;
4702 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
4703 sc->sc_stats.ast_tx_noack++;
4704 #ifdef IEEE80211_SUPPORT_TDMA
4705 if (sc->sc_tdma && (flags & HAL_TXDESC_NOACK) == 0) {
4706 DPRINTF(sc, ATH_DEBUG_TDMA,
4707 "%s: discard frame, ACK required w/ TDMA\n", __func__);
4708 sc->sc_stats.ast_tdma_ack++;
4715 * If 802.11g protection is enabled, determine whether
4716 * to use RTS/CTS or just CTS. Note that this is only
4717 * done for OFDM unicast frames.
4719 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
4720 rt->info[rix].phy == IEEE80211_T_OFDM &&
4721 (flags & HAL_TXDESC_NOACK) == 0) {
4722 /* XXX fragments must use CCK rates w/ protection */
4723 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
4724 flags |= HAL_TXDESC_RTSENA;
4725 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
4726 flags |= HAL_TXDESC_CTSENA;
4729 * For frags it would be desirable to use the
4730 * highest CCK rate for RTS/CTS. But stations
4731 * farther away may detect it at a lower CCK rate
4732 * so use the configured protection rate instead
4735 cix = rt->info[sc->sc_protrix].controlRate;
4737 cix = rt->info[sc->sc_protrix].controlRate;
4738 sc->sc_stats.ast_tx_protect++;
4742 * Calculate duration. This logically belongs in the 802.11
4743 * layer but it lacks sufficient information to calculate it.
4745 if ((flags & HAL_TXDESC_NOACK) == 0 &&
4746 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
4749 dur = rt->info[rix].spAckDuration;
4751 dur = rt->info[rix].lpAckDuration;
4752 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) {
4753 dur += dur; /* additional SIFS+ACK */
4754 KASSERT(m0->m_nextpkt != NULL, ("no fragment"));
4756 * Include the size of next fragment so NAV is
4757 * updated properly. The last fragment uses only
4760 dur += ath_hal_computetxtime(ah, rt,
4761 m0->m_nextpkt->m_pkthdr.len,
4762 rix, shortPreamble);
4766 * Force hardware to use computed duration for next
4767 * fragment by disabling multi-rate retry which updates
4768 * duration based on the multi-rate duration table.
4771 try0 = ATH_TXMGTTRY; /* XXX? */
4773 *(u_int16_t *)wh->i_dur = htole16(dur);
4777 * Calculate RTS/CTS rate and duration if needed.
4780 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
4782 * CTS transmit rate is derived from the transmit rate
4783 * by looking in the h/w rate table. We must also factor
4784 * in whether or not a short preamble is to be used.
4786 /* NB: cix is set above where RTS/CTS is enabled */
4787 KASSERT(cix != 0xff, ("cix not setup"));
4788 ctsrate = rt->info[cix].rateCode;
4790 * Compute the transmit duration based on the frame
4791 * size and the size of an ACK frame. We call into the
4792 * HAL to do the computation since it depends on the
4793 * characteristics of the actual PHY being used.
4795 * NB: CTS is assumed the same size as an ACK so we can
4796 * use the precalculated ACK durations.
4798 if (shortPreamble) {
4799 ctsrate |= rt->info[cix].shortPreamble;
4800 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
4801 ctsduration += rt->info[cix].spAckDuration;
4802 ctsduration += ath_hal_computetxtime(ah,
4803 rt, pktlen, rix, AH_TRUE);
4804 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
4805 ctsduration += rt->info[rix].spAckDuration;
4807 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
4808 ctsduration += rt->info[cix].lpAckDuration;
4809 ctsduration += ath_hal_computetxtime(ah,
4810 rt, pktlen, rix, AH_FALSE);
4811 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
4812 ctsduration += rt->info[rix].lpAckDuration;
4815 * Must disable multi-rate retry when using RTS/CTS.
4818 try0 = ATH_TXMGTTRY; /* XXX */
4823 * At this point we are committed to sending the frame
4824 * and we don't need to look at m_nextpkt; clear it in
4825 * case this frame is part of frag chain.
4827 m0->m_nextpkt = NULL;
4829 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
4830 ieee80211_dump_pkt(ic, mtod(m0, const uint8_t *), m0->m_len,
4831 sc->sc_hwmap[rix].ieeerate, -1);
4833 if (ieee80211_radiotap_active_vap(vap)) {
4834 u_int64_t tsf = ath_hal_gettsf64(ah);
4836 sc->sc_tx_th.wt_tsf = htole64(tsf);
4837 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
4839 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
4841 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
4842 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
4843 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
4844 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
4846 ieee80211_radiotap_tx(vap, m0);
4850 * Determine if a tx interrupt should be generated for
4851 * this descriptor. We take a tx interrupt to reap
4852 * descriptors when the h/w hits an EOL condition or
4853 * when the descriptor is specifically marked to generate
4854 * an interrupt. We periodically mark descriptors in this
4855 * way to insure timely replenishing of the supply needed
4856 * for sending frames. Defering interrupts reduces system
4857 * load and potentially allows more concurrent work to be
4858 * done but if done to aggressively can cause senders to
4861 * NB: use >= to deal with sc_txintrperiod changing
4862 * dynamically through sysctl.
4864 if (flags & HAL_TXDESC_INTREQ) {
4865 txq->axq_intrcnt = 0;
4866 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
4867 flags |= HAL_TXDESC_INTREQ;
4868 txq->axq_intrcnt = 0;
4872 * Formulate first tx descriptor with tx controls.
4874 /* XXX check return value? */
4875 ath_hal_setuptxdesc(ah, ds
4876 , pktlen /* packet length */
4877 , hdrlen /* header length */
4878 , atype /* Atheros packet type */
4879 , ni->ni_txpower /* txpower */
4880 , txrate, try0 /* series 0 rate/tries */
4881 , keyix /* key cache index */
4882 , sc->sc_txantenna /* antenna mode */
4884 , ctsrate /* rts/cts rate */
4885 , ctsduration /* rts/cts duration */
4887 bf->bf_txflags = flags;
4889 * Setup the multi-rate retry state only when we're
4890 * going to use it. This assumes ath_hal_setuptxdesc
4891 * initializes the descriptors (so we don't have to)
4892 * when the hardware supports multi-rate retry and
4896 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
4898 ath_tx_handoff(sc, txq, bf);
4903 * Process completed xmit descriptors from the specified queue.
4906 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
4908 struct ath_hal *ah = sc->sc_ah;
4909 struct ifnet *ifp = sc->sc_ifp;
4910 struct ieee80211com *ic = ifp->if_l2com;
4911 struct ath_buf *bf, *last;
4912 struct ath_desc *ds, *ds0;
4913 struct ath_tx_status *ts;
4914 struct ieee80211_node *ni;
4915 struct ath_node *an;
4916 int sr, lr, pri, nacked;
4919 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4920 __func__, txq->axq_qnum,
4921 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4926 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4927 bf = STAILQ_FIRST(&txq->axq_q);
4929 ATH_TXQ_UNLOCK(txq);
4932 ds0 = &bf->bf_desc[0];
4933 ds = &bf->bf_desc[bf->bf_nseg - 1];
4934 ts = &bf->bf_status.ds_txstat;
4935 status = ath_hal_txprocdesc(ah, ds, ts);
4937 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4938 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4941 if (status == HAL_EINPROGRESS) {
4942 ATH_TXQ_UNLOCK(txq);
4945 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
4946 #ifdef IEEE80211_SUPPORT_TDMA
4947 if (txq->axq_depth > 0) {
4949 * More frames follow. Mark the buffer busy
4950 * so it's not re-used while the hardware may
4951 * still re-read the link field in the descriptor.
4953 bf->bf_flags |= ATH_BUF_BUSY;
4956 if (txq->axq_depth == 0)
4958 txq->axq_link = NULL;
4959 ATH_TXQ_UNLOCK(txq);
4964 if (ts->ts_status == 0) {
4965 u_int8_t txant = ts->ts_antenna;
4966 sc->sc_stats.ast_ant_tx[txant]++;
4967 sc->sc_ant_tx[txant]++;
4968 if (ts->ts_finaltsi != 0)
4969 sc->sc_stats.ast_tx_altrate++;
4970 pri = M_WME_GETAC(bf->bf_m);
4971 if (pri >= WME_AC_VO)
4972 ic->ic_wme.wme_hipri_traffic++;
4973 if ((bf->bf_txflags & HAL_TXDESC_NOACK) == 0)
4974 ni->ni_inact = ni->ni_inact_reload;
4976 if (ts->ts_status & HAL_TXERR_XRETRY)
4977 sc->sc_stats.ast_tx_xretries++;
4978 if (ts->ts_status & HAL_TXERR_FIFO)
4979 sc->sc_stats.ast_tx_fifoerr++;
4980 if (ts->ts_status & HAL_TXERR_FILT)
4981 sc->sc_stats.ast_tx_filtered++;
4982 if (bf->bf_m->m_flags & M_FF)
4983 sc->sc_stats.ast_ff_txerr++;
4985 sr = ts->ts_shortretry;
4986 lr = ts->ts_longretry;
4987 sc->sc_stats.ast_tx_shortretry += sr;
4988 sc->sc_stats.ast_tx_longretry += lr;
4990 * Hand the descriptor to the rate control algorithm.
4992 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4993 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0) {
4995 * If frame was ack'd update statistics,
4996 * including the last rx time used to
4997 * workaround phantom bmiss interrupts.
4999 if (ts->ts_status == 0) {
5001 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
5002 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
5005 ath_rate_tx_complete(sc, an, bf);
5008 * Do any tx complete callback. Note this must
5009 * be done before releasing the node reference.
5011 if (bf->bf_m->m_flags & M_TXCB)
5012 ieee80211_process_callback(ni, bf->bf_m,
5013 (bf->bf_txflags & HAL_TXDESC_NOACK) == 0 ?
5014 ts->ts_status : HAL_TXERR_XRETRY);
5015 ieee80211_free_node(ni);
5017 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
5018 BUS_DMASYNC_POSTWRITE);
5019 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5026 last = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list);
5028 last->bf_flags &= ~ATH_BUF_BUSY;
5029 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5030 ATH_TXBUF_UNLOCK(sc);
5032 #ifdef IEEE80211_SUPPORT_SUPERG
5034 * Flush fast-frame staging queue when traffic slows.
5036 if (txq->axq_depth <= 1)
5037 ieee80211_ff_flush(ic, txq->axq_ac);
5043 txqactive(struct ath_hal *ah, int qnum)
5045 u_int32_t txqs = 1<<qnum;
5046 ath_hal_gettxintrtxqs(ah, &txqs);
5047 return (txqs & (1<<qnum));
5051 * Deferred processing of transmit interrupt; special-cased
5052 * for a single hardware transmit queue (e.g. 5210 and 5211).
5055 ath_tx_proc_q0(void *arg, int npending)
5057 struct ath_softc *sc = arg;
5058 struct ifnet *ifp = sc->sc_ifp;
5060 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]))
5061 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5062 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
5063 ath_tx_processq(sc, sc->sc_cabq);
5064 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5065 sc->sc_wd_timer = 0;
5068 ath_led_event(sc, sc->sc_txrix);
5074 * Deferred processing of transmit interrupt; special-cased
5075 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
5078 ath_tx_proc_q0123(void *arg, int npending)
5080 struct ath_softc *sc = arg;
5081 struct ifnet *ifp = sc->sc_ifp;
5085 * Process each active queue.
5088 if (txqactive(sc->sc_ah, 0))
5089 nacked += ath_tx_processq(sc, &sc->sc_txq[0]);
5090 if (txqactive(sc->sc_ah, 1))
5091 nacked += ath_tx_processq(sc, &sc->sc_txq[1]);
5092 if (txqactive(sc->sc_ah, 2))
5093 nacked += ath_tx_processq(sc, &sc->sc_txq[2]);
5094 if (txqactive(sc->sc_ah, 3))
5095 nacked += ath_tx_processq(sc, &sc->sc_txq[3]);
5096 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
5097 ath_tx_processq(sc, sc->sc_cabq);
5099 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5101 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5102 sc->sc_wd_timer = 0;
5105 ath_led_event(sc, sc->sc_txrix);
5111 * Deferred processing of transmit interrupt.
5114 ath_tx_proc(void *arg, int npending)
5116 struct ath_softc *sc = arg;
5117 struct ifnet *ifp = sc->sc_ifp;
5121 * Process each active queue.
5124 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5125 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i))
5126 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
5128 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5130 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5131 sc->sc_wd_timer = 0;
5134 ath_led_event(sc, sc->sc_txrix);
5140 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
5143 struct ath_hal *ah = sc->sc_ah;
5145 struct ieee80211_node *ni;
5150 * NB: this assumes output has been stopped and
5151 * we do not need to block ath_tx_proc
5154 bf = STAILQ_LAST(&sc->sc_txbuf, ath_buf, bf_list);
5156 bf->bf_flags &= ~ATH_BUF_BUSY;
5157 ATH_TXBUF_UNLOCK(sc);
5158 for (ix = 0;; ix++) {
5160 bf = STAILQ_FIRST(&txq->axq_q);
5162 txq->axq_link = NULL;
5163 ATH_TXQ_UNLOCK(txq);
5166 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
5167 ATH_TXQ_UNLOCK(txq);
5169 if (sc->sc_debug & ATH_DEBUG_RESET) {
5170 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5172 ath_printtxbuf(sc, bf, txq->axq_qnum, ix,
5173 ath_hal_txprocdesc(ah, bf->bf_desc,
5174 &bf->bf_status.ds_txstat) == HAL_OK);
5175 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
5176 bf->bf_m->m_len, 0, -1);
5178 #endif /* ATH_DEBUG */
5179 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5184 * Do any callback and reclaim the node reference.
5186 if (bf->bf_m->m_flags & M_TXCB)
5187 ieee80211_process_callback(ni, bf->bf_m, -1);
5188 ieee80211_free_node(ni);
5192 bf->bf_flags &= ~ATH_BUF_BUSY;
5195 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5196 ATH_TXBUF_UNLOCK(sc);
5201 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5203 struct ath_hal *ah = sc->sc_ah;
5205 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5206 __func__, txq->axq_qnum,
5207 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
5209 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
5213 * Drain the transmit queues and reclaim resources.
5216 ath_draintxq(struct ath_softc *sc)
5218 struct ath_hal *ah = sc->sc_ah;
5219 struct ifnet *ifp = sc->sc_ifp;
5222 /* XXX return value */
5223 if (!sc->sc_invalid) {
5224 /* don't touch the hardware if marked invalid */
5225 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5226 __func__, sc->sc_bhalq,
5227 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5229 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5230 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5231 if (ATH_TXQ_SETUP(sc, i))
5232 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5234 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5235 if (ATH_TXQ_SETUP(sc, i))
5236 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5238 if (sc->sc_debug & ATH_DEBUG_RESET) {
5239 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
5240 if (bf != NULL && bf->bf_m != NULL) {
5241 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
5242 ath_hal_txprocdesc(ah, bf->bf_desc,
5243 &bf->bf_status.ds_txstat) == HAL_OK);
5244 ieee80211_dump_pkt(ifp->if_l2com,
5245 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
5249 #endif /* ATH_DEBUG */
5250 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5251 sc->sc_wd_timer = 0;
5255 * Disable the receive h/w in preparation for a reset.
5258 ath_stoprecv(struct ath_softc *sc)
5260 #define PA2DESC(_sc, _pa) \
5261 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
5262 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
5263 struct ath_hal *ah = sc->sc_ah;
5265 ath_hal_stoppcurecv(ah); /* disable PCU */
5266 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
5267 ath_hal_stopdmarecv(ah); /* disable DMA engine */
5268 DELAY(3000); /* 3ms is long enough for 1 frame */
5270 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
5274 printf("%s: rx queue %p, link %p\n", __func__,
5275 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
5277 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5278 struct ath_desc *ds = bf->bf_desc;
5279 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
5280 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
5281 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
5282 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
5283 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
5288 if (sc->sc_rxpending != NULL) {
5289 m_freem(sc->sc_rxpending);
5290 sc->sc_rxpending = NULL;
5292 sc->sc_rxlink = NULL; /* just in case */
5297 * Enable the receive h/w following a reset.
5300 ath_startrecv(struct ath_softc *sc)
5302 struct ath_hal *ah = sc->sc_ah;
5305 sc->sc_rxlink = NULL;
5306 sc->sc_rxpending = NULL;
5307 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5308 int error = ath_rxbuf_init(sc, bf);
5310 DPRINTF(sc, ATH_DEBUG_RECV,
5311 "%s: ath_rxbuf_init failed %d\n",
5317 bf = STAILQ_FIRST(&sc->sc_rxbuf);
5318 ath_hal_putrxbuf(ah, bf->bf_daddr);
5319 ath_hal_rxena(ah); /* enable recv descriptors */
5320 ath_mode_init(sc); /* set filters, etc. */
5321 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
5326 * Update internal state after a channel change.
5329 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5331 enum ieee80211_phymode mode;
5334 * Change channels and update the h/w rate map
5335 * if we're switching; e.g. 11a to 11b/g.
5337 mode = ieee80211_chan2mode(chan);
5338 if (mode != sc->sc_curmode)
5339 ath_setcurmode(sc, mode);
5340 sc->sc_curchan = chan;
5344 * Set/change channels. If the channel is really being changed,
5345 * it's done by reseting the chip. To accomplish this we must
5346 * first cleanup any pending DMA, then restart stuff after a la
5350 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5352 struct ifnet *ifp = sc->sc_ifp;
5353 struct ieee80211com *ic = ifp->if_l2com;
5354 struct ath_hal *ah = sc->sc_ah;
5356 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
5357 __func__, ieee80211_chan2ieee(ic, chan),
5358 chan->ic_freq, chan->ic_flags);
5359 if (chan != sc->sc_curchan) {
5362 * To switch channels clear any pending DMA operations;
5363 * wait long enough for the RX fifo to drain, reset the
5364 * hardware at the new frequency, and then re-enable
5365 * the relevant bits of the h/w.
5367 ath_hal_intrset(ah, 0); /* disable interrupts */
5368 ath_draintxq(sc); /* clear pending tx frames */
5369 ath_stoprecv(sc); /* turn off frame recv */
5370 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
5371 if_printf(ifp, "%s: unable to reset "
5372 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
5373 __func__, ieee80211_chan2ieee(ic, chan),
5374 chan->ic_freq, chan->ic_flags, status);
5377 sc->sc_diversity = ath_hal_getdiversity(ah);
5380 * Re-enable rx framework.
5382 if (ath_startrecv(sc) != 0) {
5383 if_printf(ifp, "%s: unable to restart recv logic\n",
5389 * Change channels and update the h/w rate map
5390 * if we're switching; e.g. 11a to 11b/g.
5392 ath_chan_change(sc, chan);
5395 * Re-enable interrupts.
5397 ath_hal_intrset(ah, sc->sc_imask);
5403 * Periodically recalibrate the PHY to account
5404 * for temperature/environment changes.
5407 ath_calibrate(void *arg)
5409 struct ath_softc *sc = arg;
5410 struct ath_hal *ah = sc->sc_ah;
5411 struct ifnet *ifp = sc->sc_ifp;
5412 struct ieee80211com *ic = ifp->if_l2com;
5413 HAL_BOOL longCal, isCalDone;
5416 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
5418 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5420 sc->sc_stats.ast_per_cal++;
5421 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5423 * Rfgain is out of bounds, reset the chip
5424 * to load new gain values.
5426 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5427 "%s: rfgain change\n", __func__);
5428 sc->sc_stats.ast_per_rfgain++;
5432 * If this long cal is after an idle period, then
5433 * reset the data collection state so we start fresh.
5435 if (sc->sc_resetcal) {
5436 (void) ath_hal_calreset(ah, sc->sc_curchan);
5437 sc->sc_lastcalreset = ticks;
5438 sc->sc_resetcal = 0;
5441 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5444 * Calibrate noise floor data again in case of change.
5446 ath_hal_process_noisefloor(ah);
5449 DPRINTF(sc, ATH_DEBUG_ANY,
5450 "%s: calibration of channel %u failed\n",
5451 __func__, sc->sc_curchan->ic_freq);
5452 sc->sc_stats.ast_per_calfail++;
5457 * Use a shorter interval to potentially collect multiple
5458 * data samples required to complete calibration. Once
5459 * we're told the work is done we drop back to a longer
5460 * interval between requests. We're more aggressive doing
5461 * work when operating as an AP to improve operation right
5464 nextcal = (1000*ath_shortcalinterval)/hz;
5465 if (sc->sc_opmode != HAL_M_HOSTAP)
5468 nextcal = ath_longcalinterval*hz;
5469 sc->sc_lastlongcal = ticks;
5470 if (sc->sc_lastcalreset == 0)
5471 sc->sc_lastcalreset = sc->sc_lastlongcal;
5472 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5473 sc->sc_resetcal = 1; /* setup reset next trip */
5477 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5478 __func__, nextcal, isCalDone ? "" : "!");
5479 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5481 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5483 /* NB: don't rearm timer */
5488 ath_scan_start(struct ieee80211com *ic)
5490 struct ifnet *ifp = ic->ic_ifp;
5491 struct ath_softc *sc = ifp->if_softc;
5492 struct ath_hal *ah = sc->sc_ah;
5495 /* XXX calibration timer? */
5497 sc->sc_scanning = 1;
5498 sc->sc_syncbeacon = 0;
5499 rfilt = ath_calcrxfilter(sc);
5500 ath_hal_setrxfilter(ah, rfilt);
5501 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5503 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5504 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5508 ath_scan_end(struct ieee80211com *ic)
5510 struct ifnet *ifp = ic->ic_ifp;
5511 struct ath_softc *sc = ifp->if_softc;
5512 struct ath_hal *ah = sc->sc_ah;
5515 sc->sc_scanning = 0;
5516 rfilt = ath_calcrxfilter(sc);
5517 ath_hal_setrxfilter(ah, rfilt);
5518 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5520 ath_hal_process_noisefloor(ah);
5522 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5523 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5528 ath_set_channel(struct ieee80211com *ic)
5530 struct ifnet *ifp = ic->ic_ifp;
5531 struct ath_softc *sc = ifp->if_softc;
5533 (void) ath_chan_set(sc, ic->ic_curchan);
5535 * If we are returning to our bss channel then mark state
5536 * so the next recv'd beacon's tsf will be used to sync the
5537 * beacon timers. Note that since we only hear beacons in
5538 * sta/ibss mode this has no effect in other operating modes.
5540 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5541 sc->sc_syncbeacon = 1;
5545 * Walk the vap list and check if there any vap's in RUN state.
5548 ath_isanyrunningvaps(struct ieee80211vap *this)
5550 struct ieee80211com *ic = this->iv_ic;
5551 struct ieee80211vap *vap;
5553 IEEE80211_LOCK_ASSERT(ic);
5555 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5556 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5563 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5565 struct ieee80211com *ic = vap->iv_ic;
5566 struct ath_softc *sc = ic->ic_ifp->if_softc;
5567 struct ath_vap *avp = ATH_VAP(vap);
5568 struct ath_hal *ah = sc->sc_ah;
5569 struct ieee80211_node *ni = NULL;
5570 int i, error, stamode;
5572 static const HAL_LED_STATE leds[] = {
5573 HAL_LED_INIT, /* IEEE80211_S_INIT */
5574 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5575 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5576 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5577 HAL_LED_RUN, /* IEEE80211_S_CAC */
5578 HAL_LED_RUN, /* IEEE80211_S_RUN */
5579 HAL_LED_RUN, /* IEEE80211_S_CSA */
5580 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5583 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5584 ieee80211_state_name[vap->iv_state],
5585 ieee80211_state_name[nstate]);
5587 callout_drain(&sc->sc_cal_ch);
5588 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5590 if (nstate == IEEE80211_S_SCAN) {
5592 * Scanning: turn off beacon miss and don't beacon.
5593 * Mark beacon state so when we reach RUN state we'll
5594 * [re]setup beacons. Unblock the task q thread so
5595 * deferred interrupt processing is done.
5598 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5599 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5601 taskqueue_unblock(sc->sc_tq);
5605 rfilt = ath_calcrxfilter(sc);
5606 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5607 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5608 vap->iv_opmode == IEEE80211_M_IBSS);
5609 if (stamode && nstate == IEEE80211_S_RUN) {
5610 sc->sc_curaid = ni->ni_associd;
5611 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5612 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5614 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5615 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5616 ath_hal_setrxfilter(ah, rfilt);
5618 /* XXX is this to restore keycache on resume? */
5619 if (vap->iv_opmode != IEEE80211_M_STA &&
5620 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5621 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5622 if (ath_hal_keyisvalid(ah, i))
5623 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5627 * Invoke the parent method to do net80211 work.
5629 error = avp->av_newstate(vap, nstate, arg);
5633 if (nstate == IEEE80211_S_RUN) {
5634 /* NB: collect bss node again, it may have changed */
5637 DPRINTF(sc, ATH_DEBUG_STATE,
5638 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5639 "capinfo 0x%04x chan %d\n", __func__,
5640 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5641 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5643 switch (vap->iv_opmode) {
5644 #ifdef IEEE80211_SUPPORT_TDMA
5645 case IEEE80211_M_AHDEMO:
5646 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
5650 case IEEE80211_M_HOSTAP:
5651 case IEEE80211_M_IBSS:
5652 case IEEE80211_M_MBSS:
5654 * Allocate and setup the beacon frame.
5656 * Stop any previous beacon DMA. This may be
5657 * necessary, for example, when an ibss merge
5658 * causes reconfiguration; there will be a state
5659 * transition from RUN->RUN that means we may
5660 * be called with beacon transmission active.
5662 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5664 error = ath_beacon_alloc(sc, ni);
5668 * If joining an adhoc network defer beacon timer
5669 * configuration to the next beacon frame so we
5670 * have a current TSF to use. Otherwise we're
5671 * starting an ibss/bss so there's no need to delay;
5672 * if this is the first vap moving to RUN state, then
5673 * beacon state needs to be [re]configured.
5675 if (vap->iv_opmode == IEEE80211_M_IBSS &&
5676 ni->ni_tstamp.tsf != 0) {
5677 sc->sc_syncbeacon = 1;
5678 } else if (!sc->sc_beacons) {
5679 #ifdef IEEE80211_SUPPORT_TDMA
5680 if (vap->iv_caps & IEEE80211_C_TDMA)
5681 ath_tdma_config(sc, vap);
5684 ath_beacon_config(sc, vap);
5688 case IEEE80211_M_STA:
5690 * Defer beacon timer configuration to the next
5691 * beacon frame so we have a current TSF to use
5692 * (any TSF collected when scanning is likely old).
5694 sc->sc_syncbeacon = 1;
5696 case IEEE80211_M_MONITOR:
5698 * Monitor mode vaps have only INIT->RUN and RUN->RUN
5699 * transitions so we must re-enable interrupts here to
5700 * handle the case of a single monitor mode vap.
5702 ath_hal_intrset(ah, sc->sc_imask);
5704 case IEEE80211_M_WDS:
5710 * Let the hal process statistics collected during a
5711 * scan so it can provide calibrated noise floor data.
5713 ath_hal_process_noisefloor(ah);
5715 * Reset rssi stats; maybe not the best place...
5717 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
5718 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
5719 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
5721 * Finally, start any timers and the task q thread
5722 * (in case we didn't go through SCAN state).
5724 if (ath_longcalinterval != 0) {
5725 /* start periodic recalibration timer */
5726 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5728 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5729 "%s: calibration disabled\n", __func__);
5731 taskqueue_unblock(sc->sc_tq);
5732 } else if (nstate == IEEE80211_S_INIT) {
5734 * If there are no vaps left in RUN state then
5735 * shutdown host/driver operation:
5736 * o disable interrupts
5737 * o disable the task queue thread
5738 * o mark beacon processing as stopped
5740 if (!ath_isanyrunningvaps(vap)) {
5741 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5742 /* disable interrupts */
5743 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
5744 taskqueue_block(sc->sc_tq);
5747 #ifdef IEEE80211_SUPPORT_TDMA
5748 ath_hal_setcca(ah, AH_TRUE);
5756 * Allocate a key cache slot to the station so we can
5757 * setup a mapping from key index to node. The key cache
5758 * slot is needed for managing antenna state and for
5759 * compression when stations do not use crypto. We do
5760 * it uniliaterally here; if crypto is employed this slot
5761 * will be reassigned.
5764 ath_setup_stationkey(struct ieee80211_node *ni)
5766 struct ieee80211vap *vap = ni->ni_vap;
5767 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5768 ieee80211_keyix keyix, rxkeyix;
5770 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
5772 * Key cache is full; we'll fall back to doing
5773 * the more expensive lookup in software. Note
5774 * this also means no h/w compression.
5776 /* XXX msg+statistic */
5779 ni->ni_ucastkey.wk_keyix = keyix;
5780 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
5781 /* NB: must mark device key to get called back on delete */
5782 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
5783 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
5784 /* NB: this will create a pass-thru key entry */
5785 ath_keyset(sc, &ni->ni_ucastkey, vap->iv_bss);
5790 * Setup driver-specific state for a newly associated node.
5791 * Note that we're called also on a re-associate, the isnew
5792 * param tells us if this is the first time or not.
5795 ath_newassoc(struct ieee80211_node *ni, int isnew)
5797 struct ath_node *an = ATH_NODE(ni);
5798 struct ieee80211vap *vap = ni->ni_vap;
5799 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5800 const struct ieee80211_txparam *tp = ni->ni_txparms;
5802 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
5803 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
5805 ath_rate_newassoc(sc, an, isnew);
5807 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
5808 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
5809 ath_setup_stationkey(ni);
5813 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
5814 int nchans, struct ieee80211_channel chans[])
5816 struct ath_softc *sc = ic->ic_ifp->if_softc;
5817 struct ath_hal *ah = sc->sc_ah;
5820 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5821 "%s: rd %u cc %u location %c%s\n",
5822 __func__, reg->regdomain, reg->country, reg->location,
5823 reg->ecm ? " ecm" : "");
5825 status = ath_hal_set_channels(ah, chans, nchans,
5826 reg->country, reg->regdomain);
5827 if (status != HAL_OK) {
5828 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
5830 return EINVAL; /* XXX */
5836 ath_getradiocaps(struct ieee80211com *ic,
5837 int maxchans, int *nchans, struct ieee80211_channel chans[])
5839 struct ath_softc *sc = ic->ic_ifp->if_softc;
5840 struct ath_hal *ah = sc->sc_ah;
5842 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
5843 __func__, SKU_DEBUG, CTRY_DEFAULT);
5845 /* XXX check return */
5846 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
5847 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
5852 ath_getchannels(struct ath_softc *sc)
5854 struct ifnet *ifp = sc->sc_ifp;
5855 struct ieee80211com *ic = ifp->if_l2com;
5856 struct ath_hal *ah = sc->sc_ah;
5860 * Collect channel set based on EEPROM contents.
5862 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
5863 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
5864 if (status != HAL_OK) {
5865 if_printf(ifp, "%s: unable to collect channel list from hal, "
5866 "status %d\n", __func__, status);
5869 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
5870 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
5871 /* XXX map Atheros sku's to net80211 SKU's */
5872 /* XXX net80211 types too small */
5873 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
5874 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
5875 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
5876 ic->ic_regdomain.isocc[1] = ' ';
5878 ic->ic_regdomain.ecm = 1;
5879 ic->ic_regdomain.location = 'I';
5881 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
5882 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
5883 __func__, sc->sc_eerd, sc->sc_eecc,
5884 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
5885 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
5890 ath_led_done(void *arg)
5892 struct ath_softc *sc = arg;
5894 sc->sc_blinking = 0;
5898 * Turn the LED off: flip the pin and then set a timer so no
5899 * update will happen for the specified duration.
5902 ath_led_off(void *arg)
5904 struct ath_softc *sc = arg;
5906 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
5907 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
5911 * Blink the LED according to the specified on/off times.
5914 ath_led_blink(struct ath_softc *sc, int on, int off)
5916 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
5917 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
5918 sc->sc_blinking = 1;
5919 sc->sc_ledoff = off;
5920 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
5924 ath_led_event(struct ath_softc *sc, int rix)
5926 sc->sc_ledevent = ticks; /* time of last event */
5927 if (sc->sc_blinking) /* don't interrupt active blink */
5929 ath_led_blink(sc, sc->sc_hwmap[rix].ledon, sc->sc_hwmap[rix].ledoff);
5933 ath_rate_setup(struct ath_softc *sc, u_int mode)
5935 struct ath_hal *ah = sc->sc_ah;
5936 const HAL_RATE_TABLE *rt;
5939 case IEEE80211_MODE_11A:
5940 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
5942 case IEEE80211_MODE_HALF:
5943 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
5945 case IEEE80211_MODE_QUARTER:
5946 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
5948 case IEEE80211_MODE_11B:
5949 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
5951 case IEEE80211_MODE_11G:
5952 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
5954 case IEEE80211_MODE_TURBO_A:
5955 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
5957 case IEEE80211_MODE_TURBO_G:
5958 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
5960 case IEEE80211_MODE_STURBO_A:
5961 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
5963 case IEEE80211_MODE_11NA:
5964 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
5966 case IEEE80211_MODE_11NG:
5967 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
5970 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
5974 sc->sc_rates[mode] = rt;
5975 return (rt != NULL);
5979 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
5981 #define N(a) (sizeof(a)/sizeof(a[0]))
5982 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
5983 static const struct {
5984 u_int rate; /* tx/rx 802.11 rate */
5985 u_int16_t timeOn; /* LED on time (ms) */
5986 u_int16_t timeOff; /* LED off time (ms) */
6002 /* XXX half/quarter rates */
6004 const HAL_RATE_TABLE *rt;
6007 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
6008 rt = sc->sc_rates[mode];
6009 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
6010 for (i = 0; i < rt->rateCount; i++) {
6011 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6012 if (rt->info[i].phy != IEEE80211_T_HT)
6013 sc->sc_rixmap[ieeerate] = i;
6015 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
6017 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6018 for (i = 0; i < N(sc->sc_hwmap); i++) {
6019 if (i >= rt->rateCount) {
6020 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6021 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6024 sc->sc_hwmap[i].ieeerate =
6025 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6026 if (rt->info[i].phy == IEEE80211_T_HT)
6027 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
6028 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6029 if (rt->info[i].shortPreamble ||
6030 rt->info[i].phy == IEEE80211_T_OFDM)
6031 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6032 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
6033 for (j = 0; j < N(blinkrates)-1; j++)
6034 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6036 /* NB: this uses the last entry if the rate isn't found */
6037 /* XXX beware of overlow */
6038 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6039 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6041 sc->sc_currates = rt;
6042 sc->sc_curmode = mode;
6044 * All protection frames are transmited at 2Mb/s for
6045 * 11g, otherwise at 1Mb/s.
6047 if (mode == IEEE80211_MODE_11G)
6048 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
6050 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
6051 /* NB: caller is responsible for reseting rate control state */
6057 ath_printrxbuf(struct ath_softc *sc, const struct ath_buf *bf,
6060 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
6061 struct ath_hal *ah = sc->sc_ah;
6062 const struct ath_desc *ds;
6065 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
6066 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n"
6067 " %08x %08x %08x %08x\n",
6068 ix, ds, (const struct ath_desc *)bf->bf_daddr + i,
6069 ds->ds_link, ds->ds_data,
6070 !done ? "" : (rs->rs_status == 0) ? " *" : " !",
6071 ds->ds_ctl0, ds->ds_ctl1,
6072 ds->ds_hw[0], ds->ds_hw[1]);
6073 if (ah->ah_magic == 0x20065416) {
6074 printf(" %08x %08x %08x %08x %08x %08x %08x\n",
6075 ds->ds_hw[2], ds->ds_hw[3], ds->ds_hw[4],
6076 ds->ds_hw[5], ds->ds_hw[6], ds->ds_hw[7],
6083 ath_printtxbuf(struct ath_softc *sc, const struct ath_buf *bf,
6084 u_int qnum, u_int ix, int done)
6086 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
6087 struct ath_hal *ah = sc->sc_ah;
6088 const struct ath_desc *ds;
6091 printf("Q%u[%3u]", qnum, ix);
6092 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
6093 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
6094 " %08x %08x %08x %08x %08x %08x\n",
6095 ds, (const struct ath_desc *)bf->bf_daddr + i,
6096 ds->ds_link, ds->ds_data, bf->bf_txflags,
6097 !done ? "" : (ts->ts_status == 0) ? " *" : " !",
6098 ds->ds_ctl0, ds->ds_ctl1,
6099 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
6100 if (ah->ah_magic == 0x20065416) {
6101 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n",
6102 ds->ds_hw[4], ds->ds_hw[5], ds->ds_hw[6],
6103 ds->ds_hw[7], ds->ds_hw[8], ds->ds_hw[9],
6104 ds->ds_hw[10],ds->ds_hw[11]);
6105 printf(" %08x %08x %08x %08x %08x %08x %08x %08x\n",
6106 ds->ds_hw[12],ds->ds_hw[13],ds->ds_hw[14],
6107 ds->ds_hw[15],ds->ds_hw[16],ds->ds_hw[17],
6108 ds->ds_hw[18], ds->ds_hw[19]);
6112 #endif /* ATH_DEBUG */
6115 ath_watchdog(void *arg)
6117 struct ath_softc *sc = arg;
6119 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
6120 struct ifnet *ifp = sc->sc_ifp;
6123 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
6125 if_printf(ifp, "%s hang detected (0x%x)\n",
6126 hangs & 0xff ? "bb" : "mac", hangs);
6128 if_printf(ifp, "device timeout\n");
6131 sc->sc_stats.ast_watchdog++;
6133 callout_schedule(&sc->sc_wd_ch, hz);
6138 * Diagnostic interface to the HAL. This is used by various
6139 * tools to do things like retrieve register contents for
6140 * debugging. The mechanism is intentionally opaque so that
6141 * it can change frequently w/o concern for compatiblity.
6144 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
6146 struct ath_hal *ah = sc->sc_ah;
6147 u_int id = ad->ad_id & ATH_DIAG_ID;
6148 void *indata = NULL;
6149 void *outdata = NULL;
6150 u_int32_t insize = ad->ad_in_size;
6151 u_int32_t outsize = ad->ad_out_size;
6154 if (ad->ad_id & ATH_DIAG_IN) {
6158 indata = malloc(insize, M_TEMP, M_NOWAIT);
6159 if (indata == NULL) {
6163 error = copyin(ad->ad_in_data, indata, insize);
6167 if (ad->ad_id & ATH_DIAG_DYN) {
6169 * Allocate a buffer for the results (otherwise the HAL
6170 * returns a pointer to a buffer where we can read the
6171 * results). Note that we depend on the HAL leaving this
6172 * pointer for us to use below in reclaiming the buffer;
6173 * may want to be more defensive.
6175 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
6176 if (outdata == NULL) {
6181 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
6182 if (outsize < ad->ad_out_size)
6183 ad->ad_out_size = outsize;
6184 if (outdata != NULL)
6185 error = copyout(outdata, ad->ad_out_data,
6191 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
6192 free(indata, M_TEMP);
6193 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
6194 free(outdata, M_TEMP);
6197 #endif /* ATH_DIAGAPI */
6200 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
6202 #define IS_RUNNING(ifp) \
6203 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
6204 struct ath_softc *sc = ifp->if_softc;
6205 struct ieee80211com *ic = ifp->if_l2com;
6206 struct ifreq *ifr = (struct ifreq *)data;
6207 const HAL_RATE_TABLE *rt;
6213 if (IS_RUNNING(ifp)) {
6215 * To avoid rescanning another access point,
6216 * do not call ath_init() here. Instead,
6217 * only reflect promisc mode settings.
6220 } else if (ifp->if_flags & IFF_UP) {
6222 * Beware of being called during attach/detach
6223 * to reset promiscuous mode. In that case we
6224 * will still be marked UP but not RUNNING.
6225 * However trying to re-init the interface
6226 * is the wrong thing to do as we've already
6227 * torn down much of our state. There's
6228 * probably a better way to deal with this.
6230 if (!sc->sc_invalid)
6231 ath_init(sc); /* XXX lose error */
6233 ath_stop_locked(ifp);
6235 /* XXX must wakeup in places like ath_vap_delete */
6236 if (!sc->sc_invalid)
6237 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
6244 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
6247 /* NB: embed these numbers to get a consistent view */
6248 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
6249 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
6250 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
6251 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
6252 #ifdef IEEE80211_SUPPORT_TDMA
6253 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
6254 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
6256 rt = sc->sc_currates;
6258 sc->sc_stats.ast_tx_rate =
6259 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
6260 return copyout(&sc->sc_stats,
6261 ifr->ifr_data, sizeof (sc->sc_stats));
6263 error = priv_check(curthread, PRIV_DRIVER);
6265 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
6269 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
6273 error = ether_ioctl(ifp, cmd, data);
6284 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
6286 struct ath_softc *sc = arg1;
6287 u_int slottime = ath_hal_getslottime(sc->sc_ah);
6290 error = sysctl_handle_int(oidp, &slottime, 0, req);
6291 if (error || !req->newptr)
6293 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
6297 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
6299 struct ath_softc *sc = arg1;
6300 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah);
6303 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
6304 if (error || !req->newptr)
6306 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
6310 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
6312 struct ath_softc *sc = arg1;
6313 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
6316 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
6317 if (error || !req->newptr)
6319 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
6323 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
6325 struct ath_softc *sc = arg1;
6326 int softled = sc->sc_softled;
6329 error = sysctl_handle_int(oidp, &softled, 0, req);
6330 if (error || !req->newptr)
6332 softled = (softled != 0);
6333 if (softled != sc->sc_softled) {
6335 /* NB: handle any sc_ledpin change */
6336 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
6337 HAL_GPIO_MUX_MAC_NETWORK_LED);
6338 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
6341 sc->sc_softled = softled;
6347 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS)
6349 struct ath_softc *sc = arg1;
6350 int ledpin = sc->sc_ledpin;
6353 error = sysctl_handle_int(oidp, &ledpin, 0, req);
6354 if (error || !req->newptr)
6356 if (ledpin != sc->sc_ledpin) {
6357 sc->sc_ledpin = ledpin;
6358 if (sc->sc_softled) {
6359 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin,
6360 HAL_GPIO_MUX_MAC_NETWORK_LED);
6361 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
6369 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS)
6371 struct ath_softc *sc = arg1;
6372 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah);
6375 error = sysctl_handle_int(oidp, &txantenna, 0, req);
6376 if (!error && req->newptr) {
6377 /* XXX assumes 2 antenna ports */
6378 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B)
6380 ath_hal_setantennaswitch(sc->sc_ah, txantenna);
6382 * NB: with the switch locked this isn't meaningful,
6383 * but set it anyway so things like radiotap get
6384 * consistent info in their data.
6386 sc->sc_txantenna = txantenna;
6392 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
6394 struct ath_softc *sc = arg1;
6395 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah);
6398 error = sysctl_handle_int(oidp, &defantenna, 0, req);
6399 if (!error && req->newptr)
6400 ath_hal_setdefantenna(sc->sc_ah, defantenna);
6405 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
6407 struct ath_softc *sc = arg1;
6408 u_int diversity = ath_hal_getdiversity(sc->sc_ah);
6411 error = sysctl_handle_int(oidp, &diversity, 0, req);
6412 if (error || !req->newptr)
6414 if (!ath_hal_setdiversity(sc->sc_ah, diversity))
6416 sc->sc_diversity = diversity;
6421 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
6423 struct ath_softc *sc = arg1;
6427 if (!ath_hal_getdiag(sc->sc_ah, &diag))
6429 error = sysctl_handle_int(oidp, &diag, 0, req);
6430 if (error || !req->newptr)
6432 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
6436 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
6438 struct ath_softc *sc = arg1;
6439 struct ifnet *ifp = sc->sc_ifp;
6443 (void) ath_hal_gettpscale(sc->sc_ah, &scale);
6444 error = sysctl_handle_int(oidp, &scale, 0, req);
6445 if (error || !req->newptr)
6447 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL :
6448 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0;
6452 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
6454 struct ath_softc *sc = arg1;
6455 u_int tpc = ath_hal_gettpc(sc->sc_ah);
6458 error = sysctl_handle_int(oidp, &tpc, 0, req);
6459 if (error || !req->newptr)
6461 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
6465 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS)
6467 struct ath_softc *sc = arg1;
6468 struct ifnet *ifp = sc->sc_ifp;
6469 struct ath_hal *ah = sc->sc_ah;
6470 u_int rfkill = ath_hal_getrfkill(ah);
6473 error = sysctl_handle_int(oidp, &rfkill, 0, req);
6474 if (error || !req->newptr)
6476 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */
6478 if (!ath_hal_setrfkill(ah, rfkill))
6480 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0;
6484 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS)
6486 struct ath_softc *sc = arg1;
6490 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent);
6491 error = sysctl_handle_int(oidp, &rfsilent, 0, req);
6492 if (error || !req->newptr)
6494 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent))
6496 sc->sc_rfsilentpin = rfsilent & 0x1c;
6497 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0;
6502 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS)
6504 struct ath_softc *sc = arg1;
6508 (void) ath_hal_gettpack(sc->sc_ah, &tpack);
6509 error = sysctl_handle_int(oidp, &tpack, 0, req);
6510 if (error || !req->newptr)
6512 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0;
6516 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS)
6518 struct ath_softc *sc = arg1;
6522 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts);
6523 error = sysctl_handle_int(oidp, &tpcts, 0, req);
6524 if (error || !req->newptr)
6526 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0;
6530 ath_sysctl_intmit(SYSCTL_HANDLER_ARGS)
6532 struct ath_softc *sc = arg1;
6535 intmit = ath_hal_getintmit(sc->sc_ah);
6536 error = sysctl_handle_int(oidp, &intmit, 0, req);
6537 if (error || !req->newptr)
6539 return !ath_hal_setintmit(sc->sc_ah, intmit) ? EINVAL : 0;
6542 #ifdef IEEE80211_SUPPORT_TDMA
6544 ath_sysctl_setcca(SYSCTL_HANDLER_ARGS)
6546 struct ath_softc *sc = arg1;
6549 setcca = sc->sc_setcca;
6550 error = sysctl_handle_int(oidp, &setcca, 0, req);
6551 if (error || !req->newptr)
6553 sc->sc_setcca = (setcca != 0);
6556 #endif /* IEEE80211_SUPPORT_TDMA */
6559 ath_sysctlattach(struct ath_softc *sc)
6561 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
6562 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
6563 struct ath_hal *ah = sc->sc_ah;
6565 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6566 "countrycode", CTLFLAG_RD, &sc->sc_eecc, 0,
6567 "EEPROM country code");
6568 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6569 "regdomain", CTLFLAG_RD, &sc->sc_eerd, 0,
6570 "EEPROM regdomain code");
6572 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6573 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
6574 "control debugging printfs");
6576 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6577 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6578 ath_sysctl_slottime, "I", "802.11 slot time (us)");
6579 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6580 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6581 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
6582 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6583 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6584 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
6585 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6586 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6587 ath_sysctl_softled, "I", "enable/disable software LED support");
6588 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6589 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6590 ath_sysctl_ledpin, "I", "GPIO pin connected to LED");
6591 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6592 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
6593 "setting to turn LED on");
6594 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6595 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
6596 "idle time for inactivity LED (ticks)");
6597 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6598 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6599 ath_sysctl_txantenna, "I", "antenna switch");
6600 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6601 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6602 ath_sysctl_rxantenna, "I", "default/rx antenna");
6603 if (ath_hal_hasdiversity(ah))
6604 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6605 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6606 ath_sysctl_diversity, "I", "antenna diversity");
6607 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
6608 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6609 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
6610 "tx descriptor batching");
6611 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6612 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6613 ath_sysctl_diag, "I", "h/w diagnostic control");
6614 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6615 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6616 ath_sysctl_tpscale, "I", "tx power scaling");
6617 if (ath_hal_hastpc(ah)) {
6618 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6619 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6620 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
6621 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6622 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6623 ath_sysctl_tpack, "I", "tx power for ack frames");
6624 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6625 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6626 ath_sysctl_tpcts, "I", "tx power for cts frames");
6628 if (ath_hal_hasrfsilent(ah)) {
6629 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6630 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6631 ath_sysctl_rfsilent, "I", "h/w RF silent config");
6632 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6633 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6634 ath_sysctl_rfkill, "I", "enable/disable RF kill switch");
6636 if (ath_hal_hasintmit(ah)) {
6637 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6638 "intmit", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6639 ath_sysctl_intmit, "I", "interference mitigation");
6641 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
6642 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6643 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
6644 "mask of error frames to pass when monitoring");
6645 #ifdef IEEE80211_SUPPORT_TDMA
6646 if (ath_hal_macversion(ah) > 0x78) {
6647 sc->sc_tdmadbaprep = 2;
6648 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6649 "dbaprep", CTLFLAG_RW, &sc->sc_tdmadbaprep, 0,
6650 "TDMA DBA preparation time");
6651 sc->sc_tdmaswbaprep = 10;
6652 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6653 "swbaprep", CTLFLAG_RW, &sc->sc_tdmaswbaprep, 0,
6654 "TDMA SWBA preparation time");
6655 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6656 "guardtime", CTLFLAG_RW, &sc->sc_tdmaguard, 0,
6657 "TDMA slot guard time");
6658 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6659 "superframe", CTLFLAG_RD, &sc->sc_tdmabintval, 0,
6660 "TDMA calculated super frame");
6661 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6662 "setcca", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6663 ath_sysctl_setcca, "I", "enable CCA control");
6669 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
6670 struct ath_buf *bf, struct mbuf *m0,
6671 const struct ieee80211_bpf_params *params)
6673 struct ifnet *ifp = sc->sc_ifp;
6674 struct ieee80211com *ic = ifp->if_l2com;
6675 struct ath_hal *ah = sc->sc_ah;
6676 struct ieee80211vap *vap = ni->ni_vap;
6677 int error, ismcast, ismrr;
6678 int keyix, hdrlen, pktlen, try0, txantenna;
6679 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3;
6680 struct ieee80211_frame *wh;
6681 u_int flags, ctsduration;
6683 const HAL_RATE_TABLE *rt;
6684 struct ath_desc *ds;
6687 wh = mtod(m0, struct ieee80211_frame *);
6688 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
6689 hdrlen = ieee80211_anyhdrsize(wh);
6691 * Packet length must not include any
6692 * pad bytes; deduct them here.
6694 /* XXX honor IEEE80211_BPF_DATAPAD */
6695 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN;
6697 if (params->ibp_flags & IEEE80211_BPF_CRYPTO) {
6698 const struct ieee80211_cipher *cip;
6699 struct ieee80211_key *k;
6702 * Construct the 802.11 header+trailer for an encrypted
6703 * frame. The only reason this can fail is because of an
6704 * unknown or unsupported cipher/key type.
6706 k = ieee80211_crypto_encap(ni, m0);
6709 * This can happen when the key is yanked after the
6710 * frame was queued. Just discard the frame; the
6711 * 802.11 layer counts failures and provides
6712 * debugging/diagnostics.
6718 * Adjust the packet + header lengths for the crypto
6719 * additions and calculate the h/w key index. When
6720 * a s/w mic is done the frame will have had any mic
6721 * added to it prior to entry so m0->m_pkthdr.len will
6722 * account for it. Otherwise we need to add it to the
6726 hdrlen += cip->ic_header;
6727 pktlen += cip->ic_header + cip->ic_trailer;
6728 /* NB: frags always have any TKIP MIC done in s/w */
6729 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
6730 pktlen += cip->ic_miclen;
6731 keyix = k->wk_keyix;
6733 /* packet header may have moved, reset our local pointer */
6734 wh = mtod(m0, struct ieee80211_frame *);
6735 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
6737 * Use station key cache slot, if assigned.
6739 keyix = ni->ni_ucastkey.wk_keyix;
6740 if (keyix == IEEE80211_KEYIX_NONE)
6741 keyix = HAL_TXKEYIX_INVALID;
6743 keyix = HAL_TXKEYIX_INVALID;
6745 error = ath_tx_dmasetup(sc, bf, m0);
6748 m0 = bf->bf_m; /* NB: may have changed */
6749 wh = mtod(m0, struct ieee80211_frame *);
6750 bf->bf_node = ni; /* NB: held reference */
6752 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
6753 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
6754 if (params->ibp_flags & IEEE80211_BPF_RTS)
6755 flags |= HAL_TXDESC_RTSENA;
6756 else if (params->ibp_flags & IEEE80211_BPF_CTS)
6757 flags |= HAL_TXDESC_CTSENA;
6758 /* XXX leave ismcast to injector? */
6759 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast)
6760 flags |= HAL_TXDESC_NOACK;
6762 rt = sc->sc_currates;
6763 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
6764 rix = ath_tx_findrix(sc, params->ibp_rate0);
6765 txrate = rt->info[rix].rateCode;
6766 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6767 txrate |= rt->info[rix].shortPreamble;
6769 try0 = params->ibp_try0;
6770 ismrr = (params->ibp_try1 != 0);
6771 txantenna = params->ibp_pri >> 2;
6772 if (txantenna == 0) /* XXX? */
6773 txantenna = sc->sc_txantenna;
6775 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) {
6776 cix = ath_tx_findrix(sc, params->ibp_ctsrate);
6777 ctsrate = rt->info[cix].rateCode;
6778 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) {
6779 ctsrate |= rt->info[cix].shortPreamble;
6780 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
6781 ctsduration += rt->info[cix].spAckDuration;
6782 ctsduration += ath_hal_computetxtime(ah,
6783 rt, pktlen, rix, AH_TRUE);
6784 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
6785 ctsduration += rt->info[rix].spAckDuration;
6787 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
6788 ctsduration += rt->info[cix].lpAckDuration;
6789 ctsduration += ath_hal_computetxtime(ah,
6790 rt, pktlen, rix, AH_FALSE);
6791 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
6792 ctsduration += rt->info[rix].lpAckDuration;
6794 ismrr = 0; /* XXX */
6797 pri = params->ibp_pri & 3;
6799 * NB: we mark all packets as type PSPOLL so the h/w won't
6800 * set the sequence number, duration, etc.
6802 atype = HAL_PKT_TYPE_PSPOLL;
6804 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
6805 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
6806 sc->sc_hwmap[rix].ieeerate, -1);
6808 if (ieee80211_radiotap_active_vap(vap)) {
6809 u_int64_t tsf = ath_hal_gettsf64(ah);
6811 sc->sc_tx_th.wt_tsf = htole64(tsf);
6812 sc->sc_tx_th.wt_flags = sc->sc_hwmap[rix].txflags;
6813 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
6814 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
6815 if (m0->m_flags & M_FRAG)
6816 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
6817 sc->sc_tx_th.wt_rate = sc->sc_hwmap[rix].ieeerate;
6818 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
6819 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
6821 ieee80211_radiotap_tx(vap, m0);
6825 * Formulate first tx descriptor with tx controls.
6828 /* XXX check return value? */
6829 ath_hal_setuptxdesc(ah, ds
6830 , pktlen /* packet length */
6831 , hdrlen /* header length */
6832 , atype /* Atheros packet type */
6833 , params->ibp_power /* txpower */
6834 , txrate, try0 /* series 0 rate/tries */
6835 , keyix /* key cache index */
6836 , txantenna /* antenna mode */
6838 , ctsrate /* rts/cts rate */
6839 , ctsduration /* rts/cts duration */
6841 bf->bf_txflags = flags;
6844 rix = ath_tx_findrix(sc, params->ibp_rate1);
6845 rate1 = rt->info[rix].rateCode;
6846 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6847 rate1 |= rt->info[rix].shortPreamble;
6848 if (params->ibp_try2) {
6849 rix = ath_tx_findrix(sc, params->ibp_rate2);
6850 rate2 = rt->info[rix].rateCode;
6851 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6852 rate2 |= rt->info[rix].shortPreamble;
6855 if (params->ibp_try3) {
6856 rix = ath_tx_findrix(sc, params->ibp_rate3);
6857 rate3 = rt->info[rix].rateCode;
6858 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6859 rate3 |= rt->info[rix].shortPreamble;
6862 ath_hal_setupxtxdesc(ah, ds
6863 , rate1, params->ibp_try1 /* series 1 */
6864 , rate2, params->ibp_try2 /* series 2 */
6865 , rate3, params->ibp_try3 /* series 3 */
6869 /* NB: no buffered multicast in power save support */
6870 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf);
6875 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
6876 const struct ieee80211_bpf_params *params)
6878 struct ieee80211com *ic = ni->ni_ic;
6879 struct ifnet *ifp = ic->ic_ifp;
6880 struct ath_softc *sc = ifp->if_softc;
6884 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) {
6885 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: discard frame, %s", __func__,
6886 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ?
6887 "!running" : "invalid");
6893 * Grab a TX buffer and associated resources.
6895 bf = ath_getbuf(sc);
6897 sc->sc_stats.ast_tx_nobuf++;
6903 if (params == NULL) {
6905 * Legacy path; interpret frame contents to decide
6906 * precisely how to send the frame.
6908 if (ath_tx_start(sc, ni, bf, m)) {
6909 error = EIO; /* XXX */
6914 * Caller supplied explicit parameters to use in
6915 * sending the frame.
6917 if (ath_tx_raw_start(sc, ni, bf, m, params)) {
6918 error = EIO; /* XXX */
6922 sc->sc_wd_timer = 5;
6924 sc->sc_stats.ast_tx_raw++;
6929 STAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
6930 ATH_TXBUF_UNLOCK(sc);
6933 sc->sc_stats.ast_tx_raw_fail++;
6934 ieee80211_free_node(ni);
6939 * Announce various information on device/driver attach.
6942 ath_announce(struct ath_softc *sc)
6944 struct ifnet *ifp = sc->sc_ifp;
6945 struct ath_hal *ah = sc->sc_ah;
6947 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
6948 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
6949 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6952 for (i = 0; i <= WME_AC_VO; i++) {
6953 struct ath_txq *txq = sc->sc_ac2q[i];
6954 if_printf(ifp, "Use hw queue %u for %s traffic\n",
6955 txq->axq_qnum, ieee80211_wme_acnames[i]);
6957 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
6958 sc->sc_cabq->axq_qnum);
6959 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
6961 if (ath_rxbuf != ATH_RXBUF)
6962 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
6963 if (ath_txbuf != ATH_TXBUF)
6964 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
6965 if (sc->sc_mcastkey && bootverbose)
6966 if_printf(ifp, "using multicast key search\n");
6969 #ifdef IEEE80211_SUPPORT_TDMA
6970 static __inline uint32_t
6971 ath_hal_getnexttbtt(struct ath_hal *ah)
6973 #define AR_TIMER0 0x8028
6974 return OS_REG_READ(ah, AR_TIMER0);
6977 static __inline void
6978 ath_hal_adjusttsf(struct ath_hal *ah, int32_t tsfdelta)
6980 /* XXX handle wrap/overflow */
6981 OS_REG_WRITE(ah, AR_TSF_L32, OS_REG_READ(ah, AR_TSF_L32) + tsfdelta);
6985 ath_tdma_settimers(struct ath_softc *sc, u_int32_t nexttbtt, u_int32_t bintval)
6987 struct ath_hal *ah = sc->sc_ah;
6988 HAL_BEACON_TIMERS bt;
6990 bt.bt_intval = bintval | HAL_BEACON_ENA;
6991 bt.bt_nexttbtt = nexttbtt;
6992 bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep;
6993 bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep;
6994 bt.bt_nextatim = nexttbtt+1;
6995 ath_hal_beaconsettimers(ah, &bt);
6999 * Calculate the beacon interval. This is periodic in the
7000 * superframe for the bss. We assume each station is configured
7001 * identically wrt transmit rate so the guard time we calculate
7002 * above will be the same on all stations. Note we need to
7003 * factor in the xmit time because the hardware will schedule
7004 * a frame for transmit if the start of the frame is within
7005 * the burst time. When we get hardware that properly kills
7006 * frames in the PCU we can reduce/eliminate the guard time.
7008 * Roundup to 1024 is so we have 1 TU buffer in the guard time
7009 * to deal with the granularity of the nexttbtt timer. 11n MAC's
7010 * with 1us timer granularity should allow us to reduce/eliminate
7014 ath_tdma_bintvalsetup(struct ath_softc *sc,
7015 const struct ieee80211_tdma_state *tdma)
7017 /* copy from vap state (XXX check all vaps have same value?) */
7018 sc->sc_tdmaslotlen = tdma->tdma_slotlen;
7020 sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) *
7021 tdma->tdma_slotcnt, 1024);
7022 sc->sc_tdmabintval >>= 10; /* TSF -> TU */
7023 if (sc->sc_tdmabintval & 1)
7024 sc->sc_tdmabintval++;
7026 if (tdma->tdma_slot == 0) {
7028 * Only slot 0 beacons; other slots respond.
7030 sc->sc_imask |= HAL_INT_SWBA;
7031 sc->sc_tdmaswba = 0; /* beacon immediately */
7033 /* XXX all vaps must be slot 0 or slot !0 */
7034 sc->sc_imask &= ~HAL_INT_SWBA;
7039 * Max 802.11 overhead. This assumes no 4-address frames and
7040 * the encapsulation done by ieee80211_encap (llc). We also
7041 * include potential crypto overhead.
7043 #define IEEE80211_MAXOVERHEAD \
7044 (sizeof(struct ieee80211_qosframe) \
7045 + sizeof(struct llc) \
7046 + IEEE80211_ADDR_LEN \
7047 + IEEE80211_WEP_IVLEN \
7048 + IEEE80211_WEP_KIDLEN \
7049 + IEEE80211_WEP_CRCLEN \
7050 + IEEE80211_WEP_MICLEN \
7051 + IEEE80211_CRC_LEN)
7054 * Setup initially for tdma operation. Start the beacon
7055 * timers and enable SWBA if we are slot 0. Otherwise
7056 * we wait for slot 0 to arrive so we can sync up before
7057 * starting to transmit.
7060 ath_tdma_config(struct ath_softc *sc, struct ieee80211vap *vap)
7062 struct ath_hal *ah = sc->sc_ah;
7063 struct ifnet *ifp = sc->sc_ifp;
7064 struct ieee80211com *ic = ifp->if_l2com;
7065 const struct ieee80211_txparam *tp;
7066 const struct ieee80211_tdma_state *tdma = NULL;
7070 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
7072 if_printf(ifp, "%s: no vaps?\n", __func__);
7076 tp = vap->iv_bss->ni_txparms;
7078 * Calculate the guard time for each slot. This is the
7079 * time to send a maximal-size frame according to the
7080 * fixed/lowest transmit rate. Note that the interface
7081 * mtu does not include the 802.11 overhead so we must
7082 * tack that on (ath_hal_computetxtime includes the
7083 * preamble and plcp in it's calculation).
7085 tdma = vap->iv_tdma;
7086 if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
7087 rix = ath_tx_findrix(sc, tp->ucastrate);
7089 rix = ath_tx_findrix(sc, tp->mcastrate);
7090 /* XXX short preamble assumed */
7091 sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,
7092 ifp->if_mtu + IEEE80211_MAXOVERHEAD, rix, AH_TRUE);
7094 ath_hal_intrset(ah, 0);
7096 ath_beaconq_config(sc); /* setup h/w beacon q */
7098 ath_hal_setcca(ah, AH_FALSE); /* disable CCA */
7099 ath_tdma_bintvalsetup(sc, tdma); /* calculate beacon interval */
7100 ath_tdma_settimers(sc, sc->sc_tdmabintval,
7101 sc->sc_tdmabintval | HAL_BEACON_RESET_TSF);
7102 sc->sc_syncbeacon = 0;
7104 sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER;
7105 sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER;
7107 ath_hal_intrset(ah, sc->sc_imask);
7109 DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u "
7110 "bsched %u guard %uus bintval %u TU dba prep %u\n", __func__,
7111 tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt,
7112 tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval,
7113 sc->sc_tdmadbaprep);
7117 * Update tdma operation. Called from the 802.11 layer
7118 * when a beacon is received from the TDMA station operating
7119 * in the slot immediately preceding us in the bss. Use
7120 * the rx timestamp for the beacon frame to update our
7121 * beacon timers so we follow their schedule. Note that
7122 * by using the rx timestamp we implicitly include the
7123 * propagation delay in our schedule.
7126 ath_tdma_update(struct ieee80211_node *ni,
7127 const struct ieee80211_tdma_param *tdma, int changed)
7129 #define TSF_TO_TU(_h,_l) \
7130 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
7131 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10)
7132 struct ieee80211vap *vap = ni->ni_vap;
7133 struct ieee80211com *ic = ni->ni_ic;
7134 struct ath_softc *sc = ic->ic_ifp->if_softc;
7135 struct ath_hal *ah = sc->sc_ah;
7136 const HAL_RATE_TABLE *rt = sc->sc_currates;
7137 u_int64_t tsf, rstamp, nextslot;
7138 u_int32_t txtime, nextslottu, timer0;
7139 int32_t tudelta, tsfdelta;
7140 const struct ath_rx_status *rs;
7143 sc->sc_stats.ast_tdma_update++;
7146 * Check for and adopt configuration changes.
7149 const struct ieee80211_tdma_state *ts = vap->iv_tdma;
7151 ath_tdma_bintvalsetup(sc, ts);
7152 if (changed & TDMA_UPDATE_SLOTLEN)
7155 DPRINTF(sc, ATH_DEBUG_TDMA,
7156 "%s: adopt slot %u slotcnt %u slotlen %u us "
7157 "bintval %u TU\n", __func__,
7158 ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen,
7159 sc->sc_tdmabintval);
7162 ath_hal_intrset(ah, sc->sc_imask);
7163 /* NB: beacon timers programmed below */
7166 /* extend rx timestamp to 64 bits */
7168 tsf = ath_hal_gettsf64(ah);
7169 rstamp = ath_extend_tsf(rs->rs_tstamp, tsf);
7171 * The rx timestamp is set by the hardware on completing
7172 * reception (at the point where the rx descriptor is DMA'd
7173 * to the host). To find the start of our next slot we
7174 * must adjust this time by the time required to send
7175 * the packet just received.
7177 rix = rt->rateCodeToIndex[rs->rs_rate];
7178 txtime = ath_hal_computetxtime(ah, rt, rs->rs_datalen, rix,
7179 rt->info[rix].shortPreamble);
7180 /* NB: << 9 is to cvt to TU and /2 */
7181 nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9);
7182 nextslottu = TSF_TO_TU(nextslot>>32, nextslot) & HAL_BEACON_PERIOD;
7185 * TIMER0 is the h/w's idea of NextTBTT (in TU's). Convert
7186 * to usecs and calculate the difference between what the
7187 * other station thinks and what we have programmed. This
7188 * lets us figure how to adjust our timers to match. The
7189 * adjustments are done by pulling the TSF forward and possibly
7190 * rewriting the beacon timers.
7192 timer0 = ath_hal_getnexttbtt(ah);
7193 tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD+1)) - TU_TO_TSF(timer0));
7195 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
7196 "tsfdelta %d avg +%d/-%d\n", tsfdelta,
7197 TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam));
7200 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
7201 TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta);
7202 tsfdelta = -tsfdelta % 1024;
7204 } else if (tsfdelta > 0) {
7205 TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta);
7206 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
7207 tsfdelta = 1024 - (tsfdelta % 1024);
7210 TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);
7211 TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);
7213 tudelta = nextslottu - timer0;
7216 * Copy sender's timetstamp into tdma ie so they can
7217 * calculate roundtrip time. We submit a beacon frame
7218 * below after any timer adjustment. The frame goes out
7219 * at the next TBTT so the sender can calculate the
7220 * roundtrip by inspecting the tdma ie in our beacon frame.
7222 * NB: This tstamp is subtlely preserved when
7223 * IEEE80211_BEACON_TDMA is marked (e.g. when the
7224 * slot position changes) because ieee80211_add_tdma
7225 * skips over the data.
7227 memcpy(ATH_VAP(vap)->av_boff.bo_tdma +
7228 __offsetof(struct ieee80211_tdma_param, tdma_tstamp),
7229 &ni->ni_tstamp.data, 8);
7231 DPRINTF(sc, ATH_DEBUG_TDMA_TIMER,
7232 "tsf %llu nextslot %llu (%d, %d) nextslottu %u timer0 %u (%d)\n",
7233 (unsigned long long) tsf, (unsigned long long) nextslot,
7234 (int)(nextslot - tsf), tsfdelta,
7235 nextslottu, timer0, tudelta);
7238 * Adjust the beacon timers only when pulling them forward
7239 * or when going back by less than the beacon interval.
7240 * Negative jumps larger than the beacon interval seem to
7241 * cause the timers to stop and generally cause instability.
7242 * This basically filters out jumps due to missed beacons.
7244 if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) {
7245 ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval);
7246 sc->sc_stats.ast_tdma_timers++;
7249 ath_hal_adjusttsf(ah, tsfdelta);
7250 sc->sc_stats.ast_tdma_tsf++;
7252 ath_tdma_beacon_send(sc, vap); /* prepare response */
7258 * Transmit a beacon frame at SWBA. Dynamic updates
7259 * to the frame contents are done as needed.
7262 ath_tdma_beacon_send(struct ath_softc *sc, struct ieee80211vap *vap)
7264 struct ath_hal *ah = sc->sc_ah;
7269 * Check if the previous beacon has gone out. If
7270 * not don't try to post another, skip this period
7271 * and wait for the next. Missed beacons indicate
7272 * a problem and should not occur. If we miss too
7273 * many consecutive beacons reset the device.
7275 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
7276 sc->sc_bmisscount++;
7277 DPRINTF(sc, ATH_DEBUG_BEACON,
7278 "%s: missed %u consecutive beacons\n",
7279 __func__, sc->sc_bmisscount);
7280 if (sc->sc_bmisscount >= ath_bstuck_threshold)
7281 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
7284 if (sc->sc_bmisscount != 0) {
7285 DPRINTF(sc, ATH_DEBUG_BEACON,
7286 "%s: resume beacon xmit after %u misses\n",
7287 __func__, sc->sc_bmisscount);
7288 sc->sc_bmisscount = 0;
7292 * Check recent per-antenna transmit statistics and flip
7293 * the default antenna if noticeably more frames went out
7294 * on the non-default antenna.
7295 * XXX assumes 2 anntenae
7297 if (!sc->sc_diversity) {
7298 otherant = sc->sc_defant & 1 ? 2 : 1;
7299 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
7300 ath_setdefantenna(sc, otherant);
7301 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
7304 bf = ath_beacon_generate(sc, vap);
7307 * Stop any current dma and put the new frame on the queue.
7308 * This should never fail since we check above that no frames
7309 * are still pending on the queue.
7311 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
7312 DPRINTF(sc, ATH_DEBUG_ANY,
7313 "%s: beacon queue %u did not stop?\n",
7314 __func__, sc->sc_bhalq);
7315 /* NB: the HAL still stops DMA, so proceed */
7317 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
7318 ath_hal_txstart(ah, sc->sc_bhalq);
7320 sc->sc_stats.ast_be_xmit++; /* XXX per-vap? */
7323 * Record local TSF for our last send for use
7324 * in arbitrating slot collisions.
7326 vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);
7329 #endif /* IEEE80211_SUPPORT_TDMA */