sys/dev/e1000/e1000_82571.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82571EB Gigabit Ethernet Controller
  37  * 82571EB Gigabit Ethernet Controller (Copper)
  38  * 82571EB Gigabit Ethernet Controller (Fiber)
  39  * 82571EB Dual Port Gigabit Mezzanine Adapter
  40  * 82571EB Quad Port Gigabit Mezzanine Adapter
  41  * 82571PT Gigabit PT Quad Port Server ExpressModule
  42  * 82572EI Gigabit Ethernet Controller (Copper)
  43  * 82572EI Gigabit Ethernet Controller (Fiber)
  44  * 82572EI Gigabit Ethernet Controller
  45  * 82573V Gigabit Ethernet Controller (Copper)
  46  * 82573E Gigabit Ethernet Controller (Copper)
  47  * 82573L Gigabit Ethernet Controller
  48  * 82574L Gigabit Network Connection
  49  * 82583V Gigabit Network Connection
  50  */
  51
  52 #include "e1000_api.h"
  53
  54 static s32  e1000_init_phy_params_82571(struct e1000_hw *hw);
  55 static s32  e1000_init_nvm_params_82571(struct e1000_hw *hw);
  56 static s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
  57 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  58 static void e1000_release_nvm_82571(struct e1000_hw *hw);
  59 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  60                                   u16 words, u16 *data);
  61 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  62 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  63 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  64 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  65                                           bool active);
  66 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  67 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
  68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  71 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
  72 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  73 static s32  e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
  74 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  75 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  76 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  77 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  78 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  79 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  80 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  81 static s32  e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
  82 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
  83 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
  84 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
  85 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  86 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  87                                        u16 words, u16 *data);
  88 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  89 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  90
  91 /**
  92  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  93  *  @hw: pointer to the HW structure
  94  **/
  95 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  96 {
  97         struct e1000_phy_info *phy = &hw->phy;
  98         struct e1000_dev_spec_82571 *dev_spec = &hw->dev_spec._82571;
  99         s32 ret_val = E1000_SUCCESS;
 100
 101         DEBUGFUNC("e1000_init_phy_params_82571");
 102
 103         if (hw->phy.media_type != e1000_media_type_copper) {
 104                 phy->type = e1000_phy_none;
 105                 goto out;
 106         }
 107
 108         phy->addr                        = 1;
 109         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 110         phy->reset_delay_us              = 100;
 111
 112         phy->ops.check_reset_block       = e1000_check_reset_block_generic;
 113         phy->ops.reset                   = e1000_phy_hw_reset_generic;
 114         phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
 115         phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
 116         phy->ops.power_up                = e1000_power_up_phy_copper;
 117         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
 118
 119         switch (hw->mac.type) {
 120         case e1000_82571:
 121         case e1000_82572:
 122                 phy->type                   = e1000_phy_igp_2;
 123                 phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
 124                 phy->ops.get_info           = e1000_get_phy_info_igp;
 125                 phy->ops.check_polarity     = e1000_check_polarity_igp;
 126                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 127                 phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
 128                 phy->ops.read_reg           = e1000_read_phy_reg_igp;
 129                 phy->ops.write_reg          = e1000_write_phy_reg_igp;
 130                 phy->ops.acquire            = e1000_get_hw_semaphore_82571;
 131                 phy->ops.release            = e1000_put_hw_semaphore_82571;
 132
 133                 /* This uses above function pointers */
 134                 ret_val = e1000_get_phy_id_82571(hw);
 135
 136                 /* Verify PHY ID */
 137                 if (phy->id != IGP01E1000_I_PHY_ID) {
 138                         ret_val = -E1000_ERR_PHY;
 139                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 140                         goto out;
 141                 }
 142                 break;
 143         case e1000_82573:
 144                 phy->type                   = e1000_phy_m88;
 145                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 146                 phy->ops.get_info           = e1000_get_phy_info_m88;
 147                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 148                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 149                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 150                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 151                 phy->ops.read_reg           = e1000_read_phy_reg_m88;
 152                 phy->ops.write_reg          = e1000_write_phy_reg_m88;
 153                 phy->ops.acquire            = e1000_get_hw_semaphore_82571;
 154                 phy->ops.release            = e1000_put_hw_semaphore_82571;
 155
 156                 /* This uses above function pointers */
 157                 ret_val = e1000_get_phy_id_82571(hw);
 158
 159                 /* Verify PHY ID */
 160                 if (phy->id != M88E1111_I_PHY_ID) {
 161                         ret_val = -E1000_ERR_PHY;
 162                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 163                         goto out;
 164                 }
 165                 break;
 166         case e1000_82574:
 167         case e1000_82583:
 168                 E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 169
 170                 phy->type                   = e1000_phy_bm;
 171                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 172                 phy->ops.get_info           = e1000_get_phy_info_m88;
 173                 phy->ops.check_polarity     = e1000_check_polarity_m88;
 174                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 175                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 176                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 177                 phy->ops.read_reg           = e1000_read_phy_reg_bm2;
 178                 phy->ops.write_reg          = e1000_write_phy_reg_bm2;
 179                 phy->ops.acquire            = e1000_get_hw_semaphore_82574;
 180                 phy->ops.release            = e1000_put_hw_semaphore_82574;
 181
 182                 /* This uses above function pointers */
 183                 ret_val = e1000_get_phy_id_82571(hw);
 184                 /* Verify PHY ID */
 185                 if (phy->id != BME1000_E_PHY_ID_R2) {
 186                         ret_val = -E1000_ERR_PHY;
 187                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 188                         goto out;
 189                 }
 190                 break;
 191         default:
 192                 ret_val = -E1000_ERR_PHY;
 193                 goto out;
 194                 break;
 195         }
 196
 197 out:
 198         return ret_val;
 199 }
 200
 201 /**
 202  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 203  *  @hw: pointer to the HW structure
 204  **/
 205 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 206 {
 207         struct e1000_nvm_info *nvm = &hw->nvm;
 208         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 209         u16 size;
 210
 211         DEBUGFUNC("e1000_init_nvm_params_82571");
 212
 213         nvm->opcode_bits = 8;
 214         nvm->delay_usec = 1;
 215         switch (nvm->override) {
 216         case e1000_nvm_override_spi_large:
 217                 nvm->page_size = 32;
 218                 nvm->address_bits = 16;
 219                 break;
 220         case e1000_nvm_override_spi_small:
 221                 nvm->page_size = 8;
 222                 nvm->address_bits = 8;
 223                 break;
 224         default:
 225                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 226                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 227                 break;
 228         }
 229
 230         switch (hw->mac.type) {
 231         case e1000_82573:
 232         case e1000_82574:
 233         case e1000_82583:
 234                 if (((eecd >> 15) & 0x3) == 0x3) {
 235                         nvm->type = e1000_nvm_flash_hw;
 236                         nvm->word_size = 2048;
 237                         /*
 238                          * Autonomous Flash update bit must be cleared due
 239                          * to Flash update issue.
 240                          */
 241                         eecd &= ~E1000_EECD_AUPDEN;
 242                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 243                         break;
 244                 }
 245                 /* Fall Through */
 246         default:
 247                 nvm->type = e1000_nvm_eeprom_spi;
 248                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 249                                   E1000_EECD_SIZE_EX_SHIFT);
 250                 /*
 251                  * Added to a constant, "size" becomes the left-shift value
 252                  * for setting word_size.
 253                  */
 254                 size += NVM_WORD_SIZE_BASE_SHIFT;
 255
 256                 /* EEPROM access above 16k is unsupported */
 257                 if (size > 14)
 258                         size = 14;
 259                 nvm->word_size  = 1 << size;
 260                 break;
 261         }
 262
 263         /* Function Pointers */
 264         switch (hw->mac.type) {
 265         case e1000_82574:
 266         case e1000_82583:
 267                 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
 268                 nvm->ops.release = e1000_put_hw_semaphore_82574;
 269                 break;
 270         default:
 271                 nvm->ops.acquire = e1000_acquire_nvm_82571;
 272                 nvm->ops.release = e1000_release_nvm_82571;
 273                 break;
 274         }
 275         nvm->ops.read          = e1000_read_nvm_eerd;
 276         nvm->ops.update        = e1000_update_nvm_checksum_82571;
 277         nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
 278         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 279         nvm->ops.write         = e1000_write_nvm_82571;
 280
 281         return E1000_SUCCESS;
 282 }
 283
 284 /**
 285  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 286  *  @hw: pointer to the HW structure
 287  **/
 288 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 289 {
 290         struct e1000_mac_info *mac = &hw->mac;
 291         u32 swsm = 0;
 292         u32 swsm2 = 0;
 293         bool force_clear_smbi = FALSE;
 294
 295         DEBUGFUNC("e1000_init_mac_params_82571");
 296
 297         /* Set media type and media-dependent function pointers */
 298         switch (hw->device_id) {
 299         case E1000_DEV_ID_82571EB_FIBER:
 300         case E1000_DEV_ID_82572EI_FIBER:
 301         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 302                 hw->phy.media_type = e1000_media_type_fiber;
 303                 mac->ops.setup_physical_interface =
 304                         e1000_setup_fiber_serdes_link_82571;
 305                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 306                 mac->ops.get_link_up_info =
 307                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 308                 break;
 309         case E1000_DEV_ID_82571EB_SERDES:
 310         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 311         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 312         case E1000_DEV_ID_82572EI_SERDES:
 313                 hw->phy.media_type = e1000_media_type_internal_serdes;
 314                 mac->ops.setup_physical_interface =
 315                         e1000_setup_fiber_serdes_link_82571;
 316                 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
 317                 mac->ops.get_link_up_info =
 318                         e1000_get_speed_and_duplex_fiber_serdes_generic;
 319                 break;
 320         default:
 321                 hw->phy.media_type = e1000_media_type_copper;
 322                 mac->ops.setup_physical_interface =
 323                         e1000_setup_copper_link_82571;
 324                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 325                 mac->ops.get_link_up_info =
 326                         e1000_get_speed_and_duplex_copper_generic;
 327                 break;
 328         }
 329
 330         /* Set mta register count */
 331         mac->mta_reg_count = 128;
 332         /* Set rar entry count */
 333         mac->rar_entry_count = E1000_RAR_ENTRIES;
 334         /* Set if part includes ASF firmware */
 335         mac->asf_firmware_present = TRUE;
 336         /* Adaptive IFS supported */
 337         mac->adaptive_ifs = TRUE;
 338
 339         /* Function pointers */
 340
 341         /* bus type/speed/width */
 342         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 343         /* reset */
 344         mac->ops.reset_hw = e1000_reset_hw_82571;
 345         /* hw initialization */
 346         mac->ops.init_hw = e1000_init_hw_82571;
 347         /* link setup */
 348         mac->ops.setup_link = e1000_setup_link_82571;
 349         /* multicast address update */
 350         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 351         /* writing VFTA */
 352         mac->ops.write_vfta = e1000_write_vfta_generic;
 353         /* clearing VFTA */
 354         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 355         /* read mac address */
 356         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 357         /* ID LED init */
 358         mac->ops.id_led_init = e1000_id_led_init_generic;
 359         /* blink LED */
 360         mac->ops.blink_led = e1000_blink_led_generic;
 361         /* setup LED */
 362         mac->ops.setup_led = e1000_setup_led_generic;
 363         /* cleanup LED */
 364         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 365         /* turn off LED */
 366         mac->ops.led_off = e1000_led_off_generic;
 367         /* clear hardware counters */
 368         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 369
 370         /* MAC-specific function pointers */
 371         switch (hw->mac.type) {
 372         case e1000_82573:
 373                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 374                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 375                 mac->ops.led_on = e1000_led_on_generic;
 376
 377                 /* FWSM register */
 378                 mac->has_fwsm = TRUE;
 379                 /*
 380                  * ARC supported; valid only if manageability features are
 381                  * enabled.
 382                  */
 383                 mac->arc_subsystem_valid =
 384                         (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 385                         ? TRUE : FALSE;
 386                 break;
 387         case e1000_82574:
 388         case e1000_82583:
 389                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 390                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 391                 mac->ops.led_on = e1000_led_on_82574;
 392                 break;
 393         default:
 394                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 395                 mac->ops.led_on = e1000_led_on_generic;
 396
 397                 /* FWSM register */
 398                 mac->has_fwsm = TRUE;
 399                 break;
 400         }
 401
 402         /*
 403          * Ensure that the inter-port SWSM.SMBI lock bit is clear before
 404          * first NVM or PHY acess. This should be done for single-port
 405          * devices, and for one port only on dual-port devices so that
 406          * for those devices we can still use the SMBI lock to synchronize
 407          * inter-port accesses to the PHY & NVM.
 408          */
 409         switch (hw->mac.type) {
 410         case e1000_82571:
 411         case e1000_82572:
 412                 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
 413
 414                 if (!(swsm2 & E1000_SWSM2_LOCK)) {
 415                         /* Only do this for the first interface on this card */
 416                         E1000_WRITE_REG(hw, E1000_SWSM2,
 417                             swsm2 | E1000_SWSM2_LOCK);
 418                         force_clear_smbi = TRUE;
 419                 } else
 420                         force_clear_smbi = FALSE;
 421                 break;
 422         default:
 423                 force_clear_smbi = TRUE;
 424                 break;
 425         }
 426
 427         if (force_clear_smbi) {
 428                 /* Make sure SWSM.SMBI is clear */
 429                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 430                 if (swsm & E1000_SWSM_SMBI) {
 431                         /* This bit should not be set on a first interface, and
 432                          * indicates that the bootagent or EFI code has
 433                          * improperly left this bit enabled
 434                          */
 435                         DEBUGOUT("Please update your 82571 Bootagent\n");
 436                 }
 437                 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
 438         }
 439
 440         /*
 441          * Initialze device specific counter of SMBI acquisition
 442          * timeouts.
 443          */
 444          hw->dev_spec._82571.smb_counter = 0;
 445
 446         return E1000_SUCCESS;
 447 }
 448
 449 /**
 450  *  e1000_init_function_pointers_82571 - Init func ptrs.
 451  *  @hw: pointer to the HW structure
 452  *
 453  *  Called to initialize all function pointers and parameters.
 454  **/
 455 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 456 {
 457         DEBUGFUNC("e1000_init_function_pointers_82571");
 458
 459         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 460         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 461         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 462 }
 463
 464 /**
 465  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 466  *  @hw: pointer to the HW structure
 467  *
 468  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 469  *  revision in the hardware structure.
 470  **/
 471 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 472 {
 473         struct e1000_phy_info *phy = &hw->phy;
 474         s32 ret_val = E1000_SUCCESS;
 475         u16 phy_id = 0;
 476
 477         DEBUGFUNC("e1000_get_phy_id_82571");
 478
 479         switch (hw->mac.type) {
 480         case e1000_82571:
 481         case e1000_82572:
 482                 /*
 483                  * The 82571 firmware may still be configuring the PHY.
 484                  * In this case, we cannot access the PHY until the
 485                  * configuration is done.  So we explicitly set the
 486                  * PHY ID.
 487                  */
 488                 phy->id = IGP01E1000_I_PHY_ID;
 489                 break;
 490         case e1000_82573:
 491                 ret_val = e1000_get_phy_id(hw);
 492                 break;
 493         case e1000_82574:
 494         case e1000_82583:
 495                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 496                 if (ret_val)
 497                         goto out;
 498
 499                 phy->id = (u32)(phy_id << 16);
 500                 usec_delay(20);
 501                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 502                 if (ret_val)
 503                         goto out;
 504
 505                 phy->id |= (u32)(phy_id);
 506                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 507                 break;
 508         default:
 509                 ret_val = -E1000_ERR_PHY;
 510                 break;
 511         }
 512 out:
 513         return ret_val;
 514 }
 515
 516 /**
 517  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 518  *  @hw: pointer to the HW structure
 519  *
 520  *  Acquire the HW semaphore to access the PHY or NVM
 521  **/
 522 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 523 {
 524         u32 swsm;
 525         s32 ret_val = E1000_SUCCESS;
 526         s32 sw_timeout = hw->nvm.word_size + 1;
 527         s32 fw_timeout = hw->nvm.word_size + 1;
 528         s32 i = 0;
 529
 530         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 531
 532         /*
 533          * If we have timedout 3 times on trying to acquire
 534          * the inter-port SMBI semaphore, there is old code
 535          * operating on the other port, and it is not
 536          * releasing SMBI. Modify the number of times that
 537          * we try for the semaphore to interwork with this
 538          * older code.
 539          */
 540         if (hw->dev_spec._82571.smb_counter > 2)
 541                 sw_timeout = 1;
 542
 543         /* Get the SW semaphore */
 544         while (i < sw_timeout) {
 545                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 546                 if (!(swsm & E1000_SWSM_SMBI))
 547                         break;
 548
 549                 usec_delay(50);
 550                 i++;
 551         }
 552
 553         if (i == sw_timeout) {
 554                 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
 555                 hw->dev_spec._82571.smb_counter++;
 556         }
 557         /* Get the FW semaphore. */
 558         for (i = 0; i < fw_timeout; i++) {
 559                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 560                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 561
 562                 /* Semaphore acquired if bit latched */
 563                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 564                         break;
 565
 566                 usec_delay(50);
 567         }
 568
 569         if (i == fw_timeout) {
 570                 /* Release semaphores */
 571                 e1000_put_hw_semaphore_82571(hw);
 572                 DEBUGOUT("Driver can't access the NVM\n");
 573                 ret_val = -E1000_ERR_NVM;
 574                 goto out;
 575         }
 576
 577 out:
 578         return ret_val;
 579 }
 580
 581 /**
 582  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 583  *  @hw: pointer to the HW structure
 584  *
 585  *  Release hardware semaphore used to access the PHY or NVM
 586  **/
 587 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 588 {
 589         u32 swsm;
 590
 591         DEBUGFUNC("e1000_put_hw_semaphore_generic");
 592
 593         swsm = E1000_READ_REG(hw, E1000_SWSM);
 594
 595         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
 596
 597         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 598 }
 599
 600 /**
 601  *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
 602  *  @hw: pointer to the HW structure
 603  *
 604  *  Acquire the HW semaphore during reset.
 605  *
 606  **/
 607 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
 608 {
 609         u32 extcnf_ctrl;
 610         s32 ret_val = E1000_SUCCESS;
 611         s32 i = 0;
 612
 613         DEBUGFUNC("e1000_get_hw_semaphore_82573");
 614
 615         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 616         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 617         do {
 618                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 619                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 620
 621                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 622                         break;
 623
 624                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 625
 626                 msec_delay(2);
 627                 i++;
 628         } while (i < MDIO_OWNERSHIP_TIMEOUT);
 629
 630         if (i == MDIO_OWNERSHIP_TIMEOUT) {
 631                 /* Release semaphores */
 632                 e1000_put_hw_semaphore_82573(hw);
 633                 DEBUGOUT("Driver can't access the PHY\n");
 634                 ret_val = -E1000_ERR_PHY;
 635                 goto out;
 636         }
 637
 638 out:
 639         return ret_val;
 640 }
 641
 642 /**
 643  *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
 644  *  @hw: pointer to the HW structure
 645  *
 646  *  Release hardware semaphore used during reset.
 647  *
 648  **/
 649 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
 650 {
 651         u32 extcnf_ctrl;
 652
 653         DEBUGFUNC("e1000_put_hw_semaphore_82573");
 654
 655         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 656         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 657         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 658 }
 659
 660 /**
 661  *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
 662  *  @hw: pointer to the HW structure
 663  *
 664  *  Acquire the HW semaphore to access the PHY or NVM.
 665  *
 666  **/
 667 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
 668 {
 669         s32 ret_val;
 670
 671         DEBUGFUNC("e1000_get_hw_semaphore_82574");
 672
 673         E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
 674         ret_val = e1000_get_hw_semaphore_82573(hw);
 675         if (ret_val)
 676                 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 677         return ret_val;
 678 }
 679
 680 /**
 681  *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
 682  *  @hw: pointer to the HW structure
 683  *
 684  *  Release hardware semaphore used to access the PHY or NVM
 685  *
 686  **/
 687 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
 688 {
 689         DEBUGFUNC("e1000_put_hw_semaphore_82574");
 690
 691         e1000_put_hw_semaphore_82573(hw);
 692         E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
 693 }
 694
 695 /**
 696  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 697  *  @hw: pointer to the HW structure
 698  *
 699  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 700  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 701  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 702  *  hardware semaphore.
 703  **/
 704 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 705 {
 706         s32 ret_val;
 707
 708         DEBUGFUNC("e1000_acquire_nvm_82571");
 709
 710         ret_val = e1000_get_hw_semaphore_82571(hw);
 711         if (ret_val)
 712                 goto out;
 713
 714         switch (hw->mac.type) {
 715         case e1000_82573:
 716                 break;
 717         default:
 718                 ret_val = e1000_acquire_nvm_generic(hw);
 719                 break;
 720         }
 721
 722         if (ret_val)
 723                 e1000_put_hw_semaphore_82571(hw);
 724
 725 out:
 726         return ret_val;
 727 }
 728
 729 /**
 730  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 731  *  @hw: pointer to the HW structure
 732  *
 733  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 734  **/
 735 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 736 {
 737         DEBUGFUNC("e1000_release_nvm_82571");
 738
 739         e1000_release_nvm_generic(hw);
 740         e1000_put_hw_semaphore_82571(hw);
 741 }
 742
 743 /**
 744  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 745  *  @hw: pointer to the HW structure
 746  *  @offset: offset within the EEPROM to be written to
 747  *  @words: number of words to write
 748  *  @data: 16 bit word(s) to be written to the EEPROM
 749  *
 750  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 751  *
 752  *  If e1000_update_nvm_checksum is not called after this function, the
 753  *  EEPROM will most likely contain an invalid checksum.
 754  **/
 755 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 756                                  u16 *data)
 757 {
 758         s32 ret_val = E1000_SUCCESS;
 759
 760         DEBUGFUNC("e1000_write_nvm_82571");
 761
 762         switch (hw->mac.type) {
 763         case e1000_82573:
 764         case e1000_82574:
 765         case e1000_82583:
 766                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 767                 break;
 768         case e1000_82571:
 769         case e1000_82572:
 770                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 771                 break;
 772         default:
 773                 ret_val = -E1000_ERR_NVM;
 774                 break;
 775         }
 776
 777         return ret_val;
 778 }
 779
 780 /**
 781  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 782  *  @hw: pointer to the HW structure
 783  *
 784  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 785  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 786  *  value to the EEPROM.
 787  **/
 788 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 789 {
 790         u32 eecd;
 791         s32 ret_val;
 792         u16 i;
 793
 794         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 795
 796         ret_val = e1000_update_nvm_checksum_generic(hw);
 797         if (ret_val)
 798                 goto out;
 799
 800         /*
 801          * If our nvm is an EEPROM, then we're done
 802          * otherwise, commit the checksum to the flash NVM.
 803          */
 804         if (hw->nvm.type != e1000_nvm_flash_hw)
 805                 goto out;
 806
 807         /* Check for pending operations. */
 808         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 809                 msec_delay(1);
 810                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 811                         break;
 812         }
 813
 814         if (i == E1000_FLASH_UPDATES) {
 815                 ret_val = -E1000_ERR_NVM;
 816                 goto out;
 817         }
 818
 819         /* Reset the firmware if using STM opcode. */
 820         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 821                 /*
 822                  * The enabling of and the actual reset must be done
 823                  * in two write cycles.
 824                  */
 825                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 826                 E1000_WRITE_FLUSH(hw);
 827                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 828         }
 829
 830         /* Commit the write to flash */
 831         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 832         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 833
 834         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 835                 msec_delay(1);
 836                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 837                         break;
 838         }
 839
 840         if (i == E1000_FLASH_UPDATES) {
 841                 ret_val = -E1000_ERR_NVM;
 842                 goto out;
 843         }
 844
 845 out:
 846         return ret_val;
 847 }
 848
 849 /**
 850  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 851  *  @hw: pointer to the HW structure
 852  *
 853  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 854  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 855  **/
 856 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 857 {
 858         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 859
 860         if (hw->nvm.type == e1000_nvm_flash_hw)
 861                 e1000_fix_nvm_checksum_82571(hw);
 862
 863         return e1000_validate_nvm_checksum_generic(hw);
 864 }
 865
 866 /**
 867  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 868  *  @hw: pointer to the HW structure
 869  *  @offset: offset within the EEPROM to be written to
 870  *  @words: number of words to write
 871  *  @data: 16 bit word(s) to be written to the EEPROM
 872  *
 873  *  After checking for invalid values, poll the EEPROM to ensure the previous
 874  *  command has completed before trying to write the next word.  After write
 875  *  poll for completion.
 876  *
 877  *  If e1000_update_nvm_checksum is not called after this function, the
 878  *  EEPROM will most likely contain an invalid checksum.
 879  **/
 880 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 881                                       u16 words, u16 *data)
 882 {
 883         struct e1000_nvm_info *nvm = &hw->nvm;
 884         u32 i, eewr = 0;
 885         s32 ret_val = 0;
 886
 887         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 888
 889         /*
 890          * A check for invalid values:  offset too large, too many words,
 891          * and not enough words.
 892          */
 893         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 894             (words == 0)) {
 895                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 896                 ret_val = -E1000_ERR_NVM;
 897                 goto out;
 898         }
 899
 900         for (i = 0; i < words; i++) {
 901                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 902                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 903                        E1000_NVM_RW_REG_START;
 904
 905                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 906                 if (ret_val)
 907                         break;
 908
 909                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 910
 911                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 912                 if (ret_val)
 913                         break;
 914         }
 915
 916 out:
 917         return ret_val;
 918 }
 919
 920 /**
 921  *  e1000_get_cfg_done_82571 - Poll for configuration done
 922  *  @hw: pointer to the HW structure
 923  *
 924  *  Reads the management control register for the config done bit to be set.
 925  **/
 926 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 927 {
 928         s32 timeout = PHY_CFG_TIMEOUT;
 929         s32 ret_val = E1000_SUCCESS;
 930
 931         DEBUGFUNC("e1000_get_cfg_done_82571");
 932
 933         while (timeout) {
 934                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
 935                     E1000_NVM_CFG_DONE_PORT_0)
 936                         break;
 937                 msec_delay(1);
 938                 timeout--;
 939         }
 940         if (!timeout) {
 941                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 942                 ret_val = -E1000_ERR_RESET;
 943                 goto out;
 944         }
 945
 946 out:
 947         return ret_val;
 948 }
 949
 950 /**
 951  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 952  *  @hw: pointer to the HW structure
 953  *  @active: TRUE to enable LPLU, FALSE to disable
 954  *
 955  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 956  *  this function also disables smart speed and vice versa.  LPLU will not be
 957  *  activated unless the device autonegotiation advertisement meets standards
 958  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 959  *  pointer entry point only called by PHY setup routines.
 960  **/
 961 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 962 {
 963         struct e1000_phy_info *phy = &hw->phy;
 964         s32 ret_val = E1000_SUCCESS;
 965         u16 data;
 966
 967         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 968
 969         if (!(phy->ops.read_reg))
 970                 goto out;
 971
 972         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 973         if (ret_val)
 974                 goto out;
 975
 976         if (active) {
 977                 data |= IGP02E1000_PM_D0_LPLU;
 978                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 979                                              data);
 980                 if (ret_val)
 981                         goto out;
 982
 983                 /* When LPLU is enabled, we should disable SmartSpeed */
 984                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 985                                             &data);
 986                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 987                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 988                                              data);
 989                 if (ret_val)
 990                         goto out;
 991         } else {
 992                 data &= ~IGP02E1000_PM_D0_LPLU;
 993                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 994                                              data);
 995                 /*
 996                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 997                  * during Dx states where the power conservation is most
 998                  * important.  During driver activity we should enable
 999                  * SmartSpeed, so performance is maintained.
1000                  */
1001                 if (phy->smart_speed == e1000_smart_speed_on) {
1002                         ret_val = phy->ops.read_reg(hw,
1003                                                     IGP01E1000_PHY_PORT_CONFIG,
1004                                                     &data);
1005                         if (ret_val)
1006                                 goto out;
1007
1008                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1009                         ret_val = phy->ops.write_reg(hw,
1010                                                      IGP01E1000_PHY_PORT_CONFIG,
1011                                                      data);
1012                         if (ret_val)
1013                                 goto out;
1014                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1015                         ret_val = phy->ops.read_reg(hw,
1016                                                     IGP01E1000_PHY_PORT_CONFIG,
1017                                                     &data);
1018                         if (ret_val)
1019                                 goto out;
1020
1021                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1022                         ret_val = phy->ops.write_reg(hw,
1023                                                      IGP01E1000_PHY_PORT_CONFIG,
1024                                                      data);
1025                         if (ret_val)
1026                                 goto out;
1027                 }
1028         }
1029
1030 out:
1031         return ret_val;
1032 }
1033
1034 /**
1035  *  e1000_reset_hw_82571 - Reset hardware
1036  *  @hw: pointer to the HW structure
1037  *
1038  *  This resets the hardware into a known state.
1039  **/
1040 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1041 {
1042         u32 ctrl, ctrl_ext, icr;
1043         s32 ret_val;
1044
1045         DEBUGFUNC("e1000_reset_hw_82571");
1046
1047         /*
1048          * Prevent the PCI-E bus from sticking if there is no TLP connection
1049          * on the last TLP read/write transaction when MAC is reset.
1050          */
1051         ret_val = e1000_disable_pcie_master_generic(hw);
1052         if (ret_val)
1053                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1054
1055         DEBUGOUT("Masking off all interrupts\n");
1056         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1057
1058         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1059         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1060         E1000_WRITE_FLUSH(hw);
1061
1062         msec_delay(10);
1063
1064         /*
1065          * Must acquire the MDIO ownership before MAC reset.
1066          * Ownership defaults to firmware after a reset.
1067          */
1068         switch (hw->mac.type) {
1069         case e1000_82573:
1070                 ret_val = e1000_get_hw_semaphore_82573(hw);
1071                 break;
1072         case e1000_82574:
1073         case e1000_82583:
1074                 ret_val = e1000_get_hw_semaphore_82574(hw);
1075                 break;
1076         default:
1077                 break;
1078         }
1079         if (ret_val)
1080                 DEBUGOUT("Cannot acquire MDIO ownership\n");
1081
1082         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1083
1084         DEBUGOUT("Issuing a global reset to MAC\n");
1085         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1086
1087         /* Must release MDIO ownership and mutex after MAC reset. */
1088         switch (hw->mac.type) {
1089         case e1000_82574:
1090         case e1000_82583:
1091                 e1000_put_hw_semaphore_82574(hw);
1092                 break;
1093         default:
1094                 break;
1095         }
1096
1097         if (hw->nvm.type == e1000_nvm_flash_hw) {
1098                 usec_delay(10);
1099                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1100                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1101                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1102                 E1000_WRITE_FLUSH(hw);
1103         }
1104
1105         ret_val = e1000_get_auto_rd_done_generic(hw);
1106         if (ret_val)
1107                 /* We don't want to continue accessing MAC registers. */
1108                 goto out;
1109
1110         /*
1111          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1112          * Need to wait for Phy configuration completion before accessing
1113          * NVM and Phy.
1114          */
1115
1116         switch (hw->mac.type) {
1117         case e1000_82573:
1118         case e1000_82574:
1119         case e1000_82583:
1120                 msec_delay(25);
1121                 break;
1122         default:
1123                 break;
1124         }
1125
1126         /* Clear any pending interrupt events. */
1127         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1128         icr = E1000_READ_REG(hw, E1000_ICR);
1129
1130         if (hw->mac.type == e1000_82571) {
1131                 /* Install any alternate MAC address into RAR0 */
1132                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1133                 if (ret_val)
1134                         goto out;
1135
1136                 e1000_set_laa_state_82571(hw, TRUE);
1137         }
1138
1139         /* Reinitialize the 82571 serdes link state machine */
1140         if (hw->phy.media_type == e1000_media_type_internal_serdes)
1141                 hw->mac.serdes_link_state = e1000_serdes_link_down;
1142
1143 out:
1144         return ret_val;
1145 }
1146
1147 /**
1148  *  e1000_init_hw_82571 - Initialize hardware
1149  *  @hw: pointer to the HW structure
1150  *
1151  *  This inits the hardware readying it for operation.
1152  **/
1153 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1154 {
1155         struct e1000_mac_info *mac = &hw->mac;
1156         u32 reg_data;
1157         s32 ret_val;
1158         u16 i, rar_count = mac->rar_entry_count;
1159
1160         DEBUGFUNC("e1000_init_hw_82571");
1161
1162         e1000_initialize_hw_bits_82571(hw);
1163
1164         /* Initialize identification LED */
1165         ret_val = mac->ops.id_led_init(hw);
1166         if (ret_val)
1167                 DEBUGOUT("Error initializing identification LED\n");
1168                 /* This is not fatal and we should not stop init due to this */
1169
1170         /* Disabling VLAN filtering */
1171         DEBUGOUT("Initializing the IEEE VLAN\n");
1172         mac->ops.clear_vfta(hw);
1173
1174         /* Setup the receive address. */
1175         /*
1176          * If, however, a locally administered address was assigned to the
1177          * 82571, we must reserve a RAR for it to work around an issue where
1178          * resetting one port will reload the MAC on the other port.
1179          */
1180         if (e1000_get_laa_state_82571(hw))
1181                 rar_count--;
1182         e1000_init_rx_addrs_generic(hw, rar_count);
1183
1184         /* Zero out the Multicast HASH table */
1185         DEBUGOUT("Zeroing the MTA\n");
1186         for (i = 0; i < mac->mta_reg_count; i++)
1187                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1188
1189         /* Setup link and flow control */
1190         ret_val = mac->ops.setup_link(hw);
1191
1192         /* Set the transmit descriptor write-back policy */
1193         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1194         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1195                    E1000_TXDCTL_FULL_TX_DESC_WB |
1196                    E1000_TXDCTL_COUNT_DESC;
1197         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1198
1199         /* ...for both queues. */
1200         switch (mac->type) {
1201         case e1000_82573:
1202                 e1000_enable_tx_pkt_filtering_generic(hw);
1203                 /* fall through */
1204         case e1000_82574:
1205         case e1000_82583:
1206                 reg_data = E1000_READ_REG(hw, E1000_GCR);
1207                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1208                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1209                 break;
1210         default:
1211                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1212                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1213                            E1000_TXDCTL_FULL_TX_DESC_WB |
1214                            E1000_TXDCTL_COUNT_DESC;
1215                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1216                 break;
1217         }
1218
1219         /*
1220          * Clear all of the statistics registers (clear on read).  It is
1221          * important that we do this after we have tried to establish link
1222          * because the symbol error count will increment wildly if there
1223          * is no link.
1224          */
1225         e1000_clear_hw_cntrs_82571(hw);
1226
1227         return ret_val;
1228 }
1229
1230 /**
1231  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1232  *  @hw: pointer to the HW structure
1233  *
1234  *  Initializes required hardware-dependent bits needed for normal operation.
1235  **/
1236 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1237 {
1238         u32 reg;
1239
1240         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1241
1242         /* Transmit Descriptor Control 0 */
1243         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1244         reg |= (1 << 22);
1245         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1246
1247         /* Transmit Descriptor Control 1 */
1248         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1249         reg |= (1 << 22);
1250         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1251
1252         /* Transmit Arbitration Control 0 */
1253         reg = E1000_READ_REG(hw, E1000_TARC(0));
1254         reg &= ~(0xF << 27); /* 30:27 */
1255         switch (hw->mac.type) {
1256         case e1000_82571:
1257         case e1000_82572:
1258                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1259                 break;
1260         default:
1261                 break;
1262         }
1263         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1264
1265         /* Transmit Arbitration Control 1 */
1266         reg = E1000_READ_REG(hw, E1000_TARC(1));
1267         switch (hw->mac.type) {
1268         case e1000_82571:
1269         case e1000_82572:
1270                 reg &= ~((1 << 29) | (1 << 30));
1271                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1272                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1273                         reg &= ~(1 << 28);
1274                 else
1275                         reg |= (1 << 28);
1276                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1277                 break;
1278         default:
1279                 break;
1280         }
1281
1282         /* Device Control */
1283         switch (hw->mac.type) {
1284         case e1000_82573:
1285         case e1000_82574:
1286         case e1000_82583:
1287                 reg = E1000_READ_REG(hw, E1000_CTRL);
1288                 reg &= ~(1 << 29);
1289                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1290                 break;
1291         default:
1292                 break;
1293         }
1294
1295         /* Extended Device Control */
1296         switch (hw->mac.type) {
1297         case e1000_82573:
1298         case e1000_82574:
1299         case e1000_82583:
1300                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1301                 reg &= ~(1 << 23);
1302                 reg |= (1 << 22);
1303                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1304                 break;
1305         default:
1306                 break;
1307         }
1308
1309         if (hw->mac.type == e1000_82571) {
1310                 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1311                 reg |= E1000_PBA_ECC_CORR_EN;
1312                 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1313         }
1314
1315         /*
1316          * Workaround for hardware errata.
1317          * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1318          */
1319         if ((hw->mac.type == e1000_82571) ||
1320            (hw->mac.type == e1000_82572)) {
1321                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1322                 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1323                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1324         }
1325
1326         /* PCI-Ex Control Registers */
1327         switch (hw->mac.type) {
1328         case e1000_82574:
1329         case e1000_82583:
1330                 reg = E1000_READ_REG(hw, E1000_GCR);
1331                 reg |= (1 << 22);
1332                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1333
1334                 /*
1335                  * Workaround for hardware errata.
1336                  * apply workaround for hardware errata documented in errata
1337                  * docs Fixes issue where some error prone or unreliable PCIe
1338                  * completions are occurring, particularly with ASPM enabled.
1339                  * Without fix, issue can cause tx timeouts.
1340                  */
1341                 reg = E1000_READ_REG(hw, E1000_GCR2);
1342                 reg |= 1;
1343                 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1344                 break;
1345         default:
1346                 break;
1347         }
1348
1349         return;
1350 }
1351
1352 /**
1353  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1354  *  @hw: pointer to the HW structure
1355  *
1356  *  Clears the register array which contains the VLAN filter table by
1357  *  setting all the values to 0.
1358  **/
1359 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1360 {
1361         u32 offset;
1362         u32 vfta_value = 0;
1363         u32 vfta_offset = 0;
1364         u32 vfta_bit_in_reg = 0;
1365
1366         DEBUGFUNC("e1000_clear_vfta_82571");
1367
1368         switch (hw->mac.type) {
1369         case e1000_82573:
1370         case e1000_82574:
1371         case e1000_82583:
1372                 if (hw->mng_cookie.vlan_id != 0) {
1373                         /*
1374                          * The VFTA is a 4096b bit-field, each identifying
1375                          * a single VLAN ID.  The following operations
1376                          * determine which 32b entry (i.e. offset) into the
1377                          * array we want to set the VLAN ID (i.e. bit) of
1378                          * the manageability unit.
1379                          */
1380                         vfta_offset = (hw->mng_cookie.vlan_id >>
1381                                 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1382                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1383                                 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1384                 }
1385                 break;
1386         default:
1387                 break;
1388         }
1389         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1390                 /*
1391                  * If the offset we want to clear is the same offset of the
1392                  * manageability VLAN ID, then clear all bits except that of
1393                  * the manageability unit.
1394                  */
1395                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1396                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1397                 E1000_WRITE_FLUSH(hw);
1398         }
1399 }
1400
1401 /**
1402  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1403  *  @hw: pointer to the HW structure
1404  *
1405  *  Reads the NVM Initialization Control Word 2 and returns TRUE
1406  *  (>0) if any manageability is enabled, else FALSE (0).
1407  **/
1408 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1409 {
1410         u16 data;
1411
1412         DEBUGFUNC("e1000_check_mng_mode_82574");
1413
1414         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1415         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1416 }
1417
1418 /**
1419  *  e1000_led_on_82574 - Turn LED on
1420  *  @hw: pointer to the HW structure
1421  *
1422  *  Turn LED on.
1423  **/
1424 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1425 {
1426         u32 ctrl;
1427         u32 i;
1428
1429         DEBUGFUNC("e1000_led_on_82574");
1430
1431         ctrl = hw->mac.ledctl_mode2;
1432         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1433                 /*
1434                  * If no link, then turn LED on by setting the invert bit
1435                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1436                  */
1437                 for (i = 0; i < 4; i++)
1438                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1439                             E1000_LEDCTL_MODE_LED_ON)
1440                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1441         }
1442         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1443
1444         return E1000_SUCCESS;
1445 }
1446
1447 /**
1448  *  e1000_check_phy_82574 - check 82574 phy hung state
1449  *  @hw: pointer to the HW structure
1450  *
1451  *  Returns whether phy is hung or not
1452  **/
1453 bool e1000_check_phy_82574(struct e1000_hw *hw)
1454 {
1455         u16 status_1kbt = 0;
1456         u16 receive_errors = 0;
1457         bool phy_hung = FALSE;
1458         s32 ret_val = E1000_SUCCESS;
1459
1460         DEBUGFUNC("e1000_check_phy_82574");
1461
1462         /*
1463          * Read PHY Receive Error counter first, if its is max - all F's then
1464          * read the Base1000T status register If both are max then PHY is hung.
1465          */
1466         ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1467                                        &receive_errors);
1468         if (ret_val)
1469                 goto out;
1470         if (receive_errors == E1000_RECEIVE_ERROR_MAX)  {
1471                 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1472                                                &status_1kbt);
1473                 if (ret_val)
1474                         goto out;
1475                 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1476                     E1000_IDLE_ERROR_COUNT_MASK)
1477                         phy_hung = TRUE;
1478         }
1479 out:
1480         return phy_hung;
1481 }
1482
1483
1484 /**
1485  *  e1000_setup_link_82571 - Setup flow control and link settings
1486  *  @hw: pointer to the HW structure
1487  *
1488  *  Determines which flow control settings to use, then configures flow
1489  *  control.  Calls the appropriate media-specific link configuration
1490  *  function.  Assuming the adapter has a valid link partner, a valid link
1491  *  should be established.  Assumes the hardware has previously been reset
1492  *  and the transmitter and receiver are not enabled.
1493  **/
1494 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1495 {
1496         DEBUGFUNC("e1000_setup_link_82571");
1497
1498         /*
1499          * 82573 does not have a word in the NVM to determine
1500          * the default flow control setting, so we explicitly
1501          * set it to full.
1502          */
1503         switch (hw->mac.type) {
1504         case e1000_82573:
1505         case e1000_82574:
1506         case e1000_82583:
1507                 if (hw->fc.requested_mode == e1000_fc_default)
1508                         hw->fc.requested_mode = e1000_fc_full;
1509                 break;
1510         default:
1511                 break;
1512         }
1513         return e1000_setup_link_generic(hw);
1514 }
1515
1516 /**
1517  *  e1000_setup_copper_link_82571 - Configure copper link settings
1518  *  @hw: pointer to the HW structure
1519  *
1520  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1521  *  for link, once link is established calls to configure collision distance
1522  *  and flow control are called.
1523  **/
1524 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1525 {
1526         u32 ctrl;
1527         s32 ret_val;
1528
1529         DEBUGFUNC("e1000_setup_copper_link_82571");
1530
1531         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1532         ctrl |= E1000_CTRL_SLU;
1533         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1534         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1535
1536         switch (hw->phy.type) {
1537         case e1000_phy_m88:
1538         case e1000_phy_bm:
1539                 ret_val = e1000_copper_link_setup_m88(hw);
1540                 break;
1541         case e1000_phy_igp_2:
1542                 ret_val = e1000_copper_link_setup_igp(hw);
1543                 break;
1544         default:
1545                 ret_val = -E1000_ERR_PHY;
1546                 break;
1547         }
1548
1549         if (ret_val)
1550                 goto out;
1551
1552         ret_val = e1000_setup_copper_link_generic(hw);
1553
1554 out:
1555         return ret_val;
1556 }
1557
1558 /**
1559  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1560  *  @hw: pointer to the HW structure
1561  *
1562  *  Configures collision distance and flow control for fiber and serdes links.
1563  *  Upon successful setup, poll for link.
1564  **/
1565 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1566 {
1567         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1568
1569         switch (hw->mac.type) {
1570         case e1000_82571:
1571         case e1000_82572:
1572                 /*
1573                  * If SerDes loopback mode is entered, there is no form
1574                  * of reset to take the adapter out of that mode.  So we
1575                  * have to explicitly take the adapter out of loopback
1576                  * mode.  This prevents drivers from twiddling their thumbs
1577                  * if another tool failed to take it out of loopback mode.
1578                  */
1579                 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1580                 break;
1581         default:
1582                 break;
1583         }
1584
1585         return e1000_setup_fiber_serdes_link_generic(hw);
1586 }
1587
1588 /**
1589  *  e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1590  *  @hw: pointer to the HW structure
1591  *
1592  *  Reports the link state as up or down.
1593  *
1594  *  If autonegotiation is supported by the link partner, the link state is
1595  *  determined by the result of autonegotiation. This is the most likely case.
1596  *  If autonegotiation is not supported by the link partner, and the link
1597  *  has a valid signal, force the link up.
1598  *
1599  *  The link state is represented internally here by 4 states:
1600  *
1601  *  1) down
1602  *  2) autoneg_progress
1603  *  3) autoneg_complete (the link sucessfully autonegotiated)
1604  *  4) forced_up (the link has been forced up, it did not autonegotiate)
1605  *
1606  **/
1607 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1608 {
1609         struct e1000_mac_info *mac = &hw->mac;
1610         u32 rxcw;
1611         u32 ctrl;
1612         u32 status;
1613         u32 txcw;
1614         u32 i;
1615         s32 ret_val = E1000_SUCCESS;
1616
1617         DEBUGFUNC("e1000_check_for_serdes_link_82571");
1618
1619         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1620         status = E1000_READ_REG(hw, E1000_STATUS);
1621         rxcw = E1000_READ_REG(hw, E1000_RXCW);
1622
1623         if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1624
1625                 /* Receiver is synchronized with no invalid bits.  */
1626                 switch (mac->serdes_link_state) {
1627                 case e1000_serdes_link_autoneg_complete:
1628                         if (!(status & E1000_STATUS_LU)) {
1629                                 /*
1630                                  * We have lost link, retry autoneg before
1631                                  * reporting link failure
1632                                  */
1633                                 mac->serdes_link_state =
1634                                     e1000_serdes_link_autoneg_progress;
1635                                 mac->serdes_has_link = FALSE;
1636                                 DEBUGOUT("AN_UP     -> AN_PROG\n");
1637                         } else {
1638                                 mac->serdes_has_link = TRUE;
1639                         }
1640                         break;
1641
1642                 case e1000_serdes_link_forced_up:
1643                         /*
1644                          * If we are receiving /C/ ordered sets, re-enable
1645                          * auto-negotiation in the TXCW register and disable
1646                          * forced link in the Device Control register in an
1647                          * attempt to auto-negotiate with our link partner.
1648                          * If the partner code word is null, stop forcing
1649                          * and restart auto negotiation.
1650                          */
1651                         if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW))  {
1652                                 /* Enable autoneg, and unforce link up */
1653                                 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1654                                 E1000_WRITE_REG(hw, E1000_CTRL,
1655                                     (ctrl & ~E1000_CTRL_SLU));
1656                                 mac->serdes_link_state =
1657                                     e1000_serdes_link_autoneg_progress;
1658                                 mac->serdes_has_link = FALSE;
1659                                 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1660                         } else {
1661                                 mac->serdes_has_link = TRUE;
1662                         }
1663                         break;
1664
1665                 case e1000_serdes_link_autoneg_progress:
1666                         if (rxcw & E1000_RXCW_C) {
1667                                 /*
1668                                  * We received /C/ ordered sets, meaning the
1669                                  * link partner has autonegotiated, and we can
1670                                  * trust the Link Up (LU) status bit.
1671                                  */
1672                                 if (status & E1000_STATUS_LU) {
1673                                         mac->serdes_link_state =
1674                                             e1000_serdes_link_autoneg_complete;
1675                                         DEBUGOUT("AN_PROG   -> AN_UP\n");
1676                                         mac->serdes_has_link = TRUE;
1677                                 } else {
1678                                         /* Autoneg completed, but failed. */
1679                                         mac->serdes_link_state =
1680                                             e1000_serdes_link_down;
1681                                         DEBUGOUT("AN_PROG   -> DOWN\n");
1682                                 }
1683                         } else {
1684                                 /*
1685                                  * The link partner did not autoneg.
1686                                  * Force link up and full duplex, and change
1687                                  * state to forced.
1688                                  */
1689                                 E1000_WRITE_REG(hw, E1000_TXCW,
1690                                 (mac->txcw & ~E1000_TXCW_ANE));
1691                                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1692                                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1693
1694                                 /* Configure Flow Control after link up. */
1695                                 ret_val =
1696                                     e1000_config_fc_after_link_up_generic(hw);
1697                                 if (ret_val) {
1698                                         DEBUGOUT("Error config flow control\n");
1699                                         break;
1700                                 }
1701                                 mac->serdes_link_state =
1702                                 e1000_serdes_link_forced_up;
1703                                 mac->serdes_has_link = TRUE;
1704                                 DEBUGOUT("AN_PROG   -> FORCED_UP\n");
1705                         }
1706                         break;
1707
1708                 case e1000_serdes_link_down:
1709                 default:
1710                         /*
1711                          * The link was down but the receiver has now gained
1712                          * valid sync, so lets see if we can bring the link
1713                          * up.
1714                          */
1715                         E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1716                         E1000_WRITE_REG(hw, E1000_CTRL,
1717                             (ctrl & ~E1000_CTRL_SLU));
1718                         mac->serdes_link_state =
1719                             e1000_serdes_link_autoneg_progress;
1720                         mac->serdes_has_link = FALSE;
1721                         DEBUGOUT("DOWN      -> AN_PROG\n");
1722                         break;
1723                 }
1724         } else {
1725                 if (!(rxcw & E1000_RXCW_SYNCH)) {
1726                         mac->serdes_has_link = FALSE;
1727                         mac->serdes_link_state = e1000_serdes_link_down;
1728                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1729                 } else {
1730                         /*
1731                          * Check several times, if Sync and Config
1732                          * both are consistently 1 then simply ignore
1733                          * the Invalid bit and restart Autoneg
1734                          */
1735                         for (i = 0; i < AN_RETRY_COUNT; i++) {
1736                                 usec_delay(10);
1737                                 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1738                                 if ((rxcw & E1000_RXCW_IV) &&
1739                                     !((rxcw & E1000_RXCW_SYNCH) &&
1740                                       (rxcw & E1000_RXCW_C))) {
1741                                         mac->serdes_has_link = FALSE;
1742                                         mac->serdes_link_state =
1743                                             e1000_serdes_link_down;
1744                                         DEBUGOUT("ANYSTATE  -> DOWN\n");
1745                                         break;
1746                                 }
1747                         }
1748
1749                         if (i == AN_RETRY_COUNT) {
1750                                 txcw = E1000_READ_REG(hw, E1000_TXCW);
1751                                 txcw |= E1000_TXCW_ANE;
1752                                 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1753                                 mac->serdes_link_state =
1754                                     e1000_serdes_link_autoneg_progress;
1755                                 mac->serdes_has_link = FALSE;
1756                                 DEBUGOUT("ANYSTATE  -> AN_PROG\n");
1757                         }
1758                 }
1759         }
1760
1761         return ret_val;
1762 }
1763
1764 /**
1765  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1766  *  @hw: pointer to the HW structure
1767  *  @data: pointer to the NVM (EEPROM)
1768  *
1769  *  Read the EEPROM for the current default LED configuration.  If the
1770  *  LED configuration is not valid, set to a valid LED configuration.
1771  **/
1772 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1773 {
1774         s32 ret_val;
1775
1776         DEBUGFUNC("e1000_valid_led_default_82571");
1777
1778         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1779         if (ret_val) {
1780                 DEBUGOUT("NVM Read Error\n");
1781                 goto out;
1782         }
1783
1784         switch (hw->mac.type) {
1785         case e1000_82573:
1786         case e1000_82574:
1787         case e1000_82583:
1788                 if (*data == ID_LED_RESERVED_F746)
1789                         *data = ID_LED_DEFAULT_82573;
1790                 break;
1791         default:
1792                 if (*data == ID_LED_RESERVED_0000 ||
1793                     *data == ID_LED_RESERVED_FFFF)
1794                         *data = ID_LED_DEFAULT;
1795                 break;
1796         }
1797
1798 out:
1799         return ret_val;
1800 }
1801
1802 /**
1803  *  e1000_get_laa_state_82571 - Get locally administered address state
1804  *  @hw: pointer to the HW structure
1805  *
1806  *  Retrieve and return the current locally administered address state.
1807  **/
1808 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1809 {
1810         DEBUGFUNC("e1000_get_laa_state_82571");
1811
1812         if (hw->mac.type != e1000_82571)
1813                 return FALSE;
1814
1815         return hw->dev_spec._82571.laa_is_present;
1816 }
1817
1818 /**
1819  *  e1000_set_laa_state_82571 - Set locally administered address state
1820  *  @hw: pointer to the HW structure
1821  *  @state: enable/disable locally administered address
1822  *
1823  *  Enable/Disable the current locally administered address state.
1824  **/
1825 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1826 {
1827         DEBUGFUNC("e1000_set_laa_state_82571");
1828
1829         if (hw->mac.type != e1000_82571)
1830                 return;
1831
1832         hw->dev_spec._82571.laa_is_present = state;
1833
1834         /* If workaround is activated... */
1835         if (state)
1836                 /*
1837                  * Hold a copy of the LAA in RAR[14] This is done so that
1838                  * between the time RAR[0] gets clobbered and the time it
1839                  * gets fixed, the actual LAA is in one of the RARs and no
1840                  * incoming packets directed to this port are dropped.
1841                  * Eventually the LAA will be in RAR[0] and RAR[14].
1842                  */
1843                 e1000_rar_set_generic(hw, hw->mac.addr,
1844                                       hw->mac.rar_entry_count - 1);
1845         return;
1846 }
1847
1848 /**
1849  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1850  *  @hw: pointer to the HW structure
1851  *
1852  *  Verifies that the EEPROM has completed the update.  After updating the
1853  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1854  *  the checksum fix is not implemented, we need to set the bit and update
1855  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1856  *  we need to return bad checksum.
1857  **/
1858 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1859 {
1860         struct e1000_nvm_info *nvm = &hw->nvm;
1861         s32 ret_val = E1000_SUCCESS;
1862         u16 data;
1863
1864         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1865
1866         if (nvm->type != e1000_nvm_flash_hw)
1867                 goto out;
1868
1869         /*
1870          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1871          * 10h-12h.  Checksum may need to be fixed.
1872          */
1873         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1874         if (ret_val)
1875                 goto out;
1876
1877         if (!(data & 0x10)) {
1878                 /*
1879                  * Read 0x23 and check bit 15.  This bit is a 1
1880                  * when the checksum has already been fixed.  If
1881                  * the checksum is still wrong and this bit is a
1882                  * 1, we need to return bad checksum.  Otherwise,
1883                  * we need to set this bit to a 1 and update the
1884                  * checksum.
1885                  */
1886                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1887                 if (ret_val)
1888                         goto out;
1889
1890                 if (!(data & 0x8000)) {
1891                         data |= 0x8000;
1892                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1893                         if (ret_val)
1894                                 goto out;
1895                         ret_val = nvm->ops.update(hw);
1896                 }
1897         }
1898
1899 out:
1900         return ret_val;
1901 }
1902
1903
1904 /**
1905  *  e1000_read_mac_addr_82571 - Read device MAC address
1906  *  @hw: pointer to the HW structure
1907  **/
1908 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1909 {
1910         s32 ret_val = E1000_SUCCESS;
1911
1912         DEBUGFUNC("e1000_read_mac_addr_82571");
1913
1914         if (hw->mac.type == e1000_82571) {
1915                 /*
1916                  * If there's an alternate MAC address place it in RAR0
1917                  * so that it will override the Si installed default perm
1918                  * address.
1919                  */
1920                 ret_val = e1000_check_alt_mac_addr_generic(hw);
1921                 if (ret_val)
1922                         goto out;
1923         }
1924
1925         ret_val = e1000_read_mac_addr_generic(hw);
1926
1927 out:
1928         return ret_val;
1929 }
1930
1931 /**
1932  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1933  * @hw: pointer to the HW structure
1934  *
1935  * In the case of a PHY power down to save power, or to turn off link during a
1936  * driver unload, or wake on lan is not enabled, remove the link.
1937  **/
1938 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1939 {
1940         struct e1000_phy_info *phy = &hw->phy;
1941         struct e1000_mac_info *mac = &hw->mac;
1942
1943         if (!(phy->ops.check_reset_block))
1944                 return;
1945
1946         /* If the management interface is not enabled, then power down */
1947         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1948                 e1000_power_down_phy_copper(hw);
1949
1950         return;
1951 }
1952
1953 /**
1954  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1955  *  @hw: pointer to the HW structure
1956  *
1957  *  Clears the hardware counters by reading the counter registers.
1958  **/
1959 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1960 {
1961         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1962
1963         e1000_clear_hw_cntrs_base_generic(hw);
1964
1965         E1000_READ_REG(hw, E1000_PRC64);
1966         E1000_READ_REG(hw, E1000_PRC127);
1967         E1000_READ_REG(hw, E1000_PRC255);
1968         E1000_READ_REG(hw, E1000_PRC511);
1969         E1000_READ_REG(hw, E1000_PRC1023);
1970         E1000_READ_REG(hw, E1000_PRC1522);
1971         E1000_READ_REG(hw, E1000_PTC64);
1972         E1000_READ_REG(hw, E1000_PTC127);
1973         E1000_READ_REG(hw, E1000_PTC255);
1974         E1000_READ_REG(hw, E1000_PTC511);
1975         E1000_READ_REG(hw, E1000_PTC1023);
1976         E1000_READ_REG(hw, E1000_PTC1522);
1977
1978         E1000_READ_REG(hw, E1000_ALGNERRC);
1979         E1000_READ_REG(hw, E1000_RXERRC);
1980         E1000_READ_REG(hw, E1000_TNCRS);
1981         E1000_READ_REG(hw, E1000_CEXTERR);
1982         E1000_READ_REG(hw, E1000_TSCTC);
1983         E1000_READ_REG(hw, E1000_TSCTFC);
1984
1985         E1000_READ_REG(hw, E1000_MGTPRC);
1986         E1000_READ_REG(hw, E1000_MGTPDC);
1987         E1000_READ_REG(hw, E1000_MGTPTC);
1988
1989         E1000_READ_REG(hw, E1000_IAC);
1990         E1000_READ_REG(hw, E1000_ICRXOC);
1991
1992         E1000_READ_REG(hw, E1000_ICRXPTC);
1993         E1000_READ_REG(hw, E1000_ICRXATC);
1994         E1000_READ_REG(hw, E1000_ICTXPTC);
1995         E1000_READ_REG(hw, E1000_ICTXATC);
1996         E1000_READ_REG(hw, E1000_ICTXQEC);
1997         E1000_READ_REG(hw, E1000_ICTXQMTC);
1998         E1000_READ_REG(hw, E1000_ICRXDMTC);
1999 }