sys/dev/e1000/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2010, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #define E1000_DEV_ID_82542                    0x1000
  45 #define E1000_DEV_ID_82543GC_FIBER            0x1001
  46 #define E1000_DEV_ID_82543GC_COPPER           0x1004
  47 #define E1000_DEV_ID_82544EI_COPPER           0x1008
  48 #define E1000_DEV_ID_82544EI_FIBER            0x1009
  49 #define E1000_DEV_ID_82544GC_COPPER           0x100C
  50 #define E1000_DEV_ID_82544GC_LOM              0x100D
  51 #define E1000_DEV_ID_82540EM                  0x100E
  52 #define E1000_DEV_ID_82540EM_LOM              0x1015
  53 #define E1000_DEV_ID_82540EP_LOM              0x1016
  54 #define E1000_DEV_ID_82540EP                  0x1017
  55 #define E1000_DEV_ID_82540EP_LP               0x101E
  56 #define E1000_DEV_ID_82545EM_COPPER           0x100F
  57 #define E1000_DEV_ID_82545EM_FIBER            0x1011
  58 #define E1000_DEV_ID_82545GM_COPPER           0x1026
  59 #define E1000_DEV_ID_82545GM_FIBER            0x1027
  60 #define E1000_DEV_ID_82545GM_SERDES           0x1028
  61 #define E1000_DEV_ID_82546EB_COPPER           0x1010
  62 #define E1000_DEV_ID_82546EB_FIBER            0x1012
  63 #define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
  64 #define E1000_DEV_ID_82546GB_COPPER           0x1079
  65 #define E1000_DEV_ID_82546GB_FIBER            0x107A
  66 #define E1000_DEV_ID_82546GB_SERDES           0x107B
  67 #define E1000_DEV_ID_82546GB_PCIE             0x108A
  68 #define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
  69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
  70 #define E1000_DEV_ID_82541EI                  0x1013
  71 #define E1000_DEV_ID_82541EI_MOBILE           0x1018
  72 #define E1000_DEV_ID_82541ER_LOM              0x1014
  73 #define E1000_DEV_ID_82541ER                  0x1078
  74 #define E1000_DEV_ID_82541GI                  0x1076
  75 #define E1000_DEV_ID_82541GI_LF               0x107C
  76 #define E1000_DEV_ID_82541GI_MOBILE           0x1077
  77 #define E1000_DEV_ID_82547EI                  0x1019
  78 #define E1000_DEV_ID_82547EI_MOBILE           0x101A
  79 #define E1000_DEV_ID_82547GI                  0x1075
  80 #define E1000_DEV_ID_82571EB_COPPER           0x105E
  81 #define E1000_DEV_ID_82571EB_FIBER            0x105F
  82 #define E1000_DEV_ID_82571EB_SERDES           0x1060
  83 #define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
  84 #define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
  85 #define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
  86 #define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
  87 #define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
  88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
  89 #define E1000_DEV_ID_82572EI_COPPER           0x107D
  90 #define E1000_DEV_ID_82572EI_FIBER            0x107E
  91 #define E1000_DEV_ID_82572EI_SERDES           0x107F
  92 #define E1000_DEV_ID_82572EI                  0x10B9
  93 #define E1000_DEV_ID_82573E                   0x108B
  94 #define E1000_DEV_ID_82573E_IAMT              0x108C
  95 #define E1000_DEV_ID_82573L                   0x109A
  96 #define E1000_DEV_ID_82574L                   0x10D3
  97 #define E1000_DEV_ID_82574LA                  0x10F6
  98 #define E1000_DEV_ID_82583V                   0x150C
  99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
 103 #define E1000_DEV_ID_ICH8_82567V_3            0x1501
 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
 105 #define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
 106 #define E1000_DEV_ID_ICH8_IGP_C               0x104B
 107 #define E1000_DEV_ID_ICH8_IFE                 0x104C
 108 #define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
 109 #define E1000_DEV_ID_ICH8_IFE_G               0x10C5
 110 #define E1000_DEV_ID_ICH8_IGP_M               0x104D
 111 #define E1000_DEV_ID_ICH9_IGP_M               0x10BF
 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
 113 #define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
 114 #define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
 115 #define E1000_DEV_ID_ICH9_BM                  0x10E5
 116 #define E1000_DEV_ID_ICH9_IGP_C               0x294C
 117 #define E1000_DEV_ID_ICH9_IFE                 0x10C0
 118 #define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
 119 #define E1000_DEV_ID_ICH9_IFE_G               0x10C2
 120 #define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
 121 #define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
 122 #define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
 123 #define E1000_DEV_ID_ICH10_HANKSVILLE         0xF0FE
 124 #define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
 125 #define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
 126 #define E1000_DEV_ID_ICH10_D_BM_V             0x1525
 127
 128 #define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
 129 #define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
 130 #define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
 131 #define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
 132 #define E1000_DEV_ID_PCH2_LV_LM               0x1502
 133 #define E1000_DEV_ID_PCH2_LV_V                0x1503
 134 #define E1000_DEV_ID_82576                    0x10C9
 135 #define E1000_DEV_ID_82576_FIBER              0x10E6
 136 #define E1000_DEV_ID_82576_SERDES             0x10E7
 137 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
 138 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2    0x1526
 139 #define E1000_DEV_ID_82576_NS                 0x150A
 140 #define E1000_DEV_ID_82576_NS_SERDES          0x1518
 141 #define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
 142 #define E1000_DEV_ID_82576_VF                 0x10CA
 143 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
 144 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
 145 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
 146 #define E1000_DEV_ID_82575GB_QUAD_COPPER_PM   0x10E2
 147 #define E1000_DEV_ID_82580_COPPER             0x150E
 148 #define E1000_DEV_ID_82580_FIBER              0x150F
 149 #define E1000_DEV_ID_82580_SERDES             0x1510
 150 #define E1000_DEV_ID_82580_SGMII              0x1511
 151 #define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
 152 #define E1000_DEV_ID_82580_QUAD_FIBER         0x1527
 153 #define E1000_DEV_ID_DH89XXCC_SGMII           0x0436
 154 #define E1000_DEV_ID_DH89XXCC_SERDES          0x0438
 155 #define E1000_REVISION_0 0
 156 #define E1000_REVISION_1 1
 157 #define E1000_REVISION_2 2
 158 #define E1000_REVISION_3 3
 159 #define E1000_REVISION_4 4
 160
 161 #define E1000_FUNC_0     0
 162 #define E1000_FUNC_1     1
 163 #define E1000_FUNC_2     2
 164 #define E1000_FUNC_3     3
 165
 166 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
 167 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
 168 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
 169 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
 170
 171 enum e1000_mac_type {
 172         e1000_undefined = 0,
 173         e1000_82542,
 174         e1000_82543,
 175         e1000_82544,
 176         e1000_82540,
 177         e1000_82545,
 178         e1000_82545_rev_3,
 179         e1000_82546,
 180         e1000_82546_rev_3,
 181         e1000_82541,
 182         e1000_82541_rev_2,
 183         e1000_82547,
 184         e1000_82547_rev_2,
 185         e1000_82571,
 186         e1000_82572,
 187         e1000_82573,
 188         e1000_82574,
 189         e1000_82583,
 190         e1000_80003es2lan,
 191         e1000_ich8lan,
 192         e1000_ich9lan,
 193         e1000_ich10lan,
 194         e1000_pchlan,
 195         e1000_pch2lan,
 196         e1000_82575,
 197         e1000_82576,
 198         e1000_82580,
 199         e1000_vfadapt,
 200         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 201 };
 202
 203 enum e1000_media_type {
 204         e1000_media_type_unknown = 0,
 205         e1000_media_type_copper = 1,
 206         e1000_media_type_fiber = 2,
 207         e1000_media_type_internal_serdes = 3,
 208         e1000_num_media_types
 209 };
 210
 211 enum e1000_nvm_type {
 212         e1000_nvm_unknown = 0,
 213         e1000_nvm_none,
 214         e1000_nvm_eeprom_spi,
 215         e1000_nvm_eeprom_microwire,
 216         e1000_nvm_flash_hw,
 217         e1000_nvm_flash_sw
 218 };
 219
 220 enum e1000_nvm_override {
 221         e1000_nvm_override_none = 0,
 222         e1000_nvm_override_spi_small,
 223         e1000_nvm_override_spi_large,
 224         e1000_nvm_override_microwire_small,
 225         e1000_nvm_override_microwire_large
 226 };
 227
 228 enum e1000_phy_type {
 229         e1000_phy_unknown = 0,
 230         e1000_phy_none,
 231         e1000_phy_m88,
 232         e1000_phy_igp,
 233         e1000_phy_igp_2,
 234         e1000_phy_gg82563,
 235         e1000_phy_igp_3,
 236         e1000_phy_ife,
 237         e1000_phy_bm,
 238         e1000_phy_82578,
 239         e1000_phy_82577,
 240         e1000_phy_82579,
 241         e1000_phy_82580,
 242         e1000_phy_vf,
 243 };
 244
 245 enum e1000_bus_type {
 246         e1000_bus_type_unknown = 0,
 247         e1000_bus_type_pci,
 248         e1000_bus_type_pcix,
 249         e1000_bus_type_pci_express,
 250         e1000_bus_type_reserved
 251 };
 252
 253 enum e1000_bus_speed {
 254         e1000_bus_speed_unknown = 0,
 255         e1000_bus_speed_33,
 256         e1000_bus_speed_66,
 257         e1000_bus_speed_100,
 258         e1000_bus_speed_120,
 259         e1000_bus_speed_133,
 260         e1000_bus_speed_2500,
 261         e1000_bus_speed_5000,
 262         e1000_bus_speed_reserved
 263 };
 264
 265 enum e1000_bus_width {
 266         e1000_bus_width_unknown = 0,
 267         e1000_bus_width_pcie_x1,
 268         e1000_bus_width_pcie_x2,
 269         e1000_bus_width_pcie_x4 = 4,
 270         e1000_bus_width_pcie_x8 = 8,
 271         e1000_bus_width_32,
 272         e1000_bus_width_64,
 273         e1000_bus_width_reserved
 274 };
 275
 276 enum e1000_1000t_rx_status {
 277         e1000_1000t_rx_status_not_ok = 0,
 278         e1000_1000t_rx_status_ok,
 279         e1000_1000t_rx_status_undefined = 0xFF
 280 };
 281
 282 enum e1000_rev_polarity {
 283         e1000_rev_polarity_normal = 0,
 284         e1000_rev_polarity_reversed,
 285         e1000_rev_polarity_undefined = 0xFF
 286 };
 287
 288 enum e1000_fc_mode {
 289         e1000_fc_none = 0,
 290         e1000_fc_rx_pause,
 291         e1000_fc_tx_pause,
 292         e1000_fc_full,
 293         e1000_fc_default = 0xFF
 294 };
 295
 296 enum e1000_ffe_config {
 297         e1000_ffe_config_enabled = 0,
 298         e1000_ffe_config_active,
 299         e1000_ffe_config_blocked
 300 };
 301
 302 enum e1000_dsp_config {
 303         e1000_dsp_config_disabled = 0,
 304         e1000_dsp_config_enabled,
 305         e1000_dsp_config_activated,
 306         e1000_dsp_config_undefined = 0xFF
 307 };
 308
 309 enum e1000_ms_type {
 310         e1000_ms_hw_default = 0,
 311         e1000_ms_force_master,
 312         e1000_ms_force_slave,
 313         e1000_ms_auto
 314 };
 315
 316 enum e1000_smart_speed {
 317         e1000_smart_speed_default = 0,
 318         e1000_smart_speed_on,
 319         e1000_smart_speed_off
 320 };
 321
 322 enum e1000_serdes_link_state {
 323         e1000_serdes_link_down = 0,
 324         e1000_serdes_link_autoneg_progress,
 325         e1000_serdes_link_autoneg_complete,
 326         e1000_serdes_link_forced_up
 327 };
 328
 329 #define __le16 u16
 330 #define __le32 u32
 331 #define __le64 u64
 332 /* Receive Descriptor */
 333 struct e1000_rx_desc {
 334         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 335         __le16 length;      /* Length of data DMAed into data buffer */
 336         __le16 csum;        /* Packet checksum */
 337         u8  status;         /* Descriptor status */
 338         u8  errors;         /* Descriptor Errors */
 339         __le16 special;
 340 };
 341
 342 /* Receive Descriptor - Extended */
 343 union e1000_rx_desc_extended {
 344         struct {
 345                 __le64 buffer_addr;
 346                 __le64 reserved;
 347         } read;
 348         struct {
 349                 struct {
 350                         __le32 mrq;           /* Multiple Rx Queues */
 351                         union {
 352                                 __le32 rss;         /* RSS Hash */
 353                                 struct {
 354                                         __le16 ip_id;  /* IP id */
 355                                         __le16 csum;   /* Packet Checksum */
 356                                 } csum_ip;
 357                         } hi_dword;
 358                 } lower;
 359                 struct {
 360                         __le32 status_error;  /* ext status/error */
 361                         __le16 length;
 362                         __le16 vlan;          /* VLAN tag */
 363                 } upper;
 364         } wb;  /* writeback */
 365 };
 366
 367 #define MAX_PS_BUFFERS 4
 368 /* Receive Descriptor - Packet Split */
 369 union e1000_rx_desc_packet_split {
 370         struct {
 371                 /* one buffer for protocol header(s), three data buffers */
 372                 __le64 buffer_addr[MAX_PS_BUFFERS];
 373         } read;
 374         struct {
 375                 struct {
 376                         __le32 mrq;           /* Multiple Rx Queues */
 377                         union {
 378                                 __le32 rss;           /* RSS Hash */
 379                                 struct {
 380                                         __le16 ip_id;    /* IP id */
 381                                         __le16 csum;     /* Packet Checksum */
 382                                 } csum_ip;
 383                         } hi_dword;
 384                 } lower;
 385                 struct {
 386                         __le32 status_error;  /* ext status/error */
 387                         __le16 length0;       /* length of buffer 0 */
 388                         __le16 vlan;          /* VLAN tag */
 389                 } middle;
 390                 struct {
 391                         __le16 header_status;
 392                         __le16 length[3];     /* length of buffers 1-3 */
 393                 } upper;
 394                 __le64 reserved;
 395         } wb; /* writeback */
 396 };
 397
 398 /* Transmit Descriptor */
 399 struct e1000_tx_desc {
 400         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 401         union {
 402                 __le32 data;
 403                 struct {
 404                         __le16 length;    /* Data buffer length */
 405                         u8 cso;           /* Checksum offset */
 406                         u8 cmd;           /* Descriptor control */
 407                 } flags;
 408         } lower;
 409         union {
 410                 __le32 data;
 411                 struct {
 412                         u8 status;        /* Descriptor status */
 413                         u8 css;           /* Checksum start */
 414                         __le16 special;
 415                 } fields;
 416         } upper;
 417 };
 418
 419 /* Offload Context Descriptor */
 420 struct e1000_context_desc {
 421         union {
 422                 __le32 ip_config;
 423                 struct {
 424                         u8 ipcss;         /* IP checksum start */
 425                         u8 ipcso;         /* IP checksum offset */
 426                         __le16 ipcse;     /* IP checksum end */
 427                 } ip_fields;
 428         } lower_setup;
 429         union {
 430                 __le32 tcp_config;
 431                 struct {
 432                         u8 tucss;         /* TCP checksum start */
 433                         u8 tucso;         /* TCP checksum offset */
 434                         __le16 tucse;     /* TCP checksum end */
 435                 } tcp_fields;
 436         } upper_setup;
 437         __le32 cmd_and_length;
 438         union {
 439                 __le32 data;
 440                 struct {
 441                         u8 status;        /* Descriptor status */
 442                         u8 hdr_len;       /* Header length */
 443                         __le16 mss;       /* Maximum segment size */
 444                 } fields;
 445         } tcp_seg_setup;
 446 };
 447
 448 /* Offload data descriptor */
 449 struct e1000_data_desc {
 450         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 451         union {
 452                 __le32 data;
 453                 struct {
 454                         __le16 length;    /* Data buffer length */
 455                         u8 typ_len_ext;
 456                         u8 cmd;
 457                 } flags;
 458         } lower;
 459         union {
 460                 __le32 data;
 461                 struct {
 462                         u8 status;        /* Descriptor status */
 463                         u8 popts;         /* Packet Options */
 464                         __le16 special;
 465                 } fields;
 466         } upper;
 467 };
 468
 469 /* Statistics counters collected by the MAC */
 470 struct e1000_hw_stats {
 471         u64 crcerrs;
 472         u64 algnerrc;
 473         u64 symerrs;
 474         u64 rxerrc;
 475         u64 mpc;
 476         u64 scc;
 477         u64 ecol;
 478         u64 mcc;
 479         u64 latecol;
 480         u64 colc;
 481         u64 dc;
 482         u64 tncrs;
 483         u64 sec;
 484         u64 cexterr;
 485         u64 rlec;
 486         u64 xonrxc;
 487         u64 xontxc;
 488         u64 xoffrxc;
 489         u64 xofftxc;
 490         u64 fcruc;
 491         u64 prc64;
 492         u64 prc127;
 493         u64 prc255;
 494         u64 prc511;
 495         u64 prc1023;
 496         u64 prc1522;
 497         u64 gprc;
 498         u64 bprc;
 499         u64 mprc;
 500         u64 gptc;
 501         u64 gorc;
 502         u64 gotc;
 503         u64 rnbc;
 504         u64 ruc;
 505         u64 rfc;
 506         u64 roc;
 507         u64 rjc;
 508         u64 mgprc;
 509         u64 mgpdc;
 510         u64 mgptc;
 511         u64 tor;
 512         u64 tot;
 513         u64 tpr;
 514         u64 tpt;
 515         u64 ptc64;
 516         u64 ptc127;
 517         u64 ptc255;
 518         u64 ptc511;
 519         u64 ptc1023;
 520         u64 ptc1522;
 521         u64 mptc;
 522         u64 bptc;
 523         u64 tsctc;
 524         u64 tsctfc;
 525         u64 iac;
 526         u64 icrxptc;
 527         u64 icrxatc;
 528         u64 ictxptc;
 529         u64 ictxatc;
 530         u64 ictxqec;
 531         u64 ictxqmtc;
 532         u64 icrxdmtc;
 533         u64 icrxoc;
 534         u64 cbtmpc;
 535         u64 htdpmc;
 536         u64 cbrdpc;
 537         u64 cbrmpc;
 538         u64 rpthc;
 539         u64 hgptc;
 540         u64 htcbdpc;
 541         u64 hgorc;
 542         u64 hgotc;
 543         u64 lenerrs;
 544         u64 scvpc;
 545         u64 hrmpc;
 546         u64 doosync;
 547 };
 548
 549 struct e1000_vf_stats {
 550         u64 base_gprc;
 551         u64 base_gptc;
 552         u64 base_gorc;
 553         u64 base_gotc;
 554         u64 base_mprc;
 555         u64 base_gotlbc;
 556         u64 base_gptlbc;
 557         u64 base_gorlbc;
 558         u64 base_gprlbc;
 559
 560         u32 last_gprc;
 561         u32 last_gptc;
 562         u32 last_gorc;
 563         u32 last_gotc;
 564         u32 last_mprc;
 565         u32 last_gotlbc;
 566         u32 last_gptlbc;
 567         u32 last_gorlbc;
 568         u32 last_gprlbc;
 569
 570         u64 gprc;
 571         u64 gptc;
 572         u64 gorc;
 573         u64 gotc;
 574         u64 mprc;
 575         u64 gotlbc;
 576         u64 gptlbc;
 577         u64 gorlbc;
 578         u64 gprlbc;
 579 };
 580
 581 struct e1000_phy_stats {
 582         u32 idle_errors;
 583         u32 receive_errors;
 584 };
 585
 586 struct e1000_host_mng_dhcp_cookie {
 587         u32 signature;
 588         u8  status;
 589         u8  reserved0;
 590         u16 vlan_id;
 591         u32 reserved1;
 592         u16 reserved2;
 593         u8  reserved3;
 594         u8  checksum;
 595 };
 596
 597 /* Host Interface "Rev 1" */
 598 struct e1000_host_command_header {
 599         u8 command_id;
 600         u8 command_length;
 601         u8 command_options;
 602         u8 checksum;
 603 };
 604
 605 #define E1000_HI_MAX_DATA_LENGTH     252
 606 struct e1000_host_command_info {
 607         struct e1000_host_command_header command_header;
 608         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 609 };
 610
 611 /* Host Interface "Rev 2" */
 612 struct e1000_host_mng_command_header {
 613         u8  command_id;
 614         u8  checksum;
 615         u16 reserved1;
 616         u16 reserved2;
 617         u16 command_length;
 618 };
 619
 620 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 621 struct e1000_host_mng_command_info {
 622         struct e1000_host_mng_command_header command_header;
 623         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 624 };
 625
 626 #include "e1000_mac.h"
 627 #include "e1000_phy.h"
 628 #include "e1000_nvm.h"
 629 #include "e1000_manage.h"
 630 #include "e1000_mbx.h"
 631
 632 struct e1000_mac_operations {
 633         /* Function pointers for the MAC. */
 634         s32  (*init_params)(struct e1000_hw *);
 635         s32  (*id_led_init)(struct e1000_hw *);
 636         s32  (*blink_led)(struct e1000_hw *);
 637         s32  (*check_for_link)(struct e1000_hw *);
 638         bool (*check_mng_mode)(struct e1000_hw *hw);
 639         s32  (*cleanup_led)(struct e1000_hw *);
 640         void (*clear_hw_cntrs)(struct e1000_hw *);
 641         void (*clear_vfta)(struct e1000_hw *);
 642         s32  (*get_bus_info)(struct e1000_hw *);
 643         void (*set_lan_id)(struct e1000_hw *);
 644         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 645         s32  (*led_on)(struct e1000_hw *);
 646         s32  (*led_off)(struct e1000_hw *);
 647         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 648         s32  (*reset_hw)(struct e1000_hw *);
 649         s32  (*init_hw)(struct e1000_hw *);
 650         void (*shutdown_serdes)(struct e1000_hw *);
 651         void (*power_up_serdes)(struct e1000_hw *);
 652         s32  (*setup_link)(struct e1000_hw *);
 653         s32  (*setup_physical_interface)(struct e1000_hw *);
 654         s32  (*setup_led)(struct e1000_hw *);
 655         void (*write_vfta)(struct e1000_hw *, u32, u32);
 656         void (*config_collision_dist)(struct e1000_hw *);
 657         void (*rar_set)(struct e1000_hw *, u8*, u32);
 658         s32  (*read_mac_addr)(struct e1000_hw *);
 659         s32  (*validate_mdi_setting)(struct e1000_hw *);
 660         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 661         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 662                       struct e1000_host_mng_command_header*);
 663         s32  (*mng_enable_host_if)(struct e1000_hw *);
 664         s32  (*wait_autoneg)(struct e1000_hw *);
 665 };
 666
 667 struct e1000_phy_operations {
 668         s32  (*init_params)(struct e1000_hw *);
 669         s32  (*acquire)(struct e1000_hw *);
 670         s32  (*cfg_on_link_up)(struct e1000_hw *);
 671         s32  (*check_polarity)(struct e1000_hw *);
 672         s32  (*check_reset_block)(struct e1000_hw *);
 673         s32  (*commit)(struct e1000_hw *);
 674         s32  (*force_speed_duplex)(struct e1000_hw *);
 675         s32  (*get_cfg_done)(struct e1000_hw *hw);
 676         s32  (*get_cable_length)(struct e1000_hw *);
 677         s32  (*get_info)(struct e1000_hw *);
 678         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 679         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 680         void (*release)(struct e1000_hw *);
 681         s32  (*reset)(struct e1000_hw *);
 682         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 683         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 684         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 685         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 686         void (*power_up)(struct e1000_hw *);
 687         void (*power_down)(struct e1000_hw *);
 688 };
 689
 690 struct e1000_nvm_operations {
 691         s32  (*init_params)(struct e1000_hw *);
 692         s32  (*acquire)(struct e1000_hw *);
 693         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 694         void (*release)(struct e1000_hw *);
 695         void (*reload)(struct e1000_hw *);
 696         s32  (*update)(struct e1000_hw *);
 697         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 698         s32  (*validate)(struct e1000_hw *);
 699         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 700 };
 701
 702 struct e1000_mac_info {
 703         struct e1000_mac_operations ops;
 704         u8 addr[6];
 705         u8 perm_addr[6];
 706
 707         enum e1000_mac_type type;
 708
 709         u32 collision_delta;
 710         u32 ledctl_default;
 711         u32 ledctl_mode1;
 712         u32 ledctl_mode2;
 713         u32 mc_filter_type;
 714         u32 tx_packet_delta;
 715         u32 txcw;
 716
 717         u16 current_ifs_val;
 718         u16 ifs_max_val;
 719         u16 ifs_min_val;
 720         u16 ifs_ratio;
 721         u16 ifs_step_size;
 722         u16 mta_reg_count;
 723         u16 uta_reg_count;
 724
 725         /* Maximum size of the MTA register table in all supported adapters */
 726         #define MAX_MTA_REG 128
 727         u32 mta_shadow[MAX_MTA_REG];
 728         u16 rar_entry_count;
 729
 730         u8  forced_speed_duplex;
 731
 732         bool adaptive_ifs;
 733         bool has_fwsm;
 734         bool arc_subsystem_valid;
 735         bool asf_firmware_present;
 736         bool autoneg;
 737         bool autoneg_failed;
 738         bool get_link_status;
 739         bool in_ifs_mode;
 740         bool report_tx_early;
 741         enum e1000_serdes_link_state serdes_link_state;
 742         bool serdes_has_link;
 743         bool tx_pkt_filtering;
 744 };
 745
 746 struct e1000_phy_info {
 747         struct e1000_phy_operations ops;
 748         enum e1000_phy_type type;
 749
 750         enum e1000_1000t_rx_status local_rx;
 751         enum e1000_1000t_rx_status remote_rx;
 752         enum e1000_ms_type ms_type;
 753         enum e1000_ms_type original_ms_type;
 754         enum e1000_rev_polarity cable_polarity;
 755         enum e1000_smart_speed smart_speed;
 756
 757         u32 addr;
 758         u32 id;
 759         u32 reset_delay_us; /* in usec */
 760         u32 revision;
 761
 762         enum e1000_media_type media_type;
 763
 764         u16 autoneg_advertised;
 765         u16 autoneg_mask;
 766         u16 cable_length;
 767         u16 max_cable_length;
 768         u16 min_cable_length;
 769
 770         u8 mdix;
 771
 772         bool disable_polarity_correction;
 773         bool is_mdix;
 774         bool polarity_correction;
 775         bool reset_disable;
 776         bool speed_downgraded;
 777         bool autoneg_wait_to_complete;
 778 };
 779
 780 struct e1000_nvm_info {
 781         struct e1000_nvm_operations ops;
 782         enum e1000_nvm_type type;
 783         enum e1000_nvm_override override;
 784
 785         u32 flash_bank_size;
 786         u32 flash_base_addr;
 787
 788         u16 word_size;
 789         u16 delay_usec;
 790         u16 address_bits;
 791         u16 opcode_bits;
 792         u16 page_size;
 793 };
 794
 795 struct e1000_bus_info {
 796         enum e1000_bus_type type;
 797         enum e1000_bus_speed speed;
 798         enum e1000_bus_width width;
 799
 800         u16 func;
 801         u16 pci_cmd_word;
 802 };
 803
 804 struct e1000_fc_info {
 805         u32 high_water;          /* Flow control high-water mark */
 806         u32 low_water;           /* Flow control low-water mark */
 807         u16 pause_time;          /* Flow control pause timer */
 808         u16 refresh_time;        /* Flow control refresh timer */
 809         bool send_xon;           /* Flow control send XON */
 810         bool strict_ieee;        /* Strict IEEE mode */
 811         enum e1000_fc_mode current_mode; /* FC mode in effect */
 812         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 813 };
 814
 815 struct e1000_mbx_operations {
 816         s32 (*init_params)(struct e1000_hw *hw);
 817         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 818         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 819         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 820         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 821         s32 (*check_for_msg)(struct e1000_hw *, u16);
 822         s32 (*check_for_ack)(struct e1000_hw *, u16);
 823         s32 (*check_for_rst)(struct e1000_hw *, u16);
 824 };
 825
 826 struct e1000_mbx_stats {
 827         u32 msgs_tx;
 828         u32 msgs_rx;
 829
 830         u32 acks;
 831         u32 reqs;
 832         u32 rsts;
 833 };
 834
 835 struct e1000_mbx_info {
 836         struct e1000_mbx_operations ops;
 837         struct e1000_mbx_stats stats;
 838         u32 timeout;
 839         u32 usec_delay;
 840         u16 size;
 841 };
 842
 843 struct e1000_dev_spec_82541 {
 844         enum e1000_dsp_config dsp_config;
 845         enum e1000_ffe_config ffe_config;
 846         u16 spd_default;
 847         bool phy_init_script;
 848 };
 849
 850 struct e1000_dev_spec_82542 {
 851         bool dma_fairness;
 852 };
 853
 854 struct e1000_dev_spec_82543 {
 855         u32  tbi_compatibility;
 856         bool dma_fairness;
 857         bool init_phy_disabled;
 858 };
 859
 860 struct e1000_dev_spec_82571 {
 861         bool laa_is_present;
 862         u32 smb_counter;
 863         E1000_MUTEX swflag_mutex;
 864 };
 865
 866 struct e1000_dev_spec_80003es2lan {
 867         bool  mdic_wa_enable;
 868 };
 869
 870 struct e1000_shadow_ram {
 871         u16  value;
 872         bool modified;
 873 };
 874
 875 #define E1000_SHADOW_RAM_WORDS          2048
 876
 877 struct e1000_dev_spec_ich8lan {
 878         bool kmrn_lock_loss_workaround_enabled;
 879         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 880         E1000_MUTEX nvm_mutex;
 881         E1000_MUTEX swflag_mutex;
 882         bool nvm_k1_enabled;
 883         bool eee_disable;
 884 };
 885
 886 struct e1000_dev_spec_82575 {
 887         bool sgmii_active;
 888         bool global_device_reset;
 889 };
 890
 891 struct e1000_dev_spec_vf {
 892         u32     vf_number;
 893         u32     v2p_mailbox;
 894 };
 895
 896 struct e1000_hw {
 897         void *back;
 898
 899         u8 *hw_addr;
 900         u8 *flash_address;
 901         unsigned long io_base;
 902
 903         struct e1000_mac_info  mac;
 904         struct e1000_fc_info   fc;
 905         struct e1000_phy_info  phy;
 906         struct e1000_nvm_info  nvm;
 907         struct e1000_bus_info  bus;
 908         struct e1000_mbx_info mbx;
 909         struct e1000_host_mng_dhcp_cookie mng_cookie;
 910
 911         union {
 912                 struct e1000_dev_spec_82541     _82541;
 913                 struct e1000_dev_spec_82542     _82542;
 914                 struct e1000_dev_spec_82543     _82543;
 915                 struct e1000_dev_spec_82571     _82571;
 916                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 917                 struct e1000_dev_spec_ich8lan   ich8lan;
 918                 struct e1000_dev_spec_82575     _82575;
 919                 struct e1000_dev_spec_vf        vf;
 920         } dev_spec;
 921
 922         u16 device_id;
 923         u16 subsystem_vendor_id;
 924         u16 subsystem_device_id;
 925         u16 vendor_id;
 926
 927         u8  revision_id;
 928 };
 929
 930 #include "e1000_82541.h"
 931 #include "e1000_82543.h"
 932 #include "e1000_82571.h"
 933 #include "e1000_80003es2lan.h"
 934 #include "e1000_ich8lan.h"
 935 #include "e1000_82575.h"
 936
 937 /* These functions must be implemented by drivers */
 938 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 939 void e1000_pci_set_mwi(struct e1000_hw *hw);
 940 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 941 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 942 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 943 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 944
 945 #endif