2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
39 #include <sys/module.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_vlan_var.h>
56 #include <netinet/in.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/ip.h>
59 #include <netinet/tcp.h>
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
67 #include <machine/atomic.h>
68 #include <machine/bus.h>
69 #include <machine/in_cksum.h>
71 #include <dev/jme/if_jmereg.h>
72 #include <dev/jme/if_jmevar.h>
74 /* "device miibus" required. See GENERIC if you get errors here. */
75 #include "miibus_if.h"
77 /* Define the following to disable printing Rx errors. */
78 #undef JME_SHOW_ERRORS
80 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
82 MODULE_DEPEND(jme, pci, 1, 1, 1);
83 MODULE_DEPEND(jme, ether, 1, 1, 1);
84 MODULE_DEPEND(jme, miibus, 1, 1, 1);
87 static int msi_disable = 0;
88 static int msix_disable = 0;
89 TUNABLE_INT("hw.jme.msi_disable", &msi_disable);
90 TUNABLE_INT("hw.jme.msix_disable", &msix_disable);
93 * Devices supported by this driver.
95 static struct jme_dev {
96 uint16_t jme_vendorid;
97 uint16_t jme_deviceid;
100 { VENDORID_JMICRON, DEVICEID_JMC250,
101 "JMicron Inc, JMC250 Gigabit Ethernet" },
102 { VENDORID_JMICRON, DEVICEID_JMC260,
103 "JMicron Inc, JMC260 Fast Ethernet" },
106 static int jme_miibus_readreg(device_t, int, int);
107 static int jme_miibus_writereg(device_t, int, int, int);
108 static void jme_miibus_statchg(device_t);
109 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
110 static int jme_mediachange(struct ifnet *);
111 static int jme_probe(device_t);
112 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
113 static int jme_eeprom_macaddr(struct jme_softc *);
114 static void jme_reg_macaddr(struct jme_softc *);
115 static void jme_map_intr_vector(struct jme_softc *);
116 static int jme_attach(device_t);
117 static int jme_detach(device_t);
118 static void jme_sysctl_node(struct jme_softc *);
119 static void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int);
120 static int jme_dma_alloc(struct jme_softc *);
121 static void jme_dma_free(struct jme_softc *);
122 static int jme_shutdown(device_t);
123 static void jme_setlinkspeed(struct jme_softc *);
124 static void jme_setwol(struct jme_softc *);
125 static int jme_suspend(device_t);
126 static int jme_resume(device_t);
127 static int jme_encap(struct jme_softc *, struct mbuf **);
128 static void jme_tx_task(void *, int);
129 static void jme_start(struct ifnet *);
130 static void jme_watchdog(struct jme_softc *);
131 static int jme_ioctl(struct ifnet *, u_long, caddr_t);
132 static void jme_mac_config(struct jme_softc *);
133 static void jme_link_task(void *, int);
134 static int jme_intr(void *);
135 static void jme_int_task(void *, int);
136 static void jme_txeof(struct jme_softc *);
137 static __inline void jme_discard_rxbuf(struct jme_softc *, int);
138 static void jme_rxeof(struct jme_softc *);
139 static int jme_rxintr(struct jme_softc *, int);
140 static void jme_tick(void *);
141 static void jme_reset(struct jme_softc *);
142 static void jme_init(void *);
143 static void jme_init_locked(struct jme_softc *);
144 static void jme_stop(struct jme_softc *);
145 static void jme_stop_tx(struct jme_softc *);
146 static void jme_stop_rx(struct jme_softc *);
147 static int jme_init_rx_ring(struct jme_softc *);
148 static void jme_init_tx_ring(struct jme_softc *);
149 static void jme_init_ssb(struct jme_softc *);
150 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *);
151 static void jme_set_vlan(struct jme_softc *);
152 static void jme_set_filter(struct jme_softc *);
153 static void jme_stats_clear(struct jme_softc *);
154 static void jme_stats_save(struct jme_softc *);
155 static void jme_stats_update(struct jme_softc *);
156 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
157 static int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS);
158 static int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
159 static int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS);
160 static int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
161 static int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS);
164 static device_method_t jme_methods[] = {
165 /* Device interface. */
166 DEVMETHOD(device_probe, jme_probe),
167 DEVMETHOD(device_attach, jme_attach),
168 DEVMETHOD(device_detach, jme_detach),
169 DEVMETHOD(device_shutdown, jme_shutdown),
170 DEVMETHOD(device_suspend, jme_suspend),
171 DEVMETHOD(device_resume, jme_resume),
174 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
175 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
176 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
181 static driver_t jme_driver = {
184 sizeof(struct jme_softc)
187 static devclass_t jme_devclass;
189 DRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0);
190 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
192 static struct resource_spec jme_res_spec_mem[] = {
193 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
197 static struct resource_spec jme_irq_spec_legacy[] = {
198 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
202 static struct resource_spec jme_irq_spec_msi[] = {
203 { SYS_RES_IRQ, 1, RF_ACTIVE },
208 * Read a PHY register on the MII of the JMC250.
211 jme_miibus_readreg(device_t dev, int phy, int reg)
213 struct jme_softc *sc;
217 sc = device_get_softc(dev);
219 /* For FPGA version, PHY address 0 should be ignored. */
220 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
223 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
224 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
225 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
227 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
232 device_printf(sc->jme_dev, "phy read timeout : %d\n", reg);
236 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
240 * Write a PHY register on the MII of the JMC250.
243 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
245 struct jme_softc *sc;
248 sc = device_get_softc(dev);
250 /* For FPGA version, PHY address 0 should be ignored. */
251 if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0)
254 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
255 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
256 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
257 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
259 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
264 device_printf(sc->jme_dev, "phy write timeout : %d\n", reg);
270 * Callback from MII layer when media changes.
273 jme_miibus_statchg(device_t dev)
275 struct jme_softc *sc;
277 sc = device_get_softc(dev);
278 taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task);
282 * Get the current interface media status.
285 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
287 struct jme_softc *sc;
288 struct mii_data *mii;
292 if ((ifp->if_flags & IFF_UP) == 0) {
296 mii = device_get_softc(sc->jme_miibus);
299 ifmr->ifm_status = mii->mii_media_status;
300 ifmr->ifm_active = mii->mii_media_active;
305 * Set hardware to newly-selected media.
308 jme_mediachange(struct ifnet *ifp)
310 struct jme_softc *sc;
311 struct mii_data *mii;
312 struct mii_softc *miisc;
317 mii = device_get_softc(sc->jme_miibus);
318 if (mii->mii_instance != 0) {
319 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
320 mii_phy_reset(miisc);
322 error = mii_mediachg(mii);
329 jme_probe(device_t dev)
333 uint16_t vendor, devid;
335 vendor = pci_get_vendor(dev);
336 devid = pci_get_device(dev);
338 for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]);
340 if (vendor == sp->jme_vendorid &&
341 devid == sp->jme_deviceid) {
342 device_set_desc(dev, sp->jme_name);
343 return (BUS_PROBE_DEFAULT);
351 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
357 for (i = JME_TIMEOUT; i > 0; i--) {
358 reg = CSR_READ_4(sc, JME_SMBCSR);
359 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
365 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
369 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
370 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
371 for (i = JME_TIMEOUT; i > 0; i--) {
373 reg = CSR_READ_4(sc, JME_SMBINTF);
374 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
379 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
383 reg = CSR_READ_4(sc, JME_SMBINTF);
384 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
390 jme_eeprom_macaddr(struct jme_softc *sc)
392 uint8_t eaddr[ETHER_ADDR_LEN];
393 uint8_t fup, reg, val;
398 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
399 fup != JME_EEPROM_SIG0)
401 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
402 fup != JME_EEPROM_SIG1)
406 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
408 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
409 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
410 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
412 if (reg >= JME_PAR0 &&
413 reg < JME_PAR0 + ETHER_ADDR_LEN) {
414 if (jme_eeprom_read_byte(sc, offset + 2,
417 eaddr[reg - JME_PAR0] = val;
421 /* Check for the end of EEPROM descriptor. */
422 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
424 /* Try next eeprom descriptor. */
425 offset += JME_EEPROM_DESC_BYTES;
426 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
428 if (match == ETHER_ADDR_LEN) {
429 bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN);
437 jme_reg_macaddr(struct jme_softc *sc)
441 /* Read station address. */
442 par0 = CSR_READ_4(sc, JME_PAR0);
443 par1 = CSR_READ_4(sc, JME_PAR1);
445 if ((par0 == 0 && par1 == 0) ||
446 (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) {
447 device_printf(sc->jme_dev,
448 "generating fake ethernet address.\n");
450 /* Set OUI to JMicron. */
451 sc->jme_eaddr[0] = 0x02; /* U/L bit set. */
452 sc->jme_eaddr[1] = 0x1B;
453 sc->jme_eaddr[2] = 0x8C;
454 sc->jme_eaddr[3] = (par0 >> 16) & 0xff;
455 sc->jme_eaddr[4] = (par0 >> 8) & 0xff;
456 sc->jme_eaddr[5] = par0 & 0xff;
458 sc->jme_eaddr[0] = (par0 >> 0) & 0xFF;
459 sc->jme_eaddr[1] = (par0 >> 8) & 0xFF;
460 sc->jme_eaddr[2] = (par0 >> 16) & 0xFF;
461 sc->jme_eaddr[3] = (par0 >> 24) & 0xFF;
462 sc->jme_eaddr[4] = (par1 >> 0) & 0xFF;
463 sc->jme_eaddr[5] = (par1 >> 8) & 0xFF;
468 jme_map_intr_vector(struct jme_softc *sc)
470 uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES];
472 bzero(map, sizeof(map));
474 /* Map Tx interrupts source to MSI/MSIX vector 2. */
475 map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] =
476 MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP);
477 map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |=
478 MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP);
479 map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |=
480 MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP);
481 map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |=
482 MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP);
483 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
484 MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP);
485 map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |=
486 MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP);
487 map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |=
488 MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP);
489 map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |=
490 MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP);
491 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |=
492 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL);
493 map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |=
494 MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO);
496 /* Map Rx interrupts source to MSI/MSIX vector 1. */
497 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] =
498 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP);
499 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] =
500 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP);
501 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] =
502 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP);
503 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] =
504 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP);
505 map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] =
506 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY);
507 map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] =
508 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY);
509 map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] =
510 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY);
511 map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] =
512 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY);
513 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] =
514 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL);
515 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] =
516 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL);
517 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] =
518 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL);
519 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] =
520 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL);
521 map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] =
522 MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO);
523 map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] =
524 MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO);
525 map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] =
526 MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO);
527 map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] =
528 MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO);
530 /* Map all other interrupts source to MSI/MSIX vector 0. */
531 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]);
532 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]);
533 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]);
534 CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]);
538 jme_attach(device_t dev)
540 struct jme_softc *sc;
542 struct mii_softc *miisc;
543 struct mii_data *mii;
546 int error, i, msic, msixc, pmc;
549 sc = device_get_softc(dev);
552 mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
554 callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0);
555 TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc);
556 TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc);
559 * Map the device. JMC250 supports both memory mapped and I/O
560 * register space access. Because I/O register access should
561 * use different BARs to access registers it's waste of time
562 * to use I/O register spce access. JMC250 uses 16K to map
563 * entire memory space.
565 pci_enable_busmaster(dev);
566 sc->jme_res_spec = jme_res_spec_mem;
567 sc->jme_irq_spec = jme_irq_spec_legacy;
568 error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res);
570 device_printf(dev, "cannot allocate memory resources.\n");
574 /* Allocate IRQ resources. */
575 msixc = pci_msix_count(dev);
576 msic = pci_msi_count(dev);
578 device_printf(dev, "MSIX count : %d\n", msixc);
579 device_printf(dev, "MSI count : %d\n", msic);
582 /* Use 1 MSI/MSI-X. */
587 /* Prefer MSIX over MSI. */
588 if (msix_disable == 0 || msi_disable == 0) {
589 if (msix_disable == 0 && msixc > 0 &&
590 pci_alloc_msix(dev, &msixc) == 0) {
592 device_printf(dev, "Using %d MSIX messages.\n",
594 sc->jme_flags |= JME_FLAG_MSIX;
595 sc->jme_irq_spec = jme_irq_spec_msi;
597 pci_release_msi(dev);
599 if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 &&
600 msic > 0 && pci_alloc_msi(dev, &msic) == 0) {
602 device_printf(dev, "Using %d MSI messages.\n",
604 sc->jme_flags |= JME_FLAG_MSI;
605 sc->jme_irq_spec = jme_irq_spec_msi;
607 pci_release_msi(dev);
609 /* Map interrupt vector 0, 1 and 2. */
610 if ((sc->jme_flags & JME_FLAG_MSI) != 0 ||
611 (sc->jme_flags & JME_FLAG_MSIX) != 0)
612 jme_map_intr_vector(sc);
615 error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq);
617 device_printf(dev, "cannot allocate IRQ resources.\n");
621 sc->jme_rev = pci_get_device(dev);
622 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) {
623 sc->jme_flags |= JME_FLAG_FASTETH;
624 sc->jme_flags |= JME_FLAG_NOJUMBO;
626 reg = CSR_READ_4(sc, JME_CHIPMODE);
627 sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT;
628 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
630 sc->jme_flags |= JME_FLAG_FPGA;
632 device_printf(dev, "PCI device revision : 0x%04x\n",
634 device_printf(dev, "Chip revision : 0x%02x\n",
636 if ((sc->jme_flags & JME_FLAG_FPGA) != 0)
637 device_printf(dev, "FPGA revision : 0x%04x\n",
638 (reg & CHIPMODE_FPGA_REV_MASK) >>
639 CHIPMODE_FPGA_REV_SHIFT);
641 if (sc->jme_chip_rev == 0xFF) {
642 device_printf(dev, "Unknown chip revision : 0x%02x\n",
648 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) {
649 if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 &&
650 CHIPMODE_REVFM(sc->jme_chip_rev) == 2)
651 sc->jme_flags |= JME_FLAG_DMA32BIT;
652 sc->jme_flags |= JME_FLAG_TXCLK;
653 sc->jme_flags |= JME_FLAG_HWMIB;
656 /* Reset the ethernet controller. */
659 /* Get station address. */
660 reg = CSR_READ_4(sc, JME_SMBCSR);
661 if ((reg & SMBCSR_EEPROM_PRESENT) != 0)
662 error = jme_eeprom_macaddr(sc);
663 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
664 if (error != 0 && (bootverbose))
665 device_printf(sc->jme_dev,
666 "ethernet hardware address not found in EEPROM.\n");
672 * Integrated JR0211 has fixed PHY address whereas FPGA version
673 * requires PHY probing to get correct PHY address.
675 if ((sc->jme_flags & JME_FLAG_FPGA) == 0) {
676 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
677 GPREG0_PHY_ADDR_MASK;
679 device_printf(dev, "PHY is at address %d.\n",
684 /* Set max allowable DMA size. */
685 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) {
686 sc->jme_flags |= JME_FLAG_PCIE;
687 burst = pci_read_config(dev, i + 0x08, 2);
689 device_printf(dev, "Read request size : %d bytes.\n",
690 128 << ((burst >> 12) & 0x07));
691 device_printf(dev, "TLP payload size : %d bytes.\n",
692 128 << ((burst >> 5) & 0x07));
694 switch ((burst >> 12) & 0x07) {
696 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
699 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
702 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
705 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
707 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
708 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
710 /* Create coalescing sysctl node. */
712 if ((error = jme_dma_alloc(sc) != 0))
715 ifp = sc->jme_ifp = if_alloc(IFT_ETHER);
717 device_printf(dev, "cannot allocate ifnet structure.\n");
723 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
724 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
725 ifp->if_ioctl = jme_ioctl;
726 ifp->if_start = jme_start;
727 ifp->if_init = jme_init;
728 ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1;
729 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
730 IFQ_SET_READY(&ifp->if_snd);
731 /* JMC250 supports Tx/Rx checksum offload as well as TSO. */
732 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
733 ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO;
734 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) {
735 sc->jme_flags |= JME_FLAG_PMCAP;
736 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
738 ifp->if_capenable = ifp->if_capabilities;
740 /* Set up MII bus. */
741 error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange,
742 jme_mediastatus, BMSR_DEFCAPMASK, sc->jme_phyaddr, MII_OFFSET_ANY,
745 device_printf(dev, "attaching PHYs failed\n");
750 * Force PHY to FPGA mode.
752 if ((sc->jme_flags & JME_FLAG_FPGA) != 0) {
753 mii = device_get_softc(sc->jme_miibus);
754 if (mii->mii_instance != 0) {
755 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
756 if (miisc->mii_phy != 0) {
757 sc->jme_phyaddr = miisc->mii_phy;
761 if (sc->jme_phyaddr != 0) {
762 device_printf(sc->jme_dev,
763 "FPGA PHY is at %d\n", sc->jme_phyaddr);
765 jme_miibus_writereg(dev, sc->jme_phyaddr, 27,
771 ether_ifattach(ifp, sc->jme_eaddr);
773 /* VLAN capability setup */
774 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
775 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
776 ifp->if_capenable = ifp->if_capabilities;
778 /* Tell the upper layer(s) we support long frames. */
779 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
781 /* Create local taskq. */
782 TASK_INIT(&sc->jme_tx_task, 1, jme_tx_task, ifp);
783 sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK,
784 taskqueue_thread_enqueue, &sc->jme_tq);
785 if (sc->jme_tq == NULL) {
786 device_printf(dev, "could not create taskqueue.\n");
791 taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq",
792 device_get_nameunit(sc->jme_dev));
794 for (i = 0; i < 1; i++) {
795 error = bus_setup_intr(dev, sc->jme_irq[i],
796 INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc,
797 &sc->jme_intrhand[i]);
803 device_printf(dev, "could not set up interrupt handler.\n");
804 taskqueue_free(sc->jme_tq);
818 jme_detach(device_t dev)
820 struct jme_softc *sc;
824 sc = device_get_softc(dev);
827 if (device_is_attached(dev)) {
829 sc->jme_flags |= JME_FLAG_DETACH;
832 callout_drain(&sc->jme_tick_ch);
833 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
834 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
835 taskqueue_drain(taskqueue_swi, &sc->jme_link_task);
839 if (sc->jme_tq != NULL) {
840 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
841 taskqueue_free(sc->jme_tq);
845 if (sc->jme_miibus != NULL) {
846 device_delete_child(dev, sc->jme_miibus);
847 sc->jme_miibus = NULL;
849 bus_generic_detach(dev);
857 for (i = 0; i < 1; i++) {
858 if (sc->jme_intrhand[i] != NULL) {
859 bus_teardown_intr(dev, sc->jme_irq[i],
860 sc->jme_intrhand[i]);
861 sc->jme_intrhand[i] = NULL;
865 bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq);
866 if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0)
867 pci_release_msi(dev);
868 bus_release_resources(dev, sc->jme_res_spec, sc->jme_res);
869 mtx_destroy(&sc->jme_mtx);
874 #define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \
875 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
878 jme_sysctl_node(struct jme_softc *sc)
880 struct sysctl_ctx_list *ctx;
881 struct sysctl_oid_list *child, *parent;
882 struct sysctl_oid *tree;
883 struct jme_hw_stats *stats;
886 stats = &sc->jme_stats;
887 ctx = device_get_sysctl_ctx(sc->jme_dev);
888 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev));
890 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to",
891 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0,
892 sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout");
894 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt",
895 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0,
896 sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet");
898 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to",
899 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0,
900 sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout");
902 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt",
903 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0,
904 sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet");
906 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
907 CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0,
908 sysctl_hw_jme_proc_limit, "I",
909 "max number of Rx events to process");
911 /* Pull in device tunables. */
912 sc->jme_process_limit = JME_PROC_DEFAULT;
913 error = resource_int_value(device_get_name(sc->jme_dev),
914 device_get_unit(sc->jme_dev), "process_limit",
915 &sc->jme_process_limit);
917 if (sc->jme_process_limit < JME_PROC_MIN ||
918 sc->jme_process_limit > JME_PROC_MAX) {
919 device_printf(sc->jme_dev,
920 "process_limit value out of range; "
921 "using default: %d\n", JME_PROC_DEFAULT);
922 sc->jme_process_limit = JME_PROC_DEFAULT;
926 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
927 error = resource_int_value(device_get_name(sc->jme_dev),
928 device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to);
930 if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN ||
931 sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) {
932 device_printf(sc->jme_dev,
933 "tx_coal_to value out of range; "
934 "using default: %d\n", PCCTX_COAL_TO_DEFAULT);
935 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
939 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
940 error = resource_int_value(device_get_name(sc->jme_dev),
941 device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to);
943 if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN ||
944 sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) {
945 device_printf(sc->jme_dev,
946 "tx_coal_pkt value out of range; "
947 "using default: %d\n", PCCTX_COAL_PKT_DEFAULT);
948 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
952 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
953 error = resource_int_value(device_get_name(sc->jme_dev),
954 device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to);
956 if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN ||
957 sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) {
958 device_printf(sc->jme_dev,
959 "rx_coal_to value out of range; "
960 "using default: %d\n", PCCRX_COAL_TO_DEFAULT);
961 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
965 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
966 error = resource_int_value(device_get_name(sc->jme_dev),
967 device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to);
969 if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN ||
970 sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) {
971 device_printf(sc->jme_dev,
972 "tx_coal_pkt value out of range; "
973 "using default: %d\n", PCCRX_COAL_PKT_DEFAULT);
974 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
978 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
981 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
982 NULL, "JME statistics");
983 parent = SYSCTL_CHILDREN(tree);
986 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
987 NULL, "Rx MAC statistics");
988 child = SYSCTL_CHILDREN(tree);
989 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
990 &stats->rx_good_frames, "Good frames");
991 JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
992 &stats->rx_crc_errs, "CRC errors");
993 JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs",
994 &stats->rx_mii_errs, "MII errors");
995 JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
996 &stats->rx_fifo_oflows, "FIFO overflows");
997 JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty",
998 &stats->rx_desc_empty, "Descriptor empty");
999 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1000 &stats->rx_bad_frames, "Bad frames");
1002 /* Tx statistics. */
1003 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
1004 NULL, "Tx MAC statistics");
1005 child = SYSCTL_CHILDREN(tree);
1006 JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
1007 &stats->tx_good_frames, "Good frames");
1008 JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames",
1009 &stats->tx_bad_frames, "Bad frames");
1012 #undef JME_SYSCTL_STAT_ADD32
1014 struct jme_dmamap_arg {
1015 bus_addr_t jme_busaddr;
1019 jme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1021 struct jme_dmamap_arg *ctx;
1026 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1028 ctx = (struct jme_dmamap_arg *)arg;
1029 ctx->jme_busaddr = segs[0].ds_addr;
1033 jme_dma_alloc(struct jme_softc *sc)
1035 struct jme_dmamap_arg ctx;
1036 struct jme_txdesc *txd;
1037 struct jme_rxdesc *rxd;
1038 bus_addr_t lowaddr, rx_ring_end, tx_ring_end;
1041 lowaddr = BUS_SPACE_MAXADDR;
1042 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1043 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1046 /* Create parent ring tag. */
1047 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1048 1, 0, /* algnmnt, boundary */
1049 lowaddr, /* lowaddr */
1050 BUS_SPACE_MAXADDR, /* highaddr */
1051 NULL, NULL, /* filter, filterarg */
1052 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1054 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1056 NULL, NULL, /* lockfunc, lockarg */
1057 &sc->jme_cdata.jme_ring_tag);
1059 device_printf(sc->jme_dev,
1060 "could not create parent ring DMA tag.\n");
1063 /* Create tag for Tx ring. */
1064 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1065 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */
1066 BUS_SPACE_MAXADDR, /* lowaddr */
1067 BUS_SPACE_MAXADDR, /* highaddr */
1068 NULL, NULL, /* filter, filterarg */
1069 JME_TX_RING_SIZE, /* maxsize */
1071 JME_TX_RING_SIZE, /* maxsegsize */
1073 NULL, NULL, /* lockfunc, lockarg */
1074 &sc->jme_cdata.jme_tx_ring_tag);
1076 device_printf(sc->jme_dev,
1077 "could not allocate Tx ring DMA tag.\n");
1081 /* Create tag for Rx ring. */
1082 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1083 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */
1084 lowaddr, /* lowaddr */
1085 BUS_SPACE_MAXADDR, /* highaddr */
1086 NULL, NULL, /* filter, filterarg */
1087 JME_RX_RING_SIZE, /* maxsize */
1089 JME_RX_RING_SIZE, /* maxsegsize */
1091 NULL, NULL, /* lockfunc, lockarg */
1092 &sc->jme_cdata.jme_rx_ring_tag);
1094 device_printf(sc->jme_dev,
1095 "could not allocate Rx ring DMA tag.\n");
1099 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1100 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
1101 (void **)&sc->jme_rdata.jme_tx_ring,
1102 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1103 &sc->jme_cdata.jme_tx_ring_map);
1105 device_printf(sc->jme_dev,
1106 "could not allocate DMA'able memory for Tx ring.\n");
1110 ctx.jme_busaddr = 0;
1111 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
1112 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
1113 JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1114 if (error != 0 || ctx.jme_busaddr == 0) {
1115 device_printf(sc->jme_dev,
1116 "could not load DMA'able memory for Tx ring.\n");
1119 sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr;
1121 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1122 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1123 (void **)&sc->jme_rdata.jme_rx_ring,
1124 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1125 &sc->jme_cdata.jme_rx_ring_map);
1127 device_printf(sc->jme_dev,
1128 "could not allocate DMA'able memory for Rx ring.\n");
1132 ctx.jme_busaddr = 0;
1133 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1134 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1135 JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1136 if (error != 0 || ctx.jme_busaddr == 0) {
1137 device_printf(sc->jme_dev,
1138 "could not load DMA'able memory for Rx ring.\n");
1141 sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr;
1143 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1144 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
1145 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
1147 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
1149 if ((JME_ADDR_HI(tx_ring_end) !=
1150 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1151 (JME_ADDR_HI(rx_ring_end) !=
1152 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1153 device_printf(sc->jme_dev, "4GB boundary crossed, "
1154 "switching to 32bit DMA address mode.\n");
1156 /* Limit DMA address space to 32bit and try again. */
1157 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1162 lowaddr = BUS_SPACE_MAXADDR;
1163 if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0)
1164 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1165 /* Create parent buffer tag. */
1166 error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */
1167 1, 0, /* algnmnt, boundary */
1168 lowaddr, /* lowaddr */
1169 BUS_SPACE_MAXADDR, /* highaddr */
1170 NULL, NULL, /* filter, filterarg */
1171 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1173 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1175 NULL, NULL, /* lockfunc, lockarg */
1176 &sc->jme_cdata.jme_buffer_tag);
1178 device_printf(sc->jme_dev,
1179 "could not create parent buffer DMA tag.\n");
1183 /* Create shadow status block tag. */
1184 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1185 JME_SSB_ALIGN, 0, /* algnmnt, boundary */
1186 BUS_SPACE_MAXADDR, /* lowaddr */
1187 BUS_SPACE_MAXADDR, /* highaddr */
1188 NULL, NULL, /* filter, filterarg */
1189 JME_SSB_SIZE, /* maxsize */
1191 JME_SSB_SIZE, /* maxsegsize */
1193 NULL, NULL, /* lockfunc, lockarg */
1194 &sc->jme_cdata.jme_ssb_tag);
1196 device_printf(sc->jme_dev,
1197 "could not create shared status block DMA tag.\n");
1201 /* Create tag for Tx buffers. */
1202 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1203 1, 0, /* algnmnt, boundary */
1204 BUS_SPACE_MAXADDR, /* lowaddr */
1205 BUS_SPACE_MAXADDR, /* highaddr */
1206 NULL, NULL, /* filter, filterarg */
1207 JME_TSO_MAXSIZE, /* maxsize */
1208 JME_MAXTXSEGS, /* nsegments */
1209 JME_TSO_MAXSEGSIZE, /* maxsegsize */
1211 NULL, NULL, /* lockfunc, lockarg */
1212 &sc->jme_cdata.jme_tx_tag);
1214 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1218 /* Create tag for Rx buffers. */
1219 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1220 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
1221 BUS_SPACE_MAXADDR, /* lowaddr */
1222 BUS_SPACE_MAXADDR, /* highaddr */
1223 NULL, NULL, /* filter, filterarg */
1224 MCLBYTES, /* maxsize */
1226 MCLBYTES, /* maxsegsize */
1228 NULL, NULL, /* lockfunc, lockarg */
1229 &sc->jme_cdata.jme_rx_tag);
1231 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1236 * Allocate DMA'able memory and load the DMA map for shared
1239 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1240 (void **)&sc->jme_rdata.jme_ssb_block,
1241 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1242 &sc->jme_cdata.jme_ssb_map);
1244 device_printf(sc->jme_dev, "could not allocate DMA'able "
1245 "memory for shared status block.\n");
1249 ctx.jme_busaddr = 0;
1250 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1251 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1252 JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
1253 if (error != 0 || ctx.jme_busaddr == 0) {
1254 device_printf(sc->jme_dev, "could not load DMA'able memory "
1255 "for shared status block.\n");
1258 sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr;
1260 /* Create DMA maps for Tx buffers. */
1261 for (i = 0; i < JME_TX_RING_CNT; i++) {
1262 txd = &sc->jme_cdata.jme_txdesc[i];
1264 txd->tx_dmamap = NULL;
1265 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1268 device_printf(sc->jme_dev,
1269 "could not create Tx dmamap.\n");
1273 /* Create DMA maps for Rx buffers. */
1274 if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1275 &sc->jme_cdata.jme_rx_sparemap)) != 0) {
1276 device_printf(sc->jme_dev,
1277 "could not create spare Rx dmamap.\n");
1280 for (i = 0; i < JME_RX_RING_CNT; i++) {
1281 rxd = &sc->jme_cdata.jme_rxdesc[i];
1283 rxd->rx_dmamap = NULL;
1284 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1287 device_printf(sc->jme_dev,
1288 "could not create Rx dmamap.\n");
1298 jme_dma_free(struct jme_softc *sc)
1300 struct jme_txdesc *txd;
1301 struct jme_rxdesc *rxd;
1305 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1306 if (sc->jme_cdata.jme_tx_ring_map)
1307 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1308 sc->jme_cdata.jme_tx_ring_map);
1309 if (sc->jme_cdata.jme_tx_ring_map &&
1310 sc->jme_rdata.jme_tx_ring)
1311 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1312 sc->jme_rdata.jme_tx_ring,
1313 sc->jme_cdata.jme_tx_ring_map);
1314 sc->jme_rdata.jme_tx_ring = NULL;
1315 sc->jme_cdata.jme_tx_ring_map = NULL;
1316 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1317 sc->jme_cdata.jme_tx_ring_tag = NULL;
1320 if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1321 if (sc->jme_cdata.jme_rx_ring_map)
1322 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1323 sc->jme_cdata.jme_rx_ring_map);
1324 if (sc->jme_cdata.jme_rx_ring_map &&
1325 sc->jme_rdata.jme_rx_ring)
1326 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1327 sc->jme_rdata.jme_rx_ring,
1328 sc->jme_cdata.jme_rx_ring_map);
1329 sc->jme_rdata.jme_rx_ring = NULL;
1330 sc->jme_cdata.jme_rx_ring_map = NULL;
1331 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1332 sc->jme_cdata.jme_rx_ring_tag = NULL;
1335 if (sc->jme_cdata.jme_tx_tag != NULL) {
1336 for (i = 0; i < JME_TX_RING_CNT; i++) {
1337 txd = &sc->jme_cdata.jme_txdesc[i];
1338 if (txd->tx_dmamap != NULL) {
1339 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1341 txd->tx_dmamap = NULL;
1344 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1345 sc->jme_cdata.jme_tx_tag = NULL;
1348 if (sc->jme_cdata.jme_rx_tag != NULL) {
1349 for (i = 0; i < JME_RX_RING_CNT; i++) {
1350 rxd = &sc->jme_cdata.jme_rxdesc[i];
1351 if (rxd->rx_dmamap != NULL) {
1352 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1354 rxd->rx_dmamap = NULL;
1357 if (sc->jme_cdata.jme_rx_sparemap != NULL) {
1358 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1359 sc->jme_cdata.jme_rx_sparemap);
1360 sc->jme_cdata.jme_rx_sparemap = NULL;
1362 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1363 sc->jme_cdata.jme_rx_tag = NULL;
1366 /* Shared status block. */
1367 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1368 if (sc->jme_cdata.jme_ssb_map)
1369 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1370 sc->jme_cdata.jme_ssb_map);
1371 if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block)
1372 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1373 sc->jme_rdata.jme_ssb_block,
1374 sc->jme_cdata.jme_ssb_map);
1375 sc->jme_rdata.jme_ssb_block = NULL;
1376 sc->jme_cdata.jme_ssb_map = NULL;
1377 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1378 sc->jme_cdata.jme_ssb_tag = NULL;
1381 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1382 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1383 sc->jme_cdata.jme_buffer_tag = NULL;
1385 if (sc->jme_cdata.jme_ring_tag != NULL) {
1386 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1387 sc->jme_cdata.jme_ring_tag = NULL;
1392 * Make sure the interface is stopped at reboot time.
1395 jme_shutdown(device_t dev)
1398 return (jme_suspend(dev));
1402 * Unlike other ethernet controllers, JMC250 requires
1403 * explicit resetting link speed to 10/100Mbps as gigabit
1404 * link will cunsume more power than 375mA.
1405 * Note, we reset the link speed to 10/100Mbps with
1406 * auto-negotiation but we don't know whether that operation
1407 * would succeed or not as we have no control after powering
1408 * off. If the renegotiation fail WOL may not work. Running
1409 * at 1Gbps draws more power than 375mA at 3.3V which is
1410 * specified in PCI specification and that would result in
1411 * complete shutdowning power to ethernet controller.
1414 * Save current negotiated media speed/duplex/flow-control
1415 * to softc and restore the same link again after resuming.
1416 * PHY handling such as power down/resetting to 100Mbps
1417 * may be better handled in suspend method in phy driver.
1420 jme_setlinkspeed(struct jme_softc *sc)
1422 struct mii_data *mii;
1425 JME_LOCK_ASSERT(sc);
1427 mii = device_get_softc(sc->jme_miibus);
1430 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1431 switch IFM_SUBTYPE(mii->mii_media_active) {
1441 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1442 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1443 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1444 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1445 BMCR_AUTOEN | BMCR_STARTNEG);
1448 /* Poll link state until jme(4) get a 10/100 link. */
1449 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1451 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1452 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1462 pause("jmelnk", hz);
1465 if (i == MII_ANEGTICKS_GIGE)
1466 device_printf(sc->jme_dev, "establishing link failed, "
1467 "WOL may not work!");
1470 * No link, force MAC to have 100Mbps, full-duplex link.
1471 * This is the last resort and may/may not work.
1473 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1474 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1479 jme_setwol(struct jme_softc *sc)
1486 JME_LOCK_ASSERT(sc);
1488 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1489 /* Remove Tx MAC/offload clock to save more power. */
1490 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1491 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1492 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1493 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1494 /* No PME capability, PHY power down. */
1495 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1496 MII_BMCR, BMCR_PDOWN);
1501 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1502 pmcs = CSR_READ_4(sc, JME_PMCS);
1503 pmcs &= ~PMCS_WOL_ENB_MASK;
1504 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1505 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1506 /* Enable PME message. */
1507 gpr |= GPREG0_PME_ENB;
1508 /* For gigabit controllers, reset link speed to 10/100. */
1509 if ((sc->jme_flags & JME_FLAG_FASTETH) == 0)
1510 jme_setlinkspeed(sc);
1513 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1514 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1515 /* Remove Tx MAC/offload clock to save more power. */
1516 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
1517 CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) &
1518 ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 |
1519 GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000));
1521 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1522 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1523 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1524 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1525 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1526 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1527 /* No WOL, PHY power down. */
1528 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1529 MII_BMCR, BMCR_PDOWN);
1534 jme_suspend(device_t dev)
1536 struct jme_softc *sc;
1538 sc = device_get_softc(dev);
1549 jme_resume(device_t dev)
1551 struct jme_softc *sc;
1556 sc = device_get_softc(dev);
1559 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1560 pmstat = pci_read_config(sc->jme_dev,
1561 pmc + PCIR_POWER_STATUS, 2);
1562 /* Disable PME clear PME status. */
1563 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1564 pci_write_config(sc->jme_dev,
1565 pmc + PCIR_POWER_STATUS, pmstat, 2);
1568 if ((ifp->if_flags & IFF_UP) != 0) {
1569 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1570 jme_init_locked(sc);
1579 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1581 struct jme_txdesc *txd;
1582 struct jme_desc *desc;
1584 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1585 int error, i, nsegs, prod;
1586 uint32_t cflags, tso_segsz;
1588 JME_LOCK_ASSERT(sc);
1590 M_ASSERTPKTHDR((*m_head));
1592 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1594 * Due to the adherence to NDIS specification JMC250
1595 * assumes upper stack computed TCP pseudo checksum
1596 * without including payload length. This breaks
1597 * checksum offload for TSO case so recompute TCP
1598 * pseudo checksum for JMC250. Hopefully this wouldn't
1599 * be much burden on modern CPUs.
1601 struct ether_header *eh;
1604 uint32_t ip_off, poff;
1606 if (M_WRITABLE(*m_head) == 0) {
1607 /* Get a writable copy. */
1608 m = m_dup(*m_head, M_DONTWAIT);
1616 ip_off = sizeof(struct ether_header);
1617 m = m_pullup(*m_head, ip_off);
1622 eh = mtod(m, struct ether_header *);
1623 /* Check the existence of VLAN tag. */
1624 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1625 ip_off = sizeof(struct ether_vlan_header);
1626 m = m_pullup(m, ip_off);
1632 m = m_pullup(m, ip_off + sizeof(struct ip));
1637 ip = (struct ip *)(mtod(m, char *) + ip_off);
1638 poff = ip_off + (ip->ip_hl << 2);
1639 m = m_pullup(m, poff + sizeof(struct tcphdr));
1645 * Reset IP checksum and recompute TCP pseudo
1646 * checksum that NDIS specification requires.
1648 ip = (struct ip *)(mtod(m, char *) + ip_off);
1649 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1651 if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) {
1652 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1654 htons((tcp->th_off << 2) + IPPROTO_TCP));
1655 /* No need to TSO, force IP checksum offload. */
1656 (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO;
1657 (*m_head)->m_pkthdr.csum_flags |= CSUM_IP;
1659 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1660 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1664 prod = sc->jme_cdata.jme_tx_prod;
1665 txd = &sc->jme_cdata.jme_txdesc[prod];
1667 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1668 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1669 if (error == EFBIG) {
1670 m = m_collapse(*m_head, M_DONTWAIT, JME_MAXTXSEGS);
1677 error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag,
1678 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1684 } else if (error != 0)
1693 * Check descriptor overrun. Leave one free descriptor.
1694 * Since we always use 64bit address mode for transmitting,
1695 * each Tx request requires one more dummy descriptor.
1697 if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) {
1698 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1705 /* Configure checksum offload and TSO. */
1706 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1707 tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz <<
1709 cflags |= JME_TD_TSO;
1711 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0)
1712 cflags |= JME_TD_IPCSUM;
1713 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1714 cflags |= JME_TD_TCPCSUM;
1715 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1716 cflags |= JME_TD_UDPCSUM;
1718 /* Configure VLAN. */
1719 if ((m->m_flags & M_VLANTAG) != 0) {
1720 cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK);
1721 cflags |= JME_TD_VLAN_TAG;
1724 desc = &sc->jme_rdata.jme_tx_ring[prod];
1725 desc->flags = htole32(cflags);
1726 desc->buflen = htole32(tso_segsz);
1727 desc->addr_hi = htole32(m->m_pkthdr.len);
1729 sc->jme_cdata.jme_tx_cnt++;
1730 JME_DESC_INC(prod, JME_TX_RING_CNT);
1731 for (i = 0; i < nsegs; i++) {
1732 desc = &sc->jme_rdata.jme_tx_ring[prod];
1733 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1734 desc->buflen = htole32(txsegs[i].ds_len);
1735 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1736 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1737 sc->jme_cdata.jme_tx_cnt++;
1738 JME_DESC_INC(prod, JME_TX_RING_CNT);
1741 /* Update producer index. */
1742 sc->jme_cdata.jme_tx_prod = prod;
1744 * Finally request interrupt and give the first descriptor
1745 * owenership to hardware.
1747 desc = txd->tx_desc;
1748 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1751 txd->tx_ndesc = nsegs + 1;
1753 /* Sync descriptors. */
1754 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1755 BUS_DMASYNC_PREWRITE);
1756 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1757 sc->jme_cdata.jme_tx_ring_map,
1758 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1764 jme_tx_task(void *arg, int pending)
1768 ifp = (struct ifnet *)arg;
1773 jme_start(struct ifnet *ifp)
1775 struct jme_softc *sc;
1776 struct mbuf *m_head;
1783 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT)
1786 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1787 IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) {
1792 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1793 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1797 * Pack the data into the transmit ring. If we
1798 * don't have room, set the OACTIVE flag and wait
1799 * for the NIC to drain the ring.
1801 if (jme_encap(sc, &m_head)) {
1804 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1805 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1811 * If there's a BPF listener, bounce a copy of this frame
1814 ETHER_BPF_MTAP(ifp, m_head);
1819 * Reading TXCSR takes very long time under heavy load
1820 * so cache TXCSR value and writes the ORed value with
1821 * the kick command to the TXCSR. This saves one register
1824 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1825 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1826 /* Set a timeout in case the chip goes out to lunch. */
1827 sc->jme_watchdog_timer = JME_TX_TIMEOUT;
1834 jme_watchdog(struct jme_softc *sc)
1838 JME_LOCK_ASSERT(sc);
1840 if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer)
1844 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1845 if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n");
1847 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1848 jme_init_locked(sc);
1852 if (sc->jme_cdata.jme_tx_cnt == 0) {
1853 if_printf(sc->jme_ifp,
1854 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1855 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1856 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1860 if_printf(sc->jme_ifp, "watchdog timeout\n");
1862 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1863 jme_init_locked(sc);
1864 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1865 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
1869 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1871 struct jme_softc *sc;
1873 struct mii_data *mii;
1878 ifr = (struct ifreq *)data;
1882 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1883 ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 &&
1884 ifr->ifr_mtu > JME_MAX_MTU)) {
1889 if (ifp->if_mtu != ifr->ifr_mtu) {
1891 * No special configuration is required when interface
1892 * MTU is changed but availability of TSO/Tx checksum
1893 * offload should be chcked against new MTU size as
1894 * FIFO size is just 2K.
1897 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1898 ifp->if_capenable &=
1899 ~(IFCAP_TXCSUM | IFCAP_TSO4);
1901 ~(JME_CSUM_FEATURES | CSUM_TSO);
1902 VLAN_CAPABILITIES(ifp);
1904 ifp->if_mtu = ifr->ifr_mtu;
1905 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1906 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1907 jme_init_locked(sc);
1914 if ((ifp->if_flags & IFF_UP) != 0) {
1915 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1916 if (((ifp->if_flags ^ sc->jme_if_flags)
1917 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1920 if ((sc->jme_flags & JME_FLAG_DETACH) == 0)
1921 jme_init_locked(sc);
1924 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1927 sc->jme_if_flags = ifp->if_flags;
1933 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1939 mii = device_get_softc(sc->jme_miibus);
1940 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1944 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1945 if ((mask & IFCAP_TXCSUM) != 0 &&
1946 ifp->if_mtu < JME_TX_FIFO_SIZE) {
1947 if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1948 ifp->if_capenable ^= IFCAP_TXCSUM;
1949 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
1950 ifp->if_hwassist |= JME_CSUM_FEATURES;
1952 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1955 if ((mask & IFCAP_RXCSUM) != 0 &&
1956 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
1957 ifp->if_capenable ^= IFCAP_RXCSUM;
1958 reg = CSR_READ_4(sc, JME_RXMAC);
1959 reg &= ~RXMAC_CSUM_ENB;
1960 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1961 reg |= RXMAC_CSUM_ENB;
1962 CSR_WRITE_4(sc, JME_RXMAC, reg);
1964 if ((mask & IFCAP_TSO4) != 0 &&
1965 ifp->if_mtu < JME_TX_FIFO_SIZE) {
1966 if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) {
1967 ifp->if_capenable ^= IFCAP_TSO4;
1968 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
1969 ifp->if_hwassist |= CSUM_TSO;
1971 ifp->if_hwassist &= ~CSUM_TSO;
1974 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1975 (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0)
1976 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1977 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1978 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1979 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1980 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1981 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1982 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1983 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1984 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
1985 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1989 VLAN_CAPABILITIES(ifp);
1992 error = ether_ioctl(ifp, cmd, data);
2000 jme_mac_config(struct jme_softc *sc)
2002 struct mii_data *mii;
2003 uint32_t ghc, gpreg, rxmac, txmac, txpause;
2006 JME_LOCK_ASSERT(sc);
2008 mii = device_get_softc(sc->jme_miibus);
2010 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2012 CSR_WRITE_4(sc, JME_GHC, 0);
2015 rxmac = CSR_READ_4(sc, JME_RXMAC);
2016 rxmac &= ~RXMAC_FC_ENB;
2017 txmac = CSR_READ_4(sc, JME_TXMAC);
2018 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
2019 txpause = CSR_READ_4(sc, JME_TXPFC);
2020 txpause &= ~TXPFC_PAUSE_ENB;
2021 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2022 ghc |= GHC_FULL_DUPLEX;
2023 rxmac &= ~RXMAC_COLL_DET_ENB;
2024 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
2025 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
2027 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2028 txpause |= TXPFC_PAUSE_ENB;
2029 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2030 rxmac |= RXMAC_FC_ENB;
2031 /* Disable retry transmit timer/retry limit. */
2032 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
2033 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
2035 rxmac |= RXMAC_COLL_DET_ENB;
2036 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
2037 /* Enable retry transmit timer/retry limit. */
2038 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
2039 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
2041 /* Reprogram Tx/Rx MACs with resolved speed/duplex. */
2042 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2044 ghc |= GHC_SPEED_10;
2045 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2048 ghc |= GHC_SPEED_100;
2049 txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100;
2052 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2054 ghc |= GHC_SPEED_1000;
2055 txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000;
2056 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
2057 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
2062 if (sc->jme_rev == DEVICEID_JMC250 &&
2063 sc->jme_chip_rev == DEVICEREVID_JMC250_A2) {
2065 * Workaround occasional packet loss issue of JMC250 A2
2066 * when it runs on half-duplex media.
2068 gpreg = CSR_READ_4(sc, JME_GPREG1);
2069 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
2070 gpreg &= ~GPREG1_HDPX_FIX;
2072 gpreg |= GPREG1_HDPX_FIX;
2073 CSR_WRITE_4(sc, JME_GPREG1, gpreg);
2074 /* Workaround CRC errors at 100Mbps on JMC250 A2. */
2075 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
2076 /* Extend interface FIFO depth. */
2077 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2080 /* Select default interface FIFO depth. */
2081 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2085 if ((sc->jme_flags & JME_FLAG_TXCLK) != 0)
2087 CSR_WRITE_4(sc, JME_GHC, ghc);
2088 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
2089 CSR_WRITE_4(sc, JME_TXMAC, txmac);
2090 CSR_WRITE_4(sc, JME_TXPFC, txpause);
2094 jme_link_task(void *arg, int pending)
2096 struct jme_softc *sc;
2097 struct mii_data *mii;
2099 struct jme_txdesc *txd;
2103 sc = (struct jme_softc *)arg;
2106 mii = device_get_softc(sc->jme_miibus);
2108 if (mii == NULL || ifp == NULL ||
2109 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2114 sc->jme_flags &= ~JME_FLAG_LINK;
2115 if ((mii->mii_media_status & IFM_AVALID) != 0) {
2116 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2119 sc->jme_flags |= JME_FLAG_LINK;
2122 if ((sc->jme_flags & JME_FLAG_FASTETH) != 0)
2124 sc->jme_flags |= JME_FLAG_LINK;
2132 * Disabling Rx/Tx MACs have a side-effect of resetting
2133 * JME_TXNDA/JME_RXNDA register to the first address of
2134 * Tx/Rx descriptor address. So driver should reset its
2135 * internal procucer/consumer pointer and reclaim any
2136 * allocated resources. Note, just saving the value of
2137 * JME_TXNDA and JME_RXNDA registers before stopping MAC
2138 * and restoring JME_TXNDA/JME_RXNDA register is not
2139 * sufficient to make sure correct MAC state because
2140 * stopping MAC operation can take a while and hardware
2141 * might have updated JME_TXNDA/JME_RXNDA registers
2142 * during the stop operation.
2144 /* Block execution of task. */
2145 taskqueue_block(sc->jme_tq);
2146 /* Disable interrupts and stop driver. */
2147 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2148 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2149 callout_stop(&sc->jme_tick_ch);
2150 sc->jme_watchdog_timer = 0;
2152 /* Stop receiver/transmitter. */
2156 /* XXX Drain all queued tasks. */
2158 taskqueue_drain(sc->jme_tq, &sc->jme_int_task);
2159 taskqueue_drain(sc->jme_tq, &sc->jme_tx_task);
2162 jme_rxintr(sc, JME_RX_RING_CNT);
2163 if (sc->jme_cdata.jme_rxhead != NULL)
2164 m_freem(sc->jme_cdata.jme_rxhead);
2165 JME_RXCHAIN_RESET(sc);
2167 if (sc->jme_cdata.jme_tx_cnt != 0) {
2168 /* Remove queued packets for transmit. */
2169 for (i = 0; i < JME_TX_RING_CNT; i++) {
2170 txd = &sc->jme_cdata.jme_txdesc[i];
2171 if (txd->tx_m != NULL) {
2173 sc->jme_cdata.jme_tx_tag,
2175 BUS_DMASYNC_POSTWRITE);
2177 sc->jme_cdata.jme_tx_tag,
2188 * Reuse configured Rx descriptors and reset
2189 * procuder/consumer index.
2191 sc->jme_cdata.jme_rx_cons = 0;
2192 atomic_set_int(&sc->jme_morework, 0);
2193 jme_init_tx_ring(sc);
2194 /* Initialize shadow status block. */
2197 /* Program MAC with resolved speed/duplex/flow-control. */
2198 if ((sc->jme_flags & JME_FLAG_LINK) != 0) {
2200 jme_stats_clear(sc);
2202 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2203 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2205 /* Set Tx ring address to the hardware. */
2206 paddr = JME_TX_RING_ADDR(sc, 0);
2207 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2208 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2210 /* Set Rx ring address to the hardware. */
2211 paddr = JME_RX_RING_ADDR(sc, 0);
2212 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2213 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2215 /* Restart receiver/transmitter. */
2216 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
2218 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
2221 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2222 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2223 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2224 /* Unblock execution of task. */
2225 taskqueue_unblock(sc->jme_tq);
2226 /* Reenable interrupts. */
2227 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2235 struct jme_softc *sc;
2238 sc = (struct jme_softc *)arg;
2240 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2241 if (status == 0 || status == 0xFFFFFFFF)
2242 return (FILTER_STRAY);
2243 /* Disable interrupts. */
2244 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2245 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2247 return (FILTER_HANDLED);
2251 jme_int_task(void *arg, int pending)
2253 struct jme_softc *sc;
2258 sc = (struct jme_softc *)arg;
2261 status = CSR_READ_4(sc, JME_INTR_STATUS);
2262 more = atomic_readandclear_int(&sc->jme_morework);
2264 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO;
2267 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2269 /* Reset PCC counter/timer and Ack interrupts. */
2270 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2271 if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0)
2272 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2273 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0)
2274 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
2275 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2277 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2278 if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) {
2279 more = jme_rxintr(sc, sc->jme_process_limit);
2281 atomic_set_int(&sc->jme_morework, 1);
2283 if ((status & INTR_RXQ_DESC_EMPTY) != 0) {
2285 * Notify hardware availability of new Rx
2287 * Reading RXCSR takes very long time under
2288 * heavy load so cache RXCSR value and writes
2289 * the ORed value with the kick command to
2290 * the RXCSR. This saves one register access
2293 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2294 RXCSR_RX_ENB | RXCSR_RXQ_START);
2297 * Reclaiming Tx buffers are deferred to make jme(4) run
2298 * without locks held.
2300 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2301 taskqueue_enqueue(sc->jme_tq, &sc->jme_tx_task);
2304 if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) {
2305 taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task);
2309 /* Reenable interrupts. */
2310 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2314 jme_txeof(struct jme_softc *sc)
2317 struct jme_txdesc *txd;
2321 JME_LOCK_ASSERT(sc);
2325 cons = sc->jme_cdata.jme_tx_cons;
2326 if (cons == sc->jme_cdata.jme_tx_prod)
2329 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2330 sc->jme_cdata.jme_tx_ring_map,
2331 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2334 * Go through our Tx list and free mbufs for those
2335 * frames which have been transmitted.
2337 for (; cons != sc->jme_cdata.jme_tx_prod;) {
2338 txd = &sc->jme_cdata.jme_txdesc[cons];
2339 status = le32toh(txd->tx_desc->flags);
2340 if ((status & JME_TD_OWN) == JME_TD_OWN)
2343 if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0)
2347 if ((status & JME_TD_COLLISION) != 0)
2348 ifp->if_collisions +=
2349 le32toh(txd->tx_desc->buflen) &
2350 JME_TD_BUF_LEN_MASK;
2353 * Only the first descriptor of multi-descriptor
2354 * transmission is updated so driver have to skip entire
2355 * chained buffers for the transmiited frame. In other
2356 * words, JME_TD_OWN bit is valid only at the first
2357 * descriptor of a multi-descriptor transmission.
2359 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2360 sc->jme_rdata.jme_tx_ring[cons].flags = 0;
2361 JME_DESC_INC(cons, JME_TX_RING_CNT);
2364 /* Reclaim transferred mbufs. */
2365 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
2366 BUS_DMASYNC_POSTWRITE);
2367 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2369 KASSERT(txd->tx_m != NULL,
2370 ("%s: freeing NULL mbuf!\n", __func__));
2373 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2374 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2375 ("%s: Active Tx desc counter was garbled\n", __func__));
2377 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2379 sc->jme_cdata.jme_tx_cons = cons;
2380 /* Unarm watchog timer when there is no pending descriptors in queue. */
2381 if (sc->jme_cdata.jme_tx_cnt == 0)
2382 sc->jme_watchdog_timer = 0;
2384 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2385 sc->jme_cdata.jme_tx_ring_map,
2386 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2389 static __inline void
2390 jme_discard_rxbuf(struct jme_softc *sc, int cons)
2392 struct jme_desc *desc;
2394 desc = &sc->jme_rdata.jme_rx_ring[cons];
2395 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2396 desc->buflen = htole32(MCLBYTES);
2399 /* Receive a frame. */
2401 jme_rxeof(struct jme_softc *sc)
2404 struct jme_desc *desc;
2405 struct jme_rxdesc *rxd;
2406 struct mbuf *mp, *m;
2407 uint32_t flags, status;
2408 int cons, count, nsegs;
2412 cons = sc->jme_cdata.jme_rx_cons;
2413 desc = &sc->jme_rdata.jme_rx_ring[cons];
2414 flags = le32toh(desc->flags);
2415 status = le32toh(desc->buflen);
2416 nsegs = JME_RX_NSEGS(status);
2417 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2418 if ((status & JME_RX_ERR_STAT) != 0) {
2420 jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons);
2421 #ifdef JME_SHOW_ERRORS
2422 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2423 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2425 sc->jme_cdata.jme_rx_cons += nsegs;
2426 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2430 for (count = 0; count < nsegs; count++,
2431 JME_DESC_INC(cons, JME_RX_RING_CNT)) {
2432 rxd = &sc->jme_cdata.jme_rxdesc[cons];
2434 /* Add a new receive buffer to the ring. */
2435 if (jme_newbuf(sc, rxd) != 0) {
2438 for (; count < nsegs; count++) {
2439 jme_discard_rxbuf(sc, cons);
2440 JME_DESC_INC(cons, JME_RX_RING_CNT);
2442 if (sc->jme_cdata.jme_rxhead != NULL) {
2443 m_freem(sc->jme_cdata.jme_rxhead);
2444 JME_RXCHAIN_RESET(sc);
2450 * Assume we've received a full sized frame.
2451 * Actual size is fixed when we encounter the end of
2452 * multi-segmented frame.
2454 mp->m_len = MCLBYTES;
2456 /* Chain received mbufs. */
2457 if (sc->jme_cdata.jme_rxhead == NULL) {
2458 sc->jme_cdata.jme_rxhead = mp;
2459 sc->jme_cdata.jme_rxtail = mp;
2462 * Receive processor can receive a maximum frame
2463 * size of 65535 bytes.
2465 mp->m_flags &= ~M_PKTHDR;
2466 sc->jme_cdata.jme_rxtail->m_next = mp;
2467 sc->jme_cdata.jme_rxtail = mp;
2470 if (count == nsegs - 1) {
2471 /* Last desc. for this frame. */
2472 m = sc->jme_cdata.jme_rxhead;
2473 m->m_flags |= M_PKTHDR;
2474 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2476 /* Set first mbuf size. */
2477 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2478 /* Set last mbuf size. */
2479 mp->m_len = sc->jme_cdata.jme_rxlen -
2480 ((MCLBYTES - JME_RX_PAD_BYTES) +
2481 (MCLBYTES * (nsegs - 2)));
2483 m->m_len = sc->jme_cdata.jme_rxlen;
2484 m->m_pkthdr.rcvif = ifp;
2487 * Account for 10bytes auto padding which is used
2488 * to align IP header on 32bit boundary. Also note,
2489 * CRC bytes is automatically removed by the
2492 m->m_data += JME_RX_PAD_BYTES;
2494 /* Set checksum information. */
2495 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2496 (flags & JME_RD_IPV4) != 0) {
2497 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2498 if ((flags & JME_RD_IPCSUM) != 0)
2499 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2500 if (((flags & JME_RD_MORE_FRAG) == 0) &&
2501 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2502 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2503 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2504 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2505 m->m_pkthdr.csum_flags |=
2506 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2507 m->m_pkthdr.csum_data = 0xffff;
2511 /* Check for VLAN tagged packets. */
2512 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2513 (flags & JME_RD_VLAN_TAG) != 0) {
2514 m->m_pkthdr.ether_vtag =
2515 flags & JME_RD_VLAN_MASK;
2516 m->m_flags |= M_VLANTAG;
2521 (*ifp->if_input)(ifp, m);
2523 /* Reset mbuf chains. */
2524 JME_RXCHAIN_RESET(sc);
2528 sc->jme_cdata.jme_rx_cons += nsegs;
2529 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2533 jme_rxintr(struct jme_softc *sc, int count)
2535 struct jme_desc *desc;
2536 int nsegs, prog, pktlen;
2538 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2539 sc->jme_cdata.jme_rx_ring_map,
2540 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2542 for (prog = 0; count > 0; prog++) {
2543 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2544 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2546 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2548 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2550 * Check number of segments against received bytes.
2551 * Non-matching value would indicate that hardware
2552 * is still trying to update Rx descriptors. I'm not
2553 * sure whether this check is needed.
2555 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2556 if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES))
2559 /* Received a frame. */
2565 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2566 sc->jme_cdata.jme_rx_ring_map,
2567 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2569 return (count > 0 ? 0 : EAGAIN);
2575 struct jme_softc *sc;
2576 struct mii_data *mii;
2578 sc = (struct jme_softc *)arg;
2580 JME_LOCK_ASSERT(sc);
2582 mii = device_get_softc(sc->jme_miibus);
2585 * Reclaim Tx buffers that have been completed. It's not
2586 * needed here but it would release allocated mbuf chains
2587 * faster and limit the maximum delay to a hz.
2590 jme_stats_update(sc);
2592 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2596 jme_reset(struct jme_softc *sc)
2599 /* Stop receiver, transmitter. */
2602 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2604 CSR_WRITE_4(sc, JME_GHC, 0);
2610 struct jme_softc *sc;
2612 sc = (struct jme_softc *)xsc;
2614 jme_init_locked(sc);
2619 jme_init_locked(struct jme_softc *sc)
2622 struct mii_data *mii;
2623 uint8_t eaddr[ETHER_ADDR_LEN];
2628 JME_LOCK_ASSERT(sc);
2631 mii = device_get_softc(sc->jme_miibus);
2633 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2636 * Cancel any pending I/O.
2641 * Reset the chip to a known state.
2645 /* Init descriptors. */
2646 error = jme_init_rx_ring(sc);
2648 device_printf(sc->jme_dev,
2649 "%s: initialization failed: no memory for Rx buffers.\n",
2654 jme_init_tx_ring(sc);
2655 /* Initialize shadow status block. */
2658 /* Reprogram the station address. */
2659 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2660 CSR_WRITE_4(sc, JME_PAR0,
2661 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2662 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2665 * Configure Tx queue.
2666 * Tx priority queue weight value : 0
2667 * Tx FIFO threshold for processing next packet : 16QW
2668 * Maximum Tx DMA length : 512
2669 * Allow Tx DMA burst.
2671 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2672 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2673 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2674 sc->jme_txcsr |= sc->jme_tx_dma_size;
2675 sc->jme_txcsr |= TXCSR_DMA_BURST;
2676 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2678 /* Set Tx descriptor counter. */
2679 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT);
2681 /* Set Tx ring address to the hardware. */
2682 paddr = JME_TX_RING_ADDR(sc, 0);
2683 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2684 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2686 /* Configure TxMAC parameters. */
2687 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2688 reg |= TXMAC_THRESH_1_PKT;
2689 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2690 CSR_WRITE_4(sc, JME_TXMAC, reg);
2693 * Configure Rx queue.
2694 * FIFO full threshold for transmitting Tx pause packet : 128T
2695 * FIFO threshold for processing next packet : 128QW
2697 * Max Rx DMA length : 128
2698 * Rx descriptor retry : 32
2699 * Rx descriptor retry time gap : 256ns
2700 * Don't receive runt/bad frame.
2702 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2704 * Since Rx FIFO size is 4K bytes, receiving frames larger
2705 * than 4K bytes will suffer from Rx FIFO overruns. So
2706 * decrease FIFO threshold to reduce the FIFO overruns for
2707 * frames larger than 4000 bytes.
2708 * For best performance of standard MTU sized frames use
2709 * maximum allowable FIFO threshold, 128QW. Note these do
2710 * not hold on chip full mask verion >=2. For these
2711 * controllers 64QW and 128QW are not valid value.
2713 if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2)
2714 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2716 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2717 ETHER_CRC_LEN) > JME_RX_FIFO_SIZE)
2718 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2720 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2722 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2723 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2724 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2725 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2727 /* Set Rx descriptor counter. */
2728 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT);
2730 /* Set Rx ring address to the hardware. */
2731 paddr = JME_RX_RING_ADDR(sc, 0);
2732 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2733 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2735 /* Clear receive filter. */
2736 CSR_WRITE_4(sc, JME_RXMAC, 0);
2737 /* Set up the receive filter. */
2742 * Disable all WOL bits as WOL can interfere normal Rx
2743 * operation. Also clear WOL detection status bits.
2745 reg = CSR_READ_4(sc, JME_PMCS);
2746 reg &= ~PMCS_WOL_ENB_MASK;
2747 CSR_WRITE_4(sc, JME_PMCS, reg);
2749 reg = CSR_READ_4(sc, JME_RXMAC);
2751 * Pad 10bytes right before received frame. This will greatly
2752 * help Rx performance on strict-alignment architectures as
2753 * it does not need to copy the frame to align the payload.
2755 reg |= RXMAC_PAD_10BYTES;
2756 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2757 reg |= RXMAC_CSUM_ENB;
2758 CSR_WRITE_4(sc, JME_RXMAC, reg);
2760 /* Configure general purpose reg0 */
2761 reg = CSR_READ_4(sc, JME_GPREG0);
2762 reg &= ~GPREG0_PCC_UNIT_MASK;
2763 /* Set PCC timer resolution to micro-seconds unit. */
2764 reg |= GPREG0_PCC_UNIT_US;
2766 * Disable all shadow register posting as we have to read
2767 * JME_INTR_STATUS register in jme_int_task. Also it seems
2768 * that it's hard to synchronize interrupt status between
2769 * hardware and software with shadow posting due to
2770 * requirements of bus_dmamap_sync(9).
2772 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2773 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2774 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2775 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2776 /* Disable posting of DW0. */
2777 reg &= ~GPREG0_POST_DW0_ENB;
2778 /* Clear PME message. */
2779 reg &= ~GPREG0_PME_ENB;
2780 /* Set PHY address. */
2781 reg &= ~GPREG0_PHY_ADDR_MASK;
2782 reg |= sc->jme_phyaddr;
2783 CSR_WRITE_4(sc, JME_GPREG0, reg);
2785 /* Configure Tx queue 0 packet completion coalescing. */
2786 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2788 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2789 PCCTX_COAL_PKT_MASK;
2790 reg |= PCCTX_COAL_TXQ0;
2791 CSR_WRITE_4(sc, JME_PCCTX, reg);
2793 /* Configure Rx queue 0 packet completion coalescing. */
2794 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2796 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2797 PCCRX_COAL_PKT_MASK;
2798 CSR_WRITE_4(sc, JME_PCCRX0, reg);
2800 /* Configure shadow status block but don't enable posting. */
2801 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2802 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2803 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2805 /* Disable Timer 1 and Timer 2. */
2806 CSR_WRITE_4(sc, JME_TIMER1, 0);
2807 CSR_WRITE_4(sc, JME_TIMER2, 0);
2809 /* Configure retry transmit period, retry limit value. */
2810 CSR_WRITE_4(sc, JME_TXTRHD,
2811 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2812 TXTRHD_RT_PERIOD_MASK) |
2813 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2814 TXTRHD_RT_LIMIT_SHIFT));
2817 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2819 /* Initialize the interrupt mask. */
2820 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2821 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2824 * Enabling Tx/Rx DMA engines and Rx queue processing is
2825 * done after detection of valid link in jme_link_task.
2828 sc->jme_flags &= ~JME_FLAG_LINK;
2829 /* Set the current media. */
2832 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2834 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2835 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2839 jme_stop(struct jme_softc *sc)
2842 struct jme_txdesc *txd;
2843 struct jme_rxdesc *rxd;
2846 JME_LOCK_ASSERT(sc);
2848 * Mark the interface down and cancel the watchdog timer.
2851 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2852 sc->jme_flags &= ~JME_FLAG_LINK;
2853 callout_stop(&sc->jme_tick_ch);
2854 sc->jme_watchdog_timer = 0;
2857 * Disable interrupts.
2859 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2860 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2862 /* Disable updating shadow status block. */
2863 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2864 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2866 /* Stop receiver, transmitter. */
2870 /* Reclaim Rx/Tx buffers that have been completed. */
2871 jme_rxintr(sc, JME_RX_RING_CNT);
2872 if (sc->jme_cdata.jme_rxhead != NULL)
2873 m_freem(sc->jme_cdata.jme_rxhead);
2874 JME_RXCHAIN_RESET(sc);
2877 * Free RX and TX mbufs still in the queues.
2879 for (i = 0; i < JME_RX_RING_CNT; i++) {
2880 rxd = &sc->jme_cdata.jme_rxdesc[i];
2881 if (rxd->rx_m != NULL) {
2882 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag,
2883 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2884 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2890 for (i = 0; i < JME_TX_RING_CNT; i++) {
2891 txd = &sc->jme_cdata.jme_txdesc[i];
2892 if (txd->tx_m != NULL) {
2893 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag,
2894 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2895 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2902 jme_stats_update(sc);
2907 jme_stop_tx(struct jme_softc *sc)
2912 reg = CSR_READ_4(sc, JME_TXCSR);
2913 if ((reg & TXCSR_TX_ENB) == 0)
2915 reg &= ~TXCSR_TX_ENB;
2916 CSR_WRITE_4(sc, JME_TXCSR, reg);
2917 for (i = JME_TIMEOUT; i > 0; i--) {
2919 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2923 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2927 jme_stop_rx(struct jme_softc *sc)
2932 reg = CSR_READ_4(sc, JME_RXCSR);
2933 if ((reg & RXCSR_RX_ENB) == 0)
2935 reg &= ~RXCSR_RX_ENB;
2936 CSR_WRITE_4(sc, JME_RXCSR, reg);
2937 for (i = JME_TIMEOUT; i > 0; i--) {
2939 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2943 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2947 jme_init_tx_ring(struct jme_softc *sc)
2949 struct jme_ring_data *rd;
2950 struct jme_txdesc *txd;
2953 sc->jme_cdata.jme_tx_prod = 0;
2954 sc->jme_cdata.jme_tx_cons = 0;
2955 sc->jme_cdata.jme_tx_cnt = 0;
2957 rd = &sc->jme_rdata;
2958 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE);
2959 for (i = 0; i < JME_TX_RING_CNT; i++) {
2960 txd = &sc->jme_cdata.jme_txdesc[i];
2962 txd->tx_desc = &rd->jme_tx_ring[i];
2966 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2967 sc->jme_cdata.jme_tx_ring_map,
2968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2972 jme_init_ssb(struct jme_softc *sc)
2974 struct jme_ring_data *rd;
2976 rd = &sc->jme_rdata;
2977 bzero(rd->jme_ssb_block, JME_SSB_SIZE);
2978 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
2979 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2983 jme_init_rx_ring(struct jme_softc *sc)
2985 struct jme_ring_data *rd;
2986 struct jme_rxdesc *rxd;
2989 sc->jme_cdata.jme_rx_cons = 0;
2990 JME_RXCHAIN_RESET(sc);
2991 atomic_set_int(&sc->jme_morework, 0);
2993 rd = &sc->jme_rdata;
2994 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE);
2995 for (i = 0; i < JME_RX_RING_CNT; i++) {
2996 rxd = &sc->jme_cdata.jme_rxdesc[i];
2998 rxd->rx_desc = &rd->jme_rx_ring[i];
2999 if (jme_newbuf(sc, rxd) != 0)
3003 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
3004 sc->jme_cdata.jme_rx_ring_map,
3005 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3011 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd)
3013 struct jme_desc *desc;
3015 bus_dma_segment_t segs[1];
3019 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3023 * JMC250 has 64bit boundary alignment limitation so jme(4)
3024 * takes advantage of 10 bytes padding feature of hardware
3025 * in order not to copy entire frame to align IP header on
3028 m->m_len = m->m_pkthdr.len = MCLBYTES;
3030 if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag,
3031 sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3035 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3037 if (rxd->rx_m != NULL) {
3038 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3039 BUS_DMASYNC_POSTREAD);
3040 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
3042 map = rxd->rx_dmamap;
3043 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
3044 sc->jme_cdata.jme_rx_sparemap = map;
3045 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
3046 BUS_DMASYNC_PREREAD);
3049 desc = rxd->rx_desc;
3050 desc->buflen = htole32(segs[0].ds_len);
3051 desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr));
3052 desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr));
3053 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
3059 jme_set_vlan(struct jme_softc *sc)
3064 JME_LOCK_ASSERT(sc);
3067 reg = CSR_READ_4(sc, JME_RXMAC);
3068 reg &= ~RXMAC_VLAN_ENB;
3069 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3070 reg |= RXMAC_VLAN_ENB;
3071 CSR_WRITE_4(sc, JME_RXMAC, reg);
3075 jme_set_filter(struct jme_softc *sc)
3078 struct ifmultiaddr *ifma;
3083 JME_LOCK_ASSERT(sc);
3087 rxcfg = CSR_READ_4(sc, JME_RXMAC);
3088 rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3090 /* Always accept frames destined to our station address. */
3091 rxcfg |= RXMAC_UNICAST;
3092 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3093 rxcfg |= RXMAC_BROADCAST;
3094 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3095 if ((ifp->if_flags & IFF_PROMISC) != 0)
3096 rxcfg |= RXMAC_PROMISC;
3097 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3098 rxcfg |= RXMAC_ALLMULTI;
3099 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3100 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3101 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3106 * Set up the multicast address filter by passing all multicast
3107 * addresses through a CRC generator, and then using the low-order
3108 * 6 bits as an index into the 64 bit multicast hash table. The
3109 * high order bits select the register, while the rest of the bits
3110 * select the bit within the register.
3112 rxcfg |= RXMAC_MULTICAST;
3113 bzero(mchash, sizeof(mchash));
3115 if_maddr_rlock(ifp);
3116 TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) {
3117 if (ifma->ifma_addr->sa_family != AF_LINK)
3119 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3120 ifma->ifma_addr), ETHER_ADDR_LEN);
3122 /* Just want the 6 least significant bits. */
3125 /* Set the corresponding bit in the hash table. */
3126 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3128 if_maddr_runlock(ifp);
3130 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3131 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3132 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3136 jme_stats_clear(struct jme_softc *sc)
3139 JME_LOCK_ASSERT(sc);
3141 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3144 /* Disable and clear counters. */
3145 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3146 /* Activate hw counters. */
3147 CSR_WRITE_4(sc, JME_STATCSR, 0);
3148 CSR_READ_4(sc, JME_STATCSR);
3149 bzero(&sc->jme_stats, sizeof(struct jme_hw_stats));
3153 jme_stats_save(struct jme_softc *sc)
3156 JME_LOCK_ASSERT(sc);
3158 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3160 /* Save current counters. */
3161 bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats));
3162 /* Disable and clear counters. */
3163 CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF);
3167 jme_stats_update(struct jme_softc *sc)
3169 struct jme_hw_stats *stat, *ostat;
3172 JME_LOCK_ASSERT(sc);
3174 if ((sc->jme_flags & JME_FLAG_HWMIB) == 0)
3176 stat = &sc->jme_stats;
3177 ostat = &sc->jme_ostats;
3178 stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD);
3179 stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD);
3180 reg = CSR_READ_4(sc, JME_STAT_CRCMII);
3181 stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >>
3182 STAT_RX_CRC_ERR_SHIFT;
3183 stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >>
3184 STAT_RX_MII_ERR_SHIFT;
3185 reg = CSR_READ_4(sc, JME_STAT_RXERR);
3186 stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >>
3187 STAT_RXERR_OFLOW_SHIFT;
3188 stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >>
3189 STAT_RXERR_MPTY_SHIFT;
3190 reg = CSR_READ_4(sc, JME_STAT_FAIL);
3191 stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT;
3192 stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT;
3194 /* Account for previous counters. */
3195 stat->rx_good_frames += ostat->rx_good_frames;
3196 stat->rx_crc_errs += ostat->rx_crc_errs;
3197 stat->rx_mii_errs += ostat->rx_mii_errs;
3198 stat->rx_fifo_oflows += ostat->rx_fifo_oflows;
3199 stat->rx_desc_empty += ostat->rx_desc_empty;
3200 stat->rx_bad_frames += ostat->rx_bad_frames;
3201 stat->tx_good_frames += ostat->tx_good_frames;
3202 stat->tx_bad_frames += ostat->tx_bad_frames;
3206 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3212 value = *(int *)arg1;
3213 error = sysctl_handle_int(oidp, &value, 0, req);
3214 if (error || req->newptr == NULL)
3216 if (value < low || value > high)
3218 *(int *)arg1 = value;
3224 sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS)
3226 return (sysctl_int_range(oidp, arg1, arg2, req,
3227 PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX));
3231 sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3233 return (sysctl_int_range(oidp, arg1, arg2, req,
3234 PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX));
3238 sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS)
3240 return (sysctl_int_range(oidp, arg1, arg2, req,
3241 PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX));
3245 sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3247 return (sysctl_int_range(oidp, arg1, arg2, req,
3248 PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX));
3252 sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS)
3254 return (sysctl_int_range(oidp, arg1, arg2, req,
3255 JME_PROC_MIN, JME_PROC_MAX));