2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
35 * PCI:PCI bridge support.
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
43 #include <machine/bus.h>
45 #include <sys/sysctl.h>
47 #include <machine/resource.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcib_private.h>
55 static int pcib_probe(device_t dev);
57 static device_method_t pcib_methods[] = {
58 /* Device interface */
59 DEVMETHOD(device_probe, pcib_probe),
60 DEVMETHOD(device_attach, pcib_attach),
61 DEVMETHOD(device_detach, bus_generic_detach),
62 DEVMETHOD(device_shutdown, bus_generic_shutdown),
63 DEVMETHOD(device_suspend, bus_generic_suspend),
64 DEVMETHOD(device_resume, bus_generic_resume),
67 DEVMETHOD(bus_print_child, bus_generic_print_child),
68 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
69 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
70 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
71 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
72 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
73 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
74 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
75 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
78 DEVMETHOD(pcib_maxslots, pcib_maxslots),
79 DEVMETHOD(pcib_read_config, pcib_read_config),
80 DEVMETHOD(pcib_write_config, pcib_write_config),
81 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
82 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
83 DEVMETHOD(pcib_release_msi, pcib_release_msi),
84 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
85 DEVMETHOD(pcib_release_msix, pcib_release_msix),
86 DEVMETHOD(pcib_map_msi, pcib_map_msi),
91 static devclass_t pcib_devclass;
93 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
94 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
97 * Is the prefetch window open (eg, can we allocate memory in it?)
100 pcib_is_prefetch_open(struct pcib_softc *sc)
102 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
106 * Is the nonprefetch window open (eg, can we allocate memory in it?)
109 pcib_is_nonprefetch_open(struct pcib_softc *sc)
111 return (sc->membase > 0 && sc->membase < sc->memlimit);
115 * Is the io window open (eg, can we allocate ports in it?)
118 pcib_is_io_open(struct pcib_softc *sc)
120 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
124 * Generic device interface
127 pcib_probe(device_t dev)
129 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
130 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
131 device_set_desc(dev, "PCI-PCI bridge");
138 pcib_attach_common(device_t dev)
140 struct pcib_softc *sc;
142 struct sysctl_ctx_list *sctx;
143 struct sysctl_oid *soid;
145 sc = device_get_softc(dev);
149 * Get current bridge configuration.
151 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
152 sc->domain = pci_get_domain(dev);
153 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1);
154 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
155 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
156 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
157 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
158 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
161 * Setup sysctl reporting nodes
163 sctx = device_get_sysctl_ctx(dev);
164 soid = device_get_sysctl_tree(dev);
165 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
166 CTLFLAG_RD, &sc->domain, 0, "Domain number");
167 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
168 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
169 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
170 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number");
171 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
172 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number");
175 * Determine current I/O decode.
177 if (sc->command & PCIM_CMD_PORTEN) {
178 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
179 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
180 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
181 pci_read_config(dev, PCIR_IOBASEL_1, 1));
183 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
186 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
187 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
188 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
189 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
191 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
196 * Determine current memory decode.
198 if (sc->command & PCIM_CMD_MEMEN) {
199 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
200 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
201 iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1);
202 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
203 sc->pmembase = PCI_PPBMEMBASE(
204 pci_read_config(dev, PCIR_PMBASEH_1, 4),
205 pci_read_config(dev, PCIR_PMBASEL_1, 2));
207 sc->pmembase = PCI_PPBMEMBASE(0,
208 pci_read_config(dev, PCIR_PMBASEL_1, 2));
209 iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1);
210 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
211 sc->pmemlimit = PCI_PPBMEMLIMIT(
212 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
213 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
215 sc->pmemlimit = PCI_PPBMEMLIMIT(0,
216 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
222 switch (pci_get_devid(dev)) {
223 case 0x12258086: /* Intel 82454KX/GX (Orion) */
227 supbus = pci_read_config(dev, 0x41, 1);
228 if (supbus != 0xff) {
229 sc->secbus = supbus + 1;
230 sc->subbus = supbus + 1;
236 * The i82380FB mobile docking controller is a PCI-PCI bridge,
237 * and it is a subtractive bridge. However, the ProgIf is wrong
238 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
239 * happen. There's also a Toshiba bridge that behaves this
242 case 0x124b8086: /* Intel 82380FB Mobile */
243 case 0x060513d7: /* Toshiba ???? */
244 sc->flags |= PCIB_SUBTRACTIVE;
247 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
252 if ((cp = getenv("smbios.planar.maker")) == NULL)
254 if (strncmp(cp, "Compal", 6) != 0) {
259 if ((cp = getenv("smbios.planar.product")) == NULL)
261 if (strncmp(cp, "08A0", 4) != 0) {
266 if (sc->subbus < 0xa) {
267 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
268 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
274 if (pci_msi_device_blacklisted(dev))
275 sc->flags |= PCIB_DISABLE_MSI;
278 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
279 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
280 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
281 * This means they act as if they were subtractively decoding
282 * bridges and pass all transactions. Mark them and real ProgIf 1
283 * parts as subtractive.
285 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
286 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
287 sc->flags |= PCIB_SUBTRACTIVE;
290 device_printf(dev, " domain %d\n", sc->domain);
291 device_printf(dev, " secondary bus %d\n", sc->secbus);
292 device_printf(dev, " subordinate bus %d\n", sc->subbus);
293 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
294 if (pcib_is_nonprefetch_open(sc))
295 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
296 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
297 if (pcib_is_prefetch_open(sc))
298 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
299 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
301 device_printf(dev, " no prefetched decode\n");
302 if (sc->flags & PCIB_SUBTRACTIVE)
303 device_printf(dev, " Subtractively decoded bridge.\n");
307 * XXX If the secondary bus number is zero, we should assign a bus number
308 * since the BIOS hasn't, then initialise the bridge. A simple
309 * bus_alloc_resource with the a couple of busses seems like the right
310 * approach, but we don't know what busses the BIOS might have already
311 * assigned to other bridges on this bus that probe later than we do.
313 * If the subordinate bus number is less than the secondary bus number,
314 * we should pick a better value. One sensible alternative would be to
315 * pick 255; the only tradeoff here is that configuration transactions
316 * would be more widely routed than absolutely necessary. We could
317 * then do a walk of the tree later and fix it.
322 pcib_attach(device_t dev)
324 struct pcib_softc *sc;
327 pcib_attach_common(dev);
328 sc = device_get_softc(dev);
329 if (sc->secbus != 0) {
330 child = device_add_child(dev, "pci", sc->secbus);
332 return(bus_generic_attach(dev));
335 /* no secondary bus; we should have fixed this */
340 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
342 struct pcib_softc *sc = device_get_softc(dev);
345 case PCIB_IVAR_DOMAIN:
346 *result = sc->domain;
349 *result = sc->secbus;
356 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
358 struct pcib_softc *sc = device_get_softc(dev);
361 case PCIB_IVAR_DOMAIN:
371 * We have to trap resource allocation requests and ensure that the bridge
372 * is set up to, or capable of handling them.
375 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
376 u_long start, u_long end, u_long count, u_int flags)
378 struct pcib_softc *sc = device_get_softc(dev);
379 const char *name, *suffix;
383 * Fail the allocation for this range if it's not supported.
385 name = device_get_nameunit(child);
394 if (!pcib_is_io_open(sc))
396 ok = (start >= sc->iobase && end <= sc->iolimit);
399 * Make sure we allow access to VGA I/O addresses when the
400 * bridge has the "VGA Enable" bit set.
402 if (!ok && pci_is_vga_ioport_range(start, end))
403 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
405 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
407 if (start < sc->iobase)
409 if (end > sc->iolimit)
418 * If we overlap with the subtractive range, then
419 * pick the upper range to use.
421 if (start < sc->iolimit && end > sc->iobase)
422 start = sc->iolimit + 1;
426 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
433 device_printf(dev, "%s%srequested unsupported I/O "
434 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
435 name, suffix, start, end, sc->iobase, sc->iolimit);
440 "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
441 name, suffix, start, end);
446 if (pcib_is_nonprefetch_open(sc))
447 ok = ok || (start >= sc->membase && end <= sc->memlimit);
448 if (pcib_is_prefetch_open(sc))
449 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
452 * Make sure we allow access to VGA memory addresses when the
453 * bridge has the "VGA Enable" bit set.
455 if (!ok && pci_is_vga_memory_range(start, end))
456 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
458 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
461 if (flags & RF_PREFETCHABLE) {
462 if (pcib_is_prefetch_open(sc)) {
463 if (start < sc->pmembase)
464 start = sc->pmembase;
465 if (end > sc->pmemlimit)
470 } else { /* non-prefetchable */
471 if (pcib_is_nonprefetch_open(sc)) {
472 if (start < sc->membase)
474 if (end > sc->memlimit)
482 ok = 1; /* subtractive bridge: always ok */
484 if (pcib_is_nonprefetch_open(sc)) {
485 if (start < sc->memlimit && end > sc->membase)
486 start = sc->memlimit + 1;
488 if (pcib_is_prefetch_open(sc)) {
489 if (start < sc->pmemlimit && end > sc->pmembase)
490 start = sc->pmemlimit + 1;
495 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
501 if (!ok && bootverbose)
503 "%s%srequested unsupported memory range %#lx-%#lx "
504 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
505 name, suffix, start, end,
506 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
507 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
511 device_printf(dev,"%s%srequested memory range "
512 "0x%lx-0x%lx: good\n",
513 name, suffix, start, end);
520 * Bridge is OK decoding this resource, so pass it up.
522 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
530 pcib_maxslots(device_t dev)
536 * Since we are a child of a PCI bus, its parent must support the pcib interface.
539 pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
541 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
545 pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
547 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
551 * Route an interrupt across a PCI bridge.
554 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
562 * The PCI standard defines a swizzle of the child-side device/intpin to
563 * the parent-side intpin as follows.
565 * device = device on child bus
566 * child_intpin = intpin on child bus slot (0-3)
567 * parent_intpin = intpin on parent bus slot (0-3)
569 * parent_intpin = (device + child_intpin) % 4
571 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
574 * Our parent is a PCI bus. Its parent must export the pcib interface
575 * which includes the ability to route interrupts.
577 bus = device_get_parent(pcib);
578 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
579 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
580 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
581 pci_get_slot(dev), 'A' + pin - 1, intnum);
586 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
588 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
590 struct pcib_softc *sc = device_get_softc(pcib);
593 if (sc->flags & PCIB_DISABLE_MSI)
595 bus = device_get_parent(pcib);
596 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
600 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
602 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
606 bus = device_get_parent(pcib);
607 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
610 /* Pass request to alloc an MSI-X message up to the parent bridge. */
612 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
614 struct pcib_softc *sc = device_get_softc(pcib);
617 if (sc->flags & PCIB_DISABLE_MSI)
619 bus = device_get_parent(pcib);
620 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
623 /* Pass request to release an MSI-X message up to the parent bridge. */
625 pcib_release_msix(device_t pcib, device_t dev, int irq)
629 bus = device_get_parent(pcib);
630 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
633 /* Pass request to map MSI/MSI-X message up to parent bridge. */
635 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
641 bus = device_get_parent(pcib);
642 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
646 pci_ht_map_msi(pcib, *addr);
651 * Try to read the bus number of a host-PCI bridge using appropriate config
655 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
660 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
661 if (id == 0xffffffff)
667 /* XXX This is a guess */
668 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
672 /* Intel 82454KX/GX (Orion) */
673 *busnum = read_config(bus, slot, func, 0x4a, 1);
677 * For the 450nx chipset, there is a whole bundle of
678 * things pretending to be host bridges. The MIOC will
679 * be seen first and isn't really a pci bridge (the
680 * actual busses are attached to the PXB's). We need to
681 * read the registers of the MIOC to figure out the
682 * bus numbers for the PXB channels.
684 * Since the MIOC doesn't have a pci bus attached, we
685 * pretend it wasn't there.
691 /* Intel 82454NX PXB#0, Bus#A */
692 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
695 /* Intel 82454NX PXB#0, Bus#B */
696 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
699 /* Intel 82454NX PXB#1, Bus#A */
700 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
703 /* Intel 82454NX PXB#1, Bus#B */
704 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
709 /* ServerWorks -- vendor 0x1166 */
723 *busnum = read_config(bus, slot, func, 0x44, 1);
726 /* Compaq/HP -- vendor 0x0e11 */
728 *busnum = read_config(bus, slot, func, 0xc8, 1);
731 /* Don't know how to read bus number. */