2 * Copyright (c) 2008-2010 Nikolay Denev <ndenev@gmail.com>
3 * Copyright (c) 2007-2008 Alexander Pohoyda <alexander.pohoyda@gmx.net>
4 * Copyright (c) 1997, 1998, 1999
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS''
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR
26 * THE VOICES IN THEIR HEADS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
33 * OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
40 * SiS 190/191 PCI Ethernet NIC driver.
42 * Adapted to SiS 190 NIC by Alexander Pohoyda based on the original
43 * SiS 900 driver by Bill Paul, using SiS 190/191 Solaris driver by
44 * Masayuki Murayama and SiS 190/191 GNU/Linux driver by K.M. Liu
45 * <kmliu@sis.com>. Thanks to Pyun YongHyeon <pyunyh@gmail.com> for
46 * review and very useful comments.
48 * Adapted to SiS 191 NIC by Nikolay Denev with further ideas from the
49 * Linux and Solaris drivers.
52 #include <sys/param.h>
53 #include <sys/systm.h>
55 #include <sys/endian.h>
56 #include <sys/kernel.h>
58 #include <sys/malloc.h>
60 #include <sys/module.h>
61 #include <sys/mutex.h>
63 #include <sys/socket.h>
64 #include <sys/sockio.h>
68 #include <net/if_arp.h>
69 #include <net/ethernet.h>
70 #include <net/if_dl.h>
71 #include <net/if_media.h>
72 #include <net/if_types.h>
73 #include <net/if_vlan_var.h>
75 #include <netinet/in.h>
76 #include <netinet/in_systm.h>
77 #include <netinet/ip.h>
78 #include <netinet/tcp.h>
80 #include <machine/bus.h>
81 #include <machine/in_cksum.h>
83 #include <dev/mii/mii.h>
84 #include <dev/mii/miivar.h>
86 #include <dev/pci/pcireg.h>
87 #include <dev/pci/pcivar.h>
89 #include <dev/sge/if_sgereg.h>
91 MODULE_DEPEND(sge, pci, 1, 1, 1);
92 MODULE_DEPEND(sge, ether, 1, 1, 1);
93 MODULE_DEPEND(sge, miibus, 1, 1, 1);
95 /* "device miibus0" required. See GENERIC if you get errors here. */
96 #include "miibus_if.h"
99 * Various supported device vendors/types and their names.
101 static struct sge_type sge_devs[] = {
102 { SIS_VENDORID, SIS_DEVICEID_190, "SiS190 Fast Ethernet" },
103 { SIS_VENDORID, SIS_DEVICEID_191, "SiS191 Fast/Gigabit Ethernet" },
107 static int sge_probe(device_t);
108 static int sge_attach(device_t);
109 static int sge_detach(device_t);
110 static int sge_shutdown(device_t);
111 static int sge_suspend(device_t);
112 static int sge_resume(device_t);
114 static int sge_miibus_readreg(device_t, int, int);
115 static int sge_miibus_writereg(device_t, int, int, int);
116 static void sge_miibus_statchg(device_t);
118 static int sge_newbuf(struct sge_softc *, int);
119 static int sge_encap(struct sge_softc *, struct mbuf **);
121 sge_discard_rxbuf(struct sge_softc *, int);
122 static void sge_rxeof(struct sge_softc *);
123 static void sge_txeof(struct sge_softc *);
124 static void sge_intr(void *);
125 static void sge_tick(void *);
126 static void sge_start(struct ifnet *);
127 static void sge_start_locked(struct ifnet *);
128 static int sge_ioctl(struct ifnet *, u_long, caddr_t);
129 static void sge_init(void *);
130 static void sge_init_locked(struct sge_softc *);
131 static void sge_stop(struct sge_softc *);
132 static void sge_watchdog(struct sge_softc *);
133 static int sge_ifmedia_upd(struct ifnet *);
134 static void sge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
136 static int sge_get_mac_addr_apc(struct sge_softc *, uint8_t *);
137 static int sge_get_mac_addr_eeprom(struct sge_softc *, uint8_t *);
138 static uint16_t sge_read_eeprom(struct sge_softc *, int);
140 static void sge_rxfilter(struct sge_softc *);
141 static void sge_setvlan(struct sge_softc *);
142 static void sge_reset(struct sge_softc *);
143 static int sge_list_rx_init(struct sge_softc *);
144 static int sge_list_rx_free(struct sge_softc *);
145 static int sge_list_tx_init(struct sge_softc *);
146 static int sge_list_tx_free(struct sge_softc *);
148 static int sge_dma_alloc(struct sge_softc *);
149 static void sge_dma_free(struct sge_softc *);
150 static void sge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
152 static device_method_t sge_methods[] = {
153 /* Device interface */
154 DEVMETHOD(device_probe, sge_probe),
155 DEVMETHOD(device_attach, sge_attach),
156 DEVMETHOD(device_detach, sge_detach),
157 DEVMETHOD(device_suspend, sge_suspend),
158 DEVMETHOD(device_resume, sge_resume),
159 DEVMETHOD(device_shutdown, sge_shutdown),
162 DEVMETHOD(bus_print_child, bus_generic_print_child),
163 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
166 DEVMETHOD(miibus_readreg, sge_miibus_readreg),
167 DEVMETHOD(miibus_writereg, sge_miibus_writereg),
168 DEVMETHOD(miibus_statchg, sge_miibus_statchg),
173 static driver_t sge_driver = {
174 "sge", sge_methods, sizeof(struct sge_softc)
177 static devclass_t sge_devclass;
179 DRIVER_MODULE(sge, pci, sge_driver, sge_devclass, 0, 0);
180 DRIVER_MODULE(miibus, sge, miibus_driver, miibus_devclass, 0, 0);
183 * Register space access macros.
185 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sge_res, reg, val)
186 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val)
187 #define CSR_WRITE_1(cs, reg, val) bus_write_1(sc->sge_res, reg, val)
189 #define CSR_READ_4(sc, reg) bus_read_4(sc->sge_res, reg)
190 #define CSR_READ_2(sc, reg) bus_read_2(sc->sge_res, reg)
191 #define CSR_READ_1(sc, reg) bus_read_1(sc->sge_res, reg)
193 /* Define to show Tx/Rx error status. */
194 #undef SGE_SHOW_ERRORS
196 #define SGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
199 sge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
205 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
211 * Read a sequence of words from the EEPROM.
214 sge_read_eeprom(struct sge_softc *sc, int offset)
219 KASSERT(offset <= EI_OFFSET, ("EEPROM offset too big"));
220 CSR_WRITE_4(sc, ROMInterface,
221 EI_REQ | EI_OP_RD | (offset << EI_OFFSET_SHIFT));
223 for (i = 0; i < SGE_TIMEOUT; i++) {
224 val = CSR_READ_4(sc, ROMInterface);
225 if ((val & EI_REQ) == 0)
229 if (i == SGE_TIMEOUT) {
230 device_printf(sc->sge_dev,
231 "EEPROM read timeout : 0x%08x\n", val);
235 return ((val & EI_DATA) >> EI_DATA_SHIFT);
239 sge_get_mac_addr_eeprom(struct sge_softc *sc, uint8_t *dest)
244 val = sge_read_eeprom(sc, EEPROMSignature);
245 if (val == 0xffff || val == 0) {
246 device_printf(sc->sge_dev,
247 "invalid EEPROM signature : 0x%04x\n", val);
251 for (i = 0; i < ETHER_ADDR_LEN; i += 2) {
252 val = sge_read_eeprom(sc, EEPROMMACAddr + i / 2);
253 dest[i + 0] = (uint8_t)val;
254 dest[i + 1] = (uint8_t)(val >> 8);
257 if ((sge_read_eeprom(sc, EEPROMInfo) & 0x80) != 0)
258 sc->sge_flags |= SGE_FLAG_RGMII;
263 * For SiS96x, APC CMOS RAM is used to store ethernet address.
264 * APC CMOS RAM is accessed through ISA bridge.
267 sge_get_mac_addr_apc(struct sge_softc *sc, uint8_t *dest)
269 #if defined(__amd64__) || defined(__i386__)
271 device_t bus, dev = NULL;
276 } *tp, apc_tbls[] = {
277 { SIS_VENDORID, 0x0965 },
278 { SIS_VENDORID, 0x0966 },
279 { SIS_VENDORID, 0x0968 }
282 int busnum, cnt, i, j, numkids;
284 cnt = sizeof(apc_tbls) / sizeof(apc_tbls[0]);
285 pci = devclass_find("pci");
286 for (busnum = 0; busnum < devclass_get_maxunit(pci); busnum++) {
287 bus = devclass_get_device(pci, busnum);
290 if (device_get_children(bus, &kids, &numkids) != 0)
292 for (i = 0; i < numkids; i++) {
294 if (pci_get_class(dev) == PCIC_BRIDGE &&
295 pci_get_subclass(dev) == PCIS_BRIDGE_ISA) {
297 for (j = 0; j < cnt; j++) {
298 if (pci_get_vendor(dev) == tp->vid &&
299 pci_get_device(dev) == tp->did) {
309 device_printf(sc->sge_dev, "couldn't find PCI-ISA bridge\n");
312 /* Enable port 0x78 and 0x79 to access APC registers. */
313 reg = pci_read_config(dev, 0x48, 1);
314 pci_write_config(dev, 0x48, reg & ~0x02, 1);
316 pci_read_config(dev, 0x48, 1);
317 /* Read stored ethernet address. */
318 for (i = 0; i < ETHER_ADDR_LEN; i++) {
319 outb(0x78, 0x09 + i);
323 if ((inb(0x79) & 0x80) != 0)
324 sc->sge_flags |= SGE_FLAG_RGMII;
325 /* Restore access to APC registers. */
326 pci_write_config(dev, 0x48, reg, 1);
335 sge_miibus_readreg(device_t dev, int phy, int reg)
337 struct sge_softc *sc;
341 sc = device_get_softc(dev);
342 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
343 (reg << GMI_REG_SHIFT) | GMI_OP_RD | GMI_REQ);
345 for (i = 0; i < SGE_TIMEOUT; i++) {
346 val = CSR_READ_4(sc, GMIIControl);
347 if ((val & GMI_REQ) == 0)
351 if (i == SGE_TIMEOUT) {
352 device_printf(sc->sge_dev, "PHY read timeout : %d\n", reg);
355 return ((val & GMI_DATA) >> GMI_DATA_SHIFT);
359 sge_miibus_writereg(device_t dev, int phy, int reg, int data)
361 struct sge_softc *sc;
365 sc = device_get_softc(dev);
366 CSR_WRITE_4(sc, GMIIControl, (phy << GMI_PHY_SHIFT) |
367 (reg << GMI_REG_SHIFT) | (data << GMI_DATA_SHIFT) |
368 GMI_OP_WR | GMI_REQ);
370 for (i = 0; i < SGE_TIMEOUT; i++) {
371 val = CSR_READ_4(sc, GMIIControl);
372 if ((val & GMI_REQ) == 0)
376 if (i == SGE_TIMEOUT)
377 device_printf(sc->sge_dev, "PHY write timeout : %d\n", reg);
382 sge_miibus_statchg(device_t dev)
384 struct sge_softc *sc;
385 struct mii_data *mii;
389 sc = device_get_softc(dev);
390 mii = device_get_softc(sc->sge_miibus);
392 if (mii == NULL || ifp == NULL ||
393 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
396 sc->sge_flags &= ~SGE_FLAG_LINK;
397 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
398 (IFM_ACTIVE | IFM_AVALID)) {
399 switch (IFM_SUBTYPE(mii->mii_media_active)) {
401 sc->sge_flags |= SGE_FLAG_LINK;
405 sc->sge_flags |= SGE_FLAG_LINK;
406 speed = SC_SPEED_100;
409 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0) {
410 sc->sge_flags |= SGE_FLAG_LINK;
411 speed = SC_SPEED_1000;
418 if ((sc->sge_flags & SGE_FLAG_LINK) == 0)
420 /* Reprogram MAC to resolved speed/duplex/flow-control parameters. */
421 ctl = CSR_READ_4(sc, StationControl);
422 ctl &= ~(0x0f000000 | SC_FDX | SC_SPEED_MASK);
423 if (speed == SC_SPEED_1000) {
425 sc->sge_flags |= SGE_FLAG_SPEED_1000;
428 sc->sge_flags &= ~SGE_FLAG_SPEED_1000;
431 if ((sc->sge_flags & SGE_FLAG_GMII) != 0)
435 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
437 sc->sge_flags |= SGE_FLAG_FDX;
439 sc->sge_flags &= ~SGE_FLAG_FDX;
440 CSR_WRITE_4(sc, StationControl, ctl);
441 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0) {
442 CSR_WRITE_4(sc, RGMIIDelay, 0x0441);
443 CSR_WRITE_4(sc, RGMIIDelay, 0x0440);
448 sge_rxfilter(struct sge_softc *sc)
451 struct ifmultiaddr *ifma;
452 uint32_t crc, hashes[2];
458 rxfilt = CSR_READ_2(sc, RxMacControl);
459 rxfilt &= ~(AcceptBroadcast | AcceptAllPhys | AcceptMulticast);
460 rxfilt |= AcceptMyPhys;
461 if ((ifp->if_flags & IFF_BROADCAST) != 0)
462 rxfilt |= AcceptBroadcast;
463 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
464 if ((ifp->if_flags & IFF_PROMISC) != 0)
465 rxfilt |= AcceptAllPhys;
466 rxfilt |= AcceptMulticast;
467 hashes[0] = 0xFFFFFFFF;
468 hashes[1] = 0xFFFFFFFF;
470 rxfilt |= AcceptMulticast;
471 hashes[0] = hashes[1] = 0;
472 /* Now program new ones. */
474 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
475 if (ifma->ifma_addr->sa_family != AF_LINK)
477 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
478 ifma->ifma_addr), ETHER_ADDR_LEN);
479 hashes[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
481 if_maddr_runlock(ifp);
483 CSR_WRITE_2(sc, RxMacControl, rxfilt);
484 CSR_WRITE_4(sc, RxHashTable, hashes[0]);
485 CSR_WRITE_4(sc, RxHashTable2, hashes[1]);
489 sge_setvlan(struct sge_softc *sc)
497 if ((ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) == 0)
499 rxfilt = CSR_READ_2(sc, RxMacControl);
500 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
501 rxfilt |= RXMAC_STRIP_VLAN;
503 rxfilt &= ~RXMAC_STRIP_VLAN;
504 CSR_WRITE_2(sc, RxMacControl, rxfilt);
508 sge_reset(struct sge_softc *sc)
511 CSR_WRITE_4(sc, IntrMask, 0);
512 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
515 CSR_WRITE_4(sc, IntrControl, 0x8000);
516 CSR_READ_4(sc, IntrControl);
518 CSR_WRITE_4(sc, IntrControl, 0);
520 CSR_WRITE_4(sc, TX_CTL, 0x1a00);
521 CSR_WRITE_4(sc, RX_CTL, 0x1a00);
523 CSR_WRITE_4(sc, IntrMask, 0);
524 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
526 CSR_WRITE_4(sc, GMIIControl, 0);
530 * Probe for an SiS chip. Check the PCI vendor and device
531 * IDs against our list and return a device name if we find a match.
534 sge_probe(device_t dev)
539 while (t->sge_name != NULL) {
540 if ((pci_get_vendor(dev) == t->sge_vid) &&
541 (pci_get_device(dev) == t->sge_did)) {
542 device_set_desc(dev, t->sge_name);
543 return (BUS_PROBE_DEFAULT);
552 * Attach the interface. Allocate softc structures, do ifmedia
553 * setup and ethernet/BPF attach.
556 sge_attach(device_t dev)
558 struct sge_softc *sc;
560 uint8_t eaddr[ETHER_ADDR_LEN];
563 sc = device_get_softc(dev);
566 mtx_init(&sc->sge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
568 callout_init_mtx(&sc->sge_stat_ch, &sc->sge_mtx, 0);
571 * Map control/status registers.
573 pci_enable_busmaster(dev);
575 /* Allocate resources. */
576 sc->sge_res_id = PCIR_BAR(0);
577 sc->sge_res_type = SYS_RES_MEMORY;
578 sc->sge_res = bus_alloc_resource_any(dev, sc->sge_res_type,
579 &sc->sge_res_id, RF_ACTIVE);
580 if (sc->sge_res == NULL) {
581 device_printf(dev, "couldn't allocate resource\n");
587 sc->sge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
588 RF_SHAREABLE | RF_ACTIVE);
589 if (sc->sge_irq == NULL) {
590 device_printf(dev, "couldn't allocate IRQ resources\n");
594 sc->sge_rev = pci_get_revid(dev);
595 if (pci_get_device(dev) == SIS_DEVICEID_190)
596 sc->sge_flags |= SGE_FLAG_FASTETHER | SGE_FLAG_SIS190;
597 /* Reset the adapter. */
600 /* Get MAC address from the EEPROM. */
601 if ((pci_read_config(dev, 0x73, 1) & 0x01) != 0)
602 sge_get_mac_addr_apc(sc, eaddr);
604 sge_get_mac_addr_eeprom(sc, eaddr);
606 if ((error = sge_dma_alloc(sc)) != 0)
609 ifp = sc->sge_ifp = if_alloc(IFT_ETHER);
611 device_printf(dev, "cannot allocate ifnet structure.\n");
616 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
618 ifp->if_ioctl = sge_ioctl;
619 ifp->if_start = sge_start;
620 ifp->if_init = sge_init;
621 ifp->if_snd.ifq_drv_maxlen = SGE_TX_RING_CNT - 1;
622 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
623 IFQ_SET_READY(&ifp->if_snd);
624 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_RXCSUM | IFCAP_TSO4;
625 ifp->if_hwassist = SGE_CSUM_FEATURES | CSUM_TSO;
626 ifp->if_capenable = ifp->if_capabilities;
630 error = mii_attach(dev, &sc->sge_miibus, ifp, sge_ifmedia_upd,
631 sge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
633 device_printf(dev, "attaching PHYs failed\n");
638 * Call MI attach routine.
640 ether_ifattach(ifp, eaddr);
643 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM |
644 IFCAP_VLAN_HWTSO | IFCAP_VLAN_MTU;
645 ifp->if_capenable = ifp->if_capabilities;
646 /* Tell the upper layer(s) we support long frames. */
647 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
649 /* Hook interrupt last to avoid having to lock softc */
650 error = bus_setup_intr(dev, sc->sge_irq, INTR_TYPE_NET | INTR_MPSAFE,
651 NULL, sge_intr, sc, &sc->sge_intrhand);
653 device_printf(dev, "couldn't set up irq\n");
666 * Shutdown hardware and free up resources. This can be called any
667 * time after the mutex has been initialized. It is called in both
668 * the error case in attach and the normal detach case so it needs
669 * to be careful about only freeing resources that have actually been
673 sge_detach(device_t dev)
675 struct sge_softc *sc;
678 sc = device_get_softc(dev);
680 /* These should only be active if attach succeeded. */
681 if (device_is_attached(dev)) {
686 callout_drain(&sc->sge_stat_ch);
689 device_delete_child(dev, sc->sge_miibus);
690 bus_generic_detach(dev);
692 if (sc->sge_intrhand)
693 bus_teardown_intr(dev, sc->sge_irq, sc->sge_intrhand);
695 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sge_irq);
697 bus_release_resource(dev, sc->sge_res_type, sc->sge_res_id,
702 mtx_destroy(&sc->sge_mtx);
708 * Stop all chip I/O so that the kernel's probe routines don't
709 * get confused by errant DMAs when rebooting.
712 sge_shutdown(device_t dev)
714 struct sge_softc *sc;
716 sc = device_get_softc(dev);
724 sge_suspend(device_t dev)
726 struct sge_softc *sc;
729 sc = device_get_softc(dev);
732 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
739 sge_resume(device_t dev)
741 struct sge_softc *sc;
744 sc = device_get_softc(dev);
747 if ((ifp->if_flags & IFF_UP) != 0)
754 sge_dma_alloc(struct sge_softc *sc)
756 struct sge_chain_data *cd;
757 struct sge_list_data *ld;
758 struct sge_rxdesc *rxd;
759 struct sge_txdesc *txd;
764 error = bus_dma_tag_create(bus_get_dma_tag(sc->sge_dev),
765 1, 0, /* alignment, boundary */
766 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
767 BUS_SPACE_MAXADDR, /* highaddr */
768 NULL, NULL, /* filter, filterarg */
769 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
771 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
777 device_printf(sc->sge_dev,
778 "could not create parent DMA tag.\n");
782 /* RX descriptor ring */
783 error = bus_dma_tag_create(cd->sge_tag,
784 SGE_DESC_ALIGN, 0, /* alignment, boundary */
785 BUS_SPACE_MAXADDR, /* lowaddr */
786 BUS_SPACE_MAXADDR, /* highaddr */
787 NULL, NULL, /* filter, filterarg */
788 SGE_RX_RING_SZ, 1, /* maxsize,nsegments */
789 SGE_RX_RING_SZ, /* maxsegsize */
795 device_printf(sc->sge_dev,
796 "could not create Rx ring DMA tag.\n");
799 /* Allocate DMA'able memory and load DMA map for RX ring. */
800 error = bus_dmamem_alloc(cd->sge_rx_tag, (void **)&ld->sge_rx_ring,
801 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
804 device_printf(sc->sge_dev,
805 "could not allocate DMA'able memory for Rx ring.\n");
808 error = bus_dmamap_load(cd->sge_rx_tag, cd->sge_rx_dmamap,
809 ld->sge_rx_ring, SGE_RX_RING_SZ, sge_dma_map_addr,
810 &ld->sge_rx_paddr, BUS_DMA_NOWAIT);
812 device_printf(sc->sge_dev,
813 "could not load DMA'able memory for Rx ring.\n");
816 /* TX descriptor ring */
817 error = bus_dma_tag_create(cd->sge_tag,
818 SGE_DESC_ALIGN, 0, /* alignment, boundary */
819 BUS_SPACE_MAXADDR, /* lowaddr */
820 BUS_SPACE_MAXADDR, /* highaddr */
821 NULL, NULL, /* filter, filterarg */
822 SGE_TX_RING_SZ, 1, /* maxsize,nsegments */
823 SGE_TX_RING_SZ, /* maxsegsize */
829 device_printf(sc->sge_dev,
830 "could not create Rx ring DMA tag.\n");
833 /* Allocate DMA'able memory and load DMA map for TX ring. */
834 error = bus_dmamem_alloc(cd->sge_tx_tag, (void **)&ld->sge_tx_ring,
835 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
838 device_printf(sc->sge_dev,
839 "could not allocate DMA'able memory for Tx ring.\n");
842 error = bus_dmamap_load(cd->sge_tx_tag, cd->sge_tx_dmamap,
843 ld->sge_tx_ring, SGE_TX_RING_SZ, sge_dma_map_addr,
844 &ld->sge_tx_paddr, BUS_DMA_NOWAIT);
846 device_printf(sc->sge_dev,
847 "could not load DMA'able memory for Rx ring.\n");
851 /* Create DMA tag for Tx buffers. */
852 error = bus_dma_tag_create(cd->sge_tag, 1, 0, BUS_SPACE_MAXADDR,
853 BUS_SPACE_MAXADDR, NULL, NULL, SGE_TSO_MAXSIZE, SGE_MAXTXSEGS,
854 SGE_TSO_MAXSEGSIZE, 0, NULL, NULL, &cd->sge_txmbuf_tag);
856 device_printf(sc->sge_dev,
857 "could not create Tx mbuf DMA tag.\n");
861 /* Create DMA tag for Rx buffers. */
862 error = bus_dma_tag_create(cd->sge_tag, SGE_RX_BUF_ALIGN, 0,
863 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
864 MCLBYTES, 0, NULL, NULL, &cd->sge_rxmbuf_tag);
866 device_printf(sc->sge_dev,
867 "could not create Rx mbuf DMA tag.\n");
871 /* Create DMA maps for Tx buffers. */
872 for (i = 0; i < SGE_TX_RING_CNT; i++) {
873 txd = &cd->sge_txdesc[i];
875 txd->tx_dmamap = NULL;
877 error = bus_dmamap_create(cd->sge_txmbuf_tag, 0,
880 device_printf(sc->sge_dev,
881 "could not create Tx DMA map.\n");
885 /* Create spare DMA map for Rx buffer. */
886 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0, &cd->sge_rx_spare_map);
888 device_printf(sc->sge_dev,
889 "could not create spare Rx DMA map.\n");
892 /* Create DMA maps for Rx buffers. */
893 for (i = 0; i < SGE_RX_RING_CNT; i++) {
894 rxd = &cd->sge_rxdesc[i];
896 rxd->rx_dmamap = NULL;
897 error = bus_dmamap_create(cd->sge_rxmbuf_tag, 0,
900 device_printf(sc->sge_dev,
901 "could not create Rx DMA map.\n");
910 sge_dma_free(struct sge_softc *sc)
912 struct sge_chain_data *cd;
913 struct sge_list_data *ld;
914 struct sge_rxdesc *rxd;
915 struct sge_txdesc *txd;
921 if (cd->sge_rx_tag != NULL) {
922 if (cd->sge_rx_dmamap != NULL)
923 bus_dmamap_unload(cd->sge_rx_tag, cd->sge_rx_dmamap);
924 if (cd->sge_rx_dmamap != NULL && ld->sge_rx_ring != NULL)
925 bus_dmamem_free(cd->sge_rx_tag, ld->sge_rx_ring,
927 ld->sge_rx_ring = NULL;
928 cd->sge_rx_dmamap = NULL;
929 bus_dma_tag_destroy(cd->sge_rx_tag);
930 cd->sge_rx_tag = NULL;
933 if (cd->sge_tx_tag != NULL) {
934 if (cd->sge_tx_dmamap != NULL)
935 bus_dmamap_unload(cd->sge_tx_tag, cd->sge_tx_dmamap);
936 if (cd->sge_tx_dmamap != NULL && ld->sge_tx_ring != NULL)
937 bus_dmamem_free(cd->sge_tx_tag, ld->sge_tx_ring,
939 ld->sge_tx_ring = NULL;
940 cd->sge_tx_dmamap = NULL;
941 bus_dma_tag_destroy(cd->sge_tx_tag);
942 cd->sge_tx_tag = NULL;
945 if (cd->sge_rxmbuf_tag != NULL) {
946 for (i = 0; i < SGE_RX_RING_CNT; i++) {
947 rxd = &cd->sge_rxdesc[i];
948 if (rxd->rx_dmamap != NULL) {
949 bus_dmamap_destroy(cd->sge_rxmbuf_tag,
951 rxd->rx_dmamap = NULL;
954 if (cd->sge_rx_spare_map != NULL) {
955 bus_dmamap_destroy(cd->sge_rxmbuf_tag,
956 cd->sge_rx_spare_map);
957 cd->sge_rx_spare_map = NULL;
959 bus_dma_tag_destroy(cd->sge_rxmbuf_tag);
960 cd->sge_rxmbuf_tag = NULL;
963 if (cd->sge_txmbuf_tag != NULL) {
964 for (i = 0; i < SGE_TX_RING_CNT; i++) {
965 txd = &cd->sge_txdesc[i];
966 if (txd->tx_dmamap != NULL) {
967 bus_dmamap_destroy(cd->sge_txmbuf_tag,
969 txd->tx_dmamap = NULL;
972 bus_dma_tag_destroy(cd->sge_txmbuf_tag);
973 cd->sge_txmbuf_tag = NULL;
975 if (cd->sge_tag != NULL)
976 bus_dma_tag_destroy(cd->sge_tag);
981 * Initialize the TX descriptors.
984 sge_list_tx_init(struct sge_softc *sc)
986 struct sge_list_data *ld;
987 struct sge_chain_data *cd;
992 bzero(ld->sge_tx_ring, SGE_TX_RING_SZ);
993 ld->sge_tx_ring[SGE_TX_RING_CNT - 1].sge_flags = htole32(RING_END);
994 bus_dmamap_sync(cd->sge_tx_tag, cd->sge_tx_dmamap,
995 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1003 sge_list_tx_free(struct sge_softc *sc)
1005 struct sge_chain_data *cd;
1006 struct sge_txdesc *txd;
1009 SGE_LOCK_ASSERT(sc);
1010 cd = &sc->sge_cdata;
1011 for (i = 0; i < SGE_TX_RING_CNT; i++) {
1012 txd = &cd->sge_txdesc[i];
1013 if (txd->tx_m != NULL) {
1014 bus_dmamap_sync(cd->sge_txmbuf_tag, txd->tx_dmamap,
1015 BUS_DMASYNC_POSTWRITE);
1016 bus_dmamap_unload(cd->sge_txmbuf_tag, txd->tx_dmamap);
1027 * Initialize the RX descriptors and allocate mbufs for them. Note that
1028 * we arrange the descriptors in a closed ring, so that the last descriptor
1029 * has RING_END flag set.
1032 sge_list_rx_init(struct sge_softc *sc)
1034 struct sge_chain_data *cd;
1037 SGE_LOCK_ASSERT(sc);
1038 cd = &sc->sge_cdata;
1039 cd->sge_rx_cons = 0;
1040 bzero(sc->sge_ldata.sge_rx_ring, SGE_RX_RING_SZ);
1041 for (i = 0; i < SGE_RX_RING_CNT; i++) {
1042 if (sge_newbuf(sc, i) != 0)
1045 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1051 sge_list_rx_free(struct sge_softc *sc)
1053 struct sge_chain_data *cd;
1054 struct sge_rxdesc *rxd;
1057 SGE_LOCK_ASSERT(sc);
1058 cd = &sc->sge_cdata;
1059 for (i = 0; i < SGE_RX_RING_CNT; i++) {
1060 rxd = &cd->sge_rxdesc[i];
1061 if (rxd->rx_m != NULL) {
1062 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1063 BUS_DMASYNC_POSTREAD);
1064 bus_dmamap_unload(cd->sge_rxmbuf_tag,
1074 * Initialize an RX descriptor and attach an MBUF cluster.
1077 sge_newbuf(struct sge_softc *sc, int prod)
1080 struct sge_desc *desc;
1081 struct sge_chain_data *cd;
1082 struct sge_rxdesc *rxd;
1083 bus_dma_segment_t segs[1];
1087 SGE_LOCK_ASSERT(sc);
1089 cd = &sc->sge_cdata;
1090 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1093 m->m_len = m->m_pkthdr.len = MCLBYTES;
1094 m_adj(m, SGE_RX_BUF_ALIGN);
1095 error = bus_dmamap_load_mbuf_sg(cd->sge_rxmbuf_tag,
1096 cd->sge_rx_spare_map, m, segs, &nsegs, 0);
1101 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1102 rxd = &cd->sge_rxdesc[prod];
1103 if (rxd->rx_m != NULL) {
1104 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1105 BUS_DMASYNC_POSTREAD);
1106 bus_dmamap_unload(cd->sge_rxmbuf_tag, rxd->rx_dmamap);
1108 map = rxd->rx_dmamap;
1109 rxd->rx_dmamap = cd->sge_rx_spare_map;
1110 cd->sge_rx_spare_map = map;
1111 bus_dmamap_sync(cd->sge_rxmbuf_tag, rxd->rx_dmamap,
1112 BUS_DMASYNC_PREREAD);
1115 desc = &sc->sge_ldata.sge_rx_ring[prod];
1116 desc->sge_sts_size = 0;
1117 desc->sge_ptr = htole32(SGE_ADDR_LO(segs[0].ds_addr));
1118 desc->sge_flags = htole32(segs[0].ds_len);
1119 if (prod == SGE_RX_RING_CNT - 1)
1120 desc->sge_flags |= htole32(RING_END);
1121 desc->sge_cmdsts = htole32(RDC_OWN | RDC_INTR);
1125 static __inline void
1126 sge_discard_rxbuf(struct sge_softc *sc, int index)
1128 struct sge_desc *desc;
1130 desc = &sc->sge_ldata.sge_rx_ring[index];
1131 desc->sge_sts_size = 0;
1132 desc->sge_flags = htole32(MCLBYTES - SGE_RX_BUF_ALIGN);
1133 if (index == SGE_RX_RING_CNT - 1)
1134 desc->sge_flags |= htole32(RING_END);
1135 desc->sge_cmdsts = htole32(RDC_OWN | RDC_INTR);
1139 * A frame has been uploaded: pass the resulting mbuf chain up to
1140 * the higher level protocols.
1143 sge_rxeof(struct sge_softc *sc)
1147 struct sge_chain_data *cd;
1148 struct sge_desc *cur_rx;
1149 uint32_t rxinfo, rxstat;
1152 SGE_LOCK_ASSERT(sc);
1155 cd = &sc->sge_cdata;
1157 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1158 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1159 cons = cd->sge_rx_cons;
1160 for (prog = 0; prog < SGE_RX_RING_CNT; prog++,
1161 SGE_INC(cons, SGE_RX_RING_CNT)) {
1162 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1164 cur_rx = &sc->sge_ldata.sge_rx_ring[cons];
1165 rxinfo = le32toh(cur_rx->sge_cmdsts);
1166 if ((rxinfo & RDC_OWN) != 0)
1168 rxstat = le32toh(cur_rx->sge_sts_size);
1169 if ((rxstat & RDS_CRCOK) == 0 || SGE_RX_ERROR(rxstat) != 0 ||
1170 SGE_RX_NSEGS(rxstat) != 1) {
1171 /* XXX We don't support multi-segment frames yet. */
1172 #ifdef SGE_SHOW_ERRORS
1173 device_printf(sc->sge_dev, "Rx error : 0x%b\n", rxstat,
1176 sge_discard_rxbuf(sc, cons);
1180 m = cd->sge_rxdesc[cons].rx_m;
1181 if (sge_newbuf(sc, cons) != 0) {
1182 sge_discard_rxbuf(sc, cons);
1186 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1187 if ((rxinfo & RDC_IP_CSUM) != 0 &&
1188 (rxinfo & RDC_IP_CSUM_OK) != 0)
1189 m->m_pkthdr.csum_flags |=
1190 CSUM_IP_CHECKED | CSUM_IP_VALID;
1191 if (((rxinfo & RDC_TCP_CSUM) != 0 &&
1192 (rxinfo & RDC_TCP_CSUM_OK) != 0) ||
1193 ((rxinfo & RDC_UDP_CSUM) != 0 &&
1194 (rxinfo & RDC_UDP_CSUM_OK) != 0)) {
1195 m->m_pkthdr.csum_flags |=
1196 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1197 m->m_pkthdr.csum_data = 0xffff;
1200 /* Check for VLAN tagged frame. */
1201 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1202 (rxstat & RDS_VLAN) != 0) {
1203 m->m_pkthdr.ether_vtag = rxinfo & RDC_VLAN_MASK;
1204 m->m_flags |= M_VLANTAG;
1207 * Account for 10bytes auto padding which is used
1208 * to align IP header on 32bit boundary. Also note,
1209 * CRC bytes is automatically removed by the
1212 m->m_data += SGE_RX_PAD_BYTES;
1213 m->m_pkthdr.len = m->m_len = SGE_RX_BYTES(rxstat) -
1215 m->m_pkthdr.rcvif = ifp;
1218 (*ifp->if_input)(ifp, m);
1223 bus_dmamap_sync(cd->sge_rx_tag, cd->sge_rx_dmamap,
1224 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1225 cd->sge_rx_cons = cons;
1230 * A frame was downloaded to the chip. It's safe for us to clean up
1234 sge_txeof(struct sge_softc *sc)
1237 struct sge_list_data *ld;
1238 struct sge_chain_data *cd;
1239 struct sge_txdesc *txd;
1241 int cons, nsegs, prod;
1243 SGE_LOCK_ASSERT(sc);
1246 ld = &sc->sge_ldata;
1247 cd = &sc->sge_cdata;
1249 if (cd->sge_tx_cnt == 0)
1251 bus_dmamap_sync(cd->sge_tx_tag, cd->sge_tx_dmamap,
1252 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1253 cons = cd->sge_tx_cons;
1254 prod = cd->sge_tx_prod;
1255 for (; cons != prod;) {
1256 txstat = le32toh(ld->sge_tx_ring[cons].sge_cmdsts);
1257 if ((txstat & TDC_OWN) != 0)
1260 * Only the first descriptor of multi-descriptor transmission
1261 * is updated by controller. Driver should skip entire
1262 * chained buffers for the transmitted frame. In other words
1263 * TDC_OWN bit is valid only at the first descriptor of a
1264 * multi-descriptor transmission.
1266 if (SGE_TX_ERROR(txstat) != 0) {
1267 #ifdef SGE_SHOW_ERRORS
1268 device_printf(sc->sge_dev, "Tx error : 0x%b\n",
1269 txstat, TX_ERR_BITS);
1274 ifp->if_collisions += (txstat & 0xFFFF) - 1;
1278 txd = &cd->sge_txdesc[cons];
1279 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
1280 ld->sge_tx_ring[cons].sge_cmdsts = 0;
1281 SGE_INC(cons, SGE_TX_RING_CNT);
1283 /* Reclaim transmitted mbuf. */
1284 KASSERT(txd->tx_m != NULL,
1285 ("%s: freeing NULL mbuf\n", __func__));
1286 bus_dmamap_sync(cd->sge_txmbuf_tag, txd->tx_dmamap,
1287 BUS_DMASYNC_POSTWRITE);
1288 bus_dmamap_unload(cd->sge_txmbuf_tag, txd->tx_dmamap);
1291 cd->sge_tx_cnt -= txd->tx_ndesc;
1292 KASSERT(cd->sge_tx_cnt >= 0,
1293 ("%s: Active Tx desc counter was garbled\n", __func__));
1295 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1297 cd->sge_tx_cons = cons;
1298 if (cd->sge_tx_cnt == 0)
1305 struct sge_softc *sc;
1306 struct mii_data *mii;
1310 SGE_LOCK_ASSERT(sc);
1313 mii = device_get_softc(sc->sge_miibus);
1315 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) {
1316 sge_miibus_statchg(sc->sge_dev);
1317 if ((sc->sge_flags & SGE_FLAG_LINK) != 0 &&
1318 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1319 sge_start_locked(ifp);
1322 * Reclaim transmitted frames here as we do not request
1323 * Tx completion interrupt for every queued frames to
1324 * reduce excessive interrupts.
1328 callout_reset(&sc->sge_stat_ch, hz, sge_tick, sc);
1334 struct sge_softc *sc;
1342 status = CSR_READ_4(sc, IntrStatus);
1343 if (status == 0xFFFFFFFF || (status & SGE_INTRS) == 0) {
1348 /* Acknowledge interrupts. */
1349 CSR_WRITE_4(sc, IntrStatus, status);
1350 /* Disable further interrupts. */
1351 CSR_WRITE_4(sc, IntrMask, 0);
1353 * It seems the controller supports some kind of interrupt
1354 * moderation mechanism but we still don't know how to
1355 * enable that. To reduce number of generated interrupts
1356 * under load we check pending interrupts in a loop. This
1357 * will increase number of register access and is not correct
1358 * way to handle interrupt moderation but there seems to be
1359 * no other way at this time.
1362 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1364 if ((status & (INTR_RX_DONE | INTR_RX_IDLE)) != 0) {
1366 /* Wakeup Rx MAC. */
1367 if ((status & INTR_RX_IDLE) != 0)
1368 CSR_WRITE_4(sc, RX_CTL,
1369 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);
1371 if ((status & (INTR_TX_DONE | INTR_TX_IDLE)) != 0)
1373 status = CSR_READ_4(sc, IntrStatus);
1374 if ((status & SGE_INTRS) == 0)
1376 /* Acknowledge interrupts. */
1377 CSR_WRITE_4(sc, IntrStatus, status);
1379 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1380 /* Re-enable interrupts */
1381 CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1382 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1383 sge_start_locked(ifp);
1389 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1390 * pointers to the fragment pointers.
1393 sge_encap(struct sge_softc *sc, struct mbuf **m_head)
1396 struct sge_desc *desc;
1397 struct sge_txdesc *txd;
1398 bus_dma_segment_t txsegs[SGE_MAXTXSEGS];
1399 uint32_t cflags, mss;
1400 int error, i, nsegs, prod, si;
1402 SGE_LOCK_ASSERT(sc);
1404 si = prod = sc->sge_cdata.sge_tx_prod;
1405 txd = &sc->sge_cdata.sge_txdesc[prod];
1406 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1407 struct ether_header *eh;
1410 uint32_t ip_off, poff;
1412 if (M_WRITABLE(*m_head) == 0) {
1413 /* Get a writable copy. */
1414 m = m_dup(*m_head, M_DONTWAIT);
1422 ip_off = sizeof(struct ether_header);
1423 m = m_pullup(*m_head, ip_off);
1428 eh = mtod(m, struct ether_header *);
1429 /* Check the existence of VLAN tag. */
1430 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1431 ip_off = sizeof(struct ether_vlan_header);
1432 m = m_pullup(m, ip_off);
1438 m = m_pullup(m, ip_off + sizeof(struct ip));
1443 ip = (struct ip *)(mtod(m, char *) + ip_off);
1444 poff = ip_off + (ip->ip_hl << 2);
1445 m = m_pullup(m, poff + sizeof(struct tcphdr));
1450 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1451 m = m_pullup(m, poff + (tcp->th_off << 2));
1457 * Reset IP checksum and recompute TCP pseudo
1458 * checksum that NDIS specification requires.
1460 ip = (struct ip *)(mtod(m, char *) + ip_off);
1462 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1463 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
1464 htons(IPPROTO_TCP));
1468 error = bus_dmamap_load_mbuf_sg(sc->sge_cdata.sge_txmbuf_tag,
1469 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1470 if (error == EFBIG) {
1471 m = m_collapse(*m_head, M_DONTWAIT, SGE_MAXTXSEGS);
1478 error = bus_dmamap_load_mbuf_sg(sc->sge_cdata.sge_txmbuf_tag,
1479 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1485 } else if (error != 0)
1488 KASSERT(nsegs != 0, ("zero segment returned"));
1489 /* Check descriptor overrun. */
1490 if (sc->sge_cdata.sge_tx_cnt + nsegs >= SGE_TX_RING_CNT) {
1491 bus_dmamap_unload(sc->sge_cdata.sge_txmbuf_tag, txd->tx_dmamap);
1494 bus_dmamap_sync(sc->sge_cdata.sge_txmbuf_tag, txd->tx_dmamap,
1495 BUS_DMASYNC_PREWRITE);
1500 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1502 mss = (uint32_t)m->m_pkthdr.tso_segsz;
1505 if (m->m_pkthdr.csum_flags & CSUM_IP)
1506 cflags |= TDC_IP_CSUM;
1507 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1508 cflags |= TDC_TCP_CSUM;
1509 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1510 cflags |= TDC_UDP_CSUM;
1512 for (i = 0; i < nsegs; i++) {
1513 desc = &sc->sge_ldata.sge_tx_ring[prod];
1515 desc->sge_sts_size = htole32(m->m_pkthdr.len | mss);
1516 desc->sge_cmdsts = 0;
1518 desc->sge_sts_size = 0;
1519 desc->sge_cmdsts = htole32(TDC_OWN);
1521 desc->sge_ptr = htole32(SGE_ADDR_LO(txsegs[i].ds_addr));
1522 desc->sge_flags = htole32(txsegs[i].ds_len);
1523 if (prod == SGE_TX_RING_CNT - 1)
1524 desc->sge_flags |= htole32(RING_END);
1525 sc->sge_cdata.sge_tx_cnt++;
1526 SGE_INC(prod, SGE_TX_RING_CNT);
1528 /* Update producer index. */
1529 sc->sge_cdata.sge_tx_prod = prod;
1531 desc = &sc->sge_ldata.sge_tx_ring[si];
1532 /* Configure VLAN. */
1533 if((m->m_flags & M_VLANTAG) != 0) {
1534 cflags |= m->m_pkthdr.ether_vtag;
1535 desc->sge_sts_size |= htole32(TDS_INS_VLAN);
1537 desc->sge_cmdsts |= htole32(TDC_DEF | TDC_CRC | TDC_PAD | cflags);
1539 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0)
1540 desc->sge_cmdsts |= htole32(TDC_BST);
1542 if ((sc->sge_flags & SGE_FLAG_FDX) == 0) {
1543 desc->sge_cmdsts |= htole32(TDC_COL | TDC_CRS | TDC_BKF);
1544 if ((sc->sge_flags & SGE_FLAG_SPEED_1000) != 0)
1545 desc->sge_cmdsts |= htole32(TDC_EXT | TDC_BST);
1548 /* Request interrupt and give ownership to controller. */
1549 desc->sge_cmdsts |= htole32(TDC_OWN | TDC_INTR);
1551 txd->tx_ndesc = nsegs;
1556 sge_start(struct ifnet *ifp)
1558 struct sge_softc *sc;
1562 sge_start_locked(ifp);
1567 sge_start_locked(struct ifnet *ifp)
1569 struct sge_softc *sc;
1570 struct mbuf *m_head;
1574 SGE_LOCK_ASSERT(sc);
1576 if ((sc->sge_flags & SGE_FLAG_LINK) == 0 ||
1577 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1581 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1582 if (sc->sge_cdata.sge_tx_cnt > (SGE_TX_RING_CNT -
1584 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1587 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1590 if (sge_encap(sc, &m_head)) {
1593 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1594 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1599 * If there's a BPF listener, bounce a copy of this frame
1602 BPF_MTAP(ifp, m_head);
1606 bus_dmamap_sync(sc->sge_cdata.sge_tx_tag,
1607 sc->sge_cdata.sge_tx_dmamap,
1608 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1609 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB | TX_CTL_POLL);
1617 struct sge_softc *sc;
1621 sge_init_locked(sc);
1626 sge_init_locked(struct sge_softc *sc)
1629 struct mii_data *mii;
1633 SGE_LOCK_ASSERT(sc);
1635 mii = device_get_softc(sc->sge_miibus);
1636 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1639 * Cancel pending I/O and free all RX/TX buffers.
1644 /* Init circular RX list. */
1645 if (sge_list_rx_init(sc) == ENOBUFS) {
1646 device_printf(sc->sge_dev, "no memory for Rx buffers\n");
1650 /* Init TX descriptors. */
1651 sge_list_tx_init(sc);
1653 * Load the address of the RX and TX lists.
1655 CSR_WRITE_4(sc, TX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_tx_paddr));
1656 CSR_WRITE_4(sc, RX_DESC, SGE_ADDR_LO(sc->sge_ldata.sge_rx_paddr));
1658 CSR_WRITE_4(sc, TxMacControl, 0x60);
1659 CSR_WRITE_4(sc, RxWakeOnLan, 0);
1660 CSR_WRITE_4(sc, RxWakeOnLanData, 0);
1661 /* Allow receiving VLAN frames. */
1662 CSR_WRITE_2(sc, RxMPSControl, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN +
1665 for (i = 0; i < ETHER_ADDR_LEN; i++)
1666 CSR_WRITE_1(sc, RxMacAddr + i, IF_LLADDR(ifp)[i]);
1667 /* Configure RX MAC. */
1668 rxfilt = RXMAC_STRIP_FCS | RXMAC_PAD_ENB | RXMAC_CSUM_ENB;
1669 CSR_WRITE_2(sc, RxMacControl, rxfilt);
1673 /* Initialize default speed/duplex information. */
1674 if ((sc->sge_flags & SGE_FLAG_FASTETHER) == 0)
1675 sc->sge_flags |= SGE_FLAG_SPEED_1000;
1676 sc->sge_flags |= SGE_FLAG_FDX;
1677 if ((sc->sge_flags & SGE_FLAG_RGMII) != 0)
1678 CSR_WRITE_4(sc, StationControl, 0x04008001);
1680 CSR_WRITE_4(sc, StationControl, 0x04000001);
1682 * XXX Try to mitigate interrupts.
1684 CSR_WRITE_4(sc, IntrControl, 0x08880000);
1686 if (sc->sge_intrcontrol != 0)
1687 CSR_WRITE_4(sc, IntrControl, sc->sge_intrcontrol);
1688 if (sc->sge_intrtimer != 0)
1689 CSR_WRITE_4(sc, IntrTimer, sc->sge_intrtimer);
1693 * Clear and enable interrupts.
1695 CSR_WRITE_4(sc, IntrStatus, 0xFFFFFFFF);
1696 CSR_WRITE_4(sc, IntrMask, SGE_INTRS);
1698 /* Enable receiver and transmitter. */
1699 CSR_WRITE_4(sc, TX_CTL, 0x1a00 | TX_CTL_ENB);
1700 CSR_WRITE_4(sc, RX_CTL, 0x1a00 | 0x000c | RX_CTL_POLL | RX_CTL_ENB);
1702 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1703 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1705 sc->sge_flags &= ~SGE_FLAG_LINK;
1707 callout_reset(&sc->sge_stat_ch, hz, sge_tick, sc);
1711 * Set media options.
1714 sge_ifmedia_upd(struct ifnet *ifp)
1716 struct sge_softc *sc;
1717 struct mii_data *mii;
1722 mii = device_get_softc(sc->sge_miibus);
1723 if (mii->mii_instance) {
1724 struct mii_softc *miisc;
1725 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1726 mii_phy_reset(miisc);
1728 error = mii_mediachg(mii);
1735 * Report current media status.
1738 sge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1740 struct sge_softc *sc;
1741 struct mii_data *mii;
1745 mii = device_get_softc(sc->sge_miibus);
1746 if ((ifp->if_flags & IFF_UP) == 0) {
1752 ifmr->ifm_active = mii->mii_media_active;
1753 ifmr->ifm_status = mii->mii_media_status;
1757 sge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1759 struct sge_softc *sc;
1761 struct mii_data *mii;
1762 int error = 0, mask, reinit;
1765 ifr = (struct ifreq *)data;
1770 if ((ifp->if_flags & IFF_UP) != 0) {
1771 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1772 ((ifp->if_flags ^ sc->sge_if_flags) &
1773 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1776 sge_init_locked(sc);
1777 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1779 sc->sge_if_flags = ifp->if_flags;
1785 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1786 if ((mask & IFCAP_TXCSUM) != 0 &&
1787 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1788 ifp->if_capenable ^= IFCAP_TXCSUM;
1789 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1790 ifp->if_hwassist |= SGE_CSUM_FEATURES;
1792 ifp->if_hwassist &= ~SGE_CSUM_FEATURES;
1794 if ((mask & IFCAP_RXCSUM) != 0 &&
1795 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
1796 ifp->if_capenable ^= IFCAP_RXCSUM;
1797 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1798 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1799 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1800 if ((mask & IFCAP_TSO4) != 0 &&
1801 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1802 ifp->if_capenable ^= IFCAP_TSO4;
1803 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1804 ifp->if_hwassist |= CSUM_TSO;
1806 ifp->if_hwassist &= ~CSUM_TSO;
1808 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1809 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1810 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1811 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1812 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1814 * Due to unknown reason, toggling VLAN hardware
1815 * tagging require interface reinitialization.
1817 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1818 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1819 ifp->if_capenable &=
1820 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1823 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1824 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1825 sge_init_locked(sc);
1828 VLAN_CAPABILITIES(ifp);
1833 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1839 mii = device_get_softc(sc->sge_miibus);
1840 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1843 error = ether_ioctl(ifp, command, data);
1851 sge_watchdog(struct sge_softc *sc)
1855 SGE_LOCK_ASSERT(sc);
1856 if (sc->sge_timer == 0 || --sc->sge_timer > 0)
1860 if ((sc->sge_flags & SGE_FLAG_LINK) == 0) {
1861 if (1 || bootverbose)
1862 device_printf(sc->sge_dev,
1863 "watchdog timeout (lost link)\n");
1865 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1866 sge_init_locked(sc);
1869 device_printf(sc->sge_dev, "watchdog timeout\n");
1872 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1873 sge_init_locked(sc);
1874 if (!IFQ_DRV_IS_EMPTY(&sc->sge_ifp->if_snd))
1875 sge_start_locked(ifp);
1879 * Stop the adapter and free any mbufs allocated to the
1883 sge_stop(struct sge_softc *sc)
1889 SGE_LOCK_ASSERT(sc);
1892 callout_stop(&sc->sge_stat_ch);
1893 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1895 CSR_WRITE_4(sc, IntrMask, 0);
1896 CSR_READ_4(sc, IntrMask);
1897 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
1898 /* Stop TX/RX MAC. */
1899 CSR_WRITE_4(sc, TX_CTL, 0x1a00);
1900 CSR_WRITE_4(sc, RX_CTL, 0x1a00);
1901 /* XXX Can we assume active DMA cycles gone? */
1903 CSR_WRITE_4(sc, IntrMask, 0);
1904 CSR_WRITE_4(sc, IntrStatus, 0xffffffff);
1906 sc->sge_flags &= ~SGE_FLAG_LINK;
1907 sge_list_rx_free(sc);
1908 sge_list_tx_free(sc);