2 * Copyright (c) 2000-2004 Taku YAMAMOTO <taku@tackymt.homeip.net>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * maestro.c,v 1.23.2.1 2003/10/03 18:21:38 taku Exp
32 * Part of this code (especially in many magic numbers) was heavily inspired
33 * by the Linux driver originally written by
34 * Alan Cox <alan.cox@linux.org>, modified heavily by
35 * Zach Brown <zab@zabbo.net>.
37 * busdma()-ize and buffer size reduction were suggested by
38 * Cameron Grant <cg@freebsd.org>.
39 * Also he showed me the way to use busdma() suite.
41 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
43 * Munehiro Matsuda <haro@tk.kubota.co.jp>,
44 * who brought patches based on the Linux driver with some simplification.
46 * Hardware volume controller was implemented by
47 * John Baldwin <jhb@freebsd.org>.
50 #ifdef HAVE_KERNEL_OPTION_HEADERS
54 #include <dev/sound/pcm/sound.h>
55 #include <dev/sound/pcm/ac97.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
59 #include <dev/sound/pci/maestro_reg.h>
61 SND_DECLARE_FILE("$FreeBSD$");
64 * PCI IDs of supported chips:
66 * MAESTRO-1 0x01001285
67 * MAESTRO-2 0x1968125d
68 * MAESTRO-2E 0x1978125d
71 #define MAESTRO_1_PCI_ID 0x01001285
72 #define MAESTRO_2_PCI_ID 0x1968125d
73 #define MAESTRO_2E_PCI_ID 0x1978125d
75 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
76 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
79 # if AGG_MAXPLAYCH > 4
81 # define AGG_MAXPLAYCH 4
84 # define AGG_MAXPLAYCH 4
87 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
91 #if __FreeBSD_version < 500000
92 # define critical_enter() disable_intr()
93 # define critical_exit() enable_intr()
97 #define PCIR_BAR(x) (PCIR_MAPS + (x) * 4)
101 /* -----------------------------
106 struct agg_info *parent;
108 /* FreeBSD newpcm related */
109 struct pcm_channel *channel;
110 struct snd_dbuf *buffer;
113 bus_addr_t phys; /* channel buffer physical address */
114 bus_addr_t base; /* channel buffer segment base */
115 u_int32_t blklen; /* DMA block length in WORDs */
116 u_int32_t buflen; /* channel buffer length in WORDs */
120 unsigned qs16 : 1; /* quantum size is 16bit */
121 unsigned us : 1; /* in unsigned format */
126 struct agg_info *parent;
128 /* FreeBSD newpcm related */
129 struct pcm_channel *channel;
130 struct snd_dbuf *buffer;
133 bus_addr_t phys; /* channel buffer physical address */
134 bus_addr_t base; /* channel buffer segment base */
135 u_int32_t blklen; /* DMA block length in WORDs */
136 u_int32_t buflen; /* channel buffer length in WORDs */
141 int16_t *src; /* stereo peer buffer */
142 int16_t *sink; /* channel buffer pointer */
143 volatile u_int32_t hwptr; /* ready point in 16bit sample */
147 /* FreeBSD newbus related */
150 /* I wonder whether bus_space_* are in common in *BSD... */
151 struct resource *reg;
154 bus_space_handle_t sh;
156 struct resource *irq;
160 bus_dma_tag_t buf_dmat;
161 bus_dma_tag_t stat_dmat;
163 /* FreeBSD SMPng related */
164 struct mtx lock; /* mutual exclusion */
165 /* FreeBSD newpcm related */
166 struct ac97_info *codec;
169 u_int8_t *stat; /* status buffer pointer */
170 bus_addr_t phys; /* status buffer physical address */
171 unsigned int bufsz; /* channel buffer size in bytes */
173 volatile u_int active;
174 struct agg_chinfo pch[AGG_MAXPLAYCH];
175 struct agg_rchinfo rch;
176 volatile u_int8_t curpwr; /* current power status: D[0-3] */
180 /* -----------------------------
183 static unsigned int powerstate_active = PCI_POWERSTATE_D1;
184 #ifdef MAESTRO_AGGRESSIVE_POWERSAVE
185 static unsigned int powerstate_idle = PCI_POWERSTATE_D2;
187 static unsigned int powerstate_idle = PCI_POWERSTATE_D1;
189 static unsigned int powerstate_init = PCI_POWERSTATE_D2;
191 /* XXX: this should move to a device specific sysctl dev.pcm.X.debug.Y via
192 device_get_sysctl_*() as discussed on multimedia@ in msg-id
193 <861wujij2q.fsf@xps.des.no> */
194 SYSCTL_NODE(_debug, OID_AUTO, maestro, CTLFLAG_RD, 0, "");
195 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_active, CTLFLAG_RW,
196 &powerstate_active, 0, "The Dx power state when active (0-1)");
197 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_idle, CTLFLAG_RW,
198 &powerstate_idle, 0, "The Dx power state when idle (0-2)");
199 SYSCTL_UINT(_debug_maestro, OID_AUTO, powerstate_init, CTLFLAG_RW,
201 "The Dx power state prior to the first use (0-2)");
204 /* -----------------------------
208 static void agg_sleep(struct agg_info*, const char *wmesg, int msec);
210 static __inline u_int32_t agg_rd(struct agg_info*, int, int size);
211 static __inline void agg_wr(struct agg_info*, int, u_int32_t data,
213 static int agg_rdcodec(struct agg_info*, int);
214 static int agg_wrcodec(struct agg_info*, int, u_int32_t);
216 static void ringbus_setdest(struct agg_info*, int, int);
218 static u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
219 static void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
220 static u_int16_t wp_rdapu(struct agg_info*, unsigned, u_int16_t);
221 static void wp_wrapu(struct agg_info*, unsigned, u_int16_t, u_int16_t);
222 static void wp_settimer(struct agg_info*, u_int);
223 static void wp_starttimer(struct agg_info*);
224 static void wp_stoptimer(struct agg_info*);
227 static u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
229 static void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
231 static u_int16_t wc_rdchctl(struct agg_info*, int);
233 static void wc_wrchctl(struct agg_info*, int, u_int16_t);
235 static void agg_stopclock(struct agg_info*, int part, int st);
237 static void agg_initcodec(struct agg_info*);
238 static void agg_init(struct agg_info*);
239 static void agg_power(struct agg_info*, int);
241 static void aggch_start_dac(struct agg_chinfo*);
242 static void aggch_stop_dac(struct agg_chinfo*);
243 static void aggch_start_adc(struct agg_rchinfo*);
244 static void aggch_stop_adc(struct agg_rchinfo*);
245 static void aggch_feed_adc_stereo(struct agg_rchinfo*);
246 static void aggch_feed_adc_mono(struct agg_rchinfo*);
248 #ifdef AGG_JITTER_CORRECTION
249 static void suppress_jitter(struct agg_chinfo*);
250 static void suppress_rec_jitter(struct agg_rchinfo*);
253 static void set_timer(struct agg_info*);
255 static void agg_intr(void *);
256 static int agg_probe(device_t);
257 static int agg_attach(device_t);
258 static int agg_detach(device_t);
259 static int agg_suspend(device_t);
260 static int agg_resume(device_t);
261 static int agg_shutdown(device_t);
263 static void *dma_malloc(bus_dma_tag_t, u_int32_t, bus_addr_t*);
264 static void dma_free(bus_dma_tag_t, void *);
267 /* -----------------------------
272 #define agg_lock(sc) snd_mtxlock(&((sc)->lock))
273 #define agg_unlock(sc) snd_mtxunlock(&((sc)->lock))
276 agg_sleep(struct agg_info *sc, const char *wmesg, int msec)
280 timo = msec * hz / 1000;
283 msleep(sc, &sc->lock, PWAIT, wmesg, timo);
289 static __inline u_int32_t
290 agg_rd(struct agg_info *sc, int regno, int size)
294 return bus_space_read_1(sc->st, sc->sh, regno);
296 return bus_space_read_2(sc->st, sc->sh, regno);
298 return bus_space_read_4(sc->st, sc->sh, regno);
300 return ~(u_int32_t)0;
304 #define AGG_RD(sc, regno, size) \
305 bus_space_read_##size( \
306 ((struct agg_info*)(sc))->st, \
307 ((struct agg_info*)(sc))->sh, (regno))
310 agg_wr(struct agg_info *sc, int regno, u_int32_t data, int size)
314 bus_space_write_1(sc->st, sc->sh, regno, data);
317 bus_space_write_2(sc->st, sc->sh, regno, data);
320 bus_space_write_4(sc->st, sc->sh, regno, data);
325 #define AGG_WR(sc, regno, data, size) \
326 bus_space_write_##size( \
327 ((struct agg_info*)(sc))->st, \
328 ((struct agg_info*)(sc))->sh, (regno), (data))
330 /* -------------------------------------------------------------------- */
335 agg_codec_wait4idle(struct agg_info *ess)
339 while (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK) {
342 DELAY(2); /* 20.8us / 13 */
349 agg_rdcodec(struct agg_info *ess, int regno)
353 /* We have to wait for a SAFE time to write addr/data */
354 if (agg_codec_wait4idle(ess)) {
355 /* Timed out. No read performed. */
356 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
360 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_READ | regno, 1);
361 /*DELAY(21); * AC97 cycle = 20.8usec */
363 /* Wait for data retrieve */
364 if (!agg_codec_wait4idle(ess)) {
365 ret = AGG_RD(ess, PORT_CODEC_REG, 2);
367 /* Timed out. No read performed. */
368 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
376 agg_wrcodec(struct agg_info *ess, int regno, u_int32_t data)
378 /* We have to wait for a SAFE time to write addr/data */
379 if (agg_codec_wait4idle(ess)) {
380 /* Timed out. Abort writing. */
381 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
385 AGG_WR(ess, PORT_CODEC_REG, data, 2);
386 AGG_WR(ess, PORT_CODEC_CMD, CODEC_CMD_WRITE | regno, 1);
388 /* Wait for write completion */
389 if (agg_codec_wait4idle(ess)) {
391 device_printf(ess->dev, "agg_wrcodec() RW_DONE timed out.\n");
399 ringbus_setdest(struct agg_info *ess, int src, int dest)
403 data = AGG_RD(ess, PORT_RINGBUS_CTRL, 4);
404 data &= ~(0xfU << src);
405 data |= (0xfU & dest) << src;
406 AGG_WR(ess, PORT_RINGBUS_CTRL, data, 4);
409 /* -------------------------------------------------------------------- */
414 wp_rdreg(struct agg_info *ess, u_int16_t reg)
416 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
417 return AGG_RD(ess, PORT_DSP_DATA, 2);
421 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
423 AGG_WR(ess, PORT_DSP_INDEX, reg, 2);
424 AGG_WR(ess, PORT_DSP_DATA, data, 2);
428 wp_wait_data(struct agg_info *ess, u_int16_t data)
432 while (AGG_RD(ess, PORT_DSP_DATA, 2) != data) {
436 AGG_WR(ess, PORT_DSP_DATA, data, 2);
443 wp_rdapu(struct agg_info *ess, unsigned ch, u_int16_t reg)
445 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
446 if (wp_wait_data(ess, reg | (ch << 4)) != 0)
447 device_printf(ess->dev, "wp_rdapu() indexing timed out.\n");
448 return wp_rdreg(ess, WPREG_DATA_PORT);
452 wp_wrapu(struct agg_info *ess, unsigned ch, u_int16_t reg, u_int16_t data)
454 wp_wrreg(ess, WPREG_CRAM_PTR, reg | (ch << 4));
455 if (wp_wait_data(ess, reg | (ch << 4)) == 0) {
456 wp_wrreg(ess, WPREG_DATA_PORT, data);
457 if (wp_wait_data(ess, data) != 0)
458 device_printf(ess->dev,
459 "wp_wrapu() write timed out.\n");
461 device_printf(ess->dev, "wp_wrapu() indexing timed out.\n");
466 apu_setparam(struct agg_info *ess, int apuch,
467 u_int32_t wpwa, u_int16_t size, int16_t pan, u_int dv)
469 wp_wrapu(ess, apuch, APUREG_WAVESPACE, (wpwa >> 8) & APU_64KPAGE_MASK);
470 wp_wrapu(ess, apuch, APUREG_CURPTR, wpwa);
471 wp_wrapu(ess, apuch, APUREG_ENDPTR, wpwa + size);
472 wp_wrapu(ess, apuch, APUREG_LOOPLEN, size);
473 wp_wrapu(ess, apuch, APUREG_ROUTING, 0);
474 wp_wrapu(ess, apuch, APUREG_AMPLITUDE, 0xf000);
475 wp_wrapu(ess, apuch, APUREG_POSITION, 0x8f00
476 | (APU_RADIUS_MASK & (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT))
477 | (APU_PAN_MASK & ((pan + PAN_FRONT) << APU_PAN_SHIFT)));
478 wp_wrapu(ess, apuch, APUREG_FREQ_LOBYTE,
479 APU_plus6dB | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
480 wp_wrapu(ess, apuch, APUREG_FREQ_HIWORD, dv >> 8);
484 wp_settimer(struct agg_info *ess, u_int divide)
488 RANGE(divide, 2, 32 << 7);
490 for (; divide > 32; divide >>= 1) {
495 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
498 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
499 wp_wrreg(ess, WPREG_TIMER_FREQ, 0x9000 |
500 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
501 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
505 wp_starttimer(struct agg_info *ess)
507 AGG_WR(ess, PORT_INT_STAT, 1, 2);
508 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_INT_ENABLED
509 | AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
510 wp_wrreg(ess, WPREG_TIMER_START, 1);
514 wp_stoptimer(struct agg_info *ess)
516 AGG_WR(ess, PORT_HOSTINT_CTRL, ~HOSTINT_CTRL_DSOUND_INT_ENABLED
517 & AGG_RD(ess, PORT_HOSTINT_CTRL, 2), 2);
518 AGG_WR(ess, PORT_INT_STAT, 1, 2);
519 wp_wrreg(ess, WPREG_TIMER_START, 0);
522 /* -------------------------------------------------------------------- */
528 wc_rdreg(struct agg_info *ess, u_int16_t reg)
530 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
531 return AGG_RD(ess, PORT_WAVCACHE_DATA, 2);
536 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
538 AGG_WR(ess, PORT_WAVCACHE_INDEX, reg, 2);
539 AGG_WR(ess, PORT_WAVCACHE_DATA, data, 2);
544 wc_rdchctl(struct agg_info *ess, int ch)
546 return wc_rdreg(ess, ch << 3);
551 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
553 wc_wrreg(ess, ch << 3, data);
556 /* -------------------------------------------------------------------- */
558 /* Power management */
560 agg_stopclock(struct agg_info *ess, int part, int st)
564 data = pci_read_config(ess->dev, CONF_ACPI_STOPCLOCK, 4);
566 if (st == PCI_POWERSTATE_D1)
567 data &= ~(1 << part);
570 if (st == PCI_POWERSTATE_D1 || st == PCI_POWERSTATE_D2)
571 data |= (0x10000 << part);
573 data &= ~(0x10000 << part);
574 pci_write_config(ess->dev, CONF_ACPI_STOPCLOCK, data, 4);
579 /* -----------------------------
584 agg_initcodec(struct agg_info* ess)
588 if (AGG_RD(ess, PORT_RINGBUS_CTRL, 4) & RINGBUS_CTRL_ACLINK_ENABLED) {
589 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
590 DELAY(104); /* 20.8us * (4 + 1) */
592 /* XXX - 2nd codec should be looked at. */
593 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_AC97_SWRESET, 4);
595 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
598 if (agg_rdcodec(ess, 0) < 0) {
599 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
602 /* Try cold reset. */
603 device_printf(ess->dev, "will perform cold reset.\n");
604 data = AGG_RD(ess, PORT_GPIO_DIR, 2);
605 if (pci_read_config(ess->dev, 0x58, 2) & 1)
607 data |= 0x009 & ~AGG_RD(ess, PORT_GPIO_DATA, 2);
608 AGG_WR(ess, PORT_GPIO_MASK, 0xff6, 2);
609 AGG_WR(ess, PORT_GPIO_DIR, data | 0x009, 2);
610 AGG_WR(ess, PORT_GPIO_DATA, 0x000, 2);
612 AGG_WR(ess, PORT_GPIO_DATA, 0x001, 2);
614 AGG_WR(ess, PORT_GPIO_DATA, 0x009, 2);
615 agg_sleep(ess, "agginicd", 500);
616 AGG_WR(ess, PORT_GPIO_DIR, data, 2);
617 DELAY(84); /* 20.8us * 4 */
618 AGG_WR(ess, PORT_RINGBUS_CTRL, RINGBUS_CTRL_ACLINK_ENABLED, 4);
624 agg_init(struct agg_info* ess)
628 /* Setup PCI config registers. */
630 /* Disable all legacy emulations. */
631 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
632 data |= LEGACY_DISABLED;
633 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
635 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
636 * Enable posted write.
637 * Prefer PCI timing rather than that of ISA.
639 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
641 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
642 data &= ~MAESTRO_SWAP_LR;
643 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
645 /* Turn off unused parts if necessary. */
646 /* consult CONF_MAESTRO. */
647 if (data & MAESTRO_SPDIF)
648 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D2);
650 agg_stopclock(ess, ACPI_PART_SPDIF, PCI_POWERSTATE_D1);
651 if (data & MAESTRO_HWVOL)
652 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D3);
654 agg_stopclock(ess, ACPI_PART_HW_VOL, PCI_POWERSTATE_D1);
656 /* parts that never be used */
657 agg_stopclock(ess, ACPI_PART_978, PCI_POWERSTATE_D1);
658 agg_stopclock(ess, ACPI_PART_DAA, PCI_POWERSTATE_D1);
659 agg_stopclock(ess, ACPI_PART_GPIO, PCI_POWERSTATE_D1);
660 agg_stopclock(ess, ACPI_PART_SB, PCI_POWERSTATE_D1);
661 agg_stopclock(ess, ACPI_PART_FM, PCI_POWERSTATE_D1);
662 agg_stopclock(ess, ACPI_PART_MIDI, PCI_POWERSTATE_D1);
663 agg_stopclock(ess, ACPI_PART_GAME_PORT, PCI_POWERSTATE_D1);
665 /* parts that will be used only when play/recording */
666 agg_stopclock(ess, ACPI_PART_WP, PCI_POWERSTATE_D2);
668 /* parts that should always be turned on */
669 agg_stopclock(ess, ACPI_PART_CODEC_CLOCK, PCI_POWERSTATE_D3);
670 agg_stopclock(ess, ACPI_PART_GLUE, PCI_POWERSTATE_D3);
671 agg_stopclock(ess, ACPI_PART_PCI_IF, PCI_POWERSTATE_D3);
672 agg_stopclock(ess, ACPI_PART_RINGBUS, PCI_POWERSTATE_D3);
674 /* Reset direct sound. */
675 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_SOFT_RESET, 2);
677 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
679 AGG_WR(ess, PORT_HOSTINT_CTRL, HOSTINT_CTRL_DSOUND_RESET, 2);
681 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
684 /* Enable hardware volume control interruption. */
685 if (data & MAESTRO_HWVOL) /* XXX - why not use device flags? */
686 AGG_WR(ess, PORT_HOSTINT_CTRL,HOSTINT_CTRL_HWVOL_ENABLED, 2);
688 /* Setup Wave Processor. */
690 /* Enable WaveCache, set DMA base address. */
691 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
692 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
693 wp_wrreg(ess, WPREG_CRAM_DATA, 0);
695 AGG_WR(ess, PORT_WAVCACHE_CTRL,
696 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_2MB | WAVCACHE_SGC_32_47, 2);
698 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
699 wc_wrreg(ess, data, ess->phys >> WAVCACHE_BASEADDR_SHIFT);
701 /* Setup Codec/Ringbus. */
703 AGG_WR(ess, PORT_RINGBUS_CTRL,
704 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED, 4);
706 wp_wrreg(ess, 0x08, 0xB004);
707 wp_wrreg(ess, 0x09, 0x001B);
708 wp_wrreg(ess, 0x0A, 0x8000);
709 wp_wrreg(ess, 0x0B, 0x3F37);
710 wp_wrreg(ess, WPREG_BASE, 0x8598); /* Parallel I/O */
711 wp_wrreg(ess, WPREG_BASE + 1, 0x7632);
712 ringbus_setdest(ess, RINGBUS_SRC_ADC,
713 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
714 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
715 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
717 /* Enable S/PDIF if necessary. */
718 if (pci_read_config(ess->dev, CONF_MAESTRO, 4) & MAESTRO_SPDIF)
719 /* XXX - why not use device flags? */
720 AGG_WR(ess, PORT_RINGBUS_CTRL_B, RINGBUS_CTRL_SPDIF |
721 AGG_RD(ess, PORT_RINGBUS_CTRL_B, 1), 1);
723 /* Setup ASSP. Needed for Dell Inspiron 7500? */
724 AGG_WR(ess, PORT_ASSP_CTRL_B, 0x00, 1);
725 AGG_WR(ess, PORT_ASSP_CTRL_A, 0x03, 1);
726 AGG_WR(ess, PORT_ASSP_CTRL_C, 0x00, 1);
730 * There seems to be speciality with NEC systems.
732 switch (pci_get_subvendor(ess->dev)
733 | (pci_get_subdevice(ess->dev) << 16)) {
736 /* Matthew Braithwaite <matt@braithwaite.net> reported that
737 * NEC Versa LX doesn't need GPIO operation. */
738 AGG_WR(ess, PORT_GPIO_MASK, 0x9ff, 2);
739 AGG_WR(ess, PORT_GPIO_DIR,
740 AGG_RD(ess, PORT_GPIO_DIR, 2) | 0x600, 2);
741 AGG_WR(ess, PORT_GPIO_DATA, 0x200, 2);
746 /* Deals power state transition. Must be called with softc->lock held. */
748 agg_power(struct agg_info *ess, int status)
752 lastpwr = ess->curpwr;
753 if (lastpwr == status)
757 case PCI_POWERSTATE_D0:
758 case PCI_POWERSTATE_D1:
760 case PCI_POWERSTATE_D2:
761 pci_set_powerstate(ess->dev, status);
762 /* Turn on PCM-related parts. */
763 agg_wrcodec(ess, AC97_REG_POWER, 0);
766 if ((agg_rdcodec(ess, AC97_REG_POWER) & 3) != 3)
767 device_printf(ess->dev,
768 "warning: codec not ready.\n");
770 AGG_WR(ess, PORT_RINGBUS_CTRL,
771 (AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
772 & ~RINGBUS_CTRL_ACLINK_ENABLED)
773 | RINGBUS_CTRL_RINGBUS_ENABLED, 4);
775 AGG_WR(ess, PORT_RINGBUS_CTRL,
776 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
777 | RINGBUS_CTRL_ACLINK_ENABLED, 4);
779 case PCI_POWERSTATE_D3:
781 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
785 case PCI_POWERSTATE_D0:
786 case PCI_POWERSTATE_D1:
787 pci_set_powerstate(ess->dev, status);
791 case PCI_POWERSTATE_D2:
793 case PCI_POWERSTATE_D3:
795 pci_set_powerstate(ess->dev, PCI_POWERSTATE_D0);
799 case PCI_POWERSTATE_D0:
800 case PCI_POWERSTATE_D1:
801 /* Turn off PCM-related parts. */
802 AGG_WR(ess, PORT_RINGBUS_CTRL,
803 AGG_RD(ess, PORT_RINGBUS_CTRL, 4)
804 & ~RINGBUS_CTRL_RINGBUS_ENABLED, 4);
806 agg_wrcodec(ess, AC97_REG_POWER, 0x300);
810 pci_set_powerstate(ess->dev, status);
812 case PCI_POWERSTATE_D3:
813 /* Entirely power down. */
814 agg_wrcodec(ess, AC97_REG_POWER, 0xdf00);
816 AGG_WR(ess, PORT_RINGBUS_CTRL, 0, 4);
818 if (lastpwr != PCI_POWERSTATE_D2)
820 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
821 AGG_WR(ess, PORT_HOSTINT_STAT, 0xff, 1);
822 pci_set_powerstate(ess->dev, status);
825 /* Invalid power state; let it ignored. */
830 ess->curpwr = status;
833 /* -------------------------------------------------------------------- */
835 /* Channel controller. */
838 aggch_start_dac(struct agg_chinfo *ch)
842 u_int16_t size, apuch, wtbar, wcreg, aputype;
847 wpwa = (ch->phys - ch->base) >> 1;
848 wtbar = 0xc & (wpwa >> WPWA_WTBAR_SHIFT(2));
849 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
851 apuch = (ch->num << 1) | 32;
852 pan = PAN_RIGHT - PAN_FRONT;
855 wcreg |= WAVCACHE_CHCTL_STEREO;
857 aputype = APUTYPE_16BITSTEREO;
862 aputype = APUTYPE_8BITSTEREO;
866 aputype = APUTYPE_16BITLINEAR;
868 aputype = APUTYPE_8BITLINEAR;
873 wcreg |= WAVCACHE_CHCTL_U8;
876 wtbar = (wtbar >> 1) + 4;
878 dv = (((speed % 48000) << 16) + 24000) / 48000
879 + ((speed / 48000) << 16);
881 agg_lock(ch->parent);
882 agg_power(ch->parent, powerstate_active);
884 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar,
885 ch->base >> WAVCACHE_BASEADDR_SHIFT);
886 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 1,
887 ch->base >> WAVCACHE_BASEADDR_SHIFT);
889 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 2,
890 ch->base >> WAVCACHE_BASEADDR_SHIFT);
891 wc_wrreg(ch->parent, WAVCACHE_WTBAR + wtbar + 3,
892 ch->base >> WAVCACHE_BASEADDR_SHIFT);
894 wc_wrchctl(ch->parent, apuch, wcreg);
895 wc_wrchctl(ch->parent, apuch + 1, wcreg);
897 apu_setparam(ch->parent, apuch, wpwa, size, pan, dv);
900 wpwa |= (WPWA_STEREO >> 1);
901 apu_setparam(ch->parent, apuch + 1, wpwa, size, -pan, dv);
904 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
905 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
906 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
907 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
910 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
911 (aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
914 /* to mark that this channel is ready for intr. */
915 ch->parent->active |= (1 << ch->num);
917 set_timer(ch->parent);
918 wp_starttimer(ch->parent);
919 agg_unlock(ch->parent);
923 aggch_stop_dac(struct agg_chinfo *ch)
925 agg_lock(ch->parent);
927 /* to mark that this channel no longer needs further intrs. */
928 ch->parent->active &= ~(1 << ch->num);
930 wp_wrapu(ch->parent, (ch->num << 1) | 32, APUREG_APUTYPE,
931 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
932 wp_wrapu(ch->parent, (ch->num << 1) | 33, APUREG_APUTYPE,
933 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
935 if (ch->parent->active) {
936 set_timer(ch->parent);
937 wp_starttimer(ch->parent);
939 wp_stoptimer(ch->parent);
940 agg_power(ch->parent, powerstate_idle);
942 agg_unlock(ch->parent);
946 aggch_start_adc(struct agg_rchinfo *ch)
948 bus_addr_t wpwa, wpwa2;
949 u_int16_t wcreg, wcreg2;
953 /* speed > 48000 not cared */
954 dv = ((ch->speed << 16) + 24000) / 48000;
956 /* RATECONV doesn't seem to like dv == 0x10000. */
961 wpwa = (ch->srcphys - ch->base) >> 1;
962 wpwa2 = (ch->srcphys + ch->parent->bufsz/2 - ch->base) >> 1;
963 wcreg = (ch->srcphys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
964 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
965 pan = PAN_LEFT - PAN_FRONT;
967 wpwa = (ch->phys - ch->base) >> 1;
968 wpwa2 = (ch->srcphys - ch->base) >> 1;
969 wcreg = (ch->phys - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
970 wcreg2 = (ch->base - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
974 agg_lock(ch->parent);
977 agg_power(ch->parent, powerstate_active);
979 /* Invalidate WaveCache. */
980 wc_wrchctl(ch->parent, 0, wcreg | WAVCACHE_CHCTL_STEREO);
981 wc_wrchctl(ch->parent, 1, wcreg | WAVCACHE_CHCTL_STEREO);
982 wc_wrchctl(ch->parent, 2, wcreg2 | WAVCACHE_CHCTL_STEREO);
983 wc_wrchctl(ch->parent, 3, wcreg2 | WAVCACHE_CHCTL_STEREO);
985 /* Load APU registers. */
986 /* APU #0 : Sample rate converter for left/center. */
987 apu_setparam(ch->parent, 0, WPWA_USE_SYSMEM | wpwa,
988 ch->buflen >> ch->stereo, 0, dv);
989 wp_wrapu(ch->parent, 0, APUREG_AMPLITUDE, 0);
990 wp_wrapu(ch->parent, 0, APUREG_ROUTING, 2 << APU_DATASRC_A_SHIFT);
992 /* APU #1 : Sample rate converter for right. */
993 apu_setparam(ch->parent, 1, WPWA_USE_SYSMEM | wpwa2,
994 ch->buflen >> ch->stereo, 0, dv);
995 wp_wrapu(ch->parent, 1, APUREG_AMPLITUDE, 0);
996 wp_wrapu(ch->parent, 1, APUREG_ROUTING, 3 << APU_DATASRC_A_SHIFT);
998 /* APU #2 : Input mixer for left. */
999 apu_setparam(ch->parent, 2, WPWA_USE_SYSMEM | 0,
1000 ch->parent->bufsz >> 2, pan, 0x10000);
1001 wp_wrapu(ch->parent, 2, APUREG_AMPLITUDE, 0);
1002 wp_wrapu(ch->parent, 2, APUREG_EFFECT_GAIN, 0xf0);
1003 wp_wrapu(ch->parent, 2, APUREG_ROUTING, 0x15 << APU_DATASRC_A_SHIFT);
1005 /* APU #3 : Input mixer for right. */
1006 apu_setparam(ch->parent, 3, WPWA_USE_SYSMEM | (ch->parent->bufsz >> 2),
1007 ch->parent->bufsz >> 2, -pan, 0x10000);
1008 wp_wrapu(ch->parent, 3, APUREG_AMPLITUDE, 0);
1009 wp_wrapu(ch->parent, 3, APUREG_EFFECT_GAIN, 0xf0);
1010 wp_wrapu(ch->parent, 3, APUREG_ROUTING, 0x14 << APU_DATASRC_A_SHIFT);
1012 /* to mark this channel ready for intr. */
1013 ch->parent->active |= (1 << ch->parent->playchns);
1017 wp_wrapu(ch->parent, 0, APUREG_APUTYPE,
1018 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1019 wp_wrapu(ch->parent, 1, APUREG_APUTYPE,
1020 (APUTYPE_RATECONV << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
1021 wp_wrapu(ch->parent, 2, APUREG_APUTYPE,
1022 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1023 wp_wrapu(ch->parent, 3, APUREG_APUTYPE,
1024 (APUTYPE_INPUTMIXER << APU_APUTYPE_SHIFT) | 0xf);
1027 set_timer(ch->parent);
1028 wp_starttimer(ch->parent);
1029 agg_unlock(ch->parent);
1033 aggch_stop_adc(struct agg_rchinfo *ch)
1037 agg_lock(ch->parent);
1039 /* to mark that this channel no longer needs further intrs. */
1040 ch->parent->active &= ~(1 << ch->parent->playchns);
1042 for (apuch = 0; apuch < 4; apuch++)
1043 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
1044 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
1046 if (ch->parent->active) {
1047 set_timer(ch->parent);
1048 wp_starttimer(ch->parent);
1050 wp_stoptimer(ch->parent);
1051 agg_power(ch->parent, powerstate_idle);
1053 agg_unlock(ch->parent);
1057 * Feed from L/R channel of ADC to destination with stereo interleaving.
1058 * This function expects n not overwrapping the buffer boundary.
1059 * Note that n is measured in sample unit.
1061 * XXX - this function works in 16bit stereo format only.
1064 interleave(int16_t *l, int16_t *r, int16_t *p, unsigned n)
1068 for (end = l + n; l < end; ) {
1075 aggch_feed_adc_stereo(struct agg_rchinfo *ch)
1080 agg_lock(ch->parent);
1081 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1082 agg_unlock(ch->parent);
1083 cur -= 0xffff & ((ch->srcphys - ch->base) >> 1);
1085 src2 = ch->src + ch->parent->bufsz/4;
1088 interleave(ch->src + last, src2 + last,
1089 ch->sink + 2*last, ch->buflen/2 - last);
1090 interleave(ch->src, src2,
1092 } else if (cur > last)
1093 interleave(ch->src + last, src2 + last,
1094 ch->sink + 2*last, cur - last);
1099 * Feed from R channel of ADC and mixdown to destination L/center.
1100 * This function expects n not overwrapping the buffer boundary.
1101 * Note that n is measured in sample unit.
1103 * XXX - this function works in 16bit monoral format only.
1106 mixdown(int16_t *src, int16_t *dest, unsigned n)
1110 for (end = dest + n; dest < end; dest++)
1111 *dest = (int16_t)(((int)*dest - (int)*src++) / 2);
1115 aggch_feed_adc_mono(struct agg_rchinfo *ch)
1119 agg_lock(ch->parent);
1120 cur = wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1121 agg_unlock(ch->parent);
1122 cur -= 0xffff & ((ch->phys - ch->base) >> 1);
1126 mixdown(ch->src + last, ch->sink + last, ch->buflen - last);
1127 mixdown(ch->src, ch->sink, cur);
1128 } else if (cur > last)
1129 mixdown(ch->src + last, ch->sink + last, cur - last);
1133 #ifdef AGG_JITTER_CORRECTION
1135 * Stereo jitter suppressor.
1136 * Sometimes playback pointers differ in stereo-paired channels.
1137 * Calling this routine within intr fixes the problem.
1140 suppress_jitter(struct agg_chinfo *ch)
1143 int cp1, cp2, diff /*, halfsize*/ ;
1145 /*halfsize = (ch->qs16? ch->buflen >> 2 : ch->buflen >> 1);*/
1146 cp1 = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1147 cp2 = wp_rdapu(ch->parent, (ch->num << 1) | 33, APUREG_CURPTR);
1149 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1150 if (diff > 1 /* && diff < halfsize*/ )
1151 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1157 suppress_rec_jitter(struct agg_rchinfo *ch)
1159 int cp1, cp2, diff /*, halfsize*/ ;
1161 /*halfsize = (ch->stereo? ch->buflen >> 2 : ch->buflen >> 1);*/
1162 cp1 = (ch->stereo? ch->parent->bufsz >> 2 : ch->parent->bufsz >> 1)
1163 + wp_rdapu(ch->parent, 0, APUREG_CURPTR);
1164 cp2 = wp_rdapu(ch->parent, 1, APUREG_CURPTR);
1166 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1167 if (diff > 1 /* && diff < halfsize*/ )
1168 AGG_WR(ch->parent, PORT_DSP_DATA, cp1, 2);
1174 calc_timer_div(struct agg_chinfo *ch)
1181 printf("snd_maestro: pch[%d].speed == 0, which shouldn't\n",
1186 return (48000 * (ch->blklen << (!ch->qs16 + !ch->stereo))
1187 + speed - 1) / speed;
1191 calc_timer_div_rch(struct agg_rchinfo *ch)
1198 printf("snd_maestro: rch.speed == 0, which shouldn't\n");
1202 return (48000 * (ch->blklen << (!ch->stereo))
1203 + speed - 1) / speed;
1207 set_timer(struct agg_info *ess)
1210 u_int dv = 32 << 7, newdv;
1212 for (i = 0; i < ess->playchns; i++)
1213 if ((ess->active & (1 << i)) &&
1214 (dv > (newdv = calc_timer_div(ess->pch + i))))
1216 if ((ess->active & (1 << i)) &&
1217 (dv > (newdv = calc_timer_div_rch(&ess->rch))))
1220 wp_settimer(ess, dv);
1224 /* -----------------------------
1228 /* AC97 mixer interface. */
1231 agg_ac97_init(kobj_t obj, void *sc)
1233 struct agg_info *ess = sc;
1235 return (AGG_RD(ess, PORT_CODEC_STAT, 1) & CODEC_STAT_MASK)? 0 : 1;
1239 agg_ac97_read(kobj_t obj, void *sc, int regno)
1241 struct agg_info *ess = sc;
1244 /* XXX sound locking violation: agg_lock(ess); */
1245 ret = agg_rdcodec(ess, regno);
1246 /* agg_unlock(ess); */
1251 agg_ac97_write(kobj_t obj, void *sc, int regno, u_int32_t data)
1253 struct agg_info *ess = sc;
1256 /* XXX sound locking violation: agg_lock(ess); */
1257 ret = agg_wrcodec(ess, regno, data);
1258 /* agg_unlock(ess); */
1263 static kobj_method_t agg_ac97_methods[] = {
1264 KOBJMETHOD(ac97_init, agg_ac97_init),
1265 KOBJMETHOD(ac97_read, agg_ac97_read),
1266 KOBJMETHOD(ac97_write, agg_ac97_write),
1269 AC97_DECLARE(agg_ac97);
1272 /* -------------------------------------------------------------------- */
1274 /* Playback channel. */
1277 aggpch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1278 struct pcm_channel *c, int dir)
1280 struct agg_info *ess = devinfo;
1281 struct agg_chinfo *ch;
1282 bus_addr_t physaddr;
1285 KASSERT((dir == PCMDIR_PLAY),
1286 ("aggpch_init() called for RECORDING channel!"));
1287 ch = ess->pch + ess->playchns;
1292 ch->num = ess->playchns;
1294 p = dma_malloc(ess->buf_dmat, ess->bufsz, &physaddr);
1297 ch->phys = physaddr;
1298 ch->base = physaddr & ((~(bus_addr_t)0) << WAVCACHE_BASEADDR_SHIFT);
1300 sndbuf_setup(b, p, ess->bufsz);
1301 ch->blklen = sndbuf_getblksz(b) / 2;
1302 ch->buflen = sndbuf_getsize(b) / 2;
1309 adjust_pchbase(struct agg_chinfo *chans, u_int n, u_int size)
1311 struct agg_chinfo *pchs[AGG_MAXPLAYCH];
1315 /* sort pchs by phys address */
1316 for (i = 0; i < n; i++) {
1317 for (j = 0; j < i; j++)
1318 if (chans[i].phys < pchs[j]->phys) {
1319 for (k = i; k > j; k--)
1320 pchs[k] = pchs[k - 1];
1323 pchs[j] = chans + i;
1326 /* use new base register if next buffer can not be addressed
1327 via current base. */
1328 #define BASE_SHIFT (WPWA_WTBAR_SHIFT(2) + 2 + 1)
1329 base = pchs[0]->base;
1330 for (k = 1, i = 1; i < n; i++) {
1331 if (pchs[i]->phys + size - base >= 1 << BASE_SHIFT)
1332 /* not addressable: assign new base */
1333 base = (pchs[i]->base -= k++ << BASE_SHIFT);
1335 pchs[i]->base = base;
1340 printf("Total of %d bases are assigned.\n", k);
1341 for (i = 0; i < n; i++) {
1342 printf("ch.%d: phys 0x%llx, wpwa 0x%llx\n",
1343 i, (long long)chans[i].phys,
1344 (long long)(chans[i].phys -
1345 chans[i].base) >> 1);
1351 aggpch_free(kobj_t obj, void *data)
1353 struct agg_chinfo *ch = data;
1354 struct agg_info *ess = ch->parent;
1356 /* free up buffer - called after channel stopped */
1357 dma_free(ess->buf_dmat, sndbuf_getbuf(ch->buffer));
1359 /* return 0 if ok */
1364 aggpch_setformat(kobj_t obj, void *data, u_int32_t format)
1366 struct agg_chinfo *ch = data;
1368 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE)
1370 ch->stereo = ch->qs16 = ch->us = 0;
1371 if (AFMT_CHANNEL(format) > 1)
1374 if (format & AFMT_U8 || format & AFMT_S8) {
1375 if (format & AFMT_U8)
1383 aggpch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1386 ((struct agg_chinfo*)data)->speed = speed;
1392 aggpch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1394 struct agg_chinfo *ch = data;
1397 /* try to keep at least 20msec DMA space */
1398 blkcnt = (ch->speed << (ch->stereo + ch->qs16)) / (50 * blocksize);
1399 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1401 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1402 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1403 blkcnt = sndbuf_getblkcnt(ch->buffer);
1404 blocksize = sndbuf_getblksz(ch->buffer);
1406 sndbuf_setblkcnt(ch->buffer, blkcnt);
1407 sndbuf_setblksz(ch->buffer, blocksize);
1410 ch->blklen = blocksize / 2;
1411 ch->buflen = blkcnt * blocksize / 2;
1416 aggpch_trigger(kobj_t obj, void *data, int go)
1418 struct agg_chinfo *ch = data;
1421 case PCMTRIG_EMLDMAWR:
1424 aggch_start_dac(ch);
1435 aggpch_getptr(kobj_t obj, void *data)
1437 struct agg_chinfo *ch = data;
1440 agg_lock(ch->parent);
1441 cp = wp_rdapu(ch->parent, (ch->num << 1) | 32, APUREG_CURPTR);
1442 agg_unlock(ch->parent);
1444 return ch->qs16 && ch->stereo
1445 ? (cp << 2) - ((0xffff << 2) & (ch->phys - ch->base))
1446 : (cp << 1) - ((0xffff << 1) & (ch->phys - ch->base));
1449 static struct pcmchan_caps *
1450 aggpch_getcaps(kobj_t obj, void *data)
1452 static u_int32_t playfmt[] = {
1453 SND_FORMAT(AFMT_U8, 1, 0),
1454 SND_FORMAT(AFMT_U8, 2, 0),
1455 SND_FORMAT(AFMT_S8, 1, 0),
1456 SND_FORMAT(AFMT_S8, 2, 0),
1457 SND_FORMAT(AFMT_S16_LE, 1, 0),
1458 SND_FORMAT(AFMT_S16_LE, 2, 0),
1461 static struct pcmchan_caps playcaps = {8000, 48000, playfmt, 0};
1467 static kobj_method_t aggpch_methods[] = {
1468 KOBJMETHOD(channel_init, aggpch_init),
1469 KOBJMETHOD(channel_free, aggpch_free),
1470 KOBJMETHOD(channel_setformat, aggpch_setformat),
1471 KOBJMETHOD(channel_setspeed, aggpch_setspeed),
1472 KOBJMETHOD(channel_setblocksize, aggpch_setblocksize),
1473 KOBJMETHOD(channel_trigger, aggpch_trigger),
1474 KOBJMETHOD(channel_getptr, aggpch_getptr),
1475 KOBJMETHOD(channel_getcaps, aggpch_getcaps),
1478 CHANNEL_DECLARE(aggpch);
1481 /* -------------------------------------------------------------------- */
1483 /* Recording channel. */
1486 aggrch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
1487 struct pcm_channel *c, int dir)
1489 struct agg_info *ess = devinfo;
1490 struct agg_rchinfo *ch;
1493 KASSERT((dir == PCMDIR_REC),
1494 ("aggrch_init() called for PLAYBACK channel!"));
1501 /* Uses the bottom-half of the status buffer. */
1502 p = ess->stat + ess->bufsz;
1503 ch->phys = ess->phys + ess->bufsz;
1504 ch->base = ess->phys;
1505 ch->src = (int16_t *)(p + ess->bufsz);
1506 ch->srcphys = ch->phys + ess->bufsz;
1507 ch->sink = (int16_t *)p;
1509 sndbuf_setup(b, p, ess->bufsz);
1510 ch->blklen = sndbuf_getblksz(b) / 2;
1511 ch->buflen = sndbuf_getsize(b) / 2;
1517 aggrch_setformat(kobj_t obj, void *data, u_int32_t format)
1519 struct agg_rchinfo *ch = data;
1521 if (!(format & AFMT_S16_LE))
1523 if (AFMT_CHANNEL(format) > 1)
1531 aggrch_setspeed(kobj_t obj, void *data, u_int32_t speed)
1534 ((struct agg_rchinfo*)data)->speed = speed;
1540 aggrch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
1542 struct agg_rchinfo *ch = data;
1545 /* try to keep at least 20msec DMA space */
1546 blkcnt = (ch->speed << ch->stereo) / (25 * blocksize);
1547 RANGE(blkcnt, 2, ch->parent->bufsz / blocksize);
1549 if (sndbuf_getsize(ch->buffer) != blkcnt * blocksize) {
1550 sndbuf_resize(ch->buffer, blkcnt, blocksize);
1551 blkcnt = sndbuf_getblkcnt(ch->buffer);
1552 blocksize = sndbuf_getblksz(ch->buffer);
1554 sndbuf_setblkcnt(ch->buffer, blkcnt);
1555 sndbuf_setblksz(ch->buffer, blocksize);
1558 ch->blklen = blocksize / 2;
1559 ch->buflen = blkcnt * blocksize / 2;
1564 aggrch_trigger(kobj_t obj, void *sc, int go)
1566 struct agg_rchinfo *ch = sc;
1569 case PCMTRIG_EMLDMARD:
1571 aggch_feed_adc_stereo(ch);
1573 aggch_feed_adc_mono(ch);
1576 aggch_start_adc(ch);
1587 aggrch_getptr(kobj_t obj, void *sc)
1589 struct agg_rchinfo *ch = sc;
1591 return ch->stereo? ch->hwptr << 2 : ch->hwptr << 1;
1594 static struct pcmchan_caps *
1595 aggrch_getcaps(kobj_t obj, void *sc)
1597 static u_int32_t recfmt[] = {
1598 SND_FORMAT(AFMT_S16_LE, 1, 0),
1599 SND_FORMAT(AFMT_S16_LE, 2, 0),
1602 static struct pcmchan_caps reccaps = {8000, 48000, recfmt, 0};
1607 static kobj_method_t aggrch_methods[] = {
1608 KOBJMETHOD(channel_init, aggrch_init),
1609 /* channel_free: no-op */
1610 KOBJMETHOD(channel_setformat, aggrch_setformat),
1611 KOBJMETHOD(channel_setspeed, aggrch_setspeed),
1612 KOBJMETHOD(channel_setblocksize, aggrch_setblocksize),
1613 KOBJMETHOD(channel_trigger, aggrch_trigger),
1614 KOBJMETHOD(channel_getptr, aggrch_getptr),
1615 KOBJMETHOD(channel_getcaps, aggrch_getcaps),
1618 CHANNEL_DECLARE(aggrch);
1621 /* -----------------------------
1628 struct agg_info* ess = sc;
1629 register u_int8_t status;
1633 status = AGG_RD(ess, PORT_HOSTINT_STAT, 1);
1637 /* Acknowledge intr. */
1638 AGG_WR(ess, PORT_HOSTINT_STAT, status, 1);
1640 if (status & HOSTINT_STAT_DSOUND) {
1641 #ifdef AGG_JITTER_CORRECTION
1644 if (ess->curpwr <= PCI_POWERSTATE_D1) {
1645 AGG_WR(ess, PORT_INT_STAT, 1, 2);
1646 #ifdef AGG_JITTER_CORRECTION
1647 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1648 if (ess->active & m)
1649 suppress_jitter(ess->pch + i);
1651 if (ess->active & m)
1652 suppress_rec_jitter(&ess->rch);
1655 for (i = 0, m = 1; i < ess->playchns; i++, m <<= 1) {
1656 if (ess->active & m) {
1657 if (ess->curpwr <= PCI_POWERSTATE_D1)
1658 chn_intr(ess->pch[i].channel);
1665 if ((ess->active & m)
1666 && ess->curpwr <= PCI_POWERSTATE_D1)
1667 chn_intr(ess->rch.channel);
1669 #ifdef AGG_JITTER_CORRECTION
1675 if (status & HOSTINT_STAT_HWVOL) {
1676 register u_int8_t event;
1679 event = AGG_RD(ess, PORT_HWVOL_MASTER, 1);
1680 AGG_WR(ess, PORT_HWVOL_MASTER, HWVOL_NOP, 1);
1685 mixer_hwvol_step(ess->dev, 1, 1);
1688 mixer_hwvol_step(ess->dev, -1, -1);
1693 if (event & HWVOL_MUTE) {
1694 mixer_hwvol_mute(ess->dev);
1697 device_printf(ess->dev,
1698 "%s: unknown HWVOL event 0x%x\n",
1699 device_get_nameunit(ess->dev), event);
1705 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1707 bus_addr_t *phys = arg;
1709 *phys = error? 0 : segs->ds_addr;
1712 printf("setmap (%lx, %lx), nseg=%d, error=%d\n",
1713 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1719 dma_malloc(bus_dma_tag_t dmat, u_int32_t sz, bus_addr_t *phys)
1724 if (bus_dmamem_alloc(dmat, &buf, BUS_DMA_NOWAIT, &map))
1726 if (bus_dmamap_load(dmat, map, buf, sz, setmap, phys, 0)
1728 bus_dmamem_free(dmat, buf, map);
1735 dma_free(bus_dma_tag_t dmat, void *buf)
1737 bus_dmamem_free(dmat, buf, NULL);
1741 agg_probe(device_t dev)
1745 switch (pci_get_devid(dev)) {
1746 case MAESTRO_1_PCI_ID:
1747 s = "ESS Technology Maestro-1";
1750 case MAESTRO_2_PCI_ID:
1751 s = "ESS Technology Maestro-2";
1754 case MAESTRO_2E_PCI_ID:
1755 s = "ESS Technology Maestro-2E";
1759 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
1760 device_set_desc(dev, s);
1761 return BUS_PROBE_DEFAULT;
1767 agg_attach(device_t dev)
1769 struct agg_info *ess = NULL;
1771 int regid = PCIR_BAR(0);
1772 struct resource *reg = NULL;
1773 struct ac97_info *codec = NULL;
1775 struct resource *irq = NULL;
1777 char status[SND_STATUSLEN];
1780 ess = malloc(sizeof(*ess), M_DEVBUF, M_WAITOK | M_ZERO);
1783 mtx_init(&ess->lock, device_get_desc(dev), "snd_maestro softc",
1784 MTX_DEF | MTX_RECURSE);
1785 if (!mtx_initialized(&ess->lock)) {
1786 device_printf(dev, "failed to create a mutex.\n");
1791 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
1792 "dac", &dacn) == 0) {
1795 else if (dacn > AGG_MAXPLAYCH)
1796 dacn = AGG_MAXPLAYCH;
1798 dacn = AGG_MAXPLAYCH;
1800 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
1801 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1802 /*align */ 4, 1 << (16+1),
1803 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1804 /*filter*/ NULL, NULL,
1805 /*size */ ess->bufsz, 1, 0x3ffff,
1807 #if __FreeBSD_version >= 501102
1808 /*lock */ busdma_lock_mutex, &Giant,
1810 &ess->buf_dmat) != 0) {
1811 device_printf(dev, "unable to create dma tag\n");
1816 if (bus_dma_tag_create(/*parent*/ bus_get_dma_tag(dev),
1817 /*align */ 1 << WAVCACHE_BASEADDR_SHIFT,
1819 /*limit */ MAESTRO_MAXADDR, BUS_SPACE_MAXADDR,
1820 /*filter*/ NULL, NULL,
1821 /*size */ 3*ess->bufsz, 1, 0x3ffff,
1823 #if __FreeBSD_version >= 501102
1824 /*lock */ busdma_lock_mutex, &Giant,
1826 &ess->stat_dmat) != 0) {
1827 device_printf(dev, "unable to create dma tag\n");
1832 /* Allocate the room for brain-damaging status buffer. */
1833 ess->stat = dma_malloc(ess->stat_dmat, 3*ess->bufsz, &ess->phys);
1834 if (ess->stat == NULL) {
1835 device_printf(dev, "cannot allocate status buffer\n");
1840 device_printf(dev, "Maestro status/record buffer: %#llx\n",
1841 (long long)ess->phys);
1843 /* State D0-uninitialized. */
1844 ess->curpwr = PCI_POWERSTATE_D3;
1845 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1847 data = pci_read_config(dev, PCIR_COMMAND, 2);
1848 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
1849 pci_write_config(dev, PCIR_COMMAND, data, 2);
1850 data = pci_read_config(dev, PCIR_COMMAND, 2);
1852 /* Allocate resources. */
1853 if (data & PCIM_CMD_PORTEN)
1854 reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, ®id,
1859 ess->st = rman_get_bustag(reg);
1860 ess->sh = rman_get_bushandle(reg);
1862 device_printf(dev, "unable to map register space\n");
1866 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqid,
1867 RF_ACTIVE | RF_SHAREABLE);
1872 device_printf(dev, "unable to map interrupt\n");
1877 /* Setup resources. */
1878 if (snd_setup_intr(dev, irq, INTR_MPSAFE, agg_intr, ess, &ih)) {
1879 device_printf(dev, "unable to setup interrupt\n");
1885 /* Transition from D0-uninitialized to D0. */
1887 agg_power(ess, PCI_POWERSTATE_D0);
1888 if (agg_rdcodec(ess, 0) == 0x80) {
1889 /* XXX - TODO: PT101 */
1891 device_printf(dev, "PT101 codec detected!\n");
1896 codec = AC97_CREATE(dev, ess, agg_ac97);
1897 if (codec == NULL) {
1898 device_printf(dev, "failed to create AC97 codec softc!\n");
1902 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) {
1903 device_printf(dev, "mixer initialization failed!\n");
1909 ret = pcm_register(dev, ess, dacn, 1);
1913 mixer_hwvol_init(dev);
1915 agg_power(ess, powerstate_init);
1917 for (data = 0; data < dacn; data++)
1918 pcm_addchan(dev, PCMDIR_PLAY, &aggpch_class, ess);
1919 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1920 adjust_pchbase(ess->pch, ess->playchns, ess->bufsz);
1922 snprintf(status, SND_STATUSLEN,
1923 "port 0x%lx-0x%lx irq %ld at device %d.%d on pci%d",
1924 rman_get_start(reg), rman_get_end(reg), rman_get_start(irq),
1925 pci_get_slot(dev), pci_get_function(dev), pci_get_bus(dev));
1926 pcm_setstatus(dev, status);
1932 ac97_destroy(codec);
1934 bus_teardown_intr(dev, irq, ih);
1936 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1938 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1940 if (ess->stat != NULL)
1941 dma_free(ess->stat_dmat, ess->stat);
1942 if (ess->stat_dmat != NULL)
1943 bus_dma_tag_destroy(ess->stat_dmat);
1944 if (ess->buf_dmat != NULL)
1945 bus_dma_tag_destroy(ess->buf_dmat);
1946 if (mtx_initialized(&ess->lock))
1947 mtx_destroy(&ess->lock);
1948 free(ess, M_DEVBUF);
1955 agg_detach(device_t dev)
1957 struct agg_info *ess = pcm_getdevinfo(dev);
1961 icr = AGG_RD(ess, PORT_HOSTINT_CTRL, 2);
1962 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
1966 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1972 r = pcm_unregister(dev);
1974 AGG_WR(ess, PORT_HOSTINT_CTRL, icr, 2);
1979 agg_power(ess, PCI_POWERSTATE_D3);
1982 bus_teardown_intr(dev, ess->irq, ess->ih);
1983 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1984 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1985 dma_free(ess->stat_dmat, ess->stat);
1986 bus_dma_tag_destroy(ess->stat_dmat);
1987 bus_dma_tag_destroy(ess->buf_dmat);
1988 mtx_destroy(&ess->lock);
1989 free(ess, M_DEVBUF);
1994 agg_suspend(device_t dev)
1996 struct agg_info *ess = pcm_getdevinfo(dev);
1998 AGG_WR(ess, PORT_HOSTINT_CTRL, 0, 2);
2000 agg_power(ess, PCI_POWERSTATE_D3);
2007 agg_resume(device_t dev)
2010 struct agg_info *ess = pcm_getdevinfo(dev);
2012 for (i = 0; i < ess->playchns; i++)
2013 if (ess->active & (1 << i))
2014 aggch_start_dac(ess->pch + i);
2015 if (ess->active & (1 << i))
2016 aggch_start_adc(&ess->rch);
2020 agg_power(ess, powerstate_init);
2023 if (mixer_reinit(dev)) {
2024 device_printf(dev, "unable to reinitialize the mixer\n");
2032 agg_shutdown(device_t dev)
2034 struct agg_info *ess = pcm_getdevinfo(dev);
2037 agg_power(ess, PCI_POWERSTATE_D3);
2044 static device_method_t agg_methods[] = {
2045 DEVMETHOD(device_probe, agg_probe),
2046 DEVMETHOD(device_attach, agg_attach),
2047 DEVMETHOD(device_detach, agg_detach),
2048 DEVMETHOD(device_suspend, agg_suspend),
2049 DEVMETHOD(device_resume, agg_resume),
2050 DEVMETHOD(device_shutdown, agg_shutdown),
2055 static driver_t agg_driver = {
2061 /*static devclass_t pcm_devclass;*/
2063 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0);
2064 MODULE_DEPEND(snd_maestro, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2065 MODULE_VERSION(snd_maestro, 1);