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42 * octeon_pip.h Packet Input Processing Block
48 #ifndef __OCTEON_PIP_H__
49 #define __OCTEON_PIP_H__
52 * Enumeration representing the amount of packet processing
53 * and validation performed by the input hardware.
57 OCTEON_PIP_PORT_CFG_MODE_NONE = 0ull, /**< Packet input doesn't perform any
58 processing of the input packet. */
59 OCTEON_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,/**< Full packet processing is performed
60 with pointer starting at the L2
61 (ethernet MAC) header. */
62 OCTEON_PIP_PORT_CFG_MODE_SKIPIP = 2ull /**< Input packets are assumed to be IP.
63 Results from non IP packets is
64 undefined. Pointers reference the
65 beginning of the IP header. */
66 } octeon_pip_port_parse_mode_t;
70 #define OCTEON_PIP_PRT_CFGX(offset) (0x80011800A0000200ull+((offset)*8))
71 #define OCTEON_PIP_PRT_TAGX(offset) (0x80011800A0000400ull+((offset)*8))
72 #define OCTEON_PIP_STAT_INB_PKTS(port) (0x80011800A0001A00ull+((port) * 32))
73 #define OCTEON_PIP_STAT_INB_ERRS(port) (0x80011800A0001A10ull+((port) * 32))
81 uint64_t reserved2 : 45; /* Must be zero */
82 uint64_t tag_syn : 1; /* Not Include src_crc in TCP..*/
83 uint64_t ip6_udp : 1; /* IPv6/UDP checksum is mandatory */
84 uint64_t max_l2 : 1; /* Largest L2 frame. 0/1 : 1500/1535 */
85 uint64_t reserved1 : 5; /* Must be zero */
86 uint64_t raw_shf : 3; /* PCI RAW Packet shift/pad amount */
87 uint64_t reserved0 : 5; /* Must be zero */
88 uint64_t nip_shf : 3; /* Non-IP shift/pad amount */
90 } octeon_pip_gbl_cfg_t;
96 uint64_t reserved4 : 37; /* Must be zero */
97 uint64_t qos : 3; /* Default POW QoS queue */
98 uint64_t qos_wat : 4; /* Bitfield to enable QoS watcher */
99 /* look up tables. 4 per port. */
100 uint64_t reserved3 : 1; /* Must be zero */
101 uint64_t spare : 1; /* Must be zero */
102 uint64_t qos_diff : 1; /* Use IP diffserv to determine */
103 /* the queue in the POW */
104 uint64_t qos_vlan : 1; /* Use the VLAN tag to determine */
105 /* the queue in the POW */
106 uint64_t reserved2 : 3; /* Must be zero */
107 uint64_t crc_en : 1; /* Enable HW checksum */
108 uint64_t reserved1 : 2; /* Must be zero */
109 octeon_pip_port_parse_mode_t mode : 2; /* Raw/Parsed/IP/etc */
110 uint64_t reserved0 : 1; /* Must be zero */
111 uint64_t skip : 7; /* 8 byte words to skip in the */
112 /* beginning of a packet buffer */
114 } octeon_pip_port_cfg_t;
119 * Packet input to POW interface. How input packets are tagged for
120 * the POW is controlled here.
125 uint64_t reserved : 24; /**< Reserved */
126 uint64_t grptagbase : 4; /**< Offset to use when computing group from tag bits
127 when GRPTAG is set. Only applies to IP packets.
129 uint64_t grptagmask : 4; /**< Which bits of the tag to exclude when computing
130 group when GRPTAG is set. Only applies to IP packets.
132 uint64_t grptag : 1; /**< When set, use the lower bit of the tag to compute
133 the group in the work queue entry
134 GRP = WQE[TAG[3:0]] & ~GRPTAGMASK + GRPTAGBASE.
135 Only applies to IP packets. (PASS2 only) */
136 uint64_t spare : 1; /**< Spare bit
138 uint64_t tag_mode : 2; /**< Which tag algorithm to use
139 0 = always use tuple tag algorithm
140 1 = always use mask tag algorithm
141 2 = if packet is IP, use tuple else use mask
144 uint64_t inc_vs : 2; /**< determines the VLAN ID (VID) to be included in
145 tuple tag when VLAN stacking is detected
146 0 = do not include VID in tuple tag generation
147 1 = include VID (VLAN0) in hash
148 2 = include VID (VLAN1) in hash
149 3 = include VID ([VLAN0,VLAN1]) in hash
151 uint64_t inc_vlan : 1; /**< when set, the VLAN ID is included in tuple tag
152 when VLAN stacking is not detected
153 0 = do not include VID in tuple tag generation
154 1 = include VID in hash
156 uint64_t inc_prt_flag : 1; /**< sets whether the port is included in tuple tag */
157 uint64_t ip6_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is
158 included in tuple tag for IPv6 packets */
159 uint64_t ip4_dprt_flag : 1; /**< sets whether the TCP/UDP dst port is
160 included in tuple tag for IPv4 */
161 uint64_t ip6_sprt_flag : 1; /**< sets whether the TCP/UDP src port is
162 included in tuple tag for IPv6 packets */
163 uint64_t ip4_sprt_flag : 1; /**< sets whether the TCP/UDP src port is
164 included in tuple tag for IPv4 */
165 uint64_t ip6_nxth_flag : 1; /**< sets whether ipv6 includes next header in tuple
167 uint64_t ip4_pctl_flag : 1; /**< sets whether ipv4 includes protocol in tuple
169 uint64_t ip6_dst_flag : 1; /**< sets whether ipv6 includes dst address in tuple
171 uint64_t ip4_dst_flag : 1; /**< sets whether ipv4 includes dst address in tuple
173 uint64_t ip6_src_flag : 1; /**< sets whether ipv6 includes src address in tuple
175 uint64_t ip4_src_flag : 1; /**< sets whether ipv4 includes src address in tuple
177 uint64_t tcp6_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv6)
181 uint64_t tcp4_tag_type : 2; /**< sets the tag_type of a TCP packet (IPv4)
185 uint64_t ip6_tag_type : 2; /**< sets whether IPv6 packet tag type
189 uint64_t ip4_tag_type : 2; /**< sets whether IPv4 packet tag type
193 uint64_t non_tag_type : 2; /**< sets whether non-IP packet tag type
197 uint64_t grp : 4; /* POW group for input pkts */
199 } octeon_pip_port_tag_cfg_t;
203 * Configure an ethernet input port
205 * @param port_num Port number to configure
206 * @param port_cfg Port hardware configuration
207 * @param port_tag_cfg
208 * Port POW tagging configuration
210 static inline void octeon_pip_config_port(u_int port_num,
211 octeon_pip_port_cfg_t port_cfg,
212 octeon_pip_port_tag_cfg_t port_tag_cfg)
214 oct_write64(OCTEON_PIP_PRT_CFGX(port_num), port_cfg.word64);
215 oct_write64(OCTEON_PIP_PRT_TAGX(port_num), port_tag_cfg.word64);
219 #endif /* __OCTEON_PIP_H__ */