1 /***********************license start***************
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
35 * For any questions regarding licensing please contact marketing@caviumnetworks.com
37 ***********************license end**************************************/
40 * This product includes software developed by the University of
41 * California, Berkeley and its contributors."
46 #ifndef __OCTEON_PCMAP_REGS_H__
47 #define __OCTEON_PCMAP_REGS_H__
52 * Utility inlines & macros
55 #if defined(__mips_n64)
56 #define oct_write64(a, v) (*(volatile uint64_t *)(a) = (uint64_t)(v))
57 #define oct_write8_x8(a, v) (*(volatile uint8_t *)(a) = (uint8_t)(v))
59 #define OCT_READ(n, t) \
60 static inline t oct_read ## n(uintptr_t a) \
62 volatile t *p = (volatile t *)a; \
67 OCT_READ(16, uint16_t);
68 OCT_READ(32, uint32_t);
69 OCT_READ(64, uint64_t);
71 #elif defined(__mips_n32) || defined(__mips_o32)
72 #if defined(__mips_n32)
73 static inline void oct_write64 (uint64_t csr_addr, uint64_t val64)
81 : "r"(val64), "r"(csr_addr));
84 static inline void oct_write8_x8 (uint64_t csr_addr, uint8_t val8)
92 : "r"(val8), "r"(csr_addr));
95 #define OCT_READ(n, t, insn) \
96 static inline t oct_read ## n(uint64_t a) \
103 insn "\t%0, 0(%1)\n" \
110 OCT_READ(8, uint8_t, "lb");
111 OCT_READ(16, uint16_t, "lh");
112 OCT_READ(32, uint32_t, "lw");
113 OCT_READ(64, uint64_t, "ld");
118 * Add o32 variants that load the address into a register and the result out
119 * of a register properly, and simply disable interrupts before and after and
120 * hope that we don't need to refill or modify the TLB to access the address.
121 * I'd be a lot happier if csr_addr were a physical address and we mapped it
122 * into XKPHYS here so that we could guarantee that interrupts were the only
123 * kind of exception we needed to worry about.
125 * Also, some of this inline assembly is needlessly verbose. Oh, well.
127 static inline void oct_write64 (uint64_t csr_addr, uint64_t val64)
129 uint32_t csr_addrh = csr_addr >> 32;
130 uint32_t csr_addrl = csr_addr;
131 uint32_t valh = val64 >> 32;
132 uint32_t vall = val64;
155 : "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
156 : "r" (valh), "r" (vall), "r" (csr_addrh), "r" (csr_addrl));
161 static inline void oct_write8_x8 (uint64_t csr_addr, uint8_t val8)
163 uint32_t csr_addrh = csr_addr >> 32;
164 uint32_t csr_addrl = csr_addr;
182 : "=&r" (tmp1), "=&r" (tmp2)
183 : "r" (val8), "r" (csr_addrh), "r" (csr_addrl));
188 #define OCT_READ(n, t, insn) \
189 static inline t oct_read ## n(uint64_t csr_addr) \
191 uint32_t csr_addrh = csr_addr >> 32; \
192 uint32_t csr_addrl = csr_addr; \
193 uint32_t tmp1, tmp2; \
196 sr = intr_disable(); \
203 "dsll %1, %2, 32\n" \
204 "dsll %0, %3, 32\n" \
205 "dsrl %0, %0, 32\n" \
209 : "=&r" (tmp1), "=&r" (tmp2) \
210 : "r" (csr_addrh), "r" (csr_addrl)); \
217 OCT_READ(8, uint8_t, "lb");
218 OCT_READ(16, uint16_t, "lh");
219 OCT_READ(32, uint32_t, "lw");
221 static inline uint64_t oct_read64 (uint64_t csr_addr)
223 uint32_t csr_addrh = csr_addr >> 32;
224 uint32_t csr_addrl = csr_addr;
245 : "=&r" (valh), "=&r" (vall)
246 : "r" (csr_addrh), "r" (csr_addrl));
250 return ((uint64_t)valh << 32) | vall;
256 #define oct_write64_int64(a, v) (oct_write64(a, (int64_t)(v)))
259 * Most write bus transactions are actually 64-bit on Octeon.
261 static inline void oct_write8 (uint64_t csr_addr, uint8_t val8)
263 oct_write64(csr_addr, (uint64_t) val8);
266 static inline void oct_write16 (uint64_t csr_addr, uint16_t val16)
268 oct_write64(csr_addr, (uint64_t) val16);
271 static inline void oct_write32 (uint64_t csr_addr, uint32_t val32)
273 oct_write64(csr_addr, (uint64_t) val32);
276 #define oct_readint32(a) ((int32_t)oct_read32((a)))
281 * Direct to Board Support level.
283 extern void octeon_led_write_char(int char_position, char val);
284 extern void octeon_led_write_hexchar(int char_position, char hexval);
285 extern void octeon_led_write_hex(uint32_t wl);
286 extern void octeon_led_write_string(const char *str);
287 extern void octeon_reset(void);
288 extern void octeon_led_write_char0(char val);
289 extern void octeon_led_run_wheel(int *pos, int led_position);
290 extern void octeon_debug_symbol(void);
291 extern void octeon_ciu_reset(void);
292 extern int octeon_is_simulation(void);
298 #define OCTEON_CHAR_LED_BASE_ADDR (0x1d020000 | (0x1ffffffffull << 31))
300 #endif /* !OCTEON_PCMAP_REGS_H__ */