2 * Copyright (c) 2003-2009 RMI Corporation
5 * Redistribution and use in source and binary forms, with or without
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31 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
33 #include <sys/param.h>
34 #include <sys/kernel.h>
36 #include <sys/mutex.h>
37 #include <sys/queue.h>
39 #include <sys/sysctl.h>
40 #include <sys/systm.h>
41 #include <sys/timetc.h>
43 #include <sys/module.h>
44 #include <sys/stdint.h>
48 #include <sys/systm.h>
49 #include <sys/clock.h>
51 #include <machine/clock.h>
52 #include <machine/md_var.h>
53 #include <machine/hwfunc.h>
54 #include <machine/intr_machdep.h>
56 #include <mips/rmi/iomap.h>
57 #include <mips/rmi/clock.h>
58 #include <mips/rmi/interrupt.h>
59 #include <mips/rmi/pic.h>
60 #include <mips/rmi/shared_structs.h>
63 #include <mips/rmi/perfmon.h>
66 uint64_t counter_freq;
67 uint64_t cycles_per_tick;
68 uint64_t cycles_per_usec;
69 uint64_t cycles_per_sec;
70 uint64_t cycles_per_hz;
72 u_int32_t counter_upper = 0;
73 u_int32_t counter_lower_last = 0;
75 #define STAT_PROF_CLOCK_SCALE_FACTOR 8
77 static int scale_factor;
78 static int count_scale_factor[32];
81 platform_get_frequency()
87 mips_timer_early_init(uint64_t clock_hz)
89 /* Initialize clock early so that we can use DELAY sooner */
90 counter_freq = clock_hz;
91 cycles_per_usec = (clock_hz / (1000 * 1000));
96 * count_compare_clockhandler:
98 * Handle the clock interrupt when count becomes equal to
102 count_compare_clockhandler(struct trapframe *tf)
104 int cpu = PCPU_GET(cpuid);
112 count_scale_factor[cpu]++;
113 cycles = mips_rd_count();
114 cycles += XLR_CPU_HZ / hz;
115 mips_wr_compare(cycles);
117 hardclock_cpu(USERMODE(tf->sr));
118 if (count_scale_factor[cpu] == STAT_PROF_CLOCK_SCALE_FACTOR) {
119 statclock(USERMODE(tf->sr));
120 if (profprocs != 0) {
121 profclock(USERMODE(tf->sr), tf->pc);
123 count_scale_factor[cpu] = 0;
125 /* If needed , handle count compare tick skew here */
129 return (FILTER_HANDLED);
133 pic_hardclockhandler(struct trapframe *tf)
135 int cpu = PCPU_GET(cpuid);
141 hardclock(USERMODE(tf->sr), tf->pc);
142 if (scale_factor == STAT_PROF_CLOCK_SCALE_FACTOR) {
143 statclock(USERMODE(tf->sr));
144 if (profprocs != 0) {
145 profclock(USERMODE(tf->sr), tf->pc);
150 if (xlr_perfmon_started)
151 xlr_perfmon_clockhandler();
155 /* If needed , handle count compare tick skew here */
158 return (FILTER_HANDLED);
162 pic_timecounthandler(struct trapframe *tf)
164 return (FILTER_HANDLED);
168 rmi_early_counter_init()
170 int cpu = PCPU_GET(cpuid);
171 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
174 * We do this to get the PIC time counter running right after system
175 * start. Otherwise the DELAY() function will not be able to work
176 * since it won't have a TC to read.
178 xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
179 xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
180 xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
181 xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
182 pic_update_control(1 << (8 + 6));
185 void tick_init(void);
188 platform_initclocks(void)
190 int cpu = PCPU_GET(cpuid);
194 * Note: Passing #3 as NULL ensures that clockhandler gets called
197 /* profiling/process accounting timer interrupt for non-zero cpus */
198 cpu_establish_hardintr("compare",
199 (driver_filter_t *) count_compare_clockhandler,
203 INTR_TYPE_CLK | INTR_FAST, &cookie);
205 /* timekeeping timer interrupt for cpu 0 */
206 cpu_establish_hardintr("hardclk",
207 (driver_filter_t *) pic_hardclockhandler,
211 INTR_TYPE_CLK | INTR_FAST,
214 /* this is used by timecounter */
215 cpu_establish_hardintr("timecount",
216 (driver_filter_t *) pic_timecounthandler, NULL,
217 NULL, PIC_TIMER_6_IRQ, INTR_TYPE_CLK | INTR_FAST,
221 __uint64_t maxval = XLR_PIC_HZ / hz;
222 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
224 stathz = hz / STAT_PROF_CLOCK_SCALE_FACTOR;
227 /* Setup PIC Interrupt */
229 if (rmi_spin_mutex_safe)
230 mtx_lock_spin(&xlr_pic_lock);
231 xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff)); /* 0x100 + 7 */
232 xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff); /* 0x110 + 7 */
234 /* reg 40 is lower bits 31-0 and holds CPU mask */
235 xlr_write_reg(mmio, PIC_IRT_0_TIMER_7, (1 << cpu));
237 /* Reg 80 is upper bits 63-32 and holds */
238 /* Valid Edge Local IRQ */
239 xlr_write_reg(mmio, PIC_IRT_1_TIMER_7, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_7_IRQ));
240 pic_update_control(1 << (8 + 7));
242 xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
243 xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0x0 & 0xffffffff));
244 xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
245 xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
246 pic_update_control(1 << (8 + 6));
247 if (rmi_spin_mutex_safe)
248 mtx_unlock_spin(&xlr_pic_lock);
250 /* Setup count-compare interrupt for vcpu[1-31] */
251 mips_wr_compare((xlr_boot1_info.cpu_frequency) / hz);
257 __attribute__((no_instrument_function))
258 platform_get_timecount(struct timecounter *tc __unused)
260 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
262 return 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
268 uint32_t cur, last, delta, usecs;
271 * This works by polling the timer and counting the number of
272 * microseconds that go by.
274 last = platform_get_timecount(NULL);
278 cur = platform_get_timecount(NULL);
280 /* Check to see if the timer has wrapped around. */
282 delta += (cur + (cycles_per_hz - last));
284 delta += (cur - last);
288 if (delta >= cycles_per_usec) {
289 usecs += delta / cycles_per_usec;
290 delta %= cycles_per_usec;
297 read_pic_counter(void)
299 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
300 uint32_t lower, upper;
304 * Pull the value of the 64 bit counter which is stored in PIC
305 * register 120+N and 130+N
307 upper = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_1);
308 lower = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
309 tc = (((uint64_t) upper << 32) | (uint64_t) lower);
313 extern struct timecounter counter_timecounter;
316 mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
320 * XXX: Do not use printf here: uart code 8250 may use DELAY so this
321 * function should be called before cninit.
323 counter_freq = platform_counter_freq;
325 * XXX: Some MIPS32 cores update the Count register only every two
328 if (double_count != 0)
331 cycles_per_tick = counter_freq / 1000;
332 cycles_per_hz = counter_freq / hz;
333 cycles_per_usec = counter_freq / (1 * 1000 * 1000);
334 cycles_per_sec = counter_freq;
336 counter_timecounter.tc_frequency = counter_freq;
337 printf("hz=%d cyl_per_hz:%jd cyl_per_usec:%jd freq:%jd cyl_per_hz:%jd cyl_per_sec:%jd\n",
345 set_cputicker(read_pic_counter, counter_freq, 1);