2 * Copyright (c) 1991 The Regents of the University of California.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: @(#)com.c 7.5 (Berkeley) 5/16/91
31 * from: i386/isa sio.c,v 1.234
34 #include "opt_comconsole.h"
35 #include "opt_compat.h"
41 * Serial driver, based on 386BSD-0.1 com driver.
42 * Mostly rewritten to use pseudo-DMA.
43 * Works for National Semiconductor NS8250-NS16550AF UARTs.
44 * COM driver, based on HP dca driver.
46 * Changes for PC Card integration:
47 * - Added PC Card driver table and handlers
49 /*===============================================================
50 * 386BSD(98),FreeBSD-1.1x(98) com driver.
52 * modified for PC9801 by M.Ishii
53 * Kyoto University Microcomputer Club (KMC)
54 * Chou "TEFUTEFU" Hirotomi
55 * Kyoto Univ. the faculty of medicine
56 *===============================================================
57 * FreeBSD-2.0.1(98) sio driver.
59 * modified for pc98 Internal i8251 and MICRO CORE MC16550II
60 * T.Koike(hfc01340@niftyserve.or.jp)
61 * implement kernel device configuration
62 * aizu@orient.center.nitech.ac.jp
66 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local
68 * This driver is under debugging,has bugs.
71 * modified for AIWA B98-01
72 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995
75 * Modified by Y.Takahashi of Kogakuin University.
78 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org>
81 #include <sys/param.h>
82 #include <sys/systm.h>
85 #include <sys/fcntl.h>
86 #include <sys/interrupt.h>
88 #include <sys/kernel.h>
89 #include <sys/limits.h>
91 #include <sys/malloc.h>
92 #include <sys/module.h>
93 #include <sys/mutex.h>
95 #include <sys/reboot.h>
96 #include <sys/serial.h>
97 #include <sys/sysctl.h>
98 #include <sys/syslog.h>
100 #include <machine/bus.h>
101 #include <sys/rman.h>
102 #include <sys/timepps.h>
104 #include <sys/cons.h>
106 #include <isa/isavar.h>
108 #include <machine/resource.h>
110 #include <dev/sio/sioreg.h>
111 #include <dev/sio/siovar.h>
114 #include <pc98/cbus/cbus.h>
115 #include <pc98/pc98/pc98_machdep.h>
119 #include <dev/ic/esp.h>
121 #include <dev/ic/ns16550.h>
123 #include <dev/ic/i8251.h>
124 #include <dev/ic/i8255.h>
125 #include <dev/ic/rsa.h>
128 #define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */
133 * 0x00000001 shared IRQs
134 * 0x00000002 disable FIFO
135 * 0x00000008 recover sooner from lost output interrupts
136 * 0x00000010 device is potential system console
137 * 0x00000020 device is forced to become system console
138 * 0x00000040 device is reserved for low-level IO
139 * 0x00000080 use this port for remote kernel debugging
140 * 0x0000??00 minor number of master port
141 * 0x00010000 PPS timestamping on CTS instead of DCD
142 * 0x00080000 IIR_TXRDY bug
143 * 0x00400000 If no comconsole found then mark as a comconsole
144 * 0x1?000000 interface type
148 /* checks in flags for multiport and which is multiport "master chip"
151 #define COM_ISMULTIPORT(flags) ((flags) & 0x01)
152 #define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff)
154 #define COM_NOTAST4(flags) ((flags) & 0x04)
157 #define COM_ISMULTIPORT(flags) (0)
158 #endif /* COM_MULTIPORT */
160 #define COM_C_IIR_TXRDYBUG 0x80000
161 #define COM_CONSOLE(flags) ((flags) & 0x10)
162 #define COM_DEBUGGER(flags) ((flags) & 0x80)
164 #define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24)
166 #define COM_FORCECONSOLE(flags) ((flags) & 0x20)
167 #define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG)
168 #define COM_LLCONSOLE(flags) ((flags) & 0x40)
169 #define COM_LOSESOUTINTS(flags) ((flags) & 0x08)
170 #define COM_NOFIFO(flags) ((flags) & 0x02)
172 #define COM_NOSCR(flags) ((flags) & 0x100000)
174 #define COM_PPSCTS(flags) ((flags) & 0x10000)
176 #define COM_ST16650A(flags) ((flags) & 0x20000)
177 #define COM_TI16754(flags) ((flags) & 0x200000)
180 #define sio_getreg(com, off) \
181 (bus_space_read_1((com)->bst, (com)->bsh, (off)))
182 #define sio_setreg(com, off, value) \
183 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value)))
187 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher
188 * than the other bits so that they can be tested as a group without masking
191 * The following com and tty flags correspond closely:
192 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and
194 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart())
195 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam())
196 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam())
197 * TS_FLUSH is not used.
198 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON.
199 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state).
201 #define CS_BUSY 0x80 /* output in progress */
202 #define CS_TTGO 0x40 /* output not stopped by XOFF */
203 #define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */
204 #define CS_CHECKMSR 1 /* check of MSR scheduled */
205 #define CS_CTS_OFLOW 2 /* use CTS output flow control */
206 #define CS_ODONE 4 /* output completed */
207 #define CS_RTS_IFLOW 8 /* use RTS input flow control */
208 #define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */
210 static char const * const error_desc[] = {
213 #define CE_INTERRUPT_BUF_OVERFLOW 1
214 "interrupt-level buffer overflow",
215 #define CE_TTY_BUF_OVERFLOW 2
216 "tty-level buffer overflow",
220 #define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum])
222 /* types. XXX - should be elsewhere */
223 typedef u_int Port_t; /* hardware port */
224 typedef u_char bool_t; /* boolean */
226 /* queue of linear buffers */
228 u_char *l_head; /* next char to process */
229 u_char *l_tail; /* one past the last char to process */
230 struct lbq *l_next; /* next in queue */
231 bool_t l_queued; /* nonzero if queued */
234 /* com device structure */
236 u_char state; /* miscellaneous flag bits */
237 u_char cfcr_image; /* copy of value written to CFCR */
239 bool_t esp; /* is this unit a hayes esp board? */
241 u_char extra_state; /* more flag bits, separate for order trick */
242 u_char fifo_image; /* copy of value written to FIFO */
243 bool_t hasfifo; /* nonzero for 16550 UARTs */
244 bool_t loses_outints; /* nonzero if device loses output interrupts */
245 u_char mcr_image; /* copy of value written to MCR */
247 bool_t multiport; /* is this unit part of a multiport device? */
248 #endif /* COM_MULTIPORT */
249 bool_t no_irq; /* nonzero if irq is not attached */
250 bool_t gone; /* hardware disappeared */
251 bool_t poll; /* nonzero if polling is required */
252 bool_t poll_output; /* nonzero if polling for output is required */
253 bool_t st16650a; /* nonzero if Startech 16650A compatible */
254 int unit; /* unit number */
255 u_int flags; /* copy of device flags */
259 * The high level of the driver never reads status registers directly
260 * because there would be too many side effects to handle conveniently.
261 * Instead, it reads copies of the registers stored here by the
264 u_char last_modem_status; /* last MSR read by intr handler */
265 u_char prev_modem_status; /* last MSR handled by high level */
267 u_char *ibuf; /* start of input buffer */
268 u_char *ibufend; /* end of input buffer */
269 u_char *ibufold; /* old input buffer, to be freed */
270 u_char *ihighwater; /* threshold in input buffer */
271 u_char *iptr; /* next free spot in input buffer */
272 int ibufsize; /* size of ibuf (not include error bytes) */
273 int ierroff; /* offset of error bytes in ibuf */
275 struct lbq obufq; /* head of queue of output buffers */
276 struct lbq obufs[2]; /* output buffers */
279 bus_space_handle_t bsh;
284 Port_t in_modem_port;
285 Port_t intr_ctrl_port;
286 Port_t rsabase; /* Iobase address of an I/O-DATA RSA board. */
288 int pc98_prev_modem_status;
289 int pc98_modem_delta;
290 int modem_car_chg_timer;
291 int pc98_prev_siocmd;
292 int pc98_prev_siomod;
296 bool_t pc98_8251fifo;
297 bool_t pc98_8251fifo_enable;
299 Port_t data_port; /* i/o ports */
305 Port_t modem_ctl_port;
306 Port_t line_status_port;
307 Port_t modem_status_port;
309 struct tty *tp; /* cross reference */
311 struct pps_state pps;
313 #ifdef ALT_BREAK_TO_DEBUGGER
317 u_long bytes_in; /* statistics */
319 u_int delta_error_counts[CE_NTYPES];
320 u_long error_counts[CE_NTYPES];
324 struct resource *irqres;
325 struct resource *ioportres;
330 * Data area for output buffers. Someday we should build the output
331 * buffer queue without copying data.
344 static int espattach(struct com_s *com, Port_t esp_port);
347 static void combreak(struct tty *tp, int sig);
348 static timeout_t siobusycheck;
349 static u_int siodivisor(u_long rclk, speed_t speed);
350 static void comclose(struct tty *tp);
351 static int comopen(struct tty *tp, struct cdev *dev);
352 static void sioinput(struct com_s *com);
353 static void siointr1(struct com_s *com);
354 static int siointr(void *arg);
355 static int commodem(struct tty *tp, int sigon, int sigoff);
356 static int comparam(struct tty *tp, struct termios *t);
357 static void siopoll(void *);
358 static void siosettimeout(void);
359 static int siosetwater(struct com_s *com, speed_t speed);
360 static void comstart(struct tty *tp);
361 static void comstop(struct tty *tp, int rw);
362 static timeout_t comwakeup;
364 char sio_driver_name[] = "sio";
365 static struct mtx sio_lock;
366 static int sio_inited;
368 /* table and macro for fast conversion from a unit number to its com struct */
369 devclass_t sio_devclass;
370 #define com_addr(unit) ((struct com_s *) \
371 devclass_get_softc(sio_devclass, unit)) /* XXX */
374 static volatile speed_t comdefaultrate = CONSPEED;
375 static u_long comdefaultrclk = DEFAULT_RCLK;
376 SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, "");
377 static speed_t gdbdefaultrate = GDBSPEED;
378 SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW,
379 &gdbdefaultrate, GDBSPEED, "");
380 static u_int com_events; /* input chars + weighted output completions */
381 static Port_t siocniobase;
382 static int siocnunit = -1;
383 static void *sio_slow_ih;
384 static void *sio_fast_ih;
385 static int sio_timeout;
386 static int sio_timeouts_until_log;
387 static struct callout_handle sio_timeout_handle
388 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle);
389 static int sio_numunits;
395 Port_t cmd, sts, ctrl, mod;
399 #define COM_INT_DISABLE {int previpri; previpri=spltty();
400 #define COM_INT_ENABLE splx(previpri);}
401 #define IEN_TxFLAG IEN_Tx
403 #define COM_CARRIER_DETECT_EMULATE 0
404 #define PC98_CHECK_MODEM_INTERVAL (hz/10)
405 #define DCD_OFF_TOLERANCE 2
406 #define DCD_ON_RECOGNITION 2
407 #define IS_8251(if_type) (!(if_type & 0x10))
408 #define COM1_EXT_CLOCK 0x40000
410 static void commint(struct cdev *dev);
411 static void com_tiocm_bis(struct com_s *com, int msr);
412 static void com_tiocm_bic(struct com_s *com, int msr);
413 static int com_tiocm_get(struct com_s *com);
414 static int com_tiocm_get_delta(struct com_s *com);
415 static void pc98_msrint_start(struct cdev *dev);
416 static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed);
417 static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor);
418 static int pc98_get_modem_status(struct com_s *com);
419 static timeout_t pc98_check_msr;
420 static void pc98_set_baud_rate(struct com_s *com, u_int count);
421 static void pc98_i8251_reset(struct com_s *com, int mode, int command);
422 static void pc98_disable_i8251_interrupt(struct com_s *com, int mod);
423 static void pc98_enable_i8251_interrupt(struct com_s *com, int mod);
424 static int pc98_check_i8251_interrupt(struct com_s *com);
425 static int pc98_i8251_get_cmd(struct com_s *com);
426 static int pc98_i8251_get_mod(struct com_s *com);
427 static void pc98_i8251_set_cmd(struct com_s *com, int x);
428 static void pc98_i8251_or_cmd(struct com_s *com, int x);
429 static void pc98_i8251_clear_cmd(struct com_s *com, int x);
430 static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x);
431 static int pc98_check_if_type(device_t dev, struct siodev *iod);
432 static int pc98_check_8251vfast(void);
433 static int pc98_check_8251fifo(void);
434 static void pc98_check_sysclock(void);
435 static void pc98_set_ioport(struct com_s *com);
437 #define com_int_Tx_disable(com) \
438 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP)
439 #define com_int_Tx_enable(com) \
440 pc98_enable_i8251_interrupt(com,IEN_TxFLAG)
441 #define com_int_Rx_disable(com) \
442 pc98_disable_i8251_interrupt(com,IEN_Rx)
443 #define com_int_Rx_enable(com) \
444 pc98_enable_i8251_interrupt(com,IEN_Rx)
445 #define com_int_TxRx_disable(com) \
446 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx)
447 #define com_int_TxRx_enable(com) \
448 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx)
449 #define com_send_break_on(com) \
450 (IS_8251((com)->pc98_if_type) ? \
451 pc98_i8251_or_cmd((com), CMD8251_SBRK) : \
452 sio_setreg((com), com_cfcr, (com)->cfcr_image |= CFCR_SBREAK))
453 #define com_send_break_off(com) \
454 (IS_8251((com)->pc98_if_type) ? \
455 pc98_i8251_clear_cmd((com), CMD8251_SBRK) : \
456 sio_setreg((com), com_cfcr, (com)->cfcr_image &= ~CFCR_SBREAK))
458 static struct speedtab pc98speedtab[] = { /* internal RS232C interface */
480 static struct speedtab pc98fast_speedtab[] = {
481 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), },
482 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), },
483 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), },
484 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), },
485 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), },
488 static struct speedtab comspeedtab_pio9032b[] = {
499 static struct speedtab comspeedtab_b98_01[] = {
514 static struct speedtab comspeedtab_ind[] = {
535 struct speedtab *speedtab;
538 /* COM_IF_INTERNAL */
539 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1},
540 -1, pc98speedtab, 1 },
541 /* COM_IF_PC9861K_1 */
542 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1},
544 /* COM_IF_PC9861K_2 */
545 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1},
547 /* COM_IF_IND_SS_1 */
548 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1},
549 3, comspeedtab_ind, 1 },
550 /* COM_IF_IND_SS_2 */
551 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1},
552 3, comspeedtab_ind, 1 },
553 /* COM_IF_PIO9032B_1 */
554 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1},
555 7, comspeedtab_pio9032b, 1 },
556 /* COM_IF_PIO9032B_2 */
557 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1},
558 7, comspeedtab_pio9032b, 1 },
559 /* COM_IF_B98_01_1 */
560 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3},
561 7, comspeedtab_b98_01, 0 },
562 /* COM_IF_B98_01_2 */
563 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7},
564 7, comspeedtab_b98_01, 0 },
566 #define PC98SIO_data_port(type) (if_8251_type[type].port_table[0])
567 #define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1])
568 #define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2])
569 #define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3])
570 #define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4])
571 #define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5])
572 #define PC98SIO_func_port(type) (if_8251_type[type].port_table[6])
574 #define I8251F_data 0x130
575 #define I8251F_lsr 0x132
576 #define I8251F_msr 0x134
577 #define I8251F_iir 0x136
578 #define I8251F_fcr 0x138
579 #define I8251F_div 0x13a
582 static bus_addr_t port_table_0[] =
583 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007};
584 static bus_addr_t port_table_1[] =
585 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e};
586 static bus_addr_t port_table_8[] =
587 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700};
588 static bus_addr_t port_table_rsa[] = {
589 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f,
590 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007
600 } if_16550a_type[] = {
602 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
604 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
605 /* COM_IF_SECOND_CCU */
606 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
607 /* COM_IF_MC16550II */
608 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE,
611 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4},
613 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10},
615 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10},
616 /* COM_IF_MODEM_CARD */
617 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK},
618 /* COM_IF_RSA98III */
619 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8},
621 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4},
626 static Port_t siogdbiobase = 0;
632 /* XXX configure this properly. */
633 /* XXX quite broken for new-bus. */
634 static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 };
635 static Port_t likely_esp_ports[] = { 0xc0d0, 0 };
637 #define ESP98_CMD1 (ESP_CMD1 * 0x100)
638 #define ESP98_CMD2 (ESP_CMD2 * 0x100)
639 #define ESP98_STATUS1 (ESP_STATUS1 * 0x100)
640 #define ESP98_STATUS2 (ESP_STATUS2 * 0x100)
644 /* XXX configure this properly. */
645 static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, };
646 static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 };
652 * handle sysctl read/write requests for console speed
654 * In addition to setting comdefaultrate for I/O through /dev/console,
655 * also set the initial and lock values for the /dev/ttyXX device
656 * if there is one associated with the console. Finally, if the /dev/tty
657 * device has already been open, change the speed on the open running port
662 sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS)
669 newspeed = comdefaultrate;
671 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req);
672 if (error || !req->newptr)
675 comdefaultrate = newspeed;
677 if (comconsole < 0) /* serial console not selected? */
680 com = com_addr(comconsole);
689 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX
690 * (note, the lock rates really are boolean -- if non-zero, disallow
693 tp->t_init_in.c_ispeed = tp->t_init_in.c_ospeed =
694 tp->t_lock_in.c_ispeed = tp->t_lock_in.c_ospeed =
695 tp->t_init_out.c_ispeed = tp->t_init_out.c_ospeed =
696 tp->t_lock_out.c_ispeed = tp->t_lock_out.c_ospeed = comdefaultrate;
698 if (tp->t_state & TS_ISOPEN) {
699 tp->t_termios.c_ispeed =
700 tp->t_termios.c_ospeed = comdefaultrate;
702 error = comparam(tp, &tp->t_termios);
708 SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW,
709 0, 0, sysctl_machdep_comdefaultrate, "I", "");
710 TUNABLE_INT("machdep.conspeed", __DEVOLATILE(int *, &comdefaultrate));
713 * Unload the driver and clear the table.
714 * XXX this is mostly wrong.
716 * This is usually called when the card is ejected, but
717 * can be caused by a kldunload of a controller driver.
718 * The idea is to reset the driver's view of the device
719 * and ensure that any driver entry points such as
720 * read and write do not hang.
723 siodetach(device_t dev)
727 com = (struct com_s *) device_get_softc(dev);
729 device_printf(dev, "NULL com in siounload\n");
736 bus_teardown_intr(dev, com->irqres, com->cookie);
737 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres);
740 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid,
742 if (com->ibuf != NULL)
743 free(com->ibuf, M_DEVBUF);
745 if (com->obuf1 != NULL)
746 free(com->obuf1, M_DEVBUF);
749 device_set_softc(dev, NULL);
755 sioprobe(dev, xrid, rclk, noprobe)
762 static bool_t already_init;
771 intrmask_t irqmap[4];
776 u_int flags = device_get_flags(dev);
778 struct resource *port;
785 iod.if_type = GET_IFTYPE(flags);
786 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) &&
787 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2))
793 if (IS_8251(iod.if_type)) {
794 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
796 } else if (iod.if_type == COM_IF_MODEM_CARD ||
797 iod.if_type == COM_IF_RSA98III ||
798 isa_get_vendorid(dev)) {
799 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
800 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
802 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
803 if_16550a_type[iod.if_type & 0x0f].iat,
804 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE);
807 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
808 0, ~0, IO_COMSIZE, RF_ACTIVE);
813 if (!IS_8251(iod.if_type)) {
814 if (isa_load_resourcev(port,
815 if_16550a_type[iod.if_type & 0x0f].iat,
816 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) {
817 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
823 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO);
825 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
828 device_set_softc(dev, com);
829 com->bst = rman_get_bustag(port);
830 com->bsh = rman_get_bushandle(port);
832 if (!IS_8251(iod.if_type) && rclk == 0)
833 rclk = if_16550a_type[iod.if_type & 0x0f].rclk;
840 while (sio_inited != 2)
841 if (atomic_cmpset_int(&sio_inited, 0, 1)) {
842 mtx_init(&sio_lock, sio_driver_name, NULL,
844 MTX_SPIN | MTX_QUIET : MTX_SPIN);
845 atomic_store_rel_int(&sio_inited, 2);
850 * XXX this is broken - when we are first called, there are no
851 * previously configured IO ports. We could hard code
852 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse.
853 * This code has been doing nothing since the conversion since
854 * "count" is zero the first time around.
858 * Turn off MCR_IENABLE for all likely serial ports. An unused
859 * port with its MCR_IENABLE gate open will inhibit interrupts
860 * from any used port that shares the interrupt vector.
861 * XXX the gate enable is elsewhere for some multiports.
864 int count, i, xioport;
869 devclass_get_devices(sio_devclass, &devs, &count);
871 for (i = 0; i < count; i++) {
873 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0);
874 xiftype = GET_IFTYPE(device_get_flags(xdev));
875 if (device_is_enabled(xdev) && xioport > 0) {
876 if (IS_8251(xiftype))
877 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2);
879 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0);
883 for (i = 0; i < count; i++) {
885 if (device_is_enabled(xdev) &&
886 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport,
888 outb(xioport + com_mcr, 0);
896 if (COM_LLCONSOLE(flags)) {
897 printf("sio%d: reserved for low-level i/o\n",
898 device_get_unit(dev));
899 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
900 device_set_softc(dev, NULL);
909 * If the port is i8251 UART (internal, B98_01)
911 if (pc98_check_if_type(dev, &iod) == -1) {
912 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
913 device_set_softc(dev, NULL);
918 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1);
919 if (IS_8251(iod.if_type)) {
926 outb(iod.cmd, CMD8251_RESET);
927 DELAY(1000); /* for a while...*/
928 outb(iod.cmd, 0xf2); /* MODE (dummy) */
930 outb(iod.cmd, 0x01); /* CMD (dummy) */
931 DELAY(1000); /* for a while...*/
932 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) {
935 if (if_8251_type[iod.if_type & 0x0f].check_irq) {
937 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx));
938 outb( iod.ctrl, tmp|IEN_TxEMP );
940 result = isa_irq_pending() ? 0 : ENXIO;
941 outb( iod.ctrl, tmp );
945 * B98_01 doesn't activate TxEMP interrupt line
946 * when being reset, so we can't check irq pending.
950 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
952 device_set_softc(dev, NULL);
959 * If the device is on a multiport card and has an AST/4
960 * compatible interrupt control register, initialize this
961 * register and prepare to leave MCR_IENABLE clear in the mcr.
962 * Otherwise, prepare to set MCR_IENABLE in the mcr.
963 * Point idev to the device struct giving the correct id_irq.
964 * This is the struct for the master device if there is one.
967 mcr_image = MCR_IENABLE;
969 if (COM_ISMULTIPORT(flags)) {
975 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags));
977 printf("sio%d: master device %d not configured\n",
978 device_get_unit(dev), COM_MPMASTER(flags));
982 if (!COM_NOTAST4(flags)) {
983 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io,
986 if (bus_get_resource(idev, SYS_RES_IRQ, 0,
988 outb(xiobase + com_scr, 0x80);
990 outb(xiobase + com_scr, 0);
996 #endif /* COM_MULTIPORT */
997 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0)
1000 bzero(failures, sizeof failures);
1001 iobase = rman_get_start(port);
1004 if (iod.if_type == COM_IF_RSA98III) {
1007 outb(iobase + rsa_msr, 0x04);
1008 outb(iobase + rsa_frr, 0x00);
1009 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) {
1010 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1011 device_set_softc(dev, NULL);
1012 free(com, M_DEVBUF);
1015 outb(iobase + rsa_ier, 0x00);
1016 outb(iobase + rsa_frr, 0x00);
1017 outb(iobase + rsa_tivsr, 0x00);
1018 outb(iobase + rsa_tcr, 0x00);
1021 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write;
1025 switch (isa_get_irq(idev)) {
1026 case 3: irqout = 4; break;
1027 case 5: irqout = 5; break;
1028 case 6: irqout = 6; break;
1029 case 12: irqout = 7; break;
1031 printf("sio%d: irq configuration error\n",
1032 device_get_unit(dev));
1033 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1034 device_set_softc(dev, NULL);
1035 free(com, M_DEVBUF);
1038 outb((iobase & 0x00ff) | tmp, irqout);
1043 * We don't want to get actual interrupts, just masked ones.
1044 * Interrupts from this line should already be masked in the ICU,
1045 * but mask them in the processor as well in case there are some
1046 * (misconfigured) shared interrupts.
1048 mtx_lock_spin(&sio_lock);
1052 * Initialize the speed and the word size and wait long enough to
1053 * drain the maximum of 16 bytes of junk in device output queues.
1054 * The speed is undefined after a master reset and must be set
1055 * before relying on anything related to output. There may be
1056 * junk after a (very fast) soft reboot and (apparently) after
1058 * XXX what about the UART bug avoided by waiting in comparam()?
1059 * We don't want to to wait long enough to drain at 2 bps.
1061 if (iobase == siocniobase)
1062 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10));
1064 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS);
1065 divisor = siodivisor(rclk, SIO_TEST_SPEED);
1066 sio_setreg(com, com_dlbl, divisor & 0xff);
1067 sio_setreg(com, com_dlbh, divisor >> 8);
1068 sio_setreg(com, com_cfcr, CFCR_8BITS);
1069 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10));
1073 * Enable the interrupt gate and disable device interrupts. This
1074 * should leave the device driving the interrupt line low and
1075 * guarantee an edge trigger if an interrupt can be generated.
1078 sio_setreg(com, com_mcr, mcr_image);
1079 sio_setreg(com, com_ier, 0);
1080 DELAY(1000); /* XXX */
1081 irqmap[0] = isa_irq_pending();
1084 * Attempt to set loopback mode so that we can send a null byte
1085 * without annoying any external device.
1088 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK);
1091 * Attempt to generate an output interrupt. On 8250's, setting
1092 * IER_ETXRDY generates an interrupt independent of the current
1093 * setting and independent of whether the THR is empty. On 16450's,
1094 * setting IER_ETXRDY generates an interrupt independent of the
1095 * current setting. On 16550A's, setting IER_ETXRDY only
1096 * generates an interrupt when IER_ETXRDY is not already set.
1098 sio_setreg(com, com_ier, IER_ETXRDY);
1100 if (iod.if_type == COM_IF_RSA98III)
1101 outb(iobase + rsa_ier, 0x04);
1105 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate
1106 * an interrupt. They'd better generate one for actually doing
1107 * output. Loopback may be broken on the same incompatibles but
1108 * it's unlikely to do more than allow the null byte out.
1110 sio_setreg(com, com_data, 0);
1111 if (iobase == siocniobase)
1112 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10));
1114 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10));
1117 * Turn off loopback mode so that the interrupt gate works again
1118 * (MCR_IENABLE was hidden). This should leave the device driving
1119 * an interrupt line high. It doesn't matter if the interrupt
1120 * line oscillates while we are not looking at it, since interrupts
1124 sio_setreg(com, com_mcr, mcr_image);
1127 * It seems my Xircom CBEM56G Cardbus modem wants to be reset
1128 * to 8 bits *again*, or else probe test 0 will fail.
1129 * gwk@sgi.com, 4/19/2001
1131 sio_setreg(com, com_cfcr, CFCR_8BITS);
1134 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug",
1135 * so we probe for a buggy IIR_TXRDY implementation even in the
1136 * noprobe case. We don't probe for it in the !noprobe case because
1137 * noprobe is always set for PCMCIA cards and the problem is not
1138 * known to affect any other cards.
1141 /* Read IIR a few times. */
1142 for (fn = 0; fn < 2; fn ++) {
1144 failures[6] = sio_getreg(com, com_iir);
1147 /* IIR_TXRDY should be clear. Is it? */
1149 if (failures[6] & IIR_TXRDY) {
1151 * No. We seem to have the bug. Does our fix for
1154 sio_setreg(com, com_ier, 0);
1155 if (sio_getreg(com, com_iir) & IIR_NOPEND) {
1156 /* Yes. We discovered the TXRDY bug! */
1157 SET_FLAG(dev, COM_C_IIR_TXRDYBUG);
1159 /* No. Just fail. XXX */
1161 sio_setreg(com, com_mcr, 0);
1165 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG);
1167 sio_setreg(com, com_ier, 0);
1168 sio_setreg(com, com_cfcr, CFCR_8BITS);
1169 mtx_unlock_spin(&sio_lock);
1170 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1171 if (iobase == siocniobase)
1174 device_set_softc(dev, NULL);
1175 free(com, M_DEVBUF);
1182 * o the CFCR, IER and MCR in UART hold the values written to them
1183 * (the values happen to be all distinct - this is good for
1184 * avoiding false positive tests from bus echoes).
1185 * o an output interrupt is generated and its vector is correct.
1186 * o the interrupt goes away when the IIR in the UART is read.
1189 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS;
1190 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY;
1191 failures[2] = sio_getreg(com, com_mcr) - mcr_image;
1192 DELAY(10000); /* Some internal modems need this time */
1193 irqmap[1] = isa_irq_pending();
1194 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY;
1196 if (iod.if_type == COM_IF_RSA98III)
1197 inb(iobase + rsa_srr);
1199 DELAY(1000); /* XXX */
1200 irqmap[2] = isa_irq_pending();
1201 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1203 if (iod.if_type == COM_IF_RSA98III)
1204 inb(iobase + rsa_srr);
1208 * Turn off all device interrupts and check that they go off properly.
1209 * Leave MCR_IENABLE alone. For ports without a master port, it gates
1210 * the OUT2 output of the UART to
1211 * the ICU input. Closing the gate would give a floating ICU input
1212 * (unless there is another device driving it) and spurious interrupts.
1213 * (On the system that this was first tested on, the input floats high
1214 * and gives a (masked) interrupt as soon as the gate is closed.)
1216 sio_setreg(com, com_ier, 0);
1217 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */
1218 failures[7] = sio_getreg(com, com_ier);
1220 if (iod.if_type == COM_IF_RSA98III)
1221 outb(iobase + rsa_ier, 0x00);
1223 DELAY(1000); /* XXX */
1224 irqmap[3] = isa_irq_pending();
1225 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND;
1227 if (iod.if_type == COM_IF_RSA98III) {
1228 inb(iobase + rsa_srr);
1229 outb(iobase + rsa_frr, 0x00);
1233 mtx_unlock_spin(&sio_lock);
1235 irqs = irqmap[1] & ~irqmap[0];
1236 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 &&
1237 ((1 << xirq) & irqs) == 0) {
1239 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n",
1240 device_get_unit(dev), xirq, irqs);
1242 "sio%d: port may not be enabled\n",
1243 device_get_unit(dev));
1246 printf("sio%d: irq maps: %#x %#x %#x %#x\n",
1247 device_get_unit(dev),
1248 irqmap[0], irqmap[1], irqmap[2], irqmap[3]);
1251 for (fn = 0; fn < sizeof failures; ++fn)
1253 sio_setreg(com, com_mcr, 0);
1256 printf("sio%d: probe failed test(s):",
1257 device_get_unit(dev));
1258 for (fn = 0; fn < sizeof failures; ++fn)
1265 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1266 if (iobase == siocniobase)
1269 device_set_softc(dev, NULL);
1270 free(com, M_DEVBUF);
1277 espattach(com, esp_port)
1285 * Check the ESP-specific I/O port to see if we're an ESP
1286 * card. If not, return failure immediately.
1288 if ((inb(esp_port) & 0xf3) == 0) {
1289 printf(" port 0x%x is not an ESP board?\n", esp_port);
1294 * We've got something that claims to be a Hayes ESP card.
1298 /* Get the dip-switch configuration */
1300 outb(esp_port + ESP98_CMD1, ESP_GETDIPS);
1301 dips = inb(esp_port + ESP98_STATUS1);
1303 outb(esp_port + ESP_CMD1, ESP_GETDIPS);
1304 dips = inb(esp_port + ESP_STATUS1);
1308 * Bits 0,1 of dips say which COM port we are.
1311 if ((rman_get_start(com->ioportres) & 0xff) ==
1312 likely_com_ports[dips & 0x03])
1314 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03])
1318 printf(" esp_port has com %d\n", dips & 0x03);
1323 * Check for ESP version 2.0 or later: bits 4,5,6 = 010.
1326 outb(esp_port + ESP98_CMD1, ESP_GETTEST);
1327 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */
1328 val = inb(esp_port + ESP98_STATUS2);
1330 outb(esp_port + ESP_CMD1, ESP_GETTEST);
1331 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */
1332 val = inb(esp_port + ESP_STATUS2);
1334 if ((val & 0x70) < 0x20) {
1335 printf("-old (%o)", val & 0x70);
1340 * Check for ability to emulate 16550: bit 7 == 1
1342 if ((dips & 0x80) == 0) {
1348 * Okay, we seem to be a Hayes ESP card. Whee.
1351 com->esp_port = esp_port;
1354 #endif /* COM_ESP */
1357 sioattach(dev, xrid, rclk)
1370 struct resource *port;
1377 int if_type = GET_IFTYPE(device_get_flags(dev));
1382 if (IS_8251(if_type)) {
1383 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1385 } else if (if_type == COM_IF_MODEM_CARD ||
1386 if_type == COM_IF_RSA98III ||
1387 isa_get_vendorid(dev)) {
1388 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0,
1389 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1391 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid,
1392 if_16550a_type[if_type & 0x0f].iat,
1393 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE);
1396 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1397 0, ~0, IO_COMSIZE, RF_ACTIVE);
1402 if (!IS_8251(if_type)) {
1403 if (isa_load_resourcev(port,
1404 if_16550a_type[if_type & 0x0f].iat,
1405 if_16550a_type[if_type & 0x0f].iatsz) != 0) {
1406 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1412 iobase = rman_get_start(port);
1413 unit = device_get_unit(dev);
1414 com = device_get_softc(dev);
1415 flags = device_get_flags(dev);
1417 if (unit >= sio_numunits)
1418 sio_numunits = unit + 1;
1422 if (if_type == COM_IF_RSA98III)
1424 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) {
1425 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1428 bzero(obuf, obufsize * 2);
1432 * sioprobe() has initialized the device registers as follows:
1433 * o cfcr = CFCR_8BITS.
1434 * It is most important that CFCR_DLAB is off, so that the
1435 * data port is not hidden when we enable interrupts.
1437 * Interrupts are only enabled when the line is open.
1438 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible
1439 * interrupt control register or the config specifies no irq.
1440 * Keeping MCR_DTR and MCR_RTS off might stop the external
1441 * device from sending before we are ready.
1443 bzero(com, sizeof *com);
1445 com->ioportres = port;
1446 com->ioportrid = rid;
1447 com->bst = rman_get_bustag(port);
1448 com->bsh = rman_get_bushandle(port);
1449 com->cfcr_image = CFCR_8BITS;
1450 com->loses_outints = COM_LOSESOUTINTS(flags) != 0;
1451 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0;
1452 com->tx_fifo_size = 1;
1454 com->obufsize = obufsize;
1456 com->obuf2 = obuf + obufsize;
1458 com->obufs[0].l_head = com->obuf1;
1459 com->obufs[1].l_head = com->obuf2;
1462 com->pc98_if_type = if_type;
1464 if (IS_8251(if_type)) {
1465 pc98_set_ioport(com);
1467 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) {
1468 com->pc98_8251fifo = 1;
1469 com->pc98_8251fifo_enable = 0;
1472 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat;
1474 com->data_port = iobase + iat[com_data];
1475 com->int_ctl_port = iobase + iat[com_ier];
1476 com->int_id_port = iobase + iat[com_iir];
1477 com->modem_ctl_port = iobase + iat[com_mcr];
1478 com->mcr_image = inb(com->modem_ctl_port);
1479 com->line_status_port = iobase + iat[com_lsr];
1480 com->modem_status_port = iobase + iat[com_msr];
1482 #else /* not PC98 */
1483 com->data_port = iobase + com_data;
1484 com->int_ctl_port = iobase + com_ier;
1485 com->int_id_port = iobase + com_iir;
1486 com->modem_ctl_port = iobase + com_mcr;
1487 com->mcr_image = inb(com->modem_ctl_port);
1488 com->line_status_port = iobase + com_lsr;
1489 com->modem_status_port = iobase + com_msr;
1492 tp = com->tp = ttyalloc();
1493 tp->t_oproc = comstart;
1494 tp->t_param = comparam;
1495 tp->t_stop = comstop;
1496 tp->t_modem = commodem;
1497 tp->t_break = combreak;
1498 tp->t_close = comclose;
1499 tp->t_open = comopen;
1503 if (!IS_8251(if_type) && rclk == 0)
1504 rclk = if_16550a_type[if_type & 0x0f].rclk;
1507 rclk = DEFAULT_RCLK;
1511 if (unit == comconsole)
1512 ttyconsolemode(tp, comdefaultrate);
1513 error = siosetwater(com, tp->t_init_in.c_ispeed);
1514 mtx_unlock_spin(&sio_lock);
1517 * Leave i/o resources allocated if this is a `cn'-level
1518 * console, so that other devices can't snarf them.
1520 if (iobase != siocniobase)
1521 bus_release_resource(dev, SYS_RES_IOPORT, rid, port);
1525 /* attempt to determine UART type */
1526 printf("sio%d: type", unit);
1529 if (!COM_ISMULTIPORT(flags) &&
1530 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) {
1535 scr = sio_getreg(com, com_scr);
1536 sio_setreg(com, com_scr, 0xa5);
1537 scr1 = sio_getreg(com, com_scr);
1538 sio_setreg(com, com_scr, 0x5a);
1539 scr2 = sio_getreg(com, com_scr);
1540 sio_setreg(com, com_scr, scr);
1541 if (scr1 != 0xa5 || scr2 != 0x5a) {
1542 printf(" 8250 or not responding");
1543 goto determined_type;
1548 if (IS_8251(com->pc98_if_type)) {
1549 if (com->pc98_8251fifo && !COM_NOFIFO(flags))
1550 com->tx_fifo_size = 16;
1551 com_int_TxRx_disable( com );
1552 com_cflag_and_speed_set( com, tp->t_init_in.c_cflag, comdefaultrate );
1553 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE );
1554 com_send_break_off( com );
1556 if (com->pc98_if_type == COM_IF_INTERNAL) {
1557 printf(" (internal%s%s)",
1558 com->pc98_8251fifo ? " fifo" : "",
1559 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ?
1562 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name);
1566 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH);
1568 switch (inb(com->int_id_port) & IIR_FIFO_MASK) {
1579 if (COM_NOFIFO(flags)) {
1580 printf(" 16550A fifo disabled");
1583 com->hasfifo = TRUE;
1585 if (com->pc98_if_type == COM_IF_RSA98III) {
1586 com->tx_fifo_size = 2048;
1587 com->rsabase = iobase;
1588 outb(com->rsabase + rsa_ier, 0x00);
1589 outb(com->rsabase + rsa_frr, 0x00);
1592 if (COM_ST16650A(flags)) {
1593 printf(" ST16650A");
1594 com->st16650a = TRUE;
1595 com->tx_fifo_size = 32;
1598 if (COM_TI16754(flags)) {
1600 com->tx_fifo_size = 64;
1607 if (com->pc98_if_type == COM_IF_ESP98)
1609 for (espp = likely_esp_ports; *espp != 0; espp++)
1610 if (espattach(com, *espp)) {
1611 com->tx_fifo_size = 1024;
1618 com->tx_fifo_size = 16;
1620 com->tx_fifo_size = COM_FIFOSIZE(flags);
1621 if (com->tx_fifo_size == 0)
1622 com->tx_fifo_size = 16;
1624 printf(" lookalike with %u bytes FIFO",
1631 if (com->pc98_if_type == COM_IF_RSB3000) {
1632 /* Set RSB-2000/3000 Extended Buffer mode. */
1634 lcr = sio_getreg(com, com_cfcr);
1635 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB);
1636 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE);
1637 sio_setreg(com, com_cfcr, lcr);
1644 * Set 16550 compatibility mode.
1645 * We don't use the ESP_MODE_SCALE bit to increase the
1646 * fifo trigger levels because we can't handle large
1648 * XXX flow control should be set in comparam(), not here.
1651 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE);
1652 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1654 outb(com->esp_port + ESP_CMD1, ESP_SETMODE);
1655 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO);
1658 /* Set RTS/CTS flow control. */
1660 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE);
1661 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS);
1662 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS);
1664 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE);
1665 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS);
1666 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS);
1669 /* Set flow-control levels. */
1671 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW);
1672 outb(com->esp_port + ESP98_CMD2, HIBYTE(768));
1673 outb(com->esp_port + ESP98_CMD2, LOBYTE(768));
1674 outb(com->esp_port + ESP98_CMD2, HIBYTE(512));
1675 outb(com->esp_port + ESP98_CMD2, LOBYTE(512));
1677 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW);
1678 outb(com->esp_port + ESP_CMD2, HIBYTE(768));
1679 outb(com->esp_port + ESP_CMD2, LOBYTE(768));
1680 outb(com->esp_port + ESP_CMD2, HIBYTE(512));
1681 outb(com->esp_port + ESP_CMD2, LOBYTE(512));
1685 /* Set UART clock prescaler. */
1686 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK);
1687 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */
1690 #endif /* COM_ESP */
1691 sio_setreg(com, com_fifo, 0);
1693 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name);
1698 #ifdef COM_MULTIPORT
1699 if (COM_ISMULTIPORT(flags)) {
1702 com->multiport = TRUE;
1703 printf(" (multiport");
1704 if (unit == COM_MPMASTER(flags))
1707 masterdev = devclass_get_device(sio_devclass,
1708 COM_MPMASTER(flags));
1709 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev,
1710 SYS_RES_IRQ, 0, NULL, NULL) != 0);
1712 #endif /* COM_MULTIPORT */
1716 if (unit == comconsole)
1717 printf(", console");
1718 if (COM_IIR_TXRDYBUG(flags))
1719 printf(" with a buggy IIR_TXRDY implementation");
1722 if (sio_fast_ih == NULL) {
1723 swi_add(&tty_intr_event, "sio", siopoll, NULL, SWI_TTY, 0,
1725 swi_add(&clk_intr_event, "sio", siopoll, NULL, SWI_CLOCK, 0,
1730 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
1731 tp->t_pps = &com->pps;
1733 if (COM_PPSCTS(flags))
1734 com->pps_bit = MSR_CTS;
1736 com->pps_bit = MSR_DCD;
1737 pps_init(&com->pps);
1740 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
1742 ret = bus_setup_intr(dev, com->irqres,
1744 siointr, NULL, com, &com->cookie);
1746 ret = bus_setup_intr(dev,
1747 com->irqres, INTR_TYPE_TTY,
1748 NULL, (driver_intr_t *)siointr,
1751 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n");
1754 device_printf(dev, "could not activate interrupt\n");
1755 #if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \
1756 defined(ALT_BREAK_TO_DEBUGGER))
1758 * Enable interrupts for early break-to-debugger support
1761 if (ret == 0 && unit == comconsole)
1762 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS |
1767 /* We're ready, open the doors... */
1768 ttycreate(tp, TS_CALLOUT, "d%r", unit);
1774 comopen(struct tty *tp, struct cdev *dev)
1780 com->poll = com->no_irq;
1781 com->poll_output = com->loses_outints;
1783 if (IS_8251(com->pc98_if_type)) {
1784 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS);
1785 pc98_msrint_start(dev);
1786 if (com->pc98_8251fifo) {
1787 com->pc98_8251fifo_enable = 1;
1789 FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST);
1795 * (Re)enable and drain fifos.
1797 * Certain SMC chips cause problems if the fifos
1798 * are enabled while input is ready. Turn off the
1799 * fifo if necessary to clear the input. We test
1800 * the input ready bit after enabling the fifos
1801 * since we've already enabled them in comparam()
1802 * and to handle races between enabling and fresh
1805 for (i = 0; i < 500; i++) {
1806 sio_setreg(com, com_fifo,
1807 FIFO_RCV_RST | FIFO_XMT_RST | com->fifo_image);
1809 if (com->pc98_if_type == COM_IF_RSA98III)
1810 outb(com->rsabase + rsa_frr , 0x00);
1813 * XXX the delays are for superstitious
1814 * historical reasons. It must be less than
1815 * the character time at the maximum
1816 * supported speed (87 usec at 115200 bps
1817 * 8N1). Otherwise we might loop endlessly
1818 * if data is streaming in. We used to use
1819 * delays of 100. That usually worked
1820 * because DELAY(100) used to usually delay
1821 * for about 85 usec instead of 100.
1825 if (com->pc98_if_type == COM_IF_RSA98III ?
1826 !(inb(com->rsabase + rsa_srr) & 0x08) :
1827 !(inb(com->line_status_port) & LSR_RXRDY))
1830 if (!(inb(com->line_status_port) & LSR_RXRDY))
1833 sio_setreg(com, com_fifo, 0);
1835 (void) inb(com->data_port);
1841 mtx_lock_spin(&sio_lock);
1843 if (IS_8251(com->pc98_if_type)) {
1844 com_tiocm_bis(com, TIOCM_LE);
1845 com->pc98_prev_modem_status = pc98_get_modem_status(com);
1846 com_int_Rx_enable(com);
1849 (void) inb(com->line_status_port);
1850 (void) inb(com->data_port);
1851 com->prev_modem_status = com->last_modem_status
1852 = inb(com->modem_status_port);
1853 outb(com->int_ctl_port,
1854 IER_ERXRDY | IER_ERLS | IER_EMSC
1855 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY));
1857 if (com->pc98_if_type == COM_IF_RSA98III) {
1858 outb(com->rsabase + rsa_ier, 0x1d);
1859 outb(com->int_ctl_port, IER_ERLS | IER_EMSC);
1865 mtx_unlock_spin(&sio_lock);
1867 /* XXX: should be generic ? */
1869 if ((IS_8251(com->pc98_if_type) &&
1870 (pc98_get_modem_status(com) & TIOCM_CAR)) ||
1871 (!IS_8251(com->pc98_if_type) &&
1872 (com->prev_modem_status & MSR_DCD)) ||
1876 if (com->prev_modem_status & MSR_DCD || ISCALLOUT(dev))
1892 com->poll_output = FALSE;
1894 com_send_break_off(com);
1896 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
1899 #if defined(KDB) && (defined(BREAK_TO_DEBUGGER) || \
1900 defined(ALT_BREAK_TO_DEBUGGER))
1902 * Leave interrupts enabled and don't clear DTR if this is the
1903 * console. This allows us to detect break-to-debugger events
1904 * while the console device is closed.
1906 if (com->unit != comconsole)
1911 if (IS_8251(com->pc98_if_type))
1912 com_int_TxRx_disable(com);
1914 sio_setreg(com, com_ier, 0);
1915 if (com->pc98_if_type == COM_IF_RSA98III)
1916 outb(com->rsabase + rsa_ier, 0x00);
1917 if (IS_8251(com->pc98_if_type))
1918 tmp = pc98_get_modem_status(com) & TIOCM_CAR;
1920 tmp = com->prev_modem_status & MSR_DCD;
1922 sio_setreg(com, com_ier, 0);
1924 if (tp->t_cflag & HUPCL
1926 * XXX we will miss any carrier drop between here and the
1927 * next open. Perhaps we should watch DCD even when the
1928 * port is closed; it is not sufficient to check it at
1929 * the next open because it might go up and down while
1930 * we're not watching.
1936 && !(com->prev_modem_status & MSR_DCD)
1938 && !(tp->t_init_in.c_cflag & CLOCAL))
1939 || !(tp->t_state & TS_ISOPEN)) {
1941 if (IS_8251(com->pc98_if_type))
1942 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
1945 (void)commodem(tp, 0, SER_DTR);
1946 ttydtrwaitstart(tp);
1950 if (IS_8251(com->pc98_if_type))
1951 com_tiocm_bic(com, TIOCM_LE);
1956 if (com->pc98_8251fifo) {
1957 if (com->pc98_8251fifo_enable)
1958 outb(I8251F_fcr, FIFO_XMT_RST | FIFO_RCV_RST);
1959 com->pc98_8251fifo_enable = 0;
1964 * Disable fifos so that they are off after controlled
1965 * reboots. Some BIOSes fail to detect 16550s when the
1966 * fifos are enabled.
1968 sio_setreg(com, com_fifo, 0);
1970 tp->t_actout = FALSE;
1971 wakeup(&tp->t_actout);
1972 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */
1984 com = (struct com_s *)chan;
1987 * Clear TS_BUSY if low-level output is complete.
1988 * spl locking is sufficient because siointr1() does not set CS_BUSY.
1989 * If siointr1() clears CS_BUSY after we look at it, then we'll get
1990 * called again. Reading the line status port outside of siointr1()
1991 * is safe because CS_BUSY is clear so there are no output interrupts
1995 if (com->state & CS_BUSY)
1996 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */
1998 else if ((IS_8251(com->pc98_if_type) &&
1999 ((com->pc98_8251fifo_enable &&
2000 (inb(I8251F_lsr) & (FLSR_TxRDY | FLSR_TxEMP))
2001 == (FLSR_TxRDY | FLSR_TxEMP)) ||
2002 (!com->pc98_8251fifo_enable &&
2003 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP))
2004 == (STS8251_TxRDY | STS8251_TxEMP)))) ||
2005 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2006 == (LSR_TSRE | LSR_TXRDY))) {
2008 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY))
2009 == (LSR_TSRE | LSR_TXRDY)) {
2011 com->tp->t_state &= ~TS_BUSY;
2013 com->extra_state &= ~CSE_BUSYCHECK;
2015 timeout(siobusycheck, com, hz / 100);
2020 siodivisor(rclk, speed)
2030 #if UINT_MAX > (ULONG_MAX - 1) / 8
2031 if (speed > (ULONG_MAX - 1) / 8)
2034 divisor = (rclk / (8UL * speed) + 1) / 2;
2035 if (divisor == 0 || divisor >= 65536)
2037 actual_speed = rclk / (16UL * divisor);
2039 /* 10 times error in percent: */
2040 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2;
2042 /* 3.0% maximum error tolerance: */
2043 if (error < -30 || error > 30)
2050 * Call this function with the sio_lock mutex held. It will return with the
2065 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) {
2066 com_events -= (com->iptr - com->ibuf);
2067 com->iptr = com->ibuf;
2070 if (tp->t_state & TS_CAN_BYPASS_L_RINT) {
2072 * Avoid the grotesquely inefficient lineswitch routine
2073 * (ttyinput) in "raw" mode. It usually takes about 450
2074 * instructions (that's without canonical processing or echo!).
2075 * slinput is reasonably fast (usually 40 instructions plus
2080 * This may look odd, but it is using save-and-enable
2081 * semantics instead of the save-and-disable semantics
2082 * that are used everywhere else.
2084 mtx_unlock_spin(&sio_lock);
2085 incc = com->iptr - buf;
2086 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat
2087 && (com->state & CS_RTS_IFLOW
2088 || tp->t_iflag & IXOFF)
2089 && !(tp->t_state & TS_TBLOCK))
2091 com->delta_error_counts[CE_TTY_BUF_OVERFLOW]
2092 += b_to_q((char *)buf, incc, &tp->t_rawq);
2096 tp->t_rawcc += incc;
2098 if (tp->t_state & TS_TTSTOP
2099 && (tp->t_iflag & IXANY
2100 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) {
2101 tp->t_state &= ~TS_TTSTOP;
2102 tp->t_lflag &= ~FLUSHO;
2105 mtx_lock_spin(&sio_lock);
2106 } while (buf < com->iptr);
2110 * This may look odd, but it is using save-and-enable
2111 * semantics instead of the save-and-disable semantics
2112 * that are used everywhere else.
2114 mtx_unlock_spin(&sio_lock);
2115 line_status = buf[com->ierroff];
2118 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) {
2119 if (line_status & LSR_BI)
2120 recv_data |= TTY_BI;
2121 if (line_status & LSR_FE)
2122 recv_data |= TTY_FE;
2123 if (line_status & LSR_OE)
2124 recv_data |= TTY_OE;
2125 if (line_status & LSR_PE)
2126 recv_data |= TTY_PE;
2128 ttyld_rint(tp, recv_data);
2129 mtx_lock_spin(&sio_lock);
2130 } while (buf < com->iptr);
2132 com_events -= (com->iptr - com->ibuf);
2133 com->iptr = com->ibuf;
2136 * There is now room for another low-level buffer full of input,
2137 * so enable RTS if it is now disabled and there is room in the
2138 * high-level buffer.
2141 if (IS_8251(com->pc98_if_type)) {
2142 if ((com->state & CS_RTS_IFLOW) &&
2143 !(com_tiocm_get(com) & TIOCM_RTS) &&
2144 !(tp->t_state & TS_TBLOCK))
2145 com_tiocm_bis(com, TIOCM_RTS);
2147 if ((com->state & CS_RTS_IFLOW) &&
2148 !(com->mcr_image & MCR_RTS) &&
2149 !(tp->t_state & TS_TBLOCK))
2150 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2153 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) &&
2154 !(tp->t_state & TS_TBLOCK))
2155 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2164 #if defined(PC98) && defined(COM_MULTIPORT)
2165 u_char rsa_buf_status;
2168 #ifndef COM_MULTIPORT
2169 com = (struct com_s *)arg;
2171 mtx_lock_spin(&sio_lock);
2173 mtx_unlock_spin(&sio_lock);
2174 #else /* COM_MULTIPORT */
2175 bool_t possibly_more_intrs;
2179 * Loop until there is no activity on any port. This is necessary
2180 * to get an interrupt edge more than to avoid another interrupt.
2181 * If the IRQ signal is just an OR of the IRQ signals from several
2182 * devices, then the edge from one may be lost because another is
2185 mtx_lock_spin(&sio_lock);
2187 possibly_more_intrs = FALSE;
2188 for (unit = 0; unit < sio_numunits; ++unit) {
2189 com = com_addr(unit);
2192 * would it work here, or be counter-productive?
2197 && IS_8251(com->pc98_if_type)) {
2199 } else if (com != NULL
2201 && com->pc98_if_type == COM_IF_RSA98III) {
2203 inb(com->rsabase + rsa_srr) & 0xc9;
2204 if ((rsa_buf_status & 0xc8)
2205 || !(rsa_buf_status & 0x01)) {
2207 if (rsa_buf_status !=
2208 (inb(com->rsabase + rsa_srr) & 0xc9))
2209 possibly_more_intrs = TRUE;
2215 && (inb(com->int_id_port) & IIR_IMASK)
2218 possibly_more_intrs = TRUE;
2220 /* XXX COM_UNLOCK(); */
2222 } while (possibly_more_intrs);
2223 mtx_unlock_spin(&sio_lock);
2224 #endif /* COM_MULTIPORT */
2225 return (FILTER_HANDLED);
2228 static struct timespec siots[8];
2230 static int volatile siotsunit = -1;
2233 sysctl_siots(SYSCTL_HANDLER_ARGS)
2240 for (i = 1, tso = siotso; i < tso; i++) {
2241 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) *
2243 (siots[i].tv_nsec - siots[i - 1].tv_nsec);
2244 len = sprintf(buf, "%lld\n", delta);
2245 if (delta >= 110000)
2246 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n",
2247 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1;
2249 buf[len - 1] = '\0';
2250 error = SYSCTL_OUT(req, buf, len);
2258 SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD,
2259 0, 0, sysctl_siots, "A", "sio timestamps");
2268 u_char modem_status;
2273 u_char rsa_buf_status = 0;
2274 int rsa_tx_fifo_size = 0;
2276 #if defined(KDB) && defined(ALT_BREAK_TO_DEBUGGER)
2282 if (COM_IIR_TXRDYBUG(com->flags)) {
2283 int_ctl = inb(com->int_ctl_port);
2284 int_ctl_new = int_ctl;
2290 while (!com->gone) {
2293 if (IS_8251(com->pc98_if_type)) {
2294 if (com->pc98_8251fifo_enable)
2295 tmp = inb(I8251F_lsr);
2297 tmp = inb(com->sts_port);
2300 if (com->pc98_8251fifo_enable) {
2301 if (tmp & FLSR_TxRDY) line_status |= LSR_TXRDY;
2302 if (tmp & FLSR_RxRDY) line_status |= LSR_RXRDY;
2303 if (tmp & FLSR_TxEMP) line_status |= LSR_TSRE;
2304 if (tmp & FLSR_PE) line_status |= LSR_PE;
2305 if (tmp & FLSR_OE) line_status |= LSR_OE;
2306 if (tmp & FLSR_BI) line_status |= LSR_BI;
2308 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY;
2309 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY;
2310 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE;
2311 if (tmp & STS8251_PE) line_status |= LSR_PE;
2312 if (tmp & STS8251_OE) line_status |= LSR_OE;
2313 if (tmp & STS8251_FE) line_status |= LSR_FE;
2314 if (tmp & STS8251_BI) line_status |= LSR_BI;
2318 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) {
2319 modem_status = inb(com->modem_status_port);
2320 if ((modem_status ^ com->last_modem_status) &
2322 pps_capture(&com->pps);
2323 pps_event(&com->pps,
2324 (modem_status & com->pps_bit) ?
2325 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
2328 line_status = inb(com->line_status_port);
2331 if (com->pc98_if_type == COM_IF_RSA98III)
2332 rsa_buf_status = inb(com->rsabase + rsa_srr);
2335 /* input event? (check first to help avoid overruns) */
2337 while (line_status & LSR_RCV_MASK) {
2339 while ((line_status & LSR_RCV_MASK)
2340 || (com->pc98_if_type == COM_IF_RSA98III
2341 && (rsa_buf_status & 0x08))) {
2343 /* break/unnattached error bits or real input? */
2345 if (IS_8251(com->pc98_if_type)) {
2346 if (com->pc98_8251fifo_enable) {
2347 recv_data = inb(I8251F_data);
2349 (FLSR_PE | FLSR_OE | FLSR_BI)) {
2350 pc98_i8251_or_cmd(com, CMD8251_ER);
2354 recv_data = inb(com->data_port);
2355 if (tmp & (STS8251_PE | STS8251_OE |
2356 STS8251_FE | STS8251_BI)) {
2357 pc98_i8251_or_cmd(com, CMD8251_ER);
2361 } else if (com->pc98_if_type == COM_IF_RSA98III) {
2362 if (!(rsa_buf_status & 0x08))
2365 recv_data = inb(com->data_port);
2368 if (!(line_status & LSR_RXRDY))
2371 recv_data = inb(com->data_port);
2373 #ifdef ALT_BREAK_TO_DEBUGGER
2374 if (com->unit == comconsole &&
2375 (kdb_brk = kdb_alt_break(recv_data,
2376 &com->alt_brk_state)) != 0) {
2377 mtx_unlock_spin(&sio_lock);
2379 case KDB_REQ_DEBUGGER:
2380 kdb_enter(KDB_WHY_BREAK,
2381 "Break sequence on console");
2384 kdb_panic("panic on console");
2386 case KDB_REQ_REBOOT:
2390 mtx_lock_spin(&sio_lock);
2393 #endif /* ALT_BREAK_TO_DEBUGGER */
2395 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) {
2397 * Don't store BI if IGNBRK or FE/PE if IGNPAR.
2398 * Otherwise, push the work to a higher level
2399 * (to handle PARMRK) if we're bypassing.
2400 * Otherwise, convert BI/FE and PE+INPCK to 0.
2402 * This makes bypassing work right in the
2403 * usual "raw" case (IGNBRK set, and IGNPAR
2406 * Note: BI together with FE/PE means just BI.
2408 if (line_status & LSR_BI) {
2409 #if defined(KDB) && defined(BREAK_TO_DEBUGGER)
2410 if (com->unit == comconsole) {
2411 kdb_enter(KDB_WHY_BREAK,
2412 "Line break on console");
2417 || com->tp->t_iflag & IGNBRK)
2421 || com->tp->t_iflag & IGNPAR)
2424 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT
2425 && (line_status & (LSR_BI | LSR_FE)
2426 || com->tp->t_iflag & INPCK))
2430 if (com->tp != NULL &&
2431 com->tp->t_hotchar != 0 && recv_data == com->tp->t_hotchar)
2432 swi_sched(sio_fast_ih, 0);
2434 if (ioptr >= com->ibufend)
2435 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW);
2437 if (com->tp != NULL && com->tp->t_do_timestamp)
2438 microtime(&com->tp->t_timestamp);
2440 swi_sched(sio_slow_ih, SWI_DELAY);
2441 #if 0 /* for testing input latency vs efficiency */
2442 if (com->iptr - com->ibuf == 8)
2443 swi_sched(sio_fast_ih, 0);
2445 ioptr[0] = recv_data;
2446 ioptr[com->ierroff] = line_status;
2447 com->iptr = ++ioptr;
2448 if (ioptr == com->ihighwater
2449 && com->state & CS_RTS_IFLOW)
2451 IS_8251(com->pc98_if_type) ?
2452 com_tiocm_bic(com, TIOCM_RTS) :
2454 outb(com->modem_ctl_port,
2455 com->mcr_image &= ~MCR_RTS);
2456 if (line_status & LSR_OE)
2457 CE_RECORD(com, CE_OVERRUN);
2460 if (line_status & LSR_TXRDY
2461 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY))
2465 * "& 0x7F" is to avoid the gcc-1.40 generating a slow
2466 * jump from the top of the loop to here
2469 if (IS_8251(com->pc98_if_type))
2473 line_status = inb(com->line_status_port) & 0x7F;
2475 if (com->pc98_if_type == COM_IF_RSA98III)
2476 rsa_buf_status = inb(com->rsabase + rsa_srr);
2480 /* modem status change? (always check before doing output) */
2482 if (!IS_8251(com->pc98_if_type)) {
2484 modem_status = inb(com->modem_status_port);
2485 if (modem_status != com->last_modem_status) {
2487 * Schedule high level to handle DCD changes. Note
2488 * that we don't use the delta bits anywhere. Some
2489 * UARTs mess them up, and it's easy to remember the
2490 * previous bits and calculate the delta.
2492 com->last_modem_status = modem_status;
2493 if (!(com->state & CS_CHECKMSR)) {
2494 com_events += LOTS_OF_EVENTS;
2495 com->state |= CS_CHECKMSR;
2496 swi_sched(sio_fast_ih, 0);
2499 /* handle CTS change immediately for crisp flow ctl */
2500 if (com->state & CS_CTS_OFLOW) {
2501 if (modem_status & MSR_CTS)
2502 com->state |= CS_ODEVREADY;
2504 com->state &= ~CS_ODEVREADY;
2512 /* output queued and everything ready? */
2514 if (line_status & LSR_TXRDY
2515 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2517 if (((com->pc98_if_type == COM_IF_RSA98III)
2518 ? (rsa_buf_status & 0x02)
2519 : (line_status & LSR_TXRDY))
2520 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) {
2523 Port_t tmp_data_port;
2525 if (IS_8251(com->pc98_if_type) &&
2526 com->pc98_8251fifo_enable)
2527 tmp_data_port = I8251F_data;
2529 tmp_data_port = com->data_port;
2532 ioptr = com->obufq.l_head;
2533 if (com->tx_fifo_size > 1 && com->unit != siotsunit) {
2536 ocount = com->obufq.l_tail - ioptr;
2538 if (com->pc98_if_type == COM_IF_RSA98III) {
2539 rsa_buf_status = inb(com->rsabase + rsa_srr);
2540 rsa_tx_fifo_size = 1024;
2541 if (!(rsa_buf_status & 0x01))
2542 rsa_tx_fifo_size = 2048;
2543 if (ocount > rsa_tx_fifo_size)
2544 ocount = rsa_tx_fifo_size;
2547 if (ocount > com->tx_fifo_size)
2548 ocount = com->tx_fifo_size;
2549 com->bytes_out += ocount;
2552 outb(tmp_data_port, *ioptr++);
2554 outb(com->data_port, *ioptr++);
2556 while (--ocount != 0);
2559 outb(tmp_data_port, *ioptr++);
2561 outb(com->data_port, *ioptr++);
2564 if (com->unit == siotsunit
2565 && siotso < sizeof siots / sizeof siots[0])
2566 nanouptime(&siots[siotso++]);
2569 if (IS_8251(com->pc98_if_type))
2570 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG))
2571 com_int_Tx_enable(com);
2573 com->obufq.l_head = ioptr;
2574 if (COM_IIR_TXRDYBUG(com->flags))
2575 int_ctl_new = int_ctl | IER_ETXRDY;
2576 if (ioptr >= com->obufq.l_tail) {
2579 qp = com->obufq.l_next;
2580 qp->l_queued = FALSE;
2583 com->obufq.l_head = qp->l_head;
2584 com->obufq.l_tail = qp->l_tail;
2585 com->obufq.l_next = qp;
2587 /* output just completed */
2588 if (COM_IIR_TXRDYBUG(com->flags))
2589 int_ctl_new = int_ctl
2591 com->state &= ~CS_BUSY;
2593 if (IS_8251(com->pc98_if_type) &&
2594 pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
2595 com_int_Tx_disable(com);
2598 if (!(com->state & CS_ODONE)) {
2599 com_events += LOTS_OF_EVENTS;
2600 com->state |= CS_ODONE;
2601 /* handle at high level ASAP */
2602 swi_sched(sio_fast_ih, 0);
2606 if (COM_IIR_TXRDYBUG(com->flags)
2607 && int_ctl != int_ctl_new) {
2608 if (com->pc98_if_type == COM_IF_RSA98III) {
2609 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY);
2610 outb(com->int_ctl_port, int_ctl_new);
2611 outb(com->rsabase + rsa_ier, 0x1d);
2613 outb(com->int_ctl_port, int_ctl_new);
2616 if (COM_IIR_TXRDYBUG(com->flags)
2617 && int_ctl != int_ctl_new)
2618 outb(com->int_ctl_port, int_ctl_new);
2622 else if (line_status & LSR_TXRDY) {
2623 if (IS_8251(com->pc98_if_type))
2624 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG)
2625 com_int_Tx_disable(com);
2627 if (IS_8251(com->pc98_if_type)) {
2628 if (com->pc98_8251fifo_enable) {
2629 if ((tmp = inb(I8251F_lsr)) & FLSR_RxRDY)
2632 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY)
2639 #ifndef COM_MULTIPORT
2641 if (IS_8251(com->pc98_if_type))
2644 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND)
2645 #endif /* COM_MULTIPORT */
2650 /* software interrupt handler for SWI_TTY */
2652 siopoll(void *dummy)
2656 if (com_events == 0)
2659 for (unit = 0; unit < sio_numunits; ++unit) {
2664 com = com_addr(unit);
2668 if (tp == NULL || com->gone) {
2670 * Discard any events related to never-opened or
2671 * going-away devices.
2673 mtx_lock_spin(&sio_lock);
2674 incc = com->iptr - com->ibuf;
2675 com->iptr = com->ibuf;
2676 if (com->state & CS_CHECKMSR) {
2677 incc += LOTS_OF_EVENTS;
2678 com->state &= ~CS_CHECKMSR;
2681 mtx_unlock_spin(&sio_lock);
2684 if (com->iptr != com->ibuf) {
2685 mtx_lock_spin(&sio_lock);
2687 mtx_unlock_spin(&sio_lock);
2689 if (com->state & CS_CHECKMSR) {
2690 u_char delta_modem_status;
2693 if (!IS_8251(com->pc98_if_type)) {
2695 mtx_lock_spin(&sio_lock);
2696 delta_modem_status = com->last_modem_status
2697 ^ com->prev_modem_status;
2698 com->prev_modem_status = com->last_modem_status;
2699 com_events -= LOTS_OF_EVENTS;
2700 com->state &= ~CS_CHECKMSR;
2701 mtx_unlock_spin(&sio_lock);
2702 if (delta_modem_status & MSR_DCD)
2704 com->prev_modem_status & MSR_DCD);
2709 if (com->state & CS_ODONE) {
2710 mtx_lock_spin(&sio_lock);
2711 com_events -= LOTS_OF_EVENTS;
2712 com->state &= ~CS_ODONE;
2713 mtx_unlock_spin(&sio_lock);
2714 if (!(com->state & CS_BUSY)
2715 && !(com->extra_state & CSE_BUSYCHECK)) {
2716 timeout(siobusycheck, com, hz / 100);
2717 com->extra_state |= CSE_BUSYCHECK;
2721 if (com_events == 0)
2724 if (com_events >= LOTS_OF_EVENTS)
2739 com_send_break_on(com);
2741 com_send_break_off(com);
2744 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK);
2746 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK);
2761 u_char efr_flowbits;
2774 if (IS_8251(com->pc98_if_type)) {
2775 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0)
2779 /* check requested parameters */
2780 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed))
2782 divisor = siodivisor(com->rclk, t->c_ispeed);
2789 /* parameters are OK, convert them to the com struct and the device */
2792 if (IS_8251(com->pc98_if_type)) {
2793 if (t->c_ospeed == 0)
2794 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2796 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE);
2799 if (t->c_ospeed == 0)
2800 (void)commodem(tp, 0, SER_DTR); /* hang up line */
2802 (void)commodem(tp, SER_DTR, 0);
2805 if (!IS_8251(com->pc98_if_type)) {
2807 switch (cflag & CSIZE) {
2821 if (cflag & PARENB) {
2823 if (!(cflag & PARODD))
2831 * Use a fifo trigger level low enough so that the input
2832 * latency from the fifo is less than about 16 msec and
2833 * the total latency is less than about 30 msec. These
2834 * latencies are reasonable for humans. Serial comms
2835 * protocols shouldn't expect anything better since modem
2836 * latencies are larger.
2838 * The fifo trigger level cannot be set at RX_HIGH for high
2839 * speed connections without further work on reducing
2840 * interrupt disablement times in other parts of the system,
2841 * without producing silo overflow errors.
2843 com->fifo_image = com->unit == siotsunit ? 0
2844 : t->c_ispeed <= 4800
2845 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH;
2848 * The Hayes ESP card needs the fifo DMA mode bit set
2849 * in compatibility mode. If not, it will interrupt
2850 * for each character received.
2853 com->fifo_image |= FIFO_DMA_MODE;
2855 sio_setreg(com, com_fifo, com->fifo_image);
2862 * This returns with interrupts disabled so that we can complete
2863 * the speed change atomically. Keeping interrupts disabled is
2864 * especially important while com_data is hidden.
2866 (void) siosetwater(com, t->c_ispeed);
2869 if (IS_8251(com->pc98_if_type))
2870 com_cflag_and_speed_set(com, cflag, t->c_ospeed);
2873 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB);
2875 * Only set the divisor registers if they would change, since on
2876 * some 16550 incompatibles (UMC8669F), setting them while input
2877 * is arriving loses sync until data stops arriving.
2879 dlbl = divisor & 0xFF;
2880 if (sio_getreg(com, com_dlbl) != dlbl)
2881 sio_setreg(com, com_dlbl, dlbl);
2882 dlbh = divisor >> 8;
2883 if (sio_getreg(com, com_dlbh) != dlbh)
2884 sio_setreg(com, com_dlbh, dlbh);
2891 if (cflag & CRTS_IFLOW) {
2892 com->state |= CS_RTS_IFLOW;
2893 efr_flowbits |= EFR_AUTORTS;
2895 * If CS_RTS_IFLOW just changed from off to on, the change
2896 * needs to be propagated to MCR_RTS. This isn't urgent,
2897 * so do it later by calling comstart() instead of repeating
2898 * a lot of code from comstart() here.
2900 } else if (com->state & CS_RTS_IFLOW) {
2901 com->state &= ~CS_RTS_IFLOW;
2903 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS
2904 * on here, since comstart() won't do it later.
2907 if (IS_8251(com->pc98_if_type))
2908 com_tiocm_bis(com, TIOCM_RTS);
2910 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2912 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
2917 * Set up state to handle output flow control.
2918 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level?
2919 * Now has 10+ msec latency, while CTS flow has 50- usec latency.
2921 com->state |= CS_ODEVREADY;
2922 com->state &= ~CS_CTS_OFLOW;
2924 if (com->pc98_if_type == COM_IF_RSA98III) {
2925 param = inb(com->rsabase + rsa_msr);
2926 outb(com->rsabase + rsa_msr, param & 0x14);
2929 if (cflag & CCTS_OFLOW) {
2930 com->state |= CS_CTS_OFLOW;
2931 efr_flowbits |= EFR_AUTOCTS;
2933 if (IS_8251(com->pc98_if_type)) {
2934 if (!(pc98_get_modem_status(com) & TIOCM_CTS))
2935 com->state &= ~CS_ODEVREADY;
2936 } else if (com->pc98_if_type == COM_IF_RSA98III) {
2937 /* Set automatic flow control mode */
2938 outb(com->rsabase + rsa_msr, param | 0x08);
2941 if (!(com->last_modem_status & MSR_CTS))
2942 com->state &= ~CS_ODEVREADY;
2946 if (!IS_8251(com->pc98_if_type))
2947 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2949 if (com->st16650a) {
2950 sio_setreg(com, com_lcr, LCR_EFR_ENABLE);
2951 sio_setreg(com, com_efr,
2952 (sio_getreg(com, com_efr)
2953 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits);
2955 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr);
2958 /* XXX shouldn't call functions while intrs are disabled. */
2961 mtx_unlock_spin(&sio_lock);
2964 if (com->ibufold != NULL) {
2965 free(com->ibufold, M_DEVBUF);
2966 com->ibufold = NULL;
2972 * This function must be called with the sio_lock mutex released and will
2973 * return with it obtained.
2976 siosetwater(com, speed)
2986 * Make the buffer size large enough to handle a softtty interrupt
2987 * latency of about 2 ticks without loss of throughput or data
2988 * (about 3 ticks if input flow control is not used or not honoured,
2989 * but a bit less for CS5-CS7 modes).
2991 cp4ticks = speed / 10 / hz * 4;
2992 for (ibufsize = 128; ibufsize < cp4ticks;)
2995 if (com->pc98_if_type == COM_IF_RSA98III)
2998 if (ibufsize == com->ibufsize) {
2999 mtx_lock_spin(&sio_lock);
3004 * Allocate input buffer. The extra factor of 2 in the size is
3005 * to allow for an error byte for each input byte.
3007 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT);
3009 mtx_lock_spin(&sio_lock);
3013 /* Initialize non-critical variables. */
3014 com->ibufold = com->ibuf;
3015 com->ibufsize = ibufsize;
3018 tp->t_ififosize = 2 * ibufsize;
3019 tp->t_ispeedwat = (speed_t)-1;
3020 tp->t_ospeedwat = (speed_t)-1;
3024 * Read current input buffer, if any. Continue with interrupts
3027 mtx_lock_spin(&sio_lock);
3028 if (com->iptr != com->ibuf)
3032 * Initialize critical variables, including input buffer watermarks.
3033 * The external device is asked to stop sending when the buffer
3034 * exactly reaches high water, or when the high level requests it.
3035 * The high level is notified immediately (rather than at a later
3036 * clock tick) when this watermark is reached.
3037 * The buffer size is chosen so the watermark should almost never
3039 * The low watermark is invisibly 0 since the buffer is always
3040 * emptied all at once.
3042 com->iptr = com->ibuf = ibuf;
3043 com->ibufend = ibuf + ibufsize;
3044 com->ierroff = ibufsize;
3045 com->ihighwater = ibuf + 3 * ibufsize / 4;
3060 mtx_lock_spin(&sio_lock);
3061 if (tp->t_state & TS_TTSTOP)
3062 com->state &= ~CS_TTGO;
3064 com->state |= CS_TTGO;
3065 if (tp->t_state & TS_TBLOCK) {
3067 if (IS_8251(com->pc98_if_type)) {
3068 if ((com_tiocm_get(com) & TIOCM_RTS) &&
3069 (com->state & CS_RTS_IFLOW))
3070 com_tiocm_bic(com, TIOCM_RTS);
3072 if ((com->mcr_image & MCR_RTS) &&
3073 (com->state & CS_RTS_IFLOW))
3074 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3077 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW)
3078 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS);
3082 if (IS_8251(com->pc98_if_type)) {
3083 if (!(com_tiocm_get(com) & TIOCM_RTS) &&
3084 com->iptr < com->ihighwater &&
3085 com->state & CS_RTS_IFLOW)
3086 com_tiocm_bis(com, TIOCM_RTS);
3088 if (!(com->mcr_image & MCR_RTS) &&
3089 com->iptr < com->ihighwater &&
3090 com->state & CS_RTS_IFLOW)
3091 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3094 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater
3095 && com->state & CS_RTS_IFLOW)
3096 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS);
3099 mtx_unlock_spin(&sio_lock);
3100 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) {
3105 if (tp->t_outq.c_cc != 0) {
3109 if (!com->obufs[0].l_queued) {
3110 com->obufs[0].l_tail
3111 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1,
3117 com->obufs[0].l_next = NULL;
3118 com->obufs[0].l_queued = TRUE;
3119 mtx_lock_spin(&sio_lock);
3120 if (com->state & CS_BUSY) {
3121 qp = com->obufq.l_next;
3122 while ((next = qp->l_next) != NULL)
3124 qp->l_next = &com->obufs[0];
3126 com->obufq.l_head = com->obufs[0].l_head;
3127 com->obufq.l_tail = com->obufs[0].l_tail;
3128 com->obufq.l_next = &com->obufs[0];
3129 com->state |= CS_BUSY;
3131 mtx_unlock_spin(&sio_lock);
3133 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) {
3134 com->obufs[1].l_tail
3135 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2,
3141 com->obufs[1].l_next = NULL;
3142 com->obufs[1].l_queued = TRUE;
3143 mtx_lock_spin(&sio_lock);
3144 if (com->state & CS_BUSY) {
3145 qp = com->obufq.l_next;
3146 while ((next = qp->l_next) != NULL)
3148 qp->l_next = &com->obufs[1];
3150 com->obufq.l_head = com->obufs[1].l_head;
3151 com->obufq.l_tail = com->obufs[1].l_tail;
3152 com->obufq.l_next = &com->obufs[1];
3153 com->state |= CS_BUSY;
3155 mtx_unlock_spin(&sio_lock);
3157 tp->t_state |= TS_BUSY;
3159 mtx_lock_spin(&sio_lock);
3160 if (com->state >= (CS_BUSY | CS_TTGO))
3161 siointr1(com); /* fake interrupt to start output */
3162 mtx_unlock_spin(&sio_lock);
3178 if (com == NULL || com->gone)
3180 mtx_lock_spin(&sio_lock);
3183 if (!IS_8251(com->pc98_if_type)) {
3187 /* XXX avoid h/w bug. */
3190 sio_setreg(com, com_fifo,
3191 FIFO_XMT_RST | com->fifo_image);
3193 if (com->pc98_if_type == COM_IF_RSA98III)
3194 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3195 sio_setreg(com, com_fifo,
3196 FIFO_XMT_RST | com->fifo_image);
3199 com->obufs[0].l_queued = FALSE;
3200 com->obufs[1].l_queued = FALSE;
3201 if (com->state & CS_ODONE)
3202 com_events -= LOTS_OF_EVENTS;
3203 com->state &= ~(CS_ODONE | CS_BUSY);
3204 com->tp->t_state &= ~TS_BUSY;
3208 if (!IS_8251(com->pc98_if_type)) {
3209 if (com->pc98_if_type == COM_IF_RSA98III)
3210 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++)
3211 sio_getreg(com, com_data);
3215 /* XXX avoid h/w bug. */
3218 sio_setreg(com, com_fifo,
3219 FIFO_RCV_RST | com->fifo_image);
3223 com_events -= (com->iptr - com->ibuf);
3224 com->iptr = com->ibuf;
3226 mtx_unlock_spin(&sio_lock);
3231 commodem(struct tty *tp, int sigon, int sigoff)
3234 int bitand, bitor, msr;
3242 if (sigon != 0 || sigoff != 0) {
3244 if (IS_8251(com->pc98_if_type)) {
3247 if (sigoff & SER_DTR) {
3248 bitand |= TIOCM_DTR;
3251 if (sigoff & SER_RTS) {
3252 bitand |= TIOCM_RTS;
3253 clr |= CMD8251_RxEN | CMD8251_RTS;
3255 if (sigon & SER_DTR) {
3257 set |= CMD8251_TxEN | CMD8251_RxEN |
3260 if (sigon & SER_RTS) {
3262 set |= CMD8251_TxEN | CMD8251_RxEN |
3266 mtx_lock_spin(&sio_lock);
3267 com->pc98_prev_modem_status &= bitand;
3268 com->pc98_prev_modem_status |= bitor;
3269 pc98_i8251_clear_or_cmd(com, clr, set);
3270 mtx_unlock_spin(&sio_lock);
3275 if (sigoff & SER_DTR)
3277 if (sigoff & SER_RTS)
3279 if (sigon & SER_DTR)
3281 if (sigon & SER_RTS)
3284 mtx_lock_spin(&sio_lock);
3285 com->mcr_image &= bitand;
3286 com->mcr_image |= bitor;
3287 outb(com->modem_ctl_port, com->mcr_image);
3288 mtx_unlock_spin(&sio_lock);
3295 if (IS_8251(com->pc98_if_type))
3296 return (com_tiocm_get(com));
3300 if (com->mcr_image & MCR_DTR)
3302 if (com->mcr_image & MCR_RTS)
3304 msr = com->prev_modem_status;
3313 if (msr & (MSR_RI | MSR_TERI))
3330 * Set our timeout period to 1 second if no polled devices are open.
3331 * Otherwise set it to max(1/200, 1/hz).
3332 * Enable timeouts iff some device is open.
3334 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3337 for (unit = 0; unit < sio_numunits; ++unit) {
3338 com = com_addr(unit);
3339 if (com != NULL && com->tp != NULL
3340 && com->tp->t_state & TS_ISOPEN && !com->gone) {
3342 if (com->poll || com->poll_output) {
3343 sio_timeout = hz > 200 ? hz / 200 : 1;
3349 sio_timeouts_until_log = hz / sio_timeout;
3350 sio_timeout_handle = timeout(comwakeup, (void *)NULL,
3353 /* Flush error messages, if any. */
3354 sio_timeouts_until_log = 1;
3355 comwakeup((void *)NULL);
3356 untimeout(comwakeup, (void *)NULL, sio_timeout_handle);
3367 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout);
3370 * Recover from lost output interrupts.
3371 * Poll any lines that don't use interrupts.
3373 for (unit = 0; unit < sio_numunits; ++unit) {
3374 com = com_addr(unit);
3375 if (com != NULL && !com->gone
3376 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) {
3377 mtx_lock_spin(&sio_lock);
3379 mtx_unlock_spin(&sio_lock);
3384 * Check for and log errors, but not too often.
3386 if (--sio_timeouts_until_log > 0)
3388 sio_timeouts_until_log = hz / sio_timeout;
3389 for (unit = 0; unit < sio_numunits; ++unit) {
3392 com = com_addr(unit);
3397 for (errnum = 0; errnum < CE_NTYPES; ++errnum) {
3401 mtx_lock_spin(&sio_lock);
3402 delta = com->delta_error_counts[errnum];
3403 com->delta_error_counts[errnum] = 0;
3404 mtx_unlock_spin(&sio_lock);
3407 total = com->error_counts[errnum] += delta;
3408 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n",
3409 unit, delta, error_desc[errnum],
3410 delta == 1 ? "" : "s", total);
3416 /* commint is called when modem control line changes */
3418 commint(struct cdev *dev)
3420 register struct tty *tp;
3427 stat = com_tiocm_get(com);
3428 delta = com_tiocm_get_delta(com);
3430 if (com->state & CS_CTS_OFLOW) {
3431 if (stat & TIOCM_CTS)
3432 com->state |= CS_ODEVREADY;
3434 com->state &= ~CS_ODEVREADY;
3436 if ((delta & TIOCM_CAR) && (ISCALLOUT(dev)) == 0) {
3437 if (stat & TIOCM_CAR )
3438 (void)ttyld_modem(tp, 1);
3439 else if (ttyld_modem(tp, 0) == 0) {
3440 /* negate DTR, RTS */
3441 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ?
3442 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE );
3443 /* disable IENABLE */
3444 com_int_TxRx_disable( com );
3451 * Following are all routines needed for SIO to act as console
3462 * This is a function in order to not replicate "ttyd%d" more
3463 * places than absolutely necessary.
3466 siocnset(struct consdev *cd, int unit)
3470 sprintf(cd->cn_name, "ttyd%d", unit);
3473 static speed_t siocngetspeed(Port_t, u_long rclk);
3474 static void siocnclose(struct siocnstate *sp, Port_t iobase);
3475 static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed);
3476 static void siocntxwait(Port_t iobase);
3478 static cn_probe_t sio_cnprobe;
3479 static cn_init_t sio_cninit;
3480 static cn_term_t sio_cnterm;
3481 static cn_getc_t sio_cngetc;
3482 static cn_putc_t sio_cnputc;
3484 CONSOLE_DRIVER(sio);
3493 * Wait for any pending transmission to finish. Required to avoid
3494 * the UART lockup bug when the speed is changed, and for normal
3498 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY))
3499 != (LSR_TSRE | LSR_TXRDY) && --timo != 0)
3504 * Read the serial port specified and try to figure out what speed
3505 * it's currently running at. We're assuming the serial port has
3506 * been initialized and is basicly idle. This routine is only intended
3507 * to be run at system startup.
3509 * If the value read from the serial port doesn't make sense, return 0.
3513 siocngetspeed(iobase, rclk)
3522 cfcr = inb(iobase + com_cfcr);
3523 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3525 dlbl = inb(iobase + com_dlbl);
3526 dlbh = inb(iobase + com_dlbh);
3528 outb(iobase + com_cfcr, cfcr);
3530 divisor = dlbh << 8 | dlbl;
3532 /* XXX there should be more sanity checking. */
3535 return (rclk / (16UL * divisor));
3539 siocnopen(sp, iobase, speed)
3540 struct siocnstate *sp;
3549 * Save all the device control registers except the fifo register
3550 * and set our default ones (cs8 -parenb speed=comdefaultrate).
3551 * We can't save the fifo register since it is read-only.
3553 sp->ier = inb(iobase + com_ier);
3554 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */
3555 siocntxwait(iobase);
3556 sp->cfcr = inb(iobase + com_cfcr);
3557 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3558 sp->dlbl = inb(iobase + com_dlbl);
3559 sp->dlbh = inb(iobase + com_dlbh);
3561 * Only set the divisor registers if they would change, since on
3562 * some 16550 incompatibles (Startech), setting them clears the
3563 * data input register. This also reduces the effects of the
3566 divisor = siodivisor(comdefaultrclk, speed);
3567 dlbl = divisor & 0xFF;
3568 if (sp->dlbl != dlbl)
3569 outb(iobase + com_dlbl, dlbl);
3570 dlbh = divisor >> 8;
3571 if (sp->dlbh != dlbh)
3572 outb(iobase + com_dlbh, dlbh);
3573 outb(iobase + com_cfcr, CFCR_8BITS);
3574 sp->mcr = inb(iobase + com_mcr);
3576 * We don't want interrupts, but must be careful not to "disable"
3577 * them by clearing the MCR_IENABLE bit, since that might cause
3578 * an interrupt by floating the IRQ line.
3580 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS);
3584 siocnclose(sp, iobase)
3585 struct siocnstate *sp;
3589 * Restore the device control registers.
3591 siocntxwait(iobase);
3592 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS);
3593 if (sp->dlbl != inb(iobase + com_dlbl))
3594 outb(iobase + com_dlbl, sp->dlbl);
3595 if (sp->dlbh != inb(iobase + com_dlbh))
3596 outb(iobase + com_dlbh, sp->dlbh);
3597 outb(iobase + com_cfcr, sp->cfcr);
3599 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them.
3601 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS);
3602 outb(iobase + com_ier, sp->ier);
3613 struct siocnstate sp;
3616 * Find our first enabled console, if any. If it is a high-level
3617 * console device, then initialize it and return successfully.
3618 * If it is a low-level console device, then initialize it and
3619 * return unsuccessfully. It must be initialized in both cases
3620 * for early use by console drivers and debuggers. Initializing
3621 * the hardware is not necessary in all cases, since the i/o
3622 * routines initialize it on the fly, but it is necessary if
3623 * input might arrive while the hardware is switched back to an
3624 * uninitialized state. We can't handle multiple console devices
3625 * yet because our low-level routines don't take a device arg.
3626 * We trust the user to set the console flags properly so that we
3627 * don't need to probe.
3629 cp->cn_pri = CN_DEAD;
3631 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */
3634 if (resource_disabled("sio", unit))
3636 if (resource_int_value("sio", unit, "flags", &flags))
3638 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) {
3642 if (resource_int_value("sio", unit, "port", &port))
3646 if ((boothowto & RB_SERIAL) && COM_CONSOLE(flags)) {
3648 siocngetspeed(iobase, comdefaultrclk);
3650 comdefaultrate = boot_speed;
3654 * Initialize the divisor latch. We can't rely on
3655 * siocnopen() to do this the first time, since it
3656 * avoids writing to the latch if the latch appears
3657 * to have the correct value. Also, if we didn't
3658 * just read the speed from the hardware, then we
3659 * need to set the speed in hardware so that
3660 * switching it later is null.
3662 cfcr = inb(iobase + com_cfcr);
3663 outb(iobase + com_cfcr, CFCR_DLAB | cfcr);
3664 divisor = siodivisor(comdefaultrclk, comdefaultrate);
3665 outb(iobase + com_dlbl, divisor & 0xff);
3666 outb(iobase + com_dlbh, divisor >> 8);
3667 outb(iobase + com_cfcr, cfcr);
3669 siocnopen(&sp, iobase, comdefaultrate);
3672 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) {
3674 cp->cn_pri = COM_FORCECONSOLE(flags)
3675 || boothowto & RB_SERIAL
3676 ? CN_REMOTE : CN_NORMAL;
3677 siocniobase = iobase;
3681 if (COM_DEBUGGER(flags))
3682 siogdbiobase = iobase;
3692 comconsole = cp->cn_unit;
3703 sio_cngetc(struct consdev *cd)
3708 struct siocnstate sp;
3711 if (cd != NULL && cd->cn_unit == siocnunit) {
3712 iobase = siocniobase;
3713 speed = comdefaultrate;
3716 iobase = siogdbiobase;
3717 speed = gdbdefaultrate;
3723 siocnopen(&sp, iobase, speed);
3724 if (inb(iobase + com_lsr) & LSR_RXRDY)
3725 c = inb(iobase + com_data);
3728 siocnclose(&sp, iobase);
3734 sio_cnputc(struct consdev *cd, int c)
3738 struct siocnstate sp;
3742 if (cd != NULL && cd->cn_unit == siocnunit) {
3743 iobase = siocniobase;
3744 speed = comdefaultrate;
3747 iobase = siogdbiobase;
3748 speed = gdbdefaultrate;
3755 if (!kdb_active && sio_inited == 2 && !mtx_owned(&sio_lock)) {
3756 mtx_lock_spin(&sio_lock);
3759 siocnopen(&sp, iobase, speed);
3760 siocntxwait(iobase);
3761 outb(iobase + com_data, c);
3762 siocnclose(&sp, iobase);
3764 mtx_unlock_spin(&sio_lock);
3769 * Remote gdb(1) support.
3774 #include <gdb/gdb.h>
3776 static gdb_probe_f siogdbprobe;
3777 static gdb_init_f siogdbinit;
3778 static gdb_term_f siogdbterm;
3779 static gdb_getc_f siogdbgetc;
3780 static gdb_putc_f siogdbputc;
3782 GDB_DBGPORT(sio, siogdbprobe, siogdbinit, siogdbterm, siogdbgetc, siogdbputc);
3787 return ((siogdbiobase != 0) ? 0 : -1);
3803 sio_cnputc(NULL, c);
3809 return (sio_cngetc(NULL));
3816 * pc98 local function
3819 com_tiocm_bis(struct com_s *com, int msr)
3825 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
3826 tmp |= CMD8251_TxEN|CMD8251_RxEN;
3827 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
3828 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
3830 pc98_i8251_or_cmd( com, tmp );
3835 com_tiocm_bic(struct com_s *com, int msr)
3841 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) );
3842 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR;
3843 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS;
3845 pc98_i8251_clear_cmd( com, tmp );
3850 com_tiocm_get(struct com_s *com)
3852 return( com->pc98_prev_modem_status );
3856 com_tiocm_get_delta(struct com_s *com)
3860 tmp = com->pc98_modem_delta;
3861 com->pc98_modem_delta = 0;
3865 /* convert to TIOCM_?? ( ioctl.h ) */
3867 pc98_get_modem_status(struct com_s *com)
3871 msr = com->pc98_prev_modem_status
3872 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
3873 if (com->pc98_8251fifo_enable) {
3876 stat2 = inb(I8251F_msr);
3877 if ( stat2 & MSR_DCD ) msr |= TIOCM_CAR;
3878 if ( stat2 & MSR_RI ) msr |= TIOCM_RI;
3879 if ( stat2 & MSR_DSR ) msr |= TIOCM_DSR;
3880 if ( stat2 & MSR_CTS ) msr |= TIOCM_CTS;
3881 #if COM_CARRIER_DETECT_EMULATE
3882 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
3889 stat = inb(com->sts_port);
3890 stat2 = inb(com->in_modem_port);
3891 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR;
3892 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI;
3893 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR;
3894 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS;
3895 #if COM_CARRIER_DETECT_EMULATE
3896 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) {
3905 pc98_check_msr(void* chan)
3909 register struct tty *tp;
3913 dev=(struct cdev *)chan;
3918 msr = pc98_get_modem_status(com);
3919 /* make change flag */
3920 delta = msr ^ com->pc98_prev_modem_status;
3921 if ( delta & TIOCM_CAR ) {
3922 if ( com->modem_car_chg_timer ) {
3923 if ( -- com->modem_car_chg_timer )
3926 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ?
3927 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0)
3931 com->modem_car_chg_timer = 0;
3932 delta = ( msr ^ com->pc98_prev_modem_status ) &
3933 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS);
3934 com->pc98_prev_modem_status = msr;
3935 delta = ( com->pc98_modem_delta |= delta );
3937 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) {
3941 timeout(pc98_check_msr, (caddr_t)dev,
3942 PC98_CHECK_MODEM_INTERVAL);
3944 com->modem_checking = 0;
3949 pc98_msrint_start(struct cdev *dev)
3955 /* modem control line check routine envoke interval is 1/10 sec */
3956 if ( com->modem_checking == 0 ) {
3957 com->pc98_prev_modem_status = pc98_get_modem_status(com);
3958 com->pc98_modem_delta = 0;
3959 timeout(pc98_check_msr, (caddr_t)dev,
3960 PC98_CHECK_MODEM_INTERVAL);
3961 com->modem_checking = 1;
3967 pc98_disable_i8251_interrupt(struct com_s *com, int mod)
3969 /* disable interrupt */
3972 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
3974 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
3975 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp );
3980 pc98_enable_i8251_interrupt(struct com_s *com, int mod)
3985 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx);
3986 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp );
3991 pc98_check_i8251_interrupt(struct com_s *com)
3993 return ( com->intr_enable & 0x07 );
3997 pc98_i8251_clear_cmd(struct com_s *com, int x)
4002 tmp = com->pc98_prev_siocmd & ~(x);
4003 if (com->pc98_8251fifo_enable)
4004 outb(I8251F_fcr, 0);
4005 outb(com->cmd_port, tmp);
4006 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4007 if (com->pc98_8251fifo_enable)
4008 outb(I8251F_fcr, FIFO_ENABLE);
4013 pc98_i8251_or_cmd(struct com_s *com, int x)
4018 if (com->pc98_8251fifo_enable)
4019 outb(I8251F_fcr, 0);
4020 tmp = com->pc98_prev_siocmd | (x);
4021 outb(com->cmd_port, tmp);
4022 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4023 if (com->pc98_8251fifo_enable)
4024 outb(I8251F_fcr, FIFO_ENABLE);
4029 pc98_i8251_set_cmd(struct com_s *com, int x)
4034 if (com->pc98_8251fifo_enable)
4035 outb(I8251F_fcr, 0);
4037 outb(com->cmd_port, tmp);
4038 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4039 if (com->pc98_8251fifo_enable)
4040 outb(I8251F_fcr, FIFO_ENABLE);
4045 pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x)
4049 if (com->pc98_8251fifo_enable)
4050 outb(I8251F_fcr, 0);
4051 tmp = com->pc98_prev_siocmd & ~(clr);
4053 outb(com->cmd_port, tmp);
4054 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH);
4055 if (com->pc98_8251fifo_enable)
4056 outb(I8251F_fcr, FIFO_ENABLE);
4061 pc98_i8251_get_cmd(struct com_s *com)
4063 return com->pc98_prev_siocmd;
4067 pc98_i8251_get_mod(struct com_s *com)
4069 return com->pc98_prev_siomod;
4073 pc98_i8251_reset(struct com_s *com, int mode, int command)
4075 if (com->pc98_8251fifo_enable)
4076 outb(I8251F_fcr, 0);
4077 outb(com->cmd_port, 0); /* dummy */
4079 outb(com->cmd_port, 0); /* dummy */
4081 outb(com->cmd_port, 0); /* dummy */
4083 outb(com->cmd_port, CMD8251_RESET); /* internal reset */
4085 outb(com->cmd_port, mode ); /* mode register */
4086 com->pc98_prev_siomod = mode;
4088 pc98_i8251_set_cmd( com, (command|CMD8251_ER) );
4090 if (com->pc98_8251fifo_enable)
4091 outb(I8251F_fcr, FIFO_ENABLE | FIFO_XMT_RST | FIFO_RCV_RST);
4095 pc98_check_sysclock(void)
4097 /* get system clock from port */
4098 if ( pc98_machine_type & M_8M ) {
4099 /* 8 MHz system & H98 */
4108 com_cflag_and_speed_set( struct com_s *com, int cflag, int speed)
4115 if (pc98_ttspeedtab(com, speed, &count) != 0)
4118 previnterrupt = pc98_check_i8251_interrupt(com);
4119 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx );
4121 switch ( cflag&CSIZE ) {
4123 cfcr = MOD8251_5BITS; break;
4125 cfcr = MOD8251_6BITS; break;
4127 cfcr = MOD8251_7BITS; break;
4129 cfcr = MOD8251_8BITS; break;
4131 if ( cflag&PARENB ) {
4133 cfcr |= MOD8251_PENAB;
4135 cfcr |= MOD8251_PENAB | MOD8251_PEVEN;
4139 cfcr |= MOD8251_STOP2;
4141 cfcr |= MOD8251_STOP1;
4143 if ( count & 0x10000 )
4144 cfcr |= MOD8251_CLKx1;
4146 cfcr |= MOD8251_CLKx16;
4148 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP))
4151 /* set baud rate from ospeed */
4152 pc98_set_baud_rate( com, count );
4154 if ( cfcr != pc98_i8251_get_mod(com) )
4155 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) );
4157 pc98_enable_i8251_interrupt( com, previnterrupt );
4161 pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor)
4163 int if_type, effect_sp, count = -1, mod;
4165 if_type = com->pc98_if_type & 0x0f;
4167 switch (com->pc98_if_type) {
4168 case COM_IF_INTERNAL:
4169 if (PC98SIO_baud_rate_port(if_type) != -1) {
4170 count = ttspeedtab(speed, if_8251_type[if_type].speedtab);
4172 count |= COM1_EXT_CLOCK;
4177 /* for *1CLK asynchronous! mode, TEFUTEFU */
4178 mod = (sysclock == 5) ? 2457600 : 1996800;
4179 effect_sp = ttspeedtab( speed, pc98speedtab );
4180 if ( effect_sp < 0 ) /* XXX */
4181 effect_sp = ttspeedtab( (speed - 1), pc98speedtab );
4182 if ( effect_sp <= 0 )
4184 if ( effect_sp == speed )
4186 if ( mod % effect_sp )
4188 count = mod / effect_sp;
4189 if ( count > 65535 )
4191 if ( effect_sp != speed )
4194 case COM_IF_PC9861K_1:
4195 case COM_IF_PC9861K_2:
4198 case COM_IF_IND_SS_1:
4199 case COM_IF_IND_SS_2:
4200 case COM_IF_PIO9032B_1:
4201 case COM_IF_PIO9032B_2:
4202 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4204 case COM_IF_B98_01_1:
4205 case COM_IF_B98_01_2:
4206 count = ttspeedtab( speed, if_8251_type[if_type].speedtab );
4208 if (count == 0 || count == 1) {
4210 count |= 0x20000; /* x1 mode for 76800 and 153600 */
4219 *divisor = (u_int) count;
4224 pc98_set_baud_rate( struct com_s *com, u_int count )
4228 if_type = com->pc98_if_type & 0x0f;
4229 io = rman_get_start(com->ioportres) & 0xff00;
4231 switch (com->pc98_if_type) {
4232 case COM_IF_INTERNAL:
4233 if (PC98SIO_baud_rate_port(if_type) != -1) {
4234 if (count & COM1_EXT_CLOCK) {
4235 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff);
4238 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09);
4252 outb( 0x75, count & 0xff );
4254 outb( 0x75, (count >> 8) & 0xff );
4257 case COM_IF_IND_SS_1:
4258 case COM_IF_IND_SS_2:
4259 outb(io | PC98SIO_intr_ctrl_port(if_type), 0);
4260 outb(io | PC98SIO_baud_rate_port(if_type), 0);
4261 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0);
4262 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80);
4263 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff);
4265 case COM_IF_PIO9032B_1:
4266 case COM_IF_PIO9032B_2:
4267 outb(io | PC98SIO_baud_rate_port(if_type), count);
4269 case COM_IF_B98_01_1:
4270 case COM_IF_B98_01_2:
4271 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f);
4274 * Some old B98_01 board should be controlled
4275 * in different way, but this hasn't been tested yet.
4277 outb(io | PC98SIO_func_port(if_type),
4278 (count & 0x20000) ? 0xf0 : 0xf2);
4284 pc98_check_if_type(device_t dev, struct siodev *iod)
4286 int irr, io, if_type, tmp;
4287 static short irq_tab[2][8] = {
4288 { 3, 5, 6, 9, 10, 12, 13, -1},
4289 { 3, 10, 12, 13, 5, 6, 9, -1}
4292 if_type = iod->if_type & 0x0f;
4294 io = isa_get_port(dev) & 0xff00;
4296 if (IS_8251(iod->if_type)) {
4297 if (PC98SIO_func_port(if_type) != -1) {
4298 outb(io | PC98SIO_func_port(if_type), 0xf2);
4299 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab);
4300 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1)
4301 outb(io | PC98SIO_baud_rate_port(if_type), tmp);
4304 iod->cmd = io | PC98SIO_cmd_port(if_type);
4305 iod->sts = io | PC98SIO_sts_port(if_type);
4306 iod->mod = io | PC98SIO_in_modem_port(if_type);
4307 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type);
4309 if (iod->if_type == COM_IF_INTERNAL) {
4312 if (pc98_check_8251vfast()) {
4313 PC98SIO_baud_rate_port(if_type) = I8251F_div;
4314 if_8251_type[if_type].speedtab = pc98fast_speedtab;
4317 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask;
4318 if ((isa_get_port(dev) & 0xff) == IO_COM2)
4319 iod->irq = irq_tab[0][tmp];
4321 iod->irq = irq_tab[1][tmp];
4324 irr = if_16550a_type[if_type].irr_read;
4325 #ifdef COM_MULTIPORT
4326 if (!COM_ISMULTIPORT(device_get_flags(dev)) ||
4327 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev)))
4330 tmp = inb(io | irr);
4331 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */
4332 iod->irq = irq_tab[1][tmp >> 3];
4334 iod->irq = irq_tab[0][tmp & 0x07];
4341 if ( iod->irq == -1 ) return -1;
4346 pc98_set_ioport(struct com_s *com)
4348 int if_type = com->pc98_if_type & 0x0f;
4349 Port_t io = rman_get_start(com->ioportres) & 0xff00;
4351 pc98_check_sysclock();
4352 com->data_port = io | PC98SIO_data_port(if_type);
4353 com->cmd_port = io | PC98SIO_cmd_port(if_type);
4354 com->sts_port = io | PC98SIO_sts_port(if_type);
4355 com->in_modem_port = io | PC98SIO_in_modem_port(if_type);
4356 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type);
4359 pc98_check_8251vfast(void)
4363 outb(I8251F_div, 0x8c);
4365 for (i = 0; i < 100; i++) {
4366 if ((inb(I8251F_div) & 0x80) != 0) {
4372 outb(I8251F_div, 0);
4374 for (; i < 100; i++) {
4375 if ((inb(I8251F_div) & 0x80) == 0)
4383 pc98_check_8251fifo(void)
4387 tmp1 = inb(I8251F_iir);
4389 tmp2 = inb(I8251F_iir);
4390 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0)
4395 #endif /* PC98 defined */