2 * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
38 #include <machine/bootinfo.h>
39 #include <machine/bus.h>
40 #include <machine/cpu.h>
41 #include <machine/hid.h>
42 #include <machine/platform.h>
43 #include <machine/platformvar.h>
44 #include <machine/smp.h>
45 #include <machine/spr.h>
46 #include <machine/vmparam.h>
48 #include <powerpc/mpc85xx/mpc85xx.h>
49 #include <powerpc/mpc85xx/ocpbus.h>
51 #include "platform_if.h"
55 extern uint8_t __boot_page[]; /* Boot page body */
56 extern uint32_t kernload; /* Kernel physical load address */
59 static int cpu, maxcpu;
61 static int bare_probe(platform_t);
62 static void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz,
63 struct mem_region **avail, int *availsz);
64 static u_long bare_timebase_freq(platform_t, struct cpuref *cpuref);
65 static int bare_smp_first_cpu(platform_t, struct cpuref *cpuref);
66 static int bare_smp_next_cpu(platform_t, struct cpuref *cpuref);
67 static int bare_smp_get_bsp(platform_t, struct cpuref *cpuref);
68 static int bare_smp_start_cpu(platform_t, struct pcpu *cpu);
70 static void e500_reset(platform_t);
72 static platform_method_t bare_methods[] = {
73 PLATFORMMETHOD(platform_probe, bare_probe),
74 PLATFORMMETHOD(platform_mem_regions, bare_mem_regions),
75 PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq),
77 PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu),
78 PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu),
79 PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp),
80 PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu),
82 PLATFORMMETHOD(platform_reset, e500_reset);
87 static platform_def_t bare_platform = {
93 PLATFORM_DEF(bare_platform);
96 bare_probe(platform_t plat)
100 ver = SVR_VER(mfspr(SPR_SVR));
101 if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
106 return (BUS_PROBE_GENERIC);
109 #define MEM_REGIONS 8
110 static struct mem_region avail_regions[MEM_REGIONS];
113 bare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz,
114 struct mem_region **avail, int *availsz)
116 struct bi_mem_region *mr;
119 /* Initialize memory regions table */
121 for (i = 0; i < bootinfo->bi_mem_reg_no; i++, mr++) {
122 if (i == MEM_REGIONS)
124 if (mr->mem_base < 1048576) {
125 avail_regions[i].mr_start = 1048576;
126 avail_regions[i].mr_size = mr->mem_size -
127 (1048576 - mr->mem_base);
129 avail_regions[i].mr_start = mr->mem_base;
130 avail_regions[i].mr_size = mr->mem_size;
134 *avail = avail_regions;
136 /* On the bare metal platform phys == avail memory */
142 bare_timebase_freq(platform_t plat, struct cpuref *cpuref)
147 * Time Base and Decrementer are updated every 8 CCB bus clocks.
148 * HID0[SEL_TBCLK] = 0
150 ticks = bootinfo->bi_bus_clk / 8;
152 panic("Unable to determine timebase frequency!");
158 bare_smp_first_cpu(platform_t plat, struct cpuref *cpuref)
162 cpuref->cr_cpuid = cpu;
163 cpuref->cr_hwref = cpuref->cr_cpuid;
165 printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid);
172 bare_smp_next_cpu(platform_t plat, struct cpuref *cpuref)
178 cpuref->cr_cpuid = cpu++;
179 cpuref->cr_hwref = cpuref->cr_cpuid;
181 printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid);
187 bare_smp_get_bsp(platform_t plat, struct cpuref *cpuref)
190 cpuref->cr_cpuid = mfspr(SPR_PIR);
191 cpuref->cr_hwref = cpuref->cr_cpuid;
197 bare_smp_start_cpu(platform_t plat, struct pcpu *pc)
200 uint32_t bptr, eebpcr;
203 eebpcr = ccsr_read4(OCP85XX_EEBPCR);
204 if ((eebpcr & (pc->pc_cpumask << 24)) != 0) {
205 printf("%s: CPU=%d already out of hold-off state!\n",
206 __func__, pc->pc_cpuid);
211 __asm __volatile("msync; isync");
214 * Set BPTR to the physical address of the boot page
216 bptr = ((uint32_t)__boot_page - KERNBASE) + kernload;
217 ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000);
220 * Release AP from hold-off state
222 eebpcr |= (pc->pc_cpumask << 24);
223 ccsr_write4(OCP85XX_EEBPCR, eebpcr);
224 __asm __volatile("isync; msync");
227 while (!pc->pc_awake && timeout--)
228 DELAY(1000); /* wait 1ms */
230 return ((pc->pc_awake) ? 0 : EBUSY);
238 e500_reset(platform_t plat)
240 uint32_t ver = SVR_VER(mfspr(SPR_SVR));
242 if (ver == SVR_MPC8572E || ver == SVR_MPC8572 ||
243 ver == SVR_MPC8548E || ver == SVR_MPC8548)
244 /* Systems with dedicated reset register */
245 ccsr_write4(OCP85XX_RSTCR, 2);
247 /* Clear DBCR0, disables debug interrupts and events. */
249 __asm __volatile("isync");
251 /* Enable Debug Interrupts in MSR. */
252 mtmsr(mfmsr() | PSL_DE);
254 /* Enable debug interrupts and issue reset. */
255 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM |
259 printf("Reset failed...\n");