2 * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Berkeley Software Design Inc's name may not be used to endorse or
13 * promote products derived from this software without specific prior
16 * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * from BSDI: locore.s,v 1.36.2.15 1999/08/23 22:34:41 cp Exp
31 * Copyright (c) 2002 Jake Burkholder.
32 * Copyright (c) 2007 - 2010 Marius Strobl <marius@FreeBSD.org>
33 * All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD$");
60 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <sys/kernel.h>
66 #include <sys/mutex.h>
69 #include <sys/sched.h>
73 #include <vm/vm_param.h>
75 #include <vm/vm_kern.h>
76 #include <vm/vm_extern.h>
77 #include <vm/vm_map.h>
79 #include <dev/ofw/openfirm.h>
81 #include <machine/asi.h>
82 #include <machine/atomic.h>
83 #include <machine/bus.h>
84 #include <machine/cpu.h>
85 #include <machine/md_var.h>
86 #include <machine/metadata.h>
87 #include <machine/ofw_machdep.h>
88 #include <machine/pcb.h>
89 #include <machine/smp.h>
90 #include <machine/tick.h>
91 #include <machine/tlb.h>
92 #include <machine/tte.h>
93 #include <machine/ver.h>
95 #define SUNW_STARTCPU "SUNW,start-cpu"
96 #define SUNW_STOPSELF "SUNW,stop-self"
98 static ih_func_t cpu_ipi_ast;
99 static ih_func_t cpu_ipi_preempt;
100 static ih_func_t cpu_ipi_stop;
103 * Argument area used to pass data to non-boot processors as they start up.
104 * This must be statically initialized with a known invalid CPU module ID,
105 * since the other processors will use it before the boot CPU enters the
108 struct cpu_start_args cpu_start_args = { 0, -1, -1, 0, 0, 0 };
109 struct ipi_cache_args ipi_cache_args;
110 struct ipi_rd_args ipi_rd_args;
111 struct ipi_tlb_args ipi_tlb_args;
112 struct pcb stoppcbs[MAXCPU];
116 cpu_ipi_selected_t *cpu_ipi_selected;
117 cpu_ipi_single_t *cpu_ipi_single;
119 static vm_offset_t mp_tramp;
120 static u_int cpuid_to_mid[MAXCPU];
122 static volatile cpumask_t shutdown_cpus;
124 static void ap_count(phandle_t node, u_int mid, u_int cpu_impl);
125 static void ap_start(phandle_t node, u_int mid, u_int cpu_impl);
126 static void cpu_mp_unleash(void *v);
127 static void foreach_ap(phandle_t node, void (*func)(phandle_t node,
128 u_int mid, u_int cpu_impl));
129 static void sun4u_startcpu(phandle_t cpu, void *func, u_long arg);
131 static cpu_ipi_selected_t cheetah_ipi_selected;
132 static cpu_ipi_single_t cheetah_ipi_single;
133 static cpu_ipi_selected_t jalapeno_ipi_selected;
134 static cpu_ipi_single_t jalapeno_ipi_single;
135 static cpu_ipi_selected_t spitfire_ipi_selected;
136 static cpu_ipi_single_t spitfire_ipi_single;
138 SYSINIT(cpu_mp_unleash, SI_SUB_SMP, SI_ORDER_FIRST, cpu_mp_unleash, NULL);
140 CTASSERT(MAXCPU <= IDR_CHEETAH_MAX_BN_PAIRS);
141 CTASSERT(MAXCPU <= sizeof(u_int) * NBBY);
142 CTASSERT(MAXCPU <= sizeof(int) * NBBY);
145 mp_init(u_int cpu_impl)
150 mp_tramp = (vm_offset_t)OF_claim(NULL, PAGE_SIZE, PAGE_SIZE);
151 if (mp_tramp == (vm_offset_t)-1)
152 panic("%s", __func__);
153 bcopy(mp_tramp_code, (void *)mp_tramp, mp_tramp_code_len);
154 *(vm_offset_t *)(mp_tramp + mp_tramp_tlb_slots) = kernel_tlb_slots;
155 *(vm_offset_t *)(mp_tramp + mp_tramp_func) = (vm_offset_t)mp_startup;
156 tp = (struct tte *)(mp_tramp + mp_tramp_code_len);
157 for (i = 0; i < kernel_tlb_slots; i++) {
158 tp[i].tte_vpn = TV_VPN(kernel_tlbs[i].te_va, TS_4M);
159 tp[i].tte_data = TD_V | TD_4M | TD_PA(kernel_tlbs[i].te_pa) |
160 TD_L | TD_CP | TD_CV | TD_P | TD_W;
162 for (i = 0; i < PAGE_SIZE; i += sizeof(vm_offset_t))
166 * On UP systems cpu_ipi_selected() can be called while
167 * cpu_mp_start() wasn't so initialize these here.
169 if (cpu_impl == CPU_IMPL_ULTRASPARCIIIi ||
170 cpu_impl == CPU_IMPL_ULTRASPARCIIIip) {
172 cpu_ipi_selected = jalapeno_ipi_selected;
173 cpu_ipi_single = jalapeno_ipi_single;
174 } else if (cpu_impl == CPU_IMPL_SPARC64V ||
175 cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
176 cpu_ipi_selected = cheetah_ipi_selected;
177 cpu_ipi_single = cheetah_ipi_single;
179 cpu_ipi_selected = spitfire_ipi_selected;
180 cpu_ipi_single = spitfire_ipi_single;
185 foreach_ap(phandle_t node, void (*func)(phandle_t node, u_int mid,
188 char type[sizeof("cpu")];
193 /* There's no need to traverse the whole OFW tree twice. */
194 if (mp_maxid > 0 && mp_ncpus >= mp_maxid + 1)
197 for (; node != 0; node = OF_peer(node)) {
198 child = OF_child(node);
200 foreach_ap(child, func);
202 if (OF_getprop(node, "device_type", type,
205 if (strcmp(type, "cpu") != 0)
207 if (OF_getprop(node, "implementation#", &cpu_impl,
208 sizeof(cpu_impl)) <= 0)
209 panic("%s: couldn't determine CPU "
210 "implementation", __func__);
211 if (OF_getprop(node, cpu_cpuid_prop(cpu_impl), &cpuid,
213 panic("%s: couldn't determine CPU module ID",
215 if (cpuid == PCPU_GET(mid))
217 (*func)(node, cpuid, cpu_impl);
223 * Probe for other CPUs.
229 all_cpus = 1 << curcpu;
233 foreach_ap(OF_child(OF_peer(0)), ap_count);
237 ap_count(phandle_t node __unused, u_int mid __unused, u_int cpu_impl __unused)
247 return (mp_maxid > 0);
254 return (smp_topo_none());
258 sun4u_startcpu(phandle_t cpu, void *func, u_long arg)
268 (cell_t)SUNW_STARTCPU,
273 args.func = (cell_t)func;
274 args.arg = (cell_t)arg;
279 * Fire up any non-boot processors.
285 mtx_init(&ipi_mtx, "ipi", NULL, MTX_SPIN);
287 intr_setup(PIL_AST, cpu_ipi_ast, -1, NULL, NULL);
288 intr_setup(PIL_RENDEZVOUS, (ih_func_t *)smp_rendezvous_action,
290 intr_setup(PIL_STOP, cpu_ipi_stop, -1, NULL, NULL);
291 intr_setup(PIL_PREEMPT, cpu_ipi_preempt, -1, NULL, NULL);
293 cpuid_to_mid[curcpu] = PCPU_GET(mid);
295 foreach_ap(OF_child(OF_peer(0)), ap_start);
296 KASSERT(!isjbus || mp_ncpus <= IDR_JALAPENO_MAX_BN_PAIRS,
297 ("%s: can only IPI a maximum of %d JBus-CPUs",
298 __func__, IDR_JALAPENO_MAX_BN_PAIRS));
299 PCPU_SET(other_cpus, all_cpus & ~(1 << curcpu));
304 ap_start(phandle_t node, u_int mid, u_int cpu_impl)
306 volatile struct cpu_start_args *csa;
313 if (mp_ncpus > MAXCPU)
316 if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) <= 0)
317 panic("%s: couldn't determine CPU frequency", __func__);
318 if (clock != PCPU_GET(clock))
319 hardclock_use_stick = 1;
321 csa = &cpu_start_args;
323 sun4u_startcpu(node, (void *)mp_tramp, 0);
325 while (csa->csa_state != CPU_TICKSYNC)
328 csa->csa_tick = rd(tick);
329 if (cpu_impl == CPU_IMPL_SPARC64V ||
330 cpu_impl >= CPU_IMPL_ULTRASPARCIII) {
331 while (csa->csa_state != CPU_STICKSYNC)
334 csa->csa_stick = rdstick();
336 while (csa->csa_state != CPU_INIT)
338 csa->csa_tick = csa->csa_stick = 0;
342 cpuid_to_mid[cpuid] = mid;
343 cpu_identify(csa->csa_ver, clock, cpuid);
345 va = kmem_alloc(kernel_map, PCPU_PAGES * PAGE_SIZE);
346 pc = (struct pcpu *)(va + (PCPU_PAGES * PAGE_SIZE)) - 1;
347 pcpu_init(pc, cpuid, sizeof(*pc));
348 dpcpu_init((void *)kmem_alloc(kernel_map, DPCPU_SIZE), cpuid);
350 pc->pc_clock = clock;
351 pc->pc_impl = cpu_impl;
357 all_cpus |= 1 << cpuid;
362 cpu_mp_announce(void)
368 cpu_mp_unleash(void *v)
370 volatile struct cpu_start_args *csa;
379 ctx_min = TLB_CTX_USER_MIN;
380 ctx_inc = (TLB_CTX_USER_MAX - 1) / mp_ncpus;
381 csa = &cpu_start_args;
382 csa->csa_count = mp_ncpus;
383 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) {
384 pc->pc_tlb_ctx = ctx_min;
385 pc->pc_tlb_ctx_min = ctx_min;
386 pc->pc_tlb_ctx_max = ctx_min + ctx_inc;
389 if (pc->pc_cpuid == curcpu)
391 KASSERT(pc->pc_idlethread != NULL,
392 ("%s: idlethread", __func__));
393 pc->pc_curthread = pc->pc_idlethread;
394 pc->pc_curpcb = pc->pc_curthread->td_pcb;
395 for (i = 0; i < PCPU_PAGES; i++) {
396 va = pc->pc_addr + i * PAGE_SIZE;
397 pa = pmap_kextract(va);
399 panic("%s: pmap_kextract", __func__);
400 csa->csa_ttes[i].tte_vpn = TV_VPN(va, TS_8K);
401 csa->csa_ttes[i].tte_data = TD_V | TD_8K | TD_PA(pa) |
402 TD_L | TD_CP | TD_CV | TD_P | TD_W;
405 csa->csa_pcpu = pc->pc_addr;
406 csa->csa_mid = pc->pc_mid;
408 while (csa->csa_state != CPU_BOOTSTRAP)
419 cpu_mp_bootstrap(struct pcpu *pc)
421 volatile struct cpu_start_args *csa;
423 csa = &cpu_start_args;
425 /* Do CPU-specific initialization. */
426 if (pc->pc_impl == CPU_IMPL_SPARC64V ||
427 pc->pc_impl >= CPU_IMPL_ULTRASPARCIII)
428 cheetah_init(pc->pc_impl);
430 * Enable the caches. Note that his may include applying workarounds.
432 cache_enable(pc->pc_impl);
435 * Clear (S)TICK timer(s) (including NPT) and ensure they are stopped.
437 tick_clear(pc->pc_impl);
438 tick_stop(pc->pc_impl);
440 /* Lock the kernel TSB in the TLB. */
444 * Flush all non-locked TLB entries possibly left over by the
447 tlb_flush_nonlocked();
449 /* Initialize global registers. */
454 * Note that the PIL we be lowered indirectly via sched_throw(NULL)
455 * when fake spinlock held by the idle thread eventually is released.
457 wrpr(pstate, 0, PSTATE_KERNEL);
459 /* Start the (S)TICK interrupts. */
463 KASSERT(curthread != NULL, ("%s: curthread", __func__));
464 PCPU_SET(other_cpus, all_cpus & ~(1 << curcpu));
465 printf("SMP: AP CPU #%d Launched!\n", curcpu);
469 csa->csa_state = CPU_BOOTSTRAP;
470 while (csa->csa_count != 0)
473 /* Ok, now enter the scheduler. */
478 cpu_mp_shutdown(void)
483 shutdown_cpus = PCPU_GET(other_cpus);
484 if (stopped_cpus != PCPU_GET(other_cpus)) /* XXX */
485 stop_cpus(stopped_cpus ^ PCPU_GET(other_cpus));
487 while (shutdown_cpus != 0) {
489 printf("timeout shutting down CPUs.\n");
497 cpu_ipi_ast(struct trapframe *tf)
503 cpu_ipi_stop(struct trapframe *tf)
506 CTR2(KTR_SMP, "%s: stopped %d", __func__, curcpu);
507 savectx(&stoppcbs[curcpu]);
508 atomic_set_acq_int(&stopped_cpus, PCPU_GET(cpumask));
509 while ((started_cpus & PCPU_GET(cpumask)) == 0) {
510 if ((shutdown_cpus & PCPU_GET(cpumask)) != 0) {
511 atomic_clear_int(&shutdown_cpus, PCPU_GET(cpumask));
512 (void)intr_disable();
517 atomic_clear_rel_int(&started_cpus, PCPU_GET(cpumask));
518 atomic_clear_rel_int(&stopped_cpus, PCPU_GET(cpumask));
519 CTR2(KTR_SMP, "%s: restarted %d", __func__, curcpu);
523 cpu_ipi_preempt(struct trapframe *tf)
526 sched_preempt(curthread);
530 spitfire_ipi_selected(u_int cpus, u_long d0, u_long d1, u_long d2)
537 spitfire_ipi_single(cpu, d0, d1, d2);
542 spitfire_ipi_single(u_int cpu, u_long d0, u_long d1, u_long d2)
549 KASSERT(cpu != curcpu, ("%s: CPU can't IPI itself", __func__));
550 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) & IDR_BUSY) == 0,
551 ("%s: outstanding dispatch", __func__));
552 mid = cpuid_to_mid[cpu];
553 for (i = 0; i < IPI_RETRIES; i++) {
555 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
556 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
557 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
559 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
562 * Workaround for SpitFire erratum #54; do a dummy read
563 * from a SDB internal register before the MEMBAR #Sync
564 * for the write to ASI_SDB_INTR_W (requiring another
565 * MEMBAR #Sync in order to make sure the write has
566 * occurred before the load).
569 (void)ldxa(AA_SDB_CNTL_HIGH, ASI_SDB_CONTROL_R);
571 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
575 if ((ids & (IDR_BUSY | IDR_NACK)) == 0)
578 * Leave interrupts enabled for a bit before retrying
579 * in order to avoid deadlocks if the other CPU is also
580 * trying to send an IPI.
584 if (kdb_active != 0 || panicstr != NULL)
585 printf("%s: couldn't send IPI to module 0x%u\n",
588 panic("%s: couldn't send IPI to module 0x%u",
593 cheetah_ipi_single(u_int cpu, u_long d0, u_long d1, u_long d2)
600 KASSERT(cpu != curcpu, ("%s: CPU can't IPI itself", __func__));
601 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
602 IDR_CHEETAH_ALL_BUSY) == 0,
603 ("%s: outstanding dispatch", __func__));
604 mid = cpuid_to_mid[cpu];
605 for (i = 0; i < IPI_RETRIES; i++) {
607 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
608 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
609 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
611 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
614 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
618 if ((ids & (IDR_BUSY | IDR_NACK)) == 0)
621 * Leave interrupts enabled for a bit before retrying
622 * in order to avoid deadlocks if the other CPU is also
623 * trying to send an IPI.
627 if (kdb_active != 0 || panicstr != NULL)
628 printf("%s: couldn't send IPI to module 0x%u\n",
631 panic("%s: couldn't send IPI to module 0x%u",
636 cheetah_ipi_selected(u_int cpus, u_long d0, u_long d1, u_long d2)
644 KASSERT((cpus & (1 << curcpu)) == 0,
645 ("%s: CPU can't IPI itself", __func__));
646 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
647 IDR_CHEETAH_ALL_BUSY) == 0,
648 ("%s: outstanding dispatch", __func__));
652 for (i = 0; i < IPI_RETRIES * mp_ncpus; i++) {
654 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
655 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
656 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
659 for (cpu = 0; cpu < mp_ncpus; cpu++) {
660 if ((cpus & (1 << cpu)) != 0) {
661 stxa(AA_INTR_SEND | (cpuid_to_mid[cpu] <<
662 IDC_ITID_SHIFT) | bnp << IDC_BN_SHIFT,
668 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
669 IDR_CHEETAH_ALL_BUSY) != 0)
673 (IDR_CHEETAH_ALL_BUSY | IDR_CHEETAH_ALL_NACK)) == 0)
676 for (cpu = 0; cpu < mp_ncpus; cpu++) {
677 if ((cpus & (1 << cpu)) != 0) {
678 if ((ids & (IDR_NACK << (2 * bnp))) == 0)
684 * On at least Fire V880 we may receive IDR_NACKs for
685 * CPUs we actually haven't tried to send an IPI to,
686 * but which apparently can be safely ignored.
691 * Leave interrupts enabled for a bit before retrying
692 * in order to avoid deadlocks if the other CPUs are
693 * also trying to send IPIs.
697 if (kdb_active != 0 || panicstr != NULL)
698 printf("%s: couldn't send IPI (cpus=0x%u ids=0x%lu)\n",
699 __func__, cpus, ids);
701 panic("%s: couldn't send IPI (cpus=0x%u ids=0x%lu)",
702 __func__, cpus, ids);
706 jalapeno_ipi_single(u_int cpu, u_long d0, u_long d1, u_long d2)
710 u_int busy, busynack, mid;
713 KASSERT(cpu != curcpu, ("%s: CPU can't IPI itself", __func__));
714 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
715 IDR_CHEETAH_ALL_BUSY) == 0,
716 ("%s: outstanding dispatch", __func__));
717 mid = cpuid_to_mid[cpu];
718 busy = IDR_BUSY << (2 * mid);
719 busynack = (IDR_BUSY | IDR_NACK) << (2 * mid);
720 for (i = 0; i < IPI_RETRIES; i++) {
722 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
723 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
724 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
726 stxa(AA_INTR_SEND | (mid << IDC_ITID_SHIFT),
729 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
733 if ((ids & busynack) == 0)
736 * Leave interrupts enabled for a bit before retrying
737 * in order to avoid deadlocks if the other CPU is also
738 * trying to send an IPI.
742 if (kdb_active != 0 || panicstr != NULL)
743 printf("%s: couldn't send IPI to module 0x%u\n",
746 panic("%s: couldn't send IPI to module 0x%u",
751 jalapeno_ipi_selected(u_int cpus, u_long d0, u_long d1, u_long d2)
758 KASSERT((cpus & (1 << curcpu)) == 0,
759 ("%s: CPU can't IPI itself", __func__));
760 KASSERT((ldxa(0, ASI_INTR_DISPATCH_STATUS) &
761 IDR_CHEETAH_ALL_BUSY) == 0,
762 ("%s: outstanding dispatch", __func__));
766 for (i = 0; i < IPI_RETRIES * mp_ncpus; i++) {
768 stxa(AA_SDB_INTR_D0, ASI_SDB_INTR_W, d0);
769 stxa(AA_SDB_INTR_D1, ASI_SDB_INTR_W, d1);
770 stxa(AA_SDB_INTR_D2, ASI_SDB_INTR_W, d2);
772 for (cpu = 0; cpu < mp_ncpus; cpu++) {
773 if ((cpus & (1 << cpu)) != 0) {
774 stxa(AA_INTR_SEND | (cpuid_to_mid[cpu] <<
775 IDC_ITID_SHIFT), ASI_SDB_INTR_W, 0);
779 while (((ids = ldxa(0, ASI_INTR_DISPATCH_STATUS)) &
780 IDR_CHEETAH_ALL_BUSY) != 0)
784 (IDR_CHEETAH_ALL_BUSY | IDR_CHEETAH_ALL_NACK)) == 0)
786 for (cpu = 0; cpu < mp_ncpus; cpu++)
787 if ((cpus & (1 << cpu)) != 0)
788 if ((ids & (IDR_NACK <<
789 (2 * cpuid_to_mid[cpu]))) == 0)
792 * Leave interrupts enabled for a bit before retrying
793 * in order to avoid deadlocks if the other CPUs are
794 * also trying to send IPIs.
798 if (kdb_active != 0 || panicstr != NULL)
799 printf("%s: couldn't send IPI (cpus=0x%u ids=0x%lu)\n",
800 __func__, cpus, ids);
802 panic("%s: couldn't send IPI (cpus=0x%u ids=0x%lu)",
803 __func__, cpus, ids);