2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #define BXE_DRIVER_VERSION "1.78.81"
34 #include "ecore_init.h"
35 #include "ecore_init_ops.h"
37 #include "57710_int_offsets.h"
38 #include "57711_int_offsets.h"
39 #include "57712_int_offsets.h"
42 * CTLTYPE_U64 and sysctl_handle_64 were added in r217616. Define these
43 * explicitly here for older kernels that don't include this changeset.
46 #define CTLTYPE_U64 CTLTYPE_QUAD
47 #define sysctl_handle_64 sysctl_handle_quad
51 * CSUM_TCP_IPV6 and CSUM_UDP_IPV6 were added in r236170. Define these
52 * here as zero(0) for older kernels that don't include this changeset
53 * thereby masking the functionality.
56 #define CSUM_TCP_IPV6 0
57 #define CSUM_UDP_IPV6 0
61 * pci_find_cap was added in r219865. Re-define this at pci_find_extcap
62 * for older kernels that don't include this changeset.
64 #if __FreeBSD_version < 900035
65 #define pci_find_cap pci_find_extcap
68 #define BXE_DEF_SB_ATT_IDX 0x0001
69 #define BXE_DEF_SB_IDX 0x0002
72 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per
73 * function HW initialization.
75 #define FLR_WAIT_USEC 10000 /* 10 msecs */
76 #define FLR_WAIT_INTERVAL 50 /* usecs */
77 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
79 struct pbf_pN_buf_regs {
86 struct pbf_pN_cmd_regs {
93 * PCI Device ID Table used by bxe_probe().
95 #define BXE_DEVDESC_MAX 64
96 static struct bxe_device_type bxe_devs[] = {
100 PCI_ANY_ID, PCI_ANY_ID,
101 "QLogic NetXtreme II BCM57710 10GbE"
106 PCI_ANY_ID, PCI_ANY_ID,
107 "QLogic NetXtreme II BCM57711 10GbE"
112 PCI_ANY_ID, PCI_ANY_ID,
113 "QLogic NetXtreme II BCM57711E 10GbE"
118 PCI_ANY_ID, PCI_ANY_ID,
119 "QLogic NetXtreme II BCM57712 10GbE"
124 PCI_ANY_ID, PCI_ANY_ID,
125 "QLogic NetXtreme II BCM57712 MF 10GbE"
130 PCI_ANY_ID, PCI_ANY_ID,
131 "QLogic NetXtreme II BCM57800 10GbE"
136 PCI_ANY_ID, PCI_ANY_ID,
137 "QLogic NetXtreme II BCM57800 MF 10GbE"
142 PCI_ANY_ID, PCI_ANY_ID,
143 "QLogic NetXtreme II BCM57810 10GbE"
148 PCI_ANY_ID, PCI_ANY_ID,
149 "QLogic NetXtreme II BCM57810 MF 10GbE"
154 PCI_ANY_ID, PCI_ANY_ID,
155 "QLogic NetXtreme II BCM57811 10GbE"
160 PCI_ANY_ID, PCI_ANY_ID,
161 "QLogic NetXtreme II BCM57811 MF 10GbE"
166 PCI_ANY_ID, PCI_ANY_ID,
167 "QLogic NetXtreme II BCM57840 4x10GbE"
172 PCI_ANY_ID, PCI_ANY_ID,
173 "QLogic NetXtreme II BCM57840 MF 10GbE"
180 MALLOC_DECLARE(M_BXE_ILT);
181 MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer");
184 * FreeBSD device entry points.
186 static int bxe_probe(device_t);
187 static int bxe_attach(device_t);
188 static int bxe_detach(device_t);
189 static int bxe_shutdown(device_t);
192 * FreeBSD KLD module/device interface event handler method.
194 static device_method_t bxe_methods[] = {
195 /* Device interface (device_if.h) */
196 DEVMETHOD(device_probe, bxe_probe),
197 DEVMETHOD(device_attach, bxe_attach),
198 DEVMETHOD(device_detach, bxe_detach),
199 DEVMETHOD(device_shutdown, bxe_shutdown),
200 /* Bus interface (bus_if.h) */
201 DEVMETHOD(bus_print_child, bus_generic_print_child),
202 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
207 * FreeBSD KLD Module data declaration
209 static driver_t bxe_driver = {
210 "bxe", /* module name */
211 bxe_methods, /* event handler */
212 sizeof(struct bxe_softc) /* extra data */
216 * FreeBSD dev class is needed to manage dev instances and
217 * to associate with a bus type
219 static devclass_t bxe_devclass;
221 MODULE_DEPEND(bxe, pci, 1, 1, 1);
222 MODULE_DEPEND(bxe, ether, 1, 1, 1);
223 DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0);
225 /* resources needed for unloading a previously loaded device */
227 #define BXE_PREV_WAIT_NEEDED 1
228 struct mtx bxe_prev_mtx;
229 MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF);
230 struct bxe_prev_list_node {
231 LIST_ENTRY(bxe_prev_list_node) node;
235 uint8_t aer; /* XXX automatic error recovery */
238 static LIST_HEAD(, bxe_prev_list_node) bxe_prev_list = LIST_HEAD_INITIALIZER(bxe_prev_list);
240 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
242 /* Tunable device values... */
244 SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters");
247 unsigned long bxe_debug = 0;
248 TUNABLE_ULONG("hw.bxe.debug", &bxe_debug);
249 SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, (CTLFLAG_RDTUN),
250 &bxe_debug, 0, "Debug logging mode");
252 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
253 static int bxe_interrupt_mode = INTR_MODE_MSIX;
254 TUNABLE_INT("hw.bxe.interrupt_mode", &bxe_interrupt_mode);
255 SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN,
256 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode");
258 /* Number of Queues: 0 (Auto) or 1 to 16 (fixed queue number) */
259 static int bxe_queue_count = 4;
260 TUNABLE_INT("hw.bxe.queue_count", &bxe_queue_count);
261 SYSCTL_INT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN,
262 &bxe_queue_count, 0, "Multi-Queue queue count");
264 /* max number of buffers per queue (default RX_BD_USABLE) */
265 static int bxe_max_rx_bufs = 0;
266 TUNABLE_INT("hw.bxe.max_rx_bufs", &bxe_max_rx_bufs);
267 SYSCTL_INT(_hw_bxe, OID_AUTO, max_rx_bufs, CTLFLAG_RDTUN,
268 &bxe_max_rx_bufs, 0, "Maximum Number of Rx Buffers Per Queue");
270 /* Host interrupt coalescing RX tick timer (usecs) */
271 static int bxe_hc_rx_ticks = 25;
272 TUNABLE_INT("hw.bxe.hc_rx_ticks", &bxe_hc_rx_ticks);
273 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_rx_ticks, CTLFLAG_RDTUN,
274 &bxe_hc_rx_ticks, 0, "Host Coalescing Rx ticks");
276 /* Host interrupt coalescing TX tick timer (usecs) */
277 static int bxe_hc_tx_ticks = 50;
278 TUNABLE_INT("hw.bxe.hc_tx_ticks", &bxe_hc_tx_ticks);
279 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_tx_ticks, CTLFLAG_RDTUN,
280 &bxe_hc_tx_ticks, 0, "Host Coalescing Tx ticks");
282 /* Maximum number of Rx packets to process at a time */
283 static int bxe_rx_budget = 0xffffffff;
284 TUNABLE_INT("hw.bxe.rx_budget", &bxe_rx_budget);
285 SYSCTL_INT(_hw_bxe, OID_AUTO, rx_budget, CTLFLAG_TUN,
286 &bxe_rx_budget, 0, "Rx processing budget");
288 /* Maximum LRO aggregation size */
289 static int bxe_max_aggregation_size = 0;
290 TUNABLE_INT("hw.bxe.max_aggregation_size", &bxe_max_aggregation_size);
291 SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_TUN,
292 &bxe_max_aggregation_size, 0, "max aggregation size");
294 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */
295 static int bxe_mrrs = -1;
296 TUNABLE_INT("hw.bxe.mrrs", &bxe_mrrs);
297 SYSCTL_INT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN,
298 &bxe_mrrs, 0, "PCIe maximum read request size");
300 /* AutoGrEEEn: 0 (hardware default), 1 (force on), 2 (force off) */
301 static int bxe_autogreeen = 0;
302 TUNABLE_INT("hw.bxe.autogreeen", &bxe_autogreeen);
303 SYSCTL_INT(_hw_bxe, OID_AUTO, autogreeen, CTLFLAG_RDTUN,
304 &bxe_autogreeen, 0, "AutoGrEEEn support");
306 /* 4-tuple RSS support for UDP: 0 (disabled), 1 (enabled) */
307 static int bxe_udp_rss = 0;
308 TUNABLE_INT("hw.bxe.udp_rss", &bxe_udp_rss);
309 SYSCTL_INT(_hw_bxe, OID_AUTO, udp_rss, CTLFLAG_RDTUN,
310 &bxe_udp_rss, 0, "UDP RSS support");
313 #define STAT_NAME_LEN 32 /* no stat names below can be longer than this */
315 #define STATS_OFFSET32(stat_name) \
316 (offsetof(struct bxe_eth_stats, stat_name) / 4)
318 #define Q_STATS_OFFSET32(stat_name) \
319 (offsetof(struct bxe_eth_q_stats, stat_name) / 4)
321 static const struct {
325 #define STATS_FLAGS_PORT 1
326 #define STATS_FLAGS_FUNC 2 /* MF only cares about function stats */
327 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
328 char string[STAT_NAME_LEN];
329 } bxe_eth_stats_arr[] = {
330 { STATS_OFFSET32(total_bytes_received_hi),
331 8, STATS_FLAGS_BOTH, "rx_bytes" },
332 { STATS_OFFSET32(error_bytes_received_hi),
333 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
334 { STATS_OFFSET32(total_unicast_packets_received_hi),
335 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
336 { STATS_OFFSET32(total_multicast_packets_received_hi),
337 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
338 { STATS_OFFSET32(total_broadcast_packets_received_hi),
339 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
340 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
341 8, STATS_FLAGS_PORT, "rx_crc_errors" },
342 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
343 8, STATS_FLAGS_PORT, "rx_align_errors" },
344 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
345 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
346 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
347 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
348 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
349 8, STATS_FLAGS_PORT, "rx_fragments" },
350 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
351 8, STATS_FLAGS_PORT, "rx_jabbers" },
352 { STATS_OFFSET32(no_buff_discard_hi),
353 8, STATS_FLAGS_BOTH, "rx_discards" },
354 { STATS_OFFSET32(mac_filter_discard),
355 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
356 { STATS_OFFSET32(mf_tag_discard),
357 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
358 { STATS_OFFSET32(pfc_frames_received_hi),
359 8, STATS_FLAGS_PORT, "pfc_frames_received" },
360 { STATS_OFFSET32(pfc_frames_sent_hi),
361 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
362 { STATS_OFFSET32(brb_drop_hi),
363 8, STATS_FLAGS_PORT, "rx_brb_discard" },
364 { STATS_OFFSET32(brb_truncate_hi),
365 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
366 { STATS_OFFSET32(pause_frames_received_hi),
367 8, STATS_FLAGS_PORT, "rx_pause_frames" },
368 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
369 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
370 { STATS_OFFSET32(nig_timer_max),
371 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
372 { STATS_OFFSET32(total_bytes_transmitted_hi),
373 8, STATS_FLAGS_BOTH, "tx_bytes" },
374 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
375 8, STATS_FLAGS_PORT, "tx_error_bytes" },
376 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
377 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
378 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
379 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
380 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
381 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
382 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
383 8, STATS_FLAGS_PORT, "tx_mac_errors" },
384 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
385 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
386 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
387 8, STATS_FLAGS_PORT, "tx_single_collisions" },
388 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
389 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
390 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
391 8, STATS_FLAGS_PORT, "tx_deferred" },
392 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
393 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
394 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
395 8, STATS_FLAGS_PORT, "tx_late_collisions" },
396 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
397 8, STATS_FLAGS_PORT, "tx_total_collisions" },
398 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
399 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
400 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
401 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
402 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
403 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
404 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
405 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
406 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
407 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
408 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
409 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
410 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
411 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
412 { STATS_OFFSET32(pause_frames_sent_hi),
413 8, STATS_FLAGS_PORT, "tx_pause_frames" },
414 { STATS_OFFSET32(total_tpa_aggregations_hi),
415 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
416 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
417 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
418 { STATS_OFFSET32(total_tpa_bytes_hi),
419 8, STATS_FLAGS_FUNC, "tpa_bytes"},
420 { STATS_OFFSET32(eee_tx_lpi),
421 4, STATS_FLAGS_PORT, "eee_tx_lpi"},
422 { STATS_OFFSET32(rx_calls),
423 4, STATS_FLAGS_FUNC, "rx_calls"},
424 { STATS_OFFSET32(rx_pkts),
425 4, STATS_FLAGS_FUNC, "rx_pkts"},
426 { STATS_OFFSET32(rx_tpa_pkts),
427 4, STATS_FLAGS_FUNC, "rx_tpa_pkts"},
428 { STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts),
429 4, STATS_FLAGS_FUNC, "rx_erroneous_jumbo_sge_pkts"},
430 { STATS_OFFSET32(rx_bxe_service_rxsgl),
431 4, STATS_FLAGS_FUNC, "rx_bxe_service_rxsgl"},
432 { STATS_OFFSET32(rx_jumbo_sge_pkts),
433 4, STATS_FLAGS_FUNC, "rx_jumbo_sge_pkts"},
434 { STATS_OFFSET32(rx_soft_errors),
435 4, STATS_FLAGS_FUNC, "rx_soft_errors"},
436 { STATS_OFFSET32(rx_hw_csum_errors),
437 4, STATS_FLAGS_FUNC, "rx_hw_csum_errors"},
438 { STATS_OFFSET32(rx_ofld_frames_csum_ip),
439 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_ip"},
440 { STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
441 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_tcp_udp"},
442 { STATS_OFFSET32(rx_budget_reached),
443 4, STATS_FLAGS_FUNC, "rx_budget_reached"},
444 { STATS_OFFSET32(tx_pkts),
445 4, STATS_FLAGS_FUNC, "tx_pkts"},
446 { STATS_OFFSET32(tx_soft_errors),
447 4, STATS_FLAGS_FUNC, "tx_soft_errors"},
448 { STATS_OFFSET32(tx_ofld_frames_csum_ip),
449 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_ip"},
450 { STATS_OFFSET32(tx_ofld_frames_csum_tcp),
451 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_tcp"},
452 { STATS_OFFSET32(tx_ofld_frames_csum_udp),
453 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_udp"},
454 { STATS_OFFSET32(tx_ofld_frames_lso),
455 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso"},
456 { STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
457 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso_hdr_splits"},
458 { STATS_OFFSET32(tx_encap_failures),
459 4, STATS_FLAGS_FUNC, "tx_encap_failures"},
460 { STATS_OFFSET32(tx_hw_queue_full),
461 4, STATS_FLAGS_FUNC, "tx_hw_queue_full"},
462 { STATS_OFFSET32(tx_hw_max_queue_depth),
463 4, STATS_FLAGS_FUNC, "tx_hw_max_queue_depth"},
464 { STATS_OFFSET32(tx_dma_mapping_failure),
465 4, STATS_FLAGS_FUNC, "tx_dma_mapping_failure"},
466 { STATS_OFFSET32(tx_max_drbr_queue_depth),
467 4, STATS_FLAGS_FUNC, "tx_max_drbr_queue_depth"},
468 { STATS_OFFSET32(tx_window_violation_std),
469 4, STATS_FLAGS_FUNC, "tx_window_violation_std"},
470 { STATS_OFFSET32(tx_window_violation_tso),
471 4, STATS_FLAGS_FUNC, "tx_window_violation_tso"},
472 { STATS_OFFSET32(tx_chain_lost_mbuf),
473 4, STATS_FLAGS_FUNC, "tx_chain_lost_mbuf"},
474 { STATS_OFFSET32(tx_frames_deferred),
475 4, STATS_FLAGS_FUNC, "tx_frames_deferred"},
476 { STATS_OFFSET32(tx_queue_xoff),
477 4, STATS_FLAGS_FUNC, "tx_queue_xoff"},
478 { STATS_OFFSET32(mbuf_defrag_attempts),
479 4, STATS_FLAGS_FUNC, "mbuf_defrag_attempts"},
480 { STATS_OFFSET32(mbuf_defrag_failures),
481 4, STATS_FLAGS_FUNC, "mbuf_defrag_failures"},
482 { STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
483 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_alloc_failed"},
484 { STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
485 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_mapping_failed"},
486 { STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
487 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_alloc_failed"},
488 { STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
489 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_mapping_failed"},
490 { STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
491 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_alloc_failed"},
492 { STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
493 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_mapping_failed"},
494 { STATS_OFFSET32(mbuf_alloc_tx),
495 4, STATS_FLAGS_FUNC, "mbuf_alloc_tx"},
496 { STATS_OFFSET32(mbuf_alloc_rx),
497 4, STATS_FLAGS_FUNC, "mbuf_alloc_rx"},
498 { STATS_OFFSET32(mbuf_alloc_sge),
499 4, STATS_FLAGS_FUNC, "mbuf_alloc_sge"},
500 { STATS_OFFSET32(mbuf_alloc_tpa),
501 4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"},
502 { STATS_OFFSET32(tx_queue_full_return),
503 4, STATS_FLAGS_FUNC, "tx_queue_full_return"}
506 static const struct {
509 char string[STAT_NAME_LEN];
510 } bxe_eth_q_stats_arr[] = {
511 { Q_STATS_OFFSET32(total_bytes_received_hi),
513 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
514 8, "rx_ucast_packets" },
515 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
516 8, "rx_mcast_packets" },
517 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
518 8, "rx_bcast_packets" },
519 { Q_STATS_OFFSET32(no_buff_discard_hi),
521 { Q_STATS_OFFSET32(total_bytes_transmitted_hi),
523 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
524 8, "tx_ucast_packets" },
525 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
526 8, "tx_mcast_packets" },
527 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
528 8, "tx_bcast_packets" },
529 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
530 8, "tpa_aggregations" },
531 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
532 8, "tpa_aggregated_frames"},
533 { Q_STATS_OFFSET32(total_tpa_bytes_hi),
535 { Q_STATS_OFFSET32(rx_calls),
537 { Q_STATS_OFFSET32(rx_pkts),
539 { Q_STATS_OFFSET32(rx_tpa_pkts),
541 { Q_STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts),
542 4, "rx_erroneous_jumbo_sge_pkts"},
543 { Q_STATS_OFFSET32(rx_bxe_service_rxsgl),
544 4, "rx_bxe_service_rxsgl"},
545 { Q_STATS_OFFSET32(rx_jumbo_sge_pkts),
546 4, "rx_jumbo_sge_pkts"},
547 { Q_STATS_OFFSET32(rx_soft_errors),
548 4, "rx_soft_errors"},
549 { Q_STATS_OFFSET32(rx_hw_csum_errors),
550 4, "rx_hw_csum_errors"},
551 { Q_STATS_OFFSET32(rx_ofld_frames_csum_ip),
552 4, "rx_ofld_frames_csum_ip"},
553 { Q_STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
554 4, "rx_ofld_frames_csum_tcp_udp"},
555 { Q_STATS_OFFSET32(rx_budget_reached),
556 4, "rx_budget_reached"},
557 { Q_STATS_OFFSET32(tx_pkts),
559 { Q_STATS_OFFSET32(tx_soft_errors),
560 4, "tx_soft_errors"},
561 { Q_STATS_OFFSET32(tx_ofld_frames_csum_ip),
562 4, "tx_ofld_frames_csum_ip"},
563 { Q_STATS_OFFSET32(tx_ofld_frames_csum_tcp),
564 4, "tx_ofld_frames_csum_tcp"},
565 { Q_STATS_OFFSET32(tx_ofld_frames_csum_udp),
566 4, "tx_ofld_frames_csum_udp"},
567 { Q_STATS_OFFSET32(tx_ofld_frames_lso),
568 4, "tx_ofld_frames_lso"},
569 { Q_STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
570 4, "tx_ofld_frames_lso_hdr_splits"},
571 { Q_STATS_OFFSET32(tx_encap_failures),
572 4, "tx_encap_failures"},
573 { Q_STATS_OFFSET32(tx_hw_queue_full),
574 4, "tx_hw_queue_full"},
575 { Q_STATS_OFFSET32(tx_hw_max_queue_depth),
576 4, "tx_hw_max_queue_depth"},
577 { Q_STATS_OFFSET32(tx_dma_mapping_failure),
578 4, "tx_dma_mapping_failure"},
579 { Q_STATS_OFFSET32(tx_max_drbr_queue_depth),
580 4, "tx_max_drbr_queue_depth"},
581 { Q_STATS_OFFSET32(tx_window_violation_std),
582 4, "tx_window_violation_std"},
583 { Q_STATS_OFFSET32(tx_window_violation_tso),
584 4, "tx_window_violation_tso"},
585 { Q_STATS_OFFSET32(tx_chain_lost_mbuf),
586 4, "tx_chain_lost_mbuf"},
587 { Q_STATS_OFFSET32(tx_frames_deferred),
588 4, "tx_frames_deferred"},
589 { Q_STATS_OFFSET32(tx_queue_xoff),
591 { Q_STATS_OFFSET32(mbuf_defrag_attempts),
592 4, "mbuf_defrag_attempts"},
593 { Q_STATS_OFFSET32(mbuf_defrag_failures),
594 4, "mbuf_defrag_failures"},
595 { Q_STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
596 4, "mbuf_rx_bd_alloc_failed"},
597 { Q_STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
598 4, "mbuf_rx_bd_mapping_failed"},
599 { Q_STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
600 4, "mbuf_rx_tpa_alloc_failed"},
601 { Q_STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
602 4, "mbuf_rx_tpa_mapping_failed"},
603 { Q_STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
604 4, "mbuf_rx_sge_alloc_failed"},
605 { Q_STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
606 4, "mbuf_rx_sge_mapping_failed"},
607 { Q_STATS_OFFSET32(mbuf_alloc_tx),
609 { Q_STATS_OFFSET32(mbuf_alloc_rx),
611 { Q_STATS_OFFSET32(mbuf_alloc_sge),
612 4, "mbuf_alloc_sge"},
613 { Q_STATS_OFFSET32(mbuf_alloc_tpa),
614 4, "mbuf_alloc_tpa"},
615 { Q_STATS_OFFSET32(tx_queue_full_return),
616 4, "tx_queue_full_return"}
619 #define BXE_NUM_ETH_STATS ARRAY_SIZE(bxe_eth_stats_arr)
620 #define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr)
623 static void bxe_cmng_fns_init(struct bxe_softc *sc,
626 static int bxe_get_cmng_fns_mode(struct bxe_softc *sc);
627 static void storm_memset_cmng(struct bxe_softc *sc,
628 struct cmng_init *cmng,
630 static void bxe_set_reset_global(struct bxe_softc *sc);
631 static void bxe_set_reset_in_progress(struct bxe_softc *sc);
632 static uint8_t bxe_reset_is_done(struct bxe_softc *sc,
634 static uint8_t bxe_clear_pf_load(struct bxe_softc *sc);
635 static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc,
638 static void bxe_int_disable(struct bxe_softc *sc);
639 static int bxe_release_leader_lock(struct bxe_softc *sc);
640 static void bxe_pf_disable(struct bxe_softc *sc);
641 static void bxe_free_fp_buffers(struct bxe_softc *sc);
642 static inline void bxe_update_rx_prod(struct bxe_softc *sc,
643 struct bxe_fastpath *fp,
646 uint16_t rx_sge_prod);
647 static void bxe_link_report_locked(struct bxe_softc *sc);
648 static void bxe_link_report(struct bxe_softc *sc);
649 static void bxe_link_status_update(struct bxe_softc *sc);
650 static void bxe_periodic_callout_func(void *xsc);
651 static void bxe_periodic_start(struct bxe_softc *sc);
652 static void bxe_periodic_stop(struct bxe_softc *sc);
653 static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
656 static int bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
658 static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
660 static uint8_t bxe_txeof(struct bxe_softc *sc,
661 struct bxe_fastpath *fp);
662 static void bxe_task_fp(struct bxe_fastpath *fp);
663 static __noinline void bxe_dump_mbuf(struct bxe_softc *sc,
666 static int bxe_alloc_mem(struct bxe_softc *sc);
667 static void bxe_free_mem(struct bxe_softc *sc);
668 static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc);
669 static void bxe_free_fw_stats_mem(struct bxe_softc *sc);
670 static int bxe_interrupt_attach(struct bxe_softc *sc);
671 static void bxe_interrupt_detach(struct bxe_softc *sc);
672 static void bxe_set_rx_mode(struct bxe_softc *sc);
673 static int bxe_init_locked(struct bxe_softc *sc);
674 static int bxe_stop_locked(struct bxe_softc *sc);
675 static __noinline int bxe_nic_load(struct bxe_softc *sc,
677 static __noinline int bxe_nic_unload(struct bxe_softc *sc,
678 uint32_t unload_mode,
681 static void bxe_handle_sp_tq(void *context, int pending);
682 static void bxe_handle_fp_tq(void *context, int pending);
684 static int bxe_add_cdev(struct bxe_softc *sc);
685 static void bxe_del_cdev(struct bxe_softc *sc);
686 static int bxe_grc_dump(struct bxe_softc *sc);
687 static int bxe_alloc_buf_rings(struct bxe_softc *sc);
688 static void bxe_free_buf_rings(struct bxe_softc *sc);
690 /* calculate crc32 on a buffer (NOTE: crc32_length MUST be aligned to 8) */
692 calc_crc32(uint8_t *crc32_packet,
693 uint32_t crc32_length,
702 uint8_t current_byte = 0;
703 uint32_t crc32_result = crc32_seed;
704 const uint32_t CRC32_POLY = 0x1edc6f41;
706 if ((crc32_packet == NULL) ||
707 (crc32_length == 0) ||
708 ((crc32_length % 8) != 0))
710 return (crc32_result);
713 for (byte = 0; byte < crc32_length; byte = byte + 1)
715 current_byte = crc32_packet[byte];
716 for (bit = 0; bit < 8; bit = bit + 1)
718 /* msb = crc32_result[31]; */
719 msb = (uint8_t)(crc32_result >> 31);
721 crc32_result = crc32_result << 1;
723 /* it (msb != current_byte[bit]) */
724 if (msb != (0x1 & (current_byte >> bit)))
726 crc32_result = crc32_result ^ CRC32_POLY;
727 /* crc32_result[0] = 1 */
734 * 1. "mirror" every bit
735 * 2. swap the 4 bytes
736 * 3. complement each bit
741 shft = sizeof(crc32_result) * 8 - 1;
743 for (crc32_result >>= 1; crc32_result; crc32_result >>= 1)
746 temp |= crc32_result & 1;
750 /* temp[31-bit] = crc32_result[bit] */
754 /* crc32_result = {temp[7:0], temp[15:8], temp[23:16], temp[31:24]} */
756 uint32_t t0, t1, t2, t3;
757 t0 = (0x000000ff & (temp >> 24));
758 t1 = (0x0000ff00 & (temp >> 8));
759 t2 = (0x00ff0000 & (temp << 8));
760 t3 = (0xff000000 & (temp << 24));
761 crc32_result = t0 | t1 | t2 | t3;
767 crc32_result = ~crc32_result;
770 return (crc32_result);
775 volatile unsigned long *addr)
777 return ((atomic_load_acq_long(addr) & (1 << nr)) != 0);
781 bxe_set_bit(unsigned int nr,
782 volatile unsigned long *addr)
784 atomic_set_acq_long(addr, (1 << nr));
788 bxe_clear_bit(int nr,
789 volatile unsigned long *addr)
791 atomic_clear_acq_long(addr, (1 << nr));
795 bxe_test_and_set_bit(int nr,
796 volatile unsigned long *addr)
802 } while (atomic_cmpset_acq_long(addr, x, x | nr) == 0);
803 // if (x & nr) bit_was_set; else bit_was_not_set;
808 bxe_test_and_clear_bit(int nr,
809 volatile unsigned long *addr)
815 } while (atomic_cmpset_acq_long(addr, x, x & ~nr) == 0);
816 // if (x & nr) bit_was_set; else bit_was_not_set;
821 bxe_cmpxchg(volatile int *addr,
828 } while (atomic_cmpset_acq_int(addr, old, new) == 0);
833 * Get DMA memory from the OS.
835 * Validates that the OS has provided DMA buffers in response to a
836 * bus_dmamap_load call and saves the physical address of those buffers.
837 * When the callback is used the OS will return 0 for the mapping function
838 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any
839 * failures back to the caller.
845 bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
847 struct bxe_dma *dma = arg;
852 BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error);
854 dma->paddr = segs->ds_addr;
860 * Allocate a block of memory and map it for DMA. No partial completions
861 * allowed and release any resources acquired if we can't acquire all
865 * 0 = Success, !0 = Failure
868 bxe_dma_alloc(struct bxe_softc *sc,
876 BLOGE(sc, "dma block '%s' already has size %lu\n", msg,
877 (unsigned long)dma->size);
881 memset(dma, 0, sizeof(*dma)); /* sanity */
884 snprintf(dma->msg, sizeof(dma->msg), "%s", msg);
886 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
887 BCM_PAGE_SIZE, /* alignment */
888 0, /* boundary limit */
889 BUS_SPACE_MAXADDR, /* restricted low */
890 BUS_SPACE_MAXADDR, /* restricted hi */
891 NULL, /* addr filter() */
892 NULL, /* addr filter() arg */
893 size, /* max map size */
894 1, /* num discontinuous */
895 size, /* max seg size */
896 BUS_DMA_ALLOCNOW, /* flags */
898 NULL, /* lock() arg */
899 &dma->tag); /* returned dma tag */
901 BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc);
902 memset(dma, 0, sizeof(*dma));
906 rc = bus_dmamem_alloc(dma->tag,
907 (void **)&dma->vaddr,
908 (BUS_DMA_NOWAIT | BUS_DMA_ZERO),
911 BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc);
912 bus_dma_tag_destroy(dma->tag);
913 memset(dma, 0, sizeof(*dma));
917 rc = bus_dmamap_load(dma->tag,
921 bxe_dma_map_addr, /* BLOGD in here */
925 BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc);
926 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
927 bus_dma_tag_destroy(dma->tag);
928 memset(dma, 0, sizeof(*dma));
936 bxe_dma_free(struct bxe_softc *sc,
940 DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL"));
942 bus_dmamap_sync(dma->tag, dma->map,
943 (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE));
944 bus_dmamap_unload(dma->tag, dma->map);
945 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
946 bus_dma_tag_destroy(dma->tag);
949 memset(dma, 0, sizeof(*dma));
953 * These indirect read and write routines are only during init.
954 * The locking is handled by the MCP.
958 bxe_reg_wr_ind(struct bxe_softc *sc,
962 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
963 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4);
964 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
968 bxe_reg_rd_ind(struct bxe_softc *sc,
973 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
974 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4);
975 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
981 bxe_acquire_hw_lock(struct bxe_softc *sc,
984 uint32_t lock_status;
985 uint32_t resource_bit = (1 << resource);
986 int func = SC_FUNC(sc);
987 uint32_t hw_lock_control_reg;
990 /* validate the resource is within range */
991 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
992 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
993 " resource_bit 0x%x\n", resource, resource_bit);
998 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1000 hw_lock_control_reg =
1001 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1004 /* validate the resource is not already taken */
1005 lock_status = REG_RD(sc, hw_lock_control_reg);
1006 if (lock_status & resource_bit) {
1007 BLOGE(sc, "resource (0x%x) in use (status 0x%x bit 0x%x)\n",
1008 resource, lock_status, resource_bit);
1012 /* try every 5ms for 5 seconds */
1013 for (cnt = 0; cnt < 1000; cnt++) {
1014 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
1015 lock_status = REG_RD(sc, hw_lock_control_reg);
1016 if (lock_status & resource_bit) {
1022 BLOGE(sc, "Resource 0x%x resource_bit 0x%x lock timeout!\n",
1023 resource, resource_bit);
1028 bxe_release_hw_lock(struct bxe_softc *sc,
1031 uint32_t lock_status;
1032 uint32_t resource_bit = (1 << resource);
1033 int func = SC_FUNC(sc);
1034 uint32_t hw_lock_control_reg;
1036 /* validate the resource is within range */
1037 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1038 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
1039 " resource_bit 0x%x\n", resource, resource_bit);
1044 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1046 hw_lock_control_reg =
1047 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1050 /* validate the resource is currently taken */
1051 lock_status = REG_RD(sc, hw_lock_control_reg);
1052 if (!(lock_status & resource_bit)) {
1053 BLOGE(sc, "resource (0x%x) not in use (status 0x%x bit 0x%x)\n",
1054 resource, lock_status, resource_bit);
1058 REG_WR(sc, hw_lock_control_reg, resource_bit);
1061 static void bxe_acquire_phy_lock(struct bxe_softc *sc)
1064 bxe_acquire_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1067 static void bxe_release_phy_lock(struct bxe_softc *sc)
1069 bxe_release_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1073 * Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1074 * had we done things the other way around, if two pfs from the same port
1075 * would attempt to access nvram at the same time, we could run into a
1077 * pf A takes the port lock.
1078 * pf B succeeds in taking the same lock since they are from the same port.
1079 * pf A takes the per pf misc lock. Performs eeprom access.
1080 * pf A finishes. Unlocks the per pf misc lock.
1081 * Pf B takes the lock and proceeds to perform it's own access.
1082 * pf A unlocks the per port lock, while pf B is still working (!).
1083 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1084 * access corrupted by pf B).*
1087 bxe_acquire_nvram_lock(struct bxe_softc *sc)
1089 int port = SC_PORT(sc);
1093 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1094 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1096 /* adjust timeout for emulation/FPGA */
1097 count = NVRAM_TIMEOUT_COUNT;
1098 if (CHIP_REV_IS_SLOW(sc)) {
1102 /* request access to nvram interface */
1103 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1104 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1106 for (i = 0; i < count*10; i++) {
1107 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1108 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1115 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1116 BLOGE(sc, "Cannot get access to nvram interface "
1117 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1126 bxe_release_nvram_lock(struct bxe_softc *sc)
1128 int port = SC_PORT(sc);
1132 /* adjust timeout for emulation/FPGA */
1133 count = NVRAM_TIMEOUT_COUNT;
1134 if (CHIP_REV_IS_SLOW(sc)) {
1138 /* relinquish nvram interface */
1139 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1140 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1142 for (i = 0; i < count*10; i++) {
1143 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1144 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1151 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1152 BLOGE(sc, "Cannot free access to nvram interface "
1153 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1158 /* release HW lock: protect against other PFs in PF Direct Assignment */
1159 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1165 bxe_enable_nvram_access(struct bxe_softc *sc)
1169 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1171 /* enable both bits, even on read */
1172 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1173 (val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN));
1177 bxe_disable_nvram_access(struct bxe_softc *sc)
1181 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1183 /* disable both bits, even after read */
1184 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1185 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1186 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1190 bxe_nvram_read_dword(struct bxe_softc *sc,
1198 /* build the command word */
1199 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1201 /* need to clear DONE bit separately */
1202 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1204 /* address of the NVRAM to read from */
1205 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1206 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1208 /* issue a read command */
1209 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1211 /* adjust timeout for emulation/FPGA */
1212 count = NVRAM_TIMEOUT_COUNT;
1213 if (CHIP_REV_IS_SLOW(sc)) {
1217 /* wait for completion */
1220 for (i = 0; i < count; i++) {
1222 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1224 if (val & MCPR_NVM_COMMAND_DONE) {
1225 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
1226 /* we read nvram data in cpu order
1227 * but ethtool sees it as an array of bytes
1228 * converting to big-endian will do the work
1230 *ret_val = htobe32(val);
1237 BLOGE(sc, "nvram read timeout expired "
1238 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1239 offset, cmd_flags, val);
1246 bxe_nvram_read(struct bxe_softc *sc,
1255 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1256 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1261 if ((offset + buf_size) > sc->devinfo.flash_size) {
1262 BLOGE(sc, "Invalid parameter, "
1263 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1264 offset, buf_size, sc->devinfo.flash_size);
1268 /* request access to nvram interface */
1269 rc = bxe_acquire_nvram_lock(sc);
1274 /* enable access to nvram interface */
1275 bxe_enable_nvram_access(sc);
1277 /* read the first word(s) */
1278 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1279 while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
1280 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1281 memcpy(ret_buf, &val, 4);
1283 /* advance to the next dword */
1284 offset += sizeof(uint32_t);
1285 ret_buf += sizeof(uint32_t);
1286 buf_size -= sizeof(uint32_t);
1291 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1292 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1293 memcpy(ret_buf, &val, 4);
1296 /* disable access to nvram interface */
1297 bxe_disable_nvram_access(sc);
1298 bxe_release_nvram_lock(sc);
1304 bxe_nvram_write_dword(struct bxe_softc *sc,
1311 /* build the command word */
1312 cmd_flags |= (MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR);
1314 /* need to clear DONE bit separately */
1315 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1317 /* write the data */
1318 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val);
1320 /* address of the NVRAM to write to */
1321 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1322 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1324 /* issue the write command */
1325 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1327 /* adjust timeout for emulation/FPGA */
1328 count = NVRAM_TIMEOUT_COUNT;
1329 if (CHIP_REV_IS_SLOW(sc)) {
1333 /* wait for completion */
1335 for (i = 0; i < count; i++) {
1337 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1338 if (val & MCPR_NVM_COMMAND_DONE) {
1345 BLOGE(sc, "nvram write timeout expired "
1346 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1347 offset, cmd_flags, val);
1353 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1356 bxe_nvram_write1(struct bxe_softc *sc,
1362 uint32_t align_offset;
1366 if ((offset + buf_size) > sc->devinfo.flash_size) {
1367 BLOGE(sc, "Invalid parameter, "
1368 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1369 offset, buf_size, sc->devinfo.flash_size);
1373 /* request access to nvram interface */
1374 rc = bxe_acquire_nvram_lock(sc);
1379 /* enable access to nvram interface */
1380 bxe_enable_nvram_access(sc);
1382 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1383 align_offset = (offset & ~0x03);
1384 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags);
1387 val &= ~(0xff << BYTE_OFFSET(offset));
1388 val |= (*data_buf << BYTE_OFFSET(offset));
1390 /* nvram data is returned as an array of bytes
1391 * convert it back to cpu order
1395 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags);
1398 /* disable access to nvram interface */
1399 bxe_disable_nvram_access(sc);
1400 bxe_release_nvram_lock(sc);
1406 bxe_nvram_write(struct bxe_softc *sc,
1413 uint32_t written_so_far;
1416 if (buf_size == 1) {
1417 return (bxe_nvram_write1(sc, offset, data_buf, buf_size));
1420 if ((offset & 0x03) || (buf_size & 0x03) /* || (buf_size == 0) */) {
1421 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1426 if (buf_size == 0) {
1427 return (0); /* nothing to do */
1430 if ((offset + buf_size) > sc->devinfo.flash_size) {
1431 BLOGE(sc, "Invalid parameter, "
1432 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1433 offset, buf_size, sc->devinfo.flash_size);
1437 /* request access to nvram interface */
1438 rc = bxe_acquire_nvram_lock(sc);
1443 /* enable access to nvram interface */
1444 bxe_enable_nvram_access(sc);
1447 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1448 while ((written_so_far < buf_size) && (rc == 0)) {
1449 if (written_so_far == (buf_size - sizeof(uint32_t))) {
1450 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1451 } else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) {
1452 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1453 } else if ((offset % NVRAM_PAGE_SIZE) == 0) {
1454 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1457 memcpy(&val, data_buf, 4);
1459 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags);
1461 /* advance to the next dword */
1462 offset += sizeof(uint32_t);
1463 data_buf += sizeof(uint32_t);
1464 written_so_far += sizeof(uint32_t);
1468 /* disable access to nvram interface */
1469 bxe_disable_nvram_access(sc);
1470 bxe_release_nvram_lock(sc);
1475 /* copy command into DMAE command memory and set DMAE command Go */
1477 bxe_post_dmae(struct bxe_softc *sc,
1478 struct dmae_cmd *dmae,
1481 uint32_t cmd_offset;
1484 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_cmd) * idx));
1485 for (i = 0; i < ((sizeof(struct dmae_cmd) / 4)); i++) {
1486 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1489 REG_WR(sc, dmae_reg_go_c[idx], 1);
1493 bxe_dmae_opcode_add_comp(uint32_t opcode,
1496 return (opcode | ((comp_type << DMAE_CMD_C_DST_SHIFT) |
1497 DMAE_CMD_C_TYPE_ENABLE));
1501 bxe_dmae_opcode_clr_src_reset(uint32_t opcode)
1503 return (opcode & ~DMAE_CMD_SRC_RESET);
1507 bxe_dmae_opcode(struct bxe_softc *sc,
1513 uint32_t opcode = 0;
1515 opcode |= ((src_type << DMAE_CMD_SRC_SHIFT) |
1516 (dst_type << DMAE_CMD_DST_SHIFT));
1518 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
1520 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
1522 opcode |= ((SC_VN(sc) << DMAE_CMD_E1HVN_SHIFT) |
1523 (SC_VN(sc) << DMAE_CMD_DST_VN_SHIFT));
1525 opcode |= (DMAE_COM_SET_ERR << DMAE_CMD_ERR_POLICY_SHIFT);
1528 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
1530 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
1534 opcode = bxe_dmae_opcode_add_comp(opcode, comp_type);
1541 bxe_prep_dmae_with_comp(struct bxe_softc *sc,
1542 struct dmae_cmd *dmae,
1546 memset(dmae, 0, sizeof(struct dmae_cmd));
1548 /* set the opcode */
1549 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type,
1550 TRUE, DMAE_COMP_PCI);
1552 /* fill in the completion parameters */
1553 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
1554 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
1555 dmae->comp_val = DMAE_COMP_VAL;
1558 /* issue a DMAE command over the init channel and wait for completion */
1560 bxe_issue_dmae_with_comp(struct bxe_softc *sc,
1561 struct dmae_cmd *dmae)
1563 uint32_t *wb_comp = BXE_SP(sc, wb_comp);
1564 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
1568 /* reset completion */
1571 /* post the command on the channel used for initializations */
1572 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
1574 /* wait for completion */
1577 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
1579 (sc->recovery_state != BXE_RECOVERY_DONE &&
1580 sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) {
1581 BLOGE(sc, "DMAE timeout! *wb_comp 0x%x recovery_state 0x%x\n",
1582 *wb_comp, sc->recovery_state);
1583 BXE_DMAE_UNLOCK(sc);
1584 return (DMAE_TIMEOUT);
1591 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
1592 BLOGE(sc, "DMAE PCI error! *wb_comp 0x%x recovery_state 0x%x\n",
1593 *wb_comp, sc->recovery_state);
1594 BXE_DMAE_UNLOCK(sc);
1595 return (DMAE_PCI_ERROR);
1598 BXE_DMAE_UNLOCK(sc);
1603 bxe_read_dmae(struct bxe_softc *sc,
1607 struct dmae_cmd dmae;
1611 DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32));
1613 if (!sc->dmae_ready) {
1614 data = BXE_SP(sc, wb_data[0]);
1616 for (i = 0; i < len32; i++) {
1617 data[i] = (CHIP_IS_E1(sc)) ?
1618 bxe_reg_rd_ind(sc, (src_addr + (i * 4))) :
1619 REG_RD(sc, (src_addr + (i * 4)));
1625 /* set opcode and fixed command fields */
1626 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
1628 /* fill in addresses and len */
1629 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
1630 dmae.src_addr_hi = 0;
1631 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
1632 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
1635 /* issue the command and wait for completion */
1636 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1637 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1642 bxe_write_dmae(struct bxe_softc *sc,
1643 bus_addr_t dma_addr,
1647 struct dmae_cmd dmae;
1650 if (!sc->dmae_ready) {
1651 DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32));
1653 if (CHIP_IS_E1(sc)) {
1654 ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1656 ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1662 /* set opcode and fixed command fields */
1663 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
1665 /* fill in addresses and len */
1666 dmae.src_addr_lo = U64_LO(dma_addr);
1667 dmae.src_addr_hi = U64_HI(dma_addr);
1668 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
1669 dmae.dst_addr_hi = 0;
1672 /* issue the command and wait for completion */
1673 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1674 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1679 bxe_write_dmae_phys_len(struct bxe_softc *sc,
1680 bus_addr_t phys_addr,
1684 int dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
1687 while (len > dmae_wr_max) {
1689 (phys_addr + offset), /* src DMA address */
1690 (addr + offset), /* dst GRC address */
1692 offset += (dmae_wr_max * 4);
1697 (phys_addr + offset), /* src DMA address */
1698 (addr + offset), /* dst GRC address */
1703 bxe_set_ctx_validation(struct bxe_softc *sc,
1704 struct eth_context *cxt,
1707 /* ustorm cxt validation */
1708 cxt->ustorm_ag_context.cdu_usage =
1709 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1710 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
1711 /* xcontext validation */
1712 cxt->xstorm_ag_context.cdu_reserved =
1713 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1714 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
1718 bxe_storm_memset_hc_timeout(struct bxe_softc *sc,
1725 (BAR_CSTRORM_INTMEM +
1726 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
1728 REG_WR8(sc, addr, ticks);
1731 "port %d fw_sb_id %d sb_index %d ticks %d\n",
1732 port, fw_sb_id, sb_index, ticks);
1736 bxe_storm_memset_hc_disable(struct bxe_softc *sc,
1742 uint32_t enable_flag =
1743 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
1745 (BAR_CSTRORM_INTMEM +
1746 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
1750 flags = REG_RD8(sc, addr);
1751 flags &= ~HC_INDEX_DATA_HC_ENABLED;
1752 flags |= enable_flag;
1753 REG_WR8(sc, addr, flags);
1756 "port %d fw_sb_id %d sb_index %d disable %d\n",
1757 port, fw_sb_id, sb_index, disable);
1761 bxe_update_coalesce_sb_index(struct bxe_softc *sc,
1767 int port = SC_PORT(sc);
1768 uint8_t ticks = (usec / 4); /* XXX ??? */
1770 bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks);
1772 disable = (disable) ? 1 : ((usec) ? 0 : 1);
1773 bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable);
1777 elink_cb_udelay(struct bxe_softc *sc,
1784 elink_cb_reg_read(struct bxe_softc *sc,
1787 return (REG_RD(sc, reg_addr));
1791 elink_cb_reg_write(struct bxe_softc *sc,
1795 REG_WR(sc, reg_addr, val);
1799 elink_cb_reg_wb_write(struct bxe_softc *sc,
1804 REG_WR_DMAE(sc, offset, wb_write, len);
1808 elink_cb_reg_wb_read(struct bxe_softc *sc,
1813 REG_RD_DMAE(sc, offset, wb_write, len);
1817 elink_cb_path_id(struct bxe_softc *sc)
1819 return (SC_PATH(sc));
1823 elink_cb_event_log(struct bxe_softc *sc,
1824 const elink_log_id_t elink_log_id,
1828 BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id);
1832 bxe_set_spio(struct bxe_softc *sc,
1838 /* Only 2 SPIOs are configurable */
1839 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
1840 BLOGE(sc, "Invalid SPIO 0x%x mode 0x%x\n", spio, mode);
1844 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1846 /* read SPIO and mask except the float bits */
1847 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
1850 case MISC_SPIO_OUTPUT_LOW:
1851 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio);
1852 /* clear FLOAT and set CLR */
1853 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1854 spio_reg |= (spio << MISC_SPIO_CLR_POS);
1857 case MISC_SPIO_OUTPUT_HIGH:
1858 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio);
1859 /* clear FLOAT and set SET */
1860 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1861 spio_reg |= (spio << MISC_SPIO_SET_POS);
1864 case MISC_SPIO_INPUT_HI_Z:
1865 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio);
1867 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
1874 REG_WR(sc, MISC_REG_SPIO, spio_reg);
1875 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1881 bxe_gpio_read(struct bxe_softc *sc,
1885 /* The GPIO should be swapped if swap register is set and active */
1886 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1887 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1888 int gpio_shift = (gpio_num +
1889 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
1890 uint32_t gpio_mask = (1 << gpio_shift);
1893 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1894 BLOGE(sc, "Invalid GPIO %d port 0x%x gpio_port %d gpio_shift %d"
1895 " gpio_mask 0x%x\n", gpio_num, port, gpio_port, gpio_shift,
1900 /* read GPIO value */
1901 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
1903 /* get the requested pin value */
1904 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
1908 bxe_gpio_write(struct bxe_softc *sc,
1913 /* The GPIO should be swapped if swap register is set and active */
1914 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1915 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1916 int gpio_shift = (gpio_num +
1917 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
1918 uint32_t gpio_mask = (1 << gpio_shift);
1921 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1922 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
1923 " gpio_shift %d gpio_mask 0x%x\n",
1924 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
1928 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
1930 /* read GPIO and mask except the float bits */
1931 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1934 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1936 "Set GPIO %d (shift %d) -> output low\n",
1937 gpio_num, gpio_shift);
1938 /* clear FLOAT and set CLR */
1939 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1940 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1943 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1945 "Set GPIO %d (shift %d) -> output high\n",
1946 gpio_num, gpio_shift);
1947 /* clear FLOAT and set SET */
1948 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1949 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1952 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1954 "Set GPIO %d (shift %d) -> input\n",
1955 gpio_num, gpio_shift);
1957 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1964 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
1965 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
1971 bxe_gpio_mult_write(struct bxe_softc *sc,
1977 /* any port swapping should be handled by caller */
1979 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
1981 /* read GPIO and mask except the float bits */
1982 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
1983 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1984 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1985 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1988 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1989 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins);
1991 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1994 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1995 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins);
1997 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2000 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2001 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins);
2003 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2007 BLOGE(sc, "Invalid GPIO mode assignment pins 0x%x mode 0x%x"
2008 " gpio_reg 0x%x\n", pins, mode, gpio_reg);
2009 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2013 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
2014 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2020 bxe_gpio_int_write(struct bxe_softc *sc,
2025 /* The GPIO should be swapped if swap register is set and active */
2026 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
2027 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
2028 int gpio_shift = (gpio_num +
2029 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
2030 uint32_t gpio_mask = (1 << gpio_shift);
2033 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2034 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
2035 " gpio_shift %d gpio_mask 0x%x\n",
2036 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
2040 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2043 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
2046 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2048 "Clear GPIO INT %d (shift %d) -> output low\n",
2049 gpio_num, gpio_shift);
2050 /* clear SET and set CLR */
2051 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2052 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2055 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2057 "Set GPIO INT %d (shift %d) -> output high\n",
2058 gpio_num, gpio_shift);
2059 /* clear CLR and set SET */
2060 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2061 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2068 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
2069 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2075 elink_cb_gpio_read(struct bxe_softc *sc,
2079 return (bxe_gpio_read(sc, gpio_num, port));
2083 elink_cb_gpio_write(struct bxe_softc *sc,
2085 uint8_t mode, /* 0=low 1=high */
2088 return (bxe_gpio_write(sc, gpio_num, mode, port));
2092 elink_cb_gpio_mult_write(struct bxe_softc *sc,
2094 uint8_t mode) /* 0=low 1=high */
2096 return (bxe_gpio_mult_write(sc, pins, mode));
2100 elink_cb_gpio_int_write(struct bxe_softc *sc,
2102 uint8_t mode, /* 0=low 1=high */
2105 return (bxe_gpio_int_write(sc, gpio_num, mode, port));
2109 elink_cb_notify_link_changed(struct bxe_softc *sc)
2111 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
2112 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
2115 /* send the MCP a request, block until there is a reply */
2117 elink_cb_fw_command(struct bxe_softc *sc,
2121 int mb_idx = SC_FW_MB_IDX(sc);
2125 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
2130 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
2131 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
2134 "wrote command 0x%08x to FW MB param 0x%08x\n",
2135 (command | seq), param);
2137 /* Let the FW do it's magic. GIve it up to 5 seconds... */
2139 DELAY(delay * 1000);
2140 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
2141 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2144 "[after %d ms] read 0x%x seq 0x%x from FW MB\n",
2145 cnt*delay, rc, seq);
2147 /* is this a reply to our command? */
2148 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
2149 rc &= FW_MSG_CODE_MASK;
2152 BLOGE(sc, "FW failed to respond!\n");
2153 // XXX bxe_fw_dump(sc);
2157 BXE_FWMB_UNLOCK(sc);
2162 bxe_fw_command(struct bxe_softc *sc,
2166 return (elink_cb_fw_command(sc, command, param));
2170 __storm_memset_dma_mapping(struct bxe_softc *sc,
2174 REG_WR(sc, addr, U64_LO(mapping));
2175 REG_WR(sc, (addr + 4), U64_HI(mapping));
2179 storm_memset_spq_addr(struct bxe_softc *sc,
2183 uint32_t addr = (XSEM_REG_FAST_MEMORY +
2184 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
2185 __storm_memset_dma_mapping(sc, addr, mapping);
2189 storm_memset_vf_to_pf(struct bxe_softc *sc,
2193 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2194 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2195 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2196 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2200 storm_memset_func_en(struct bxe_softc *sc,
2204 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2205 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2206 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2207 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2211 storm_memset_eq_data(struct bxe_softc *sc,
2212 struct event_ring_data *eq_data,
2218 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
2219 size = sizeof(struct event_ring_data);
2220 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data);
2224 storm_memset_eq_prod(struct bxe_softc *sc,
2228 uint32_t addr = (BAR_CSTRORM_INTMEM +
2229 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
2230 REG_WR16(sc, addr, eq_prod);
2234 * Post a slowpath command.
2236 * A slowpath command is used to propogate a configuration change through
2237 * the controller in a controlled manner, allowing each STORM processor and
2238 * other H/W blocks to phase in the change. The commands sent on the
2239 * slowpath are referred to as ramrods. Depending on the ramrod used the
2240 * completion of the ramrod will occur in different ways. Here's a
2241 * breakdown of ramrods and how they complete:
2243 * RAMROD_CMD_ID_ETH_PORT_SETUP
2244 * Used to setup the leading connection on a port. Completes on the
2245 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
2247 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
2248 * Used to setup an additional connection on a port. Completes on the
2249 * RCQ of the multi-queue/RSS connection being initialized.
2251 * RAMROD_CMD_ID_ETH_STAT_QUERY
2252 * Used to force the storm processors to update the statistics database
2253 * in host memory. This ramrod is send on the leading connection CID and
2254 * completes as an index increment of the CSTORM on the default status
2257 * RAMROD_CMD_ID_ETH_UPDATE
2258 * Used to update the state of the leading connection, usually to udpate
2259 * the RSS indirection table. Completes on the RCQ of the leading
2260 * connection. (Not currently used under FreeBSD until OS support becomes
2263 * RAMROD_CMD_ID_ETH_HALT
2264 * Used when tearing down a connection prior to driver unload. Completes
2265 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
2266 * use this on the leading connection.
2268 * RAMROD_CMD_ID_ETH_SET_MAC
2269 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
2270 * the RCQ of the leading connection.
2272 * RAMROD_CMD_ID_ETH_CFC_DEL
2273 * Used when tearing down a conneciton prior to driver unload. Completes
2274 * on the RCQ of the leading connection (since the current connection
2275 * has been completely removed from controller memory).
2277 * RAMROD_CMD_ID_ETH_PORT_DEL
2278 * Used to tear down the leading connection prior to driver unload,
2279 * typically fp[0]. Completes as an index increment of the CSTORM on the
2280 * default status block.
2282 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
2283 * Used for connection offload. Completes on the RCQ of the multi-queue
2284 * RSS connection that is being offloaded. (Not currently used under
2287 * There can only be one command pending per function.
2290 * 0 = Success, !0 = Failure.
2293 /* must be called under the spq lock */
2295 struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc)
2297 struct eth_spe *next_spe = sc->spq_prod_bd;
2299 if (sc->spq_prod_bd == sc->spq_last_bd) {
2300 /* wrap back to the first eth_spq */
2301 sc->spq_prod_bd = sc->spq;
2302 sc->spq_prod_idx = 0;
2311 /* must be called under the spq lock */
2313 void bxe_sp_prod_update(struct bxe_softc *sc)
2315 int func = SC_FUNC(sc);
2318 * Make sure that BD data is updated before writing the producer.
2319 * BD data is written to the memory, the producer is read from the
2320 * memory, thus we need a full memory barrier to ensure the ordering.
2324 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
2327 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
2328 BUS_SPACE_BARRIER_WRITE);
2332 * bxe_is_contextless_ramrod - check if the current command ends on EQ
2334 * @cmd: command to check
2335 * @cmd_type: command type
2338 int bxe_is_contextless_ramrod(int cmd,
2341 if ((cmd_type == NONE_CONNECTION_TYPE) ||
2342 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
2343 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
2344 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
2345 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
2346 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
2347 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
2355 * bxe_sp_post - place a single command on an SP ring
2357 * @sc: driver handle
2358 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
2359 * @cid: SW CID the command is related to
2360 * @data_hi: command private data address (high 32 bits)
2361 * @data_lo: command private data address (low 32 bits)
2362 * @cmd_type: command type (e.g. NONE, ETH)
2364 * SP data is handled as if it's always an address pair, thus data fields are
2365 * not swapped to little endian in upper functions. Instead this function swaps
2366 * data as if it's two uint32 fields.
2369 bxe_sp_post(struct bxe_softc *sc,
2376 struct eth_spe *spe;
2380 common = bxe_is_contextless_ramrod(command, cmd_type);
2385 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
2386 BLOGE(sc, "EQ ring is full!\n");
2391 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
2392 BLOGE(sc, "SPQ ring is full!\n");
2398 spe = bxe_sp_get_next(sc);
2400 /* CID needs port number to be encoded int it */
2401 spe->hdr.conn_and_cmd_data =
2402 htole32((command << SPE_HDR_T_CMD_ID_SHIFT) | HW_CID(sc, cid));
2404 type = (cmd_type << SPE_HDR_T_CONN_TYPE_SHIFT) & SPE_HDR_T_CONN_TYPE;
2406 /* TBD: Check if it works for VFs */
2407 type |= ((SC_FUNC(sc) << SPE_HDR_T_FUNCTION_ID_SHIFT) &
2408 SPE_HDR_T_FUNCTION_ID);
2410 spe->hdr.type = htole16(type);
2412 spe->data.update_data_addr.hi = htole32(data_hi);
2413 spe->data.update_data_addr.lo = htole32(data_lo);
2416 * It's ok if the actual decrement is issued towards the memory
2417 * somewhere between the lock and unlock. Thus no more explict
2418 * memory barrier is needed.
2421 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
2423 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
2426 BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr);
2427 BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n",
2428 BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata));
2430 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n",
2432 (uint32_t)U64_HI(sc->spq_dma.paddr),
2433 (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq),
2440 atomic_load_acq_long(&sc->cq_spq_left),
2441 atomic_load_acq_long(&sc->eq_spq_left));
2443 bxe_sp_prod_update(sc);
2450 * bxe_debug_print_ind_table - prints the indirection table configuration.
2452 * @sc: driver hanlde
2453 * @p: pointer to rss configuration
2457 * FreeBSD Device probe function.
2459 * Compares the device found to the driver's list of supported devices and
2460 * reports back to the bsd loader whether this is the right driver for the device.
2461 * This is the driver entry function called from the "kldload" command.
2464 * BUS_PROBE_DEFAULT on success, positive value on failure.
2467 bxe_probe(device_t dev)
2469 struct bxe_softc *sc;
2470 struct bxe_device_type *t;
2472 uint16_t did, sdid, svid, vid;
2474 /* Find our device structure */
2475 sc = device_get_softc(dev);
2479 /* Get the data for the device to be probed. */
2480 vid = pci_get_vendor(dev);
2481 did = pci_get_device(dev);
2482 svid = pci_get_subvendor(dev);
2483 sdid = pci_get_subdevice(dev);
2486 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
2487 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
2489 /* Look through the list of known devices for a match. */
2490 while (t->bxe_name != NULL) {
2491 if ((vid == t->bxe_vid) && (did == t->bxe_did) &&
2492 ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) &&
2493 ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) {
2494 descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
2495 if (descbuf == NULL)
2498 /* Print out the device identity. */
2499 snprintf(descbuf, BXE_DEVDESC_MAX,
2500 "%s (%c%d) BXE v:%s\n", t->bxe_name,
2501 (((pci_read_config(dev, PCIR_REVID, 4) &
2503 (pci_read_config(dev, PCIR_REVID, 4) & 0xf),
2504 BXE_DRIVER_VERSION);
2506 device_set_desc_copy(dev, descbuf);
2507 free(descbuf, M_TEMP);
2508 return (BUS_PROBE_DEFAULT);
2517 bxe_init_mutexes(struct bxe_softc *sc)
2519 #ifdef BXE_CORE_LOCK_SX
2520 snprintf(sc->core_sx_name, sizeof(sc->core_sx_name),
2521 "bxe%d_core_lock", sc->unit);
2522 sx_init(&sc->core_sx, sc->core_sx_name);
2524 snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name),
2525 "bxe%d_core_lock", sc->unit);
2526 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF);
2529 snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name),
2530 "bxe%d_sp_lock", sc->unit);
2531 mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF);
2533 snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name),
2534 "bxe%d_dmae_lock", sc->unit);
2535 mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF);
2537 snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name),
2538 "bxe%d_phy_lock", sc->unit);
2539 mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF);
2541 snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name),
2542 "bxe%d_fwmb_lock", sc->unit);
2543 mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF);
2545 snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name),
2546 "bxe%d_print_lock", sc->unit);
2547 mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF);
2549 snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name),
2550 "bxe%d_stats_lock", sc->unit);
2551 mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF);
2553 snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name),
2554 "bxe%d_mcast_lock", sc->unit);
2555 mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF);
2559 bxe_release_mutexes(struct bxe_softc *sc)
2561 #ifdef BXE_CORE_LOCK_SX
2562 sx_destroy(&sc->core_sx);
2564 if (mtx_initialized(&sc->core_mtx)) {
2565 mtx_destroy(&sc->core_mtx);
2569 if (mtx_initialized(&sc->sp_mtx)) {
2570 mtx_destroy(&sc->sp_mtx);
2573 if (mtx_initialized(&sc->dmae_mtx)) {
2574 mtx_destroy(&sc->dmae_mtx);
2577 if (mtx_initialized(&sc->port.phy_mtx)) {
2578 mtx_destroy(&sc->port.phy_mtx);
2581 if (mtx_initialized(&sc->fwmb_mtx)) {
2582 mtx_destroy(&sc->fwmb_mtx);
2585 if (mtx_initialized(&sc->print_mtx)) {
2586 mtx_destroy(&sc->print_mtx);
2589 if (mtx_initialized(&sc->stats_mtx)) {
2590 mtx_destroy(&sc->stats_mtx);
2593 if (mtx_initialized(&sc->mcast_mtx)) {
2594 mtx_destroy(&sc->mcast_mtx);
2599 bxe_tx_disable(struct bxe_softc* sc)
2601 struct ifnet *ifp = sc->ifnet;
2603 /* tell the stack the driver is stopped and TX queue is full */
2605 ifp->if_drv_flags = 0;
2610 bxe_drv_pulse(struct bxe_softc *sc)
2612 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
2613 sc->fw_drv_pulse_wr_seq);
2616 static inline uint16_t
2617 bxe_tx_avail(struct bxe_softc *sc,
2618 struct bxe_fastpath *fp)
2624 prod = fp->tx_bd_prod;
2625 cons = fp->tx_bd_cons;
2627 used = SUB_S16(prod, cons);
2629 return (int16_t)(sc->tx_ring_size) - used;
2633 bxe_tx_queue_has_work(struct bxe_fastpath *fp)
2637 mb(); /* status block fields can change */
2638 hw_cons = le16toh(*fp->tx_cons_sb);
2639 return (hw_cons != fp->tx_pkt_cons);
2642 static inline uint8_t
2643 bxe_has_tx_work(struct bxe_fastpath *fp)
2645 /* expand this for multi-cos if ever supported */
2646 return (bxe_tx_queue_has_work(fp)) ? TRUE : FALSE;
2650 bxe_has_rx_work(struct bxe_fastpath *fp)
2652 uint16_t rx_cq_cons_sb;
2654 mb(); /* status block fields can change */
2655 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
2656 if ((rx_cq_cons_sb & RCQ_MAX) == RCQ_MAX)
2658 return (fp->rx_cq_cons != rx_cq_cons_sb);
2662 bxe_sp_event(struct bxe_softc *sc,
2663 struct bxe_fastpath *fp,
2664 union eth_rx_cqe *rr_cqe)
2666 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2667 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2668 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
2669 struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
2671 BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n",
2672 fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type);
2675 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
2676 BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid);
2677 drv_cmd = ECORE_Q_CMD_UPDATE;
2680 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
2681 BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid);
2682 drv_cmd = ECORE_Q_CMD_SETUP;
2685 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
2686 BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
2687 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
2690 case (RAMROD_CMD_ID_ETH_HALT):
2691 BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid);
2692 drv_cmd = ECORE_Q_CMD_HALT;
2695 case (RAMROD_CMD_ID_ETH_TERMINATE):
2696 BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid);
2697 drv_cmd = ECORE_Q_CMD_TERMINATE;
2700 case (RAMROD_CMD_ID_ETH_EMPTY):
2701 BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid);
2702 drv_cmd = ECORE_Q_CMD_EMPTY;
2706 BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n",
2707 command, fp->index);
2711 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
2712 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
2714 * q_obj->complete_cmd() failure means that this was
2715 * an unexpected completion.
2717 * In this case we don't want to increase the sc->spq_left
2718 * because apparently we haven't sent this command the first
2721 // bxe_panic(sc, ("Unexpected SP completion\n"));
2725 atomic_add_acq_long(&sc->cq_spq_left, 1);
2727 BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n",
2728 atomic_load_acq_long(&sc->cq_spq_left));
2732 * The current mbuf is part of an aggregation. Move the mbuf into the TPA
2733 * aggregation queue, put an empty mbuf back onto the receive chain, and mark
2734 * the current aggregation queue as in-progress.
2737 bxe_tpa_start(struct bxe_softc *sc,
2738 struct bxe_fastpath *fp,
2742 struct eth_fast_path_rx_cqe *cqe)
2744 struct bxe_sw_rx_bd tmp_bd;
2745 struct bxe_sw_rx_bd *rx_buf;
2746 struct eth_rx_bd *rx_bd;
2748 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
2751 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START "
2752 "cons=%d prod=%d\n",
2753 fp->index, queue, cons, prod);
2755 max_agg_queues = MAX_AGG_QS(sc);
2757 KASSERT((queue < max_agg_queues),
2758 ("fp[%02d] invalid aggr queue (%d >= %d)!",
2759 fp->index, queue, max_agg_queues));
2761 KASSERT((tpa_info->state == BXE_TPA_STATE_STOP),
2762 ("fp[%02d].tpa[%02d] starting aggr on queue not stopped!",
2765 /* copy the existing mbuf and mapping from the TPA pool */
2766 tmp_bd = tpa_info->bd;
2768 if (tmp_bd.m == NULL) {
2771 tmp = (uint32_t *)cqe;
2773 BLOGE(sc, "fp[%02d].tpa[%02d] cons[%d] prod[%d]mbuf not allocated!\n",
2774 fp->index, queue, cons, prod);
2775 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2776 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2778 /* XXX Error handling? */
2782 /* change the TPA queue to the start state */
2783 tpa_info->state = BXE_TPA_STATE_START;
2784 tpa_info->placement_offset = cqe->placement_offset;
2785 tpa_info->parsing_flags = le16toh(cqe->pars_flags.flags);
2786 tpa_info->vlan_tag = le16toh(cqe->vlan_tag);
2787 tpa_info->len_on_bd = le16toh(cqe->len_on_bd);
2789 fp->rx_tpa_queue_used |= (1 << queue);
2792 * If all the buffer descriptors are filled with mbufs then fill in
2793 * the current consumer index with a new BD. Else if a maximum Rx
2794 * buffer limit is imposed then fill in the next producer index.
2796 index = (sc->max_rx_bufs != RX_BD_USABLE) ?
2799 /* move the received mbuf and mapping to TPA pool */
2800 tpa_info->bd = fp->rx_mbuf_chain[cons];
2802 /* release any existing RX BD mbuf mappings */
2803 if (cons != index) {
2804 rx_buf = &fp->rx_mbuf_chain[cons];
2806 if (rx_buf->m_map != NULL) {
2807 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
2808 BUS_DMASYNC_POSTREAD);
2809 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
2813 * We get here when the maximum number of rx buffers is less than
2814 * RX_BD_USABLE. The mbuf is already saved above so it's OK to NULL
2815 * it out here without concern of a memory leak.
2817 fp->rx_mbuf_chain[cons].m = NULL;
2820 /* update the Rx SW BD with the mbuf info from the TPA pool */
2821 fp->rx_mbuf_chain[index] = tmp_bd;
2823 /* update the Rx BD with the empty mbuf phys address from the TPA pool */
2824 rx_bd = &fp->rx_chain[index];
2825 rx_bd->addr_hi = htole32(U64_HI(tpa_info->seg.ds_addr));
2826 rx_bd->addr_lo = htole32(U64_LO(tpa_info->seg.ds_addr));
2830 * When a TPA aggregation is completed, loop through the individual mbufs
2831 * of the aggregation, combining them into a single mbuf which will be sent
2832 * up the stack. Refill all freed SGEs with mbufs as we go along.
2835 bxe_fill_frag_mbuf(struct bxe_softc *sc,
2836 struct bxe_fastpath *fp,
2837 struct bxe_sw_tpa_info *tpa_info,
2841 struct eth_end_agg_rx_cqe *cqe,
2844 struct mbuf *m_frag;
2845 uint32_t frag_len, frag_size, i;
2850 frag_size = le16toh(cqe->pkt_len) - tpa_info->len_on_bd;
2853 "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n",
2854 fp->index, queue, tpa_info->len_on_bd, frag_size, pages);
2856 /* make sure the aggregated frame is not too big to handle */
2857 if (pages > 8 * PAGES_PER_SGE) {
2859 uint32_t *tmp = (uint32_t *)cqe;
2861 BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! "
2862 "pkt_len=%d len_on_bd=%d frag_size=%d\n",
2863 fp->index, cqe_idx, pages, le16toh(cqe->pkt_len),
2864 tpa_info->len_on_bd, frag_size);
2866 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2867 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2869 bxe_panic(sc, ("sge page count error\n"));
2874 * Scan through the scatter gather list pulling individual mbufs into a
2875 * single mbuf for the host stack.
2877 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
2878 sge_idx = RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[j]));
2881 * Firmware gives the indices of the SGE as if the ring is an array
2882 * (meaning that the "next" element will consume 2 indices).
2884 frag_len = min(frag_size, (uint32_t)(SGE_PAGES));
2886 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d "
2887 "sge_idx=%d frag_size=%d frag_len=%d\n",
2888 fp->index, queue, i, j, sge_idx, frag_size, frag_len);
2890 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
2892 /* allocate a new mbuf for the SGE */
2893 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
2895 /* Leave all remaining SGEs in the ring! */
2899 /* update the fragment length */
2900 m_frag->m_len = frag_len;
2902 /* concatenate the fragment to the head mbuf */
2904 fp->eth_q_stats.mbuf_alloc_sge--;
2906 /* update the TPA mbuf size and remaining fragment size */
2907 m->m_pkthdr.len += frag_len;
2908 frag_size -= frag_len;
2912 "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n",
2913 fp->index, queue, frag_size);
2919 bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp)
2923 for (i = 1; i <= RX_SGE_NUM_PAGES; i++) {
2924 int idx = RX_SGE_TOTAL_PER_PAGE * i - 1;
2926 for (j = 0; j < 2; j++) {
2927 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
2934 bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp)
2936 /* set the mask to all 1's, it's faster to compare to 0 than to 0xf's */
2937 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
2940 * Clear the two last indices in the page to 1. These are the indices that
2941 * correspond to the "next" element, hence will never be indicated and
2942 * should be removed from the calculations.
2944 bxe_clear_sge_mask_next_elems(fp);
2948 bxe_update_last_max_sge(struct bxe_fastpath *fp,
2951 uint16_t last_max = fp->last_max_sge;
2953 if (SUB_S16(idx, last_max) > 0) {
2954 fp->last_max_sge = idx;
2959 bxe_update_sge_prod(struct bxe_softc *sc,
2960 struct bxe_fastpath *fp,
2962 union eth_sgl_or_raw_data *cqe)
2964 uint16_t last_max, last_elem, first_elem;
2972 /* first mark all used pages */
2973 for (i = 0; i < sge_len; i++) {
2974 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
2975 RX_SGE(le16toh(cqe->sgl[i])));
2979 "fp[%02d] fp_cqe->sgl[%d] = %d\n",
2980 fp->index, sge_len - 1,
2981 le16toh(cqe->sgl[sge_len - 1]));
2983 /* assume that the last SGE index is the biggest */
2984 bxe_update_last_max_sge(fp,
2985 le16toh(cqe->sgl[sge_len - 1]));
2987 last_max = RX_SGE(fp->last_max_sge);
2988 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
2989 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
2991 /* if ring is not full */
2992 if (last_elem + 1 != first_elem) {
2996 /* now update the prod */
2997 for (i = first_elem; i != last_elem; i = RX_SGE_NEXT_MASK_ELEM(i)) {
2998 if (__predict_true(fp->sge_mask[i])) {
3002 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
3003 delta += BIT_VEC64_ELEM_SZ;
3007 fp->rx_sge_prod += delta;
3008 /* clear page-end entries */
3009 bxe_clear_sge_mask_next_elems(fp);
3013 "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n",
3014 fp->index, fp->last_max_sge, fp->rx_sge_prod);
3018 * The aggregation on the current TPA queue has completed. Pull the individual
3019 * mbuf fragments together into a single mbuf, perform all necessary checksum
3020 * calculations, and send the resuting mbuf to the stack.
3023 bxe_tpa_stop(struct bxe_softc *sc,
3024 struct bxe_fastpath *fp,
3025 struct bxe_sw_tpa_info *tpa_info,
3028 struct eth_end_agg_rx_cqe *cqe,
3031 struct ifnet *ifp = sc->ifnet;
3036 "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n",
3037 fp->index, queue, tpa_info->placement_offset,
3038 le16toh(cqe->pkt_len), pages, tpa_info->vlan_tag);
3042 /* allocate a replacement before modifying existing mbuf */
3043 rc = bxe_alloc_rx_tpa_mbuf(fp, queue);
3045 /* drop the frame and log an error */
3046 fp->eth_q_stats.rx_soft_errors++;
3047 goto bxe_tpa_stop_exit;
3050 /* we have a replacement, fixup the current mbuf */
3051 m_adj(m, tpa_info->placement_offset);
3052 m->m_pkthdr.len = m->m_len = tpa_info->len_on_bd;
3054 /* mark the checksums valid (taken care of by the firmware) */
3055 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3056 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3057 m->m_pkthdr.csum_data = 0xffff;
3058 m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED |
3063 /* aggregate all of the SGEs into a single mbuf */
3064 rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx);
3066 /* drop the packet and log an error */
3067 fp->eth_q_stats.rx_soft_errors++;
3070 if (tpa_info->parsing_flags & PARSING_FLAGS_INNER_VLAN_EXIST) {
3071 m->m_pkthdr.ether_vtag = tpa_info->vlan_tag;
3072 m->m_flags |= M_VLANTAG;
3075 /* assign packet to this interface interface */
3076 m->m_pkthdr.rcvif = ifp;
3078 #if __FreeBSD_version >= 800000
3079 /* specify what RSS queue was used for this flow */
3080 m->m_pkthdr.flowid = fp->index;
3085 fp->eth_q_stats.rx_tpa_pkts++;
3087 /* pass the frame to the stack */
3088 (*ifp->if_input)(ifp, m);
3091 /* we passed an mbuf up the stack or dropped the frame */
3092 fp->eth_q_stats.mbuf_alloc_tpa--;
3096 fp->rx_tpa_info[queue].state = BXE_TPA_STATE_STOP;
3097 fp->rx_tpa_queue_used &= ~(1 << queue);
3102 struct bxe_fastpath *fp,
3106 struct eth_fast_path_rx_cqe *cqe_fp)
3108 struct mbuf *m_frag;
3109 uint16_t frags, frag_len;
3110 uint16_t sge_idx = 0;
3115 /* adjust the mbuf */
3118 frag_size = len - lenonbd;
3119 frags = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3121 for (i = 0, j = 0; i < frags; i += PAGES_PER_SGE, j++) {
3122 sge_idx = RX_SGE(le16toh(cqe_fp->sgl_or_raw_data.sgl[j]));
3124 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
3125 frag_len = min(frag_size, (uint32_t)(SGE_PAGE_SIZE));
3126 m_frag->m_len = frag_len;
3128 /* allocate a new mbuf for the SGE */
3129 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
3131 /* Leave all remaining SGEs in the ring! */
3134 fp->eth_q_stats.mbuf_alloc_sge--;
3136 /* concatenate the fragment to the head mbuf */
3139 frag_size -= frag_len;
3142 bxe_update_sge_prod(fp->sc, fp, frags, &cqe_fp->sgl_or_raw_data);
3148 bxe_rxeof(struct bxe_softc *sc,
3149 struct bxe_fastpath *fp)
3151 struct ifnet *ifp = sc->ifnet;
3152 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
3153 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
3159 /* CQ "next element" is of the size of the regular element */
3160 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
3161 if ((hw_cq_cons & RCQ_USABLE_PER_PAGE) == RCQ_USABLE_PER_PAGE) {
3165 bd_cons = fp->rx_bd_cons;
3166 bd_prod = fp->rx_bd_prod;
3167 bd_prod_fw = bd_prod;
3168 sw_cq_cons = fp->rx_cq_cons;
3169 sw_cq_prod = fp->rx_cq_prod;
3172 * Memory barrier necessary as speculative reads of the rx
3173 * buffer can be ahead of the index in the status block
3178 "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n",
3179 fp->index, hw_cq_cons, sw_cq_cons);
3181 while (sw_cq_cons != hw_cq_cons) {
3182 struct bxe_sw_rx_bd *rx_buf = NULL;
3183 union eth_rx_cqe *cqe;
3184 struct eth_fast_path_rx_cqe *cqe_fp;
3185 uint8_t cqe_fp_flags;
3186 enum eth_rx_cqe_type cqe_fp_type;
3187 uint16_t len, lenonbd, pad;
3188 struct mbuf *m = NULL;
3190 comp_ring_cons = RCQ(sw_cq_cons);
3191 bd_prod = RX_BD(bd_prod);
3192 bd_cons = RX_BD(bd_cons);
3194 cqe = &fp->rcq_chain[comp_ring_cons];
3195 cqe_fp = &cqe->fast_path_cqe;
3196 cqe_fp_flags = cqe_fp->type_error_flags;
3197 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
3200 "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d "
3201 "BD prod=%d cons=%d CQE type=0x%x err=0x%x "
3202 "status=0x%x rss_hash=0x%x vlan=0x%x len=%u lenonbd=%u\n",
3208 CQE_TYPE(cqe_fp_flags),
3210 cqe_fp->status_flags,
3211 le32toh(cqe_fp->rss_hash_result),
3212 le16toh(cqe_fp->vlan_tag),
3213 le16toh(cqe_fp->pkt_len_or_gro_seg_len),
3214 le16toh(cqe_fp->len_on_bd));
3216 /* is this a slowpath msg? */
3217 if (__predict_false(CQE_TYPE_SLOW(cqe_fp_type))) {
3218 bxe_sp_event(sc, fp, cqe);
3222 rx_buf = &fp->rx_mbuf_chain[bd_cons];
3224 if (!CQE_TYPE_FAST(cqe_fp_type)) {
3225 struct bxe_sw_tpa_info *tpa_info;
3226 uint16_t frag_size, pages;
3229 if (CQE_TYPE_START(cqe_fp_type)) {
3230 bxe_tpa_start(sc, fp, cqe_fp->queue_index,
3231 bd_cons, bd_prod, cqe_fp);
3232 m = NULL; /* packet not ready yet */
3236 KASSERT(CQE_TYPE_STOP(cqe_fp_type),
3237 ("CQE type is not STOP! (0x%x)\n", cqe_fp_type));
3239 queue = cqe->end_agg_cqe.queue_index;
3240 tpa_info = &fp->rx_tpa_info[queue];
3242 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n",
3245 frag_size = (le16toh(cqe->end_agg_cqe.pkt_len) -
3246 tpa_info->len_on_bd);
3247 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3249 bxe_tpa_stop(sc, fp, tpa_info, queue, pages,
3250 &cqe->end_agg_cqe, comp_ring_cons);
3252 bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe.sgl_or_raw_data);
3259 /* is this an error packet? */
3260 if (__predict_false(cqe_fp_flags &
3261 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
3262 BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons);
3263 fp->eth_q_stats.rx_soft_errors++;
3267 len = le16toh(cqe_fp->pkt_len_or_gro_seg_len);
3268 lenonbd = le16toh(cqe_fp->len_on_bd);
3269 pad = cqe_fp->placement_offset;
3273 if (__predict_false(m == NULL)) {
3274 BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n",
3275 bd_cons, fp->index);
3279 /* XXX double copy if packet length under a threshold */
3282 * If all the buffer descriptors are filled with mbufs then fill in
3283 * the current consumer index with a new BD. Else if a maximum Rx
3284 * buffer limit is imposed then fill in the next producer index.
3286 rc = bxe_alloc_rx_bd_mbuf(fp, bd_cons,
3287 (sc->max_rx_bufs != RX_BD_USABLE) ?
3291 /* we simply reuse the received mbuf and don't post it to the stack */
3294 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
3296 fp->eth_q_stats.rx_soft_errors++;
3298 if (sc->max_rx_bufs != RX_BD_USABLE) {
3299 /* copy this consumer index to the producer index */
3300 memcpy(&fp->rx_mbuf_chain[bd_prod], rx_buf,
3301 sizeof(struct bxe_sw_rx_bd));
3302 memset(rx_buf, 0, sizeof(struct bxe_sw_rx_bd));
3308 /* current mbuf was detached from the bd */
3309 fp->eth_q_stats.mbuf_alloc_rx--;
3311 /* we allocated a replacement mbuf, fixup the current one */
3313 m->m_pkthdr.len = m->m_len = len;
3315 if ((len > 60) && (len > lenonbd)) {
3316 fp->eth_q_stats.rx_bxe_service_rxsgl++;
3317 rc = bxe_service_rxsgl(fp, len, lenonbd, m, cqe_fp);
3320 fp->eth_q_stats.rx_jumbo_sge_pkts++;
3321 } else if (lenonbd < len) {
3322 fp->eth_q_stats.rx_erroneous_jumbo_sge_pkts++;
3325 /* assign packet to this interface interface */
3326 m->m_pkthdr.rcvif = ifp;
3328 /* assume no hardware checksum has complated */
3329 m->m_pkthdr.csum_flags = 0;
3331 /* validate checksum if offload enabled */
3332 if (ifp->if_capenable & IFCAP_RXCSUM) {
3333 /* check for a valid IP frame */
3334 if (!(cqe->fast_path_cqe.status_flags &
3335 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) {
3336 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3337 if (__predict_false(cqe_fp_flags &
3338 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) {
3339 fp->eth_q_stats.rx_hw_csum_errors++;
3341 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3342 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3346 /* check for a valid TCP/UDP frame */
3347 if (!(cqe->fast_path_cqe.status_flags &
3348 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) {
3349 if (__predict_false(cqe_fp_flags &
3350 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) {
3351 fp->eth_q_stats.rx_hw_csum_errors++;
3353 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3354 m->m_pkthdr.csum_data = 0xFFFF;
3355 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID |
3361 /* if there is a VLAN tag then flag that info */
3362 if (cqe->fast_path_cqe.pars_flags.flags & PARSING_FLAGS_INNER_VLAN_EXIST) {
3363 m->m_pkthdr.ether_vtag = cqe->fast_path_cqe.vlan_tag;
3364 m->m_flags |= M_VLANTAG;
3367 #if __FreeBSD_version >= 800000
3368 /* specify what RSS queue was used for this flow */
3369 m->m_pkthdr.flowid = fp->index;
3375 bd_cons = RX_BD_NEXT(bd_cons);
3376 bd_prod = RX_BD_NEXT(bd_prod);
3377 bd_prod_fw = RX_BD_NEXT(bd_prod_fw);
3379 /* pass the frame to the stack */
3380 if (__predict_true(m != NULL)) {
3383 (*ifp->if_input)(ifp, m);
3388 sw_cq_prod = RCQ_NEXT(sw_cq_prod);
3389 sw_cq_cons = RCQ_NEXT(sw_cq_cons);
3391 /* limit spinning on the queue */
3395 if (rx_pkts == sc->rx_budget) {
3396 fp->eth_q_stats.rx_budget_reached++;
3399 } /* while work to do */
3401 fp->rx_bd_cons = bd_cons;
3402 fp->rx_bd_prod = bd_prod_fw;
3403 fp->rx_cq_cons = sw_cq_cons;
3404 fp->rx_cq_prod = sw_cq_prod;
3406 /* Update producers */
3407 bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod);
3409 fp->eth_q_stats.rx_pkts += rx_pkts;
3410 fp->eth_q_stats.rx_calls++;
3412 BXE_FP_RX_UNLOCK(fp);
3414 return (sw_cq_cons != hw_cq_cons);
3418 bxe_free_tx_pkt(struct bxe_softc *sc,
3419 struct bxe_fastpath *fp,
3422 struct bxe_sw_tx_bd *tx_buf = &fp->tx_mbuf_chain[idx];
3423 struct eth_tx_start_bd *tx_start_bd;
3424 uint16_t bd_idx = TX_BD(tx_buf->first_bd);
3428 /* unmap the mbuf from non-paged memory */
3429 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
3431 tx_start_bd = &fp->tx_chain[bd_idx].start_bd;
3432 nbd = le16toh(tx_start_bd->nbd) - 1;
3434 new_cons = (tx_buf->first_bd + nbd);
3437 if (__predict_true(tx_buf->m != NULL)) {
3439 fp->eth_q_stats.mbuf_alloc_tx--;
3441 fp->eth_q_stats.tx_chain_lost_mbuf++;
3445 tx_buf->first_bd = 0;
3450 /* transmit timeout watchdog */
3452 bxe_watchdog(struct bxe_softc *sc,
3453 struct bxe_fastpath *fp)
3457 if ((fp->watchdog_timer == 0) || (--fp->watchdog_timer)) {
3458 BXE_FP_TX_UNLOCK(fp);
3462 BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index);
3464 BXE_FP_TX_UNLOCK(fp);
3466 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT);
3467 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task);
3472 /* processes transmit completions */
3474 bxe_txeof(struct bxe_softc *sc,
3475 struct bxe_fastpath *fp)
3477 struct ifnet *ifp = sc->ifnet;
3478 uint16_t bd_cons, hw_cons, sw_cons, pkt_cons;
3479 uint16_t tx_bd_avail;
3481 BXE_FP_TX_LOCK_ASSERT(fp);
3483 bd_cons = fp->tx_bd_cons;
3484 hw_cons = le16toh(*fp->tx_cons_sb);
3485 sw_cons = fp->tx_pkt_cons;
3487 while (sw_cons != hw_cons) {
3488 pkt_cons = TX_BD(sw_cons);
3491 "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n",
3492 fp->index, hw_cons, sw_cons, pkt_cons);
3494 bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons);
3499 fp->tx_pkt_cons = sw_cons;
3500 fp->tx_bd_cons = bd_cons;
3503 "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n",
3504 fp->index, hw_cons, fp->tx_pkt_cons, fp->tx_pkt_prod);
3508 tx_bd_avail = bxe_tx_avail(sc, fp);
3510 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
3511 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3513 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3516 if (fp->tx_pkt_prod != fp->tx_pkt_cons) {
3517 /* reset the watchdog timer if there are pending transmits */
3518 fp->watchdog_timer = BXE_TX_TIMEOUT;
3521 /* clear watchdog when there are no pending transmits */
3522 fp->watchdog_timer = 0;
3528 bxe_drain_tx_queues(struct bxe_softc *sc)
3530 struct bxe_fastpath *fp;
3533 /* wait until all TX fastpath tasks have completed */
3534 for (i = 0; i < sc->num_queues; i++) {
3539 while (bxe_has_tx_work(fp)) {
3543 BXE_FP_TX_UNLOCK(fp);
3546 BLOGE(sc, "Timeout waiting for fp[%d] "
3547 "transmits to complete!\n", i);
3548 bxe_panic(sc, ("tx drain failure\n"));
3562 bxe_del_all_macs(struct bxe_softc *sc,
3563 struct ecore_vlan_mac_obj *mac_obj,
3565 uint8_t wait_for_comp)
3567 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
3570 /* wait for completion of requested */
3571 if (wait_for_comp) {
3572 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
3575 /* Set the mac type of addresses we want to clear */
3576 bxe_set_bit(mac_type, &vlan_mac_flags);
3578 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
3580 BLOGE(sc, "Failed to delete MACs (%d) mac_type %d wait_for_comp 0x%x\n",
3581 rc, mac_type, wait_for_comp);
3588 bxe_fill_accept_flags(struct bxe_softc *sc,
3590 unsigned long *rx_accept_flags,
3591 unsigned long *tx_accept_flags)
3593 /* Clear the flags first */
3594 *rx_accept_flags = 0;
3595 *tx_accept_flags = 0;
3598 case BXE_RX_MODE_NONE:
3600 * 'drop all' supersedes any accept flags that may have been
3601 * passed to the function.
3605 case BXE_RX_MODE_NORMAL:
3606 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3607 bxe_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
3608 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3610 /* internal switching mode */
3611 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3612 bxe_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
3613 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3617 case BXE_RX_MODE_ALLMULTI:
3618 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3619 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3620 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3622 /* internal switching mode */
3623 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3624 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3625 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3629 case BXE_RX_MODE_PROMISC:
3631 * According to deffinition of SI mode, iface in promisc mode
3632 * should receive matched and unmatched (in resolution of port)
3635 bxe_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
3636 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3637 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3638 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3640 /* internal switching mode */
3641 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3642 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3645 bxe_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
3647 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3653 BLOGE(sc, "Unknown rx_mode (0x%x)\n", rx_mode);
3657 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
3658 if (rx_mode != BXE_RX_MODE_NONE) {
3659 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
3660 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
3667 bxe_set_q_rx_mode(struct bxe_softc *sc,
3669 unsigned long rx_mode_flags,
3670 unsigned long rx_accept_flags,
3671 unsigned long tx_accept_flags,
3672 unsigned long ramrod_flags)
3674 struct ecore_rx_mode_ramrod_params ramrod_param;
3677 memset(&ramrod_param, 0, sizeof(ramrod_param));
3679 /* Prepare ramrod parameters */
3680 ramrod_param.cid = 0;
3681 ramrod_param.cl_id = cl_id;
3682 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
3683 ramrod_param.func_id = SC_FUNC(sc);
3685 ramrod_param.pstate = &sc->sp_state;
3686 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
3688 ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata);
3689 ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata);
3691 bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
3693 ramrod_param.ramrod_flags = ramrod_flags;
3694 ramrod_param.rx_mode_flags = rx_mode_flags;
3696 ramrod_param.rx_accept_flags = rx_accept_flags;
3697 ramrod_param.tx_accept_flags = tx_accept_flags;
3699 rc = ecore_config_rx_mode(sc, &ramrod_param);
3701 BLOGE(sc, "Set rx_mode %d cli_id 0x%x rx_mode_flags 0x%x "
3702 "rx_accept_flags 0x%x tx_accept_flags 0x%x "
3703 "ramrod_flags 0x%x rc %d failed\n", sc->rx_mode, cl_id,
3704 (uint32_t)rx_mode_flags, (uint32_t)rx_accept_flags,
3705 (uint32_t)tx_accept_flags, (uint32_t)ramrod_flags, rc);
3713 bxe_set_storm_rx_mode(struct bxe_softc *sc)
3715 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
3716 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
3719 rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
3725 bxe_set_bit(RAMROD_RX, &ramrod_flags);
3726 bxe_set_bit(RAMROD_TX, &ramrod_flags);
3728 /* XXX ensure all fastpath have same cl_id and/or move it to bxe_softc */
3729 return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
3730 rx_accept_flags, tx_accept_flags,
3734 /* returns the "mcp load_code" according to global load_count array */
3736 bxe_nic_load_no_mcp(struct bxe_softc *sc)
3738 int path = SC_PATH(sc);
3739 int port = SC_PORT(sc);
3741 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3742 path, load_count[path][0], load_count[path][1],
3743 load_count[path][2]);
3744 load_count[path][0]++;
3745 load_count[path][1 + port]++;
3746 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3747 path, load_count[path][0], load_count[path][1],
3748 load_count[path][2]);
3749 if (load_count[path][0] == 1) {
3750 return (FW_MSG_CODE_DRV_LOAD_COMMON);
3751 } else if (load_count[path][1 + port] == 1) {
3752 return (FW_MSG_CODE_DRV_LOAD_PORT);
3754 return (FW_MSG_CODE_DRV_LOAD_FUNCTION);
3758 /* returns the "mcp load_code" according to global load_count array */
3760 bxe_nic_unload_no_mcp(struct bxe_softc *sc)
3762 int port = SC_PORT(sc);
3763 int path = SC_PATH(sc);
3765 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3766 path, load_count[path][0], load_count[path][1],
3767 load_count[path][2]);
3768 load_count[path][0]--;
3769 load_count[path][1 + port]--;
3770 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3771 path, load_count[path][0], load_count[path][1],
3772 load_count[path][2]);
3773 if (load_count[path][0] == 0) {
3774 return (FW_MSG_CODE_DRV_UNLOAD_COMMON);
3775 } else if (load_count[path][1 + port] == 0) {
3776 return (FW_MSG_CODE_DRV_UNLOAD_PORT);
3778 return (FW_MSG_CODE_DRV_UNLOAD_FUNCTION);
3782 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
3784 bxe_send_unload_req(struct bxe_softc *sc,
3787 uint32_t reset_code = 0;
3789 /* Select the UNLOAD request mode */
3790 if (unload_mode == UNLOAD_NORMAL) {
3791 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3793 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3796 /* Send the request to the MCP */
3797 if (!BXE_NOMCP(sc)) {
3798 reset_code = bxe_fw_command(sc, reset_code, 0);
3800 reset_code = bxe_nic_unload_no_mcp(sc);
3803 return (reset_code);
3806 /* send UNLOAD_DONE command to the MCP */
3808 bxe_send_unload_done(struct bxe_softc *sc,
3811 uint32_t reset_param =
3812 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
3814 /* Report UNLOAD_DONE to MCP */
3815 if (!BXE_NOMCP(sc)) {
3816 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
3821 bxe_func_wait_started(struct bxe_softc *sc)
3825 if (!sc->port.pmf) {
3830 * (assumption: No Attention from MCP at this stage)
3831 * PMF probably in the middle of TX disable/enable transaction
3832 * 1. Sync IRS for default SB
3833 * 2. Sync SP queue - this guarantees us that attention handling started
3834 * 3. Wait, that TX disable/enable transaction completes
3836 * 1+2 guarantee that if DCBX attention was scheduled it already changed
3837 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
3838 * received completion for the transaction the state is TX_STOPPED.
3839 * State will return to STARTED after completion of TX_STOPPED-->STARTED
3843 /* XXX make sure default SB ISR is done */
3844 /* need a way to synchronize an irq (intr_mtx?) */
3846 /* XXX flush any work queues */
3848 while (ecore_func_get_state(sc, &sc->func_obj) !=
3849 ECORE_F_STATE_STARTED && tout--) {
3853 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
3855 * Failed to complete the transaction in a "good way"
3856 * Force both transactions with CLR bit.
3858 struct ecore_func_state_params func_params = { NULL };
3860 BLOGE(sc, "Unexpected function state! "
3861 "Forcing STARTED-->TX_STOPPED-->STARTED\n");
3863 func_params.f_obj = &sc->func_obj;
3864 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
3866 /* STARTED-->TX_STOPPED */
3867 func_params.cmd = ECORE_F_CMD_TX_STOP;
3868 ecore_func_state_change(sc, &func_params);
3870 /* TX_STOPPED-->STARTED */
3871 func_params.cmd = ECORE_F_CMD_TX_START;
3872 return (ecore_func_state_change(sc, &func_params));
3879 bxe_stop_queue(struct bxe_softc *sc,
3882 struct bxe_fastpath *fp = &sc->fp[index];
3883 struct ecore_queue_state_params q_params = { NULL };
3886 BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index);
3888 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
3889 /* We want to wait for completion in this context */
3890 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
3892 /* Stop the primary connection: */
3894 /* ...halt the connection */
3895 q_params.cmd = ECORE_Q_CMD_HALT;
3896 rc = ecore_queue_state_change(sc, &q_params);
3901 /* ...terminate the connection */
3902 q_params.cmd = ECORE_Q_CMD_TERMINATE;
3903 memset(&q_params.params.terminate, 0, sizeof(q_params.params.terminate));
3904 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
3905 rc = ecore_queue_state_change(sc, &q_params);
3910 /* ...delete cfc entry */
3911 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
3912 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
3913 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
3914 return (ecore_queue_state_change(sc, &q_params));
3917 /* wait for the outstanding SP commands */
3918 static inline uint8_t
3919 bxe_wait_sp_comp(struct bxe_softc *sc,
3923 int tout = 5000; /* wait for 5 secs tops */
3927 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
3936 tmp = atomic_load_acq_long(&sc->sp_state);
3938 BLOGE(sc, "Filtering completion timed out: "
3939 "sp_state 0x%lx, mask 0x%lx\n",
3948 bxe_func_stop(struct bxe_softc *sc)
3950 struct ecore_func_state_params func_params = { NULL };
3953 /* prepare parameters for function state transitions */
3954 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
3955 func_params.f_obj = &sc->func_obj;
3956 func_params.cmd = ECORE_F_CMD_STOP;
3959 * Try to stop the function the 'good way'. If it fails (in case
3960 * of a parity error during bxe_chip_cleanup()) and we are
3961 * not in a debug mode, perform a state transaction in order to
3962 * enable further HW_RESET transaction.
3964 rc = ecore_func_state_change(sc, &func_params);
3966 BLOGE(sc, "FUNC_STOP ramrod failed. "
3967 "Running a dry transaction (%d)\n", rc);
3968 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
3969 return (ecore_func_state_change(sc, &func_params));
3976 bxe_reset_hw(struct bxe_softc *sc,
3979 struct ecore_func_state_params func_params = { NULL };
3981 /* Prepare parameters for function state transitions */
3982 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
3984 func_params.f_obj = &sc->func_obj;
3985 func_params.cmd = ECORE_F_CMD_HW_RESET;
3987 func_params.params.hw_init.load_phase = load_code;
3989 return (ecore_func_state_change(sc, &func_params));
3993 bxe_int_disable_sync(struct bxe_softc *sc,
3997 /* prevent the HW from sending interrupts */
3998 bxe_int_disable(sc);
4001 /* XXX need a way to synchronize ALL irqs (intr_mtx?) */
4002 /* make sure all ISRs are done */
4004 /* XXX make sure sp_task is not running */
4005 /* cancel and flush work queues */
4009 bxe_chip_cleanup(struct bxe_softc *sc,
4010 uint32_t unload_mode,
4013 int port = SC_PORT(sc);
4014 struct ecore_mcast_ramrod_params rparam = { NULL };
4015 uint32_t reset_code;
4018 bxe_drain_tx_queues(sc);
4020 /* give HW time to discard old tx messages */
4023 /* Clean all ETH MACs */
4024 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE);
4026 BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc);
4029 /* Clean up UC list */
4030 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE);
4032 BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc);
4036 if (!CHIP_IS_E1(sc)) {
4037 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
4040 /* Set "drop all" to stop Rx */
4043 * We need to take the BXE_MCAST_LOCK() here in order to prevent
4044 * a race between the completion code and this code.
4048 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
4049 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
4051 bxe_set_storm_rx_mode(sc);
4054 /* Clean up multicast configuration */
4055 rparam.mcast_obj = &sc->mcast_obj;
4056 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4058 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4061 BXE_MCAST_UNLOCK(sc);
4063 // XXX bxe_iov_chip_cleanup(sc);
4066 * Send the UNLOAD_REQUEST to the MCP. This will return if
4067 * this function should perform FUNCTION, PORT, or COMMON HW
4070 reset_code = bxe_send_unload_req(sc, unload_mode);
4073 * (assumption: No Attention from MCP at this stage)
4074 * PMF probably in the middle of TX disable/enable transaction
4076 rc = bxe_func_wait_started(sc);
4078 BLOGE(sc, "bxe_func_wait_started failed (%d)\n", rc);
4082 * Close multi and leading connections
4083 * Completions for ramrods are collected in a synchronous way
4085 for (i = 0; i < sc->num_queues; i++) {
4086 if (bxe_stop_queue(sc, i)) {
4092 * If SP settings didn't get completed so far - something
4093 * very wrong has happen.
4095 if (!bxe_wait_sp_comp(sc, ~0x0UL)) {
4096 BLOGE(sc, "Common slow path ramrods got stuck!(%d)\n", rc);
4101 rc = bxe_func_stop(sc);
4103 BLOGE(sc, "Function stop failed!(%d)\n", rc);
4106 /* disable HW interrupts */
4107 bxe_int_disable_sync(sc, TRUE);
4109 /* detach interrupts */
4110 bxe_interrupt_detach(sc);
4112 /* Reset the chip */
4113 rc = bxe_reset_hw(sc, reset_code);
4115 BLOGE(sc, "Hardware reset failed(%d)\n", rc);
4118 /* Report UNLOAD_DONE to MCP */
4119 bxe_send_unload_done(sc, keep_link);
4123 bxe_disable_close_the_gate(struct bxe_softc *sc)
4126 int port = SC_PORT(sc);
4129 "Disabling 'close the gates'\n");
4131 if (CHIP_IS_E1(sc)) {
4132 uint32_t addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4133 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4134 val = REG_RD(sc, addr);
4136 REG_WR(sc, addr, val);
4138 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
4139 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
4140 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
4141 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
4146 * Cleans the object that have internal lists without sending
4147 * ramrods. Should be run when interrutps are disabled.
4150 bxe_squeeze_objects(struct bxe_softc *sc)
4152 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
4153 struct ecore_mcast_ramrod_params rparam = { NULL };
4154 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
4157 /* Cleanup MACs' object first... */
4159 /* Wait for completion of requested */
4160 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
4161 /* Perform a dry cleanup */
4162 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
4164 /* Clean ETH primary MAC */
4165 bxe_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
4166 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
4169 BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc);
4172 /* Cleanup UC list */
4174 bxe_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
4175 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags,
4178 BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc);
4181 /* Now clean mcast object... */
4183 rparam.mcast_obj = &sc->mcast_obj;
4184 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
4186 /* Add a DEL command... */
4187 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4189 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4192 /* now wait until all pending commands are cleared */
4194 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4197 BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc);
4201 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4205 /* stop the controller */
4206 static __noinline int
4207 bxe_nic_unload(struct bxe_softc *sc,
4208 uint32_t unload_mode,
4211 uint8_t global = FALSE;
4215 BXE_CORE_LOCK_ASSERT(sc);
4217 sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING;
4219 for (i = 0; i < sc->num_queues; i++) {
4220 struct bxe_fastpath *fp;
4224 BXE_FP_TX_UNLOCK(fp);
4227 BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n");
4229 /* mark driver as unloaded in shmem2 */
4230 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
4231 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
4232 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
4233 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
4236 if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE &&
4237 (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) {
4239 * We can get here if the driver has been unloaded
4240 * during parity error recovery and is either waiting for a
4241 * leader to complete or for other functions to unload and
4242 * then ifconfig down has been issued. In this case we want to
4243 * unload and let other functions to complete a recovery
4246 sc->recovery_state = BXE_RECOVERY_DONE;
4248 bxe_release_leader_lock(sc);
4251 BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n");
4252 BLOGE(sc, "Can't unload in closed or error state recover_state 0x%x"
4253 " state = 0x%x\n", sc->recovery_state, sc->state);
4258 * Nothing to do during unload if previous bxe_nic_load()
4259 * did not completed succesfully - all resourses are released.
4261 if ((sc->state == BXE_STATE_CLOSED) ||
4262 (sc->state == BXE_STATE_ERROR)) {
4266 sc->state = BXE_STATE_CLOSING_WAITING_HALT;
4272 sc->rx_mode = BXE_RX_MODE_NONE;
4273 /* XXX set rx mode ??? */
4275 if (IS_PF(sc) && !sc->grcdump_done) {
4276 /* set ALWAYS_ALIVE bit in shmem */
4277 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
4281 bxe_stats_handle(sc, STATS_EVENT_STOP);
4282 bxe_save_statistics(sc);
4285 /* wait till consumers catch up with producers in all queues */
4286 bxe_drain_tx_queues(sc);
4288 /* if VF indicate to PF this function is going down (PF will delete sp
4289 * elements and clear initializations
4292 ; /* bxe_vfpf_close_vf(sc); */
4293 } else if (unload_mode != UNLOAD_RECOVERY) {
4294 /* if this is a normal/close unload need to clean up chip */
4295 if (!sc->grcdump_done)
4296 bxe_chip_cleanup(sc, unload_mode, keep_link);
4298 /* Send the UNLOAD_REQUEST to the MCP */
4299 bxe_send_unload_req(sc, unload_mode);
4302 * Prevent transactions to host from the functions on the
4303 * engine that doesn't reset global blocks in case of global
4304 * attention once gloabl blocks are reset and gates are opened
4305 * (the engine which leader will perform the recovery
4308 if (!CHIP_IS_E1x(sc)) {
4312 /* disable HW interrupts */
4313 bxe_int_disable_sync(sc, TRUE);
4315 /* detach interrupts */
4316 bxe_interrupt_detach(sc);
4318 /* Report UNLOAD_DONE to MCP */
4319 bxe_send_unload_done(sc, FALSE);
4323 * At this stage no more interrupts will arrive so we may safely clean
4324 * the queue'able objects here in case they failed to get cleaned so far.
4327 bxe_squeeze_objects(sc);
4330 /* There should be no more pending SP commands at this stage */
4335 bxe_free_fp_buffers(sc);
4341 bxe_free_fw_stats_mem(sc);
4343 sc->state = BXE_STATE_CLOSED;
4346 * Check if there are pending parity attentions. If there are - set
4347 * RECOVERY_IN_PROGRESS.
4349 if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) {
4350 bxe_set_reset_in_progress(sc);
4352 /* Set RESET_IS_GLOBAL if needed */
4354 bxe_set_reset_global(sc);
4359 * The last driver must disable a "close the gate" if there is no
4360 * parity attention or "process kill" pending.
4362 if (IS_PF(sc) && !bxe_clear_pf_load(sc) &&
4363 bxe_reset_is_done(sc, SC_PATH(sc))) {
4364 bxe_disable_close_the_gate(sc);
4367 BLOGD(sc, DBG_LOAD, "Ended NIC unload\n");
4373 * Called by the OS to set various media options (i.e. link, speed, etc.) when
4374 * the user runs "ifconfig bxe media ..." or "ifconfig bxe mediaopt ...".
4377 bxe_ifmedia_update(struct ifnet *ifp)
4379 struct bxe_softc *sc = (struct bxe_softc *)ifp->if_softc;
4380 struct ifmedia *ifm;
4384 /* We only support Ethernet media type. */
4385 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
4389 switch (IFM_SUBTYPE(ifm->ifm_media)) {
4395 case IFM_10G_TWINAX:
4397 /* We don't support changing the media type. */
4398 BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n",
4399 IFM_SUBTYPE(ifm->ifm_media));
4407 * Called by the OS to get the current media status (i.e. link, speed, etc.).
4410 bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
4412 struct bxe_softc *sc = ifp->if_softc;
4414 /* Report link down if the driver isn't running. */
4415 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4416 ifmr->ifm_active |= IFM_NONE;
4420 /* Setup the default interface info. */
4421 ifmr->ifm_status = IFM_AVALID;
4422 ifmr->ifm_active = IFM_ETHER;
4424 if (sc->link_vars.link_up) {
4425 ifmr->ifm_status |= IFM_ACTIVE;
4427 ifmr->ifm_active |= IFM_NONE;
4431 ifmr->ifm_active |= sc->media;
4433 if (sc->link_vars.duplex == DUPLEX_FULL) {
4434 ifmr->ifm_active |= IFM_FDX;
4436 ifmr->ifm_active |= IFM_HDX;
4441 bxe_ioctl_nvram(struct bxe_softc *sc,
4445 struct bxe_nvram_data nvdata_base;
4446 struct bxe_nvram_data *nvdata;
4450 copyin(ifr->ifr_data, &nvdata_base, sizeof(nvdata_base));
4452 len = (sizeof(struct bxe_nvram_data) +
4456 if (len > sizeof(struct bxe_nvram_data)) {
4457 if ((nvdata = (struct bxe_nvram_data *)
4458 malloc(len, M_DEVBUF,
4459 (M_NOWAIT | M_ZERO))) == NULL) {
4460 BLOGE(sc, "BXE_IOC_RD_NVRAM malloc failed priv_op 0x%x "
4461 " len = 0x%x\n", priv_op, len);
4464 memcpy(nvdata, &nvdata_base, sizeof(struct bxe_nvram_data));
4466 nvdata = &nvdata_base;
4469 if (priv_op == BXE_IOC_RD_NVRAM) {
4470 BLOGD(sc, DBG_IOCTL, "IOC_RD_NVRAM 0x%x %d\n",
4471 nvdata->offset, nvdata->len);
4472 error = bxe_nvram_read(sc,
4474 (uint8_t *)nvdata->value,
4476 copyout(nvdata, ifr->ifr_data, len);
4477 } else { /* BXE_IOC_WR_NVRAM */
4478 BLOGD(sc, DBG_IOCTL, "IOC_WR_NVRAM 0x%x %d\n",
4479 nvdata->offset, nvdata->len);
4480 copyin(ifr->ifr_data, nvdata, len);
4481 error = bxe_nvram_write(sc,
4483 (uint8_t *)nvdata->value,
4487 if (len > sizeof(struct bxe_nvram_data)) {
4488 free(nvdata, M_DEVBUF);
4495 bxe_ioctl_stats_show(struct bxe_softc *sc,
4499 const size_t str_size = (BXE_NUM_ETH_STATS * STAT_NAME_LEN);
4500 const size_t stats_size = (BXE_NUM_ETH_STATS * sizeof(uint64_t));
4507 case BXE_IOC_STATS_SHOW_NUM:
4508 memset(ifr->ifr_data, 0, sizeof(union bxe_stats_show_data));
4509 ((union bxe_stats_show_data *)ifr->ifr_data)->desc.num =
4511 ((union bxe_stats_show_data *)ifr->ifr_data)->desc.len =
4515 case BXE_IOC_STATS_SHOW_STR:
4516 memset(ifr->ifr_data, 0, str_size);
4517 p_tmp = ifr->ifr_data;
4518 for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
4519 strcpy(p_tmp, bxe_eth_stats_arr[i].string);
4520 p_tmp += STAT_NAME_LEN;
4524 case BXE_IOC_STATS_SHOW_CNT:
4525 memset(ifr->ifr_data, 0, stats_size);
4526 p_tmp = ifr->ifr_data;
4527 for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
4528 offset = ((uint32_t *)&sc->eth_stats +
4529 bxe_eth_stats_arr[i].offset);
4530 switch (bxe_eth_stats_arr[i].size) {
4532 *((uint64_t *)p_tmp) = (uint64_t)*offset;
4535 *((uint64_t *)p_tmp) = HILO_U64(*offset, *(offset + 1));
4538 *((uint64_t *)p_tmp) = 0;
4540 p_tmp += sizeof(uint64_t);
4550 bxe_handle_chip_tq(void *context,
4553 struct bxe_softc *sc = (struct bxe_softc *)context;
4554 long work = atomic_load_acq_long(&sc->chip_tq_flags);
4558 case CHIP_TQ_REINIT:
4559 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
4560 /* restart the interface */
4561 BLOGD(sc, DBG_LOAD, "Restarting the interface...\n");
4562 bxe_periodic_stop(sc);
4564 bxe_stop_locked(sc);
4565 bxe_init_locked(sc);
4566 BXE_CORE_UNLOCK(sc);
4576 * Handles any IOCTL calls from the operating system.
4579 * 0 = Success, >0 Failure
4582 bxe_ioctl(struct ifnet *ifp,
4586 struct bxe_softc *sc = ifp->if_softc;
4587 struct ifreq *ifr = (struct ifreq *)data;
4588 struct bxe_nvram_data *nvdata;
4594 int mtu_min = (ETH_MIN_PACKET_SIZE - ETH_HLEN);
4595 int mtu_max = (MJUM9BYTES - ETH_OVERHEAD - IP_HEADER_ALIGNMENT_PADDING);
4600 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n",
4603 if (sc->mtu == ifr->ifr_mtu) {
4604 /* nothing to change */
4608 if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) {
4609 BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n",
4610 ifr->ifr_mtu, mtu_min, mtu_max);
4615 atomic_store_rel_int((volatile unsigned int *)&sc->mtu,
4616 (unsigned long)ifr->ifr_mtu);
4617 atomic_store_rel_long((volatile unsigned long *)&ifp->if_mtu,
4618 (unsigned long)ifr->ifr_mtu);
4624 /* toggle the interface state up or down */
4625 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n");
4628 /* check if the interface is up */
4629 if (ifp->if_flags & IFF_UP) {
4630 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4631 /* set the receive mode flags */
4632 bxe_set_rx_mode(sc);
4633 } else if(sc->state != BXE_STATE_DISABLED) {
4634 bxe_init_locked(sc);
4637 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4638 bxe_periodic_stop(sc);
4639 bxe_stop_locked(sc);
4642 BXE_CORE_UNLOCK(sc);
4648 /* add/delete multicast addresses */
4649 BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n");
4651 /* check if the interface is up */
4652 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4653 /* set the receive mode flags */
4655 bxe_set_rx_mode(sc);
4656 BXE_CORE_UNLOCK(sc);
4662 /* find out which capabilities have changed */
4663 mask = (ifr->ifr_reqcap ^ ifp->if_capenable);
4665 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n",
4668 /* toggle the LRO capabilites enable flag */
4669 if (mask & IFCAP_LRO) {
4670 ifp->if_capenable ^= IFCAP_LRO;
4671 BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n",
4672 (ifp->if_capenable & IFCAP_LRO) ? "ON" : "OFF");
4676 /* toggle the TXCSUM checksum capabilites enable flag */
4677 if (mask & IFCAP_TXCSUM) {
4678 ifp->if_capenable ^= IFCAP_TXCSUM;
4679 BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n",
4680 (ifp->if_capenable & IFCAP_TXCSUM) ? "ON" : "OFF");
4681 if (ifp->if_capenable & IFCAP_TXCSUM) {
4682 ifp->if_hwassist = (CSUM_IP |
4689 ifp->if_hwassist = 0;
4693 /* toggle the RXCSUM checksum capabilities enable flag */
4694 if (mask & IFCAP_RXCSUM) {
4695 ifp->if_capenable ^= IFCAP_RXCSUM;
4696 BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n",
4697 (ifp->if_capenable & IFCAP_RXCSUM) ? "ON" : "OFF");
4698 if (ifp->if_capenable & IFCAP_RXCSUM) {
4699 ifp->if_hwassist = (CSUM_IP |
4706 ifp->if_hwassist = 0;
4710 /* toggle TSO4 capabilities enabled flag */
4711 if (mask & IFCAP_TSO4) {
4712 ifp->if_capenable ^= IFCAP_TSO4;
4713 BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n",
4714 (ifp->if_capenable & IFCAP_TSO4) ? "ON" : "OFF");
4717 /* toggle TSO6 capabilities enabled flag */
4718 if (mask & IFCAP_TSO6) {
4719 ifp->if_capenable ^= IFCAP_TSO6;
4720 BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n",
4721 (ifp->if_capenable & IFCAP_TSO6) ? "ON" : "OFF");
4724 /* toggle VLAN_HWTSO capabilities enabled flag */
4725 if (mask & IFCAP_VLAN_HWTSO) {
4726 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4727 BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n",
4728 (ifp->if_capenable & IFCAP_VLAN_HWTSO) ? "ON" : "OFF");
4731 /* toggle VLAN_HWCSUM capabilities enabled flag */
4732 if (mask & IFCAP_VLAN_HWCSUM) {
4733 /* XXX investigate this... */
4734 BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n");
4738 /* toggle VLAN_MTU capabilities enable flag */
4739 if (mask & IFCAP_VLAN_MTU) {
4740 /* XXX investigate this... */
4741 BLOGE(sc, "Changing VLAN_MTU is not supported!\n");
4745 /* toggle VLAN_HWTAGGING capabilities enabled flag */
4746 if (mask & IFCAP_VLAN_HWTAGGING) {
4747 /* XXX investigate this... */
4748 BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n");
4752 /* toggle VLAN_HWFILTER capabilities enabled flag */
4753 if (mask & IFCAP_VLAN_HWFILTER) {
4754 /* XXX investigate this... */
4755 BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n");
4767 /* set/get interface media */
4768 BLOGD(sc, DBG_IOCTL,
4769 "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n",
4771 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
4774 case SIOCGPRIVATE_0:
4775 copyin(ifr->ifr_data, &priv_op, sizeof(priv_op));
4779 case BXE_IOC_RD_NVRAM:
4780 case BXE_IOC_WR_NVRAM:
4781 nvdata = (struct bxe_nvram_data *)ifr->ifr_data;
4782 BLOGD(sc, DBG_IOCTL,
4783 "Received Private NVRAM ioctl addr=0x%x size=%u\n",
4784 nvdata->offset, nvdata->len);
4785 error = bxe_ioctl_nvram(sc, priv_op, ifr);
4788 case BXE_IOC_STATS_SHOW_NUM:
4789 case BXE_IOC_STATS_SHOW_STR:
4790 case BXE_IOC_STATS_SHOW_CNT:
4791 BLOGD(sc, DBG_IOCTL, "Received Private Stats ioctl (%d)\n",
4793 error = bxe_ioctl_stats_show(sc, priv_op, ifr);
4797 BLOGW(sc, "Received Private Unknown ioctl (%d)\n", priv_op);
4805 BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n",
4807 error = ether_ioctl(ifp, command, data);
4811 if (reinit && (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
4812 BLOGD(sc, DBG_LOAD | DBG_IOCTL,
4813 "Re-initializing hardware from IOCTL change\n");
4814 bxe_periodic_stop(sc);
4816 bxe_stop_locked(sc);
4817 bxe_init_locked(sc);
4818 BXE_CORE_UNLOCK(sc);
4824 static __noinline void
4825 bxe_dump_mbuf(struct bxe_softc *sc,
4832 if (!(sc->debug & DBG_MBUF)) {
4837 BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n");
4843 #if __FreeBSD_version >= 1000000
4845 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
4846 i, m, m->m_len, m->m_flags, M_FLAG_BITS, m->m_data);
4848 if (m->m_flags & M_PKTHDR) {
4850 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
4851 i, m->m_pkthdr.len, m->m_flags, M_FLAG_BITS,
4852 (int)m->m_pkthdr.csum_flags, CSUM_BITS);
4856 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
4857 i, m, m->m_len, m->m_flags,
4858 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", m->m_data);
4860 if (m->m_flags & M_PKTHDR) {
4862 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
4863 i, m->m_pkthdr.len, m->m_flags,
4864 "\20\12M_BCAST\13M_MCAST\14M_FRAG"
4865 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
4866 "\22M_PROMISC\23M_NOFREE",
4867 (int)m->m_pkthdr.csum_flags,
4868 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
4869 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
4870 "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
4871 "\14CSUM_PSEUDO_HDR");
4873 #endif /* #if __FreeBSD_version >= 1000000 */
4875 if (m->m_flags & M_EXT) {
4876 switch (m->m_ext.ext_type) {
4877 case EXT_CLUSTER: type = "EXT_CLUSTER"; break;
4878 case EXT_SFBUF: type = "EXT_SFBUF"; break;
4879 case EXT_JUMBOP: type = "EXT_JUMBOP"; break;
4880 case EXT_JUMBO9: type = "EXT_JUMBO9"; break;
4881 case EXT_JUMBO16: type = "EXT_JUMBO16"; break;
4882 case EXT_PACKET: type = "EXT_PACKET"; break;
4883 case EXT_MBUF: type = "EXT_MBUF"; break;
4884 case EXT_NET_DRV: type = "EXT_NET_DRV"; break;
4885 case EXT_MOD_TYPE: type = "EXT_MOD_TYPE"; break;
4886 case EXT_DISPOSABLE: type = "EXT_DISPOSABLE"; break;
4887 case EXT_EXTREF: type = "EXT_EXTREF"; break;
4888 default: type = "UNKNOWN"; break;
4892 "%02d: - m_ext: %p ext_size=%d type=%s\n",
4893 i, m->m_ext.ext_buf, m->m_ext.ext_size, type);
4897 bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE);
4906 * Checks to ensure the 13 bd sliding window is >= MSS for TSO.
4907 * Check that (13 total bds - 3 bds) = 10 bd window >= MSS.
4908 * The window: 3 bds are = 1 for headers BD + 2 for parse BD and last BD
4909 * The headers comes in a seperate bd in FreeBSD so 13-3=10.
4910 * Returns: 0 if OK to send, 1 if packet needs further defragmentation
4913 bxe_chktso_window(struct bxe_softc *sc,
4915 bus_dma_segment_t *segs,
4918 uint32_t num_wnds, wnd_size, wnd_sum;
4919 int32_t frag_idx, wnd_idx;
4920 unsigned short lso_mss;
4926 num_wnds = nsegs - wnd_size;
4927 lso_mss = htole16(m->m_pkthdr.tso_segsz);
4930 * Total header lengths Eth+IP+TCP in first FreeBSD mbuf so calculate the
4931 * first window sum of data while skipping the first assuming it is the
4932 * header in FreeBSD.
4934 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) {
4935 wnd_sum += htole16(segs[frag_idx].ds_len);
4938 /* check the first 10 bd window size */
4939 if (wnd_sum < lso_mss) {
4943 /* run through the windows */
4944 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) {
4945 /* subtract the first mbuf->m_len of the last wndw(-header) */
4946 wnd_sum -= htole16(segs[wnd_idx+1].ds_len);
4947 /* add the next mbuf len to the len of our new window */
4948 wnd_sum += htole16(segs[frag_idx].ds_len);
4949 if (wnd_sum < lso_mss) {
4958 bxe_set_pbd_csum_e2(struct bxe_fastpath *fp,
4960 uint32_t *parsing_data)
4962 struct ether_vlan_header *eh = NULL;
4963 struct ip *ip4 = NULL;
4964 struct ip6_hdr *ip6 = NULL;
4966 struct tcphdr *th = NULL;
4967 int e_hlen, ip_hlen, l4_off;
4970 if (m->m_pkthdr.csum_flags == CSUM_IP) {
4971 /* no L4 checksum offload needed */
4975 /* get the Ethernet header */
4976 eh = mtod(m, struct ether_vlan_header *);
4978 /* handle VLAN encapsulation if present */
4979 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4980 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4981 proto = ntohs(eh->evl_proto);
4983 e_hlen = ETHER_HDR_LEN;
4984 proto = ntohs(eh->evl_encap_proto);
4989 /* get the IP header, if mbuf len < 20 then header in next mbuf */
4990 ip4 = (m->m_len < sizeof(struct ip)) ?
4991 (struct ip *)m->m_next->m_data :
4992 (struct ip *)(m->m_data + e_hlen);
4993 /* ip_hl is number of 32-bit words */
4994 ip_hlen = (ip4->ip_hl << 2);
4997 case ETHERTYPE_IPV6:
4998 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
4999 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
5000 (struct ip6_hdr *)m->m_next->m_data :
5001 (struct ip6_hdr *)(m->m_data + e_hlen);
5002 /* XXX cannot support offload with IPv6 extensions */
5003 ip_hlen = sizeof(struct ip6_hdr);
5007 /* We can't offload in this case... */
5008 /* XXX error stat ??? */
5012 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
5013 l4_off = (e_hlen + ip_hlen);
5016 (((l4_off >> 1) << ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
5017 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W);
5019 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5022 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
5023 th = (struct tcphdr *)(ip + ip_hlen);
5024 /* th_off is number of 32-bit words */
5025 *parsing_data |= ((th->th_off <<
5026 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
5027 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW);
5028 return (l4_off + (th->th_off << 2)); /* entire header length */
5029 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5031 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
5032 return (l4_off + sizeof(struct udphdr)); /* entire header length */
5034 /* XXX error stat ??? */
5040 bxe_set_pbd_csum(struct bxe_fastpath *fp,
5042 struct eth_tx_parse_bd_e1x *pbd)
5044 struct ether_vlan_header *eh = NULL;
5045 struct ip *ip4 = NULL;
5046 struct ip6_hdr *ip6 = NULL;
5048 struct tcphdr *th = NULL;
5049 struct udphdr *uh = NULL;
5050 int e_hlen, ip_hlen;
5056 /* get the Ethernet header */
5057 eh = mtod(m, struct ether_vlan_header *);
5059 /* handle VLAN encapsulation if present */
5060 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
5061 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
5062 proto = ntohs(eh->evl_proto);
5064 e_hlen = ETHER_HDR_LEN;
5065 proto = ntohs(eh->evl_encap_proto);
5070 /* get the IP header, if mbuf len < 20 then header in next mbuf */
5071 ip4 = (m->m_len < sizeof(struct ip)) ?
5072 (struct ip *)m->m_next->m_data :
5073 (struct ip *)(m->m_data + e_hlen);
5074 /* ip_hl is number of 32-bit words */
5075 ip_hlen = (ip4->ip_hl << 1);
5078 case ETHERTYPE_IPV6:
5079 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
5080 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
5081 (struct ip6_hdr *)m->m_next->m_data :
5082 (struct ip6_hdr *)(m->m_data + e_hlen);
5083 /* XXX cannot support offload with IPv6 extensions */
5084 ip_hlen = (sizeof(struct ip6_hdr) >> 1);
5088 /* We can't offload in this case... */
5089 /* XXX error stat ??? */
5093 hlen = (e_hlen >> 1);
5095 /* note that rest of global_data is indirectly zeroed here */
5096 if (m->m_flags & M_VLANTAG) {
5098 htole16(hlen | (1 << ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
5100 pbd->global_data = htole16(hlen);
5103 pbd->ip_hlen_w = ip_hlen;
5105 hlen += pbd->ip_hlen_w;
5107 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
5109 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5112 th = (struct tcphdr *)(ip + (ip_hlen << 1));
5113 /* th_off is number of 32-bit words */
5114 hlen += (uint16_t)(th->th_off << 1);
5115 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5117 uh = (struct udphdr *)(ip + (ip_hlen << 1));
5118 hlen += (sizeof(struct udphdr) / 2);
5120 /* valid case as only CSUM_IP was set */
5124 pbd->total_hlen_w = htole16(hlen);
5126 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5129 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
5130 pbd->tcp_pseudo_csum = ntohs(th->th_sum);
5131 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5133 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
5136 * Everest1 (i.e. 57710, 57711, 57711E) does not natively support UDP
5137 * checksums and does not know anything about the UDP header and where
5138 * the checksum field is located. It only knows about TCP. Therefore
5139 * we "lie" to the hardware for outgoing UDP packets w/ checksum
5140 * offload. Since the checksum field offset for TCP is 16 bytes and
5141 * for UDP it is 6 bytes we pass a pointer to the hardware that is 10
5142 * bytes less than the start of the UDP header. This allows the
5143 * hardware to write the checksum in the correct spot. But the
5144 * hardware will compute a checksum which includes the last 10 bytes
5145 * of the IP header. To correct this we tweak the stack computed
5146 * pseudo checksum by folding in the calculation of the inverse
5147 * checksum for those final 10 bytes of the IP header. This allows
5148 * the correct checksum to be computed by the hardware.
5151 /* set pointer 10 bytes before UDP header */
5152 tmp_uh = (uint32_t *)((uint8_t *)uh - 10);
5154 /* calculate a pseudo header checksum over the first 10 bytes */
5155 tmp_csum = in_pseudo(*tmp_uh,
5157 *(uint16_t *)(tmp_uh + 2));
5159 pbd->tcp_pseudo_csum = ntohs(in_addword(uh->uh_sum, ~tmp_csum));
5162 return (hlen * 2); /* entire header length, number of bytes */
5166 bxe_set_pbd_lso_e2(struct mbuf *m,
5167 uint32_t *parsing_data)
5169 *parsing_data |= ((m->m_pkthdr.tso_segsz <<
5170 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
5171 ETH_TX_PARSE_BD_E2_LSO_MSS);
5173 /* XXX test for IPv6 with extension header... */
5177 bxe_set_pbd_lso(struct mbuf *m,
5178 struct eth_tx_parse_bd_e1x *pbd)
5180 struct ether_vlan_header *eh = NULL;
5181 struct ip *ip = NULL;
5182 struct tcphdr *th = NULL;
5185 /* get the Ethernet header */
5186 eh = mtod(m, struct ether_vlan_header *);
5188 /* handle VLAN encapsulation if present */
5189 e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ?
5190 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN;
5192 /* get the IP and TCP header, with LSO entire header in first mbuf */
5193 /* XXX assuming IPv4 */
5194 ip = (struct ip *)(m->m_data + e_hlen);
5195 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
5197 pbd->lso_mss = htole16(m->m_pkthdr.tso_segsz);
5198 pbd->tcp_send_seq = ntohl(th->th_seq);
5199 pbd->tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff);
5203 pbd->ip_id = ntohs(ip->ip_id);
5204 pbd->tcp_pseudo_csum =
5205 ntohs(in_pseudo(ip->ip_src.s_addr,
5207 htons(IPPROTO_TCP)));
5210 pbd->tcp_pseudo_csum =
5211 ntohs(in_pseudo(&ip6->ip6_src,
5213 htons(IPPROTO_TCP)));
5217 htole16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
5221 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
5222 * visible to the controller.
5224 * If an mbuf is submitted to this routine and cannot be given to the
5225 * controller (e.g. it has too many fragments) then the function may free
5226 * the mbuf and return to the caller.
5229 * 0 = Success, !0 = Failure
5230 * Note the side effect that an mbuf may be freed if it causes a problem.
5233 bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head)
5235 bus_dma_segment_t segs[32];
5237 struct bxe_sw_tx_bd *tx_buf;
5238 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
5239 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
5240 /* struct eth_tx_parse_2nd_bd *pbd2 = NULL; */
5241 struct eth_tx_bd *tx_data_bd;
5242 struct eth_tx_bd *tx_total_pkt_size_bd;
5243 struct eth_tx_start_bd *tx_start_bd;
5244 uint16_t bd_prod, pkt_prod, total_pkt_size;
5246 int defragged, error, nsegs, rc, nbds, vlan_off, ovlan;
5247 struct bxe_softc *sc;
5248 uint16_t tx_bd_avail;
5249 struct ether_vlan_header *eh;
5250 uint32_t pbd_e2_parsing_data = 0;
5257 #if __FreeBSD_version >= 800000
5258 M_ASSERTPKTHDR(*m_head);
5259 #endif /* #if __FreeBSD_version >= 800000 */
5262 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0;
5265 tx_total_pkt_size_bd = NULL;
5267 /* get the H/W pointer for packets and BDs */
5268 pkt_prod = fp->tx_pkt_prod;
5269 bd_prod = fp->tx_bd_prod;
5271 mac_type = UNICAST_ADDRESS;
5273 /* map the mbuf into the next open DMAable memory */
5274 tx_buf = &fp->tx_mbuf_chain[TX_BD(pkt_prod)];
5275 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5277 segs, &nsegs, BUS_DMA_NOWAIT);
5279 /* mapping errors */
5280 if(__predict_false(error != 0)) {
5281 fp->eth_q_stats.tx_dma_mapping_failure++;
5282 if (error == ENOMEM) {
5283 /* resource issue, try again later */
5285 } else if (error == EFBIG) {
5286 /* possibly recoverable with defragmentation */
5287 fp->eth_q_stats.mbuf_defrag_attempts++;
5288 m0 = m_defrag(*m_head, M_DONTWAIT);
5290 fp->eth_q_stats.mbuf_defrag_failures++;
5293 /* defrag successful, try mapping again */
5295 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5297 segs, &nsegs, BUS_DMA_NOWAIT);
5299 fp->eth_q_stats.tx_dma_mapping_failure++;
5304 /* unknown, unrecoverable mapping error */
5305 BLOGE(sc, "Unknown TX mapping error rc=%d\n", error);
5306 bxe_dump_mbuf(sc, m0, FALSE);
5310 goto bxe_tx_encap_continue;
5313 tx_bd_avail = bxe_tx_avail(sc, fp);
5315 /* make sure there is enough room in the send queue */
5316 if (__predict_false(tx_bd_avail < (nsegs + 2))) {
5317 /* Recoverable, try again later. */
5318 fp->eth_q_stats.tx_hw_queue_full++;
5319 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5321 goto bxe_tx_encap_continue;
5324 /* capture the current H/W TX chain high watermark */
5325 if (__predict_false(fp->eth_q_stats.tx_hw_max_queue_depth <
5326 (TX_BD_USABLE - tx_bd_avail))) {
5327 fp->eth_q_stats.tx_hw_max_queue_depth = (TX_BD_USABLE - tx_bd_avail);
5330 /* make sure it fits in the packet window */
5331 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5333 * The mbuf may be to big for the controller to handle. If the frame
5334 * is a TSO frame we'll need to do an additional check.
5336 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5337 if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) {
5338 goto bxe_tx_encap_continue; /* OK to send */
5340 fp->eth_q_stats.tx_window_violation_tso++;
5343 fp->eth_q_stats.tx_window_violation_std++;
5346 /* lets try to defragment this mbuf and remap it */
5347 fp->eth_q_stats.mbuf_defrag_attempts++;
5348 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5350 m0 = m_defrag(*m_head, M_DONTWAIT);
5352 fp->eth_q_stats.mbuf_defrag_failures++;
5353 /* Ugh, just drop the frame... :( */
5356 /* defrag successful, try mapping again */
5358 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5360 segs, &nsegs, BUS_DMA_NOWAIT);
5362 fp->eth_q_stats.tx_dma_mapping_failure++;
5363 /* No sense in trying to defrag/copy chain, drop it. :( */
5367 /* if the chain is still too long then drop it */
5368 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5369 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5376 bxe_tx_encap_continue:
5378 /* Check for errors */
5381 /* recoverable try again later */
5383 fp->eth_q_stats.tx_soft_errors++;
5384 fp->eth_q_stats.mbuf_alloc_tx--;
5392 /* set flag according to packet type (UNICAST_ADDRESS is default) */
5393 if (m0->m_flags & M_BCAST) {
5394 mac_type = BROADCAST_ADDRESS;
5395 } else if (m0->m_flags & M_MCAST) {
5396 mac_type = MULTICAST_ADDRESS;
5399 /* store the mbuf into the mbuf ring */
5401 tx_buf->first_bd = fp->tx_bd_prod;
5404 /* prepare the first transmit (start) BD for the mbuf */
5405 tx_start_bd = &fp->tx_chain[TX_BD(bd_prod)].start_bd;
5408 "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n",
5409 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
5411 tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
5412 tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
5413 tx_start_bd->nbytes = htole16(segs[0].ds_len);
5414 total_pkt_size += tx_start_bd->nbytes;
5415 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
5417 tx_start_bd->general_data = (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
5419 /* all frames have at least Start BD + Parsing BD */
5421 tx_start_bd->nbd = htole16(nbds);
5423 if (m0->m_flags & M_VLANTAG) {
5424 tx_start_bd->vlan_or_ethertype = htole16(m0->m_pkthdr.ether_vtag);
5425 tx_start_bd->bd_flags.as_bitfield |=
5426 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
5428 /* vf tx, start bd must hold the ethertype for fw to enforce it */
5430 /* map ethernet header to find type and header length */
5431 eh = mtod(m0, struct ether_vlan_header *);
5432 tx_start_bd->vlan_or_ethertype = eh->evl_encap_proto;
5434 /* used by FW for packet accounting */
5435 tx_start_bd->vlan_or_ethertype = htole16(fp->tx_pkt_prod);
5440 * add a parsing BD from the chain. The parsing BD is always added
5441 * though it is only used for TSO and chksum
5443 bd_prod = TX_BD_NEXT(bd_prod);
5445 if (m0->m_pkthdr.csum_flags) {
5446 if (m0->m_pkthdr.csum_flags & CSUM_IP) {
5447 fp->eth_q_stats.tx_ofld_frames_csum_ip++;
5448 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
5451 if (m0->m_pkthdr.csum_flags & CSUM_TCP_IPV6) {
5452 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5453 ETH_TX_BD_FLAGS_L4_CSUM);
5454 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP_IPV6) {
5455 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5456 ETH_TX_BD_FLAGS_IS_UDP |
5457 ETH_TX_BD_FLAGS_L4_CSUM);
5458 } else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) ||
5459 (m0->m_pkthdr.csum_flags & CSUM_TSO)) {
5460 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
5461 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) {
5462 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_L4_CSUM |
5463 ETH_TX_BD_FLAGS_IS_UDP);
5467 if (!CHIP_IS_E1x(sc)) {
5468 pbd_e2 = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e2;
5469 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
5471 if (m0->m_pkthdr.csum_flags) {
5472 hlen = bxe_set_pbd_csum_e2(fp, m0, &pbd_e2_parsing_data);
5475 SET_FLAG(pbd_e2_parsing_data, ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE,
5478 uint16_t global_data = 0;
5480 pbd_e1x = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e1x;
5481 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
5483 if (m0->m_pkthdr.csum_flags) {
5484 hlen = bxe_set_pbd_csum(fp, m0, pbd_e1x);
5487 SET_FLAG(global_data,
5488 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
5489 pbd_e1x->global_data |= htole16(global_data);
5492 /* setup the parsing BD with TSO specific info */
5493 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5494 fp->eth_q_stats.tx_ofld_frames_lso++;
5495 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
5497 if (__predict_false(tx_start_bd->nbytes > hlen)) {
5498 fp->eth_q_stats.tx_ofld_frames_lso_hdr_splits++;
5500 /* split the first BD into header/data making the fw job easy */
5502 tx_start_bd->nbd = htole16(nbds);
5503 tx_start_bd->nbytes = htole16(hlen);
5505 bd_prod = TX_BD_NEXT(bd_prod);
5507 /* new transmit BD after the tx_parse_bd */
5508 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5509 tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hlen));
5510 tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hlen));
5511 tx_data_bd->nbytes = htole16(segs[0].ds_len - hlen);
5512 if (tx_total_pkt_size_bd == NULL) {
5513 tx_total_pkt_size_bd = tx_data_bd;
5517 "TSO split header size is %d (%x:%x) nbds %d\n",
5518 le16toh(tx_start_bd->nbytes),
5519 le32toh(tx_start_bd->addr_hi),
5520 le32toh(tx_start_bd->addr_lo),
5524 if (!CHIP_IS_E1x(sc)) {
5525 bxe_set_pbd_lso_e2(m0, &pbd_e2_parsing_data);
5527 bxe_set_pbd_lso(m0, pbd_e1x);
5531 if (pbd_e2_parsing_data) {
5532 pbd_e2->parsing_data = htole32(pbd_e2_parsing_data);
5535 /* prepare remaining BDs, start tx bd contains first seg/frag */
5536 for (i = 1; i < nsegs ; i++) {
5537 bd_prod = TX_BD_NEXT(bd_prod);
5538 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5539 tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr));
5540 tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr));
5541 tx_data_bd->nbytes = htole16(segs[i].ds_len);
5542 if (tx_total_pkt_size_bd == NULL) {
5543 tx_total_pkt_size_bd = tx_data_bd;
5545 total_pkt_size += tx_data_bd->nbytes;
5548 BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd);
5550 if (tx_total_pkt_size_bd != NULL) {
5551 tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size;
5554 if (__predict_false(sc->debug & DBG_TX)) {
5555 tmp_bd = tx_buf->first_bd;
5556 for (i = 0; i < nbds; i++)
5560 "TX Strt: %p bd=%d nbd=%d vlan=0x%x "
5561 "bd_flags=0x%x hdr_nbds=%d\n",
5564 le16toh(tx_start_bd->nbd),
5565 le16toh(tx_start_bd->vlan_or_ethertype),
5566 tx_start_bd->bd_flags.as_bitfield,
5567 (tx_start_bd->general_data & ETH_TX_START_BD_HDR_NBDS));
5568 } else if (i == 1) {
5571 "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u "
5572 "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x "
5573 "tcp_seq=%u total_hlen_w=%u\n",
5576 pbd_e1x->global_data,
5581 pbd_e1x->tcp_pseudo_csum,
5582 pbd_e1x->tcp_send_seq,
5583 le16toh(pbd_e1x->total_hlen_w));
5584 } else { /* if (pbd_e2) */
5586 "-> Parse: %p bd=%d dst=%02x:%02x:%02x "
5587 "src=%02x:%02x:%02x parsing_data=0x%x\n",
5590 pbd_e2->data.mac_addr.dst_hi,
5591 pbd_e2->data.mac_addr.dst_mid,
5592 pbd_e2->data.mac_addr.dst_lo,
5593 pbd_e2->data.mac_addr.src_hi,
5594 pbd_e2->data.mac_addr.src_mid,
5595 pbd_e2->data.mac_addr.src_lo,
5596 pbd_e2->parsing_data);
5600 if (i != 1) { /* skip parse db as it doesn't hold data */
5601 tx_data_bd = &fp->tx_chain[TX_BD(tmp_bd)].reg_bd;
5603 "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n",
5606 le16toh(tx_data_bd->nbytes),
5607 le32toh(tx_data_bd->addr_hi),
5608 le32toh(tx_data_bd->addr_lo));
5611 tmp_bd = TX_BD_NEXT(tmp_bd);
5615 BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod);
5617 /* update TX BD producer index value for next TX */
5618 bd_prod = TX_BD_NEXT(bd_prod);
5621 * If the chain of tx_bd's describing this frame is adjacent to or spans
5622 * an eth_tx_next_bd element then we need to increment the nbds value.
5624 if (TX_BD_IDX(bd_prod) < nbds) {
5628 /* don't allow reordering of writes for nbd and packets */
5631 fp->tx_db.data.prod += nbds;
5633 /* producer points to the next free tx_bd at this point */
5635 fp->tx_bd_prod = bd_prod;
5637 DOORBELL(sc, fp->index, fp->tx_db.raw);
5639 fp->eth_q_stats.tx_pkts++;
5641 /* Prevent speculative reads from getting ahead of the status block. */
5642 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle,
5643 0, 0, BUS_SPACE_BARRIER_READ);
5645 /* Prevent speculative reads from getting ahead of the doorbell. */
5646 bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle,
5647 0, 0, BUS_SPACE_BARRIER_READ);
5653 bxe_tx_start_locked(struct bxe_softc *sc,
5655 struct bxe_fastpath *fp)
5657 struct mbuf *m = NULL;
5659 uint16_t tx_bd_avail;
5661 BXE_FP_TX_LOCK_ASSERT(fp);
5663 /* keep adding entries while there are frames to send */
5664 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
5667 * check for any frames to send
5668 * dequeue can still be NULL even if queue is not empty
5670 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
5671 if (__predict_false(m == NULL)) {
5675 /* the mbuf now belongs to us */
5676 fp->eth_q_stats.mbuf_alloc_tx++;
5679 * Put the frame into the transmit ring. If we don't have room,
5680 * place the mbuf back at the head of the TX queue, set the
5681 * OACTIVE flag, and wait for the NIC to drain the chain.
5683 if (__predict_false(bxe_tx_encap(fp, &m))) {
5684 fp->eth_q_stats.tx_encap_failures++;
5686 /* mark the TX queue as full and return the frame */
5687 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5688 IFQ_DRV_PREPEND(&ifp->if_snd, m);
5689 fp->eth_q_stats.mbuf_alloc_tx--;
5690 fp->eth_q_stats.tx_queue_xoff++;
5693 /* stop looking for more work */
5697 /* the frame was enqueued successfully */
5700 /* send a copy of the frame to any BPF listeners. */
5703 tx_bd_avail = bxe_tx_avail(sc, fp);
5705 /* handle any completions if we're running low */
5706 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5707 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5709 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
5715 /* all TX packets were dequeued and/or the tx ring is full */
5717 /* reset the TX watchdog timeout timer */
5718 fp->watchdog_timer = BXE_TX_TIMEOUT;
5722 /* Legacy (non-RSS) dispatch routine */
5724 bxe_tx_start(struct ifnet *ifp)
5726 struct bxe_softc *sc;
5727 struct bxe_fastpath *fp;
5731 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5732 BLOGW(sc, "Interface not running, ignoring transmit request\n");
5736 if (!sc->link_vars.link_up) {
5737 BLOGW(sc, "Interface link is down, ignoring transmit request\n");
5743 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
5744 fp->eth_q_stats.tx_queue_full_return++;
5749 bxe_tx_start_locked(sc, ifp, fp);
5750 BXE_FP_TX_UNLOCK(fp);
5753 #if __FreeBSD_version >= 800000
5756 bxe_tx_mq_start_locked(struct bxe_softc *sc,
5758 struct bxe_fastpath *fp,
5761 struct buf_ring *tx_br = fp->tx_br;
5763 int depth, rc, tx_count;
5764 uint16_t tx_bd_avail;
5768 BXE_FP_TX_LOCK_ASSERT(fp);
5771 BLOGE(sc, "Multiqueue TX and no buf_ring!\n");
5775 if (!sc->link_vars.link_up ||
5776 (ifp->if_drv_flags &
5777 (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING) {
5778 rc = drbr_enqueue(ifp, tx_br, m);
5779 goto bxe_tx_mq_start_locked_exit;
5782 /* fetch the depth of the driver queue */
5783 depth = drbr_inuse(ifp, tx_br);
5784 if (depth > fp->eth_q_stats.tx_max_drbr_queue_depth) {
5785 fp->eth_q_stats.tx_max_drbr_queue_depth = depth;
5789 /* no new work, check for pending frames */
5790 next = drbr_dequeue(ifp, tx_br);
5791 } else if (drbr_needs_enqueue(ifp, tx_br)) {
5792 /* have both new and pending work, maintain packet order */
5793 rc = drbr_enqueue(ifp, tx_br, m);
5795 fp->eth_q_stats.tx_soft_errors++;
5796 goto bxe_tx_mq_start_locked_exit;
5798 next = drbr_dequeue(ifp, tx_br);
5800 /* new work only and nothing pending */
5804 /* keep adding entries while there are frames to send */
5805 while (next != NULL) {
5807 /* the mbuf now belongs to us */
5808 fp->eth_q_stats.mbuf_alloc_tx++;
5811 * Put the frame into the transmit ring. If we don't have room,
5812 * place the mbuf back at the head of the TX queue, set the
5813 * OACTIVE flag, and wait for the NIC to drain the chain.
5815 rc = bxe_tx_encap(fp, &next);
5816 if (__predict_false(rc != 0)) {
5817 fp->eth_q_stats.tx_encap_failures++;
5819 /* mark the TX queue as full and save the frame */
5820 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5821 /* XXX this may reorder the frame */
5822 rc = drbr_enqueue(ifp, tx_br, next);
5823 fp->eth_q_stats.mbuf_alloc_tx--;
5824 fp->eth_q_stats.tx_frames_deferred++;
5827 /* stop looking for more work */
5831 /* the transmit frame was enqueued successfully */
5834 /* send a copy of the frame to any BPF listeners */
5835 BPF_MTAP(ifp, next);
5837 tx_bd_avail = bxe_tx_avail(sc, fp);
5839 /* handle any completions if we're running low */
5840 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5841 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5843 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
5848 next = drbr_dequeue(ifp, tx_br);
5851 /* all TX packets were dequeued and/or the tx ring is full */
5853 /* reset the TX watchdog timeout timer */
5854 fp->watchdog_timer = BXE_TX_TIMEOUT;
5857 bxe_tx_mq_start_locked_exit:
5862 /* Multiqueue (TSS) dispatch routine. */
5864 bxe_tx_mq_start(struct ifnet *ifp,
5867 struct bxe_softc *sc = ifp->if_softc;
5868 struct bxe_fastpath *fp;
5871 fp_index = 0; /* default is the first queue */
5873 /* check if flowid is set */
5875 if (BXE_VALID_FLOWID(m))
5876 fp_index = (m->m_pkthdr.flowid % sc->num_queues);
5878 fp = &sc->fp[fp_index];
5880 if (BXE_FP_TX_TRYLOCK(fp)) {
5881 rc = bxe_tx_mq_start_locked(sc, ifp, fp, m);
5882 BXE_FP_TX_UNLOCK(fp);
5884 rc = drbr_enqueue(ifp, fp->tx_br, m);
5890 bxe_mq_flush(struct ifnet *ifp)
5892 struct bxe_softc *sc = ifp->if_softc;
5893 struct bxe_fastpath *fp;
5897 for (i = 0; i < sc->num_queues; i++) {
5900 if (fp->state != BXE_FP_STATE_OPEN) {
5901 BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n",
5902 fp->index, fp->state);
5906 if (fp->tx_br != NULL) {
5907 BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index);
5909 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) {
5912 BXE_FP_TX_UNLOCK(fp);
5919 #endif /* FreeBSD_version >= 800000 */
5922 bxe_cid_ilt_lines(struct bxe_softc *sc)
5925 return ((BXE_FIRST_VF_CID + BXE_VF_CIDS) / ILT_PAGE_CIDS);
5927 return (L2_ILT_LINES(sc));
5931 bxe_ilt_set_info(struct bxe_softc *sc)
5933 struct ilt_client_info *ilt_client;
5934 struct ecore_ilt *ilt = sc->ilt;
5937 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
5938 BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line);
5941 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
5942 ilt_client->client_num = ILT_CLIENT_CDU;
5943 ilt_client->page_size = CDU_ILT_PAGE_SZ;
5944 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
5945 ilt_client->start = line;
5946 line += bxe_cid_ilt_lines(sc);
5948 if (CNIC_SUPPORT(sc)) {
5949 line += CNIC_ILT_LINES;
5952 ilt_client->end = (line - 1);
5955 "ilt client[CDU]: start %d, end %d, "
5956 "psz 0x%x, flags 0x%x, hw psz %d\n",
5957 ilt_client->start, ilt_client->end,
5958 ilt_client->page_size,
5960 ilog2(ilt_client->page_size >> 12));
5963 if (QM_INIT(sc->qm_cid_count)) {
5964 ilt_client = &ilt->clients[ILT_CLIENT_QM];
5965 ilt_client->client_num = ILT_CLIENT_QM;
5966 ilt_client->page_size = QM_ILT_PAGE_SZ;
5967 ilt_client->flags = 0;
5968 ilt_client->start = line;
5970 /* 4 bytes for each cid */
5971 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
5974 ilt_client->end = (line - 1);
5977 "ilt client[QM]: start %d, end %d, "
5978 "psz 0x%x, flags 0x%x, hw psz %d\n",
5979 ilt_client->start, ilt_client->end,
5980 ilt_client->page_size, ilt_client->flags,
5981 ilog2(ilt_client->page_size >> 12));
5984 if (CNIC_SUPPORT(sc)) {
5986 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
5987 ilt_client->client_num = ILT_CLIENT_SRC;
5988 ilt_client->page_size = SRC_ILT_PAGE_SZ;
5989 ilt_client->flags = 0;
5990 ilt_client->start = line;
5991 line += SRC_ILT_LINES;
5992 ilt_client->end = (line - 1);
5995 "ilt client[SRC]: start %d, end %d, "
5996 "psz 0x%x, flags 0x%x, hw psz %d\n",
5997 ilt_client->start, ilt_client->end,
5998 ilt_client->page_size, ilt_client->flags,
5999 ilog2(ilt_client->page_size >> 12));
6002 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6003 ilt_client->client_num = ILT_CLIENT_TM;
6004 ilt_client->page_size = TM_ILT_PAGE_SZ;
6005 ilt_client->flags = 0;
6006 ilt_client->start = line;
6007 line += TM_ILT_LINES;
6008 ilt_client->end = (line - 1);
6011 "ilt client[TM]: start %d, end %d, "
6012 "psz 0x%x, flags 0x%x, hw psz %d\n",
6013 ilt_client->start, ilt_client->end,
6014 ilt_client->page_size, ilt_client->flags,
6015 ilog2(ilt_client->page_size >> 12));
6018 KASSERT((line <= ILT_MAX_LINES), ("Invalid number of ILT lines!"));
6022 bxe_set_fp_rx_buf_size(struct bxe_softc *sc)
6025 uint32_t rx_buf_size;
6027 rx_buf_size = (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
6029 for (i = 0; i < sc->num_queues; i++) {
6030 if(rx_buf_size <= MCLBYTES){
6031 sc->fp[i].rx_buf_size = rx_buf_size;
6032 sc->fp[i].mbuf_alloc_size = MCLBYTES;
6033 }else if (rx_buf_size <= MJUMPAGESIZE){
6034 sc->fp[i].rx_buf_size = rx_buf_size;
6035 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
6036 }else if (rx_buf_size <= (MJUMPAGESIZE + MCLBYTES)){
6037 sc->fp[i].rx_buf_size = MCLBYTES;
6038 sc->fp[i].mbuf_alloc_size = MCLBYTES;
6039 }else if (rx_buf_size <= (2 * MJUMPAGESIZE)){
6040 sc->fp[i].rx_buf_size = MJUMPAGESIZE;
6041 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
6043 sc->fp[i].rx_buf_size = MCLBYTES;
6044 sc->fp[i].mbuf_alloc_size = MCLBYTES;
6050 bxe_alloc_ilt_mem(struct bxe_softc *sc)
6055 (struct ecore_ilt *)malloc(sizeof(struct ecore_ilt),
6057 (M_NOWAIT | M_ZERO))) == NULL) {
6065 bxe_alloc_ilt_lines_mem(struct bxe_softc *sc)
6069 if ((sc->ilt->lines =
6070 (struct ilt_line *)malloc((sizeof(struct ilt_line) * ILT_MAX_LINES),
6072 (M_NOWAIT | M_ZERO))) == NULL) {
6080 bxe_free_ilt_mem(struct bxe_softc *sc)
6082 if (sc->ilt != NULL) {
6083 free(sc->ilt, M_BXE_ILT);
6089 bxe_free_ilt_lines_mem(struct bxe_softc *sc)
6091 if (sc->ilt->lines != NULL) {
6092 free(sc->ilt->lines, M_BXE_ILT);
6093 sc->ilt->lines = NULL;
6098 bxe_free_mem(struct bxe_softc *sc)
6102 for (i = 0; i < L2_ILT_LINES(sc); i++) {
6103 bxe_dma_free(sc, &sc->context[i].vcxt_dma);
6104 sc->context[i].vcxt = NULL;
6105 sc->context[i].size = 0;
6108 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
6110 bxe_free_ilt_lines_mem(sc);
6115 bxe_alloc_mem(struct bxe_softc *sc)
6122 * Allocate memory for CDU context:
6123 * This memory is allocated separately and not in the generic ILT
6124 * functions because CDU differs in few aspects:
6125 * 1. There can be multiple entities allocating memory for context -
6126 * regular L2, CNIC, and SRIOV drivers. Each separately controls
6127 * its own ILT lines.
6128 * 2. Since CDU page-size is not a single 4KB page (which is the case
6129 * for the other ILT clients), to be efficient we want to support
6130 * allocation of sub-page-size in the last entry.
6131 * 3. Context pointers are used by the driver to pass to FW / update
6132 * the context (for the other ILT clients the pointers are used just to
6133 * free the memory during unload).
6135 context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc));
6136 for (i = 0, allocated = 0; allocated < context_size; i++) {
6137 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
6138 (context_size - allocated));
6140 if (bxe_dma_alloc(sc, sc->context[i].size,
6141 &sc->context[i].vcxt_dma,
6142 "cdu context") != 0) {
6147 sc->context[i].vcxt =
6148 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
6150 allocated += sc->context[i].size;
6153 bxe_alloc_ilt_lines_mem(sc);
6155 BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n",
6156 sc->ilt, sc->ilt->start_line, sc->ilt->lines);
6158 for (i = 0; i < 4; i++) {
6160 "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n",
6162 sc->ilt->clients[i].page_size,
6163 sc->ilt->clients[i].start,
6164 sc->ilt->clients[i].end,
6165 sc->ilt->clients[i].client_num,
6166 sc->ilt->clients[i].flags);
6169 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
6170 BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n");
6179 bxe_free_rx_bd_chain(struct bxe_fastpath *fp)
6181 struct bxe_softc *sc;
6186 if (fp->rx_mbuf_tag == NULL) {
6190 /* free all mbufs and unload all maps */
6191 for (i = 0; i < RX_BD_TOTAL; i++) {
6192 if (fp->rx_mbuf_chain[i].m_map != NULL) {
6193 bus_dmamap_sync(fp->rx_mbuf_tag,
6194 fp->rx_mbuf_chain[i].m_map,
6195 BUS_DMASYNC_POSTREAD);
6196 bus_dmamap_unload(fp->rx_mbuf_tag,
6197 fp->rx_mbuf_chain[i].m_map);
6200 if (fp->rx_mbuf_chain[i].m != NULL) {
6201 m_freem(fp->rx_mbuf_chain[i].m);
6202 fp->rx_mbuf_chain[i].m = NULL;
6203 fp->eth_q_stats.mbuf_alloc_rx--;
6209 bxe_free_tpa_pool(struct bxe_fastpath *fp)
6211 struct bxe_softc *sc;
6212 int i, max_agg_queues;
6216 if (fp->rx_mbuf_tag == NULL) {
6220 max_agg_queues = MAX_AGG_QS(sc);
6222 /* release all mbufs and unload all DMA maps in the TPA pool */
6223 for (i = 0; i < max_agg_queues; i++) {
6224 if (fp->rx_tpa_info[i].bd.m_map != NULL) {
6225 bus_dmamap_sync(fp->rx_mbuf_tag,
6226 fp->rx_tpa_info[i].bd.m_map,
6227 BUS_DMASYNC_POSTREAD);
6228 bus_dmamap_unload(fp->rx_mbuf_tag,
6229 fp->rx_tpa_info[i].bd.m_map);
6232 if (fp->rx_tpa_info[i].bd.m != NULL) {
6233 m_freem(fp->rx_tpa_info[i].bd.m);
6234 fp->rx_tpa_info[i].bd.m = NULL;
6235 fp->eth_q_stats.mbuf_alloc_tpa--;
6241 bxe_free_sge_chain(struct bxe_fastpath *fp)
6243 struct bxe_softc *sc;
6248 if (fp->rx_sge_mbuf_tag == NULL) {
6252 /* rree all mbufs and unload all maps */
6253 for (i = 0; i < RX_SGE_TOTAL; i++) {
6254 if (fp->rx_sge_mbuf_chain[i].m_map != NULL) {
6255 bus_dmamap_sync(fp->rx_sge_mbuf_tag,
6256 fp->rx_sge_mbuf_chain[i].m_map,
6257 BUS_DMASYNC_POSTREAD);
6258 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
6259 fp->rx_sge_mbuf_chain[i].m_map);
6262 if (fp->rx_sge_mbuf_chain[i].m != NULL) {
6263 m_freem(fp->rx_sge_mbuf_chain[i].m);
6264 fp->rx_sge_mbuf_chain[i].m = NULL;
6265 fp->eth_q_stats.mbuf_alloc_sge--;
6271 bxe_free_fp_buffers(struct bxe_softc *sc)
6273 struct bxe_fastpath *fp;
6276 for (i = 0; i < sc->num_queues; i++) {
6279 #if __FreeBSD_version >= 800000
6280 if (fp->tx_br != NULL) {
6281 /* just in case bxe_mq_flush() wasn't called */
6282 if (mtx_initialized(&fp->tx_mtx)) {
6286 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL)
6288 BXE_FP_TX_UNLOCK(fp);
6293 /* free all RX buffers */
6294 bxe_free_rx_bd_chain(fp);
6295 bxe_free_tpa_pool(fp);
6296 bxe_free_sge_chain(fp);
6298 if (fp->eth_q_stats.mbuf_alloc_rx != 0) {
6299 BLOGE(sc, "failed to claim all rx mbufs (%d left)\n",
6300 fp->eth_q_stats.mbuf_alloc_rx);
6303 if (fp->eth_q_stats.mbuf_alloc_sge != 0) {
6304 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6305 fp->eth_q_stats.mbuf_alloc_sge);
6308 if (fp->eth_q_stats.mbuf_alloc_tpa != 0) {
6309 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6310 fp->eth_q_stats.mbuf_alloc_tpa);
6313 if (fp->eth_q_stats.mbuf_alloc_tx != 0) {
6314 BLOGE(sc, "failed to release tx mbufs (%d left)\n",
6315 fp->eth_q_stats.mbuf_alloc_tx);
6318 /* XXX verify all mbufs were reclaimed */
6323 bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
6324 uint16_t prev_index,
6327 struct bxe_sw_rx_bd *rx_buf;
6328 struct eth_rx_bd *rx_bd;
6329 bus_dma_segment_t segs[1];
6336 /* allocate the new RX BD mbuf */
6337 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6338 if (__predict_false(m == NULL)) {
6339 fp->eth_q_stats.mbuf_rx_bd_alloc_failed++;
6343 fp->eth_q_stats.mbuf_alloc_rx++;
6345 /* initialize the mbuf buffer length */
6346 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6348 /* map the mbuf into non-paged pool */
6349 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6350 fp->rx_mbuf_spare_map,
6351 m, segs, &nsegs, BUS_DMA_NOWAIT);
6352 if (__predict_false(rc != 0)) {
6353 fp->eth_q_stats.mbuf_rx_bd_mapping_failed++;
6355 fp->eth_q_stats.mbuf_alloc_rx--;
6359 /* all mbufs must map to a single segment */
6360 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6362 /* release any existing RX BD mbuf mappings */
6364 if (prev_index != index) {
6365 rx_buf = &fp->rx_mbuf_chain[prev_index];
6367 if (rx_buf->m_map != NULL) {
6368 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6369 BUS_DMASYNC_POSTREAD);
6370 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6374 * We only get here from bxe_rxeof() when the maximum number
6375 * of rx buffers is less than RX_BD_USABLE. bxe_rxeof() already
6376 * holds the mbuf in the prev_index so it's OK to NULL it out
6377 * here without concern of a memory leak.
6379 fp->rx_mbuf_chain[prev_index].m = NULL;
6382 rx_buf = &fp->rx_mbuf_chain[index];
6384 if (rx_buf->m_map != NULL) {
6385 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6386 BUS_DMASYNC_POSTREAD);
6387 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6390 /* save the mbuf and mapping info for a future packet */
6391 map = (prev_index != index) ?
6392 fp->rx_mbuf_chain[prev_index].m_map : rx_buf->m_map;
6393 rx_buf->m_map = fp->rx_mbuf_spare_map;
6394 fp->rx_mbuf_spare_map = map;
6395 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6396 BUS_DMASYNC_PREREAD);
6399 rx_bd = &fp->rx_chain[index];
6400 rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6401 rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6407 bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
6410 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
6411 bus_dma_segment_t segs[1];
6417 /* allocate the new TPA mbuf */
6418 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6419 if (__predict_false(m == NULL)) {
6420 fp->eth_q_stats.mbuf_rx_tpa_alloc_failed++;
6424 fp->eth_q_stats.mbuf_alloc_tpa++;
6426 /* initialize the mbuf buffer length */
6427 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6429 /* map the mbuf into non-paged pool */
6430 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6431 fp->rx_tpa_info_mbuf_spare_map,
6432 m, segs, &nsegs, BUS_DMA_NOWAIT);
6433 if (__predict_false(rc != 0)) {
6434 fp->eth_q_stats.mbuf_rx_tpa_mapping_failed++;
6436 fp->eth_q_stats.mbuf_alloc_tpa--;
6440 /* all mbufs must map to a single segment */
6441 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6443 /* release any existing TPA mbuf mapping */
6444 if (tpa_info->bd.m_map != NULL) {
6445 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6446 BUS_DMASYNC_POSTREAD);
6447 bus_dmamap_unload(fp->rx_mbuf_tag, tpa_info->bd.m_map);
6450 /* save the mbuf and mapping info for the TPA mbuf */
6451 map = tpa_info->bd.m_map;
6452 tpa_info->bd.m_map = fp->rx_tpa_info_mbuf_spare_map;
6453 fp->rx_tpa_info_mbuf_spare_map = map;
6454 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6455 BUS_DMASYNC_PREREAD);
6457 tpa_info->seg = segs[0];
6463 * Allocate an mbuf and assign it to the receive scatter gather chain. The
6464 * caller must take care to save a copy of the existing mbuf in the SG mbuf
6468 bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
6471 struct bxe_sw_rx_bd *sge_buf;
6472 struct eth_rx_sge *sge;
6473 bus_dma_segment_t segs[1];
6479 /* allocate a new SGE mbuf */
6480 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE);
6481 if (__predict_false(m == NULL)) {
6482 fp->eth_q_stats.mbuf_rx_sge_alloc_failed++;
6486 fp->eth_q_stats.mbuf_alloc_sge++;
6488 /* initialize the mbuf buffer length */
6489 m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE;
6491 /* map the SGE mbuf into non-paged pool */
6492 rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_mbuf_tag,
6493 fp->rx_sge_mbuf_spare_map,
6494 m, segs, &nsegs, BUS_DMA_NOWAIT);
6495 if (__predict_false(rc != 0)) {
6496 fp->eth_q_stats.mbuf_rx_sge_mapping_failed++;
6498 fp->eth_q_stats.mbuf_alloc_sge--;
6502 /* all mbufs must map to a single segment */
6503 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6505 sge_buf = &fp->rx_sge_mbuf_chain[index];
6507 /* release any existing SGE mbuf mapping */
6508 if (sge_buf->m_map != NULL) {
6509 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6510 BUS_DMASYNC_POSTREAD);
6511 bus_dmamap_unload(fp->rx_sge_mbuf_tag, sge_buf->m_map);
6514 /* save the mbuf and mapping info for a future packet */
6515 map = sge_buf->m_map;
6516 sge_buf->m_map = fp->rx_sge_mbuf_spare_map;
6517 fp->rx_sge_mbuf_spare_map = map;
6518 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6519 BUS_DMASYNC_PREREAD);
6522 sge = &fp->rx_sge_chain[index];
6523 sge->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6524 sge->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6529 static __noinline int
6530 bxe_alloc_fp_buffers(struct bxe_softc *sc)
6532 struct bxe_fastpath *fp;
6534 int ring_prod, cqe_ring_prod;
6537 for (i = 0; i < sc->num_queues; i++) {
6540 ring_prod = cqe_ring_prod = 0;
6544 /* allocate buffers for the RX BDs in RX BD chain */
6545 for (j = 0; j < sc->max_rx_bufs; j++) {
6546 rc = bxe_alloc_rx_bd_mbuf(fp, ring_prod, ring_prod);
6548 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
6550 goto bxe_alloc_fp_buffers_error;
6553 ring_prod = RX_BD_NEXT(ring_prod);
6554 cqe_ring_prod = RCQ_NEXT(cqe_ring_prod);
6557 fp->rx_bd_prod = ring_prod;
6558 fp->rx_cq_prod = cqe_ring_prod;
6559 fp->eth_q_stats.rx_calls = fp->eth_q_stats.rx_pkts = 0;
6561 max_agg_queues = MAX_AGG_QS(sc);
6563 fp->tpa_enable = TRUE;
6565 /* fill the TPA pool */
6566 for (j = 0; j < max_agg_queues; j++) {
6567 rc = bxe_alloc_rx_tpa_mbuf(fp, j);
6569 BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n",
6571 fp->tpa_enable = FALSE;
6572 goto bxe_alloc_fp_buffers_error;
6575 fp->rx_tpa_info[j].state = BXE_TPA_STATE_STOP;
6578 if (fp->tpa_enable) {
6579 /* fill the RX SGE chain */
6581 for (j = 0; j < RX_SGE_USABLE; j++) {
6582 rc = bxe_alloc_rx_sge_mbuf(fp, ring_prod);
6584 BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n",
6586 fp->tpa_enable = FALSE;
6588 goto bxe_alloc_fp_buffers_error;
6591 ring_prod = RX_SGE_NEXT(ring_prod);
6594 fp->rx_sge_prod = ring_prod;
6600 bxe_alloc_fp_buffers_error:
6602 /* unwind what was already allocated */
6603 bxe_free_rx_bd_chain(fp);
6604 bxe_free_tpa_pool(fp);
6605 bxe_free_sge_chain(fp);
6611 bxe_free_fw_stats_mem(struct bxe_softc *sc)
6613 bxe_dma_free(sc, &sc->fw_stats_dma);
6615 sc->fw_stats_num = 0;
6617 sc->fw_stats_req_size = 0;
6618 sc->fw_stats_req = NULL;
6619 sc->fw_stats_req_mapping = 0;
6621 sc->fw_stats_data_size = 0;
6622 sc->fw_stats_data = NULL;
6623 sc->fw_stats_data_mapping = 0;
6627 bxe_alloc_fw_stats_mem(struct bxe_softc *sc)
6629 uint8_t num_queue_stats;
6632 /* number of queues for statistics is number of eth queues */
6633 num_queue_stats = BXE_NUM_ETH_QUEUES(sc);
6636 * Total number of FW statistics requests =
6637 * 1 for port stats + 1 for PF stats + num of queues
6639 sc->fw_stats_num = (2 + num_queue_stats);
6642 * Request is built from stats_query_header and an array of
6643 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
6644 * rules. The real number or requests is configured in the
6645 * stats_query_header.
6648 ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) +
6649 ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0));
6651 BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n",
6652 sc->fw_stats_num, num_groups);
6654 sc->fw_stats_req_size =
6655 (sizeof(struct stats_query_header) +
6656 (num_groups * sizeof(struct stats_query_cmd_group)));
6659 * Data for statistics requests + stats_counter.
6660 * stats_counter holds per-STORM counters that are incremented when
6661 * STORM has finished with the current request. Memory for FCoE
6662 * offloaded statistics are counted anyway, even if they will not be sent.
6663 * VF stats are not accounted for here as the data of VF stats is stored
6664 * in memory allocated by the VF, not here.
6666 sc->fw_stats_data_size =
6667 (sizeof(struct stats_counter) +
6668 sizeof(struct per_port_stats) +
6669 sizeof(struct per_pf_stats) +
6670 /* sizeof(struct fcoe_statistics_params) + */
6671 (sizeof(struct per_queue_stats) * num_queue_stats));
6673 if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
6674 &sc->fw_stats_dma, "fw stats") != 0) {
6675 bxe_free_fw_stats_mem(sc);
6679 /* set up the shortcuts */
6682 (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr;
6683 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
6686 (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr +
6687 sc->fw_stats_req_size);
6688 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
6689 sc->fw_stats_req_size);
6691 BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n",
6692 (uintmax_t)sc->fw_stats_req_mapping);
6694 BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n",
6695 (uintmax_t)sc->fw_stats_data_mapping);
6702 * 0-7 - Engine0 load counter.
6703 * 8-15 - Engine1 load counter.
6704 * 16 - Engine0 RESET_IN_PROGRESS bit.
6705 * 17 - Engine1 RESET_IN_PROGRESS bit.
6706 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
6707 * function on the engine
6708 * 19 - Engine1 ONE_IS_LOADED.
6709 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
6710 * leader to complete (check for both RESET_IN_PROGRESS bits and not
6711 * for just the one belonging to its engine).
6713 #define BXE_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
6714 #define BXE_PATH0_LOAD_CNT_MASK 0x000000ff
6715 #define BXE_PATH0_LOAD_CNT_SHIFT 0
6716 #define BXE_PATH1_LOAD_CNT_MASK 0x0000ff00
6717 #define BXE_PATH1_LOAD_CNT_SHIFT 8
6718 #define BXE_PATH0_RST_IN_PROG_BIT 0x00010000
6719 #define BXE_PATH1_RST_IN_PROG_BIT 0x00020000
6720 #define BXE_GLOBAL_RESET_BIT 0x00040000
6722 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
6724 bxe_set_reset_global(struct bxe_softc *sc)
6727 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6728 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6729 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT);
6730 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6733 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
6735 bxe_clear_reset_global(struct bxe_softc *sc)
6738 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6739 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6740 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT));
6741 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6744 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
6746 bxe_reset_is_global(struct bxe_softc *sc)
6748 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6749 BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val);
6750 return (val & BXE_GLOBAL_RESET_BIT) ? TRUE : FALSE;
6753 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
6755 bxe_set_reset_done(struct bxe_softc *sc)
6758 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
6759 BXE_PATH0_RST_IN_PROG_BIT;
6761 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6763 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6766 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6768 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6771 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
6773 bxe_set_reset_in_progress(struct bxe_softc *sc)
6776 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
6777 BXE_PATH0_RST_IN_PROG_BIT;
6779 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6781 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6784 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6786 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6789 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
6791 bxe_reset_is_done(struct bxe_softc *sc,
6794 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6795 uint32_t bit = engine ? BXE_PATH1_RST_IN_PROG_BIT :
6796 BXE_PATH0_RST_IN_PROG_BIT;
6798 /* return false if bit is set */
6799 return (val & bit) ? FALSE : TRUE;
6802 /* get the load status for an engine, should be run under rtnl lock */
6804 bxe_get_load_status(struct bxe_softc *sc,
6807 uint32_t mask = engine ? BXE_PATH1_LOAD_CNT_MASK :
6808 BXE_PATH0_LOAD_CNT_MASK;
6809 uint32_t shift = engine ? BXE_PATH1_LOAD_CNT_SHIFT :
6810 BXE_PATH0_LOAD_CNT_SHIFT;
6811 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6813 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
6815 val = ((val & mask) >> shift);
6817 BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val);
6822 /* set pf load mark */
6823 /* XXX needs to be under rtnl lock */
6825 bxe_set_pf_load(struct bxe_softc *sc)
6829 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
6830 BXE_PATH0_LOAD_CNT_MASK;
6831 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
6832 BXE_PATH0_LOAD_CNT_SHIFT;
6834 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6836 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6837 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
6839 /* get the current counter value */
6840 val1 = ((val & mask) >> shift);
6842 /* set bit of this PF */
6843 val1 |= (1 << SC_ABS_FUNC(sc));
6845 /* clear the old value */
6848 /* set the new one */
6849 val |= ((val1 << shift) & mask);
6851 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6853 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6856 /* clear pf load mark */
6857 /* XXX needs to be under rtnl lock */
6859 bxe_clear_pf_load(struct bxe_softc *sc)
6862 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
6863 BXE_PATH0_LOAD_CNT_MASK;
6864 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
6865 BXE_PATH0_LOAD_CNT_SHIFT;
6867 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6868 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6869 BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val);
6871 /* get the current counter value */
6872 val1 = (val & mask) >> shift;
6874 /* clear bit of that PF */
6875 val1 &= ~(1 << SC_ABS_FUNC(sc));
6877 /* clear the old value */
6880 /* set the new one */
6881 val |= ((val1 << shift) & mask);
6883 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6884 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6888 /* send load requrest to mcp and analyze response */
6890 bxe_nic_load_request(struct bxe_softc *sc,
6891 uint32_t *load_code)
6895 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
6896 DRV_MSG_SEQ_NUMBER_MASK);
6898 BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq);
6900 /* get the current FW pulse sequence */
6901 sc->fw_drv_pulse_wr_seq =
6902 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
6903 DRV_PULSE_SEQ_MASK);
6905 BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n",
6906 sc->fw_drv_pulse_wr_seq);
6909 (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6910 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6912 /* if the MCP fails to respond we must abort */
6913 if (!(*load_code)) {
6914 BLOGE(sc, "MCP response failure!\n");
6918 /* if MCP refused then must abort */
6919 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
6920 BLOGE(sc, "MCP refused load request\n");
6928 * Check whether another PF has already loaded FW to chip. In virtualized
6929 * environments a pf from anoth VM may have already initialized the device
6930 * including loading FW.
6933 bxe_nic_load_analyze_req(struct bxe_softc *sc,
6936 uint32_t my_fw, loaded_fw;
6938 /* is another pf loaded on this engine? */
6939 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6940 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6941 /* build my FW version dword */
6942 my_fw = (BCM_5710_FW_MAJOR_VERSION +
6943 (BCM_5710_FW_MINOR_VERSION << 8 ) +
6944 (BCM_5710_FW_REVISION_VERSION << 16) +
6945 (BCM_5710_FW_ENGINEERING_VERSION << 24));
6947 /* read loaded FW from chip */
6948 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
6949 BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n",
6952 /* abort nic load if version mismatch */
6953 if (my_fw != loaded_fw) {
6954 BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)",
6963 /* mark PMF if applicable */
6965 bxe_nic_load_pmf(struct bxe_softc *sc,
6968 uint32_t ncsi_oem_data_addr;
6970 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
6971 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
6972 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
6974 * Barrier here for ordering between the writing to sc->port.pmf here
6975 * and reading it from the periodic task.
6983 BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf);
6986 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
6987 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
6988 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
6989 if (ncsi_oem_data_addr) {
6991 (ncsi_oem_data_addr +
6992 offsetof(struct glob_ncsi_oem_data, driver_version)),
7000 bxe_read_mf_cfg(struct bxe_softc *sc)
7002 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
7006 if (BXE_NOMCP(sc)) {
7007 return; /* what should be the default bvalue in this case */
7011 * The formula for computing the absolute function number is...
7012 * For 2 port configuration (4 functions per port):
7013 * abs_func = 2 * vn + SC_PORT + SC_PATH
7014 * For 4 port configuration (2 functions per port):
7015 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
7017 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
7018 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
7019 if (abs_func >= E1H_FUNC_MAX) {
7022 sc->devinfo.mf_info.mf_config[vn] =
7023 MFCFG_RD(sc, func_mf_config[abs_func].config);
7026 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
7027 FUNC_MF_CFG_FUNC_DISABLED) {
7028 BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n");
7029 sc->flags |= BXE_MF_FUNC_DIS;
7031 BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n");
7032 sc->flags &= ~BXE_MF_FUNC_DIS;
7036 /* acquire split MCP access lock register */
7037 static int bxe_acquire_alr(struct bxe_softc *sc)
7041 for (j = 0; j < 1000; j++) {
7043 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
7044 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
7045 if (val & (1L << 31))
7051 if (!(val & (1L << 31))) {
7052 BLOGE(sc, "Cannot acquire MCP access lock register\n");
7059 /* release split MCP access lock register */
7060 static void bxe_release_alr(struct bxe_softc *sc)
7062 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
7066 bxe_fan_failure(struct bxe_softc *sc)
7068 int port = SC_PORT(sc);
7069 uint32_t ext_phy_config;
7071 /* mark the failure */
7073 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
7075 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
7076 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
7077 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
7080 /* log the failure */
7081 BLOGW(sc, "Fan Failure has caused the driver to shutdown "
7082 "the card to prevent permanent damage. "
7083 "Please contact OEM Support for assistance\n");
7087 bxe_panic(sc, ("Schedule task to handle fan failure\n"));
7090 * Schedule device reset (unload)
7091 * This is due to some boards consuming sufficient power when driver is
7092 * up to overheat if fan fails.
7094 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state);
7095 schedule_delayed_work(&sc->sp_rtnl_task, 0);
7099 /* this function is called upon a link interrupt */
7101 bxe_link_attn(struct bxe_softc *sc)
7103 uint32_t pause_enabled = 0;
7104 struct host_port_stats *pstats;
7107 /* Make sure that we are synced with the current statistics */
7108 bxe_stats_handle(sc, STATS_EVENT_STOP);
7110 elink_link_update(&sc->link_params, &sc->link_vars);
7112 if (sc->link_vars.link_up) {
7114 /* dropless flow control */
7115 if (!CHIP_IS_E1(sc) && sc->dropless_fc) {
7118 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
7123 (BAR_USTRORM_INTMEM +
7124 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
7128 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
7129 pstats = BXE_SP(sc, port_stats);
7130 /* reset old mac stats */
7131 memset(&(pstats->mac_stx[0]), 0, sizeof(struct mac_stx));
7134 if (sc->state == BXE_STATE_OPEN) {
7135 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
7139 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
7140 cmng_fns = bxe_get_cmng_fns_mode(sc);
7142 if (cmng_fns != CMNG_FNS_NONE) {
7143 bxe_cmng_fns_init(sc, FALSE, cmng_fns);
7144 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7146 /* rate shaping and fairness are disabled */
7147 BLOGD(sc, DBG_LOAD, "single function mode without fairness\n");
7151 bxe_link_report_locked(sc);
7154 ; // XXX bxe_link_sync_notify(sc);
7159 bxe_attn_int_asserted(struct bxe_softc *sc,
7162 int port = SC_PORT(sc);
7163 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7164 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7165 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
7166 NIG_REG_MASK_INTERRUPT_PORT0;
7168 uint32_t nig_mask = 0;
7173 if (sc->attn_state & asserted) {
7174 BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted);
7177 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7179 aeu_mask = REG_RD(sc, aeu_addr);
7181 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n",
7182 aeu_mask, asserted);
7184 aeu_mask &= ~(asserted & 0x3ff);
7186 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
7188 REG_WR(sc, aeu_addr, aeu_mask);
7190 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7192 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
7193 sc->attn_state |= asserted;
7194 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
7196 if (asserted & ATTN_HARD_WIRED_MASK) {
7197 if (asserted & ATTN_NIG_FOR_FUNC) {
7199 bxe_acquire_phy_lock(sc);
7200 /* save nig interrupt mask */
7201 nig_mask = REG_RD(sc, nig_int_mask_addr);
7203 /* If nig_mask is not set, no need to call the update function */
7205 REG_WR(sc, nig_int_mask_addr, 0);
7210 /* handle unicore attn? */
7213 if (asserted & ATTN_SW_TIMER_4_FUNC) {
7214 BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n");
7217 if (asserted & GPIO_2_FUNC) {
7218 BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n");
7221 if (asserted & GPIO_3_FUNC) {
7222 BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n");
7225 if (asserted & GPIO_4_FUNC) {
7226 BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n");
7230 if (asserted & ATTN_GENERAL_ATTN_1) {
7231 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n");
7232 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
7234 if (asserted & ATTN_GENERAL_ATTN_2) {
7235 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n");
7236 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
7238 if (asserted & ATTN_GENERAL_ATTN_3) {
7239 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n");
7240 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
7243 if (asserted & ATTN_GENERAL_ATTN_4) {
7244 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n");
7245 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
7247 if (asserted & ATTN_GENERAL_ATTN_5) {
7248 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n");
7249 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
7251 if (asserted & ATTN_GENERAL_ATTN_6) {
7252 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n");
7253 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
7258 if (sc->devinfo.int_block == INT_BLOCK_HC) {
7259 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET);
7261 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
7264 BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n",
7266 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
7267 REG_WR(sc, reg_addr, asserted);
7269 /* now set back the mask */
7270 if (asserted & ATTN_NIG_FOR_FUNC) {
7272 * Verify that IGU ack through BAR was written before restoring
7273 * NIG mask. This loop should exit after 2-3 iterations max.
7275 if (sc->devinfo.int_block != INT_BLOCK_HC) {
7279 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
7280 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
7281 (++cnt < MAX_IGU_ATTN_ACK_TO));
7284 BLOGE(sc, "Failed to verify IGU ack on time\n");
7290 REG_WR(sc, nig_int_mask_addr, nig_mask);
7292 bxe_release_phy_lock(sc);
7297 bxe_print_next_block(struct bxe_softc *sc,
7301 BLOGI(sc, "%s%s", idx ? ", " : "", blk);
7305 bxe_check_blocks_with_parity0(struct bxe_softc *sc,
7310 uint32_t cur_bit = 0;
7313 for (i = 0; sig; i++) {
7314 cur_bit = ((uint32_t)0x1 << i);
7315 if (sig & cur_bit) {
7317 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
7319 bxe_print_next_block(sc, par_num++, "BRB");
7321 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
7323 bxe_print_next_block(sc, par_num++, "PARSER");
7325 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
7327 bxe_print_next_block(sc, par_num++, "TSDM");
7329 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
7331 bxe_print_next_block(sc, par_num++, "SEARCHER");
7333 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
7335 bxe_print_next_block(sc, par_num++, "TCM");
7337 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
7339 bxe_print_next_block(sc, par_num++, "TSEMI");
7341 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
7343 bxe_print_next_block(sc, par_num++, "XPB");
7356 bxe_check_blocks_with_parity1(struct bxe_softc *sc,
7363 uint32_t cur_bit = 0;
7364 for (i = 0; sig; i++) {
7365 cur_bit = ((uint32_t)0x1 << i);
7366 if (sig & cur_bit) {
7368 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
7370 bxe_print_next_block(sc, par_num++, "PBF");
7372 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
7374 bxe_print_next_block(sc, par_num++, "QM");
7376 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
7378 bxe_print_next_block(sc, par_num++, "TM");
7380 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
7382 bxe_print_next_block(sc, par_num++, "XSDM");
7384 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
7386 bxe_print_next_block(sc, par_num++, "XCM");
7388 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
7390 bxe_print_next_block(sc, par_num++, "XSEMI");
7392 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
7394 bxe_print_next_block(sc, par_num++, "DOORBELLQ");
7396 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
7398 bxe_print_next_block(sc, par_num++, "NIG");
7400 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
7402 bxe_print_next_block(sc, par_num++, "VAUX PCI CORE");
7405 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
7407 bxe_print_next_block(sc, par_num++, "DEBUG");
7409 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
7411 bxe_print_next_block(sc, par_num++, "USDM");
7413 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
7415 bxe_print_next_block(sc, par_num++, "UCM");
7417 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
7419 bxe_print_next_block(sc, par_num++, "USEMI");
7421 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
7423 bxe_print_next_block(sc, par_num++, "UPB");
7425 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
7427 bxe_print_next_block(sc, par_num++, "CSDM");
7429 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
7431 bxe_print_next_block(sc, par_num++, "CCM");
7444 bxe_check_blocks_with_parity2(struct bxe_softc *sc,
7449 uint32_t cur_bit = 0;
7452 for (i = 0; sig; i++) {
7453 cur_bit = ((uint32_t)0x1 << i);
7454 if (sig & cur_bit) {
7456 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
7458 bxe_print_next_block(sc, par_num++, "CSEMI");
7460 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
7462 bxe_print_next_block(sc, par_num++, "PXP");
7464 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
7466 bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT");
7468 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
7470 bxe_print_next_block(sc, par_num++, "CFC");
7472 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
7474 bxe_print_next_block(sc, par_num++, "CDU");
7476 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
7478 bxe_print_next_block(sc, par_num++, "DMAE");
7480 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
7482 bxe_print_next_block(sc, par_num++, "IGU");
7484 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
7486 bxe_print_next_block(sc, par_num++, "MISC");
7499 bxe_check_blocks_with_parity3(struct bxe_softc *sc,
7505 uint32_t cur_bit = 0;
7508 for (i = 0; sig; i++) {
7509 cur_bit = ((uint32_t)0x1 << i);
7510 if (sig & cur_bit) {
7512 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
7514 bxe_print_next_block(sc, par_num++, "MCP ROM");
7517 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
7519 bxe_print_next_block(sc, par_num++,
7523 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
7525 bxe_print_next_block(sc, par_num++,
7529 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
7531 bxe_print_next_block(sc, par_num++,
7546 bxe_check_blocks_with_parity4(struct bxe_softc *sc,
7551 uint32_t cur_bit = 0;
7554 for (i = 0; sig; i++) {
7555 cur_bit = ((uint32_t)0x1 << i);
7556 if (sig & cur_bit) {
7558 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
7560 bxe_print_next_block(sc, par_num++, "PGLUE_B");
7562 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
7564 bxe_print_next_block(sc, par_num++, "ATC");
7577 bxe_parity_attn(struct bxe_softc *sc,
7584 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
7585 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
7586 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
7587 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
7588 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
7589 BLOGE(sc, "Parity error: HW block parity attention:\n"
7590 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
7591 (uint32_t)(sig[0] & HW_PRTY_ASSERT_SET_0),
7592 (uint32_t)(sig[1] & HW_PRTY_ASSERT_SET_1),
7593 (uint32_t)(sig[2] & HW_PRTY_ASSERT_SET_2),
7594 (uint32_t)(sig[3] & HW_PRTY_ASSERT_SET_3),
7595 (uint32_t)(sig[4] & HW_PRTY_ASSERT_SET_4));
7598 BLOGI(sc, "Parity errors detected in blocks: ");
7601 bxe_check_blocks_with_parity0(sc, sig[0] &
7602 HW_PRTY_ASSERT_SET_0,
7605 bxe_check_blocks_with_parity1(sc, sig[1] &
7606 HW_PRTY_ASSERT_SET_1,
7607 par_num, global, print);
7609 bxe_check_blocks_with_parity2(sc, sig[2] &
7610 HW_PRTY_ASSERT_SET_2,
7613 bxe_check_blocks_with_parity3(sc, sig[3] &
7614 HW_PRTY_ASSERT_SET_3,
7615 par_num, global, print);
7617 bxe_check_blocks_with_parity4(sc, sig[4] &
7618 HW_PRTY_ASSERT_SET_4,
7631 bxe_chk_parity_attn(struct bxe_softc *sc,
7635 struct attn_route attn = { {0} };
7636 int port = SC_PORT(sc);
7638 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
7639 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
7640 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
7641 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
7644 * Since MCP attentions can't be disabled inside the block, we need to
7645 * read AEU registers to see whether they're currently disabled
7647 attn.sig[3] &= ((REG_RD(sc, (!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
7648 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0)) &
7649 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
7650 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
7653 if (!CHIP_IS_E1x(sc))
7654 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
7656 return (bxe_parity_attn(sc, global, print, attn.sig));
7660 bxe_attn_int_deasserted4(struct bxe_softc *sc,
7665 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
7666 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
7667 BLOGE(sc, "PGLUE hw attention 0x%08x\n", val);
7668 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
7669 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
7670 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
7671 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
7672 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
7673 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
7674 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
7675 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
7676 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
7677 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
7678 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
7679 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
7680 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
7681 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
7682 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
7683 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
7684 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
7685 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
7688 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
7689 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
7690 BLOGE(sc, "ATC hw attention 0x%08x\n", val);
7691 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
7692 BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
7693 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
7694 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
7695 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
7696 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
7697 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
7698 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
7699 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
7700 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
7701 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
7702 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
7705 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7706 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
7707 BLOGE(sc, "FATAL parity attention set4 0x%08x\n",
7708 (uint32_t)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7709 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
7714 bxe_e1h_disable(struct bxe_softc *sc)
7716 int port = SC_PORT(sc);
7720 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7724 bxe_e1h_enable(struct bxe_softc *sc)
7726 int port = SC_PORT(sc);
7728 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7730 // XXX bxe_tx_enable(sc);
7734 * called due to MCP event (on pmf):
7735 * reread new bandwidth configuration
7737 * notify others function about the change
7740 bxe_config_mf_bw(struct bxe_softc *sc)
7742 if (sc->link_vars.link_up) {
7743 bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
7744 // XXX bxe_link_sync_notify(sc);
7747 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7751 bxe_set_mf_bw(struct bxe_softc *sc)
7753 bxe_config_mf_bw(sc);
7754 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
7758 bxe_handle_eee_event(struct bxe_softc *sc)
7760 BLOGD(sc, DBG_INTR, "EEE - LLDP event\n");
7761 bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
7764 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
7767 bxe_drv_info_ether_stat(struct bxe_softc *sc)
7769 struct eth_stats_info *ether_stat =
7770 &sc->sp->drv_info_to_mcp.ether_stat;
7772 strlcpy(ether_stat->version, BXE_DRIVER_VERSION,
7773 ETH_STAT_INFO_VERSION_LEN);
7775 /* XXX (+ MAC_PAD) taken from other driver... verify this is right */
7776 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
7777 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
7778 ether_stat->mac_local + MAC_PAD,
7781 ether_stat->mtu_size = sc->mtu;
7783 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
7784 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) {
7785 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
7788 // XXX ether_stat->feature_flags |= ???;
7790 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
7792 ether_stat->txq_size = sc->tx_ring_size;
7793 ether_stat->rxq_size = sc->rx_ring_size;
7797 bxe_handle_drv_info_req(struct bxe_softc *sc)
7799 enum drv_info_opcode op_code;
7800 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
7802 /* if drv_info version supported by MFW doesn't match - send NACK */
7803 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
7804 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
7808 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
7809 DRV_INFO_CONTROL_OP_CODE_SHIFT);
7811 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
7814 case ETH_STATS_OPCODE:
7815 bxe_drv_info_ether_stat(sc);
7817 case FCOE_STATS_OPCODE:
7818 case ISCSI_STATS_OPCODE:
7820 /* if op code isn't supported - send NACK */
7821 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
7826 * If we got drv_info attn from MFW then these fields are defined in
7829 SHMEM2_WR(sc, drv_info_host_addr_lo,
7830 U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
7831 SHMEM2_WR(sc, drv_info_host_addr_hi,
7832 U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
7834 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
7838 bxe_dcc_event(struct bxe_softc *sc,
7841 BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event);
7843 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
7845 * This is the only place besides the function initialization
7846 * where the sc->flags can change so it is done without any
7849 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
7850 BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n");
7851 sc->flags |= BXE_MF_FUNC_DIS;
7852 bxe_e1h_disable(sc);
7854 BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n");
7855 sc->flags &= ~BXE_MF_FUNC_DIS;
7858 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
7861 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
7862 bxe_config_mf_bw(sc);
7863 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
7866 /* Report results to MCP */
7868 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
7870 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
7874 bxe_pmf_update(struct bxe_softc *sc)
7876 int port = SC_PORT(sc);
7880 BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf);
7883 * We need the mb() to ensure the ordering between the writing to
7884 * sc->port.pmf here and reading it from the bxe_periodic_task().
7888 /* queue a periodic task */
7889 // XXX schedule task...
7891 // XXX bxe_dcbx_pmf_update(sc);
7893 /* enable nig attention */
7894 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
7895 if (sc->devinfo.int_block == INT_BLOCK_HC) {
7896 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val);
7897 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val);
7898 } else if (!CHIP_IS_E1x(sc)) {
7899 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
7900 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
7903 bxe_stats_handle(sc, STATS_EVENT_PMF);
7907 bxe_mc_assert(struct bxe_softc *sc)
7911 uint32_t row0, row1, row2, row3;
7914 last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
7916 BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7918 /* print the asserts */
7919 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7921 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
7922 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4);
7923 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8);
7924 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12);
7926 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7927 BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7928 i, row3, row2, row1, row0);
7936 last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
7938 BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7941 /* print the asserts */
7942 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7944 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
7945 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4);
7946 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8);
7947 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12);
7949 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7950 BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7951 i, row3, row2, row1, row0);
7959 last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
7961 BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7964 /* print the asserts */
7965 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7967 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
7968 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4);
7969 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8);
7970 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12);
7972 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7973 BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7974 i, row3, row2, row1, row0);
7982 last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
7984 BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7987 /* print the asserts */
7988 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7990 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
7991 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4);
7992 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8);
7993 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12);
7995 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7996 BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7997 i, row3, row2, row1, row0);
8008 bxe_attn_int_deasserted3(struct bxe_softc *sc,
8011 int func = SC_FUNC(sc);
8014 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
8016 if (attn & BXE_PMF_LINK_ASSERT(sc)) {
8018 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8019 bxe_read_mf_cfg(sc);
8020 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
8021 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8022 val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
8024 if (val & DRV_STATUS_DCC_EVENT_MASK)
8025 bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK));
8027 if (val & DRV_STATUS_SET_MF_BW)
8030 if (val & DRV_STATUS_DRV_INFO_REQ)
8031 bxe_handle_drv_info_req(sc);
8033 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
8036 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
8037 bxe_handle_eee_event(sc);
8039 if (sc->link_vars.periodic_flags &
8040 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
8041 /* sync with link */
8042 bxe_acquire_phy_lock(sc);
8043 sc->link_vars.periodic_flags &=
8044 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
8045 bxe_release_phy_lock(sc);
8047 ; // XXX bxe_link_sync_notify(sc);
8048 bxe_link_report(sc);
8052 * Always call it here: bxe_link_report() will
8053 * prevent the link indication duplication.
8055 bxe_link_status_update(sc);
8057 } else if (attn & BXE_MC_ASSERT_BITS) {
8059 BLOGE(sc, "MC assert!\n");
8061 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
8062 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
8063 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
8064 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
8065 bxe_panic(sc, ("MC assert!\n"));
8067 } else if (attn & BXE_MCP_ASSERT) {
8069 BLOGE(sc, "MCP assert!\n");
8070 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
8071 // XXX bxe_fw_dump(sc);
8074 BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn);
8078 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
8079 BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn);
8080 if (attn & BXE_GRC_TIMEOUT) {
8081 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
8082 BLOGE(sc, "GRC time-out 0x%08x\n", val);
8084 if (attn & BXE_GRC_RSV) {
8085 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
8086 BLOGE(sc, "GRC reserved 0x%08x\n", val);
8088 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
8093 bxe_attn_int_deasserted2(struct bxe_softc *sc,
8096 int port = SC_PORT(sc);
8098 uint32_t val0, mask0, val1, mask1;
8101 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
8102 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
8103 BLOGE(sc, "CFC hw attention 0x%08x\n", val);
8104 /* CFC error attention */
8106 BLOGE(sc, "FATAL error from CFC\n");
8110 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
8111 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
8112 BLOGE(sc, "PXP hw attention-0 0x%08x\n", val);
8113 /* RQ_USDMDP_FIFO_OVERFLOW */
8114 if (val & 0x18000) {
8115 BLOGE(sc, "FATAL error from PXP\n");
8118 if (!CHIP_IS_E1x(sc)) {
8119 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
8120 BLOGE(sc, "PXP hw attention-1 0x%08x\n", val);
8124 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
8125 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
8127 if (attn & AEU_PXP2_HW_INT_BIT) {
8128 /* CQ47854 workaround do not panic on
8129 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8131 if (!CHIP_IS_E1x(sc)) {
8132 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
8133 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
8134 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
8135 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
8137 * If the olny PXP2_EOP_ERROR_BIT is set in
8138 * STS0 and STS1 - clear it
8140 * probably we lose additional attentions between
8141 * STS0 and STS_CLR0, in this case user will not
8142 * be notified about them
8144 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
8146 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
8148 /* print the register, since no one can restore it */
8149 BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0);
8152 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8155 if (val0 & PXP2_EOP_ERROR_BIT) {
8156 BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n");
8159 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
8160 * set then clear attention from PXP2 block without panic
8162 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
8163 ((val1 & mask1) == 0))
8164 attn &= ~AEU_PXP2_HW_INT_BIT;
8169 if (attn & HW_INTERRUT_ASSERT_SET_2) {
8170 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
8171 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
8173 val = REG_RD(sc, reg_offset);
8174 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
8175 REG_WR(sc, reg_offset, val);
8177 BLOGE(sc, "FATAL HW block attention set2 0x%x\n",
8178 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_2));
8179 bxe_panic(sc, ("HW block attention set2\n"));
8184 bxe_attn_int_deasserted1(struct bxe_softc *sc,
8187 int port = SC_PORT(sc);
8191 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
8192 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
8193 BLOGE(sc, "DB hw attention 0x%08x\n", val);
8194 /* DORQ discard attention */
8196 BLOGE(sc, "FATAL error from DORQ\n");
8200 if (attn & HW_INTERRUT_ASSERT_SET_1) {
8201 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
8202 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
8204 val = REG_RD(sc, reg_offset);
8205 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
8206 REG_WR(sc, reg_offset, val);
8208 BLOGE(sc, "FATAL HW block attention set1 0x%08x\n",
8209 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_1));
8210 bxe_panic(sc, ("HW block attention set1\n"));
8215 bxe_attn_int_deasserted0(struct bxe_softc *sc,
8218 int port = SC_PORT(sc);
8222 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
8223 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
8225 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
8226 val = REG_RD(sc, reg_offset);
8227 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
8228 REG_WR(sc, reg_offset, val);
8230 BLOGW(sc, "SPIO5 hw attention\n");
8232 /* Fan failure attention */
8233 elink_hw_reset_phy(&sc->link_params);
8234 bxe_fan_failure(sc);
8237 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
8238 bxe_acquire_phy_lock(sc);
8239 elink_handle_module_detect_int(&sc->link_params);
8240 bxe_release_phy_lock(sc);
8243 if (attn & HW_INTERRUT_ASSERT_SET_0) {
8244 val = REG_RD(sc, reg_offset);
8245 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
8246 REG_WR(sc, reg_offset, val);
8248 bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n",
8249 (attn & HW_INTERRUT_ASSERT_SET_0)));
8254 bxe_attn_int_deasserted(struct bxe_softc *sc,
8255 uint32_t deasserted)
8257 struct attn_route attn;
8258 struct attn_route *group_mask;
8259 int port = SC_PORT(sc);
8264 uint8_t global = FALSE;
8267 * Need to take HW lock because MCP or other port might also
8268 * try to handle this event.
8270 bxe_acquire_alr(sc);
8272 if (bxe_chk_parity_attn(sc, &global, TRUE)) {
8274 * In case of parity errors don't handle attentions so that
8275 * other function would "see" parity errors.
8277 sc->recovery_state = BXE_RECOVERY_INIT;
8278 // XXX schedule a recovery task...
8279 /* disable HW interrupts */
8280 bxe_int_disable(sc);
8281 bxe_release_alr(sc);
8285 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
8286 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
8287 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
8288 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
8289 if (!CHIP_IS_E1x(sc)) {
8290 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
8295 BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
8296 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
8298 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
8299 if (deasserted & (1 << index)) {
8300 group_mask = &sc->attn_group[index];
8303 "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index,
8304 group_mask->sig[0], group_mask->sig[1],
8305 group_mask->sig[2], group_mask->sig[3],
8306 group_mask->sig[4]);
8308 bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]);
8309 bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]);
8310 bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]);
8311 bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]);
8312 bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]);
8316 bxe_release_alr(sc);
8318 if (sc->devinfo.int_block == INT_BLOCK_HC) {
8319 reg_addr = (HC_REG_COMMAND_REG + port*32 +
8320 COMMAND_REG_ATTN_BITS_CLR);
8322 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
8327 "about to mask 0x%08x at %s addr 0x%08x\n", val,
8328 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
8329 REG_WR(sc, reg_addr, val);
8331 if (~sc->attn_state & deasserted) {
8332 BLOGE(sc, "IGU error\n");
8335 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8336 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8338 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8340 aeu_mask = REG_RD(sc, reg_addr);
8342 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n",
8343 aeu_mask, deasserted);
8344 aeu_mask |= (deasserted & 0x3ff);
8345 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
8347 REG_WR(sc, reg_addr, aeu_mask);
8348 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8350 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
8351 sc->attn_state &= ~deasserted;
8352 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
8356 bxe_attn_int(struct bxe_softc *sc)
8358 /* read local copy of bits */
8359 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
8360 uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
8361 uint32_t attn_state = sc->attn_state;
8363 /* look for changed bits */
8364 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
8365 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
8368 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n",
8369 attn_bits, attn_ack, asserted, deasserted);
8371 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
8372 BLOGE(sc, "BAD attention state\n");
8375 /* handle bits that were raised */
8377 bxe_attn_int_asserted(sc, asserted);
8381 bxe_attn_int_deasserted(sc, deasserted);
8386 bxe_update_dsb_idx(struct bxe_softc *sc)
8388 struct host_sp_status_block *def_sb = sc->def_sb;
8391 mb(); /* status block is written to by the chip */
8393 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
8394 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
8395 rc |= BXE_DEF_SB_ATT_IDX;
8398 if (sc->def_idx != def_sb->sp_sb.running_index) {
8399 sc->def_idx = def_sb->sp_sb.running_index;
8400 rc |= BXE_DEF_SB_IDX;
8408 static inline struct ecore_queue_sp_obj *
8409 bxe_cid_to_q_obj(struct bxe_softc *sc,
8412 BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid);
8413 return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj);
8417 bxe_handle_mcast_eqe(struct bxe_softc *sc)
8419 struct ecore_mcast_ramrod_params rparam;
8422 memset(&rparam, 0, sizeof(rparam));
8424 rparam.mcast_obj = &sc->mcast_obj;
8428 /* clear pending state for the last command */
8429 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
8431 /* if there are pending mcast commands - send them */
8432 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
8433 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
8436 "ERROR: Failed to send pending mcast commands (%d)\n", rc);
8440 BXE_MCAST_UNLOCK(sc);
8444 bxe_handle_classification_eqe(struct bxe_softc *sc,
8445 union event_ring_elem *elem)
8447 unsigned long ramrod_flags = 0;
8449 uint32_t cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8450 struct ecore_vlan_mac_obj *vlan_mac_obj;
8452 /* always push next commands out, don't wait here */
8453 bit_set(&ramrod_flags, RAMROD_CONT);
8455 switch (le32toh(elem->message.data.eth_event.echo) >> BXE_SWCID_SHIFT) {
8456 case ECORE_FILTER_MAC_PENDING:
8457 BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n");
8458 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
8461 case ECORE_FILTER_MCAST_PENDING:
8462 BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n");
8464 * This is only relevant for 57710 where multicast MACs are
8465 * configured as unicast MACs using the same ramrod.
8467 bxe_handle_mcast_eqe(sc);
8471 BLOGE(sc, "Unsupported classification command: %d\n",
8472 elem->message.data.eth_event.echo);
8476 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
8479 BLOGE(sc, "Failed to schedule new commands (%d)\n", rc);
8480 } else if (rc > 0) {
8481 BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n");
8486 bxe_handle_rx_mode_eqe(struct bxe_softc *sc,
8487 union event_ring_elem *elem)
8489 bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
8491 /* send rx_mode command again if was requested */
8492 if (bxe_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED,
8494 bxe_set_storm_rx_mode(sc);
8499 bxe_update_eq_prod(struct bxe_softc *sc,
8502 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
8503 wmb(); /* keep prod updates ordered */
8507 bxe_eq_int(struct bxe_softc *sc)
8509 uint16_t hw_cons, sw_cons, sw_prod;
8510 union event_ring_elem *elem;
8515 struct ecore_queue_sp_obj *q_obj;
8516 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
8517 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
8519 hw_cons = le16toh(*sc->eq_cons_sb);
8522 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
8523 * when we get to the next-page we need to adjust so the loop
8524 * condition below will be met. The next element is the size of a
8525 * regular element and hence incrementing by 1
8527 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
8532 * This function may never run in parallel with itself for a
8533 * specific sc and no need for a read memory barrier here.
8535 sw_cons = sc->eq_cons;
8536 sw_prod = sc->eq_prod;
8538 BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n",
8539 hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left));
8543 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
8545 elem = &sc->eq[EQ_DESC(sw_cons)];
8547 /* elem CID originates from FW, actually LE */
8548 cid = SW_CID(elem->message.data.cfc_del_event.cid);
8549 opcode = elem->message.opcode;
8551 /* handle eq element */
8554 case EVENT_RING_OPCODE_STAT_QUERY:
8555 BLOGD(sc, DBG_SP, "got statistics completion event %d\n",
8557 /* nothing to do with stats comp */
8560 case EVENT_RING_OPCODE_CFC_DEL:
8561 /* handle according to cid range */
8562 /* we may want to verify here that the sc state is HALTING */
8563 BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid);
8564 q_obj = bxe_cid_to_q_obj(sc, cid);
8565 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
8570 case EVENT_RING_OPCODE_STOP_TRAFFIC:
8571 BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n");
8572 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
8575 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_PAUSED);
8578 case EVENT_RING_OPCODE_START_TRAFFIC:
8579 BLOGD(sc, DBG_SP, "got START TRAFFIC\n");
8580 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) {
8583 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_RELEASED);
8586 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
8587 echo = elem->message.data.function_update_event.echo;
8588 if (echo == SWITCH_UPDATE) {
8589 BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n");
8590 if (f_obj->complete_cmd(sc, f_obj,
8591 ECORE_F_CMD_SWITCH_UPDATE)) {
8597 "AFEX: ramrod completed FUNCTION_UPDATE\n");
8601 case EVENT_RING_OPCODE_FORWARD_SETUP:
8602 q_obj = &bxe_fwd_sp_obj(sc, q_obj);
8603 if (q_obj->complete_cmd(sc, q_obj,
8604 ECORE_Q_CMD_SETUP_TX_ONLY)) {
8609 case EVENT_RING_OPCODE_FUNCTION_START:
8610 BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n");
8611 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
8616 case EVENT_RING_OPCODE_FUNCTION_STOP:
8617 BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n");
8618 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
8624 switch (opcode | sc->state) {
8625 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPEN):
8626 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPENING_WAITING_PORT):
8627 cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8628 BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid);
8629 rss_raw->clear_pending(rss_raw);
8632 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_OPEN):
8633 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_DIAG):
8634 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_CLOSING_WAITING_HALT):
8635 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_OPEN):
8636 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_DIAG):
8637 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8638 BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n");
8639 bxe_handle_classification_eqe(sc, elem);
8642 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_OPEN):
8643 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_DIAG):
8644 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8645 BLOGD(sc, DBG_SP, "got mcast ramrod\n");
8646 bxe_handle_mcast_eqe(sc);
8649 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_OPEN):
8650 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_DIAG):
8651 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8652 BLOGD(sc, DBG_SP, "got rx_mode ramrod\n");
8653 bxe_handle_rx_mode_eqe(sc, elem);
8657 /* unknown event log error and continue */
8658 BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n",
8659 elem->message.opcode, sc->state);
8667 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
8669 sc->eq_cons = sw_cons;
8670 sc->eq_prod = sw_prod;
8672 /* make sure that above mem writes were issued towards the memory */
8675 /* update producer */
8676 bxe_update_eq_prod(sc, sc->eq_prod);
8680 bxe_handle_sp_tq(void *context,
8683 struct bxe_softc *sc = (struct bxe_softc *)context;
8686 BLOGD(sc, DBG_SP, "---> SP TASK <---\n");
8688 /* what work needs to be performed? */
8689 status = bxe_update_dsb_idx(sc);
8691 BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status);
8694 if (status & BXE_DEF_SB_ATT_IDX) {
8695 BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n");
8697 status &= ~BXE_DEF_SB_ATT_IDX;
8700 /* SP events: STAT_QUERY and others */
8701 if (status & BXE_DEF_SB_IDX) {
8702 /* handle EQ completions */
8703 BLOGD(sc, DBG_SP, "---> EQ INTR <---\n");
8705 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
8706 le16toh(sc->def_idx), IGU_INT_NOP, 1);
8707 status &= ~BXE_DEF_SB_IDX;
8710 /* if status is non zero then something went wrong */
8711 if (__predict_false(status)) {
8712 BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status);
8715 /* ack status block only if something was actually handled */
8716 bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
8717 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
8720 * Must be called after the EQ processing (since eq leads to sriov
8721 * ramrod completion flows).
8722 * This flow may have been scheduled by the arrival of a ramrod
8723 * completion, or by the sriov code rescheduling itself.
8725 // XXX bxe_iov_sp_task(sc);
8730 bxe_handle_fp_tq(void *context,
8733 struct bxe_fastpath *fp = (struct bxe_fastpath *)context;
8734 struct bxe_softc *sc = fp->sc;
8735 uint8_t more_tx = FALSE;
8736 uint8_t more_rx = FALSE;
8738 BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index);
8741 * IFF_DRV_RUNNING state can't be checked here since we process
8742 * slowpath events on a client queue during setup. Instead
8743 * we need to add a "process/continue" flag here that the driver
8744 * can use to tell the task here not to do anything.
8747 if (!(sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
8752 /* update the fastpath index */
8753 bxe_update_fp_sb_idx(fp);
8755 /* XXX add loop here if ever support multiple tx CoS */
8756 /* fp->txdata[cos] */
8757 if (bxe_has_tx_work(fp)) {
8759 more_tx = bxe_txeof(sc, fp);
8760 BXE_FP_TX_UNLOCK(fp);
8763 if (bxe_has_rx_work(fp)) {
8764 more_rx = bxe_rxeof(sc, fp);
8767 if (more_rx /*|| more_tx*/) {
8768 /* still more work to do */
8769 taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
8773 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
8774 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
8778 bxe_task_fp(struct bxe_fastpath *fp)
8780 struct bxe_softc *sc = fp->sc;
8781 uint8_t more_tx = FALSE;
8782 uint8_t more_rx = FALSE;
8784 BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index);
8786 /* update the fastpath index */
8787 bxe_update_fp_sb_idx(fp);
8789 /* XXX add loop here if ever support multiple tx CoS */
8790 /* fp->txdata[cos] */
8791 if (bxe_has_tx_work(fp)) {
8793 more_tx = bxe_txeof(sc, fp);
8794 BXE_FP_TX_UNLOCK(fp);
8797 if (bxe_has_rx_work(fp)) {
8798 more_rx = bxe_rxeof(sc, fp);
8801 if (more_rx /*|| more_tx*/) {
8802 /* still more work to do, bail out if this ISR and process later */
8803 taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
8808 * Here we write the fastpath index taken before doing any tx or rx work.
8809 * It is very well possible other hw events occurred up to this point and
8810 * they were actually processed accordingly above. Since we're going to
8811 * write an older fastpath index, an interrupt is coming which we might
8812 * not do any work in.
8814 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
8815 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
8819 * Legacy interrupt entry point.
8821 * Verifies that the controller generated the interrupt and
8822 * then calls a separate routine to handle the various
8823 * interrupt causes: link, RX, and TX.
8826 bxe_intr_legacy(void *xsc)
8828 struct bxe_softc *sc = (struct bxe_softc *)xsc;
8829 struct bxe_fastpath *fp;
8830 uint16_t status, mask;
8833 BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n");
8836 * 0 for ustorm, 1 for cstorm
8837 * the bits returned from ack_int() are 0-15
8838 * bit 0 = attention status block
8839 * bit 1 = fast path status block
8840 * a mask of 0x2 or more = tx/rx event
8841 * a mask of 1 = slow path event
8844 status = bxe_ack_int(sc);
8846 /* the interrupt is not for us */
8847 if (__predict_false(status == 0)) {
8848 BLOGD(sc, DBG_INTR, "Not our interrupt!\n");
8852 BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status);
8854 FOR_EACH_ETH_QUEUE(sc, i) {
8856 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
8857 if (status & mask) {
8858 /* acknowledge and disable further fastpath interrupts */
8859 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8865 if (__predict_false(status & 0x1)) {
8866 /* acknowledge and disable further slowpath interrupts */
8867 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8869 /* schedule slowpath handler */
8870 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
8875 if (__predict_false(status)) {
8876 BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status);
8880 /* slowpath interrupt entry point */
8882 bxe_intr_sp(void *xsc)
8884 struct bxe_softc *sc = (struct bxe_softc *)xsc;
8886 BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n");
8888 /* acknowledge and disable further slowpath interrupts */
8889 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8891 /* schedule slowpath handler */
8892 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
8895 /* fastpath interrupt entry point */
8897 bxe_intr_fp(void *xfp)
8899 struct bxe_fastpath *fp = (struct bxe_fastpath *)xfp;
8900 struct bxe_softc *sc = fp->sc;
8902 BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index);
8905 "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n",
8906 curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id);
8908 /* acknowledge and disable further fastpath interrupts */
8909 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8914 /* Release all interrupts allocated by the driver. */
8916 bxe_interrupt_free(struct bxe_softc *sc)
8920 switch (sc->interrupt_mode) {
8921 case INTR_MODE_INTX:
8922 BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n");
8923 if (sc->intr[0].resource != NULL) {
8924 bus_release_resource(sc->dev,
8927 sc->intr[0].resource);
8931 for (i = 0; i < sc->intr_count; i++) {
8932 BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i);
8933 if (sc->intr[i].resource && sc->intr[i].rid) {
8934 bus_release_resource(sc->dev,
8937 sc->intr[i].resource);
8940 pci_release_msi(sc->dev);
8942 case INTR_MODE_MSIX:
8943 for (i = 0; i < sc->intr_count; i++) {
8944 BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i);
8945 if (sc->intr[i].resource && sc->intr[i].rid) {
8946 bus_release_resource(sc->dev,
8949 sc->intr[i].resource);
8952 pci_release_msi(sc->dev);
8955 /* nothing to do as initial allocation failed */
8961 * This function determines and allocates the appropriate
8962 * interrupt based on system capabilites and user request.
8964 * The user may force a particular interrupt mode, specify
8965 * the number of receive queues, specify the method for
8966 * distribuitng received frames to receive queues, or use
8967 * the default settings which will automatically select the
8968 * best supported combination. In addition, the OS may or
8969 * may not support certain combinations of these settings.
8970 * This routine attempts to reconcile the settings requested
8971 * by the user with the capabilites available from the system
8972 * to select the optimal combination of features.
8975 * 0 = Success, !0 = Failure.
8978 bxe_interrupt_alloc(struct bxe_softc *sc)
8982 int num_requested = 0;
8983 int num_allocated = 0;
8987 /* get the number of available MSI/MSI-X interrupts from the OS */
8988 if (sc->interrupt_mode > 0) {
8989 if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) {
8990 msix_count = pci_msix_count(sc->dev);
8993 if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) {
8994 msi_count = pci_msi_count(sc->dev);
8997 BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n",
8998 msi_count, msix_count);
9001 do { /* try allocating MSI-X interrupt resources (at least 2) */
9002 if (sc->interrupt_mode != INTR_MODE_MSIX) {
9006 if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) ||
9008 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9012 /* ask for the necessary number of MSI-X vectors */
9013 num_requested = min((sc->num_queues + 1), msix_count);
9015 BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested);
9017 num_allocated = num_requested;
9018 if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) {
9019 BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc);
9020 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9024 if (num_allocated < 2) { /* possible? */
9025 BLOGE(sc, "MSI-X allocation less than 2!\n");
9026 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9027 pci_release_msi(sc->dev);
9031 BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n",
9032 num_requested, num_allocated);
9034 /* best effort so use the number of vectors allocated to us */
9035 sc->intr_count = num_allocated;
9036 sc->num_queues = num_allocated - 1;
9038 rid = 1; /* initial resource identifier */
9040 /* allocate the MSI-X vectors */
9041 for (i = 0; i < num_allocated; i++) {
9042 sc->intr[i].rid = (rid + i);
9044 if ((sc->intr[i].resource =
9045 bus_alloc_resource_any(sc->dev,
9048 RF_ACTIVE)) == NULL) {
9049 BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n",
9052 for (j = (i - 1); j >= 0; j--) {
9053 bus_release_resource(sc->dev,
9056 sc->intr[j].resource);
9061 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9062 pci_release_msi(sc->dev);
9066 BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i));
9070 do { /* try allocating MSI vector resources (at least 2) */
9071 if (sc->interrupt_mode != INTR_MODE_MSI) {
9075 if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) ||
9077 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9081 /* ask for a single MSI vector */
9084 BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested);
9086 num_allocated = num_requested;
9087 if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) {
9088 BLOGE(sc, "MSI alloc failed (%d)!\n", rc);
9089 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9093 if (num_allocated != 1) { /* possible? */
9094 BLOGE(sc, "MSI allocation is not 1!\n");
9095 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9096 pci_release_msi(sc->dev);
9100 BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n",
9101 num_requested, num_allocated);
9103 /* best effort so use the number of vectors allocated to us */
9104 sc->intr_count = num_allocated;
9105 sc->num_queues = num_allocated;
9107 rid = 1; /* initial resource identifier */
9109 sc->intr[0].rid = rid;
9111 if ((sc->intr[0].resource =
9112 bus_alloc_resource_any(sc->dev,
9115 RF_ACTIVE)) == NULL) {
9116 BLOGE(sc, "Failed to map MSI[0] (rid=%d)!\n", rid);
9119 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9120 pci_release_msi(sc->dev);
9124 BLOGD(sc, DBG_LOAD, "Mapped MSI[0] (rid=%d)\n", rid);
9127 do { /* try allocating INTx vector resources */
9128 if (sc->interrupt_mode != INTR_MODE_INTX) {
9132 BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n");
9134 /* only one vector for INTx */
9138 rid = 0; /* initial resource identifier */
9140 sc->intr[0].rid = rid;
9142 if ((sc->intr[0].resource =
9143 bus_alloc_resource_any(sc->dev,
9146 (RF_ACTIVE | RF_SHAREABLE))) == NULL) {
9147 BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid);
9150 sc->interrupt_mode = -1; /* Failed! */
9154 BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid);
9157 if (sc->interrupt_mode == -1) {
9158 BLOGE(sc, "Interrupt Allocation: FAILED!!!\n");
9162 "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n",
9163 sc->interrupt_mode, sc->num_queues);
9171 bxe_interrupt_detach(struct bxe_softc *sc)
9173 struct bxe_fastpath *fp;
9176 /* release interrupt resources */
9177 for (i = 0; i < sc->intr_count; i++) {
9178 if (sc->intr[i].resource && sc->intr[i].tag) {
9179 BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i);
9180 bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag);
9184 for (i = 0; i < sc->num_queues; i++) {
9187 taskqueue_drain(fp->tq, &fp->tq_task);
9188 taskqueue_free(fp->tq);
9195 taskqueue_drain(sc->sp_tq, &sc->sp_tq_task);
9196 taskqueue_free(sc->sp_tq);
9202 * Enables interrupts and attach to the ISR.
9204 * When using multiple MSI/MSI-X vectors the first vector
9205 * is used for slowpath operations while all remaining
9206 * vectors are used for fastpath operations. If only a
9207 * single MSI/MSI-X vector is used (SINGLE_ISR) then the
9208 * ISR must look for both slowpath and fastpath completions.
9211 bxe_interrupt_attach(struct bxe_softc *sc)
9213 struct bxe_fastpath *fp;
9217 snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name),
9218 "bxe%d_sp_tq", sc->unit);
9219 TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc);
9220 sc->sp_tq = taskqueue_create_fast(sc->sp_tq_name, M_NOWAIT,
9221 taskqueue_thread_enqueue,
9223 taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */
9224 "%s", sc->sp_tq_name);
9227 for (i = 0; i < sc->num_queues; i++) {
9229 snprintf(fp->tq_name, sizeof(fp->tq_name),
9230 "bxe%d_fp%d_tq", sc->unit, i);
9231 TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp);
9232 fp->tq = taskqueue_create_fast(fp->tq_name, M_NOWAIT,
9233 taskqueue_thread_enqueue,
9235 taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */
9239 /* setup interrupt handlers */
9240 if (sc->interrupt_mode == INTR_MODE_MSIX) {
9241 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n");
9244 * Setup the interrupt handler. Note that we pass the driver instance
9245 * to the interrupt handler for the slowpath.
9247 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9248 (INTR_TYPE_NET | INTR_MPSAFE),
9249 NULL, bxe_intr_sp, sc,
9250 &sc->intr[0].tag)) != 0) {
9251 BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc);
9252 goto bxe_interrupt_attach_exit;
9255 bus_describe_intr(sc->dev, sc->intr[0].resource,
9256 sc->intr[0].tag, "sp");
9258 /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */
9260 /* initialize the fastpath vectors (note the first was used for sp) */
9261 for (i = 0; i < sc->num_queues; i++) {
9263 BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1));
9266 * Setup the interrupt handler. Note that we pass the
9267 * fastpath context to the interrupt handler in this
9270 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource,
9271 (INTR_TYPE_NET | INTR_MPSAFE),
9272 NULL, bxe_intr_fp, fp,
9273 &sc->intr[i + 1].tag)) != 0) {
9274 BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n",
9276 goto bxe_interrupt_attach_exit;
9279 bus_describe_intr(sc->dev, sc->intr[i + 1].resource,
9280 sc->intr[i + 1].tag, "fp%02d", i);
9282 /* bind the fastpath instance to a cpu */
9283 if (sc->num_queues > 1) {
9284 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i);
9287 fp->state = BXE_FP_STATE_IRQ;
9289 } else if (sc->interrupt_mode == INTR_MODE_MSI) {
9290 BLOGD(sc, DBG_LOAD, "Enabling MSI[0] vector\n");
9293 * Setup the interrupt handler. Note that we pass the
9294 * driver instance to the interrupt handler which
9295 * will handle both the slowpath and fastpath.
9297 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9298 (INTR_TYPE_NET | INTR_MPSAFE),
9299 NULL, bxe_intr_legacy, sc,
9300 &sc->intr[0].tag)) != 0) {
9301 BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc);
9302 goto bxe_interrupt_attach_exit;
9305 } else { /* (sc->interrupt_mode == INTR_MODE_INTX) */
9306 BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n");
9309 * Setup the interrupt handler. Note that we pass the
9310 * driver instance to the interrupt handler which
9311 * will handle both the slowpath and fastpath.
9313 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9314 (INTR_TYPE_NET | INTR_MPSAFE),
9315 NULL, bxe_intr_legacy, sc,
9316 &sc->intr[0].tag)) != 0) {
9317 BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc);
9318 goto bxe_interrupt_attach_exit;
9322 bxe_interrupt_attach_exit:
9327 static int bxe_init_hw_common_chip(struct bxe_softc *sc);
9328 static int bxe_init_hw_common(struct bxe_softc *sc);
9329 static int bxe_init_hw_port(struct bxe_softc *sc);
9330 static int bxe_init_hw_func(struct bxe_softc *sc);
9331 static void bxe_reset_common(struct bxe_softc *sc);
9332 static void bxe_reset_port(struct bxe_softc *sc);
9333 static void bxe_reset_func(struct bxe_softc *sc);
9334 static int bxe_gunzip_init(struct bxe_softc *sc);
9335 static void bxe_gunzip_end(struct bxe_softc *sc);
9336 static int bxe_init_firmware(struct bxe_softc *sc);
9337 static void bxe_release_firmware(struct bxe_softc *sc);
9340 ecore_func_sp_drv_ops bxe_func_sp_drv = {
9341 .init_hw_cmn_chip = bxe_init_hw_common_chip,
9342 .init_hw_cmn = bxe_init_hw_common,
9343 .init_hw_port = bxe_init_hw_port,
9344 .init_hw_func = bxe_init_hw_func,
9346 .reset_hw_cmn = bxe_reset_common,
9347 .reset_hw_port = bxe_reset_port,
9348 .reset_hw_func = bxe_reset_func,
9350 .gunzip_init = bxe_gunzip_init,
9351 .gunzip_end = bxe_gunzip_end,
9353 .init_fw = bxe_init_firmware,
9354 .release_fw = bxe_release_firmware,
9358 bxe_init_func_obj(struct bxe_softc *sc)
9362 ecore_init_func_obj(sc,
9364 BXE_SP(sc, func_rdata),
9365 BXE_SP_MAPPING(sc, func_rdata),
9366 BXE_SP(sc, func_afex_rdata),
9367 BXE_SP_MAPPING(sc, func_afex_rdata),
9372 bxe_init_hw(struct bxe_softc *sc,
9375 struct ecore_func_state_params func_params = { NULL };
9378 /* prepare the parameters for function state transitions */
9379 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
9381 func_params.f_obj = &sc->func_obj;
9382 func_params.cmd = ECORE_F_CMD_HW_INIT;
9384 func_params.params.hw_init.load_phase = load_code;
9387 * Via a plethora of function pointers, we will eventually reach
9388 * bxe_init_hw_common(), bxe_init_hw_port(), or bxe_init_hw_func().
9390 rc = ecore_func_state_change(sc, &func_params);
9396 bxe_fill(struct bxe_softc *sc,
9403 if (!(len % 4) && !(addr % 4)) {
9404 for (i = 0; i < len; i += 4) {
9405 REG_WR(sc, (addr + i), fill);
9408 for (i = 0; i < len; i++) {
9409 REG_WR8(sc, (addr + i), fill);
9414 /* writes FP SP data to FW - data_size in dwords */
9416 bxe_wr_fp_sb_data(struct bxe_softc *sc,
9418 uint32_t *sb_data_p,
9423 for (index = 0; index < data_size; index++) {
9425 (BAR_CSTRORM_INTMEM +
9426 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
9427 (sizeof(uint32_t) * index)),
9428 *(sb_data_p + index));
9433 bxe_zero_fp_sb(struct bxe_softc *sc,
9436 struct hc_status_block_data_e2 sb_data_e2;
9437 struct hc_status_block_data_e1x sb_data_e1x;
9438 uint32_t *sb_data_p;
9439 uint32_t data_size = 0;
9441 if (!CHIP_IS_E1x(sc)) {
9442 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9443 sb_data_e2.common.state = SB_DISABLED;
9444 sb_data_e2.common.p_func.vf_valid = FALSE;
9445 sb_data_p = (uint32_t *)&sb_data_e2;
9446 data_size = (sizeof(struct hc_status_block_data_e2) /
9449 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9450 sb_data_e1x.common.state = SB_DISABLED;
9451 sb_data_e1x.common.p_func.vf_valid = FALSE;
9452 sb_data_p = (uint32_t *)&sb_data_e1x;
9453 data_size = (sizeof(struct hc_status_block_data_e1x) /
9457 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9459 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)),
9460 0, CSTORM_STATUS_BLOCK_SIZE);
9461 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
9462 0, CSTORM_SYNC_BLOCK_SIZE);
9466 bxe_wr_sp_sb_data(struct bxe_softc *sc,
9467 struct hc_sp_status_block_data *sp_sb_data)
9472 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
9475 (BAR_CSTRORM_INTMEM +
9476 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
9477 (i * sizeof(uint32_t))),
9478 *((uint32_t *)sp_sb_data + i));
9483 bxe_zero_sp_sb(struct bxe_softc *sc)
9485 struct hc_sp_status_block_data sp_sb_data;
9487 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9489 sp_sb_data.state = SB_DISABLED;
9490 sp_sb_data.p_func.vf_valid = FALSE;
9492 bxe_wr_sp_sb_data(sc, &sp_sb_data);
9495 (BAR_CSTRORM_INTMEM +
9496 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
9497 0, CSTORM_SP_STATUS_BLOCK_SIZE);
9499 (BAR_CSTRORM_INTMEM +
9500 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
9501 0, CSTORM_SP_SYNC_BLOCK_SIZE);
9505 bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
9509 hc_sm->igu_sb_id = igu_sb_id;
9510 hc_sm->igu_seg_id = igu_seg_id;
9511 hc_sm->timer_value = 0xFF;
9512 hc_sm->time_to_expire = 0xFFFFFFFF;
9516 bxe_map_sb_state_machines(struct hc_index_data *index_data)
9518 /* zero out state machine indices */
9521 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9524 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9525 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
9526 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
9527 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
9532 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
9533 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9536 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
9537 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9538 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
9539 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9540 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
9541 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9542 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
9543 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9547 bxe_init_sb(struct bxe_softc *sc,
9554 struct hc_status_block_data_e2 sb_data_e2;
9555 struct hc_status_block_data_e1x sb_data_e1x;
9556 struct hc_status_block_sm *hc_sm_p;
9557 uint32_t *sb_data_p;
9561 if (CHIP_INT_MODE_IS_BC(sc)) {
9562 igu_seg_id = HC_SEG_ACCESS_NORM;
9564 igu_seg_id = IGU_SEG_ACCESS_NORM;
9567 bxe_zero_fp_sb(sc, fw_sb_id);
9569 if (!CHIP_IS_E1x(sc)) {
9570 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9571 sb_data_e2.common.state = SB_ENABLED;
9572 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
9573 sb_data_e2.common.p_func.vf_id = vfid;
9574 sb_data_e2.common.p_func.vf_valid = vf_valid;
9575 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
9576 sb_data_e2.common.same_igu_sb_1b = TRUE;
9577 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
9578 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
9579 hc_sm_p = sb_data_e2.common.state_machine;
9580 sb_data_p = (uint32_t *)&sb_data_e2;
9581 data_size = (sizeof(struct hc_status_block_data_e2) /
9583 bxe_map_sb_state_machines(sb_data_e2.index_data);
9585 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9586 sb_data_e1x.common.state = SB_ENABLED;
9587 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
9588 sb_data_e1x.common.p_func.vf_id = 0xff;
9589 sb_data_e1x.common.p_func.vf_valid = FALSE;
9590 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
9591 sb_data_e1x.common.same_igu_sb_1b = TRUE;
9592 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
9593 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
9594 hc_sm_p = sb_data_e1x.common.state_machine;
9595 sb_data_p = (uint32_t *)&sb_data_e1x;
9596 data_size = (sizeof(struct hc_status_block_data_e1x) /
9598 bxe_map_sb_state_machines(sb_data_e1x.index_data);
9601 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
9602 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
9604 BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id);
9606 /* write indices to HW - PCI guarantees endianity of regpairs */
9607 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9610 static inline uint8_t
9611 bxe_fp_qzone_id(struct bxe_fastpath *fp)
9613 if (CHIP_IS_E1x(fp->sc)) {
9614 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
9620 static inline uint32_t
9621 bxe_rx_ustorm_prods_offset(struct bxe_softc *sc,
9622 struct bxe_fastpath *fp)
9624 uint32_t offset = BAR_USTRORM_INTMEM;
9626 if (!CHIP_IS_E1x(sc)) {
9627 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
9629 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
9636 bxe_init_eth_fp(struct bxe_softc *sc,
9639 struct bxe_fastpath *fp = &sc->fp[idx];
9640 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
9641 unsigned long q_type = 0;
9647 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
9648 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
9650 fp->cl_id = (CHIP_IS_E1x(sc)) ?
9651 (SC_L_ID(sc) + idx) :
9652 /* want client ID same as IGU SB ID for non-E1 */
9654 fp->cl_qzone_id = bxe_fp_qzone_id(fp);
9656 /* setup sb indices */
9657 if (!CHIP_IS_E1x(sc)) {
9658 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
9659 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
9661 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
9662 fp->sb_running_index = fp->status_block.e1x_sb->sb.running_index;
9666 fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp);
9668 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
9671 * XXX If multiple CoS is ever supported then each fastpath structure
9672 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
9674 for (cos = 0; cos < sc->max_cos; cos++) {
9677 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
9679 /* nothing more for a VF to do */
9684 bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE,
9685 fp->fw_sb_id, fp->igu_sb_id);
9687 bxe_update_fp_sb_idx(fp);
9689 /* Configure Queue State object */
9690 bit_set(&q_type, ECORE_Q_TYPE_HAS_RX);
9691 bit_set(&q_type, ECORE_Q_TYPE_HAS_TX);
9693 ecore_init_queue_obj(sc,
9694 &sc->sp_objs[idx].q_obj,
9699 BXE_SP(sc, q_rdata),
9700 BXE_SP_MAPPING(sc, q_rdata),
9703 /* configure classification DBs */
9704 ecore_init_mac_obj(sc,
9705 &sc->sp_objs[idx].mac_obj,
9709 BXE_SP(sc, mac_rdata),
9710 BXE_SP_MAPPING(sc, mac_rdata),
9711 ECORE_FILTER_MAC_PENDING,
9713 ECORE_OBJ_TYPE_RX_TX,
9716 BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n",
9717 idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id);
9721 bxe_update_rx_prod(struct bxe_softc *sc,
9722 struct bxe_fastpath *fp,
9723 uint16_t rx_bd_prod,
9724 uint16_t rx_cq_prod,
9725 uint16_t rx_sge_prod)
9727 struct ustorm_eth_rx_producers rx_prods = { 0 };
9730 /* update producers */
9731 rx_prods.bd_prod = rx_bd_prod;
9732 rx_prods.cqe_prod = rx_cq_prod;
9733 rx_prods.sge_prod = rx_sge_prod;
9736 * Make sure that the BD and SGE data is updated before updating the
9737 * producers since FW might read the BD/SGE right after the producer
9739 * This is only applicable for weak-ordered memory model archs such
9740 * as IA-64. The following barrier is also mandatory since FW will
9741 * assumes BDs must have buffers.
9745 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
9747 (fp->ustorm_rx_prods_offset + (i * 4)),
9748 ((uint32_t *)&rx_prods)[i]);
9751 wmb(); /* keep prod updates ordered */
9754 "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n",
9755 fp->index, rx_bd_prod, rx_cq_prod, rx_sge_prod);
9759 bxe_init_rx_rings(struct bxe_softc *sc)
9761 struct bxe_fastpath *fp;
9764 for (i = 0; i < sc->num_queues; i++) {
9770 * Activate the BD ring...
9771 * Warning, this will generate an interrupt (to the TSTORM)
9772 * so this can only be done after the chip is initialized
9774 bxe_update_rx_prod(sc, fp,
9783 if (CHIP_IS_E1(sc)) {
9785 (BAR_USTRORM_INTMEM +
9786 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))),
9787 U64_LO(fp->rcq_dma.paddr));
9789 (BAR_USTRORM_INTMEM +
9790 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4),
9791 U64_HI(fp->rcq_dma.paddr));
9797 bxe_init_tx_ring_one(struct bxe_fastpath *fp)
9799 SET_FLAG(fp->tx_db.data.header.data, DOORBELL_HDR_T_DB_TYPE, 1);
9800 fp->tx_db.data.zero_fill1 = 0;
9801 fp->tx_db.data.prod = 0;
9803 fp->tx_pkt_prod = 0;
9804 fp->tx_pkt_cons = 0;
9807 fp->eth_q_stats.tx_pkts = 0;
9811 bxe_init_tx_rings(struct bxe_softc *sc)
9815 for (i = 0; i < sc->num_queues; i++) {
9816 bxe_init_tx_ring_one(&sc->fp[i]);
9821 bxe_init_def_sb(struct bxe_softc *sc)
9823 struct host_sp_status_block *def_sb = sc->def_sb;
9824 bus_addr_t mapping = sc->def_sb_dma.paddr;
9825 int igu_sp_sb_index;
9827 int port = SC_PORT(sc);
9828 int func = SC_FUNC(sc);
9829 int reg_offset, reg_offset_en5;
9832 struct hc_sp_status_block_data sp_sb_data;
9834 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9836 if (CHIP_INT_MODE_IS_BC(sc)) {
9837 igu_sp_sb_index = DEF_SB_IGU_ID;
9838 igu_seg_id = HC_SEG_ACCESS_DEF;
9840 igu_sp_sb_index = sc->igu_dsb_id;
9841 igu_seg_id = IGU_SEG_ACCESS_DEF;
9845 section = ((uint64_t)mapping +
9846 offsetof(struct host_sp_status_block, atten_status_block));
9847 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
9850 reg_offset = (port) ?
9851 MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
9852 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
9853 reg_offset_en5 = (port) ?
9854 MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
9855 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
9857 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
9858 /* take care of sig[0]..sig[4] */
9859 for (sindex = 0; sindex < 4; sindex++) {
9860 sc->attn_group[index].sig[sindex] =
9861 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index)));
9864 if (!CHIP_IS_E1x(sc)) {
9866 * enable5 is separate from the rest of the registers,
9867 * and the address skip is 4 and not 16 between the
9870 sc->attn_group[index].sig[4] =
9871 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
9873 sc->attn_group[index].sig[4] = 0;
9877 if (sc->devinfo.int_block == INT_BLOCK_HC) {
9878 reg_offset = (port) ?
9879 HC_REG_ATTN_MSG1_ADDR_L :
9880 HC_REG_ATTN_MSG0_ADDR_L;
9881 REG_WR(sc, reg_offset, U64_LO(section));
9882 REG_WR(sc, (reg_offset + 4), U64_HI(section));
9883 } else if (!CHIP_IS_E1x(sc)) {
9884 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
9885 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
9888 section = ((uint64_t)mapping +
9889 offsetof(struct host_sp_status_block, sp_sb));
9893 /* PCI guarantees endianity of regpair */
9894 sp_sb_data.state = SB_ENABLED;
9895 sp_sb_data.host_sb_addr.lo = U64_LO(section);
9896 sp_sb_data.host_sb_addr.hi = U64_HI(section);
9897 sp_sb_data.igu_sb_id = igu_sp_sb_index;
9898 sp_sb_data.igu_seg_id = igu_seg_id;
9899 sp_sb_data.p_func.pf_id = func;
9900 sp_sb_data.p_func.vnic_id = SC_VN(sc);
9901 sp_sb_data.p_func.vf_id = 0xff;
9903 bxe_wr_sp_sb_data(sc, &sp_sb_data);
9905 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
9909 bxe_init_sp_ring(struct bxe_softc *sc)
9911 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
9912 sc->spq_prod_idx = 0;
9913 sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
9914 sc->spq_prod_bd = sc->spq;
9915 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
9919 bxe_init_eq_ring(struct bxe_softc *sc)
9921 union event_ring_elem *elem;
9924 for (i = 1; i <= NUM_EQ_PAGES; i++) {
9925 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
9927 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
9929 (i % NUM_EQ_PAGES)));
9930 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
9932 (i % NUM_EQ_PAGES)));
9936 sc->eq_prod = NUM_EQ_DESC;
9937 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
9939 atomic_store_rel_long(&sc->eq_spq_left,
9940 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
9945 bxe_init_internal_common(struct bxe_softc *sc)
9950 * Zero this manually as its initialization is currently missing
9953 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
9955 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
9959 if (!CHIP_IS_E1x(sc)) {
9960 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
9961 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
9966 bxe_init_internal(struct bxe_softc *sc,
9969 switch (load_code) {
9970 case FW_MSG_CODE_DRV_LOAD_COMMON:
9971 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
9972 bxe_init_internal_common(sc);
9975 case FW_MSG_CODE_DRV_LOAD_PORT:
9979 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
9980 /* internal memory per function is initialized inside bxe_pf_init */
9984 BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code);
9990 storm_memset_func_cfg(struct bxe_softc *sc,
9991 struct tstorm_eth_function_common_config *tcfg,
9997 addr = (BAR_TSTRORM_INTMEM +
9998 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
9999 size = sizeof(struct tstorm_eth_function_common_config);
10000 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg);
10004 bxe_func_init(struct bxe_softc *sc,
10005 struct bxe_func_init_params *p)
10007 struct tstorm_eth_function_common_config tcfg = { 0 };
10009 if (CHIP_IS_E1x(sc)) {
10010 storm_memset_func_cfg(sc, &tcfg, p->func_id);
10013 /* Enable the function in the FW */
10014 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
10015 storm_memset_func_en(sc, p->func_id, 1);
10018 if (p->func_flgs & FUNC_FLG_SPQ) {
10019 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
10021 (XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(p->func_id)),
10027 * Calculates the sum of vn_min_rates.
10028 * It's needed for further normalizing of the min_rates.
10030 * sum of vn_min_rates.
10032 * 0 - if all the min_rates are 0.
10033 * In the later case fainess algorithm should be deactivated.
10034 * If all min rates are not zero then those that are zeroes will be set to 1.
10037 bxe_calc_vn_min(struct bxe_softc *sc,
10038 struct cmng_init_input *input)
10041 uint32_t vn_min_rate;
10045 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10046 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10047 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
10048 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
10050 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10051 /* skip hidden VNs */
10053 } else if (!vn_min_rate) {
10054 /* If min rate is zero - set it to 100 */
10055 vn_min_rate = DEF_MIN_RATE;
10060 input->vnic_min_rate[vn] = vn_min_rate;
10063 /* if ETS or all min rates are zeros - disable fairness */
10064 if (BXE_IS_ETS_ENABLED(sc)) {
10065 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10066 BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n");
10067 } else if (all_zero) {
10068 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10069 BLOGD(sc, DBG_LOAD,
10070 "Fariness disabled (all MIN values are zeroes)\n");
10072 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10076 static inline uint16_t
10077 bxe_extract_max_cfg(struct bxe_softc *sc,
10080 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
10081 FUNC_MF_CFG_MAX_BW_SHIFT);
10084 BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n");
10092 bxe_calc_vn_max(struct bxe_softc *sc,
10094 struct cmng_init_input *input)
10096 uint16_t vn_max_rate;
10097 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10100 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10103 max_cfg = bxe_extract_max_cfg(sc, vn_cfg);
10105 if (IS_MF_SI(sc)) {
10106 /* max_cfg in percents of linkspeed */
10107 vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100);
10108 } else { /* SD modes */
10109 /* max_cfg is absolute in 100Mb units */
10110 vn_max_rate = (max_cfg * 100);
10114 BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
10116 input->vnic_max_rate[vn] = vn_max_rate;
10120 bxe_cmng_fns_init(struct bxe_softc *sc,
10124 struct cmng_init_input input;
10127 memset(&input, 0, sizeof(struct cmng_init_input));
10129 input.port_rate = sc->link_vars.line_speed;
10131 if (cmng_type == CMNG_FNS_MINMAX) {
10132 /* read mf conf from shmem */
10134 bxe_read_mf_cfg(sc);
10137 /* get VN min rate and enable fairness if not 0 */
10138 bxe_calc_vn_min(sc, &input);
10140 /* get VN max rate */
10141 if (sc->port.pmf) {
10142 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10143 bxe_calc_vn_max(sc, vn, &input);
10147 /* always enable rate shaping and fairness */
10148 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
10150 ecore_init_cmng(&input, &sc->cmng);
10154 /* rate shaping and fairness are disabled */
10155 BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n");
10159 bxe_get_cmng_fns_mode(struct bxe_softc *sc)
10161 if (CHIP_REV_IS_SLOW(sc)) {
10162 return (CMNG_FNS_NONE);
10166 return (CMNG_FNS_MINMAX);
10169 return (CMNG_FNS_NONE);
10173 storm_memset_cmng(struct bxe_softc *sc,
10174 struct cmng_init *cmng,
10182 addr = (BAR_XSTRORM_INTMEM +
10183 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
10184 size = sizeof(struct cmng_struct_per_port);
10185 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port);
10187 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10188 func = func_by_vn(sc, vn);
10190 addr = (BAR_XSTRORM_INTMEM +
10191 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
10192 size = sizeof(struct rate_shaping_vars_per_vn);
10193 ecore_storm_memset_struct(sc, addr, size,
10194 (uint32_t *)&cmng->vnic.vnic_max_rate[vn]);
10196 addr = (BAR_XSTRORM_INTMEM +
10197 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
10198 size = sizeof(struct fairness_vars_per_vn);
10199 ecore_storm_memset_struct(sc, addr, size,
10200 (uint32_t *)&cmng->vnic.vnic_min_rate[vn]);
10205 bxe_pf_init(struct bxe_softc *sc)
10207 struct bxe_func_init_params func_init = { 0 };
10208 struct event_ring_data eq_data = { { 0 } };
10211 if (!CHIP_IS_E1x(sc)) {
10212 /* reset IGU PF statistics: MSIX + ATTN */
10215 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10216 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10217 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10221 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10222 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10223 (BXE_IGU_STAS_MSG_PF_CNT * 4) +
10224 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10228 /* function setup flags */
10229 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
10232 * This flag is relevant for E1x only.
10233 * E2 doesn't have a TPA configuration in a function level.
10235 flags |= (sc->ifnet->if_capenable & IFCAP_LRO) ? FUNC_FLG_TPA : 0;
10237 func_init.func_flgs = flags;
10238 func_init.pf_id = SC_FUNC(sc);
10239 func_init.func_id = SC_FUNC(sc);
10240 func_init.spq_map = sc->spq_dma.paddr;
10241 func_init.spq_prod = sc->spq_prod_idx;
10243 bxe_func_init(sc, &func_init);
10245 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
10248 * Congestion management values depend on the link rate.
10249 * There is no active link so initial link rate is set to 10Gbps.
10250 * When the link comes up the congestion management values are
10251 * re-calculated according to the actual link rate.
10253 sc->link_vars.line_speed = SPEED_10000;
10254 bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc));
10256 /* Only the PMF sets the HW */
10257 if (sc->port.pmf) {
10258 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
10261 /* init Event Queue - PCI bus guarantees correct endainity */
10262 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
10263 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
10264 eq_data.producer = sc->eq_prod;
10265 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
10266 eq_data.sb_id = DEF_SB_ID;
10267 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
10271 bxe_hc_int_enable(struct bxe_softc *sc)
10273 int port = SC_PORT(sc);
10274 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10275 uint32_t val = REG_RD(sc, addr);
10276 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10277 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10278 (sc->intr_count == 1)) ? TRUE : FALSE;
10279 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10282 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10283 HC_CONFIG_0_REG_INT_LINE_EN_0);
10284 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10285 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10287 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
10290 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
10291 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10292 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10293 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10295 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10296 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10297 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10298 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10300 if (!CHIP_IS_E1(sc)) {
10301 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n",
10304 REG_WR(sc, addr, val);
10306 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
10310 if (CHIP_IS_E1(sc)) {
10311 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF);
10314 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
10315 val, port, addr, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10317 REG_WR(sc, addr, val);
10319 /* ensure that HC_CONFIG is written before leading/trailing edge config */
10322 if (!CHIP_IS_E1(sc)) {
10323 /* init leading/trailing edge */
10325 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10326 if (sc->port.pmf) {
10327 /* enable nig and gpio3 attention */
10334 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val);
10335 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val);
10338 /* make sure that interrupts are indeed enabled from here on */
10343 bxe_igu_int_enable(struct bxe_softc *sc)
10346 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10347 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10348 (sc->intr_count == 1)) ? TRUE : FALSE;
10349 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10351 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10354 val &= ~(IGU_PF_CONF_INT_LINE_EN |
10355 IGU_PF_CONF_SINGLE_ISR_EN);
10356 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10357 IGU_PF_CONF_ATTN_BIT_EN);
10359 val |= IGU_PF_CONF_SINGLE_ISR_EN;
10362 val &= ~IGU_PF_CONF_INT_LINE_EN;
10363 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10364 IGU_PF_CONF_ATTN_BIT_EN |
10365 IGU_PF_CONF_SINGLE_ISR_EN);
10367 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
10368 val |= (IGU_PF_CONF_INT_LINE_EN |
10369 IGU_PF_CONF_ATTN_BIT_EN |
10370 IGU_PF_CONF_SINGLE_ISR_EN);
10373 /* clean previous status - need to configure igu prior to ack*/
10374 if ((!msix) || single_msix) {
10375 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10379 val |= IGU_PF_CONF_FUNC_EN;
10381 BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n",
10382 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10384 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10388 /* init leading/trailing edge */
10390 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10391 if (sc->port.pmf) {
10392 /* enable nig and gpio3 attention */
10399 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
10400 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
10402 /* make sure that interrupts are indeed enabled from here on */
10407 bxe_int_enable(struct bxe_softc *sc)
10409 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10410 bxe_hc_int_enable(sc);
10412 bxe_igu_int_enable(sc);
10417 bxe_hc_int_disable(struct bxe_softc *sc)
10419 int port = SC_PORT(sc);
10420 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10421 uint32_t val = REG_RD(sc, addr);
10424 * In E1 we must use only PCI configuration space to disable MSI/MSIX
10425 * capablility. It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC
10428 if (CHIP_IS_E1(sc)) {
10430 * Since IGU_PF_CONF_MSI_MSIX_EN still always on use mask register
10431 * to prevent from HC sending interrupts after we exit the function
10433 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0);
10435 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10436 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10437 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10439 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10440 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10441 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10442 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10445 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr);
10447 /* flush all outstanding writes */
10450 REG_WR(sc, addr, val);
10451 if (REG_RD(sc, addr) != val) {
10452 BLOGE(sc, "proper val not read from HC IGU!\n");
10457 bxe_igu_int_disable(struct bxe_softc *sc)
10459 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10461 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
10462 IGU_PF_CONF_INT_LINE_EN |
10463 IGU_PF_CONF_ATTN_BIT_EN);
10465 BLOGD(sc, DBG_INTR, "write %x to IGU\n", val);
10467 /* flush all outstanding writes */
10470 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10471 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
10472 BLOGE(sc, "proper val not read from IGU!\n");
10477 bxe_int_disable(struct bxe_softc *sc)
10479 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10480 bxe_hc_int_disable(sc);
10482 bxe_igu_int_disable(sc);
10487 bxe_nic_init(struct bxe_softc *sc,
10492 for (i = 0; i < sc->num_queues; i++) {
10493 bxe_init_eth_fp(sc, i);
10496 rmb(); /* ensure status block indices were read */
10498 bxe_init_rx_rings(sc);
10499 bxe_init_tx_rings(sc);
10505 /* initialize MOD_ABS interrupts */
10506 elink_init_mod_abs_int(sc, &sc->link_vars,
10507 sc->devinfo.chip_id,
10508 sc->devinfo.shmem_base,
10509 sc->devinfo.shmem2_base,
10512 bxe_init_def_sb(sc);
10513 bxe_update_dsb_idx(sc);
10514 bxe_init_sp_ring(sc);
10515 bxe_init_eq_ring(sc);
10516 bxe_init_internal(sc, load_code);
10518 bxe_stats_init(sc);
10520 /* flush all before enabling interrupts */
10523 bxe_int_enable(sc);
10525 /* check for SPIO5 */
10526 bxe_attn_int_deasserted0(sc,
10528 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
10530 AEU_INPUTS_ATTN_BITS_SPIO5);
10534 bxe_init_objs(struct bxe_softc *sc)
10536 /* mcast rules must be added to tx if tx switching is enabled */
10537 ecore_obj_type o_type =
10538 (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX :
10541 /* RX_MODE controlling object */
10542 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
10544 /* multicast configuration controlling object */
10545 ecore_init_mcast_obj(sc,
10551 BXE_SP(sc, mcast_rdata),
10552 BXE_SP_MAPPING(sc, mcast_rdata),
10553 ECORE_FILTER_MCAST_PENDING,
10557 /* Setup CAM credit pools */
10558 ecore_init_mac_credit_pool(sc,
10561 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10562 VNICS_PER_PATH(sc));
10564 ecore_init_vlan_credit_pool(sc,
10566 SC_ABS_FUNC(sc) >> 1,
10567 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10568 VNICS_PER_PATH(sc));
10570 /* RSS configuration object */
10571 ecore_init_rss_config_obj(sc,
10577 BXE_SP(sc, rss_rdata),
10578 BXE_SP_MAPPING(sc, rss_rdata),
10579 ECORE_FILTER_RSS_CONF_PENDING,
10580 &sc->sp_state, ECORE_OBJ_TYPE_RX);
10584 * Initialize the function. This must be called before sending CLIENT_SETUP
10585 * for the first client.
10588 bxe_func_start(struct bxe_softc *sc)
10590 struct ecore_func_state_params func_params = { NULL };
10591 struct ecore_func_start_params *start_params = &func_params.params.start;
10593 /* Prepare parameters for function state transitions */
10594 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
10596 func_params.f_obj = &sc->func_obj;
10597 func_params.cmd = ECORE_F_CMD_START;
10599 /* Function parameters */
10600 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
10601 start_params->sd_vlan_tag = OVLAN(sc);
10603 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
10604 start_params->network_cos_mode = STATIC_COS;
10605 } else { /* CHIP_IS_E1X */
10606 start_params->network_cos_mode = FW_WRR;
10609 //start_params->gre_tunnel_mode = 0;
10610 //start_params->gre_tunnel_rss = 0;
10612 return (ecore_func_state_change(sc, &func_params));
10616 bxe_set_power_state(struct bxe_softc *sc,
10621 /* If there is no power capability, silently succeed */
10622 if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) {
10623 BLOGW(sc, "No power capability\n");
10627 pmcsr = pci_read_config(sc->dev,
10628 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10633 pci_write_config(sc->dev,
10634 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10635 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2);
10637 if (pmcsr & PCIM_PSTAT_DMASK) {
10638 /* delay required during transition out of D3hot */
10645 /* XXX if there are other clients above don't shut down the power */
10647 /* don't shut down the power for emulation and FPGA */
10648 if (CHIP_REV_IS_SLOW(sc)) {
10652 pmcsr &= ~PCIM_PSTAT_DMASK;
10653 pmcsr |= PCIM_PSTAT_D3;
10656 pmcsr |= PCIM_PSTAT_PMEENABLE;
10659 pci_write_config(sc->dev,
10660 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10664 * No more memory access after this point until device is brought back
10670 BLOGE(sc, "Can't support PCI power state = 0x%x pmcsr 0x%x\n",
10679 /* return true if succeeded to acquire the lock */
10681 bxe_trylock_hw_lock(struct bxe_softc *sc,
10684 uint32_t lock_status;
10685 uint32_t resource_bit = (1 << resource);
10686 int func = SC_FUNC(sc);
10687 uint32_t hw_lock_control_reg;
10689 BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource);
10691 /* Validating that the resource is within range */
10692 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
10693 BLOGD(sc, DBG_LOAD,
10694 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
10695 resource, HW_LOCK_MAX_RESOURCE_VALUE);
10700 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
10702 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
10705 /* try to acquire the lock */
10706 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
10707 lock_status = REG_RD(sc, hw_lock_control_reg);
10708 if (lock_status & resource_bit) {
10712 BLOGE(sc, "Failed to get a resource lock 0x%x func %d "
10713 "lock_status 0x%x resource_bit 0x%x\n", resource, func,
10714 lock_status, resource_bit);
10720 * Get the recovery leader resource id according to the engine this function
10721 * belongs to. Currently only only 2 engines is supported.
10724 bxe_get_leader_lock_resource(struct bxe_softc *sc)
10727 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_1);
10729 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_0);
10733 /* try to acquire a leader lock for current engine */
10735 bxe_trylock_leader_lock(struct bxe_softc *sc)
10737 return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
10741 bxe_release_leader_lock(struct bxe_softc *sc)
10743 return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
10746 /* close gates #2, #3 and #4 */
10748 bxe_set_234_gates(struct bxe_softc *sc,
10753 /* gates #2 and #4a are closed/opened for "not E1" only */
10754 if (!CHIP_IS_E1(sc)) {
10756 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
10758 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
10762 if (CHIP_IS_E1x(sc)) {
10763 /* prevent interrupts from HC on both ports */
10764 val = REG_RD(sc, HC_REG_CONFIG_1);
10765 REG_WR(sc, HC_REG_CONFIG_1,
10766 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
10767 (val & ~(uint32_t)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
10769 val = REG_RD(sc, HC_REG_CONFIG_0);
10770 REG_WR(sc, HC_REG_CONFIG_0,
10771 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
10772 (val & ~(uint32_t)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
10774 /* Prevent incomming interrupts in IGU */
10775 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
10777 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
10779 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
10780 (val & ~(uint32_t)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
10783 BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n",
10784 close ? "closing" : "opening");
10789 /* poll for pending writes bit, it should get cleared in no more than 1s */
10791 bxe_er_poll_igu_vq(struct bxe_softc *sc)
10793 uint32_t cnt = 1000;
10794 uint32_t pend_bits = 0;
10797 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
10799 if (pend_bits == 0) {
10804 } while (--cnt > 0);
10807 BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits);
10814 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
10817 bxe_clp_reset_prep(struct bxe_softc *sc,
10818 uint32_t *magic_val)
10820 /* Do some magic... */
10821 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
10822 *magic_val = val & SHARED_MF_CLP_MAGIC;
10823 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
10826 /* restore the value of the 'magic' bit */
10828 bxe_clp_reset_done(struct bxe_softc *sc,
10829 uint32_t magic_val)
10831 /* Restore the 'magic' bit value... */
10832 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
10833 MFCFG_WR(sc, shared_mf_config.clp_mb,
10834 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
10837 /* prepare for MCP reset, takes care of CLP configurations */
10839 bxe_reset_mcp_prep(struct bxe_softc *sc,
10840 uint32_t *magic_val)
10843 uint32_t validity_offset;
10845 /* set `magic' bit in order to save MF config */
10846 if (!CHIP_IS_E1(sc)) {
10847 bxe_clp_reset_prep(sc, magic_val);
10850 /* get shmem offset */
10851 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
10853 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
10855 /* Clear validity map flags */
10857 REG_WR(sc, shmem + validity_offset, 0);
10861 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
10862 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
10865 bxe_mcp_wait_one(struct bxe_softc *sc)
10867 /* special handling for emulation and FPGA (10 times longer) */
10868 if (CHIP_REV_IS_SLOW(sc)) {
10869 DELAY((MCP_ONE_TIMEOUT*10) * 1000);
10871 DELAY((MCP_ONE_TIMEOUT) * 1000);
10875 /* initialize shmem_base and waits for validity signature to appear */
10877 bxe_init_shmem(struct bxe_softc *sc)
10883 sc->devinfo.shmem_base =
10884 sc->link_params.shmem_base =
10885 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
10887 if (sc->devinfo.shmem_base) {
10888 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
10889 if (val & SHR_MEM_VALIDITY_MB)
10893 bxe_mcp_wait_one(sc);
10895 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
10897 BLOGE(sc, "BAD MCP validity signature\n");
10903 bxe_reset_mcp_comp(struct bxe_softc *sc,
10904 uint32_t magic_val)
10906 int rc = bxe_init_shmem(sc);
10908 /* Restore the `magic' bit value */
10909 if (!CHIP_IS_E1(sc)) {
10910 bxe_clp_reset_done(sc, magic_val);
10917 bxe_pxp_prep(struct bxe_softc *sc)
10919 if (!CHIP_IS_E1(sc)) {
10920 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
10921 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
10927 * Reset the whole chip except for:
10929 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
10931 * - MISC (including AEU)
10936 bxe_process_kill_chip_reset(struct bxe_softc *sc,
10939 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
10940 uint32_t global_bits2, stay_reset2;
10943 * Bits that have to be set in reset_mask2 if we want to reset 'global'
10944 * (per chip) blocks.
10947 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
10948 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
10951 * Don't reset the following blocks.
10952 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
10953 * reset, as in 4 port device they might still be owned
10954 * by the MCP (there is only one leader per path).
10957 MISC_REGISTERS_RESET_REG_1_RST_HC |
10958 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
10959 MISC_REGISTERS_RESET_REG_1_RST_PXP;
10962 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
10963 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
10964 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
10965 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
10966 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
10967 MISC_REGISTERS_RESET_REG_2_RST_GRC |
10968 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
10969 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
10970 MISC_REGISTERS_RESET_REG_2_RST_ATC |
10971 MISC_REGISTERS_RESET_REG_2_PGLC |
10972 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
10973 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
10974 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
10975 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
10976 MISC_REGISTERS_RESET_REG_2_UMAC0 |
10977 MISC_REGISTERS_RESET_REG_2_UMAC1;
10980 * Keep the following blocks in reset:
10981 * - all xxMACs are handled by the elink code.
10984 MISC_REGISTERS_RESET_REG_2_XMAC |
10985 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
10987 /* Full reset masks according to the chip */
10988 reset_mask1 = 0xffffffff;
10990 if (CHIP_IS_E1(sc))
10991 reset_mask2 = 0xffff;
10992 else if (CHIP_IS_E1H(sc))
10993 reset_mask2 = 0x1ffff;
10994 else if (CHIP_IS_E2(sc))
10995 reset_mask2 = 0xfffff;
10996 else /* CHIP_IS_E3 */
10997 reset_mask2 = 0x3ffffff;
10999 /* Don't reset global blocks unless we need to */
11001 reset_mask2 &= ~global_bits2;
11004 * In case of attention in the QM, we need to reset PXP
11005 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
11006 * because otherwise QM reset would release 'close the gates' shortly
11007 * before resetting the PXP, then the PSWRQ would send a write
11008 * request to PGLUE. Then when PXP is reset, PGLUE would try to
11009 * read the payload data from PSWWR, but PSWWR would not
11010 * respond. The write queue in PGLUE would stuck, dmae commands
11011 * would not return. Therefore it's important to reset the second
11012 * reset register (containing the
11013 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
11014 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
11017 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11018 reset_mask2 & (~not_reset_mask2));
11020 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
11021 reset_mask1 & (~not_reset_mask1));
11026 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
11027 reset_mask2 & (~stay_reset2));
11032 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
11037 bxe_process_kill(struct bxe_softc *sc,
11042 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
11043 uint32_t tags_63_32 = 0;
11045 /* Empty the Tetris buffer, wait for 1s */
11047 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
11048 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
11049 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
11050 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
11051 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
11052 if (CHIP_IS_E3(sc)) {
11053 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
11056 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
11057 ((port_is_idle_0 & 0x1) == 0x1) &&
11058 ((port_is_idle_1 & 0x1) == 0x1) &&
11059 (pgl_exp_rom2 == 0xffffffff) &&
11060 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
11063 } while (cnt-- > 0);
11066 BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there "
11067 "are still outstanding read requests after 1s! "
11068 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
11069 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
11070 sr_cnt, blk_cnt, port_is_idle_0,
11071 port_is_idle_1, pgl_exp_rom2);
11077 /* Close gates #2, #3 and #4 */
11078 bxe_set_234_gates(sc, TRUE);
11080 /* Poll for IGU VQs for 57712 and newer chips */
11081 if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) {
11085 /* XXX indicate that "process kill" is in progress to MCP */
11087 /* clear "unprepared" bit */
11088 REG_WR(sc, MISC_REG_UNPREPARED, 0);
11091 /* Make sure all is written to the chip before the reset */
11095 * Wait for 1ms to empty GLUE and PCI-E core queues,
11096 * PSWHST, GRC and PSWRD Tetris buffer.
11100 /* Prepare to chip reset: */
11103 bxe_reset_mcp_prep(sc, &val);
11110 /* reset the chip */
11111 bxe_process_kill_chip_reset(sc, global);
11114 /* clear errors in PGB */
11115 if (!CHIP_IS_E1(sc))
11116 REG_WR(sc, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
11118 /* Recover after reset: */
11120 if (global && bxe_reset_mcp_comp(sc, val)) {
11124 /* XXX add resetting the NO_MCP mode DB here */
11126 /* Open the gates #2, #3 and #4 */
11127 bxe_set_234_gates(sc, FALSE);
11130 * IGU/AEU preparation bring back the AEU/IGU to a reset state
11131 * re-enable attentions
11138 bxe_leader_reset(struct bxe_softc *sc)
11141 uint8_t global = bxe_reset_is_global(sc);
11142 uint32_t load_code;
11145 * If not going to reset MCP, load "fake" driver to reset HW while
11146 * driver is owner of the HW.
11148 if (!global && !BXE_NOMCP(sc)) {
11149 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
11150 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
11152 BLOGE(sc, "MCP response failure, aborting\n");
11154 goto exit_leader_reset;
11157 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
11158 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
11159 BLOGE(sc, "MCP unexpected response, aborting\n");
11161 goto exit_leader_reset2;
11164 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
11166 BLOGE(sc, "MCP response failure, aborting\n");
11168 goto exit_leader_reset2;
11172 /* try to recover after the failure */
11173 if (bxe_process_kill(sc, global)) {
11174 BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc));
11176 goto exit_leader_reset2;
11180 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
11183 bxe_set_reset_done(sc);
11185 bxe_clear_reset_global(sc);
11188 exit_leader_reset2:
11190 /* unload "fake driver" if it was loaded */
11191 if (!global && !BXE_NOMCP(sc)) {
11192 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
11193 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
11199 bxe_release_leader_lock(sc);
11206 * prepare INIT transition, parameters configured:
11207 * - HC configuration
11208 * - Queue's CDU context
11211 bxe_pf_q_prep_init(struct bxe_softc *sc,
11212 struct bxe_fastpath *fp,
11213 struct ecore_queue_init_params *init_params)
11216 int cxt_index, cxt_offset;
11218 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
11219 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
11221 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
11222 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
11225 init_params->rx.hc_rate =
11226 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
11227 init_params->tx.hc_rate =
11228 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
11231 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
11233 /* CQ index among the SB indices */
11234 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11235 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
11237 /* set maximum number of COSs supported by this queue */
11238 init_params->max_cos = sc->max_cos;
11240 BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n",
11241 fp->index, init_params->max_cos);
11243 /* set the context pointers queue object */
11244 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
11245 /* XXX change index/cid here if ever support multiple tx CoS */
11246 /* fp->txdata[cos]->cid */
11247 cxt_index = fp->index / ILT_PAGE_CIDS;
11248 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
11249 init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth;
11253 /* set flags that are common for the Tx-only and not normal connections */
11254 static unsigned long
11255 bxe_get_common_flags(struct bxe_softc *sc,
11256 struct bxe_fastpath *fp,
11257 uint8_t zero_stats)
11259 unsigned long flags = 0;
11261 /* PF driver will always initialize the Queue to an ACTIVE state */
11262 bxe_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
11265 * tx only connections collect statistics (on the same index as the
11266 * parent connection). The statistics are zeroed when the parent
11267 * connection is initialized.
11270 bxe_set_bit(ECORE_Q_FLG_STATS, &flags);
11272 bxe_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
11276 * tx only connections can support tx-switching, though their
11277 * CoS-ness doesn't survive the loopback
11279 if (sc->flags & BXE_TX_SWITCHING) {
11280 bxe_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
11283 bxe_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
11288 static unsigned long
11289 bxe_get_q_flags(struct bxe_softc *sc,
11290 struct bxe_fastpath *fp,
11293 unsigned long flags = 0;
11295 if (IS_MF_SD(sc)) {
11296 bxe_set_bit(ECORE_Q_FLG_OV, &flags);
11299 if (sc->ifnet->if_capenable & IFCAP_LRO) {
11300 bxe_set_bit(ECORE_Q_FLG_TPA, &flags);
11301 bxe_set_bit(ECORE_Q_FLG_TPA_IPV6, &flags);
11305 bxe_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
11306 bxe_set_bit(ECORE_Q_FLG_MCAST, &flags);
11309 bxe_set_bit(ECORE_Q_FLG_VLAN, &flags);
11311 /* merge with common flags */
11312 return (flags | bxe_get_common_flags(sc, fp, TRUE));
11316 bxe_pf_q_prep_general(struct bxe_softc *sc,
11317 struct bxe_fastpath *fp,
11318 struct ecore_general_setup_params *gen_init,
11321 gen_init->stat_id = bxe_stats_id(fp);
11322 gen_init->spcl_id = fp->cl_id;
11323 gen_init->mtu = sc->mtu;
11324 gen_init->cos = cos;
11328 bxe_pf_rx_q_prep(struct bxe_softc *sc,
11329 struct bxe_fastpath *fp,
11330 struct rxq_pause_params *pause,
11331 struct ecore_rxq_setup_params *rxq_init)
11333 uint8_t max_sge = 0;
11334 uint16_t sge_sz = 0;
11335 uint16_t tpa_agg_size = 0;
11337 pause->sge_th_lo = SGE_TH_LO(sc);
11338 pause->sge_th_hi = SGE_TH_HI(sc);
11340 /* validate SGE ring has enough to cross high threshold */
11341 if (sc->dropless_fc &&
11342 (pause->sge_th_hi + FW_PREFETCH_CNT) >
11343 (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)) {
11344 BLOGW(sc, "sge ring threshold limit\n");
11347 /* minimum max_aggregation_size is 2*MTU (two full buffers) */
11348 tpa_agg_size = (2 * sc->mtu);
11349 if (tpa_agg_size < sc->max_aggregation_size) {
11350 tpa_agg_size = sc->max_aggregation_size;
11353 max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT;
11354 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
11355 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
11356 sge_sz = (uint16_t)min(SGE_PAGES, 0xffff);
11358 /* pause - not for e1 */
11359 if (!CHIP_IS_E1(sc)) {
11360 pause->bd_th_lo = BD_TH_LO(sc);
11361 pause->bd_th_hi = BD_TH_HI(sc);
11363 pause->rcq_th_lo = RCQ_TH_LO(sc);
11364 pause->rcq_th_hi = RCQ_TH_HI(sc);
11366 /* validate rings have enough entries to cross high thresholds */
11367 if (sc->dropless_fc &&
11368 pause->bd_th_hi + FW_PREFETCH_CNT >
11369 sc->rx_ring_size) {
11370 BLOGW(sc, "rx bd ring threshold limit\n");
11373 if (sc->dropless_fc &&
11374 pause->rcq_th_hi + FW_PREFETCH_CNT >
11375 RCQ_NUM_PAGES * RCQ_USABLE_PER_PAGE) {
11376 BLOGW(sc, "rcq ring threshold limit\n");
11379 pause->pri_map = 1;
11383 rxq_init->dscr_map = fp->rx_dma.paddr;
11384 rxq_init->sge_map = fp->rx_sge_dma.paddr;
11385 rxq_init->rcq_map = fp->rcq_dma.paddr;
11386 rxq_init->rcq_np_map = (fp->rcq_dma.paddr + BCM_PAGE_SIZE);
11389 * This should be a maximum number of data bytes that may be
11390 * placed on the BD (not including paddings).
11392 rxq_init->buf_sz = (fp->rx_buf_size -
11393 IP_HEADER_ALIGNMENT_PADDING);
11395 rxq_init->cl_qzone_id = fp->cl_qzone_id;
11396 rxq_init->tpa_agg_sz = tpa_agg_size;
11397 rxq_init->sge_buf_sz = sge_sz;
11398 rxq_init->max_sges_pkt = max_sge;
11399 rxq_init->rss_engine_id = SC_FUNC(sc);
11400 rxq_init->mcast_engine_id = SC_FUNC(sc);
11403 * Maximum number or simultaneous TPA aggregation for this Queue.
11404 * For PF Clients it should be the maximum available number.
11405 * VF driver(s) may want to define it to a smaller value.
11407 rxq_init->max_tpa_queues = MAX_AGG_QS(sc);
11409 rxq_init->cache_line_log = BXE_RX_ALIGN_SHIFT;
11410 rxq_init->fw_sb_id = fp->fw_sb_id;
11412 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11415 * configure silent vlan removal
11416 * if multi function mode is afex, then mask default vlan
11418 if (IS_MF_AFEX(sc)) {
11419 rxq_init->silent_removal_value =
11420 sc->devinfo.mf_info.afex_def_vlan_tag;
11421 rxq_init->silent_removal_mask = EVL_VLID_MASK;
11426 bxe_pf_tx_q_prep(struct bxe_softc *sc,
11427 struct bxe_fastpath *fp,
11428 struct ecore_txq_setup_params *txq_init,
11432 * XXX If multiple CoS is ever supported then each fastpath structure
11433 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
11434 * fp->txdata[cos]->tx_dma.paddr;
11436 txq_init->dscr_map = fp->tx_dma.paddr;
11437 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
11438 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
11439 txq_init->fw_sb_id = fp->fw_sb_id;
11442 * set the TSS leading client id for TX classfication to the
11443 * leading RSS client id
11445 txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id);
11449 * This function performs 2 steps in a queue state machine:
11454 bxe_setup_queue(struct bxe_softc *sc,
11455 struct bxe_fastpath *fp,
11458 struct ecore_queue_state_params q_params = { NULL };
11459 struct ecore_queue_setup_params *setup_params =
11460 &q_params.params.setup;
11463 BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index);
11465 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
11467 q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
11469 /* we want to wait for completion in this context */
11470 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
11472 /* prepare the INIT parameters */
11473 bxe_pf_q_prep_init(sc, fp, &q_params.params.init);
11475 /* Set the command */
11476 q_params.cmd = ECORE_Q_CMD_INIT;
11478 /* Change the state to INIT */
11479 rc = ecore_queue_state_change(sc, &q_params);
11481 BLOGE(sc, "Queue(%d) INIT failed rc = %d\n", fp->index, rc);
11485 BLOGD(sc, DBG_LOAD, "init complete\n");
11487 /* now move the Queue to the SETUP state */
11488 memset(setup_params, 0, sizeof(*setup_params));
11490 /* set Queue flags */
11491 setup_params->flags = bxe_get_q_flags(sc, fp, leading);
11493 /* set general SETUP parameters */
11494 bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params,
11495 FIRST_TX_COS_INDEX);
11497 bxe_pf_rx_q_prep(sc, fp,
11498 &setup_params->pause_params,
11499 &setup_params->rxq_params);
11501 bxe_pf_tx_q_prep(sc, fp,
11502 &setup_params->txq_params,
11503 FIRST_TX_COS_INDEX);
11505 /* Set the command */
11506 q_params.cmd = ECORE_Q_CMD_SETUP;
11508 /* change the state to SETUP */
11509 rc = ecore_queue_state_change(sc, &q_params);
11511 BLOGE(sc, "Queue(%d) SETUP failed (rc = %d)\n", fp->index, rc);
11519 bxe_setup_leading(struct bxe_softc *sc)
11521 return (bxe_setup_queue(sc, &sc->fp[0], TRUE));
11525 bxe_config_rss_pf(struct bxe_softc *sc,
11526 struct ecore_rss_config_obj *rss_obj,
11527 uint8_t config_hash)
11529 struct ecore_config_rss_params params = { NULL };
11533 * Although RSS is meaningless when there is a single HW queue we
11534 * still need it enabled in order to have HW Rx hash generated.
11537 params.rss_obj = rss_obj;
11539 bxe_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
11541 bxe_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
11543 /* RSS configuration */
11544 bxe_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
11545 bxe_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
11546 bxe_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
11547 bxe_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
11548 if (rss_obj->udp_rss_v4) {
11549 bxe_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
11551 if (rss_obj->udp_rss_v6) {
11552 bxe_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
11556 params.rss_result_mask = MULTI_MASK;
11558 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
11562 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
11563 params.rss_key[i] = arc4random();
11566 bxe_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
11569 return (ecore_config_rss(sc, ¶ms));
11573 bxe_config_rss_eth(struct bxe_softc *sc,
11574 uint8_t config_hash)
11576 return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash));
11580 bxe_init_rss_pf(struct bxe_softc *sc)
11582 uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc);
11586 * Prepare the initial contents of the indirection table if
11589 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
11590 sc->rss_conf_obj.ind_table[i] =
11591 (sc->fp->cl_id + (i % num_eth_queues));
11595 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
11599 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
11600 * per-port, so if explicit configuration is needed, do it only
11603 * For 57712 and newer it's a per-function configuration.
11605 return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc)));
11609 bxe_set_mac_one(struct bxe_softc *sc,
11611 struct ecore_vlan_mac_obj *obj,
11614 unsigned long *ramrod_flags)
11616 struct ecore_vlan_mac_ramrod_params ramrod_param;
11619 memset(&ramrod_param, 0, sizeof(ramrod_param));
11621 /* fill in general parameters */
11622 ramrod_param.vlan_mac_obj = obj;
11623 ramrod_param.ramrod_flags = *ramrod_flags;
11625 /* fill a user request section if needed */
11626 if (!bxe_test_bit(RAMROD_CONT, ramrod_flags)) {
11627 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
11629 bxe_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
11631 /* Set the command: ADD or DEL */
11632 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
11633 ECORE_VLAN_MAC_DEL;
11636 rc = ecore_config_vlan_mac(sc, &ramrod_param);
11638 if (rc == ECORE_EXISTS) {
11639 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
11640 /* do not treat adding same MAC as error */
11642 } else if (rc < 0) {
11643 BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc);
11650 bxe_set_eth_mac(struct bxe_softc *sc,
11653 unsigned long ramrod_flags = 0;
11655 BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n");
11657 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11659 /* Eth MAC is set on RSS leading client (fp[0]) */
11660 return (bxe_set_mac_one(sc, sc->link_params.mac_addr,
11661 &sc->sp_objs->mac_obj,
11662 set, ECORE_ETH_MAC, &ramrod_flags));
11666 bxe_get_cur_phy_idx(struct bxe_softc *sc)
11668 uint32_t sel_phy_idx = 0;
11670 if (sc->link_params.num_phys <= 1) {
11671 return (ELINK_INT_PHY);
11674 if (sc->link_vars.link_up) {
11675 sel_phy_idx = ELINK_EXT_PHY1;
11676 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
11677 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
11678 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
11679 ELINK_SUPPORTED_FIBRE))
11680 sel_phy_idx = ELINK_EXT_PHY2;
11682 switch (elink_phy_selection(&sc->link_params)) {
11683 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
11684 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11685 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11686 sel_phy_idx = ELINK_EXT_PHY1;
11688 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11689 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11690 sel_phy_idx = ELINK_EXT_PHY2;
11695 return (sel_phy_idx);
11699 bxe_get_link_cfg_idx(struct bxe_softc *sc)
11701 uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc);
11704 * The selected activated PHY is always after swapping (in case PHY
11705 * swapping is enabled). So when swapping is enabled, we need to reverse
11706 * the configuration
11709 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11710 if (sel_phy_idx == ELINK_EXT_PHY1)
11711 sel_phy_idx = ELINK_EXT_PHY2;
11712 else if (sel_phy_idx == ELINK_EXT_PHY2)
11713 sel_phy_idx = ELINK_EXT_PHY1;
11716 return (ELINK_LINK_CONFIG_IDX(sel_phy_idx));
11720 bxe_set_requested_fc(struct bxe_softc *sc)
11723 * Initialize link parameters structure variables
11724 * It is recommended to turn off RX FC for jumbo frames
11725 * for better performance
11727 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
11728 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
11730 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
11735 bxe_calc_fc_adv(struct bxe_softc *sc)
11737 uint8_t cfg_idx = bxe_get_link_cfg_idx(sc);
11738 switch (sc->link_vars.ieee_fc &
11739 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
11740 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
11742 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
11746 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
11747 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
11751 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
11752 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
11758 bxe_get_mf_speed(struct bxe_softc *sc)
11760 uint16_t line_speed = sc->link_vars.line_speed;
11763 bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]);
11765 /* calculate the current MAX line speed limit for the MF devices */
11766 if (IS_MF_SI(sc)) {
11767 line_speed = (line_speed * maxCfg) / 100;
11768 } else { /* SD mode */
11769 uint16_t vn_max_rate = maxCfg * 100;
11771 if (vn_max_rate < line_speed) {
11772 line_speed = vn_max_rate;
11777 return (line_speed);
11781 bxe_fill_report_data(struct bxe_softc *sc,
11782 struct bxe_link_report_data *data)
11784 uint16_t line_speed = bxe_get_mf_speed(sc);
11786 memset(data, 0, sizeof(*data));
11788 /* fill the report data with the effective line speed */
11789 data->line_speed = line_speed;
11792 if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) {
11793 bxe_set_bit(BXE_LINK_REPORT_LINK_DOWN, &data->link_report_flags);
11797 if (sc->link_vars.duplex == DUPLEX_FULL) {
11798 bxe_set_bit(BXE_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags);
11801 /* Rx Flow Control is ON */
11802 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
11803 bxe_set_bit(BXE_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
11806 /* Tx Flow Control is ON */
11807 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
11808 bxe_set_bit(BXE_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
11812 /* report link status to OS, should be called under phy_lock */
11814 bxe_link_report_locked(struct bxe_softc *sc)
11816 struct bxe_link_report_data cur_data;
11818 /* reread mf_cfg */
11819 if (IS_PF(sc) && !CHIP_IS_E1(sc)) {
11820 bxe_read_mf_cfg(sc);
11823 /* Read the current link report info */
11824 bxe_fill_report_data(sc, &cur_data);
11826 /* Don't report link down or exactly the same link status twice */
11827 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
11828 (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11829 &sc->last_reported_link.link_report_flags) &&
11830 bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11831 &cur_data.link_report_flags))) {
11837 /* report new link params and remember the state for the next time */
11838 memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
11840 if (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11841 &cur_data.link_report_flags)) {
11842 if_link_state_change(sc->ifnet, LINK_STATE_DOWN);
11843 BLOGI(sc, "NIC Link is Down\n");
11845 const char *duplex;
11848 if (bxe_test_and_clear_bit(BXE_LINK_REPORT_FULL_DUPLEX,
11849 &cur_data.link_report_flags)) {
11856 * Handle the FC at the end so that only these flags would be
11857 * possibly set. This way we may easily check if there is no FC
11860 if (cur_data.link_report_flags) {
11861 if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11862 &cur_data.link_report_flags) &&
11863 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11864 &cur_data.link_report_flags)) {
11865 flow = "ON - receive & transmit";
11866 } else if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11867 &cur_data.link_report_flags) &&
11868 !bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11869 &cur_data.link_report_flags)) {
11870 flow = "ON - receive";
11871 } else if (!bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11872 &cur_data.link_report_flags) &&
11873 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11874 &cur_data.link_report_flags)) {
11875 flow = "ON - transmit";
11877 flow = "none"; /* possible? */
11883 if_link_state_change(sc->ifnet, LINK_STATE_UP);
11884 BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
11885 cur_data.line_speed, duplex, flow);
11890 bxe_link_report(struct bxe_softc *sc)
11892 bxe_acquire_phy_lock(sc);
11893 bxe_link_report_locked(sc);
11894 bxe_release_phy_lock(sc);
11898 bxe_link_status_update(struct bxe_softc *sc)
11900 if (sc->state != BXE_STATE_OPEN) {
11904 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
11905 elink_link_status_update(&sc->link_params, &sc->link_vars);
11907 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
11908 ELINK_SUPPORTED_10baseT_Full |
11909 ELINK_SUPPORTED_100baseT_Half |
11910 ELINK_SUPPORTED_100baseT_Full |
11911 ELINK_SUPPORTED_1000baseT_Full |
11912 ELINK_SUPPORTED_2500baseX_Full |
11913 ELINK_SUPPORTED_10000baseT_Full |
11914 ELINK_SUPPORTED_TP |
11915 ELINK_SUPPORTED_FIBRE |
11916 ELINK_SUPPORTED_Autoneg |
11917 ELINK_SUPPORTED_Pause |
11918 ELINK_SUPPORTED_Asym_Pause);
11919 sc->port.advertising[0] = sc->port.supported[0];
11921 sc->link_params.sc = sc;
11922 sc->link_params.port = SC_PORT(sc);
11923 sc->link_params.req_duplex[0] = DUPLEX_FULL;
11924 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
11925 sc->link_params.req_line_speed[0] = SPEED_10000;
11926 sc->link_params.speed_cap_mask[0] = 0x7f0000;
11927 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
11929 if (CHIP_REV_IS_FPGA(sc)) {
11930 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
11931 sc->link_vars.line_speed = ELINK_SPEED_1000;
11932 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
11933 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
11935 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
11936 sc->link_vars.line_speed = ELINK_SPEED_10000;
11937 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
11938 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
11941 sc->link_vars.link_up = 1;
11943 sc->link_vars.duplex = DUPLEX_FULL;
11944 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
11947 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0);
11948 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11949 bxe_link_report(sc);
11954 if (sc->link_vars.link_up) {
11955 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11957 bxe_stats_handle(sc, STATS_EVENT_STOP);
11959 bxe_link_report(sc);
11961 bxe_link_report(sc);
11962 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11967 bxe_initial_phy_init(struct bxe_softc *sc,
11970 int rc, cfg_idx = bxe_get_link_cfg_idx(sc);
11971 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
11972 struct elink_params *lp = &sc->link_params;
11974 bxe_set_requested_fc(sc);
11976 if (CHIP_REV_IS_SLOW(sc)) {
11977 uint32_t bond = CHIP_BOND_ID(sc);
11980 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
11981 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
11982 } else if (bond & 0x4) {
11983 if (CHIP_IS_E3(sc)) {
11984 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
11986 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
11988 } else if (bond & 0x8) {
11989 if (CHIP_IS_E3(sc)) {
11990 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
11992 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
11996 /* disable EMAC for E3 and above */
11998 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
12001 sc->link_params.feature_config_flags |= feat;
12004 bxe_acquire_phy_lock(sc);
12006 if (load_mode == LOAD_DIAG) {
12007 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
12008 /* Prefer doing PHY loopback at 10G speed, if possible */
12009 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
12010 if (lp->speed_cap_mask[cfg_idx] &
12011 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
12012 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
12014 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
12019 if (load_mode == LOAD_LOOPBACK_EXT) {
12020 lp->loopback_mode = ELINK_LOOPBACK_EXT;
12023 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
12025 bxe_release_phy_lock(sc);
12027 bxe_calc_fc_adv(sc);
12029 if (sc->link_vars.link_up) {
12030 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12031 bxe_link_report(sc);
12034 if (!CHIP_REV_IS_SLOW(sc)) {
12035 bxe_periodic_start(sc);
12038 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
12042 /* must be called under IF_ADDR_LOCK */
12044 bxe_init_mcast_macs_list(struct bxe_softc *sc,
12045 struct ecore_mcast_ramrod_params *p)
12047 struct ifnet *ifp = sc->ifnet;
12049 struct ifmultiaddr *ifma;
12050 struct ecore_mcast_list_elem *mc_mac;
12052 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
12053 if (ifma->ifma_addr->sa_family != AF_LINK) {
12060 ECORE_LIST_INIT(&p->mcast_list);
12061 p->mcast_list_len = 0;
12067 mc_mac = malloc(sizeof(*mc_mac) * mc_count, M_DEVBUF,
12068 (M_NOWAIT | M_ZERO));
12070 BLOGE(sc, "Failed to allocate temp mcast list\n");
12073 bzero(mc_mac, (sizeof(*mc_mac) * mc_count));
12075 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
12076 if (ifma->ifma_addr->sa_family != AF_LINK) {
12080 mc_mac->mac = (uint8_t *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
12081 ECORE_LIST_PUSH_TAIL(&mc_mac->link, &p->mcast_list);
12083 BLOGD(sc, DBG_LOAD,
12084 "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X\n",
12085 mc_mac->mac[0], mc_mac->mac[1], mc_mac->mac[2],
12086 mc_mac->mac[3], mc_mac->mac[4], mc_mac->mac[5]);
12091 p->mcast_list_len = mc_count;
12097 bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params *p)
12099 struct ecore_mcast_list_elem *mc_mac =
12100 ECORE_LIST_FIRST_ENTRY(&p->mcast_list,
12101 struct ecore_mcast_list_elem,
12105 /* only a single free as all mc_macs are in the same heap array */
12106 free(mc_mac, M_DEVBUF);
12111 bxe_set_mc_list(struct bxe_softc *sc)
12113 struct ecore_mcast_ramrod_params rparam = { NULL };
12116 rparam.mcast_obj = &sc->mcast_obj;
12118 BXE_MCAST_LOCK(sc);
12120 /* first, clear all configured multicast MACs */
12121 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
12123 BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc);
12124 BXE_MCAST_UNLOCK(sc);
12128 /* configure a new MACs list */
12129 rc = bxe_init_mcast_macs_list(sc, &rparam);
12131 BLOGE(sc, "Failed to create mcast MACs list (%d)\n", rc);
12132 BXE_MCAST_UNLOCK(sc);
12136 /* Now add the new MACs */
12137 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD);
12139 BLOGE(sc, "Failed to set new mcast config (%d)\n", rc);
12142 bxe_free_mcast_macs_list(&rparam);
12144 BXE_MCAST_UNLOCK(sc);
12150 bxe_set_uc_list(struct bxe_softc *sc)
12152 struct ifnet *ifp = sc->ifnet;
12153 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
12154 struct ifaddr *ifa;
12155 unsigned long ramrod_flags = 0;
12158 #if __FreeBSD_version < 800000
12161 if_addr_rlock(ifp);
12164 /* first schedule a cleanup up of old configuration */
12165 rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE);
12167 BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc);
12168 #if __FreeBSD_version < 800000
12169 IF_ADDR_UNLOCK(ifp);
12171 if_addr_runlock(ifp);
12176 ifa = ifp->if_addr;
12178 if (ifa->ifa_addr->sa_family != AF_LINK) {
12179 ifa = TAILQ_NEXT(ifa, ifa_link);
12183 rc = bxe_set_mac_one(sc, (uint8_t *)LLADDR((struct sockaddr_dl *)ifa->ifa_addr),
12184 mac_obj, TRUE, ECORE_UC_LIST_MAC, &ramrod_flags);
12185 if (rc == -EEXIST) {
12186 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
12187 /* do not treat adding same MAC as an error */
12189 } else if (rc < 0) {
12190 BLOGE(sc, "Failed to schedule ADD operations (%d)\n", rc);
12191 #if __FreeBSD_version < 800000
12192 IF_ADDR_UNLOCK(ifp);
12194 if_addr_runlock(ifp);
12199 ifa = TAILQ_NEXT(ifa, ifa_link);
12202 #if __FreeBSD_version < 800000
12203 IF_ADDR_UNLOCK(ifp);
12205 if_addr_runlock(ifp);
12208 /* Execute the pending commands */
12209 bit_set(&ramrod_flags, RAMROD_CONT);
12210 return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */,
12211 ECORE_UC_LIST_MAC, &ramrod_flags));
12215 bxe_set_rx_mode(struct bxe_softc *sc)
12217 struct ifnet *ifp = sc->ifnet;
12218 uint32_t rx_mode = BXE_RX_MODE_NORMAL;
12220 if (sc->state != BXE_STATE_OPEN) {
12221 BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state);
12225 BLOGD(sc, DBG_SP, "ifp->if_flags=0x%x\n", ifp->if_flags);
12227 if (ifp->if_flags & IFF_PROMISC) {
12228 rx_mode = BXE_RX_MODE_PROMISC;
12229 } else if ((ifp->if_flags & IFF_ALLMULTI) ||
12230 ((ifp->if_amcount > BXE_MAX_MULTICAST) &&
12232 rx_mode = BXE_RX_MODE_ALLMULTI;
12235 /* some multicasts */
12236 if (bxe_set_mc_list(sc) < 0) {
12237 rx_mode = BXE_RX_MODE_ALLMULTI;
12239 if (bxe_set_uc_list(sc) < 0) {
12240 rx_mode = BXE_RX_MODE_PROMISC;
12245 sc->rx_mode = rx_mode;
12247 /* schedule the rx_mode command */
12248 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
12249 BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n");
12250 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
12255 bxe_set_storm_rx_mode(sc);
12260 /* update flags in shmem */
12262 bxe_update_drv_flags(struct bxe_softc *sc,
12266 uint32_t drv_flags;
12268 if (SHMEM2_HAS(sc, drv_flags)) {
12269 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12270 drv_flags = SHMEM2_RD(sc, drv_flags);
12273 SET_FLAGS(drv_flags, flags);
12275 RESET_FLAGS(drv_flags, flags);
12278 SHMEM2_WR(sc, drv_flags, drv_flags);
12279 BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags);
12281 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12285 /* periodic timer callout routine, only runs when the interface is up */
12288 bxe_periodic_callout_func(void *xsc)
12290 struct bxe_softc *sc = (struct bxe_softc *)xsc;
12291 struct bxe_fastpath *fp;
12292 uint16_t tx_bd_avail;
12295 if (!BXE_CORE_TRYLOCK(sc)) {
12296 /* just bail and try again next time */
12298 if ((sc->state == BXE_STATE_OPEN) &&
12299 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12300 /* schedule the next periodic callout */
12301 callout_reset(&sc->periodic_callout, hz,
12302 bxe_periodic_callout_func, sc);
12308 if ((sc->state != BXE_STATE_OPEN) ||
12309 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
12310 BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state);
12311 BXE_CORE_UNLOCK(sc);
12315 #if __FreeBSD_version >= 800000
12317 FOR_EACH_QUEUE(sc, i) {
12320 if (BXE_FP_TX_TRYLOCK(fp)) {
12321 struct ifnet *ifp = sc->ifnet;
12323 * If interface was stopped due to unavailable
12324 * bds, try to process some tx completions
12326 (void) bxe_txeof(sc, fp);
12328 tx_bd_avail = bxe_tx_avail(sc, fp);
12329 if (tx_bd_avail >= BXE_TX_CLEANUP_THRESHOLD) {
12330 bxe_tx_mq_start_locked(sc, ifp, fp, NULL);
12332 BXE_FP_TX_UNLOCK(fp);
12339 if (BXE_FP_TX_TRYLOCK(fp)) {
12340 struct ifnet *ifp = sc->ifnet;
12342 * If interface was stopped due to unavailable
12343 * bds, try to process some tx completions
12345 (void) bxe_txeof(sc, fp);
12347 tx_bd_avail = bxe_tx_avail(sc, fp);
12348 if (tx_bd_avail >= BXE_TX_CLEANUP_THRESHOLD) {
12349 bxe_tx_start_locked(sc, ifp, fp);
12352 BXE_FP_TX_UNLOCK(fp);
12355 #endif /* #if __FreeBSD_version >= 800000 */
12357 /* Check for TX timeouts on any fastpath. */
12358 FOR_EACH_QUEUE(sc, i) {
12359 if (bxe_watchdog(sc, &sc->fp[i]) != 0) {
12360 /* Ruh-Roh, chip was reset! */
12365 if (!CHIP_REV_IS_SLOW(sc)) {
12367 * This barrier is needed to ensure the ordering between the writing
12368 * to the sc->port.pmf in the bxe_nic_load() or bxe_pmf_update() and
12369 * the reading here.
12372 if (sc->port.pmf) {
12373 bxe_acquire_phy_lock(sc);
12374 elink_period_func(&sc->link_params, &sc->link_vars);
12375 bxe_release_phy_lock(sc);
12379 if (IS_PF(sc) && !(sc->flags & BXE_NO_PULSE)) {
12380 int mb_idx = SC_FW_MB_IDX(sc);
12381 uint32_t drv_pulse;
12382 uint32_t mcp_pulse;
12384 ++sc->fw_drv_pulse_wr_seq;
12385 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
12387 drv_pulse = sc->fw_drv_pulse_wr_seq;
12390 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
12391 MCP_PULSE_SEQ_MASK);
12394 * The delta between driver pulse and mcp response should
12395 * be 1 (before mcp response) or 0 (after mcp response).
12397 if ((drv_pulse != mcp_pulse) &&
12398 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
12399 /* someone lost a heartbeat... */
12400 BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
12401 drv_pulse, mcp_pulse);
12405 /* state is BXE_STATE_OPEN */
12406 bxe_stats_handle(sc, STATS_EVENT_UPDATE);
12408 BXE_CORE_UNLOCK(sc);
12410 if ((sc->state == BXE_STATE_OPEN) &&
12411 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12412 /* schedule the next periodic callout */
12413 callout_reset(&sc->periodic_callout, hz,
12414 bxe_periodic_callout_func, sc);
12419 bxe_periodic_start(struct bxe_softc *sc)
12421 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
12422 callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc);
12426 bxe_periodic_stop(struct bxe_softc *sc)
12428 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
12429 callout_drain(&sc->periodic_callout);
12432 /* start the controller */
12433 static __noinline int
12434 bxe_nic_load(struct bxe_softc *sc,
12441 BXE_CORE_LOCK_ASSERT(sc);
12443 BLOGD(sc, DBG_LOAD, "Starting NIC load...\n");
12445 sc->state = BXE_STATE_OPENING_WAITING_LOAD;
12448 /* must be called before memory allocation and HW init */
12449 bxe_ilt_set_info(sc);
12452 sc->last_reported_link_state = LINK_STATE_UNKNOWN;
12454 bxe_set_fp_rx_buf_size(sc);
12456 if (bxe_alloc_fp_buffers(sc) != 0) {
12457 BLOGE(sc, "Failed to allocate fastpath memory\n");
12458 sc->state = BXE_STATE_CLOSED;
12460 goto bxe_nic_load_error0;
12463 if (bxe_alloc_mem(sc) != 0) {
12464 sc->state = BXE_STATE_CLOSED;
12466 goto bxe_nic_load_error0;
12469 if (bxe_alloc_fw_stats_mem(sc) != 0) {
12470 sc->state = BXE_STATE_CLOSED;
12472 goto bxe_nic_load_error0;
12476 /* set pf load just before approaching the MCP */
12477 bxe_set_pf_load(sc);
12479 /* if MCP exists send load request and analyze response */
12480 if (!BXE_NOMCP(sc)) {
12481 /* attempt to load pf */
12482 if (bxe_nic_load_request(sc, &load_code) != 0) {
12483 sc->state = BXE_STATE_CLOSED;
12485 goto bxe_nic_load_error1;
12488 /* what did the MCP say? */
12489 if (bxe_nic_load_analyze_req(sc, load_code) != 0) {
12490 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12491 sc->state = BXE_STATE_CLOSED;
12493 goto bxe_nic_load_error2;
12496 BLOGI(sc, "Device has no MCP!\n");
12497 load_code = bxe_nic_load_no_mcp(sc);
12500 /* mark PMF if applicable */
12501 bxe_nic_load_pmf(sc, load_code);
12503 /* Init Function state controlling object */
12504 bxe_init_func_obj(sc);
12506 /* Initialize HW */
12507 if (bxe_init_hw(sc, load_code) != 0) {
12508 BLOGE(sc, "HW init failed\n");
12509 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12510 sc->state = BXE_STATE_CLOSED;
12512 goto bxe_nic_load_error2;
12516 /* set ALWAYS_ALIVE bit in shmem */
12517 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
12519 sc->flags |= BXE_NO_PULSE;
12521 /* attach interrupts */
12522 if (bxe_interrupt_attach(sc) != 0) {
12523 sc->state = BXE_STATE_CLOSED;
12525 goto bxe_nic_load_error2;
12528 bxe_nic_init(sc, load_code);
12530 /* Init per-function objects */
12533 // XXX bxe_iov_nic_init(sc);
12535 /* set AFEX default VLAN tag to an invalid value */
12536 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
12537 // XXX bxe_nic_load_afex_dcc(sc, load_code);
12539 sc->state = BXE_STATE_OPENING_WAITING_PORT;
12540 rc = bxe_func_start(sc);
12542 BLOGE(sc, "Function start failed! rc = %d\n", rc);
12543 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12544 sc->state = BXE_STATE_ERROR;
12545 goto bxe_nic_load_error3;
12548 /* send LOAD_DONE command to MCP */
12549 if (!BXE_NOMCP(sc)) {
12550 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12552 BLOGE(sc, "MCP response failure, aborting\n");
12553 sc->state = BXE_STATE_ERROR;
12555 goto bxe_nic_load_error3;
12559 rc = bxe_setup_leading(sc);
12561 BLOGE(sc, "Setup leading failed! rc = %d\n", rc);
12562 sc->state = BXE_STATE_ERROR;
12563 goto bxe_nic_load_error3;
12566 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
12567 rc = bxe_setup_queue(sc, &sc->fp[i], FALSE);
12569 BLOGE(sc, "Queue(%d) setup failed rc = %d\n", i, rc);
12570 sc->state = BXE_STATE_ERROR;
12571 goto bxe_nic_load_error3;
12575 rc = bxe_init_rss_pf(sc);
12577 BLOGE(sc, "PF RSS init failed\n");
12578 sc->state = BXE_STATE_ERROR;
12579 goto bxe_nic_load_error3;
12584 /* now when Clients are configured we are ready to work */
12585 sc->state = BXE_STATE_OPEN;
12587 /* Configure a ucast MAC */
12589 rc = bxe_set_eth_mac(sc, TRUE);
12592 BLOGE(sc, "Setting Ethernet MAC failed rc = %d\n", rc);
12593 sc->state = BXE_STATE_ERROR;
12594 goto bxe_nic_load_error3;
12597 if (sc->port.pmf) {
12598 rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN);
12600 sc->state = BXE_STATE_ERROR;
12601 goto bxe_nic_load_error3;
12605 sc->link_params.feature_config_flags &=
12606 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
12608 /* start fast path */
12610 /* Initialize Rx filter */
12611 bxe_set_rx_mode(sc);
12614 switch (/* XXX load_mode */LOAD_OPEN) {
12620 case LOAD_LOOPBACK_EXT:
12621 sc->state = BXE_STATE_DIAG;
12628 if (sc->port.pmf) {
12629 bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
12631 bxe_link_status_update(sc);
12634 /* start the periodic timer callout */
12635 bxe_periodic_start(sc);
12637 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
12638 /* mark driver is loaded in shmem2 */
12639 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
12640 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
12642 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
12643 DRV_FLAGS_CAPABILITIES_LOADED_L2));
12646 /* wait for all pending SP commands to complete */
12647 if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) {
12648 BLOGE(sc, "Timeout waiting for all SPs to complete!\n");
12649 bxe_periodic_stop(sc);
12650 bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE);
12654 /* Tell the stack the driver is running! */
12655 sc->ifnet->if_drv_flags = IFF_DRV_RUNNING;
12657 BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n");
12661 bxe_nic_load_error3:
12664 bxe_int_disable_sync(sc, 1);
12666 /* clean out queued objects */
12667 bxe_squeeze_objects(sc);
12670 bxe_interrupt_detach(sc);
12672 bxe_nic_load_error2:
12674 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
12675 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
12676 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
12681 bxe_nic_load_error1:
12683 /* clear pf_load status, as it was already set */
12685 bxe_clear_pf_load(sc);
12688 bxe_nic_load_error0:
12690 bxe_free_fw_stats_mem(sc);
12691 bxe_free_fp_buffers(sc);
12698 bxe_init_locked(struct bxe_softc *sc)
12700 int other_engine = SC_PATH(sc) ? 0 : 1;
12701 uint8_t other_load_status, load_status;
12702 uint8_t global = FALSE;
12705 BXE_CORE_LOCK_ASSERT(sc);
12707 /* check if the driver is already running */
12708 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
12709 BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n");
12713 bxe_set_power_state(sc, PCI_PM_D0);
12716 * If parity occurred during the unload, then attentions and/or
12717 * RECOVERY_IN_PROGRES may still be set. If so we want the first function
12718 * loaded on the current engine to complete the recovery. Parity recovery
12719 * is only relevant for PF driver.
12722 other_load_status = bxe_get_load_status(sc, other_engine);
12723 load_status = bxe_get_load_status(sc, SC_PATH(sc));
12725 if (!bxe_reset_is_done(sc, SC_PATH(sc)) ||
12726 bxe_chk_parity_attn(sc, &global, TRUE)) {
12729 * If there are attentions and they are in global blocks, set
12730 * the GLOBAL_RESET bit regardless whether it will be this
12731 * function that will complete the recovery or not.
12734 bxe_set_reset_global(sc);
12738 * Only the first function on the current engine should try
12739 * to recover in open. In case of attentions in global blocks
12740 * only the first in the chip should try to recover.
12742 if ((!load_status && (!global || !other_load_status)) &&
12743 bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) {
12744 BLOGI(sc, "Recovered during init\n");
12748 /* recovery has failed... */
12749 bxe_set_power_state(sc, PCI_PM_D3hot);
12750 sc->recovery_state = BXE_RECOVERY_FAILED;
12752 BLOGE(sc, "Recovery flow hasn't properly "
12753 "completed yet, try again later. "
12754 "If you still see this message after a "
12755 "few retries then power cycle is required.\n");
12758 goto bxe_init_locked_done;
12763 sc->recovery_state = BXE_RECOVERY_DONE;
12765 rc = bxe_nic_load(sc, LOAD_OPEN);
12767 bxe_init_locked_done:
12770 /* Tell the stack the driver is NOT running! */
12771 BLOGE(sc, "Initialization failed, "
12772 "stack notified driver is NOT running!\n");
12773 sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING;
12780 bxe_stop_locked(struct bxe_softc *sc)
12782 BXE_CORE_LOCK_ASSERT(sc);
12783 return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE));
12787 * Handles controller initialization when called from an unlocked routine.
12788 * ifconfig calls this function.
12794 bxe_init(void *xsc)
12796 struct bxe_softc *sc = (struct bxe_softc *)xsc;
12799 bxe_init_locked(sc);
12800 BXE_CORE_UNLOCK(sc);
12804 bxe_init_ifnet(struct bxe_softc *sc)
12808 /* ifconfig entrypoint for media type/status reporting */
12809 ifmedia_init(&sc->ifmedia, IFM_IMASK,
12810 bxe_ifmedia_update,
12811 bxe_ifmedia_status);
12813 /* set the default interface values */
12814 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL);
12815 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL);
12816 ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO));
12818 sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */
12820 /* allocate the ifnet structure */
12821 if ((ifp = if_alloc(IFT_ETHER)) == NULL) {
12822 BLOGE(sc, "Interface allocation failed!\n");
12826 ifp->if_softc = sc;
12827 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
12828 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
12829 ifp->if_ioctl = bxe_ioctl;
12830 ifp->if_start = bxe_tx_start;
12831 #if __FreeBSD_version >= 800000
12832 ifp->if_transmit = bxe_tx_mq_start;
12833 ifp->if_qflush = bxe_mq_flush;
12838 ifp->if_init = bxe_init;
12839 ifp->if_mtu = sc->mtu;
12840 ifp->if_hwassist = (CSUM_IP |
12846 ifp->if_capabilities =
12847 #if __FreeBSD_version < 700000
12849 IFCAP_VLAN_HWTAGGING |
12855 IFCAP_VLAN_HWTAGGING |
12857 IFCAP_VLAN_HWFILTER |
12858 IFCAP_VLAN_HWCSUM |
12866 ifp->if_capenable = ifp->if_capabilities;
12867 ifp->if_capenable &= ~IFCAP_WOL_MAGIC; /* XXX not yet... */
12868 #if __FreeBSD_version < 1000025
12869 ifp->if_baudrate = 1000000000;
12871 if_initbaudrate(ifp, IF_Gbps(10));
12873 ifp->if_snd.ifq_drv_maxlen = sc->tx_ring_size;
12875 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
12876 IFQ_SET_READY(&ifp->if_snd);
12880 /* attach to the Ethernet interface list */
12881 ether_ifattach(ifp, sc->link_params.mac_addr);
12887 bxe_deallocate_bars(struct bxe_softc *sc)
12891 for (i = 0; i < MAX_BARS; i++) {
12892 if (sc->bar[i].resource != NULL) {
12893 bus_release_resource(sc->dev,
12896 sc->bar[i].resource);
12897 BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n",
12904 bxe_allocate_bars(struct bxe_softc *sc)
12909 memset(sc->bar, 0, sizeof(sc->bar));
12911 for (i = 0; i < MAX_BARS; i++) {
12913 /* memory resources reside at BARs 0, 2, 4 */
12914 /* Run `pciconf -lb` to see mappings */
12915 if ((i != 0) && (i != 2) && (i != 4)) {
12919 sc->bar[i].rid = PCIR_BAR(i);
12923 flags |= RF_SHAREABLE;
12926 if ((sc->bar[i].resource =
12927 bus_alloc_resource_any(sc->dev,
12934 sc->bar[i].tag = rman_get_bustag(sc->bar[i].resource);
12935 sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource);
12936 sc->bar[i].kva = (vm_offset_t)rman_get_virtual(sc->bar[i].resource);
12938 BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %p-%p (%ld) -> %p\n",
12940 (void *)rman_get_start(sc->bar[i].resource),
12941 (void *)rman_get_end(sc->bar[i].resource),
12942 rman_get_size(sc->bar[i].resource),
12943 (void *)sc->bar[i].kva);
12950 bxe_get_function_num(struct bxe_softc *sc)
12955 * Read the ME register to get the function number. The ME register
12956 * holds the relative-function number and absolute-function number. The
12957 * absolute-function number appears only in E2 and above. Before that
12958 * these bits always contained zero, therefore we cannot blindly use them.
12961 val = REG_RD(sc, BAR_ME_REGISTER);
12964 (uint8_t)((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
12966 (uint8_t)((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) & 1;
12968 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
12969 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
12971 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
12974 BLOGD(sc, DBG_LOAD,
12975 "Relative function %d, Absolute function %d, Path %d\n",
12976 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
12980 bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc)
12982 uint32_t shmem2_size;
12984 uint32_t mf_cfg_offset_value;
12987 offset = (SHMEM_RD(sc, func_mb) +
12988 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
12991 if (sc->devinfo.shmem2_base != 0) {
12992 shmem2_size = SHMEM2_RD(sc, size);
12993 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
12994 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
12995 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
12996 offset = mf_cfg_offset_value;
13005 bxe_pcie_capability_read(struct bxe_softc *sc,
13011 /* ensure PCIe capability is enabled */
13012 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) {
13013 if (pcie_reg != 0) {
13014 BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg);
13015 return (pci_read_config(sc->dev, (pcie_reg + reg), width));
13019 BLOGE(sc, "PCIe capability NOT FOUND!!!\n");
13025 bxe_is_pcie_pending(struct bxe_softc *sc)
13027 return (bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA, 2) &
13028 PCIM_EXP_STA_TRANSACTION_PND);
13032 * Walk the PCI capabiites list for the device to find what features are
13033 * supported. These capabilites may be enabled/disabled by firmware so it's
13034 * best to walk the list rather than make assumptions.
13037 bxe_probe_pci_caps(struct bxe_softc *sc)
13039 uint16_t link_status;
13042 /* check if PCI Power Management is enabled */
13043 if (pci_find_cap(sc->dev, PCIY_PMG, ®) == 0) {
13045 BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg);
13047 sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG;
13048 sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg;
13052 link_status = bxe_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA, 2);
13054 /* handle PCIe 2.0 workarounds for 57710 */
13055 if (CHIP_IS_E1(sc)) {
13056 /* workaround for 57710 errata E4_57710_27462 */
13057 sc->devinfo.pcie_link_speed =
13058 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
13060 /* workaround for 57710 errata E4_57710_27488 */
13061 sc->devinfo.pcie_link_width =
13062 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
13063 if (sc->devinfo.pcie_link_speed > 1) {
13064 sc->devinfo.pcie_link_width =
13065 ((link_status & PCIM_LINK_STA_WIDTH) >> 4) >> 1;
13068 sc->devinfo.pcie_link_speed =
13069 (link_status & PCIM_LINK_STA_SPEED);
13070 sc->devinfo.pcie_link_width =
13071 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
13074 BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n",
13075 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
13077 sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG;
13078 sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg;
13080 /* check if MSI capability is enabled */
13081 if (pci_find_cap(sc->dev, PCIY_MSI, ®) == 0) {
13083 BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg);
13085 sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG;
13086 sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg;
13090 /* check if MSI-X capability is enabled */
13091 if (pci_find_cap(sc->dev, PCIY_MSIX, ®) == 0) {
13093 BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg);
13095 sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG;
13096 sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg;
13102 bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc)
13104 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13107 /* get the outer vlan if we're in switch-dependent mode */
13109 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13110 mf_info->ext_id = (uint16_t)val;
13112 mf_info->multi_vnics_mode = 1;
13114 if (!VALID_OVLAN(mf_info->ext_id)) {
13115 BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id);
13119 /* get the capabilities */
13120 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13121 FUNC_MF_CFG_PROTOCOL_ISCSI) {
13122 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
13123 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13124 FUNC_MF_CFG_PROTOCOL_FCOE) {
13125 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
13127 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
13130 mf_info->vnics_per_port =
13131 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13137 bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc)
13139 uint32_t retval = 0;
13142 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13144 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
13145 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
13146 retval |= MF_PROTO_SUPPORT_ETHERNET;
13148 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
13149 retval |= MF_PROTO_SUPPORT_ISCSI;
13151 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
13152 retval |= MF_PROTO_SUPPORT_FCOE;
13160 bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc)
13162 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13166 * There is no outer vlan if we're in switch-independent mode.
13167 * If the mac is valid then assume multi-function.
13170 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13172 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
13174 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13176 mf_info->vnics_per_port =
13177 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13183 bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc)
13185 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13186 uint32_t e1hov_tag;
13187 uint32_t func_config;
13188 uint32_t niv_config;
13190 mf_info->multi_vnics_mode = 1;
13192 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13193 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13194 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
13197 (uint16_t)((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
13198 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
13200 mf_info->default_vlan =
13201 (uint16_t)((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
13202 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
13204 mf_info->niv_allowed_priorities =
13205 (uint8_t)((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
13206 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
13208 mf_info->niv_default_cos =
13209 (uint8_t)((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
13210 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
13212 mf_info->afex_vlan_mode =
13213 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
13214 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
13216 mf_info->niv_mba_enabled =
13217 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
13218 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
13220 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13222 mf_info->vnics_per_port =
13223 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13229 bxe_check_valid_mf_cfg(struct bxe_softc *sc)
13231 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13238 BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n",
13240 BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n",
13241 mf_info->mf_config[SC_VN(sc)]);
13242 BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n",
13243 mf_info->multi_vnics_mode);
13244 BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n",
13245 mf_info->vnics_per_port);
13246 BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n",
13248 BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n",
13249 mf_info->min_bw[0], mf_info->min_bw[1],
13250 mf_info->min_bw[2], mf_info->min_bw[3]);
13251 BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n",
13252 mf_info->max_bw[0], mf_info->max_bw[1],
13253 mf_info->max_bw[2], mf_info->max_bw[3]);
13254 BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n",
13257 /* various MF mode sanity checks... */
13259 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
13260 BLOGE(sc, "Enumerated function %d is marked as hidden\n",
13265 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
13266 BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n",
13267 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
13271 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13272 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
13273 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
13274 BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n",
13275 SC_VN(sc), OVLAN(sc));
13279 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
13280 BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n",
13281 mf_info->multi_vnics_mode, OVLAN(sc));
13286 * Verify all functions are either MF or SF mode. If MF, make sure
13287 * sure that all non-hidden functions have a valid ovlan. If SF,
13288 * make sure that all non-hidden functions have an invalid ovlan.
13290 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13291 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13292 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13293 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13294 (((mf_info->multi_vnics_mode) && !VALID_OVLAN(ovlan1)) ||
13295 ((!mf_info->multi_vnics_mode) && VALID_OVLAN(ovlan1)))) {
13296 BLOGE(sc, "mf_mode=SD function %d MF config "
13297 "mismatch, multi_vnics_mode=%d ovlan=%d\n",
13298 i, mf_info->multi_vnics_mode, ovlan1);
13303 /* Verify all funcs on the same port each have a different ovlan. */
13304 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13305 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13306 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13307 /* iterate from the next function on the port to the max func */
13308 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
13309 mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config);
13310 ovlan2 = MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
13311 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13312 VALID_OVLAN(ovlan1) &&
13313 !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE) &&
13314 VALID_OVLAN(ovlan2) &&
13315 (ovlan1 == ovlan2)) {
13316 BLOGE(sc, "mf_mode=SD functions %d and %d "
13317 "have the same ovlan (%d)\n",
13323 } /* MULTI_FUNCTION_SD */
13329 bxe_get_mf_cfg_info(struct bxe_softc *sc)
13331 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13332 uint32_t val, mac_upper;
13335 /* initialize mf_info defaults */
13336 mf_info->vnics_per_port = 1;
13337 mf_info->multi_vnics_mode = FALSE;
13338 mf_info->path_has_ovlan = FALSE;
13339 mf_info->mf_mode = SINGLE_FUNCTION;
13341 if (!CHIP_IS_MF_CAP(sc)) {
13345 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
13346 BLOGE(sc, "Invalid mf_cfg_base!\n");
13350 /* get the MF mode (switch dependent / independent / single-function) */
13352 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13354 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK)
13356 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
13358 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13360 /* check for legal upper mac bytes */
13361 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
13362 mf_info->mf_mode = MULTI_FUNCTION_SI;
13364 BLOGE(sc, "Invalid config for Switch Independent mode\n");
13369 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
13370 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
13372 /* get outer vlan configuration */
13373 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13375 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
13376 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
13377 mf_info->mf_mode = MULTI_FUNCTION_SD;
13379 BLOGE(sc, "Invalid config for Switch Dependent mode\n");
13384 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
13386 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
13389 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
13392 * Mark MF mode as NIV if MCP version includes NPAR-SD support
13393 * and the MAC address is valid.
13395 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13397 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
13398 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
13399 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
13401 BLOGE(sc, "Invalid config for AFEX mode\n");
13408 BLOGE(sc, "Unknown MF mode (0x%08x)\n",
13409 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
13414 /* set path mf_mode (which could be different than function mf_mode) */
13415 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13416 mf_info->path_has_ovlan = TRUE;
13417 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
13419 * Decide on path multi vnics mode. If we're not in MF mode and in
13420 * 4-port mode, this is good enough to check vnic-0 of the other port
13423 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
13424 uint8_t other_port = !(PORT_ID(sc) & 1);
13425 uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port));
13427 val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag);
13429 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t)val) ? 1 : 0;
13433 if (mf_info->mf_mode == SINGLE_FUNCTION) {
13434 /* invalid MF config */
13435 if (SC_VN(sc) >= 1) {
13436 BLOGE(sc, "VNIC ID >= 1 in SF mode\n");
13443 /* get the MF configuration */
13444 mf_info->mf_config[SC_VN(sc)] =
13445 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13447 switch(mf_info->mf_mode)
13449 case MULTI_FUNCTION_SD:
13451 bxe_get_shmem_mf_cfg_info_sd(sc);
13454 case MULTI_FUNCTION_SI:
13456 bxe_get_shmem_mf_cfg_info_si(sc);
13459 case MULTI_FUNCTION_AFEX:
13461 bxe_get_shmem_mf_cfg_info_niv(sc);
13466 BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n",
13471 /* get the congestion management parameters */
13474 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13475 /* get min/max bw */
13476 val = MFCFG_RD(sc, func_mf_config[i].config);
13477 mf_info->min_bw[vnic] =
13478 ((val & FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT);
13479 mf_info->max_bw[vnic] =
13480 ((val & FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT);
13484 return (bxe_check_valid_mf_cfg(sc));
13488 bxe_get_shmem_info(struct bxe_softc *sc)
13491 uint32_t mac_hi, mac_lo, val;
13493 port = SC_PORT(sc);
13494 mac_hi = mac_lo = 0;
13496 sc->link_params.sc = sc;
13497 sc->link_params.port = port;
13499 /* get the hardware config info */
13500 sc->devinfo.hw_config =
13501 SHMEM_RD(sc, dev_info.shared_hw_config.config);
13502 sc->devinfo.hw_config2 =
13503 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
13505 sc->link_params.hw_led_mode =
13506 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
13507 SHARED_HW_CFG_LED_MODE_SHIFT);
13509 /* get the port feature config */
13511 SHMEM_RD(sc, dev_info.port_feature_config[port].config),
13513 /* get the link params */
13514 sc->link_params.speed_cap_mask[0] =
13515 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask);
13516 sc->link_params.speed_cap_mask[1] =
13517 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2);
13519 /* get the lane config */
13520 sc->link_params.lane_config =
13521 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
13523 /* get the link config */
13524 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
13525 sc->port.link_config[ELINK_INT_PHY] = val;
13526 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
13527 sc->port.link_config[ELINK_EXT_PHY1] =
13528 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
13530 /* get the override preemphasis flag and enable it or turn it off */
13531 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13532 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
13533 sc->link_params.feature_config_flags |=
13534 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13536 sc->link_params.feature_config_flags &=
13537 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13540 /* get the initial value of the link params */
13541 sc->link_params.multi_phy_config =
13542 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
13544 /* get external phy info */
13545 sc->port.ext_phy_config =
13546 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
13548 /* get the multifunction configuration */
13549 bxe_get_mf_cfg_info(sc);
13551 /* get the mac address */
13553 mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13554 mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
13556 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
13557 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
13560 if ((mac_lo == 0) && (mac_hi == 0)) {
13561 *sc->mac_addr_str = 0;
13562 BLOGE(sc, "No Ethernet address programmed!\n");
13564 sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8);
13565 sc->link_params.mac_addr[1] = (uint8_t)(mac_hi);
13566 sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24);
13567 sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16);
13568 sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8);
13569 sc->link_params.mac_addr[5] = (uint8_t)(mac_lo);
13570 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
13571 "%02x:%02x:%02x:%02x:%02x:%02x",
13572 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1],
13573 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3],
13574 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]);
13575 BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str);
13582 bxe_get_tunable_params(struct bxe_softc *sc)
13584 /* sanity checks */
13586 if ((bxe_interrupt_mode != INTR_MODE_INTX) &&
13587 (bxe_interrupt_mode != INTR_MODE_MSI) &&
13588 (bxe_interrupt_mode != INTR_MODE_MSIX)) {
13589 BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode);
13590 bxe_interrupt_mode = INTR_MODE_MSIX;
13593 if ((bxe_queue_count < 0) || (bxe_queue_count > MAX_RSS_CHAINS)) {
13594 BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count);
13595 bxe_queue_count = 0;
13598 if ((bxe_max_rx_bufs < 1) || (bxe_max_rx_bufs > RX_BD_USABLE)) {
13599 if (bxe_max_rx_bufs == 0) {
13600 bxe_max_rx_bufs = RX_BD_USABLE;
13602 BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs);
13603 bxe_max_rx_bufs = 2048;
13607 if ((bxe_hc_rx_ticks < 1) || (bxe_hc_rx_ticks > 100)) {
13608 BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks);
13609 bxe_hc_rx_ticks = 25;
13612 if ((bxe_hc_tx_ticks < 1) || (bxe_hc_tx_ticks > 100)) {
13613 BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks);
13614 bxe_hc_tx_ticks = 50;
13617 if (bxe_max_aggregation_size == 0) {
13618 bxe_max_aggregation_size = TPA_AGG_SIZE;
13621 if (bxe_max_aggregation_size > 0xffff) {
13622 BLOGW(sc, "invalid max_aggregation_size (%d)\n",
13623 bxe_max_aggregation_size);
13624 bxe_max_aggregation_size = TPA_AGG_SIZE;
13627 if ((bxe_mrrs < -1) || (bxe_mrrs > 3)) {
13628 BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs);
13632 if ((bxe_autogreeen < 0) || (bxe_autogreeen > 2)) {
13633 BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen);
13634 bxe_autogreeen = 0;
13637 if ((bxe_udp_rss < 0) || (bxe_udp_rss > 1)) {
13638 BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss);
13642 /* pull in user settings */
13644 sc->interrupt_mode = bxe_interrupt_mode;
13645 sc->max_rx_bufs = bxe_max_rx_bufs;
13646 sc->hc_rx_ticks = bxe_hc_rx_ticks;
13647 sc->hc_tx_ticks = bxe_hc_tx_ticks;
13648 sc->max_aggregation_size = bxe_max_aggregation_size;
13649 sc->mrrs = bxe_mrrs;
13650 sc->autogreeen = bxe_autogreeen;
13651 sc->udp_rss = bxe_udp_rss;
13653 if (bxe_interrupt_mode == INTR_MODE_INTX) {
13654 sc->num_queues = 1;
13655 } else { /* INTR_MODE_MSI or INTR_MODE_MSIX */
13657 min((bxe_queue_count ? bxe_queue_count : mp_ncpus),
13659 if (sc->num_queues > mp_ncpus) {
13660 sc->num_queues = mp_ncpus;
13664 BLOGD(sc, DBG_LOAD,
13667 "interrupt_mode=%d "
13672 "max_aggregation_size=%d "
13677 sc->interrupt_mode,
13682 sc->max_aggregation_size,
13689 bxe_media_detect(struct bxe_softc *sc)
13692 uint32_t phy_idx = bxe_get_cur_phy_idx(sc);
13694 switch (sc->link_params.phy[phy_idx].media_type) {
13695 case ELINK_ETH_PHY_SFPP_10G_FIBER:
13696 case ELINK_ETH_PHY_XFP_FIBER:
13697 BLOGI(sc, "Found 10Gb Fiber media.\n");
13698 sc->media = IFM_10G_SR;
13699 port_type = PORT_FIBRE;
13701 case ELINK_ETH_PHY_SFP_1G_FIBER:
13702 BLOGI(sc, "Found 1Gb Fiber media.\n");
13703 sc->media = IFM_1000_SX;
13704 port_type = PORT_FIBRE;
13706 case ELINK_ETH_PHY_KR:
13707 case ELINK_ETH_PHY_CX4:
13708 BLOGI(sc, "Found 10GBase-CX4 media.\n");
13709 sc->media = IFM_10G_CX4;
13710 port_type = PORT_FIBRE;
13712 case ELINK_ETH_PHY_DA_TWINAX:
13713 BLOGI(sc, "Found 10Gb Twinax media.\n");
13714 sc->media = IFM_10G_TWINAX;
13715 port_type = PORT_DA;
13717 case ELINK_ETH_PHY_BASE_T:
13718 if (sc->link_params.speed_cap_mask[0] &
13719 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
13720 BLOGI(sc, "Found 10GBase-T media.\n");
13721 sc->media = IFM_10G_T;
13722 port_type = PORT_TP;
13724 BLOGI(sc, "Found 1000Base-T media.\n");
13725 sc->media = IFM_1000_T;
13726 port_type = PORT_TP;
13729 case ELINK_ETH_PHY_NOT_PRESENT:
13730 BLOGI(sc, "Media not present.\n");
13732 port_type = PORT_OTHER;
13734 case ELINK_ETH_PHY_UNSPECIFIED:
13736 BLOGI(sc, "Unknown media!\n");
13738 port_type = PORT_OTHER;
13744 #define GET_FIELD(value, fname) \
13745 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
13746 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
13747 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
13750 bxe_get_igu_cam_info(struct bxe_softc *sc)
13752 int pfid = SC_FUNC(sc);
13755 uint8_t fid, igu_sb_cnt = 0;
13757 sc->igu_base_sb = 0xff;
13759 if (CHIP_INT_MODE_IS_BC(sc)) {
13760 int vn = SC_VN(sc);
13761 igu_sb_cnt = sc->igu_sb_cnt;
13762 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
13764 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
13765 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
13769 /* IGU in normal mode - read CAM */
13770 for (igu_sb_id = 0;
13771 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
13773 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
13774 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
13777 fid = IGU_FID(val);
13778 if ((fid & IGU_FID_ENCODE_IS_PF)) {
13779 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
13782 if (IGU_VEC(val) == 0) {
13783 /* default status block */
13784 sc->igu_dsb_id = igu_sb_id;
13786 if (sc->igu_base_sb == 0xff) {
13787 sc->igu_base_sb = igu_sb_id;
13795 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
13796 * that number of CAM entries will not be equal to the value advertised in
13797 * PCI. Driver should use the minimal value of both as the actual status
13800 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
13802 if (igu_sb_cnt == 0) {
13803 BLOGE(sc, "CAM configuration error\n");
13811 * Gather various information from the device config space, the device itself,
13812 * shmem, and the user input.
13815 bxe_get_device_info(struct bxe_softc *sc)
13820 /* Get the data for the device */
13821 sc->devinfo.vendor_id = pci_get_vendor(sc->dev);
13822 sc->devinfo.device_id = pci_get_device(sc->dev);
13823 sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev);
13824 sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev);
13826 /* get the chip revision (chip metal comes from pci config space) */
13827 sc->devinfo.chip_id =
13828 sc->link_params.chip_id =
13829 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
13830 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
13831 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
13832 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
13834 /* force 57811 according to MISC register */
13835 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
13836 if (CHIP_IS_57810(sc)) {
13837 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
13838 (sc->devinfo.chip_id & 0x0000ffff));
13839 } else if (CHIP_IS_57810_MF(sc)) {
13840 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
13841 (sc->devinfo.chip_id & 0x0000ffff));
13843 sc->devinfo.chip_id |= 0x1;
13846 BLOGD(sc, DBG_LOAD,
13847 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n",
13848 sc->devinfo.chip_id,
13849 ((sc->devinfo.chip_id >> 16) & 0xffff),
13850 ((sc->devinfo.chip_id >> 12) & 0xf),
13851 ((sc->devinfo.chip_id >> 4) & 0xff),
13852 ((sc->devinfo.chip_id >> 0) & 0xf));
13854 val = (REG_RD(sc, 0x2874) & 0x55);
13855 if ((sc->devinfo.chip_id & 0x1) ||
13856 (CHIP_IS_E1(sc) && val) ||
13857 (CHIP_IS_E1H(sc) && (val == 0x55))) {
13858 sc->flags |= BXE_ONE_PORT_FLAG;
13859 BLOGD(sc, DBG_LOAD, "single port device\n");
13862 /* set the doorbell size */
13863 sc->doorbell_size = (1 << BXE_DB_SHIFT);
13865 /* determine whether the device is in 2 port or 4 port mode */
13866 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/
13867 if (CHIP_IS_E2E3(sc)) {
13869 * Read port4mode_en_ovwr[0]:
13870 * If 1, four port mode is in port4mode_en_ovwr[1].
13871 * If 0, four port mode is in port4mode_en[0].
13873 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
13875 val = ((val >> 1) & 1);
13877 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
13880 sc->devinfo.chip_port_mode =
13881 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
13883 BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2");
13886 /* get the function and path info for the device */
13887 bxe_get_function_num(sc);
13889 /* get the shared memory base address */
13890 sc->devinfo.shmem_base =
13891 sc->link_params.shmem_base =
13892 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
13893 sc->devinfo.shmem2_base =
13894 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
13895 MISC_REG_GENERIC_CR_0));
13897 BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n",
13898 sc->devinfo.shmem_base, sc->devinfo.shmem2_base);
13900 if (!sc->devinfo.shmem_base) {
13901 /* this should ONLY prevent upcoming shmem reads */
13902 BLOGI(sc, "MCP not active\n");
13903 sc->flags |= BXE_NO_MCP_FLAG;
13907 /* make sure the shared memory contents are valid */
13908 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
13909 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
13910 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
13911 BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val);
13914 BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val);
13916 /* get the bootcode version */
13917 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
13918 snprintf(sc->devinfo.bc_ver_str,
13919 sizeof(sc->devinfo.bc_ver_str),
13921 ((sc->devinfo.bc_ver >> 24) & 0xff),
13922 ((sc->devinfo.bc_ver >> 16) & 0xff),
13923 ((sc->devinfo.bc_ver >> 8) & 0xff));
13924 BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str);
13926 /* get the bootcode shmem address */
13927 sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc);
13928 BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base);
13930 /* clean indirect addresses as they're not used */
13931 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
13933 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
13934 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
13935 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
13936 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
13937 if (CHIP_IS_E1x(sc)) {
13938 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
13939 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
13940 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
13941 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
13945 * Enable internal target-read (in case we are probed after PF
13946 * FLR). Must be done prior to any BAR read access. Only for
13949 if (!CHIP_IS_E1x(sc)) {
13950 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13954 /* get the nvram size */
13955 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
13956 sc->devinfo.flash_size =
13957 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
13958 BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size);
13960 /* get PCI capabilites */
13961 bxe_probe_pci_caps(sc);
13963 bxe_set_power_state(sc, PCI_PM_D0);
13965 /* get various configuration parameters from shmem */
13966 bxe_get_shmem_info(sc);
13968 if (sc->devinfo.pcie_msix_cap_reg != 0) {
13969 val = pci_read_config(sc->dev,
13970 (sc->devinfo.pcie_msix_cap_reg +
13973 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
13975 sc->igu_sb_cnt = 1;
13978 sc->igu_base_addr = BAR_IGU_INTMEM;
13980 /* initialize IGU parameters */
13981 if (CHIP_IS_E1x(sc)) {
13982 sc->devinfo.int_block = INT_BLOCK_HC;
13983 sc->igu_dsb_id = DEF_SB_IGU_ID;
13984 sc->igu_base_sb = 0;
13986 sc->devinfo.int_block = INT_BLOCK_IGU;
13988 /* do not allow device reset during IGU info preocessing */
13989 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
13991 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
13993 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
13996 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n");
13998 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
13999 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
14000 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
14002 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14007 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14008 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n");
14009 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14014 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
14015 BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n");
14016 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
14018 BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n");
14021 rc = bxe_get_igu_cam_info(sc);
14023 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14031 * Get base FW non-default (fast path) status block ID. This value is
14032 * used to initialize the fw_sb_id saved on the fp/queue structure to
14033 * determine the id used by the FW.
14035 if (CHIP_IS_E1x(sc)) {
14036 sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
14039 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
14040 * the same queue are indicated on the same IGU SB). So we prefer
14041 * FW and IGU SBs to be the same value.
14043 sc->base_fw_ndsb = sc->igu_base_sb;
14046 BLOGD(sc, DBG_LOAD,
14047 "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n",
14048 sc->igu_dsb_id, sc->igu_base_sb,
14049 sc->igu_sb_cnt, sc->base_fw_ndsb);
14051 elink_phy_probe(&sc->link_params);
14057 bxe_link_settings_supported(struct bxe_softc *sc,
14058 uint32_t switch_cfg)
14060 uint32_t cfg_size = 0;
14062 uint8_t port = SC_PORT(sc);
14064 /* aggregation of supported attributes of all external phys */
14065 sc->port.supported[0] = 0;
14066 sc->port.supported[1] = 0;
14068 switch (sc->link_params.num_phys) {
14070 sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported;
14074 sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported;
14078 if (sc->link_params.multi_phy_config &
14079 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
14080 sc->port.supported[1] =
14081 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14082 sc->port.supported[0] =
14083 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14085 sc->port.supported[0] =
14086 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14087 sc->port.supported[1] =
14088 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14094 if (!(sc->port.supported[0] || sc->port.supported[1])) {
14095 BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n",
14097 dev_info.port_hw_config[port].external_phy_config),
14099 dev_info.port_hw_config[port].external_phy_config2));
14103 if (CHIP_IS_E3(sc))
14104 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
14106 switch (switch_cfg) {
14107 case ELINK_SWITCH_CFG_1G:
14108 sc->port.phy_addr =
14109 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
14111 case ELINK_SWITCH_CFG_10G:
14112 sc->port.phy_addr =
14113 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
14116 BLOGE(sc, "Invalid switch config in link_config=0x%08x\n",
14117 sc->port.link_config[0]);
14122 BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr);
14124 /* mask what we support according to speed_cap_mask per configuration */
14125 for (idx = 0; idx < cfg_size; idx++) {
14126 if (!(sc->link_params.speed_cap_mask[idx] &
14127 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
14128 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half;
14131 if (!(sc->link_params.speed_cap_mask[idx] &
14132 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
14133 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full;
14136 if (!(sc->link_params.speed_cap_mask[idx] &
14137 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
14138 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half;
14141 if (!(sc->link_params.speed_cap_mask[idx] &
14142 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
14143 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full;
14146 if (!(sc->link_params.speed_cap_mask[idx] &
14147 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
14148 sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full;
14151 if (!(sc->link_params.speed_cap_mask[idx] &
14152 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
14153 sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full;
14156 if (!(sc->link_params.speed_cap_mask[idx] &
14157 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
14158 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full;
14161 if (!(sc->link_params.speed_cap_mask[idx] &
14162 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
14163 sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full;
14167 BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n",
14168 sc->port.supported[0], sc->port.supported[1]);
14172 bxe_link_settings_requested(struct bxe_softc *sc)
14174 uint32_t link_config;
14176 uint32_t cfg_size = 0;
14178 sc->port.advertising[0] = 0;
14179 sc->port.advertising[1] = 0;
14181 switch (sc->link_params.num_phys) {
14191 for (idx = 0; idx < cfg_size; idx++) {
14192 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
14193 link_config = sc->port.link_config[idx];
14195 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
14196 case PORT_FEATURE_LINK_SPEED_AUTO:
14197 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
14198 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14199 sc->port.advertising[idx] |= sc->port.supported[idx];
14200 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
14201 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
14202 sc->port.advertising[idx] |=
14203 (ELINK_SUPPORTED_100baseT_Half |
14204 ELINK_SUPPORTED_100baseT_Full);
14206 /* force 10G, no AN */
14207 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14208 sc->port.advertising[idx] |=
14209 (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
14214 case PORT_FEATURE_LINK_SPEED_10M_FULL:
14215 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) {
14216 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14217 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full |
14220 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14221 "speed_cap_mask=0x%08x\n",
14222 link_config, sc->link_params.speed_cap_mask[idx]);
14227 case PORT_FEATURE_LINK_SPEED_10M_HALF:
14228 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) {
14229 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14230 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14231 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half |
14234 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14235 "speed_cap_mask=0x%08x\n",
14236 link_config, sc->link_params.speed_cap_mask[idx]);
14241 case PORT_FEATURE_LINK_SPEED_100M_FULL:
14242 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) {
14243 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14244 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full |
14247 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14248 "speed_cap_mask=0x%08x\n",
14249 link_config, sc->link_params.speed_cap_mask[idx]);
14254 case PORT_FEATURE_LINK_SPEED_100M_HALF:
14255 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) {
14256 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14257 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14258 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half |
14261 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14262 "speed_cap_mask=0x%08x\n",
14263 link_config, sc->link_params.speed_cap_mask[idx]);
14268 case PORT_FEATURE_LINK_SPEED_1G:
14269 if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) {
14270 sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000;
14271 sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full |
14274 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14275 "speed_cap_mask=0x%08x\n",
14276 link_config, sc->link_params.speed_cap_mask[idx]);
14281 case PORT_FEATURE_LINK_SPEED_2_5G:
14282 if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) {
14283 sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500;
14284 sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full |
14287 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14288 "speed_cap_mask=0x%08x\n",
14289 link_config, sc->link_params.speed_cap_mask[idx]);
14294 case PORT_FEATURE_LINK_SPEED_10G_CX4:
14295 if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) {
14296 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14297 sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full |
14300 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14301 "speed_cap_mask=0x%08x\n",
14302 link_config, sc->link_params.speed_cap_mask[idx]);
14307 case PORT_FEATURE_LINK_SPEED_20G:
14308 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
14312 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14313 "speed_cap_mask=0x%08x\n",
14314 link_config, sc->link_params.speed_cap_mask[idx]);
14315 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14316 sc->port.advertising[idx] = sc->port.supported[idx];
14320 sc->link_params.req_flow_ctrl[idx] =
14321 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
14323 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
14324 if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
14325 sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE;
14327 bxe_set_requested_fc(sc);
14331 BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d "
14332 "req_flow_ctrl=0x%x advertising=0x%x\n",
14333 sc->link_params.req_line_speed[idx],
14334 sc->link_params.req_duplex[idx],
14335 sc->link_params.req_flow_ctrl[idx],
14336 sc->port.advertising[idx]);
14341 bxe_get_phy_info(struct bxe_softc *sc)
14343 uint8_t port = SC_PORT(sc);
14344 uint32_t config = sc->port.config;
14347 /* shmem data already read in bxe_get_shmem_info() */
14349 BLOGD(sc, DBG_LOAD, "lane_config=0x%08x speed_cap_mask0=0x%08x "
14350 "link_config0=0x%08x\n",
14351 sc->link_params.lane_config,
14352 sc->link_params.speed_cap_mask[0],
14353 sc->port.link_config[0]);
14355 bxe_link_settings_supported(sc, sc->link_params.switch_cfg);
14356 bxe_link_settings_requested(sc);
14358 if (sc->autogreeen == AUTO_GREEN_FORCE_ON) {
14359 sc->link_params.feature_config_flags |=
14360 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14361 } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) {
14362 sc->link_params.feature_config_flags &=
14363 ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14364 } else if (config & PORT_FEAT_CFG_AUTOGREEEN_ENABLED) {
14365 sc->link_params.feature_config_flags |=
14366 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14369 /* configure link feature according to nvram value */
14371 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) &
14372 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
14373 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
14374 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
14375 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
14376 ELINK_EEE_MODE_ENABLE_LPI |
14377 ELINK_EEE_MODE_OUTPUT_TIME);
14379 sc->link_params.eee_mode = 0;
14382 /* get the media type */
14383 bxe_media_detect(sc);
14387 bxe_get_params(struct bxe_softc *sc)
14389 /* get user tunable params */
14390 bxe_get_tunable_params(sc);
14392 /* select the RX and TX ring sizes */
14393 sc->tx_ring_size = TX_BD_USABLE;
14394 sc->rx_ring_size = RX_BD_USABLE;
14396 /* XXX disable WoL */
14401 bxe_set_modes_bitmap(struct bxe_softc *sc)
14403 uint32_t flags = 0;
14405 if (CHIP_REV_IS_FPGA(sc)) {
14406 SET_FLAGS(flags, MODE_FPGA);
14407 } else if (CHIP_REV_IS_EMUL(sc)) {
14408 SET_FLAGS(flags, MODE_EMUL);
14410 SET_FLAGS(flags, MODE_ASIC);
14413 if (CHIP_IS_MODE_4_PORT(sc)) {
14414 SET_FLAGS(flags, MODE_PORT4);
14416 SET_FLAGS(flags, MODE_PORT2);
14419 if (CHIP_IS_E2(sc)) {
14420 SET_FLAGS(flags, MODE_E2);
14421 } else if (CHIP_IS_E3(sc)) {
14422 SET_FLAGS(flags, MODE_E3);
14423 if (CHIP_REV(sc) == CHIP_REV_Ax) {
14424 SET_FLAGS(flags, MODE_E3_A0);
14425 } else /*if (CHIP_REV(sc) == CHIP_REV_Bx)*/ {
14426 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
14431 SET_FLAGS(flags, MODE_MF);
14432 switch (sc->devinfo.mf_info.mf_mode) {
14433 case MULTI_FUNCTION_SD:
14434 SET_FLAGS(flags, MODE_MF_SD);
14436 case MULTI_FUNCTION_SI:
14437 SET_FLAGS(flags, MODE_MF_SI);
14439 case MULTI_FUNCTION_AFEX:
14440 SET_FLAGS(flags, MODE_MF_AFEX);
14444 SET_FLAGS(flags, MODE_SF);
14447 #if defined(__LITTLE_ENDIAN)
14448 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
14449 #else /* __BIG_ENDIAN */
14450 SET_FLAGS(flags, MODE_BIG_ENDIAN);
14453 INIT_MODE_FLAGS(sc) = flags;
14457 bxe_alloc_hsi_mem(struct bxe_softc *sc)
14459 struct bxe_fastpath *fp;
14460 bus_addr_t busaddr;
14461 int max_agg_queues;
14463 bus_size_t max_size;
14464 bus_size_t max_seg_size;
14469 /* XXX zero out all vars here and call bxe_alloc_hsi_mem on error */
14471 /* allocate the parent bus DMA tag */
14472 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */
14474 0, /* boundary limit */
14475 BUS_SPACE_MAXADDR, /* restricted low */
14476 BUS_SPACE_MAXADDR, /* restricted hi */
14477 NULL, /* addr filter() */
14478 NULL, /* addr filter() arg */
14479 BUS_SPACE_MAXSIZE_32BIT, /* max map size */
14480 BUS_SPACE_UNRESTRICTED, /* num discontinuous */
14481 BUS_SPACE_MAXSIZE_32BIT, /* max seg size */
14484 NULL, /* lock() arg */
14485 &sc->parent_dma_tag); /* returned dma tag */
14487 BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc);
14491 /************************/
14492 /* DEFAULT STATUS BLOCK */
14493 /************************/
14495 if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block),
14496 &sc->def_sb_dma, "default status block") != 0) {
14498 bus_dma_tag_destroy(sc->parent_dma_tag);
14502 sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
14508 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14509 &sc->eq_dma, "event queue") != 0) {
14511 bxe_dma_free(sc, &sc->def_sb_dma);
14513 bus_dma_tag_destroy(sc->parent_dma_tag);
14517 sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr;
14523 if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath),
14524 &sc->sp_dma, "slow path") != 0) {
14526 bxe_dma_free(sc, &sc->eq_dma);
14528 bxe_dma_free(sc, &sc->def_sb_dma);
14530 bus_dma_tag_destroy(sc->parent_dma_tag);
14534 sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr;
14536 /*******************/
14537 /* SLOW PATH QUEUE */
14538 /*******************/
14540 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14541 &sc->spq_dma, "slow path queue") != 0) {
14543 bxe_dma_free(sc, &sc->sp_dma);
14545 bxe_dma_free(sc, &sc->eq_dma);
14547 bxe_dma_free(sc, &sc->def_sb_dma);
14549 bus_dma_tag_destroy(sc->parent_dma_tag);
14553 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
14555 /***************************/
14556 /* FW DECOMPRESSION BUFFER */
14557 /***************************/
14559 if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
14560 "fw decompression buffer") != 0) {
14562 bxe_dma_free(sc, &sc->spq_dma);
14564 bxe_dma_free(sc, &sc->sp_dma);
14566 bxe_dma_free(sc, &sc->eq_dma);
14568 bxe_dma_free(sc, &sc->def_sb_dma);
14570 bus_dma_tag_destroy(sc->parent_dma_tag);
14574 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
14577 malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) {
14579 bxe_dma_free(sc, &sc->gz_buf_dma);
14581 bxe_dma_free(sc, &sc->spq_dma);
14583 bxe_dma_free(sc, &sc->sp_dma);
14585 bxe_dma_free(sc, &sc->eq_dma);
14587 bxe_dma_free(sc, &sc->def_sb_dma);
14589 bus_dma_tag_destroy(sc->parent_dma_tag);
14597 /* allocate DMA memory for each fastpath structure */
14598 for (i = 0; i < sc->num_queues; i++) {
14603 /*******************/
14604 /* FP STATUS BLOCK */
14605 /*******************/
14607 snprintf(buf, sizeof(buf), "fp %d status block", i);
14608 if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block),
14609 &fp->sb_dma, buf) != 0) {
14610 /* XXX unwind and free previous fastpath allocations */
14611 BLOGE(sc, "Failed to alloc %s\n", buf);
14614 if (CHIP_IS_E2E3(sc)) {
14615 fp->status_block.e2_sb =
14616 (struct host_hc_status_block_e2 *)fp->sb_dma.vaddr;
14618 fp->status_block.e1x_sb =
14619 (struct host_hc_status_block_e1x *)fp->sb_dma.vaddr;
14623 /******************/
14624 /* FP TX BD CHAIN */
14625 /******************/
14627 snprintf(buf, sizeof(buf), "fp %d tx bd chain", i);
14628 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES),
14629 &fp->tx_dma, buf) != 0) {
14630 /* XXX unwind and free previous fastpath allocations */
14631 BLOGE(sc, "Failed to alloc %s\n", buf);
14634 fp->tx_chain = (union eth_tx_bd_types *)fp->tx_dma.vaddr;
14637 /* link together the tx bd chain pages */
14638 for (j = 1; j <= TX_BD_NUM_PAGES; j++) {
14639 /* index into the tx bd chain array to last entry per page */
14640 struct eth_tx_next_bd *tx_next_bd =
14641 &fp->tx_chain[TX_BD_TOTAL_PER_PAGE * j - 1].next_bd;
14642 /* point to the next page and wrap from last page */
14643 busaddr = (fp->tx_dma.paddr +
14644 (BCM_PAGE_SIZE * (j % TX_BD_NUM_PAGES)));
14645 tx_next_bd->addr_hi = htole32(U64_HI(busaddr));
14646 tx_next_bd->addr_lo = htole32(U64_LO(busaddr));
14649 /******************/
14650 /* FP RX BD CHAIN */
14651 /******************/
14653 snprintf(buf, sizeof(buf), "fp %d rx bd chain", i);
14654 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES),
14655 &fp->rx_dma, buf) != 0) {
14656 /* XXX unwind and free previous fastpath allocations */
14657 BLOGE(sc, "Failed to alloc %s\n", buf);
14660 fp->rx_chain = (struct eth_rx_bd *)fp->rx_dma.vaddr;
14663 /* link together the rx bd chain pages */
14664 for (j = 1; j <= RX_BD_NUM_PAGES; j++) {
14665 /* index into the rx bd chain array to last entry per page */
14666 struct eth_rx_bd *rx_bd =
14667 &fp->rx_chain[RX_BD_TOTAL_PER_PAGE * j - 2];
14668 /* point to the next page and wrap from last page */
14669 busaddr = (fp->rx_dma.paddr +
14670 (BCM_PAGE_SIZE * (j % RX_BD_NUM_PAGES)));
14671 rx_bd->addr_hi = htole32(U64_HI(busaddr));
14672 rx_bd->addr_lo = htole32(U64_LO(busaddr));
14675 /*******************/
14676 /* FP RX RCQ CHAIN */
14677 /*******************/
14679 snprintf(buf, sizeof(buf), "fp %d rcq chain", i);
14680 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES),
14681 &fp->rcq_dma, buf) != 0) {
14682 /* XXX unwind and free previous fastpath allocations */
14683 BLOGE(sc, "Failed to alloc %s\n", buf);
14686 fp->rcq_chain = (union eth_rx_cqe *)fp->rcq_dma.vaddr;
14689 /* link together the rcq chain pages */
14690 for (j = 1; j <= RCQ_NUM_PAGES; j++) {
14691 /* index into the rcq chain array to last entry per page */
14692 struct eth_rx_cqe_next_page *rx_cqe_next =
14693 (struct eth_rx_cqe_next_page *)
14694 &fp->rcq_chain[RCQ_TOTAL_PER_PAGE * j - 1];
14695 /* point to the next page and wrap from last page */
14696 busaddr = (fp->rcq_dma.paddr +
14697 (BCM_PAGE_SIZE * (j % RCQ_NUM_PAGES)));
14698 rx_cqe_next->addr_hi = htole32(U64_HI(busaddr));
14699 rx_cqe_next->addr_lo = htole32(U64_LO(busaddr));
14702 /*******************/
14703 /* FP RX SGE CHAIN */
14704 /*******************/
14706 snprintf(buf, sizeof(buf), "fp %d sge chain", i);
14707 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES),
14708 &fp->rx_sge_dma, buf) != 0) {
14709 /* XXX unwind and free previous fastpath allocations */
14710 BLOGE(sc, "Failed to alloc %s\n", buf);
14713 fp->rx_sge_chain = (struct eth_rx_sge *)fp->rx_sge_dma.vaddr;
14716 /* link together the sge chain pages */
14717 for (j = 1; j <= RX_SGE_NUM_PAGES; j++) {
14718 /* index into the rcq chain array to last entry per page */
14719 struct eth_rx_sge *rx_sge =
14720 &fp->rx_sge_chain[RX_SGE_TOTAL_PER_PAGE * j - 2];
14721 /* point to the next page and wrap from last page */
14722 busaddr = (fp->rx_sge_dma.paddr +
14723 (BCM_PAGE_SIZE * (j % RX_SGE_NUM_PAGES)));
14724 rx_sge->addr_hi = htole32(U64_HI(busaddr));
14725 rx_sge->addr_lo = htole32(U64_LO(busaddr));
14728 /***********************/
14729 /* FP TX MBUF DMA MAPS */
14730 /***********************/
14732 /* set required sizes before mapping to conserve resources */
14733 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) {
14734 max_size = BXE_TSO_MAX_SIZE;
14735 max_segments = BXE_TSO_MAX_SEGMENTS;
14736 max_seg_size = BXE_TSO_MAX_SEG_SIZE;
14738 max_size = (MCLBYTES * BXE_MAX_SEGMENTS);
14739 max_segments = BXE_MAX_SEGMENTS;
14740 max_seg_size = MCLBYTES;
14743 /* create a dma tag for the tx mbufs */
14744 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14746 0, /* boundary limit */
14747 BUS_SPACE_MAXADDR, /* restricted low */
14748 BUS_SPACE_MAXADDR, /* restricted hi */
14749 NULL, /* addr filter() */
14750 NULL, /* addr filter() arg */
14751 max_size, /* max map size */
14752 max_segments, /* num discontinuous */
14753 max_seg_size, /* max seg size */
14756 NULL, /* lock() arg */
14757 &fp->tx_mbuf_tag); /* returned dma tag */
14759 /* XXX unwind and free previous fastpath allocations */
14760 BLOGE(sc, "Failed to create dma tag for "
14761 "'fp %d tx mbufs' (%d)\n", i, rc);
14765 /* create dma maps for each of the tx mbuf clusters */
14766 for (j = 0; j < TX_BD_TOTAL; j++) {
14767 if (bus_dmamap_create(fp->tx_mbuf_tag,
14769 &fp->tx_mbuf_chain[j].m_map)) {
14770 /* XXX unwind and free previous fastpath allocations */
14771 BLOGE(sc, "Failed to create dma map for "
14772 "'fp %d tx mbuf %d' (%d)\n", i, j, rc);
14777 /***********************/
14778 /* FP RX MBUF DMA MAPS */
14779 /***********************/
14781 /* create a dma tag for the rx mbufs */
14782 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14784 0, /* boundary limit */
14785 BUS_SPACE_MAXADDR, /* restricted low */
14786 BUS_SPACE_MAXADDR, /* restricted hi */
14787 NULL, /* addr filter() */
14788 NULL, /* addr filter() arg */
14789 MJUM9BYTES, /* max map size */
14790 1, /* num discontinuous */
14791 MJUM9BYTES, /* max seg size */
14794 NULL, /* lock() arg */
14795 &fp->rx_mbuf_tag); /* returned dma tag */
14797 /* XXX unwind and free previous fastpath allocations */
14798 BLOGE(sc, "Failed to create dma tag for "
14799 "'fp %d rx mbufs' (%d)\n", i, rc);
14803 /* create dma maps for each of the rx mbuf clusters */
14804 for (j = 0; j < RX_BD_TOTAL; j++) {
14805 if (bus_dmamap_create(fp->rx_mbuf_tag,
14807 &fp->rx_mbuf_chain[j].m_map)) {
14808 /* XXX unwind and free previous fastpath allocations */
14809 BLOGE(sc, "Failed to create dma map for "
14810 "'fp %d rx mbuf %d' (%d)\n", i, j, rc);
14815 /* create dma map for the spare rx mbuf cluster */
14816 if (bus_dmamap_create(fp->rx_mbuf_tag,
14818 &fp->rx_mbuf_spare_map)) {
14819 /* XXX unwind and free previous fastpath allocations */
14820 BLOGE(sc, "Failed to create dma map for "
14821 "'fp %d spare rx mbuf' (%d)\n", i, rc);
14825 /***************************/
14826 /* FP RX SGE MBUF DMA MAPS */
14827 /***************************/
14829 /* create a dma tag for the rx sge mbufs */
14830 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14832 0, /* boundary limit */
14833 BUS_SPACE_MAXADDR, /* restricted low */
14834 BUS_SPACE_MAXADDR, /* restricted hi */
14835 NULL, /* addr filter() */
14836 NULL, /* addr filter() arg */
14837 BCM_PAGE_SIZE, /* max map size */
14838 1, /* num discontinuous */
14839 BCM_PAGE_SIZE, /* max seg size */
14842 NULL, /* lock() arg */
14843 &fp->rx_sge_mbuf_tag); /* returned dma tag */
14845 /* XXX unwind and free previous fastpath allocations */
14846 BLOGE(sc, "Failed to create dma tag for "
14847 "'fp %d rx sge mbufs' (%d)\n", i, rc);
14851 /* create dma maps for the rx sge mbuf clusters */
14852 for (j = 0; j < RX_SGE_TOTAL; j++) {
14853 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
14855 &fp->rx_sge_mbuf_chain[j].m_map)) {
14856 /* XXX unwind and free previous fastpath allocations */
14857 BLOGE(sc, "Failed to create dma map for "
14858 "'fp %d rx sge mbuf %d' (%d)\n", i, j, rc);
14863 /* create dma map for the spare rx sge mbuf cluster */
14864 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
14866 &fp->rx_sge_mbuf_spare_map)) {
14867 /* XXX unwind and free previous fastpath allocations */
14868 BLOGE(sc, "Failed to create dma map for "
14869 "'fp %d spare rx sge mbuf' (%d)\n", i, rc);
14873 /***************************/
14874 /* FP RX TPA MBUF DMA MAPS */
14875 /***************************/
14877 /* create dma maps for the rx tpa mbuf clusters */
14878 max_agg_queues = MAX_AGG_QS(sc);
14880 for (j = 0; j < max_agg_queues; j++) {
14881 if (bus_dmamap_create(fp->rx_mbuf_tag,
14883 &fp->rx_tpa_info[j].bd.m_map)) {
14884 /* XXX unwind and free previous fastpath allocations */
14885 BLOGE(sc, "Failed to create dma map for "
14886 "'fp %d rx tpa mbuf %d' (%d)\n", i, j, rc);
14891 /* create dma map for the spare rx tpa mbuf cluster */
14892 if (bus_dmamap_create(fp->rx_mbuf_tag,
14894 &fp->rx_tpa_info_mbuf_spare_map)) {
14895 /* XXX unwind and free previous fastpath allocations */
14896 BLOGE(sc, "Failed to create dma map for "
14897 "'fp %d spare rx tpa mbuf' (%d)\n", i, rc);
14901 bxe_init_sge_ring_bit_mask(fp);
14908 bxe_free_hsi_mem(struct bxe_softc *sc)
14910 struct bxe_fastpath *fp;
14911 int max_agg_queues;
14914 if (sc->parent_dma_tag == NULL) {
14915 return; /* assume nothing was allocated */
14918 for (i = 0; i < sc->num_queues; i++) {
14921 /*******************/
14922 /* FP STATUS BLOCK */
14923 /*******************/
14925 bxe_dma_free(sc, &fp->sb_dma);
14926 memset(&fp->status_block, 0, sizeof(fp->status_block));
14928 /******************/
14929 /* FP TX BD CHAIN */
14930 /******************/
14932 bxe_dma_free(sc, &fp->tx_dma);
14933 fp->tx_chain = NULL;
14935 /******************/
14936 /* FP RX BD CHAIN */
14937 /******************/
14939 bxe_dma_free(sc, &fp->rx_dma);
14940 fp->rx_chain = NULL;
14942 /*******************/
14943 /* FP RX RCQ CHAIN */
14944 /*******************/
14946 bxe_dma_free(sc, &fp->rcq_dma);
14947 fp->rcq_chain = NULL;
14949 /*******************/
14950 /* FP RX SGE CHAIN */
14951 /*******************/
14953 bxe_dma_free(sc, &fp->rx_sge_dma);
14954 fp->rx_sge_chain = NULL;
14956 /***********************/
14957 /* FP TX MBUF DMA MAPS */
14958 /***********************/
14960 if (fp->tx_mbuf_tag != NULL) {
14961 for (j = 0; j < TX_BD_TOTAL; j++) {
14962 if (fp->tx_mbuf_chain[j].m_map != NULL) {
14963 bus_dmamap_unload(fp->tx_mbuf_tag,
14964 fp->tx_mbuf_chain[j].m_map);
14965 bus_dmamap_destroy(fp->tx_mbuf_tag,
14966 fp->tx_mbuf_chain[j].m_map);
14970 bus_dma_tag_destroy(fp->tx_mbuf_tag);
14971 fp->tx_mbuf_tag = NULL;
14974 /***********************/
14975 /* FP RX MBUF DMA MAPS */
14976 /***********************/
14978 if (fp->rx_mbuf_tag != NULL) {
14979 for (j = 0; j < RX_BD_TOTAL; j++) {
14980 if (fp->rx_mbuf_chain[j].m_map != NULL) {
14981 bus_dmamap_unload(fp->rx_mbuf_tag,
14982 fp->rx_mbuf_chain[j].m_map);
14983 bus_dmamap_destroy(fp->rx_mbuf_tag,
14984 fp->rx_mbuf_chain[j].m_map);
14988 if (fp->rx_mbuf_spare_map != NULL) {
14989 bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
14990 bus_dmamap_destroy(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
14993 /***************************/
14994 /* FP RX TPA MBUF DMA MAPS */
14995 /***************************/
14997 max_agg_queues = MAX_AGG_QS(sc);
14999 for (j = 0; j < max_agg_queues; j++) {
15000 if (fp->rx_tpa_info[j].bd.m_map != NULL) {
15001 bus_dmamap_unload(fp->rx_mbuf_tag,
15002 fp->rx_tpa_info[j].bd.m_map);
15003 bus_dmamap_destroy(fp->rx_mbuf_tag,
15004 fp->rx_tpa_info[j].bd.m_map);
15008 if (fp->rx_tpa_info_mbuf_spare_map != NULL) {
15009 bus_dmamap_unload(fp->rx_mbuf_tag,
15010 fp->rx_tpa_info_mbuf_spare_map);
15011 bus_dmamap_destroy(fp->rx_mbuf_tag,
15012 fp->rx_tpa_info_mbuf_spare_map);
15015 bus_dma_tag_destroy(fp->rx_mbuf_tag);
15016 fp->rx_mbuf_tag = NULL;
15019 /***************************/
15020 /* FP RX SGE MBUF DMA MAPS */
15021 /***************************/
15023 if (fp->rx_sge_mbuf_tag != NULL) {
15024 for (j = 0; j < RX_SGE_TOTAL; j++) {
15025 if (fp->rx_sge_mbuf_chain[j].m_map != NULL) {
15026 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
15027 fp->rx_sge_mbuf_chain[j].m_map);
15028 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
15029 fp->rx_sge_mbuf_chain[j].m_map);
15033 if (fp->rx_sge_mbuf_spare_map != NULL) {
15034 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
15035 fp->rx_sge_mbuf_spare_map);
15036 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
15037 fp->rx_sge_mbuf_spare_map);
15040 bus_dma_tag_destroy(fp->rx_sge_mbuf_tag);
15041 fp->rx_sge_mbuf_tag = NULL;
15045 /***************************/
15046 /* FW DECOMPRESSION BUFFER */
15047 /***************************/
15049 bxe_dma_free(sc, &sc->gz_buf_dma);
15051 free(sc->gz_strm, M_DEVBUF);
15052 sc->gz_strm = NULL;
15054 /*******************/
15055 /* SLOW PATH QUEUE */
15056 /*******************/
15058 bxe_dma_free(sc, &sc->spq_dma);
15065 bxe_dma_free(sc, &sc->sp_dma);
15072 bxe_dma_free(sc, &sc->eq_dma);
15075 /************************/
15076 /* DEFAULT STATUS BLOCK */
15077 /************************/
15079 bxe_dma_free(sc, &sc->def_sb_dma);
15082 bus_dma_tag_destroy(sc->parent_dma_tag);
15083 sc->parent_dma_tag = NULL;
15087 * Previous driver DMAE transaction may have occurred when pre-boot stage
15088 * ended and boot began. This would invalidate the addresses of the
15089 * transaction, resulting in was-error bit set in the PCI causing all
15090 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
15091 * the interrupt which detected this from the pglueb and the was-done bit
15094 bxe_prev_interrupted_dmae(struct bxe_softc *sc)
15098 if (!CHIP_IS_E1x(sc)) {
15099 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
15100 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
15101 BLOGD(sc, DBG_LOAD,
15102 "Clearing 'was-error' bit that was set in pglueb");
15103 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc));
15109 bxe_prev_mcp_done(struct bxe_softc *sc)
15111 uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
15112 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
15114 BLOGE(sc, "MCP response failure, aborting\n");
15121 static struct bxe_prev_list_node *
15122 bxe_prev_path_get_entry(struct bxe_softc *sc)
15124 struct bxe_prev_list_node *tmp;
15126 LIST_FOREACH(tmp, &bxe_prev_list, node) {
15127 if ((sc->pcie_bus == tmp->bus) &&
15128 (sc->pcie_device == tmp->slot) &&
15129 (SC_PATH(sc) == tmp->path)) {
15138 bxe_prev_is_path_marked(struct bxe_softc *sc)
15140 struct bxe_prev_list_node *tmp;
15143 mtx_lock(&bxe_prev_mtx);
15145 tmp = bxe_prev_path_get_entry(sc);
15148 BLOGD(sc, DBG_LOAD,
15149 "Path %d/%d/%d was marked by AER\n",
15150 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15153 BLOGD(sc, DBG_LOAD,
15154 "Path %d/%d/%d was already cleaned from previous drivers\n",
15155 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15159 mtx_unlock(&bxe_prev_mtx);
15165 bxe_prev_mark_path(struct bxe_softc *sc,
15166 uint8_t after_undi)
15168 struct bxe_prev_list_node *tmp;
15170 mtx_lock(&bxe_prev_mtx);
15172 /* Check whether the entry for this path already exists */
15173 tmp = bxe_prev_path_get_entry(sc);
15176 BLOGD(sc, DBG_LOAD,
15177 "Re-marking AER in path %d/%d/%d\n",
15178 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15180 BLOGD(sc, DBG_LOAD,
15181 "Removing AER indication from path %d/%d/%d\n",
15182 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15186 mtx_unlock(&bxe_prev_mtx);
15190 mtx_unlock(&bxe_prev_mtx);
15192 /* Create an entry for this path and add it */
15193 tmp = malloc(sizeof(struct bxe_prev_list_node), M_DEVBUF,
15194 (M_NOWAIT | M_ZERO));
15196 BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n");
15200 tmp->bus = sc->pcie_bus;
15201 tmp->slot = sc->pcie_device;
15202 tmp->path = SC_PATH(sc);
15204 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
15206 mtx_lock(&bxe_prev_mtx);
15208 BLOGD(sc, DBG_LOAD,
15209 "Marked path %d/%d/%d - finished previous unload\n",
15210 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15211 LIST_INSERT_HEAD(&bxe_prev_list, tmp, node);
15213 mtx_unlock(&bxe_prev_mtx);
15219 bxe_do_flr(struct bxe_softc *sc)
15223 /* only E2 and onwards support FLR */
15224 if (CHIP_IS_E1x(sc)) {
15225 BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n");
15229 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
15230 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
15231 BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n",
15232 sc->devinfo.bc_ver);
15236 /* Wait for Transaction Pending bit clean */
15237 for (i = 0; i < 4; i++) {
15239 DELAY(((1 << (i - 1)) * 100) * 1000);
15242 if (!bxe_is_pcie_pending(sc)) {
15247 BLOGE(sc, "PCIE transaction is not cleared, "
15248 "proceeding with reset anyway\n");
15252 BLOGD(sc, DBG_LOAD, "Initiating FLR\n");
15253 bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
15258 struct bxe_mac_vals {
15259 uint32_t xmac_addr;
15261 uint32_t emac_addr;
15263 uint32_t umac_addr;
15265 uint32_t bmac_addr;
15266 uint32_t bmac_val[2];
15270 bxe_prev_unload_close_mac(struct bxe_softc *sc,
15271 struct bxe_mac_vals *vals)
15273 uint32_t val, base_addr, offset, mask, reset_reg;
15274 uint8_t mac_stopped = FALSE;
15275 uint8_t port = SC_PORT(sc);
15276 uint32_t wb_data[2];
15278 /* reset addresses as they also mark which values were changed */
15279 vals->bmac_addr = 0;
15280 vals->umac_addr = 0;
15281 vals->xmac_addr = 0;
15282 vals->emac_addr = 0;
15284 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
15286 if (!CHIP_IS_E3(sc)) {
15287 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
15288 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
15289 if ((mask & reset_reg) && val) {
15290 BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n");
15291 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
15292 : NIG_REG_INGRESS_BMAC0_MEM;
15293 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
15294 : BIGMAC_REGISTER_BMAC_CONTROL;
15297 * use rd/wr since we cannot use dmae. This is safe
15298 * since MCP won't access the bus due to the request
15299 * to unload, and no function on the path can be
15300 * loaded at this time.
15302 wb_data[0] = REG_RD(sc, base_addr + offset);
15303 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
15304 vals->bmac_addr = base_addr + offset;
15305 vals->bmac_val[0] = wb_data[0];
15306 vals->bmac_val[1] = wb_data[1];
15307 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
15308 REG_WR(sc, vals->bmac_addr, wb_data[0]);
15309 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
15312 BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n");
15313 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4;
15314 vals->emac_val = REG_RD(sc, vals->emac_addr);
15315 REG_WR(sc, vals->emac_addr, 0);
15316 mac_stopped = TRUE;
15318 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
15319 BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n");
15320 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
15321 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
15322 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1));
15323 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1));
15324 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
15325 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
15326 REG_WR(sc, vals->xmac_addr, 0);
15327 mac_stopped = TRUE;
15330 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
15331 if (mask & reset_reg) {
15332 BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n");
15333 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
15334 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
15335 vals->umac_val = REG_RD(sc, vals->umac_addr);
15336 REG_WR(sc, vals->umac_addr, 0);
15337 mac_stopped = TRUE;
15346 #define BXE_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
15347 #define BXE_PREV_UNDI_RCQ(val) ((val) & 0xffff)
15348 #define BXE_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
15349 #define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
15352 bxe_prev_unload_undi_inc(struct bxe_softc *sc,
15357 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port));
15359 rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc;
15360 bd = BXE_PREV_UNDI_BD(tmp_reg) + inc;
15362 tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd);
15363 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg);
15365 BLOGD(sc, DBG_LOAD,
15366 "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
15371 bxe_prev_unload_common(struct bxe_softc *sc)
15373 uint32_t reset_reg, tmp_reg = 0, rc;
15374 uint8_t prev_undi = FALSE;
15375 struct bxe_mac_vals mac_vals;
15376 uint32_t timer_count = 1000;
15380 * It is possible a previous function received 'common' answer,
15381 * but hasn't loaded yet, therefore creating a scenario of
15382 * multiple functions receiving 'common' on the same path.
15384 BLOGD(sc, DBG_LOAD, "Common unload Flow\n");
15386 memset(&mac_vals, 0, sizeof(mac_vals));
15388 if (bxe_prev_is_path_marked(sc)) {
15389 return (bxe_prev_mcp_done(sc));
15392 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
15394 /* Reset should be performed after BRB is emptied */
15395 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
15396 /* Close the MAC Rx to prevent BRB from filling up */
15397 bxe_prev_unload_close_mac(sc, &mac_vals);
15399 /* close LLH filters towards the BRB */
15400 elink_set_rx_filter(&sc->link_params, 0);
15403 * Check if the UNDI driver was previously loaded.
15404 * UNDI driver initializes CID offset for normal bell to 0x7
15406 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
15407 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
15408 if (tmp_reg == 0x7) {
15409 BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n");
15411 /* clear the UNDI indication */
15412 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
15413 /* clear possible idle check errors */
15414 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
15418 /* wait until BRB is empty */
15419 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15420 while (timer_count) {
15421 prev_brb = tmp_reg;
15423 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15428 BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg);
15430 /* reset timer as long as BRB actually gets emptied */
15431 if (prev_brb > tmp_reg) {
15432 timer_count = 1000;
15437 /* If UNDI resides in memory, manually increment it */
15439 bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
15445 if (!timer_count) {
15446 BLOGE(sc, "Failed to empty BRB\n");
15450 /* No packets are in the pipeline, path is ready for reset */
15451 bxe_reset_common(sc);
15453 if (mac_vals.xmac_addr) {
15454 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
15456 if (mac_vals.umac_addr) {
15457 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
15459 if (mac_vals.emac_addr) {
15460 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
15462 if (mac_vals.bmac_addr) {
15463 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
15464 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
15467 rc = bxe_prev_mark_path(sc, prev_undi);
15469 bxe_prev_mcp_done(sc);
15473 return (bxe_prev_mcp_done(sc));
15477 bxe_prev_unload_uncommon(struct bxe_softc *sc)
15481 BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n");
15483 /* Test if previous unload process was already finished for this path */
15484 if (bxe_prev_is_path_marked(sc)) {
15485 return (bxe_prev_mcp_done(sc));
15488 BLOGD(sc, DBG_LOAD, "Path is unmarked\n");
15491 * If function has FLR capabilities, and existing FW version matches
15492 * the one required, then FLR will be sufficient to clean any residue
15493 * left by previous driver
15495 rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
15497 /* fw version is good */
15498 BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n");
15499 rc = bxe_do_flr(sc);
15503 /* FLR was performed */
15504 BLOGD(sc, DBG_LOAD, "FLR successful\n");
15508 BLOGD(sc, DBG_LOAD, "Could not FLR\n");
15510 /* Close the MCP request, return failure*/
15511 rc = bxe_prev_mcp_done(sc);
15513 rc = BXE_PREV_WAIT_NEEDED;
15520 bxe_prev_unload(struct bxe_softc *sc)
15522 int time_counter = 10;
15523 uint32_t fw, hw_lock_reg, hw_lock_val;
15527 * Clear HW from errors which may have resulted from an interrupted
15528 * DMAE transaction.
15530 bxe_prev_interrupted_dmae(sc);
15532 /* Release previously held locks */
15534 (SC_FUNC(sc) <= 5) ?
15535 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
15536 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
15538 hw_lock_val = (REG_RD(sc, hw_lock_reg));
15540 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
15541 BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n");
15542 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
15543 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
15545 BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n");
15546 REG_WR(sc, hw_lock_reg, 0xffffffff);
15548 BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n");
15551 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
15552 BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n");
15553 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
15557 /* Lock MCP using an unload request */
15558 fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
15560 BLOGE(sc, "MCP response failure, aborting\n");
15565 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
15566 rc = bxe_prev_unload_common(sc);
15570 /* non-common reply from MCP night require looping */
15571 rc = bxe_prev_unload_uncommon(sc);
15572 if (rc != BXE_PREV_WAIT_NEEDED) {
15577 } while (--time_counter);
15579 if (!time_counter || rc) {
15580 BLOGE(sc, "Failed to unload previous driver!"
15581 " time_counter %d rc %d\n", time_counter, rc);
15589 bxe_dcbx_set_state(struct bxe_softc *sc,
15591 uint32_t dcbx_enabled)
15593 if (!CHIP_IS_E1x(sc)) {
15594 sc->dcb_state = dcb_on;
15595 sc->dcbx_enabled = dcbx_enabled;
15597 sc->dcb_state = FALSE;
15598 sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID;
15600 BLOGD(sc, DBG_LOAD,
15601 "DCB state [%s:%s]\n",
15602 dcb_on ? "ON" : "OFF",
15603 (dcbx_enabled == BXE_DCBX_ENABLED_OFF) ? "user-mode" :
15604 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static" :
15605 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_ON) ?
15606 "on-chip with negotiation" : "invalid");
15609 /* must be called after sriov-enable */
15611 bxe_set_qm_cid_count(struct bxe_softc *sc)
15613 int cid_count = BXE_L2_MAX_CID(sc);
15615 if (IS_SRIOV(sc)) {
15616 cid_count += BXE_VF_CIDS;
15619 if (CNIC_SUPPORT(sc)) {
15620 cid_count += CNIC_CID_MAX;
15623 return (roundup(cid_count, QM_CID_ROUND));
15627 bxe_init_multi_cos(struct bxe_softc *sc)
15631 uint32_t pri_map = 0; /* XXX change to user config */
15633 for (pri = 0; pri < BXE_MAX_PRIORITY; pri++) {
15634 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
15635 if (cos < sc->max_cos) {
15636 sc->prio_to_cos[pri] = cos;
15638 BLOGW(sc, "Invalid COS %d for priority %d "
15639 "(max COS is %d), setting to 0\n",
15640 cos, pri, (sc->max_cos - 1));
15641 sc->prio_to_cos[pri] = 0;
15647 bxe_sysctl_state(SYSCTL_HANDLER_ARGS)
15649 struct bxe_softc *sc;
15653 error = sysctl_handle_int(oidp, &result, 0, req);
15655 if (error || !req->newptr) {
15661 sc = (struct bxe_softc *)arg1;
15663 BLOGI(sc, "... dumping driver state ...\n");
15664 temp = SHMEM2_RD(sc, temperature_in_half_celsius);
15665 BLOGI(sc, "\t Device Temperature = %d Celsius\n", (temp/2));
15672 bxe_sysctl_trigger_grcdump(SYSCTL_HANDLER_ARGS)
15674 struct bxe_softc *sc;
15678 error = sysctl_handle_int(oidp, &result, 0, req);
15680 if (error || !req->newptr) {
15685 sc = (struct bxe_softc *)arg1;
15687 BLOGI(sc, "... grcdump start ...\n");
15689 BLOGI(sc, "... grcdump done ...\n");
15696 bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS)
15698 struct bxe_softc *sc = (struct bxe_softc *)arg1;
15699 uint32_t *eth_stats = (uint32_t *)&sc->eth_stats;
15701 uint64_t value = 0;
15702 int index = (int)arg2;
15704 if (index >= BXE_NUM_ETH_STATS) {
15705 BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index);
15709 offset = (eth_stats + bxe_eth_stats_arr[index].offset);
15711 switch (bxe_eth_stats_arr[index].size) {
15713 value = (uint64_t)*offset;
15716 value = HILO_U64(*offset, *(offset + 1));
15719 BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n",
15720 index, bxe_eth_stats_arr[index].size);
15724 return (sysctl_handle_64(oidp, &value, 0, req));
15728 bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS)
15730 struct bxe_softc *sc = (struct bxe_softc *)arg1;
15731 uint32_t *eth_stats;
15733 uint64_t value = 0;
15734 uint32_t q_stat = (uint32_t)arg2;
15735 uint32_t fp_index = ((q_stat >> 16) & 0xffff);
15736 uint32_t index = (q_stat & 0xffff);
15738 eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats;
15740 if (index >= BXE_NUM_ETH_Q_STATS) {
15741 BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index);
15745 offset = (eth_stats + bxe_eth_q_stats_arr[index].offset);
15747 switch (bxe_eth_q_stats_arr[index].size) {
15749 value = (uint64_t)*offset;
15752 value = HILO_U64(*offset, *(offset + 1));
15755 BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n",
15756 index, bxe_eth_q_stats_arr[index].size);
15760 return (sysctl_handle_64(oidp, &value, 0, req));
15764 bxe_add_sysctls(struct bxe_softc *sc)
15766 struct sysctl_ctx_list *ctx;
15767 struct sysctl_oid_list *children;
15768 struct sysctl_oid *queue_top, *queue;
15769 struct sysctl_oid_list *queue_top_children, *queue_children;
15770 char queue_num_buf[32];
15774 ctx = device_get_sysctl_ctx(sc->dev);
15775 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
15777 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "version",
15778 CTLFLAG_RD, BXE_DRIVER_VERSION, 0,
15781 snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d",
15782 BCM_5710_FW_MAJOR_VERSION,
15783 BCM_5710_FW_MINOR_VERSION,
15784 BCM_5710_FW_REVISION_VERSION,
15785 BCM_5710_FW_ENGINEERING_VERSION);
15787 snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s",
15788 ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION) ? "Single" :
15789 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD) ? "MF-SD" :
15790 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI) ? "MF-SI" :
15791 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" :
15793 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "mf_vnics",
15794 CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0,
15795 "multifunction vnics per port");
15797 snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d",
15798 ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" :
15799 (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" :
15800 (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" :
15802 sc->devinfo.pcie_link_width);
15804 sc->debug = bxe_debug;
15806 #if __FreeBSD_version >= 900000
15807 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version",
15808 CTLFLAG_RD, sc->devinfo.bc_ver_str, 0,
15809 "bootcode version");
15810 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version",
15811 CTLFLAG_RD, sc->fw_ver_str, 0,
15812 "firmware version");
15813 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode",
15814 CTLFLAG_RD, sc->mf_mode_str, 0,
15815 "multifunction mode");
15816 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr",
15817 CTLFLAG_RD, sc->mac_addr_str, 0,
15819 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link",
15820 CTLFLAG_RD, &sc->pci_link_str, 0,
15821 "pci link status");
15822 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "debug",
15823 CTLFLAG_RW, &sc->debug, 0,
15824 "debug logging mode");
15826 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version",
15827 CTLFLAG_RD, &sc->devinfo.bc_ver_str, 0,
15828 "bootcode version");
15829 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version",
15830 CTLFLAG_RD, &sc->fw_ver_str, 0,
15831 "firmware version");
15832 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode",
15833 CTLFLAG_RD, &sc->mf_mode_str, 0,
15834 "multifunction mode");
15835 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr",
15836 CTLFLAG_RD, &sc->mac_addr_str, 0,
15838 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link",
15839 CTLFLAG_RD, &sc->pci_link_str, 0,
15840 "pci link status");
15841 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "debug",
15842 CTLFLAG_RW, &sc->debug, 0,
15843 "debug logging mode");
15844 #endif /* #if __FreeBSD_version >= 900000 */
15846 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "trigger_grcdump",
15847 CTLTYPE_UINT | CTLFLAG_RW, sc, 0,
15848 bxe_sysctl_trigger_grcdump, "IU",
15849 "set by driver when a grcdump is needed");
15851 sc->grcdump_done = 0;
15852 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "grcdump_done",
15853 CTLFLAG_RW, &sc->grcdump_done, 0,
15854 "set by driver when grcdump is done");
15856 sc->rx_budget = bxe_rx_budget;
15857 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_budget",
15858 CTLFLAG_RW, &sc->rx_budget, 0,
15859 "rx processing budget");
15861 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "state",
15862 CTLTYPE_UINT | CTLFLAG_RW, sc, 0,
15863 bxe_sysctl_state, "IU", "dump driver state");
15865 for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
15866 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
15867 bxe_eth_stats_arr[i].string,
15868 CTLTYPE_U64 | CTLFLAG_RD, sc, i,
15869 bxe_sysctl_eth_stat, "LU",
15870 bxe_eth_stats_arr[i].string);
15873 /* add a new parent node for all queues "dev.bxe.#.queue" */
15874 queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "queue",
15875 CTLFLAG_RD, NULL, "queue");
15876 queue_top_children = SYSCTL_CHILDREN(queue_top);
15878 for (i = 0; i < sc->num_queues; i++) {
15879 /* add a new parent node for a single queue "dev.bxe.#.queue.#" */
15880 snprintf(queue_num_buf, sizeof(queue_num_buf), "%d", i);
15881 queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO,
15882 queue_num_buf, CTLFLAG_RD, NULL,
15884 queue_children = SYSCTL_CHILDREN(queue);
15886 for (j = 0; j < BXE_NUM_ETH_Q_STATS; j++) {
15887 q_stat = ((i << 16) | j);
15888 SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO,
15889 bxe_eth_q_stats_arr[j].string,
15890 CTLTYPE_U64 | CTLFLAG_RD, sc, q_stat,
15891 bxe_sysctl_eth_q_stat, "LU",
15892 bxe_eth_q_stats_arr[j].string);
15898 bxe_alloc_buf_rings(struct bxe_softc *sc)
15900 #if __FreeBSD_version >= 800000
15903 struct bxe_fastpath *fp;
15905 for (i = 0; i < sc->num_queues; i++) {
15909 fp->tx_br = buf_ring_alloc(BXE_BR_SIZE, M_DEVBUF,
15910 M_NOWAIT, &fp->tx_mtx);
15911 if (fp->tx_br == NULL)
15919 bxe_free_buf_rings(struct bxe_softc *sc)
15921 #if __FreeBSD_version >= 800000
15924 struct bxe_fastpath *fp;
15926 for (i = 0; i < sc->num_queues; i++) {
15931 buf_ring_free(fp->tx_br, M_DEVBUF);
15940 bxe_init_fp_mutexs(struct bxe_softc *sc)
15943 struct bxe_fastpath *fp;
15945 for (i = 0; i < sc->num_queues; i++) {
15949 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name),
15950 "bxe%d_fp%d_tx_lock", sc->unit, i);
15951 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF);
15953 snprintf(fp->rx_mtx_name, sizeof(fp->rx_mtx_name),
15954 "bxe%d_fp%d_rx_lock", sc->unit, i);
15955 mtx_init(&fp->rx_mtx, fp->rx_mtx_name, NULL, MTX_DEF);
15960 bxe_destroy_fp_mutexs(struct bxe_softc *sc)
15963 struct bxe_fastpath *fp;
15965 for (i = 0; i < sc->num_queues; i++) {
15969 if (mtx_initialized(&fp->tx_mtx)) {
15970 mtx_destroy(&fp->tx_mtx);
15973 if (mtx_initialized(&fp->rx_mtx)) {
15974 mtx_destroy(&fp->rx_mtx);
15981 * Device attach function.
15983 * Allocates device resources, performs secondary chip identification, and
15984 * initializes driver instance variables. This function is called from driver
15985 * load after a successful probe.
15988 * 0 = Success, >0 = Failure
15991 bxe_attach(device_t dev)
15993 struct bxe_softc *sc;
15995 sc = device_get_softc(dev);
15997 BLOGD(sc, DBG_LOAD, "Starting attach...\n");
15999 sc->state = BXE_STATE_CLOSED;
16002 sc->unit = device_get_unit(dev);
16004 BLOGD(sc, DBG_LOAD, "softc = %p\n", sc);
16006 sc->pcie_bus = pci_get_bus(dev);
16007 sc->pcie_device = pci_get_slot(dev);
16008 sc->pcie_func = pci_get_function(dev);
16010 /* enable bus master capability */
16011 pci_enable_busmaster(dev);
16014 if (bxe_allocate_bars(sc) != 0) {
16018 /* initialize the mutexes */
16019 bxe_init_mutexes(sc);
16021 /* prepare the periodic callout */
16022 callout_init(&sc->periodic_callout, 0);
16024 /* prepare the chip taskqueue */
16025 sc->chip_tq_flags = CHIP_TQ_NONE;
16026 snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name),
16027 "bxe%d_chip_tq", sc->unit);
16028 TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc);
16029 sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT,
16030 taskqueue_thread_enqueue,
16032 taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */
16033 "%s", sc->chip_tq_name);
16035 /* get device info and set params */
16036 if (bxe_get_device_info(sc) != 0) {
16037 BLOGE(sc, "getting device info\n");
16038 bxe_deallocate_bars(sc);
16039 pci_disable_busmaster(dev);
16043 /* get final misc params */
16044 bxe_get_params(sc);
16046 /* set the default MTU (changed via ifconfig) */
16047 sc->mtu = ETHERMTU;
16049 bxe_set_modes_bitmap(sc);
16052 * If in AFEX mode and the function is configured for FCoE
16053 * then bail... no L2 allowed.
16056 /* get phy settings from shmem and 'and' against admin settings */
16057 bxe_get_phy_info(sc);
16059 /* initialize the FreeBSD ifnet interface */
16060 if (bxe_init_ifnet(sc) != 0) {
16061 bxe_release_mutexes(sc);
16062 bxe_deallocate_bars(sc);
16063 pci_disable_busmaster(dev);
16067 if (bxe_add_cdev(sc) != 0) {
16068 if (sc->ifnet != NULL) {
16069 ether_ifdetach(sc->ifnet);
16071 ifmedia_removeall(&sc->ifmedia);
16072 bxe_release_mutexes(sc);
16073 bxe_deallocate_bars(sc);
16074 pci_disable_busmaster(dev);
16078 /* allocate device interrupts */
16079 if (bxe_interrupt_alloc(sc) != 0) {
16081 if (sc->ifnet != NULL) {
16082 ether_ifdetach(sc->ifnet);
16084 ifmedia_removeall(&sc->ifmedia);
16085 bxe_release_mutexes(sc);
16086 bxe_deallocate_bars(sc);
16087 pci_disable_busmaster(dev);
16091 bxe_init_fp_mutexs(sc);
16093 if (bxe_alloc_buf_rings(sc) != 0) {
16094 bxe_free_buf_rings(sc);
16095 bxe_interrupt_free(sc);
16097 if (sc->ifnet != NULL) {
16098 ether_ifdetach(sc->ifnet);
16100 ifmedia_removeall(&sc->ifmedia);
16101 bxe_release_mutexes(sc);
16102 bxe_deallocate_bars(sc);
16103 pci_disable_busmaster(dev);
16108 if (bxe_alloc_ilt_mem(sc) != 0) {
16109 bxe_free_buf_rings(sc);
16110 bxe_interrupt_free(sc);
16112 if (sc->ifnet != NULL) {
16113 ether_ifdetach(sc->ifnet);
16115 ifmedia_removeall(&sc->ifmedia);
16116 bxe_release_mutexes(sc);
16117 bxe_deallocate_bars(sc);
16118 pci_disable_busmaster(dev);
16122 /* allocate the host hardware/software hsi structures */
16123 if (bxe_alloc_hsi_mem(sc) != 0) {
16124 bxe_free_ilt_mem(sc);
16125 bxe_free_buf_rings(sc);
16126 bxe_interrupt_free(sc);
16128 if (sc->ifnet != NULL) {
16129 ether_ifdetach(sc->ifnet);
16131 ifmedia_removeall(&sc->ifmedia);
16132 bxe_release_mutexes(sc);
16133 bxe_deallocate_bars(sc);
16134 pci_disable_busmaster(dev);
16138 /* need to reset chip if UNDI was active */
16139 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
16142 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
16143 DRV_MSG_SEQ_NUMBER_MASK);
16144 BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq);
16145 bxe_prev_unload(sc);
16150 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16152 if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) &&
16153 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) &&
16154 SHMEM2_RD(sc, dcbx_lldp_params_offset) &&
16155 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) {
16156 bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON);
16157 bxe_dcbx_init_params(sc);
16159 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16163 /* calculate qm_cid_count */
16164 sc->qm_cid_count = bxe_set_qm_cid_count(sc);
16165 BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count);
16168 bxe_init_multi_cos(sc);
16170 bxe_add_sysctls(sc);
16176 * Device detach function.
16178 * Stops the controller, resets the controller, and releases resources.
16181 * 0 = Success, >0 = Failure
16184 bxe_detach(device_t dev)
16186 struct bxe_softc *sc;
16189 sc = device_get_softc(dev);
16191 BLOGD(sc, DBG_LOAD, "Starting detach...\n");
16194 if (ifp != NULL && ifp->if_vlantrunk != NULL) {
16195 BLOGE(sc, "Cannot detach while VLANs are in use.\n");
16201 /* stop the periodic callout */
16202 bxe_periodic_stop(sc);
16204 /* stop the chip taskqueue */
16205 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE);
16207 taskqueue_drain(sc->chip_tq, &sc->chip_tq_task);
16208 taskqueue_free(sc->chip_tq);
16209 sc->chip_tq = NULL;
16212 /* stop and reset the controller if it was open */
16213 if (sc->state != BXE_STATE_CLOSED) {
16215 bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE);
16216 sc->state = BXE_STATE_DISABLED;
16217 BXE_CORE_UNLOCK(sc);
16220 /* release the network interface */
16222 ether_ifdetach(ifp);
16224 ifmedia_removeall(&sc->ifmedia);
16226 /* XXX do the following based on driver state... */
16228 /* free the host hardware/software hsi structures */
16229 bxe_free_hsi_mem(sc);
16232 bxe_free_ilt_mem(sc);
16234 bxe_free_buf_rings(sc);
16236 /* release the interrupts */
16237 bxe_interrupt_free(sc);
16239 /* Release the mutexes*/
16240 bxe_destroy_fp_mutexs(sc);
16241 bxe_release_mutexes(sc);
16244 /* Release the PCIe BAR mapped memory */
16245 bxe_deallocate_bars(sc);
16247 /* Release the FreeBSD interface. */
16248 if (sc->ifnet != NULL) {
16249 if_free(sc->ifnet);
16252 pci_disable_busmaster(dev);
16258 * Device shutdown function.
16260 * Stops and resets the controller.
16266 bxe_shutdown(device_t dev)
16268 struct bxe_softc *sc;
16270 sc = device_get_softc(dev);
16272 BLOGD(sc, DBG_LOAD, "Starting shutdown...\n");
16274 /* stop the periodic callout */
16275 bxe_periodic_stop(sc);
16278 bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE);
16279 BXE_CORE_UNLOCK(sc);
16285 bxe_igu_ack_sb(struct bxe_softc *sc,
16292 uint32_t igu_addr = sc->igu_base_addr;
16293 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
16294 bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr);
16298 bxe_igu_clear_sb_gen(struct bxe_softc *sc,
16303 uint32_t data, ctl, cnt = 100;
16304 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
16305 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
16306 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
16307 uint32_t sb_bit = 1 << (idu_sb_id%32);
16308 uint32_t func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
16309 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
16311 /* Not supported in BC mode */
16312 if (CHIP_INT_MODE_IS_BC(sc)) {
16316 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
16317 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
16318 IGU_REGULAR_CLEANUP_SET |
16319 IGU_REGULAR_BCLEANUP);
16321 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
16322 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
16323 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
16325 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16326 data, igu_addr_data);
16327 REG_WR(sc, igu_addr_data, data);
16329 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16330 BUS_SPACE_BARRIER_WRITE);
16333 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16334 ctl, igu_addr_ctl);
16335 REG_WR(sc, igu_addr_ctl, ctl);
16337 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16338 BUS_SPACE_BARRIER_WRITE);
16341 /* wait for clean up to finish */
16342 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
16346 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
16347 BLOGD(sc, DBG_LOAD,
16348 "Unable to finish IGU cleanup: "
16349 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
16350 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
16355 bxe_igu_clear_sb(struct bxe_softc *sc,
16358 bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
16367 /*******************/
16368 /* ECORE CALLBACKS */
16369 /*******************/
16372 bxe_reset_common(struct bxe_softc *sc)
16374 uint32_t val = 0x1400;
16377 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f);
16379 if (CHIP_IS_E3(sc)) {
16380 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
16381 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
16384 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
16388 bxe_common_init_phy(struct bxe_softc *sc)
16390 uint32_t shmem_base[2];
16391 uint32_t shmem2_base[2];
16393 /* Avoid common init in case MFW supports LFA */
16394 if (SHMEM2_RD(sc, size) >
16395 (uint32_t)offsetof(struct shmem2_region,
16396 lfa_host_addr[SC_PORT(sc)])) {
16400 shmem_base[0] = sc->devinfo.shmem_base;
16401 shmem2_base[0] = sc->devinfo.shmem2_base;
16403 if (!CHIP_IS_E1x(sc)) {
16404 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
16405 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
16408 bxe_acquire_phy_lock(sc);
16409 elink_common_init_phy(sc, shmem_base, shmem2_base,
16410 sc->devinfo.chip_id, 0);
16411 bxe_release_phy_lock(sc);
16415 bxe_pf_disable(struct bxe_softc *sc)
16417 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
16419 val &= ~IGU_PF_CONF_FUNC_EN;
16421 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
16422 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
16423 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
16427 bxe_init_pxp(struct bxe_softc *sc)
16430 int r_order, w_order;
16432 devctl = bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL, 2);
16434 BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl);
16436 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
16438 if (sc->mrrs == -1) {
16439 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
16441 BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs);
16442 r_order = sc->mrrs;
16445 ecore_init_pxp_arb(sc, r_order, w_order);
16449 bxe_get_pretend_reg(struct bxe_softc *sc)
16451 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
16452 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
16453 return (base + (SC_ABS_FUNC(sc)) * stride);
16457 * Called only on E1H or E2.
16458 * When pretending to be PF, the pretend value is the function number 0..7.
16459 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
16463 bxe_pretend_func(struct bxe_softc *sc,
16464 uint16_t pretend_func_val)
16466 uint32_t pretend_reg;
16468 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) {
16472 /* get my own pretend register */
16473 pretend_reg = bxe_get_pretend_reg(sc);
16474 REG_WR(sc, pretend_reg, pretend_func_val);
16475 REG_RD(sc, pretend_reg);
16480 bxe_iov_init_dmae(struct bxe_softc *sc)
16486 bxe_iov_init_dq(struct bxe_softc *sc)
16491 /* send a NIG loopback debug packet */
16493 bxe_lb_pckt(struct bxe_softc *sc)
16495 uint32_t wb_write[3];
16497 /* Ethernet source and destination addresses */
16498 wb_write[0] = 0x55555555;
16499 wb_write[1] = 0x55555555;
16500 wb_write[2] = 0x20; /* SOP */
16501 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16503 /* NON-IP protocol */
16504 wb_write[0] = 0x09000000;
16505 wb_write[1] = 0x55555555;
16506 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
16507 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16511 * Some of the internal memories are not directly readable from the driver.
16512 * To test them we send debug packets.
16515 bxe_int_mem_test(struct bxe_softc *sc)
16521 if (CHIP_REV_IS_FPGA(sc)) {
16523 } else if (CHIP_REV_IS_EMUL(sc)) {
16529 /* disable inputs of parser neighbor blocks */
16530 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16531 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16532 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16533 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16535 /* write 0 to parser credits for CFC search request */
16536 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16538 /* send Ethernet packet */
16541 /* TODO do i reset NIG statistic? */
16542 /* Wait until NIG register shows 1 packet of size 0x10 */
16543 count = 1000 * factor;
16545 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16546 val = *BXE_SP(sc, wb_data[0]);
16556 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16560 /* wait until PRS register shows 1 packet */
16561 count = (1000 * factor);
16563 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16573 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16577 /* Reset and init BRB, PRS */
16578 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16580 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16582 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16583 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16585 /* Disable inputs of parser neighbor blocks */
16586 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16587 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16588 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16589 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16591 /* Write 0 to parser credits for CFC search request */
16592 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16594 /* send 10 Ethernet packets */
16595 for (i = 0; i < 10; i++) {
16599 /* Wait until NIG register shows 10+1 packets of size 11*0x10 = 0xb0 */
16600 count = (1000 * factor);
16602 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16603 val = *BXE_SP(sc, wb_data[0]);
16613 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16617 /* Wait until PRS register shows 2 packets */
16618 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16620 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16623 /* Write 1 to parser credits for CFC search request */
16624 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
16626 /* Wait until PRS register shows 3 packets */
16627 DELAY(10000 * factor);
16629 /* Wait until NIG register shows 1 packet of size 0x10 */
16630 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16632 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16635 /* clear NIG EOP FIFO */
16636 for (i = 0; i < 11; i++) {
16637 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);
16640 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);
16642 BLOGE(sc, "clear of NIG failed val=0x%x\n", val);
16646 /* Reset and init BRB, PRS, NIG */
16647 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16649 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16651 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16652 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16653 if (!CNIC_SUPPORT(sc)) {
16655 REG_WR(sc, PRS_REG_NIC_MODE, 1);
16658 /* Enable inputs of parser neighbor blocks */
16659 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff);
16660 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1);
16661 REG_WR(sc, CFC_REG_DEBUG0, 0x0);
16662 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1);
16668 bxe_setup_fan_failure_detection(struct bxe_softc *sc)
16675 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
16676 SHARED_HW_CFG_FAN_FAILURE_MASK);
16678 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
16682 * The fan failure mechanism is usually related to the PHY type since
16683 * the power consumption of the board is affected by the PHY. Currently,
16684 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
16686 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
16687 for (port = PORT_0; port < PORT_MAX; port++) {
16688 is_required |= elink_fan_failure_det_req(sc,
16689 sc->devinfo.shmem_base,
16690 sc->devinfo.shmem2_base,
16695 BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required);
16697 if (is_required == 0) {
16701 /* Fan failure is indicated by SPIO 5 */
16702 bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
16704 /* set to active low mode */
16705 val = REG_RD(sc, MISC_REG_SPIO_INT);
16706 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
16707 REG_WR(sc, MISC_REG_SPIO_INT, val);
16709 /* enable interrupt to signal the IGU */
16710 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
16711 val |= MISC_SPIO_SPIO5;
16712 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
16716 bxe_enable_blocks_attention(struct bxe_softc *sc)
16720 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
16721 if (!CHIP_IS_E1x(sc)) {
16722 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
16724 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
16726 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
16727 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
16729 * mask read length error interrupts in brb for parser
16730 * (parsing unit and 'checksum and crc' unit)
16731 * these errors are legal (PU reads fixed length and CAC can cause
16732 * read length error on truncated packets)
16734 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
16735 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
16736 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
16737 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
16738 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
16739 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
16740 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
16741 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
16742 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
16743 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
16744 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
16745 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
16746 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
16747 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
16748 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
16749 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
16750 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
16751 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
16752 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
16754 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
16755 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
16756 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
16757 if (!CHIP_IS_E1x(sc)) {
16758 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
16759 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
16761 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
16763 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
16764 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
16765 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
16766 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
16768 if (!CHIP_IS_E1x(sc)) {
16769 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
16770 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
16773 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
16774 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
16775 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
16776 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
16780 * bxe_init_hw_common - initialize the HW at the COMMON phase.
16782 * @sc: driver handle
16785 bxe_init_hw_common(struct bxe_softc *sc)
16787 uint8_t abs_func_id;
16790 BLOGD(sc, DBG_LOAD, "starting common init for func %d\n",
16794 * take the RESET lock to protect undi_unload flow from accessing
16795 * registers while we are resetting the chip
16797 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
16799 bxe_reset_common(sc);
16801 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
16804 if (CHIP_IS_E3(sc)) {
16805 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
16806 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
16809 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
16811 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
16813 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
16814 BLOGD(sc, DBG_LOAD, "after misc block init\n");
16816 if (!CHIP_IS_E1x(sc)) {
16818 * 4-port mode or 2-port mode we need to turn off master-enable for
16819 * everyone. After that we turn it back on for self. So, we disregard
16820 * multi-function, and always disable all functions on the given path,
16821 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
16823 for (abs_func_id = SC_PATH(sc);
16824 abs_func_id < (E2_FUNC_MAX * 2);
16825 abs_func_id += 2) {
16826 if (abs_func_id == SC_ABS_FUNC(sc)) {
16827 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
16831 bxe_pretend_func(sc, abs_func_id);
16833 /* clear pf enable */
16834 bxe_pf_disable(sc);
16836 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
16840 BLOGD(sc, DBG_LOAD, "after pf disable\n");
16842 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
16844 if (CHIP_IS_E1(sc)) {
16846 * enable HW interrupt from PXP on USDM overflow
16847 * bit 16 on INT_MASK_0
16849 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
16852 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
16855 #ifdef __BIG_ENDIAN
16856 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
16857 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
16858 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
16859 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
16860 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
16861 /* make sure this value is 0 */
16862 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
16864 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
16865 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
16866 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
16867 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
16868 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
16871 ecore_ilt_init_page_size(sc, INITOP_SET);
16873 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
16874 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
16877 /* let the HW do it's magic... */
16880 /* finish PXP init */
16881 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
16883 BLOGE(sc, "PXP2 CFG failed PXP2_REG_RQ_CFG_DONE val = 0x%x\n",
16887 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
16889 BLOGE(sc, "PXP2 RD_INIT failed val = 0x%x\n", val);
16893 BLOGD(sc, DBG_LOAD, "after pxp init\n");
16896 * Timer bug workaround for E2 only. We need to set the entire ILT to have
16897 * entries with value "0" and valid bit on. This needs to be done by the
16898 * first PF that is loaded in a path (i.e. common phase)
16900 if (!CHIP_IS_E1x(sc)) {
16902 * In E2 there is a bug in the timers block that can cause function 6 / 7
16903 * (i.e. vnic3) to start even if it is marked as "scan-off".
16904 * This occurs when a different function (func2,3) is being marked
16905 * as "scan-off". Real-life scenario for example: if a driver is being
16906 * load-unloaded while func6,7 are down. This will cause the timer to access
16907 * the ilt, translate to a logical address and send a request to read/write.
16908 * Since the ilt for the function that is down is not valid, this will cause
16909 * a translation error which is unrecoverable.
16910 * The Workaround is intended to make sure that when this happens nothing
16911 * fatal will occur. The workaround:
16912 * 1. First PF driver which loads on a path will:
16913 * a. After taking the chip out of reset, by using pretend,
16914 * it will write "0" to the following registers of
16916 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
16917 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
16918 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
16919 * And for itself it will write '1' to
16920 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
16921 * dmae-operations (writing to pram for example.)
16922 * note: can be done for only function 6,7 but cleaner this
16924 * b. Write zero+valid to the entire ILT.
16925 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
16926 * VNIC3 (of that port). The range allocated will be the
16927 * entire ILT. This is needed to prevent ILT range error.
16928 * 2. Any PF driver load flow:
16929 * a. ILT update with the physical addresses of the allocated
16931 * b. Wait 20msec. - note that this timeout is needed to make
16932 * sure there are no requests in one of the PXP internal
16933 * queues with "old" ILT addresses.
16934 * c. PF enable in the PGLC.
16935 * d. Clear the was_error of the PF in the PGLC. (could have
16936 * occurred while driver was down)
16937 * e. PF enable in the CFC (WEAK + STRONG)
16938 * f. Timers scan enable
16939 * 3. PF driver unload flow:
16940 * a. Clear the Timers scan_en.
16941 * b. Polling for scan_on=0 for that PF.
16942 * c. Clear the PF enable bit in the PXP.
16943 * d. Clear the PF enable in the CFC (WEAK + STRONG)
16944 * e. Write zero+valid to all ILT entries (The valid bit must
16946 * f. If this is VNIC 3 of a port then also init
16947 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16948 * to the last enrty in the ILT.
16951 * Currently the PF error in the PGLC is non recoverable.
16952 * In the future the there will be a recovery routine for this error.
16953 * Currently attention is masked.
16954 * Having an MCP lock on the load/unload process does not guarantee that
16955 * there is no Timer disable during Func6/7 enable. This is because the
16956 * Timers scan is currently being cleared by the MCP on FLR.
16957 * Step 2.d can be done only for PF6/7 and the driver can also check if
16958 * there is error before clearing it. But the flow above is simpler and
16960 * All ILT entries are written by zero+valid and not just PF6/7
16961 * ILT entries since in the future the ILT entries allocation for
16962 * PF-s might be dynamic.
16964 struct ilt_client_info ilt_cli;
16965 struct ecore_ilt ilt;
16967 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
16968 memset(&ilt, 0, sizeof(struct ecore_ilt));
16970 /* initialize dummy TM client */
16972 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
16973 ilt_cli.client_num = ILT_CLIENT_TM;
16976 * Step 1: set zeroes to all ilt page entries with valid bit on
16977 * Step 2: set the timers first/last ilt entry to point
16978 * to the entire range to prevent ILT range error for 3rd/4th
16979 * vnic (this code assumes existence of the vnic)
16981 * both steps performed by call to ecore_ilt_client_init_op()
16982 * with dummy TM client
16984 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
16985 * and his brother are split registers
16988 bxe_pretend_func(sc, (SC_PATH(sc) + 6));
16989 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
16990 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
16992 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN);
16993 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN);
16994 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
16997 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
16998 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
17000 if (!CHIP_IS_E1x(sc)) {
17001 int factor = CHIP_REV_IS_EMUL(sc) ? 1000 :
17002 (CHIP_REV_IS_FPGA(sc) ? 400 : 0);
17004 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
17005 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
17007 /* let the HW do it's magic... */
17010 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
17011 } while (factor-- && (val != 1));
17014 BLOGE(sc, "ATC_INIT failed val = 0x%x\n", val);
17019 BLOGD(sc, DBG_LOAD, "after pglue and atc init\n");
17021 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
17023 bxe_iov_init_dmae(sc);
17025 /* clean the DMAE memory */
17026 sc->dmae_ready = 1;
17027 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
17029 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
17031 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
17033 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
17035 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
17037 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
17038 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
17039 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
17040 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
17042 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
17044 /* QM queues pointers table */
17045 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
17047 /* soft reset pulse */
17048 REG_WR(sc, QM_REG_SOFT_RESET, 1);
17049 REG_WR(sc, QM_REG_SOFT_RESET, 0);
17051 if (CNIC_SUPPORT(sc))
17052 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
17054 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
17055 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT);
17056 if (!CHIP_REV_IS_SLOW(sc)) {
17057 /* enable hw interrupt from doorbell Q */
17058 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
17061 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
17063 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
17064 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
17066 if (!CHIP_IS_E1(sc)) {
17067 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
17070 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
17071 if (IS_MF_AFEX(sc)) {
17073 * configure that AFEX and VLAN headers must be
17074 * received in AFEX mode
17076 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
17077 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
17078 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
17079 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
17080 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
17083 * Bit-map indicating which L2 hdrs may appear
17084 * after the basic Ethernet header
17086 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
17087 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17091 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
17092 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
17093 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
17094 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
17096 if (!CHIP_IS_E1x(sc)) {
17097 /* reset VFC memories */
17098 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17099 VFC_MEMORIES_RST_REG_CAM_RST |
17100 VFC_MEMORIES_RST_REG_RAM_RST);
17101 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17102 VFC_MEMORIES_RST_REG_CAM_RST |
17103 VFC_MEMORIES_RST_REG_RAM_RST);
17108 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
17109 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
17110 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
17111 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
17113 /* sync semi rtc */
17114 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
17116 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
17119 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
17120 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
17121 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
17123 if (!CHIP_IS_E1x(sc)) {
17124 if (IS_MF_AFEX(sc)) {
17126 * configure that AFEX and VLAN headers must be
17127 * sent in AFEX mode
17129 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
17130 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
17131 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
17132 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
17133 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
17135 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
17136 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17140 REG_WR(sc, SRC_REG_SOFT_RST, 1);
17142 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
17144 if (CNIC_SUPPORT(sc)) {
17145 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
17146 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
17147 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
17148 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
17149 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
17150 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
17151 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
17152 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
17153 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
17154 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
17156 REG_WR(sc, SRC_REG_SOFT_RST, 0);
17158 if (sizeof(union cdu_context) != 1024) {
17159 /* we currently assume that a context is 1024 bytes */
17160 BLOGE(sc, "please adjust the size of cdu_context(%ld)\n",
17161 (long)sizeof(union cdu_context));
17164 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
17165 val = (4 << 24) + (0 << 12) + 1024;
17166 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
17168 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
17170 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
17171 /* enable context validation interrupt from CFC */
17172 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
17174 /* set the thresholds to prevent CFC/CDU race */
17175 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
17176 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
17178 if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) {
17179 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
17182 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
17183 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
17185 /* Reset PCIE errors for debug */
17186 REG_WR(sc, 0x2814, 0xffffffff);
17187 REG_WR(sc, 0x3820, 0xffffffff);
17189 if (!CHIP_IS_E1x(sc)) {
17190 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
17191 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
17192 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
17193 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
17194 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
17195 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
17196 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
17197 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
17198 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
17199 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
17200 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
17203 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
17205 if (!CHIP_IS_E1(sc)) {
17206 /* in E3 this done in per-port section */
17207 if (!CHIP_IS_E3(sc))
17208 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
17211 if (CHIP_IS_E1H(sc)) {
17212 /* not applicable for E2 (and above ...) */
17213 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
17216 if (CHIP_REV_IS_SLOW(sc)) {
17220 /* finish CFC init */
17221 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
17223 BLOGE(sc, "CFC LL_INIT failed val=0x%x\n", val);
17226 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
17228 BLOGE(sc, "CFC AC_INIT failed val=0x%x\n", val);
17231 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
17233 BLOGE(sc, "CFC CAM_INIT failed val=0x%x\n", val);
17236 REG_WR(sc, CFC_REG_DEBUG0, 0);
17238 if (CHIP_IS_E1(sc)) {
17239 /* read NIG statistic to see if this is our first up since powerup */
17240 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
17241 val = *BXE_SP(sc, wb_data[0]);
17243 /* do internal memory self test */
17244 if ((val == 0) && bxe_int_mem_test(sc)) {
17245 BLOGE(sc, "internal mem self test failed val=0x%x\n", val);
17250 bxe_setup_fan_failure_detection(sc);
17252 /* clear PXP2 attentions */
17253 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
17255 bxe_enable_blocks_attention(sc);
17257 if (!CHIP_REV_IS_SLOW(sc)) {
17258 ecore_enable_blocks_parity(sc);
17261 if (!BXE_NOMCP(sc)) {
17262 if (CHIP_IS_E1x(sc)) {
17263 bxe_common_init_phy(sc);
17271 * bxe_init_hw_common_chip - init HW at the COMMON_CHIP phase.
17273 * @sc: driver handle
17276 bxe_init_hw_common_chip(struct bxe_softc *sc)
17278 int rc = bxe_init_hw_common(sc);
17281 BLOGE(sc, "bxe_init_hw_common failed rc=%d\n", rc);
17285 /* In E2 2-PORT mode, same ext phy is used for the two paths */
17286 if (!BXE_NOMCP(sc)) {
17287 bxe_common_init_phy(sc);
17294 bxe_init_hw_port(struct bxe_softc *sc)
17296 int port = SC_PORT(sc);
17297 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
17298 uint32_t low, high;
17301 BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port);
17303 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
17305 ecore_init_block(sc, BLOCK_MISC, init_phase);
17306 ecore_init_block(sc, BLOCK_PXP, init_phase);
17307 ecore_init_block(sc, BLOCK_PXP2, init_phase);
17310 * Timers bug workaround: disables the pf_master bit in pglue at
17311 * common phase, we need to enable it here before any dmae access are
17312 * attempted. Therefore we manually added the enable-master to the
17313 * port phase (it also happens in the function phase)
17315 if (!CHIP_IS_E1x(sc)) {
17316 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17319 ecore_init_block(sc, BLOCK_ATC, init_phase);
17320 ecore_init_block(sc, BLOCK_DMAE, init_phase);
17321 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
17322 ecore_init_block(sc, BLOCK_QM, init_phase);
17324 ecore_init_block(sc, BLOCK_TCM, init_phase);
17325 ecore_init_block(sc, BLOCK_UCM, init_phase);
17326 ecore_init_block(sc, BLOCK_CCM, init_phase);
17327 ecore_init_block(sc, BLOCK_XCM, init_phase);
17329 /* QM cid (connection) count */
17330 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
17332 if (CNIC_SUPPORT(sc)) {
17333 ecore_init_block(sc, BLOCK_TM, init_phase);
17334 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20);
17335 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
17338 ecore_init_block(sc, BLOCK_DORQ, init_phase);
17340 ecore_init_block(sc, BLOCK_BRB1, init_phase);
17342 if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) {
17344 low = (BXE_ONE_PORT(sc) ? 160 : 246);
17345 } else if (sc->mtu > 4096) {
17346 if (BXE_ONE_PORT(sc)) {
17350 /* (24*1024 + val*4)/256 */
17351 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
17354 low = (BXE_ONE_PORT(sc) ? 80 : 160);
17356 high = (low + 56); /* 14*1024/256 */
17357 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
17358 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
17361 if (CHIP_IS_MODE_4_PORT(sc)) {
17362 REG_WR(sc, SC_PORT(sc) ?
17363 BRB1_REG_MAC_GUARANTIED_1 :
17364 BRB1_REG_MAC_GUARANTIED_0, 40);
17367 ecore_init_block(sc, BLOCK_PRS, init_phase);
17368 if (CHIP_IS_E3B0(sc)) {
17369 if (IS_MF_AFEX(sc)) {
17370 /* configure headers for AFEX mode */
17371 REG_WR(sc, SC_PORT(sc) ?
17372 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17373 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
17374 REG_WR(sc, SC_PORT(sc) ?
17375 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
17376 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
17377 REG_WR(sc, SC_PORT(sc) ?
17378 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
17379 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
17381 /* Ovlan exists only if we are in multi-function +
17382 * switch-dependent mode, in switch-independent there
17383 * is no ovlan headers
17385 REG_WR(sc, SC_PORT(sc) ?
17386 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17387 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
17388 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
17392 ecore_init_block(sc, BLOCK_TSDM, init_phase);
17393 ecore_init_block(sc, BLOCK_CSDM, init_phase);
17394 ecore_init_block(sc, BLOCK_USDM, init_phase);
17395 ecore_init_block(sc, BLOCK_XSDM, init_phase);
17397 ecore_init_block(sc, BLOCK_TSEM, init_phase);
17398 ecore_init_block(sc, BLOCK_USEM, init_phase);
17399 ecore_init_block(sc, BLOCK_CSEM, init_phase);
17400 ecore_init_block(sc, BLOCK_XSEM, init_phase);
17402 ecore_init_block(sc, BLOCK_UPB, init_phase);
17403 ecore_init_block(sc, BLOCK_XPB, init_phase);
17405 ecore_init_block(sc, BLOCK_PBF, init_phase);
17407 if (CHIP_IS_E1x(sc)) {
17408 /* configure PBF to work without PAUSE mtu 9000 */
17409 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
17411 /* update threshold */
17412 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
17413 /* update init credit */
17414 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
17416 /* probe changes */
17417 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1);
17419 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0);
17422 if (CNIC_SUPPORT(sc)) {
17423 ecore_init_block(sc, BLOCK_SRC, init_phase);
17426 ecore_init_block(sc, BLOCK_CDU, init_phase);
17427 ecore_init_block(sc, BLOCK_CFC, init_phase);
17429 if (CHIP_IS_E1(sc)) {
17430 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
17431 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
17433 ecore_init_block(sc, BLOCK_HC, init_phase);
17435 ecore_init_block(sc, BLOCK_IGU, init_phase);
17437 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
17438 /* init aeu_mask_attn_func_0/1:
17439 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
17440 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
17441 * bits 4-7 are used for "per vn group attention" */
17442 val = IS_MF(sc) ? 0xF7 : 0x7;
17443 /* Enable DCBX attention for all but E1 */
17444 val |= CHIP_IS_E1(sc) ? 0 : 0x10;
17445 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
17447 ecore_init_block(sc, BLOCK_NIG, init_phase);
17449 if (!CHIP_IS_E1x(sc)) {
17450 /* Bit-map indicating which L2 hdrs may appear after the
17451 * basic Ethernet header
17453 if (IS_MF_AFEX(sc)) {
17454 REG_WR(sc, SC_PORT(sc) ?
17455 NIG_REG_P1_HDRS_AFTER_BASIC :
17456 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
17458 REG_WR(sc, SC_PORT(sc) ?
17459 NIG_REG_P1_HDRS_AFTER_BASIC :
17460 NIG_REG_P0_HDRS_AFTER_BASIC,
17461 IS_MF_SD(sc) ? 7 : 6);
17464 if (CHIP_IS_E3(sc)) {
17465 REG_WR(sc, SC_PORT(sc) ?
17466 NIG_REG_LLH1_MF_MODE :
17467 NIG_REG_LLH_MF_MODE, IS_MF(sc));
17470 if (!CHIP_IS_E3(sc)) {
17471 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
17474 if (!CHIP_IS_E1(sc)) {
17475 /* 0x2 disable mf_ov, 0x1 enable */
17476 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
17477 (IS_MF_SD(sc) ? 0x1 : 0x2));
17479 if (!CHIP_IS_E1x(sc)) {
17481 switch (sc->devinfo.mf_info.mf_mode) {
17482 case MULTI_FUNCTION_SD:
17485 case MULTI_FUNCTION_SI:
17486 case MULTI_FUNCTION_AFEX:
17491 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
17492 NIG_REG_LLH0_CLS_TYPE), val);
17494 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
17495 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
17496 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
17499 /* If SPIO5 is set to generate interrupts, enable it for this port */
17500 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17501 if (val & MISC_SPIO_SPIO5) {
17502 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
17503 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
17504 val = REG_RD(sc, reg_addr);
17505 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
17506 REG_WR(sc, reg_addr, val);
17513 bxe_flr_clnup_reg_poll(struct bxe_softc *sc,
17516 uint32_t poll_count)
17518 uint32_t cur_cnt = poll_count;
17521 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
17522 DELAY(FLR_WAIT_INTERVAL);
17529 bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc,
17534 uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
17537 BLOGE(sc, "%s usage count=%d\n", msg, val);
17544 /* Common routines with VF FLR cleanup */
17546 bxe_flr_clnup_poll_count(struct bxe_softc *sc)
17548 /* adjust polling timeout */
17549 if (CHIP_REV_IS_EMUL(sc)) {
17550 return (FLR_POLL_CNT * 2000);
17553 if (CHIP_REV_IS_FPGA(sc)) {
17554 return (FLR_POLL_CNT * 120);
17557 return (FLR_POLL_CNT);
17561 bxe_poll_hw_usage_counters(struct bxe_softc *sc,
17564 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
17565 if (bxe_flr_clnup_poll_hw_counter(sc,
17566 CFC_REG_NUM_LCIDS_INSIDE_PF,
17567 "CFC PF usage counter timed out",
17572 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
17573 if (bxe_flr_clnup_poll_hw_counter(sc,
17574 DORQ_REG_PF_USAGE_CNT,
17575 "DQ PF usage counter timed out",
17580 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
17581 if (bxe_flr_clnup_poll_hw_counter(sc,
17582 QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc),
17583 "QM PF usage counter timed out",
17588 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
17589 if (bxe_flr_clnup_poll_hw_counter(sc,
17590 TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc),
17591 "Timers VNIC usage counter timed out",
17596 if (bxe_flr_clnup_poll_hw_counter(sc,
17597 TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc),
17598 "Timers NUM_SCANS usage counter timed out",
17603 /* Wait DMAE PF usage counter to zero */
17604 if (bxe_flr_clnup_poll_hw_counter(sc,
17605 dmae_reg_go_c[INIT_DMAE_C(sc)],
17606 "DMAE dommand register timed out",
17614 #define OP_GEN_PARAM(param) \
17615 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
17616 #define OP_GEN_TYPE(type) \
17617 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
17618 #define OP_GEN_AGG_VECT(index) \
17619 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
17622 bxe_send_final_clnup(struct bxe_softc *sc,
17623 uint8_t clnup_func,
17626 uint32_t op_gen_command = 0;
17627 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
17628 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
17631 if (REG_RD(sc, comp_addr)) {
17632 BLOGE(sc, "Cleanup complete was not 0 before sending\n");
17636 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
17637 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
17638 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
17639 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
17641 BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n");
17642 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
17644 if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
17645 BLOGE(sc, "FW final cleanup did not succeed\n");
17646 BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n",
17647 (REG_RD(sc, comp_addr)));
17648 bxe_panic(sc, ("FLR cleanup failed\n"));
17652 /* Zero completion for nxt FLR */
17653 REG_WR(sc, comp_addr, 0);
17659 bxe_pbf_pN_buf_flushed(struct bxe_softc *sc,
17660 struct pbf_pN_buf_regs *regs,
17661 uint32_t poll_count)
17663 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
17664 uint32_t cur_cnt = poll_count;
17666 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
17667 crd = crd_start = REG_RD(sc, regs->crd);
17668 init_crd = REG_RD(sc, regs->init_crd);
17670 BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
17671 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : s:%x\n", regs->pN, crd);
17672 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
17674 while ((crd != init_crd) &&
17675 ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) <
17676 (init_crd - crd_start))) {
17678 DELAY(FLR_WAIT_INTERVAL);
17679 crd = REG_RD(sc, regs->crd);
17680 crd_freed = REG_RD(sc, regs->crd_freed);
17682 BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN);
17683 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : c:%x\n", regs->pN, crd);
17684 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed);
17689 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n",
17690 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
17694 bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc,
17695 struct pbf_pN_cmd_regs *regs,
17696 uint32_t poll_count)
17698 uint32_t occup, to_free, freed, freed_start;
17699 uint32_t cur_cnt = poll_count;
17701 occup = to_free = REG_RD(sc, regs->lines_occup);
17702 freed = freed_start = REG_RD(sc, regs->lines_freed);
17704 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
17705 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
17708 ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) {
17710 DELAY(FLR_WAIT_INTERVAL);
17711 occup = REG_RD(sc, regs->lines_occup);
17712 freed = REG_RD(sc, regs->lines_freed);
17714 BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN);
17715 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
17716 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
17721 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n",
17722 poll_count - cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
17726 bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count)
17728 struct pbf_pN_cmd_regs cmd_regs[] = {
17729 {0, (CHIP_IS_E3B0(sc)) ?
17730 PBF_REG_TQ_OCCUPANCY_Q0 :
17731 PBF_REG_P0_TQ_OCCUPANCY,
17732 (CHIP_IS_E3B0(sc)) ?
17733 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
17734 PBF_REG_P0_TQ_LINES_FREED_CNT},
17735 {1, (CHIP_IS_E3B0(sc)) ?
17736 PBF_REG_TQ_OCCUPANCY_Q1 :
17737 PBF_REG_P1_TQ_OCCUPANCY,
17738 (CHIP_IS_E3B0(sc)) ?
17739 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
17740 PBF_REG_P1_TQ_LINES_FREED_CNT},
17741 {4, (CHIP_IS_E3B0(sc)) ?
17742 PBF_REG_TQ_OCCUPANCY_LB_Q :
17743 PBF_REG_P4_TQ_OCCUPANCY,
17744 (CHIP_IS_E3B0(sc)) ?
17745 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
17746 PBF_REG_P4_TQ_LINES_FREED_CNT}
17749 struct pbf_pN_buf_regs buf_regs[] = {
17750 {0, (CHIP_IS_E3B0(sc)) ?
17751 PBF_REG_INIT_CRD_Q0 :
17752 PBF_REG_P0_INIT_CRD ,
17753 (CHIP_IS_E3B0(sc)) ?
17754 PBF_REG_CREDIT_Q0 :
17756 (CHIP_IS_E3B0(sc)) ?
17757 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
17758 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
17759 {1, (CHIP_IS_E3B0(sc)) ?
17760 PBF_REG_INIT_CRD_Q1 :
17761 PBF_REG_P1_INIT_CRD,
17762 (CHIP_IS_E3B0(sc)) ?
17763 PBF_REG_CREDIT_Q1 :
17765 (CHIP_IS_E3B0(sc)) ?
17766 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
17767 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
17768 {4, (CHIP_IS_E3B0(sc)) ?
17769 PBF_REG_INIT_CRD_LB_Q :
17770 PBF_REG_P4_INIT_CRD,
17771 (CHIP_IS_E3B0(sc)) ?
17772 PBF_REG_CREDIT_LB_Q :
17774 (CHIP_IS_E3B0(sc)) ?
17775 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
17776 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
17781 /* Verify the command queues are flushed P0, P1, P4 */
17782 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
17783 bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
17786 /* Verify the transmission buffers are flushed P0, P1, P4 */
17787 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
17788 bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
17793 bxe_hw_enable_status(struct bxe_softc *sc)
17797 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
17798 BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
17800 val = REG_RD(sc, PBF_REG_DISABLE_PF);
17801 BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val);
17803 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
17804 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
17806 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
17807 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
17809 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
17810 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
17812 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
17813 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
17815 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
17816 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
17818 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
17819 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val);
17823 bxe_pf_flr_clnup(struct bxe_softc *sc)
17825 uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc);
17827 BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc));
17829 /* Re-enable PF target read access */
17830 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
17832 /* Poll HW usage counters */
17833 BLOGD(sc, DBG_LOAD, "Polling usage counters\n");
17834 if (bxe_poll_hw_usage_counters(sc, poll_cnt)) {
17838 /* Zero the igu 'trailing edge' and 'leading edge' */
17840 /* Send the FW cleanup command */
17841 if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) {
17847 /* Verify TX hw is flushed */
17848 bxe_tx_hw_flushed(sc, poll_cnt);
17850 /* Wait 100ms (not adjusted according to platform) */
17853 /* Verify no pending pci transactions */
17854 if (bxe_is_pcie_pending(sc)) {
17855 BLOGE(sc, "PCIE Transactions still pending\n");
17859 bxe_hw_enable_status(sc);
17862 * Master enable - Due to WB DMAE writes performed before this
17863 * register is re-initialized as part of the regular function init
17865 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17871 bxe_init_hw_func(struct bxe_softc *sc)
17873 int port = SC_PORT(sc);
17874 int func = SC_FUNC(sc);
17875 int init_phase = PHASE_PF0 + func;
17876 struct ecore_ilt *ilt = sc->ilt;
17877 uint16_t cdu_ilt_start;
17878 uint32_t addr, val;
17879 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
17880 int i, main_mem_width, rc;
17882 BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func);
17885 if (!CHIP_IS_E1x(sc)) {
17886 rc = bxe_pf_flr_clnup(sc);
17888 BLOGE(sc, "FLR cleanup failed!\n");
17889 // XXX bxe_fw_dump(sc);
17890 // XXX bxe_idle_chk(sc);
17895 /* set MSI reconfigure capability */
17896 if (sc->devinfo.int_block == INT_BLOCK_HC) {
17897 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
17898 val = REG_RD(sc, addr);
17899 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
17900 REG_WR(sc, addr, val);
17903 ecore_init_block(sc, BLOCK_PXP, init_phase);
17904 ecore_init_block(sc, BLOCK_PXP2, init_phase);
17907 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
17909 for (i = 0; i < L2_ILT_LINES(sc); i++) {
17910 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
17911 ilt->lines[cdu_ilt_start + i].page_mapping =
17912 sc->context[i].vcxt_dma.paddr;
17913 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
17915 ecore_ilt_init_op(sc, INITOP_SET);
17918 REG_WR(sc, PRS_REG_NIC_MODE, 1);
17919 BLOGD(sc, DBG_LOAD, "NIC MODE configured\n");
17921 if (!CHIP_IS_E1x(sc)) {
17922 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
17924 /* Turn on a single ISR mode in IGU if driver is going to use
17927 if (sc->interrupt_mode != INTR_MODE_MSIX) {
17928 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
17932 * Timers workaround bug: function init part.
17933 * Need to wait 20msec after initializing ILT,
17934 * needed to make sure there are no requests in
17935 * one of the PXP internal queues with "old" ILT addresses
17940 * Master enable - Due to WB DMAE writes performed before this
17941 * register is re-initialized as part of the regular function
17944 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17945 /* Enable the function in IGU */
17946 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
17949 sc->dmae_ready = 1;
17951 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
17953 if (!CHIP_IS_E1x(sc))
17954 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
17956 ecore_init_block(sc, BLOCK_ATC, init_phase);
17957 ecore_init_block(sc, BLOCK_DMAE, init_phase);
17958 ecore_init_block(sc, BLOCK_NIG, init_phase);
17959 ecore_init_block(sc, BLOCK_SRC, init_phase);
17960 ecore_init_block(sc, BLOCK_MISC, init_phase);
17961 ecore_init_block(sc, BLOCK_TCM, init_phase);
17962 ecore_init_block(sc, BLOCK_UCM, init_phase);
17963 ecore_init_block(sc, BLOCK_CCM, init_phase);
17964 ecore_init_block(sc, BLOCK_XCM, init_phase);
17965 ecore_init_block(sc, BLOCK_TSEM, init_phase);
17966 ecore_init_block(sc, BLOCK_USEM, init_phase);
17967 ecore_init_block(sc, BLOCK_CSEM, init_phase);
17968 ecore_init_block(sc, BLOCK_XSEM, init_phase);
17970 if (!CHIP_IS_E1x(sc))
17971 REG_WR(sc, QM_REG_PF_EN, 1);
17973 if (!CHIP_IS_E1x(sc)) {
17974 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17975 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17976 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17977 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17979 ecore_init_block(sc, BLOCK_QM, init_phase);
17981 ecore_init_block(sc, BLOCK_TM, init_phase);
17982 ecore_init_block(sc, BLOCK_DORQ, init_phase);
17984 bxe_iov_init_dq(sc);
17986 ecore_init_block(sc, BLOCK_BRB1, init_phase);
17987 ecore_init_block(sc, BLOCK_PRS, init_phase);
17988 ecore_init_block(sc, BLOCK_TSDM, init_phase);
17989 ecore_init_block(sc, BLOCK_CSDM, init_phase);
17990 ecore_init_block(sc, BLOCK_USDM, init_phase);
17991 ecore_init_block(sc, BLOCK_XSDM, init_phase);
17992 ecore_init_block(sc, BLOCK_UPB, init_phase);
17993 ecore_init_block(sc, BLOCK_XPB, init_phase);
17994 ecore_init_block(sc, BLOCK_PBF, init_phase);
17995 if (!CHIP_IS_E1x(sc))
17996 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
17998 ecore_init_block(sc, BLOCK_CDU, init_phase);
18000 ecore_init_block(sc, BLOCK_CFC, init_phase);
18002 if (!CHIP_IS_E1x(sc))
18003 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
18006 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
18007 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc));
18010 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
18012 /* HC init per function */
18013 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18014 if (CHIP_IS_E1H(sc)) {
18015 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18017 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18018 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18020 ecore_init_block(sc, BLOCK_HC, init_phase);
18023 int num_segs, sb_idx, prod_offset;
18025 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18027 if (!CHIP_IS_E1x(sc)) {
18028 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18029 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18032 ecore_init_block(sc, BLOCK_IGU, init_phase);
18034 if (!CHIP_IS_E1x(sc)) {
18038 * E2 mode: address 0-135 match to the mapping memory;
18039 * 136 - PF0 default prod; 137 - PF1 default prod;
18040 * 138 - PF2 default prod; 139 - PF3 default prod;
18041 * 140 - PF0 attn prod; 141 - PF1 attn prod;
18042 * 142 - PF2 attn prod; 143 - PF3 attn prod;
18043 * 144-147 reserved.
18045 * E1.5 mode - In backward compatible mode;
18046 * for non default SB; each even line in the memory
18047 * holds the U producer and each odd line hold
18048 * the C producer. The first 128 producers are for
18049 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
18050 * producers are for the DSB for each PF.
18051 * Each PF has five segments: (the order inside each
18052 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
18053 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
18054 * 144-147 attn prods;
18056 /* non-default-status-blocks */
18057 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18058 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
18059 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
18060 prod_offset = (sc->igu_base_sb + sb_idx) *
18063 for (i = 0; i < num_segs; i++) {
18064 addr = IGU_REG_PROD_CONS_MEMORY +
18065 (prod_offset + i) * 4;
18066 REG_WR(sc, addr, 0);
18068 /* send consumer update with value 0 */
18069 bxe_ack_sb(sc, sc->igu_base_sb + sb_idx,
18070 USTORM_ID, 0, IGU_INT_NOP, 1);
18071 bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
18074 /* default-status-blocks */
18075 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18076 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
18078 if (CHIP_IS_MODE_4_PORT(sc))
18079 dsb_idx = SC_FUNC(sc);
18081 dsb_idx = SC_VN(sc);
18083 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
18084 IGU_BC_BASE_DSB_PROD + dsb_idx :
18085 IGU_NORM_BASE_DSB_PROD + dsb_idx);
18088 * igu prods come in chunks of E1HVN_MAX (4) -
18089 * does not matters what is the current chip mode
18091 for (i = 0; i < (num_segs * E1HVN_MAX);
18093 addr = IGU_REG_PROD_CONS_MEMORY +
18094 (prod_offset + i)*4;
18095 REG_WR(sc, addr, 0);
18097 /* send consumer update with 0 */
18098 if (CHIP_INT_MODE_IS_BC(sc)) {
18099 bxe_ack_sb(sc, sc->igu_dsb_id,
18100 USTORM_ID, 0, IGU_INT_NOP, 1);
18101 bxe_ack_sb(sc, sc->igu_dsb_id,
18102 CSTORM_ID, 0, IGU_INT_NOP, 1);
18103 bxe_ack_sb(sc, sc->igu_dsb_id,
18104 XSTORM_ID, 0, IGU_INT_NOP, 1);
18105 bxe_ack_sb(sc, sc->igu_dsb_id,
18106 TSTORM_ID, 0, IGU_INT_NOP, 1);
18107 bxe_ack_sb(sc, sc->igu_dsb_id,
18108 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18110 bxe_ack_sb(sc, sc->igu_dsb_id,
18111 USTORM_ID, 0, IGU_INT_NOP, 1);
18112 bxe_ack_sb(sc, sc->igu_dsb_id,
18113 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18115 bxe_igu_clear_sb(sc, sc->igu_dsb_id);
18117 /* !!! these should become driver const once
18118 rf-tool supports split-68 const */
18119 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
18120 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
18121 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
18122 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
18123 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
18124 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
18128 /* Reset PCIE errors for debug */
18129 REG_WR(sc, 0x2114, 0xffffffff);
18130 REG_WR(sc, 0x2120, 0xffffffff);
18132 if (CHIP_IS_E1x(sc)) {
18133 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
18134 main_mem_base = HC_REG_MAIN_MEMORY +
18135 SC_PORT(sc) * (main_mem_size * 4);
18136 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
18137 main_mem_width = 8;
18139 val = REG_RD(sc, main_mem_prty_clr);
18141 BLOGD(sc, DBG_LOAD,
18142 "Parity errors in HC block during function init (0x%x)!\n",
18146 /* Clear "false" parity errors in MSI-X table */
18147 for (i = main_mem_base;
18148 i < main_mem_base + main_mem_size * 4;
18149 i += main_mem_width) {
18150 bxe_read_dmae(sc, i, main_mem_width / 4);
18151 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data),
18152 i, main_mem_width / 4);
18154 /* Clear HC parity attention */
18155 REG_RD(sc, main_mem_prty_clr);
18159 /* Enable STORMs SP logging */
18160 REG_WR8(sc, BAR_USTRORM_INTMEM +
18161 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18162 REG_WR8(sc, BAR_TSTRORM_INTMEM +
18163 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18164 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18165 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18166 REG_WR8(sc, BAR_XSTRORM_INTMEM +
18167 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18170 elink_phy_probe(&sc->link_params);
18176 bxe_link_reset(struct bxe_softc *sc)
18178 if (!BXE_NOMCP(sc)) {
18179 bxe_acquire_phy_lock(sc);
18180 elink_lfa_reset(&sc->link_params, &sc->link_vars);
18181 bxe_release_phy_lock(sc);
18183 if (!CHIP_REV_IS_SLOW(sc)) {
18184 BLOGW(sc, "Bootcode is missing - cannot reset link\n");
18190 bxe_reset_port(struct bxe_softc *sc)
18192 int port = SC_PORT(sc);
18195 /* reset physical Link */
18196 bxe_link_reset(sc);
18198 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
18200 /* Do not rcv packets to BRB */
18201 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
18202 /* Do not direct rcv packets that are not for MCP to the BRB */
18203 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
18204 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
18206 /* Configure AEU */
18207 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
18211 /* Check for BRB port occupancy */
18212 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
18214 BLOGD(sc, DBG_LOAD,
18215 "BRB1 is not empty, %d blocks are occupied\n", val);
18218 /* TODO: Close Doorbell port? */
18222 bxe_ilt_wr(struct bxe_softc *sc,
18227 uint32_t wb_write[2];
18229 if (CHIP_IS_E1(sc)) {
18230 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
18232 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
18235 wb_write[0] = ONCHIP_ADDR1(addr);
18236 wb_write[1] = ONCHIP_ADDR2(addr);
18237 REG_WR_DMAE(sc, reg, wb_write, 2);
18241 bxe_clear_func_ilt(struct bxe_softc *sc,
18244 uint32_t i, base = FUNC_ILT_BASE(func);
18245 for (i = base; i < base + ILT_PER_FUNC; i++) {
18246 bxe_ilt_wr(sc, i, 0);
18251 bxe_reset_func(struct bxe_softc *sc)
18253 struct bxe_fastpath *fp;
18254 int port = SC_PORT(sc);
18255 int func = SC_FUNC(sc);
18258 /* Disable the function in the FW */
18259 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
18260 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
18261 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
18262 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
18265 FOR_EACH_ETH_QUEUE(sc, i) {
18267 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18268 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
18273 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18274 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
18277 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
18278 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0);
18281 /* Configure IGU */
18282 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18283 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18284 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18286 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18287 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18290 if (CNIC_LOADED(sc)) {
18291 /* Disable Timer scan */
18292 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
18294 * Wait for at least 10ms and up to 2 second for the timers
18297 for (i = 0; i < 200; i++) {
18299 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4))
18305 bxe_clear_func_ilt(sc, func);
18308 * Timers workaround bug for E2: if this is vnic-3,
18309 * we need to set the entire ilt range for this timers.
18311 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
18312 struct ilt_client_info ilt_cli;
18313 /* use dummy TM client */
18314 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
18316 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
18317 ilt_cli.client_num = ILT_CLIENT_TM;
18319 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
18322 /* this assumes that reset_port() called before reset_func()*/
18323 if (!CHIP_IS_E1x(sc)) {
18324 bxe_pf_disable(sc);
18327 sc->dmae_ready = 0;
18331 bxe_gunzip_init(struct bxe_softc *sc)
18337 bxe_gunzip_end(struct bxe_softc *sc)
18343 bxe_init_firmware(struct bxe_softc *sc)
18345 if (CHIP_IS_E1(sc)) {
18346 ecore_init_e1_firmware(sc);
18347 sc->iro_array = e1_iro_arr;
18348 } else if (CHIP_IS_E1H(sc)) {
18349 ecore_init_e1h_firmware(sc);
18350 sc->iro_array = e1h_iro_arr;
18351 } else if (!CHIP_IS_E1x(sc)) {
18352 ecore_init_e2_firmware(sc);
18353 sc->iro_array = e2_iro_arr;
18355 BLOGE(sc, "Unsupported chip revision\n");
18363 bxe_release_firmware(struct bxe_softc *sc)
18370 ecore_gunzip(struct bxe_softc *sc,
18371 const uint8_t *zbuf,
18374 /* XXX : Implement... */
18375 BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n");
18380 ecore_reg_wr_ind(struct bxe_softc *sc,
18384 bxe_reg_wr_ind(sc, addr, val);
18388 ecore_write_dmae_phys_len(struct bxe_softc *sc,
18389 bus_addr_t phys_addr,
18393 bxe_write_dmae_phys_len(sc, phys_addr, addr, len);
18397 ecore_storm_memset_struct(struct bxe_softc *sc,
18403 for (i = 0; i < size/4; i++) {
18404 REG_WR(sc, addr + (i * 4), data[i]);
18410 * character device - ioctl interface definitions
18414 #include "bxe_dump.h"
18415 #include "bxe_ioctl.h"
18416 #include <sys/conf.h>
18418 static int bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
18419 struct thread *td);
18421 static struct cdevsw bxe_cdevsw = {
18422 .d_version = D_VERSION,
18423 .d_ioctl = bxe_eioctl,
18424 .d_name = "bxecnic",
18427 #define BXE_PATH(sc) (CHIP_IS_E1x(sc) ? 0 : (sc->pcie_func & 1))
18430 #define DUMP_ALL_PRESETS 0x1FFF
18431 #define DUMP_MAX_PRESETS 13
18432 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
18433 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
18434 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
18435 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
18436 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
18438 #define IS_REG_IN_PRESET(presets, idx) \
18439 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
18443 bxe_get_preset_regs_len(struct bxe_softc *sc, uint32_t preset)
18445 if (CHIP_IS_E1(sc))
18446 return dump_num_registers[0][preset-1];
18447 else if (CHIP_IS_E1H(sc))
18448 return dump_num_registers[1][preset-1];
18449 else if (CHIP_IS_E2(sc))
18450 return dump_num_registers[2][preset-1];
18451 else if (CHIP_IS_E3A0(sc))
18452 return dump_num_registers[3][preset-1];
18453 else if (CHIP_IS_E3B0(sc))
18454 return dump_num_registers[4][preset-1];
18460 bxe_get_total_regs_len32(struct bxe_softc *sc)
18462 uint32_t preset_idx;
18463 int regdump_len32 = 0;
18466 /* Calculate the total preset regs length */
18467 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
18468 regdump_len32 += bxe_get_preset_regs_len(sc, preset_idx);
18471 return regdump_len32;
18474 static const uint32_t *
18475 __bxe_get_page_addr_ar(struct bxe_softc *sc)
18477 if (CHIP_IS_E2(sc))
18478 return page_vals_e2;
18479 else if (CHIP_IS_E3(sc))
18480 return page_vals_e3;
18486 __bxe_get_page_reg_num(struct bxe_softc *sc)
18488 if (CHIP_IS_E2(sc))
18489 return PAGE_MODE_VALUES_E2;
18490 else if (CHIP_IS_E3(sc))
18491 return PAGE_MODE_VALUES_E3;
18496 static const uint32_t *
18497 __bxe_get_page_write_ar(struct bxe_softc *sc)
18499 if (CHIP_IS_E2(sc))
18500 return page_write_regs_e2;
18501 else if (CHIP_IS_E3(sc))
18502 return page_write_regs_e3;
18508 __bxe_get_page_write_num(struct bxe_softc *sc)
18510 if (CHIP_IS_E2(sc))
18511 return PAGE_WRITE_REGS_E2;
18512 else if (CHIP_IS_E3(sc))
18513 return PAGE_WRITE_REGS_E3;
18518 static const struct reg_addr *
18519 __bxe_get_page_read_ar(struct bxe_softc *sc)
18521 if (CHIP_IS_E2(sc))
18522 return page_read_regs_e2;
18523 else if (CHIP_IS_E3(sc))
18524 return page_read_regs_e3;
18530 __bxe_get_page_read_num(struct bxe_softc *sc)
18532 if (CHIP_IS_E2(sc))
18533 return PAGE_READ_REGS_E2;
18534 else if (CHIP_IS_E3(sc))
18535 return PAGE_READ_REGS_E3;
18541 bxe_is_reg_in_chip(struct bxe_softc *sc, const struct reg_addr *reg_info)
18543 if (CHIP_IS_E1(sc))
18544 return IS_E1_REG(reg_info->chips);
18545 else if (CHIP_IS_E1H(sc))
18546 return IS_E1H_REG(reg_info->chips);
18547 else if (CHIP_IS_E2(sc))
18548 return IS_E2_REG(reg_info->chips);
18549 else if (CHIP_IS_E3A0(sc))
18550 return IS_E3A0_REG(reg_info->chips);
18551 else if (CHIP_IS_E3B0(sc))
18552 return IS_E3B0_REG(reg_info->chips);
18558 bxe_is_wreg_in_chip(struct bxe_softc *sc, const struct wreg_addr *wreg_info)
18560 if (CHIP_IS_E1(sc))
18561 return IS_E1_REG(wreg_info->chips);
18562 else if (CHIP_IS_E1H(sc))
18563 return IS_E1H_REG(wreg_info->chips);
18564 else if (CHIP_IS_E2(sc))
18565 return IS_E2_REG(wreg_info->chips);
18566 else if (CHIP_IS_E3A0(sc))
18567 return IS_E3A0_REG(wreg_info->chips);
18568 else if (CHIP_IS_E3B0(sc))
18569 return IS_E3B0_REG(wreg_info->chips);
18575 * bxe_read_pages_regs - read "paged" registers
18577 * @bp device handle
18580 * Reads "paged" memories: memories that may only be read by first writing to a
18581 * specific address ("write address") and then reading from a specific address
18582 * ("read address"). There may be more than one write address per "page" and
18583 * more than one read address per write address.
18586 bxe_read_pages_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
18588 uint32_t i, j, k, n;
18590 /* addresses of the paged registers */
18591 const uint32_t *page_addr = __bxe_get_page_addr_ar(sc);
18592 /* number of paged registers */
18593 int num_pages = __bxe_get_page_reg_num(sc);
18594 /* write addresses */
18595 const uint32_t *write_addr = __bxe_get_page_write_ar(sc);
18596 /* number of write addresses */
18597 int write_num = __bxe_get_page_write_num(sc);
18598 /* read addresses info */
18599 const struct reg_addr *read_addr = __bxe_get_page_read_ar(sc);
18600 /* number of read addresses */
18601 int read_num = __bxe_get_page_read_num(sc);
18602 uint32_t addr, size;
18604 for (i = 0; i < num_pages; i++) {
18605 for (j = 0; j < write_num; j++) {
18606 REG_WR(sc, write_addr[j], page_addr[i]);
18608 for (k = 0; k < read_num; k++) {
18609 if (IS_REG_IN_PRESET(read_addr[k].presets, preset)) {
18610 size = read_addr[k].size;
18611 for (n = 0; n < size; n++) {
18612 addr = read_addr[k].addr + n*4;
18613 *p++ = REG_RD(sc, addr);
18624 bxe_get_preset_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
18626 uint32_t i, j, addr;
18627 const struct wreg_addr *wreg_addr_p = NULL;
18629 if (CHIP_IS_E1(sc))
18630 wreg_addr_p = &wreg_addr_e1;
18631 else if (CHIP_IS_E1H(sc))
18632 wreg_addr_p = &wreg_addr_e1h;
18633 else if (CHIP_IS_E2(sc))
18634 wreg_addr_p = &wreg_addr_e2;
18635 else if (CHIP_IS_E3A0(sc))
18636 wreg_addr_p = &wreg_addr_e3;
18637 else if (CHIP_IS_E3B0(sc))
18638 wreg_addr_p = &wreg_addr_e3b0;
18642 /* Read the idle_chk registers */
18643 for (i = 0; i < IDLE_REGS_COUNT; i++) {
18644 if (bxe_is_reg_in_chip(sc, &idle_reg_addrs[i]) &&
18645 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
18646 for (j = 0; j < idle_reg_addrs[i].size; j++)
18647 *p++ = REG_RD(sc, idle_reg_addrs[i].addr + j*4);
18651 /* Read the regular registers */
18652 for (i = 0; i < REGS_COUNT; i++) {
18653 if (bxe_is_reg_in_chip(sc, ®_addrs[i]) &&
18654 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
18655 for (j = 0; j < reg_addrs[i].size; j++)
18656 *p++ = REG_RD(sc, reg_addrs[i].addr + j*4);
18660 /* Read the CAM registers */
18661 if (bxe_is_wreg_in_chip(sc, wreg_addr_p) &&
18662 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
18663 for (i = 0; i < wreg_addr_p->size; i++) {
18664 *p++ = REG_RD(sc, wreg_addr_p->addr + i*4);
18666 /* In case of wreg_addr register, read additional
18667 registers from read_regs array
18669 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
18670 addr = *(wreg_addr_p->read_regs);
18671 *p++ = REG_RD(sc, addr + j*4);
18676 /* Paged registers are supported in E2 & E3 only */
18677 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
18678 /* Read "paged" registers */
18679 bxe_read_pages_regs(sc, p, preset);
18686 bxe_grc_dump(struct bxe_softc *sc)
18689 uint32_t preset_idx;
18692 struct dump_header *d_hdr;
18694 if (sc->grcdump_done)
18697 ecore_disable_blocks_parity(sc);
18699 buf = sc->grc_dump;
18700 d_hdr = sc->grc_dump;
18702 d_hdr->header_size = (sizeof(struct dump_header) >> 2) - 1;
18703 d_hdr->version = BNX2X_DUMP_VERSION;
18704 d_hdr->preset = DUMP_ALL_PRESETS;
18706 if (CHIP_IS_E1(sc)) {
18707 d_hdr->dump_meta_data = DUMP_CHIP_E1;
18708 } else if (CHIP_IS_E1H(sc)) {
18709 d_hdr->dump_meta_data = DUMP_CHIP_E1H;
18710 } else if (CHIP_IS_E2(sc)) {
18711 d_hdr->dump_meta_data = DUMP_CHIP_E2 |
18712 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18713 } else if (CHIP_IS_E3A0(sc)) {
18714 d_hdr->dump_meta_data = DUMP_CHIP_E3A0 |
18715 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18716 } else if (CHIP_IS_E3B0(sc)) {
18717 d_hdr->dump_meta_data = DUMP_CHIP_E3B0 |
18718 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18721 buf += sizeof(struct dump_header);
18723 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
18725 /* Skip presets with IOR */
18726 if ((preset_idx == 2) || (preset_idx == 5) || (preset_idx == 8) ||
18727 (preset_idx == 11))
18730 rval = bxe_get_preset_regs(sc, sc->grc_dump, preset_idx);
18735 size = bxe_get_preset_regs_len(sc, preset_idx) * (sizeof (uint32_t));
18740 ecore_clear_blocks_parity(sc);
18741 ecore_enable_blocks_parity(sc);
18743 sc->grcdump_done = 1;
18748 bxe_add_cdev(struct bxe_softc *sc)
18752 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
18753 sizeof(struct dump_header);
18755 sc->grc_dump = malloc(grc_dump_size, M_DEVBUF, M_NOWAIT);
18757 if (sc->grc_dump == NULL)
18760 sc->eeprom = malloc(BXE_EEPROM_MAX_DATA_LEN, M_DEVBUF, M_NOWAIT);
18762 if (sc->eeprom == NULL) {
18763 BLOGW(sc, "Unable to alloc for eeprom size buffer\n");
18764 free(sc->grc_dump, M_DEVBUF); sc->grc_dump = NULL;
18768 sc->ioctl_dev = make_dev(&bxe_cdevsw,
18769 sc->ifnet->if_dunit,
18774 if_name(sc->ifnet));
18776 if (sc->ioctl_dev == NULL) {
18778 free(sc->grc_dump, M_DEVBUF);
18779 free(sc->eeprom, M_DEVBUF);
18785 sc->ioctl_dev->si_drv1 = sc;
18791 bxe_del_cdev(struct bxe_softc *sc)
18793 if (sc->ioctl_dev != NULL)
18794 destroy_dev(sc->ioctl_dev);
18796 if (sc->grc_dump != NULL)
18797 free(sc->grc_dump, M_DEVBUF);
18799 if (sc->eeprom != NULL) {
18800 free(sc->eeprom, M_DEVBUF);
18807 static bool bxe_is_nvram_accessible(struct bxe_softc *sc)
18810 if ((sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) == 0)
18818 bxe_wr_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
18822 if(!bxe_is_nvram_accessible(sc)) {
18823 BLOGW(sc, "Cannot access eeprom when interface is down\n");
18826 rval = bxe_nvram_write(sc, offset, (uint8_t *)data, len);
18833 bxe_rd_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
18837 if(!bxe_is_nvram_accessible(sc)) {
18838 BLOGW(sc, "Cannot access eeprom when interface is down\n");
18841 rval = bxe_nvram_read(sc, offset, (uint8_t *)data, len);
18847 bxe_eeprom_rd_wr(struct bxe_softc *sc, bxe_eeprom_t *eeprom)
18851 switch (eeprom->eeprom_cmd) {
18853 case BXE_EEPROM_CMD_SET_EEPROM:
18855 rval = copyin(eeprom->eeprom_data, sc->eeprom,
18856 eeprom->eeprom_data_len);
18861 rval = bxe_wr_eeprom(sc, sc->eeprom, eeprom->eeprom_offset,
18862 eeprom->eeprom_data_len);
18865 case BXE_EEPROM_CMD_GET_EEPROM:
18867 rval = bxe_rd_eeprom(sc, sc->eeprom, eeprom->eeprom_offset,
18868 eeprom->eeprom_data_len);
18874 rval = copyout(sc->eeprom, eeprom->eeprom_data,
18875 eeprom->eeprom_data_len);
18884 BLOGW(sc, "ioctl cmd %d failed rval %d\n", eeprom->eeprom_cmd, rval);
18891 bxe_get_settings(struct bxe_softc *sc, bxe_dev_setting_t *dev_p)
18893 uint32_t ext_phy_config;
18894 int port = SC_PORT(sc);
18895 int cfg_idx = bxe_get_link_cfg_idx(sc);
18897 dev_p->supported = sc->port.supported[cfg_idx] |
18898 (sc->port.supported[cfg_idx ^ 1] &
18899 (ELINK_SUPPORTED_TP | ELINK_SUPPORTED_FIBRE));
18900 dev_p->advertising = sc->port.advertising[cfg_idx];
18901 if(sc->link_params.phy[bxe_get_cur_phy_idx(sc)].media_type ==
18902 ELINK_ETH_PHY_SFP_1G_FIBER) {
18903 dev_p->supported = ~(ELINK_SUPPORTED_10000baseT_Full);
18904 dev_p->advertising &= ~(ADVERTISED_10000baseT_Full);
18906 if ((sc->state == BXE_STATE_OPEN) && sc->link_vars.link_up &&
18907 !(sc->flags & BXE_MF_FUNC_DIS)) {
18908 dev_p->duplex = sc->link_vars.duplex;
18909 if (IS_MF(sc) && !BXE_NOMCP(sc))
18910 dev_p->speed = bxe_get_mf_speed(sc);
18912 dev_p->speed = sc->link_vars.line_speed;
18914 dev_p->duplex = DUPLEX_UNKNOWN;
18915 dev_p->speed = SPEED_UNKNOWN;
18918 dev_p->port = bxe_media_detect(sc);
18920 ext_phy_config = SHMEM_RD(sc,
18921 dev_info.port_hw_config[port].external_phy_config);
18922 if((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) ==
18923 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
18924 dev_p->phy_address = sc->port.phy_addr;
18925 else if(((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) !=
18926 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
18927 ((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) !=
18928 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
18929 dev_p->phy_address = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
18931 dev_p->phy_address = 0;
18933 if(sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG)
18934 dev_p->autoneg = AUTONEG_ENABLE;
18936 dev_p->autoneg = AUTONEG_DISABLE;
18943 bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
18946 struct bxe_softc *sc;
18949 bxe_grcdump_t *dump = NULL;
18951 bxe_drvinfo_t *drv_infop = NULL;
18952 bxe_dev_setting_t *dev_p;
18953 bxe_dev_setting_t dev_set;
18954 bxe_get_regs_t *reg_p;
18955 bxe_reg_rdw_t *reg_rdw_p;
18956 bxe_pcicfg_rdw_t *cfg_rdw_p;
18957 bxe_perm_mac_addr_t *mac_addr_p;
18960 if ((sc = (struct bxe_softc *)dev->si_drv1) == NULL)
18965 dump = (bxe_grcdump_t *)data;
18969 case BXE_GRC_DUMP_SIZE:
18970 dump->pci_func = sc->pcie_func;
18971 dump->grcdump_size =
18972 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
18973 sizeof(struct dump_header);
18978 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
18979 sizeof(struct dump_header);
18981 if ((sc->grc_dump == NULL) || (dump->grcdump == NULL) ||
18982 (dump->grcdump_size < grc_dump_size) || (!sc->grcdump_done)) {
18986 dump->grcdump_dwords = grc_dump_size >> 2;
18987 rval = copyout(sc->grc_dump, dump->grcdump, grc_dump_size);
18988 sc->grcdump_done = 0;
18993 drv_infop = (bxe_drvinfo_t *)data;
18994 snprintf(drv_infop->drv_name, BXE_DRV_NAME_LENGTH, "%s", "bxe");
18995 snprintf(drv_infop->drv_version, BXE_DRV_VERSION_LENGTH, "v:%s",
18996 BXE_DRIVER_VERSION);
18997 snprintf(drv_infop->mfw_version, BXE_MFW_VERSION_LENGTH, "%s",
18998 sc->devinfo.bc_ver_str);
18999 snprintf(drv_infop->stormfw_version, BXE_STORMFW_VERSION_LENGTH,
19000 "%s", sc->fw_ver_str);
19001 drv_infop->eeprom_dump_len = sc->devinfo.flash_size;
19002 drv_infop->reg_dump_len =
19003 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t))
19004 + sizeof(struct dump_header);
19005 snprintf(drv_infop->bus_info, BXE_BUS_INFO_LENGTH, "%d:%d:%d",
19006 sc->pcie_bus, sc->pcie_device, sc->pcie_func);
19008 case BXE_DEV_SETTING:
19009 dev_p = (bxe_dev_setting_t *)data;
19010 bxe_get_settings(sc, &dev_set);
19011 dev_p->supported = dev_set.supported;
19012 dev_p->advertising = dev_set.advertising;
19013 dev_p->speed = dev_set.speed;
19014 dev_p->duplex = dev_set.duplex;
19015 dev_p->port = dev_set.port;
19016 dev_p->phy_address = dev_set.phy_address;
19017 dev_p->autoneg = dev_set.autoneg;
19023 reg_p = (bxe_get_regs_t *)data;
19024 grc_dump_size = reg_p->reg_buf_len;
19026 if (sc->grc_dump == NULL) {
19031 if(!sc->grcdump_done) {
19034 if(sc->grcdump_done) {
19035 rval = copyout(sc->grc_dump, reg_p->reg_buf, grc_dump_size);
19036 sc->grcdump_done = 0;
19041 reg_rdw_p = (bxe_reg_rdw_t *)data;
19042 if((reg_rdw_p->reg_cmd == BXE_READ_REG_CMD) &&
19043 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT))
19044 reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id);
19046 if((reg_rdw_p->reg_cmd == BXE_WRITE_REG_CMD) &&
19047 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT))
19048 REG_WR(sc, reg_rdw_p->reg_id, reg_rdw_p->reg_val);
19052 case BXE_RDW_PCICFG:
19053 cfg_rdw_p = (bxe_pcicfg_rdw_t *)data;
19054 if(cfg_rdw_p->cfg_cmd == BXE_READ_PCICFG) {
19056 cfg_rdw_p->cfg_val = pci_read_config(sc->dev, cfg_rdw_p->cfg_id,
19057 cfg_rdw_p->cfg_width);
19059 } else if(cfg_rdw_p->cfg_cmd == BXE_WRITE_PCICFG) {
19060 pci_write_config(sc->dev, cfg_rdw_p->cfg_id, cfg_rdw_p->cfg_val,
19061 cfg_rdw_p->cfg_width);
19063 BLOGW(sc, "BXE_RDW_PCICFG ioctl wrong cmd passed\n");
19068 mac_addr_p = (bxe_perm_mac_addr_t *)data;
19069 snprintf(mac_addr_p->mac_addr_str, sizeof(sc->mac_addr_str), "%s",
19074 rval = bxe_eeprom_rd_wr(sc, (bxe_eeprom_t *)data);