2 * Copyright (C) 2005 Internet Systems Consortium, Inc. ("ISC")
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH
9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
10 * AND FITNESS. IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT,
11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
13 * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
14 * PERFORMANCE OF THIS SOFTWARE.
17 /* $Id: atomic.h,v 1.2.2.2 2005/06/16 22:01:01 jinmei Exp $ */
20 * This code was written based on FreeBSD's kernel source whose copyright
25 * Copyright (c) 1998 Doug Rabson
26 * All rights reserved.
28 * Redistribution and use in source and binary forms, with or without
29 * modification, are permitted provided that the following conditions
31 * 1. Redistributions of source code must retain the above copyright
32 * notice, this list of conditions and the following disclaimer.
33 * 2. Redistributions in binary form must reproduce the above copyright
34 * notice, this list of conditions and the following disclaimer in the
35 * documentation and/or other materials provided with the distribution.
37 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
38 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
40 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
41 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
42 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
43 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
44 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
45 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
46 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
53 #define ISC_ATOMIC_H 1
55 #include <isc/platform.h>
56 #include <isc/types.h>
58 #ifdef ISC_PLATFORM_USEOSFASM
61 #pragma intrinsic(asm)
64 * This routine atomically increments the value stored in 'p' by 'val', and
65 * returns the previous value.
67 static inline isc_int32_t
68 isc_atomic_xadd(isc_int32_t *p, isc_int32_t val) {
70 "ldl_l %t0, 0(%a0);" /* load old value */
71 "mov %t0, %v0;" /* copy the old value */
72 "addl %t0, %a1, %t0;" /* calculate new value */
73 "stl_c %t0, 0(%a0);" /* attempt to store */
74 "beq %t0, 1b;", /* spin if failed */
79 * This routine atomically stores the value 'val' in 'p'.
82 isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
84 "ldl_l %t0, 0(%a0);" /* load old value */
85 "mov %a1, %t0;" /* value to store */
86 "stl_c %t0, 0(%a0);" /* attempt to store */
87 "beq %t0, 1b;", /* spin if failed */
92 * This routine atomically replaces the value in 'p' with 'val', if the
93 * original value is equal to 'cmpval'. The original value is returned in any
96 static inline isc_int32_t
97 isc_atomic_cmpxchg(isc_int32_t *p, isc_int32_t cmpval, isc_int32_t val) {
100 "ldl_l %t0, 0(%a0);" /* load old value */
101 "mov %t0, %v0;" /* copy the old value */
102 "cmpeq %t0, %a1, %t0;" /* compare */
103 "beq %t0, 2f;" /* exit if not equal */
104 "mov %a2, %t0;" /* value to store */
105 "stl_c %t0, 0(%a0);" /* attempt to store */
106 "beq %t0, 1b;" /* if it failed, spin */
110 #elif defined (ISC_PLATFORM_USEGCCASM)
111 static inline isc_int32_t
112 isc_atomic_xadd(isc_int32_t *p, isc_int32_t val) {
113 isc_int32_t temp, prev;
117 "ldl_l %0, %1;" /* load old value */
118 "mov %0, %2;" /* copy the old value */
119 "addl %0, %3, %0;" /* calculate new value */
120 "stl_c %0, %1;" /* attempt to store */
121 "beq %0, 1b;" /* spin if failed */
122 : "=&r"(temp), "+m"(*p), "=r"(prev)
130 isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
135 "ldl_l %0, %1;" /* load old value */
136 "mov %2, %0;" /* value to store */
137 "stl_c %0, %1;" /* attempt to store */
138 "beq %0, 1b;" /* if it failed, spin */
139 : "=&r"(temp), "+m"(*p)
144 static inline isc_int32_t
145 isc_atomic_cmpxchg(isc_int32_t *p, isc_int32_t cmpval, isc_int32_t val) {
146 isc_int32_t temp, prev;
150 "ldl_l %0, %1;" /* load old value */
151 "mov %0, %2;" /* copy the old value */
152 "cmpeq %0, %3, %0;" /* compare */
153 "beq %0, 2f;" /* exit if not equal */
154 "mov %4, %0;" /* value to store */
155 "stl_c %0, %1;" /* attempt to store */
156 "beq %0, 1b;" /* if it failed, spin */
158 : "=&r"(temp), "+m"(*p), "=r"(prev)
159 : "r"(cmpval), "r"(val)
166 #error "unsupported compiler. disable atomic ops by --disable-atomic"
170 #endif /* ISC_ATOMIC_H */