1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target-independent interfaces used by SelectionDAG
10 // instruction selection generators.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Selection DAG Type Constraint definitions.
17 // Note that the semantics of these constraints are hard coded into tblgen. To
18 // modify or add constraints, you have to hack tblgen.
21 class SDTypeConstraint<int opnum> {
22 int OperandNum = opnum;
25 // SDTCisVT - The specified operand has exactly this VT.
26 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
30 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
32 // SDTCisInt - The specified operand has integer type.
33 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
35 // SDTCisFP - The specified operand has floating-point type.
36 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
38 // SDTCisVec - The specified operand has a vector type.
39 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
41 // SDTCisSameAs - The two specified operands have identical types.
42 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
43 int OtherOperandNum = OtherOp;
46 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
47 // smaller than the 'Other' operand.
48 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
49 int OtherOperandNum = OtherOp;
52 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
53 int BigOperandNum = BigOp;
56 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
57 /// type as the element type of OtherOp, which is a vector type.
58 class SDTCisEltOfVec<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
64 /// with length less that of OtherOp, which is a vector type.
65 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 // SDTCVecEltisVT - The specified operand is vector type with element type
72 class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
76 // SDTCisSameNumEltsAs - The two specified operands have identical number
78 class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
79 int OtherOperandNum = OtherOp;
82 // SDTCisSameSizeAs - The two specified operands have identical size.
83 class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
84 int OtherOperandNum = OtherOp;
87 //===----------------------------------------------------------------------===//
88 // Selection DAG Type Profile definitions.
90 // These use the constraints defined above to describe the type requirements of
91 // the various nodes. These are not hard coded into tblgen, allowing targets to
92 // add their own if needed.
95 // SDTypeProfile - This profile describes the type requirements of a Selection
97 class SDTypeProfile<int numresults, int numoperands,
98 list<SDTypeConstraint> constraints> {
99 int NumResults = numresults;
100 int NumOperands = numoperands;
101 list<SDTypeConstraint> Constraints = constraints;
105 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
106 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
107 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
108 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
109 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
110 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
112 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
115 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
116 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
118 def SDTIntShiftDOp: SDTypeProfile<1, 3, [ // fshl, fshr
119 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
121 def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift
122 SDTCisSameAs<0, 1>, SDTCisInt<2>
124 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
125 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
127 def SDTIntScaledBinOp : SDTypeProfile<1, 3, [ // smulfix, sdivfix, etc
128 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
131 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
132 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
134 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
135 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
137 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
140 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // bitreverse
141 SDTCisSameAs<0, 1>, SDTCisInt<0>
143 def SDTIntBitCountUnaryOp : SDTypeProfile<1, 1, [ // ctlz, cttz
144 SDTCisInt<0>, SDTCisInt<1>
146 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
147 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>
149 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
150 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>
152 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
153 SDTCisSameAs<0, 1>, SDTCisFP<0>
155 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
156 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>
158 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
159 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>
161 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
162 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>
164 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
165 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>
167 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
168 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
169 SDTCisVTSmallerThanOp<2, 1>
171 def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec
172 SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>,
173 SDTCisOpSmallerThanOp<1, 0>
176 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
177 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
180 def SDTSelect : SDTypeProfile<1, 3, [ // select
181 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
184 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
185 SDTCisVec<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1>
188 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
189 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
193 def SDTBr : SDTypeProfile<0, 1, [ // br
197 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc
198 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
201 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
202 SDTCisInt<0>, SDTCisVT<1, OtherVT>
205 def SDTBrind : SDTypeProfile<0, 1, [ // brind
209 def SDTCatchret : SDTypeProfile<0, 2, [ // catchret
210 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>
213 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
215 def SDTLoad : SDTypeProfile<1, 1, [ // load
219 def SDTStore : SDTypeProfile<0, 2, [ // store
223 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
224 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
227 def SDTMaskedStore: SDTypeProfile<0, 4, [ // masked store
228 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameNumEltsAs<0, 3>
231 def SDTMaskedLoad: SDTypeProfile<1, 4, [ // masked load
232 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameAs<0, 4>,
233 SDTCisSameNumEltsAs<0, 3>
236 def SDTVecShuffle : SDTypeProfile<1, 2, [
237 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
239 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
240 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
242 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
243 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
245 def SDTVecReduce : SDTypeProfile<1, 1, [ // vector reduction
246 SDTCisInt<0>, SDTCisVec<1>
249 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
250 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
252 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
253 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
256 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
257 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
260 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier
261 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
264 def SDTAtomicFence : SDTypeProfile<0, 2, [
265 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
267 def SDTAtomic3 : SDTypeProfile<1, 3, [
268 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
270 def SDTAtomic2 : SDTypeProfile<1, 2, [
271 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
274 def SDTFPAtomic2 : SDTypeProfile<1, 2, [
275 SDTCisSameAs<0,2>, SDTCisFP<0>, SDTCisPtrTy<1>
278 def SDTAtomicStore : SDTypeProfile<0, 2, [
279 SDTCisPtrTy<0>, SDTCisInt<1>
281 def SDTAtomicLoad : SDTypeProfile<1, 1, [
282 SDTCisInt<0>, SDTCisPtrTy<1>
285 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
286 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
289 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
290 SDTypeProfile<0, 2, constraints>;
291 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
292 SDTypeProfile<0, 2, constraints>;
294 //===----------------------------------------------------------------------===//
295 // Selection DAG Node definitions.
297 class SDNode<string opcode, SDTypeProfile typeprof,
298 list<SDNodeProperty> props = [], string sdclass = "SDNode">
299 : SDPatternOperator {
300 string Opcode = opcode;
301 string SDClass = sdclass;
302 let Properties = props;
303 SDTypeProfile TypeProfile = typeprof;
306 // Special TableGen-recognized dag nodes
312 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
313 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
314 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
315 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
316 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
317 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
318 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
319 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
320 "GlobalAddressSDNode">;
321 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
322 "GlobalAddressSDNode">;
323 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
324 "GlobalAddressSDNode">;
325 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
326 "GlobalAddressSDNode">;
327 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
328 "ConstantPoolSDNode">;
329 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
330 "ConstantPoolSDNode">;
331 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
333 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
335 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
337 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
339 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
340 "ExternalSymbolSDNode">;
341 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
342 "ExternalSymbolSDNode">;
343 def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">;
344 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
345 "BlockAddressSDNode">;
346 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
347 "BlockAddressSDNode">;
349 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
350 [SDNPCommutative, SDNPAssociative]>;
351 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
352 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
353 [SDNPCommutative, SDNPAssociative]>;
354 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
355 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
356 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
357 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
358 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
359 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
360 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
361 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
362 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
363 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
364 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
365 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
366 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
367 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
368 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
369 def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>;
370 def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
371 def and : SDNode<"ISD::AND" , SDTIntBinOp,
372 [SDNPCommutative, SDNPAssociative]>;
373 def or : SDNode<"ISD::OR" , SDTIntBinOp,
374 [SDNPCommutative, SDNPAssociative]>;
375 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
376 [SDNPCommutative, SDNPAssociative]>;
377 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
378 [SDNPCommutative, SDNPOutGlue]>;
379 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
380 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
381 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
383 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
384 [SDNPOutGlue, SDNPInGlue]>;
385 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp,
386 [SDNPCommutative, SDNPAssociative]>;
387 def smax : SDNode<"ISD::SMAX" , SDTIntBinOp,
388 [SDNPCommutative, SDNPAssociative]>;
389 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp,
390 [SDNPCommutative, SDNPAssociative]>;
391 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
392 [SDNPCommutative, SDNPAssociative]>;
394 def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
395 def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
396 def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>;
397 def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>;
399 def smulfix : SDNode<"ISD::SMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>;
400 def smulfixsat : SDNode<"ISD::SMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>;
401 def umulfix : SDNode<"ISD::UMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>;
402 def umulfixsat : SDNode<"ISD::UMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>;
403 def sdivfix : SDNode<"ISD::SDIVFIX" , SDTIntScaledBinOp>;
404 def udivfix : SDNode<"ISD::UDIVFIX" , SDTIntScaledBinOp>;
406 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
407 def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>;
408 def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>;
410 def abs : SDNode<"ISD::ABS" , SDTIntUnaryOp>;
411 def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>;
412 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
413 def ctlz : SDNode<"ISD::CTLZ" , SDTIntBitCountUnaryOp>;
414 def cttz : SDNode<"ISD::CTTZ" , SDTIntBitCountUnaryOp>;
415 def ctpop : SDNode<"ISD::CTPOP" , SDTIntBitCountUnaryOp>;
416 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>;
417 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>;
418 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
419 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
420 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
421 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
422 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
423 def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>;
424 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
425 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
427 def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>;
428 def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>;
429 def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>;
430 def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>;
431 def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>;
433 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
434 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
435 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
436 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
437 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
438 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
439 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
440 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
441 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp,
442 [SDNPCommutative, SDNPAssociative]>;
443 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp,
444 [SDNPCommutative, SDNPAssociative]>;
445 def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp,
447 def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp,
449 def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp,
450 [SDNPCommutative, SDNPAssociative]>;
451 def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp,
452 [SDNPCommutative, SDNPAssociative]>;
453 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
454 def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>;
455 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
456 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
457 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
458 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
459 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
460 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
461 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
462 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
463 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
464 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
465 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
466 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
467 def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
469 def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>;
470 def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>;
471 def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>;
472 def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>;
474 def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
475 def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
476 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
478 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
479 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
480 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
481 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
482 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
483 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
485 def strict_fadd : SDNode<"ISD::STRICT_FADD",
486 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>;
487 def strict_fsub : SDNode<"ISD::STRICT_FSUB",
488 SDTFPBinOp, [SDNPHasChain]>;
489 def strict_fmul : SDNode<"ISD::STRICT_FMUL",
490 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>;
491 def strict_fdiv : SDNode<"ISD::STRICT_FDIV",
492 SDTFPBinOp, [SDNPHasChain]>;
493 def strict_frem : SDNode<"ISD::STRICT_FREM",
494 SDTFPBinOp, [SDNPHasChain]>;
495 def strict_fma : SDNode<"ISD::STRICT_FMA",
496 SDTFPTernaryOp, [SDNPHasChain]>;
497 def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT",
498 SDTFPUnaryOp, [SDNPHasChain]>;
499 def strict_fsin : SDNode<"ISD::STRICT_FSIN",
500 SDTFPUnaryOp, [SDNPHasChain]>;
501 def strict_fcos : SDNode<"ISD::STRICT_FCOS",
502 SDTFPUnaryOp, [SDNPHasChain]>;
503 def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2",
504 SDTFPUnaryOp, [SDNPHasChain]>;
505 def strict_fpow : SDNode<"ISD::STRICT_FPOW",
506 SDTFPBinOp, [SDNPHasChain]>;
507 def strict_flog2 : SDNode<"ISD::STRICT_FLOG2",
508 SDTFPUnaryOp, [SDNPHasChain]>;
509 def strict_frint : SDNode<"ISD::STRICT_FRINT",
510 SDTFPUnaryOp, [SDNPHasChain]>;
511 def strict_lrint : SDNode<"ISD::STRICT_LRINT",
512 SDTFPToIntOp, [SDNPHasChain]>;
513 def strict_llrint : SDNode<"ISD::STRICT_LLRINT",
514 SDTFPToIntOp, [SDNPHasChain]>;
515 def strict_fnearbyint : SDNode<"ISD::STRICT_FNEARBYINT",
516 SDTFPUnaryOp, [SDNPHasChain]>;
517 def strict_fceil : SDNode<"ISD::STRICT_FCEIL",
518 SDTFPUnaryOp, [SDNPHasChain]>;
519 def strict_ffloor : SDNode<"ISD::STRICT_FFLOOR",
520 SDTFPUnaryOp, [SDNPHasChain]>;
521 def strict_lround : SDNode<"ISD::STRICT_LROUND",
522 SDTFPToIntOp, [SDNPHasChain]>;
523 def strict_llround : SDNode<"ISD::STRICT_LLROUND",
524 SDTFPToIntOp, [SDNPHasChain]>;
525 def strict_fround : SDNode<"ISD::STRICT_FROUND",
526 SDTFPUnaryOp, [SDNPHasChain]>;
527 def strict_ftrunc : SDNode<"ISD::STRICT_FTRUNC",
528 SDTFPUnaryOp, [SDNPHasChain]>;
529 def strict_fminnum : SDNode<"ISD::STRICT_FMINNUM",
530 SDTFPBinOp, [SDNPHasChain,
531 SDNPCommutative, SDNPAssociative]>;
532 def strict_fmaxnum : SDNode<"ISD::STRICT_FMAXNUM",
533 SDTFPBinOp, [SDNPHasChain,
534 SDNPCommutative, SDNPAssociative]>;
535 def strict_fminimum : SDNode<"ISD::STRICT_FMINIMUM",
536 SDTFPBinOp, [SDNPHasChain,
537 SDNPCommutative, SDNPAssociative]>;
538 def strict_fmaximum : SDNode<"ISD::STRICT_FMAXIMUM",
539 SDTFPBinOp, [SDNPHasChain,
540 SDNPCommutative, SDNPAssociative]>;
541 def strict_fpround : SDNode<"ISD::STRICT_FP_ROUND",
542 SDTFPRoundOp, [SDNPHasChain]>;
543 def strict_fpextend : SDNode<"ISD::STRICT_FP_EXTEND",
544 SDTFPExtendOp, [SDNPHasChain]>;
545 def strict_fp_to_sint : SDNode<"ISD::STRICT_FP_TO_SINT",
546 SDTFPToIntOp, [SDNPHasChain]>;
547 def strict_fp_to_uint : SDNode<"ISD::STRICT_FP_TO_UINT",
548 SDTFPToIntOp, [SDNPHasChain]>;
549 def strict_sint_to_fp : SDNode<"ISD::STRICT_SINT_TO_FP",
550 SDTIntToFPOp, [SDNPHasChain]>;
551 def strict_uint_to_fp : SDNode<"ISD::STRICT_UINT_TO_FP",
552 SDTIntToFPOp, [SDNPHasChain]>;
554 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
555 def select : SDNode<"ISD::SELECT" , SDTSelect>;
556 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
557 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
559 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>;
560 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
561 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
562 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
563 def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret,
564 [SDNPHasChain, SDNPSideEffect]>;
565 def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>;
566 def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone,
567 [SDNPHasChain, SDNPSideEffect]>;
569 def trap : SDNode<"ISD::TRAP" , SDTNone,
570 [SDNPHasChain, SDNPSideEffect]>;
571 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
572 [SDNPHasChain, SDNPSideEffect]>;
574 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
575 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
578 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
579 [SDNPHasChain, SDNPSideEffect]>;
581 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
582 [SDNPHasChain, SDNPSideEffect]>;
584 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
585 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
586 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
587 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
588 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
589 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
590 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
591 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
592 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
593 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
594 def atomic_load_clr : SDNode<"ISD::ATOMIC_LOAD_CLR" , SDTAtomic2,
595 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
596 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
597 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
598 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
599 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
600 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
601 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
602 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
603 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
604 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
605 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
606 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
607 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
608 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
609 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
610 def atomic_load_fadd : SDNode<"ISD::ATOMIC_LOAD_FADD" , SDTFPAtomic2,
611 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
612 def atomic_load_fsub : SDNode<"ISD::ATOMIC_LOAD_FSUB" , SDTFPAtomic2,
613 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
615 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
616 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
617 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
618 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
620 def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore,
621 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
622 def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad,
623 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
625 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
626 // and truncst (see below).
627 def ld : SDNode<"ISD::LOAD" , SDTLoad,
628 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
629 def st : SDNode<"ISD::STORE" , SDTStore,
630 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
631 def ist : SDNode<"ISD::STORE" , SDTIStore,
632 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
634 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
635 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
636 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
639 // vector_extract/vector_insert are deprecated. extractelt/insertelt
641 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
642 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
643 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
644 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
645 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
646 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
648 // This operator does not do subvector type checking. The ARM
649 // backend, at least, needs it.
650 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
651 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
654 // This operator does subvector type checking.
655 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
656 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
658 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
659 // these internally. Don't reference these directly.
660 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
661 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
663 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
664 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
666 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
667 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
669 def SDT_assertext : SDTypeProfile<1, 1,
670 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
671 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
672 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
675 //===----------------------------------------------------------------------===//
676 // Selection DAG Condition Codes
678 class CondCode<string fcmpName = "", string icmpName = ""> {
679 string ICmpPredicate = icmpName;
680 string FCmpPredicate = fcmpName;
683 // ISD::CondCode enums, and mapping to CmpInst::Predicate names
684 def SETOEQ : CondCode<"FCMP_OEQ">;
685 def SETOGT : CondCode<"FCMP_OGT">;
686 def SETOGE : CondCode<"FCMP_OGE">;
687 def SETOLT : CondCode<"FCMP_OLT">;
688 def SETOLE : CondCode<"FCMP_OLE">;
689 def SETONE : CondCode<"FCMP_ONE">;
690 def SETO : CondCode<"FCMP_ORD">;
691 def SETUO : CondCode<"FCMP_UNO">;
692 def SETUEQ : CondCode<"FCMP_UEQ">;
693 def SETUGT : CondCode<"FCMP_UGT", "ICMP_UGT">;
694 def SETUGE : CondCode<"FCMP_UGE", "ICMP_UGE">;
695 def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">;
696 def SETULE : CondCode<"FCMP_ULE", "ICMP_ULE">;
697 def SETUNE : CondCode<"FCMP_UNE">;
698 def SETEQ : CondCode<"", "ICMP_EQ">;
699 def SETGT : CondCode<"", "ICMP_SGT">;
700 def SETGE : CondCode<"", "ICMP_SGE">;
701 def SETLT : CondCode<"", "ICMP_SLT">;
702 def SETLE : CondCode<"", "ICMP_SLE">;
703 def SETNE : CondCode<"", "ICMP_NE">;
705 //===----------------------------------------------------------------------===//
706 // Selection DAG Node Transformation Functions.
708 // This mechanism allows targets to manipulate nodes in the output DAG once a
709 // match has been formed. This is typically used to manipulate immediate
712 class SDNodeXForm<SDNode opc, code xformFunction> {
714 code XFormFunction = xformFunction;
717 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
719 //===----------------------------------------------------------------------===//
720 // PatPred Subclasses.
722 // These allow specifying different sorts of predicates that control whether a
727 class CodePatPred<code predicate> : PatPred {
728 code PredicateCode = predicate;
732 //===----------------------------------------------------------------------===//
733 // Selection DAG Pattern Fragments.
735 // Pattern fragments are reusable chunks of dags that match specific things.
736 // They can take arguments and have C++ predicates that control whether they
737 // match. They are intended to make the patterns for common instructions more
738 // compact and readable.
741 /// PatFrags - Represents a set of pattern fragments. Each single fragment
742 /// can match something on the DAG, from a single node to multiple nested other
743 /// fragments. The whole set of fragments matches if any of the single
744 /// fragemnts match. This allows e.g. matching and "add with overflow" and
745 /// a regular "add" with the same fragment set.
747 class PatFrags<dag ops, list<dag> frags, code pred = [{}],
748 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
750 list<dag> Fragments = frags;
751 code PredicateCode = pred;
752 code GISelPredicateCode = [{}];
753 code ImmediateCode = [{}];
754 SDNodeXForm OperandTransform = xform;
756 // When this is set, the PredicateCode may refer to a constant Operands
757 // vector which contains the captured nodes of the DAG, in the order listed
758 // by the Operands field above.
760 // This is useful when Fragments involves associative / commutative
761 // operators: a single piece of code can easily refer to all operands even
762 // when re-associated / commuted variants of the fragment are matched.
763 bit PredicateCodeUsesOperands = 0;
765 // Define a few pre-packaged predicates. This helps GlobalISel import
766 // existing rules from SelectionDAG for many common cases.
767 // They will be tested prior to the code in pred and must not be used in
768 // ImmLeaf and its subclasses.
770 // Is the desired pre-packaged predicate for a load?
772 // Is the desired pre-packaged predicate for a store?
774 // Is the desired pre-packaged predicate for an atomic?
777 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
778 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
781 // cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD
782 bit IsNonExtLoad = ?;
783 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
784 bit IsAnyExtLoad = ?;
785 // cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
786 bit IsSignExtLoad = ?;
787 // cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
788 bit IsZeroExtLoad = ?;
789 // !cast<StoreSDNode>(N)->isTruncatingStore();
790 // cast<StoreSDNode>(N)->isTruncatingStore();
791 bit IsTruncStore = ?;
793 // cast<MemSDNode>(N)->getAddressSpace() ==
794 // If this empty, accept any address space.
795 list<int> AddressSpaces = ?;
797 // cast<MemSDNode>(N)->getAlignment() >=
798 // If this is empty, accept any alignment.
799 int MinAlignment = ?;
801 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Monotonic
802 bit IsAtomicOrderingMonotonic = ?;
803 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Acquire
804 bit IsAtomicOrderingAcquire = ?;
805 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Release
806 bit IsAtomicOrderingRelease = ?;
807 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::AcquireRelease
808 bit IsAtomicOrderingAcquireRelease = ?;
809 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent
810 bit IsAtomicOrderingSequentiallyConsistent = ?;
812 // isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering())
813 // !isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering())
814 bit IsAtomicOrderingAcquireOrStronger = ?;
816 // isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering())
817 // !isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering())
818 bit IsAtomicOrderingReleaseOrStronger = ?;
820 // cast<LoadSDNode>(N)->getMemoryVT() == MVT::<VT>;
821 // cast<StoreSDNode>(N)->getMemoryVT() == MVT::<VT>;
822 ValueType MemoryVT = ?;
823 // cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>;
824 // cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>;
825 ValueType ScalarMemoryVT = ?;
828 // PatFrag - A version of PatFrags matching only a single fragment.
829 class PatFrag<dag ops, dag frag, code pred = [{}],
830 SDNodeXForm xform = NOOP_SDNodeXForm>
831 : PatFrags<ops, [frag], pred, xform>;
833 // OutPatFrag is a pattern fragment that is used as part of an output pattern
834 // (not an input pattern). These do not have predicates or transforms, but are
835 // used to avoid repeated subexpressions in output patterns.
836 class OutPatFrag<dag ops, dag frag>
837 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
839 // PatLeaf's are pattern fragments that have no operands. This is just a helper
840 // to define immediates and other common things concisely.
841 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
842 : PatFrag<(ops), frag, pred, xform>;
845 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
846 // constraint is a function that is run on the immediate (always with the value
847 // sign extended out to an int64_t) as Imm. For example:
849 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
851 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
852 // is preferred over using PatLeaf because it allows the code generator to
853 // reason more about the constraint.
855 // If FastIsel should ignore all instructions that have an operand of this type,
856 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
857 // the code size of the generated fast instruction selector.
858 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm,
859 SDNode ImmNode = imm>
860 : PatFrag<(ops), (vt ImmNode), [{}], xform> {
861 let ImmediateCode = pred;
862 bit FastIselShouldIgnore = 0;
864 // Is the data type of the immediate an APInt?
867 // Is the data type of the immediate an APFloat?
871 // Convenience wrapper for ImmLeaf to use timm/TargetConstant instead
873 class TImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm,
874 SDNode ImmNode = timm> : ImmLeaf<vt, pred, xform, ImmNode>;
876 // An ImmLeaf except that Imm is an APInt. This is useful when you need to
877 // zero-extend the immediate instead of sign-extend it.
879 // Note that FastISel does not currently understand IntImmLeaf and will not
880 // generate code for rules that make use of it. As such, it does not make sense
881 // to replace ImmLeaf with IntImmLeaf. However, replacing PatLeaf with an
882 // IntImmLeaf will allow GlobalISel to import the rule.
883 class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
884 : ImmLeaf<vt, pred, xform> {
886 let FastIselShouldIgnore = 1;
889 // An ImmLeaf except that Imm is an APFloat.
891 // Note that FastISel does not currently understand FPImmLeaf and will not
892 // generate code for rules that make use of it.
893 class FPImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
894 : ImmLeaf<vt, pred, xform, fpimm> {
896 let FastIselShouldIgnore = 1;
901 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
902 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
904 // Use ISD::isBuildVectorAllOnes or ISD::isBuildVectorAllZeros to look for
905 // the corresponding build_vector. Will look through bitcasts except when used
906 // as a pattern root.
907 def immAllOnesV; // ISD::isBuildVectorAllOnes
908 def immAllZerosV; // ISD::isBuildVectorAllZeros
910 // Other helper fragments.
911 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
912 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
913 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
915 // null_frag - The null pattern operator is used in multiclass instantiations
916 // which accept an SDPatternOperator for use in matching patterns for internal
917 // definitions. When expanding a pattern, if the null fragment is referenced
918 // in the expansion, the pattern is discarded and it is as-if '[]' had been
919 // specified. This allows multiclasses to have the isel patterns be optional.
920 def null_frag : SDPatternOperator;
923 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr)> {
927 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
929 let IsNonExtLoad = 1;
932 // extending load fragments.
933 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
935 let IsAnyExtLoad = 1;
937 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
939 let IsSignExtLoad = 1;
941 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
943 let IsZeroExtLoad = 1;
946 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
950 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
954 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
958 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
962 def extloadf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
966 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
970 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
975 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
979 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
983 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
987 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
992 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
996 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
1000 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
1004 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
1009 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
1011 let ScalarMemoryVT = i1;
1013 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
1015 let ScalarMemoryVT = i8;
1017 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
1019 let ScalarMemoryVT = i16;
1021 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
1023 let ScalarMemoryVT = i32;
1025 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
1027 let ScalarMemoryVT = f32;
1029 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
1031 let ScalarMemoryVT = f64;
1034 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
1036 let ScalarMemoryVT = i1;
1038 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
1040 let ScalarMemoryVT = i8;
1042 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
1044 let ScalarMemoryVT = i16;
1046 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
1048 let ScalarMemoryVT = i32;
1051 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
1053 let ScalarMemoryVT = i1;
1055 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
1057 let ScalarMemoryVT = i8;
1059 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
1061 let ScalarMemoryVT = i16;
1063 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
1065 let ScalarMemoryVT = i32;
1069 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
1070 (st node:$val, node:$ptr)> {
1072 let IsUnindexed = 1;
1074 def store : PatFrag<(ops node:$val, node:$ptr),
1075 (unindexedstore node:$val, node:$ptr)> {
1077 let IsTruncStore = 0;
1080 // truncstore fragments.
1081 def truncstore : PatFrag<(ops node:$val, node:$ptr),
1082 (unindexedstore node:$val, node:$ptr)> {
1084 let IsTruncStore = 1;
1086 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
1087 (truncstore node:$val, node:$ptr)> {
1091 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
1092 (truncstore node:$val, node:$ptr)> {
1096 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
1097 (truncstore node:$val, node:$ptr)> {
1101 def truncstoref16 : PatFrag<(ops node:$val, node:$ptr),
1102 (truncstore node:$val, node:$ptr)> {
1106 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
1107 (truncstore node:$val, node:$ptr)> {
1111 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
1112 (truncstore node:$val, node:$ptr)> {
1117 def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr),
1118 (truncstore node:$val, node:$ptr)> {
1120 let ScalarMemoryVT = i8;
1123 def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr),
1124 (truncstore node:$val, node:$ptr)> {
1126 let ScalarMemoryVT = i16;
1129 def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr),
1130 (truncstore node:$val, node:$ptr)> {
1132 let ScalarMemoryVT = i32;
1135 // indexed store fragments.
1136 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
1137 (ist node:$val, node:$base, node:$offset)> {
1139 let IsTruncStore = 0;
1142 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
1143 (istore node:$val, node:$base, node:$offset), [{
1144 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1145 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1148 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
1149 (ist node:$val, node:$base, node:$offset)> {
1151 let IsTruncStore = 1;
1153 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
1154 (itruncstore node:$val, node:$base, node:$offset), [{
1155 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1156 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1158 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
1159 (pre_truncst node:$val, node:$base, node:$offset)> {
1163 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
1164 (pre_truncst node:$val, node:$base, node:$offset)> {
1168 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
1169 (pre_truncst node:$val, node:$base, node:$offset)> {
1173 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
1174 (pre_truncst node:$val, node:$base, node:$offset)> {
1178 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
1179 (pre_truncst node:$val, node:$base, node:$offset)> {
1183 def pre_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset),
1184 (pre_truncst node:$val, node:$base, node:$offset)> {
1186 let ScalarMemoryVT = i8;
1188 def pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset),
1189 (pre_truncst node:$val, node:$base, node:$offset)> {
1191 let ScalarMemoryVT = i16;
1194 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
1195 (istore node:$val, node:$ptr, node:$offset), [{
1196 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1197 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
1200 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
1201 (itruncstore node:$val, node:$base, node:$offset), [{
1202 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
1203 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
1205 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
1206 (post_truncst node:$val, node:$base, node:$offset)> {
1210 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
1211 (post_truncst node:$val, node:$base, node:$offset)> {
1215 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
1216 (post_truncst node:$val, node:$base, node:$offset)> {
1220 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
1221 (post_truncst node:$val, node:$base, node:$offset)> {
1225 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
1226 (post_truncst node:$val, node:$base, node:$offset)> {
1230 def post_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset),
1231 (post_truncst node:$val, node:$base, node:$offset)> {
1233 let ScalarMemoryVT = i8;
1235 def post_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset),
1236 (post_truncst node:$val, node:$base, node:$offset)> {
1238 let ScalarMemoryVT = i16;
1241 // TODO: Split these into volatile and unordered flavors to enable
1242 // selectively legal optimizations for each. (See D66309)
1243 def simple_load : PatFrag<(ops node:$ptr),
1244 (load node:$ptr), [{
1245 return cast<LoadSDNode>(N)->isSimple();
1247 def simple_store : PatFrag<(ops node:$val, node:$ptr),
1248 (store node:$val, node:$ptr), [{
1249 return cast<StoreSDNode>(N)->isSimple();
1252 // nontemporal store fragments.
1253 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
1254 (store node:$val, node:$ptr), [{
1255 return cast<StoreSDNode>(N)->isNonTemporal();
1258 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
1259 (nontemporalstore node:$val, node:$ptr), [{
1260 StoreSDNode *St = cast<StoreSDNode>(N);
1261 return St->getAlignment() >= St->getMemoryVT().getStoreSize();
1264 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
1265 (nontemporalstore node:$val, node:$ptr), [{
1266 StoreSDNode *St = cast<StoreSDNode>(N);
1267 return St->getAlignment() < St->getMemoryVT().getStoreSize();
1270 // nontemporal load fragments.
1271 def nontemporalload : PatFrag<(ops node:$ptr),
1272 (load node:$ptr), [{
1273 return cast<LoadSDNode>(N)->isNonTemporal();
1276 def alignednontemporalload : PatFrag<(ops node:$ptr),
1277 (nontemporalload node:$ptr), [{
1278 LoadSDNode *Ld = cast<LoadSDNode>(N);
1279 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize();
1282 // setcc convenience fragments.
1283 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
1284 (setcc node:$lhs, node:$rhs, SETOEQ)>;
1285 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
1286 (setcc node:$lhs, node:$rhs, SETOGT)>;
1287 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
1288 (setcc node:$lhs, node:$rhs, SETOGE)>;
1289 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
1290 (setcc node:$lhs, node:$rhs, SETOLT)>;
1291 def setole : PatFrag<(ops node:$lhs, node:$rhs),
1292 (setcc node:$lhs, node:$rhs, SETOLE)>;
1293 def setone : PatFrag<(ops node:$lhs, node:$rhs),
1294 (setcc node:$lhs, node:$rhs, SETONE)>;
1295 def seto : PatFrag<(ops node:$lhs, node:$rhs),
1296 (setcc node:$lhs, node:$rhs, SETO)>;
1297 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
1298 (setcc node:$lhs, node:$rhs, SETUO)>;
1299 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
1300 (setcc node:$lhs, node:$rhs, SETUEQ)>;
1301 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
1302 (setcc node:$lhs, node:$rhs, SETUGT)>;
1303 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
1304 (setcc node:$lhs, node:$rhs, SETUGE)>;
1305 def setult : PatFrag<(ops node:$lhs, node:$rhs),
1306 (setcc node:$lhs, node:$rhs, SETULT)>;
1307 def setule : PatFrag<(ops node:$lhs, node:$rhs),
1308 (setcc node:$lhs, node:$rhs, SETULE)>;
1309 def setune : PatFrag<(ops node:$lhs, node:$rhs),
1310 (setcc node:$lhs, node:$rhs, SETUNE)>;
1311 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
1312 (setcc node:$lhs, node:$rhs, SETEQ)>;
1313 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
1314 (setcc node:$lhs, node:$rhs, SETGT)>;
1315 def setge : PatFrag<(ops node:$lhs, node:$rhs),
1316 (setcc node:$lhs, node:$rhs, SETGE)>;
1317 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
1318 (setcc node:$lhs, node:$rhs, SETLT)>;
1319 def setle : PatFrag<(ops node:$lhs, node:$rhs),
1320 (setcc node:$lhs, node:$rhs, SETLE)>;
1321 def setne : PatFrag<(ops node:$lhs, node:$rhs),
1322 (setcc node:$lhs, node:$rhs, SETNE)>;
1324 // We don't have strict FP extended loads as single DAG nodes, but we can
1325 // still provide convenience fragments to match those operations.
1326 def strict_extloadf32 : PatFrag<(ops node:$ptr),
1327 (strict_fpextend (f32 (load node:$ptr)))>;
1328 def strict_extloadf64 : PatFrag<(ops node:$ptr),
1329 (strict_fpextend (f64 (load node:$ptr)))>;
1331 // Convenience fragments to match both strict and non-strict fp operations
1332 def any_fadd : PatFrags<(ops node:$lhs, node:$rhs),
1333 [(strict_fadd node:$lhs, node:$rhs),
1334 (fadd node:$lhs, node:$rhs)]>;
1335 def any_fsub : PatFrags<(ops node:$lhs, node:$rhs),
1336 [(strict_fsub node:$lhs, node:$rhs),
1337 (fsub node:$lhs, node:$rhs)]>;
1338 def any_fmul : PatFrags<(ops node:$lhs, node:$rhs),
1339 [(strict_fmul node:$lhs, node:$rhs),
1340 (fmul node:$lhs, node:$rhs)]>;
1341 def any_fdiv : PatFrags<(ops node:$lhs, node:$rhs),
1342 [(strict_fdiv node:$lhs, node:$rhs),
1343 (fdiv node:$lhs, node:$rhs)]>;
1344 def any_frem : PatFrags<(ops node:$lhs, node:$rhs),
1345 [(strict_frem node:$lhs, node:$rhs),
1346 (frem node:$lhs, node:$rhs)]>;
1347 def any_fma : PatFrags<(ops node:$src1, node:$src2, node:$src3),
1348 [(strict_fma node:$src1, node:$src2, node:$src3),
1349 (fma node:$src1, node:$src2, node:$src3)]>;
1350 def any_fsqrt : PatFrags<(ops node:$src),
1351 [(strict_fsqrt node:$src),
1352 (fsqrt node:$src)]>;
1353 def any_fsin : PatFrags<(ops node:$src),
1354 [(strict_fsin node:$src),
1356 def any_fcos : PatFrags<(ops node:$src),
1357 [(strict_fcos node:$src),
1359 def any_fexp2 : PatFrags<(ops node:$src),
1360 [(strict_fexp2 node:$src),
1361 (fexp2 node:$src)]>;
1362 def any_fpow : PatFrags<(ops node:$lhs, node:$rhs),
1363 [(strict_fpow node:$lhs, node:$rhs),
1364 (fpow node:$lhs, node:$rhs)]>;
1365 def any_flog2 : PatFrags<(ops node:$src),
1366 [(strict_flog2 node:$src),
1367 (flog2 node:$src)]>;
1368 def any_frint : PatFrags<(ops node:$src),
1369 [(strict_frint node:$src),
1370 (frint node:$src)]>;
1371 def any_lrint : PatFrags<(ops node:$src),
1372 [(strict_lrint node:$src),
1373 (lrint node:$src)]>;
1374 def any_llrint : PatFrags<(ops node:$src),
1375 [(strict_llrint node:$src),
1376 (llrint node:$src)]>;
1377 def any_fnearbyint : PatFrags<(ops node:$src),
1378 [(strict_fnearbyint node:$src),
1379 (fnearbyint node:$src)]>;
1380 def any_fceil : PatFrags<(ops node:$src),
1381 [(strict_fceil node:$src),
1382 (fceil node:$src)]>;
1383 def any_ffloor : PatFrags<(ops node:$src),
1384 [(strict_ffloor node:$src),
1385 (ffloor node:$src)]>;
1386 def any_lround : PatFrags<(ops node:$src),
1387 [(strict_lround node:$src),
1388 (lround node:$src)]>;
1389 def any_llround : PatFrags<(ops node:$src),
1390 [(strict_llround node:$src),
1391 (llround node:$src)]>;
1392 def any_fround : PatFrags<(ops node:$src),
1393 [(strict_fround node:$src),
1394 (fround node:$src)]>;
1395 def any_ftrunc : PatFrags<(ops node:$src),
1396 [(strict_ftrunc node:$src),
1397 (ftrunc node:$src)]>;
1398 def any_fmaxnum : PatFrags<(ops node:$lhs, node:$rhs),
1399 [(strict_fmaxnum node:$lhs, node:$rhs),
1400 (fmaxnum node:$lhs, node:$rhs)]>;
1401 def any_fminnum : PatFrags<(ops node:$lhs, node:$rhs),
1402 [(strict_fminnum node:$lhs, node:$rhs),
1403 (fminnum node:$lhs, node:$rhs)]>;
1404 def any_fmaximum : PatFrags<(ops node:$lhs, node:$rhs),
1405 [(strict_fmaximum node:$lhs, node:$rhs),
1406 (fmaximum node:$lhs, node:$rhs)]>;
1407 def any_fminimum : PatFrags<(ops node:$lhs, node:$rhs),
1408 [(strict_fminimum node:$lhs, node:$rhs),
1409 (fminimum node:$lhs, node:$rhs)]>;
1410 def any_fpround : PatFrags<(ops node:$src),
1411 [(strict_fpround node:$src),
1412 (fpround node:$src)]>;
1413 def any_fpextend : PatFrags<(ops node:$src),
1414 [(strict_fpextend node:$src),
1415 (fpextend node:$src)]>;
1416 def any_extloadf32 : PatFrags<(ops node:$ptr),
1417 [(strict_extloadf32 node:$ptr),
1418 (extloadf32 node:$ptr)]>;
1419 def any_extloadf64 : PatFrags<(ops node:$ptr),
1420 [(strict_extloadf64 node:$ptr),
1421 (extloadf64 node:$ptr)]>;
1422 def any_fp_to_sint : PatFrags<(ops node:$src),
1423 [(strict_fp_to_sint node:$src),
1424 (fp_to_sint node:$src)]>;
1425 def any_fp_to_uint : PatFrags<(ops node:$src),
1426 [(strict_fp_to_uint node:$src),
1427 (fp_to_uint node:$src)]>;
1428 def any_sint_to_fp : PatFrags<(ops node:$src),
1429 [(strict_sint_to_fp node:$src),
1430 (sint_to_fp node:$src)]>;
1431 def any_uint_to_fp : PatFrags<(ops node:$src),
1432 [(strict_uint_to_fp node:$src),
1433 (uint_to_fp node:$src)]>;
1435 multiclass binary_atomic_op_ord<SDNode atomic_op> {
1436 def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val),
1437 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
1439 let IsAtomicOrderingMonotonic = 1;
1441 def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$val),
1442 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
1444 let IsAtomicOrderingAcquire = 1;
1446 def #NAME#_release : PatFrag<(ops node:$ptr, node:$val),
1447 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
1449 let IsAtomicOrderingRelease = 1;
1451 def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val),
1452 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
1454 let IsAtomicOrderingAcquireRelease = 1;
1456 def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val),
1457 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$val)> {
1459 let IsAtomicOrderingSequentiallyConsistent = 1;
1463 multiclass ternary_atomic_op_ord<SDNode atomic_op> {
1464 def #NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1465 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1467 let IsAtomicOrderingMonotonic = 1;
1469 def #NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1470 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1472 let IsAtomicOrderingAcquire = 1;
1474 def #NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1475 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1477 let IsAtomicOrderingRelease = 1;
1479 def #NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1480 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1482 let IsAtomicOrderingAcquireRelease = 1;
1484 def #NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1485 (!cast<SDPatternOperator>(#NAME) node:$ptr, node:$cmp, node:$val)> {
1487 let IsAtomicOrderingSequentiallyConsistent = 1;
1491 multiclass binary_atomic_op<SDNode atomic_op, bit IsInt = 1> {
1492 def _8 : PatFrag<(ops node:$ptr, node:$val),
1493 (atomic_op node:$ptr, node:$val)> {
1495 let MemoryVT = !if(IsInt, i8, ?);
1497 def _16 : PatFrag<(ops node:$ptr, node:$val),
1498 (atomic_op node:$ptr, node:$val)> {
1500 let MemoryVT = !if(IsInt, i16, f16);
1502 def _32 : PatFrag<(ops node:$ptr, node:$val),
1503 (atomic_op node:$ptr, node:$val)> {
1505 let MemoryVT = !if(IsInt, i32, f32);
1507 def _64 : PatFrag<(ops node:$ptr, node:$val),
1508 (atomic_op node:$ptr, node:$val)> {
1510 let MemoryVT = !if(IsInt, i64, f64);
1513 defm NAME#_8 : binary_atomic_op_ord<atomic_op>;
1514 defm NAME#_16 : binary_atomic_op_ord<atomic_op>;
1515 defm NAME#_32 : binary_atomic_op_ord<atomic_op>;
1516 defm NAME#_64 : binary_atomic_op_ord<atomic_op>;
1519 multiclass ternary_atomic_op<SDNode atomic_op> {
1520 def _8 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1521 (atomic_op node:$ptr, node:$cmp, node:$val)> {
1525 def _16 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1526 (atomic_op node:$ptr, node:$cmp, node:$val)> {
1530 def _32 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1531 (atomic_op node:$ptr, node:$cmp, node:$val)> {
1535 def _64 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
1536 (atomic_op node:$ptr, node:$cmp, node:$val)> {
1541 defm NAME#_8 : ternary_atomic_op_ord<atomic_op>;
1542 defm NAME#_16 : ternary_atomic_op_ord<atomic_op>;
1543 defm NAME#_32 : ternary_atomic_op_ord<atomic_op>;
1544 defm NAME#_64 : ternary_atomic_op_ord<atomic_op>;
1547 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
1548 defm atomic_swap : binary_atomic_op<atomic_swap>;
1549 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
1550 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
1551 defm atomic_load_clr : binary_atomic_op<atomic_load_clr>;
1552 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
1553 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
1554 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
1555 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
1556 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
1557 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
1558 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
1559 defm atomic_store : binary_atomic_op<atomic_store>;
1560 defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>;
1563 PatFrag<(ops node:$ptr),
1564 (atomic_load node:$ptr)> {
1568 def atomic_load_16 :
1569 PatFrag<(ops node:$ptr),
1570 (atomic_load node:$ptr)> {
1574 def atomic_load_32 :
1575 PatFrag<(ops node:$ptr),
1576 (atomic_load node:$ptr)> {
1580 def atomic_load_64 :
1581 PatFrag<(ops node:$ptr),
1582 (atomic_load node:$ptr)> {
1587 //===----------------------------------------------------------------------===//
1588 // Selection DAG Pattern Support.
1590 // Patterns are what are actually matched against by the target-flavored
1591 // instruction selection DAG. Instructions defined by the target implicitly
1592 // define patterns in most cases, but patterns can also be explicitly added when
1593 // an operation is defined by a sequence of instructions (e.g. loading a large
1594 // immediate value on RISC targets that do not support immediates as large as
1598 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1599 dag PatternToMatch = patternToMatch;
1600 list<dag> ResultInstrs = resultInstrs;
1601 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1602 int AddedComplexity = 0; // See class Instruction in Target.td.
1605 // Pat - A simple (but common) form of a pattern, which produces a simple result
1606 // not needing a full list.
1607 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1609 //===----------------------------------------------------------------------===//
1610 // Complex pattern definitions.
1613 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1614 // in C++. NumOperands is the number of operands returned by the select function;
1615 // SelectFunc is the name of the function used to pattern match the max. pattern;
1616 // RootNodes are the list of possible root nodes of the sub-dags to match.
1617 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1619 class ComplexPattern<ValueType ty, int numops, string fn,
1620 list<SDNode> roots = [], list<SDNodeProperty> props = [],
1621 int complexity = -1> {
1623 int NumOperands = numops;
1624 string SelectFunc = fn;
1625 list<SDNode> RootNodes = roots;
1626 list<SDNodeProperty> Properties = props;
1627 int Complexity = complexity;